| 1 | /* |
| 2 | * hdmi.c |
| 3 | * |
| 4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. |
| 5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 6 | * Authors: Yong Zhi |
| 7 | * Mythri pk <mythripk@ti.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License version 2 as published by |
| 11 | * the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 16 | * more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License along with |
| 19 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 20 | */ |
| 21 | |
| 22 | #define DSS_SUBSYS_NAME "HDMI" |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/io.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/mutex.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/string.h> |
| 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/pm_runtime.h> |
| 34 | #include <linux/clk.h> |
| 35 | #include <video/omapdss.h> |
| 36 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 37 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 38 | #include <sound/soc.h> |
| 39 | #include <sound/pcm_params.h> |
| 40 | #include "ti_hdmi_4xxx_ip.h" |
| 41 | #endif |
| 42 | |
| 43 | #include "ti_hdmi.h" |
| 44 | #include "dss.h" |
| 45 | #include "dss_features.h" |
| 46 | |
| 47 | #define HDMI_WP 0x0 |
| 48 | #define HDMI_CORE_SYS 0x400 |
| 49 | #define HDMI_CORE_AV 0x900 |
| 50 | #define HDMI_PLLCTRL 0x200 |
| 51 | #define HDMI_PHY 0x300 |
| 52 | |
| 53 | /* HDMI EDID Length move this */ |
| 54 | #define HDMI_EDID_MAX_LENGTH 256 |
| 55 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 |
| 56 | #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 |
| 57 | #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 |
| 58 | #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 |
| 59 | #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 |
| 60 | |
| 61 | #define HDMI_DEFAULT_REGN 16 |
| 62 | #define HDMI_DEFAULT_REGM2 1 |
| 63 | |
| 64 | static struct { |
| 65 | struct mutex lock; |
| 66 | struct omap_display_platform_data *pdata; |
| 67 | struct platform_device *pdev; |
| 68 | struct hdmi_ip_data ip_data; |
| 69 | |
| 70 | struct clk *sys_clk; |
| 71 | } hdmi; |
| 72 | |
| 73 | /* |
| 74 | * Logic for the below structure : |
| 75 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. |
| 76 | * There is a correspondence between CEA/VESA timing and code, please |
| 77 | * refer to section 6.3 in HDMI 1.3 specification for timing code. |
| 78 | * |
| 79 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 |
| 80 | * supported CEA and VESA timing values.code_cea corresponds to the CEA |
| 81 | * code, It is used to get the timing from cea_vesa_timing array.Similarly |
| 82 | * with code_vesa. Code_index is used for back mapping, that is once EDID |
| 83 | * is read from the TV, EDID is parsed to find the timing values and then |
| 84 | * map it to corresponding CEA or VESA index. |
| 85 | */ |
| 86 | |
| 87 | static const struct hdmi_config cea_timings[] = { |
| 88 | { {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} }, |
| 89 | { {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} }, |
| 90 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} }, |
| 91 | { {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI} }, |
| 92 | { {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI} }, |
| 93 | { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI} }, |
| 94 | { {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI} }, |
| 95 | { {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI} }, |
| 96 | { {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI} }, |
| 97 | { {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI} }, |
| 98 | { {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI} }, |
| 99 | { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI} }, |
| 100 | { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} }, |
| 101 | { {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} }, |
| 102 | { {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} }, |
| 103 | }; |
| 104 | static const struct hdmi_config vesa_timings[] = { |
| 105 | /* VESA From Here */ |
| 106 | { {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} }, |
| 107 | { {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} }, |
| 108 | { {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI} }, |
| 109 | { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI} }, |
| 110 | { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI} }, |
| 111 | { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI} }, |
| 112 | { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI} }, |
| 113 | { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI} }, |
| 114 | { {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI} }, |
| 115 | { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI} }, |
| 116 | { {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI} }, |
| 117 | { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI} }, |
| 118 | { {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI} }, |
| 119 | { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI} }, |
| 120 | { {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI} }, |
| 121 | { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI} }, |
| 122 | { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI} }, |
| 123 | { {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI} }, |
| 124 | { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} } |
| 125 | }; |
| 126 | |
| 127 | static int hdmi_runtime_get(void) |
| 128 | { |
| 129 | int r; |
| 130 | |
| 131 | DSSDBG("hdmi_runtime_get\n"); |
| 132 | |
| 133 | r = pm_runtime_get_sync(&hdmi.pdev->dev); |
| 134 | WARN_ON(r < 0); |
| 135 | return r < 0 ? r : 0; |
| 136 | } |
| 137 | |
| 138 | static void hdmi_runtime_put(void) |
| 139 | { |
| 140 | int r; |
| 141 | |
| 142 | DSSDBG("hdmi_runtime_put\n"); |
| 143 | |
| 144 | r = pm_runtime_put_sync(&hdmi.pdev->dev); |
| 145 | WARN_ON(r < 0); |
| 146 | } |
| 147 | |
| 148 | int hdmi_init_display(struct omap_dss_device *dssdev) |
| 149 | { |
| 150 | DSSDBG("init_display\n"); |
| 151 | |
| 152 | dss_init_hdmi_ip_ops(&hdmi.ip_data); |
| 153 | return 0; |
| 154 | } |
| 155 | |
| 156 | static const struct hdmi_config *hdmi_find_timing( |
| 157 | const struct hdmi_config *timings_arr, |
| 158 | int len) |
| 159 | { |
| 160 | int i; |
| 161 | |
| 162 | for (i = 0; i < len; i++) { |
| 163 | if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code) |
| 164 | return &timings_arr[i]; |
| 165 | } |
| 166 | return NULL; |
| 167 | } |
| 168 | |
| 169 | static const struct hdmi_config *hdmi_get_timings(void) |
| 170 | { |
| 171 | const struct hdmi_config *arr; |
| 172 | int len; |
| 173 | |
| 174 | if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) { |
| 175 | arr = vesa_timings; |
| 176 | len = ARRAY_SIZE(vesa_timings); |
| 177 | } else { |
| 178 | arr = cea_timings; |
| 179 | len = ARRAY_SIZE(cea_timings); |
| 180 | } |
| 181 | |
| 182 | return hdmi_find_timing(arr, len); |
| 183 | } |
| 184 | |
| 185 | static bool hdmi_timings_compare(struct omap_video_timings *timing1, |
| 186 | const struct hdmi_video_timings *timing2) |
| 187 | { |
| 188 | int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; |
| 189 | |
| 190 | if ((timing2->pixel_clock == timing1->pixel_clock) && |
| 191 | (timing2->x_res == timing1->x_res) && |
| 192 | (timing2->y_res == timing1->y_res)) { |
| 193 | |
| 194 | timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp; |
| 195 | timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp; |
| 196 | timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp; |
| 197 | timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp; |
| 198 | |
| 199 | DSSDBG("timing1_hsync = %d timing1_vsync = %d"\ |
| 200 | "timing2_hsync = %d timing2_vsync = %d\n", |
| 201 | timing1_hsync, timing1_vsync, |
| 202 | timing2_hsync, timing2_vsync); |
| 203 | |
| 204 | if ((timing1_hsync == timing2_hsync) && |
| 205 | (timing1_vsync == timing2_vsync)) { |
| 206 | return true; |
| 207 | } |
| 208 | } |
| 209 | return false; |
| 210 | } |
| 211 | |
| 212 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) |
| 213 | { |
| 214 | int i; |
| 215 | struct hdmi_cm cm = {-1}; |
| 216 | DSSDBG("hdmi_get_code\n"); |
| 217 | |
| 218 | for (i = 0; i < ARRAY_SIZE(cea_timings); i++) { |
| 219 | if (hdmi_timings_compare(timing, &cea_timings[i].timings)) { |
| 220 | cm = cea_timings[i].cm; |
| 221 | goto end; |
| 222 | } |
| 223 | } |
| 224 | for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) { |
| 225 | if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) { |
| 226 | cm = vesa_timings[i].cm; |
| 227 | goto end; |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | end: return cm; |
| 232 | |
| 233 | } |
| 234 | |
| 235 | unsigned long hdmi_get_pixel_clock(void) |
| 236 | { |
| 237 | /* HDMI Pixel Clock in Mhz */ |
| 238 | return hdmi.ip_data.cfg.timings.pixel_clock * 1000; |
| 239 | } |
| 240 | |
| 241 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
| 242 | struct hdmi_pll_info *pi) |
| 243 | { |
| 244 | unsigned long clkin, refclk; |
| 245 | u32 mf; |
| 246 | |
| 247 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; |
| 248 | /* |
| 249 | * Input clock is predivided by N + 1 |
| 250 | * out put of which is reference clk |
| 251 | */ |
| 252 | if (dssdev->clocks.hdmi.regn == 0) |
| 253 | pi->regn = HDMI_DEFAULT_REGN; |
| 254 | else |
| 255 | pi->regn = dssdev->clocks.hdmi.regn; |
| 256 | |
| 257 | refclk = clkin / pi->regn; |
| 258 | |
| 259 | /* |
| 260 | * multiplier is pixel_clk/ref_clk |
| 261 | * Multiplying by 100 to avoid fractional part removal |
| 262 | */ |
| 263 | pi->regm = (phy * 100 / (refclk)) / 100; |
| 264 | |
| 265 | if (dssdev->clocks.hdmi.regm2 == 0) |
| 266 | pi->regm2 = HDMI_DEFAULT_REGM2; |
| 267 | else |
| 268 | pi->regm2 = dssdev->clocks.hdmi.regm2; |
| 269 | |
| 270 | /* |
| 271 | * fractional multiplier is remainder of the difference between |
| 272 | * multiplier and actual phy(required pixel clock thus should be |
| 273 | * multiplied by 2^18(262144) divided by the reference clock |
| 274 | */ |
| 275 | mf = (phy - pi->regm * refclk) * 262144; |
| 276 | pi->regmf = mf / (refclk); |
| 277 | |
| 278 | /* |
| 279 | * Dcofreq should be set to 1 if required pixel clock |
| 280 | * is greater than 1000MHz |
| 281 | */ |
| 282 | pi->dcofreq = phy > 1000 * 100; |
| 283 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; |
| 284 | |
| 285 | /* Set the reference clock to sysclk reference */ |
| 286 | pi->refsel = HDMI_REFSEL_SYSCLK; |
| 287 | |
| 288 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
| 289 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); |
| 290 | } |
| 291 | |
| 292 | static int hdmi_power_on(struct omap_dss_device *dssdev) |
| 293 | { |
| 294 | int r; |
| 295 | const struct hdmi_config *timing; |
| 296 | struct omap_video_timings *p; |
| 297 | unsigned long phy; |
| 298 | |
| 299 | r = hdmi_runtime_get(); |
| 300 | if (r) |
| 301 | return r; |
| 302 | |
| 303 | dss_mgr_disable(dssdev->manager); |
| 304 | |
| 305 | p = &dssdev->panel.timings; |
| 306 | |
| 307 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", |
| 308 | dssdev->panel.timings.x_res, |
| 309 | dssdev->panel.timings.y_res); |
| 310 | |
| 311 | timing = hdmi_get_timings(); |
| 312 | if (timing == NULL) { |
| 313 | /* HDMI code 4 corresponds to 640 * 480 VGA */ |
| 314 | hdmi.ip_data.cfg.cm.code = 4; |
| 315 | /* DVI mode 1 corresponds to HDMI 0 to DVI */ |
| 316 | hdmi.ip_data.cfg.cm.mode = HDMI_DVI; |
| 317 | hdmi.ip_data.cfg = vesa_timings[0]; |
| 318 | } else { |
| 319 | hdmi.ip_data.cfg = *timing; |
| 320 | } |
| 321 | phy = p->pixel_clock; |
| 322 | |
| 323 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
| 324 | |
| 325 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0); |
| 326 | |
| 327 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
| 328 | r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); |
| 329 | if (r) { |
| 330 | DSSDBG("Failed to lock PLL\n"); |
| 331 | goto err; |
| 332 | } |
| 333 | |
| 334 | r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data); |
| 335 | if (r) { |
| 336 | DSSDBG("Failed to start PHY\n"); |
| 337 | goto err; |
| 338 | } |
| 339 | |
| 340 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); |
| 341 | |
| 342 | /* Make selection of HDMI in DSS */ |
| 343 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); |
| 344 | |
| 345 | /* Select the dispc clock source as PRCM clock, to ensure that it is not |
| 346 | * DSI PLL source as the clock selected by DSI PLL might not be |
| 347 | * sufficient for the resolution selected / that can be changed |
| 348 | * dynamically by user. This can be moved to single location , say |
| 349 | * Boardfile. |
| 350 | */ |
| 351 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
| 352 | |
| 353 | /* bypass TV gamma table */ |
| 354 | dispc_enable_gamma_table(0); |
| 355 | |
| 356 | /* tv size */ |
| 357 | dispc_set_digit_size(dssdev->panel.timings.x_res, |
| 358 | dssdev->panel.timings.y_res); |
| 359 | |
| 360 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 1); |
| 361 | |
| 362 | r = dss_mgr_enable(dssdev->manager); |
| 363 | if (r) |
| 364 | goto err_mgr_enable; |
| 365 | |
| 366 | return 0; |
| 367 | |
| 368 | err_mgr_enable: |
| 369 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0); |
| 370 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
| 371 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); |
| 372 | err: |
| 373 | hdmi_runtime_put(); |
| 374 | return -EIO; |
| 375 | } |
| 376 | |
| 377 | static void hdmi_power_off(struct omap_dss_device *dssdev) |
| 378 | { |
| 379 | dss_mgr_disable(dssdev->manager); |
| 380 | |
| 381 | hdmi.ip_data.ops->video_enable(&hdmi.ip_data, 0); |
| 382 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
| 383 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); |
| 384 | hdmi_runtime_put(); |
| 385 | } |
| 386 | |
| 387 | int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, |
| 388 | struct omap_video_timings *timings) |
| 389 | { |
| 390 | struct hdmi_cm cm; |
| 391 | |
| 392 | cm = hdmi_get_code(timings); |
| 393 | if (cm.code == -1) { |
| 394 | return -EINVAL; |
| 395 | } |
| 396 | |
| 397 | return 0; |
| 398 | |
| 399 | } |
| 400 | |
| 401 | void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev) |
| 402 | { |
| 403 | struct hdmi_cm cm; |
| 404 | |
| 405 | cm = hdmi_get_code(&dssdev->panel.timings); |
| 406 | hdmi.ip_data.cfg.cm.code = cm.code; |
| 407 | hdmi.ip_data.cfg.cm.mode = cm.mode; |
| 408 | |
| 409 | if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { |
| 410 | int r; |
| 411 | |
| 412 | hdmi_power_off(dssdev); |
| 413 | |
| 414 | r = hdmi_power_on(dssdev); |
| 415 | if (r) |
| 416 | DSSERR("failed to power on device\n"); |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | void hdmi_dump_regs(struct seq_file *s) |
| 421 | { |
| 422 | mutex_lock(&hdmi.lock); |
| 423 | |
| 424 | if (hdmi_runtime_get()) |
| 425 | return; |
| 426 | |
| 427 | hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s); |
| 428 | hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); |
| 429 | hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); |
| 430 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); |
| 431 | |
| 432 | hdmi_runtime_put(); |
| 433 | mutex_unlock(&hdmi.lock); |
| 434 | } |
| 435 | |
| 436 | int omapdss_hdmi_read_edid(u8 *buf, int len) |
| 437 | { |
| 438 | int r; |
| 439 | |
| 440 | mutex_lock(&hdmi.lock); |
| 441 | |
| 442 | r = hdmi_runtime_get(); |
| 443 | BUG_ON(r); |
| 444 | |
| 445 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); |
| 446 | |
| 447 | hdmi_runtime_put(); |
| 448 | mutex_unlock(&hdmi.lock); |
| 449 | |
| 450 | return r; |
| 451 | } |
| 452 | |
| 453 | bool omapdss_hdmi_detect(void) |
| 454 | { |
| 455 | int r; |
| 456 | |
| 457 | mutex_lock(&hdmi.lock); |
| 458 | |
| 459 | r = hdmi_runtime_get(); |
| 460 | BUG_ON(r); |
| 461 | |
| 462 | r = hdmi.ip_data.ops->detect(&hdmi.ip_data); |
| 463 | |
| 464 | hdmi_runtime_put(); |
| 465 | mutex_unlock(&hdmi.lock); |
| 466 | |
| 467 | return r == 1; |
| 468 | } |
| 469 | |
| 470 | int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) |
| 471 | { |
| 472 | struct omap_dss_hdmi_data *priv = dssdev->data; |
| 473 | int r = 0; |
| 474 | |
| 475 | DSSDBG("ENTER hdmi_display_enable\n"); |
| 476 | |
| 477 | mutex_lock(&hdmi.lock); |
| 478 | |
| 479 | if (dssdev->manager == NULL) { |
| 480 | DSSERR("failed to enable display: no manager\n"); |
| 481 | r = -ENODEV; |
| 482 | goto err0; |
| 483 | } |
| 484 | |
| 485 | hdmi.ip_data.hpd_gpio = priv->hpd_gpio; |
| 486 | |
| 487 | r = omap_dss_start_device(dssdev); |
| 488 | if (r) { |
| 489 | DSSERR("failed to start device\n"); |
| 490 | goto err0; |
| 491 | } |
| 492 | |
| 493 | if (dssdev->platform_enable) { |
| 494 | r = dssdev->platform_enable(dssdev); |
| 495 | if (r) { |
| 496 | DSSERR("failed to enable GPIO's\n"); |
| 497 | goto err1; |
| 498 | } |
| 499 | } |
| 500 | |
| 501 | r = hdmi_power_on(dssdev); |
| 502 | if (r) { |
| 503 | DSSERR("failed to power on device\n"); |
| 504 | goto err2; |
| 505 | } |
| 506 | |
| 507 | mutex_unlock(&hdmi.lock); |
| 508 | return 0; |
| 509 | |
| 510 | err2: |
| 511 | if (dssdev->platform_disable) |
| 512 | dssdev->platform_disable(dssdev); |
| 513 | err1: |
| 514 | omap_dss_stop_device(dssdev); |
| 515 | err0: |
| 516 | mutex_unlock(&hdmi.lock); |
| 517 | return r; |
| 518 | } |
| 519 | |
| 520 | void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) |
| 521 | { |
| 522 | DSSDBG("Enter hdmi_display_disable\n"); |
| 523 | |
| 524 | mutex_lock(&hdmi.lock); |
| 525 | |
| 526 | hdmi_power_off(dssdev); |
| 527 | |
| 528 | if (dssdev->platform_disable) |
| 529 | dssdev->platform_disable(dssdev); |
| 530 | |
| 531 | omap_dss_stop_device(dssdev); |
| 532 | |
| 533 | mutex_unlock(&hdmi.lock); |
| 534 | } |
| 535 | |
| 536 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 537 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 538 | |
| 539 | static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, |
| 540 | struct snd_soc_dai *dai) |
| 541 | { |
| 542 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 543 | struct snd_soc_codec *codec = rtd->codec; |
| 544 | struct platform_device *pdev = to_platform_device(codec->dev); |
| 545 | struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec); |
| 546 | int err = 0; |
| 547 | |
| 548 | if (!(ip_data->ops) && !(ip_data->ops->audio_enable)) { |
| 549 | dev_err(&pdev->dev, "Cannot enable/disable audio\n"); |
| 550 | return -ENODEV; |
| 551 | } |
| 552 | |
| 553 | switch (cmd) { |
| 554 | case SNDRV_PCM_TRIGGER_START: |
| 555 | case SNDRV_PCM_TRIGGER_RESUME: |
| 556 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 557 | ip_data->ops->audio_enable(ip_data, true); |
| 558 | break; |
| 559 | case SNDRV_PCM_TRIGGER_STOP: |
| 560 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 561 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 562 | ip_data->ops->audio_enable(ip_data, false); |
| 563 | break; |
| 564 | default: |
| 565 | err = -EINVAL; |
| 566 | } |
| 567 | return err; |
| 568 | } |
| 569 | |
| 570 | static int hdmi_audio_hw_params(struct snd_pcm_substream *substream, |
| 571 | struct snd_pcm_hw_params *params, |
| 572 | struct snd_soc_dai *dai) |
| 573 | { |
| 574 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 575 | struct snd_soc_codec *codec = rtd->codec; |
| 576 | struct hdmi_ip_data *ip_data = snd_soc_codec_get_drvdata(codec); |
| 577 | struct hdmi_audio_format audio_format; |
| 578 | struct hdmi_audio_dma audio_dma; |
| 579 | struct hdmi_core_audio_config core_cfg; |
| 580 | struct hdmi_core_infoframe_audio aud_if_cfg; |
| 581 | int err, n, cts; |
| 582 | enum hdmi_core_audio_sample_freq sample_freq; |
| 583 | |
| 584 | switch (params_format(params)) { |
| 585 | case SNDRV_PCM_FORMAT_S16_LE: |
| 586 | core_cfg.i2s_cfg.word_max_length = |
| 587 | HDMI_AUDIO_I2S_MAX_WORD_20BITS; |
| 588 | core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS; |
| 589 | core_cfg.i2s_cfg.in_length_bits = |
| 590 | HDMI_AUDIO_I2S_INPUT_LENGTH_16; |
| 591 | core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
| 592 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; |
| 593 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; |
| 594 | audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; |
| 595 | audio_dma.transfer_size = 0x10; |
| 596 | break; |
| 597 | case SNDRV_PCM_FORMAT_S24_LE: |
| 598 | core_cfg.i2s_cfg.word_max_length = |
| 599 | HDMI_AUDIO_I2S_MAX_WORD_24BITS; |
| 600 | core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS; |
| 601 | core_cfg.i2s_cfg.in_length_bits = |
| 602 | HDMI_AUDIO_I2S_INPUT_LENGTH_24; |
| 603 | audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; |
| 604 | audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; |
| 605 | audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
| 606 | core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; |
| 607 | audio_dma.transfer_size = 0x20; |
| 608 | break; |
| 609 | default: |
| 610 | return -EINVAL; |
| 611 | } |
| 612 | |
| 613 | switch (params_rate(params)) { |
| 614 | case 32000: |
| 615 | sample_freq = HDMI_AUDIO_FS_32000; |
| 616 | break; |
| 617 | case 44100: |
| 618 | sample_freq = HDMI_AUDIO_FS_44100; |
| 619 | break; |
| 620 | case 48000: |
| 621 | sample_freq = HDMI_AUDIO_FS_48000; |
| 622 | break; |
| 623 | default: |
| 624 | return -EINVAL; |
| 625 | } |
| 626 | |
| 627 | err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts); |
| 628 | if (err < 0) |
| 629 | return err; |
| 630 | |
| 631 | /* Audio wrapper config */ |
| 632 | audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; |
| 633 | audio_format.active_chnnls_msk = 0x03; |
| 634 | audio_format.type = HDMI_AUDIO_TYPE_LPCM; |
| 635 | audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; |
| 636 | /* Disable start/stop signals of IEC 60958 blocks */ |
| 637 | audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF; |
| 638 | |
| 639 | audio_dma.block_size = 0xC0; |
| 640 | audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; |
| 641 | audio_dma.fifo_threshold = 0x20; /* in number of samples */ |
| 642 | |
| 643 | hdmi_wp_audio_config_dma(ip_data, &audio_dma); |
| 644 | hdmi_wp_audio_config_format(ip_data, &audio_format); |
| 645 | |
| 646 | /* |
| 647 | * I2S config |
| 648 | */ |
| 649 | core_cfg.i2s_cfg.en_high_bitrate_aud = false; |
| 650 | /* Only used with high bitrate audio */ |
| 651 | core_cfg.i2s_cfg.cbit_order = false; |
| 652 | /* Serial data and word select should change on sck rising edge */ |
| 653 | core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; |
| 654 | core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; |
| 655 | /* Set I2S word select polarity */ |
| 656 | core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT; |
| 657 | core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; |
| 658 | /* Set serial data to word select shift. See Phillips spec. */ |
| 659 | core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; |
| 660 | /* Enable one of the four available serial data channels */ |
| 661 | core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; |
| 662 | |
| 663 | /* Core audio config */ |
| 664 | core_cfg.freq_sample = sample_freq; |
| 665 | core_cfg.n = n; |
| 666 | core_cfg.cts = cts; |
| 667 | if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) { |
| 668 | core_cfg.aud_par_busclk = 0; |
| 669 | core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW; |
| 670 | core_cfg.use_mclk = false; |
| 671 | } else { |
| 672 | core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8); |
| 673 | core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW; |
| 674 | core_cfg.use_mclk = true; |
| 675 | core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS; |
| 676 | } |
| 677 | core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH; |
| 678 | core_cfg.en_spdif = false; |
| 679 | /* Use sample frequency from channel status word */ |
| 680 | core_cfg.fs_override = true; |
| 681 | /* Enable ACR packets */ |
| 682 | core_cfg.en_acr_pkt = true; |
| 683 | /* Disable direct streaming digital audio */ |
| 684 | core_cfg.en_dsd_audio = false; |
| 685 | /* Use parallel audio interface */ |
| 686 | core_cfg.en_parallel_aud_input = true; |
| 687 | |
| 688 | hdmi_core_audio_config(ip_data, &core_cfg); |
| 689 | |
| 690 | /* |
| 691 | * Configure packet |
| 692 | * info frame audio see doc CEA861-D page 74 |
| 693 | */ |
| 694 | aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM; |
| 695 | aud_if_cfg.db1_channel_count = 2; |
| 696 | aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM; |
| 697 | aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM; |
| 698 | aud_if_cfg.db4_channel_alloc = 0x00; |
| 699 | aud_if_cfg.db5_downmix_inh = false; |
| 700 | aud_if_cfg.db5_lsv = 0; |
| 701 | |
| 702 | hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg); |
| 703 | return 0; |
| 704 | } |
| 705 | |
| 706 | static int hdmi_audio_startup(struct snd_pcm_substream *substream, |
| 707 | struct snd_soc_dai *dai) |
| 708 | { |
| 709 | if (!hdmi.ip_data.cfg.cm.mode) { |
| 710 | pr_err("Current video settings do not support audio.\n"); |
| 711 | return -EIO; |
| 712 | } |
| 713 | return 0; |
| 714 | } |
| 715 | |
| 716 | static int hdmi_audio_codec_probe(struct snd_soc_codec *codec) |
| 717 | { |
| 718 | struct hdmi_ip_data *priv = &hdmi.ip_data; |
| 719 | |
| 720 | snd_soc_codec_set_drvdata(codec, priv); |
| 721 | return 0; |
| 722 | } |
| 723 | |
| 724 | static struct snd_soc_codec_driver hdmi_audio_codec_drv = { |
| 725 | .probe = hdmi_audio_codec_probe, |
| 726 | }; |
| 727 | |
| 728 | static struct snd_soc_dai_ops hdmi_audio_codec_ops = { |
| 729 | .hw_params = hdmi_audio_hw_params, |
| 730 | .trigger = hdmi_audio_trigger, |
| 731 | .startup = hdmi_audio_startup, |
| 732 | }; |
| 733 | |
| 734 | static struct snd_soc_dai_driver hdmi_codec_dai_drv = { |
| 735 | .name = "hdmi-audio-codec", |
| 736 | .playback = { |
| 737 | .channels_min = 2, |
| 738 | .channels_max = 2, |
| 739 | .rates = SNDRV_PCM_RATE_32000 | |
| 740 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, |
| 741 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
| 742 | SNDRV_PCM_FMTBIT_S24_LE, |
| 743 | }, |
| 744 | .ops = &hdmi_audio_codec_ops, |
| 745 | }; |
| 746 | #endif |
| 747 | |
| 748 | static int hdmi_get_clocks(struct platform_device *pdev) |
| 749 | { |
| 750 | struct clk *clk; |
| 751 | |
| 752 | clk = clk_get(&pdev->dev, "sys_clk"); |
| 753 | if (IS_ERR(clk)) { |
| 754 | DSSERR("can't get sys_clk\n"); |
| 755 | return PTR_ERR(clk); |
| 756 | } |
| 757 | |
| 758 | hdmi.sys_clk = clk; |
| 759 | |
| 760 | return 0; |
| 761 | } |
| 762 | |
| 763 | static void hdmi_put_clocks(void) |
| 764 | { |
| 765 | if (hdmi.sys_clk) |
| 766 | clk_put(hdmi.sys_clk); |
| 767 | } |
| 768 | |
| 769 | /* HDMI HW IP initialisation */ |
| 770 | static int omapdss_hdmihw_probe(struct platform_device *pdev) |
| 771 | { |
| 772 | struct resource *hdmi_mem; |
| 773 | int r; |
| 774 | |
| 775 | hdmi.pdata = pdev->dev.platform_data; |
| 776 | hdmi.pdev = pdev; |
| 777 | |
| 778 | mutex_init(&hdmi.lock); |
| 779 | |
| 780 | hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); |
| 781 | if (!hdmi_mem) { |
| 782 | DSSERR("can't get IORESOURCE_MEM HDMI\n"); |
| 783 | return -EINVAL; |
| 784 | } |
| 785 | |
| 786 | /* Base address taken from platform */ |
| 787 | hdmi.ip_data.base_wp = ioremap(hdmi_mem->start, |
| 788 | resource_size(hdmi_mem)); |
| 789 | if (!hdmi.ip_data.base_wp) { |
| 790 | DSSERR("can't ioremap WP\n"); |
| 791 | return -ENOMEM; |
| 792 | } |
| 793 | |
| 794 | r = hdmi_get_clocks(pdev); |
| 795 | if (r) { |
| 796 | iounmap(hdmi.ip_data.base_wp); |
| 797 | return r; |
| 798 | } |
| 799 | |
| 800 | pm_runtime_enable(&pdev->dev); |
| 801 | |
| 802 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; |
| 803 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; |
| 804 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; |
| 805 | hdmi.ip_data.phy_offset = HDMI_PHY; |
| 806 | |
| 807 | hdmi_panel_init(); |
| 808 | |
| 809 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 810 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 811 | |
| 812 | /* Register ASoC codec DAI */ |
| 813 | r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv, |
| 814 | &hdmi_codec_dai_drv, 1); |
| 815 | if (r) { |
| 816 | DSSERR("can't register ASoC HDMI audio codec\n"); |
| 817 | return r; |
| 818 | } |
| 819 | #endif |
| 820 | return 0; |
| 821 | } |
| 822 | |
| 823 | static int omapdss_hdmihw_remove(struct platform_device *pdev) |
| 824 | { |
| 825 | hdmi_panel_exit(); |
| 826 | |
| 827 | #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ |
| 828 | defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) |
| 829 | snd_soc_unregister_codec(&pdev->dev); |
| 830 | #endif |
| 831 | |
| 832 | pm_runtime_disable(&pdev->dev); |
| 833 | |
| 834 | hdmi_put_clocks(); |
| 835 | |
| 836 | iounmap(hdmi.ip_data.base_wp); |
| 837 | |
| 838 | return 0; |
| 839 | } |
| 840 | |
| 841 | static int hdmi_runtime_suspend(struct device *dev) |
| 842 | { |
| 843 | clk_disable(hdmi.sys_clk); |
| 844 | |
| 845 | dispc_runtime_put(); |
| 846 | dss_runtime_put(); |
| 847 | |
| 848 | return 0; |
| 849 | } |
| 850 | |
| 851 | static int hdmi_runtime_resume(struct device *dev) |
| 852 | { |
| 853 | int r; |
| 854 | |
| 855 | r = dss_runtime_get(); |
| 856 | if (r < 0) |
| 857 | goto err_get_dss; |
| 858 | |
| 859 | r = dispc_runtime_get(); |
| 860 | if (r < 0) |
| 861 | goto err_get_dispc; |
| 862 | |
| 863 | |
| 864 | clk_enable(hdmi.sys_clk); |
| 865 | |
| 866 | return 0; |
| 867 | |
| 868 | err_get_dispc: |
| 869 | dss_runtime_put(); |
| 870 | err_get_dss: |
| 871 | return r; |
| 872 | } |
| 873 | |
| 874 | static const struct dev_pm_ops hdmi_pm_ops = { |
| 875 | .runtime_suspend = hdmi_runtime_suspend, |
| 876 | .runtime_resume = hdmi_runtime_resume, |
| 877 | }; |
| 878 | |
| 879 | static struct platform_driver omapdss_hdmihw_driver = { |
| 880 | .probe = omapdss_hdmihw_probe, |
| 881 | .remove = omapdss_hdmihw_remove, |
| 882 | .driver = { |
| 883 | .name = "omapdss_hdmi", |
| 884 | .owner = THIS_MODULE, |
| 885 | .pm = &hdmi_pm_ops, |
| 886 | }, |
| 887 | }; |
| 888 | |
| 889 | int hdmi_init_platform_driver(void) |
| 890 | { |
| 891 | return platform_driver_register(&omapdss_hdmihw_driver); |
| 892 | } |
| 893 | |
| 894 | void hdmi_uninit_platform_driver(void) |
| 895 | { |
| 896 | return platform_driver_unregister(&omapdss_hdmihw_driver); |
| 897 | } |