[deliverable/linux.git] / drivers / watchdog / davinci_wdt.c

/*
 * drivers/char/watchdog/davinci_wdt.c
 *
 * Watchdog driver for DaVinci DM644x/DM646x processors
 *
 * Copyright (C) 2006-2013 Texas Instruments.
 *
 * 2007 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/watchdog.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/clk.h>
#include <linux/err.h>

#define MODULE_NAME "DAVINCI-WDT: "

#define DEFAULT_HEARTBEAT 60
#define MAX_HEARTBEAT     600	/* really the max margin is 264/27MHz*/

/* Timer register set definition */
#define PID12	(0x0)
#define EMUMGT	(0x4)
#define TIM12	(0x10)
#define TIM34	(0x14)
#define PRD12	(0x18)
#define PRD34	(0x1C)
#define TCR	(0x20)
#define TGCR	(0x24)
#define WDTCR	(0x28)

/* TCR bit definitions */
#define ENAMODE12_DISABLED	(0 << 6)
#define ENAMODE12_ONESHOT	(1 << 6)
#define ENAMODE12_PERIODIC	(2 << 6)

/* TGCR bit definitions */
#define TIM12RS_UNRESET		(1 << 0)
#define TIM34RS_UNRESET		(1 << 1)
#define TIMMODE_64BIT_WDOG      (2 << 2)

/* WDTCR bit definitions */
#define WDEN			(1 << 14)
#define WDFLAG			(1 << 15)
#define WDKEY_SEQ0		(0xa5c6 << 16)
#define WDKEY_SEQ1		(0xda7e << 16)

static int heartbeat;

/*
 * struct to hold data for each WDT device
 * @base - base io address of WD device
 * @clk - source clock of WDT
 * @wdd - hold watchdog device as is in WDT core
 */
struct davinci_wdt_device {
	void __iomem		*base;
	struct clk		*clk;
	struct watchdog_device	wdd;
};

static int davinci_wdt_start(struct watchdog_device *wdd)
{
	u32 tgcr;
	u32 timer_margin;
	unsigned long wdt_freq;
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

	wdt_freq = clk_get_rate(davinci_wdt->clk);

	/* disable, internal clock source */
	iowrite32(0, davinci_wdt->base + TCR);
	/* reset timer, set mode to 64-bit watchdog, and unreset */
	iowrite32(0, davinci_wdt->base + TGCR);
	tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
	iowrite32(tgcr, davinci_wdt->base + TGCR);
	/* clear counter regs */
	iowrite32(0, davinci_wdt->base + TIM12);
	iowrite32(0, davinci_wdt->base + TIM34);
	/* set timeout period */
	timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
	iowrite32(timer_margin, davinci_wdt->base + PRD12);
	timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
	iowrite32(timer_margin, davinci_wdt->base + PRD34);
	/* enable run continuously */
	iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
	/* Once the WDT is in pre-active state write to
	 * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
	 * write protected (except for the WDKEY field)
	 */
	/* put watchdog in pre-active state */
	iowrite32(WDKEY_SEQ0 | WDEN, davinci_wdt->base + WDTCR);
	/* put watchdog in active state */
	iowrite32(WDKEY_SEQ1 | WDEN, davinci_wdt->base + WDTCR);
	return 0;
}

static int davinci_wdt_ping(struct watchdog_device *wdd)
{
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

	/* put watchdog in service state */
	iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
	/* put watchdog in active state */
	iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
	return 0;
}

static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
{
	u64 timer_counter;
	unsigned long freq;
	u32 val;
	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);

	/* if timeout has occured then return 0 */
	val = ioread32(davinci_wdt->base + WDTCR);
	if (val & WDFLAG)
		return 0;

	freq = clk_get_rate(davinci_wdt->clk);

	if (!freq)
		return 0;

	timer_counter = ioread32(davinci_wdt->base + TIM12);
	timer_counter |= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);

	do_div(timer_counter, freq);

	return wdd->timeout - timer_counter;
}

static const struct watchdog_info davinci_wdt_info = {
	.options = WDIOF_KEEPALIVEPING,
	.identity = "DaVinci Watchdog",
};

static const struct watchdog_ops davinci_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= davinci_wdt_start,
	.stop		= davinci_wdt_ping,
	.ping		= davinci_wdt_ping,
	.get_timeleft	= davinci_wdt_get_timeleft,
};

static int davinci_wdt_probe(struct platform_device *pdev)
{
	int ret = 0;
	struct device *dev = &pdev->dev;
	struct resource  *wdt_mem;
	struct watchdog_device *wdd;
	struct davinci_wdt_device *davinci_wdt;

	davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
	if (!davinci_wdt)
		return -ENOMEM;

	davinci_wdt->clk = devm_clk_get(dev, NULL);
	if (WARN_ON(IS_ERR(davinci_wdt->clk)))
		return PTR_ERR(davinci_wdt->clk);

	clk_prepare_enable(davinci_wdt->clk);

	platform_set_drvdata(pdev, davinci_wdt);

	wdd			= &davinci_wdt->wdd;
	wdd->info		= &davinci_wdt_info;
	wdd->ops		= &davinci_wdt_ops;
	wdd->min_timeout	= 1;
	wdd->max_timeout	= MAX_HEARTBEAT;
	wdd->timeout		= DEFAULT_HEARTBEAT;

	watchdog_init_timeout(wdd, heartbeat, dev);

	dev_info(dev, "heartbeat %d sec\n", wdd->timeout);

	watchdog_set_drvdata(wdd, davinci_wdt);
	watchdog_set_nowayout(wdd, 1);

	wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	davinci_wdt->base = devm_ioremap_resource(dev, wdt_mem);
	if (IS_ERR(davinci_wdt->base))
		return PTR_ERR(davinci_wdt->base);

	ret = watchdog_register_device(wdd);
	if (ret < 0)
		dev_err(dev, "cannot register watchdog device\n");

	return ret;
}

static int davinci_wdt_remove(struct platform_device *pdev)
{
	struct davinci_wdt_device *davinci_wdt = platform_get_drvdata(pdev);

	watchdog_unregister_device(&davinci_wdt->wdd);
	clk_disable_unprepare(davinci_wdt->clk);

	return 0;
}

static const struct of_device_id davinci_wdt_of_match[] = {
	{ .compatible = "ti,davinci-wdt", },
	{},
};
MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);

static struct platform_driver platform_wdt_driver = {
	.driver = {
		.name = "davinci-wdt",
		.owner	= THIS_MODULE,
		.of_match_table = davinci_wdt_of_match,
	},
	.probe = davinci_wdt_probe,
	.remove = davinci_wdt_remove,
};

module_platform_driver(platform_wdt_driver);

MODULE_AUTHOR("Texas Instruments");
MODULE_DESCRIPTION("DaVinci Watchdog Driver");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
		 "Watchdog heartbeat period in seconds from 1 to "
		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
		 __MODULE_STRING(DEFAULT_HEARTBEAT));

MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:davinci-wdt");
Commit	Line	Data
	1	/*
	2	* drivers/char/watchdog/davinci_wdt.c
	3	*
	4	* Watchdog driver for DaVinci DM644x/DM646x processors
	5	*
	6	* Copyright (C) 2006-2013 Texas Instruments.
	7	*
	8	* 2007 (c) MontaVista Software, Inc. This file is licensed under
	9	* the terms of the GNU General Public License version 2. This program
	10	* is licensed "as is" without any warranty of any kind, whether express
	11	* or implied.
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/moduleparam.h>
	16	#include <linux/types.h>
	17	#include <linux/kernel.h>
	18	#include <linux/watchdog.h>
	19	#include <linux/init.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/io.h>
	22	#include <linux/device.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
	25
	26	#define MODULE_NAME "DAVINCI-WDT: "
	27
	28	#define DEFAULT_HEARTBEAT 60
	29	#define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
	30
	31	/* Timer register set definition */
	32	#define PID12 (0x0)
	33	#define EMUMGT (0x4)
	34	#define TIM12 (0x10)
	35	#define TIM34 (0x14)
	36	#define PRD12 (0x18)
	37	#define PRD34 (0x1C)
	38	#define TCR (0x20)
	39	#define TGCR (0x24)
	40	#define WDTCR (0x28)
	41
	42	/* TCR bit definitions */
	43	#define ENAMODE12_DISABLED (0 << 6)
	44	#define ENAMODE12_ONESHOT (1 << 6)
	45	#define ENAMODE12_PERIODIC (2 << 6)
	46
	47	/* TGCR bit definitions */
	48	#define TIM12RS_UNRESET (1 << 0)
	49	#define TIM34RS_UNRESET (1 << 1)
	50	#define TIMMODE_64BIT_WDOG (2 << 2)
	51
	52	/* WDTCR bit definitions */
	53	#define WDEN (1 << 14)
	54	#define WDFLAG (1 << 15)
	55	#define WDKEY_SEQ0 (0xa5c6 << 16)
	56	#define WDKEY_SEQ1 (0xda7e << 16)
	57
	58	static int heartbeat;
	59
	60	/*
	61	* struct to hold data for each WDT device
	62	* @base - base io address of WD device
	63	* @clk - source clock of WDT
	64	* @wdd - hold watchdog device as is in WDT core
	65	*/
	66	struct davinci_wdt_device {
	67	void __iomem *base;
	68	struct clk *clk;
	69	struct watchdog_device wdd;
	70	};
	71
	72	static int davinci_wdt_start(struct watchdog_device *wdd)
	73	{
	74	u32 tgcr;
	75	u32 timer_margin;
	76	unsigned long wdt_freq;
	77	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
	78
	79	wdt_freq = clk_get_rate(davinci_wdt->clk);
	80
	81	/* disable, internal clock source */
	82	iowrite32(0, davinci_wdt->base + TCR);
	83	/* reset timer, set mode to 64-bit watchdog, and unreset */
	84	iowrite32(0, davinci_wdt->base + TGCR);
	85	tgcr = TIMMODE_64BIT_WDOG \| TIM12RS_UNRESET \| TIM34RS_UNRESET;
	86	iowrite32(tgcr, davinci_wdt->base + TGCR);
	87	/* clear counter regs */
	88	iowrite32(0, davinci_wdt->base + TIM12);
	89	iowrite32(0, davinci_wdt->base + TIM34);
	90	/* set timeout period */
	91	timer_margin = (((u64)wdd->timeout * wdt_freq) & 0xffffffff);
	92	iowrite32(timer_margin, davinci_wdt->base + PRD12);
	93	timer_margin = (((u64)wdd->timeout * wdt_freq) >> 32);
	94	iowrite32(timer_margin, davinci_wdt->base + PRD34);
	95	/* enable run continuously */
	96	iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR);
	97	/* Once the WDT is in pre-active state write to
	98	* TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
	99	* write protected (except for the WDKEY field)
	100	*/
	101	/* put watchdog in pre-active state */
	102	iowrite32(WDKEY_SEQ0 \| WDEN, davinci_wdt->base + WDTCR);
	103	/* put watchdog in active state */
	104	iowrite32(WDKEY_SEQ1 \| WDEN, davinci_wdt->base + WDTCR);
	105	return 0;
	106	}
	107
	108	static int davinci_wdt_ping(struct watchdog_device *wdd)
	109	{
	110	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
	111
	112	/* put watchdog in service state */
	113	iowrite32(WDKEY_SEQ0, davinci_wdt->base + WDTCR);
	114	/* put watchdog in active state */
	115	iowrite32(WDKEY_SEQ1, davinci_wdt->base + WDTCR);
	116	return 0;
	117	}
	118
	119	static unsigned int davinci_wdt_get_timeleft(struct watchdog_device *wdd)
	120	{
	121	u64 timer_counter;
	122	unsigned long freq;
	123	u32 val;
	124	struct davinci_wdt_device *davinci_wdt = watchdog_get_drvdata(wdd);
	125
	126	/* if timeout has occured then return 0 */
	127	val = ioread32(davinci_wdt->base + WDTCR);
	128	if (val & WDFLAG)
	129	return 0;
	130
	131	freq = clk_get_rate(davinci_wdt->clk);
	132
	133	if (!freq)
	134	return 0;
	135
	136	timer_counter = ioread32(davinci_wdt->base + TIM12);
	137	timer_counter \|= ((u64)ioread32(davinci_wdt->base + TIM34) << 32);
	138
	139	do_div(timer_counter, freq);
	140
	141	return wdd->timeout - timer_counter;
	142	}
	143
	144	static const struct watchdog_info davinci_wdt_info = {
	145	.options = WDIOF_KEEPALIVEPING,
	146	.identity = "DaVinci Watchdog",
	147	};
	148
	149	static const struct watchdog_ops davinci_wdt_ops = {
	150	.owner = THIS_MODULE,
	151	.start = davinci_wdt_start,
	152	.stop = davinci_wdt_ping,
	153	.ping = davinci_wdt_ping,
	154	.get_timeleft = davinci_wdt_get_timeleft,
	155	};
	156
	157	static int davinci_wdt_probe(struct platform_device *pdev)
	158	{
	159	int ret = 0;
	160	struct device *dev = &pdev->dev;
	161	struct resource *wdt_mem;
	162	struct watchdog_device *wdd;
	163	struct davinci_wdt_device *davinci_wdt;
	164
	165	davinci_wdt = devm_kzalloc(dev, sizeof(*davinci_wdt), GFP_KERNEL);
	166	if (!davinci_wdt)
	167	return -ENOMEM;
	168
	169	davinci_wdt->clk = devm_clk_get(dev, NULL);
	170	if (WARN_ON(IS_ERR(davinci_wdt->clk)))
	171	return PTR_ERR(davinci_wdt->clk);
	172
	173	clk_prepare_enable(davinci_wdt->clk);
	174
	175	platform_set_drvdata(pdev, davinci_wdt);
	176
	177	wdd = &davinci_wdt->wdd;
	178	wdd->info = &davinci_wdt_info;
	179	wdd->ops = &davinci_wdt_ops;
	180	wdd->min_timeout = 1;
	181	wdd->max_timeout = MAX_HEARTBEAT;
	182	wdd->timeout = DEFAULT_HEARTBEAT;
	183
	184	watchdog_init_timeout(wdd, heartbeat, dev);
	185
	186	dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
	187
	188	watchdog_set_drvdata(wdd, davinci_wdt);
	189	watchdog_set_nowayout(wdd, 1);
	190
	191	wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	192	davinci_wdt->base = devm_ioremap_resource(dev, wdt_mem);
	193	if (IS_ERR(davinci_wdt->base))
	194	return PTR_ERR(davinci_wdt->base);
	195
	196	ret = watchdog_register_device(wdd);
	197	if (ret < 0)
	198	dev_err(dev, "cannot register watchdog device\n");
	199
	200	return ret;
	201	}
	202
	203	static int davinci_wdt_remove(struct platform_device *pdev)
	204	{
	205	struct davinci_wdt_device *davinci_wdt = platform_get_drvdata(pdev);
	206
	207	watchdog_unregister_device(&davinci_wdt->wdd);
	208	clk_disable_unprepare(davinci_wdt->clk);
	209
	210	return 0;
	211	}
	212
	213	static const struct of_device_id davinci_wdt_of_match[] = {
	214	{ .compatible = "ti,davinci-wdt", },
	215	{},
	216	};
	217	MODULE_DEVICE_TABLE(of, davinci_wdt_of_match);
	218
	219	static struct platform_driver platform_wdt_driver = {
	220	.driver = {
	221	.name = "davinci-wdt",
	222	.owner = THIS_MODULE,
	223	.of_match_table = davinci_wdt_of_match,
	224	},
	225	.probe = davinci_wdt_probe,
	226	.remove = davinci_wdt_remove,
	227	};
	228
	229	module_platform_driver(platform_wdt_driver);
	230
	231	MODULE_AUTHOR("Texas Instruments");
	232	MODULE_DESCRIPTION("DaVinci Watchdog Driver");
	233
	234	module_param(heartbeat, int, 0);
	235	MODULE_PARM_DESC(heartbeat,
	236	"Watchdog heartbeat period in seconds from 1 to "
	237	__MODULE_STRING(MAX_HEARTBEAT) ", default "
	238	__MODULE_STRING(DEFAULT_HEARTBEAT));
	239
	240	MODULE_LICENSE("GPL");
	241	MODULE_ALIAS("platform:davinci-wdt");