| 1 | /* |
| 2 | * intel TCO Watchdog Driver |
| 3 | * |
| 4 | * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor |
| 12 | * provide warranty for any of this software. This material is |
| 13 | * provided "AS-IS" and at no charge. |
| 14 | * |
| 15 | * The TCO watchdog is implemented in the following I/O controller hubs: |
| 16 | * (See the intel documentation on http://developer.intel.com.) |
| 17 | * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) |
| 18 | * document number 290687-002, 298242-027: 82801BA (ICH2) |
| 19 | * document number 290733-003, 290739-013: 82801CA (ICH3-S) |
| 20 | * document number 290716-001, 290718-007: 82801CAM (ICH3-M) |
| 21 | * document number 290744-001, 290745-025: 82801DB (ICH4) |
| 22 | * document number 252337-001, 252663-008: 82801DBM (ICH4-M) |
| 23 | * document number 273599-001, 273645-002: 82801E (C-ICH) |
| 24 | * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) |
| 25 | * document number 300641-004, 300884-013: 6300ESB |
| 26 | * document number 301473-002, 301474-026: 82801F (ICH6) |
| 27 | * document number 313082-001, 313075-006: 631xESB, 632xESB |
| 28 | * document number 307013-003, 307014-024: 82801G (ICH7) |
| 29 | * document number 322896-001, 322897-001: NM10 |
| 30 | * document number 313056-003, 313057-017: 82801H (ICH8) |
| 31 | * document number 316972-004, 316973-012: 82801I (ICH9) |
| 32 | * document number 319973-002, 319974-002: 82801J (ICH10) |
| 33 | * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) |
| 34 | * document number 320066-003, 320257-008: EP80597 (IICH) |
| 35 | * document number 324645-001, 324646-001: Cougar Point (CPT) |
| 36 | * document number TBD : Patsburg (PBG) |
| 37 | * document number TBD : DH89xxCC |
| 38 | * document number TBD : Panther Point |
| 39 | * document number TBD : Lynx Point |
| 40 | * document number TBD : Lynx Point-LP |
| 41 | */ |
| 42 | |
| 43 | /* |
| 44 | * Includes, defines, variables, module parameters, ... |
| 45 | */ |
| 46 | |
| 47 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 48 | |
| 49 | /* Module and version information */ |
| 50 | #define DRV_NAME "iTCO_wdt" |
| 51 | #define DRV_VERSION "1.11" |
| 52 | |
| 53 | /* Includes */ |
| 54 | #include <linux/acpi.h> /* For ACPI support */ |
| 55 | #include <linux/module.h> /* For module specific items */ |
| 56 | #include <linux/moduleparam.h> /* For new moduleparam's */ |
| 57 | #include <linux/types.h> /* For standard types (like size_t) */ |
| 58 | #include <linux/errno.h> /* For the -ENODEV/... values */ |
| 59 | #include <linux/kernel.h> /* For printk/panic/... */ |
| 60 | #include <linux/watchdog.h> /* For the watchdog specific items */ |
| 61 | #include <linux/init.h> /* For __init/__exit/... */ |
| 62 | #include <linux/fs.h> /* For file operations */ |
| 63 | #include <linux/platform_device.h> /* For platform_driver framework */ |
| 64 | #include <linux/pci.h> /* For pci functions */ |
| 65 | #include <linux/ioport.h> /* For io-port access */ |
| 66 | #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */ |
| 67 | #include <linux/uaccess.h> /* For copy_to_user/put_user/... */ |
| 68 | #include <linux/io.h> /* For inb/outb/... */ |
| 69 | #include <linux/mfd/core.h> |
| 70 | #include <linux/mfd/lpc_ich.h> |
| 71 | |
| 72 | #include "iTCO_vendor.h" |
| 73 | |
| 74 | /* Address definitions for the TCO */ |
| 75 | /* TCO base address */ |
| 76 | #define TCOBASE (iTCO_wdt_private.tco_res->start) |
| 77 | /* SMI Control and Enable Register */ |
| 78 | #define SMI_EN (iTCO_wdt_private.smi_res->start) |
| 79 | |
| 80 | #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */ |
| 81 | #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */ |
| 82 | #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */ |
| 83 | #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */ |
| 84 | #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */ |
| 85 | #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */ |
| 86 | #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */ |
| 87 | #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */ |
| 88 | #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */ |
| 89 | |
| 90 | /* internal variables */ |
| 91 | static struct { /* this is private data for the iTCO_wdt device */ |
| 92 | /* TCO version/generation */ |
| 93 | unsigned int iTCO_version; |
| 94 | struct resource *tco_res; |
| 95 | struct resource *smi_res; |
| 96 | /* |
| 97 | * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2), |
| 98 | * or memory-mapped PMC register bit 4 (TCO version 3). |
| 99 | */ |
| 100 | struct resource *gcs_pmc_res; |
| 101 | unsigned long __iomem *gcs_pmc; |
| 102 | /* the lock for io operations */ |
| 103 | spinlock_t io_lock; |
| 104 | struct platform_device *dev; |
| 105 | /* the PCI-device */ |
| 106 | struct pci_dev *pdev; |
| 107 | /* whether or not the watchdog has been suspended */ |
| 108 | bool suspended; |
| 109 | } iTCO_wdt_private; |
| 110 | |
| 111 | /* module parameters */ |
| 112 | #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */ |
| 113 | static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */ |
| 114 | module_param(heartbeat, int, 0); |
| 115 | MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. " |
| 116 | "5..76 (TCO v1) or 3..614 (TCO v2), default=" |
| 117 | __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); |
| 118 | |
| 119 | static bool nowayout = WATCHDOG_NOWAYOUT; |
| 120 | module_param(nowayout, bool, 0); |
| 121 | MODULE_PARM_DESC(nowayout, |
| 122 | "Watchdog cannot be stopped once started (default=" |
| 123 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
| 124 | |
| 125 | static int turn_SMI_watchdog_clear_off = 1; |
| 126 | module_param(turn_SMI_watchdog_clear_off, int, 0); |
| 127 | MODULE_PARM_DESC(turn_SMI_watchdog_clear_off, |
| 128 | "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)"); |
| 129 | |
| 130 | /* |
| 131 | * Some TCO specific functions |
| 132 | */ |
| 133 | |
| 134 | /* |
| 135 | * The iTCO v1 and v2's internal timer is stored as ticks which decrement |
| 136 | * every 0.6 seconds. v3's internal timer is stored as seconds (some |
| 137 | * datasheets incorrectly state 0.6 seconds). |
| 138 | */ |
| 139 | static inline unsigned int seconds_to_ticks(int secs) |
| 140 | { |
| 141 | return iTCO_wdt_private.iTCO_version == 3 ? secs : (secs * 10) / 6; |
| 142 | } |
| 143 | |
| 144 | static inline unsigned int ticks_to_seconds(int ticks) |
| 145 | { |
| 146 | return iTCO_wdt_private.iTCO_version == 3 ? ticks : (ticks * 6) / 10; |
| 147 | } |
| 148 | |
| 149 | static void iTCO_wdt_set_NO_REBOOT_bit(void) |
| 150 | { |
| 151 | u32 val32; |
| 152 | |
| 153 | /* Set the NO_REBOOT bit: this disables reboots */ |
| 154 | if (iTCO_wdt_private.iTCO_version == 3) { |
| 155 | val32 = readl(iTCO_wdt_private.gcs_pmc); |
| 156 | val32 |= 0x00000010; |
| 157 | writel(val32, iTCO_wdt_private.gcs_pmc); |
| 158 | } else if (iTCO_wdt_private.iTCO_version == 2) { |
| 159 | val32 = readl(iTCO_wdt_private.gcs_pmc); |
| 160 | val32 |= 0x00000020; |
| 161 | writel(val32, iTCO_wdt_private.gcs_pmc); |
| 162 | } else if (iTCO_wdt_private.iTCO_version == 1) { |
| 163 | pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); |
| 164 | val32 |= 0x00000002; |
| 165 | pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | static int iTCO_wdt_unset_NO_REBOOT_bit(void) |
| 170 | { |
| 171 | int ret = 0; |
| 172 | u32 val32; |
| 173 | |
| 174 | /* Unset the NO_REBOOT bit: this enables reboots */ |
| 175 | if (iTCO_wdt_private.iTCO_version == 3) { |
| 176 | val32 = readl(iTCO_wdt_private.gcs_pmc); |
| 177 | val32 &= 0xffffffef; |
| 178 | writel(val32, iTCO_wdt_private.gcs_pmc); |
| 179 | |
| 180 | val32 = readl(iTCO_wdt_private.gcs_pmc); |
| 181 | if (val32 & 0x00000010) |
| 182 | ret = -EIO; |
| 183 | } else if (iTCO_wdt_private.iTCO_version == 2) { |
| 184 | val32 = readl(iTCO_wdt_private.gcs_pmc); |
| 185 | val32 &= 0xffffffdf; |
| 186 | writel(val32, iTCO_wdt_private.gcs_pmc); |
| 187 | |
| 188 | val32 = readl(iTCO_wdt_private.gcs_pmc); |
| 189 | if (val32 & 0x00000020) |
| 190 | ret = -EIO; |
| 191 | } else if (iTCO_wdt_private.iTCO_version == 1) { |
| 192 | pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); |
| 193 | val32 &= 0xfffffffd; |
| 194 | pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32); |
| 195 | |
| 196 | pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32); |
| 197 | if (val32 & 0x00000002) |
| 198 | ret = -EIO; |
| 199 | } |
| 200 | |
| 201 | return ret; /* returns: 0 = OK, -EIO = Error */ |
| 202 | } |
| 203 | |
| 204 | static int iTCO_wdt_start(struct watchdog_device *wd_dev) |
| 205 | { |
| 206 | unsigned int val; |
| 207 | |
| 208 | spin_lock(&iTCO_wdt_private.io_lock); |
| 209 | |
| 210 | iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout); |
| 211 | |
| 212 | /* disable chipset's NO_REBOOT bit */ |
| 213 | if (iTCO_wdt_unset_NO_REBOOT_bit()) { |
| 214 | spin_unlock(&iTCO_wdt_private.io_lock); |
| 215 | pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n"); |
| 216 | return -EIO; |
| 217 | } |
| 218 | |
| 219 | /* Force the timer to its reload value by writing to the TCO_RLD |
| 220 | register */ |
| 221 | if (iTCO_wdt_private.iTCO_version >= 2) |
| 222 | outw(0x01, TCO_RLD); |
| 223 | else if (iTCO_wdt_private.iTCO_version == 1) |
| 224 | outb(0x01, TCO_RLD); |
| 225 | |
| 226 | /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ |
| 227 | val = inw(TCO1_CNT); |
| 228 | val &= 0xf7ff; |
| 229 | outw(val, TCO1_CNT); |
| 230 | val = inw(TCO1_CNT); |
| 231 | spin_unlock(&iTCO_wdt_private.io_lock); |
| 232 | |
| 233 | if (val & 0x0800) |
| 234 | return -1; |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | static int iTCO_wdt_stop(struct watchdog_device *wd_dev) |
| 239 | { |
| 240 | unsigned int val; |
| 241 | |
| 242 | spin_lock(&iTCO_wdt_private.io_lock); |
| 243 | |
| 244 | iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res); |
| 245 | |
| 246 | /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */ |
| 247 | val = inw(TCO1_CNT); |
| 248 | val |= 0x0800; |
| 249 | outw(val, TCO1_CNT); |
| 250 | val = inw(TCO1_CNT); |
| 251 | |
| 252 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ |
| 253 | iTCO_wdt_set_NO_REBOOT_bit(); |
| 254 | |
| 255 | spin_unlock(&iTCO_wdt_private.io_lock); |
| 256 | |
| 257 | if ((val & 0x0800) == 0) |
| 258 | return -1; |
| 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | static int iTCO_wdt_ping(struct watchdog_device *wd_dev) |
| 263 | { |
| 264 | spin_lock(&iTCO_wdt_private.io_lock); |
| 265 | |
| 266 | iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout); |
| 267 | |
| 268 | /* Reload the timer by writing to the TCO Timer Counter register */ |
| 269 | if (iTCO_wdt_private.iTCO_version >= 2) { |
| 270 | outw(0x01, TCO_RLD); |
| 271 | } else if (iTCO_wdt_private.iTCO_version == 1) { |
| 272 | /* Reset the timeout status bit so that the timer |
| 273 | * needs to count down twice again before rebooting */ |
| 274 | outw(0x0008, TCO1_STS); /* write 1 to clear bit */ |
| 275 | |
| 276 | outb(0x01, TCO_RLD); |
| 277 | } |
| 278 | |
| 279 | spin_unlock(&iTCO_wdt_private.io_lock); |
| 280 | return 0; |
| 281 | } |
| 282 | |
| 283 | static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t) |
| 284 | { |
| 285 | unsigned int val16; |
| 286 | unsigned char val8; |
| 287 | unsigned int tmrval; |
| 288 | |
| 289 | tmrval = seconds_to_ticks(t); |
| 290 | |
| 291 | /* For TCO v1 the timer counts down twice before rebooting */ |
| 292 | if (iTCO_wdt_private.iTCO_version == 1) |
| 293 | tmrval /= 2; |
| 294 | |
| 295 | /* from the specs: */ |
| 296 | /* "Values of 0h-3h are ignored and should not be attempted" */ |
| 297 | if (tmrval < 0x04) |
| 298 | return -EINVAL; |
| 299 | if (((iTCO_wdt_private.iTCO_version >= 2) && (tmrval > 0x3ff)) || |
| 300 | ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f))) |
| 301 | return -EINVAL; |
| 302 | |
| 303 | iTCO_vendor_pre_set_heartbeat(tmrval); |
| 304 | |
| 305 | /* Write new heartbeat to watchdog */ |
| 306 | if (iTCO_wdt_private.iTCO_version >= 2) { |
| 307 | spin_lock(&iTCO_wdt_private.io_lock); |
| 308 | val16 = inw(TCOv2_TMR); |
| 309 | val16 &= 0xfc00; |
| 310 | val16 |= tmrval; |
| 311 | outw(val16, TCOv2_TMR); |
| 312 | val16 = inw(TCOv2_TMR); |
| 313 | spin_unlock(&iTCO_wdt_private.io_lock); |
| 314 | |
| 315 | if ((val16 & 0x3ff) != tmrval) |
| 316 | return -EINVAL; |
| 317 | } else if (iTCO_wdt_private.iTCO_version == 1) { |
| 318 | spin_lock(&iTCO_wdt_private.io_lock); |
| 319 | val8 = inb(TCOv1_TMR); |
| 320 | val8 &= 0xc0; |
| 321 | val8 |= (tmrval & 0xff); |
| 322 | outb(val8, TCOv1_TMR); |
| 323 | val8 = inb(TCOv1_TMR); |
| 324 | spin_unlock(&iTCO_wdt_private.io_lock); |
| 325 | |
| 326 | if ((val8 & 0x3f) != tmrval) |
| 327 | return -EINVAL; |
| 328 | } |
| 329 | |
| 330 | wd_dev->timeout = t; |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) |
| 335 | { |
| 336 | unsigned int val16; |
| 337 | unsigned char val8; |
| 338 | unsigned int time_left = 0; |
| 339 | |
| 340 | /* read the TCO Timer */ |
| 341 | if (iTCO_wdt_private.iTCO_version >= 2) { |
| 342 | spin_lock(&iTCO_wdt_private.io_lock); |
| 343 | val16 = inw(TCO_RLD); |
| 344 | val16 &= 0x3ff; |
| 345 | spin_unlock(&iTCO_wdt_private.io_lock); |
| 346 | |
| 347 | time_left = ticks_to_seconds(val16); |
| 348 | } else if (iTCO_wdt_private.iTCO_version == 1) { |
| 349 | spin_lock(&iTCO_wdt_private.io_lock); |
| 350 | val8 = inb(TCO_RLD); |
| 351 | val8 &= 0x3f; |
| 352 | if (!(inw(TCO1_STS) & 0x0008)) |
| 353 | val8 += (inb(TCOv1_TMR) & 0x3f); |
| 354 | spin_unlock(&iTCO_wdt_private.io_lock); |
| 355 | |
| 356 | time_left = ticks_to_seconds(val8); |
| 357 | } |
| 358 | return time_left; |
| 359 | } |
| 360 | |
| 361 | /* |
| 362 | * Kernel Interfaces |
| 363 | */ |
| 364 | |
| 365 | static const struct watchdog_info ident = { |
| 366 | .options = WDIOF_SETTIMEOUT | |
| 367 | WDIOF_KEEPALIVEPING | |
| 368 | WDIOF_MAGICCLOSE, |
| 369 | .firmware_version = 0, |
| 370 | .identity = DRV_NAME, |
| 371 | }; |
| 372 | |
| 373 | static const struct watchdog_ops iTCO_wdt_ops = { |
| 374 | .owner = THIS_MODULE, |
| 375 | .start = iTCO_wdt_start, |
| 376 | .stop = iTCO_wdt_stop, |
| 377 | .ping = iTCO_wdt_ping, |
| 378 | .set_timeout = iTCO_wdt_set_timeout, |
| 379 | .get_timeleft = iTCO_wdt_get_timeleft, |
| 380 | }; |
| 381 | |
| 382 | static struct watchdog_device iTCO_wdt_watchdog_dev = { |
| 383 | .info = &ident, |
| 384 | .ops = &iTCO_wdt_ops, |
| 385 | }; |
| 386 | |
| 387 | /* |
| 388 | * Init & exit routines |
| 389 | */ |
| 390 | |
| 391 | static void iTCO_wdt_cleanup(void) |
| 392 | { |
| 393 | /* Stop the timer before we leave */ |
| 394 | if (!nowayout) |
| 395 | iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); |
| 396 | |
| 397 | /* Deregister */ |
| 398 | watchdog_unregister_device(&iTCO_wdt_watchdog_dev); |
| 399 | |
| 400 | /* release resources */ |
| 401 | release_region(iTCO_wdt_private.tco_res->start, |
| 402 | resource_size(iTCO_wdt_private.tco_res)); |
| 403 | release_region(iTCO_wdt_private.smi_res->start, |
| 404 | resource_size(iTCO_wdt_private.smi_res)); |
| 405 | if (iTCO_wdt_private.iTCO_version >= 2) { |
| 406 | iounmap(iTCO_wdt_private.gcs_pmc); |
| 407 | release_mem_region(iTCO_wdt_private.gcs_pmc_res->start, |
| 408 | resource_size(iTCO_wdt_private.gcs_pmc_res)); |
| 409 | } |
| 410 | |
| 411 | iTCO_wdt_private.tco_res = NULL; |
| 412 | iTCO_wdt_private.smi_res = NULL; |
| 413 | iTCO_wdt_private.gcs_pmc_res = NULL; |
| 414 | iTCO_wdt_private.gcs_pmc = NULL; |
| 415 | } |
| 416 | |
| 417 | static int iTCO_wdt_probe(struct platform_device *dev) |
| 418 | { |
| 419 | int ret = -ENODEV; |
| 420 | unsigned long val32; |
| 421 | struct lpc_ich_info *ich_info = dev_get_platdata(&dev->dev); |
| 422 | |
| 423 | if (!ich_info) |
| 424 | goto out; |
| 425 | |
| 426 | spin_lock_init(&iTCO_wdt_private.io_lock); |
| 427 | |
| 428 | iTCO_wdt_private.tco_res = |
| 429 | platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO); |
| 430 | if (!iTCO_wdt_private.tco_res) |
| 431 | goto out; |
| 432 | |
| 433 | iTCO_wdt_private.smi_res = |
| 434 | platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI); |
| 435 | if (!iTCO_wdt_private.smi_res) |
| 436 | goto out; |
| 437 | |
| 438 | iTCO_wdt_private.iTCO_version = ich_info->iTCO_version; |
| 439 | iTCO_wdt_private.dev = dev; |
| 440 | iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent); |
| 441 | |
| 442 | /* |
| 443 | * Get the Memory-Mapped GCS or PMC register, we need it for the |
| 444 | * NO_REBOOT flag (TCO v2 and v3). |
| 445 | */ |
| 446 | if (iTCO_wdt_private.iTCO_version >= 2) { |
| 447 | iTCO_wdt_private.gcs_pmc_res = platform_get_resource(dev, |
| 448 | IORESOURCE_MEM, |
| 449 | ICH_RES_MEM_GCS_PMC); |
| 450 | |
| 451 | if (!iTCO_wdt_private.gcs_pmc_res) |
| 452 | goto out; |
| 453 | |
| 454 | if (!request_mem_region(iTCO_wdt_private.gcs_pmc_res->start, |
| 455 | resource_size(iTCO_wdt_private.gcs_pmc_res), dev->name)) { |
| 456 | ret = -EBUSY; |
| 457 | goto out; |
| 458 | } |
| 459 | iTCO_wdt_private.gcs_pmc = ioremap(iTCO_wdt_private.gcs_pmc_res->start, |
| 460 | resource_size(iTCO_wdt_private.gcs_pmc_res)); |
| 461 | if (!iTCO_wdt_private.gcs_pmc) { |
| 462 | ret = -EIO; |
| 463 | goto unreg_gcs_pmc; |
| 464 | } |
| 465 | } |
| 466 | |
| 467 | /* Check chipset's NO_REBOOT bit */ |
| 468 | if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) { |
| 469 | pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n"); |
| 470 | ret = -ENODEV; /* Cannot reset NO_REBOOT bit */ |
| 471 | goto unmap_gcs_pmc; |
| 472 | } |
| 473 | |
| 474 | /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ |
| 475 | iTCO_wdt_set_NO_REBOOT_bit(); |
| 476 | |
| 477 | /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ |
| 478 | if (!request_region(iTCO_wdt_private.smi_res->start, |
| 479 | resource_size(iTCO_wdt_private.smi_res), dev->name)) { |
| 480 | pr_err("I/O address 0x%04llx already in use, device disabled\n", |
| 481 | (u64)SMI_EN); |
| 482 | ret = -EBUSY; |
| 483 | goto unmap_gcs_pmc; |
| 484 | } |
| 485 | if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) { |
| 486 | /* |
| 487 | * Bit 13: TCO_EN -> 0 |
| 488 | * Disables TCO logic generating an SMI# |
| 489 | */ |
| 490 | val32 = inl(SMI_EN); |
| 491 | val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ |
| 492 | outl(val32, SMI_EN); |
| 493 | } |
| 494 | |
| 495 | if (!request_region(iTCO_wdt_private.tco_res->start, |
| 496 | resource_size(iTCO_wdt_private.tco_res), dev->name)) { |
| 497 | pr_err("I/O address 0x%04llx already in use, device disabled\n", |
| 498 | (u64)TCOBASE); |
| 499 | ret = -EBUSY; |
| 500 | goto unreg_smi; |
| 501 | } |
| 502 | |
| 503 | pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n", |
| 504 | ich_info->name, ich_info->iTCO_version, (u64)TCOBASE); |
| 505 | |
| 506 | /* Clear out the (probably old) status */ |
| 507 | if (iTCO_wdt_private.iTCO_version == 3) { |
| 508 | outl(0x20008, TCO1_STS); |
| 509 | } else { |
| 510 | outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */ |
| 511 | outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */ |
| 512 | outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */ |
| 513 | } |
| 514 | |
| 515 | iTCO_wdt_watchdog_dev.bootstatus = 0; |
| 516 | iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT; |
| 517 | watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout); |
| 518 | iTCO_wdt_watchdog_dev.parent = &dev->dev; |
| 519 | |
| 520 | /* Make sure the watchdog is not running */ |
| 521 | iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); |
| 522 | |
| 523 | /* Check that the heartbeat value is within it's range; |
| 524 | if not reset to the default */ |
| 525 | if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) { |
| 526 | iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT); |
| 527 | pr_info("timeout value out of range, using %d\n", |
| 528 | WATCHDOG_TIMEOUT); |
| 529 | } |
| 530 | |
| 531 | ret = watchdog_register_device(&iTCO_wdt_watchdog_dev); |
| 532 | if (ret != 0) { |
| 533 | pr_err("cannot register watchdog device (err=%d)\n", ret); |
| 534 | goto unreg_tco; |
| 535 | } |
| 536 | |
| 537 | pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n", |
| 538 | heartbeat, nowayout); |
| 539 | |
| 540 | return 0; |
| 541 | |
| 542 | unreg_tco: |
| 543 | release_region(iTCO_wdt_private.tco_res->start, |
| 544 | resource_size(iTCO_wdt_private.tco_res)); |
| 545 | unreg_smi: |
| 546 | release_region(iTCO_wdt_private.smi_res->start, |
| 547 | resource_size(iTCO_wdt_private.smi_res)); |
| 548 | unmap_gcs_pmc: |
| 549 | if (iTCO_wdt_private.iTCO_version >= 2) |
| 550 | iounmap(iTCO_wdt_private.gcs_pmc); |
| 551 | unreg_gcs_pmc: |
| 552 | if (iTCO_wdt_private.iTCO_version >= 2) |
| 553 | release_mem_region(iTCO_wdt_private.gcs_pmc_res->start, |
| 554 | resource_size(iTCO_wdt_private.gcs_pmc_res)); |
| 555 | out: |
| 556 | iTCO_wdt_private.tco_res = NULL; |
| 557 | iTCO_wdt_private.smi_res = NULL; |
| 558 | iTCO_wdt_private.gcs_pmc_res = NULL; |
| 559 | iTCO_wdt_private.gcs_pmc = NULL; |
| 560 | |
| 561 | return ret; |
| 562 | } |
| 563 | |
| 564 | static int iTCO_wdt_remove(struct platform_device *dev) |
| 565 | { |
| 566 | if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res) |
| 567 | iTCO_wdt_cleanup(); |
| 568 | |
| 569 | return 0; |
| 570 | } |
| 571 | |
| 572 | static void iTCO_wdt_shutdown(struct platform_device *dev) |
| 573 | { |
| 574 | iTCO_wdt_stop(NULL); |
| 575 | } |
| 576 | |
| 577 | #ifdef CONFIG_PM_SLEEP |
| 578 | /* |
| 579 | * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so |
| 580 | * the watchdog cannot be pinged while in that state. In ACPI sleep states the |
| 581 | * watchdog is stopped by the platform firmware. |
| 582 | */ |
| 583 | |
| 584 | #ifdef CONFIG_ACPI |
| 585 | static inline bool need_suspend(void) |
| 586 | { |
| 587 | return acpi_target_system_state() == ACPI_STATE_S0; |
| 588 | } |
| 589 | #else |
| 590 | static inline bool need_suspend(void) { return true; } |
| 591 | #endif |
| 592 | |
| 593 | static int iTCO_wdt_suspend_noirq(struct device *dev) |
| 594 | { |
| 595 | int ret = 0; |
| 596 | |
| 597 | iTCO_wdt_private.suspended = false; |
| 598 | if (watchdog_active(&iTCO_wdt_watchdog_dev) && need_suspend()) { |
| 599 | ret = iTCO_wdt_stop(&iTCO_wdt_watchdog_dev); |
| 600 | if (!ret) |
| 601 | iTCO_wdt_private.suspended = true; |
| 602 | } |
| 603 | return ret; |
| 604 | } |
| 605 | |
| 606 | static int iTCO_wdt_resume_noirq(struct device *dev) |
| 607 | { |
| 608 | if (iTCO_wdt_private.suspended) |
| 609 | iTCO_wdt_start(&iTCO_wdt_watchdog_dev); |
| 610 | |
| 611 | return 0; |
| 612 | } |
| 613 | |
| 614 | static struct dev_pm_ops iTCO_wdt_pm = { |
| 615 | .suspend_noirq = iTCO_wdt_suspend_noirq, |
| 616 | .resume_noirq = iTCO_wdt_resume_noirq, |
| 617 | }; |
| 618 | |
| 619 | #define ITCO_WDT_PM_OPS (&iTCO_wdt_pm) |
| 620 | #else |
| 621 | #define ITCO_WDT_PM_OPS NULL |
| 622 | #endif /* CONFIG_PM_SLEEP */ |
| 623 | |
| 624 | static struct platform_driver iTCO_wdt_driver = { |
| 625 | .probe = iTCO_wdt_probe, |
| 626 | .remove = iTCO_wdt_remove, |
| 627 | .shutdown = iTCO_wdt_shutdown, |
| 628 | .driver = { |
| 629 | .name = DRV_NAME, |
| 630 | .pm = ITCO_WDT_PM_OPS, |
| 631 | }, |
| 632 | }; |
| 633 | |
| 634 | static int __init iTCO_wdt_init_module(void) |
| 635 | { |
| 636 | int err; |
| 637 | |
| 638 | pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION); |
| 639 | |
| 640 | err = platform_driver_register(&iTCO_wdt_driver); |
| 641 | if (err) |
| 642 | return err; |
| 643 | |
| 644 | return 0; |
| 645 | } |
| 646 | |
| 647 | static void __exit iTCO_wdt_cleanup_module(void) |
| 648 | { |
| 649 | platform_driver_unregister(&iTCO_wdt_driver); |
| 650 | pr_info("Watchdog Module Unloaded\n"); |
| 651 | } |
| 652 | |
| 653 | module_init(iTCO_wdt_init_module); |
| 654 | module_exit(iTCO_wdt_cleanup_module); |
| 655 | |
| 656 | MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>"); |
| 657 | MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver"); |
| 658 | MODULE_VERSION(DRV_VERSION); |
| 659 | MODULE_LICENSE("GPL"); |
| 660 | MODULE_ALIAS("platform:" DRV_NAME); |