| 1 | /* tc-d10v.c -- Assembler code for the Mitsubishi D10V |
| 2 | Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation. |
| 3 | |
| 4 | This file is part of GAS, the GNU Assembler. |
| 5 | |
| 6 | GAS is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2, or (at your option) |
| 9 | any later version. |
| 10 | |
| 11 | GAS is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with GAS; see the file COPYING. If not, write to |
| 18 | the Free Software Foundation, 59 Temple Place - Suite 330, |
| 19 | Boston, MA 02111-1307, USA. */ |
| 20 | |
| 21 | #include <stdio.h> |
| 22 | #include <ctype.h> |
| 23 | #include "as.h" |
| 24 | #include "subsegs.h" |
| 25 | #include "opcode/d10v.h" |
| 26 | #include "elf/ppc.h" |
| 27 | |
| 28 | const char comment_chars[] = ";"; |
| 29 | const char line_comment_chars[] = "#"; |
| 30 | const char line_separator_chars[] = ""; |
| 31 | const char *md_shortopts = "O"; |
| 32 | const char EXP_CHARS[] = "eE"; |
| 33 | const char FLT_CHARS[] = "dD"; |
| 34 | |
| 35 | int Optimizing = 0; |
| 36 | |
| 37 | #define AT_WORD_P(X) ((X)->X_op == O_right_shift \ |
| 38 | && (X)->X_op_symbol != NULL \ |
| 39 | && symbol_constant_p ((X)->X_op_symbol) \ |
| 40 | && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT) |
| 41 | #define AT_WORD_RIGHT_SHIFT 2 |
| 42 | |
| 43 | |
| 44 | /* fixups */ |
| 45 | #define MAX_INSN_FIXUPS (5) |
| 46 | struct d10v_fixup |
| 47 | { |
| 48 | expressionS exp; |
| 49 | int operand; |
| 50 | int pcrel; |
| 51 | int size; |
| 52 | bfd_reloc_code_real_type reloc; |
| 53 | }; |
| 54 | |
| 55 | typedef struct _fixups |
| 56 | { |
| 57 | int fc; |
| 58 | struct d10v_fixup fix[MAX_INSN_FIXUPS]; |
| 59 | struct _fixups *next; |
| 60 | } Fixups; |
| 61 | |
| 62 | static Fixups FixUps[2]; |
| 63 | static Fixups *fixups; |
| 64 | |
| 65 | static int do_not_ignore_hash = 0; |
| 66 | |
| 67 | /* True if instruction swapping warnings should be inhibited. */ |
| 68 | static unsigned char flag_warn_suppress_instructionswap; /* --nowarnswap */ |
| 69 | |
| 70 | /* local functions */ |
| 71 | static int reg_name_search PARAMS ((char *name)); |
| 72 | static int register_name PARAMS ((expressionS *expressionP)); |
| 73 | static int check_range PARAMS ((unsigned long num, int bits, int flags)); |
| 74 | static int postfix PARAMS ((char *p)); |
| 75 | static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op)); |
| 76 | static int get_operands PARAMS ((expressionS exp[])); |
| 77 | static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[])); |
| 78 | static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn)); |
| 79 | static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); |
| 80 | static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); |
| 81 | static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, |
| 82 | struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx)); |
| 83 | static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode)); |
| 84 | static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type, |
| 85 | offsetT value, int left, fixS *fix)); |
| 86 | static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, |
| 87 | struct d10v_opcode *opcode2, unsigned long insn2, |
| 88 | int exec_type)); |
| 89 | static symbolS * find_symbol_matching_register PARAMS ((expressionS *)); |
| 90 | |
| 91 | struct option md_longopts[] = |
| 92 | { |
| 93 | #define OPTION_NOWARNSWAP (OPTION_MD_BASE) |
| 94 | {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, |
| 95 | {NULL, no_argument, NULL, 0} |
| 96 | }; |
| 97 | size_t md_longopts_size = sizeof(md_longopts); |
| 98 | |
| 99 | static void d10v_dot_word PARAMS ((int)); |
| 100 | |
| 101 | /* The target specific pseudo-ops which we support. */ |
| 102 | const pseudo_typeS md_pseudo_table[] = |
| 103 | { |
| 104 | { "word", d10v_dot_word, 2 }, |
| 105 | { NULL, NULL, 0 } |
| 106 | }; |
| 107 | |
| 108 | /* Opcode hash table. */ |
| 109 | static struct hash_control *d10v_hash; |
| 110 | |
| 111 | /* reg_name_search does a binary search of the d10v_predefined_registers |
| 112 | array to see if "name" is a valid regiter name. Returns the register |
| 113 | number from the array on success, or -1 on failure. */ |
| 114 | |
| 115 | static int |
| 116 | reg_name_search (name) |
| 117 | char *name; |
| 118 | { |
| 119 | int middle, low, high; |
| 120 | int cmp; |
| 121 | |
| 122 | low = 0; |
| 123 | high = d10v_reg_name_cnt() - 1; |
| 124 | |
| 125 | do |
| 126 | { |
| 127 | middle = (low + high) / 2; |
| 128 | cmp = strcasecmp (name, d10v_predefined_registers[middle].name); |
| 129 | if (cmp < 0) |
| 130 | high = middle - 1; |
| 131 | else if (cmp > 0) |
| 132 | low = middle + 1; |
| 133 | else |
| 134 | return d10v_predefined_registers[middle].value; |
| 135 | } |
| 136 | while (low <= high); |
| 137 | return -1; |
| 138 | } |
| 139 | |
| 140 | /* register_name() checks the string at input_line_pointer |
| 141 | to see if it is a valid register name */ |
| 142 | |
| 143 | static int |
| 144 | register_name (expressionP) |
| 145 | expressionS *expressionP; |
| 146 | { |
| 147 | int reg_number; |
| 148 | char c, *p = input_line_pointer; |
| 149 | |
| 150 | while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')') |
| 151 | p++; |
| 152 | |
| 153 | c = *p; |
| 154 | if (c) |
| 155 | *p++ = 0; |
| 156 | |
| 157 | /* look to see if it's in the register table */ |
| 158 | reg_number = reg_name_search (input_line_pointer); |
| 159 | if (reg_number >= 0) |
| 160 | { |
| 161 | expressionP->X_op = O_register; |
| 162 | /* temporarily store a pointer to the string here */ |
| 163 | expressionP->X_op_symbol = (symbolS *)input_line_pointer; |
| 164 | expressionP->X_add_number = reg_number; |
| 165 | input_line_pointer = p; |
| 166 | return 1; |
| 167 | } |
| 168 | if (c) |
| 169 | *(p-1) = c; |
| 170 | return 0; |
| 171 | } |
| 172 | |
| 173 | |
| 174 | static int |
| 175 | check_range (num, bits, flags) |
| 176 | unsigned long num; |
| 177 | int bits; |
| 178 | int flags; |
| 179 | { |
| 180 | long min, max, bit1; |
| 181 | int retval=0; |
| 182 | |
| 183 | /* don't bother checking 16-bit values */ |
| 184 | if (bits == 16) |
| 185 | return 0; |
| 186 | |
| 187 | if (flags & OPERAND_SHIFT) |
| 188 | { |
| 189 | /* all special shift operands are unsigned */ |
| 190 | /* and <= 16. We allow 0 for now. */ |
| 191 | if (num>16) |
| 192 | return 1; |
| 193 | else |
| 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | if (flags & OPERAND_SIGNED) |
| 198 | { |
| 199 | /* Signed 3-bit integers are restricted to the (-2, 3) range */ |
| 200 | if (flags & RESTRICTED_NUM3) |
| 201 | { |
| 202 | if ((long) num < -2 || (long) num > 3) |
| 203 | retval = 1; |
| 204 | } |
| 205 | else |
| 206 | { |
| 207 | max = (1 << (bits - 1)) - 1; |
| 208 | min = - (1 << (bits - 1)); |
| 209 | if (((long) num > max) || ((long) num < min)) |
| 210 | retval = 1; |
| 211 | } |
| 212 | } |
| 213 | else |
| 214 | { |
| 215 | max = (1 << bits) - 1; |
| 216 | min = 0; |
| 217 | if ((num > max) || (num < min)) |
| 218 | retval = 1; |
| 219 | } |
| 220 | return retval; |
| 221 | } |
| 222 | |
| 223 | |
| 224 | void |
| 225 | md_show_usage (stream) |
| 226 | FILE *stream; |
| 227 | { |
| 228 | fprintf(stream, _("D10V options:\n\ |
| 229 | -O optimize. Will do some operations in parallel.\n")); |
| 230 | } |
| 231 | |
| 232 | int |
| 233 | md_parse_option (c, arg) |
| 234 | int c; |
| 235 | char *arg; |
| 236 | { |
| 237 | switch (c) |
| 238 | { |
| 239 | case 'O': |
| 240 | /* Optimize. Will attempt to parallelize operations */ |
| 241 | Optimizing = 1; |
| 242 | break; |
| 243 | case OPTION_NOWARNSWAP: |
| 244 | flag_warn_suppress_instructionswap = 1; |
| 245 | break; |
| 246 | default: |
| 247 | return 0; |
| 248 | } |
| 249 | return 1; |
| 250 | } |
| 251 | |
| 252 | symbolS * |
| 253 | md_undefined_symbol (name) |
| 254 | char *name; |
| 255 | { |
| 256 | return 0; |
| 257 | } |
| 258 | |
| 259 | /* Turn a string in input_line_pointer into a floating point constant of type |
| 260 | type, and store the appropriate bytes in *litP. The number of LITTLENUMS |
| 261 | emitted is stored in *sizeP . An error message is returned, or NULL on OK. |
| 262 | */ |
| 263 | char * |
| 264 | md_atof (type, litP, sizeP) |
| 265 | int type; |
| 266 | char *litP; |
| 267 | int *sizeP; |
| 268 | { |
| 269 | int prec; |
| 270 | LITTLENUM_TYPE words[4]; |
| 271 | char *t; |
| 272 | int i; |
| 273 | |
| 274 | switch (type) |
| 275 | { |
| 276 | case 'f': |
| 277 | prec = 2; |
| 278 | break; |
| 279 | case 'd': |
| 280 | prec = 4; |
| 281 | break; |
| 282 | default: |
| 283 | *sizeP = 0; |
| 284 | return _("bad call to md_atof"); |
| 285 | } |
| 286 | |
| 287 | t = atof_ieee (input_line_pointer, type, words); |
| 288 | if (t) |
| 289 | input_line_pointer = t; |
| 290 | |
| 291 | *sizeP = prec * 2; |
| 292 | |
| 293 | for (i = 0; i < prec; i++) |
| 294 | { |
| 295 | md_number_to_chars (litP, (valueT) words[i], 2); |
| 296 | litP += 2; |
| 297 | } |
| 298 | return NULL; |
| 299 | } |
| 300 | |
| 301 | void |
| 302 | md_convert_frag (abfd, sec, fragP) |
| 303 | bfd *abfd; |
| 304 | asection *sec; |
| 305 | fragS *fragP; |
| 306 | { |
| 307 | abort (); |
| 308 | } |
| 309 | |
| 310 | valueT |
| 311 | md_section_align (seg, addr) |
| 312 | asection *seg; |
| 313 | valueT addr; |
| 314 | { |
| 315 | int align = bfd_get_section_alignment (stdoutput, seg); |
| 316 | return ((addr + (1 << align) - 1) & (-1 << align)); |
| 317 | } |
| 318 | |
| 319 | |
| 320 | void |
| 321 | md_begin () |
| 322 | { |
| 323 | char *prev_name = ""; |
| 324 | struct d10v_opcode *opcode; |
| 325 | d10v_hash = hash_new(); |
| 326 | |
| 327 | /* Insert unique names into hash table. The D10v instruction set |
| 328 | has many identical opcode names that have different opcodes based |
| 329 | on the operands. This hash table then provides a quick index to |
| 330 | the first opcode with a particular name in the opcode table. */ |
| 331 | |
| 332 | for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++) |
| 333 | { |
| 334 | if (strcmp (prev_name, opcode->name)) |
| 335 | { |
| 336 | prev_name = (char *)opcode->name; |
| 337 | hash_insert (d10v_hash, opcode->name, (char *) opcode); |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | fixups = &FixUps[0]; |
| 342 | FixUps[0].next = &FixUps[1]; |
| 343 | FixUps[1].next = &FixUps[0]; |
| 344 | } |
| 345 | |
| 346 | |
| 347 | /* this function removes the postincrement or postdecrement |
| 348 | operator ( '+' or '-' ) from an expression */ |
| 349 | |
| 350 | static int postfix (p) |
| 351 | char *p; |
| 352 | { |
| 353 | while (*p != '-' && *p != '+') |
| 354 | { |
| 355 | if (*p==0 || *p=='\n' || *p=='\r') |
| 356 | break; |
| 357 | p++; |
| 358 | } |
| 359 | |
| 360 | if (*p == '-') |
| 361 | { |
| 362 | *p = ' '; |
| 363 | return (-1); |
| 364 | } |
| 365 | if (*p == '+') |
| 366 | { |
| 367 | *p = ' '; |
| 368 | return (1); |
| 369 | } |
| 370 | |
| 371 | return (0); |
| 372 | } |
| 373 | |
| 374 | |
| 375 | static bfd_reloc_code_real_type |
| 376 | get_reloc (op) |
| 377 | struct d10v_operand *op; |
| 378 | { |
| 379 | int bits = op->bits; |
| 380 | |
| 381 | if (bits <= 4) |
| 382 | return (0); |
| 383 | |
| 384 | if (op->flags & OPERAND_ADDR) |
| 385 | { |
| 386 | if (bits == 8) |
| 387 | return (BFD_RELOC_D10V_10_PCREL_R); |
| 388 | else |
| 389 | return (BFD_RELOC_D10V_18_PCREL); |
| 390 | } |
| 391 | |
| 392 | return (BFD_RELOC_16); |
| 393 | } |
| 394 | |
| 395 | |
| 396 | /* get_operands parses a string of operands and returns |
| 397 | an array of expressions */ |
| 398 | |
| 399 | static int |
| 400 | get_operands (exp) |
| 401 | expressionS exp[]; |
| 402 | { |
| 403 | char *p = input_line_pointer; |
| 404 | int numops = 0; |
| 405 | int post = 0; |
| 406 | int uses_at = 0; |
| 407 | |
| 408 | while (*p) |
| 409 | { |
| 410 | while (*p == ' ' || *p == '\t' || *p == ',') |
| 411 | p++; |
| 412 | if (*p==0 || *p=='\n' || *p=='\r') |
| 413 | break; |
| 414 | |
| 415 | if (*p == '@') |
| 416 | { |
| 417 | uses_at = 1; |
| 418 | |
| 419 | p++; |
| 420 | exp[numops].X_op = O_absent; |
| 421 | if (*p == '(') |
| 422 | { |
| 423 | p++; |
| 424 | exp[numops].X_add_number = OPERAND_ATPAR; |
| 425 | } |
| 426 | else if (*p == '-') |
| 427 | { |
| 428 | p++; |
| 429 | exp[numops].X_add_number = OPERAND_ATMINUS; |
| 430 | } |
| 431 | else |
| 432 | { |
| 433 | exp[numops].X_add_number = OPERAND_ATSIGN; |
| 434 | post = postfix (p); |
| 435 | } |
| 436 | numops++; |
| 437 | continue; |
| 438 | } |
| 439 | |
| 440 | if (*p == ')') |
| 441 | { |
| 442 | /* just skip the trailing paren */ |
| 443 | p++; |
| 444 | continue; |
| 445 | } |
| 446 | |
| 447 | input_line_pointer = p; |
| 448 | |
| 449 | /* check to see if it might be a register name */ |
| 450 | if (!register_name (&exp[numops])) |
| 451 | { |
| 452 | /* parse as an expression */ |
| 453 | if (uses_at) |
| 454 | { |
| 455 | /* Any expression that involves the indirect addressing |
| 456 | cannot also involve immediate addressing. Therefore |
| 457 | the use of the hash character is illegal. */ |
| 458 | int save = do_not_ignore_hash; |
| 459 | do_not_ignore_hash = 1; |
| 460 | |
| 461 | expression (&exp[numops]); |
| 462 | |
| 463 | do_not_ignore_hash = save; |
| 464 | } |
| 465 | else |
| 466 | expression (&exp[numops]); |
| 467 | } |
| 468 | |
| 469 | if (strncasecmp (input_line_pointer, "@word", 5) == 0) |
| 470 | { |
| 471 | input_line_pointer += 5; |
| 472 | if (exp[numops].X_op == O_register) |
| 473 | { |
| 474 | /* if it looked like a register name but was followed by |
| 475 | "@word" then it was really a symbol, so change it to |
| 476 | one */ |
| 477 | exp[numops].X_op = O_symbol; |
| 478 | exp[numops].X_add_symbol = symbol_find_or_make ((char *)exp[numops].X_op_symbol); |
| 479 | } |
| 480 | |
| 481 | /* check for identifier@word+constant */ |
| 482 | if (*input_line_pointer == '-' || *input_line_pointer == '+') |
| 483 | { |
| 484 | char *orig_line = input_line_pointer; |
| 485 | expressionS new_exp; |
| 486 | expression (&new_exp); |
| 487 | exp[numops].X_add_number = new_exp.X_add_number; |
| 488 | } |
| 489 | |
| 490 | /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */ |
| 491 | { |
| 492 | expressionS new_exp; |
| 493 | memset (&new_exp, 0, sizeof new_exp); |
| 494 | new_exp.X_add_number = AT_WORD_RIGHT_SHIFT; |
| 495 | new_exp.X_op = O_constant; |
| 496 | new_exp.X_unsigned = 1; |
| 497 | exp[numops].X_op_symbol = make_expr_symbol (&new_exp); |
| 498 | exp[numops].X_op = O_right_shift; |
| 499 | } |
| 500 | |
| 501 | know (AT_WORD_P (&exp[numops])); |
| 502 | } |
| 503 | |
| 504 | if (exp[numops].X_op == O_illegal) |
| 505 | as_bad (_("illegal operand")); |
| 506 | else if (exp[numops].X_op == O_absent) |
| 507 | as_bad (_("missing operand")); |
| 508 | |
| 509 | numops++; |
| 510 | p = input_line_pointer; |
| 511 | } |
| 512 | |
| 513 | switch (post) |
| 514 | { |
| 515 | case -1: /* postdecrement mode */ |
| 516 | exp[numops].X_op = O_absent; |
| 517 | exp[numops++].X_add_number = OPERAND_MINUS; |
| 518 | break; |
| 519 | case 1: /* postincrement mode */ |
| 520 | exp[numops].X_op = O_absent; |
| 521 | exp[numops++].X_add_number = OPERAND_PLUS; |
| 522 | break; |
| 523 | } |
| 524 | |
| 525 | exp[numops].X_op = 0; |
| 526 | return (numops); |
| 527 | } |
| 528 | |
| 529 | static unsigned long |
| 530 | d10v_insert_operand (insn, op_type, value, left, fix) |
| 531 | unsigned long insn; |
| 532 | int op_type; |
| 533 | offsetT value; |
| 534 | int left; |
| 535 | fixS *fix; |
| 536 | { |
| 537 | int shift, bits; |
| 538 | |
| 539 | shift = d10v_operands[op_type].shift; |
| 540 | if (left) |
| 541 | shift += 15; |
| 542 | |
| 543 | bits = d10v_operands[op_type].bits; |
| 544 | |
| 545 | /* truncate to the proper number of bits */ |
| 546 | if (check_range (value, bits, d10v_operands[op_type].flags)) |
| 547 | as_bad_where (fix->fx_file, fix->fx_line, _("operand out of range: %d"), value); |
| 548 | |
| 549 | value &= 0x7FFFFFFF >> (31 - bits); |
| 550 | insn |= (value << shift); |
| 551 | |
| 552 | return insn; |
| 553 | } |
| 554 | |
| 555 | |
| 556 | /* build_insn takes a pointer to the opcode entry in the opcode table |
| 557 | and the array of operand expressions and returns the instruction */ |
| 558 | |
| 559 | static unsigned long |
| 560 | build_insn (opcode, opers, insn) |
| 561 | struct d10v_opcode *opcode; |
| 562 | expressionS *opers; |
| 563 | unsigned long insn; |
| 564 | { |
| 565 | int i, bits, shift, flags, format; |
| 566 | unsigned long number; |
| 567 | |
| 568 | /* the insn argument is only used for the DIVS kludge */ |
| 569 | if (insn) |
| 570 | format = LONG_R; |
| 571 | else |
| 572 | { |
| 573 | insn = opcode->opcode; |
| 574 | format = opcode->format; |
| 575 | } |
| 576 | |
| 577 | for (i=0;opcode->operands[i];i++) |
| 578 | { |
| 579 | flags = d10v_operands[opcode->operands[i]].flags; |
| 580 | bits = d10v_operands[opcode->operands[i]].bits; |
| 581 | shift = d10v_operands[opcode->operands[i]].shift; |
| 582 | number = opers[i].X_add_number; |
| 583 | |
| 584 | if (flags & OPERAND_REG) |
| 585 | { |
| 586 | number &= REGISTER_MASK; |
| 587 | if (format == LONG_L) |
| 588 | shift += 15; |
| 589 | } |
| 590 | |
| 591 | if (opers[i].X_op != O_register && opers[i].X_op != O_constant) |
| 592 | { |
| 593 | /* now create a fixup */ |
| 594 | |
| 595 | if (fixups->fc >= MAX_INSN_FIXUPS) |
| 596 | as_fatal (_("too many fixups")); |
| 597 | |
| 598 | if (AT_WORD_P (&opers[i])) |
| 599 | { |
| 600 | /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */ |
| 601 | fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18; |
| 602 | opers[i].X_op = O_symbol; |
| 603 | opers[i].X_op_symbol = NULL; /* Should free it */ |
| 604 | /* number is left shifted by AT_WORD_RIGHT_SHIFT so |
| 605 | that, it is aligned with the symbol's value. Later, |
| 606 | BFD_RELOC_D10V_18 will right shift (symbol_value + |
| 607 | X_add_number). */ |
| 608 | number <<= AT_WORD_RIGHT_SHIFT; |
| 609 | opers[i].X_add_number = number; |
| 610 | } |
| 611 | else |
| 612 | fixups->fix[fixups->fc].reloc = |
| 613 | get_reloc((struct d10v_operand *)&d10v_operands[opcode->operands[i]]); |
| 614 | |
| 615 | if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 || |
| 616 | fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18) |
| 617 | fixups->fix[fixups->fc].size = 2; |
| 618 | else |
| 619 | fixups->fix[fixups->fc].size = 4; |
| 620 | |
| 621 | fixups->fix[fixups->fc].exp = opers[i]; |
| 622 | fixups->fix[fixups->fc].operand = opcode->operands[i]; |
| 623 | fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false; |
| 624 | (fixups->fc)++; |
| 625 | } |
| 626 | |
| 627 | /* truncate to the proper number of bits */ |
| 628 | if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) |
| 629 | as_bad (_("operand out of range: %d"),number); |
| 630 | number &= 0x7FFFFFFF >> (31 - bits); |
| 631 | insn = insn | (number << shift); |
| 632 | } |
| 633 | |
| 634 | /* kludge: for DIVS, we need to put the operands in twice */ |
| 635 | /* on the second pass, format is changed to LONG_R to force */ |
| 636 | /* the second set of operands to not be shifted over 15 */ |
| 637 | if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L)) |
| 638 | insn = build_insn (opcode, opers, insn); |
| 639 | |
| 640 | return insn; |
| 641 | } |
| 642 | |
| 643 | /* write out a long form instruction */ |
| 644 | static void |
| 645 | write_long (opcode, insn, fx) |
| 646 | struct d10v_opcode *opcode; |
| 647 | unsigned long insn; |
| 648 | Fixups *fx; |
| 649 | { |
| 650 | int i, where; |
| 651 | char *f = frag_more(4); |
| 652 | |
| 653 | insn |= FM11; |
| 654 | number_to_chars_bigendian (f, insn, 4); |
| 655 | |
| 656 | for (i=0; i < fx->fc; i++) |
| 657 | { |
| 658 | if (fx->fix[i].reloc) |
| 659 | { |
| 660 | where = f - frag_now->fr_literal; |
| 661 | if (fx->fix[i].size == 2) |
| 662 | where += 2; |
| 663 | |
| 664 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) |
| 665 | fx->fix[i].operand |= 4096; |
| 666 | |
| 667 | fix_new_exp (frag_now, |
| 668 | where, |
| 669 | fx->fix[i].size, |
| 670 | &(fx->fix[i].exp), |
| 671 | fx->fix[i].pcrel, |
| 672 | fx->fix[i].operand|2048); |
| 673 | } |
| 674 | } |
| 675 | fx->fc = 0; |
| 676 | } |
| 677 | |
| 678 | |
| 679 | /* write out a short form instruction by itself */ |
| 680 | static void |
| 681 | write_1_short (opcode, insn, fx) |
| 682 | struct d10v_opcode *opcode; |
| 683 | unsigned long insn; |
| 684 | Fixups *fx; |
| 685 | { |
| 686 | char *f = frag_more(4); |
| 687 | int i, where; |
| 688 | |
| 689 | if (opcode->exec_type & PARONLY) |
| 690 | as_fatal (_("Instruction must be executed in parallel with another instruction.")); |
| 691 | |
| 692 | /* the other container needs to be NOP */ |
| 693 | /* according to 4.3.1: for FM=00, sub-instructions performed only |
| 694 | by IU cannot be encoded in L-container. */ |
| 695 | if (opcode->unit == IU) |
| 696 | insn |= FM00 | (NOP << 15); /* right container */ |
| 697 | else |
| 698 | insn = FM00 | (insn << 15) | NOP; /* left container */ |
| 699 | |
| 700 | number_to_chars_bigendian (f, insn, 4); |
| 701 | for (i=0; i < fx->fc; i++) |
| 702 | { |
| 703 | if (fx->fix[i].reloc) |
| 704 | { |
| 705 | where = f - frag_now->fr_literal; |
| 706 | if (fx->fix[i].size == 2) |
| 707 | where += 2; |
| 708 | |
| 709 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) |
| 710 | fx->fix[i].operand |= 4096; |
| 711 | |
| 712 | /* if it's an R reloc, we may have to switch it to L */ |
| 713 | if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) ) |
| 714 | fx->fix[i].operand |= 1024; |
| 715 | |
| 716 | fix_new_exp (frag_now, |
| 717 | where, |
| 718 | fx->fix[i].size, |
| 719 | &(fx->fix[i].exp), |
| 720 | fx->fix[i].pcrel, |
| 721 | fx->fix[i].operand|2048); |
| 722 | } |
| 723 | } |
| 724 | fx->fc = 0; |
| 725 | } |
| 726 | |
| 727 | /* write out a short form instruction if possible */ |
| 728 | /* return number of instructions not written out */ |
| 729 | static int |
| 730 | write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) |
| 731 | struct d10v_opcode *opcode1, *opcode2; |
| 732 | unsigned long insn1, insn2; |
| 733 | int exec_type; |
| 734 | Fixups *fx; |
| 735 | { |
| 736 | unsigned long insn; |
| 737 | char *f; |
| 738 | int i,j, where; |
| 739 | |
| 740 | if ( (exec_type != 1) && ((opcode1->exec_type & PARONLY) |
| 741 | || (opcode2->exec_type & PARONLY))) |
| 742 | as_fatal (_("Instruction must be executed in parallel")); |
| 743 | |
| 744 | if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE)) |
| 745 | as_fatal (_("Long instructions may not be combined.")); |
| 746 | |
| 747 | if(opcode1->exec_type & BRANCH_LINK && exec_type == 0) |
| 748 | { |
| 749 | /* Instructions paired with a subroutine call are executed before the |
| 750 | subroutine, so don't do these pairings unless explicitly requested. */ |
| 751 | write_1_short (opcode1, insn1, fx->next); |
| 752 | return (1); |
| 753 | } |
| 754 | |
| 755 | switch (exec_type) |
| 756 | { |
| 757 | case 0: /* order not specified */ |
| 758 | if ( Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) |
| 759 | { |
| 760 | /* parallel */ |
| 761 | if (opcode1->unit == IU) |
| 762 | insn = FM00 | (insn2 << 15) | insn1; |
| 763 | else if (opcode2->unit == MU) |
| 764 | insn = FM00 | (insn2 << 15) | insn1; |
| 765 | else |
| 766 | { |
| 767 | insn = FM00 | (insn1 << 15) | insn2; |
| 768 | fx = fx->next; |
| 769 | } |
| 770 | } |
| 771 | else if (opcode1->unit == IU) |
| 772 | { |
| 773 | /* reverse sequential */ |
| 774 | insn = FM10 | (insn2 << 15) | insn1; |
| 775 | } |
| 776 | else |
| 777 | { |
| 778 | /* sequential */ |
| 779 | insn = FM01 | (insn1 << 15) | insn2; |
| 780 | fx = fx->next; |
| 781 | } |
| 782 | break; |
| 783 | case 1: /* parallel */ |
| 784 | if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) |
| 785 | as_fatal (_("One of these instructions may not be executed in parallel.")); |
| 786 | |
| 787 | if (opcode1->unit == IU) |
| 788 | { |
| 789 | if (opcode2->unit == IU) |
| 790 | as_fatal (_("Two IU instructions may not be executed in parallel")); |
| 791 | if (!flag_warn_suppress_instructionswap) |
| 792 | as_warn (_("Swapping instruction order")); |
| 793 | insn = FM00 | (insn2 << 15) | insn1; |
| 794 | } |
| 795 | else if (opcode2->unit == MU) |
| 796 | { |
| 797 | if (opcode1->unit == MU) |
| 798 | as_fatal (_("Two MU instructions may not be executed in parallel")); |
| 799 | if (!flag_warn_suppress_instructionswap) |
| 800 | as_warn (_("Swapping instruction order")); |
| 801 | insn = FM00 | (insn2 << 15) | insn1; |
| 802 | } |
| 803 | else |
| 804 | { |
| 805 | insn = FM00 | (insn1 << 15) | insn2; |
| 806 | fx = fx->next; |
| 807 | } |
| 808 | break; |
| 809 | case 2: /* sequential */ |
| 810 | if (opcode1->unit != IU) |
| 811 | insn = FM01 | (insn1 << 15) | insn2; |
| 812 | else if (opcode2->unit == MU || opcode2->unit == EITHER) |
| 813 | { |
| 814 | if (!flag_warn_suppress_instructionswap) |
| 815 | as_warn (_("Swapping instruction order")); |
| 816 | insn = FM10 | (insn2 << 15) | insn1; |
| 817 | } |
| 818 | else |
| 819 | as_fatal (_("IU instruction may not be in the left container")); |
| 820 | fx = fx->next; |
| 821 | break; |
| 822 | case 3: /* reverse sequential */ |
| 823 | if (opcode2->unit != MU) |
| 824 | insn = FM10 | (insn1 << 15) | insn2; |
| 825 | else if (opcode1->unit == IU || opcode1->unit == EITHER) |
| 826 | { |
| 827 | if (!flag_warn_suppress_instructionswap) |
| 828 | as_warn (_("Swapping instruction order")); |
| 829 | insn = FM01 | (insn2 << 15) | insn1; |
| 830 | } |
| 831 | else |
| 832 | as_fatal (_("MU instruction may not be in the right container")); |
| 833 | fx = fx->next; |
| 834 | break; |
| 835 | default: |
| 836 | as_fatal (_("unknown execution type passed to write_2_short()")); |
| 837 | } |
| 838 | |
| 839 | f = frag_more(4); |
| 840 | number_to_chars_bigendian (f, insn, 4); |
| 841 | |
| 842 | for (j=0; j<2; j++) |
| 843 | { |
| 844 | for (i=0; i < fx->fc; i++) |
| 845 | { |
| 846 | if (fx->fix[i].reloc) |
| 847 | { |
| 848 | where = f - frag_now->fr_literal; |
| 849 | if (fx->fix[i].size == 2) |
| 850 | where += 2; |
| 851 | |
| 852 | if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) ) |
| 853 | fx->fix[i].operand |= 1024; |
| 854 | |
| 855 | if (fx->fix[i].reloc == BFD_RELOC_D10V_18) |
| 856 | fx->fix[i].operand |= 4096; |
| 857 | |
| 858 | fix_new_exp (frag_now, |
| 859 | where, |
| 860 | fx->fix[i].size, |
| 861 | &(fx->fix[i].exp), |
| 862 | fx->fix[i].pcrel, |
| 863 | fx->fix[i].operand|2048); |
| 864 | } |
| 865 | } |
| 866 | fx->fc = 0; |
| 867 | fx = fx->next; |
| 868 | } |
| 869 | return (0); |
| 870 | } |
| 871 | |
| 872 | |
| 873 | /* Check 2 instructions and determine if they can be safely */ |
| 874 | /* executed in parallel. Returns 1 if they can be. */ |
| 875 | static int |
| 876 | parallel_ok (op1, insn1, op2, insn2, exec_type) |
| 877 | struct d10v_opcode *op1, *op2; |
| 878 | unsigned long insn1, insn2; |
| 879 | int exec_type; |
| 880 | { |
| 881 | int i, j, flags, mask, shift, regno; |
| 882 | unsigned long ins, mod[2], used[2]; |
| 883 | struct d10v_opcode *op; |
| 884 | |
| 885 | if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0 |
| 886 | || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0 |
| 887 | || (op1->unit == BOTH) || (op2->unit == BOTH) |
| 888 | || (op1->unit == IU && op2->unit == IU) |
| 889 | || (op1->unit == MU && op2->unit == MU)) |
| 890 | return 0; |
| 891 | |
| 892 | /* If the first instruction is a branch and this is auto parallazation, |
| 893 | don't combine with any second instruction. */ |
| 894 | if (exec_type == 0 && (op1->exec_type & BRANCH) != 0) |
| 895 | return 0; |
| 896 | |
| 897 | /* The idea here is to create two sets of bitmasks (mod and used) |
| 898 | which indicate which registers are modified or used by each |
| 899 | instruction. The operation can only be done in parallel if |
| 900 | instruction 1 and instruction 2 modify different registers, and |
| 901 | the first instruction does not modify registers that the second |
| 902 | is using (The second instruction can modify registers that the |
| 903 | first is using as they are only written back after the first |
| 904 | instruction has completed). Accesses to control registers, PSW, |
| 905 | and memory are treated as accesses to a single register. So if |
| 906 | both instructions write memory or if the first instruction writes |
| 907 | memory and the second reads, then they cannot be done in |
| 908 | parallel. Likewise, if the first instruction mucks with the psw |
| 909 | and the second reads the PSW (which includes C, F0, and F1), then |
| 910 | they cannot operate safely in parallel. */ |
| 911 | |
| 912 | /* the bitmasks (mod and used) look like this (bit 31 = MSB) */ |
| 913 | /* r0-r15 0-15 */ |
| 914 | /* a0-a1 16-17 */ |
| 915 | /* cr (not psw) 18 */ |
| 916 | /* psw 19 */ |
| 917 | /* mem 20 */ |
| 918 | |
| 919 | for (j=0;j<2;j++) |
| 920 | { |
| 921 | if (j == 0) |
| 922 | { |
| 923 | op = op1; |
| 924 | ins = insn1; |
| 925 | } |
| 926 | else |
| 927 | { |
| 928 | op = op2; |
| 929 | ins = insn2; |
| 930 | } |
| 931 | mod[j] = used[j] = 0; |
| 932 | if (op->exec_type & BRANCH_LINK) |
| 933 | mod[j] |= 1 << 13; |
| 934 | |
| 935 | for (i = 0; op->operands[i]; i++) |
| 936 | { |
| 937 | flags = d10v_operands[op->operands[i]].flags; |
| 938 | shift = d10v_operands[op->operands[i]].shift; |
| 939 | mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); |
| 940 | if (flags & OPERAND_REG) |
| 941 | { |
| 942 | regno = (ins >> shift) & mask; |
| 943 | if (flags & (OPERAND_ACC0|OPERAND_ACC1)) |
| 944 | regno += 16; |
| 945 | else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */ |
| 946 | { |
| 947 | if (regno == 0) |
| 948 | regno = 19; |
| 949 | else |
| 950 | regno = 18; |
| 951 | } |
| 952 | else if (flags & (OPERAND_FFLAG|OPERAND_CFLAG)) |
| 953 | regno = 19; |
| 954 | |
| 955 | if ( flags & OPERAND_DEST ) |
| 956 | { |
| 957 | mod[j] |= 1 << regno; |
| 958 | if (flags & OPERAND_EVEN) |
| 959 | mod[j] |= 1 << (regno + 1); |
| 960 | } |
| 961 | else |
| 962 | { |
| 963 | used[j] |= 1 << regno ; |
| 964 | if (flags & OPERAND_EVEN) |
| 965 | used[j] |= 1 << (regno + 1); |
| 966 | |
| 967 | /* Auto inc/dec also modifies the register. */ |
| 968 | if (op->operands[i+1] != 0 |
| 969 | && (d10v_operands[op->operands[i+1]].flags |
| 970 | & (OPERAND_PLUS | OPERAND_MINUS)) != 0) |
| 971 | mod[j] |= 1 << regno; |
| 972 | } |
| 973 | } |
| 974 | else if (flags & OPERAND_ATMINUS) |
| 975 | { |
| 976 | /* SP implicitly used/modified */ |
| 977 | mod[j] |= 1 << 15; |
| 978 | used[j] |= 1 << 15; |
| 979 | } |
| 980 | } |
| 981 | if (op->exec_type & RMEM) |
| 982 | used[j] |= 1 << 20; |
| 983 | else if (op->exec_type & WMEM) |
| 984 | mod[j] |= 1 << 20; |
| 985 | else if (op->exec_type & RF0) |
| 986 | used[j] |= 1 << 19; |
| 987 | else if (op->exec_type & WF0) |
| 988 | mod[j] |= 1 << 19; |
| 989 | else if (op->exec_type & WCAR) |
| 990 | mod[j] |= 1 << 19; |
| 991 | } |
| 992 | if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0) |
| 993 | return 1; |
| 994 | return 0; |
| 995 | } |
| 996 | |
| 997 | |
| 998 | /* This is the main entry point for the machine-dependent assembler. str points to a |
| 999 | machine-dependent instruction. This function is supposed to emit the frags/bytes |
| 1000 | it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing |
| 1001 | and leaves the difficult stuff to do_assemble(). |
| 1002 | */ |
| 1003 | |
| 1004 | static unsigned long prev_insn; |
| 1005 | static struct d10v_opcode *prev_opcode = 0; |
| 1006 | static subsegT prev_subseg; |
| 1007 | static segT prev_seg = 0;; |
| 1008 | static int etype = 0; /* saved extype. used for multiline instructions */ |
| 1009 | |
| 1010 | void |
| 1011 | md_assemble (str) |
| 1012 | char *str; |
| 1013 | { |
| 1014 | struct d10v_opcode * opcode; |
| 1015 | unsigned long insn; |
| 1016 | int extype = 0; /* execution type; parallel, etc */ |
| 1017 | char * str2; |
| 1018 | |
| 1019 | if (etype == 0) |
| 1020 | { |
| 1021 | /* look for the special multiple instruction separators */ |
| 1022 | str2 = strstr (str, "||"); |
| 1023 | if (str2) |
| 1024 | extype = 1; |
| 1025 | else |
| 1026 | { |
| 1027 | str2 = strstr (str, "->"); |
| 1028 | if (str2) |
| 1029 | extype = 2; |
| 1030 | else |
| 1031 | { |
| 1032 | str2 = strstr (str, "<-"); |
| 1033 | if (str2) |
| 1034 | extype = 3; |
| 1035 | } |
| 1036 | } |
| 1037 | /* str2 points to the separator, if one */ |
| 1038 | if (str2) |
| 1039 | { |
| 1040 | *str2 = 0; |
| 1041 | |
| 1042 | /* if two instructions are present and we already have one saved |
| 1043 | then first write it out */ |
| 1044 | d10v_cleanup (); |
| 1045 | |
| 1046 | /* assemble first instruction and save it */ |
| 1047 | prev_insn = do_assemble (str, &prev_opcode); |
| 1048 | if (prev_insn == -1) |
| 1049 | as_fatal (_("can't find opcode ")); |
| 1050 | fixups = fixups->next; |
| 1051 | str = str2 + 2; |
| 1052 | } |
| 1053 | } |
| 1054 | |
| 1055 | insn = do_assemble (str, &opcode); |
| 1056 | if (insn == -1) |
| 1057 | { |
| 1058 | if (extype) |
| 1059 | { |
| 1060 | etype = extype; |
| 1061 | return; |
| 1062 | } |
| 1063 | as_fatal (_("can't find opcode ")); |
| 1064 | } |
| 1065 | |
| 1066 | if (etype) |
| 1067 | { |
| 1068 | extype = etype; |
| 1069 | etype = 0; |
| 1070 | } |
| 1071 | |
| 1072 | /* if this is a long instruction, write it and any previous short instruction */ |
| 1073 | if (opcode->format & LONG_OPCODE) |
| 1074 | { |
| 1075 | if (extype) |
| 1076 | as_fatal (_("Unable to mix instructions as specified")); |
| 1077 | d10v_cleanup (); |
| 1078 | write_long (opcode, insn, fixups); |
| 1079 | prev_opcode = NULL; |
| 1080 | return; |
| 1081 | } |
| 1082 | |
| 1083 | if (prev_opcode && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) |
| 1084 | d10v_cleanup(); |
| 1085 | |
| 1086 | if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0)) |
| 1087 | { |
| 1088 | /* no instructions saved */ |
| 1089 | prev_opcode = NULL; |
| 1090 | } |
| 1091 | else |
| 1092 | { |
| 1093 | if (extype) |
| 1094 | as_fatal (_("Unable to mix instructions as specified")); |
| 1095 | /* save off last instruction so it may be packed on next pass */ |
| 1096 | prev_opcode = opcode; |
| 1097 | prev_insn = insn; |
| 1098 | prev_seg = now_seg; |
| 1099 | prev_subseg = now_subseg; |
| 1100 | fixups = fixups->next; |
| 1101 | } |
| 1102 | } |
| 1103 | |
| 1104 | |
| 1105 | /* do_assemble assembles a single instruction and returns an opcode */ |
| 1106 | /* it returns -1 (an invalid opcode) on error */ |
| 1107 | |
| 1108 | static unsigned long |
| 1109 | do_assemble (str, opcode) |
| 1110 | char *str; |
| 1111 | struct d10v_opcode **opcode; |
| 1112 | { |
| 1113 | unsigned char *op_start, *save; |
| 1114 | unsigned char *op_end; |
| 1115 | char name[20]; |
| 1116 | int nlen = 0; |
| 1117 | expressionS myops[6]; |
| 1118 | unsigned long insn; |
| 1119 | |
| 1120 | /* Drop leading whitespace. */ |
| 1121 | while (*str == ' ') |
| 1122 | str++; |
| 1123 | |
| 1124 | /* Find the opcode end. */ |
| 1125 | for (op_start = op_end = (unsigned char *) (str); |
| 1126 | *op_end |
| 1127 | && nlen < 20 |
| 1128 | && !is_end_of_line[*op_end] && *op_end != ' '; |
| 1129 | op_end++) |
| 1130 | { |
| 1131 | name[nlen] = tolower (op_start[nlen]); |
| 1132 | nlen++; |
| 1133 | } |
| 1134 | name[nlen] = 0; |
| 1135 | |
| 1136 | if (nlen == 0) |
| 1137 | return -1; |
| 1138 | |
| 1139 | /* Find the first opcode with the proper name. */ |
| 1140 | *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name); |
| 1141 | if (*opcode == NULL) |
| 1142 | as_fatal (_("unknown opcode: %s"),name); |
| 1143 | |
| 1144 | save = input_line_pointer; |
| 1145 | input_line_pointer = op_end; |
| 1146 | *opcode = find_opcode (*opcode, myops); |
| 1147 | if (*opcode == 0) |
| 1148 | return -1; |
| 1149 | input_line_pointer = save; |
| 1150 | |
| 1151 | insn = build_insn ((*opcode), myops, 0); |
| 1152 | return (insn); |
| 1153 | } |
| 1154 | |
| 1155 | /* Find the symbol which has the same name as the register in the given expression. */ |
| 1156 | static symbolS * |
| 1157 | find_symbol_matching_register (exp) |
| 1158 | expressionS * exp; |
| 1159 | { |
| 1160 | int i; |
| 1161 | |
| 1162 | if (exp->X_op != O_register) |
| 1163 | return NULL; |
| 1164 | |
| 1165 | /* Find the name of the register. */ |
| 1166 | for (i = d10v_reg_name_cnt (); i--;) |
| 1167 | if (d10v_predefined_registers [i].value == exp->X_add_number) |
| 1168 | break; |
| 1169 | |
| 1170 | if (i < 0) |
| 1171 | abort (); |
| 1172 | |
| 1173 | /* Now see if a symbol has been defined with the same name. */ |
| 1174 | return symbol_find (d10v_predefined_registers [i].name); |
| 1175 | } |
| 1176 | |
| 1177 | |
| 1178 | /* find_opcode() gets a pointer to an entry in the opcode table. */ |
| 1179 | /* It must look at all opcodes with the same name and use the operands */ |
| 1180 | /* to choose the correct opcode. */ |
| 1181 | |
| 1182 | static struct d10v_opcode * |
| 1183 | find_opcode (opcode, myops) |
| 1184 | struct d10v_opcode *opcode; |
| 1185 | expressionS myops[]; |
| 1186 | { |
| 1187 | int i, match, done; |
| 1188 | struct d10v_opcode *next_opcode; |
| 1189 | |
| 1190 | /* get all the operands and save them as expressions */ |
| 1191 | get_operands (myops); |
| 1192 | |
| 1193 | /* now see if the operand is a fake. If so, find the correct size */ |
| 1194 | /* instruction, if possible */ |
| 1195 | if (opcode->format == OPCODE_FAKE) |
| 1196 | { |
| 1197 | int opnum = opcode->operands[0]; |
| 1198 | int flags; |
| 1199 | |
| 1200 | if (myops[opnum].X_op == O_register) |
| 1201 | { |
| 1202 | myops[opnum].X_op = O_symbol; |
| 1203 | myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol); |
| 1204 | myops[opnum].X_add_number = 0; |
| 1205 | myops[opnum].X_op_symbol = NULL; |
| 1206 | } |
| 1207 | |
| 1208 | next_opcode=opcode+1; |
| 1209 | |
| 1210 | /* If the first operand is supposed to be a register, make sure |
| 1211 | we got a valid one. */ |
| 1212 | flags = d10v_operands[next_opcode->operands[0]].flags; |
| 1213 | if (flags & OPERAND_REG) |
| 1214 | { |
| 1215 | int X_op = myops[0].X_op; |
| 1216 | int num = myops[0].X_add_number; |
| 1217 | |
| 1218 | if (X_op != O_register |
| 1219 | || (num & ~flags |
| 1220 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 |
| 1221 | | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL))) |
| 1222 | { |
| 1223 | as_bad (_("bad opcode or operands")); |
| 1224 | return 0; |
| 1225 | } |
| 1226 | } |
| 1227 | |
| 1228 | if (myops[opnum].X_op == O_constant || (myops[opnum].X_op == O_symbol && |
| 1229 | S_IS_DEFINED(myops[opnum].X_add_symbol) && |
| 1230 | (S_GET_SEGMENT(myops[opnum].X_add_symbol) == now_seg))) |
| 1231 | { |
| 1232 | for (i=0; opcode->operands[i+1]; i++) |
| 1233 | { |
| 1234 | int bits = d10v_operands[next_opcode->operands[opnum]].bits; |
| 1235 | int flags = d10v_operands[next_opcode->operands[opnum]].flags; |
| 1236 | if (flags & OPERAND_ADDR) |
| 1237 | bits += 2; |
| 1238 | if (myops[opnum].X_op == O_constant) |
| 1239 | { |
| 1240 | if (!check_range (myops[opnum].X_add_number, bits, flags)) |
| 1241 | return next_opcode; |
| 1242 | } |
| 1243 | else |
| 1244 | { |
| 1245 | fragS *f; |
| 1246 | long value; |
| 1247 | /* calculate the current address by running through the previous frags */ |
| 1248 | /* and adding our current offset */ |
| 1249 | for (value = 0, f = frchain_now->frch_root; f; f = f->fr_next) |
| 1250 | value += f->fr_fix + f->fr_offset; |
| 1251 | |
| 1252 | if (flags & OPERAND_ADDR) |
| 1253 | value = S_GET_VALUE(myops[opnum].X_add_symbol) - value - |
| 1254 | (obstack_next_free(&frchain_now->frch_obstack) - frag_now->fr_literal); |
| 1255 | else |
| 1256 | value = S_GET_VALUE(myops[opnum].X_add_symbol); |
| 1257 | |
| 1258 | if (AT_WORD_P (&myops[opnum])) |
| 1259 | { |
| 1260 | if (bits > 4) |
| 1261 | { |
| 1262 | bits += 2; |
| 1263 | if (!check_range (value, bits, flags)) |
| 1264 | return next_opcode; |
| 1265 | } |
| 1266 | } |
| 1267 | else if (!check_range (value, bits, flags)) |
| 1268 | return next_opcode; |
| 1269 | } |
| 1270 | next_opcode++; |
| 1271 | } |
| 1272 | as_fatal (_("value out of range")); |
| 1273 | } |
| 1274 | else |
| 1275 | { |
| 1276 | /* not a constant, so use a long instruction */ |
| 1277 | return opcode+2; |
| 1278 | } |
| 1279 | } |
| 1280 | else |
| 1281 | { |
| 1282 | match = 0; |
| 1283 | /* now search the opcode table table for one with operands */ |
| 1284 | /* that matches what we've got */ |
| 1285 | while (!match) |
| 1286 | { |
| 1287 | match = 1; |
| 1288 | for (i = 0; opcode->operands[i]; i++) |
| 1289 | { |
| 1290 | int flags = d10v_operands[opcode->operands[i]].flags; |
| 1291 | int X_op = myops[i].X_op; |
| 1292 | int num = myops[i].X_add_number; |
| 1293 | |
| 1294 | if (X_op == 0) |
| 1295 | { |
| 1296 | match = 0; |
| 1297 | break; |
| 1298 | } |
| 1299 | |
| 1300 | if (flags & OPERAND_REG) |
| 1301 | { |
| 1302 | if ((X_op != O_register) |
| 1303 | || (num & ~flags |
| 1304 | & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 |
| 1305 | | OPERAND_FFLAG | OPERAND_CFLAG |
| 1306 | | OPERAND_CONTROL))) |
| 1307 | { |
| 1308 | match = 0; |
| 1309 | break; |
| 1310 | } |
| 1311 | } |
| 1312 | |
| 1313 | if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || |
| 1314 | ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || |
| 1315 | ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) || |
| 1316 | ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || |
| 1317 | ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN)))) |
| 1318 | { |
| 1319 | match = 0; |
| 1320 | break; |
| 1321 | } |
| 1322 | |
| 1323 | /* Unfortunatly, for the indirect operand in instructions such as |
| 1324 | ``ldb r1, @(c,r14)'' this function can be passed X_op == O_register |
| 1325 | (because 'c' is a valid register name). However we cannot just |
| 1326 | ignore the case when X_op == O_register but flags & OPERAND_REG is |
| 1327 | null, so we check to see if a symbol of the same name as the register |
| 1328 | exists. If the symbol does exist, then the parser was unable to |
| 1329 | distinguish the two cases and we fix things here. (Ref: PR14826) */ |
| 1330 | |
| 1331 | if (!(flags & OPERAND_REG) && (X_op == O_register)) |
| 1332 | { |
| 1333 | symbolS * sym; |
| 1334 | |
| 1335 | sym = find_symbol_matching_register (& myops[i]); |
| 1336 | |
| 1337 | if (sym != NULL) |
| 1338 | { |
| 1339 | myops [i].X_op == X_op == O_symbol; |
| 1340 | myops [i].X_add_symbol = sym; |
| 1341 | } |
| 1342 | else |
| 1343 | as_bad |
| 1344 | (_("illegal operand - register name found where none expected")); |
| 1345 | } |
| 1346 | } |
| 1347 | |
| 1348 | /* We're only done if the operands matched so far AND there |
| 1349 | are no more to check. */ |
| 1350 | if (match && myops[i].X_op == 0) |
| 1351 | break; |
| 1352 | else |
| 1353 | match = 0; |
| 1354 | |
| 1355 | next_opcode = opcode + 1; |
| 1356 | |
| 1357 | if (next_opcode->opcode == 0) |
| 1358 | break; |
| 1359 | |
| 1360 | if (strcmp (next_opcode->name, opcode->name)) |
| 1361 | break; |
| 1362 | |
| 1363 | opcode = next_opcode; |
| 1364 | } |
| 1365 | } |
| 1366 | |
| 1367 | if (!match) |
| 1368 | { |
| 1369 | as_bad (_("bad opcode or operands")); |
| 1370 | return (0); |
| 1371 | } |
| 1372 | |
| 1373 | /* Check that all registers that are required to be even are. */ |
| 1374 | /* Also, if any operands were marked as registers, but were really symbols */ |
| 1375 | /* fix that here. */ |
| 1376 | for (i=0; opcode->operands[i]; i++) |
| 1377 | { |
| 1378 | if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) && |
| 1379 | (myops[i].X_add_number & 1)) |
| 1380 | as_fatal (_("Register number must be EVEN")); |
| 1381 | if (myops[i].X_op == O_register) |
| 1382 | { |
| 1383 | if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG)) |
| 1384 | { |
| 1385 | myops[i].X_op = O_symbol; |
| 1386 | myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol); |
| 1387 | myops[i].X_add_number = 0; |
| 1388 | myops[i].X_op_symbol = NULL; |
| 1389 | } |
| 1390 | } |
| 1391 | } |
| 1392 | return opcode; |
| 1393 | } |
| 1394 | |
| 1395 | /* if while processing a fixup, a reloc really needs to be created */ |
| 1396 | /* then it is done here */ |
| 1397 | |
| 1398 | arelent * |
| 1399 | tc_gen_reloc (seg, fixp) |
| 1400 | asection *seg; |
| 1401 | fixS *fixp; |
| 1402 | { |
| 1403 | arelent *reloc; |
| 1404 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
| 1405 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 1406 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 1407 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 1408 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
| 1409 | if (reloc->howto == (reloc_howto_type *) NULL) |
| 1410 | { |
| 1411 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 1412 | _("reloc %d not supported by object file format"), (int)fixp->fx_r_type); |
| 1413 | return NULL; |
| 1414 | } |
| 1415 | |
| 1416 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 1417 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 1418 | reloc->address = fixp->fx_offset; |
| 1419 | |
| 1420 | reloc->addend = fixp->fx_addnumber; |
| 1421 | |
| 1422 | return reloc; |
| 1423 | } |
| 1424 | |
| 1425 | int |
| 1426 | md_estimate_size_before_relax (fragp, seg) |
| 1427 | fragS *fragp; |
| 1428 | asection *seg; |
| 1429 | { |
| 1430 | abort (); |
| 1431 | return 0; |
| 1432 | } |
| 1433 | |
| 1434 | long |
| 1435 | md_pcrel_from_section (fixp, sec) |
| 1436 | fixS *fixp; |
| 1437 | segT sec; |
| 1438 | { |
| 1439 | if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) || |
| 1440 | (S_GET_SEGMENT (fixp->fx_addsy) != sec))) |
| 1441 | return 0; |
| 1442 | return fixp->fx_frag->fr_address + fixp->fx_where; |
| 1443 | } |
| 1444 | |
| 1445 | int |
| 1446 | md_apply_fix3 (fixp, valuep, seg) |
| 1447 | fixS *fixp; |
| 1448 | valueT *valuep; |
| 1449 | segT seg; |
| 1450 | { |
| 1451 | char *where; |
| 1452 | unsigned long insn; |
| 1453 | long value; |
| 1454 | int op_type; |
| 1455 | int left=0; |
| 1456 | |
| 1457 | if (fixp->fx_addsy == (symbolS *) NULL) |
| 1458 | { |
| 1459 | value = *valuep; |
| 1460 | fixp->fx_done = 1; |
| 1461 | } |
| 1462 | else if (fixp->fx_pcrel) |
| 1463 | value = *valuep; |
| 1464 | else |
| 1465 | { |
| 1466 | value = fixp->fx_offset; |
| 1467 | if (fixp->fx_subsy != (symbolS *) NULL) |
| 1468 | { |
| 1469 | if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) |
| 1470 | value -= S_GET_VALUE (fixp->fx_subsy); |
| 1471 | else |
| 1472 | { |
| 1473 | /* We don't actually support subtracting a symbol. */ |
| 1474 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 1475 | _("expression too complex")); |
| 1476 | } |
| 1477 | } |
| 1478 | } |
| 1479 | |
| 1480 | op_type = fixp->fx_r_type; |
| 1481 | if (op_type & 2048) |
| 1482 | { |
| 1483 | op_type -= 2048; |
| 1484 | if (op_type & 1024) |
| 1485 | { |
| 1486 | op_type -= 1024; |
| 1487 | fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L; |
| 1488 | left = 1; |
| 1489 | } |
| 1490 | else if (op_type & 4096) |
| 1491 | { |
| 1492 | op_type -= 4096; |
| 1493 | fixp->fx_r_type = BFD_RELOC_D10V_18; |
| 1494 | } |
| 1495 | else |
| 1496 | fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]); |
| 1497 | } |
| 1498 | |
| 1499 | /* Fetch the instruction, insert the fully resolved operand |
| 1500 | value, and stuff the instruction back again. */ |
| 1501 | where = fixp->fx_frag->fr_literal + fixp->fx_where; |
| 1502 | insn = bfd_getb32 ((unsigned char *) where); |
| 1503 | |
| 1504 | switch (fixp->fx_r_type) |
| 1505 | { |
| 1506 | case BFD_RELOC_D10V_10_PCREL_L: |
| 1507 | case BFD_RELOC_D10V_10_PCREL_R: |
| 1508 | case BFD_RELOC_D10V_18_PCREL: |
| 1509 | case BFD_RELOC_D10V_18: |
| 1510 | /* instruction addresses are always right-shifted by 2 */ |
| 1511 | value >>= AT_WORD_RIGHT_SHIFT; |
| 1512 | if (fixp->fx_size == 2) |
| 1513 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); |
| 1514 | else |
| 1515 | { |
| 1516 | struct d10v_opcode *rep, *repi; |
| 1517 | |
| 1518 | rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep"); |
| 1519 | repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi"); |
| 1520 | if ((insn & FM11) == FM11 |
| 1521 | && (repi != NULL && (insn & repi->mask) == repi->opcode |
| 1522 | || rep != NULL && (insn & rep->mask) == rep->opcode) |
| 1523 | && value < 4) |
| 1524 | as_fatal |
| 1525 | (_("line %d: rep or repi must include at least 4 instructions"), |
| 1526 | fixp->fx_line); |
| 1527 | insn = d10v_insert_operand (insn, op_type, (offsetT)value, left, fixp); |
| 1528 | bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); |
| 1529 | } |
| 1530 | break; |
| 1531 | case BFD_RELOC_32: |
| 1532 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); |
| 1533 | break; |
| 1534 | case BFD_RELOC_16: |
| 1535 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); |
| 1536 | break; |
| 1537 | |
| 1538 | case BFD_RELOC_VTABLE_INHERIT: |
| 1539 | case BFD_RELOC_VTABLE_ENTRY: |
| 1540 | fixp->fx_done = 0; |
| 1541 | return 1; |
| 1542 | |
| 1543 | default: |
| 1544 | as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp->fx_line,fixp->fx_r_type); |
| 1545 | } |
| 1546 | return 0; |
| 1547 | } |
| 1548 | |
| 1549 | /* d10v_cleanup() is called after the assembler has finished parsing the input |
| 1550 | file or after a label is defined. Because the D10V assembler sometimes saves short |
| 1551 | instructions to see if it can package them with the next instruction, there may |
| 1552 | be a short instruction that still needs written. */ |
| 1553 | int |
| 1554 | d10v_cleanup () |
| 1555 | { |
| 1556 | segT seg; |
| 1557 | subsegT subseg; |
| 1558 | |
| 1559 | if (prev_opcode && etype == 0) |
| 1560 | { |
| 1561 | seg = now_seg; |
| 1562 | subseg = now_subseg; |
| 1563 | if (prev_seg) |
| 1564 | subseg_set (prev_seg, prev_subseg); |
| 1565 | write_1_short (prev_opcode, prev_insn, fixups->next); |
| 1566 | subseg_set (seg, subseg); |
| 1567 | prev_opcode = NULL; |
| 1568 | } |
| 1569 | return 1; |
| 1570 | } |
| 1571 | |
| 1572 | /* Like normal .word, except support @word */ |
| 1573 | /* clobbers input_line_pointer, checks end-of-line. */ |
| 1574 | static void |
| 1575 | d10v_dot_word (nbytes) |
| 1576 | register int nbytes; /* 1=.byte, 2=.word, 4=.long */ |
| 1577 | { |
| 1578 | expressionS exp; |
| 1579 | bfd_reloc_code_real_type reloc; |
| 1580 | char *p; |
| 1581 | int offset; |
| 1582 | |
| 1583 | if (is_it_end_of_statement ()) |
| 1584 | { |
| 1585 | demand_empty_rest_of_line (); |
| 1586 | return; |
| 1587 | } |
| 1588 | |
| 1589 | do |
| 1590 | { |
| 1591 | expression (&exp); |
| 1592 | if (!strncasecmp (input_line_pointer, "@word", 5)) |
| 1593 | { |
| 1594 | exp.X_add_number = 0; |
| 1595 | input_line_pointer += 5; |
| 1596 | |
| 1597 | p = frag_more (2); |
| 1598 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, |
| 1599 | &exp, 0, BFD_RELOC_D10V_18); |
| 1600 | } |
| 1601 | else |
| 1602 | emit_expr (&exp, 2); |
| 1603 | } |
| 1604 | while (*input_line_pointer++ == ','); |
| 1605 | |
| 1606 | input_line_pointer--; /* Put terminator back into stream. */ |
| 1607 | demand_empty_rest_of_line (); |
| 1608 | } |
| 1609 | |
| 1610 | |
| 1611 | /* Mitsubishi asked that we support some old syntax that apparently */ |
| 1612 | /* had immediate operands starting with '#'. This is in some of their */ |
| 1613 | /* sample code but is not documented (although it appears in some */ |
| 1614 | /* examples in their assembler manual). For now, we'll solve this */ |
| 1615 | /* compatibility problem by simply ignoring any '#' at the beginning */ |
| 1616 | /* of an operand. */ |
| 1617 | |
| 1618 | /* operands that begin with '#' should fall through to here */ |
| 1619 | /* from expr.c */ |
| 1620 | |
| 1621 | void |
| 1622 | md_operand (expressionP) |
| 1623 | expressionS *expressionP; |
| 1624 | { |
| 1625 | if (*input_line_pointer == '#' && ! do_not_ignore_hash) |
| 1626 | { |
| 1627 | input_line_pointer++; |
| 1628 | expression (expressionP); |
| 1629 | } |
| 1630 | } |
| 1631 | |
| 1632 | boolean |
| 1633 | d10v_fix_adjustable (fixP) |
| 1634 | fixS *fixP; |
| 1635 | { |
| 1636 | |
| 1637 | if (fixP->fx_addsy == NULL) |
| 1638 | return 1; |
| 1639 | |
| 1640 | /* Prevent all adjustments to global symbols. */ |
| 1641 | if (S_IS_EXTERN (fixP->fx_addsy)) |
| 1642 | return 0; |
| 1643 | if (S_IS_WEAK (fixP->fx_addsy)) |
| 1644 | return 0; |
| 1645 | |
| 1646 | /* We need the symbol name for the VTABLE entries */ |
| 1647 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 1648 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 1649 | return 0; |
| 1650 | |
| 1651 | return 1; |
| 1652 | } |
| 1653 | |
| 1654 | int |
| 1655 | d10v_force_relocation (fixp) |
| 1656 | struct fix *fixp; |
| 1657 | { |
| 1658 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 1659 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 1660 | return 1; |
| 1661 | |
| 1662 | return 0; |
| 1663 | } |