| 1 | /* tc-h8300.c -- Assemble code for the Renesas H8/300 |
| 2 | Copyright (C) 1991-2016 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GAS, the GNU Assembler. |
| 5 | |
| 6 | GAS is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 3, or (at your option) |
| 9 | any later version. |
| 10 | |
| 11 | GAS is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with GAS; see the file COPYING. If not, write to the Free |
| 18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 19 | 02110-1301, USA. */ |
| 20 | |
| 21 | /* Written By Steve Chamberlain <sac@cygnus.com>. */ |
| 22 | |
| 23 | #include "as.h" |
| 24 | #include "subsegs.h" |
| 25 | #include "dwarf2dbg.h" |
| 26 | |
| 27 | #define DEFINE_TABLE |
| 28 | #define h8_opcodes ops |
| 29 | #include "opcode/h8300.h" |
| 30 | #include "safe-ctype.h" |
| 31 | |
| 32 | #ifdef OBJ_ELF |
| 33 | #include "elf/h8.h" |
| 34 | #endif |
| 35 | |
| 36 | const char comment_chars[] = ";"; |
| 37 | const char line_comment_chars[] = "#"; |
| 38 | #ifdef TE_LINUX |
| 39 | const char line_separator_chars[] = "!"; |
| 40 | #else |
| 41 | const char line_separator_chars[] = ""; |
| 42 | #endif |
| 43 | |
| 44 | static void sbranch (int); |
| 45 | static void h8300hmode (int); |
| 46 | static void h8300smode (int); |
| 47 | static void h8300hnmode (int); |
| 48 | static void h8300snmode (int); |
| 49 | static void h8300sxmode (int); |
| 50 | static void h8300sxnmode (int); |
| 51 | static void pint (int); |
| 52 | |
| 53 | int Hmode; |
| 54 | int Smode; |
| 55 | int Nmode; |
| 56 | int SXmode; |
| 57 | |
| 58 | static int default_mach = bfd_mach_h8300; |
| 59 | |
| 60 | #define PSIZE (Hmode && !Nmode ? L_32 : L_16) |
| 61 | |
| 62 | static int bsize = L_8; /* Default branch displacement. */ |
| 63 | |
| 64 | struct h8_instruction |
| 65 | { |
| 66 | int length; |
| 67 | int noperands; |
| 68 | int idx; |
| 69 | int size; |
| 70 | const struct h8_opcode *opcode; |
| 71 | }; |
| 72 | |
| 73 | static struct h8_instruction *h8_instructions; |
| 74 | |
| 75 | static void |
| 76 | h8300hmode (int arg ATTRIBUTE_UNUSED) |
| 77 | { |
| 78 | Hmode = 1; |
| 79 | Smode = 0; |
| 80 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h)) |
| 81 | as_warn (_("could not set architecture and machine")); |
| 82 | } |
| 83 | |
| 84 | static void |
| 85 | h8300smode (int arg ATTRIBUTE_UNUSED) |
| 86 | { |
| 87 | Smode = 1; |
| 88 | Hmode = 1; |
| 89 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s)) |
| 90 | as_warn (_("could not set architecture and machine")); |
| 91 | } |
| 92 | |
| 93 | static void |
| 94 | h8300hnmode (int arg ATTRIBUTE_UNUSED) |
| 95 | { |
| 96 | Hmode = 1; |
| 97 | Smode = 0; |
| 98 | Nmode = 1; |
| 99 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn)) |
| 100 | as_warn (_("could not set architecture and machine")); |
| 101 | } |
| 102 | |
| 103 | static void |
| 104 | h8300snmode (int arg ATTRIBUTE_UNUSED) |
| 105 | { |
| 106 | Smode = 1; |
| 107 | Hmode = 1; |
| 108 | Nmode = 1; |
| 109 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn)) |
| 110 | as_warn (_("could not set architecture and machine")); |
| 111 | } |
| 112 | |
| 113 | static void |
| 114 | h8300sxmode (int arg ATTRIBUTE_UNUSED) |
| 115 | { |
| 116 | Smode = 1; |
| 117 | Hmode = 1; |
| 118 | SXmode = 1; |
| 119 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx)) |
| 120 | as_warn (_("could not set architecture and machine")); |
| 121 | } |
| 122 | |
| 123 | static void |
| 124 | h8300sxnmode (int arg ATTRIBUTE_UNUSED) |
| 125 | { |
| 126 | Smode = 1; |
| 127 | Hmode = 1; |
| 128 | SXmode = 1; |
| 129 | Nmode = 1; |
| 130 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn)) |
| 131 | as_warn (_("could not set architecture and machine")); |
| 132 | } |
| 133 | |
| 134 | static void |
| 135 | sbranch (int size) |
| 136 | { |
| 137 | bsize = size; |
| 138 | } |
| 139 | |
| 140 | static void |
| 141 | pint (int arg ATTRIBUTE_UNUSED) |
| 142 | { |
| 143 | cons (Hmode ? 4 : 2); |
| 144 | } |
| 145 | |
| 146 | /* Like obj_elf_section, but issues a warning for new |
| 147 | sections which do not have an attribute specification. */ |
| 148 | |
| 149 | static void |
| 150 | h8300_elf_section (int push) |
| 151 | { |
| 152 | static const char * known_data_sections [] = { ".rodata", ".tdata", ".tbss" }; |
| 153 | static const char * known_data_prefixes [] = { ".debug", ".zdebug", ".gnu.warning" }; |
| 154 | char * saved_ilp = input_line_pointer; |
| 155 | const char * name; |
| 156 | |
| 157 | name = obj_elf_section_name (); |
| 158 | if (name == NULL) |
| 159 | return; |
| 160 | |
| 161 | if (* input_line_pointer != ',' |
| 162 | && bfd_get_section_by_name (stdoutput, name) == NULL) |
| 163 | { |
| 164 | signed int i; |
| 165 | |
| 166 | /* Ignore this warning for well known data sections. */ |
| 167 | for (i = ARRAY_SIZE (known_data_sections); i--;) |
| 168 | if (strcmp (name, known_data_sections[i]) == 0) |
| 169 | break; |
| 170 | |
| 171 | if (i < 0) |
| 172 | for (i = ARRAY_SIZE (known_data_prefixes); i--;) |
| 173 | if (strncmp (name, known_data_prefixes[i], |
| 174 | strlen (known_data_prefixes[i])) == 0) |
| 175 | break; |
| 176 | |
| 177 | if (i < 0) |
| 178 | as_warn (_("new section '%s' defined without attributes - this might cause problems"), name); |
| 179 | } |
| 180 | |
| 181 | /* FIXME: We ought to free the memory allocated by obj_elf_section_name() |
| 182 | for 'name', but we do not know if it was taken from the obstack, via |
| 183 | demand_copy_C_string(), or xmalloc()ed. */ |
| 184 | input_line_pointer = saved_ilp; |
| 185 | obj_elf_section (push); |
| 186 | } |
| 187 | |
| 188 | /* This table describes all the machine specific pseudo-ops the assembler |
| 189 | has to support. The fields are: |
| 190 | pseudo-op name without dot |
| 191 | function to call to execute this pseudo-op |
| 192 | Integer arg to pass to the function. */ |
| 193 | |
| 194 | const pseudo_typeS md_pseudo_table[] = |
| 195 | { |
| 196 | {"h8300h", h8300hmode, 0}, |
| 197 | {"h8300hn", h8300hnmode, 0}, |
| 198 | {"h8300s", h8300smode, 0}, |
| 199 | {"h8300sn", h8300snmode, 0}, |
| 200 | {"h8300sx", h8300sxmode, 0}, |
| 201 | {"h8300sxn", h8300sxnmode, 0}, |
| 202 | {"sbranch", sbranch, L_8}, |
| 203 | {"lbranch", sbranch, L_16}, |
| 204 | |
| 205 | {"int", pint, 0}, |
| 206 | {"data.b", cons, 1}, |
| 207 | {"data.w", cons, 2}, |
| 208 | {"data.l", cons, 4}, |
| 209 | {"form", listing_psize, 0}, |
| 210 | {"heading", listing_title, 0}, |
| 211 | {"import", s_ignore, 0}, |
| 212 | {"page", listing_eject, 0}, |
| 213 | {"program", s_ignore, 0}, |
| 214 | |
| 215 | #ifdef OBJ_ELF |
| 216 | {"section", h8300_elf_section, 0}, |
| 217 | {"section.s", h8300_elf_section, 0}, |
| 218 | {"sect", h8300_elf_section, 0}, |
| 219 | {"sect.s", h8300_elf_section, 0}, |
| 220 | #endif |
| 221 | |
| 222 | {0, 0, 0} |
| 223 | }; |
| 224 | |
| 225 | const char EXP_CHARS[] = "eE"; |
| 226 | |
| 227 | /* Chars that mean this number is a floating point constant |
| 228 | As in 0f12.456 |
| 229 | or 0d1.2345e12. */ |
| 230 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
| 231 | |
| 232 | static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */ |
| 233 | |
| 234 | /* This function is called once, at assembler startup time. This |
| 235 | should set up all the tables, etc. that the MD part of the assembler |
| 236 | needs. */ |
| 237 | |
| 238 | void |
| 239 | md_begin (void) |
| 240 | { |
| 241 | unsigned int nopcodes; |
| 242 | struct h8_opcode *p, *p1; |
| 243 | struct h8_instruction *pi; |
| 244 | char prev_buffer[100]; |
| 245 | int idx = 0; |
| 246 | |
| 247 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, default_mach)) |
| 248 | as_warn (_("could not set architecture and machine")); |
| 249 | |
| 250 | opcode_hash_control = hash_new (); |
| 251 | prev_buffer[0] = 0; |
| 252 | |
| 253 | nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); |
| 254 | |
| 255 | h8_instructions = (struct h8_instruction *) |
| 256 | xmalloc (nopcodes * sizeof (struct h8_instruction)); |
| 257 | |
| 258 | pi = h8_instructions; |
| 259 | p1 = h8_opcodes; |
| 260 | /* We do a minimum amount of sorting on the opcode table; this is to |
| 261 | make it easy to describe the mova instructions without unnecessary |
| 262 | code duplication. |
| 263 | Sorting only takes place inside blocks of instructions of the form |
| 264 | X/Y, so for example mova/b, mova/w and mova/l can be intermixed. */ |
| 265 | while (p1) |
| 266 | { |
| 267 | struct h8_opcode *first_skipped = 0; |
| 268 | int len, cmplen = 0; |
| 269 | const char *src = p1->name; |
| 270 | char *dst, *buffer; |
| 271 | |
| 272 | if (p1->name == 0) |
| 273 | break; |
| 274 | /* Strip off any . part when inserting the opcode and only enter |
| 275 | unique codes into the hash table. */ |
| 276 | dst = buffer = malloc (strlen (src) + 1); |
| 277 | while (*src) |
| 278 | { |
| 279 | if (*src == '.') |
| 280 | { |
| 281 | src++; |
| 282 | break; |
| 283 | } |
| 284 | if (*src == '/') |
| 285 | cmplen = src - p1->name + 1; |
| 286 | *dst++ = *src++; |
| 287 | } |
| 288 | *dst = 0; |
| 289 | len = dst - buffer; |
| 290 | if (cmplen == 0) |
| 291 | cmplen = len; |
| 292 | hash_insert (opcode_hash_control, buffer, (char *) pi); |
| 293 | strcpy (prev_buffer, buffer); |
| 294 | idx++; |
| 295 | |
| 296 | for (p = p1; p->name; p++) |
| 297 | { |
| 298 | /* A negative TIME is used to indicate that we've added this opcode |
| 299 | already. */ |
| 300 | if (p->time == -1) |
| 301 | continue; |
| 302 | if (strncmp (p->name, buffer, cmplen) != 0 |
| 303 | || (p->name[cmplen] != '\0' && p->name[cmplen] != '.' |
| 304 | && p->name[cmplen - 1] != '/')) |
| 305 | { |
| 306 | if (first_skipped == 0) |
| 307 | first_skipped = p; |
| 308 | break; |
| 309 | } |
| 310 | if (strncmp (p->name, buffer, len) != 0) |
| 311 | { |
| 312 | if (first_skipped == 0) |
| 313 | first_skipped = p; |
| 314 | continue; |
| 315 | } |
| 316 | |
| 317 | p->time = -1; |
| 318 | pi->size = p->name[len] == '.' ? p->name[len + 1] : 0; |
| 319 | pi->idx = idx; |
| 320 | |
| 321 | /* Find the number of operands. */ |
| 322 | pi->noperands = 0; |
| 323 | while (pi->noperands < 3 && p->args.nib[pi->noperands] != (op_type) E) |
| 324 | pi->noperands++; |
| 325 | |
| 326 | /* Find the length of the opcode in bytes. */ |
| 327 | pi->length = 0; |
| 328 | while (p->data.nib[pi->length * 2] != (op_type) E) |
| 329 | pi->length++; |
| 330 | |
| 331 | pi->opcode = p; |
| 332 | pi++; |
| 333 | } |
| 334 | p1 = first_skipped; |
| 335 | } |
| 336 | |
| 337 | /* Add entry for the NULL vector terminator. */ |
| 338 | pi->length = 0; |
| 339 | pi->noperands = 0; |
| 340 | pi->idx = 0; |
| 341 | pi->size = 0; |
| 342 | pi->opcode = 0; |
| 343 | |
| 344 | linkrelax = 1; |
| 345 | } |
| 346 | |
| 347 | struct h8_op |
| 348 | { |
| 349 | op_type mode; |
| 350 | unsigned reg; |
| 351 | expressionS exp; |
| 352 | }; |
| 353 | |
| 354 | static void clever_message (const struct h8_instruction *, struct h8_op *); |
| 355 | static void fix_operand_size (struct h8_op *, int); |
| 356 | static void build_bytes (const struct h8_instruction *, struct h8_op *); |
| 357 | static void do_a_fix_imm (int, int, struct h8_op *, int, const struct h8_instruction *); |
| 358 | static void check_operand (struct h8_op *, unsigned int, const char *); |
| 359 | static const struct h8_instruction * get_specific (const struct h8_instruction *, struct h8_op *, int) ; |
| 360 | static char *get_operands (unsigned, char *, struct h8_op *); |
| 361 | static void get_operand (char **, struct h8_op *, int); |
| 362 | static int parse_reg (char *, op_type *, unsigned *, int); |
| 363 | static char *skip_colonthing (char *, int *); |
| 364 | static char *parse_exp (char *, struct h8_op *); |
| 365 | |
| 366 | static int constant_fits_size_p (struct h8_op *, int, int); |
| 367 | |
| 368 | /* |
| 369 | parse operands |
| 370 | WREG r0,r1,r2,r3,r4,r5,r6,r7,fp,sp |
| 371 | r0l,r0h,..r7l,r7h |
| 372 | @WREG |
| 373 | @WREG+ |
| 374 | @-WREG |
| 375 | #const |
| 376 | ccr |
| 377 | */ |
| 378 | |
| 379 | /* Try to parse a reg name. Return the number of chars consumed. */ |
| 380 | |
| 381 | static int |
| 382 | parse_reg (char *src, op_type *mode, unsigned int *reg, int direction) |
| 383 | { |
| 384 | char *end; |
| 385 | int len; |
| 386 | |
| 387 | /* Cribbed from get_symbol_name. */ |
| 388 | if (!is_name_beginner (*src) || *src == '\001') |
| 389 | return 0; |
| 390 | end = src + 1; |
| 391 | while ((is_part_of_name (*end) && *end != '.') || *end == '\001') |
| 392 | end++; |
| 393 | len = end - src; |
| 394 | |
| 395 | if (len == 2 && TOLOWER (src[0]) == 's' && TOLOWER (src[1]) == 'p') |
| 396 | { |
| 397 | *mode = PSIZE | REG | direction; |
| 398 | *reg = 7; |
| 399 | return len; |
| 400 | } |
| 401 | if (len == 3 && |
| 402 | TOLOWER (src[0]) == 'c' && |
| 403 | TOLOWER (src[1]) == 'c' && |
| 404 | TOLOWER (src[2]) == 'r') |
| 405 | { |
| 406 | *mode = CCR; |
| 407 | *reg = 0; |
| 408 | return len; |
| 409 | } |
| 410 | if (len == 3 && |
| 411 | TOLOWER (src[0]) == 'e' && |
| 412 | TOLOWER (src[1]) == 'x' && |
| 413 | TOLOWER (src[2]) == 'r') |
| 414 | { |
| 415 | *mode = EXR; |
| 416 | *reg = 1; |
| 417 | return len; |
| 418 | } |
| 419 | if (len == 3 && |
| 420 | TOLOWER (src[0]) == 'v' && |
| 421 | TOLOWER (src[1]) == 'b' && |
| 422 | TOLOWER (src[2]) == 'r') |
| 423 | { |
| 424 | *mode = VBR; |
| 425 | *reg = 6; |
| 426 | return len; |
| 427 | } |
| 428 | if (len == 3 && |
| 429 | TOLOWER (src[0]) == 's' && |
| 430 | TOLOWER (src[1]) == 'b' && |
| 431 | TOLOWER (src[2]) == 'r') |
| 432 | { |
| 433 | *mode = SBR; |
| 434 | *reg = 7; |
| 435 | return len; |
| 436 | } |
| 437 | if (len == 2 && TOLOWER (src[0]) == 'f' && TOLOWER (src[1]) == 'p') |
| 438 | { |
| 439 | *mode = PSIZE | REG | direction; |
| 440 | *reg = 6; |
| 441 | return len; |
| 442 | } |
| 443 | if (len == 3 && TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
| 444 | src[2] >= '0' && src[2] <= '7') |
| 445 | { |
| 446 | *mode = L_32 | REG | direction; |
| 447 | *reg = src[2] - '0'; |
| 448 | if (!Hmode) |
| 449 | as_warn (_("Reg not valid for H8/300")); |
| 450 | return len; |
| 451 | } |
| 452 | if (len == 2 && TOLOWER (src[0]) == 'e' && src[1] >= '0' && src[1] <= '7') |
| 453 | { |
| 454 | *mode = L_16 | REG | direction; |
| 455 | *reg = src[1] - '0' + 8; |
| 456 | if (!Hmode) |
| 457 | as_warn (_("Reg not valid for H8/300")); |
| 458 | return len; |
| 459 | } |
| 460 | |
| 461 | if (TOLOWER (src[0]) == 'r') |
| 462 | { |
| 463 | if (src[1] >= '0' && src[1] <= '7') |
| 464 | { |
| 465 | if (len == 3 && TOLOWER (src[2]) == 'l') |
| 466 | { |
| 467 | *mode = L_8 | REG | direction; |
| 468 | *reg = (src[1] - '0') + 8; |
| 469 | return len; |
| 470 | } |
| 471 | if (len == 3 && TOLOWER (src[2]) == 'h') |
| 472 | { |
| 473 | *mode = L_8 | REG | direction; |
| 474 | *reg = (src[1] - '0'); |
| 475 | return len; |
| 476 | } |
| 477 | if (len == 2) |
| 478 | { |
| 479 | *mode = L_16 | REG | direction; |
| 480 | *reg = (src[1] - '0'); |
| 481 | return len; |
| 482 | } |
| 483 | } |
| 484 | } |
| 485 | |
| 486 | return 0; |
| 487 | } |
| 488 | |
| 489 | |
| 490 | /* Parse an immediate or address-related constant and store it in OP. |
| 491 | If the user also specifies the operand's size, store that size |
| 492 | in OP->MODE, otherwise leave it for later code to decide. */ |
| 493 | |
| 494 | static char * |
| 495 | parse_exp (char *src, struct h8_op *op) |
| 496 | { |
| 497 | char *save; |
| 498 | |
| 499 | save = input_line_pointer; |
| 500 | input_line_pointer = src; |
| 501 | expression (&op->exp); |
| 502 | if (op->exp.X_op == O_absent) |
| 503 | as_bad (_("missing operand")); |
| 504 | src = input_line_pointer; |
| 505 | input_line_pointer = save; |
| 506 | |
| 507 | return skip_colonthing (src, &op->mode); |
| 508 | } |
| 509 | |
| 510 | |
| 511 | /* If SRC starts with an explicit operand size, skip it and store the size |
| 512 | in *MODE. Leave *MODE unchanged otherwise. */ |
| 513 | |
| 514 | static char * |
| 515 | skip_colonthing (char *src, int *mode) |
| 516 | { |
| 517 | if (*src == ':') |
| 518 | { |
| 519 | src++; |
| 520 | *mode &= ~SIZE; |
| 521 | if (src[0] == '8' && !ISDIGIT (src[1])) |
| 522 | *mode |= L_8; |
| 523 | else if (src[0] == '2' && !ISDIGIT (src[1])) |
| 524 | *mode |= L_2; |
| 525 | else if (src[0] == '3' && !ISDIGIT (src[1])) |
| 526 | *mode |= L_3; |
| 527 | else if (src[0] == '4' && !ISDIGIT (src[1])) |
| 528 | *mode |= L_4; |
| 529 | else if (src[0] == '5' && !ISDIGIT (src[1])) |
| 530 | *mode |= L_5; |
| 531 | else if (src[0] == '2' && src[1] == '4' && !ISDIGIT (src[2])) |
| 532 | *mode |= L_24; |
| 533 | else if (src[0] == '3' && src[1] == '2' && !ISDIGIT (src[2])) |
| 534 | *mode |= L_32; |
| 535 | else if (src[0] == '1' && src[1] == '6' && !ISDIGIT (src[2])) |
| 536 | *mode |= L_16; |
| 537 | else |
| 538 | as_bad (_("invalid operand size requested")); |
| 539 | |
| 540 | while (ISDIGIT (*src)) |
| 541 | src++; |
| 542 | } |
| 543 | return src; |
| 544 | } |
| 545 | |
| 546 | /* The many forms of operand: |
| 547 | |
| 548 | Rn Register direct |
| 549 | @Rn Register indirect |
| 550 | @(exp[:16], Rn) Register indirect with displacement |
| 551 | @Rn+ |
| 552 | @-Rn |
| 553 | @aa:8 absolute 8 bit |
| 554 | @aa:16 absolute 16 bit |
| 555 | @aa absolute 16 bit |
| 556 | |
| 557 | #xx[:size] immediate data |
| 558 | @(exp:[8], pc) pc rel |
| 559 | @@aa[:8] memory indirect. */ |
| 560 | |
| 561 | static int |
| 562 | constant_fits_width_p (struct h8_op *operand, offsetT width) |
| 563 | { |
| 564 | offsetT num; |
| 565 | |
| 566 | num = ((operand->exp.X_add_number & 0xffffffff) ^ 0x80000000) - 0x80000000; |
| 567 | return (num & ~width) == 0 || (num | width) == ~0; |
| 568 | } |
| 569 | |
| 570 | static int |
| 571 | constant_fits_size_p (struct h8_op *operand, int size, int no_symbols) |
| 572 | { |
| 573 | offsetT num; |
| 574 | |
| 575 | if (no_symbols |
| 576 | && (operand->exp.X_add_symbol != 0 || operand->exp.X_op_symbol != 0)) |
| 577 | return 0; |
| 578 | num = operand->exp.X_add_number & 0xffffffff; |
| 579 | switch (size) |
| 580 | { |
| 581 | case L_2: |
| 582 | return (num & ~3) == 0; |
| 583 | case L_3: |
| 584 | return (num & ~7) == 0; |
| 585 | case L_3NZ: |
| 586 | return num >= 1 && num < 8; |
| 587 | case L_4: |
| 588 | return (num & ~15) == 0; |
| 589 | case L_5: |
| 590 | return num >= 1 && num < 32; |
| 591 | case L_8: |
| 592 | num = (num ^ 0x80000000) - 0x80000000; |
| 593 | return (num & ~0xFF) == 0 || (num | 0x7F) == ~0; |
| 594 | case L_8U: |
| 595 | return (num & ~0xFF) == 0; |
| 596 | case L_16: |
| 597 | num = (num ^ 0x80000000) - 0x80000000; |
| 598 | return (num & ~0xFFFF) == 0 || (num | 0x7FFF) == ~0; |
| 599 | case L_16U: |
| 600 | return (num & ~0xFFFF) == 0; |
| 601 | case L_32: |
| 602 | return 1; |
| 603 | default: |
| 604 | abort (); |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | static void |
| 609 | get_operand (char **ptr, struct h8_op *op, int direction) |
| 610 | { |
| 611 | char *src = *ptr; |
| 612 | op_type mode; |
| 613 | unsigned int num; |
| 614 | unsigned int len; |
| 615 | |
| 616 | op->mode = 0; |
| 617 | |
| 618 | /* Check for '(' and ')' for instructions ldm and stm. */ |
| 619 | if (src[0] == '(' && src[8] == ')') |
| 620 | ++ src; |
| 621 | |
| 622 | /* Gross. Gross. ldm and stm have a format not easily handled |
| 623 | by get_operand. We deal with it explicitly here. */ |
| 624 | if (TOLOWER (src[0]) == 'e' && TOLOWER (src[1]) == 'r' && |
| 625 | ISDIGIT (src[2]) && src[3] == '-' && |
| 626 | TOLOWER (src[4]) == 'e' && TOLOWER (src[5]) == 'r' && ISDIGIT (src[6])) |
| 627 | { |
| 628 | int low, high; |
| 629 | |
| 630 | low = src[2] - '0'; |
| 631 | high = src[6] - '0'; |
| 632 | |
| 633 | /* Check register pair's validity as per tech note TN-H8*-193A/E |
| 634 | from Renesas for H8S and H8SX hardware manual. */ |
| 635 | if ( !(low == 0 && (high == 1 || high == 2 || high == 3)) |
| 636 | && !(low == 1 && (high == 2 || high == 3 || high == 4) && SXmode) |
| 637 | && !(low == 2 && (high == 3 || ((high == 4 || high == 5) && SXmode))) |
| 638 | && !(low == 3 && (high == 4 || high == 5 || high == 6) && SXmode) |
| 639 | && !(low == 4 && (high == 5 || high == 6)) |
| 640 | && !(low == 4 && high == 7 && SXmode) |
| 641 | && !(low == 5 && (high == 6 || high == 7) && SXmode) |
| 642 | && !(low == 6 && high == 7 && SXmode)) |
| 643 | as_bad (_("Invalid register list for ldm/stm\n")); |
| 644 | |
| 645 | /* Even sicker. We encode two registers into op->reg. One |
| 646 | for the low register to save, the other for the high |
| 647 | register to save; we also set the high bit in op->reg |
| 648 | so we know this is "very special". */ |
| 649 | op->reg = 0x80000000 | (high << 8) | low; |
| 650 | op->mode = REG; |
| 651 | if (src[7] == ')') |
| 652 | *ptr = src + 8; |
| 653 | else |
| 654 | *ptr = src + 7; |
| 655 | return; |
| 656 | } |
| 657 | |
| 658 | len = parse_reg (src, &op->mode, &op->reg, direction); |
| 659 | if (len) |
| 660 | { |
| 661 | src += len; |
| 662 | if (*src == '.') |
| 663 | { |
| 664 | int size = op->mode & SIZE; |
| 665 | switch (src[1]) |
| 666 | { |
| 667 | case 'l': case 'L': |
| 668 | if (size != L_32) |
| 669 | as_warn (_("mismatch between register and suffix")); |
| 670 | op->mode = (op->mode & ~MODE) | LOWREG; |
| 671 | break; |
| 672 | case 'w': case 'W': |
| 673 | if (size != L_32 && size != L_16) |
| 674 | as_warn (_("mismatch between register and suffix")); |
| 675 | op->mode = (op->mode & ~MODE) | LOWREG; |
| 676 | op->mode = (op->mode & ~SIZE) | L_16; |
| 677 | break; |
| 678 | case 'b': case 'B': |
| 679 | op->mode = (op->mode & ~MODE) | LOWREG; |
| 680 | if (size != L_32 && size != L_8) |
| 681 | as_warn (_("mismatch between register and suffix")); |
| 682 | op->mode = (op->mode & ~MODE) | LOWREG; |
| 683 | op->mode = (op->mode & ~SIZE) | L_8; |
| 684 | break; |
| 685 | default: |
| 686 | as_warn (_("invalid suffix after register.")); |
| 687 | break; |
| 688 | } |
| 689 | src += 2; |
| 690 | } |
| 691 | *ptr = src; |
| 692 | return; |
| 693 | } |
| 694 | |
| 695 | if (*src == '@') |
| 696 | { |
| 697 | src++; |
| 698 | if (*src == '@') |
| 699 | { |
| 700 | *ptr = parse_exp (src + 1, op); |
| 701 | if (op->exp.X_add_number >= 0x100) |
| 702 | { |
| 703 | int divisor = 1; |
| 704 | |
| 705 | op->mode = VECIND; |
| 706 | /* FIXME : 2? or 4? */ |
| 707 | if (op->exp.X_add_number >= 0x400) |
| 708 | as_bad (_("address too high for vector table jmp/jsr")); |
| 709 | else if (op->exp.X_add_number >= 0x200) |
| 710 | divisor = 4; |
| 711 | else |
| 712 | divisor = 2; |
| 713 | |
| 714 | op->exp.X_add_number = op->exp.X_add_number / divisor - 0x80; |
| 715 | } |
| 716 | else |
| 717 | op->mode = MEMIND; |
| 718 | return; |
| 719 | } |
| 720 | |
| 721 | if (*src == '-' || *src == '+') |
| 722 | { |
| 723 | len = parse_reg (src + 1, &mode, &num, direction); |
| 724 | if (len == 0) |
| 725 | { |
| 726 | /* Oops, not a reg after all, must be ordinary exp. */ |
| 727 | op->mode = ABS | direction; |
| 728 | *ptr = parse_exp (src, op); |
| 729 | return; |
| 730 | } |
| 731 | |
| 732 | if (((mode & SIZE) != PSIZE) |
| 733 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ |
| 734 | && (!Nmode || ((mode & SIZE) != L_32))) |
| 735 | as_bad (_("Wrong size pointer register for architecture.")); |
| 736 | |
| 737 | op->mode = src[0] == '-' ? RDPREDEC : RDPREINC; |
| 738 | op->reg = num; |
| 739 | *ptr = src + 1 + len; |
| 740 | return; |
| 741 | } |
| 742 | if (*src == '(') |
| 743 | { |
| 744 | src++; |
| 745 | |
| 746 | /* See if this is @(ERn.x, PC). */ |
| 747 | len = parse_reg (src, &mode, &op->reg, direction); |
| 748 | if (len != 0 && (mode & MODE) == REG && src[len] == '.') |
| 749 | { |
| 750 | switch (TOLOWER (src[len + 1])) |
| 751 | { |
| 752 | case 'b': |
| 753 | mode = PCIDXB | direction; |
| 754 | break; |
| 755 | case 'w': |
| 756 | mode = PCIDXW | direction; |
| 757 | break; |
| 758 | case 'l': |
| 759 | mode = PCIDXL | direction; |
| 760 | break; |
| 761 | default: |
| 762 | mode = 0; |
| 763 | break; |
| 764 | } |
| 765 | if (mode |
| 766 | && src[len + 2] == ',' |
| 767 | && TOLOWER (src[len + 3]) != 'p' |
| 768 | && TOLOWER (src[len + 4]) != 'c' |
| 769 | && src[len + 5] != ')') |
| 770 | { |
| 771 | *ptr = src + len + 6; |
| 772 | op->mode |= mode; |
| 773 | return; |
| 774 | } |
| 775 | /* Fall through into disp case - the grammar is somewhat |
| 776 | ambiguous, so we should try whether it's a DISP operand |
| 777 | after all ("ER3.L" might be a poorly named label...). */ |
| 778 | } |
| 779 | |
| 780 | /* Disp. */ |
| 781 | |
| 782 | /* Start off assuming a 16 bit offset. */ |
| 783 | |
| 784 | src = parse_exp (src, op); |
| 785 | if (*src == ')') |
| 786 | { |
| 787 | op->mode |= ABS | direction; |
| 788 | *ptr = src + 1; |
| 789 | return; |
| 790 | } |
| 791 | |
| 792 | if (*src != ',') |
| 793 | { |
| 794 | as_bad (_("expected @(exp, reg16)")); |
| 795 | return; |
| 796 | } |
| 797 | src++; |
| 798 | |
| 799 | len = parse_reg (src, &mode, &op->reg, direction); |
| 800 | if (len == 0 || (mode & MODE) != REG) |
| 801 | { |
| 802 | as_bad (_("expected @(exp, reg16)")); |
| 803 | return; |
| 804 | } |
| 805 | src += len; |
| 806 | if (src[0] == '.') |
| 807 | { |
| 808 | switch (TOLOWER (src[1])) |
| 809 | { |
| 810 | case 'b': |
| 811 | op->mode |= INDEXB | direction; |
| 812 | break; |
| 813 | case 'w': |
| 814 | op->mode |= INDEXW | direction; |
| 815 | break; |
| 816 | case 'l': |
| 817 | op->mode |= INDEXL | direction; |
| 818 | break; |
| 819 | default: |
| 820 | as_bad (_("expected .L, .W or .B for register in indexed addressing mode")); |
| 821 | } |
| 822 | src += 2; |
| 823 | op->reg &= 7; |
| 824 | } |
| 825 | else |
| 826 | op->mode |= DISP | direction; |
| 827 | src = skip_colonthing (src, &op->mode); |
| 828 | |
| 829 | if (*src != ')') |
| 830 | { |
| 831 | as_bad (_("expected @(exp, reg16)")); |
| 832 | return; |
| 833 | } |
| 834 | *ptr = src + 1; |
| 835 | return; |
| 836 | } |
| 837 | len = parse_reg (src, &mode, &num, direction); |
| 838 | |
| 839 | if (len) |
| 840 | { |
| 841 | src += len; |
| 842 | if (*src == '+' || *src == '-') |
| 843 | { |
| 844 | if (((mode & SIZE) != PSIZE) |
| 845 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ |
| 846 | && (!Nmode || ((mode & SIZE) != L_32))) |
| 847 | as_bad (_("Wrong size pointer register for architecture.")); |
| 848 | op->mode = *src == '+' ? RSPOSTINC : RSPOSTDEC; |
| 849 | op->reg = num; |
| 850 | src++; |
| 851 | *ptr = src; |
| 852 | return; |
| 853 | } |
| 854 | if (((mode & SIZE) != PSIZE) |
| 855 | /* For Normal mode accept 16 bit and 32 bit pointer registers. */ |
| 856 | && (!Nmode || ((mode & SIZE) != L_32))) |
| 857 | as_bad (_("Wrong size pointer register for architecture.")); |
| 858 | |
| 859 | op->mode = direction | IND | PSIZE; |
| 860 | op->reg = num; |
| 861 | *ptr = src; |
| 862 | |
| 863 | return; |
| 864 | } |
| 865 | else |
| 866 | { |
| 867 | /* must be a symbol */ |
| 868 | |
| 869 | op->mode = ABS | direction; |
| 870 | *ptr = parse_exp (src, op); |
| 871 | return; |
| 872 | } |
| 873 | } |
| 874 | |
| 875 | if (*src == '#') |
| 876 | { |
| 877 | op->mode = IMM; |
| 878 | *ptr = parse_exp (src + 1, op); |
| 879 | return; |
| 880 | } |
| 881 | else if (strncmp (src, "mach", 4) == 0 || |
| 882 | strncmp (src, "macl", 4) == 0 || |
| 883 | strncmp (src, "MACH", 4) == 0 || |
| 884 | strncmp (src, "MACL", 4) == 0) |
| 885 | { |
| 886 | op->reg = TOLOWER (src[3]) == 'l'; |
| 887 | op->mode = MACREG; |
| 888 | *ptr = src + 4; |
| 889 | return; |
| 890 | } |
| 891 | else |
| 892 | { |
| 893 | op->mode = PCREL; |
| 894 | *ptr = parse_exp (src, op); |
| 895 | } |
| 896 | } |
| 897 | |
| 898 | static char * |
| 899 | get_operands (unsigned int noperands, char *op_end, struct h8_op *operand) |
| 900 | { |
| 901 | char *ptr = op_end; |
| 902 | |
| 903 | switch (noperands) |
| 904 | { |
| 905 | case 0: |
| 906 | break; |
| 907 | |
| 908 | case 1: |
| 909 | ptr++; |
| 910 | get_operand (&ptr, operand + 0, SRC); |
| 911 | if (*ptr == ',') |
| 912 | { |
| 913 | ptr++; |
| 914 | get_operand (&ptr, operand + 1, DST); |
| 915 | } |
| 916 | break; |
| 917 | |
| 918 | case 2: |
| 919 | ptr++; |
| 920 | get_operand (&ptr, operand + 0, SRC); |
| 921 | if (*ptr == ',') |
| 922 | ptr++; |
| 923 | get_operand (&ptr, operand + 1, DST); |
| 924 | break; |
| 925 | |
| 926 | case 3: |
| 927 | ptr++; |
| 928 | get_operand (&ptr, operand + 0, SRC); |
| 929 | if (*ptr == ',') |
| 930 | ptr++; |
| 931 | get_operand (&ptr, operand + 1, DST); |
| 932 | if (*ptr == ',') |
| 933 | ptr++; |
| 934 | get_operand (&ptr, operand + 2, OP3); |
| 935 | break; |
| 936 | |
| 937 | default: |
| 938 | abort (); |
| 939 | } |
| 940 | |
| 941 | return ptr; |
| 942 | } |
| 943 | |
| 944 | /* MOVA has special requirements. Rather than adding twice the amount of |
| 945 | addressing modes, we simply special case it a bit. */ |
| 946 | static void |
| 947 | get_mova_operands (char *op_end, struct h8_op *operand) |
| 948 | { |
| 949 | char *ptr = op_end; |
| 950 | |
| 951 | if (ptr[1] != '@' || ptr[2] != '(') |
| 952 | goto error; |
| 953 | ptr += 3; |
| 954 | operand[0].mode = 0; |
| 955 | ptr = parse_exp (ptr, &operand[0]); |
| 956 | |
| 957 | if (*ptr !=',') |
| 958 | goto error; |
| 959 | ptr++; |
| 960 | get_operand (&ptr, operand + 1, DST); |
| 961 | |
| 962 | if (*ptr =='.') |
| 963 | { |
| 964 | ptr++; |
| 965 | switch (*ptr++) |
| 966 | { |
| 967 | case 'b': case 'B': |
| 968 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; |
| 969 | break; |
| 970 | case 'w': case 'W': |
| 971 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; |
| 972 | break; |
| 973 | case 'l': case 'L': |
| 974 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; |
| 975 | break; |
| 976 | default: |
| 977 | goto error; |
| 978 | } |
| 979 | } |
| 980 | else if ((operand[1].mode & MODE) == LOWREG) |
| 981 | { |
| 982 | switch (operand[1].mode & SIZE) |
| 983 | { |
| 984 | case L_8: |
| 985 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXB; |
| 986 | break; |
| 987 | case L_16: |
| 988 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXW; |
| 989 | break; |
| 990 | case L_32: |
| 991 | operand[0].mode = (operand[0].mode & ~MODE) | INDEXL; |
| 992 | break; |
| 993 | default: |
| 994 | goto error; |
| 995 | } |
| 996 | } |
| 997 | else |
| 998 | goto error; |
| 999 | |
| 1000 | if (*ptr++ != ')' || *ptr++ != ',') |
| 1001 | goto error; |
| 1002 | get_operand (&ptr, operand + 2, OP3); |
| 1003 | /* See if we can use the short form of MOVA. */ |
| 1004 | if (((operand[1].mode & MODE) == REG || (operand[1].mode & MODE) == LOWREG) |
| 1005 | && (operand[2].mode & MODE) == REG |
| 1006 | && (operand[1].reg & 7) == (operand[2].reg & 7)) |
| 1007 | { |
| 1008 | operand[1].mode = operand[2].mode = 0; |
| 1009 | operand[0].reg = operand[2].reg & 7; |
| 1010 | } |
| 1011 | return; |
| 1012 | |
| 1013 | error: |
| 1014 | as_bad (_("expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"")); |
| 1015 | } |
| 1016 | |
| 1017 | static void |
| 1018 | get_rtsl_operands (char *ptr, struct h8_op *operand) |
| 1019 | { |
| 1020 | int mode, len, type = 0; |
| 1021 | unsigned int num, num2; |
| 1022 | |
| 1023 | ptr++; |
| 1024 | if (*ptr == '(') |
| 1025 | { |
| 1026 | ptr++; |
| 1027 | type = 1; |
| 1028 | } |
| 1029 | len = parse_reg (ptr, &mode, &num, SRC); |
| 1030 | if (len == 0 || (mode & MODE) != REG) |
| 1031 | { |
| 1032 | as_bad (_("expected register")); |
| 1033 | return; |
| 1034 | } |
| 1035 | ptr += len; |
| 1036 | if (*ptr == '-') |
| 1037 | { |
| 1038 | len = parse_reg (++ptr, &mode, &num2, SRC); |
| 1039 | if (len == 0 || (mode & MODE) != REG) |
| 1040 | { |
| 1041 | as_bad (_("expected register")); |
| 1042 | return; |
| 1043 | } |
| 1044 | ptr += len; |
| 1045 | /* CONST_xxx are used as placeholders in the opcode table. */ |
| 1046 | num = num2 - num; |
| 1047 | if (num > 3) |
| 1048 | { |
| 1049 | as_bad (_("invalid register list")); |
| 1050 | return; |
| 1051 | } |
| 1052 | } |
| 1053 | else |
| 1054 | num2 = num, num = 0; |
| 1055 | if (type == 1 && *ptr++ != ')') |
| 1056 | { |
| 1057 | as_bad (_("expected closing paren")); |
| 1058 | return; |
| 1059 | } |
| 1060 | operand[0].mode = RS32; |
| 1061 | operand[1].mode = RD32; |
| 1062 | operand[0].reg = num; |
| 1063 | operand[1].reg = num2; |
| 1064 | } |
| 1065 | |
| 1066 | /* Passed a pointer to a list of opcodes which use different |
| 1067 | addressing modes, return the opcode which matches the opcodes |
| 1068 | provided. */ |
| 1069 | |
| 1070 | static const struct h8_instruction * |
| 1071 | get_specific (const struct h8_instruction *instruction, |
| 1072 | struct h8_op *operands, int size) |
| 1073 | { |
| 1074 | const struct h8_instruction *this_try = instruction; |
| 1075 | const struct h8_instruction *found_other = 0, *found_mismatched = 0; |
| 1076 | int found = 0; |
| 1077 | int this_index = instruction->idx; |
| 1078 | int noperands = 0; |
| 1079 | |
| 1080 | /* There's only one ldm/stm and it's easier to just |
| 1081 | get out quick for them. */ |
| 1082 | if (OP_KIND (instruction->opcode->how) == O_LDM |
| 1083 | || OP_KIND (instruction->opcode->how) == O_STM) |
| 1084 | return this_try; |
| 1085 | |
| 1086 | while (noperands < 3 && operands[noperands].mode != 0) |
| 1087 | noperands++; |
| 1088 | |
| 1089 | while (this_index == instruction->idx && !found) |
| 1090 | { |
| 1091 | int this_size; |
| 1092 | |
| 1093 | found = 1; |
| 1094 | this_try = instruction++; |
| 1095 | this_size = this_try->opcode->how & SN; |
| 1096 | |
| 1097 | if (this_try->noperands != noperands) |
| 1098 | found = 0; |
| 1099 | else if (this_try->noperands > 0) |
| 1100 | { |
| 1101 | int i; |
| 1102 | |
| 1103 | for (i = 0; i < this_try->noperands && found; i++) |
| 1104 | { |
| 1105 | op_type op = this_try->opcode->args.nib[i]; |
| 1106 | int op_mode = op & MODE; |
| 1107 | int op_size = op & SIZE; |
| 1108 | int x = operands[i].mode; |
| 1109 | int x_mode = x & MODE; |
| 1110 | int x_size = x & SIZE; |
| 1111 | |
| 1112 | if (op_mode == LOWREG && (x_mode == REG || x_mode == LOWREG)) |
| 1113 | { |
| 1114 | if ((x_size == L_8 && (operands[i].reg & 8) == 0) |
| 1115 | || (x_size == L_16 && (operands[i].reg & 8) == 8)) |
| 1116 | as_warn (_("can't use high part of register in operand %d"), i); |
| 1117 | |
| 1118 | if (x_size != op_size) |
| 1119 | found = 0; |
| 1120 | } |
| 1121 | else if (op_mode == REG) |
| 1122 | { |
| 1123 | if (x_mode == LOWREG) |
| 1124 | x_mode = REG; |
| 1125 | if (x_mode != REG) |
| 1126 | found = 0; |
| 1127 | |
| 1128 | if (x_size == L_P) |
| 1129 | x_size = (Hmode ? L_32 : L_16); |
| 1130 | if (op_size == L_P) |
| 1131 | op_size = (Hmode ? L_32 : L_16); |
| 1132 | |
| 1133 | /* The size of the reg is v important. */ |
| 1134 | if (op_size != x_size) |
| 1135 | found = 0; |
| 1136 | } |
| 1137 | else if (op_mode & CTRL) /* control register */ |
| 1138 | { |
| 1139 | if (!(x_mode & CTRL)) |
| 1140 | found = 0; |
| 1141 | |
| 1142 | switch (x_mode) |
| 1143 | { |
| 1144 | case CCR: |
| 1145 | if (op_mode != CCR && |
| 1146 | op_mode != CCR_EXR && |
| 1147 | op_mode != CC_EX_VB_SB) |
| 1148 | found = 0; |
| 1149 | break; |
| 1150 | case EXR: |
| 1151 | if (op_mode != EXR && |
| 1152 | op_mode != CCR_EXR && |
| 1153 | op_mode != CC_EX_VB_SB) |
| 1154 | found = 0; |
| 1155 | break; |
| 1156 | case MACH: |
| 1157 | if (op_mode != MACH && |
| 1158 | op_mode != MACREG) |
| 1159 | found = 0; |
| 1160 | break; |
| 1161 | case MACL: |
| 1162 | if (op_mode != MACL && |
| 1163 | op_mode != MACREG) |
| 1164 | found = 0; |
| 1165 | break; |
| 1166 | case VBR: |
| 1167 | if (op_mode != VBR && |
| 1168 | op_mode != VBR_SBR && |
| 1169 | op_mode != CC_EX_VB_SB) |
| 1170 | found = 0; |
| 1171 | break; |
| 1172 | case SBR: |
| 1173 | if (op_mode != SBR && |
| 1174 | op_mode != VBR_SBR && |
| 1175 | op_mode != CC_EX_VB_SB) |
| 1176 | found = 0; |
| 1177 | break; |
| 1178 | } |
| 1179 | } |
| 1180 | else if ((op & ABSJMP) && (x_mode == ABS || x_mode == PCREL)) |
| 1181 | { |
| 1182 | operands[i].mode &= ~MODE; |
| 1183 | operands[i].mode |= ABSJMP; |
| 1184 | /* But it may not be 24 bits long. */ |
| 1185 | if (x_mode == ABS && !Hmode) |
| 1186 | { |
| 1187 | operands[i].mode &= ~SIZE; |
| 1188 | operands[i].mode |= L_16; |
| 1189 | } |
| 1190 | if ((operands[i].mode & SIZE) == L_32 |
| 1191 | && (op_mode & SIZE) != L_32) |
| 1192 | found = 0; |
| 1193 | } |
| 1194 | else if (x_mode == IMM && op_mode != IMM) |
| 1195 | { |
| 1196 | offsetT num = operands[i].exp.X_add_number & 0xffffffff; |
| 1197 | if (op_mode == KBIT || op_mode == DBIT) |
| 1198 | /* This is ok if the immediate value is sensible. */; |
| 1199 | else if (op_mode == CONST_2) |
| 1200 | found = num == 2; |
| 1201 | else if (op_mode == CONST_4) |
| 1202 | found = num == 4; |
| 1203 | else if (op_mode == CONST_8) |
| 1204 | found = num == 8; |
| 1205 | else if (op_mode == CONST_16) |
| 1206 | found = num == 16; |
| 1207 | else |
| 1208 | found = 0; |
| 1209 | } |
| 1210 | else if (op_mode == PCREL && op_mode == x_mode) |
| 1211 | { |
| 1212 | /* movsd, bsr/bc and bsr/bs only come in PCREL16 flavour: |
| 1213 | If x_size is L_8, promote it. */ |
| 1214 | if (OP_KIND (this_try->opcode->how) == O_MOVSD |
| 1215 | || OP_KIND (this_try->opcode->how) == O_BSRBC |
| 1216 | || OP_KIND (this_try->opcode->how) == O_BSRBS) |
| 1217 | if (x_size == L_8) |
| 1218 | x_size = L_16; |
| 1219 | |
| 1220 | /* The size of the displacement is important. */ |
| 1221 | if (op_size != x_size) |
| 1222 | found = 0; |
| 1223 | } |
| 1224 | else if ((op_mode == DISP || op_mode == IMM || op_mode == ABS |
| 1225 | || op_mode == INDEXB || op_mode == INDEXW |
| 1226 | || op_mode == INDEXL) |
| 1227 | && op_mode == x_mode) |
| 1228 | { |
| 1229 | /* Promote a L_24 to L_32 if it makes us match. */ |
| 1230 | if (x_size == L_24 && op_size == L_32) |
| 1231 | { |
| 1232 | x &= ~SIZE; |
| 1233 | x |= x_size = L_32; |
| 1234 | } |
| 1235 | |
| 1236 | if (((x_size == L_16 && op_size == L_16U) |
| 1237 | || (x_size == L_8 && op_size == L_8U) |
| 1238 | || (x_size == L_3 && op_size == L_3NZ)) |
| 1239 | /* We're deliberately more permissive for ABS modes. */ |
| 1240 | && (op_mode == ABS |
| 1241 | || constant_fits_size_p (operands + i, op_size, |
| 1242 | op & NO_SYMBOLS))) |
| 1243 | x_size = op_size; |
| 1244 | |
| 1245 | if (x_size != 0 && op_size != x_size) |
| 1246 | found = 0; |
| 1247 | else if (x_size == 0 |
| 1248 | && ! constant_fits_size_p (operands + i, op_size, |
| 1249 | op & NO_SYMBOLS)) |
| 1250 | found = 0; |
| 1251 | } |
| 1252 | else if (op_mode != x_mode) |
| 1253 | { |
| 1254 | found = 0; |
| 1255 | } |
| 1256 | } |
| 1257 | } |
| 1258 | if (found) |
| 1259 | { |
| 1260 | if ((this_try->opcode->available == AV_H8SX && ! SXmode) |
| 1261 | || (this_try->opcode->available == AV_H8S && ! Smode) |
| 1262 | || (this_try->opcode->available == AV_H8H && ! Hmode)) |
| 1263 | found = 0, found_other = this_try; |
| 1264 | else if (this_size != size && (this_size != SN && size != SN)) |
| 1265 | found_mismatched = this_try, found = 0; |
| 1266 | |
| 1267 | } |
| 1268 | } |
| 1269 | if (found) |
| 1270 | return this_try; |
| 1271 | if (found_other) |
| 1272 | { |
| 1273 | as_warn (_("Opcode `%s' with these operand types not available in %s mode"), |
| 1274 | found_other->opcode->name, |
| 1275 | (! Hmode && ! Smode ? "H8/300" |
| 1276 | : SXmode ? "H8sx" |
| 1277 | : Smode ? "H8/300S" |
| 1278 | : "H8/300H")); |
| 1279 | } |
| 1280 | else if (found_mismatched) |
| 1281 | { |
| 1282 | as_warn (_("mismatch between opcode size and operand size")); |
| 1283 | return found_mismatched; |
| 1284 | } |
| 1285 | return 0; |
| 1286 | } |
| 1287 | |
| 1288 | static void |
| 1289 | check_operand (struct h8_op *operand, unsigned int width, const char *string) |
| 1290 | { |
| 1291 | if (operand->exp.X_add_symbol == 0 |
| 1292 | && operand->exp.X_op_symbol == 0) |
| 1293 | { |
| 1294 | /* No symbol involved, let's look at offset, it's dangerous if |
| 1295 | any of the high bits are not 0 or ff's, find out by oring or |
| 1296 | anding with the width and seeing if the answer is 0 or all |
| 1297 | fs. */ |
| 1298 | |
| 1299 | if (! constant_fits_width_p (operand, width)) |
| 1300 | { |
| 1301 | if (width == 255 |
| 1302 | && (operand->exp.X_add_number & 0xff00) == 0xff00) |
| 1303 | { |
| 1304 | /* Just ignore this one - which happens when trying to |
| 1305 | fit a 16 bit address truncated into an 8 bit address |
| 1306 | of something like bset. */ |
| 1307 | } |
| 1308 | else if (strcmp (string, "@") == 0 |
| 1309 | && width == 0xffff |
| 1310 | && (operand->exp.X_add_number & 0xff8000) == 0xff8000) |
| 1311 | { |
| 1312 | /* Just ignore this one - which happens when trying to |
| 1313 | fit a 24 bit address truncated into a 16 bit address |
| 1314 | of something like mov.w. */ |
| 1315 | } |
| 1316 | else |
| 1317 | { |
| 1318 | as_warn (_("operand %s0x%lx out of range."), string, |
| 1319 | (unsigned long) operand->exp.X_add_number); |
| 1320 | } |
| 1321 | } |
| 1322 | } |
| 1323 | } |
| 1324 | |
| 1325 | /* RELAXMODE has one of 3 values: |
| 1326 | |
| 1327 | 0 Output a "normal" reloc, no relaxing possible for this insn/reloc |
| 1328 | |
| 1329 | 1 Output a relaxable 24bit absolute mov.w address relocation |
| 1330 | (may relax into a 16bit absolute address). |
| 1331 | |
| 1332 | 2 Output a relaxable 16/24 absolute mov.b address relocation |
| 1333 | (may relax into an 8bit absolute address). */ |
| 1334 | |
| 1335 | static void |
| 1336 | do_a_fix_imm (int offset, int nibble, struct h8_op *operand, int relaxmode, const struct h8_instruction *this_try) |
| 1337 | { |
| 1338 | int idx; |
| 1339 | int size; |
| 1340 | int where; |
| 1341 | char *bytes = frag_now->fr_literal + offset; |
| 1342 | |
| 1343 | const char *t = ((operand->mode & MODE) == IMM) ? "#" : "@"; |
| 1344 | |
| 1345 | if (operand->exp.X_add_symbol == 0) |
| 1346 | { |
| 1347 | switch (operand->mode & SIZE) |
| 1348 | { |
| 1349 | case L_2: |
| 1350 | check_operand (operand, 0x3, t); |
| 1351 | bytes[0] |= (operand->exp.X_add_number & 3) << (nibble ? 0 : 4); |
| 1352 | break; |
| 1353 | case L_3: |
| 1354 | case L_3NZ: |
| 1355 | check_operand (operand, 0x7, t); |
| 1356 | bytes[0] |= (operand->exp.X_add_number & 7) << (nibble ? 0 : 4); |
| 1357 | break; |
| 1358 | case L_4: |
| 1359 | check_operand (operand, 0xF, t); |
| 1360 | bytes[0] |= (operand->exp.X_add_number & 15) << (nibble ? 0 : 4); |
| 1361 | break; |
| 1362 | case L_5: |
| 1363 | check_operand (operand, 0x1F, t); |
| 1364 | bytes[0] |= operand->exp.X_add_number & 31; |
| 1365 | break; |
| 1366 | case L_8: |
| 1367 | case L_8U: |
| 1368 | check_operand (operand, 0xff, t); |
| 1369 | bytes[0] |= operand->exp.X_add_number; |
| 1370 | break; |
| 1371 | case L_16: |
| 1372 | case L_16U: |
| 1373 | check_operand (operand, 0xffff, t); |
| 1374 | bytes[0] |= operand->exp.X_add_number >> 8; |
| 1375 | bytes[1] |= operand->exp.X_add_number >> 0; |
| 1376 | #ifdef OBJ_ELF |
| 1377 | /* MOVA needs both relocs to relax the second operand properly. */ |
| 1378 | if (relaxmode != 0 |
| 1379 | && (OP_KIND(this_try->opcode->how) == O_MOVAB |
| 1380 | || OP_KIND(this_try->opcode->how) == O_MOVAW |
| 1381 | || OP_KIND(this_try->opcode->how) == O_MOVAL)) |
| 1382 | { |
| 1383 | idx = BFD_RELOC_16; |
| 1384 | fix_new_exp (frag_now, offset, 2, &operand->exp, 0, idx); |
| 1385 | } |
| 1386 | #endif |
| 1387 | break; |
| 1388 | case L_24: |
| 1389 | check_operand (operand, 0xffffff, t); |
| 1390 | bytes[0] |= operand->exp.X_add_number >> 16; |
| 1391 | bytes[1] |= operand->exp.X_add_number >> 8; |
| 1392 | bytes[2] |= operand->exp.X_add_number >> 0; |
| 1393 | break; |
| 1394 | |
| 1395 | case L_32: |
| 1396 | /* This should be done with bfd. */ |
| 1397 | bytes[0] |= operand->exp.X_add_number >> 24; |
| 1398 | bytes[1] |= operand->exp.X_add_number >> 16; |
| 1399 | bytes[2] |= operand->exp.X_add_number >> 8; |
| 1400 | bytes[3] |= operand->exp.X_add_number >> 0; |
| 1401 | if (relaxmode != 0) |
| 1402 | { |
| 1403 | #ifdef OBJ_ELF |
| 1404 | if ((operand->mode & MODE) == DISP && relaxmode == 1) |
| 1405 | idx = BFD_RELOC_H8_DISP32A16; |
| 1406 | else |
| 1407 | #endif |
| 1408 | idx = (relaxmode == 2) ? R_MOV24B1 : R_MOVL1; |
| 1409 | fix_new_exp (frag_now, offset, 4, &operand->exp, 0, idx); |
| 1410 | } |
| 1411 | break; |
| 1412 | } |
| 1413 | } |
| 1414 | else |
| 1415 | { |
| 1416 | switch (operand->mode & SIZE) |
| 1417 | { |
| 1418 | case L_24: |
| 1419 | case L_32: |
| 1420 | size = 4; |
| 1421 | where = (operand->mode & SIZE) == L_24 ? -1 : 0; |
| 1422 | #ifdef OBJ_ELF |
| 1423 | if ((operand->mode & MODE) == DISP && relaxmode == 1) |
| 1424 | idx = BFD_RELOC_H8_DISP32A16; |
| 1425 | else |
| 1426 | #endif |
| 1427 | if (relaxmode == 2) |
| 1428 | idx = R_MOV24B1; |
| 1429 | else if (relaxmode == 1) |
| 1430 | idx = R_MOVL1; |
| 1431 | else |
| 1432 | idx = R_RELLONG; |
| 1433 | break; |
| 1434 | default: |
| 1435 | as_bad (_("Can't work out size of operand.\n")); |
| 1436 | case L_16: |
| 1437 | case L_16U: |
| 1438 | size = 2; |
| 1439 | where = 0; |
| 1440 | if (relaxmode == 2) |
| 1441 | idx = R_MOV16B1; |
| 1442 | else |
| 1443 | idx = R_RELWORD; |
| 1444 | operand->exp.X_add_number = |
| 1445 | ((operand->exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
| 1446 | operand->exp.X_add_number |= (bytes[0] << 8) | bytes[1]; |
| 1447 | break; |
| 1448 | case L_8: |
| 1449 | size = 1; |
| 1450 | where = 0; |
| 1451 | idx = R_RELBYTE; |
| 1452 | operand->exp.X_add_number = |
| 1453 | ((operand->exp.X_add_number & 0xff) ^ 0x80) - 0x80; |
| 1454 | operand->exp.X_add_number |= bytes[0]; |
| 1455 | } |
| 1456 | |
| 1457 | fix_new_exp (frag_now, |
| 1458 | offset + where, |
| 1459 | size, |
| 1460 | &operand->exp, |
| 1461 | 0, |
| 1462 | idx); |
| 1463 | } |
| 1464 | } |
| 1465 | |
| 1466 | /* Now we know what sort of opcodes it is, let's build the bytes. */ |
| 1467 | |
| 1468 | static void |
| 1469 | build_bytes (const struct h8_instruction *this_try, struct h8_op *operand) |
| 1470 | { |
| 1471 | int i; |
| 1472 | char *output = frag_more (this_try->length); |
| 1473 | const op_type *nibble_ptr = this_try->opcode->data.nib; |
| 1474 | op_type c; |
| 1475 | unsigned int nibble_count = 0; |
| 1476 | int op_at[3]; |
| 1477 | int nib = 0; |
| 1478 | int movb = 0; |
| 1479 | char asnibbles[100]; |
| 1480 | char *p = asnibbles; |
| 1481 | int high, low; |
| 1482 | |
| 1483 | if (!Hmode && this_try->opcode->available != AV_H8) |
| 1484 | as_warn (_("Opcode `%s' with these operand types not available in H8/300 mode"), |
| 1485 | this_try->opcode->name); |
| 1486 | else if (!Smode |
| 1487 | && this_try->opcode->available != AV_H8 |
| 1488 | && this_try->opcode->available != AV_H8H) |
| 1489 | as_warn (_("Opcode `%s' with these operand types not available in H8/300H mode"), |
| 1490 | this_try->opcode->name); |
| 1491 | else if (!SXmode |
| 1492 | && this_try->opcode->available != AV_H8 |
| 1493 | && this_try->opcode->available != AV_H8H |
| 1494 | && this_try->opcode->available != AV_H8S) |
| 1495 | as_warn (_("Opcode `%s' with these operand types not available in H8/300S mode"), |
| 1496 | this_try->opcode->name); |
| 1497 | |
| 1498 | while (*nibble_ptr != (op_type) E) |
| 1499 | { |
| 1500 | int d; |
| 1501 | |
| 1502 | nib = 0; |
| 1503 | c = *nibble_ptr++; |
| 1504 | |
| 1505 | d = (c & OP3) == OP3 ? 2 : (c & DST) == DST ? 1 : 0; |
| 1506 | |
| 1507 | if (c < 16) |
| 1508 | nib = c; |
| 1509 | else |
| 1510 | { |
| 1511 | int c2 = c & MODE; |
| 1512 | |
| 1513 | if (c2 == REG || c2 == LOWREG |
| 1514 | || c2 == IND || c2 == PREINC || c2 == PREDEC |
| 1515 | || c2 == POSTINC || c2 == POSTDEC) |
| 1516 | { |
| 1517 | nib = operand[d].reg; |
| 1518 | if (c2 == LOWREG) |
| 1519 | nib &= 7; |
| 1520 | } |
| 1521 | |
| 1522 | else if (c & CTRL) /* Control reg operand. */ |
| 1523 | nib = operand[d].reg; |
| 1524 | |
| 1525 | else if ((c & DISPREG) == (DISPREG)) |
| 1526 | { |
| 1527 | nib = operand[d].reg; |
| 1528 | } |
| 1529 | else if (c2 == ABS) |
| 1530 | { |
| 1531 | operand[d].mode = c; |
| 1532 | op_at[d] = nibble_count; |
| 1533 | nib = 0; |
| 1534 | } |
| 1535 | else if (c2 == IMM || c2 == PCREL || c2 == ABS |
| 1536 | || (c & ABSJMP) || c2 == DISP) |
| 1537 | { |
| 1538 | operand[d].mode = c; |
| 1539 | op_at[d] = nibble_count; |
| 1540 | nib = 0; |
| 1541 | } |
| 1542 | else if ((c & IGNORE) || (c & DATA)) |
| 1543 | nib = 0; |
| 1544 | |
| 1545 | else if (c2 == DBIT) |
| 1546 | { |
| 1547 | switch (operand[0].exp.X_add_number) |
| 1548 | { |
| 1549 | case 1: |
| 1550 | nib = c; |
| 1551 | break; |
| 1552 | case 2: |
| 1553 | nib = 0x8 | c; |
| 1554 | break; |
| 1555 | default: |
| 1556 | as_bad (_("Need #1 or #2 here")); |
| 1557 | } |
| 1558 | } |
| 1559 | else if (c2 == KBIT) |
| 1560 | { |
| 1561 | switch (operand[0].exp.X_add_number) |
| 1562 | { |
| 1563 | case 1: |
| 1564 | nib = 0; |
| 1565 | break; |
| 1566 | case 2: |
| 1567 | nib = 8; |
| 1568 | break; |
| 1569 | case 4: |
| 1570 | if (!Hmode) |
| 1571 | as_warn (_("#4 not valid on H8/300.")); |
| 1572 | nib = 9; |
| 1573 | break; |
| 1574 | |
| 1575 | default: |
| 1576 | as_bad (_("Need #1 or #2 here")); |
| 1577 | break; |
| 1578 | } |
| 1579 | /* Stop it making a fix. */ |
| 1580 | operand[0].mode = 0; |
| 1581 | } |
| 1582 | |
| 1583 | if (c & MEMRELAX) |
| 1584 | operand[d].mode |= MEMRELAX; |
| 1585 | |
| 1586 | if (c & B31) |
| 1587 | nib |= 0x8; |
| 1588 | |
| 1589 | if (c & B21) |
| 1590 | nib |= 0x4; |
| 1591 | |
| 1592 | if (c & B11) |
| 1593 | nib |= 0x2; |
| 1594 | |
| 1595 | if (c & B01) |
| 1596 | nib |= 0x1; |
| 1597 | |
| 1598 | if (c2 == MACREG) |
| 1599 | { |
| 1600 | if (operand[0].mode == MACREG) |
| 1601 | /* stmac has mac[hl] as the first operand. */ |
| 1602 | nib = 2 + operand[0].reg; |
| 1603 | else |
| 1604 | /* ldmac has mac[hl] as the second operand. */ |
| 1605 | nib = 2 + operand[1].reg; |
| 1606 | } |
| 1607 | } |
| 1608 | nibble_count++; |
| 1609 | |
| 1610 | *p++ = nib; |
| 1611 | } |
| 1612 | |
| 1613 | /* Disgusting. Why, oh why didn't someone ask us for advice |
| 1614 | on the assembler format. */ |
| 1615 | if (OP_KIND (this_try->opcode->how) == O_LDM) |
| 1616 | { |
| 1617 | high = (operand[1].reg >> 8) & 0xf; |
| 1618 | low = (operand[1].reg) & 0xf; |
| 1619 | asnibbles[2] = high - low; |
| 1620 | asnibbles[7] = high; |
| 1621 | } |
| 1622 | else if (OP_KIND (this_try->opcode->how) == O_STM) |
| 1623 | { |
| 1624 | high = (operand[0].reg >> 8) & 0xf; |
| 1625 | low = (operand[0].reg) & 0xf; |
| 1626 | asnibbles[2] = high - low; |
| 1627 | asnibbles[7] = low; |
| 1628 | } |
| 1629 | |
| 1630 | for (i = 0; i < this_try->length; i++) |
| 1631 | output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1]; |
| 1632 | |
| 1633 | /* Note if this is a mov.b or a bit manipulation instruction |
| 1634 | there is a special relaxation which only applies. */ |
| 1635 | if ( this_try->opcode->how == O (O_MOV, SB) |
| 1636 | || this_try->opcode->how == O (O_BCLR, SB) |
| 1637 | || this_try->opcode->how == O (O_BAND, SB) |
| 1638 | || this_try->opcode->how == O (O_BIAND, SB) |
| 1639 | || this_try->opcode->how == O (O_BILD, SB) |
| 1640 | || this_try->opcode->how == O (O_BIOR, SB) |
| 1641 | || this_try->opcode->how == O (O_BIST, SB) |
| 1642 | || this_try->opcode->how == O (O_BIXOR, SB) |
| 1643 | || this_try->opcode->how == O (O_BLD, SB) |
| 1644 | || this_try->opcode->how == O (O_BNOT, SB) |
| 1645 | || this_try->opcode->how == O (O_BOR, SB) |
| 1646 | || this_try->opcode->how == O (O_BSET, SB) |
| 1647 | || this_try->opcode->how == O (O_BST, SB) |
| 1648 | || this_try->opcode->how == O (O_BTST, SB) |
| 1649 | || this_try->opcode->how == O (O_BXOR, SB)) |
| 1650 | movb = 1; |
| 1651 | |
| 1652 | /* Output any fixes. */ |
| 1653 | for (i = 0; i < this_try->noperands; i++) |
| 1654 | { |
| 1655 | int x = operand[i].mode; |
| 1656 | int x_mode = x & MODE; |
| 1657 | |
| 1658 | if (x_mode == IMM || x_mode == DISP) |
| 1659 | { |
| 1660 | #ifndef OBJ_ELF |
| 1661 | /* Remove MEMRELAX flag added in h8300.h on mov with |
| 1662 | addressing mode "register indirect with displacement". */ |
| 1663 | if (x_mode == DISP) |
| 1664 | x &= ~MEMRELAX; |
| 1665 | #endif |
| 1666 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, |
| 1667 | op_at[i] & 1, operand + i, (x & MEMRELAX) != 0, |
| 1668 | this_try); |
| 1669 | } |
| 1670 | else if (x_mode == ABS) |
| 1671 | do_a_fix_imm (output - frag_now->fr_literal + op_at[i] / 2, |
| 1672 | op_at[i] & 1, operand + i, |
| 1673 | (x & MEMRELAX) ? movb + 1 : 0, |
| 1674 | this_try); |
| 1675 | |
| 1676 | else if (x_mode == PCREL) |
| 1677 | { |
| 1678 | int size16 = (x & SIZE) == L_16; |
| 1679 | int size = size16 ? 2 : 1; |
| 1680 | int type = size16 ? R_PCRWORD : R_PCRBYTE; |
| 1681 | fixS *fixP; |
| 1682 | |
| 1683 | check_operand (operand + i, size16 ? 0x7fff : 0x7f, "@"); |
| 1684 | |
| 1685 | if (operand[i].exp.X_add_number & 1) |
| 1686 | as_warn (_("branch operand has odd offset (%lx)\n"), |
| 1687 | (unsigned long) operand->exp.X_add_number); |
| 1688 | #ifndef OBJ_ELF |
| 1689 | /* The COFF port has always been off by one, changing it |
| 1690 | now would be an incompatible change, so we leave it as-is. |
| 1691 | |
| 1692 | We don't want to do this for ELF as we want to be |
| 1693 | compatible with the proposed ELF format from Hitachi. */ |
| 1694 | operand[i].exp.X_add_number -= 1; |
| 1695 | #endif |
| 1696 | if (size16) |
| 1697 | { |
| 1698 | operand[i].exp.X_add_number = |
| 1699 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
| 1700 | } |
| 1701 | else |
| 1702 | { |
| 1703 | operand[i].exp.X_add_number = |
| 1704 | ((operand[i].exp.X_add_number & 0xff) ^ 0x80) - 0x80; |
| 1705 | } |
| 1706 | |
| 1707 | /* For BRA/S. */ |
| 1708 | if (! size16) |
| 1709 | operand[i].exp.X_add_number |= output[op_at[i] / 2]; |
| 1710 | |
| 1711 | fixP = fix_new_exp (frag_now, |
| 1712 | output - frag_now->fr_literal + op_at[i] / 2, |
| 1713 | size, |
| 1714 | &operand[i].exp, |
| 1715 | 1, |
| 1716 | type); |
| 1717 | fixP->fx_signed = 1; |
| 1718 | } |
| 1719 | else if (x_mode == MEMIND) |
| 1720 | { |
| 1721 | check_operand (operand + i, 0xff, "@@"); |
| 1722 | fix_new_exp (frag_now, |
| 1723 | output - frag_now->fr_literal + 1, |
| 1724 | 1, |
| 1725 | &operand[i].exp, |
| 1726 | 0, |
| 1727 | R_MEM_INDIRECT); |
| 1728 | } |
| 1729 | else if (x_mode == VECIND) |
| 1730 | { |
| 1731 | check_operand (operand + i, 0x7f, "@@"); |
| 1732 | /* FIXME: approximating the effect of "B31" here... |
| 1733 | This is very hackish, and ought to be done a better way. */ |
| 1734 | operand[i].exp.X_add_number |= 0x80; |
| 1735 | fix_new_exp (frag_now, |
| 1736 | output - frag_now->fr_literal + 1, |
| 1737 | 1, |
| 1738 | &operand[i].exp, |
| 1739 | 0, |
| 1740 | R_MEM_INDIRECT); |
| 1741 | } |
| 1742 | else if (x & ABSJMP) |
| 1743 | { |
| 1744 | int where = 0; |
| 1745 | bfd_reloc_code_real_type reloc_type = R_JMPL1; |
| 1746 | |
| 1747 | #ifdef OBJ_ELF |
| 1748 | /* To be compatible with the proposed H8 ELF format, we |
| 1749 | want the relocation's offset to point to the first byte |
| 1750 | that will be modified, not to the start of the instruction. */ |
| 1751 | |
| 1752 | if ((operand->mode & SIZE) == L_32) |
| 1753 | { |
| 1754 | where = 2; |
| 1755 | reloc_type = R_RELLONG; |
| 1756 | } |
| 1757 | else |
| 1758 | where = 1; |
| 1759 | #endif |
| 1760 | |
| 1761 | /* This jmp may be a jump or a branch. */ |
| 1762 | |
| 1763 | check_operand (operand + i, |
| 1764 | SXmode ? 0xffffffff : Hmode ? 0xffffff : 0xffff, |
| 1765 | "@"); |
| 1766 | |
| 1767 | if (operand[i].exp.X_add_number & 1) |
| 1768 | as_warn (_("branch operand has odd offset (%lx)\n"), |
| 1769 | (unsigned long) operand->exp.X_add_number); |
| 1770 | |
| 1771 | if (!Hmode) |
| 1772 | operand[i].exp.X_add_number = |
| 1773 | ((operand[i].exp.X_add_number & 0xffff) ^ 0x8000) - 0x8000; |
| 1774 | fix_new_exp (frag_now, |
| 1775 | output - frag_now->fr_literal + where, |
| 1776 | 4, |
| 1777 | &operand[i].exp, |
| 1778 | 0, |
| 1779 | reloc_type); |
| 1780 | } |
| 1781 | } |
| 1782 | } |
| 1783 | |
| 1784 | /* Try to give an intelligent error message for common and simple to |
| 1785 | detect errors. */ |
| 1786 | |
| 1787 | static void |
| 1788 | clever_message (const struct h8_instruction *instruction, |
| 1789 | struct h8_op *operand) |
| 1790 | { |
| 1791 | /* Find out if there was more than one possible opcode. */ |
| 1792 | |
| 1793 | if ((instruction + 1)->idx != instruction->idx) |
| 1794 | { |
| 1795 | int argn; |
| 1796 | |
| 1797 | /* Only one opcode of this flavour, try to guess which operand |
| 1798 | didn't match. */ |
| 1799 | for (argn = 0; argn < instruction->noperands; argn++) |
| 1800 | { |
| 1801 | switch (instruction->opcode->args.nib[argn]) |
| 1802 | { |
| 1803 | case RD16: |
| 1804 | if (operand[argn].mode != RD16) |
| 1805 | { |
| 1806 | as_bad (_("destination operand must be 16 bit register")); |
| 1807 | return; |
| 1808 | |
| 1809 | } |
| 1810 | break; |
| 1811 | |
| 1812 | case RS8: |
| 1813 | if (operand[argn].mode != RS8) |
| 1814 | { |
| 1815 | as_bad (_("source operand must be 8 bit register")); |
| 1816 | return; |
| 1817 | } |
| 1818 | break; |
| 1819 | |
| 1820 | case ABS16DST: |
| 1821 | if (operand[argn].mode != ABS16DST) |
| 1822 | { |
| 1823 | as_bad (_("destination operand must be 16bit absolute address")); |
| 1824 | return; |
| 1825 | } |
| 1826 | break; |
| 1827 | case RD8: |
| 1828 | if (operand[argn].mode != RD8) |
| 1829 | { |
| 1830 | as_bad (_("destination operand must be 8 bit register")); |
| 1831 | return; |
| 1832 | } |
| 1833 | break; |
| 1834 | |
| 1835 | case ABS16SRC: |
| 1836 | if (operand[argn].mode != ABS16SRC) |
| 1837 | { |
| 1838 | as_bad (_("source operand must be 16bit absolute address")); |
| 1839 | return; |
| 1840 | } |
| 1841 | break; |
| 1842 | |
| 1843 | } |
| 1844 | } |
| 1845 | } |
| 1846 | as_bad (_("invalid operands")); |
| 1847 | } |
| 1848 | |
| 1849 | |
| 1850 | /* If OPERAND is part of an address, adjust its size and value given |
| 1851 | that it addresses SIZE bytes. |
| 1852 | |
| 1853 | This function decides how big non-immediate constants are when no |
| 1854 | size was explicitly given. It also scales down the assembly-level |
| 1855 | displacement in an @(d:2,ERn) operand. */ |
| 1856 | |
| 1857 | static void |
| 1858 | fix_operand_size (struct h8_op *operand, int size) |
| 1859 | { |
| 1860 | if (SXmode && (operand->mode & MODE) == DISP) |
| 1861 | { |
| 1862 | /* If the user didn't specify an operand width, see if we |
| 1863 | can use @(d:2,ERn). */ |
| 1864 | if ((operand->mode & SIZE) == 0 |
| 1865 | && operand->exp.X_add_symbol == 0 |
| 1866 | && operand->exp.X_op_symbol == 0 |
| 1867 | && (operand->exp.X_add_number == size |
| 1868 | || operand->exp.X_add_number == size * 2 |
| 1869 | || operand->exp.X_add_number == size * 3)) |
| 1870 | operand->mode |= L_2; |
| 1871 | |
| 1872 | /* Scale down the displacement in an @(d:2,ERn) operand. |
| 1873 | X_add_number then contains the desired field value. */ |
| 1874 | if ((operand->mode & SIZE) == L_2) |
| 1875 | { |
| 1876 | if (operand->exp.X_add_number % size != 0) |
| 1877 | as_warn (_("operand/size mis-match")); |
| 1878 | operand->exp.X_add_number /= size; |
| 1879 | } |
| 1880 | } |
| 1881 | |
| 1882 | if ((operand->mode & SIZE) == 0) |
| 1883 | switch (operand->mode & MODE) |
| 1884 | { |
| 1885 | case DISP: |
| 1886 | case INDEXB: |
| 1887 | case INDEXW: |
| 1888 | case INDEXL: |
| 1889 | case ABS: |
| 1890 | /* Pick a 24-bit address unless we know that a 16-bit address |
| 1891 | is safe. get_specific() will relax L_24 into L_32 where |
| 1892 | necessary. */ |
| 1893 | if (Hmode |
| 1894 | && !Nmode |
| 1895 | && ((((addressT) operand->exp.X_add_number + 0x8000) |
| 1896 | & 0xffffffff) > 0xffff |
| 1897 | || operand->exp.X_add_symbol != 0 |
| 1898 | || operand->exp.X_op_symbol != 0)) |
| 1899 | operand->mode |= L_24; |
| 1900 | else |
| 1901 | operand->mode |= L_16; |
| 1902 | break; |
| 1903 | |
| 1904 | case PCREL: |
| 1905 | if ((((addressT) operand->exp.X_add_number + 0x80) |
| 1906 | & 0xffffffff) <= 0xff) |
| 1907 | { |
| 1908 | if (operand->exp.X_add_symbol != NULL) |
| 1909 | operand->mode |= bsize; |
| 1910 | else |
| 1911 | operand->mode |= L_8; |
| 1912 | } |
| 1913 | else |
| 1914 | operand->mode |= L_16; |
| 1915 | break; |
| 1916 | } |
| 1917 | } |
| 1918 | |
| 1919 | |
| 1920 | /* This is the guts of the machine-dependent assembler. STR points to |
| 1921 | a machine dependent instruction. This function is supposed to emit |
| 1922 | the frags/bytes it assembles. */ |
| 1923 | |
| 1924 | void |
| 1925 | md_assemble (char *str) |
| 1926 | { |
| 1927 | char *op_start; |
| 1928 | char *op_end; |
| 1929 | struct h8_op operand[3]; |
| 1930 | const struct h8_instruction *instruction; |
| 1931 | const struct h8_instruction *prev_instruction; |
| 1932 | |
| 1933 | char *dot = 0; |
| 1934 | char *slash = 0; |
| 1935 | char c; |
| 1936 | int size, i; |
| 1937 | |
| 1938 | /* Drop leading whitespace. */ |
| 1939 | while (*str == ' ') |
| 1940 | str++; |
| 1941 | |
| 1942 | /* Find the op code end. */ |
| 1943 | for (op_start = op_end = str; |
| 1944 | *op_end != 0 && *op_end != ' '; |
| 1945 | op_end++) |
| 1946 | { |
| 1947 | if (*op_end == '.') |
| 1948 | { |
| 1949 | dot = op_end + 1; |
| 1950 | *op_end = 0; |
| 1951 | op_end += 2; |
| 1952 | break; |
| 1953 | } |
| 1954 | else if (*op_end == '/' && ! slash) |
| 1955 | slash = op_end; |
| 1956 | } |
| 1957 | |
| 1958 | if (op_end == op_start) |
| 1959 | { |
| 1960 | as_bad (_("can't find opcode ")); |
| 1961 | } |
| 1962 | c = *op_end; |
| 1963 | |
| 1964 | *op_end = 0; |
| 1965 | |
| 1966 | /* The assembler stops scanning the opcode at slashes, so it fails |
| 1967 | to make characters following them lower case. Fix them. */ |
| 1968 | if (slash) |
| 1969 | while (*++slash) |
| 1970 | *slash = TOLOWER (*slash); |
| 1971 | |
| 1972 | instruction = (const struct h8_instruction *) |
| 1973 | hash_find (opcode_hash_control, op_start); |
| 1974 | |
| 1975 | if (instruction == NULL) |
| 1976 | { |
| 1977 | as_bad (_("unknown opcode")); |
| 1978 | return; |
| 1979 | } |
| 1980 | |
| 1981 | /* We used to set input_line_pointer to the result of get_operands, |
| 1982 | but that is wrong. Our caller assumes we don't change it. */ |
| 1983 | |
| 1984 | operand[0].mode = 0; |
| 1985 | operand[1].mode = 0; |
| 1986 | operand[2].mode = 0; |
| 1987 | |
| 1988 | if (OP_KIND (instruction->opcode->how) == O_MOVAB |
| 1989 | || OP_KIND (instruction->opcode->how) == O_MOVAW |
| 1990 | || OP_KIND (instruction->opcode->how) == O_MOVAL) |
| 1991 | get_mova_operands (op_end, operand); |
| 1992 | else if (OP_KIND (instruction->opcode->how) == O_RTEL |
| 1993 | || OP_KIND (instruction->opcode->how) == O_RTSL) |
| 1994 | get_rtsl_operands (op_end, operand); |
| 1995 | else |
| 1996 | get_operands (instruction->noperands, op_end, operand); |
| 1997 | |
| 1998 | *op_end = c; |
| 1999 | prev_instruction = instruction; |
| 2000 | |
| 2001 | /* Now we have operands from instruction. |
| 2002 | Let's check them out for ldm and stm. */ |
| 2003 | if (OP_KIND (instruction->opcode->how) == O_LDM) |
| 2004 | { |
| 2005 | /* The first operand must be @er7+, and the |
| 2006 | second operand must be a register pair. */ |
| 2007 | if ((operand[0].mode != RSINC) |
| 2008 | || (operand[0].reg != 7) |
| 2009 | || ((operand[1].reg & 0x80000000) == 0)) |
| 2010 | as_bad (_("invalid operand in ldm")); |
| 2011 | } |
| 2012 | else if (OP_KIND (instruction->opcode->how) == O_STM) |
| 2013 | { |
| 2014 | /* The first operand must be a register pair, |
| 2015 | and the second operand must be @-er7. */ |
| 2016 | if (((operand[0].reg & 0x80000000) == 0) |
| 2017 | || (operand[1].mode != RDDEC) |
| 2018 | || (operand[1].reg != 7)) |
| 2019 | as_bad (_("invalid operand in stm")); |
| 2020 | } |
| 2021 | |
| 2022 | size = SN; |
| 2023 | if (dot) |
| 2024 | { |
| 2025 | switch (TOLOWER (*dot)) |
| 2026 | { |
| 2027 | case 'b': |
| 2028 | size = SB; |
| 2029 | break; |
| 2030 | |
| 2031 | case 'w': |
| 2032 | size = SW; |
| 2033 | break; |
| 2034 | |
| 2035 | case 'l': |
| 2036 | size = SL; |
| 2037 | break; |
| 2038 | } |
| 2039 | } |
| 2040 | if (OP_KIND (instruction->opcode->how) == O_MOVAB || |
| 2041 | OP_KIND (instruction->opcode->how) == O_MOVAW || |
| 2042 | OP_KIND (instruction->opcode->how) == O_MOVAL) |
| 2043 | { |
| 2044 | switch (operand[0].mode & MODE) |
| 2045 | { |
| 2046 | case INDEXB: |
| 2047 | default: |
| 2048 | fix_operand_size (&operand[1], 1); |
| 2049 | break; |
| 2050 | case INDEXW: |
| 2051 | fix_operand_size (&operand[1], 2); |
| 2052 | break; |
| 2053 | case INDEXL: |
| 2054 | fix_operand_size (&operand[1], 4); |
| 2055 | break; |
| 2056 | } |
| 2057 | } |
| 2058 | else |
| 2059 | { |
| 2060 | for (i = 0; i < 3 && operand[i].mode != 0; i++) |
| 2061 | switch (size) |
| 2062 | { |
| 2063 | case SN: |
| 2064 | case SB: |
| 2065 | default: |
| 2066 | fix_operand_size (&operand[i], 1); |
| 2067 | break; |
| 2068 | case SW: |
| 2069 | fix_operand_size (&operand[i], 2); |
| 2070 | break; |
| 2071 | case SL: |
| 2072 | fix_operand_size (&operand[i], 4); |
| 2073 | break; |
| 2074 | } |
| 2075 | } |
| 2076 | |
| 2077 | instruction = get_specific (instruction, operand, size); |
| 2078 | |
| 2079 | if (instruction == 0) |
| 2080 | { |
| 2081 | /* Couldn't find an opcode which matched the operands. */ |
| 2082 | char *where = frag_more (2); |
| 2083 | |
| 2084 | where[0] = 0x0; |
| 2085 | where[1] = 0x0; |
| 2086 | clever_message (prev_instruction, operand); |
| 2087 | |
| 2088 | return; |
| 2089 | } |
| 2090 | |
| 2091 | build_bytes (instruction, operand); |
| 2092 | |
| 2093 | dwarf2_emit_insn (instruction->length); |
| 2094 | } |
| 2095 | |
| 2096 | symbolS * |
| 2097 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
| 2098 | { |
| 2099 | return 0; |
| 2100 | } |
| 2101 | |
| 2102 | /* Various routines to kill one day. */ |
| 2103 | |
| 2104 | char * |
| 2105 | md_atof (int type, char *litP, int *sizeP) |
| 2106 | { |
| 2107 | return ieee_md_atof (type, litP, sizeP, TRUE); |
| 2108 | } |
| 2109 | \f |
| 2110 | #define OPTION_H_TICK_HEX (OPTION_MD_BASE) |
| 2111 | #define OPTION_MACH (OPTION_MD_BASE+1) |
| 2112 | |
| 2113 | const char *md_shortopts = ""; |
| 2114 | struct option md_longopts[] = |
| 2115 | { |
| 2116 | { "h-tick-hex", no_argument, NULL, OPTION_H_TICK_HEX }, |
| 2117 | { "mach", required_argument, NULL, OPTION_MACH }, |
| 2118 | {NULL, no_argument, NULL, 0} |
| 2119 | }; |
| 2120 | |
| 2121 | size_t md_longopts_size = sizeof (md_longopts); |
| 2122 | |
| 2123 | struct mach_func |
| 2124 | { |
| 2125 | const char *name; |
| 2126 | void (*func) (void); |
| 2127 | }; |
| 2128 | |
| 2129 | static void |
| 2130 | mach_h8300h (void) |
| 2131 | { |
| 2132 | Hmode = 1; |
| 2133 | Smode = 0; |
| 2134 | Nmode = 0; |
| 2135 | SXmode = 0; |
| 2136 | default_mach = bfd_mach_h8300h; |
| 2137 | } |
| 2138 | |
| 2139 | static void |
| 2140 | mach_h8300hn (void) |
| 2141 | { |
| 2142 | Hmode = 1; |
| 2143 | Smode = 0; |
| 2144 | Nmode = 1; |
| 2145 | SXmode = 0; |
| 2146 | default_mach = bfd_mach_h8300hn; |
| 2147 | } |
| 2148 | |
| 2149 | static void |
| 2150 | mach_h8300s (void) |
| 2151 | { |
| 2152 | Hmode = 1; |
| 2153 | Smode = 1; |
| 2154 | Nmode = 0; |
| 2155 | SXmode = 0; |
| 2156 | default_mach = bfd_mach_h8300s; |
| 2157 | } |
| 2158 | |
| 2159 | static void |
| 2160 | mach_h8300sn (void) |
| 2161 | { |
| 2162 | Hmode = 1; |
| 2163 | Smode = 1; |
| 2164 | Nmode = 1; |
| 2165 | SXmode = 0; |
| 2166 | default_mach = bfd_mach_h8300sn; |
| 2167 | } |
| 2168 | |
| 2169 | static void |
| 2170 | mach_h8300sx (void) |
| 2171 | { |
| 2172 | Hmode = 1; |
| 2173 | Smode = 1; |
| 2174 | Nmode = 0; |
| 2175 | SXmode = 1; |
| 2176 | default_mach = bfd_mach_h8300sx; |
| 2177 | } |
| 2178 | |
| 2179 | static void |
| 2180 | mach_h8300sxn (void) |
| 2181 | { |
| 2182 | Hmode = 1; |
| 2183 | Smode = 1; |
| 2184 | Nmode = 1; |
| 2185 | SXmode = 1; |
| 2186 | default_mach = bfd_mach_h8300sxn; |
| 2187 | } |
| 2188 | |
| 2189 | const struct mach_func mach_table[] = |
| 2190 | { |
| 2191 | {"h8300h", mach_h8300h}, |
| 2192 | {"h8300hn", mach_h8300hn}, |
| 2193 | {"h8300s", mach_h8300s}, |
| 2194 | {"h8300sn", mach_h8300sn}, |
| 2195 | {"h8300sx", mach_h8300sx}, |
| 2196 | {"h8300sxn", mach_h8300sxn} |
| 2197 | }; |
| 2198 | |
| 2199 | int |
| 2200 | md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) |
| 2201 | { |
| 2202 | unsigned int i; |
| 2203 | switch (c) |
| 2204 | { |
| 2205 | case OPTION_H_TICK_HEX: |
| 2206 | enable_h_tick_hex = 1; |
| 2207 | break; |
| 2208 | case OPTION_MACH: |
| 2209 | for (i = 0; i < sizeof(mach_table) / sizeof(struct mach_func); i++) |
| 2210 | { |
| 2211 | if (strcasecmp (arg, mach_table[i].name) == 0) |
| 2212 | { |
| 2213 | mach_table[i].func(); |
| 2214 | break; |
| 2215 | } |
| 2216 | } |
| 2217 | if (i >= sizeof(mach_table) / sizeof(struct mach_func)) |
| 2218 | as_bad (_("Invalid argument to --mach option: %s"), arg); |
| 2219 | break; |
| 2220 | default: |
| 2221 | return 0; |
| 2222 | } |
| 2223 | return 1; |
| 2224 | } |
| 2225 | |
| 2226 | void |
| 2227 | md_show_usage (FILE *stream) |
| 2228 | { |
| 2229 | fprintf (stream, _(" H8300-specific assembler options:\n")); |
| 2230 | fprintf (stream, _("\ |
| 2231 | -mach=<name> Set the H8300 machine type to one of:\n\ |
| 2232 | h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn\n")); |
| 2233 | fprintf (stream, _("\ |
| 2234 | -h-tick-hex Support H'00 style hex constants\n")); |
| 2235 | } |
| 2236 | \f |
| 2237 | void tc_aout_fix_to_chars (void); |
| 2238 | |
| 2239 | void |
| 2240 | tc_aout_fix_to_chars (void) |
| 2241 | { |
| 2242 | printf (_("call to tc_aout_fix_to_chars \n")); |
| 2243 | abort (); |
| 2244 | } |
| 2245 | |
| 2246 | void |
| 2247 | md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, |
| 2248 | segT seg ATTRIBUTE_UNUSED, |
| 2249 | fragS *fragP ATTRIBUTE_UNUSED) |
| 2250 | { |
| 2251 | printf (_("call to md_convert_frag \n")); |
| 2252 | abort (); |
| 2253 | } |
| 2254 | |
| 2255 | valueT |
| 2256 | md_section_align (segT segment, valueT size) |
| 2257 | { |
| 2258 | int align = bfd_get_section_alignment (stdoutput, segment); |
| 2259 | return ((size + (1 << align) - 1) & (-1U << align)); |
| 2260 | } |
| 2261 | |
| 2262 | void |
| 2263 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
| 2264 | { |
| 2265 | char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; |
| 2266 | long val = *valP; |
| 2267 | |
| 2268 | switch (fixP->fx_size) |
| 2269 | { |
| 2270 | case 1: |
| 2271 | *buf++ = val; |
| 2272 | break; |
| 2273 | case 2: |
| 2274 | *buf++ = (val >> 8); |
| 2275 | *buf++ = val; |
| 2276 | break; |
| 2277 | case 4: |
| 2278 | *buf++ = (val >> 24); |
| 2279 | *buf++ = (val >> 16); |
| 2280 | *buf++ = (val >> 8); |
| 2281 | *buf++ = val; |
| 2282 | break; |
| 2283 | case 8: |
| 2284 | /* This can arise when the .quad or .8byte pseudo-ops are used. |
| 2285 | Returning here (without setting fx_done) will cause the code |
| 2286 | to attempt to generate a reloc which will then fail with the |
| 2287 | slightly more helpful error message: "Cannot represent |
| 2288 | relocation type BFD_RELOC_64". */ |
| 2289 | return; |
| 2290 | default: |
| 2291 | abort (); |
| 2292 | } |
| 2293 | |
| 2294 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) |
| 2295 | fixP->fx_done = 1; |
| 2296 | } |
| 2297 | |
| 2298 | int |
| 2299 | md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, |
| 2300 | segT segment_type ATTRIBUTE_UNUSED) |
| 2301 | { |
| 2302 | printf (_("call to md_estimate_size_before_relax \n")); |
| 2303 | abort (); |
| 2304 | } |
| 2305 | |
| 2306 | /* Put number into target byte order. */ |
| 2307 | void |
| 2308 | md_number_to_chars (char *ptr, valueT use, int nbytes) |
| 2309 | { |
| 2310 | number_to_chars_bigendian (ptr, use, nbytes); |
| 2311 | } |
| 2312 | |
| 2313 | long |
| 2314 | md_pcrel_from (fixS *fixp) |
| 2315 | { |
| 2316 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 2317 | _("Unexpected reference to a symbol in a non-code section")); |
| 2318 | return 0; |
| 2319 | } |
| 2320 | |
| 2321 | arelent * |
| 2322 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
| 2323 | { |
| 2324 | arelent *rel; |
| 2325 | bfd_reloc_code_real_type r_type; |
| 2326 | |
| 2327 | if (fixp->fx_addsy && fixp->fx_subsy) |
| 2328 | { |
| 2329 | if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy)) |
| 2330 | || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section) |
| 2331 | { |
| 2332 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 2333 | _("Difference of symbols in different sections is not supported")); |
| 2334 | return NULL; |
| 2335 | } |
| 2336 | } |
| 2337 | |
| 2338 | rel = xmalloc (sizeof (arelent)); |
| 2339 | rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
| 2340 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 2341 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 2342 | rel->addend = fixp->fx_offset; |
| 2343 | |
| 2344 | r_type = fixp->fx_r_type; |
| 2345 | |
| 2346 | #define DEBUG 0 |
| 2347 | #if DEBUG |
| 2348 | fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type)); |
| 2349 | fflush (stderr); |
| 2350 | #endif |
| 2351 | rel->howto = bfd_reloc_type_lookup (stdoutput, r_type); |
| 2352 | if (rel->howto == NULL) |
| 2353 | { |
| 2354 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 2355 | _("Cannot represent relocation type %s"), |
| 2356 | bfd_get_reloc_code_name (r_type)); |
| 2357 | return NULL; |
| 2358 | } |
| 2359 | |
| 2360 | return rel; |
| 2361 | } |