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Use macros for TUI window names
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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1/* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
27
28#include "as.h"
29#include "safe-ctype.h"
30#include "subsegs.h"
31#include "dwarf2dbg.h"
32#include "dw2gencfi.h"
33#include "elf/x86-64.h"
34#include "opcodes/i386-init.h"
35
36#ifdef HAVE_LIMITS_H
37#include <limits.h>
38#else
39#ifdef HAVE_SYS_PARAM_H
40#include <sys/param.h>
41#endif
42#ifndef INT_MAX
43#define INT_MAX (int) (((unsigned) (-1)) >> 1)
44#endif
45#endif
46
47#ifndef INFER_ADDR_PREFIX
48#define INFER_ADDR_PREFIX 1
49#endif
50
51#ifndef DEFAULT_ARCH
52#define DEFAULT_ARCH "i386"
53#endif
54
55#ifndef INLINE
56#if __GNUC__ >= 2
57#define INLINE __inline__
58#else
59#define INLINE
60#endif
61#endif
62
63/* Prefixes will be emitted in the order defined below.
64 WAIT_PREFIX must be the first prefix since FWAIT is really is an
65 instruction, and so must come before any prefixes.
66 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
68#define WAIT_PREFIX 0
69#define SEG_PREFIX 1
70#define ADDR_PREFIX 2
71#define DATA_PREFIX 3
72#define REP_PREFIX 4
73#define HLE_PREFIX REP_PREFIX
74#define BND_PREFIX REP_PREFIX
75#define LOCK_PREFIX 5
76#define REX_PREFIX 6 /* must come last. */
77#define MAX_PREFIXES 7 /* max prefixes per opcode */
78
79/* we define the syntax here (modulo base,index,scale syntax) */
80#define REGISTER_PREFIX '%'
81#define IMMEDIATE_PREFIX '$'
82#define ABSOLUTE_PREFIX '*'
83
84/* these are the instruction mnemonic suffixes in AT&T syntax or
85 memory operand size in Intel syntax. */
86#define WORD_MNEM_SUFFIX 'w'
87#define BYTE_MNEM_SUFFIX 'b'
88#define SHORT_MNEM_SUFFIX 's'
89#define LONG_MNEM_SUFFIX 'l'
90#define QWORD_MNEM_SUFFIX 'q'
91/* Intel Syntax. Use a non-ascii letter since since it never appears
92 in instructions. */
93#define LONG_DOUBLE_MNEM_SUFFIX '\1'
94
95#define END_OF_INSN '\0'
96
97/* This matches the C -> StaticRounding alias in the opcode table. */
98#define commutative staticrounding
99
100/*
101 'templates' is for grouping together 'template' structures for opcodes
102 of the same name. This is only used for storing the insns in the grand
103 ole hash table of insns.
104 The templates themselves start at START and range up to (but not including)
105 END.
106 */
107typedef struct
108{
109 const insn_template *start;
110 const insn_template *end;
111}
112templates;
113
114/* 386 operand encoding bytes: see 386 book for details of this. */
115typedef struct
116{
117 unsigned int regmem; /* codes register or memory operand */
118 unsigned int reg; /* codes register operand (or extended opcode) */
119 unsigned int mode; /* how to interpret regmem & reg */
120}
121modrm_byte;
122
123/* x86-64 extension prefix. */
124typedef int rex_byte;
125
126/* 386 opcode byte to code indirect addressing. */
127typedef struct
128{
129 unsigned base;
130 unsigned index;
131 unsigned scale;
132}
133sib_byte;
134
135/* x86 arch names, types and features */
136typedef struct
137{
138 const char *name; /* arch name */
139 unsigned int len; /* arch string length */
140 enum processor_type type; /* arch type */
141 i386_cpu_flags flags; /* cpu feature flags */
142 unsigned int skip; /* show_arch should skip this. */
143}
144arch_entry;
145
146/* Used to turn off indicated flags. */
147typedef struct
148{
149 const char *name; /* arch name */
150 unsigned int len; /* arch string length */
151 i386_cpu_flags flags; /* cpu feature flags */
152}
153noarch_entry;
154
155static void update_code_flag (int, int);
156static void set_code_flag (int);
157static void set_16bit_gcc_code_flag (int);
158static void set_intel_syntax (int);
159static void set_intel_mnemonic (int);
160static void set_allow_index_reg (int);
161static void set_check (int);
162static void set_cpu_arch (int);
163#ifdef TE_PE
164static void pe_directive_secrel (int);
165#endif
166static void signed_cons (int);
167static char *output_invalid (int c);
168static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
169 const char *);
170static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
171 const char *);
172static int i386_att_operand (char *);
173static int i386_intel_operand (char *, int);
174static int i386_intel_simplify (expressionS *);
175static int i386_intel_parse_name (const char *, expressionS *);
176static const reg_entry *parse_register (char *, char **);
177static char *parse_insn (char *, char *);
178static char *parse_operands (char *, const char *);
179static void swap_operands (void);
180static void swap_2_operands (int, int);
181static enum flag_code i386_addressing_mode (void);
182static void optimize_imm (void);
183static void optimize_disp (void);
184static const insn_template *match_template (char);
185static int check_string (void);
186static int process_suffix (void);
187static int check_byte_reg (void);
188static int check_long_reg (void);
189static int check_qword_reg (void);
190static int check_word_reg (void);
191static int finalize_imm (void);
192static int process_operands (void);
193static const seg_entry *build_modrm_byte (void);
194static void output_insn (void);
195static void output_imm (fragS *, offsetT);
196static void output_disp (fragS *, offsetT);
197#ifndef I386COFF
198static void s_bss (int);
199#endif
200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201static void handle_large_common (int small ATTRIBUTE_UNUSED);
202
203/* GNU_PROPERTY_X86_ISA_1_USED. */
204static unsigned int x86_isa_1_used;
205/* GNU_PROPERTY_X86_FEATURE_2_USED. */
206static unsigned int x86_feature_2_used;
207/* Generate x86 used ISA and feature properties. */
208static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
209#endif
210
211static const char *default_arch = DEFAULT_ARCH;
212
213/* parse_register() returns this when a register alias cannot be used. */
214static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0,
215 { Dw2Inval, Dw2Inval } };
216
217/* This struct describes rounding control and SAE in the instruction. */
218struct RC_Operation
219{
220 enum rc_type
221 {
222 rne = 0,
223 rd,
224 ru,
225 rz,
226 saeonly
227 } type;
228 int operand;
229};
230
231static struct RC_Operation rc_op;
232
233/* The struct describes masking, applied to OPERAND in the instruction.
234 MASK is a pointer to the corresponding mask register. ZEROING tells
235 whether merging or zeroing mask is used. */
236struct Mask_Operation
237{
238 const reg_entry *mask;
239 unsigned int zeroing;
240 /* The operand where this operation is associated. */
241 int operand;
242};
243
244static struct Mask_Operation mask_op;
245
246/* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 broadcast factor. */
248struct Broadcast_Operation
249{
250 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
251 int type;
252
253 /* Index of broadcasted operand. */
254 int operand;
255
256 /* Number of bytes to broadcast. */
257 int bytes;
258};
259
260static struct Broadcast_Operation broadcast_op;
261
262/* VEX prefix. */
263typedef struct
264{
265 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
266 unsigned char bytes[4];
267 unsigned int length;
268 /* Destination or source register specifier. */
269 const reg_entry *register_specifier;
270} vex_prefix;
271
272/* 'md_assemble ()' gathers together information and puts it into a
273 i386_insn. */
274
275union i386_op
276 {
277 expressionS *disps;
278 expressionS *imms;
279 const reg_entry *regs;
280 };
281
282enum i386_error
283 {
284 operand_size_mismatch,
285 operand_type_mismatch,
286 register_type_mismatch,
287 number_of_operands_mismatch,
288 invalid_instruction_suffix,
289 bad_imm4,
290 unsupported_with_intel_mnemonic,
291 unsupported_syntax,
292 unsupported,
293 invalid_vsib_address,
294 invalid_vector_register_set,
295 unsupported_vector_index_register,
296 unsupported_broadcast,
297 broadcast_needed,
298 unsupported_masking,
299 mask_not_on_destination,
300 no_default_mask,
301 unsupported_rc_sae,
302 rc_sae_operand_not_last_imm,
303 invalid_register_operand,
304 };
305
306struct _i386_insn
307 {
308 /* TM holds the template for the insn were currently assembling. */
309 insn_template tm;
310
311 /* SUFFIX holds the instruction size suffix for byte, word, dword
312 or qword, if given. */
313 char suffix;
314
315 /* OPERANDS gives the number of given operands. */
316 unsigned int operands;
317
318 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
319 of given register, displacement, memory operands and immediate
320 operands. */
321 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
322
323 /* TYPES [i] is the type (see above #defines) which tells us how to
324 use OP[i] for the corresponding operand. */
325 i386_operand_type types[MAX_OPERANDS];
326
327 /* Displacement expression, immediate expression, or register for each
328 operand. */
329 union i386_op op[MAX_OPERANDS];
330
331 /* Flags for operands. */
332 unsigned int flags[MAX_OPERANDS];
333#define Operand_PCrel 1
334#define Operand_Mem 2
335
336 /* Relocation type for operand */
337 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
338
339 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
340 the base index byte below. */
341 const reg_entry *base_reg;
342 const reg_entry *index_reg;
343 unsigned int log2_scale_factor;
344
345 /* SEG gives the seg_entries of this insn. They are zero unless
346 explicit segment overrides are given. */
347 const seg_entry *seg[2];
348
349 /* Copied first memory operand string, for re-checking. */
350 char *memop1_string;
351
352 /* PREFIX holds all the given prefix opcodes (usually null).
353 PREFIXES is the number of prefix opcodes. */
354 unsigned int prefixes;
355 unsigned char prefix[MAX_PREFIXES];
356
357 /* Register is in low 3 bits of opcode. */
358 bfd_boolean short_form;
359
360 /* The operand to a branch insn indicates an absolute branch. */
361 bfd_boolean jumpabsolute;
362
363 /* Has MMX register operands. */
364 bfd_boolean has_regmmx;
365
366 /* Has XMM register operands. */
367 bfd_boolean has_regxmm;
368
369 /* Has YMM register operands. */
370 bfd_boolean has_regymm;
371
372 /* Has ZMM register operands. */
373 bfd_boolean has_regzmm;
374
375 /* Has GOTPC or TLS relocation. */
376 bfd_boolean has_gotpc_tls_reloc;
377
378 /* RM and SIB are the modrm byte and the sib byte where the
379 addressing modes of this insn are encoded. */
380 modrm_byte rm;
381 rex_byte rex;
382 rex_byte vrex;
383 sib_byte sib;
384 vex_prefix vex;
385
386 /* Masking attributes. */
387 struct Mask_Operation *mask;
388
389 /* Rounding control and SAE attributes. */
390 struct RC_Operation *rounding;
391
392 /* Broadcasting attributes. */
393 struct Broadcast_Operation *broadcast;
394
395 /* Compressed disp8*N attribute. */
396 unsigned int memshift;
397
398 /* Prefer load or store in encoding. */
399 enum
400 {
401 dir_encoding_default = 0,
402 dir_encoding_load,
403 dir_encoding_store,
404 dir_encoding_swap
405 } dir_encoding;
406
407 /* Prefer 8bit or 32bit displacement in encoding. */
408 enum
409 {
410 disp_encoding_default = 0,
411 disp_encoding_8bit,
412 disp_encoding_32bit
413 } disp_encoding;
414
415 /* Prefer the REX byte in encoding. */
416 bfd_boolean rex_encoding;
417
418 /* Disable instruction size optimization. */
419 bfd_boolean no_optimize;
420
421 /* How to encode vector instructions. */
422 enum
423 {
424 vex_encoding_default = 0,
425 vex_encoding_vex,
426 vex_encoding_vex3,
427 vex_encoding_evex,
428 vex_encoding_error
429 } vec_encoding;
430
431 /* REP prefix. */
432 const char *rep_prefix;
433
434 /* HLE prefix. */
435 const char *hle_prefix;
436
437 /* Have BND prefix. */
438 const char *bnd_prefix;
439
440 /* Have NOTRACK prefix. */
441 const char *notrack_prefix;
442
443 /* Error message. */
444 enum i386_error error;
445 };
446
447typedef struct _i386_insn i386_insn;
448
449/* Link RC type with corresponding string, that'll be looked for in
450 asm. */
451struct RC_name
452{
453 enum rc_type type;
454 const char *name;
455 unsigned int len;
456};
457
458static const struct RC_name RC_NamesTable[] =
459{
460 { rne, STRING_COMMA_LEN ("rn-sae") },
461 { rd, STRING_COMMA_LEN ("rd-sae") },
462 { ru, STRING_COMMA_LEN ("ru-sae") },
463 { rz, STRING_COMMA_LEN ("rz-sae") },
464 { saeonly, STRING_COMMA_LEN ("sae") },
465};
466
467/* List of chars besides those in app.c:symbol_chars that can start an
468 operand. Used to prevent the scrubber eating vital white-space. */
469const char extra_symbol_chars[] = "*%-([{}"
470#ifdef LEX_AT
471 "@"
472#endif
473#ifdef LEX_QM
474 "?"
475#endif
476 ;
477
478#if (defined (TE_I386AIX) \
479 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
480 && !defined (TE_GNU) \
481 && !defined (TE_LINUX) \
482 && !defined (TE_NACL) \
483 && !defined (TE_FreeBSD) \
484 && !defined (TE_DragonFly) \
485 && !defined (TE_NetBSD)))
486/* This array holds the chars that always start a comment. If the
487 pre-processor is disabled, these aren't very useful. The option
488 --divide will remove '/' from this list. */
489const char *i386_comment_chars = "#/";
490#define SVR4_COMMENT_CHARS 1
491#define PREFIX_SEPARATOR '\\'
492
493#else
494const char *i386_comment_chars = "#";
495#define PREFIX_SEPARATOR '/'
496#endif
497
498/* This array holds the chars that only start a comment at the beginning of
499 a line. If the line seems to have the form '# 123 filename'
500 .line and .file directives will appear in the pre-processed output.
501 Note that input_file.c hand checks for '#' at the beginning of the
502 first line of the input file. This is because the compiler outputs
503 #NO_APP at the beginning of its output.
504 Also note that comments started like this one will always work if
505 '/' isn't otherwise defined. */
506const char line_comment_chars[] = "#/";
507
508const char line_separator_chars[] = ";";
509
510/* Chars that can be used to separate mant from exp in floating point
511 nums. */
512const char EXP_CHARS[] = "eE";
513
514/* Chars that mean this number is a floating point constant
515 As in 0f12.456
516 or 0d1.2345e12. */
517const char FLT_CHARS[] = "fFdDxX";
518
519/* Tables for lexical analysis. */
520static char mnemonic_chars[256];
521static char register_chars[256];
522static char operand_chars[256];
523static char identifier_chars[256];
524static char digit_chars[256];
525
526/* Lexical macros. */
527#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
528#define is_operand_char(x) (operand_chars[(unsigned char) x])
529#define is_register_char(x) (register_chars[(unsigned char) x])
530#define is_space_char(x) ((x) == ' ')
531#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
532#define is_digit_char(x) (digit_chars[(unsigned char) x])
533
534/* All non-digit non-letter characters that may occur in an operand. */
535static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
536
537/* md_assemble() always leaves the strings it's passed unaltered. To
538 effect this we maintain a stack of saved characters that we've smashed
539 with '\0's (indicating end of strings for various sub-fields of the
540 assembler instruction). */
541static char save_stack[32];
542static char *save_stack_p;
543#define END_STRING_AND_SAVE(s) \
544 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
545#define RESTORE_END_STRING(s) \
546 do { *(s) = *--save_stack_p; } while (0)
547
548/* The instruction we're assembling. */
549static i386_insn i;
550
551/* Possible templates for current insn. */
552static const templates *current_templates;
553
554/* Per instruction expressionS buffers: max displacements & immediates. */
555static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
556static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
557
558/* Current operand we are working on. */
559static int this_operand = -1;
560
561/* We support four different modes. FLAG_CODE variable is used to distinguish
562 these. */
563
564enum flag_code {
565 CODE_32BIT,
566 CODE_16BIT,
567 CODE_64BIT };
568
569static enum flag_code flag_code;
570static unsigned int object_64bit;
571static unsigned int disallow_64bit_reloc;
572static int use_rela_relocations = 0;
573/* __tls_get_addr/___tls_get_addr symbol for TLS. */
574static const char *tls_get_addr;
575
576#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
577 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
578 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
579
580/* The ELF ABI to use. */
581enum x86_elf_abi
582{
583 I386_ABI,
584 X86_64_ABI,
585 X86_64_X32_ABI
586};
587
588static enum x86_elf_abi x86_elf_abi = I386_ABI;
589#endif
590
591#if defined (TE_PE) || defined (TE_PEP)
592/* Use big object file format. */
593static int use_big_obj = 0;
594#endif
595
596#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
597/* 1 if generating code for a shared library. */
598static int shared = 0;
599#endif
600
601/* 1 for intel syntax,
602 0 if att syntax. */
603static int intel_syntax = 0;
604
605static enum x86_64_isa
606{
607 amd64 = 1, /* AMD64 ISA. */
608 intel64 /* Intel64 ISA. */
609} isa64;
610
611/* 1 for intel mnemonic,
612 0 if att mnemonic. */
613static int intel_mnemonic = !SYSV386_COMPAT;
614
615/* 1 if pseudo registers are permitted. */
616static int allow_pseudo_reg = 0;
617
618/* 1 if register prefix % not required. */
619static int allow_naked_reg = 0;
620
621/* 1 if the assembler should add BND prefix for all control-transferring
622 instructions supporting it, even if this prefix wasn't specified
623 explicitly. */
624static int add_bnd_prefix = 0;
625
626/* 1 if pseudo index register, eiz/riz, is allowed . */
627static int allow_index_reg = 0;
628
629/* 1 if the assembler should ignore LOCK prefix, even if it was
630 specified explicitly. */
631static int omit_lock_prefix = 0;
632
633/* 1 if the assembler should encode lfence, mfence, and sfence as
634 "lock addl $0, (%{re}sp)". */
635static int avoid_fence = 0;
636
637/* 1 if lfence should be inserted after every load. */
638static int lfence_after_load = 0;
639
640/* Non-zero if lfence should be inserted before indirect branch. */
641static enum lfence_before_indirect_branch_kind
642 {
643 lfence_branch_none = 0,
644 lfence_branch_register,
645 lfence_branch_memory,
646 lfence_branch_all
647 }
648lfence_before_indirect_branch;
649
650/* Non-zero if lfence should be inserted before ret. */
651static enum lfence_before_ret_kind
652 {
653 lfence_before_ret_none = 0,
654 lfence_before_ret_not,
655 lfence_before_ret_or,
656 lfence_before_ret_shl
657 }
658lfence_before_ret;
659
660/* Types of previous instruction is .byte or prefix. */
661static struct
662 {
663 segT seg;
664 const char *file;
665 const char *name;
666 unsigned int line;
667 enum last_insn_kind
668 {
669 last_insn_other = 0,
670 last_insn_directive,
671 last_insn_prefix
672 } kind;
673 } last_insn;
674
675/* 1 if the assembler should generate relax relocations. */
676
677static int generate_relax_relocations
678 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
679
680static enum check_kind
681 {
682 check_none = 0,
683 check_warning,
684 check_error
685 }
686sse_check, operand_check = check_warning;
687
688/* Non-zero if branches should be aligned within power of 2 boundary. */
689static int align_branch_power = 0;
690
691/* Types of branches to align. */
692enum align_branch_kind
693 {
694 align_branch_none = 0,
695 align_branch_jcc = 1,
696 align_branch_fused = 2,
697 align_branch_jmp = 3,
698 align_branch_call = 4,
699 align_branch_indirect = 5,
700 align_branch_ret = 6
701 };
702
703/* Type bits of branches to align. */
704enum align_branch_bit
705 {
706 align_branch_jcc_bit = 1 << align_branch_jcc,
707 align_branch_fused_bit = 1 << align_branch_fused,
708 align_branch_jmp_bit = 1 << align_branch_jmp,
709 align_branch_call_bit = 1 << align_branch_call,
710 align_branch_indirect_bit = 1 << align_branch_indirect,
711 align_branch_ret_bit = 1 << align_branch_ret
712 };
713
714static unsigned int align_branch = (align_branch_jcc_bit
715 | align_branch_fused_bit
716 | align_branch_jmp_bit);
717
718/* Types of condition jump used by macro-fusion. */
719enum mf_jcc_kind
720 {
721 mf_jcc_jo = 0, /* base opcode 0x70 */
722 mf_jcc_jc, /* base opcode 0x72 */
723 mf_jcc_je, /* base opcode 0x74 */
724 mf_jcc_jna, /* base opcode 0x76 */
725 mf_jcc_js, /* base opcode 0x78 */
726 mf_jcc_jp, /* base opcode 0x7a */
727 mf_jcc_jl, /* base opcode 0x7c */
728 mf_jcc_jle, /* base opcode 0x7e */
729 };
730
731/* Types of compare flag-modifying insntructions used by macro-fusion. */
732enum mf_cmp_kind
733 {
734 mf_cmp_test_and, /* test/cmp */
735 mf_cmp_alu_cmp, /* add/sub/cmp */
736 mf_cmp_incdec /* inc/dec */
737 };
738
739/* The maximum padding size for fused jcc. CMP like instruction can
740 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
741 prefixes. */
742#define MAX_FUSED_JCC_PADDING_SIZE 20
743
744/* The maximum number of prefixes added for an instruction. */
745static unsigned int align_branch_prefix_size = 5;
746
747/* Optimization:
748 1. Clear the REX_W bit with register operand if possible.
749 2. Above plus use 128bit vector instruction to clear the full vector
750 register.
751 */
752static int optimize = 0;
753
754/* Optimization:
755 1. Clear the REX_W bit with register operand if possible.
756 2. Above plus use 128bit vector instruction to clear the full vector
757 register.
758 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
759 "testb $imm7,%r8".
760 */
761static int optimize_for_space = 0;
762
763/* Register prefix used for error message. */
764static const char *register_prefix = "%";
765
766/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
767 leave, push, and pop instructions so that gcc has the same stack
768 frame as in 32 bit mode. */
769static char stackop_size = '\0';
770
771/* Non-zero to optimize code alignment. */
772int optimize_align_code = 1;
773
774/* Non-zero to quieten some warnings. */
775static int quiet_warnings = 0;
776
777/* CPU name. */
778static const char *cpu_arch_name = NULL;
779static char *cpu_sub_arch_name = NULL;
780
781/* CPU feature flags. */
782static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
783
784/* If we have selected a cpu we are generating instructions for. */
785static int cpu_arch_tune_set = 0;
786
787/* Cpu we are generating instructions for. */
788enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
789
790/* CPU feature flags of cpu we are generating instructions for. */
791static i386_cpu_flags cpu_arch_tune_flags;
792
793/* CPU instruction set architecture used. */
794enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
795
796/* CPU feature flags of instruction set architecture used. */
797i386_cpu_flags cpu_arch_isa_flags;
798
799/* If set, conditional jumps are not automatically promoted to handle
800 larger than a byte offset. */
801static unsigned int no_cond_jump_promotion = 0;
802
803/* Encode SSE instructions with VEX prefix. */
804static unsigned int sse2avx;
805
806/* Encode scalar AVX instructions with specific vector length. */
807static enum
808 {
809 vex128 = 0,
810 vex256
811 } avxscalar;
812
813/* Encode VEX WIG instructions with specific vex.w. */
814static enum
815 {
816 vexw0 = 0,
817 vexw1
818 } vexwig;
819
820/* Encode scalar EVEX LIG instructions with specific vector length. */
821static enum
822 {
823 evexl128 = 0,
824 evexl256,
825 evexl512
826 } evexlig;
827
828/* Encode EVEX WIG instructions with specific evex.w. */
829static enum
830 {
831 evexw0 = 0,
832 evexw1
833 } evexwig;
834
835/* Value to encode in EVEX RC bits, for SAE-only instructions. */
836static enum rc_type evexrcig = rne;
837
838/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
839static symbolS *GOT_symbol;
840
841/* The dwarf2 return column, adjusted for 32 or 64 bit. */
842unsigned int x86_dwarf2_return_column;
843
844/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
845int x86_cie_data_alignment;
846
847/* Interface to relax_segment.
848 There are 3 major relax states for 386 jump insns because the
849 different types of jumps add different sizes to frags when we're
850 figuring out what sort of jump to choose to reach a given label.
851
852 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
853 branches which are handled by md_estimate_size_before_relax() and
854 i386_generic_table_relax_frag(). */
855
856/* Types. */
857#define UNCOND_JUMP 0
858#define COND_JUMP 1
859#define COND_JUMP86 2
860#define BRANCH_PADDING 3
861#define BRANCH_PREFIX 4
862#define FUSED_JCC_PADDING 5
863
864/* Sizes. */
865#define CODE16 1
866#define SMALL 0
867#define SMALL16 (SMALL | CODE16)
868#define BIG 2
869#define BIG16 (BIG | CODE16)
870
871#ifndef INLINE
872#ifdef __GNUC__
873#define INLINE __inline__
874#else
875#define INLINE
876#endif
877#endif
878
879#define ENCODE_RELAX_STATE(type, size) \
880 ((relax_substateT) (((type) << 2) | (size)))
881#define TYPE_FROM_RELAX_STATE(s) \
882 ((s) >> 2)
883#define DISP_SIZE_FROM_RELAX_STATE(s) \
884 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
885
886/* This table is used by relax_frag to promote short jumps to long
887 ones where necessary. SMALL (short) jumps may be promoted to BIG
888 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
889 don't allow a short jump in a 32 bit code segment to be promoted to
890 a 16 bit offset jump because it's slower (requires data size
891 prefix), and doesn't work, unless the destination is in the bottom
892 64k of the code segment (The top 16 bits of eip are zeroed). */
893
894const relax_typeS md_relax_table[] =
895{
896 /* The fields are:
897 1) most positive reach of this state,
898 2) most negative reach of this state,
899 3) how many bytes this mode will have in the variable part of the frag
900 4) which index into the table to try if we can't fit into this one. */
901
902 /* UNCOND_JUMP states. */
903 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
904 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
905 /* dword jmp adds 4 bytes to frag:
906 0 extra opcode bytes, 4 displacement bytes. */
907 {0, 0, 4, 0},
908 /* word jmp adds 2 byte2 to frag:
909 0 extra opcode bytes, 2 displacement bytes. */
910 {0, 0, 2, 0},
911
912 /* COND_JUMP states. */
913 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
914 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
915 /* dword conditionals adds 5 bytes to frag:
916 1 extra opcode byte, 4 displacement bytes. */
917 {0, 0, 5, 0},
918 /* word conditionals add 3 bytes to frag:
919 1 extra opcode byte, 2 displacement bytes. */
920 {0, 0, 3, 0},
921
922 /* COND_JUMP86 states. */
923 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
924 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
925 /* dword conditionals adds 5 bytes to frag:
926 1 extra opcode byte, 4 displacement bytes. */
927 {0, 0, 5, 0},
928 /* word conditionals add 4 bytes to frag:
929 1 displacement byte and a 3 byte long branch insn. */
930 {0, 0, 4, 0}
931};
932
933static const arch_entry cpu_arch[] =
934{
935 /* Do not replace the first two entries - i386_target_format()
936 relies on them being there in this order. */
937 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
938 CPU_GENERIC32_FLAGS, 0 },
939 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
940 CPU_GENERIC64_FLAGS, 0 },
941 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
942 CPU_NONE_FLAGS, 0 },
943 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
944 CPU_I186_FLAGS, 0 },
945 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
946 CPU_I286_FLAGS, 0 },
947 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
948 CPU_I386_FLAGS, 0 },
949 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
950 CPU_I486_FLAGS, 0 },
951 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
952 CPU_I586_FLAGS, 0 },
953 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
954 CPU_I686_FLAGS, 0 },
955 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
956 CPU_I586_FLAGS, 0 },
957 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
958 CPU_PENTIUMPRO_FLAGS, 0 },
959 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
960 CPU_P2_FLAGS, 0 },
961 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
962 CPU_P3_FLAGS, 0 },
963 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
964 CPU_P4_FLAGS, 0 },
965 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
966 CPU_CORE_FLAGS, 0 },
967 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
968 CPU_NOCONA_FLAGS, 0 },
969 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
970 CPU_CORE_FLAGS, 1 },
971 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
972 CPU_CORE_FLAGS, 0 },
973 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
974 CPU_CORE2_FLAGS, 1 },
975 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
976 CPU_CORE2_FLAGS, 0 },
977 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
978 CPU_COREI7_FLAGS, 0 },
979 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
980 CPU_L1OM_FLAGS, 0 },
981 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
982 CPU_K1OM_FLAGS, 0 },
983 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
984 CPU_IAMCU_FLAGS, 0 },
985 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
986 CPU_K6_FLAGS, 0 },
987 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
988 CPU_K6_2_FLAGS, 0 },
989 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
990 CPU_ATHLON_FLAGS, 0 },
991 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
992 CPU_K8_FLAGS, 1 },
993 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
994 CPU_K8_FLAGS, 0 },
995 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
996 CPU_K8_FLAGS, 0 },
997 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
998 CPU_AMDFAM10_FLAGS, 0 },
999 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
1000 CPU_BDVER1_FLAGS, 0 },
1001 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
1002 CPU_BDVER2_FLAGS, 0 },
1003 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
1004 CPU_BDVER3_FLAGS, 0 },
1005 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
1006 CPU_BDVER4_FLAGS, 0 },
1007 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
1008 CPU_ZNVER1_FLAGS, 0 },
1009 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
1010 CPU_ZNVER2_FLAGS, 0 },
1011 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
1012 CPU_BTVER1_FLAGS, 0 },
1013 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
1014 CPU_BTVER2_FLAGS, 0 },
1015 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
1016 CPU_8087_FLAGS, 0 },
1017 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
1018 CPU_287_FLAGS, 0 },
1019 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
1020 CPU_387_FLAGS, 0 },
1021 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
1022 CPU_687_FLAGS, 0 },
1023 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN,
1024 CPU_CMOV_FLAGS, 0 },
1025 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN,
1026 CPU_FXSR_FLAGS, 0 },
1027 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
1028 CPU_MMX_FLAGS, 0 },
1029 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
1030 CPU_SSE_FLAGS, 0 },
1031 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
1032 CPU_SSE2_FLAGS, 0 },
1033 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
1034 CPU_SSE3_FLAGS, 0 },
1035 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
1036 CPU_SSE4A_FLAGS, 0 },
1037 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
1038 CPU_SSSE3_FLAGS, 0 },
1039 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
1040 CPU_SSE4_1_FLAGS, 0 },
1041 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
1042 CPU_SSE4_2_FLAGS, 0 },
1043 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
1044 CPU_SSE4_2_FLAGS, 0 },
1045 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
1046 CPU_AVX_FLAGS, 0 },
1047 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
1048 CPU_AVX2_FLAGS, 0 },
1049 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
1050 CPU_AVX512F_FLAGS, 0 },
1051 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
1052 CPU_AVX512CD_FLAGS, 0 },
1053 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
1054 CPU_AVX512ER_FLAGS, 0 },
1055 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
1056 CPU_AVX512PF_FLAGS, 0 },
1057 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
1058 CPU_AVX512DQ_FLAGS, 0 },
1059 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
1060 CPU_AVX512BW_FLAGS, 0 },
1061 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
1062 CPU_AVX512VL_FLAGS, 0 },
1063 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
1064 CPU_VMX_FLAGS, 0 },
1065 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
1066 CPU_VMFUNC_FLAGS, 0 },
1067 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
1068 CPU_SMX_FLAGS, 0 },
1069 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
1070 CPU_XSAVE_FLAGS, 0 },
1071 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
1072 CPU_XSAVEOPT_FLAGS, 0 },
1073 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
1074 CPU_XSAVEC_FLAGS, 0 },
1075 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
1076 CPU_XSAVES_FLAGS, 0 },
1077 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
1078 CPU_AES_FLAGS, 0 },
1079 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
1080 CPU_PCLMUL_FLAGS, 0 },
1081 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
1082 CPU_PCLMUL_FLAGS, 1 },
1083 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
1084 CPU_FSGSBASE_FLAGS, 0 },
1085 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
1086 CPU_RDRND_FLAGS, 0 },
1087 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
1088 CPU_F16C_FLAGS, 0 },
1089 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
1090 CPU_BMI2_FLAGS, 0 },
1091 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
1092 CPU_FMA_FLAGS, 0 },
1093 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
1094 CPU_FMA4_FLAGS, 0 },
1095 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
1096 CPU_XOP_FLAGS, 0 },
1097 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
1098 CPU_LWP_FLAGS, 0 },
1099 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
1100 CPU_MOVBE_FLAGS, 0 },
1101 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
1102 CPU_CX16_FLAGS, 0 },
1103 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
1104 CPU_EPT_FLAGS, 0 },
1105 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
1106 CPU_LZCNT_FLAGS, 0 },
1107 { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN,
1108 CPU_POPCNT_FLAGS, 0 },
1109 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
1110 CPU_HLE_FLAGS, 0 },
1111 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
1112 CPU_RTM_FLAGS, 0 },
1113 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
1114 CPU_INVPCID_FLAGS, 0 },
1115 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
1116 CPU_CLFLUSH_FLAGS, 0 },
1117 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
1118 CPU_NOP_FLAGS, 0 },
1119 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
1120 CPU_SYSCALL_FLAGS, 0 },
1121 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
1122 CPU_RDTSCP_FLAGS, 0 },
1123 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
1124 CPU_3DNOW_FLAGS, 0 },
1125 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
1126 CPU_3DNOWA_FLAGS, 0 },
1127 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
1128 CPU_PADLOCK_FLAGS, 0 },
1129 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
1130 CPU_SVME_FLAGS, 1 },
1131 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
1132 CPU_SVME_FLAGS, 0 },
1133 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
1134 CPU_SSE4A_FLAGS, 0 },
1135 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
1136 CPU_ABM_FLAGS, 0 },
1137 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
1138 CPU_BMI_FLAGS, 0 },
1139 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
1140 CPU_TBM_FLAGS, 0 },
1141 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
1142 CPU_ADX_FLAGS, 0 },
1143 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
1144 CPU_RDSEED_FLAGS, 0 },
1145 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
1146 CPU_PRFCHW_FLAGS, 0 },
1147 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
1148 CPU_SMAP_FLAGS, 0 },
1149 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
1150 CPU_MPX_FLAGS, 0 },
1151 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
1152 CPU_SHA_FLAGS, 0 },
1153 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
1154 CPU_CLFLUSHOPT_FLAGS, 0 },
1155 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
1156 CPU_PREFETCHWT1_FLAGS, 0 },
1157 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
1158 CPU_SE1_FLAGS, 0 },
1159 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
1160 CPU_CLWB_FLAGS, 0 },
1161 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
1162 CPU_AVX512IFMA_FLAGS, 0 },
1163 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
1164 CPU_AVX512VBMI_FLAGS, 0 },
1165 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1166 CPU_AVX512_4FMAPS_FLAGS, 0 },
1167 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1168 CPU_AVX512_4VNNIW_FLAGS, 0 },
1169 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1170 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1171 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1172 CPU_AVX512_VBMI2_FLAGS, 0 },
1173 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1174 CPU_AVX512_VNNI_FLAGS, 0 },
1175 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1176 CPU_AVX512_BITALG_FLAGS, 0 },
1177 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1178 CPU_CLZERO_FLAGS, 0 },
1179 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1180 CPU_MWAITX_FLAGS, 0 },
1181 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1182 CPU_OSPKE_FLAGS, 0 },
1183 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1184 CPU_RDPID_FLAGS, 0 },
1185 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1186 CPU_PTWRITE_FLAGS, 0 },
1187 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1188 CPU_IBT_FLAGS, 0 },
1189 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1190 CPU_SHSTK_FLAGS, 0 },
1191 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1192 CPU_GFNI_FLAGS, 0 },
1193 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1194 CPU_VAES_FLAGS, 0 },
1195 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1196 CPU_VPCLMULQDQ_FLAGS, 0 },
1197 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1198 CPU_WBNOINVD_FLAGS, 0 },
1199 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1200 CPU_PCONFIG_FLAGS, 0 },
1201 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1202 CPU_WAITPKG_FLAGS, 0 },
1203 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1204 CPU_CLDEMOTE_FLAGS, 0 },
1205 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1206 CPU_MOVDIRI_FLAGS, 0 },
1207 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1208 CPU_MOVDIR64B_FLAGS, 0 },
1209 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN,
1210 CPU_AVX512_BF16_FLAGS, 0 },
1211 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN,
1212 CPU_AVX512_VP2INTERSECT_FLAGS, 0 },
1213 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN,
1214 CPU_ENQCMD_FLAGS, 0 },
1215 { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN,
1216 CPU_SERIALIZE_FLAGS, 0 },
1217 { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN,
1218 CPU_RDPRU_FLAGS, 0 },
1219 { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN,
1220 CPU_MCOMMIT_FLAGS, 0 },
1221 { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN,
1222 CPU_SEV_ES_FLAGS, 0 },
1223 { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN,
1224 CPU_TSXLDTRK_FLAGS, 0 },
1225};
1226
1227static const noarch_entry cpu_noarch[] =
1228{
1229 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1230 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1231 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1232 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1233 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS },
1234 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS },
1235 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1236 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1237 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1238 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1239 { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS },
1240 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1241 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1242 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1243 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1244 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1245 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1246 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1247 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1248 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1249 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1250 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1251 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1252 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1253 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1254 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1255 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1256 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1257 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1258 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1259 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1260 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1261 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1262 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1263 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1264 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1265 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
1266 { STRING_COMMA_LEN ("noavx512_vp2intersect"),
1267 CPU_ANY_AVX512_VP2INTERSECT_FLAGS },
1268 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS },
1269 { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS },
1270 { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS },
1271};
1272
1273#ifdef I386COFF
1274/* Like s_lcomm_internal in gas/read.c but the alignment string
1275 is allowed to be optional. */
1276
1277static symbolS *
1278pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1279{
1280 addressT align = 0;
1281
1282 SKIP_WHITESPACE ();
1283
1284 if (needs_align
1285 && *input_line_pointer == ',')
1286 {
1287 align = parse_align (needs_align - 1);
1288
1289 if (align == (addressT) -1)
1290 return NULL;
1291 }
1292 else
1293 {
1294 if (size >= 8)
1295 align = 3;
1296 else if (size >= 4)
1297 align = 2;
1298 else if (size >= 2)
1299 align = 1;
1300 else
1301 align = 0;
1302 }
1303
1304 bss_alloc (symbolP, size, align);
1305 return symbolP;
1306}
1307
1308static void
1309pe_lcomm (int needs_align)
1310{
1311 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1312}
1313#endif
1314
1315const pseudo_typeS md_pseudo_table[] =
1316{
1317#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1318 {"align", s_align_bytes, 0},
1319#else
1320 {"align", s_align_ptwo, 0},
1321#endif
1322 {"arch", set_cpu_arch, 0},
1323#ifndef I386COFF
1324 {"bss", s_bss, 0},
1325#else
1326 {"lcomm", pe_lcomm, 1},
1327#endif
1328 {"ffloat", float_cons, 'f'},
1329 {"dfloat", float_cons, 'd'},
1330 {"tfloat", float_cons, 'x'},
1331 {"value", cons, 2},
1332 {"slong", signed_cons, 4},
1333 {"noopt", s_ignore, 0},
1334 {"optim", s_ignore, 0},
1335 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1336 {"code16", set_code_flag, CODE_16BIT},
1337 {"code32", set_code_flag, CODE_32BIT},
1338#ifdef BFD64
1339 {"code64", set_code_flag, CODE_64BIT},
1340#endif
1341 {"intel_syntax", set_intel_syntax, 1},
1342 {"att_syntax", set_intel_syntax, 0},
1343 {"intel_mnemonic", set_intel_mnemonic, 1},
1344 {"att_mnemonic", set_intel_mnemonic, 0},
1345 {"allow_index_reg", set_allow_index_reg, 1},
1346 {"disallow_index_reg", set_allow_index_reg, 0},
1347 {"sse_check", set_check, 0},
1348 {"operand_check", set_check, 1},
1349#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1350 {"largecomm", handle_large_common, 0},
1351#else
1352 {"file", dwarf2_directive_file, 0},
1353 {"loc", dwarf2_directive_loc, 0},
1354 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1355#endif
1356#ifdef TE_PE
1357 {"secrel32", pe_directive_secrel, 0},
1358#endif
1359 {0, 0, 0}
1360};
1361
1362/* For interface with expression (). */
1363extern char *input_line_pointer;
1364
1365/* Hash table for instruction mnemonic lookup. */
1366static struct hash_control *op_hash;
1367
1368/* Hash table for register lookup. */
1369static struct hash_control *reg_hash;
1370\f
1371 /* Various efficient no-op patterns for aligning code labels.
1372 Note: Don't try to assemble the instructions in the comments.
1373 0L and 0w are not legal. */
1374static const unsigned char f32_1[] =
1375 {0x90}; /* nop */
1376static const unsigned char f32_2[] =
1377 {0x66,0x90}; /* xchg %ax,%ax */
1378static const unsigned char f32_3[] =
1379 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1380static const unsigned char f32_4[] =
1381 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1382static const unsigned char f32_6[] =
1383 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1384static const unsigned char f32_7[] =
1385 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1386static const unsigned char f16_3[] =
1387 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1388static const unsigned char f16_4[] =
1389 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1390static const unsigned char jump_disp8[] =
1391 {0xeb}; /* jmp disp8 */
1392static const unsigned char jump32_disp32[] =
1393 {0xe9}; /* jmp disp32 */
1394static const unsigned char jump16_disp32[] =
1395 {0x66,0xe9}; /* jmp disp32 */
1396/* 32-bit NOPs patterns. */
1397static const unsigned char *const f32_patt[] = {
1398 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1399};
1400/* 16-bit NOPs patterns. */
1401static const unsigned char *const f16_patt[] = {
1402 f32_1, f32_2, f16_3, f16_4
1403};
1404/* nopl (%[re]ax) */
1405static const unsigned char alt_3[] =
1406 {0x0f,0x1f,0x00};
1407/* nopl 0(%[re]ax) */
1408static const unsigned char alt_4[] =
1409 {0x0f,0x1f,0x40,0x00};
1410/* nopl 0(%[re]ax,%[re]ax,1) */
1411static const unsigned char alt_5[] =
1412 {0x0f,0x1f,0x44,0x00,0x00};
1413/* nopw 0(%[re]ax,%[re]ax,1) */
1414static const unsigned char alt_6[] =
1415 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1416/* nopl 0L(%[re]ax) */
1417static const unsigned char alt_7[] =
1418 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1419/* nopl 0L(%[re]ax,%[re]ax,1) */
1420static const unsigned char alt_8[] =
1421 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1422/* nopw 0L(%[re]ax,%[re]ax,1) */
1423static const unsigned char alt_9[] =
1424 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1425/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1426static const unsigned char alt_10[] =
1427 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1428/* data16 nopw %cs:0L(%eax,%eax,1) */
1429static const unsigned char alt_11[] =
1430 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1431/* 32-bit and 64-bit NOPs patterns. */
1432static const unsigned char *const alt_patt[] = {
1433 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1434 alt_9, alt_10, alt_11
1435};
1436
1437/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1438 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1439
1440static void
1441i386_output_nops (char *where, const unsigned char *const *patt,
1442 int count, int max_single_nop_size)
1443
1444{
1445 /* Place the longer NOP first. */
1446 int last;
1447 int offset;
1448 const unsigned char *nops;
1449
1450 if (max_single_nop_size < 1)
1451 {
1452 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1453 max_single_nop_size);
1454 return;
1455 }
1456
1457 nops = patt[max_single_nop_size - 1];
1458
1459 /* Use the smaller one if the requsted one isn't available. */
1460 if (nops == NULL)
1461 {
1462 max_single_nop_size--;
1463 nops = patt[max_single_nop_size - 1];
1464 }
1465
1466 last = count % max_single_nop_size;
1467
1468 count -= last;
1469 for (offset = 0; offset < count; offset += max_single_nop_size)
1470 memcpy (where + offset, nops, max_single_nop_size);
1471
1472 if (last)
1473 {
1474 nops = patt[last - 1];
1475 if (nops == NULL)
1476 {
1477 /* Use the smaller one plus one-byte NOP if the needed one
1478 isn't available. */
1479 last--;
1480 nops = patt[last - 1];
1481 memcpy (where + offset, nops, last);
1482 where[offset + last] = *patt[0];
1483 }
1484 else
1485 memcpy (where + offset, nops, last);
1486 }
1487}
1488
1489static INLINE int
1490fits_in_imm7 (offsetT num)
1491{
1492 return (num & 0x7f) == num;
1493}
1494
1495static INLINE int
1496fits_in_imm31 (offsetT num)
1497{
1498 return (num & 0x7fffffff) == num;
1499}
1500
1501/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1502 single NOP instruction LIMIT. */
1503
1504void
1505i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1506{
1507 const unsigned char *const *patt = NULL;
1508 int max_single_nop_size;
1509 /* Maximum number of NOPs before switching to jump over NOPs. */
1510 int max_number_of_nops;
1511
1512 switch (fragP->fr_type)
1513 {
1514 case rs_fill_nop:
1515 case rs_align_code:
1516 break;
1517 case rs_machine_dependent:
1518 /* Allow NOP padding for jumps and calls. */
1519 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
1520 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
1521 break;
1522 /* Fall through. */
1523 default:
1524 return;
1525 }
1526
1527 /* We need to decide which NOP sequence to use for 32bit and
1528 64bit. When -mtune= is used:
1529
1530 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1531 PROCESSOR_GENERIC32, f32_patt will be used.
1532 2. For the rest, alt_patt will be used.
1533
1534 When -mtune= isn't used, alt_patt will be used if
1535 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1536 be used.
1537
1538 When -march= or .arch is used, we can't use anything beyond
1539 cpu_arch_isa_flags. */
1540
1541 if (flag_code == CODE_16BIT)
1542 {
1543 patt = f16_patt;
1544 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1545 /* Limit number of NOPs to 2 in 16-bit mode. */
1546 max_number_of_nops = 2;
1547 }
1548 else
1549 {
1550 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1551 {
1552 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1553 switch (cpu_arch_tune)
1554 {
1555 case PROCESSOR_UNKNOWN:
1556 /* We use cpu_arch_isa_flags to check if we SHOULD
1557 optimize with nops. */
1558 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1559 patt = alt_patt;
1560 else
1561 patt = f32_patt;
1562 break;
1563 case PROCESSOR_PENTIUM4:
1564 case PROCESSOR_NOCONA:
1565 case PROCESSOR_CORE:
1566 case PROCESSOR_CORE2:
1567 case PROCESSOR_COREI7:
1568 case PROCESSOR_L1OM:
1569 case PROCESSOR_K1OM:
1570 case PROCESSOR_GENERIC64:
1571 case PROCESSOR_K6:
1572 case PROCESSOR_ATHLON:
1573 case PROCESSOR_K8:
1574 case PROCESSOR_AMDFAM10:
1575 case PROCESSOR_BD:
1576 case PROCESSOR_ZNVER:
1577 case PROCESSOR_BT:
1578 patt = alt_patt;
1579 break;
1580 case PROCESSOR_I386:
1581 case PROCESSOR_I486:
1582 case PROCESSOR_PENTIUM:
1583 case PROCESSOR_PENTIUMPRO:
1584 case PROCESSOR_IAMCU:
1585 case PROCESSOR_GENERIC32:
1586 patt = f32_patt;
1587 break;
1588 }
1589 }
1590 else
1591 {
1592 switch (fragP->tc_frag_data.tune)
1593 {
1594 case PROCESSOR_UNKNOWN:
1595 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1596 PROCESSOR_UNKNOWN. */
1597 abort ();
1598 break;
1599
1600 case PROCESSOR_I386:
1601 case PROCESSOR_I486:
1602 case PROCESSOR_PENTIUM:
1603 case PROCESSOR_IAMCU:
1604 case PROCESSOR_K6:
1605 case PROCESSOR_ATHLON:
1606 case PROCESSOR_K8:
1607 case PROCESSOR_AMDFAM10:
1608 case PROCESSOR_BD:
1609 case PROCESSOR_ZNVER:
1610 case PROCESSOR_BT:
1611 case PROCESSOR_GENERIC32:
1612 /* We use cpu_arch_isa_flags to check if we CAN optimize
1613 with nops. */
1614 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1615 patt = alt_patt;
1616 else
1617 patt = f32_patt;
1618 break;
1619 case PROCESSOR_PENTIUMPRO:
1620 case PROCESSOR_PENTIUM4:
1621 case PROCESSOR_NOCONA:
1622 case PROCESSOR_CORE:
1623 case PROCESSOR_CORE2:
1624 case PROCESSOR_COREI7:
1625 case PROCESSOR_L1OM:
1626 case PROCESSOR_K1OM:
1627 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1628 patt = alt_patt;
1629 else
1630 patt = f32_patt;
1631 break;
1632 case PROCESSOR_GENERIC64:
1633 patt = alt_patt;
1634 break;
1635 }
1636 }
1637
1638 if (patt == f32_patt)
1639 {
1640 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1641 /* Limit number of NOPs to 2 for older processors. */
1642 max_number_of_nops = 2;
1643 }
1644 else
1645 {
1646 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1647 /* Limit number of NOPs to 7 for newer processors. */
1648 max_number_of_nops = 7;
1649 }
1650 }
1651
1652 if (limit == 0)
1653 limit = max_single_nop_size;
1654
1655 if (fragP->fr_type == rs_fill_nop)
1656 {
1657 /* Output NOPs for .nop directive. */
1658 if (limit > max_single_nop_size)
1659 {
1660 as_bad_where (fragP->fr_file, fragP->fr_line,
1661 _("invalid single nop size: %d "
1662 "(expect within [0, %d])"),
1663 limit, max_single_nop_size);
1664 return;
1665 }
1666 }
1667 else if (fragP->fr_type != rs_machine_dependent)
1668 fragP->fr_var = count;
1669
1670 if ((count / max_single_nop_size) > max_number_of_nops)
1671 {
1672 /* Generate jump over NOPs. */
1673 offsetT disp = count - 2;
1674 if (fits_in_imm7 (disp))
1675 {
1676 /* Use "jmp disp8" if possible. */
1677 count = disp;
1678 where[0] = jump_disp8[0];
1679 where[1] = count;
1680 where += 2;
1681 }
1682 else
1683 {
1684 unsigned int size_of_jump;
1685
1686 if (flag_code == CODE_16BIT)
1687 {
1688 where[0] = jump16_disp32[0];
1689 where[1] = jump16_disp32[1];
1690 size_of_jump = 2;
1691 }
1692 else
1693 {
1694 where[0] = jump32_disp32[0];
1695 size_of_jump = 1;
1696 }
1697
1698 count -= size_of_jump + 4;
1699 if (!fits_in_imm31 (count))
1700 {
1701 as_bad_where (fragP->fr_file, fragP->fr_line,
1702 _("jump over nop padding out of range"));
1703 return;
1704 }
1705
1706 md_number_to_chars (where + size_of_jump, count, 4);
1707 where += size_of_jump + 4;
1708 }
1709 }
1710
1711 /* Generate multiple NOPs. */
1712 i386_output_nops (where, patt, count, limit);
1713}
1714
1715static INLINE int
1716operand_type_all_zero (const union i386_operand_type *x)
1717{
1718 switch (ARRAY_SIZE(x->array))
1719 {
1720 case 3:
1721 if (x->array[2])
1722 return 0;
1723 /* Fall through. */
1724 case 2:
1725 if (x->array[1])
1726 return 0;
1727 /* Fall through. */
1728 case 1:
1729 return !x->array[0];
1730 default:
1731 abort ();
1732 }
1733}
1734
1735static INLINE void
1736operand_type_set (union i386_operand_type *x, unsigned int v)
1737{
1738 switch (ARRAY_SIZE(x->array))
1739 {
1740 case 3:
1741 x->array[2] = v;
1742 /* Fall through. */
1743 case 2:
1744 x->array[1] = v;
1745 /* Fall through. */
1746 case 1:
1747 x->array[0] = v;
1748 /* Fall through. */
1749 break;
1750 default:
1751 abort ();
1752 }
1753
1754 x->bitfield.class = ClassNone;
1755 x->bitfield.instance = InstanceNone;
1756}
1757
1758static INLINE int
1759operand_type_equal (const union i386_operand_type *x,
1760 const union i386_operand_type *y)
1761{
1762 switch (ARRAY_SIZE(x->array))
1763 {
1764 case 3:
1765 if (x->array[2] != y->array[2])
1766 return 0;
1767 /* Fall through. */
1768 case 2:
1769 if (x->array[1] != y->array[1])
1770 return 0;
1771 /* Fall through. */
1772 case 1:
1773 return x->array[0] == y->array[0];
1774 break;
1775 default:
1776 abort ();
1777 }
1778}
1779
1780static INLINE int
1781cpu_flags_all_zero (const union i386_cpu_flags *x)
1782{
1783 switch (ARRAY_SIZE(x->array))
1784 {
1785 case 4:
1786 if (x->array[3])
1787 return 0;
1788 /* Fall through. */
1789 case 3:
1790 if (x->array[2])
1791 return 0;
1792 /* Fall through. */
1793 case 2:
1794 if (x->array[1])
1795 return 0;
1796 /* Fall through. */
1797 case 1:
1798 return !x->array[0];
1799 default:
1800 abort ();
1801 }
1802}
1803
1804static INLINE int
1805cpu_flags_equal (const union i386_cpu_flags *x,
1806 const union i386_cpu_flags *y)
1807{
1808 switch (ARRAY_SIZE(x->array))
1809 {
1810 case 4:
1811 if (x->array[3] != y->array[3])
1812 return 0;
1813 /* Fall through. */
1814 case 3:
1815 if (x->array[2] != y->array[2])
1816 return 0;
1817 /* Fall through. */
1818 case 2:
1819 if (x->array[1] != y->array[1])
1820 return 0;
1821 /* Fall through. */
1822 case 1:
1823 return x->array[0] == y->array[0];
1824 break;
1825 default:
1826 abort ();
1827 }
1828}
1829
1830static INLINE int
1831cpu_flags_check_cpu64 (i386_cpu_flags f)
1832{
1833 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1834 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1835}
1836
1837static INLINE i386_cpu_flags
1838cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1839{
1840 switch (ARRAY_SIZE (x.array))
1841 {
1842 case 4:
1843 x.array [3] &= y.array [3];
1844 /* Fall through. */
1845 case 3:
1846 x.array [2] &= y.array [2];
1847 /* Fall through. */
1848 case 2:
1849 x.array [1] &= y.array [1];
1850 /* Fall through. */
1851 case 1:
1852 x.array [0] &= y.array [0];
1853 break;
1854 default:
1855 abort ();
1856 }
1857 return x;
1858}
1859
1860static INLINE i386_cpu_flags
1861cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1862{
1863 switch (ARRAY_SIZE (x.array))
1864 {
1865 case 4:
1866 x.array [3] |= y.array [3];
1867 /* Fall through. */
1868 case 3:
1869 x.array [2] |= y.array [2];
1870 /* Fall through. */
1871 case 2:
1872 x.array [1] |= y.array [1];
1873 /* Fall through. */
1874 case 1:
1875 x.array [0] |= y.array [0];
1876 break;
1877 default:
1878 abort ();
1879 }
1880 return x;
1881}
1882
1883static INLINE i386_cpu_flags
1884cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1885{
1886 switch (ARRAY_SIZE (x.array))
1887 {
1888 case 4:
1889 x.array [3] &= ~y.array [3];
1890 /* Fall through. */
1891 case 3:
1892 x.array [2] &= ~y.array [2];
1893 /* Fall through. */
1894 case 2:
1895 x.array [1] &= ~y.array [1];
1896 /* Fall through. */
1897 case 1:
1898 x.array [0] &= ~y.array [0];
1899 break;
1900 default:
1901 abort ();
1902 }
1903 return x;
1904}
1905
1906static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
1907
1908#define CPU_FLAGS_ARCH_MATCH 0x1
1909#define CPU_FLAGS_64BIT_MATCH 0x2
1910
1911#define CPU_FLAGS_PERFECT_MATCH \
1912 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1913
1914/* Return CPU flags match bits. */
1915
1916static int
1917cpu_flags_match (const insn_template *t)
1918{
1919 i386_cpu_flags x = t->cpu_flags;
1920 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1921
1922 x.bitfield.cpu64 = 0;
1923 x.bitfield.cpuno64 = 0;
1924
1925 if (cpu_flags_all_zero (&x))
1926 {
1927 /* This instruction is available on all archs. */
1928 match |= CPU_FLAGS_ARCH_MATCH;
1929 }
1930 else
1931 {
1932 /* This instruction is available only on some archs. */
1933 i386_cpu_flags cpu = cpu_arch_flags;
1934
1935 /* AVX512VL is no standalone feature - match it and then strip it. */
1936 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1937 return match;
1938 x.bitfield.cpuavx512vl = 0;
1939
1940 cpu = cpu_flags_and (x, cpu);
1941 if (!cpu_flags_all_zero (&cpu))
1942 {
1943 if (x.bitfield.cpuavx)
1944 {
1945 /* We need to check a few extra flags with AVX. */
1946 if (cpu.bitfield.cpuavx
1947 && (!t->opcode_modifier.sse2avx || sse2avx)
1948 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1949 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1950 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1951 match |= CPU_FLAGS_ARCH_MATCH;
1952 }
1953 else if (x.bitfield.cpuavx512f)
1954 {
1955 /* We need to check a few extra flags with AVX512F. */
1956 if (cpu.bitfield.cpuavx512f
1957 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1958 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1959 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1960 match |= CPU_FLAGS_ARCH_MATCH;
1961 }
1962 else
1963 match |= CPU_FLAGS_ARCH_MATCH;
1964 }
1965 }
1966 return match;
1967}
1968
1969static INLINE i386_operand_type
1970operand_type_and (i386_operand_type x, i386_operand_type y)
1971{
1972 if (x.bitfield.class != y.bitfield.class)
1973 x.bitfield.class = ClassNone;
1974 if (x.bitfield.instance != y.bitfield.instance)
1975 x.bitfield.instance = InstanceNone;
1976
1977 switch (ARRAY_SIZE (x.array))
1978 {
1979 case 3:
1980 x.array [2] &= y.array [2];
1981 /* Fall through. */
1982 case 2:
1983 x.array [1] &= y.array [1];
1984 /* Fall through. */
1985 case 1:
1986 x.array [0] &= y.array [0];
1987 break;
1988 default:
1989 abort ();
1990 }
1991 return x;
1992}
1993
1994static INLINE i386_operand_type
1995operand_type_and_not (i386_operand_type x, i386_operand_type y)
1996{
1997 gas_assert (y.bitfield.class == ClassNone);
1998 gas_assert (y.bitfield.instance == InstanceNone);
1999
2000 switch (ARRAY_SIZE (x.array))
2001 {
2002 case 3:
2003 x.array [2] &= ~y.array [2];
2004 /* Fall through. */
2005 case 2:
2006 x.array [1] &= ~y.array [1];
2007 /* Fall through. */
2008 case 1:
2009 x.array [0] &= ~y.array [0];
2010 break;
2011 default:
2012 abort ();
2013 }
2014 return x;
2015}
2016
2017static INLINE i386_operand_type
2018operand_type_or (i386_operand_type x, i386_operand_type y)
2019{
2020 gas_assert (x.bitfield.class == ClassNone ||
2021 y.bitfield.class == ClassNone ||
2022 x.bitfield.class == y.bitfield.class);
2023 gas_assert (x.bitfield.instance == InstanceNone ||
2024 y.bitfield.instance == InstanceNone ||
2025 x.bitfield.instance == y.bitfield.instance);
2026
2027 switch (ARRAY_SIZE (x.array))
2028 {
2029 case 3:
2030 x.array [2] |= y.array [2];
2031 /* Fall through. */
2032 case 2:
2033 x.array [1] |= y.array [1];
2034 /* Fall through. */
2035 case 1:
2036 x.array [0] |= y.array [0];
2037 break;
2038 default:
2039 abort ();
2040 }
2041 return x;
2042}
2043
2044static INLINE i386_operand_type
2045operand_type_xor (i386_operand_type x, i386_operand_type y)
2046{
2047 gas_assert (y.bitfield.class == ClassNone);
2048 gas_assert (y.bitfield.instance == InstanceNone);
2049
2050 switch (ARRAY_SIZE (x.array))
2051 {
2052 case 3:
2053 x.array [2] ^= y.array [2];
2054 /* Fall through. */
2055 case 2:
2056 x.array [1] ^= y.array [1];
2057 /* Fall through. */
2058 case 1:
2059 x.array [0] ^= y.array [0];
2060 break;
2061 default:
2062 abort ();
2063 }
2064 return x;
2065}
2066
2067static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
2068static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
2069static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
2070static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
2071static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP;
2072static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM;
2073static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
2074static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
2075static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
2076static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
2077static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
2078static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
2079static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
2080static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
2081static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
2082static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
2083static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
2084
2085enum operand_type
2086{
2087 reg,
2088 imm,
2089 disp,
2090 anymem
2091};
2092
2093static INLINE int
2094operand_type_check (i386_operand_type t, enum operand_type c)
2095{
2096 switch (c)
2097 {
2098 case reg:
2099 return t.bitfield.class == Reg;
2100
2101 case imm:
2102 return (t.bitfield.imm8
2103 || t.bitfield.imm8s
2104 || t.bitfield.imm16
2105 || t.bitfield.imm32
2106 || t.bitfield.imm32s
2107 || t.bitfield.imm64);
2108
2109 case disp:
2110 return (t.bitfield.disp8
2111 || t.bitfield.disp16
2112 || t.bitfield.disp32
2113 || t.bitfield.disp32s
2114 || t.bitfield.disp64);
2115
2116 case anymem:
2117 return (t.bitfield.disp8
2118 || t.bitfield.disp16
2119 || t.bitfield.disp32
2120 || t.bitfield.disp32s
2121 || t.bitfield.disp64
2122 || t.bitfield.baseindex);
2123
2124 default:
2125 abort ();
2126 }
2127
2128 return 0;
2129}
2130
2131/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2132 between operand GIVEN and opeand WANTED for instruction template T. */
2133
2134static INLINE int
2135match_operand_size (const insn_template *t, unsigned int wanted,
2136 unsigned int given)
2137{
2138 return !((i.types[given].bitfield.byte
2139 && !t->operand_types[wanted].bitfield.byte)
2140 || (i.types[given].bitfield.word
2141 && !t->operand_types[wanted].bitfield.word)
2142 || (i.types[given].bitfield.dword
2143 && !t->operand_types[wanted].bitfield.dword)
2144 || (i.types[given].bitfield.qword
2145 && !t->operand_types[wanted].bitfield.qword)
2146 || (i.types[given].bitfield.tbyte
2147 && !t->operand_types[wanted].bitfield.tbyte));
2148}
2149
2150/* Return 1 if there is no conflict in SIMD register between operand
2151 GIVEN and opeand WANTED for instruction template T. */
2152
2153static INLINE int
2154match_simd_size (const insn_template *t, unsigned int wanted,
2155 unsigned int given)
2156{
2157 return !((i.types[given].bitfield.xmmword
2158 && !t->operand_types[wanted].bitfield.xmmword)
2159 || (i.types[given].bitfield.ymmword
2160 && !t->operand_types[wanted].bitfield.ymmword)
2161 || (i.types[given].bitfield.zmmword
2162 && !t->operand_types[wanted].bitfield.zmmword));
2163}
2164
2165/* Return 1 if there is no conflict in any size between operand GIVEN
2166 and opeand WANTED for instruction template T. */
2167
2168static INLINE int
2169match_mem_size (const insn_template *t, unsigned int wanted,
2170 unsigned int given)
2171{
2172 return (match_operand_size (t, wanted, given)
2173 && !((i.types[given].bitfield.unspecified
2174 && !i.broadcast
2175 && !t->operand_types[wanted].bitfield.unspecified)
2176 || (i.types[given].bitfield.fword
2177 && !t->operand_types[wanted].bitfield.fword)
2178 /* For scalar opcode templates to allow register and memory
2179 operands at the same time, some special casing is needed
2180 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2181 down-conversion vpmov*. */
2182 || ((t->operand_types[wanted].bitfield.class == RegSIMD
2183 && t->operand_types[wanted].bitfield.byte
2184 + t->operand_types[wanted].bitfield.word
2185 + t->operand_types[wanted].bitfield.dword
2186 + t->operand_types[wanted].bitfield.qword
2187 > !!t->opcode_modifier.broadcast)
2188 ? (i.types[given].bitfield.xmmword
2189 || i.types[given].bitfield.ymmword
2190 || i.types[given].bitfield.zmmword)
2191 : !match_simd_size(t, wanted, given))));
2192}
2193
2194/* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2195 operands for instruction template T, and it has MATCH_REVERSE set if there
2196 is no size conflict on any operands for the template with operands reversed
2197 (and the template allows for reversing in the first place). */
2198
2199#define MATCH_STRAIGHT 1
2200#define MATCH_REVERSE 2
2201
2202static INLINE unsigned int
2203operand_size_match (const insn_template *t)
2204{
2205 unsigned int j, match = MATCH_STRAIGHT;
2206
2207 /* Don't check non-absolute jump instructions. */
2208 if (t->opcode_modifier.jump
2209 && t->opcode_modifier.jump != JUMP_ABSOLUTE)
2210 return match;
2211
2212 /* Check memory and accumulator operand size. */
2213 for (j = 0; j < i.operands; j++)
2214 {
2215 if (i.types[j].bitfield.class != Reg
2216 && i.types[j].bitfield.class != RegSIMD
2217 && t->opcode_modifier.anysize)
2218 continue;
2219
2220 if (t->operand_types[j].bitfield.class == Reg
2221 && !match_operand_size (t, j, j))
2222 {
2223 match = 0;
2224 break;
2225 }
2226
2227 if (t->operand_types[j].bitfield.class == RegSIMD
2228 && !match_simd_size (t, j, j))
2229 {
2230 match = 0;
2231 break;
2232 }
2233
2234 if (t->operand_types[j].bitfield.instance == Accum
2235 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2236 {
2237 match = 0;
2238 break;
2239 }
2240
2241 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
2242 {
2243 match = 0;
2244 break;
2245 }
2246 }
2247
2248 if (!t->opcode_modifier.d)
2249 {
2250 mismatch:
2251 if (!match)
2252 i.error = operand_size_mismatch;
2253 return match;
2254 }
2255
2256 /* Check reverse. */
2257 gas_assert (i.operands >= 2 && i.operands <= 3);
2258
2259 for (j = 0; j < i.operands; j++)
2260 {
2261 unsigned int given = i.operands - j - 1;
2262
2263 if (t->operand_types[j].bitfield.class == Reg
2264 && !match_operand_size (t, j, given))
2265 goto mismatch;
2266
2267 if (t->operand_types[j].bitfield.class == RegSIMD
2268 && !match_simd_size (t, j, given))
2269 goto mismatch;
2270
2271 if (t->operand_types[j].bitfield.instance == Accum
2272 && (!match_operand_size (t, j, given)
2273 || !match_simd_size (t, j, given)))
2274 goto mismatch;
2275
2276 if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
2277 goto mismatch;
2278 }
2279
2280 return match | MATCH_REVERSE;
2281}
2282
2283static INLINE int
2284operand_type_match (i386_operand_type overlap,
2285 i386_operand_type given)
2286{
2287 i386_operand_type temp = overlap;
2288
2289 temp.bitfield.unspecified = 0;
2290 temp.bitfield.byte = 0;
2291 temp.bitfield.word = 0;
2292 temp.bitfield.dword = 0;
2293 temp.bitfield.fword = 0;
2294 temp.bitfield.qword = 0;
2295 temp.bitfield.tbyte = 0;
2296 temp.bitfield.xmmword = 0;
2297 temp.bitfield.ymmword = 0;
2298 temp.bitfield.zmmword = 0;
2299 if (operand_type_all_zero (&temp))
2300 goto mismatch;
2301
2302 if (given.bitfield.baseindex == overlap.bitfield.baseindex)
2303 return 1;
2304
2305 mismatch:
2306 i.error = operand_type_mismatch;
2307 return 0;
2308}
2309
2310/* If given types g0 and g1 are registers they must be of the same type
2311 unless the expected operand type register overlap is null.
2312 Some Intel syntax memory operand size checking also happens here. */
2313
2314static INLINE int
2315operand_type_register_match (i386_operand_type g0,
2316 i386_operand_type t0,
2317 i386_operand_type g1,
2318 i386_operand_type t1)
2319{
2320 if (g0.bitfield.class != Reg
2321 && g0.bitfield.class != RegSIMD
2322 && (!operand_type_check (g0, anymem)
2323 || g0.bitfield.unspecified
2324 || (t0.bitfield.class != Reg
2325 && t0.bitfield.class != RegSIMD)))
2326 return 1;
2327
2328 if (g1.bitfield.class != Reg
2329 && g1.bitfield.class != RegSIMD
2330 && (!operand_type_check (g1, anymem)
2331 || g1.bitfield.unspecified
2332 || (t1.bitfield.class != Reg
2333 && t1.bitfield.class != RegSIMD)))
2334 return 1;
2335
2336 if (g0.bitfield.byte == g1.bitfield.byte
2337 && g0.bitfield.word == g1.bitfield.word
2338 && g0.bitfield.dword == g1.bitfield.dword
2339 && g0.bitfield.qword == g1.bitfield.qword
2340 && g0.bitfield.xmmword == g1.bitfield.xmmword
2341 && g0.bitfield.ymmword == g1.bitfield.ymmword
2342 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2343 return 1;
2344
2345 if (!(t0.bitfield.byte & t1.bitfield.byte)
2346 && !(t0.bitfield.word & t1.bitfield.word)
2347 && !(t0.bitfield.dword & t1.bitfield.dword)
2348 && !(t0.bitfield.qword & t1.bitfield.qword)
2349 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2350 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2351 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2352 return 1;
2353
2354 i.error = register_type_mismatch;
2355
2356 return 0;
2357}
2358
2359static INLINE unsigned int
2360register_number (const reg_entry *r)
2361{
2362 unsigned int nr = r->reg_num;
2363
2364 if (r->reg_flags & RegRex)
2365 nr += 8;
2366
2367 if (r->reg_flags & RegVRex)
2368 nr += 16;
2369
2370 return nr;
2371}
2372
2373static INLINE unsigned int
2374mode_from_disp_size (i386_operand_type t)
2375{
2376 if (t.bitfield.disp8)
2377 return 1;
2378 else if (t.bitfield.disp16
2379 || t.bitfield.disp32
2380 || t.bitfield.disp32s)
2381 return 2;
2382 else
2383 return 0;
2384}
2385
2386static INLINE int
2387fits_in_signed_byte (addressT num)
2388{
2389 return num + 0x80 <= 0xff;
2390}
2391
2392static INLINE int
2393fits_in_unsigned_byte (addressT num)
2394{
2395 return num <= 0xff;
2396}
2397
2398static INLINE int
2399fits_in_unsigned_word (addressT num)
2400{
2401 return num <= 0xffff;
2402}
2403
2404static INLINE int
2405fits_in_signed_word (addressT num)
2406{
2407 return num + 0x8000 <= 0xffff;
2408}
2409
2410static INLINE int
2411fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2412{
2413#ifndef BFD64
2414 return 1;
2415#else
2416 return num + 0x80000000 <= 0xffffffff;
2417#endif
2418} /* fits_in_signed_long() */
2419
2420static INLINE int
2421fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2422{
2423#ifndef BFD64
2424 return 1;
2425#else
2426 return num <= 0xffffffff;
2427#endif
2428} /* fits_in_unsigned_long() */
2429
2430static INLINE int
2431fits_in_disp8 (offsetT num)
2432{
2433 int shift = i.memshift;
2434 unsigned int mask;
2435
2436 if (shift == -1)
2437 abort ();
2438
2439 mask = (1 << shift) - 1;
2440
2441 /* Return 0 if NUM isn't properly aligned. */
2442 if ((num & mask))
2443 return 0;
2444
2445 /* Check if NUM will fit in 8bit after shift. */
2446 return fits_in_signed_byte (num >> shift);
2447}
2448
2449static INLINE int
2450fits_in_imm4 (offsetT num)
2451{
2452 return (num & 0xf) == num;
2453}
2454
2455static i386_operand_type
2456smallest_imm_type (offsetT num)
2457{
2458 i386_operand_type t;
2459
2460 operand_type_set (&t, 0);
2461 t.bitfield.imm64 = 1;
2462
2463 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2464 {
2465 /* This code is disabled on the 486 because all the Imm1 forms
2466 in the opcode table are slower on the i486. They're the
2467 versions with the implicitly specified single-position
2468 displacement, which has another syntax if you really want to
2469 use that form. */
2470 t.bitfield.imm1 = 1;
2471 t.bitfield.imm8 = 1;
2472 t.bitfield.imm8s = 1;
2473 t.bitfield.imm16 = 1;
2474 t.bitfield.imm32 = 1;
2475 t.bitfield.imm32s = 1;
2476 }
2477 else if (fits_in_signed_byte (num))
2478 {
2479 t.bitfield.imm8 = 1;
2480 t.bitfield.imm8s = 1;
2481 t.bitfield.imm16 = 1;
2482 t.bitfield.imm32 = 1;
2483 t.bitfield.imm32s = 1;
2484 }
2485 else if (fits_in_unsigned_byte (num))
2486 {
2487 t.bitfield.imm8 = 1;
2488 t.bitfield.imm16 = 1;
2489 t.bitfield.imm32 = 1;
2490 t.bitfield.imm32s = 1;
2491 }
2492 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2493 {
2494 t.bitfield.imm16 = 1;
2495 t.bitfield.imm32 = 1;
2496 t.bitfield.imm32s = 1;
2497 }
2498 else if (fits_in_signed_long (num))
2499 {
2500 t.bitfield.imm32 = 1;
2501 t.bitfield.imm32s = 1;
2502 }
2503 else if (fits_in_unsigned_long (num))
2504 t.bitfield.imm32 = 1;
2505
2506 return t;
2507}
2508
2509static offsetT
2510offset_in_range (offsetT val, int size)
2511{
2512 addressT mask;
2513
2514 switch (size)
2515 {
2516 case 1: mask = ((addressT) 1 << 8) - 1; break;
2517 case 2: mask = ((addressT) 1 << 16) - 1; break;
2518 case 4: mask = ((addressT) 2 << 31) - 1; break;
2519#ifdef BFD64
2520 case 8: mask = ((addressT) 2 << 63) - 1; break;
2521#endif
2522 default: abort ();
2523 }
2524
2525#ifdef BFD64
2526 /* If BFD64, sign extend val for 32bit address mode. */
2527 if (flag_code != CODE_64BIT
2528 || i.prefix[ADDR_PREFIX])
2529 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2530 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2531#endif
2532
2533 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2534 {
2535 char buf1[40], buf2[40];
2536
2537 sprint_value (buf1, val);
2538 sprint_value (buf2, val & mask);
2539 as_warn (_("%s shortened to %s"), buf1, buf2);
2540 }
2541 return val & mask;
2542}
2543
2544enum PREFIX_GROUP
2545{
2546 PREFIX_EXIST = 0,
2547 PREFIX_LOCK,
2548 PREFIX_REP,
2549 PREFIX_DS,
2550 PREFIX_OTHER
2551};
2552
2553/* Returns
2554 a. PREFIX_EXIST if attempting to add a prefix where one from the
2555 same class already exists.
2556 b. PREFIX_LOCK if lock prefix is added.
2557 c. PREFIX_REP if rep/repne prefix is added.
2558 d. PREFIX_DS if ds prefix is added.
2559 e. PREFIX_OTHER if other prefix is added.
2560 */
2561
2562static enum PREFIX_GROUP
2563add_prefix (unsigned int prefix)
2564{
2565 enum PREFIX_GROUP ret = PREFIX_OTHER;
2566 unsigned int q;
2567
2568 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2569 && flag_code == CODE_64BIT)
2570 {
2571 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2572 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2573 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2574 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2575 ret = PREFIX_EXIST;
2576 q = REX_PREFIX;
2577 }
2578 else
2579 {
2580 switch (prefix)
2581 {
2582 default:
2583 abort ();
2584
2585 case DS_PREFIX_OPCODE:
2586 ret = PREFIX_DS;
2587 /* Fall through. */
2588 case CS_PREFIX_OPCODE:
2589 case ES_PREFIX_OPCODE:
2590 case FS_PREFIX_OPCODE:
2591 case GS_PREFIX_OPCODE:
2592 case SS_PREFIX_OPCODE:
2593 q = SEG_PREFIX;
2594 break;
2595
2596 case REPNE_PREFIX_OPCODE:
2597 case REPE_PREFIX_OPCODE:
2598 q = REP_PREFIX;
2599 ret = PREFIX_REP;
2600 break;
2601
2602 case LOCK_PREFIX_OPCODE:
2603 q = LOCK_PREFIX;
2604 ret = PREFIX_LOCK;
2605 break;
2606
2607 case FWAIT_OPCODE:
2608 q = WAIT_PREFIX;
2609 break;
2610
2611 case ADDR_PREFIX_OPCODE:
2612 q = ADDR_PREFIX;
2613 break;
2614
2615 case DATA_PREFIX_OPCODE:
2616 q = DATA_PREFIX;
2617 break;
2618 }
2619 if (i.prefix[q] != 0)
2620 ret = PREFIX_EXIST;
2621 }
2622
2623 if (ret)
2624 {
2625 if (!i.prefix[q])
2626 ++i.prefixes;
2627 i.prefix[q] |= prefix;
2628 }
2629 else
2630 as_bad (_("same type of prefix used twice"));
2631
2632 return ret;
2633}
2634
2635static void
2636update_code_flag (int value, int check)
2637{
2638 PRINTF_LIKE ((*as_error));
2639
2640 flag_code = (enum flag_code) value;
2641 if (flag_code == CODE_64BIT)
2642 {
2643 cpu_arch_flags.bitfield.cpu64 = 1;
2644 cpu_arch_flags.bitfield.cpuno64 = 0;
2645 }
2646 else
2647 {
2648 cpu_arch_flags.bitfield.cpu64 = 0;
2649 cpu_arch_flags.bitfield.cpuno64 = 1;
2650 }
2651 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2652 {
2653 if (check)
2654 as_error = as_fatal;
2655 else
2656 as_error = as_bad;
2657 (*as_error) (_("64bit mode not supported on `%s'."),
2658 cpu_arch_name ? cpu_arch_name : default_arch);
2659 }
2660 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2661 {
2662 if (check)
2663 as_error = as_fatal;
2664 else
2665 as_error = as_bad;
2666 (*as_error) (_("32bit mode not supported on `%s'."),
2667 cpu_arch_name ? cpu_arch_name : default_arch);
2668 }
2669 stackop_size = '\0';
2670}
2671
2672static void
2673set_code_flag (int value)
2674{
2675 update_code_flag (value, 0);
2676}
2677
2678static void
2679set_16bit_gcc_code_flag (int new_code_flag)
2680{
2681 flag_code = (enum flag_code) new_code_flag;
2682 if (flag_code != CODE_16BIT)
2683 abort ();
2684 cpu_arch_flags.bitfield.cpu64 = 0;
2685 cpu_arch_flags.bitfield.cpuno64 = 1;
2686 stackop_size = LONG_MNEM_SUFFIX;
2687}
2688
2689static void
2690set_intel_syntax (int syntax_flag)
2691{
2692 /* Find out if register prefixing is specified. */
2693 int ask_naked_reg = 0;
2694
2695 SKIP_WHITESPACE ();
2696 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2697 {
2698 char *string;
2699 int e = get_symbol_name (&string);
2700
2701 if (strcmp (string, "prefix") == 0)
2702 ask_naked_reg = 1;
2703 else if (strcmp (string, "noprefix") == 0)
2704 ask_naked_reg = -1;
2705 else
2706 as_bad (_("bad argument to syntax directive."));
2707 (void) restore_line_pointer (e);
2708 }
2709 demand_empty_rest_of_line ();
2710
2711 intel_syntax = syntax_flag;
2712
2713 if (ask_naked_reg == 0)
2714 allow_naked_reg = (intel_syntax
2715 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2716 else
2717 allow_naked_reg = (ask_naked_reg < 0);
2718
2719 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2720
2721 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2722 identifier_chars['$'] = intel_syntax ? '$' : 0;
2723 register_prefix = allow_naked_reg ? "" : "%";
2724}
2725
2726static void
2727set_intel_mnemonic (int mnemonic_flag)
2728{
2729 intel_mnemonic = mnemonic_flag;
2730}
2731
2732static void
2733set_allow_index_reg (int flag)
2734{
2735 allow_index_reg = flag;
2736}
2737
2738static void
2739set_check (int what)
2740{
2741 enum check_kind *kind;
2742 const char *str;
2743
2744 if (what)
2745 {
2746 kind = &operand_check;
2747 str = "operand";
2748 }
2749 else
2750 {
2751 kind = &sse_check;
2752 str = "sse";
2753 }
2754
2755 SKIP_WHITESPACE ();
2756
2757 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2758 {
2759 char *string;
2760 int e = get_symbol_name (&string);
2761
2762 if (strcmp (string, "none") == 0)
2763 *kind = check_none;
2764 else if (strcmp (string, "warning") == 0)
2765 *kind = check_warning;
2766 else if (strcmp (string, "error") == 0)
2767 *kind = check_error;
2768 else
2769 as_bad (_("bad argument to %s_check directive."), str);
2770 (void) restore_line_pointer (e);
2771 }
2772 else
2773 as_bad (_("missing argument for %s_check directive"), str);
2774
2775 demand_empty_rest_of_line ();
2776}
2777
2778static void
2779check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2780 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2781{
2782#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2783 static const char *arch;
2784
2785 /* Intel LIOM is only supported on ELF. */
2786 if (!IS_ELF)
2787 return;
2788
2789 if (!arch)
2790 {
2791 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2792 use default_arch. */
2793 arch = cpu_arch_name;
2794 if (!arch)
2795 arch = default_arch;
2796 }
2797
2798 /* If we are targeting Intel MCU, we must enable it. */
2799 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2800 || new_flag.bitfield.cpuiamcu)
2801 return;
2802
2803 /* If we are targeting Intel L1OM, we must enable it. */
2804 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2805 || new_flag.bitfield.cpul1om)
2806 return;
2807
2808 /* If we are targeting Intel K1OM, we must enable it. */
2809 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2810 || new_flag.bitfield.cpuk1om)
2811 return;
2812
2813 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2814#endif
2815}
2816
2817static void
2818set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2819{
2820 SKIP_WHITESPACE ();
2821
2822 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2823 {
2824 char *string;
2825 int e = get_symbol_name (&string);
2826 unsigned int j;
2827 i386_cpu_flags flags;
2828
2829 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2830 {
2831 if (strcmp (string, cpu_arch[j].name) == 0)
2832 {
2833 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2834
2835 if (*string != '.')
2836 {
2837 cpu_arch_name = cpu_arch[j].name;
2838 cpu_sub_arch_name = NULL;
2839 cpu_arch_flags = cpu_arch[j].flags;
2840 if (flag_code == CODE_64BIT)
2841 {
2842 cpu_arch_flags.bitfield.cpu64 = 1;
2843 cpu_arch_flags.bitfield.cpuno64 = 0;
2844 }
2845 else
2846 {
2847 cpu_arch_flags.bitfield.cpu64 = 0;
2848 cpu_arch_flags.bitfield.cpuno64 = 1;
2849 }
2850 cpu_arch_isa = cpu_arch[j].type;
2851 cpu_arch_isa_flags = cpu_arch[j].flags;
2852 if (!cpu_arch_tune_set)
2853 {
2854 cpu_arch_tune = cpu_arch_isa;
2855 cpu_arch_tune_flags = cpu_arch_isa_flags;
2856 }
2857 break;
2858 }
2859
2860 flags = cpu_flags_or (cpu_arch_flags,
2861 cpu_arch[j].flags);
2862
2863 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2864 {
2865 if (cpu_sub_arch_name)
2866 {
2867 char *name = cpu_sub_arch_name;
2868 cpu_sub_arch_name = concat (name,
2869 cpu_arch[j].name,
2870 (const char *) NULL);
2871 free (name);
2872 }
2873 else
2874 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2875 cpu_arch_flags = flags;
2876 cpu_arch_isa_flags = flags;
2877 }
2878 else
2879 cpu_arch_isa_flags
2880 = cpu_flags_or (cpu_arch_isa_flags,
2881 cpu_arch[j].flags);
2882 (void) restore_line_pointer (e);
2883 demand_empty_rest_of_line ();
2884 return;
2885 }
2886 }
2887
2888 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2889 {
2890 /* Disable an ISA extension. */
2891 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2892 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2893 {
2894 flags = cpu_flags_and_not (cpu_arch_flags,
2895 cpu_noarch[j].flags);
2896 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2897 {
2898 if (cpu_sub_arch_name)
2899 {
2900 char *name = cpu_sub_arch_name;
2901 cpu_sub_arch_name = concat (name, string,
2902 (const char *) NULL);
2903 free (name);
2904 }
2905 else
2906 cpu_sub_arch_name = xstrdup (string);
2907 cpu_arch_flags = flags;
2908 cpu_arch_isa_flags = flags;
2909 }
2910 (void) restore_line_pointer (e);
2911 demand_empty_rest_of_line ();
2912 return;
2913 }
2914
2915 j = ARRAY_SIZE (cpu_arch);
2916 }
2917
2918 if (j >= ARRAY_SIZE (cpu_arch))
2919 as_bad (_("no such architecture: `%s'"), string);
2920
2921 *input_line_pointer = e;
2922 }
2923 else
2924 as_bad (_("missing cpu architecture"));
2925
2926 no_cond_jump_promotion = 0;
2927 if (*input_line_pointer == ','
2928 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2929 {
2930 char *string;
2931 char e;
2932
2933 ++input_line_pointer;
2934 e = get_symbol_name (&string);
2935
2936 if (strcmp (string, "nojumps") == 0)
2937 no_cond_jump_promotion = 1;
2938 else if (strcmp (string, "jumps") == 0)
2939 ;
2940 else
2941 as_bad (_("no such architecture modifier: `%s'"), string);
2942
2943 (void) restore_line_pointer (e);
2944 }
2945
2946 demand_empty_rest_of_line ();
2947}
2948
2949enum bfd_architecture
2950i386_arch (void)
2951{
2952 if (cpu_arch_isa == PROCESSOR_L1OM)
2953 {
2954 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2955 || flag_code != CODE_64BIT)
2956 as_fatal (_("Intel L1OM is 64bit ELF only"));
2957 return bfd_arch_l1om;
2958 }
2959 else if (cpu_arch_isa == PROCESSOR_K1OM)
2960 {
2961 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2962 || flag_code != CODE_64BIT)
2963 as_fatal (_("Intel K1OM is 64bit ELF only"));
2964 return bfd_arch_k1om;
2965 }
2966 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2967 {
2968 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2969 || flag_code == CODE_64BIT)
2970 as_fatal (_("Intel MCU is 32bit ELF only"));
2971 return bfd_arch_iamcu;
2972 }
2973 else
2974 return bfd_arch_i386;
2975}
2976
2977unsigned long
2978i386_mach (void)
2979{
2980 if (!strncmp (default_arch, "x86_64", 6))
2981 {
2982 if (cpu_arch_isa == PROCESSOR_L1OM)
2983 {
2984 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2985 || default_arch[6] != '\0')
2986 as_fatal (_("Intel L1OM is 64bit ELF only"));
2987 return bfd_mach_l1om;
2988 }
2989 else if (cpu_arch_isa == PROCESSOR_K1OM)
2990 {
2991 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2992 || default_arch[6] != '\0')
2993 as_fatal (_("Intel K1OM is 64bit ELF only"));
2994 return bfd_mach_k1om;
2995 }
2996 else if (default_arch[6] == '\0')
2997 return bfd_mach_x86_64;
2998 else
2999 return bfd_mach_x64_32;
3000 }
3001 else if (!strcmp (default_arch, "i386")
3002 || !strcmp (default_arch, "iamcu"))
3003 {
3004 if (cpu_arch_isa == PROCESSOR_IAMCU)
3005 {
3006 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
3007 as_fatal (_("Intel MCU is 32bit ELF only"));
3008 return bfd_mach_i386_iamcu;
3009 }
3010 else
3011 return bfd_mach_i386_i386;
3012 }
3013 else
3014 as_fatal (_("unknown architecture"));
3015}
3016\f
3017void
3018md_begin (void)
3019{
3020 const char *hash_err;
3021
3022 /* Support pseudo prefixes like {disp32}. */
3023 lex_type ['{'] = LEX_BEGIN_NAME;
3024
3025 /* Initialize op_hash hash table. */
3026 op_hash = hash_new ();
3027
3028 {
3029 const insn_template *optab;
3030 templates *core_optab;
3031
3032 /* Setup for loop. */
3033 optab = i386_optab;
3034 core_optab = XNEW (templates);
3035 core_optab->start = optab;
3036
3037 while (1)
3038 {
3039 ++optab;
3040 if (optab->name == NULL
3041 || strcmp (optab->name, (optab - 1)->name) != 0)
3042 {
3043 /* different name --> ship out current template list;
3044 add to hash table; & begin anew. */
3045 core_optab->end = optab;
3046 hash_err = hash_insert (op_hash,
3047 (optab - 1)->name,
3048 (void *) core_optab);
3049 if (hash_err)
3050 {
3051 as_fatal (_("can't hash %s: %s"),
3052 (optab - 1)->name,
3053 hash_err);
3054 }
3055 if (optab->name == NULL)
3056 break;
3057 core_optab = XNEW (templates);
3058 core_optab->start = optab;
3059 }
3060 }
3061 }
3062
3063 /* Initialize reg_hash hash table. */
3064 reg_hash = hash_new ();
3065 {
3066 const reg_entry *regtab;
3067 unsigned int regtab_size = i386_regtab_size;
3068
3069 for (regtab = i386_regtab; regtab_size--; regtab++)
3070 {
3071 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
3072 if (hash_err)
3073 as_fatal (_("can't hash %s: %s"),
3074 regtab->reg_name,
3075 hash_err);
3076 }
3077 }
3078
3079 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3080 {
3081 int c;
3082 char *p;
3083
3084 for (c = 0; c < 256; c++)
3085 {
3086 if (ISDIGIT (c))
3087 {
3088 digit_chars[c] = c;
3089 mnemonic_chars[c] = c;
3090 register_chars[c] = c;
3091 operand_chars[c] = c;
3092 }
3093 else if (ISLOWER (c))
3094 {
3095 mnemonic_chars[c] = c;
3096 register_chars[c] = c;
3097 operand_chars[c] = c;
3098 }
3099 else if (ISUPPER (c))
3100 {
3101 mnemonic_chars[c] = TOLOWER (c);
3102 register_chars[c] = mnemonic_chars[c];
3103 operand_chars[c] = c;
3104 }
3105 else if (c == '{' || c == '}')
3106 {
3107 mnemonic_chars[c] = c;
3108 operand_chars[c] = c;
3109 }
3110
3111 if (ISALPHA (c) || ISDIGIT (c))
3112 identifier_chars[c] = c;
3113 else if (c >= 128)
3114 {
3115 identifier_chars[c] = c;
3116 operand_chars[c] = c;
3117 }
3118 }
3119
3120#ifdef LEX_AT
3121 identifier_chars['@'] = '@';
3122#endif
3123#ifdef LEX_QM
3124 identifier_chars['?'] = '?';
3125 operand_chars['?'] = '?';
3126#endif
3127 digit_chars['-'] = '-';
3128 mnemonic_chars['_'] = '_';
3129 mnemonic_chars['-'] = '-';
3130 mnemonic_chars['.'] = '.';
3131 identifier_chars['_'] = '_';
3132 identifier_chars['.'] = '.';
3133
3134 for (p = operand_special_chars; *p != '\0'; p++)
3135 operand_chars[(unsigned char) *p] = *p;
3136 }
3137
3138 if (flag_code == CODE_64BIT)
3139 {
3140#if defined (OBJ_COFF) && defined (TE_PE)
3141 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
3142 ? 32 : 16);
3143#else
3144 x86_dwarf2_return_column = 16;
3145#endif
3146 x86_cie_data_alignment = -8;
3147 }
3148 else
3149 {
3150 x86_dwarf2_return_column = 8;
3151 x86_cie_data_alignment = -4;
3152 }
3153
3154 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3155 can be turned into BRANCH_PREFIX frag. */
3156 if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE)
3157 abort ();
3158}
3159
3160void
3161i386_print_statistics (FILE *file)
3162{
3163 hash_print_statistics (file, "i386 opcode", op_hash);
3164 hash_print_statistics (file, "i386 register", reg_hash);
3165}
3166\f
3167#ifdef DEBUG386
3168
3169/* Debugging routines for md_assemble. */
3170static void pte (insn_template *);
3171static void pt (i386_operand_type);
3172static void pe (expressionS *);
3173static void ps (symbolS *);
3174
3175static void
3176pi (const char *line, i386_insn *x)
3177{
3178 unsigned int j;
3179
3180 fprintf (stdout, "%s: template ", line);
3181 pte (&x->tm);
3182 fprintf (stdout, " address: base %s index %s scale %x\n",
3183 x->base_reg ? x->base_reg->reg_name : "none",
3184 x->index_reg ? x->index_reg->reg_name : "none",
3185 x->log2_scale_factor);
3186 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
3187 x->rm.mode, x->rm.reg, x->rm.regmem);
3188 fprintf (stdout, " sib: base %x index %x scale %x\n",
3189 x->sib.base, x->sib.index, x->sib.scale);
3190 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
3191 (x->rex & REX_W) != 0,
3192 (x->rex & REX_R) != 0,
3193 (x->rex & REX_X) != 0,
3194 (x->rex & REX_B) != 0);
3195 for (j = 0; j < x->operands; j++)
3196 {
3197 fprintf (stdout, " #%d: ", j + 1);
3198 pt (x->types[j]);
3199 fprintf (stdout, "\n");
3200 if (x->types[j].bitfield.class == Reg
3201 || x->types[j].bitfield.class == RegMMX
3202 || x->types[j].bitfield.class == RegSIMD
3203 || x->types[j].bitfield.class == RegMask
3204 || x->types[j].bitfield.class == SReg
3205 || x->types[j].bitfield.class == RegCR
3206 || x->types[j].bitfield.class == RegDR
3207 || x->types[j].bitfield.class == RegTR
3208 || x->types[j].bitfield.class == RegBND)
3209 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3210 if (operand_type_check (x->types[j], imm))
3211 pe (x->op[j].imms);
3212 if (operand_type_check (x->types[j], disp))
3213 pe (x->op[j].disps);
3214 }
3215}
3216
3217static void
3218pte (insn_template *t)
3219{
3220 unsigned int j;
3221 fprintf (stdout, " %d operands ", t->operands);
3222 fprintf (stdout, "opcode %x ", t->base_opcode);
3223 if (t->extension_opcode != None)
3224 fprintf (stdout, "ext %x ", t->extension_opcode);
3225 if (t->opcode_modifier.d)
3226 fprintf (stdout, "D");
3227 if (t->opcode_modifier.w)
3228 fprintf (stdout, "W");
3229 fprintf (stdout, "\n");
3230 for (j = 0; j < t->operands; j++)
3231 {
3232 fprintf (stdout, " #%d type ", j + 1);
3233 pt (t->operand_types[j]);
3234 fprintf (stdout, "\n");
3235 }
3236}
3237
3238static void
3239pe (expressionS *e)
3240{
3241 fprintf (stdout, " operation %d\n", e->X_op);
3242 fprintf (stdout, " add_number %ld (%lx)\n",
3243 (long) e->X_add_number, (long) e->X_add_number);
3244 if (e->X_add_symbol)
3245 {
3246 fprintf (stdout, " add_symbol ");
3247 ps (e->X_add_symbol);
3248 fprintf (stdout, "\n");
3249 }
3250 if (e->X_op_symbol)
3251 {
3252 fprintf (stdout, " op_symbol ");
3253 ps (e->X_op_symbol);
3254 fprintf (stdout, "\n");
3255 }
3256}
3257
3258static void
3259ps (symbolS *s)
3260{
3261 fprintf (stdout, "%s type %s%s",
3262 S_GET_NAME (s),
3263 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3264 segment_name (S_GET_SEGMENT (s)));
3265}
3266
3267static struct type_name
3268 {
3269 i386_operand_type mask;
3270 const char *name;
3271 }
3272const type_names[] =
3273{
3274 { OPERAND_TYPE_REG8, "r8" },
3275 { OPERAND_TYPE_REG16, "r16" },
3276 { OPERAND_TYPE_REG32, "r32" },
3277 { OPERAND_TYPE_REG64, "r64" },
3278 { OPERAND_TYPE_ACC8, "acc8" },
3279 { OPERAND_TYPE_ACC16, "acc16" },
3280 { OPERAND_TYPE_ACC32, "acc32" },
3281 { OPERAND_TYPE_ACC64, "acc64" },
3282 { OPERAND_TYPE_IMM8, "i8" },
3283 { OPERAND_TYPE_IMM8, "i8s" },
3284 { OPERAND_TYPE_IMM16, "i16" },
3285 { OPERAND_TYPE_IMM32, "i32" },
3286 { OPERAND_TYPE_IMM32S, "i32s" },
3287 { OPERAND_TYPE_IMM64, "i64" },
3288 { OPERAND_TYPE_IMM1, "i1" },
3289 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3290 { OPERAND_TYPE_DISP8, "d8" },
3291 { OPERAND_TYPE_DISP16, "d16" },
3292 { OPERAND_TYPE_DISP32, "d32" },
3293 { OPERAND_TYPE_DISP32S, "d32s" },
3294 { OPERAND_TYPE_DISP64, "d64" },
3295 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3296 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3297 { OPERAND_TYPE_CONTROL, "control reg" },
3298 { OPERAND_TYPE_TEST, "test reg" },
3299 { OPERAND_TYPE_DEBUG, "debug reg" },
3300 { OPERAND_TYPE_FLOATREG, "FReg" },
3301 { OPERAND_TYPE_FLOATACC, "FAcc" },
3302 { OPERAND_TYPE_SREG, "SReg" },
3303 { OPERAND_TYPE_REGMMX, "rMMX" },
3304 { OPERAND_TYPE_REGXMM, "rXMM" },
3305 { OPERAND_TYPE_REGYMM, "rYMM" },
3306 { OPERAND_TYPE_REGZMM, "rZMM" },
3307 { OPERAND_TYPE_REGMASK, "Mask reg" },
3308};
3309
3310static void
3311pt (i386_operand_type t)
3312{
3313 unsigned int j;
3314 i386_operand_type a;
3315
3316 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3317 {
3318 a = operand_type_and (t, type_names[j].mask);
3319 if (operand_type_equal (&a, &type_names[j].mask))
3320 fprintf (stdout, "%s, ", type_names[j].name);
3321 }
3322 fflush (stdout);
3323}
3324
3325#endif /* DEBUG386 */
3326\f
3327static bfd_reloc_code_real_type
3328reloc (unsigned int size,
3329 int pcrel,
3330 int sign,
3331 bfd_reloc_code_real_type other)
3332{
3333 if (other != NO_RELOC)
3334 {
3335 reloc_howto_type *rel;
3336
3337 if (size == 8)
3338 switch (other)
3339 {
3340 case BFD_RELOC_X86_64_GOT32:
3341 return BFD_RELOC_X86_64_GOT64;
3342 break;
3343 case BFD_RELOC_X86_64_GOTPLT64:
3344 return BFD_RELOC_X86_64_GOTPLT64;
3345 break;
3346 case BFD_RELOC_X86_64_PLTOFF64:
3347 return BFD_RELOC_X86_64_PLTOFF64;
3348 break;
3349 case BFD_RELOC_X86_64_GOTPC32:
3350 other = BFD_RELOC_X86_64_GOTPC64;
3351 break;
3352 case BFD_RELOC_X86_64_GOTPCREL:
3353 other = BFD_RELOC_X86_64_GOTPCREL64;
3354 break;
3355 case BFD_RELOC_X86_64_TPOFF32:
3356 other = BFD_RELOC_X86_64_TPOFF64;
3357 break;
3358 case BFD_RELOC_X86_64_DTPOFF32:
3359 other = BFD_RELOC_X86_64_DTPOFF64;
3360 break;
3361 default:
3362 break;
3363 }
3364
3365#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3366 if (other == BFD_RELOC_SIZE32)
3367 {
3368 if (size == 8)
3369 other = BFD_RELOC_SIZE64;
3370 if (pcrel)
3371 {
3372 as_bad (_("there are no pc-relative size relocations"));
3373 return NO_RELOC;
3374 }
3375 }
3376#endif
3377
3378 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3379 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3380 sign = -1;
3381
3382 rel = bfd_reloc_type_lookup (stdoutput, other);
3383 if (!rel)
3384 as_bad (_("unknown relocation (%u)"), other);
3385 else if (size != bfd_get_reloc_size (rel))
3386 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3387 bfd_get_reloc_size (rel),
3388 size);
3389 else if (pcrel && !rel->pc_relative)
3390 as_bad (_("non-pc-relative relocation for pc-relative field"));
3391 else if ((rel->complain_on_overflow == complain_overflow_signed
3392 && !sign)
3393 || (rel->complain_on_overflow == complain_overflow_unsigned
3394 && sign > 0))
3395 as_bad (_("relocated field and relocation type differ in signedness"));
3396 else
3397 return other;
3398 return NO_RELOC;
3399 }
3400
3401 if (pcrel)
3402 {
3403 if (!sign)
3404 as_bad (_("there are no unsigned pc-relative relocations"));
3405 switch (size)
3406 {
3407 case 1: return BFD_RELOC_8_PCREL;
3408 case 2: return BFD_RELOC_16_PCREL;
3409 case 4: return BFD_RELOC_32_PCREL;
3410 case 8: return BFD_RELOC_64_PCREL;
3411 }
3412 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3413 }
3414 else
3415 {
3416 if (sign > 0)
3417 switch (size)
3418 {
3419 case 4: return BFD_RELOC_X86_64_32S;
3420 }
3421 else
3422 switch (size)
3423 {
3424 case 1: return BFD_RELOC_8;
3425 case 2: return BFD_RELOC_16;
3426 case 4: return BFD_RELOC_32;
3427 case 8: return BFD_RELOC_64;
3428 }
3429 as_bad (_("cannot do %s %u byte relocation"),
3430 sign > 0 ? "signed" : "unsigned", size);
3431 }
3432
3433 return NO_RELOC;
3434}
3435
3436/* Here we decide which fixups can be adjusted to make them relative to
3437 the beginning of the section instead of the symbol. Basically we need
3438 to make sure that the dynamic relocations are done correctly, so in
3439 some cases we force the original symbol to be used. */
3440
3441int
3442tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3443{
3444#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3445 if (!IS_ELF)
3446 return 1;
3447
3448 /* Don't adjust pc-relative references to merge sections in 64-bit
3449 mode. */
3450 if (use_rela_relocations
3451 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3452 && fixP->fx_pcrel)
3453 return 0;
3454
3455 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3456 and changed later by validate_fix. */
3457 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3458 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3459 return 0;
3460
3461 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3462 for size relocations. */
3463 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3464 || fixP->fx_r_type == BFD_RELOC_SIZE64
3465 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3466 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3467 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3468 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3469 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3470 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3471 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3472 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3473 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3474 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3475 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3476 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3477 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3478 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3479 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3480 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3481 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3482 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3483 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3484 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3485 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3486 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3487 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3488 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3489 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3490 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3491 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3492 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3493 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3494 return 0;
3495#endif
3496 return 1;
3497}
3498
3499static int
3500intel_float_operand (const char *mnemonic)
3501{
3502 /* Note that the value returned is meaningful only for opcodes with (memory)
3503 operands, hence the code here is free to improperly handle opcodes that
3504 have no operands (for better performance and smaller code). */
3505
3506 if (mnemonic[0] != 'f')
3507 return 0; /* non-math */
3508
3509 switch (mnemonic[1])
3510 {
3511 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3512 the fs segment override prefix not currently handled because no
3513 call path can make opcodes without operands get here */
3514 case 'i':
3515 return 2 /* integer op */;
3516 case 'l':
3517 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3518 return 3; /* fldcw/fldenv */
3519 break;
3520 case 'n':
3521 if (mnemonic[2] != 'o' /* fnop */)
3522 return 3; /* non-waiting control op */
3523 break;
3524 case 'r':
3525 if (mnemonic[2] == 's')
3526 return 3; /* frstor/frstpm */
3527 break;
3528 case 's':
3529 if (mnemonic[2] == 'a')
3530 return 3; /* fsave */
3531 if (mnemonic[2] == 't')
3532 {
3533 switch (mnemonic[3])
3534 {
3535 case 'c': /* fstcw */
3536 case 'd': /* fstdw */
3537 case 'e': /* fstenv */
3538 case 's': /* fsts[gw] */
3539 return 3;
3540 }
3541 }
3542 break;
3543 case 'x':
3544 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3545 return 0; /* fxsave/fxrstor are not really math ops */
3546 break;
3547 }
3548
3549 return 1;
3550}
3551
3552/* Build the VEX prefix. */
3553
3554static void
3555build_vex_prefix (const insn_template *t)
3556{
3557 unsigned int register_specifier;
3558 unsigned int implied_prefix;
3559 unsigned int vector_length;
3560 unsigned int w;
3561
3562 /* Check register specifier. */
3563 if (i.vex.register_specifier)
3564 {
3565 register_specifier =
3566 ~register_number (i.vex.register_specifier) & 0xf;
3567 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3568 }
3569 else
3570 register_specifier = 0xf;
3571
3572 /* Use 2-byte VEX prefix by swapping destination and source operand
3573 if there are more than 1 register operand. */
3574 if (i.reg_operands > 1
3575 && i.vec_encoding != vex_encoding_vex3
3576 && i.dir_encoding == dir_encoding_default
3577 && i.operands == i.reg_operands
3578 && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
3579 && i.tm.opcode_modifier.vexopcode == VEX0F
3580 && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
3581 && i.rex == REX_B)
3582 {
3583 unsigned int xchg = i.operands - 1;
3584 union i386_op temp_op;
3585 i386_operand_type temp_type;
3586
3587 temp_type = i.types[xchg];
3588 i.types[xchg] = i.types[0];
3589 i.types[0] = temp_type;
3590 temp_op = i.op[xchg];
3591 i.op[xchg] = i.op[0];
3592 i.op[0] = temp_op;
3593
3594 gas_assert (i.rm.mode == 3);
3595
3596 i.rex = REX_R;
3597 xchg = i.rm.regmem;
3598 i.rm.regmem = i.rm.reg;
3599 i.rm.reg = xchg;
3600
3601 if (i.tm.opcode_modifier.d)
3602 i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
3603 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
3604 else /* Use the next insn. */
3605 i.tm = t[1];
3606 }
3607
3608 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3609 are no memory operands and at least 3 register ones. */
3610 if (i.reg_operands >= 3
3611 && i.vec_encoding != vex_encoding_vex3
3612 && i.reg_operands == i.operands - i.imm_operands
3613 && i.tm.opcode_modifier.vex
3614 && i.tm.opcode_modifier.commutative
3615 && (i.tm.opcode_modifier.sse2avx || optimize > 1)
3616 && i.rex == REX_B
3617 && i.vex.register_specifier
3618 && !(i.vex.register_specifier->reg_flags & RegRex))
3619 {
3620 unsigned int xchg = i.operands - i.reg_operands;
3621 union i386_op temp_op;
3622 i386_operand_type temp_type;
3623
3624 gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F);
3625 gas_assert (!i.tm.opcode_modifier.sae);
3626 gas_assert (operand_type_equal (&i.types[i.operands - 2],
3627 &i.types[i.operands - 3]));
3628 gas_assert (i.rm.mode == 3);
3629
3630 temp_type = i.types[xchg];
3631 i.types[xchg] = i.types[xchg + 1];
3632 i.types[xchg + 1] = temp_type;
3633 temp_op = i.op[xchg];
3634 i.op[xchg] = i.op[xchg + 1];
3635 i.op[xchg + 1] = temp_op;
3636
3637 i.rex = 0;
3638 xchg = i.rm.regmem | 8;
3639 i.rm.regmem = ~register_specifier & 0xf;
3640 gas_assert (!(i.rm.regmem & 8));
3641 i.vex.register_specifier += xchg - i.rm.regmem;
3642 register_specifier = ~xchg & 0xf;
3643 }
3644
3645 if (i.tm.opcode_modifier.vex == VEXScalar)
3646 vector_length = avxscalar;
3647 else if (i.tm.opcode_modifier.vex == VEX256)
3648 vector_length = 1;
3649 else
3650 {
3651 unsigned int op;
3652
3653 /* Determine vector length from the last multi-length vector
3654 operand. */
3655 vector_length = 0;
3656 for (op = t->operands; op--;)
3657 if (t->operand_types[op].bitfield.xmmword
3658 && t->operand_types[op].bitfield.ymmword
3659 && i.types[op].bitfield.ymmword)
3660 {
3661 vector_length = 1;
3662 break;
3663 }
3664 }
3665
3666 switch ((i.tm.base_opcode >> 8) & 0xff)
3667 {
3668 case 0:
3669 implied_prefix = 0;
3670 break;
3671 case DATA_PREFIX_OPCODE:
3672 implied_prefix = 1;
3673 break;
3674 case REPE_PREFIX_OPCODE:
3675 implied_prefix = 2;
3676 break;
3677 case REPNE_PREFIX_OPCODE:
3678 implied_prefix = 3;
3679 break;
3680 default:
3681 abort ();
3682 }
3683
3684 /* Check the REX.W bit and VEXW. */
3685 if (i.tm.opcode_modifier.vexw == VEXWIG)
3686 w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
3687 else if (i.tm.opcode_modifier.vexw)
3688 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3689 else
3690 w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0;
3691
3692 /* Use 2-byte VEX prefix if possible. */
3693 if (w == 0
3694 && i.vec_encoding != vex_encoding_vex3
3695 && i.tm.opcode_modifier.vexopcode == VEX0F
3696 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3697 {
3698 /* 2-byte VEX prefix. */
3699 unsigned int r;
3700
3701 i.vex.length = 2;
3702 i.vex.bytes[0] = 0xc5;
3703
3704 /* Check the REX.R bit. */
3705 r = (i.rex & REX_R) ? 0 : 1;
3706 i.vex.bytes[1] = (r << 7
3707 | register_specifier << 3
3708 | vector_length << 2
3709 | implied_prefix);
3710 }
3711 else
3712 {
3713 /* 3-byte VEX prefix. */
3714 unsigned int m;
3715
3716 i.vex.length = 3;
3717
3718 switch (i.tm.opcode_modifier.vexopcode)
3719 {
3720 case VEX0F:
3721 m = 0x1;
3722 i.vex.bytes[0] = 0xc4;
3723 break;
3724 case VEX0F38:
3725 m = 0x2;
3726 i.vex.bytes[0] = 0xc4;
3727 break;
3728 case VEX0F3A:
3729 m = 0x3;
3730 i.vex.bytes[0] = 0xc4;
3731 break;
3732 case XOP08:
3733 m = 0x8;
3734 i.vex.bytes[0] = 0x8f;
3735 break;
3736 case XOP09:
3737 m = 0x9;
3738 i.vex.bytes[0] = 0x8f;
3739 break;
3740 case XOP0A:
3741 m = 0xa;
3742 i.vex.bytes[0] = 0x8f;
3743 break;
3744 default:
3745 abort ();
3746 }
3747
3748 /* The high 3 bits of the second VEX byte are 1's compliment
3749 of RXB bits from REX. */
3750 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3751
3752 i.vex.bytes[2] = (w << 7
3753 | register_specifier << 3
3754 | vector_length << 2
3755 | implied_prefix);
3756 }
3757}
3758
3759static INLINE bfd_boolean
3760is_evex_encoding (const insn_template *t)
3761{
3762 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3763 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3764 || t->opcode_modifier.sae;
3765}
3766
3767static INLINE bfd_boolean
3768is_any_vex_encoding (const insn_template *t)
3769{
3770 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3771 || is_evex_encoding (t);
3772}
3773
3774/* Build the EVEX prefix. */
3775
3776static void
3777build_evex_prefix (void)
3778{
3779 unsigned int register_specifier;
3780 unsigned int implied_prefix;
3781 unsigned int m, w;
3782 rex_byte vrex_used = 0;
3783
3784 /* Check register specifier. */
3785 if (i.vex.register_specifier)
3786 {
3787 gas_assert ((i.vrex & REX_X) == 0);
3788
3789 register_specifier = i.vex.register_specifier->reg_num;
3790 if ((i.vex.register_specifier->reg_flags & RegRex))
3791 register_specifier += 8;
3792 /* The upper 16 registers are encoded in the fourth byte of the
3793 EVEX prefix. */
3794 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3795 i.vex.bytes[3] = 0x8;
3796 register_specifier = ~register_specifier & 0xf;
3797 }
3798 else
3799 {
3800 register_specifier = 0xf;
3801
3802 /* Encode upper 16 vector index register in the fourth byte of
3803 the EVEX prefix. */
3804 if (!(i.vrex & REX_X))
3805 i.vex.bytes[3] = 0x8;
3806 else
3807 vrex_used |= REX_X;
3808 }
3809
3810 switch ((i.tm.base_opcode >> 8) & 0xff)
3811 {
3812 case 0:
3813 implied_prefix = 0;
3814 break;
3815 case DATA_PREFIX_OPCODE:
3816 implied_prefix = 1;
3817 break;
3818 case REPE_PREFIX_OPCODE:
3819 implied_prefix = 2;
3820 break;
3821 case REPNE_PREFIX_OPCODE:
3822 implied_prefix = 3;
3823 break;
3824 default:
3825 abort ();
3826 }
3827
3828 /* 4 byte EVEX prefix. */
3829 i.vex.length = 4;
3830 i.vex.bytes[0] = 0x62;
3831
3832 /* mmmm bits. */
3833 switch (i.tm.opcode_modifier.vexopcode)
3834 {
3835 case VEX0F:
3836 m = 1;
3837 break;
3838 case VEX0F38:
3839 m = 2;
3840 break;
3841 case VEX0F3A:
3842 m = 3;
3843 break;
3844 default:
3845 abort ();
3846 break;
3847 }
3848
3849 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3850 bits from REX. */
3851 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3852
3853 /* The fifth bit of the second EVEX byte is 1's compliment of the
3854 REX_R bit in VREX. */
3855 if (!(i.vrex & REX_R))
3856 i.vex.bytes[1] |= 0x10;
3857 else
3858 vrex_used |= REX_R;
3859
3860 if ((i.reg_operands + i.imm_operands) == i.operands)
3861 {
3862 /* When all operands are registers, the REX_X bit in REX is not
3863 used. We reuse it to encode the upper 16 registers, which is
3864 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3865 as 1's compliment. */
3866 if ((i.vrex & REX_B))
3867 {
3868 vrex_used |= REX_B;
3869 i.vex.bytes[1] &= ~0x40;
3870 }
3871 }
3872
3873 /* EVEX instructions shouldn't need the REX prefix. */
3874 i.vrex &= ~vrex_used;
3875 gas_assert (i.vrex == 0);
3876
3877 /* Check the REX.W bit and VEXW. */
3878 if (i.tm.opcode_modifier.vexw == VEXWIG)
3879 w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
3880 else if (i.tm.opcode_modifier.vexw)
3881 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3882 else
3883 w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
3884
3885 /* Encode the U bit. */
3886 implied_prefix |= 0x4;
3887
3888 /* The third byte of the EVEX prefix. */
3889 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3890
3891 /* The fourth byte of the EVEX prefix. */
3892 /* The zeroing-masking bit. */
3893 if (i.mask && i.mask->zeroing)
3894 i.vex.bytes[3] |= 0x80;
3895
3896 /* Don't always set the broadcast bit if there is no RC. */
3897 if (!i.rounding)
3898 {
3899 /* Encode the vector length. */
3900 unsigned int vec_length;
3901
3902 if (!i.tm.opcode_modifier.evex
3903 || i.tm.opcode_modifier.evex == EVEXDYN)
3904 {
3905 unsigned int op;
3906
3907 /* Determine vector length from the last multi-length vector
3908 operand. */
3909 vec_length = 0;
3910 for (op = i.operands; op--;)
3911 if (i.tm.operand_types[op].bitfield.xmmword
3912 + i.tm.operand_types[op].bitfield.ymmword
3913 + i.tm.operand_types[op].bitfield.zmmword > 1)
3914 {
3915 if (i.types[op].bitfield.zmmword)
3916 {
3917 i.tm.opcode_modifier.evex = EVEX512;
3918 break;
3919 }
3920 else if (i.types[op].bitfield.ymmword)
3921 {
3922 i.tm.opcode_modifier.evex = EVEX256;
3923 break;
3924 }
3925 else if (i.types[op].bitfield.xmmword)
3926 {
3927 i.tm.opcode_modifier.evex = EVEX128;
3928 break;
3929 }
3930 else if (i.broadcast && (int) op == i.broadcast->operand)
3931 {
3932 switch (i.broadcast->bytes)
3933 {
3934 case 64:
3935 i.tm.opcode_modifier.evex = EVEX512;
3936 break;
3937 case 32:
3938 i.tm.opcode_modifier.evex = EVEX256;
3939 break;
3940 case 16:
3941 i.tm.opcode_modifier.evex = EVEX128;
3942 break;
3943 default:
3944 abort ();
3945 }
3946 break;
3947 }
3948 }
3949
3950 if (op >= MAX_OPERANDS)
3951 abort ();
3952 }
3953
3954 switch (i.tm.opcode_modifier.evex)
3955 {
3956 case EVEXLIG: /* LL' is ignored */
3957 vec_length = evexlig << 5;
3958 break;
3959 case EVEX128:
3960 vec_length = 0 << 5;
3961 break;
3962 case EVEX256:
3963 vec_length = 1 << 5;
3964 break;
3965 case EVEX512:
3966 vec_length = 2 << 5;
3967 break;
3968 default:
3969 abort ();
3970 break;
3971 }
3972 i.vex.bytes[3] |= vec_length;
3973 /* Encode the broadcast bit. */
3974 if (i.broadcast)
3975 i.vex.bytes[3] |= 0x10;
3976 }
3977 else
3978 {
3979 if (i.rounding->type != saeonly)
3980 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3981 else
3982 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3983 }
3984
3985 if (i.mask && i.mask->mask)
3986 i.vex.bytes[3] |= i.mask->mask->reg_num;
3987}
3988
3989static void
3990process_immext (void)
3991{
3992 expressionS *exp;
3993
3994 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3995 which is coded in the same place as an 8-bit immediate field
3996 would be. Here we fake an 8-bit immediate operand from the
3997 opcode suffix stored in tm.extension_opcode.
3998
3999 AVX instructions also use this encoding, for some of
4000 3 argument instructions. */
4001
4002 gas_assert (i.imm_operands <= 1
4003 && (i.operands <= 2
4004 || (is_any_vex_encoding (&i.tm)
4005 && i.operands <= 4)));
4006
4007 exp = &im_expressions[i.imm_operands++];
4008 i.op[i.operands].imms = exp;
4009 i.types[i.operands] = imm8;
4010 i.operands++;
4011 exp->X_op = O_constant;
4012 exp->X_add_number = i.tm.extension_opcode;
4013 i.tm.extension_opcode = None;
4014}
4015
4016
4017static int
4018check_hle (void)
4019{
4020 switch (i.tm.opcode_modifier.hleprefixok)
4021 {
4022 default:
4023 abort ();
4024 case HLEPrefixNone:
4025 as_bad (_("invalid instruction `%s' after `%s'"),
4026 i.tm.name, i.hle_prefix);
4027 return 0;
4028 case HLEPrefixLock:
4029 if (i.prefix[LOCK_PREFIX])
4030 return 1;
4031 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
4032 return 0;
4033 case HLEPrefixAny:
4034 return 1;
4035 case HLEPrefixRelease:
4036 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
4037 {
4038 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4039 i.tm.name);
4040 return 0;
4041 }
4042 if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem))
4043 {
4044 as_bad (_("memory destination needed for instruction `%s'"
4045 " after `xrelease'"), i.tm.name);
4046 return 0;
4047 }
4048 return 1;
4049 }
4050}
4051
4052/* Try the shortest encoding by shortening operand size. */
4053
4054static void
4055optimize_encoding (void)
4056{
4057 unsigned int j;
4058
4059 if (optimize_for_space
4060 && !is_any_vex_encoding (&i.tm)
4061 && i.reg_operands == 1
4062 && i.imm_operands == 1
4063 && !i.types[1].bitfield.byte
4064 && i.op[0].imms->X_op == O_constant
4065 && fits_in_imm7 (i.op[0].imms->X_add_number)
4066 && (i.tm.base_opcode == 0xa8
4067 || (i.tm.base_opcode == 0xf6
4068 && i.tm.extension_opcode == 0x0)))
4069 {
4070 /* Optimize: -Os:
4071 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4072 */
4073 unsigned int base_regnum = i.op[1].regs->reg_num;
4074 if (flag_code == CODE_64BIT || base_regnum < 4)
4075 {
4076 i.types[1].bitfield.byte = 1;
4077 /* Ignore the suffix. */
4078 i.suffix = 0;
4079 /* Convert to byte registers. */
4080 if (i.types[1].bitfield.word)
4081 j = 16;
4082 else if (i.types[1].bitfield.dword)
4083 j = 32;
4084 else
4085 j = 48;
4086 if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4)
4087 j += 8;
4088 i.op[1].regs -= j;
4089 }
4090 }
4091 else if (flag_code == CODE_64BIT
4092 && !is_any_vex_encoding (&i.tm)
4093 && ((i.types[1].bitfield.qword
4094 && i.reg_operands == 1
4095 && i.imm_operands == 1
4096 && i.op[0].imms->X_op == O_constant
4097 && ((i.tm.base_opcode == 0xb8
4098 && i.tm.extension_opcode == None
4099 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
4100 || (fits_in_imm31 (i.op[0].imms->X_add_number)
4101 && ((i.tm.base_opcode == 0x24
4102 || i.tm.base_opcode == 0xa8)
4103 || (i.tm.base_opcode == 0x80
4104 && i.tm.extension_opcode == 0x4)
4105 || ((i.tm.base_opcode == 0xf6
4106 || (i.tm.base_opcode | 1) == 0xc7)
4107 && i.tm.extension_opcode == 0x0)))
4108 || (fits_in_imm7 (i.op[0].imms->X_add_number)
4109 && i.tm.base_opcode == 0x83
4110 && i.tm.extension_opcode == 0x4)))
4111 || (i.types[0].bitfield.qword
4112 && ((i.reg_operands == 2
4113 && i.op[0].regs == i.op[1].regs
4114 && (i.tm.base_opcode == 0x30
4115 || i.tm.base_opcode == 0x28))
4116 || (i.reg_operands == 1
4117 && i.operands == 1
4118 && i.tm.base_opcode == 0x30)))))
4119 {
4120 /* Optimize: -O:
4121 andq $imm31, %r64 -> andl $imm31, %r32
4122 andq $imm7, %r64 -> andl $imm7, %r32
4123 testq $imm31, %r64 -> testl $imm31, %r32
4124 xorq %r64, %r64 -> xorl %r32, %r32
4125 subq %r64, %r64 -> subl %r32, %r32
4126 movq $imm31, %r64 -> movl $imm31, %r32
4127 movq $imm32, %r64 -> movl $imm32, %r32
4128 */
4129 i.tm.opcode_modifier.norex64 = 1;
4130 if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7)
4131 {
4132 /* Handle
4133 movq $imm31, %r64 -> movl $imm31, %r32
4134 movq $imm32, %r64 -> movl $imm32, %r32
4135 */
4136 i.tm.operand_types[0].bitfield.imm32 = 1;
4137 i.tm.operand_types[0].bitfield.imm32s = 0;
4138 i.tm.operand_types[0].bitfield.imm64 = 0;
4139 i.types[0].bitfield.imm32 = 1;
4140 i.types[0].bitfield.imm32s = 0;
4141 i.types[0].bitfield.imm64 = 0;
4142 i.types[1].bitfield.dword = 1;
4143 i.types[1].bitfield.qword = 0;
4144 if ((i.tm.base_opcode | 1) == 0xc7)
4145 {
4146 /* Handle
4147 movq $imm31, %r64 -> movl $imm31, %r32
4148 */
4149 i.tm.base_opcode = 0xb8;
4150 i.tm.extension_opcode = None;
4151 i.tm.opcode_modifier.w = 0;
4152 i.tm.opcode_modifier.modrm = 0;
4153 }
4154 }
4155 }
4156 else if (optimize > 1
4157 && !optimize_for_space
4158 && !is_any_vex_encoding (&i.tm)
4159 && i.reg_operands == 2
4160 && i.op[0].regs == i.op[1].regs
4161 && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8
4162 || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20)
4163 && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword))
4164 {
4165 /* Optimize: -O2:
4166 andb %rN, %rN -> testb %rN, %rN
4167 andw %rN, %rN -> testw %rN, %rN
4168 andq %rN, %rN -> testq %rN, %rN
4169 orb %rN, %rN -> testb %rN, %rN
4170 orw %rN, %rN -> testw %rN, %rN
4171 orq %rN, %rN -> testq %rN, %rN
4172
4173 and outside of 64-bit mode
4174
4175 andl %rN, %rN -> testl %rN, %rN
4176 orl %rN, %rN -> testl %rN, %rN
4177 */
4178 i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1);
4179 }
4180 else if (i.reg_operands == 3
4181 && i.op[0].regs == i.op[1].regs
4182 && !i.types[2].bitfield.xmmword
4183 && (i.tm.opcode_modifier.vex
4184 || ((!i.mask || i.mask->zeroing)
4185 && !i.rounding
4186 && is_evex_encoding (&i.tm)
4187 && (i.vec_encoding != vex_encoding_evex
4188 || cpu_arch_isa_flags.bitfield.cpuavx512vl
4189 || i.tm.cpu_flags.bitfield.cpuavx512vl
4190 || (i.tm.operand_types[2].bitfield.zmmword
4191 && i.types[2].bitfield.ymmword))))
4192 && ((i.tm.base_opcode == 0x55
4193 || i.tm.base_opcode == 0x6655
4194 || i.tm.base_opcode == 0x66df
4195 || i.tm.base_opcode == 0x57
4196 || i.tm.base_opcode == 0x6657
4197 || i.tm.base_opcode == 0x66ef
4198 || i.tm.base_opcode == 0x66f8
4199 || i.tm.base_opcode == 0x66f9
4200 || i.tm.base_opcode == 0x66fa
4201 || i.tm.base_opcode == 0x66fb
4202 || i.tm.base_opcode == 0x42
4203 || i.tm.base_opcode == 0x6642
4204 || i.tm.base_opcode == 0x47
4205 || i.tm.base_opcode == 0x6647)
4206 && i.tm.extension_opcode == None))
4207 {
4208 /* Optimize: -O1:
4209 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4210 vpsubq and vpsubw:
4211 EVEX VOP %zmmM, %zmmM, %zmmN
4212 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4213 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4214 EVEX VOP %ymmM, %ymmM, %ymmN
4215 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4216 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4217 VEX VOP %ymmM, %ymmM, %ymmN
4218 -> VEX VOP %xmmM, %xmmM, %xmmN
4219 VOP, one of vpandn and vpxor:
4220 VEX VOP %ymmM, %ymmM, %ymmN
4221 -> VEX VOP %xmmM, %xmmM, %xmmN
4222 VOP, one of vpandnd and vpandnq:
4223 EVEX VOP %zmmM, %zmmM, %zmmN
4224 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4225 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4226 EVEX VOP %ymmM, %ymmM, %ymmN
4227 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4228 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4229 VOP, one of vpxord and vpxorq:
4230 EVEX VOP %zmmM, %zmmM, %zmmN
4231 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4232 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4233 EVEX VOP %ymmM, %ymmM, %ymmN
4234 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4235 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4236 VOP, one of kxord and kxorq:
4237 VEX VOP %kM, %kM, %kN
4238 -> VEX kxorw %kM, %kM, %kN
4239 VOP, one of kandnd and kandnq:
4240 VEX VOP %kM, %kM, %kN
4241 -> VEX kandnw %kM, %kM, %kN
4242 */
4243 if (is_evex_encoding (&i.tm))
4244 {
4245 if (i.vec_encoding != vex_encoding_evex)
4246 {
4247 i.tm.opcode_modifier.vex = VEX128;
4248 i.tm.opcode_modifier.vexw = VEXW0;
4249 i.tm.opcode_modifier.evex = 0;
4250 }
4251 else if (optimize > 1)
4252 i.tm.opcode_modifier.evex = EVEX128;
4253 else
4254 return;
4255 }
4256 else if (i.tm.operand_types[0].bitfield.class == RegMask)
4257 {
4258 i.tm.base_opcode &= 0xff;
4259 i.tm.opcode_modifier.vexw = VEXW0;
4260 }
4261 else
4262 i.tm.opcode_modifier.vex = VEX128;
4263
4264 if (i.tm.opcode_modifier.vex)
4265 for (j = 0; j < 3; j++)
4266 {
4267 i.types[j].bitfield.xmmword = 1;
4268 i.types[j].bitfield.ymmword = 0;
4269 }
4270 }
4271 else if (i.vec_encoding != vex_encoding_evex
4272 && !i.types[0].bitfield.zmmword
4273 && !i.types[1].bitfield.zmmword
4274 && !i.mask
4275 && !i.broadcast
4276 && is_evex_encoding (&i.tm)
4277 && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f
4278 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f
4279 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f
4280 || (i.tm.base_opcode & ~4) == 0x66db
4281 || (i.tm.base_opcode & ~4) == 0x66eb)
4282 && i.tm.extension_opcode == None)
4283 {
4284 /* Optimize: -O1:
4285 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4286 vmovdqu32 and vmovdqu64:
4287 EVEX VOP %xmmM, %xmmN
4288 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4289 EVEX VOP %ymmM, %ymmN
4290 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4291 EVEX VOP %xmmM, mem
4292 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4293 EVEX VOP %ymmM, mem
4294 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4295 EVEX VOP mem, %xmmN
4296 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4297 EVEX VOP mem, %ymmN
4298 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4299 VOP, one of vpand, vpandn, vpor, vpxor:
4300 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4301 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4302 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4303 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4304 EVEX VOP{d,q} mem, %xmmM, %xmmN
4305 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4306 EVEX VOP{d,q} mem, %ymmM, %ymmN
4307 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4308 */
4309 for (j = 0; j < i.operands; j++)
4310 if (operand_type_check (i.types[j], disp)
4311 && i.op[j].disps->X_op == O_constant)
4312 {
4313 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4314 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4315 bytes, we choose EVEX Disp8 over VEX Disp32. */
4316 int evex_disp8, vex_disp8;
4317 unsigned int memshift = i.memshift;
4318 offsetT n = i.op[j].disps->X_add_number;
4319
4320 evex_disp8 = fits_in_disp8 (n);
4321 i.memshift = 0;
4322 vex_disp8 = fits_in_disp8 (n);
4323 if (evex_disp8 != vex_disp8)
4324 {
4325 i.memshift = memshift;
4326 return;
4327 }
4328
4329 i.types[j].bitfield.disp8 = vex_disp8;
4330 break;
4331 }
4332 if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f)
4333 i.tm.base_opcode ^= 0xf36f ^ 0xf26f;
4334 i.tm.opcode_modifier.vex
4335 = i.types[0].bitfield.ymmword ? VEX256 : VEX128;
4336 i.tm.opcode_modifier.vexw = VEXW0;
4337 /* VPAND, VPOR, and VPXOR are commutative. */
4338 if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df)
4339 i.tm.opcode_modifier.commutative = 1;
4340 i.tm.opcode_modifier.evex = 0;
4341 i.tm.opcode_modifier.masking = 0;
4342 i.tm.opcode_modifier.broadcast = 0;
4343 i.tm.opcode_modifier.disp8memshift = 0;
4344 i.memshift = 0;
4345 if (j < i.operands)
4346 i.types[j].bitfield.disp8
4347 = fits_in_disp8 (i.op[j].disps->X_add_number);
4348 }
4349}
4350
4351/* Return non-zero for load instruction. */
4352
4353static int
4354load_insn_p (void)
4355{
4356 unsigned int dest;
4357 int any_vex_p = is_any_vex_encoding (&i.tm);
4358 unsigned int base_opcode = i.tm.base_opcode | 1;
4359
4360 if (!any_vex_p)
4361 {
4362 /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
4363 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
4364 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
4365 if (i.tm.opcode_modifier.anysize)
4366 return 0;
4367
4368 /* pop, popf, popa. */
4369 if (strcmp (i.tm.name, "pop") == 0
4370 || i.tm.base_opcode == 0x9d
4371 || i.tm.base_opcode == 0x61)
4372 return 1;
4373
4374 /* movs, cmps, lods, scas. */
4375 if ((i.tm.base_opcode | 0xb) == 0xaf)
4376 return 1;
4377
4378 /* outs, xlatb. */
4379 if (base_opcode == 0x6f
4380 || i.tm.base_opcode == 0xd7)
4381 return 1;
4382 /* NB: For AMD-specific insns with implicit memory operands,
4383 they're intentionally not covered. */
4384 }
4385
4386 /* No memory operand. */
4387 if (!i.mem_operands)
4388 return 0;
4389
4390 if (any_vex_p)
4391 {
4392 /* vldmxcsr. */
4393 if (i.tm.base_opcode == 0xae
4394 && i.tm.opcode_modifier.vex
4395 && i.tm.opcode_modifier.vexopcode == VEX0F
4396 && i.tm.extension_opcode == 2)
4397 return 1;
4398 }
4399 else
4400 {
4401 /* test, not, neg, mul, imul, div, idiv. */
4402 if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7)
4403 && i.tm.extension_opcode != 1)
4404 return 1;
4405
4406 /* inc, dec. */
4407 if (base_opcode == 0xff && i.tm.extension_opcode <= 1)
4408 return 1;
4409
4410 /* add, or, adc, sbb, and, sub, xor, cmp. */
4411 if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83)
4412 return 1;
4413
4414 /* bt, bts, btr, btc. */
4415 if (i.tm.base_opcode == 0xfba
4416 && (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7))
4417 return 1;
4418
4419 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4420 if ((base_opcode == 0xc1
4421 || (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3))
4422 && i.tm.extension_opcode != 6)
4423 return 1;
4424
4425 /* cmpxchg8b, cmpxchg16b, xrstors. */
4426 if (i.tm.base_opcode == 0xfc7
4427 && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3))
4428 return 1;
4429
4430 /* fxrstor, ldmxcsr, xrstor. */
4431 if (i.tm.base_opcode == 0xfae
4432 && (i.tm.extension_opcode == 1
4433 || i.tm.extension_opcode == 2
4434 || i.tm.extension_opcode == 5))
4435 return 1;
4436
4437 /* lgdt, lidt, lmsw. */
4438 if (i.tm.base_opcode == 0xf01
4439 && (i.tm.extension_opcode == 2
4440 || i.tm.extension_opcode == 3
4441 || i.tm.extension_opcode == 6))
4442 return 1;
4443
4444 /* vmptrld */
4445 if (i.tm.base_opcode == 0xfc7
4446 && i.tm.extension_opcode == 6)
4447 return 1;
4448
4449 /* Check for x87 instructions. */
4450 if (i.tm.base_opcode >= 0xd8 && i.tm.base_opcode <= 0xdf)
4451 {
4452 /* Skip fst, fstp, fstenv, fstcw. */
4453 if (i.tm.base_opcode == 0xd9
4454 && (i.tm.extension_opcode == 2
4455 || i.tm.extension_opcode == 3
4456 || i.tm.extension_opcode == 6
4457 || i.tm.extension_opcode == 7))
4458 return 0;
4459
4460 /* Skip fisttp, fist, fistp, fstp. */
4461 if (i.tm.base_opcode == 0xdb
4462 && (i.tm.extension_opcode == 1
4463 || i.tm.extension_opcode == 2
4464 || i.tm.extension_opcode == 3
4465 || i.tm.extension_opcode == 7))
4466 return 0;
4467
4468 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4469 if (i.tm.base_opcode == 0xdd
4470 && (i.tm.extension_opcode == 1
4471 || i.tm.extension_opcode == 2
4472 || i.tm.extension_opcode == 3
4473 || i.tm.extension_opcode == 6
4474 || i.tm.extension_opcode == 7))
4475 return 0;
4476
4477 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4478 if (i.tm.base_opcode == 0xdf
4479 && (i.tm.extension_opcode == 1
4480 || i.tm.extension_opcode == 2
4481 || i.tm.extension_opcode == 3
4482 || i.tm.extension_opcode == 6
4483 || i.tm.extension_opcode == 7))
4484 return 0;
4485
4486 return 1;
4487 }
4488 }
4489
4490 dest = i.operands - 1;
4491
4492 /* Check fake imm8 operand and 3 source operands. */
4493 if ((i.tm.opcode_modifier.immext
4494 || i.tm.opcode_modifier.vexsources == VEX3SOURCES)
4495 && i.types[dest].bitfield.imm8)
4496 dest--;
4497
4498 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */
4499 if (!any_vex_p
4500 && (base_opcode == 0x1
4501 || base_opcode == 0x9
4502 || base_opcode == 0x11
4503 || base_opcode == 0x19
4504 || base_opcode == 0x21
4505 || base_opcode == 0x29
4506 || base_opcode == 0x31
4507 || base_opcode == 0x39
4508 || (i.tm.base_opcode >= 0x84 && i.tm.base_opcode <= 0x87)
4509 || base_opcode == 0xfc1))
4510 return 1;
4511
4512 /* Check for load instruction. */
4513 return (i.types[dest].bitfield.class != ClassNone
4514 || i.types[dest].bitfield.instance == Accum);
4515}
4516
4517/* Output lfence, 0xfaee8, after instruction. */
4518
4519static void
4520insert_lfence_after (void)
4521{
4522 if (lfence_after_load && load_insn_p ())
4523 {
4524 /* There are also two REP string instructions that require
4525 special treatment. Specifically, the compare string (CMPS)
4526 and scan string (SCAS) instructions set EFLAGS in a manner
4527 that depends on the data being compared/scanned. When used
4528 with a REP prefix, the number of iterations may therefore
4529 vary depending on this data. If the data is a program secret
4530 chosen by the adversary using an LVI method,
4531 then this data-dependent behavior may leak some aspect
4532 of the secret. */
4533 if (((i.tm.base_opcode | 0x1) == 0xa7
4534 || (i.tm.base_opcode | 0x1) == 0xaf)
4535 && i.prefix[REP_PREFIX])
4536 {
4537 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4538 i.tm.name);
4539 }
4540 char *p = frag_more (3);
4541 *p++ = 0xf;
4542 *p++ = 0xae;
4543 *p = 0xe8;
4544 }
4545}
4546
4547/* Output lfence, 0xfaee8, before instruction. */
4548
4549static void
4550insert_lfence_before (void)
4551{
4552 char *p;
4553
4554 if (is_any_vex_encoding (&i.tm))
4555 return;
4556
4557 if (i.tm.base_opcode == 0xff
4558 && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4))
4559 {
4560 /* Insert lfence before indirect branch if needed. */
4561
4562 if (lfence_before_indirect_branch == lfence_branch_none)
4563 return;
4564
4565 if (i.operands != 1)
4566 abort ();
4567
4568 if (i.reg_operands == 1)
4569 {
4570 /* Indirect branch via register. Don't insert lfence with
4571 -mlfence-after-load=yes. */
4572 if (lfence_after_load
4573 || lfence_before_indirect_branch == lfence_branch_memory)
4574 return;
4575 }
4576 else if (i.mem_operands == 1
4577 && lfence_before_indirect_branch != lfence_branch_register)
4578 {
4579 as_warn (_("indirect `%s` with memory operand should be avoided"),
4580 i.tm.name);
4581 return;
4582 }
4583 else
4584 return;
4585
4586 if (last_insn.kind != last_insn_other
4587 && last_insn.seg == now_seg)
4588 {
4589 as_warn_where (last_insn.file, last_insn.line,
4590 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4591 last_insn.name, i.tm.name);
4592 return;
4593 }
4594
4595 p = frag_more (3);
4596 *p++ = 0xf;
4597 *p++ = 0xae;
4598 *p = 0xe8;
4599 return;
4600 }
4601
4602 /* Output or/not/shl and lfence before near ret. */
4603 if (lfence_before_ret != lfence_before_ret_none
4604 && (i.tm.base_opcode == 0xc2
4605 || i.tm.base_opcode == 0xc3))
4606 {
4607 if (last_insn.kind != last_insn_other
4608 && last_insn.seg == now_seg)
4609 {
4610 as_warn_where (last_insn.file, last_insn.line,
4611 _("`%s` skips -mlfence-before-ret on `%s`"),
4612 last_insn.name, i.tm.name);
4613 return;
4614 }
4615
4616 /* Near ret ingore operand size override under CPU64. */
4617 char prefix = flag_code == CODE_64BIT
4618 ? 0x48
4619 : i.prefix[DATA_PREFIX] ? 0x66 : 0x0;
4620
4621 if (lfence_before_ret == lfence_before_ret_not)
4622 {
4623 /* not: 0xf71424, may add prefix
4624 for operand size override or 64-bit code. */
4625 p = frag_more ((prefix ? 2 : 0) + 6 + 3);
4626 if (prefix)
4627 *p++ = prefix;
4628 *p++ = 0xf7;
4629 *p++ = 0x14;
4630 *p++ = 0x24;
4631 if (prefix)
4632 *p++ = prefix;
4633 *p++ = 0xf7;
4634 *p++ = 0x14;
4635 *p++ = 0x24;
4636 }
4637 else
4638 {
4639 p = frag_more ((prefix ? 1 : 0) + 4 + 3);
4640 if (prefix)
4641 *p++ = prefix;
4642 if (lfence_before_ret == lfence_before_ret_or)
4643 {
4644 /* or: 0x830c2400, may add prefix
4645 for operand size override or 64-bit code. */
4646 *p++ = 0x83;
4647 *p++ = 0x0c;
4648 }
4649 else
4650 {
4651 /* shl: 0xc1242400, may add prefix
4652 for operand size override or 64-bit code. */
4653 *p++ = 0xc1;
4654 *p++ = 0x24;
4655 }
4656
4657 *p++ = 0x24;
4658 *p++ = 0x0;
4659 }
4660
4661 *p++ = 0xf;
4662 *p++ = 0xae;
4663 *p = 0xe8;
4664 }
4665}
4666
4667/* This is the guts of the machine-dependent assembler. LINE points to a
4668 machine dependent instruction. This function is supposed to emit
4669 the frags/bytes it assembles to. */
4670
4671void
4672md_assemble (char *line)
4673{
4674 unsigned int j;
4675 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4676 const insn_template *t;
4677
4678 /* Initialize globals. */
4679 memset (&i, '\0', sizeof (i));
4680 for (j = 0; j < MAX_OPERANDS; j++)
4681 i.reloc[j] = NO_RELOC;
4682 memset (disp_expressions, '\0', sizeof (disp_expressions));
4683 memset (im_expressions, '\0', sizeof (im_expressions));
4684 save_stack_p = save_stack;
4685
4686 /* First parse an instruction mnemonic & call i386_operand for the operands.
4687 We assume that the scrubber has arranged it so that line[0] is the valid
4688 start of a (possibly prefixed) mnemonic. */
4689
4690 line = parse_insn (line, mnemonic);
4691 if (line == NULL)
4692 return;
4693 mnem_suffix = i.suffix;
4694
4695 line = parse_operands (line, mnemonic);
4696 this_operand = -1;
4697 xfree (i.memop1_string);
4698 i.memop1_string = NULL;
4699 if (line == NULL)
4700 return;
4701
4702 /* Now we've parsed the mnemonic into a set of templates, and have the
4703 operands at hand. */
4704
4705 /* All Intel opcodes have reversed operands except for "bound", "enter",
4706 "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse
4707 intersegment "jmp" and "call" instructions with 2 immediate operands so
4708 that the immediate segment precedes the offset, as it does when in AT&T
4709 mode. */
4710 if (intel_syntax
4711 && i.operands > 1
4712 && (strcmp (mnemonic, "bound") != 0)
4713 && (strcmp (mnemonic, "invlpga") != 0)
4714 && (strncmp (mnemonic, "monitor", 7) != 0)
4715 && (strncmp (mnemonic, "mwait", 5) != 0)
4716 && (strcmp (mnemonic, "tpause") != 0)
4717 && (strcmp (mnemonic, "umwait") != 0)
4718 && !(operand_type_check (i.types[0], imm)
4719 && operand_type_check (i.types[1], imm)))
4720 swap_operands ();
4721
4722 /* The order of the immediates should be reversed
4723 for 2 immediates extrq and insertq instructions */
4724 if (i.imm_operands == 2
4725 && (strcmp (mnemonic, "extrq") == 0
4726 || strcmp (mnemonic, "insertq") == 0))
4727 swap_2_operands (0, 1);
4728
4729 if (i.imm_operands)
4730 optimize_imm ();
4731
4732 /* Don't optimize displacement for movabs since it only takes 64bit
4733 displacement. */
4734 if (i.disp_operands
4735 && i.disp_encoding != disp_encoding_32bit
4736 && (flag_code != CODE_64BIT
4737 || strcmp (mnemonic, "movabs") != 0))
4738 optimize_disp ();
4739
4740 /* Next, we find a template that matches the given insn,
4741 making sure the overlap of the given operands types is consistent
4742 with the template operand types. */
4743
4744 if (!(t = match_template (mnem_suffix)))
4745 return;
4746
4747 if (sse_check != check_none
4748 && !i.tm.opcode_modifier.noavx
4749 && !i.tm.cpu_flags.bitfield.cpuavx
4750 && !i.tm.cpu_flags.bitfield.cpuavx512f
4751 && (i.tm.cpu_flags.bitfield.cpusse
4752 || i.tm.cpu_flags.bitfield.cpusse2
4753 || i.tm.cpu_flags.bitfield.cpusse3
4754 || i.tm.cpu_flags.bitfield.cpussse3
4755 || i.tm.cpu_flags.bitfield.cpusse4_1
4756 || i.tm.cpu_flags.bitfield.cpusse4_2
4757 || i.tm.cpu_flags.bitfield.cpupclmul
4758 || i.tm.cpu_flags.bitfield.cpuaes
4759 || i.tm.cpu_flags.bitfield.cpusha
4760 || i.tm.cpu_flags.bitfield.cpugfni))
4761 {
4762 (sse_check == check_warning
4763 ? as_warn
4764 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4765 }
4766
4767 if (i.tm.opcode_modifier.fwait)
4768 if (!add_prefix (FWAIT_OPCODE))
4769 return;
4770
4771 /* Check if REP prefix is OK. */
4772 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4773 {
4774 as_bad (_("invalid instruction `%s' after `%s'"),
4775 i.tm.name, i.rep_prefix);
4776 return;
4777 }
4778
4779 /* Check for lock without a lockable instruction. Destination operand
4780 must be memory unless it is xchg (0x86). */
4781 if (i.prefix[LOCK_PREFIX]
4782 && (!i.tm.opcode_modifier.islockable
4783 || i.mem_operands == 0
4784 || (i.tm.base_opcode != 0x86
4785 && !(i.flags[i.operands - 1] & Operand_Mem))))
4786 {
4787 as_bad (_("expecting lockable instruction after `lock'"));
4788 return;
4789 }
4790
4791 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4792 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4793 {
4794 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4795 return;
4796 }
4797
4798 /* Check if HLE prefix is OK. */
4799 if (i.hle_prefix && !check_hle ())
4800 return;
4801
4802 /* Check BND prefix. */
4803 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4804 as_bad (_("expecting valid branch instruction after `bnd'"));
4805
4806 /* Check NOTRACK prefix. */
4807 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4808 as_bad (_("expecting indirect branch instruction after `notrack'"));
4809
4810 if (i.tm.cpu_flags.bitfield.cpumpx)
4811 {
4812 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4813 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4814 else if (flag_code != CODE_16BIT
4815 ? i.prefix[ADDR_PREFIX]
4816 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4817 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4818 }
4819
4820 /* Insert BND prefix. */
4821 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4822 {
4823 if (!i.prefix[BND_PREFIX])
4824 add_prefix (BND_PREFIX_OPCODE);
4825 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4826 {
4827 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4828 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4829 }
4830 }
4831
4832 /* Check string instruction segment overrides. */
4833 if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0)
4834 {
4835 gas_assert (i.mem_operands);
4836 if (!check_string ())
4837 return;
4838 i.disp_operands = 0;
4839 }
4840
4841 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4842 optimize_encoding ();
4843
4844 if (!process_suffix ())
4845 return;
4846
4847 /* Update operand types. */
4848 for (j = 0; j < i.operands; j++)
4849 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4850
4851 /* Make still unresolved immediate matches conform to size of immediate
4852 given in i.suffix. */
4853 if (!finalize_imm ())
4854 return;
4855
4856 if (i.types[0].bitfield.imm1)
4857 i.imm_operands = 0; /* kludge for shift insns. */
4858
4859 /* We only need to check those implicit registers for instructions
4860 with 3 operands or less. */
4861 if (i.operands <= 3)
4862 for (j = 0; j < i.operands; j++)
4863 if (i.types[j].bitfield.instance != InstanceNone
4864 && !i.types[j].bitfield.xmmword)
4865 i.reg_operands--;
4866
4867 /* ImmExt should be processed after SSE2AVX. */
4868 if (!i.tm.opcode_modifier.sse2avx
4869 && i.tm.opcode_modifier.immext)
4870 process_immext ();
4871
4872 /* For insns with operands there are more diddles to do to the opcode. */
4873 if (i.operands)
4874 {
4875 if (!process_operands ())
4876 return;
4877 }
4878 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4879 {
4880 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4881 as_warn (_("translating to `%sp'"), i.tm.name);
4882 }
4883
4884 if (is_any_vex_encoding (&i.tm))
4885 {
4886 if (!cpu_arch_flags.bitfield.cpui286)
4887 {
4888 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4889 i.tm.name);
4890 return;
4891 }
4892
4893 if (i.tm.opcode_modifier.vex)
4894 build_vex_prefix (t);
4895 else
4896 build_evex_prefix ();
4897 }
4898
4899 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4900 instructions may define INT_OPCODE as well, so avoid this corner
4901 case for those instructions that use MODRM. */
4902 if (i.tm.base_opcode == INT_OPCODE
4903 && !i.tm.opcode_modifier.modrm
4904 && i.op[0].imms->X_add_number == 3)
4905 {
4906 i.tm.base_opcode = INT3_OPCODE;
4907 i.imm_operands = 0;
4908 }
4909
4910 if ((i.tm.opcode_modifier.jump == JUMP
4911 || i.tm.opcode_modifier.jump == JUMP_BYTE
4912 || i.tm.opcode_modifier.jump == JUMP_DWORD)
4913 && i.op[0].disps->X_op == O_constant)
4914 {
4915 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4916 the absolute address given by the constant. Since ix86 jumps and
4917 calls are pc relative, we need to generate a reloc. */
4918 i.op[0].disps->X_add_symbol = &abs_symbol;
4919 i.op[0].disps->X_op = O_symbol;
4920 }
4921
4922 /* For 8 bit registers we need an empty rex prefix. Also if the
4923 instruction already has a prefix, we need to convert old
4924 registers to new ones. */
4925
4926 if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte
4927 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4928 || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte
4929 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4930 || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte)
4931 || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte))
4932 && i.rex != 0))
4933 {
4934 int x;
4935
4936 i.rex |= REX_OPCODE;
4937 for (x = 0; x < 2; x++)
4938 {
4939 /* Look for 8 bit operand that uses old registers. */
4940 if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte
4941 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4942 {
4943 gas_assert (!(i.op[x].regs->reg_flags & RegRex));
4944 /* In case it is "hi" register, give up. */
4945 if (i.op[x].regs->reg_num > 3)
4946 as_bad (_("can't encode register '%s%s' in an "
4947 "instruction requiring REX prefix."),
4948 register_prefix, i.op[x].regs->reg_name);
4949
4950 /* Otherwise it is equivalent to the extended register.
4951 Since the encoding doesn't change this is merely
4952 cosmetic cleanup for debug output. */
4953
4954 i.op[x].regs = i.op[x].regs + 8;
4955 }
4956 }
4957 }
4958
4959 if (i.rex == 0 && i.rex_encoding)
4960 {
4961 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4962 that uses legacy register. If it is "hi" register, don't add
4963 the REX_OPCODE byte. */
4964 int x;
4965 for (x = 0; x < 2; x++)
4966 if (i.types[x].bitfield.class == Reg
4967 && i.types[x].bitfield.byte
4968 && (i.op[x].regs->reg_flags & RegRex64) == 0
4969 && i.op[x].regs->reg_num > 3)
4970 {
4971 gas_assert (!(i.op[x].regs->reg_flags & RegRex));
4972 i.rex_encoding = FALSE;
4973 break;
4974 }
4975
4976 if (i.rex_encoding)
4977 i.rex = REX_OPCODE;
4978 }
4979
4980 if (i.rex != 0)
4981 add_prefix (REX_OPCODE | i.rex);
4982
4983 insert_lfence_before ();
4984
4985 /* We are ready to output the insn. */
4986 output_insn ();
4987
4988 insert_lfence_after ();
4989
4990 last_insn.seg = now_seg;
4991
4992 if (i.tm.opcode_modifier.isprefix)
4993 {
4994 last_insn.kind = last_insn_prefix;
4995 last_insn.name = i.tm.name;
4996 last_insn.file = as_where (&last_insn.line);
4997 }
4998 else
4999 last_insn.kind = last_insn_other;
5000}
5001
5002static char *
5003parse_insn (char *line, char *mnemonic)
5004{
5005 char *l = line;
5006 char *token_start = l;
5007 char *mnem_p;
5008 int supported;
5009 const insn_template *t;
5010 char *dot_p = NULL;
5011
5012 while (1)
5013 {
5014 mnem_p = mnemonic;
5015 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
5016 {
5017 if (*mnem_p == '.')
5018 dot_p = mnem_p;
5019 mnem_p++;
5020 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
5021 {
5022 as_bad (_("no such instruction: `%s'"), token_start);
5023 return NULL;
5024 }
5025 l++;
5026 }
5027 if (!is_space_char (*l)
5028 && *l != END_OF_INSN
5029 && (intel_syntax
5030 || (*l != PREFIX_SEPARATOR
5031 && *l != ',')))
5032 {
5033 as_bad (_("invalid character %s in mnemonic"),
5034 output_invalid (*l));
5035 return NULL;
5036 }
5037 if (token_start == l)
5038 {
5039 if (!intel_syntax && *l == PREFIX_SEPARATOR)
5040 as_bad (_("expecting prefix; got nothing"));
5041 else
5042 as_bad (_("expecting mnemonic; got nothing"));
5043 return NULL;
5044 }
5045
5046 /* Look up instruction (or prefix) via hash table. */
5047 current_templates = (const templates *) hash_find (op_hash, mnemonic);
5048
5049 if (*l != END_OF_INSN
5050 && (!is_space_char (*l) || l[1] != END_OF_INSN)
5051 && current_templates
5052 && current_templates->start->opcode_modifier.isprefix)
5053 {
5054 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
5055 {
5056 as_bad ((flag_code != CODE_64BIT
5057 ? _("`%s' is only supported in 64-bit mode")
5058 : _("`%s' is not supported in 64-bit mode")),
5059 current_templates->start->name);
5060 return NULL;
5061 }
5062 /* If we are in 16-bit mode, do not allow addr16 or data16.
5063 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5064 if ((current_templates->start->opcode_modifier.size == SIZE16
5065 || current_templates->start->opcode_modifier.size == SIZE32)
5066 && flag_code != CODE_64BIT
5067 && ((current_templates->start->opcode_modifier.size == SIZE32)
5068 ^ (flag_code == CODE_16BIT)))
5069 {
5070 as_bad (_("redundant %s prefix"),
5071 current_templates->start->name);
5072 return NULL;
5073 }
5074 if (current_templates->start->opcode_length == 0)
5075 {
5076 /* Handle pseudo prefixes. */
5077 switch (current_templates->start->base_opcode)
5078 {
5079 case 0x0:
5080 /* {disp8} */
5081 i.disp_encoding = disp_encoding_8bit;
5082 break;
5083 case 0x1:
5084 /* {disp32} */
5085 i.disp_encoding = disp_encoding_32bit;
5086 break;
5087 case 0x2:
5088 /* {load} */
5089 i.dir_encoding = dir_encoding_load;
5090 break;
5091 case 0x3:
5092 /* {store} */
5093 i.dir_encoding = dir_encoding_store;
5094 break;
5095 case 0x4:
5096 /* {vex} */
5097 i.vec_encoding = vex_encoding_vex;
5098 break;
5099 case 0x5:
5100 /* {vex3} */
5101 i.vec_encoding = vex_encoding_vex3;
5102 break;
5103 case 0x6:
5104 /* {evex} */
5105 i.vec_encoding = vex_encoding_evex;
5106 break;
5107 case 0x7:
5108 /* {rex} */
5109 i.rex_encoding = TRUE;
5110 break;
5111 case 0x8:
5112 /* {nooptimize} */
5113 i.no_optimize = TRUE;
5114 break;
5115 default:
5116 abort ();
5117 }
5118 }
5119 else
5120 {
5121 /* Add prefix, checking for repeated prefixes. */
5122 switch (add_prefix (current_templates->start->base_opcode))
5123 {
5124 case PREFIX_EXIST:
5125 return NULL;
5126 case PREFIX_DS:
5127 if (current_templates->start->cpu_flags.bitfield.cpuibt)
5128 i.notrack_prefix = current_templates->start->name;
5129 break;
5130 case PREFIX_REP:
5131 if (current_templates->start->cpu_flags.bitfield.cpuhle)
5132 i.hle_prefix = current_templates->start->name;
5133 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
5134 i.bnd_prefix = current_templates->start->name;
5135 else
5136 i.rep_prefix = current_templates->start->name;
5137 break;
5138 default:
5139 break;
5140 }
5141 }
5142 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5143 token_start = ++l;
5144 }
5145 else
5146 break;
5147 }
5148
5149 if (!current_templates)
5150 {
5151 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5152 Check if we should swap operand or force 32bit displacement in
5153 encoding. */
5154 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
5155 i.dir_encoding = dir_encoding_swap;
5156 else if (mnem_p - 3 == dot_p
5157 && dot_p[1] == 'd'
5158 && dot_p[2] == '8')
5159 i.disp_encoding = disp_encoding_8bit;
5160 else if (mnem_p - 4 == dot_p
5161 && dot_p[1] == 'd'
5162 && dot_p[2] == '3'
5163 && dot_p[3] == '2')
5164 i.disp_encoding = disp_encoding_32bit;
5165 else
5166 goto check_suffix;
5167 mnem_p = dot_p;
5168 *dot_p = '\0';
5169 current_templates = (const templates *) hash_find (op_hash, mnemonic);
5170 }
5171
5172 if (!current_templates)
5173 {
5174 check_suffix:
5175 if (mnem_p > mnemonic)
5176 {
5177 /* See if we can get a match by trimming off a suffix. */
5178 switch (mnem_p[-1])
5179 {
5180 case WORD_MNEM_SUFFIX:
5181 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
5182 i.suffix = SHORT_MNEM_SUFFIX;
5183 else
5184 /* Fall through. */
5185 case BYTE_MNEM_SUFFIX:
5186 case QWORD_MNEM_SUFFIX:
5187 i.suffix = mnem_p[-1];
5188 mnem_p[-1] = '\0';
5189 current_templates = (const templates *) hash_find (op_hash,
5190 mnemonic);
5191 break;
5192 case SHORT_MNEM_SUFFIX:
5193 case LONG_MNEM_SUFFIX:
5194 if (!intel_syntax)
5195 {
5196 i.suffix = mnem_p[-1];
5197 mnem_p[-1] = '\0';
5198 current_templates = (const templates *) hash_find (op_hash,
5199 mnemonic);
5200 }
5201 break;
5202
5203 /* Intel Syntax. */
5204 case 'd':
5205 if (intel_syntax)
5206 {
5207 if (intel_float_operand (mnemonic) == 1)
5208 i.suffix = SHORT_MNEM_SUFFIX;
5209 else
5210 i.suffix = LONG_MNEM_SUFFIX;
5211 mnem_p[-1] = '\0';
5212 current_templates = (const templates *) hash_find (op_hash,
5213 mnemonic);
5214 }
5215 break;
5216 }
5217 }
5218
5219 if (!current_templates)
5220 {
5221 as_bad (_("no such instruction: `%s'"), token_start);
5222 return NULL;
5223 }
5224 }
5225
5226 if (current_templates->start->opcode_modifier.jump == JUMP
5227 || current_templates->start->opcode_modifier.jump == JUMP_BYTE)
5228 {
5229 /* Check for a branch hint. We allow ",pt" and ",pn" for
5230 predict taken and predict not taken respectively.
5231 I'm not sure that branch hints actually do anything on loop
5232 and jcxz insns (JumpByte) for current Pentium4 chips. They
5233 may work in the future and it doesn't hurt to accept them
5234 now. */
5235 if (l[0] == ',' && l[1] == 'p')
5236 {
5237 if (l[2] == 't')
5238 {
5239 if (!add_prefix (DS_PREFIX_OPCODE))
5240 return NULL;
5241 l += 3;
5242 }
5243 else if (l[2] == 'n')
5244 {
5245 if (!add_prefix (CS_PREFIX_OPCODE))
5246 return NULL;
5247 l += 3;
5248 }
5249 }
5250 }
5251 /* Any other comma loses. */
5252 if (*l == ',')
5253 {
5254 as_bad (_("invalid character %s in mnemonic"),
5255 output_invalid (*l));
5256 return NULL;
5257 }
5258
5259 /* Check if instruction is supported on specified architecture. */
5260 supported = 0;
5261 for (t = current_templates->start; t < current_templates->end; ++t)
5262 {
5263 supported |= cpu_flags_match (t);
5264 if (supported == CPU_FLAGS_PERFECT_MATCH)
5265 {
5266 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
5267 as_warn (_("use .code16 to ensure correct addressing mode"));
5268
5269 return l;
5270 }
5271 }
5272
5273 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5274 as_bad (flag_code == CODE_64BIT
5275 ? _("`%s' is not supported in 64-bit mode")
5276 : _("`%s' is only supported in 64-bit mode"),
5277 current_templates->start->name);
5278 else
5279 as_bad (_("`%s' is not supported on `%s%s'"),
5280 current_templates->start->name,
5281 cpu_arch_name ? cpu_arch_name : default_arch,
5282 cpu_sub_arch_name ? cpu_sub_arch_name : "");
5283
5284 return NULL;
5285}
5286
5287static char *
5288parse_operands (char *l, const char *mnemonic)
5289{
5290 char *token_start;
5291
5292 /* 1 if operand is pending after ','. */
5293 unsigned int expecting_operand = 0;
5294
5295 /* Non-zero if operand parens not balanced. */
5296 unsigned int paren_not_balanced;
5297
5298 while (*l != END_OF_INSN)
5299 {
5300 /* Skip optional white space before operand. */
5301 if (is_space_char (*l))
5302 ++l;
5303 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
5304 {
5305 as_bad (_("invalid character %s before operand %d"),
5306 output_invalid (*l),
5307 i.operands + 1);
5308 return NULL;
5309 }
5310 token_start = l; /* After white space. */
5311 paren_not_balanced = 0;
5312 while (paren_not_balanced || *l != ',')
5313 {
5314 if (*l == END_OF_INSN)
5315 {
5316 if (paren_not_balanced)
5317 {
5318 if (!intel_syntax)
5319 as_bad (_("unbalanced parenthesis in operand %d."),
5320 i.operands + 1);
5321 else
5322 as_bad (_("unbalanced brackets in operand %d."),
5323 i.operands + 1);
5324 return NULL;
5325 }
5326 else
5327 break; /* we are done */
5328 }
5329 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
5330 {
5331 as_bad (_("invalid character %s in operand %d"),
5332 output_invalid (*l),
5333 i.operands + 1);
5334 return NULL;
5335 }
5336 if (!intel_syntax)
5337 {
5338 if (*l == '(')
5339 ++paren_not_balanced;
5340 if (*l == ')')
5341 --paren_not_balanced;
5342 }
5343 else
5344 {
5345 if (*l == '[')
5346 ++paren_not_balanced;
5347 if (*l == ']')
5348 --paren_not_balanced;
5349 }
5350 l++;
5351 }
5352 if (l != token_start)
5353 { /* Yes, we've read in another operand. */
5354 unsigned int operand_ok;
5355 this_operand = i.operands++;
5356 if (i.operands > MAX_OPERANDS)
5357 {
5358 as_bad (_("spurious operands; (%d operands/instruction max)"),
5359 MAX_OPERANDS);
5360 return NULL;
5361 }
5362 i.types[this_operand].bitfield.unspecified = 1;
5363 /* Now parse operand adding info to 'i' as we go along. */
5364 END_STRING_AND_SAVE (l);
5365
5366 if (i.mem_operands > 1)
5367 {
5368 as_bad (_("too many memory references for `%s'"),
5369 mnemonic);
5370 return 0;
5371 }
5372
5373 if (intel_syntax)
5374 operand_ok =
5375 i386_intel_operand (token_start,
5376 intel_float_operand (mnemonic));
5377 else
5378 operand_ok = i386_att_operand (token_start);
5379
5380 RESTORE_END_STRING (l);
5381 if (!operand_ok)
5382 return NULL;
5383 }
5384 else
5385 {
5386 if (expecting_operand)
5387 {
5388 expecting_operand_after_comma:
5389 as_bad (_("expecting operand after ','; got nothing"));
5390 return NULL;
5391 }
5392 if (*l == ',')
5393 {
5394 as_bad (_("expecting operand before ','; got nothing"));
5395 return NULL;
5396 }
5397 }
5398
5399 /* Now *l must be either ',' or END_OF_INSN. */
5400 if (*l == ',')
5401 {
5402 if (*++l == END_OF_INSN)
5403 {
5404 /* Just skip it, if it's \n complain. */
5405 goto expecting_operand_after_comma;
5406 }
5407 expecting_operand = 1;
5408 }
5409 }
5410 return l;
5411}
5412
5413static void
5414swap_2_operands (int xchg1, int xchg2)
5415{
5416 union i386_op temp_op;
5417 i386_operand_type temp_type;
5418 unsigned int temp_flags;
5419 enum bfd_reloc_code_real temp_reloc;
5420
5421 temp_type = i.types[xchg2];
5422 i.types[xchg2] = i.types[xchg1];
5423 i.types[xchg1] = temp_type;
5424
5425 temp_flags = i.flags[xchg2];
5426 i.flags[xchg2] = i.flags[xchg1];
5427 i.flags[xchg1] = temp_flags;
5428
5429 temp_op = i.op[xchg2];
5430 i.op[xchg2] = i.op[xchg1];
5431 i.op[xchg1] = temp_op;
5432
5433 temp_reloc = i.reloc[xchg2];
5434 i.reloc[xchg2] = i.reloc[xchg1];
5435 i.reloc[xchg1] = temp_reloc;
5436
5437 if (i.mask)
5438 {
5439 if (i.mask->operand == xchg1)
5440 i.mask->operand = xchg2;
5441 else if (i.mask->operand == xchg2)
5442 i.mask->operand = xchg1;
5443 }
5444 if (i.broadcast)
5445 {
5446 if (i.broadcast->operand == xchg1)
5447 i.broadcast->operand = xchg2;
5448 else if (i.broadcast->operand == xchg2)
5449 i.broadcast->operand = xchg1;
5450 }
5451 if (i.rounding)
5452 {
5453 if (i.rounding->operand == xchg1)
5454 i.rounding->operand = xchg2;
5455 else if (i.rounding->operand == xchg2)
5456 i.rounding->operand = xchg1;
5457 }
5458}
5459
5460static void
5461swap_operands (void)
5462{
5463 switch (i.operands)
5464 {
5465 case 5:
5466 case 4:
5467 swap_2_operands (1, i.operands - 2);
5468 /* Fall through. */
5469 case 3:
5470 case 2:
5471 swap_2_operands (0, i.operands - 1);
5472 break;
5473 default:
5474 abort ();
5475 }
5476
5477 if (i.mem_operands == 2)
5478 {
5479 const seg_entry *temp_seg;
5480 temp_seg = i.seg[0];
5481 i.seg[0] = i.seg[1];
5482 i.seg[1] = temp_seg;
5483 }
5484}
5485
5486/* Try to ensure constant immediates are represented in the smallest
5487 opcode possible. */
5488static void
5489optimize_imm (void)
5490{
5491 char guess_suffix = 0;
5492 int op;
5493
5494 if (i.suffix)
5495 guess_suffix = i.suffix;
5496 else if (i.reg_operands)
5497 {
5498 /* Figure out a suffix from the last register operand specified.
5499 We can't do this properly yet, i.e. excluding special register
5500 instances, but the following works for instructions with
5501 immediates. In any case, we can't set i.suffix yet. */
5502 for (op = i.operands; --op >= 0;)
5503 if (i.types[op].bitfield.class != Reg)
5504 continue;
5505 else if (i.types[op].bitfield.byte)
5506 {
5507 guess_suffix = BYTE_MNEM_SUFFIX;
5508 break;
5509 }
5510 else if (i.types[op].bitfield.word)
5511 {
5512 guess_suffix = WORD_MNEM_SUFFIX;
5513 break;
5514 }
5515 else if (i.types[op].bitfield.dword)
5516 {
5517 guess_suffix = LONG_MNEM_SUFFIX;
5518 break;
5519 }
5520 else if (i.types[op].bitfield.qword)
5521 {
5522 guess_suffix = QWORD_MNEM_SUFFIX;
5523 break;
5524 }
5525 }
5526 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5527 guess_suffix = WORD_MNEM_SUFFIX;
5528
5529 for (op = i.operands; --op >= 0;)
5530 if (operand_type_check (i.types[op], imm))
5531 {
5532 switch (i.op[op].imms->X_op)
5533 {
5534 case O_constant:
5535 /* If a suffix is given, this operand may be shortened. */
5536 switch (guess_suffix)
5537 {
5538 case LONG_MNEM_SUFFIX:
5539 i.types[op].bitfield.imm32 = 1;
5540 i.types[op].bitfield.imm64 = 1;
5541 break;
5542 case WORD_MNEM_SUFFIX:
5543 i.types[op].bitfield.imm16 = 1;
5544 i.types[op].bitfield.imm32 = 1;
5545 i.types[op].bitfield.imm32s = 1;
5546 i.types[op].bitfield.imm64 = 1;
5547 break;
5548 case BYTE_MNEM_SUFFIX:
5549 i.types[op].bitfield.imm8 = 1;
5550 i.types[op].bitfield.imm8s = 1;
5551 i.types[op].bitfield.imm16 = 1;
5552 i.types[op].bitfield.imm32 = 1;
5553 i.types[op].bitfield.imm32s = 1;
5554 i.types[op].bitfield.imm64 = 1;
5555 break;
5556 }
5557
5558 /* If this operand is at most 16 bits, convert it
5559 to a signed 16 bit number before trying to see
5560 whether it will fit in an even smaller size.
5561 This allows a 16-bit operand such as $0xffe0 to
5562 be recognised as within Imm8S range. */
5563 if ((i.types[op].bitfield.imm16)
5564 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
5565 {
5566 i.op[op].imms->X_add_number =
5567 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
5568 }
5569#ifdef BFD64
5570 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5571 if ((i.types[op].bitfield.imm32)
5572 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
5573 == 0))
5574 {
5575 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
5576 ^ ((offsetT) 1 << 31))
5577 - ((offsetT) 1 << 31));
5578 }
5579#endif
5580 i.types[op]
5581 = operand_type_or (i.types[op],
5582 smallest_imm_type (i.op[op].imms->X_add_number));
5583
5584 /* We must avoid matching of Imm32 templates when 64bit
5585 only immediate is available. */
5586 if (guess_suffix == QWORD_MNEM_SUFFIX)
5587 i.types[op].bitfield.imm32 = 0;
5588 break;
5589
5590 case O_absent:
5591 case O_register:
5592 abort ();
5593
5594 /* Symbols and expressions. */
5595 default:
5596 /* Convert symbolic operand to proper sizes for matching, but don't
5597 prevent matching a set of insns that only supports sizes other
5598 than those matching the insn suffix. */
5599 {
5600 i386_operand_type mask, allowed;
5601 const insn_template *t;
5602
5603 operand_type_set (&mask, 0);
5604 operand_type_set (&allowed, 0);
5605
5606 for (t = current_templates->start;
5607 t < current_templates->end;
5608 ++t)
5609 {
5610 allowed = operand_type_or (allowed, t->operand_types[op]);
5611 allowed = operand_type_and (allowed, anyimm);
5612 }
5613 switch (guess_suffix)
5614 {
5615 case QWORD_MNEM_SUFFIX:
5616 mask.bitfield.imm64 = 1;
5617 mask.bitfield.imm32s = 1;
5618 break;
5619 case LONG_MNEM_SUFFIX:
5620 mask.bitfield.imm32 = 1;
5621 break;
5622 case WORD_MNEM_SUFFIX:
5623 mask.bitfield.imm16 = 1;
5624 break;
5625 case BYTE_MNEM_SUFFIX:
5626 mask.bitfield.imm8 = 1;
5627 break;
5628 default:
5629 break;
5630 }
5631 allowed = operand_type_and (mask, allowed);
5632 if (!operand_type_all_zero (&allowed))
5633 i.types[op] = operand_type_and (i.types[op], mask);
5634 }
5635 break;
5636 }
5637 }
5638}
5639
5640/* Try to use the smallest displacement type too. */
5641static void
5642optimize_disp (void)
5643{
5644 int op;
5645
5646 for (op = i.operands; --op >= 0;)
5647 if (operand_type_check (i.types[op], disp))
5648 {
5649 if (i.op[op].disps->X_op == O_constant)
5650 {
5651 offsetT op_disp = i.op[op].disps->X_add_number;
5652
5653 if (i.types[op].bitfield.disp16
5654 && (op_disp & ~(offsetT) 0xffff) == 0)
5655 {
5656 /* If this operand is at most 16 bits, convert
5657 to a signed 16 bit number and don't use 64bit
5658 displacement. */
5659 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
5660 i.types[op].bitfield.disp64 = 0;
5661 }
5662#ifdef BFD64
5663 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5664 if (i.types[op].bitfield.disp32
5665 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
5666 {
5667 /* If this operand is at most 32 bits, convert
5668 to a signed 32 bit number and don't use 64bit
5669 displacement. */
5670 op_disp &= (((offsetT) 2 << 31) - 1);
5671 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
5672 i.types[op].bitfield.disp64 = 0;
5673 }
5674#endif
5675 if (!op_disp && i.types[op].bitfield.baseindex)
5676 {
5677 i.types[op].bitfield.disp8 = 0;
5678 i.types[op].bitfield.disp16 = 0;
5679 i.types[op].bitfield.disp32 = 0;
5680 i.types[op].bitfield.disp32s = 0;
5681 i.types[op].bitfield.disp64 = 0;
5682 i.op[op].disps = 0;
5683 i.disp_operands--;
5684 }
5685 else if (flag_code == CODE_64BIT)
5686 {
5687 if (fits_in_signed_long (op_disp))
5688 {
5689 i.types[op].bitfield.disp64 = 0;
5690 i.types[op].bitfield.disp32s = 1;
5691 }
5692 if (i.prefix[ADDR_PREFIX]
5693 && fits_in_unsigned_long (op_disp))
5694 i.types[op].bitfield.disp32 = 1;
5695 }
5696 if ((i.types[op].bitfield.disp32
5697 || i.types[op].bitfield.disp32s
5698 || i.types[op].bitfield.disp16)
5699 && fits_in_disp8 (op_disp))
5700 i.types[op].bitfield.disp8 = 1;
5701 }
5702 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5703 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5704 {
5705 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5706 i.op[op].disps, 0, i.reloc[op]);
5707 i.types[op].bitfield.disp8 = 0;
5708 i.types[op].bitfield.disp16 = 0;
5709 i.types[op].bitfield.disp32 = 0;
5710 i.types[op].bitfield.disp32s = 0;
5711 i.types[op].bitfield.disp64 = 0;
5712 }
5713 else
5714 /* We only support 64bit displacement on constants. */
5715 i.types[op].bitfield.disp64 = 0;
5716 }
5717}
5718
5719/* Return 1 if there is a match in broadcast bytes between operand
5720 GIVEN and instruction template T. */
5721
5722static INLINE int
5723match_broadcast_size (const insn_template *t, unsigned int given)
5724{
5725 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5726 && i.types[given].bitfield.byte)
5727 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5728 && i.types[given].bitfield.word)
5729 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5730 && i.types[given].bitfield.dword)
5731 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5732 && i.types[given].bitfield.qword));
5733}
5734
5735/* Check if operands are valid for the instruction. */
5736
5737static int
5738check_VecOperands (const insn_template *t)
5739{
5740 unsigned int op;
5741 i386_cpu_flags cpu;
5742
5743 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5744 any one operand are implicity requiring AVX512VL support if the actual
5745 operand size is YMMword or XMMword. Since this function runs after
5746 template matching, there's no need to check for YMMword/XMMword in
5747 the template. */
5748 cpu = cpu_flags_and (t->cpu_flags, avx512);
5749 if (!cpu_flags_all_zero (&cpu)
5750 && !t->cpu_flags.bitfield.cpuavx512vl
5751 && !cpu_arch_flags.bitfield.cpuavx512vl)
5752 {
5753 for (op = 0; op < t->operands; ++op)
5754 {
5755 if (t->operand_types[op].bitfield.zmmword
5756 && (i.types[op].bitfield.ymmword
5757 || i.types[op].bitfield.xmmword))
5758 {
5759 i.error = unsupported;
5760 return 1;
5761 }
5762 }
5763 }
5764
5765 /* Without VSIB byte, we can't have a vector register for index. */
5766 if (!t->opcode_modifier.vecsib
5767 && i.index_reg
5768 && (i.index_reg->reg_type.bitfield.xmmword
5769 || i.index_reg->reg_type.bitfield.ymmword
5770 || i.index_reg->reg_type.bitfield.zmmword))
5771 {
5772 i.error = unsupported_vector_index_register;
5773 return 1;
5774 }
5775
5776 /* Check if default mask is allowed. */
5777 if (t->opcode_modifier.nodefmask
5778 && (!i.mask || i.mask->mask->reg_num == 0))
5779 {
5780 i.error = no_default_mask;
5781 return 1;
5782 }
5783
5784 /* For VSIB byte, we need a vector register for index, and all vector
5785 registers must be distinct. */
5786 if (t->opcode_modifier.vecsib)
5787 {
5788 if (!i.index_reg
5789 || !((t->opcode_modifier.vecsib == VecSIB128
5790 && i.index_reg->reg_type.bitfield.xmmword)
5791 || (t->opcode_modifier.vecsib == VecSIB256
5792 && i.index_reg->reg_type.bitfield.ymmword)
5793 || (t->opcode_modifier.vecsib == VecSIB512
5794 && i.index_reg->reg_type.bitfield.zmmword)))
5795 {
5796 i.error = invalid_vsib_address;
5797 return 1;
5798 }
5799
5800 gas_assert (i.reg_operands == 2 || i.mask);
5801 if (i.reg_operands == 2 && !i.mask)
5802 {
5803 gas_assert (i.types[0].bitfield.class == RegSIMD);
5804 gas_assert (i.types[0].bitfield.xmmword
5805 || i.types[0].bitfield.ymmword);
5806 gas_assert (i.types[2].bitfield.class == RegSIMD);
5807 gas_assert (i.types[2].bitfield.xmmword
5808 || i.types[2].bitfield.ymmword);
5809 if (operand_check == check_none)
5810 return 0;
5811 if (register_number (i.op[0].regs)
5812 != register_number (i.index_reg)
5813 && register_number (i.op[2].regs)
5814 != register_number (i.index_reg)
5815 && register_number (i.op[0].regs)
5816 != register_number (i.op[2].regs))
5817 return 0;
5818 if (operand_check == check_error)
5819 {
5820 i.error = invalid_vector_register_set;
5821 return 1;
5822 }
5823 as_warn (_("mask, index, and destination registers should be distinct"));
5824 }
5825 else if (i.reg_operands == 1 && i.mask)
5826 {
5827 if (i.types[1].bitfield.class == RegSIMD
5828 && (i.types[1].bitfield.xmmword
5829 || i.types[1].bitfield.ymmword
5830 || i.types[1].bitfield.zmmword)
5831 && (register_number (i.op[1].regs)
5832 == register_number (i.index_reg)))
5833 {
5834 if (operand_check == check_error)
5835 {
5836 i.error = invalid_vector_register_set;
5837 return 1;
5838 }
5839 if (operand_check != check_none)
5840 as_warn (_("index and destination registers should be distinct"));
5841 }
5842 }
5843 }
5844
5845 /* Check if broadcast is supported by the instruction and is applied
5846 to the memory operand. */
5847 if (i.broadcast)
5848 {
5849 i386_operand_type type, overlap;
5850
5851 /* Check if specified broadcast is supported in this instruction,
5852 and its broadcast bytes match the memory operand. */
5853 op = i.broadcast->operand;
5854 if (!t->opcode_modifier.broadcast
5855 || !(i.flags[op] & Operand_Mem)
5856 || (!i.types[op].bitfield.unspecified
5857 && !match_broadcast_size (t, op)))
5858 {
5859 bad_broadcast:
5860 i.error = unsupported_broadcast;
5861 return 1;
5862 }
5863
5864 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5865 * i.broadcast->type);
5866 operand_type_set (&type, 0);
5867 switch (i.broadcast->bytes)
5868 {
5869 case 2:
5870 type.bitfield.word = 1;
5871 break;
5872 case 4:
5873 type.bitfield.dword = 1;
5874 break;
5875 case 8:
5876 type.bitfield.qword = 1;
5877 break;
5878 case 16:
5879 type.bitfield.xmmword = 1;
5880 break;
5881 case 32:
5882 type.bitfield.ymmword = 1;
5883 break;
5884 case 64:
5885 type.bitfield.zmmword = 1;
5886 break;
5887 default:
5888 goto bad_broadcast;
5889 }
5890
5891 overlap = operand_type_and (type, t->operand_types[op]);
5892 if (t->operand_types[op].bitfield.class == RegSIMD
5893 && t->operand_types[op].bitfield.byte
5894 + t->operand_types[op].bitfield.word
5895 + t->operand_types[op].bitfield.dword
5896 + t->operand_types[op].bitfield.qword > 1)
5897 {
5898 overlap.bitfield.xmmword = 0;
5899 overlap.bitfield.ymmword = 0;
5900 overlap.bitfield.zmmword = 0;
5901 }
5902 if (operand_type_all_zero (&overlap))
5903 goto bad_broadcast;
5904
5905 if (t->opcode_modifier.checkregsize)
5906 {
5907 unsigned int j;
5908
5909 type.bitfield.baseindex = 1;
5910 for (j = 0; j < i.operands; ++j)
5911 {
5912 if (j != op
5913 && !operand_type_register_match(i.types[j],
5914 t->operand_types[j],
5915 type,
5916 t->operand_types[op]))
5917 goto bad_broadcast;
5918 }
5919 }
5920 }
5921 /* If broadcast is supported in this instruction, we need to check if
5922 operand of one-element size isn't specified without broadcast. */
5923 else if (t->opcode_modifier.broadcast && i.mem_operands)
5924 {
5925 /* Find memory operand. */
5926 for (op = 0; op < i.operands; op++)
5927 if (i.flags[op] & Operand_Mem)
5928 break;
5929 gas_assert (op < i.operands);
5930 /* Check size of the memory operand. */
5931 if (match_broadcast_size (t, op))
5932 {
5933 i.error = broadcast_needed;
5934 return 1;
5935 }
5936 }
5937 else
5938 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5939
5940 /* Check if requested masking is supported. */
5941 if (i.mask)
5942 {
5943 switch (t->opcode_modifier.masking)
5944 {
5945 case BOTH_MASKING:
5946 break;
5947 case MERGING_MASKING:
5948 if (i.mask->zeroing)
5949 {
5950 case 0:
5951 i.error = unsupported_masking;
5952 return 1;
5953 }
5954 break;
5955 case DYNAMIC_MASKING:
5956 /* Memory destinations allow only merging masking. */
5957 if (i.mask->zeroing && i.mem_operands)
5958 {
5959 /* Find memory operand. */
5960 for (op = 0; op < i.operands; op++)
5961 if (i.flags[op] & Operand_Mem)
5962 break;
5963 gas_assert (op < i.operands);
5964 if (op == i.operands - 1)
5965 {
5966 i.error = unsupported_masking;
5967 return 1;
5968 }
5969 }
5970 break;
5971 default:
5972 abort ();
5973 }
5974 }
5975
5976 /* Check if masking is applied to dest operand. */
5977 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5978 {
5979 i.error = mask_not_on_destination;
5980 return 1;
5981 }
5982
5983 /* Check RC/SAE. */
5984 if (i.rounding)
5985 {
5986 if (!t->opcode_modifier.sae
5987 || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding))
5988 {
5989 i.error = unsupported_rc_sae;
5990 return 1;
5991 }
5992 /* If the instruction has several immediate operands and one of
5993 them is rounding, the rounding operand should be the last
5994 immediate operand. */
5995 if (i.imm_operands > 1
5996 && i.rounding->operand != (int) (i.imm_operands - 1))
5997 {
5998 i.error = rc_sae_operand_not_last_imm;
5999 return 1;
6000 }
6001 }
6002
6003 /* Check the special Imm4 cases; must be the first operand. */
6004 if (t->cpu_flags.bitfield.cpuxop && t->operands == 5)
6005 {
6006 if (i.op[0].imms->X_op != O_constant
6007 || !fits_in_imm4 (i.op[0].imms->X_add_number))
6008 {
6009 i.error = bad_imm4;
6010 return 1;
6011 }
6012
6013 /* Turn off Imm<N> so that update_imm won't complain. */
6014 operand_type_set (&i.types[0], 0);
6015 }
6016
6017 /* Check vector Disp8 operand. */
6018 if (t->opcode_modifier.disp8memshift
6019 && i.disp_encoding != disp_encoding_32bit)
6020 {
6021 if (i.broadcast)
6022 i.memshift = t->opcode_modifier.broadcast - 1;
6023 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
6024 i.memshift = t->opcode_modifier.disp8memshift;
6025 else
6026 {
6027 const i386_operand_type *type = NULL;
6028
6029 i.memshift = 0;
6030 for (op = 0; op < i.operands; op++)
6031 if (i.flags[op] & Operand_Mem)
6032 {
6033 if (t->opcode_modifier.evex == EVEXLIG)
6034 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
6035 else if (t->operand_types[op].bitfield.xmmword
6036 + t->operand_types[op].bitfield.ymmword
6037 + t->operand_types[op].bitfield.zmmword <= 1)
6038 type = &t->operand_types[op];
6039 else if (!i.types[op].bitfield.unspecified)
6040 type = &i.types[op];
6041 }
6042 else if (i.types[op].bitfield.class == RegSIMD
6043 && t->opcode_modifier.evex != EVEXLIG)
6044 {
6045 if (i.types[op].bitfield.zmmword)
6046 i.memshift = 6;
6047 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
6048 i.memshift = 5;
6049 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
6050 i.memshift = 4;
6051 }
6052
6053 if (type)
6054 {
6055 if (type->bitfield.zmmword)
6056 i.memshift = 6;
6057 else if (type->bitfield.ymmword)
6058 i.memshift = 5;
6059 else if (type->bitfield.xmmword)
6060 i.memshift = 4;
6061 }
6062
6063 /* For the check in fits_in_disp8(). */
6064 if (i.memshift == 0)
6065 i.memshift = -1;
6066 }
6067
6068 for (op = 0; op < i.operands; op++)
6069 if (operand_type_check (i.types[op], disp)
6070 && i.op[op].disps->X_op == O_constant)
6071 {
6072 if (fits_in_disp8 (i.op[op].disps->X_add_number))
6073 {
6074 i.types[op].bitfield.disp8 = 1;
6075 return 0;
6076 }
6077 i.types[op].bitfield.disp8 = 0;
6078 }
6079 }
6080
6081 i.memshift = 0;
6082
6083 return 0;
6084}
6085
6086/* Check if encoding requirements are met by the instruction. */
6087
6088static int
6089VEX_check_encoding (const insn_template *t)
6090{
6091 if (i.vec_encoding == vex_encoding_error)
6092 {
6093 i.error = unsupported;
6094 return 1;
6095 }
6096
6097 if (i.vec_encoding == vex_encoding_evex)
6098 {
6099 /* This instruction must be encoded with EVEX prefix. */
6100 if (!is_evex_encoding (t))
6101 {
6102 i.error = unsupported;
6103 return 1;
6104 }
6105 return 0;
6106 }
6107
6108 if (!t->opcode_modifier.vex)
6109 {
6110 /* This instruction template doesn't have VEX prefix. */
6111 if (i.vec_encoding != vex_encoding_default)
6112 {
6113 i.error = unsupported;
6114 return 1;
6115 }
6116 return 0;
6117 }
6118
6119 return 0;
6120}
6121
6122static const insn_template *
6123match_template (char mnem_suffix)
6124{
6125 /* Points to template once we've found it. */
6126 const insn_template *t;
6127 i386_operand_type overlap0, overlap1, overlap2, overlap3;
6128 i386_operand_type overlap4;
6129 unsigned int found_reverse_match;
6130 i386_opcode_modifier suffix_check;
6131 i386_operand_type operand_types [MAX_OPERANDS];
6132 int addr_prefix_disp;
6133 unsigned int j, size_match, check_register;
6134 enum i386_error specific_error = 0;
6135
6136#if MAX_OPERANDS != 5
6137# error "MAX_OPERANDS must be 5."
6138#endif
6139
6140 found_reverse_match = 0;
6141 addr_prefix_disp = -1;
6142
6143 /* Prepare for mnemonic suffix check. */
6144 memset (&suffix_check, 0, sizeof (suffix_check));
6145 switch (mnem_suffix)
6146 {
6147 case BYTE_MNEM_SUFFIX:
6148 suffix_check.no_bsuf = 1;
6149 break;
6150 case WORD_MNEM_SUFFIX:
6151 suffix_check.no_wsuf = 1;
6152 break;
6153 case SHORT_MNEM_SUFFIX:
6154 suffix_check.no_ssuf = 1;
6155 break;
6156 case LONG_MNEM_SUFFIX:
6157 suffix_check.no_lsuf = 1;
6158 break;
6159 case QWORD_MNEM_SUFFIX:
6160 suffix_check.no_qsuf = 1;
6161 break;
6162 default:
6163 /* NB: In Intel syntax, normally we can check for memory operand
6164 size when there is no mnemonic suffix. But jmp and call have
6165 2 different encodings with Dword memory operand size, one with
6166 No_ldSuf and the other without. i.suffix is set to
6167 LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */
6168 if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
6169 suffix_check.no_ldsuf = 1;
6170 }
6171
6172 /* Must have right number of operands. */
6173 i.error = number_of_operands_mismatch;
6174
6175 for (t = current_templates->start; t < current_templates->end; t++)
6176 {
6177 addr_prefix_disp = -1;
6178 found_reverse_match = 0;
6179
6180 if (i.operands != t->operands)
6181 continue;
6182
6183 /* Check processor support. */
6184 i.error = unsupported;
6185 if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH)
6186 continue;
6187
6188 /* Check AT&T mnemonic. */
6189 i.error = unsupported_with_intel_mnemonic;
6190 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
6191 continue;
6192
6193 /* Check AT&T/Intel syntax. */
6194 i.error = unsupported_syntax;
6195 if ((intel_syntax && t->opcode_modifier.attsyntax)
6196 || (!intel_syntax && t->opcode_modifier.intelsyntax))
6197 continue;
6198
6199 /* Check Intel64/AMD64 ISA. */
6200 switch (isa64)
6201 {
6202 default:
6203 /* Default: Don't accept Intel64. */
6204 if (t->opcode_modifier.isa64 == INTEL64)
6205 continue;
6206 break;
6207 case amd64:
6208 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6209 if (t->opcode_modifier.isa64 >= INTEL64)
6210 continue;
6211 break;
6212 case intel64:
6213 /* -mintel64: Don't accept AMD64. */
6214 if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT)
6215 continue;
6216 break;
6217 }
6218
6219 /* Check the suffix. */
6220 i.error = invalid_instruction_suffix;
6221 if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
6222 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
6223 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
6224 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
6225 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
6226 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))
6227 continue;
6228
6229 size_match = operand_size_match (t);
6230 if (!size_match)
6231 continue;
6232
6233 /* This is intentionally not
6234
6235 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
6236
6237 as the case of a missing * on the operand is accepted (perhaps with
6238 a warning, issued further down). */
6239 if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE)
6240 {
6241 i.error = operand_type_mismatch;
6242 continue;
6243 }
6244
6245 for (j = 0; j < MAX_OPERANDS; j++)
6246 operand_types[j] = t->operand_types[j];
6247
6248 /* In general, don't allow
6249 - 64-bit operands outside of 64-bit mode,
6250 - 32-bit operands on pre-386. */
6251 j = i.imm_operands + (t->operands > i.imm_operands + 1);
6252 if (((i.suffix == QWORD_MNEM_SUFFIX
6253 && flag_code != CODE_64BIT
6254 && (t->base_opcode != 0x0fc7
6255 || t->extension_opcode != 1 /* cmpxchg8b */))
6256 || (i.suffix == LONG_MNEM_SUFFIX
6257 && !cpu_arch_flags.bitfield.cpui386))
6258 && (intel_syntax
6259 ? (t->opcode_modifier.mnemonicsize != IGNORESIZE
6260 && !intel_float_operand (t->name))
6261 : intel_float_operand (t->name) != 2)
6262 && (t->operands == i.imm_operands
6263 || (operand_types[i.imm_operands].bitfield.class != RegMMX
6264 && operand_types[i.imm_operands].bitfield.class != RegSIMD
6265 && operand_types[i.imm_operands].bitfield.class != RegMask)
6266 || (operand_types[j].bitfield.class != RegMMX
6267 && operand_types[j].bitfield.class != RegSIMD
6268 && operand_types[j].bitfield.class != RegMask))
6269 && !t->opcode_modifier.vecsib)
6270 continue;
6271
6272 /* Do not verify operands when there are none. */
6273 if (!t->operands)
6274 {
6275 if (VEX_check_encoding (t))
6276 {
6277 specific_error = i.error;
6278 continue;
6279 }
6280
6281 /* We've found a match; break out of loop. */
6282 break;
6283 }
6284
6285 if (!t->opcode_modifier.jump
6286 || t->opcode_modifier.jump == JUMP_ABSOLUTE)
6287 {
6288 /* There should be only one Disp operand. */
6289 for (j = 0; j < MAX_OPERANDS; j++)
6290 if (operand_type_check (operand_types[j], disp))
6291 break;
6292 if (j < MAX_OPERANDS)
6293 {
6294 bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0);
6295
6296 addr_prefix_disp = j;
6297
6298 /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
6299 operand into Disp32/Disp32/Disp16/Disp32 operand. */
6300 switch (flag_code)
6301 {
6302 case CODE_16BIT:
6303 override = !override;
6304 /* Fall through. */
6305 case CODE_32BIT:
6306 if (operand_types[j].bitfield.disp32
6307 && operand_types[j].bitfield.disp16)
6308 {
6309 operand_types[j].bitfield.disp16 = override;
6310 operand_types[j].bitfield.disp32 = !override;
6311 }
6312 operand_types[j].bitfield.disp32s = 0;
6313 operand_types[j].bitfield.disp64 = 0;
6314 break;
6315
6316 case CODE_64BIT:
6317 if (operand_types[j].bitfield.disp32s
6318 || operand_types[j].bitfield.disp64)
6319 {
6320 operand_types[j].bitfield.disp64 &= !override;
6321 operand_types[j].bitfield.disp32s &= !override;
6322 operand_types[j].bitfield.disp32 = override;
6323 }
6324 operand_types[j].bitfield.disp16 = 0;
6325 break;
6326 }
6327 }
6328 }
6329
6330 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
6331 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
6332 continue;
6333
6334 /* We check register size if needed. */
6335 if (t->opcode_modifier.checkregsize)
6336 {
6337 check_register = (1 << t->operands) - 1;
6338 if (i.broadcast)
6339 check_register &= ~(1 << i.broadcast->operand);
6340 }
6341 else
6342 check_register = 0;
6343
6344 overlap0 = operand_type_and (i.types[0], operand_types[0]);
6345 switch (t->operands)
6346 {
6347 case 1:
6348 if (!operand_type_match (overlap0, i.types[0]))
6349 continue;
6350 break;
6351 case 2:
6352 /* xchg %eax, %eax is a special case. It is an alias for nop
6353 only in 32bit mode and we can use opcode 0x90. In 64bit
6354 mode, we can't use 0x90 for xchg %eax, %eax since it should
6355 zero-extend %eax to %rax. */
6356 if (flag_code == CODE_64BIT
6357 && t->base_opcode == 0x90
6358 && i.types[0].bitfield.instance == Accum
6359 && i.types[0].bitfield.dword
6360 && i.types[1].bitfield.instance == Accum
6361 && i.types[1].bitfield.dword)
6362 continue;
6363 /* xrelease mov %eax, <disp> is another special case. It must not
6364 match the accumulator-only encoding of mov. */
6365 if (flag_code != CODE_64BIT
6366 && i.hle_prefix
6367 && t->base_opcode == 0xa0
6368 && i.types[0].bitfield.instance == Accum
6369 && (i.flags[1] & Operand_Mem))
6370 continue;
6371 /* Fall through. */
6372
6373 case 3:
6374 if (!(size_match & MATCH_STRAIGHT))
6375 goto check_reverse;
6376 /* Reverse direction of operands if swapping is possible in the first
6377 place (operands need to be symmetric) and
6378 - the load form is requested, and the template is a store form,
6379 - the store form is requested, and the template is a load form,
6380 - the non-default (swapped) form is requested. */
6381 overlap1 = operand_type_and (operand_types[0], operand_types[1]);
6382 if (t->opcode_modifier.d && i.reg_operands == i.operands
6383 && !operand_type_all_zero (&overlap1))
6384 switch (i.dir_encoding)
6385 {
6386 case dir_encoding_load:
6387 if (operand_type_check (operand_types[i.operands - 1], anymem)
6388 || t->opcode_modifier.regmem)
6389 goto check_reverse;
6390 break;
6391
6392 case dir_encoding_store:
6393 if (!operand_type_check (operand_types[i.operands - 1], anymem)
6394 && !t->opcode_modifier.regmem)
6395 goto check_reverse;
6396 break;
6397
6398 case dir_encoding_swap:
6399 goto check_reverse;
6400
6401 case dir_encoding_default:
6402 break;
6403 }
6404 /* If we want store form, we skip the current load. */
6405 if ((i.dir_encoding == dir_encoding_store
6406 || i.dir_encoding == dir_encoding_swap)
6407 && i.mem_operands == 0
6408 && t->opcode_modifier.load)
6409 continue;
6410 /* Fall through. */
6411 case 4:
6412 case 5:
6413 overlap1 = operand_type_and (i.types[1], operand_types[1]);
6414 if (!operand_type_match (overlap0, i.types[0])
6415 || !operand_type_match (overlap1, i.types[1])
6416 || ((check_register & 3) == 3
6417 && !operand_type_register_match (i.types[0],
6418 operand_types[0],
6419 i.types[1],
6420 operand_types[1])))
6421 {
6422 /* Check if other direction is valid ... */
6423 if (!t->opcode_modifier.d)
6424 continue;
6425
6426 check_reverse:
6427 if (!(size_match & MATCH_REVERSE))
6428 continue;
6429 /* Try reversing direction of operands. */
6430 overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]);
6431 overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]);
6432 if (!operand_type_match (overlap0, i.types[0])
6433 || !operand_type_match (overlap1, i.types[i.operands - 1])
6434 || (check_register
6435 && !operand_type_register_match (i.types[0],
6436 operand_types[i.operands - 1],
6437 i.types[i.operands - 1],
6438 operand_types[0])))
6439 {
6440 /* Does not match either direction. */
6441 continue;
6442 }
6443 /* found_reverse_match holds which of D or FloatR
6444 we've found. */
6445 if (!t->opcode_modifier.d)
6446 found_reverse_match = 0;
6447 else if (operand_types[0].bitfield.tbyte)
6448 found_reverse_match = Opcode_FloatD;
6449 else if (operand_types[0].bitfield.xmmword
6450 || operand_types[i.operands - 1].bitfield.xmmword
6451 || operand_types[0].bitfield.class == RegMMX
6452 || operand_types[i.operands - 1].bitfield.class == RegMMX
6453 || is_any_vex_encoding(t))
6454 found_reverse_match = (t->base_opcode & 0xee) != 0x6e
6455 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
6456 else
6457 found_reverse_match = Opcode_D;
6458 if (t->opcode_modifier.floatr)
6459 found_reverse_match |= Opcode_FloatR;
6460 }
6461 else
6462 {
6463 /* Found a forward 2 operand match here. */
6464 switch (t->operands)
6465 {
6466 case 5:
6467 overlap4 = operand_type_and (i.types[4],
6468 operand_types[4]);
6469 /* Fall through. */
6470 case 4:
6471 overlap3 = operand_type_and (i.types[3],
6472 operand_types[3]);
6473 /* Fall through. */
6474 case 3:
6475 overlap2 = operand_type_and (i.types[2],
6476 operand_types[2]);
6477 break;
6478 }
6479
6480 switch (t->operands)
6481 {
6482 case 5:
6483 if (!operand_type_match (overlap4, i.types[4])
6484 || !operand_type_register_match (i.types[3],
6485 operand_types[3],
6486 i.types[4],
6487 operand_types[4]))
6488 continue;
6489 /* Fall through. */
6490 case 4:
6491 if (!operand_type_match (overlap3, i.types[3])
6492 || ((check_register & 0xa) == 0xa
6493 && !operand_type_register_match (i.types[1],
6494 operand_types[1],
6495 i.types[3],
6496 operand_types[3]))
6497 || ((check_register & 0xc) == 0xc
6498 && !operand_type_register_match (i.types[2],
6499 operand_types[2],
6500 i.types[3],
6501 operand_types[3])))
6502 continue;
6503 /* Fall through. */
6504 case 3:
6505 /* Here we make use of the fact that there are no
6506 reverse match 3 operand instructions. */
6507 if (!operand_type_match (overlap2, i.types[2])
6508 || ((check_register & 5) == 5
6509 && !operand_type_register_match (i.types[0],
6510 operand_types[0],
6511 i.types[2],
6512 operand_types[2]))
6513 || ((check_register & 6) == 6
6514 && !operand_type_register_match (i.types[1],
6515 operand_types[1],
6516 i.types[2],
6517 operand_types[2])))
6518 continue;
6519 break;
6520 }
6521 }
6522 /* Found either forward/reverse 2, 3 or 4 operand match here:
6523 slip through to break. */
6524 }
6525
6526 /* Check if vector operands are valid. */
6527 if (check_VecOperands (t))
6528 {
6529 specific_error = i.error;
6530 continue;
6531 }
6532
6533 /* Check if VEX/EVEX encoding requirements can be satisfied. */
6534 if (VEX_check_encoding (t))
6535 {
6536 specific_error = i.error;
6537 continue;
6538 }
6539
6540 /* We've found a match; break out of loop. */
6541 break;
6542 }
6543
6544 if (t == current_templates->end)
6545 {
6546 /* We found no match. */
6547 const char *err_msg;
6548 switch (specific_error ? specific_error : i.error)
6549 {
6550 default:
6551 abort ();
6552 case operand_size_mismatch:
6553 err_msg = _("operand size mismatch");
6554 break;
6555 case operand_type_mismatch:
6556 err_msg = _("operand type mismatch");
6557 break;
6558 case register_type_mismatch:
6559 err_msg = _("register type mismatch");
6560 break;
6561 case number_of_operands_mismatch:
6562 err_msg = _("number of operands mismatch");
6563 break;
6564 case invalid_instruction_suffix:
6565 err_msg = _("invalid instruction suffix");
6566 break;
6567 case bad_imm4:
6568 err_msg = _("constant doesn't fit in 4 bits");
6569 break;
6570 case unsupported_with_intel_mnemonic:
6571 err_msg = _("unsupported with Intel mnemonic");
6572 break;
6573 case unsupported_syntax:
6574 err_msg = _("unsupported syntax");
6575 break;
6576 case unsupported:
6577 as_bad (_("unsupported instruction `%s'"),
6578 current_templates->start->name);
6579 return NULL;
6580 case invalid_vsib_address:
6581 err_msg = _("invalid VSIB address");
6582 break;
6583 case invalid_vector_register_set:
6584 err_msg = _("mask, index, and destination registers must be distinct");
6585 break;
6586 case unsupported_vector_index_register:
6587 err_msg = _("unsupported vector index register");
6588 break;
6589 case unsupported_broadcast:
6590 err_msg = _("unsupported broadcast");
6591 break;
6592 case broadcast_needed:
6593 err_msg = _("broadcast is needed for operand of such type");
6594 break;
6595 case unsupported_masking:
6596 err_msg = _("unsupported masking");
6597 break;
6598 case mask_not_on_destination:
6599 err_msg = _("mask not on destination operand");
6600 break;
6601 case no_default_mask:
6602 err_msg = _("default mask isn't allowed");
6603 break;
6604 case unsupported_rc_sae:
6605 err_msg = _("unsupported static rounding/sae");
6606 break;
6607 case rc_sae_operand_not_last_imm:
6608 if (intel_syntax)
6609 err_msg = _("RC/SAE operand must precede immediate operands");
6610 else
6611 err_msg = _("RC/SAE operand must follow immediate operands");
6612 break;
6613 case invalid_register_operand:
6614 err_msg = _("invalid register operand");
6615 break;
6616 }
6617 as_bad (_("%s for `%s'"), err_msg,
6618 current_templates->start->name);
6619 return NULL;
6620 }
6621
6622 if (!quiet_warnings)
6623 {
6624 if (!intel_syntax
6625 && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)))
6626 as_warn (_("indirect %s without `*'"), t->name);
6627
6628 if (t->opcode_modifier.isprefix
6629 && t->opcode_modifier.mnemonicsize == IGNORESIZE)
6630 {
6631 /* Warn them that a data or address size prefix doesn't
6632 affect assembly of the next line of code. */
6633 as_warn (_("stand-alone `%s' prefix"), t->name);
6634 }
6635 }
6636
6637 /* Copy the template we found. */
6638 i.tm = *t;
6639
6640 if (addr_prefix_disp != -1)
6641 i.tm.operand_types[addr_prefix_disp]
6642 = operand_types[addr_prefix_disp];
6643
6644 if (found_reverse_match)
6645 {
6646 /* If we found a reverse match we must alter the opcode direction
6647 bit and clear/flip the regmem modifier one. found_reverse_match
6648 holds bits to change (different for int & float insns). */
6649
6650 i.tm.base_opcode ^= found_reverse_match;
6651
6652 i.tm.operand_types[0] = operand_types[i.operands - 1];
6653 i.tm.operand_types[i.operands - 1] = operand_types[0];
6654
6655 /* Certain SIMD insns have their load forms specified in the opcode
6656 table, and hence we need to _set_ RegMem instead of clearing it.
6657 We need to avoid setting the bit though on insns like KMOVW. */
6658 i.tm.opcode_modifier.regmem
6659 = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d
6660 && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx
6661 && !i.tm.opcode_modifier.regmem;
6662 }
6663
6664 return t;
6665}
6666
6667static int
6668check_string (void)
6669{
6670 unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0;
6671 unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0;
6672
6673 if (i.seg[op] != NULL && i.seg[op] != &es)
6674 {
6675 as_bad (_("`%s' operand %u must use `%ses' segment"),
6676 i.tm.name,
6677 intel_syntax ? i.tm.operands - es_op : es_op + 1,
6678 register_prefix);
6679 return 0;
6680 }
6681
6682 /* There's only ever one segment override allowed per instruction.
6683 This instruction possibly has a legal segment override on the
6684 second operand, so copy the segment to where non-string
6685 instructions store it, allowing common code. */
6686 i.seg[op] = i.seg[1];
6687
6688 return 1;
6689}
6690
6691static int
6692process_suffix (void)
6693{
6694 /* If matched instruction specifies an explicit instruction mnemonic
6695 suffix, use it. */
6696 if (i.tm.opcode_modifier.size == SIZE16)
6697 i.suffix = WORD_MNEM_SUFFIX;
6698 else if (i.tm.opcode_modifier.size == SIZE32)
6699 i.suffix = LONG_MNEM_SUFFIX;
6700 else if (i.tm.opcode_modifier.size == SIZE64)
6701 i.suffix = QWORD_MNEM_SUFFIX;
6702 else if (i.reg_operands
6703 && (i.operands > 1 || i.types[0].bitfield.class == Reg)
6704 && !i.tm.opcode_modifier.addrprefixopreg)
6705 {
6706 unsigned int numop = i.operands;
6707
6708 /* movsx/movzx want only their source operand considered here, for the
6709 ambiguity checking below. The suffix will be replaced afterwards
6710 to represent the destination (register). */
6711 if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w)
6712 || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64))
6713 --i.operands;
6714
6715 /* crc32 needs REX.W set regardless of suffix / source operand size. */
6716 if (i.tm.base_opcode == 0xf20f38f0
6717 && i.tm.operand_types[1].bitfield.qword)
6718 i.rex |= REX_W;
6719
6720 /* If there's no instruction mnemonic suffix we try to invent one
6721 based on GPR operands. */
6722 if (!i.suffix)
6723 {
6724 /* We take i.suffix from the last register operand specified,
6725 Destination register type is more significant than source
6726 register type. crc32 in SSE4.2 prefers source register
6727 type. */
6728 unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1;
6729
6730 while (op--)
6731 if (i.tm.operand_types[op].bitfield.instance == InstanceNone
6732 || i.tm.operand_types[op].bitfield.instance == Accum)
6733 {
6734 if (i.types[op].bitfield.class != Reg)
6735 continue;
6736 if (i.types[op].bitfield.byte)
6737 i.suffix = BYTE_MNEM_SUFFIX;
6738 else if (i.types[op].bitfield.word)
6739 i.suffix = WORD_MNEM_SUFFIX;
6740 else if (i.types[op].bitfield.dword)
6741 i.suffix = LONG_MNEM_SUFFIX;
6742 else if (i.types[op].bitfield.qword)
6743 i.suffix = QWORD_MNEM_SUFFIX;
6744 else
6745 continue;
6746 break;
6747 }
6748
6749 /* As an exception, movsx/movzx silently default to a byte source
6750 in AT&T mode. */
6751 if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w
6752 && !i.suffix && !intel_syntax)
6753 i.suffix = BYTE_MNEM_SUFFIX;
6754 }
6755 else if (i.suffix == BYTE_MNEM_SUFFIX)
6756 {
6757 if (intel_syntax
6758 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6759 && i.tm.opcode_modifier.no_bsuf)
6760 i.suffix = 0;
6761 else if (!check_byte_reg ())
6762 return 0;
6763 }
6764 else if (i.suffix == LONG_MNEM_SUFFIX)
6765 {
6766 if (intel_syntax
6767 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6768 && i.tm.opcode_modifier.no_lsuf
6769 && !i.tm.opcode_modifier.todword
6770 && !i.tm.opcode_modifier.toqword)
6771 i.suffix = 0;
6772 else if (!check_long_reg ())
6773 return 0;
6774 }
6775 else if (i.suffix == QWORD_MNEM_SUFFIX)
6776 {
6777 if (intel_syntax
6778 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6779 && i.tm.opcode_modifier.no_qsuf
6780 && !i.tm.opcode_modifier.todword
6781 && !i.tm.opcode_modifier.toqword)
6782 i.suffix = 0;
6783 else if (!check_qword_reg ())
6784 return 0;
6785 }
6786 else if (i.suffix == WORD_MNEM_SUFFIX)
6787 {
6788 if (intel_syntax
6789 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE
6790 && i.tm.opcode_modifier.no_wsuf)
6791 i.suffix = 0;
6792 else if (!check_word_reg ())
6793 return 0;
6794 }
6795 else if (intel_syntax
6796 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE)
6797 /* Do nothing if the instruction is going to ignore the prefix. */
6798 ;
6799 else
6800 abort ();
6801
6802 /* Undo the movsx/movzx change done above. */
6803 i.operands = numop;
6804 }
6805 else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE
6806 && !i.suffix)
6807 {
6808 i.suffix = stackop_size;
6809 if (stackop_size == LONG_MNEM_SUFFIX)
6810 {
6811 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6812 .code16gcc directive to support 16-bit mode with
6813 32-bit address. For IRET without a suffix, generate
6814 16-bit IRET (opcode 0xcf) to return from an interrupt
6815 handler. */
6816 if (i.tm.base_opcode == 0xcf)
6817 {
6818 i.suffix = WORD_MNEM_SUFFIX;
6819 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6820 }
6821 /* Warn about changed behavior for segment register push/pop. */
6822 else if ((i.tm.base_opcode | 1) == 0x07)
6823 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
6824 i.tm.name);
6825 }
6826 }
6827 else if (!i.suffix
6828 && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE
6829 || i.tm.opcode_modifier.jump == JUMP_BYTE
6830 || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT
6831 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6832 && i.tm.extension_opcode <= 3)))
6833 {
6834 switch (flag_code)
6835 {
6836 case CODE_64BIT:
6837 if (!i.tm.opcode_modifier.no_qsuf)
6838 {
6839 if (i.tm.opcode_modifier.jump == JUMP_BYTE
6840 || i.tm.opcode_modifier.no_lsuf)
6841 i.suffix = QWORD_MNEM_SUFFIX;
6842 break;
6843 }
6844 /* Fall through. */
6845 case CODE_32BIT:
6846 if (!i.tm.opcode_modifier.no_lsuf)
6847 i.suffix = LONG_MNEM_SUFFIX;
6848 break;
6849 case CODE_16BIT:
6850 if (!i.tm.opcode_modifier.no_wsuf)
6851 i.suffix = WORD_MNEM_SUFFIX;
6852 break;
6853 }
6854 }
6855
6856 if (!i.suffix
6857 && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
6858 /* Also cover lret/retf/iret in 64-bit mode. */
6859 || (flag_code == CODE_64BIT
6860 && !i.tm.opcode_modifier.no_lsuf
6861 && !i.tm.opcode_modifier.no_qsuf))
6862 && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
6863 /* Accept FLDENV et al without suffix. */
6864 && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf))
6865 {
6866 unsigned int suffixes, evex = 0;
6867
6868 suffixes = !i.tm.opcode_modifier.no_bsuf;
6869 if (!i.tm.opcode_modifier.no_wsuf)
6870 suffixes |= 1 << 1;
6871 if (!i.tm.opcode_modifier.no_lsuf)
6872 suffixes |= 1 << 2;
6873 if (!i.tm.opcode_modifier.no_ldsuf)
6874 suffixes |= 1 << 3;
6875 if (!i.tm.opcode_modifier.no_ssuf)
6876 suffixes |= 1 << 4;
6877 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6878 suffixes |= 1 << 5;
6879
6880 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
6881 also suitable for AT&T syntax mode, it was requested that this be
6882 restricted to just Intel syntax. */
6883 if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast)
6884 {
6885 unsigned int op;
6886
6887 for (op = 0; op < i.tm.operands; ++op)
6888 {
6889 if (is_evex_encoding (&i.tm)
6890 && !cpu_arch_flags.bitfield.cpuavx512vl)
6891 {
6892 if (i.tm.operand_types[op].bitfield.ymmword)
6893 i.tm.operand_types[op].bitfield.xmmword = 0;
6894 if (i.tm.operand_types[op].bitfield.zmmword)
6895 i.tm.operand_types[op].bitfield.ymmword = 0;
6896 if (!i.tm.opcode_modifier.evex
6897 || i.tm.opcode_modifier.evex == EVEXDYN)
6898 i.tm.opcode_modifier.evex = EVEX512;
6899 }
6900
6901 if (i.tm.operand_types[op].bitfield.xmmword
6902 + i.tm.operand_types[op].bitfield.ymmword
6903 + i.tm.operand_types[op].bitfield.zmmword < 2)
6904 continue;
6905
6906 /* Any properly sized operand disambiguates the insn. */
6907 if (i.types[op].bitfield.xmmword
6908 || i.types[op].bitfield.ymmword
6909 || i.types[op].bitfield.zmmword)
6910 {
6911 suffixes &= ~(7 << 6);
6912 evex = 0;
6913 break;
6914 }
6915
6916 if ((i.flags[op] & Operand_Mem)
6917 && i.tm.operand_types[op].bitfield.unspecified)
6918 {
6919 if (i.tm.operand_types[op].bitfield.xmmword)
6920 suffixes |= 1 << 6;
6921 if (i.tm.operand_types[op].bitfield.ymmword)
6922 suffixes |= 1 << 7;
6923 if (i.tm.operand_types[op].bitfield.zmmword)
6924 suffixes |= 1 << 8;
6925 if (is_evex_encoding (&i.tm))
6926 evex = EVEX512;
6927 }
6928 }
6929 }
6930
6931 /* Are multiple suffixes / operand sizes allowed? */
6932 if (suffixes & (suffixes - 1))
6933 {
6934 if (intel_syntax
6935 && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
6936 || operand_check == check_error))
6937 {
6938 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6939 return 0;
6940 }
6941 if (operand_check == check_error)
6942 {
6943 as_bad (_("no instruction mnemonic suffix given and "
6944 "no register operands; can't size `%s'"), i.tm.name);
6945 return 0;
6946 }
6947 if (operand_check == check_warning)
6948 as_warn (_("%s; using default for `%s'"),
6949 intel_syntax
6950 ? _("ambiguous operand size")
6951 : _("no instruction mnemonic suffix given and "
6952 "no register operands"),
6953 i.tm.name);
6954
6955 if (i.tm.opcode_modifier.floatmf)
6956 i.suffix = SHORT_MNEM_SUFFIX;
6957 else if ((i.tm.base_opcode | 8) == 0xfbe
6958 || (i.tm.base_opcode == 0x63
6959 && i.tm.cpu_flags.bitfield.cpu64))
6960 /* handled below */;
6961 else if (evex)
6962 i.tm.opcode_modifier.evex = evex;
6963 else if (flag_code == CODE_16BIT)
6964 i.suffix = WORD_MNEM_SUFFIX;
6965 else if (!i.tm.opcode_modifier.no_lsuf)
6966 i.suffix = LONG_MNEM_SUFFIX;
6967 else
6968 i.suffix = QWORD_MNEM_SUFFIX;
6969 }
6970 }
6971
6972 if ((i.tm.base_opcode | 8) == 0xfbe
6973 || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64))
6974 {
6975 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
6976 In AT&T syntax, if there is no suffix (warned about above), the default
6977 will be byte extension. */
6978 if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
6979 i.tm.base_opcode |= 1;
6980
6981 /* For further processing, the suffix should represent the destination
6982 (register). This is already the case when one was used with
6983 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
6984 no suffix to begin with. */
6985 if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix)
6986 {
6987 if (i.types[1].bitfield.word)
6988 i.suffix = WORD_MNEM_SUFFIX;
6989 else if (i.types[1].bitfield.qword)
6990 i.suffix = QWORD_MNEM_SUFFIX;
6991 else
6992 i.suffix = LONG_MNEM_SUFFIX;
6993
6994 i.tm.opcode_modifier.w = 0;
6995 }
6996 }
6997
6998 if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3)
6999 i.short_form = (i.tm.operand_types[0].bitfield.class == Reg)
7000 != (i.tm.operand_types[1].bitfield.class == Reg);
7001
7002 /* Change the opcode based on the operand size given by i.suffix. */
7003 switch (i.suffix)
7004 {
7005 /* Size floating point instruction. */
7006 case LONG_MNEM_SUFFIX:
7007 if (i.tm.opcode_modifier.floatmf)
7008 {
7009 i.tm.base_opcode ^= 4;
7010 break;
7011 }
7012 /* fall through */
7013 case WORD_MNEM_SUFFIX:
7014 case QWORD_MNEM_SUFFIX:
7015 /* It's not a byte, select word/dword operation. */
7016 if (i.tm.opcode_modifier.w)
7017 {
7018 if (i.short_form)
7019 i.tm.base_opcode |= 8;
7020 else
7021 i.tm.base_opcode |= 1;
7022 }
7023 /* fall through */
7024 case SHORT_MNEM_SUFFIX:
7025 /* Now select between word & dword operations via the operand
7026 size prefix, except for instructions that will ignore this
7027 prefix anyway. */
7028 if (i.suffix != QWORD_MNEM_SUFFIX
7029 && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
7030 && !i.tm.opcode_modifier.floatmf
7031 && !is_any_vex_encoding (&i.tm)
7032 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
7033 || (flag_code == CODE_64BIT
7034 && i.tm.opcode_modifier.jump == JUMP_BYTE)))
7035 {
7036 unsigned int prefix = DATA_PREFIX_OPCODE;
7037
7038 if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */
7039 prefix = ADDR_PREFIX_OPCODE;
7040
7041 if (!add_prefix (prefix))
7042 return 0;
7043 }
7044
7045 /* Set mode64 for an operand. */
7046 if (i.suffix == QWORD_MNEM_SUFFIX
7047 && flag_code == CODE_64BIT
7048 && !i.tm.opcode_modifier.norex64
7049 && !i.tm.opcode_modifier.vexw
7050 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7051 need rex64. */
7052 && ! (i.operands == 2
7053 && i.tm.base_opcode == 0x90
7054 && i.tm.extension_opcode == None
7055 && i.types[0].bitfield.instance == Accum
7056 && i.types[0].bitfield.qword
7057 && i.types[1].bitfield.instance == Accum
7058 && i.types[1].bitfield.qword))
7059 i.rex |= REX_W;
7060
7061 break;
7062 }
7063
7064 if (i.tm.opcode_modifier.addrprefixopreg)
7065 {
7066 gas_assert (!i.suffix);
7067 gas_assert (i.reg_operands);
7068
7069 if (i.tm.operand_types[0].bitfield.instance == Accum
7070 || i.operands == 1)
7071 {
7072 /* The address size override prefix changes the size of the
7073 first operand. */
7074 if (flag_code == CODE_64BIT
7075 && i.op[0].regs->reg_type.bitfield.word)
7076 {
7077 as_bad (_("16-bit addressing unavailable for `%s'"),
7078 i.tm.name);
7079 return 0;
7080 }
7081
7082 if ((flag_code == CODE_32BIT
7083 ? i.op[0].regs->reg_type.bitfield.word
7084 : i.op[0].regs->reg_type.bitfield.dword)
7085 && !add_prefix (ADDR_PREFIX_OPCODE))
7086 return 0;
7087 }
7088 else
7089 {
7090 /* Check invalid register operand when the address size override
7091 prefix changes the size of register operands. */
7092 unsigned int op;
7093 enum { need_word, need_dword, need_qword } need;
7094
7095 if (flag_code == CODE_32BIT)
7096 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
7097 else if (i.prefix[ADDR_PREFIX])
7098 need = need_dword;
7099 else
7100 need = flag_code == CODE_64BIT ? need_qword : need_word;
7101
7102 for (op = 0; op < i.operands; op++)
7103 {
7104 if (i.types[op].bitfield.class != Reg)
7105 continue;
7106
7107 switch (need)
7108 {
7109 case need_word:
7110 if (i.op[op].regs->reg_type.bitfield.word)
7111 continue;
7112 break;
7113 case need_dword:
7114 if (i.op[op].regs->reg_type.bitfield.dword)
7115 continue;
7116 break;
7117 case need_qword:
7118 if (i.op[op].regs->reg_type.bitfield.qword)
7119 continue;
7120 break;
7121 }
7122
7123 as_bad (_("invalid register operand size for `%s'"),
7124 i.tm.name);
7125 return 0;
7126 }
7127 }
7128 }
7129
7130 return 1;
7131}
7132
7133static int
7134check_byte_reg (void)
7135{
7136 int op;
7137
7138 for (op = i.operands; --op >= 0;)
7139 {
7140 /* Skip non-register operands. */
7141 if (i.types[op].bitfield.class != Reg)
7142 continue;
7143
7144 /* If this is an eight bit register, it's OK. If it's the 16 or
7145 32 bit version of an eight bit register, we will just use the
7146 low portion, and that's OK too. */
7147 if (i.types[op].bitfield.byte)
7148 continue;
7149
7150 /* I/O port address operands are OK too. */
7151 if (i.tm.operand_types[op].bitfield.instance == RegD
7152 && i.tm.operand_types[op].bitfield.word)
7153 continue;
7154
7155 /* crc32 only wants its source operand checked here. */
7156 if (i.tm.base_opcode == 0xf20f38f0 && op)
7157 continue;
7158
7159 /* Any other register is bad. */
7160 as_bad (_("`%s%s' not allowed with `%s%c'"),
7161 register_prefix, i.op[op].regs->reg_name,
7162 i.tm.name, i.suffix);
7163 return 0;
7164 }
7165 return 1;
7166}
7167
7168static int
7169check_long_reg (void)
7170{
7171 int op;
7172
7173 for (op = i.operands; --op >= 0;)
7174 /* Skip non-register operands. */
7175 if (i.types[op].bitfield.class != Reg)
7176 continue;
7177 /* Reject eight bit registers, except where the template requires
7178 them. (eg. movzb) */
7179 else if (i.types[op].bitfield.byte
7180 && (i.tm.operand_types[op].bitfield.class == Reg
7181 || i.tm.operand_types[op].bitfield.instance == Accum)
7182 && (i.tm.operand_types[op].bitfield.word
7183 || i.tm.operand_types[op].bitfield.dword))
7184 {
7185 as_bad (_("`%s%s' not allowed with `%s%c'"),
7186 register_prefix,
7187 i.op[op].regs->reg_name,
7188 i.tm.name,
7189 i.suffix);
7190 return 0;
7191 }
7192 /* Error if the e prefix on a general reg is missing. */
7193 else if (i.types[op].bitfield.word
7194 && (i.tm.operand_types[op].bitfield.class == Reg
7195 || i.tm.operand_types[op].bitfield.instance == Accum)
7196 && i.tm.operand_types[op].bitfield.dword)
7197 {
7198 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7199 register_prefix, i.op[op].regs->reg_name,
7200 i.suffix);
7201 return 0;
7202 }
7203 /* Warn if the r prefix on a general reg is present. */
7204 else if (i.types[op].bitfield.qword
7205 && (i.tm.operand_types[op].bitfield.class == Reg
7206 || i.tm.operand_types[op].bitfield.instance == Accum)
7207 && i.tm.operand_types[op].bitfield.dword)
7208 {
7209 if (intel_syntax
7210 && i.tm.opcode_modifier.toqword
7211 && i.types[0].bitfield.class != RegSIMD)
7212 {
7213 /* Convert to QWORD. We want REX byte. */
7214 i.suffix = QWORD_MNEM_SUFFIX;
7215 }
7216 else
7217 {
7218 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7219 register_prefix, i.op[op].regs->reg_name,
7220 i.suffix);
7221 return 0;
7222 }
7223 }
7224 return 1;
7225}
7226
7227static int
7228check_qword_reg (void)
7229{
7230 int op;
7231
7232 for (op = i.operands; --op >= 0; )
7233 /* Skip non-register operands. */
7234 if (i.types[op].bitfield.class != Reg)
7235 continue;
7236 /* Reject eight bit registers, except where the template requires
7237 them. (eg. movzb) */
7238 else if (i.types[op].bitfield.byte
7239 && (i.tm.operand_types[op].bitfield.class == Reg
7240 || i.tm.operand_types[op].bitfield.instance == Accum)
7241 && (i.tm.operand_types[op].bitfield.word
7242 || i.tm.operand_types[op].bitfield.dword))
7243 {
7244 as_bad (_("`%s%s' not allowed with `%s%c'"),
7245 register_prefix,
7246 i.op[op].regs->reg_name,
7247 i.tm.name,
7248 i.suffix);
7249 return 0;
7250 }
7251 /* Warn if the r prefix on a general reg is missing. */
7252 else if ((i.types[op].bitfield.word
7253 || i.types[op].bitfield.dword)
7254 && (i.tm.operand_types[op].bitfield.class == Reg
7255 || i.tm.operand_types[op].bitfield.instance == Accum)
7256 && i.tm.operand_types[op].bitfield.qword)
7257 {
7258 /* Prohibit these changes in the 64bit mode, since the
7259 lowering is more complicated. */
7260 if (intel_syntax
7261 && i.tm.opcode_modifier.todword
7262 && i.types[0].bitfield.class != RegSIMD)
7263 {
7264 /* Convert to DWORD. We don't want REX byte. */
7265 i.suffix = LONG_MNEM_SUFFIX;
7266 }
7267 else
7268 {
7269 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7270 register_prefix, i.op[op].regs->reg_name,
7271 i.suffix);
7272 return 0;
7273 }
7274 }
7275 return 1;
7276}
7277
7278static int
7279check_word_reg (void)
7280{
7281 int op;
7282 for (op = i.operands; --op >= 0;)
7283 /* Skip non-register operands. */
7284 if (i.types[op].bitfield.class != Reg)
7285 continue;
7286 /* Reject eight bit registers, except where the template requires
7287 them. (eg. movzb) */
7288 else if (i.types[op].bitfield.byte
7289 && (i.tm.operand_types[op].bitfield.class == Reg
7290 || i.tm.operand_types[op].bitfield.instance == Accum)
7291 && (i.tm.operand_types[op].bitfield.word
7292 || i.tm.operand_types[op].bitfield.dword))
7293 {
7294 as_bad (_("`%s%s' not allowed with `%s%c'"),
7295 register_prefix,
7296 i.op[op].regs->reg_name,
7297 i.tm.name,
7298 i.suffix);
7299 return 0;
7300 }
7301 /* Error if the e or r prefix on a general reg is present. */
7302 else if ((i.types[op].bitfield.dword
7303 || i.types[op].bitfield.qword)
7304 && (i.tm.operand_types[op].bitfield.class == Reg
7305 || i.tm.operand_types[op].bitfield.instance == Accum)
7306 && i.tm.operand_types[op].bitfield.word)
7307 {
7308 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
7309 register_prefix, i.op[op].regs->reg_name,
7310 i.suffix);
7311 return 0;
7312 }
7313 return 1;
7314}
7315
7316static int
7317update_imm (unsigned int j)
7318{
7319 i386_operand_type overlap = i.types[j];
7320 if ((overlap.bitfield.imm8
7321 || overlap.bitfield.imm8s
7322 || overlap.bitfield.imm16
7323 || overlap.bitfield.imm32
7324 || overlap.bitfield.imm32s
7325 || overlap.bitfield.imm64)
7326 && !operand_type_equal (&overlap, &imm8)
7327 && !operand_type_equal (&overlap, &imm8s)
7328 && !operand_type_equal (&overlap, &imm16)
7329 && !operand_type_equal (&overlap, &imm32)
7330 && !operand_type_equal (&overlap, &imm32s)
7331 && !operand_type_equal (&overlap, &imm64))
7332 {
7333 if (i.suffix)
7334 {
7335 i386_operand_type temp;
7336
7337 operand_type_set (&temp, 0);
7338 if (i.suffix == BYTE_MNEM_SUFFIX)
7339 {
7340 temp.bitfield.imm8 = overlap.bitfield.imm8;
7341 temp.bitfield.imm8s = overlap.bitfield.imm8s;
7342 }
7343 else if (i.suffix == WORD_MNEM_SUFFIX)
7344 temp.bitfield.imm16 = overlap.bitfield.imm16;
7345 else if (i.suffix == QWORD_MNEM_SUFFIX)
7346 {
7347 temp.bitfield.imm64 = overlap.bitfield.imm64;
7348 temp.bitfield.imm32s = overlap.bitfield.imm32s;
7349 }
7350 else
7351 temp.bitfield.imm32 = overlap.bitfield.imm32;
7352 overlap = temp;
7353 }
7354 else if (operand_type_equal (&overlap, &imm16_32_32s)
7355 || operand_type_equal (&overlap, &imm16_32)
7356 || operand_type_equal (&overlap, &imm16_32s))
7357 {
7358 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
7359 overlap = imm16;
7360 else
7361 overlap = imm32s;
7362 }
7363 if (!operand_type_equal (&overlap, &imm8)
7364 && !operand_type_equal (&overlap, &imm8s)
7365 && !operand_type_equal (&overlap, &imm16)
7366 && !operand_type_equal (&overlap, &imm32)
7367 && !operand_type_equal (&overlap, &imm32s)
7368 && !operand_type_equal (&overlap, &imm64))
7369 {
7370 as_bad (_("no instruction mnemonic suffix given; "
7371 "can't determine immediate size"));
7372 return 0;
7373 }
7374 }
7375 i.types[j] = overlap;
7376
7377 return 1;
7378}
7379
7380static int
7381finalize_imm (void)
7382{
7383 unsigned int j, n;
7384
7385 /* Update the first 2 immediate operands. */
7386 n = i.operands > 2 ? 2 : i.operands;
7387 if (n)
7388 {
7389 for (j = 0; j < n; j++)
7390 if (update_imm (j) == 0)
7391 return 0;
7392
7393 /* The 3rd operand can't be immediate operand. */
7394 gas_assert (operand_type_check (i.types[2], imm) == 0);
7395 }
7396
7397 return 1;
7398}
7399
7400static int
7401process_operands (void)
7402{
7403 /* Default segment register this instruction will use for memory
7404 accesses. 0 means unknown. This is only for optimizing out
7405 unnecessary segment overrides. */
7406 const seg_entry *default_seg = 0;
7407
7408 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
7409 {
7410 unsigned int dupl = i.operands;
7411 unsigned int dest = dupl - 1;
7412 unsigned int j;
7413
7414 /* The destination must be an xmm register. */
7415 gas_assert (i.reg_operands
7416 && MAX_OPERANDS > dupl
7417 && operand_type_equal (&i.types[dest], &regxmm));
7418
7419 if (i.tm.operand_types[0].bitfield.instance == Accum
7420 && i.tm.operand_types[0].bitfield.xmmword)
7421 {
7422 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
7423 {
7424 /* Keep xmm0 for instructions with VEX prefix and 3
7425 sources. */
7426 i.tm.operand_types[0].bitfield.instance = InstanceNone;
7427 i.tm.operand_types[0].bitfield.class = RegSIMD;
7428 goto duplicate;
7429 }
7430 else
7431 {
7432 /* We remove the first xmm0 and keep the number of
7433 operands unchanged, which in fact duplicates the
7434 destination. */
7435 for (j = 1; j < i.operands; j++)
7436 {
7437 i.op[j - 1] = i.op[j];
7438 i.types[j - 1] = i.types[j];
7439 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
7440 i.flags[j - 1] = i.flags[j];
7441 }
7442 }
7443 }
7444 else if (i.tm.opcode_modifier.implicit1stxmm0)
7445 {
7446 gas_assert ((MAX_OPERANDS - 1) > dupl
7447 && (i.tm.opcode_modifier.vexsources
7448 == VEX3SOURCES));
7449
7450 /* Add the implicit xmm0 for instructions with VEX prefix
7451 and 3 sources. */
7452 for (j = i.operands; j > 0; j--)
7453 {
7454 i.op[j] = i.op[j - 1];
7455 i.types[j] = i.types[j - 1];
7456 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
7457 i.flags[j] = i.flags[j - 1];
7458 }
7459 i.op[0].regs
7460 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7461 i.types[0] = regxmm;
7462 i.tm.operand_types[0] = regxmm;
7463
7464 i.operands += 2;
7465 i.reg_operands += 2;
7466 i.tm.operands += 2;
7467
7468 dupl++;
7469 dest++;
7470 i.op[dupl] = i.op[dest];
7471 i.types[dupl] = i.types[dest];
7472 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
7473 i.flags[dupl] = i.flags[dest];
7474 }
7475 else
7476 {
7477 duplicate:
7478 i.operands++;
7479 i.reg_operands++;
7480 i.tm.operands++;
7481
7482 i.op[dupl] = i.op[dest];
7483 i.types[dupl] = i.types[dest];
7484 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
7485 i.flags[dupl] = i.flags[dest];
7486 }
7487
7488 if (i.tm.opcode_modifier.immext)
7489 process_immext ();
7490 }
7491 else if (i.tm.operand_types[0].bitfield.instance == Accum
7492 && i.tm.operand_types[0].bitfield.xmmword)
7493 {
7494 unsigned int j;
7495
7496 for (j = 1; j < i.operands; j++)
7497 {
7498 i.op[j - 1] = i.op[j];
7499 i.types[j - 1] = i.types[j];
7500
7501 /* We need to adjust fields in i.tm since they are used by
7502 build_modrm_byte. */
7503 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
7504
7505 i.flags[j - 1] = i.flags[j];
7506 }
7507
7508 i.operands--;
7509 i.reg_operands--;
7510 i.tm.operands--;
7511 }
7512 else if (i.tm.opcode_modifier.implicitquadgroup)
7513 {
7514 unsigned int regnum, first_reg_in_group, last_reg_in_group;
7515
7516 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
7517 gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD);
7518 regnum = register_number (i.op[1].regs);
7519 first_reg_in_group = regnum & ~3;
7520 last_reg_in_group = first_reg_in_group + 3;
7521 if (regnum != first_reg_in_group)
7522 as_warn (_("source register `%s%s' implicitly denotes"
7523 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
7524 register_prefix, i.op[1].regs->reg_name,
7525 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
7526 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
7527 i.tm.name);
7528 }
7529 else if (i.tm.opcode_modifier.regkludge)
7530 {
7531 /* The imul $imm, %reg instruction is converted into
7532 imul $imm, %reg, %reg, and the clr %reg instruction
7533 is converted into xor %reg, %reg. */
7534
7535 unsigned int first_reg_op;
7536
7537 if (operand_type_check (i.types[0], reg))
7538 first_reg_op = 0;
7539 else
7540 first_reg_op = 1;
7541 /* Pretend we saw the extra register operand. */
7542 gas_assert (i.reg_operands == 1
7543 && i.op[first_reg_op + 1].regs == 0);
7544 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
7545 i.types[first_reg_op + 1] = i.types[first_reg_op];
7546 i.operands++;
7547 i.reg_operands++;
7548 }
7549
7550 if (i.tm.opcode_modifier.modrm)
7551 {
7552 /* The opcode is completed (modulo i.tm.extension_opcode which
7553 must be put into the modrm byte). Now, we make the modrm and
7554 index base bytes based on all the info we've collected. */
7555
7556 default_seg = build_modrm_byte ();
7557 }
7558 else if (i.types[0].bitfield.class == SReg)
7559 {
7560 if (flag_code != CODE_64BIT
7561 ? i.tm.base_opcode == POP_SEG_SHORT
7562 && i.op[0].regs->reg_num == 1
7563 : (i.tm.base_opcode | 1) == POP_SEG386_SHORT
7564 && i.op[0].regs->reg_num < 4)
7565 {
7566 as_bad (_("you can't `%s %s%s'"),
7567 i.tm.name, register_prefix, i.op[0].regs->reg_name);
7568 return 0;
7569 }
7570 if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 )
7571 {
7572 i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT;
7573 i.tm.opcode_length = 2;
7574 }
7575 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
7576 }
7577 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
7578 {
7579 default_seg = &ds;
7580 }
7581 else if (i.tm.opcode_modifier.isstring)
7582 {
7583 /* For the string instructions that allow a segment override
7584 on one of their operands, the default segment is ds. */
7585 default_seg = &ds;
7586 }
7587 else if (i.short_form)
7588 {
7589 /* The register or float register operand is in operand
7590 0 or 1. */
7591 unsigned int op = i.tm.operand_types[0].bitfield.class != Reg;
7592
7593 /* Register goes in low 3 bits of opcode. */
7594 i.tm.base_opcode |= i.op[op].regs->reg_num;
7595 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7596 i.rex |= REX_B;
7597 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
7598 {
7599 /* Warn about some common errors, but press on regardless.
7600 The first case can be generated by gcc (<= 2.8.1). */
7601 if (i.operands == 2)
7602 {
7603 /* Reversed arguments on faddp, fsubp, etc. */
7604 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
7605 register_prefix, i.op[!intel_syntax].regs->reg_name,
7606 register_prefix, i.op[intel_syntax].regs->reg_name);
7607 }
7608 else
7609 {
7610 /* Extraneous `l' suffix on fp insn. */
7611 as_warn (_("translating to `%s %s%s'"), i.tm.name,
7612 register_prefix, i.op[0].regs->reg_name);
7613 }
7614 }
7615 }
7616
7617 if ((i.seg[0] || i.prefix[SEG_PREFIX])
7618 && i.tm.base_opcode == 0x8d /* lea */
7619 && !is_any_vex_encoding(&i.tm))
7620 {
7621 if (!quiet_warnings)
7622 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
7623 if (optimize)
7624 {
7625 i.seg[0] = NULL;
7626 i.prefix[SEG_PREFIX] = 0;
7627 }
7628 }
7629
7630 /* If a segment was explicitly specified, and the specified segment
7631 is neither the default nor the one already recorded from a prefix,
7632 use an opcode prefix to select it. If we never figured out what
7633 the default segment is, then default_seg will be zero at this
7634 point, and the specified segment prefix will always be used. */
7635 if (i.seg[0]
7636 && i.seg[0] != default_seg
7637 && i.seg[0]->seg_prefix != i.prefix[SEG_PREFIX])
7638 {
7639 if (!add_prefix (i.seg[0]->seg_prefix))
7640 return 0;
7641 }
7642 return 1;
7643}
7644
7645static const seg_entry *
7646build_modrm_byte (void)
7647{
7648 const seg_entry *default_seg = 0;
7649 unsigned int source, dest;
7650 int vex_3_sources;
7651
7652 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
7653 if (vex_3_sources)
7654 {
7655 unsigned int nds, reg_slot;
7656 expressionS *exp;
7657
7658 dest = i.operands - 1;
7659 nds = dest - 1;
7660
7661 /* There are 2 kinds of instructions:
7662 1. 5 operands: 4 register operands or 3 register operands
7663 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7664 VexW0 or VexW1. The destination must be either XMM, YMM or
7665 ZMM register.
7666 2. 4 operands: 4 register operands or 3 register operands
7667 plus 1 memory operand, with VexXDS. */
7668 gas_assert ((i.reg_operands == 4
7669 || (i.reg_operands == 3 && i.mem_operands == 1))
7670 && i.tm.opcode_modifier.vexvvvv == VEXXDS
7671 && i.tm.opcode_modifier.vexw
7672 && i.tm.operand_types[dest].bitfield.class == RegSIMD);
7673
7674 /* If VexW1 is set, the first non-immediate operand is the source and
7675 the second non-immediate one is encoded in the immediate operand. */
7676 if (i.tm.opcode_modifier.vexw == VEXW1)
7677 {
7678 source = i.imm_operands;
7679 reg_slot = i.imm_operands + 1;
7680 }
7681 else
7682 {
7683 source = i.imm_operands + 1;
7684 reg_slot = i.imm_operands;
7685 }
7686
7687 if (i.imm_operands == 0)
7688 {
7689 /* When there is no immediate operand, generate an 8bit
7690 immediate operand to encode the first operand. */
7691 exp = &im_expressions[i.imm_operands++];
7692 i.op[i.operands].imms = exp;
7693 i.types[i.operands] = imm8;
7694 i.operands++;
7695
7696 gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
7697 exp->X_op = O_constant;
7698 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
7699 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
7700 }
7701 else
7702 {
7703 gas_assert (i.imm_operands == 1);
7704 gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number));
7705 gas_assert (!i.tm.opcode_modifier.immext);
7706
7707 /* Turn on Imm8 again so that output_imm will generate it. */
7708 i.types[0].bitfield.imm8 = 1;
7709
7710 gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
7711 i.op[0].imms->X_add_number
7712 |= register_number (i.op[reg_slot].regs) << 4;
7713 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
7714 }
7715
7716 gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD);
7717 i.vex.register_specifier = i.op[nds].regs;
7718 }
7719 else
7720 source = dest = 0;
7721
7722 /* i.reg_operands MUST be the number of real register operands;
7723 implicit registers do not count. If there are 3 register
7724 operands, it must be a instruction with VexNDS. For a
7725 instruction with VexNDD, the destination register is encoded
7726 in VEX prefix. If there are 4 register operands, it must be
7727 a instruction with VEX prefix and 3 sources. */
7728 if (i.mem_operands == 0
7729 && ((i.reg_operands == 2
7730 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7731 || (i.reg_operands == 3
7732 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7733 || (i.reg_operands == 4 && vex_3_sources)))
7734 {
7735 switch (i.operands)
7736 {
7737 case 2:
7738 source = 0;
7739 break;
7740 case 3:
7741 /* When there are 3 operands, one of them may be immediate,
7742 which may be the first or the last operand. Otherwise,
7743 the first operand must be shift count register (cl) or it
7744 is an instruction with VexNDS. */
7745 gas_assert (i.imm_operands == 1
7746 || (i.imm_operands == 0
7747 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7748 || (i.types[0].bitfield.instance == RegC
7749 && i.types[0].bitfield.byte))));
7750 if (operand_type_check (i.types[0], imm)
7751 || (i.types[0].bitfield.instance == RegC
7752 && i.types[0].bitfield.byte))
7753 source = 1;
7754 else
7755 source = 0;
7756 break;
7757 case 4:
7758 /* When there are 4 operands, the first two must be 8bit
7759 immediate operands. The source operand will be the 3rd
7760 one.
7761
7762 For instructions with VexNDS, if the first operand
7763 an imm8, the source operand is the 2nd one. If the last
7764 operand is imm8, the source operand is the first one. */
7765 gas_assert ((i.imm_operands == 2
7766 && i.types[0].bitfield.imm8
7767 && i.types[1].bitfield.imm8)
7768 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7769 && i.imm_operands == 1
7770 && (i.types[0].bitfield.imm8
7771 || i.types[i.operands - 1].bitfield.imm8
7772 || i.rounding)));
7773 if (i.imm_operands == 2)
7774 source = 2;
7775 else
7776 {
7777 if (i.types[0].bitfield.imm8)
7778 source = 1;
7779 else
7780 source = 0;
7781 }
7782 break;
7783 case 5:
7784 if (is_evex_encoding (&i.tm))
7785 {
7786 /* For EVEX instructions, when there are 5 operands, the
7787 first one must be immediate operand. If the second one
7788 is immediate operand, the source operand is the 3th
7789 one. If the last one is immediate operand, the source
7790 operand is the 2nd one. */
7791 gas_assert (i.imm_operands == 2
7792 && i.tm.opcode_modifier.sae
7793 && operand_type_check (i.types[0], imm));
7794 if (operand_type_check (i.types[1], imm))
7795 source = 2;
7796 else if (operand_type_check (i.types[4], imm))
7797 source = 1;
7798 else
7799 abort ();
7800 }
7801 break;
7802 default:
7803 abort ();
7804 }
7805
7806 if (!vex_3_sources)
7807 {
7808 dest = source + 1;
7809
7810 /* RC/SAE operand could be between DEST and SRC. That happens
7811 when one operand is GPR and the other one is XMM/YMM/ZMM
7812 register. */
7813 if (i.rounding && i.rounding->operand == (int) dest)
7814 dest++;
7815
7816 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7817 {
7818 /* For instructions with VexNDS, the register-only source
7819 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7820 register. It is encoded in VEX prefix. */
7821
7822 i386_operand_type op;
7823 unsigned int vvvv;
7824
7825 /* Check register-only source operand when two source
7826 operands are swapped. */
7827 if (!i.tm.operand_types[source].bitfield.baseindex
7828 && i.tm.operand_types[dest].bitfield.baseindex)
7829 {
7830 vvvv = source;
7831 source = dest;
7832 }
7833 else
7834 vvvv = dest;
7835
7836 op = i.tm.operand_types[vvvv];
7837 if ((dest + 1) >= i.operands
7838 || ((op.bitfield.class != Reg
7839 || (!op.bitfield.dword && !op.bitfield.qword))
7840 && op.bitfield.class != RegSIMD
7841 && !operand_type_equal (&op, &regmask)))
7842 abort ();
7843 i.vex.register_specifier = i.op[vvvv].regs;
7844 dest++;
7845 }
7846 }
7847
7848 i.rm.mode = 3;
7849 /* One of the register operands will be encoded in the i.rm.reg
7850 field, the other in the combined i.rm.mode and i.rm.regmem
7851 fields. If no form of this instruction supports a memory
7852 destination operand, then we assume the source operand may
7853 sometimes be a memory operand and so we need to store the
7854 destination in the i.rm.reg field. */
7855 if (!i.tm.opcode_modifier.regmem
7856 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
7857 {
7858 i.rm.reg = i.op[dest].regs->reg_num;
7859 i.rm.regmem = i.op[source].regs->reg_num;
7860 if (i.op[dest].regs->reg_type.bitfield.class == RegMMX
7861 || i.op[source].regs->reg_type.bitfield.class == RegMMX)
7862 i.has_regmmx = TRUE;
7863 else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD
7864 || i.op[source].regs->reg_type.bitfield.class == RegSIMD)
7865 {
7866 if (i.types[dest].bitfield.zmmword
7867 || i.types[source].bitfield.zmmword)
7868 i.has_regzmm = TRUE;
7869 else if (i.types[dest].bitfield.ymmword
7870 || i.types[source].bitfield.ymmword)
7871 i.has_regymm = TRUE;
7872 else
7873 i.has_regxmm = TRUE;
7874 }
7875 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7876 i.rex |= REX_R;
7877 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7878 i.vrex |= REX_R;
7879 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7880 i.rex |= REX_B;
7881 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7882 i.vrex |= REX_B;
7883 }
7884 else
7885 {
7886 i.rm.reg = i.op[source].regs->reg_num;
7887 i.rm.regmem = i.op[dest].regs->reg_num;
7888 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7889 i.rex |= REX_B;
7890 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7891 i.vrex |= REX_B;
7892 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7893 i.rex |= REX_R;
7894 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7895 i.vrex |= REX_R;
7896 }
7897 if (flag_code != CODE_64BIT && (i.rex & REX_R))
7898 {
7899 if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR)
7900 abort ();
7901 i.rex &= ~REX_R;
7902 add_prefix (LOCK_PREFIX_OPCODE);
7903 }
7904 }
7905 else
7906 { /* If it's not 2 reg operands... */
7907 unsigned int mem;
7908
7909 if (i.mem_operands)
7910 {
7911 unsigned int fake_zero_displacement = 0;
7912 unsigned int op;
7913
7914 for (op = 0; op < i.operands; op++)
7915 if (i.flags[op] & Operand_Mem)
7916 break;
7917 gas_assert (op < i.operands);
7918
7919 if (i.tm.opcode_modifier.vecsib)
7920 {
7921 if (i.index_reg->reg_num == RegIZ)
7922 abort ();
7923
7924 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7925 if (!i.base_reg)
7926 {
7927 i.sib.base = NO_BASE_REGISTER;
7928 i.sib.scale = i.log2_scale_factor;
7929 i.types[op].bitfield.disp8 = 0;
7930 i.types[op].bitfield.disp16 = 0;
7931 i.types[op].bitfield.disp64 = 0;
7932 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7933 {
7934 /* Must be 32 bit */
7935 i.types[op].bitfield.disp32 = 1;
7936 i.types[op].bitfield.disp32s = 0;
7937 }
7938 else
7939 {
7940 i.types[op].bitfield.disp32 = 0;
7941 i.types[op].bitfield.disp32s = 1;
7942 }
7943 }
7944 i.sib.index = i.index_reg->reg_num;
7945 if ((i.index_reg->reg_flags & RegRex) != 0)
7946 i.rex |= REX_X;
7947 if ((i.index_reg->reg_flags & RegVRex) != 0)
7948 i.vrex |= REX_X;
7949 }
7950
7951 default_seg = &ds;
7952
7953 if (i.base_reg == 0)
7954 {
7955 i.rm.mode = 0;
7956 if (!i.disp_operands)
7957 fake_zero_displacement = 1;
7958 if (i.index_reg == 0)
7959 {
7960 i386_operand_type newdisp;
7961
7962 gas_assert (!i.tm.opcode_modifier.vecsib);
7963 /* Operand is just <disp> */
7964 if (flag_code == CODE_64BIT)
7965 {
7966 /* 64bit mode overwrites the 32bit absolute
7967 addressing by RIP relative addressing and
7968 absolute addressing is encoded by one of the
7969 redundant SIB forms. */
7970 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7971 i.sib.base = NO_BASE_REGISTER;
7972 i.sib.index = NO_INDEX_REGISTER;
7973 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7974 }
7975 else if ((flag_code == CODE_16BIT)
7976 ^ (i.prefix[ADDR_PREFIX] != 0))
7977 {
7978 i.rm.regmem = NO_BASE_REGISTER_16;
7979 newdisp = disp16;
7980 }
7981 else
7982 {
7983 i.rm.regmem = NO_BASE_REGISTER;
7984 newdisp = disp32;
7985 }
7986 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7987 i.types[op] = operand_type_or (i.types[op], newdisp);
7988 }
7989 else if (!i.tm.opcode_modifier.vecsib)
7990 {
7991 /* !i.base_reg && i.index_reg */
7992 if (i.index_reg->reg_num == RegIZ)
7993 i.sib.index = NO_INDEX_REGISTER;
7994 else
7995 i.sib.index = i.index_reg->reg_num;
7996 i.sib.base = NO_BASE_REGISTER;
7997 i.sib.scale = i.log2_scale_factor;
7998 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7999 i.types[op].bitfield.disp8 = 0;
8000 i.types[op].bitfield.disp16 = 0;
8001 i.types[op].bitfield.disp64 = 0;
8002 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
8003 {
8004 /* Must be 32 bit */
8005 i.types[op].bitfield.disp32 = 1;
8006 i.types[op].bitfield.disp32s = 0;
8007 }
8008 else
8009 {
8010 i.types[op].bitfield.disp32 = 0;
8011 i.types[op].bitfield.disp32s = 1;
8012 }
8013 if ((i.index_reg->reg_flags & RegRex) != 0)
8014 i.rex |= REX_X;
8015 }
8016 }
8017 /* RIP addressing for 64bit mode. */
8018 else if (i.base_reg->reg_num == RegIP)
8019 {
8020 gas_assert (!i.tm.opcode_modifier.vecsib);
8021 i.rm.regmem = NO_BASE_REGISTER;
8022 i.types[op].bitfield.disp8 = 0;
8023 i.types[op].bitfield.disp16 = 0;
8024 i.types[op].bitfield.disp32 = 0;
8025 i.types[op].bitfield.disp32s = 1;
8026 i.types[op].bitfield.disp64 = 0;
8027 i.flags[op] |= Operand_PCrel;
8028 if (! i.disp_operands)
8029 fake_zero_displacement = 1;
8030 }
8031 else if (i.base_reg->reg_type.bitfield.word)
8032 {
8033 gas_assert (!i.tm.opcode_modifier.vecsib);
8034 switch (i.base_reg->reg_num)
8035 {
8036 case 3: /* (%bx) */
8037 if (i.index_reg == 0)
8038 i.rm.regmem = 7;
8039 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8040 i.rm.regmem = i.index_reg->reg_num - 6;
8041 break;
8042 case 5: /* (%bp) */
8043 default_seg = &ss;
8044 if (i.index_reg == 0)
8045 {
8046 i.rm.regmem = 6;
8047 if (operand_type_check (i.types[op], disp) == 0)
8048 {
8049 /* fake (%bp) into 0(%bp) */
8050 i.types[op].bitfield.disp8 = 1;
8051 fake_zero_displacement = 1;
8052 }
8053 }
8054 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8055 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
8056 break;
8057 default: /* (%si) -> 4 or (%di) -> 5 */
8058 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
8059 }
8060 i.rm.mode = mode_from_disp_size (i.types[op]);
8061 }
8062 else /* i.base_reg and 32/64 bit mode */
8063 {
8064 if (flag_code == CODE_64BIT
8065 && operand_type_check (i.types[op], disp))
8066 {
8067 i.types[op].bitfield.disp16 = 0;
8068 i.types[op].bitfield.disp64 = 0;
8069 if (i.prefix[ADDR_PREFIX] == 0)
8070 {
8071 i.types[op].bitfield.disp32 = 0;
8072 i.types[op].bitfield.disp32s = 1;
8073 }
8074 else
8075 {
8076 i.types[op].bitfield.disp32 = 1;
8077 i.types[op].bitfield.disp32s = 0;
8078 }
8079 }
8080
8081 if (!i.tm.opcode_modifier.vecsib)
8082 i.rm.regmem = i.base_reg->reg_num;
8083 if ((i.base_reg->reg_flags & RegRex) != 0)
8084 i.rex |= REX_B;
8085 i.sib.base = i.base_reg->reg_num;
8086 /* x86-64 ignores REX prefix bit here to avoid decoder
8087 complications. */
8088 if (!(i.base_reg->reg_flags & RegRex)
8089 && (i.base_reg->reg_num == EBP_REG_NUM
8090 || i.base_reg->reg_num == ESP_REG_NUM))
8091 default_seg = &ss;
8092 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
8093 {
8094 fake_zero_displacement = 1;
8095 i.types[op].bitfield.disp8 = 1;
8096 }
8097 i.sib.scale = i.log2_scale_factor;
8098 if (i.index_reg == 0)
8099 {
8100 gas_assert (!i.tm.opcode_modifier.vecsib);
8101 /* <disp>(%esp) becomes two byte modrm with no index
8102 register. We've already stored the code for esp
8103 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8104 Any base register besides %esp will not use the
8105 extra modrm byte. */
8106 i.sib.index = NO_INDEX_REGISTER;
8107 }
8108 else if (!i.tm.opcode_modifier.vecsib)
8109 {
8110 if (i.index_reg->reg_num == RegIZ)
8111 i.sib.index = NO_INDEX_REGISTER;
8112 else
8113 i.sib.index = i.index_reg->reg_num;
8114 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
8115 if ((i.index_reg->reg_flags & RegRex) != 0)
8116 i.rex |= REX_X;
8117 }
8118
8119 if (i.disp_operands
8120 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
8121 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
8122 i.rm.mode = 0;
8123 else
8124 {
8125 if (!fake_zero_displacement
8126 && !i.disp_operands
8127 && i.disp_encoding)
8128 {
8129 fake_zero_displacement = 1;
8130 if (i.disp_encoding == disp_encoding_8bit)
8131 i.types[op].bitfield.disp8 = 1;
8132 else
8133 i.types[op].bitfield.disp32 = 1;
8134 }
8135 i.rm.mode = mode_from_disp_size (i.types[op]);
8136 }
8137 }
8138
8139 if (fake_zero_displacement)
8140 {
8141 /* Fakes a zero displacement assuming that i.types[op]
8142 holds the correct displacement size. */
8143 expressionS *exp;
8144
8145 gas_assert (i.op[op].disps == 0);
8146 exp = &disp_expressions[i.disp_operands++];
8147 i.op[op].disps = exp;
8148 exp->X_op = O_constant;
8149 exp->X_add_number = 0;
8150 exp->X_add_symbol = (symbolS *) 0;
8151 exp->X_op_symbol = (symbolS *) 0;
8152 }
8153
8154 mem = op;
8155 }
8156 else
8157 mem = ~0;
8158
8159 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
8160 {
8161 if (operand_type_check (i.types[0], imm))
8162 i.vex.register_specifier = NULL;
8163 else
8164 {
8165 /* VEX.vvvv encodes one of the sources when the first
8166 operand is not an immediate. */
8167 if (i.tm.opcode_modifier.vexw == VEXW0)
8168 i.vex.register_specifier = i.op[0].regs;
8169 else
8170 i.vex.register_specifier = i.op[1].regs;
8171 }
8172
8173 /* Destination is a XMM register encoded in the ModRM.reg
8174 and VEX.R bit. */
8175 i.rm.reg = i.op[2].regs->reg_num;
8176 if ((i.op[2].regs->reg_flags & RegRex) != 0)
8177 i.rex |= REX_R;
8178
8179 /* ModRM.rm and VEX.B encodes the other source. */
8180 if (!i.mem_operands)
8181 {
8182 i.rm.mode = 3;
8183
8184 if (i.tm.opcode_modifier.vexw == VEXW0)
8185 i.rm.regmem = i.op[1].regs->reg_num;
8186 else
8187 i.rm.regmem = i.op[0].regs->reg_num;
8188
8189 if ((i.op[1].regs->reg_flags & RegRex) != 0)
8190 i.rex |= REX_B;
8191 }
8192 }
8193 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
8194 {
8195 i.vex.register_specifier = i.op[2].regs;
8196 if (!i.mem_operands)
8197 {
8198 i.rm.mode = 3;
8199 i.rm.regmem = i.op[1].regs->reg_num;
8200 if ((i.op[1].regs->reg_flags & RegRex) != 0)
8201 i.rex |= REX_B;
8202 }
8203 }
8204 /* Fill in i.rm.reg or i.rm.regmem field with register operand
8205 (if any) based on i.tm.extension_opcode. Again, we must be
8206 careful to make sure that segment/control/debug/test/MMX
8207 registers are coded into the i.rm.reg field. */
8208 else if (i.reg_operands)
8209 {
8210 unsigned int op;
8211 unsigned int vex_reg = ~0;
8212
8213 for (op = 0; op < i.operands; op++)
8214 {
8215 if (i.types[op].bitfield.class == Reg
8216 || i.types[op].bitfield.class == RegBND
8217 || i.types[op].bitfield.class == RegMask
8218 || i.types[op].bitfield.class == SReg
8219 || i.types[op].bitfield.class == RegCR
8220 || i.types[op].bitfield.class == RegDR
8221 || i.types[op].bitfield.class == RegTR)
8222 break;
8223 if (i.types[op].bitfield.class == RegSIMD)
8224 {
8225 if (i.types[op].bitfield.zmmword)
8226 i.has_regzmm = TRUE;
8227 else if (i.types[op].bitfield.ymmword)
8228 i.has_regymm = TRUE;
8229 else
8230 i.has_regxmm = TRUE;
8231 break;
8232 }
8233 if (i.types[op].bitfield.class == RegMMX)
8234 {
8235 i.has_regmmx = TRUE;
8236 break;
8237 }
8238 }
8239
8240 if (vex_3_sources)
8241 op = dest;
8242 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
8243 {
8244 /* For instructions with VexNDS, the register-only
8245 source operand is encoded in VEX prefix. */
8246 gas_assert (mem != (unsigned int) ~0);
8247
8248 if (op > mem)
8249 {
8250 vex_reg = op++;
8251 gas_assert (op < i.operands);
8252 }
8253 else
8254 {
8255 /* Check register-only source operand when two source
8256 operands are swapped. */
8257 if (!i.tm.operand_types[op].bitfield.baseindex
8258 && i.tm.operand_types[op + 1].bitfield.baseindex)
8259 {
8260 vex_reg = op;
8261 op += 2;
8262 gas_assert (mem == (vex_reg + 1)
8263 && op < i.operands);
8264 }
8265 else
8266 {
8267 vex_reg = op + 1;
8268 gas_assert (vex_reg < i.operands);
8269 }
8270 }
8271 }
8272 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
8273 {
8274 /* For instructions with VexNDD, the register destination
8275 is encoded in VEX prefix. */
8276 if (i.mem_operands == 0)
8277 {
8278 /* There is no memory operand. */
8279 gas_assert ((op + 2) == i.operands);
8280 vex_reg = op + 1;
8281 }
8282 else
8283 {
8284 /* There are only 2 non-immediate operands. */
8285 gas_assert (op < i.imm_operands + 2
8286 && i.operands == i.imm_operands + 2);
8287 vex_reg = i.imm_operands + 1;
8288 }
8289 }
8290 else
8291 gas_assert (op < i.operands);
8292
8293 if (vex_reg != (unsigned int) ~0)
8294 {
8295 i386_operand_type *type = &i.tm.operand_types[vex_reg];
8296
8297 if ((type->bitfield.class != Reg
8298 || (!type->bitfield.dword && !type->bitfield.qword))
8299 && type->bitfield.class != RegSIMD
8300 && !operand_type_equal (type, &regmask))
8301 abort ();
8302
8303 i.vex.register_specifier = i.op[vex_reg].regs;
8304 }
8305
8306 /* Don't set OP operand twice. */
8307 if (vex_reg != op)
8308 {
8309 /* If there is an extension opcode to put here, the
8310 register number must be put into the regmem field. */
8311 if (i.tm.extension_opcode != None)
8312 {
8313 i.rm.regmem = i.op[op].regs->reg_num;
8314 if ((i.op[op].regs->reg_flags & RegRex) != 0)
8315 i.rex |= REX_B;
8316 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
8317 i.vrex |= REX_B;
8318 }
8319 else
8320 {
8321 i.rm.reg = i.op[op].regs->reg_num;
8322 if ((i.op[op].regs->reg_flags & RegRex) != 0)
8323 i.rex |= REX_R;
8324 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
8325 i.vrex |= REX_R;
8326 }
8327 }
8328
8329 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
8330 must set it to 3 to indicate this is a register operand
8331 in the regmem field. */
8332 if (!i.mem_operands)
8333 i.rm.mode = 3;
8334 }
8335
8336 /* Fill in i.rm.reg field with extension opcode (if any). */
8337 if (i.tm.extension_opcode != None)
8338 i.rm.reg = i.tm.extension_opcode;
8339 }
8340 return default_seg;
8341}
8342
8343static unsigned int
8344flip_code16 (unsigned int code16)
8345{
8346 gas_assert (i.tm.operands == 1);
8347
8348 return !(i.prefix[REX_PREFIX] & REX_W)
8349 && (code16 ? i.tm.operand_types[0].bitfield.disp32
8350 || i.tm.operand_types[0].bitfield.disp32s
8351 : i.tm.operand_types[0].bitfield.disp16)
8352 ? CODE16 : 0;
8353}
8354
8355static void
8356output_branch (void)
8357{
8358 char *p;
8359 int size;
8360 int code16;
8361 int prefix;
8362 relax_substateT subtype;
8363 symbolS *sym;
8364 offsetT off;
8365
8366 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
8367 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
8368
8369 prefix = 0;
8370 if (i.prefix[DATA_PREFIX] != 0)
8371 {
8372 prefix = 1;
8373 i.prefixes -= 1;
8374 code16 ^= flip_code16(code16);
8375 }
8376 /* Pentium4 branch hints. */
8377 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
8378 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
8379 {
8380 prefix++;
8381 i.prefixes--;
8382 }
8383 if (i.prefix[REX_PREFIX] != 0)
8384 {
8385 prefix++;
8386 i.prefixes--;
8387 }
8388
8389 /* BND prefixed jump. */
8390 if (i.prefix[BND_PREFIX] != 0)
8391 {
8392 prefix++;
8393 i.prefixes--;
8394 }
8395
8396 if (i.prefixes != 0)
8397 as_warn (_("skipping prefixes on `%s'"), i.tm.name);
8398
8399 /* It's always a symbol; End frag & setup for relax.
8400 Make sure there is enough room in this frag for the largest
8401 instruction we may generate in md_convert_frag. This is 2
8402 bytes for the opcode and room for the prefix and largest
8403 displacement. */
8404 frag_grow (prefix + 2 + 4);
8405 /* Prefix and 1 opcode byte go in fr_fix. */
8406 p = frag_more (prefix + 1);
8407 if (i.prefix[DATA_PREFIX] != 0)
8408 *p++ = DATA_PREFIX_OPCODE;
8409 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
8410 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
8411 *p++ = i.prefix[SEG_PREFIX];
8412 if (i.prefix[BND_PREFIX] != 0)
8413 *p++ = BND_PREFIX_OPCODE;
8414 if (i.prefix[REX_PREFIX] != 0)
8415 *p++ = i.prefix[REX_PREFIX];
8416 *p = i.tm.base_opcode;
8417
8418 if ((unsigned char) *p == JUMP_PC_RELATIVE)
8419 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
8420 else if (cpu_arch_flags.bitfield.cpui386)
8421 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
8422 else
8423 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
8424 subtype |= code16;
8425
8426 sym = i.op[0].disps->X_add_symbol;
8427 off = i.op[0].disps->X_add_number;
8428
8429 if (i.op[0].disps->X_op != O_constant
8430 && i.op[0].disps->X_op != O_symbol)
8431 {
8432 /* Handle complex expressions. */
8433 sym = make_expr_symbol (i.op[0].disps);
8434 off = 0;
8435 }
8436
8437 /* 1 possible extra opcode + 4 byte displacement go in var part.
8438 Pass reloc in fr_var. */
8439 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
8440}
8441
8442#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8443/* Return TRUE iff PLT32 relocation should be used for branching to
8444 symbol S. */
8445
8446static bfd_boolean
8447need_plt32_p (symbolS *s)
8448{
8449 /* PLT32 relocation is ELF only. */
8450 if (!IS_ELF)
8451 return FALSE;
8452
8453#ifdef TE_SOLARIS
8454 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
8455 krtld support it. */
8456 return FALSE;
8457#endif
8458
8459 /* Since there is no need to prepare for PLT branch on x86-64, we
8460 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
8461 be used as a marker for 32-bit PC-relative branches. */
8462 if (!object_64bit)
8463 return FALSE;
8464
8465 /* Weak or undefined symbol need PLT32 relocation. */
8466 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
8467 return TRUE;
8468
8469 /* Non-global symbol doesn't need PLT32 relocation. */
8470 if (! S_IS_EXTERNAL (s))
8471 return FALSE;
8472
8473 /* Other global symbols need PLT32 relocation. NB: Symbol with
8474 non-default visibilities are treated as normal global symbol
8475 so that PLT32 relocation can be used as a marker for 32-bit
8476 PC-relative branches. It is useful for linker relaxation. */
8477 return TRUE;
8478}
8479#endif
8480
8481static void
8482output_jump (void)
8483{
8484 char *p;
8485 int size;
8486 fixS *fixP;
8487 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
8488
8489 if (i.tm.opcode_modifier.jump == JUMP_BYTE)
8490 {
8491 /* This is a loop or jecxz type instruction. */
8492 size = 1;
8493 if (i.prefix[ADDR_PREFIX] != 0)
8494 {
8495 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
8496 i.prefixes -= 1;
8497 }
8498 /* Pentium4 branch hints. */
8499 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
8500 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
8501 {
8502 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
8503 i.prefixes--;
8504 }
8505 }
8506 else
8507 {
8508 int code16;
8509
8510 code16 = 0;
8511 if (flag_code == CODE_16BIT)
8512 code16 = CODE16;
8513
8514 if (i.prefix[DATA_PREFIX] != 0)
8515 {
8516 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
8517 i.prefixes -= 1;
8518 code16 ^= flip_code16(code16);
8519 }
8520
8521 size = 4;
8522 if (code16)
8523 size = 2;
8524 }
8525
8526 /* BND prefixed jump. */
8527 if (i.prefix[BND_PREFIX] != 0)
8528 {
8529 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
8530 i.prefixes -= 1;
8531 }
8532
8533 if (i.prefix[REX_PREFIX] != 0)
8534 {
8535 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
8536 i.prefixes -= 1;
8537 }
8538
8539 if (i.prefixes != 0)
8540 as_warn (_("skipping prefixes on `%s'"), i.tm.name);
8541
8542 p = frag_more (i.tm.opcode_length + size);
8543 switch (i.tm.opcode_length)
8544 {
8545 case 2:
8546 *p++ = i.tm.base_opcode >> 8;
8547 /* Fall through. */
8548 case 1:
8549 *p++ = i.tm.base_opcode;
8550 break;
8551 default:
8552 abort ();
8553 }
8554
8555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8556 if (size == 4
8557 && jump_reloc == NO_RELOC
8558 && need_plt32_p (i.op[0].disps->X_add_symbol))
8559 jump_reloc = BFD_RELOC_X86_64_PLT32;
8560#endif
8561
8562 jump_reloc = reloc (size, 1, 1, jump_reloc);
8563
8564 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8565 i.op[0].disps, 1, jump_reloc);
8566
8567 /* All jumps handled here are signed, but don't use a signed limit
8568 check for 32 and 16 bit jumps as we want to allow wrap around at
8569 4G and 64k respectively. */
8570 if (size == 1)
8571 fixP->fx_signed = 1;
8572}
8573
8574static void
8575output_interseg_jump (void)
8576{
8577 char *p;
8578 int size;
8579 int prefix;
8580 int code16;
8581
8582 code16 = 0;
8583 if (flag_code == CODE_16BIT)
8584 code16 = CODE16;
8585
8586 prefix = 0;
8587 if (i.prefix[DATA_PREFIX] != 0)
8588 {
8589 prefix = 1;
8590 i.prefixes -= 1;
8591 code16 ^= CODE16;
8592 }
8593
8594 gas_assert (!i.prefix[REX_PREFIX]);
8595
8596 size = 4;
8597 if (code16)
8598 size = 2;
8599
8600 if (i.prefixes != 0)
8601 as_warn (_("skipping prefixes on `%s'"), i.tm.name);
8602
8603 /* 1 opcode; 2 segment; offset */
8604 p = frag_more (prefix + 1 + 2 + size);
8605
8606 if (i.prefix[DATA_PREFIX] != 0)
8607 *p++ = DATA_PREFIX_OPCODE;
8608
8609 if (i.prefix[REX_PREFIX] != 0)
8610 *p++ = i.prefix[REX_PREFIX];
8611
8612 *p++ = i.tm.base_opcode;
8613 if (i.op[1].imms->X_op == O_constant)
8614 {
8615 offsetT n = i.op[1].imms->X_add_number;
8616
8617 if (size == 2
8618 && !fits_in_unsigned_word (n)
8619 && !fits_in_signed_word (n))
8620 {
8621 as_bad (_("16-bit jump out of range"));
8622 return;
8623 }
8624 md_number_to_chars (p, n, size);
8625 }
8626 else
8627 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8628 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
8629 if (i.op[0].imms->X_op != O_constant)
8630 as_bad (_("can't handle non absolute segment in `%s'"),
8631 i.tm.name);
8632 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
8633}
8634
8635#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8636void
8637x86_cleanup (void)
8638{
8639 char *p;
8640 asection *seg = now_seg;
8641 subsegT subseg = now_subseg;
8642 asection *sec;
8643 unsigned int alignment, align_size_1;
8644 unsigned int isa_1_descsz, feature_2_descsz, descsz;
8645 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
8646 unsigned int padding;
8647
8648 if (!IS_ELF || !x86_used_note)
8649 return;
8650
8651 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
8652
8653 /* The .note.gnu.property section layout:
8654
8655 Field Length Contents
8656 ---- ---- ----
8657 n_namsz 4 4
8658 n_descsz 4 The note descriptor size
8659 n_type 4 NT_GNU_PROPERTY_TYPE_0
8660 n_name 4 "GNU"
8661 n_desc n_descsz The program property array
8662 .... .... ....
8663 */
8664
8665 /* Create the .note.gnu.property section. */
8666 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
8667 bfd_set_section_flags (sec,
8668 (SEC_ALLOC
8669 | SEC_LOAD
8670 | SEC_DATA
8671 | SEC_HAS_CONTENTS
8672 | SEC_READONLY));
8673
8674 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
8675 {
8676 align_size_1 = 7;
8677 alignment = 3;
8678 }
8679 else
8680 {
8681 align_size_1 = 3;
8682 alignment = 2;
8683 }
8684
8685 bfd_set_section_alignment (sec, alignment);
8686 elf_section_type (sec) = SHT_NOTE;
8687
8688 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8689 + 4-byte data */
8690 isa_1_descsz_raw = 4 + 4 + 4;
8691 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8692 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
8693
8694 feature_2_descsz_raw = isa_1_descsz;
8695 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8696 + 4-byte data */
8697 feature_2_descsz_raw += 4 + 4 + 4;
8698 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8699 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
8700 & ~align_size_1);
8701
8702 descsz = feature_2_descsz;
8703 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8704 p = frag_more (4 + 4 + 4 + 4 + descsz);
8705
8706 /* Write n_namsz. */
8707 md_number_to_chars (p, (valueT) 4, 4);
8708
8709 /* Write n_descsz. */
8710 md_number_to_chars (p + 4, (valueT) descsz, 4);
8711
8712 /* Write n_type. */
8713 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
8714
8715 /* Write n_name. */
8716 memcpy (p + 4 * 3, "GNU", 4);
8717
8718 /* Write 4-byte type. */
8719 md_number_to_chars (p + 4 * 4,
8720 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
8721
8722 /* Write 4-byte data size. */
8723 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
8724
8725 /* Write 4-byte data. */
8726 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
8727
8728 /* Zero out paddings. */
8729 padding = isa_1_descsz - isa_1_descsz_raw;
8730 if (padding)
8731 memset (p + 4 * 7, 0, padding);
8732
8733 /* Write 4-byte type. */
8734 md_number_to_chars (p + isa_1_descsz + 4 * 4,
8735 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
8736
8737 /* Write 4-byte data size. */
8738 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
8739
8740 /* Write 4-byte data. */
8741 md_number_to_chars (p + isa_1_descsz + 4 * 6,
8742 (valueT) x86_feature_2_used, 4);
8743
8744 /* Zero out paddings. */
8745 padding = feature_2_descsz - feature_2_descsz_raw;
8746 if (padding)
8747 memset (p + isa_1_descsz + 4 * 7, 0, padding);
8748
8749 /* We probably can't restore the current segment, for there likely
8750 isn't one yet... */
8751 if (seg && subseg)
8752 subseg_set (seg, subseg);
8753}
8754#endif
8755
8756static unsigned int
8757encoding_length (const fragS *start_frag, offsetT start_off,
8758 const char *frag_now_ptr)
8759{
8760 unsigned int len = 0;
8761
8762 if (start_frag != frag_now)
8763 {
8764 const fragS *fr = start_frag;
8765
8766 do {
8767 len += fr->fr_fix;
8768 fr = fr->fr_next;
8769 } while (fr && fr != frag_now);
8770 }
8771
8772 return len - start_off + (frag_now_ptr - frag_now->fr_literal);
8773}
8774
8775/* Return 1 for test, and, cmp, add, sub, inc and dec which may
8776 be macro-fused with conditional jumps.
8777 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
8778 or is one of the following format:
8779
8780 cmp m, imm
8781 add m, imm
8782 sub m, imm
8783 test m, imm
8784 and m, imm
8785 inc m
8786 dec m
8787
8788 it is unfusible. */
8789
8790static int
8791maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p)
8792{
8793 /* No RIP address. */
8794 if (i.base_reg && i.base_reg->reg_num == RegIP)
8795 return 0;
8796
8797 /* No VEX/EVEX encoding. */
8798 if (is_any_vex_encoding (&i.tm))
8799 return 0;
8800
8801 /* add, sub without add/sub m, imm. */
8802 if (i.tm.base_opcode <= 5
8803 || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d)
8804 || ((i.tm.base_opcode | 3) == 0x83
8805 && (i.tm.extension_opcode == 0x5
8806 || i.tm.extension_opcode == 0x0)))
8807 {
8808 *mf_cmp_p = mf_cmp_alu_cmp;
8809 return !(i.mem_operands && i.imm_operands);
8810 }
8811
8812 /* and without and m, imm. */
8813 if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25)
8814 || ((i.tm.base_opcode | 3) == 0x83
8815 && i.tm.extension_opcode == 0x4))
8816 {
8817 *mf_cmp_p = mf_cmp_test_and;
8818 return !(i.mem_operands && i.imm_operands);
8819 }
8820
8821 /* test without test m imm. */
8822 if ((i.tm.base_opcode | 1) == 0x85
8823 || (i.tm.base_opcode | 1) == 0xa9
8824 || ((i.tm.base_opcode | 1) == 0xf7
8825 && i.tm.extension_opcode == 0))
8826 {
8827 *mf_cmp_p = mf_cmp_test_and;
8828 return !(i.mem_operands && i.imm_operands);
8829 }
8830
8831 /* cmp without cmp m, imm. */
8832 if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d)
8833 || ((i.tm.base_opcode | 3) == 0x83
8834 && (i.tm.extension_opcode == 0x7)))
8835 {
8836 *mf_cmp_p = mf_cmp_alu_cmp;
8837 return !(i.mem_operands && i.imm_operands);
8838 }
8839
8840 /* inc, dec without inc/dec m. */
8841 if ((i.tm.cpu_flags.bitfield.cpuno64
8842 && (i.tm.base_opcode | 0xf) == 0x4f)
8843 || ((i.tm.base_opcode | 1) == 0xff
8844 && i.tm.extension_opcode <= 0x1))
8845 {
8846 *mf_cmp_p = mf_cmp_incdec;
8847 return !i.mem_operands;
8848 }
8849
8850 return 0;
8851}
8852
8853/* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
8854
8855static int
8856add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p)
8857{
8858 /* NB: Don't work with COND_JUMP86 without i386. */
8859 if (!align_branch_power
8860 || now_seg == absolute_section
8861 || !cpu_arch_flags.bitfield.cpui386
8862 || !(align_branch & align_branch_fused_bit))
8863 return 0;
8864
8865 if (maybe_fused_with_jcc_p (mf_cmp_p))
8866 {
8867 if (last_insn.kind == last_insn_other
8868 || last_insn.seg != now_seg)
8869 return 1;
8870 if (flag_debug)
8871 as_warn_where (last_insn.file, last_insn.line,
8872 _("`%s` skips -malign-branch-boundary on `%s`"),
8873 last_insn.name, i.tm.name);
8874 }
8875
8876 return 0;
8877}
8878
8879/* Return 1 if a BRANCH_PREFIX frag should be generated. */
8880
8881static int
8882add_branch_prefix_frag_p (void)
8883{
8884 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
8885 to PadLock instructions since they include prefixes in opcode. */
8886 if (!align_branch_power
8887 || !align_branch_prefix_size
8888 || now_seg == absolute_section
8889 || i.tm.cpu_flags.bitfield.cpupadlock
8890 || !cpu_arch_flags.bitfield.cpui386)
8891 return 0;
8892
8893 /* Don't add prefix if it is a prefix or there is no operand in case
8894 that segment prefix is special. */
8895 if (!i.operands || i.tm.opcode_modifier.isprefix)
8896 return 0;
8897
8898 if (last_insn.kind == last_insn_other
8899 || last_insn.seg != now_seg)
8900 return 1;
8901
8902 if (flag_debug)
8903 as_warn_where (last_insn.file, last_insn.line,
8904 _("`%s` skips -malign-branch-boundary on `%s`"),
8905 last_insn.name, i.tm.name);
8906
8907 return 0;
8908}
8909
8910/* Return 1 if a BRANCH_PADDING frag should be generated. */
8911
8912static int
8913add_branch_padding_frag_p (enum align_branch_kind *branch_p,
8914 enum mf_jcc_kind *mf_jcc_p)
8915{
8916 int add_padding;
8917
8918 /* NB: Don't work with COND_JUMP86 without i386. */
8919 if (!align_branch_power
8920 || now_seg == absolute_section
8921 || !cpu_arch_flags.bitfield.cpui386)
8922 return 0;
8923
8924 add_padding = 0;
8925
8926 /* Check for jcc and direct jmp. */
8927 if (i.tm.opcode_modifier.jump == JUMP)
8928 {
8929 if (i.tm.base_opcode == JUMP_PC_RELATIVE)
8930 {
8931 *branch_p = align_branch_jmp;
8932 add_padding = align_branch & align_branch_jmp_bit;
8933 }
8934 else
8935 {
8936 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
8937 igore the lowest bit. */
8938 *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1;
8939 *branch_p = align_branch_jcc;
8940 if ((align_branch & align_branch_jcc_bit))
8941 add_padding = 1;
8942 }
8943 }
8944 else if (is_any_vex_encoding (&i.tm))
8945 return 0;
8946 else if ((i.tm.base_opcode | 1) == 0xc3)
8947 {
8948 /* Near ret. */
8949 *branch_p = align_branch_ret;
8950 if ((align_branch & align_branch_ret_bit))
8951 add_padding = 1;
8952 }
8953 else
8954 {
8955 /* Check for indirect jmp, direct and indirect calls. */
8956 if (i.tm.base_opcode == 0xe8)
8957 {
8958 /* Direct call. */
8959 *branch_p = align_branch_call;
8960 if ((align_branch & align_branch_call_bit))
8961 add_padding = 1;
8962 }
8963 else if (i.tm.base_opcode == 0xff
8964 && (i.tm.extension_opcode == 2
8965 || i.tm.extension_opcode == 4))
8966 {
8967 /* Indirect call and jmp. */
8968 *branch_p = align_branch_indirect;
8969 if ((align_branch & align_branch_indirect_bit))
8970 add_padding = 1;
8971 }
8972
8973 if (add_padding
8974 && i.disp_operands
8975 && tls_get_addr
8976 && (i.op[0].disps->X_op == O_symbol
8977 || (i.op[0].disps->X_op == O_subtract
8978 && i.op[0].disps->X_op_symbol == GOT_symbol)))
8979 {
8980 symbolS *s = i.op[0].disps->X_add_symbol;
8981 /* No padding to call to global or undefined tls_get_addr. */
8982 if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s))
8983 && strcmp (S_GET_NAME (s), tls_get_addr) == 0)
8984 return 0;
8985 }
8986 }
8987
8988 if (add_padding
8989 && last_insn.kind != last_insn_other
8990 && last_insn.seg == now_seg)
8991 {
8992 if (flag_debug)
8993 as_warn_where (last_insn.file, last_insn.line,
8994 _("`%s` skips -malign-branch-boundary on `%s`"),
8995 last_insn.name, i.tm.name);
8996 return 0;
8997 }
8998
8999 return add_padding;
9000}
9001
9002static void
9003output_insn (void)
9004{
9005 fragS *insn_start_frag;
9006 offsetT insn_start_off;
9007 fragS *fragP = NULL;
9008 enum align_branch_kind branch = align_branch_none;
9009 /* The initializer is arbitrary just to avoid uninitialized error.
9010 it's actually either assigned in add_branch_padding_frag_p
9011 or never be used. */
9012 enum mf_jcc_kind mf_jcc = mf_jcc_jo;
9013
9014#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9015 if (IS_ELF && x86_used_note)
9016 {
9017 if (i.tm.cpu_flags.bitfield.cpucmov)
9018 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
9019 if (i.tm.cpu_flags.bitfield.cpusse)
9020 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE;
9021 if (i.tm.cpu_flags.bitfield.cpusse2)
9022 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2;
9023 if (i.tm.cpu_flags.bitfield.cpusse3)
9024 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3;
9025 if (i.tm.cpu_flags.bitfield.cpussse3)
9026 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3;
9027 if (i.tm.cpu_flags.bitfield.cpusse4_1)
9028 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1;
9029 if (i.tm.cpu_flags.bitfield.cpusse4_2)
9030 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2;
9031 if (i.tm.cpu_flags.bitfield.cpuavx)
9032 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX;
9033 if (i.tm.cpu_flags.bitfield.cpuavx2)
9034 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2;
9035 if (i.tm.cpu_flags.bitfield.cpufma)
9036 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA;
9037 if (i.tm.cpu_flags.bitfield.cpuavx512f)
9038 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F;
9039 if (i.tm.cpu_flags.bitfield.cpuavx512cd)
9040 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD;
9041 if (i.tm.cpu_flags.bitfield.cpuavx512er)
9042 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER;
9043 if (i.tm.cpu_flags.bitfield.cpuavx512pf)
9044 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF;
9045 if (i.tm.cpu_flags.bitfield.cpuavx512vl)
9046 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL;
9047 if (i.tm.cpu_flags.bitfield.cpuavx512dq)
9048 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ;
9049 if (i.tm.cpu_flags.bitfield.cpuavx512bw)
9050 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW;
9051 if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps)
9052 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS;
9053 if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)
9054 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW;
9055 if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg)
9056 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG;
9057 if (i.tm.cpu_flags.bitfield.cpuavx512ifma)
9058 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA;
9059 if (i.tm.cpu_flags.bitfield.cpuavx512vbmi)
9060 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI;
9061 if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2)
9062 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2;
9063 if (i.tm.cpu_flags.bitfield.cpuavx512_vnni)
9064 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI;
9065 if (i.tm.cpu_flags.bitfield.cpuavx512_bf16)
9066 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16;
9067
9068 if (i.tm.cpu_flags.bitfield.cpu8087
9069 || i.tm.cpu_flags.bitfield.cpu287
9070 || i.tm.cpu_flags.bitfield.cpu387
9071 || i.tm.cpu_flags.bitfield.cpu687
9072 || i.tm.cpu_flags.bitfield.cpufisttp)
9073 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
9074 if (i.has_regmmx
9075 || i.tm.base_opcode == 0xf77 /* emms */
9076 || i.tm.base_opcode == 0xf0e /* femms */
9077 || i.tm.base_opcode == 0xf2a /* cvtpi2ps */
9078 || i.tm.base_opcode == 0x660f2a /* cvtpi2pd */)
9079 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
9080 if (i.has_regxmm)
9081 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
9082 if (i.has_regymm)
9083 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
9084 if (i.has_regzmm)
9085 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
9086 if (i.tm.cpu_flags.bitfield.cpufxsr)
9087 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
9088 if (i.tm.cpu_flags.bitfield.cpuxsave)
9089 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
9090 if (i.tm.cpu_flags.bitfield.cpuxsaveopt)
9091 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
9092 if (i.tm.cpu_flags.bitfield.cpuxsavec)
9093 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
9094 }
9095#endif
9096
9097 /* Tie dwarf2 debug info to the address at the start of the insn.
9098 We can't do this after the insn has been output as the current
9099 frag may have been closed off. eg. by frag_var. */
9100 dwarf2_emit_insn (0);
9101
9102 insn_start_frag = frag_now;
9103 insn_start_off = frag_now_fix ();
9104
9105 if (add_branch_padding_frag_p (&branch, &mf_jcc))
9106 {
9107 char *p;
9108 /* Branch can be 8 bytes. Leave some room for prefixes. */
9109 unsigned int max_branch_padding_size = 14;
9110
9111 /* Align section to boundary. */
9112 record_alignment (now_seg, align_branch_power);
9113
9114 /* Make room for padding. */
9115 frag_grow (max_branch_padding_size);
9116
9117 /* Start of the padding. */
9118 p = frag_more (0);
9119
9120 fragP = frag_now;
9121
9122 frag_var (rs_machine_dependent, max_branch_padding_size, 0,
9123 ENCODE_RELAX_STATE (BRANCH_PADDING, 0),
9124 NULL, 0, p);
9125
9126 fragP->tc_frag_data.mf_type = mf_jcc;
9127 fragP->tc_frag_data.branch_type = branch;
9128 fragP->tc_frag_data.max_bytes = max_branch_padding_size;
9129 }
9130
9131 /* Output jumps. */
9132 if (i.tm.opcode_modifier.jump == JUMP)
9133 output_branch ();
9134 else if (i.tm.opcode_modifier.jump == JUMP_BYTE
9135 || i.tm.opcode_modifier.jump == JUMP_DWORD)
9136 output_jump ();
9137 else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT)
9138 output_interseg_jump ();
9139 else
9140 {
9141 /* Output normal instructions here. */
9142 char *p;
9143 unsigned char *q;
9144 unsigned int j;
9145 unsigned int prefix;
9146 enum mf_cmp_kind mf_cmp;
9147
9148 if (avoid_fence
9149 && (i.tm.base_opcode == 0xfaee8
9150 || i.tm.base_opcode == 0xfaef0
9151 || i.tm.base_opcode == 0xfaef8))
9152 {
9153 /* Encode lfence, mfence, and sfence as
9154 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9155 offsetT val = 0x240483f0ULL;
9156 p = frag_more (5);
9157 md_number_to_chars (p, val, 5);
9158 return;
9159 }
9160
9161 /* Some processors fail on LOCK prefix. This options makes
9162 assembler ignore LOCK prefix and serves as a workaround. */
9163 if (omit_lock_prefix)
9164 {
9165 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
9166 return;
9167 i.prefix[LOCK_PREFIX] = 0;
9168 }
9169
9170 if (branch)
9171 /* Skip if this is a branch. */
9172 ;
9173 else if (add_fused_jcc_padding_frag_p (&mf_cmp))
9174 {
9175 /* Make room for padding. */
9176 frag_grow (MAX_FUSED_JCC_PADDING_SIZE);
9177 p = frag_more (0);
9178
9179 fragP = frag_now;
9180
9181 frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0,
9182 ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0),
9183 NULL, 0, p);
9184
9185 fragP->tc_frag_data.mf_type = mf_cmp;
9186 fragP->tc_frag_data.branch_type = align_branch_fused;
9187 fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE;
9188 }
9189 else if (add_branch_prefix_frag_p ())
9190 {
9191 unsigned int max_prefix_size = align_branch_prefix_size;
9192
9193 /* Make room for padding. */
9194 frag_grow (max_prefix_size);
9195 p = frag_more (0);
9196
9197 fragP = frag_now;
9198
9199 frag_var (rs_machine_dependent, max_prefix_size, 0,
9200 ENCODE_RELAX_STATE (BRANCH_PREFIX, 0),
9201 NULL, 0, p);
9202
9203 fragP->tc_frag_data.max_bytes = max_prefix_size;
9204 }
9205
9206 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9207 don't need the explicit prefix. */
9208 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
9209 {
9210 switch (i.tm.opcode_length)
9211 {
9212 case 3:
9213 if (i.tm.base_opcode & 0xff000000)
9214 {
9215 prefix = (i.tm.base_opcode >> 24) & 0xff;
9216 if (!i.tm.cpu_flags.bitfield.cpupadlock
9217 || prefix != REPE_PREFIX_OPCODE
9218 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
9219 add_prefix (prefix);
9220 }
9221 break;
9222 case 2:
9223 if ((i.tm.base_opcode & 0xff0000) != 0)
9224 {
9225 prefix = (i.tm.base_opcode >> 16) & 0xff;
9226 add_prefix (prefix);
9227 }
9228 break;
9229 case 1:
9230 break;
9231 case 0:
9232 /* Check for pseudo prefixes. */
9233 as_bad_where (insn_start_frag->fr_file,
9234 insn_start_frag->fr_line,
9235 _("pseudo prefix without instruction"));
9236 return;
9237 default:
9238 abort ();
9239 }
9240
9241#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9242 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9243 R_X86_64_GOTTPOFF relocation so that linker can safely
9244 perform IE->LE optimization. A dummy REX_OPCODE prefix
9245 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9246 relocation for GDesc -> IE/LE optimization. */
9247 if (x86_elf_abi == X86_64_X32_ABI
9248 && i.operands == 2
9249 && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
9250 || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
9251 && i.prefix[REX_PREFIX] == 0)
9252 add_prefix (REX_OPCODE);
9253#endif
9254
9255 /* The prefix bytes. */
9256 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
9257 if (*q)
9258 FRAG_APPEND_1_CHAR (*q);
9259 }
9260 else
9261 {
9262 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
9263 if (*q)
9264 switch (j)
9265 {
9266 case REX_PREFIX:
9267 /* REX byte is encoded in VEX prefix. */
9268 break;
9269 case SEG_PREFIX:
9270 case ADDR_PREFIX:
9271 FRAG_APPEND_1_CHAR (*q);
9272 break;
9273 default:
9274 /* There should be no other prefixes for instructions
9275 with VEX prefix. */
9276 abort ();
9277 }
9278
9279 /* For EVEX instructions i.vrex should become 0 after
9280 build_evex_prefix. For VEX instructions upper 16 registers
9281 aren't available, so VREX should be 0. */
9282 if (i.vrex)
9283 abort ();
9284 /* Now the VEX prefix. */
9285 p = frag_more (i.vex.length);
9286 for (j = 0; j < i.vex.length; j++)
9287 p[j] = i.vex.bytes[j];
9288 }
9289
9290 /* Now the opcode; be careful about word order here! */
9291 if (i.tm.opcode_length == 1)
9292 {
9293 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
9294 }
9295 else
9296 {
9297 switch (i.tm.opcode_length)
9298 {
9299 case 4:
9300 p = frag_more (4);
9301 *p++ = (i.tm.base_opcode >> 24) & 0xff;
9302 *p++ = (i.tm.base_opcode >> 16) & 0xff;
9303 break;
9304 case 3:
9305 p = frag_more (3);
9306 *p++ = (i.tm.base_opcode >> 16) & 0xff;
9307 break;
9308 case 2:
9309 p = frag_more (2);
9310 break;
9311 default:
9312 abort ();
9313 break;
9314 }
9315
9316 /* Put out high byte first: can't use md_number_to_chars! */
9317 *p++ = (i.tm.base_opcode >> 8) & 0xff;
9318 *p = i.tm.base_opcode & 0xff;
9319 }
9320
9321 /* Now the modrm byte and sib byte (if present). */
9322 if (i.tm.opcode_modifier.modrm)
9323 {
9324 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
9325 | i.rm.reg << 3
9326 | i.rm.mode << 6));
9327 /* If i.rm.regmem == ESP (4)
9328 && i.rm.mode != (Register mode)
9329 && not 16 bit
9330 ==> need second modrm byte. */
9331 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
9332 && i.rm.mode != 3
9333 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
9334 FRAG_APPEND_1_CHAR ((i.sib.base << 0
9335 | i.sib.index << 3
9336 | i.sib.scale << 6));
9337 }
9338
9339 if (i.disp_operands)
9340 output_disp (insn_start_frag, insn_start_off);
9341
9342 if (i.imm_operands)
9343 output_imm (insn_start_frag, insn_start_off);
9344
9345 /*
9346 * frag_now_fix () returning plain abs_section_offset when we're in the
9347 * absolute section, and abs_section_offset not getting updated as data
9348 * gets added to the frag breaks the logic below.
9349 */
9350 if (now_seg != absolute_section)
9351 {
9352 j = encoding_length (insn_start_frag, insn_start_off, frag_more (0));
9353 if (j > 15)
9354 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
9355 j);
9356 else if (fragP)
9357 {
9358 /* NB: Don't add prefix with GOTPC relocation since
9359 output_disp() above depends on the fixed encoding
9360 length. Can't add prefix with TLS relocation since
9361 it breaks TLS linker optimization. */
9362 unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j;
9363 /* Prefix count on the current instruction. */
9364 unsigned int count = i.vex.length;
9365 unsigned int k;
9366 for (k = 0; k < ARRAY_SIZE (i.prefix); k++)
9367 /* REX byte is encoded in VEX/EVEX prefix. */
9368 if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length))
9369 count++;
9370
9371 /* Count prefixes for extended opcode maps. */
9372 if (!i.vex.length)
9373 switch (i.tm.opcode_length)
9374 {
9375 case 3:
9376 if (((i.tm.base_opcode >> 16) & 0xff) == 0xf)
9377 {
9378 count++;
9379 switch ((i.tm.base_opcode >> 8) & 0xff)
9380 {
9381 case 0x38:
9382 case 0x3a:
9383 count++;
9384 break;
9385 default:
9386 break;
9387 }
9388 }
9389 break;
9390 case 2:
9391 if (((i.tm.base_opcode >> 8) & 0xff) == 0xf)
9392 count++;
9393 break;
9394 case 1:
9395 break;
9396 default:
9397 abort ();
9398 }
9399
9400 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
9401 == BRANCH_PREFIX)
9402 {
9403 /* Set the maximum prefix size in BRANCH_PREFIX
9404 frag. */
9405 if (fragP->tc_frag_data.max_bytes > max)
9406 fragP->tc_frag_data.max_bytes = max;
9407 if (fragP->tc_frag_data.max_bytes > count)
9408 fragP->tc_frag_data.max_bytes -= count;
9409 else
9410 fragP->tc_frag_data.max_bytes = 0;
9411 }
9412 else
9413 {
9414 /* Remember the maximum prefix size in FUSED_JCC_PADDING
9415 frag. */
9416 unsigned int max_prefix_size;
9417 if (align_branch_prefix_size > max)
9418 max_prefix_size = max;
9419 else
9420 max_prefix_size = align_branch_prefix_size;
9421 if (max_prefix_size > count)
9422 fragP->tc_frag_data.max_prefix_length
9423 = max_prefix_size - count;
9424 }
9425
9426 /* Use existing segment prefix if possible. Use CS
9427 segment prefix in 64-bit mode. In 32-bit mode, use SS
9428 segment prefix with ESP/EBP base register and use DS
9429 segment prefix without ESP/EBP base register. */
9430 if (i.prefix[SEG_PREFIX])
9431 fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX];
9432 else if (flag_code == CODE_64BIT)
9433 fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE;
9434 else if (i.base_reg
9435 && (i.base_reg->reg_num == 4
9436 || i.base_reg->reg_num == 5))
9437 fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE;
9438 else
9439 fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE;
9440 }
9441 }
9442 }
9443
9444 /* NB: Don't work with COND_JUMP86 without i386. */
9445 if (align_branch_power
9446 && now_seg != absolute_section
9447 && cpu_arch_flags.bitfield.cpui386)
9448 {
9449 /* Terminate each frag so that we can add prefix and check for
9450 fused jcc. */
9451 frag_wane (frag_now);
9452 frag_new (0);
9453 }
9454
9455#ifdef DEBUG386
9456 if (flag_debug)
9457 {
9458 pi ("" /*line*/, &i);
9459 }
9460#endif /* DEBUG386 */
9461}
9462
9463/* Return the size of the displacement operand N. */
9464
9465static int
9466disp_size (unsigned int n)
9467{
9468 int size = 4;
9469
9470 if (i.types[n].bitfield.disp64)
9471 size = 8;
9472 else if (i.types[n].bitfield.disp8)
9473 size = 1;
9474 else if (i.types[n].bitfield.disp16)
9475 size = 2;
9476 return size;
9477}
9478
9479/* Return the size of the immediate operand N. */
9480
9481static int
9482imm_size (unsigned int n)
9483{
9484 int size = 4;
9485 if (i.types[n].bitfield.imm64)
9486 size = 8;
9487 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
9488 size = 1;
9489 else if (i.types[n].bitfield.imm16)
9490 size = 2;
9491 return size;
9492}
9493
9494static void
9495output_disp (fragS *insn_start_frag, offsetT insn_start_off)
9496{
9497 char *p;
9498 unsigned int n;
9499
9500 for (n = 0; n < i.operands; n++)
9501 {
9502 if (operand_type_check (i.types[n], disp))
9503 {
9504 if (i.op[n].disps->X_op == O_constant)
9505 {
9506 int size = disp_size (n);
9507 offsetT val = i.op[n].disps->X_add_number;
9508
9509 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
9510 size);
9511 p = frag_more (size);
9512 md_number_to_chars (p, val, size);
9513 }
9514 else
9515 {
9516 enum bfd_reloc_code_real reloc_type;
9517 int size = disp_size (n);
9518 int sign = i.types[n].bitfield.disp32s;
9519 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
9520 fixS *fixP;
9521
9522 /* We can't have 8 bit displacement here. */
9523 gas_assert (!i.types[n].bitfield.disp8);
9524
9525 /* The PC relative address is computed relative
9526 to the instruction boundary, so in case immediate
9527 fields follows, we need to adjust the value. */
9528 if (pcrel && i.imm_operands)
9529 {
9530 unsigned int n1;
9531 int sz = 0;
9532
9533 for (n1 = 0; n1 < i.operands; n1++)
9534 if (operand_type_check (i.types[n1], imm))
9535 {
9536 /* Only one immediate is allowed for PC
9537 relative address. */
9538 gas_assert (sz == 0);
9539 sz = imm_size (n1);
9540 i.op[n].disps->X_add_number -= sz;
9541 }
9542 /* We should find the immediate. */
9543 gas_assert (sz != 0);
9544 }
9545
9546 p = frag_more (size);
9547 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
9548 if (GOT_symbol
9549 && GOT_symbol == i.op[n].disps->X_add_symbol
9550 && (((reloc_type == BFD_RELOC_32
9551 || reloc_type == BFD_RELOC_X86_64_32S
9552 || (reloc_type == BFD_RELOC_64
9553 && object_64bit))
9554 && (i.op[n].disps->X_op == O_symbol
9555 || (i.op[n].disps->X_op == O_add
9556 && ((symbol_get_value_expression
9557 (i.op[n].disps->X_op_symbol)->X_op)
9558 == O_subtract))))
9559 || reloc_type == BFD_RELOC_32_PCREL))
9560 {
9561 if (!object_64bit)
9562 {
9563 reloc_type = BFD_RELOC_386_GOTPC;
9564 i.has_gotpc_tls_reloc = TRUE;
9565 i.op[n].imms->X_add_number +=
9566 encoding_length (insn_start_frag, insn_start_off, p);
9567 }
9568 else if (reloc_type == BFD_RELOC_64)
9569 reloc_type = BFD_RELOC_X86_64_GOTPC64;
9570 else
9571 /* Don't do the adjustment for x86-64, as there
9572 the pcrel addressing is relative to the _next_
9573 insn, and that is taken care of in other code. */
9574 reloc_type = BFD_RELOC_X86_64_GOTPC32;
9575 }
9576 else if (align_branch_power)
9577 {
9578 switch (reloc_type)
9579 {
9580 case BFD_RELOC_386_TLS_GD:
9581 case BFD_RELOC_386_TLS_LDM:
9582 case BFD_RELOC_386_TLS_IE:
9583 case BFD_RELOC_386_TLS_IE_32:
9584 case BFD_RELOC_386_TLS_GOTIE:
9585 case BFD_RELOC_386_TLS_GOTDESC:
9586 case BFD_RELOC_386_TLS_DESC_CALL:
9587 case BFD_RELOC_X86_64_TLSGD:
9588 case BFD_RELOC_X86_64_TLSLD:
9589 case BFD_RELOC_X86_64_GOTTPOFF:
9590 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9591 case BFD_RELOC_X86_64_TLSDESC_CALL:
9592 i.has_gotpc_tls_reloc = TRUE;
9593 default:
9594 break;
9595 }
9596 }
9597 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
9598 size, i.op[n].disps, pcrel,
9599 reloc_type);
9600 /* Check for "call/jmp *mem", "mov mem, %reg",
9601 "test %reg, mem" and "binop mem, %reg" where binop
9602 is one of adc, add, and, cmp, or, sbb, sub, xor
9603 instructions without data prefix. Always generate
9604 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
9605 if (i.prefix[DATA_PREFIX] == 0
9606 && (generate_relax_relocations
9607 || (!object_64bit
9608 && i.rm.mode == 0
9609 && i.rm.regmem == 5))
9610 && (i.rm.mode == 2
9611 || (i.rm.mode == 0 && i.rm.regmem == 5))
9612 && !is_any_vex_encoding(&i.tm)
9613 && ((i.operands == 1
9614 && i.tm.base_opcode == 0xff
9615 && (i.rm.reg == 2 || i.rm.reg == 4))
9616 || (i.operands == 2
9617 && (i.tm.base_opcode == 0x8b
9618 || i.tm.base_opcode == 0x85
9619 || (i.tm.base_opcode & ~0x38) == 0x03))))
9620 {
9621 if (object_64bit)
9622 {
9623 fixP->fx_tcbit = i.rex != 0;
9624 if (i.base_reg
9625 && (i.base_reg->reg_num == RegIP))
9626 fixP->fx_tcbit2 = 1;
9627 }
9628 else
9629 fixP->fx_tcbit2 = 1;
9630 }
9631 }
9632 }
9633 }
9634}
9635
9636static void
9637output_imm (fragS *insn_start_frag, offsetT insn_start_off)
9638{
9639 char *p;
9640 unsigned int n;
9641
9642 for (n = 0; n < i.operands; n++)
9643 {
9644 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
9645 if (i.rounding && (int) n == i.rounding->operand)
9646 continue;
9647
9648 if (operand_type_check (i.types[n], imm))
9649 {
9650 if (i.op[n].imms->X_op == O_constant)
9651 {
9652 int size = imm_size (n);
9653 offsetT val;
9654
9655 val = offset_in_range (i.op[n].imms->X_add_number,
9656 size);
9657 p = frag_more (size);
9658 md_number_to_chars (p, val, size);
9659 }
9660 else
9661 {
9662 /* Not absolute_section.
9663 Need a 32-bit fixup (don't support 8bit
9664 non-absolute imms). Try to support other
9665 sizes ... */
9666 enum bfd_reloc_code_real reloc_type;
9667 int size = imm_size (n);
9668 int sign;
9669
9670 if (i.types[n].bitfield.imm32s
9671 && (i.suffix == QWORD_MNEM_SUFFIX
9672 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
9673 sign = 1;
9674 else
9675 sign = 0;
9676
9677 p = frag_more (size);
9678 reloc_type = reloc (size, 0, sign, i.reloc[n]);
9679
9680 /* This is tough to explain. We end up with this one if we
9681 * have operands that look like
9682 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
9683 * obtain the absolute address of the GOT, and it is strongly
9684 * preferable from a performance point of view to avoid using
9685 * a runtime relocation for this. The actual sequence of
9686 * instructions often look something like:
9687 *
9688 * call .L66
9689 * .L66:
9690 * popl %ebx
9691 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
9692 *
9693 * The call and pop essentially return the absolute address
9694 * of the label .L66 and store it in %ebx. The linker itself
9695 * will ultimately change the first operand of the addl so
9696 * that %ebx points to the GOT, but to keep things simple, the
9697 * .o file must have this operand set so that it generates not
9698 * the absolute address of .L66, but the absolute address of
9699 * itself. This allows the linker itself simply treat a GOTPC
9700 * relocation as asking for a pcrel offset to the GOT to be
9701 * added in, and the addend of the relocation is stored in the
9702 * operand field for the instruction itself.
9703 *
9704 * Our job here is to fix the operand so that it would add
9705 * the correct offset so that %ebx would point to itself. The
9706 * thing that is tricky is that .-.L66 will point to the
9707 * beginning of the instruction, so we need to further modify
9708 * the operand so that it will point to itself. There are
9709 * other cases where you have something like:
9710 *
9711 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
9712 *
9713 * and here no correction would be required. Internally in
9714 * the assembler we treat operands of this form as not being
9715 * pcrel since the '.' is explicitly mentioned, and I wonder
9716 * whether it would simplify matters to do it this way. Who
9717 * knows. In earlier versions of the PIC patches, the
9718 * pcrel_adjust field was used to store the correction, but
9719 * since the expression is not pcrel, I felt it would be
9720 * confusing to do it this way. */
9721
9722 if ((reloc_type == BFD_RELOC_32
9723 || reloc_type == BFD_RELOC_X86_64_32S
9724 || reloc_type == BFD_RELOC_64)
9725 && GOT_symbol
9726 && GOT_symbol == i.op[n].imms->X_add_symbol
9727 && (i.op[n].imms->X_op == O_symbol
9728 || (i.op[n].imms->X_op == O_add
9729 && ((symbol_get_value_expression
9730 (i.op[n].imms->X_op_symbol)->X_op)
9731 == O_subtract))))
9732 {
9733 if (!object_64bit)
9734 reloc_type = BFD_RELOC_386_GOTPC;
9735 else if (size == 4)
9736 reloc_type = BFD_RELOC_X86_64_GOTPC32;
9737 else if (size == 8)
9738 reloc_type = BFD_RELOC_X86_64_GOTPC64;
9739 i.has_gotpc_tls_reloc = TRUE;
9740 i.op[n].imms->X_add_number +=
9741 encoding_length (insn_start_frag, insn_start_off, p);
9742 }
9743 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
9744 i.op[n].imms, 0, reloc_type);
9745 }
9746 }
9747 }
9748}
9749\f
9750/* x86_cons_fix_new is called via the expression parsing code when a
9751 reloc is needed. We use this hook to get the correct .got reloc. */
9752static int cons_sign = -1;
9753
9754void
9755x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
9756 expressionS *exp, bfd_reloc_code_real_type r)
9757{
9758 r = reloc (len, 0, cons_sign, r);
9759
9760#ifdef TE_PE
9761 if (exp->X_op == O_secrel)
9762 {
9763 exp->X_op = O_symbol;
9764 r = BFD_RELOC_32_SECREL;
9765 }
9766#endif
9767
9768 fix_new_exp (frag, off, len, exp, 0, r);
9769}
9770
9771/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
9772 purpose of the `.dc.a' internal pseudo-op. */
9773
9774int
9775x86_address_bytes (void)
9776{
9777 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
9778 return 4;
9779 return stdoutput->arch_info->bits_per_address / 8;
9780}
9781
9782#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
9783 || defined (LEX_AT)
9784# define lex_got(reloc, adjust, types) NULL
9785#else
9786/* Parse operands of the form
9787 <symbol>@GOTOFF+<nnn>
9788 and similar .plt or .got references.
9789
9790 If we find one, set up the correct relocation in RELOC and copy the
9791 input string, minus the `@GOTOFF' into a malloc'd buffer for
9792 parsing by the calling routine. Return this buffer, and if ADJUST
9793 is non-null set it to the length of the string we removed from the
9794 input line. Otherwise return NULL. */
9795static char *
9796lex_got (enum bfd_reloc_code_real *rel,
9797 int *adjust,
9798 i386_operand_type *types)
9799{
9800 /* Some of the relocations depend on the size of what field is to
9801 be relocated. But in our callers i386_immediate and i386_displacement
9802 we don't yet know the operand size (this will be set by insn
9803 matching). Hence we record the word32 relocation here,
9804 and adjust the reloc according to the real size in reloc(). */
9805 static const struct {
9806 const char *str;
9807 int len;
9808 const enum bfd_reloc_code_real rel[2];
9809 const i386_operand_type types64;
9810 } gotrel[] = {
9811#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9812 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
9813 BFD_RELOC_SIZE32 },
9814 OPERAND_TYPE_IMM32_64 },
9815#endif
9816 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
9817 BFD_RELOC_X86_64_PLTOFF64 },
9818 OPERAND_TYPE_IMM64 },
9819 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
9820 BFD_RELOC_X86_64_PLT32 },
9821 OPERAND_TYPE_IMM32_32S_DISP32 },
9822 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
9823 BFD_RELOC_X86_64_GOTPLT64 },
9824 OPERAND_TYPE_IMM64_DISP64 },
9825 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
9826 BFD_RELOC_X86_64_GOTOFF64 },
9827 OPERAND_TYPE_IMM64_DISP64 },
9828 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
9829 BFD_RELOC_X86_64_GOTPCREL },
9830 OPERAND_TYPE_IMM32_32S_DISP32 },
9831 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
9832 BFD_RELOC_X86_64_TLSGD },
9833 OPERAND_TYPE_IMM32_32S_DISP32 },
9834 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
9835 _dummy_first_bfd_reloc_code_real },
9836 OPERAND_TYPE_NONE },
9837 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
9838 BFD_RELOC_X86_64_TLSLD },
9839 OPERAND_TYPE_IMM32_32S_DISP32 },
9840 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
9841 BFD_RELOC_X86_64_GOTTPOFF },
9842 OPERAND_TYPE_IMM32_32S_DISP32 },
9843 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
9844 BFD_RELOC_X86_64_TPOFF32 },
9845 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
9846 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
9847 _dummy_first_bfd_reloc_code_real },
9848 OPERAND_TYPE_NONE },
9849 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
9850 BFD_RELOC_X86_64_DTPOFF32 },
9851 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
9852 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
9853 _dummy_first_bfd_reloc_code_real },
9854 OPERAND_TYPE_NONE },
9855 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
9856 _dummy_first_bfd_reloc_code_real },
9857 OPERAND_TYPE_NONE },
9858 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
9859 BFD_RELOC_X86_64_GOT32 },
9860 OPERAND_TYPE_IMM32_32S_64_DISP32 },
9861 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
9862 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
9863 OPERAND_TYPE_IMM32_32S_DISP32 },
9864 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
9865 BFD_RELOC_X86_64_TLSDESC_CALL },
9866 OPERAND_TYPE_IMM32_32S_DISP32 },
9867 };
9868 char *cp;
9869 unsigned int j;
9870
9871#if defined (OBJ_MAYBE_ELF)
9872 if (!IS_ELF)
9873 return NULL;
9874#endif
9875
9876 for (cp = input_line_pointer; *cp != '@'; cp++)
9877 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
9878 return NULL;
9879
9880 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
9881 {
9882 int len = gotrel[j].len;
9883 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
9884 {
9885 if (gotrel[j].rel[object_64bit] != 0)
9886 {
9887 int first, second;
9888 char *tmpbuf, *past_reloc;
9889
9890 *rel = gotrel[j].rel[object_64bit];
9891
9892 if (types)
9893 {
9894 if (flag_code != CODE_64BIT)
9895 {
9896 types->bitfield.imm32 = 1;
9897 types->bitfield.disp32 = 1;
9898 }
9899 else
9900 *types = gotrel[j].types64;
9901 }
9902
9903 if (j != 0 && GOT_symbol == NULL)
9904 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
9905
9906 /* The length of the first part of our input line. */
9907 first = cp - input_line_pointer;
9908
9909 /* The second part goes from after the reloc token until
9910 (and including) an end_of_line char or comma. */
9911 past_reloc = cp + 1 + len;
9912 cp = past_reloc;
9913 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
9914 ++cp;
9915 second = cp + 1 - past_reloc;
9916
9917 /* Allocate and copy string. The trailing NUL shouldn't
9918 be necessary, but be safe. */
9919 tmpbuf = XNEWVEC (char, first + second + 2);
9920 memcpy (tmpbuf, input_line_pointer, first);
9921 if (second != 0 && *past_reloc != ' ')
9922 /* Replace the relocation token with ' ', so that
9923 errors like foo@GOTOFF1 will be detected. */
9924 tmpbuf[first++] = ' ';
9925 else
9926 /* Increment length by 1 if the relocation token is
9927 removed. */
9928 len++;
9929 if (adjust)
9930 *adjust = len;
9931 memcpy (tmpbuf + first, past_reloc, second);
9932 tmpbuf[first + second] = '\0';
9933 return tmpbuf;
9934 }
9935
9936 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9937 gotrel[j].str, 1 << (5 + object_64bit));
9938 return NULL;
9939 }
9940 }
9941
9942 /* Might be a symbol version string. Don't as_bad here. */
9943 return NULL;
9944}
9945#endif
9946
9947#ifdef TE_PE
9948#ifdef lex_got
9949#undef lex_got
9950#endif
9951/* Parse operands of the form
9952 <symbol>@SECREL32+<nnn>
9953
9954 If we find one, set up the correct relocation in RELOC and copy the
9955 input string, minus the `@SECREL32' into a malloc'd buffer for
9956 parsing by the calling routine. Return this buffer, and if ADJUST
9957 is non-null set it to the length of the string we removed from the
9958 input line. Otherwise return NULL.
9959
9960 This function is copied from the ELF version above adjusted for PE targets. */
9961
9962static char *
9963lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
9964 int *adjust ATTRIBUTE_UNUSED,
9965 i386_operand_type *types)
9966{
9967 static const struct
9968 {
9969 const char *str;
9970 int len;
9971 const enum bfd_reloc_code_real rel[2];
9972 const i386_operand_type types64;
9973 }
9974 gotrel[] =
9975 {
9976 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
9977 BFD_RELOC_32_SECREL },
9978 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
9979 };
9980
9981 char *cp;
9982 unsigned j;
9983
9984 for (cp = input_line_pointer; *cp != '@'; cp++)
9985 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
9986 return NULL;
9987
9988 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
9989 {
9990 int len = gotrel[j].len;
9991
9992 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
9993 {
9994 if (gotrel[j].rel[object_64bit] != 0)
9995 {
9996 int first, second;
9997 char *tmpbuf, *past_reloc;
9998
9999 *rel = gotrel[j].rel[object_64bit];
10000 if (adjust)
10001 *adjust = len;
10002
10003 if (types)
10004 {
10005 if (flag_code != CODE_64BIT)
10006 {
10007 types->bitfield.imm32 = 1;
10008 types->bitfield.disp32 = 1;
10009 }
10010 else
10011 *types = gotrel[j].types64;
10012 }
10013
10014 /* The length of the first part of our input line. */
10015 first = cp - input_line_pointer;
10016
10017 /* The second part goes from after the reloc token until
10018 (and including) an end_of_line char or comma. */
10019 past_reloc = cp + 1 + len;
10020 cp = past_reloc;
10021 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
10022 ++cp;
10023 second = cp + 1 - past_reloc;
10024
10025 /* Allocate and copy string. The trailing NUL shouldn't
10026 be necessary, but be safe. */
10027 tmpbuf = XNEWVEC (char, first + second + 2);
10028 memcpy (tmpbuf, input_line_pointer, first);
10029 if (second != 0 && *past_reloc != ' ')
10030 /* Replace the relocation token with ' ', so that
10031 errors like foo@SECLREL321 will be detected. */
10032 tmpbuf[first++] = ' ';
10033 memcpy (tmpbuf + first, past_reloc, second);
10034 tmpbuf[first + second] = '\0';
10035 return tmpbuf;
10036 }
10037
10038 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10039 gotrel[j].str, 1 << (5 + object_64bit));
10040 return NULL;
10041 }
10042 }
10043
10044 /* Might be a symbol version string. Don't as_bad here. */
10045 return NULL;
10046}
10047
10048#endif /* TE_PE */
10049
10050bfd_reloc_code_real_type
10051x86_cons (expressionS *exp, int size)
10052{
10053 bfd_reloc_code_real_type got_reloc = NO_RELOC;
10054
10055 intel_syntax = -intel_syntax;
10056
10057 exp->X_md = 0;
10058 if (size == 4 || (object_64bit && size == 8))
10059 {
10060 /* Handle @GOTOFF and the like in an expression. */
10061 char *save;
10062 char *gotfree_input_line;
10063 int adjust = 0;
10064
10065 save = input_line_pointer;
10066 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
10067 if (gotfree_input_line)
10068 input_line_pointer = gotfree_input_line;
10069
10070 expression (exp);
10071
10072 if (gotfree_input_line)
10073 {
10074 /* expression () has merrily parsed up to the end of line,
10075 or a comma - in the wrong buffer. Transfer how far
10076 input_line_pointer has moved to the right buffer. */
10077 input_line_pointer = (save
10078 + (input_line_pointer - gotfree_input_line)
10079 + adjust);
10080 free (gotfree_input_line);
10081 if (exp->X_op == O_constant
10082 || exp->X_op == O_absent
10083 || exp->X_op == O_illegal
10084 || exp->X_op == O_register
10085 || exp->X_op == O_big)
10086 {
10087 char c = *input_line_pointer;
10088 *input_line_pointer = 0;
10089 as_bad (_("missing or invalid expression `%s'"), save);
10090 *input_line_pointer = c;
10091 }
10092 else if ((got_reloc == BFD_RELOC_386_PLT32
10093 || got_reloc == BFD_RELOC_X86_64_PLT32)
10094 && exp->X_op != O_symbol)
10095 {
10096 char c = *input_line_pointer;
10097 *input_line_pointer = 0;
10098 as_bad (_("invalid PLT expression `%s'"), save);
10099 *input_line_pointer = c;
10100 }
10101 }
10102 }
10103 else
10104 expression (exp);
10105
10106 intel_syntax = -intel_syntax;
10107
10108 if (intel_syntax)
10109 i386_intel_simplify (exp);
10110
10111 return got_reloc;
10112}
10113
10114static void
10115signed_cons (int size)
10116{
10117 if (flag_code == CODE_64BIT)
10118 cons_sign = 1;
10119 cons (size);
10120 cons_sign = -1;
10121}
10122
10123#ifdef TE_PE
10124static void
10125pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
10126{
10127 expressionS exp;
10128
10129 do
10130 {
10131 expression (&exp);
10132 if (exp.X_op == O_symbol)
10133 exp.X_op = O_secrel;
10134
10135 emit_expr (&exp, 4);
10136 }
10137 while (*input_line_pointer++ == ',');
10138
10139 input_line_pointer--;
10140 demand_empty_rest_of_line ();
10141}
10142#endif
10143
10144/* Handle Vector operations. */
10145
10146static char *
10147check_VecOperations (char *op_string, char *op_end)
10148{
10149 const reg_entry *mask;
10150 const char *saved;
10151 char *end_op;
10152
10153 while (*op_string
10154 && (op_end == NULL || op_string < op_end))
10155 {
10156 saved = op_string;
10157 if (*op_string == '{')
10158 {
10159 op_string++;
10160
10161 /* Check broadcasts. */
10162 if (strncmp (op_string, "1to", 3) == 0)
10163 {
10164 int bcst_type;
10165
10166 if (i.broadcast)
10167 goto duplicated_vec_op;
10168
10169 op_string += 3;
10170 if (*op_string == '8')
10171 bcst_type = 8;
10172 else if (*op_string == '4')
10173 bcst_type = 4;
10174 else if (*op_string == '2')
10175 bcst_type = 2;
10176 else if (*op_string == '1'
10177 && *(op_string+1) == '6')
10178 {
10179 bcst_type = 16;
10180 op_string++;
10181 }
10182 else
10183 {
10184 as_bad (_("Unsupported broadcast: `%s'"), saved);
10185 return NULL;
10186 }
10187 op_string++;
10188
10189 broadcast_op.type = bcst_type;
10190 broadcast_op.operand = this_operand;
10191 broadcast_op.bytes = 0;
10192 i.broadcast = &broadcast_op;
10193 }
10194 /* Check masking operation. */
10195 else if ((mask = parse_register (op_string, &end_op)) != NULL)
10196 {
10197 if (mask == &bad_reg)
10198 return NULL;
10199
10200 /* k0 can't be used for write mask. */
10201 if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num)
10202 {
10203 as_bad (_("`%s%s' can't be used for write mask"),
10204 register_prefix, mask->reg_name);
10205 return NULL;
10206 }
10207
10208 if (!i.mask)
10209 {
10210 mask_op.mask = mask;
10211 mask_op.zeroing = 0;
10212 mask_op.operand = this_operand;
10213 i.mask = &mask_op;
10214 }
10215 else
10216 {
10217 if (i.mask->mask)
10218 goto duplicated_vec_op;
10219
10220 i.mask->mask = mask;
10221
10222 /* Only "{z}" is allowed here. No need to check
10223 zeroing mask explicitly. */
10224 if (i.mask->operand != this_operand)
10225 {
10226 as_bad (_("invalid write mask `%s'"), saved);
10227 return NULL;
10228 }
10229 }
10230
10231 op_string = end_op;
10232 }
10233 /* Check zeroing-flag for masking operation. */
10234 else if (*op_string == 'z')
10235 {
10236 if (!i.mask)
10237 {
10238 mask_op.mask = NULL;
10239 mask_op.zeroing = 1;
10240 mask_op.operand = this_operand;
10241 i.mask = &mask_op;
10242 }
10243 else
10244 {
10245 if (i.mask->zeroing)
10246 {
10247 duplicated_vec_op:
10248 as_bad (_("duplicated `%s'"), saved);
10249 return NULL;
10250 }
10251
10252 i.mask->zeroing = 1;
10253
10254 /* Only "{%k}" is allowed here. No need to check mask
10255 register explicitly. */
10256 if (i.mask->operand != this_operand)
10257 {
10258 as_bad (_("invalid zeroing-masking `%s'"),
10259 saved);
10260 return NULL;
10261 }
10262 }
10263
10264 op_string++;
10265 }
10266 else
10267 goto unknown_vec_op;
10268
10269 if (*op_string != '}')
10270 {
10271 as_bad (_("missing `}' in `%s'"), saved);
10272 return NULL;
10273 }
10274 op_string++;
10275
10276 /* Strip whitespace since the addition of pseudo prefixes
10277 changed how the scrubber treats '{'. */
10278 if (is_space_char (*op_string))
10279 ++op_string;
10280
10281 continue;
10282 }
10283 unknown_vec_op:
10284 /* We don't know this one. */
10285 as_bad (_("unknown vector operation: `%s'"), saved);
10286 return NULL;
10287 }
10288
10289 if (i.mask && i.mask->zeroing && !i.mask->mask)
10290 {
10291 as_bad (_("zeroing-masking only allowed with write mask"));
10292 return NULL;
10293 }
10294
10295 return op_string;
10296}
10297
10298static int
10299i386_immediate (char *imm_start)
10300{
10301 char *save_input_line_pointer;
10302 char *gotfree_input_line;
10303 segT exp_seg = 0;
10304 expressionS *exp;
10305 i386_operand_type types;
10306
10307 operand_type_set (&types, ~0);
10308
10309 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
10310 {
10311 as_bad (_("at most %d immediate operands are allowed"),
10312 MAX_IMMEDIATE_OPERANDS);
10313 return 0;
10314 }
10315
10316 exp = &im_expressions[i.imm_operands++];
10317 i.op[this_operand].imms = exp;
10318
10319 if (is_space_char (*imm_start))
10320 ++imm_start;
10321
10322 save_input_line_pointer = input_line_pointer;
10323 input_line_pointer = imm_start;
10324
10325 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
10326 if (gotfree_input_line)
10327 input_line_pointer = gotfree_input_line;
10328
10329 exp_seg = expression (exp);
10330
10331 SKIP_WHITESPACE ();
10332
10333 /* Handle vector operations. */
10334 if (*input_line_pointer == '{')
10335 {
10336 input_line_pointer = check_VecOperations (input_line_pointer,
10337 NULL);
10338 if (input_line_pointer == NULL)
10339 return 0;
10340 }
10341
10342 if (*input_line_pointer)
10343 as_bad (_("junk `%s' after expression"), input_line_pointer);
10344
10345 input_line_pointer = save_input_line_pointer;
10346 if (gotfree_input_line)
10347 {
10348 free (gotfree_input_line);
10349
10350 if (exp->X_op == O_constant || exp->X_op == O_register)
10351 exp->X_op = O_illegal;
10352 }
10353
10354 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
10355}
10356
10357static int
10358i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
10359 i386_operand_type types, const char *imm_start)
10360{
10361 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
10362 {
10363 if (imm_start)
10364 as_bad (_("missing or invalid immediate expression `%s'"),
10365 imm_start);
10366 return 0;
10367 }
10368 else if (exp->X_op == O_constant)
10369 {
10370 /* Size it properly later. */
10371 i.types[this_operand].bitfield.imm64 = 1;
10372 /* If not 64bit, sign extend val. */
10373 if (flag_code != CODE_64BIT
10374 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
10375 exp->X_add_number
10376 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
10377 }
10378#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10379 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
10380 && exp_seg != absolute_section
10381 && exp_seg != text_section
10382 && exp_seg != data_section
10383 && exp_seg != bss_section
10384 && exp_seg != undefined_section
10385 && !bfd_is_com_section (exp_seg))
10386 {
10387 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
10388 return 0;
10389 }
10390#endif
10391 else if (!intel_syntax && exp_seg == reg_section)
10392 {
10393 if (imm_start)
10394 as_bad (_("illegal immediate register operand %s"), imm_start);
10395 return 0;
10396 }
10397 else
10398 {
10399 /* This is an address. The size of the address will be
10400 determined later, depending on destination register,
10401 suffix, or the default for the section. */
10402 i.types[this_operand].bitfield.imm8 = 1;
10403 i.types[this_operand].bitfield.imm16 = 1;
10404 i.types[this_operand].bitfield.imm32 = 1;
10405 i.types[this_operand].bitfield.imm32s = 1;
10406 i.types[this_operand].bitfield.imm64 = 1;
10407 i.types[this_operand] = operand_type_and (i.types[this_operand],
10408 types);
10409 }
10410
10411 return 1;
10412}
10413
10414static char *
10415i386_scale (char *scale)
10416{
10417 offsetT val;
10418 char *save = input_line_pointer;
10419
10420 input_line_pointer = scale;
10421 val = get_absolute_expression ();
10422
10423 switch (val)
10424 {
10425 case 1:
10426 i.log2_scale_factor = 0;
10427 break;
10428 case 2:
10429 i.log2_scale_factor = 1;
10430 break;
10431 case 4:
10432 i.log2_scale_factor = 2;
10433 break;
10434 case 8:
10435 i.log2_scale_factor = 3;
10436 break;
10437 default:
10438 {
10439 char sep = *input_line_pointer;
10440
10441 *input_line_pointer = '\0';
10442 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
10443 scale);
10444 *input_line_pointer = sep;
10445 input_line_pointer = save;
10446 return NULL;
10447 }
10448 }
10449 if (i.log2_scale_factor != 0 && i.index_reg == 0)
10450 {
10451 as_warn (_("scale factor of %d without an index register"),
10452 1 << i.log2_scale_factor);
10453 i.log2_scale_factor = 0;
10454 }
10455 scale = input_line_pointer;
10456 input_line_pointer = save;
10457 return scale;
10458}
10459
10460static int
10461i386_displacement (char *disp_start, char *disp_end)
10462{
10463 expressionS *exp;
10464 segT exp_seg = 0;
10465 char *save_input_line_pointer;
10466 char *gotfree_input_line;
10467 int override;
10468 i386_operand_type bigdisp, types = anydisp;
10469 int ret;
10470
10471 if (i.disp_operands == MAX_MEMORY_OPERANDS)
10472 {
10473 as_bad (_("at most %d displacement operands are allowed"),
10474 MAX_MEMORY_OPERANDS);
10475 return 0;
10476 }
10477
10478 operand_type_set (&bigdisp, 0);
10479 if (i.jumpabsolute
10480 || i.types[this_operand].bitfield.baseindex
10481 || (current_templates->start->opcode_modifier.jump != JUMP
10482 && current_templates->start->opcode_modifier.jump != JUMP_DWORD))
10483 {
10484 i386_addressing_mode ();
10485 override = (i.prefix[ADDR_PREFIX] != 0);
10486 if (flag_code == CODE_64BIT)
10487 {
10488 if (!override)
10489 {
10490 bigdisp.bitfield.disp32s = 1;
10491 bigdisp.bitfield.disp64 = 1;
10492 }
10493 else
10494 bigdisp.bitfield.disp32 = 1;
10495 }
10496 else if ((flag_code == CODE_16BIT) ^ override)
10497 bigdisp.bitfield.disp16 = 1;
10498 else
10499 bigdisp.bitfield.disp32 = 1;
10500 }
10501 else
10502 {
10503 /* For PC-relative branches, the width of the displacement may be
10504 dependent upon data size, but is never dependent upon address size.
10505 Also make sure to not unintentionally match against a non-PC-relative
10506 branch template. */
10507 static templates aux_templates;
10508 const insn_template *t = current_templates->start;
10509 bfd_boolean has_intel64 = FALSE;
10510
10511 aux_templates.start = t;
10512 while (++t < current_templates->end)
10513 {
10514 if (t->opcode_modifier.jump
10515 != current_templates->start->opcode_modifier.jump)
10516 break;
10517 if ((t->opcode_modifier.isa64 >= INTEL64))
10518 has_intel64 = TRUE;
10519 }
10520 if (t < current_templates->end)
10521 {
10522 aux_templates.end = t;
10523 current_templates = &aux_templates;
10524 }
10525
10526 override = (i.prefix[DATA_PREFIX] != 0);
10527 if (flag_code == CODE_64BIT)
10528 {
10529 if ((override || i.suffix == WORD_MNEM_SUFFIX)
10530 && (!intel64 || !has_intel64))
10531 bigdisp.bitfield.disp16 = 1;
10532 else
10533 bigdisp.bitfield.disp32s = 1;
10534 }
10535 else
10536 {
10537 if (!override)
10538 override = (i.suffix == (flag_code != CODE_16BIT
10539 ? WORD_MNEM_SUFFIX
10540 : LONG_MNEM_SUFFIX));
10541 bigdisp.bitfield.disp32 = 1;
10542 if ((flag_code == CODE_16BIT) ^ override)
10543 {
10544 bigdisp.bitfield.disp32 = 0;
10545 bigdisp.bitfield.disp16 = 1;
10546 }
10547 }
10548 }
10549 i.types[this_operand] = operand_type_or (i.types[this_operand],
10550 bigdisp);
10551
10552 exp = &disp_expressions[i.disp_operands];
10553 i.op[this_operand].disps = exp;
10554 i.disp_operands++;
10555 save_input_line_pointer = input_line_pointer;
10556 input_line_pointer = disp_start;
10557 END_STRING_AND_SAVE (disp_end);
10558
10559#ifndef GCC_ASM_O_HACK
10560#define GCC_ASM_O_HACK 0
10561#endif
10562#if GCC_ASM_O_HACK
10563 END_STRING_AND_SAVE (disp_end + 1);
10564 if (i.types[this_operand].bitfield.baseIndex
10565 && displacement_string_end[-1] == '+')
10566 {
10567 /* This hack is to avoid a warning when using the "o"
10568 constraint within gcc asm statements.
10569 For instance:
10570
10571 #define _set_tssldt_desc(n,addr,limit,type) \
10572 __asm__ __volatile__ ( \
10573 "movw %w2,%0\n\t" \
10574 "movw %w1,2+%0\n\t" \
10575 "rorl $16,%1\n\t" \
10576 "movb %b1,4+%0\n\t" \
10577 "movb %4,5+%0\n\t" \
10578 "movb $0,6+%0\n\t" \
10579 "movb %h1,7+%0\n\t" \
10580 "rorl $16,%1" \
10581 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
10582
10583 This works great except that the output assembler ends
10584 up looking a bit weird if it turns out that there is
10585 no offset. You end up producing code that looks like:
10586
10587 #APP
10588 movw $235,(%eax)
10589 movw %dx,2+(%eax)
10590 rorl $16,%edx
10591 movb %dl,4+(%eax)
10592 movb $137,5+(%eax)
10593 movb $0,6+(%eax)
10594 movb %dh,7+(%eax)
10595 rorl $16,%edx
10596 #NO_APP
10597
10598 So here we provide the missing zero. */
10599
10600 *displacement_string_end = '0';
10601 }
10602#endif
10603 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
10604 if (gotfree_input_line)
10605 input_line_pointer = gotfree_input_line;
10606
10607 exp_seg = expression (exp);
10608
10609 SKIP_WHITESPACE ();
10610 if (*input_line_pointer)
10611 as_bad (_("junk `%s' after expression"), input_line_pointer);
10612#if GCC_ASM_O_HACK
10613 RESTORE_END_STRING (disp_end + 1);
10614#endif
10615 input_line_pointer = save_input_line_pointer;
10616 if (gotfree_input_line)
10617 {
10618 free (gotfree_input_line);
10619
10620 if (exp->X_op == O_constant || exp->X_op == O_register)
10621 exp->X_op = O_illegal;
10622 }
10623
10624 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
10625
10626 RESTORE_END_STRING (disp_end);
10627
10628 return ret;
10629}
10630
10631static int
10632i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
10633 i386_operand_type types, const char *disp_start)
10634{
10635 i386_operand_type bigdisp;
10636 int ret = 1;
10637
10638 /* We do this to make sure that the section symbol is in
10639 the symbol table. We will ultimately change the relocation
10640 to be relative to the beginning of the section. */
10641 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
10642 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
10643 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
10644 {
10645 if (exp->X_op != O_symbol)
10646 goto inv_disp;
10647
10648 if (S_IS_LOCAL (exp->X_add_symbol)
10649 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
10650 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
10651 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
10652 exp->X_op = O_subtract;
10653 exp->X_op_symbol = GOT_symbol;
10654 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
10655 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
10656 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
10657 i.reloc[this_operand] = BFD_RELOC_64;
10658 else
10659 i.reloc[this_operand] = BFD_RELOC_32;
10660 }
10661
10662 else if (exp->X_op == O_absent
10663 || exp->X_op == O_illegal
10664 || exp->X_op == O_big)
10665 {
10666 inv_disp:
10667 as_bad (_("missing or invalid displacement expression `%s'"),
10668 disp_start);
10669 ret = 0;
10670 }
10671
10672 else if (flag_code == CODE_64BIT
10673 && !i.prefix[ADDR_PREFIX]
10674 && exp->X_op == O_constant)
10675 {
10676 /* Since displacement is signed extended to 64bit, don't allow
10677 disp32 and turn off disp32s if they are out of range. */
10678 i.types[this_operand].bitfield.disp32 = 0;
10679 if (!fits_in_signed_long (exp->X_add_number))
10680 {
10681 i.types[this_operand].bitfield.disp32s = 0;
10682 if (i.types[this_operand].bitfield.baseindex)
10683 {
10684 as_bad (_("0x%lx out range of signed 32bit displacement"),
10685 (long) exp->X_add_number);
10686 ret = 0;
10687 }
10688 }
10689 }
10690
10691#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10692 else if (exp->X_op != O_constant
10693 && OUTPUT_FLAVOR == bfd_target_aout_flavour
10694 && exp_seg != absolute_section
10695 && exp_seg != text_section
10696 && exp_seg != data_section
10697 && exp_seg != bss_section
10698 && exp_seg != undefined_section
10699 && !bfd_is_com_section (exp_seg))
10700 {
10701 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
10702 ret = 0;
10703 }
10704#endif
10705
10706 if (current_templates->start->opcode_modifier.jump == JUMP_BYTE
10707 /* Constants get taken care of by optimize_disp(). */
10708 && exp->X_op != O_constant)
10709 i.types[this_operand].bitfield.disp8 = 1;
10710
10711 /* Check if this is a displacement only operand. */
10712 bigdisp = i.types[this_operand];
10713 bigdisp.bitfield.disp8 = 0;
10714 bigdisp.bitfield.disp16 = 0;
10715 bigdisp.bitfield.disp32 = 0;
10716 bigdisp.bitfield.disp32s = 0;
10717 bigdisp.bitfield.disp64 = 0;
10718 if (operand_type_all_zero (&bigdisp))
10719 i.types[this_operand] = operand_type_and (i.types[this_operand],
10720 types);
10721
10722 return ret;
10723}
10724
10725/* Return the active addressing mode, taking address override and
10726 registers forming the address into consideration. Update the
10727 address override prefix if necessary. */
10728
10729static enum flag_code
10730i386_addressing_mode (void)
10731{
10732 enum flag_code addr_mode;
10733
10734 if (i.prefix[ADDR_PREFIX])
10735 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
10736 else if (flag_code == CODE_16BIT
10737 && current_templates->start->cpu_flags.bitfield.cpumpx
10738 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
10739 from md_assemble() by "is not a valid base/index expression"
10740 when there is a base and/or index. */
10741 && !i.types[this_operand].bitfield.baseindex)
10742 {
10743 /* MPX insn memory operands with neither base nor index must be forced
10744 to use 32-bit addressing in 16-bit mode. */
10745 addr_mode = CODE_32BIT;
10746 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
10747 ++i.prefixes;
10748 gas_assert (!i.types[this_operand].bitfield.disp16);
10749 gas_assert (!i.types[this_operand].bitfield.disp32);
10750 }
10751 else
10752 {
10753 addr_mode = flag_code;
10754
10755#if INFER_ADDR_PREFIX
10756 if (i.mem_operands == 0)
10757 {
10758 /* Infer address prefix from the first memory operand. */
10759 const reg_entry *addr_reg = i.base_reg;
10760
10761 if (addr_reg == NULL)
10762 addr_reg = i.index_reg;
10763
10764 if (addr_reg)
10765 {
10766 if (addr_reg->reg_type.bitfield.dword)
10767 addr_mode = CODE_32BIT;
10768 else if (flag_code != CODE_64BIT
10769 && addr_reg->reg_type.bitfield.word)
10770 addr_mode = CODE_16BIT;
10771
10772 if (addr_mode != flag_code)
10773 {
10774 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
10775 i.prefixes += 1;
10776 /* Change the size of any displacement too. At most one
10777 of Disp16 or Disp32 is set.
10778 FIXME. There doesn't seem to be any real need for
10779 separate Disp16 and Disp32 flags. The same goes for
10780 Imm16 and Imm32. Removing them would probably clean
10781 up the code quite a lot. */
10782 if (flag_code != CODE_64BIT
10783 && (i.types[this_operand].bitfield.disp16
10784 || i.types[this_operand].bitfield.disp32))
10785 i.types[this_operand]
10786 = operand_type_xor (i.types[this_operand], disp16_32);
10787 }
10788 }
10789 }
10790#endif
10791 }
10792
10793 return addr_mode;
10794}
10795
10796/* Make sure the memory operand we've been dealt is valid.
10797 Return 1 on success, 0 on a failure. */
10798
10799static int
10800i386_index_check (const char *operand_string)
10801{
10802 const char *kind = "base/index";
10803 enum flag_code addr_mode = i386_addressing_mode ();
10804
10805 if (current_templates->start->opcode_modifier.isstring
10806 && !current_templates->start->cpu_flags.bitfield.cpupadlock
10807 && (current_templates->end[-1].opcode_modifier.isstring
10808 || i.mem_operands))
10809 {
10810 /* Memory operands of string insns are special in that they only allow
10811 a single register (rDI, rSI, or rBX) as their memory address. */
10812 const reg_entry *expected_reg;
10813 static const char *di_si[][2] =
10814 {
10815 { "esi", "edi" },
10816 { "si", "di" },
10817 { "rsi", "rdi" }
10818 };
10819 static const char *bx[] = { "ebx", "bx", "rbx" };
10820
10821 kind = "string address";
10822
10823 if (current_templates->start->opcode_modifier.repprefixok)
10824 {
10825 int es_op = current_templates->end[-1].opcode_modifier.isstring
10826 - IS_STRING_ES_OP0;
10827 int op = 0;
10828
10829 if (!current_templates->end[-1].operand_types[0].bitfield.baseindex
10830 || ((!i.mem_operands != !intel_syntax)
10831 && current_templates->end[-1].operand_types[1]
10832 .bitfield.baseindex))
10833 op = 1;
10834 expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]);
10835 }
10836 else
10837 expected_reg = hash_find (reg_hash, bx[addr_mode]);
10838
10839 if (i.base_reg != expected_reg
10840 || i.index_reg
10841 || operand_type_check (i.types[this_operand], disp))
10842 {
10843 /* The second memory operand must have the same size as
10844 the first one. */
10845 if (i.mem_operands
10846 && i.base_reg
10847 && !((addr_mode == CODE_64BIT
10848 && i.base_reg->reg_type.bitfield.qword)
10849 || (addr_mode == CODE_32BIT
10850 ? i.base_reg->reg_type.bitfield.dword
10851 : i.base_reg->reg_type.bitfield.word)))
10852 goto bad_address;
10853
10854 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
10855 operand_string,
10856 intel_syntax ? '[' : '(',
10857 register_prefix,
10858 expected_reg->reg_name,
10859 intel_syntax ? ']' : ')');
10860 return 1;
10861 }
10862 else
10863 return 1;
10864
10865 bad_address:
10866 as_bad (_("`%s' is not a valid %s expression"),
10867 operand_string, kind);
10868 return 0;
10869 }
10870 else
10871 {
10872 if (addr_mode != CODE_16BIT)
10873 {
10874 /* 32-bit/64-bit checks. */
10875 if ((i.base_reg
10876 && ((addr_mode == CODE_64BIT
10877 ? !i.base_reg->reg_type.bitfield.qword
10878 : !i.base_reg->reg_type.bitfield.dword)
10879 || (i.index_reg && i.base_reg->reg_num == RegIP)
10880 || i.base_reg->reg_num == RegIZ))
10881 || (i.index_reg
10882 && !i.index_reg->reg_type.bitfield.xmmword
10883 && !i.index_reg->reg_type.bitfield.ymmword
10884 && !i.index_reg->reg_type.bitfield.zmmword
10885 && ((addr_mode == CODE_64BIT
10886 ? !i.index_reg->reg_type.bitfield.qword
10887 : !i.index_reg->reg_type.bitfield.dword)
10888 || !i.index_reg->reg_type.bitfield.baseindex)))
10889 goto bad_address;
10890
10891 /* bndmk, bndldx, and bndstx have special restrictions. */
10892 if (current_templates->start->base_opcode == 0xf30f1b
10893 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
10894 {
10895 /* They cannot use RIP-relative addressing. */
10896 if (i.base_reg && i.base_reg->reg_num == RegIP)
10897 {
10898 as_bad (_("`%s' cannot be used here"), operand_string);
10899 return 0;
10900 }
10901
10902 /* bndldx and bndstx ignore their scale factor. */
10903 if (current_templates->start->base_opcode != 0xf30f1b
10904 && i.log2_scale_factor)
10905 as_warn (_("register scaling is being ignored here"));
10906 }
10907 }
10908 else
10909 {
10910 /* 16-bit checks. */
10911 if ((i.base_reg
10912 && (!i.base_reg->reg_type.bitfield.word
10913 || !i.base_reg->reg_type.bitfield.baseindex))
10914 || (i.index_reg
10915 && (!i.index_reg->reg_type.bitfield.word
10916 || !i.index_reg->reg_type.bitfield.baseindex
10917 || !(i.base_reg
10918 && i.base_reg->reg_num < 6
10919 && i.index_reg->reg_num >= 6
10920 && i.log2_scale_factor == 0))))
10921 goto bad_address;
10922 }
10923 }
10924 return 1;
10925}
10926
10927/* Handle vector immediates. */
10928
10929static int
10930RC_SAE_immediate (const char *imm_start)
10931{
10932 unsigned int match_found, j;
10933 const char *pstr = imm_start;
10934 expressionS *exp;
10935
10936 if (*pstr != '{')
10937 return 0;
10938
10939 pstr++;
10940 match_found = 0;
10941 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
10942 {
10943 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
10944 {
10945 if (!i.rounding)
10946 {
10947 rc_op.type = RC_NamesTable[j].type;
10948 rc_op.operand = this_operand;
10949 i.rounding = &rc_op;
10950 }
10951 else
10952 {
10953 as_bad (_("duplicated `%s'"), imm_start);
10954 return 0;
10955 }
10956 pstr += RC_NamesTable[j].len;
10957 match_found = 1;
10958 break;
10959 }
10960 }
10961 if (!match_found)
10962 return 0;
10963
10964 if (*pstr++ != '}')
10965 {
10966 as_bad (_("Missing '}': '%s'"), imm_start);
10967 return 0;
10968 }
10969 /* RC/SAE immediate string should contain nothing more. */;
10970 if (*pstr != 0)
10971 {
10972 as_bad (_("Junk after '}': '%s'"), imm_start);
10973 return 0;
10974 }
10975
10976 exp = &im_expressions[i.imm_operands++];
10977 i.op[this_operand].imms = exp;
10978
10979 exp->X_op = O_constant;
10980 exp->X_add_number = 0;
10981 exp->X_add_symbol = (symbolS *) 0;
10982 exp->X_op_symbol = (symbolS *) 0;
10983
10984 i.types[this_operand].bitfield.imm8 = 1;
10985 return 1;
10986}
10987
10988/* Only string instructions can have a second memory operand, so
10989 reduce current_templates to just those if it contains any. */
10990static int
10991maybe_adjust_templates (void)
10992{
10993 const insn_template *t;
10994
10995 gas_assert (i.mem_operands == 1);
10996
10997 for (t = current_templates->start; t < current_templates->end; ++t)
10998 if (t->opcode_modifier.isstring)
10999 break;
11000
11001 if (t < current_templates->end)
11002 {
11003 static templates aux_templates;
11004 bfd_boolean recheck;
11005
11006 aux_templates.start = t;
11007 for (; t < current_templates->end; ++t)
11008 if (!t->opcode_modifier.isstring)
11009 break;
11010 aux_templates.end = t;
11011
11012 /* Determine whether to re-check the first memory operand. */
11013 recheck = (aux_templates.start != current_templates->start
11014 || t != current_templates->end);
11015
11016 current_templates = &aux_templates;
11017
11018 if (recheck)
11019 {
11020 i.mem_operands = 0;
11021 if (i.memop1_string != NULL
11022 && i386_index_check (i.memop1_string) == 0)
11023 return 0;
11024 i.mem_operands = 1;
11025 }
11026 }
11027
11028 return 1;
11029}
11030
11031/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
11032 on error. */
11033
11034static int
11035i386_att_operand (char *operand_string)
11036{
11037 const reg_entry *r;
11038 char *end_op;
11039 char *op_string = operand_string;
11040
11041 if (is_space_char (*op_string))
11042 ++op_string;
11043
11044 /* We check for an absolute prefix (differentiating,
11045 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
11046 if (*op_string == ABSOLUTE_PREFIX)
11047 {
11048 ++op_string;
11049 if (is_space_char (*op_string))
11050 ++op_string;
11051 i.jumpabsolute = TRUE;
11052 }
11053
11054 /* Check if operand is a register. */
11055 if ((r = parse_register (op_string, &end_op)) != NULL)
11056 {
11057 i386_operand_type temp;
11058
11059 if (r == &bad_reg)
11060 return 0;
11061
11062 /* Check for a segment override by searching for ':' after a
11063 segment register. */
11064 op_string = end_op;
11065 if (is_space_char (*op_string))
11066 ++op_string;
11067 if (*op_string == ':' && r->reg_type.bitfield.class == SReg)
11068 {
11069 switch (r->reg_num)
11070 {
11071 case 0:
11072 i.seg[i.mem_operands] = &es;
11073 break;
11074 case 1:
11075 i.seg[i.mem_operands] = &cs;
11076 break;
11077 case 2:
11078 i.seg[i.mem_operands] = &ss;
11079 break;
11080 case 3:
11081 i.seg[i.mem_operands] = &ds;
11082 break;
11083 case 4:
11084 i.seg[i.mem_operands] = &fs;
11085 break;
11086 case 5:
11087 i.seg[i.mem_operands] = &gs;
11088 break;
11089 }
11090
11091 /* Skip the ':' and whitespace. */
11092 ++op_string;
11093 if (is_space_char (*op_string))
11094 ++op_string;
11095
11096 if (!is_digit_char (*op_string)
11097 && !is_identifier_char (*op_string)
11098 && *op_string != '('
11099 && *op_string != ABSOLUTE_PREFIX)
11100 {
11101 as_bad (_("bad memory operand `%s'"), op_string);
11102 return 0;
11103 }
11104 /* Handle case of %es:*foo. */
11105 if (*op_string == ABSOLUTE_PREFIX)
11106 {
11107 ++op_string;
11108 if (is_space_char (*op_string))
11109 ++op_string;
11110 i.jumpabsolute = TRUE;
11111 }
11112 goto do_memory_reference;
11113 }
11114
11115 /* Handle vector operations. */
11116 if (*op_string == '{')
11117 {
11118 op_string = check_VecOperations (op_string, NULL);
11119 if (op_string == NULL)
11120 return 0;
11121 }
11122
11123 if (*op_string)
11124 {
11125 as_bad (_("junk `%s' after register"), op_string);
11126 return 0;
11127 }
11128 temp = r->reg_type;
11129 temp.bitfield.baseindex = 0;
11130 i.types[this_operand] = operand_type_or (i.types[this_operand],
11131 temp);
11132 i.types[this_operand].bitfield.unspecified = 0;
11133 i.op[this_operand].regs = r;
11134 i.reg_operands++;
11135 }
11136 else if (*op_string == REGISTER_PREFIX)
11137 {
11138 as_bad (_("bad register name `%s'"), op_string);
11139 return 0;
11140 }
11141 else if (*op_string == IMMEDIATE_PREFIX)
11142 {
11143 ++op_string;
11144 if (i.jumpabsolute)
11145 {
11146 as_bad (_("immediate operand illegal with absolute jump"));
11147 return 0;
11148 }
11149 if (!i386_immediate (op_string))
11150 return 0;
11151 }
11152 else if (RC_SAE_immediate (operand_string))
11153 {
11154 /* If it is a RC or SAE immediate, do nothing. */
11155 ;
11156 }
11157 else if (is_digit_char (*op_string)
11158 || is_identifier_char (*op_string)
11159 || *op_string == '"'
11160 || *op_string == '(')
11161 {
11162 /* This is a memory reference of some sort. */
11163 char *base_string;
11164
11165 /* Start and end of displacement string expression (if found). */
11166 char *displacement_string_start;
11167 char *displacement_string_end;
11168 char *vop_start;
11169
11170 do_memory_reference:
11171 if (i.mem_operands == 1 && !maybe_adjust_templates ())
11172 return 0;
11173 if ((i.mem_operands == 1
11174 && !current_templates->start->opcode_modifier.isstring)
11175 || i.mem_operands == 2)
11176 {
11177 as_bad (_("too many memory references for `%s'"),
11178 current_templates->start->name);
11179 return 0;
11180 }
11181
11182 /* Check for base index form. We detect the base index form by
11183 looking for an ')' at the end of the operand, searching
11184 for the '(' matching it, and finding a REGISTER_PREFIX or ','
11185 after the '('. */
11186 base_string = op_string + strlen (op_string);
11187
11188 /* Handle vector operations. */
11189 vop_start = strchr (op_string, '{');
11190 if (vop_start && vop_start < base_string)
11191 {
11192 if (check_VecOperations (vop_start, base_string) == NULL)
11193 return 0;
11194 base_string = vop_start;
11195 }
11196
11197 --base_string;
11198 if (is_space_char (*base_string))
11199 --base_string;
11200
11201 /* If we only have a displacement, set-up for it to be parsed later. */
11202 displacement_string_start = op_string;
11203 displacement_string_end = base_string + 1;
11204
11205 if (*base_string == ')')
11206 {
11207 char *temp_string;
11208 unsigned int parens_balanced = 1;
11209 /* We've already checked that the number of left & right ()'s are
11210 equal, so this loop will not be infinite. */
11211 do
11212 {
11213 base_string--;
11214 if (*base_string == ')')
11215 parens_balanced++;
11216 if (*base_string == '(')
11217 parens_balanced--;
11218 }
11219 while (parens_balanced);
11220
11221 temp_string = base_string;
11222
11223 /* Skip past '(' and whitespace. */
11224 ++base_string;
11225 if (is_space_char (*base_string))
11226 ++base_string;
11227
11228 if (*base_string == ','
11229 || ((i.base_reg = parse_register (base_string, &end_op))
11230 != NULL))
11231 {
11232 displacement_string_end = temp_string;
11233
11234 i.types[this_operand].bitfield.baseindex = 1;
11235
11236 if (i.base_reg)
11237 {
11238 if (i.base_reg == &bad_reg)
11239 return 0;
11240 base_string = end_op;
11241 if (is_space_char (*base_string))
11242 ++base_string;
11243 }
11244
11245 /* There may be an index reg or scale factor here. */
11246 if (*base_string == ',')
11247 {
11248 ++base_string;
11249 if (is_space_char (*base_string))
11250 ++base_string;
11251
11252 if ((i.index_reg = parse_register (base_string, &end_op))
11253 != NULL)
11254 {
11255 if (i.index_reg == &bad_reg)
11256 return 0;
11257 base_string = end_op;
11258 if (is_space_char (*base_string))
11259 ++base_string;
11260 if (*base_string == ',')
11261 {
11262 ++base_string;
11263 if (is_space_char (*base_string))
11264 ++base_string;
11265 }
11266 else if (*base_string != ')')
11267 {
11268 as_bad (_("expecting `,' or `)' "
11269 "after index register in `%s'"),
11270 operand_string);
11271 return 0;
11272 }
11273 }
11274 else if (*base_string == REGISTER_PREFIX)
11275 {
11276 end_op = strchr (base_string, ',');
11277 if (end_op)
11278 *end_op = '\0';
11279 as_bad (_("bad register name `%s'"), base_string);
11280 return 0;
11281 }
11282
11283 /* Check for scale factor. */
11284 if (*base_string != ')')
11285 {
11286 char *end_scale = i386_scale (base_string);
11287
11288 if (!end_scale)
11289 return 0;
11290
11291 base_string = end_scale;
11292 if (is_space_char (*base_string))
11293 ++base_string;
11294 if (*base_string != ')')
11295 {
11296 as_bad (_("expecting `)' "
11297 "after scale factor in `%s'"),
11298 operand_string);
11299 return 0;
11300 }
11301 }
11302 else if (!i.index_reg)
11303 {
11304 as_bad (_("expecting index register or scale factor "
11305 "after `,'; got '%c'"),
11306 *base_string);
11307 return 0;
11308 }
11309 }
11310 else if (*base_string != ')')
11311 {
11312 as_bad (_("expecting `,' or `)' "
11313 "after base register in `%s'"),
11314 operand_string);
11315 return 0;
11316 }
11317 }
11318 else if (*base_string == REGISTER_PREFIX)
11319 {
11320 end_op = strchr (base_string, ',');
11321 if (end_op)
11322 *end_op = '\0';
11323 as_bad (_("bad register name `%s'"), base_string);
11324 return 0;
11325 }
11326 }
11327
11328 /* If there's an expression beginning the operand, parse it,
11329 assuming displacement_string_start and
11330 displacement_string_end are meaningful. */
11331 if (displacement_string_start != displacement_string_end)
11332 {
11333 if (!i386_displacement (displacement_string_start,
11334 displacement_string_end))
11335 return 0;
11336 }
11337
11338 /* Special case for (%dx) while doing input/output op. */
11339 if (i.base_reg
11340 && i.base_reg->reg_type.bitfield.instance == RegD
11341 && i.base_reg->reg_type.bitfield.word
11342 && i.index_reg == 0
11343 && i.log2_scale_factor == 0
11344 && i.seg[i.mem_operands] == 0
11345 && !operand_type_check (i.types[this_operand], disp))
11346 {
11347 i.types[this_operand] = i.base_reg->reg_type;
11348 return 1;
11349 }
11350
11351 if (i386_index_check (operand_string) == 0)
11352 return 0;
11353 i.flags[this_operand] |= Operand_Mem;
11354 if (i.mem_operands == 0)
11355 i.memop1_string = xstrdup (operand_string);
11356 i.mem_operands++;
11357 }
11358 else
11359 {
11360 /* It's not a memory operand; argh! */
11361 as_bad (_("invalid char %s beginning operand %d `%s'"),
11362 output_invalid (*op_string),
11363 this_operand + 1,
11364 op_string);
11365 return 0;
11366 }
11367 return 1; /* Normal return. */
11368}
11369\f
11370/* Calculate the maximum variable size (i.e., excluding fr_fix)
11371 that an rs_machine_dependent frag may reach. */
11372
11373unsigned int
11374i386_frag_max_var (fragS *frag)
11375{
11376 /* The only relaxable frags are for jumps.
11377 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
11378 gas_assert (frag->fr_type == rs_machine_dependent);
11379 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
11380}
11381
11382#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11383static int
11384elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
11385{
11386 /* STT_GNU_IFUNC symbol must go through PLT. */
11387 if ((symbol_get_bfdsym (fr_symbol)->flags
11388 & BSF_GNU_INDIRECT_FUNCTION) != 0)
11389 return 0;
11390
11391 if (!S_IS_EXTERNAL (fr_symbol))
11392 /* Symbol may be weak or local. */
11393 return !S_IS_WEAK (fr_symbol);
11394
11395 /* Global symbols with non-default visibility can't be preempted. */
11396 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
11397 return 1;
11398
11399 if (fr_var != NO_RELOC)
11400 switch ((enum bfd_reloc_code_real) fr_var)
11401 {
11402 case BFD_RELOC_386_PLT32:
11403 case BFD_RELOC_X86_64_PLT32:
11404 /* Symbol with PLT relocation may be preempted. */
11405 return 0;
11406 default:
11407 abort ();
11408 }
11409
11410 /* Global symbols with default visibility in a shared library may be
11411 preempted by another definition. */
11412 return !shared;
11413}
11414#endif
11415
11416/* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
11417 Note also work for Skylake and Cascadelake.
11418---------------------------------------------------------------------
11419| JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
11420| ------ | ----------- | ------- | -------- |
11421| Jo | N | N | Y |
11422| Jno | N | N | Y |
11423| Jc/Jb | Y | N | Y |
11424| Jae/Jnb | Y | N | Y |
11425| Je/Jz | Y | Y | Y |
11426| Jne/Jnz | Y | Y | Y |
11427| Jna/Jbe | Y | N | Y |
11428| Ja/Jnbe | Y | N | Y |
11429| Js | N | N | Y |
11430| Jns | N | N | Y |
11431| Jp/Jpe | N | N | Y |
11432| Jnp/Jpo | N | N | Y |
11433| Jl/Jnge | Y | Y | Y |
11434| Jge/Jnl | Y | Y | Y |
11435| Jle/Jng | Y | Y | Y |
11436| Jg/Jnle | Y | Y | Y |
11437--------------------------------------------------------------------- */
11438static int
11439i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc)
11440{
11441 if (mf_cmp == mf_cmp_alu_cmp)
11442 return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna)
11443 || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle);
11444 if (mf_cmp == mf_cmp_incdec)
11445 return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl
11446 || mf_jcc == mf_jcc_jle);
11447 if (mf_cmp == mf_cmp_test_and)
11448 return 1;
11449 return 0;
11450}
11451
11452/* Return the next non-empty frag. */
11453
11454static fragS *
11455i386_next_non_empty_frag (fragS *fragP)
11456{
11457 /* There may be a frag with a ".fill 0" when there is no room in
11458 the current frag for frag_grow in output_insn. */
11459 for (fragP = fragP->fr_next;
11460 (fragP != NULL
11461 && fragP->fr_type == rs_fill
11462 && fragP->fr_fix == 0);
11463 fragP = fragP->fr_next)
11464 ;
11465 return fragP;
11466}
11467
11468/* Return the next jcc frag after BRANCH_PADDING. */
11469
11470static fragS *
11471i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP)
11472{
11473 fragS *branch_fragP;
11474 if (!pad_fragP)
11475 return NULL;
11476
11477 if (pad_fragP->fr_type == rs_machine_dependent
11478 && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype)
11479 == BRANCH_PADDING))
11480 {
11481 branch_fragP = i386_next_non_empty_frag (pad_fragP);
11482 if (branch_fragP->fr_type != rs_machine_dependent)
11483 return NULL;
11484 if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP
11485 && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type,
11486 pad_fragP->tc_frag_data.mf_type))
11487 return branch_fragP;
11488 }
11489
11490 return NULL;
11491}
11492
11493/* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
11494
11495static void
11496i386_classify_machine_dependent_frag (fragS *fragP)
11497{
11498 fragS *cmp_fragP;
11499 fragS *pad_fragP;
11500 fragS *branch_fragP;
11501 fragS *next_fragP;
11502 unsigned int max_prefix_length;
11503
11504 if (fragP->tc_frag_data.classified)
11505 return;
11506
11507 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
11508 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
11509 for (next_fragP = fragP;
11510 next_fragP != NULL;
11511 next_fragP = next_fragP->fr_next)
11512 {
11513 next_fragP->tc_frag_data.classified = 1;
11514 if (next_fragP->fr_type == rs_machine_dependent)
11515 switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype))
11516 {
11517 case BRANCH_PADDING:
11518 /* The BRANCH_PADDING frag must be followed by a branch
11519 frag. */
11520 branch_fragP = i386_next_non_empty_frag (next_fragP);
11521 next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
11522 break;
11523 case FUSED_JCC_PADDING:
11524 /* Check if this is a fused jcc:
11525 FUSED_JCC_PADDING
11526 CMP like instruction
11527 BRANCH_PADDING
11528 COND_JUMP
11529 */
11530 cmp_fragP = i386_next_non_empty_frag (next_fragP);
11531 pad_fragP = i386_next_non_empty_frag (cmp_fragP);
11532 branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP);
11533 if (branch_fragP)
11534 {
11535 /* The BRANCH_PADDING frag is merged with the
11536 FUSED_JCC_PADDING frag. */
11537 next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
11538 /* CMP like instruction size. */
11539 next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix;
11540 frag_wane (pad_fragP);
11541 /* Skip to branch_fragP. */
11542 next_fragP = branch_fragP;
11543 }
11544 else if (next_fragP->tc_frag_data.max_prefix_length)
11545 {
11546 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
11547 a fused jcc. */
11548 next_fragP->fr_subtype
11549 = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0);
11550 next_fragP->tc_frag_data.max_bytes
11551 = next_fragP->tc_frag_data.max_prefix_length;
11552 /* This will be updated in the BRANCH_PREFIX scan. */
11553 next_fragP->tc_frag_data.max_prefix_length = 0;
11554 }
11555 else
11556 frag_wane (next_fragP);
11557 break;
11558 }
11559 }
11560
11561 /* Stop if there is no BRANCH_PREFIX. */
11562 if (!align_branch_prefix_size)
11563 return;
11564
11565 /* Scan for BRANCH_PREFIX. */
11566 for (; fragP != NULL; fragP = fragP->fr_next)
11567 {
11568 if (fragP->fr_type != rs_machine_dependent
11569 || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
11570 != BRANCH_PREFIX))
11571 continue;
11572
11573 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
11574 COND_JUMP_PREFIX. */
11575 max_prefix_length = 0;
11576 for (next_fragP = fragP;
11577 next_fragP != NULL;
11578 next_fragP = next_fragP->fr_next)
11579 {
11580 if (next_fragP->fr_type == rs_fill)
11581 /* Skip rs_fill frags. */
11582 continue;
11583 else if (next_fragP->fr_type != rs_machine_dependent)
11584 /* Stop for all other frags. */
11585 break;
11586
11587 /* rs_machine_dependent frags. */
11588 if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11589 == BRANCH_PREFIX)
11590 {
11591 /* Count BRANCH_PREFIX frags. */
11592 if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE)
11593 {
11594 max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE;
11595 frag_wane (next_fragP);
11596 }
11597 else
11598 max_prefix_length
11599 += next_fragP->tc_frag_data.max_bytes;
11600 }
11601 else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11602 == BRANCH_PADDING)
11603 || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11604 == FUSED_JCC_PADDING))
11605 {
11606 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
11607 fragP->tc_frag_data.u.padding_fragP = next_fragP;
11608 break;
11609 }
11610 else
11611 /* Stop for other rs_machine_dependent frags. */
11612 break;
11613 }
11614
11615 fragP->tc_frag_data.max_prefix_length = max_prefix_length;
11616
11617 /* Skip to the next frag. */
11618 fragP = next_fragP;
11619 }
11620}
11621
11622/* Compute padding size for
11623
11624 FUSED_JCC_PADDING
11625 CMP like instruction
11626 BRANCH_PADDING
11627 COND_JUMP/UNCOND_JUMP
11628
11629 or
11630
11631 BRANCH_PADDING
11632 COND_JUMP/UNCOND_JUMP
11633 */
11634
11635static int
11636i386_branch_padding_size (fragS *fragP, offsetT address)
11637{
11638 unsigned int offset, size, padding_size;
11639 fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP;
11640
11641 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
11642 if (!address)
11643 address = fragP->fr_address;
11644 address += fragP->fr_fix;
11645
11646 /* CMP like instrunction size. */
11647 size = fragP->tc_frag_data.cmp_size;
11648
11649 /* The base size of the branch frag. */
11650 size += branch_fragP->fr_fix;
11651
11652 /* Add opcode and displacement bytes for the rs_machine_dependent
11653 branch frag. */
11654 if (branch_fragP->fr_type == rs_machine_dependent)
11655 size += md_relax_table[branch_fragP->fr_subtype].rlx_length;
11656
11657 /* Check if branch is within boundary and doesn't end at the last
11658 byte. */
11659 offset = address & ((1U << align_branch_power) - 1);
11660 if ((offset + size) >= (1U << align_branch_power))
11661 /* Padding needed to avoid crossing boundary. */
11662 padding_size = (1U << align_branch_power) - offset;
11663 else
11664 /* No padding needed. */
11665 padding_size = 0;
11666
11667 /* The return value may be saved in tc_frag_data.length which is
11668 unsigned byte. */
11669 if (!fits_in_unsigned_byte (padding_size))
11670 abort ();
11671
11672 return padding_size;
11673}
11674
11675/* i386_generic_table_relax_frag()
11676
11677 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
11678 grow/shrink padding to align branch frags. Hand others to
11679 relax_frag(). */
11680
11681long
11682i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch)
11683{
11684 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
11685 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
11686 {
11687 long padding_size = i386_branch_padding_size (fragP, 0);
11688 long grow = padding_size - fragP->tc_frag_data.length;
11689
11690 /* When the BRANCH_PREFIX frag is used, the computed address
11691 must match the actual address and there should be no padding. */
11692 if (fragP->tc_frag_data.padding_address
11693 && (fragP->tc_frag_data.padding_address != fragP->fr_address
11694 || padding_size))
11695 abort ();
11696
11697 /* Update the padding size. */
11698 if (grow)
11699 fragP->tc_frag_data.length = padding_size;
11700
11701 return grow;
11702 }
11703 else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
11704 {
11705 fragS *padding_fragP, *next_fragP;
11706 long padding_size, left_size, last_size;
11707
11708 padding_fragP = fragP->tc_frag_data.u.padding_fragP;
11709 if (!padding_fragP)
11710 /* Use the padding set by the leading BRANCH_PREFIX frag. */
11711 return (fragP->tc_frag_data.length
11712 - fragP->tc_frag_data.last_length);
11713
11714 /* Compute the relative address of the padding frag in the very
11715 first time where the BRANCH_PREFIX frag sizes are zero. */
11716 if (!fragP->tc_frag_data.padding_address)
11717 fragP->tc_frag_data.padding_address
11718 = padding_fragP->fr_address - (fragP->fr_address - stretch);
11719
11720 /* First update the last length from the previous interation. */
11721 left_size = fragP->tc_frag_data.prefix_length;
11722 for (next_fragP = fragP;
11723 next_fragP != padding_fragP;
11724 next_fragP = next_fragP->fr_next)
11725 if (next_fragP->fr_type == rs_machine_dependent
11726 && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11727 == BRANCH_PREFIX))
11728 {
11729 if (left_size)
11730 {
11731 int max = next_fragP->tc_frag_data.max_bytes;
11732 if (max)
11733 {
11734 int size;
11735 if (max > left_size)
11736 size = left_size;
11737 else
11738 size = max;
11739 left_size -= size;
11740 next_fragP->tc_frag_data.last_length = size;
11741 }
11742 }
11743 else
11744 next_fragP->tc_frag_data.last_length = 0;
11745 }
11746
11747 /* Check the padding size for the padding frag. */
11748 padding_size = i386_branch_padding_size
11749 (padding_fragP, (fragP->fr_address
11750 + fragP->tc_frag_data.padding_address));
11751
11752 last_size = fragP->tc_frag_data.prefix_length;
11753 /* Check if there is change from the last interation. */
11754 if (padding_size == last_size)
11755 {
11756 /* Update the expected address of the padding frag. */
11757 padding_fragP->tc_frag_data.padding_address
11758 = (fragP->fr_address + padding_size
11759 + fragP->tc_frag_data.padding_address);
11760 return 0;
11761 }
11762
11763 if (padding_size > fragP->tc_frag_data.max_prefix_length)
11764 {
11765 /* No padding if there is no sufficient room. Clear the
11766 expected address of the padding frag. */
11767 padding_fragP->tc_frag_data.padding_address = 0;
11768 padding_size = 0;
11769 }
11770 else
11771 /* Store the expected address of the padding frag. */
11772 padding_fragP->tc_frag_data.padding_address
11773 = (fragP->fr_address + padding_size
11774 + fragP->tc_frag_data.padding_address);
11775
11776 fragP->tc_frag_data.prefix_length = padding_size;
11777
11778 /* Update the length for the current interation. */
11779 left_size = padding_size;
11780 for (next_fragP = fragP;
11781 next_fragP != padding_fragP;
11782 next_fragP = next_fragP->fr_next)
11783 if (next_fragP->fr_type == rs_machine_dependent
11784 && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
11785 == BRANCH_PREFIX))
11786 {
11787 if (left_size)
11788 {
11789 int max = next_fragP->tc_frag_data.max_bytes;
11790 if (max)
11791 {
11792 int size;
11793 if (max > left_size)
11794 size = left_size;
11795 else
11796 size = max;
11797 left_size -= size;
11798 next_fragP->tc_frag_data.length = size;
11799 }
11800 }
11801 else
11802 next_fragP->tc_frag_data.length = 0;
11803 }
11804
11805 return (fragP->tc_frag_data.length
11806 - fragP->tc_frag_data.last_length);
11807 }
11808 return relax_frag (segment, fragP, stretch);
11809}
11810
11811/* md_estimate_size_before_relax()
11812
11813 Called just before relax() for rs_machine_dependent frags. The x86
11814 assembler uses these frags to handle variable size jump
11815 instructions.
11816
11817 Any symbol that is now undefined will not become defined.
11818 Return the correct fr_subtype in the frag.
11819 Return the initial "guess for variable size of frag" to caller.
11820 The guess is actually the growth beyond the fixed part. Whatever
11821 we do to grow the fixed or variable part contributes to our
11822 returned value. */
11823
11824int
11825md_estimate_size_before_relax (fragS *fragP, segT segment)
11826{
11827 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
11828 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX
11829 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
11830 {
11831 i386_classify_machine_dependent_frag (fragP);
11832 return fragP->tc_frag_data.length;
11833 }
11834
11835 /* We've already got fragP->fr_subtype right; all we have to do is
11836 check for un-relaxable symbols. On an ELF system, we can't relax
11837 an externally visible symbol, because it may be overridden by a
11838 shared library. */
11839 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
11840#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11841 || (IS_ELF
11842 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
11843 fragP->fr_var))
11844#endif
11845#if defined (OBJ_COFF) && defined (TE_PE)
11846 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
11847 && S_IS_WEAK (fragP->fr_symbol))
11848#endif
11849 )
11850 {
11851 /* Symbol is undefined in this segment, or we need to keep a
11852 reloc so that weak symbols can be overridden. */
11853 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
11854 enum bfd_reloc_code_real reloc_type;
11855 unsigned char *opcode;
11856 int old_fr_fix;
11857
11858 if (fragP->fr_var != NO_RELOC)
11859 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
11860 else if (size == 2)
11861 reloc_type = BFD_RELOC_16_PCREL;
11862#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11863 else if (need_plt32_p (fragP->fr_symbol))
11864 reloc_type = BFD_RELOC_X86_64_PLT32;
11865#endif
11866 else
11867 reloc_type = BFD_RELOC_32_PCREL;
11868
11869 old_fr_fix = fragP->fr_fix;
11870 opcode = (unsigned char *) fragP->fr_opcode;
11871
11872 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
11873 {
11874 case UNCOND_JUMP:
11875 /* Make jmp (0xeb) a (d)word displacement jump. */
11876 opcode[0] = 0xe9;
11877 fragP->fr_fix += size;
11878 fix_new (fragP, old_fr_fix, size,
11879 fragP->fr_symbol,
11880 fragP->fr_offset, 1,
11881 reloc_type);
11882 break;
11883
11884 case COND_JUMP86:
11885 if (size == 2
11886 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
11887 {
11888 /* Negate the condition, and branch past an
11889 unconditional jump. */
11890 opcode[0] ^= 1;
11891 opcode[1] = 3;
11892 /* Insert an unconditional jump. */
11893 opcode[2] = 0xe9;
11894 /* We added two extra opcode bytes, and have a two byte
11895 offset. */
11896 fragP->fr_fix += 2 + 2;
11897 fix_new (fragP, old_fr_fix + 2, 2,
11898 fragP->fr_symbol,
11899 fragP->fr_offset, 1,
11900 reloc_type);
11901 break;
11902 }
11903 /* Fall through. */
11904
11905 case COND_JUMP:
11906 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
11907 {
11908 fixS *fixP;
11909
11910 fragP->fr_fix += 1;
11911 fixP = fix_new (fragP, old_fr_fix, 1,
11912 fragP->fr_symbol,
11913 fragP->fr_offset, 1,
11914 BFD_RELOC_8_PCREL);
11915 fixP->fx_signed = 1;
11916 break;
11917 }
11918
11919 /* This changes the byte-displacement jump 0x7N
11920 to the (d)word-displacement jump 0x0f,0x8N. */
11921 opcode[1] = opcode[0] + 0x10;
11922 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
11923 /* We've added an opcode byte. */
11924 fragP->fr_fix += 1 + size;
11925 fix_new (fragP, old_fr_fix + 1, size,
11926 fragP->fr_symbol,
11927 fragP->fr_offset, 1,
11928 reloc_type);
11929 break;
11930
11931 default:
11932 BAD_CASE (fragP->fr_subtype);
11933 break;
11934 }
11935 frag_wane (fragP);
11936 return fragP->fr_fix - old_fr_fix;
11937 }
11938
11939 /* Guess size depending on current relax state. Initially the relax
11940 state will correspond to a short jump and we return 1, because
11941 the variable part of the frag (the branch offset) is one byte
11942 long. However, we can relax a section more than once and in that
11943 case we must either set fr_subtype back to the unrelaxed state,
11944 or return the value for the appropriate branch. */
11945 return md_relax_table[fragP->fr_subtype].rlx_length;
11946}
11947
11948/* Called after relax() is finished.
11949
11950 In: Address of frag.
11951 fr_type == rs_machine_dependent.
11952 fr_subtype is what the address relaxed to.
11953
11954 Out: Any fixSs and constants are set up.
11955 Caller will turn frag into a ".space 0". */
11956
11957void
11958md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
11959 fragS *fragP)
11960{
11961 unsigned char *opcode;
11962 unsigned char *where_to_put_displacement = NULL;
11963 offsetT target_address;
11964 offsetT opcode_address;
11965 unsigned int extension = 0;
11966 offsetT displacement_from_opcode_start;
11967
11968 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
11969 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING
11970 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
11971 {
11972 /* Generate nop padding. */
11973 unsigned int size = fragP->tc_frag_data.length;
11974 if (size)
11975 {
11976 if (size > fragP->tc_frag_data.max_bytes)
11977 abort ();
11978
11979 if (flag_debug)
11980 {
11981 const char *msg;
11982 const char *branch = "branch";
11983 const char *prefix = "";
11984 fragS *padding_fragP;
11985 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
11986 == BRANCH_PREFIX)
11987 {
11988 padding_fragP = fragP->tc_frag_data.u.padding_fragP;
11989 switch (fragP->tc_frag_data.default_prefix)
11990 {
11991 default:
11992 abort ();
11993 break;
11994 case CS_PREFIX_OPCODE:
11995 prefix = " cs";
11996 break;
11997 case DS_PREFIX_OPCODE:
11998 prefix = " ds";
11999 break;
12000 case ES_PREFIX_OPCODE:
12001 prefix = " es";
12002 break;
12003 case FS_PREFIX_OPCODE:
12004 prefix = " fs";
12005 break;
12006 case GS_PREFIX_OPCODE:
12007 prefix = " gs";
12008 break;
12009 case SS_PREFIX_OPCODE:
12010 prefix = " ss";
12011 break;
12012 }
12013 if (padding_fragP)
12014 msg = _("%s:%u: add %d%s at 0x%llx to align "
12015 "%s within %d-byte boundary\n");
12016 else
12017 msg = _("%s:%u: add additional %d%s at 0x%llx to "
12018 "align %s within %d-byte boundary\n");
12019 }
12020 else
12021 {
12022 padding_fragP = fragP;
12023 msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align "
12024 "%s within %d-byte boundary\n");
12025 }
12026
12027 if (padding_fragP)
12028 switch (padding_fragP->tc_frag_data.branch_type)
12029 {
12030 case align_branch_jcc:
12031 branch = "jcc";
12032 break;
12033 case align_branch_fused:
12034 branch = "fused jcc";
12035 break;
12036 case align_branch_jmp:
12037 branch = "jmp";
12038 break;
12039 case align_branch_call:
12040 branch = "call";
12041 break;
12042 case align_branch_indirect:
12043 branch = "indiret branch";
12044 break;
12045 case align_branch_ret:
12046 branch = "ret";
12047 break;
12048 default:
12049 break;
12050 }
12051
12052 fprintf (stdout, msg,
12053 fragP->fr_file, fragP->fr_line, size, prefix,
12054 (long long) fragP->fr_address, branch,
12055 1 << align_branch_power);
12056 }
12057 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
12058 memset (fragP->fr_opcode,
12059 fragP->tc_frag_data.default_prefix, size);
12060 else
12061 i386_generate_nops (fragP, (char *) fragP->fr_opcode,
12062 size, 0);
12063 fragP->fr_fix += size;
12064 }
12065 return;
12066 }
12067
12068 opcode = (unsigned char *) fragP->fr_opcode;
12069
12070 /* Address we want to reach in file space. */
12071 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
12072
12073 /* Address opcode resides at in file space. */
12074 opcode_address = fragP->fr_address + fragP->fr_fix;
12075
12076 /* Displacement from opcode start to fill into instruction. */
12077 displacement_from_opcode_start = target_address - opcode_address;
12078
12079 if ((fragP->fr_subtype & BIG) == 0)
12080 {
12081 /* Don't have to change opcode. */
12082 extension = 1; /* 1 opcode + 1 displacement */
12083 where_to_put_displacement = &opcode[1];
12084 }
12085 else
12086 {
12087 if (no_cond_jump_promotion
12088 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
12089 as_warn_where (fragP->fr_file, fragP->fr_line,
12090 _("long jump required"));
12091
12092 switch (fragP->fr_subtype)
12093 {
12094 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
12095 extension = 4; /* 1 opcode + 4 displacement */
12096 opcode[0] = 0xe9;
12097 where_to_put_displacement = &opcode[1];
12098 break;
12099
12100 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
12101 extension = 2; /* 1 opcode + 2 displacement */
12102 opcode[0] = 0xe9;
12103 where_to_put_displacement = &opcode[1];
12104 break;
12105
12106 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
12107 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
12108 extension = 5; /* 2 opcode + 4 displacement */
12109 opcode[1] = opcode[0] + 0x10;
12110 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
12111 where_to_put_displacement = &opcode[2];
12112 break;
12113
12114 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
12115 extension = 3; /* 2 opcode + 2 displacement */
12116 opcode[1] = opcode[0] + 0x10;
12117 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
12118 where_to_put_displacement = &opcode[2];
12119 break;
12120
12121 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
12122 extension = 4;
12123 opcode[0] ^= 1;
12124 opcode[1] = 3;
12125 opcode[2] = 0xe9;
12126 where_to_put_displacement = &opcode[3];
12127 break;
12128
12129 default:
12130 BAD_CASE (fragP->fr_subtype);
12131 break;
12132 }
12133 }
12134
12135 /* If size if less then four we are sure that the operand fits,
12136 but if it's 4, then it could be that the displacement is larger
12137 then -/+ 2GB. */
12138 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
12139 && object_64bit
12140 && ((addressT) (displacement_from_opcode_start - extension
12141 + ((addressT) 1 << 31))
12142 > (((addressT) 2 << 31) - 1)))
12143 {
12144 as_bad_where (fragP->fr_file, fragP->fr_line,
12145 _("jump target out of range"));
12146 /* Make us emit 0. */
12147 displacement_from_opcode_start = extension;
12148 }
12149 /* Now put displacement after opcode. */
12150 md_number_to_chars ((char *) where_to_put_displacement,
12151 (valueT) (displacement_from_opcode_start - extension),
12152 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
12153 fragP->fr_fix += extension;
12154}
12155\f
12156/* Apply a fixup (fixP) to segment data, once it has been determined
12157 by our caller that we have all the info we need to fix it up.
12158
12159 Parameter valP is the pointer to the value of the bits.
12160
12161 On the 386, immediates, displacements, and data pointers are all in
12162 the same (little-endian) format, so we don't need to care about which
12163 we are handling. */
12164
12165void
12166md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12167{
12168 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
12169 valueT value = *valP;
12170
12171#if !defined (TE_Mach)
12172 if (fixP->fx_pcrel)
12173 {
12174 switch (fixP->fx_r_type)
12175 {
12176 default:
12177 break;
12178
12179 case BFD_RELOC_64:
12180 fixP->fx_r_type = BFD_RELOC_64_PCREL;
12181 break;
12182 case BFD_RELOC_32:
12183 case BFD_RELOC_X86_64_32S:
12184 fixP->fx_r_type = BFD_RELOC_32_PCREL;
12185 break;
12186 case BFD_RELOC_16:
12187 fixP->fx_r_type = BFD_RELOC_16_PCREL;
12188 break;
12189 case BFD_RELOC_8:
12190 fixP->fx_r_type = BFD_RELOC_8_PCREL;
12191 break;
12192 }
12193 }
12194
12195 if (fixP->fx_addsy != NULL
12196 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
12197 || fixP->fx_r_type == BFD_RELOC_64_PCREL
12198 || fixP->fx_r_type == BFD_RELOC_16_PCREL
12199 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
12200 && !use_rela_relocations)
12201 {
12202 /* This is a hack. There should be a better way to handle this.
12203 This covers for the fact that bfd_install_relocation will
12204 subtract the current location (for partial_inplace, PC relative
12205 relocations); see more below. */
12206#ifndef OBJ_AOUT
12207 if (IS_ELF
12208#ifdef TE_PE
12209 || OUTPUT_FLAVOR == bfd_target_coff_flavour
12210#endif
12211 )
12212 value += fixP->fx_where + fixP->fx_frag->fr_address;
12213#endif
12214#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12215 if (IS_ELF)
12216 {
12217 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
12218
12219 if ((sym_seg == seg
12220 || (symbol_section_p (fixP->fx_addsy)
12221 && sym_seg != absolute_section))
12222 && !generic_force_reloc (fixP))
12223 {
12224 /* Yes, we add the values in twice. This is because
12225 bfd_install_relocation subtracts them out again. I think
12226 bfd_install_relocation is broken, but I don't dare change
12227 it. FIXME. */
12228 value += fixP->fx_where + fixP->fx_frag->fr_address;
12229 }
12230 }
12231#endif
12232#if defined (OBJ_COFF) && defined (TE_PE)
12233 /* For some reason, the PE format does not store a
12234 section address offset for a PC relative symbol. */
12235 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
12236 || S_IS_WEAK (fixP->fx_addsy))
12237 value += md_pcrel_from (fixP);
12238#endif
12239 }
12240#if defined (OBJ_COFF) && defined (TE_PE)
12241 if (fixP->fx_addsy != NULL
12242 && S_IS_WEAK (fixP->fx_addsy)
12243 /* PR 16858: Do not modify weak function references. */
12244 && ! fixP->fx_pcrel)
12245 {
12246#if !defined (TE_PEP)
12247 /* For x86 PE weak function symbols are neither PC-relative
12248 nor do they set S_IS_FUNCTION. So the only reliable way
12249 to detect them is to check the flags of their containing
12250 section. */
12251 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
12252 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
12253 ;
12254 else
12255#endif
12256 value -= S_GET_VALUE (fixP->fx_addsy);
12257 }
12258#endif
12259
12260 /* Fix a few things - the dynamic linker expects certain values here,
12261 and we must not disappoint it. */
12262#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12263 if (IS_ELF && fixP->fx_addsy)
12264 switch (fixP->fx_r_type)
12265 {
12266 case BFD_RELOC_386_PLT32:
12267 case BFD_RELOC_X86_64_PLT32:
12268 /* Make the jump instruction point to the address of the operand.
12269 At runtime we merely add the offset to the actual PLT entry.
12270 NB: Subtract the offset size only for jump instructions. */
12271 if (fixP->fx_pcrel)
12272 value = -4;
12273 break;
12274
12275 case BFD_RELOC_386_TLS_GD:
12276 case BFD_RELOC_386_TLS_LDM:
12277 case BFD_RELOC_386_TLS_IE_32:
12278 case BFD_RELOC_386_TLS_IE:
12279 case BFD_RELOC_386_TLS_GOTIE:
12280 case BFD_RELOC_386_TLS_GOTDESC:
12281 case BFD_RELOC_X86_64_TLSGD:
12282 case BFD_RELOC_X86_64_TLSLD:
12283 case BFD_RELOC_X86_64_GOTTPOFF:
12284 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12285 value = 0; /* Fully resolved at runtime. No addend. */
12286 /* Fallthrough */
12287 case BFD_RELOC_386_TLS_LE:
12288 case BFD_RELOC_386_TLS_LDO_32:
12289 case BFD_RELOC_386_TLS_LE_32:
12290 case BFD_RELOC_X86_64_DTPOFF32:
12291 case BFD_RELOC_X86_64_DTPOFF64:
12292 case BFD_RELOC_X86_64_TPOFF32:
12293 case BFD_RELOC_X86_64_TPOFF64:
12294 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12295 break;
12296
12297 case BFD_RELOC_386_TLS_DESC_CALL:
12298 case BFD_RELOC_X86_64_TLSDESC_CALL:
12299 value = 0; /* Fully resolved at runtime. No addend. */
12300 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12301 fixP->fx_done = 0;
12302 return;
12303
12304 case BFD_RELOC_VTABLE_INHERIT:
12305 case BFD_RELOC_VTABLE_ENTRY:
12306 fixP->fx_done = 0;
12307 return;
12308
12309 default:
12310 break;
12311 }
12312#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
12313 *valP = value;
12314#endif /* !defined (TE_Mach) */
12315
12316 /* Are we finished with this relocation now? */
12317 if (fixP->fx_addsy == NULL)
12318 fixP->fx_done = 1;
12319#if defined (OBJ_COFF) && defined (TE_PE)
12320 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
12321 {
12322 fixP->fx_done = 0;
12323 /* Remember value for tc_gen_reloc. */
12324 fixP->fx_addnumber = value;
12325 /* Clear out the frag for now. */
12326 value = 0;
12327 }
12328#endif
12329 else if (use_rela_relocations)
12330 {
12331 fixP->fx_no_overflow = 1;
12332 /* Remember value for tc_gen_reloc. */
12333 fixP->fx_addnumber = value;
12334 value = 0;
12335 }
12336
12337 md_number_to_chars (p, value, fixP->fx_size);
12338}
12339\f
12340const char *
12341md_atof (int type, char *litP, int *sizeP)
12342{
12343 /* This outputs the LITTLENUMs in REVERSE order;
12344 in accord with the bigendian 386. */
12345 return ieee_md_atof (type, litP, sizeP, FALSE);
12346}
12347\f
12348static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
12349
12350static char *
12351output_invalid (int c)
12352{
12353 if (ISPRINT (c))
12354 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
12355 "'%c'", c);
12356 else
12357 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
12358 "(0x%x)", (unsigned char) c);
12359 return output_invalid_buf;
12360}
12361
12362/* Verify that @r can be used in the current context. */
12363
12364static bfd_boolean check_register (const reg_entry *r)
12365{
12366 if (allow_pseudo_reg)
12367 return TRUE;
12368
12369 if (operand_type_all_zero (&r->reg_type))
12370 return FALSE;
12371
12372 if ((r->reg_type.bitfield.dword
12373 || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
12374 || r->reg_type.bitfield.class == RegCR
12375 || r->reg_type.bitfield.class == RegDR)
12376 && !cpu_arch_flags.bitfield.cpui386)
12377 return FALSE;
12378
12379 if (r->reg_type.bitfield.class == RegTR
12380 && (flag_code == CODE_64BIT
12381 || !cpu_arch_flags.bitfield.cpui386
12382 || cpu_arch_isa_flags.bitfield.cpui586
12383 || cpu_arch_isa_flags.bitfield.cpui686))
12384 return FALSE;
12385
12386 if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
12387 return FALSE;
12388
12389 if (!cpu_arch_flags.bitfield.cpuavx512f)
12390 {
12391 if (r->reg_type.bitfield.zmmword
12392 || r->reg_type.bitfield.class == RegMask)
12393 return FALSE;
12394
12395 if (!cpu_arch_flags.bitfield.cpuavx)
12396 {
12397 if (r->reg_type.bitfield.ymmword)
12398 return FALSE;
12399
12400 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
12401 return FALSE;
12402 }
12403 }
12404
12405 if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
12406 return FALSE;
12407
12408 /* Don't allow fake index register unless allow_index_reg isn't 0. */
12409 if (!allow_index_reg && r->reg_num == RegIZ)
12410 return FALSE;
12411
12412 /* Upper 16 vector registers are only available with VREX in 64bit
12413 mode, and require EVEX encoding. */
12414 if (r->reg_flags & RegVRex)
12415 {
12416 if (!cpu_arch_flags.bitfield.cpuavx512f
12417 || flag_code != CODE_64BIT)
12418 return FALSE;
12419
12420 if (i.vec_encoding == vex_encoding_default)
12421 i.vec_encoding = vex_encoding_evex;
12422 else if (i.vec_encoding != vex_encoding_evex)
12423 i.vec_encoding = vex_encoding_error;
12424 }
12425
12426 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
12427 && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR)
12428 && flag_code != CODE_64BIT)
12429 return FALSE;
12430
12431 if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
12432 && !intel_syntax)
12433 return FALSE;
12434
12435 return TRUE;
12436}
12437
12438/* REG_STRING starts *before* REGISTER_PREFIX. */
12439
12440static const reg_entry *
12441parse_real_register (char *reg_string, char **end_op)
12442{
12443 char *s = reg_string;
12444 char *p;
12445 char reg_name_given[MAX_REG_NAME_SIZE + 1];
12446 const reg_entry *r;
12447
12448 /* Skip possible REGISTER_PREFIX and possible whitespace. */
12449 if (*s == REGISTER_PREFIX)
12450 ++s;
12451
12452 if (is_space_char (*s))
12453 ++s;
12454
12455 p = reg_name_given;
12456 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
12457 {
12458 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
12459 return (const reg_entry *) NULL;
12460 s++;
12461 }
12462
12463 /* For naked regs, make sure that we are not dealing with an identifier.
12464 This prevents confusing an identifier like `eax_var' with register
12465 `eax'. */
12466 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
12467 return (const reg_entry *) NULL;
12468
12469 *end_op = s;
12470
12471 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
12472
12473 /* Handle floating point regs, allowing spaces in the (i) part. */
12474 if (r == i386_regtab /* %st is first entry of table */)
12475 {
12476 if (!cpu_arch_flags.bitfield.cpu8087
12477 && !cpu_arch_flags.bitfield.cpu287
12478 && !cpu_arch_flags.bitfield.cpu387
12479 && !allow_pseudo_reg)
12480 return (const reg_entry *) NULL;
12481
12482 if (is_space_char (*s))
12483 ++s;
12484 if (*s == '(')
12485 {
12486 ++s;
12487 if (is_space_char (*s))
12488 ++s;
12489 if (*s >= '0' && *s <= '7')
12490 {
12491 int fpr = *s - '0';
12492 ++s;
12493 if (is_space_char (*s))
12494 ++s;
12495 if (*s == ')')
12496 {
12497 *end_op = s + 1;
12498 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
12499 know (r);
12500 return r + fpr;
12501 }
12502 }
12503 /* We have "%st(" then garbage. */
12504 return (const reg_entry *) NULL;
12505 }
12506 }
12507
12508 return r && check_register (r) ? r : NULL;
12509}
12510
12511/* REG_STRING starts *before* REGISTER_PREFIX. */
12512
12513static const reg_entry *
12514parse_register (char *reg_string, char **end_op)
12515{
12516 const reg_entry *r;
12517
12518 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
12519 r = parse_real_register (reg_string, end_op);
12520 else
12521 r = NULL;
12522 if (!r)
12523 {
12524 char *save = input_line_pointer;
12525 char c;
12526 symbolS *symbolP;
12527
12528 input_line_pointer = reg_string;
12529 c = get_symbol_name (&reg_string);
12530 symbolP = symbol_find (reg_string);
12531 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
12532 {
12533 const expressionS *e = symbol_get_value_expression (symbolP);
12534
12535 know (e->X_op == O_register);
12536 know (e->X_add_number >= 0
12537 && (valueT) e->X_add_number < i386_regtab_size);
12538 r = i386_regtab + e->X_add_number;
12539 if (!check_register (r))
12540 {
12541 as_bad (_("register '%s%s' cannot be used here"),
12542 register_prefix, r->reg_name);
12543 r = &bad_reg;
12544 }
12545 *end_op = input_line_pointer;
12546 }
12547 *input_line_pointer = c;
12548 input_line_pointer = save;
12549 }
12550 return r;
12551}
12552
12553int
12554i386_parse_name (char *name, expressionS *e, char *nextcharP)
12555{
12556 const reg_entry *r;
12557 char *end = input_line_pointer;
12558
12559 *end = *nextcharP;
12560 r = parse_register (name, &input_line_pointer);
12561 if (r && end <= input_line_pointer)
12562 {
12563 *nextcharP = *input_line_pointer;
12564 *input_line_pointer = 0;
12565 if (r != &bad_reg)
12566 {
12567 e->X_op = O_register;
12568 e->X_add_number = r - i386_regtab;
12569 }
12570 else
12571 e->X_op = O_illegal;
12572 return 1;
12573 }
12574 input_line_pointer = end;
12575 *end = 0;
12576 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
12577}
12578
12579void
12580md_operand (expressionS *e)
12581{
12582 char *end;
12583 const reg_entry *r;
12584
12585 switch (*input_line_pointer)
12586 {
12587 case REGISTER_PREFIX:
12588 r = parse_real_register (input_line_pointer, &end);
12589 if (r)
12590 {
12591 e->X_op = O_register;
12592 e->X_add_number = r - i386_regtab;
12593 input_line_pointer = end;
12594 }
12595 break;
12596
12597 case '[':
12598 gas_assert (intel_syntax);
12599 end = input_line_pointer++;
12600 expression (e);
12601 if (*input_line_pointer == ']')
12602 {
12603 ++input_line_pointer;
12604 e->X_op_symbol = make_expr_symbol (e);
12605 e->X_add_symbol = NULL;
12606 e->X_add_number = 0;
12607 e->X_op = O_index;
12608 }
12609 else
12610 {
12611 e->X_op = O_absent;
12612 input_line_pointer = end;
12613 }
12614 break;
12615 }
12616}
12617
12618\f
12619#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12620const char *md_shortopts = "kVQ:sqnO::";
12621#else
12622const char *md_shortopts = "qnO::";
12623#endif
12624
12625#define OPTION_32 (OPTION_MD_BASE + 0)
12626#define OPTION_64 (OPTION_MD_BASE + 1)
12627#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
12628#define OPTION_MARCH (OPTION_MD_BASE + 3)
12629#define OPTION_MTUNE (OPTION_MD_BASE + 4)
12630#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
12631#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
12632#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
12633#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
12634#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
12635#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
12636#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
12637#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
12638#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
12639#define OPTION_X32 (OPTION_MD_BASE + 14)
12640#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
12641#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
12642#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
12643#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
12644#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
12645#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
12646#define OPTION_MSHARED (OPTION_MD_BASE + 21)
12647#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
12648#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
12649#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
12650#define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
12651#define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
12652#define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
12653#define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
12654#define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
12655#define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
12656#define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
12657#define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
12658#define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
12659
12660struct option md_longopts[] =
12661{
12662 {"32", no_argument, NULL, OPTION_32},
12663#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12664 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12665 {"64", no_argument, NULL, OPTION_64},
12666#endif
12667#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12668 {"x32", no_argument, NULL, OPTION_X32},
12669 {"mshared", no_argument, NULL, OPTION_MSHARED},
12670 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
12671#endif
12672 {"divide", no_argument, NULL, OPTION_DIVIDE},
12673 {"march", required_argument, NULL, OPTION_MARCH},
12674 {"mtune", required_argument, NULL, OPTION_MTUNE},
12675 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
12676 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
12677 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
12678 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
12679 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
12680 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
12681 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
12682 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
12683 {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
12684 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
12685 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
12686 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
12687# if defined (TE_PE) || defined (TE_PEP)
12688 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
12689#endif
12690 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
12691 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
12692 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
12693 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
12694 {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY},
12695 {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE},
12696 {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH},
12697 {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES},
12698 {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD},
12699 {"mlfence-before-indirect-branch", required_argument, NULL,
12700 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH},
12701 {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET},
12702 {"mamd64", no_argument, NULL, OPTION_MAMD64},
12703 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
12704 {NULL, no_argument, NULL, 0}
12705};
12706size_t md_longopts_size = sizeof (md_longopts);
12707
12708int
12709md_parse_option (int c, const char *arg)
12710{
12711 unsigned int j;
12712 char *arch, *next, *saved, *type;
12713
12714 switch (c)
12715 {
12716 case 'n':
12717 optimize_align_code = 0;
12718 break;
12719
12720 case 'q':
12721 quiet_warnings = 1;
12722 break;
12723
12724#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12725 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
12726 should be emitted or not. FIXME: Not implemented. */
12727 case 'Q':
12728 if ((arg[0] != 'y' && arg[0] != 'n') || arg[1])
12729 return 0;
12730 break;
12731
12732 /* -V: SVR4 argument to print version ID. */
12733 case 'V':
12734 print_version_id ();
12735 break;
12736
12737 /* -k: Ignore for FreeBSD compatibility. */
12738 case 'k':
12739 break;
12740
12741 case 's':
12742 /* -s: On i386 Solaris, this tells the native assembler to use
12743 .stab instead of .stab.excl. We always use .stab anyhow. */
12744 break;
12745
12746 case OPTION_MSHARED:
12747 shared = 1;
12748 break;
12749
12750 case OPTION_X86_USED_NOTE:
12751 if (strcasecmp (arg, "yes") == 0)
12752 x86_used_note = 1;
12753 else if (strcasecmp (arg, "no") == 0)
12754 x86_used_note = 0;
12755 else
12756 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
12757 break;
12758
12759
12760#endif
12761#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
12762 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
12763 case OPTION_64:
12764 {
12765 const char **list, **l;
12766
12767 list = bfd_target_list ();
12768 for (l = list; *l != NULL; l++)
12769 if (CONST_STRNEQ (*l, "elf64-x86-64")
12770 || strcmp (*l, "coff-x86-64") == 0
12771 || strcmp (*l, "pe-x86-64") == 0
12772 || strcmp (*l, "pei-x86-64") == 0
12773 || strcmp (*l, "mach-o-x86-64") == 0)
12774 {
12775 default_arch = "x86_64";
12776 break;
12777 }
12778 if (*l == NULL)
12779 as_fatal (_("no compiled in support for x86_64"));
12780 free (list);
12781 }
12782 break;
12783#endif
12784
12785#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12786 case OPTION_X32:
12787 if (IS_ELF)
12788 {
12789 const char **list, **l;
12790
12791 list = bfd_target_list ();
12792 for (l = list; *l != NULL; l++)
12793 if (CONST_STRNEQ (*l, "elf32-x86-64"))
12794 {
12795 default_arch = "x86_64:32";
12796 break;
12797 }
12798 if (*l == NULL)
12799 as_fatal (_("no compiled in support for 32bit x86_64"));
12800 free (list);
12801 }
12802 else
12803 as_fatal (_("32bit x86_64 is only supported for ELF"));
12804 break;
12805#endif
12806
12807 case OPTION_32:
12808 default_arch = "i386";
12809 break;
12810
12811 case OPTION_DIVIDE:
12812#ifdef SVR4_COMMENT_CHARS
12813 {
12814 char *n, *t;
12815 const char *s;
12816
12817 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
12818 t = n;
12819 for (s = i386_comment_chars; *s != '\0'; s++)
12820 if (*s != '/')
12821 *t++ = *s;
12822 *t = '\0';
12823 i386_comment_chars = n;
12824 }
12825#endif
12826 break;
12827
12828 case OPTION_MARCH:
12829 saved = xstrdup (arg);
12830 arch = saved;
12831 /* Allow -march=+nosse. */
12832 if (*arch == '+')
12833 arch++;
12834 do
12835 {
12836 if (*arch == '.')
12837 as_fatal (_("invalid -march= option: `%s'"), arg);
12838 next = strchr (arch, '+');
12839 if (next)
12840 *next++ = '\0';
12841 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
12842 {
12843 if (strcmp (arch, cpu_arch [j].name) == 0)
12844 {
12845 /* Processor. */
12846 if (! cpu_arch[j].flags.bitfield.cpui386)
12847 continue;
12848
12849 cpu_arch_name = cpu_arch[j].name;
12850 cpu_sub_arch_name = NULL;
12851 cpu_arch_flags = cpu_arch[j].flags;
12852 cpu_arch_isa = cpu_arch[j].type;
12853 cpu_arch_isa_flags = cpu_arch[j].flags;
12854 if (!cpu_arch_tune_set)
12855 {
12856 cpu_arch_tune = cpu_arch_isa;
12857 cpu_arch_tune_flags = cpu_arch_isa_flags;
12858 }
12859 break;
12860 }
12861 else if (*cpu_arch [j].name == '.'
12862 && strcmp (arch, cpu_arch [j].name + 1) == 0)
12863 {
12864 /* ISA extension. */
12865 i386_cpu_flags flags;
12866
12867 flags = cpu_flags_or (cpu_arch_flags,
12868 cpu_arch[j].flags);
12869
12870 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
12871 {
12872 if (cpu_sub_arch_name)
12873 {
12874 char *name = cpu_sub_arch_name;
12875 cpu_sub_arch_name = concat (name,
12876 cpu_arch[j].name,
12877 (const char *) NULL);
12878 free (name);
12879 }
12880 else
12881 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
12882 cpu_arch_flags = flags;
12883 cpu_arch_isa_flags = flags;
12884 }
12885 else
12886 cpu_arch_isa_flags
12887 = cpu_flags_or (cpu_arch_isa_flags,
12888 cpu_arch[j].flags);
12889 break;
12890 }
12891 }
12892
12893 if (j >= ARRAY_SIZE (cpu_arch))
12894 {
12895 /* Disable an ISA extension. */
12896 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
12897 if (strcmp (arch, cpu_noarch [j].name) == 0)
12898 {
12899 i386_cpu_flags flags;
12900
12901 flags = cpu_flags_and_not (cpu_arch_flags,
12902 cpu_noarch[j].flags);
12903 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
12904 {
12905 if (cpu_sub_arch_name)
12906 {
12907 char *name = cpu_sub_arch_name;
12908 cpu_sub_arch_name = concat (arch,
12909 (const char *) NULL);
12910 free (name);
12911 }
12912 else
12913 cpu_sub_arch_name = xstrdup (arch);
12914 cpu_arch_flags = flags;
12915 cpu_arch_isa_flags = flags;
12916 }
12917 break;
12918 }
12919
12920 if (j >= ARRAY_SIZE (cpu_noarch))
12921 j = ARRAY_SIZE (cpu_arch);
12922 }
12923
12924 if (j >= ARRAY_SIZE (cpu_arch))
12925 as_fatal (_("invalid -march= option: `%s'"), arg);
12926
12927 arch = next;
12928 }
12929 while (next != NULL);
12930 free (saved);
12931 break;
12932
12933 case OPTION_MTUNE:
12934 if (*arg == '.')
12935 as_fatal (_("invalid -mtune= option: `%s'"), arg);
12936 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
12937 {
12938 if (strcmp (arg, cpu_arch [j].name) == 0)
12939 {
12940 cpu_arch_tune_set = 1;
12941 cpu_arch_tune = cpu_arch [j].type;
12942 cpu_arch_tune_flags = cpu_arch[j].flags;
12943 break;
12944 }
12945 }
12946 if (j >= ARRAY_SIZE (cpu_arch))
12947 as_fatal (_("invalid -mtune= option: `%s'"), arg);
12948 break;
12949
12950 case OPTION_MMNEMONIC:
12951 if (strcasecmp (arg, "att") == 0)
12952 intel_mnemonic = 0;
12953 else if (strcasecmp (arg, "intel") == 0)
12954 intel_mnemonic = 1;
12955 else
12956 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
12957 break;
12958
12959 case OPTION_MSYNTAX:
12960 if (strcasecmp (arg, "att") == 0)
12961 intel_syntax = 0;
12962 else if (strcasecmp (arg, "intel") == 0)
12963 intel_syntax = 1;
12964 else
12965 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
12966 break;
12967
12968 case OPTION_MINDEX_REG:
12969 allow_index_reg = 1;
12970 break;
12971
12972 case OPTION_MNAKED_REG:
12973 allow_naked_reg = 1;
12974 break;
12975
12976 case OPTION_MSSE2AVX:
12977 sse2avx = 1;
12978 break;
12979
12980 case OPTION_MSSE_CHECK:
12981 if (strcasecmp (arg, "error") == 0)
12982 sse_check = check_error;
12983 else if (strcasecmp (arg, "warning") == 0)
12984 sse_check = check_warning;
12985 else if (strcasecmp (arg, "none") == 0)
12986 sse_check = check_none;
12987 else
12988 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
12989 break;
12990
12991 case OPTION_MOPERAND_CHECK:
12992 if (strcasecmp (arg, "error") == 0)
12993 operand_check = check_error;
12994 else if (strcasecmp (arg, "warning") == 0)
12995 operand_check = check_warning;
12996 else if (strcasecmp (arg, "none") == 0)
12997 operand_check = check_none;
12998 else
12999 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
13000 break;
13001
13002 case OPTION_MAVXSCALAR:
13003 if (strcasecmp (arg, "128") == 0)
13004 avxscalar = vex128;
13005 else if (strcasecmp (arg, "256") == 0)
13006 avxscalar = vex256;
13007 else
13008 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
13009 break;
13010
13011 case OPTION_MVEXWIG:
13012 if (strcmp (arg, "0") == 0)
13013 vexwig = vexw0;
13014 else if (strcmp (arg, "1") == 0)
13015 vexwig = vexw1;
13016 else
13017 as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
13018 break;
13019
13020 case OPTION_MADD_BND_PREFIX:
13021 add_bnd_prefix = 1;
13022 break;
13023
13024 case OPTION_MEVEXLIG:
13025 if (strcmp (arg, "128") == 0)
13026 evexlig = evexl128;
13027 else if (strcmp (arg, "256") == 0)
13028 evexlig = evexl256;
13029 else if (strcmp (arg, "512") == 0)
13030 evexlig = evexl512;
13031 else
13032 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
13033 break;
13034
13035 case OPTION_MEVEXRCIG:
13036 if (strcmp (arg, "rne") == 0)
13037 evexrcig = rne;
13038 else if (strcmp (arg, "rd") == 0)
13039 evexrcig = rd;
13040 else if (strcmp (arg, "ru") == 0)
13041 evexrcig = ru;
13042 else if (strcmp (arg, "rz") == 0)
13043 evexrcig = rz;
13044 else
13045 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
13046 break;
13047
13048 case OPTION_MEVEXWIG:
13049 if (strcmp (arg, "0") == 0)
13050 evexwig = evexw0;
13051 else if (strcmp (arg, "1") == 0)
13052 evexwig = evexw1;
13053 else
13054 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
13055 break;
13056
13057# if defined (TE_PE) || defined (TE_PEP)
13058 case OPTION_MBIG_OBJ:
13059 use_big_obj = 1;
13060 break;
13061#endif
13062
13063 case OPTION_MOMIT_LOCK_PREFIX:
13064 if (strcasecmp (arg, "yes") == 0)
13065 omit_lock_prefix = 1;
13066 else if (strcasecmp (arg, "no") == 0)
13067 omit_lock_prefix = 0;
13068 else
13069 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
13070 break;
13071
13072 case OPTION_MFENCE_AS_LOCK_ADD:
13073 if (strcasecmp (arg, "yes") == 0)
13074 avoid_fence = 1;
13075 else if (strcasecmp (arg, "no") == 0)
13076 avoid_fence = 0;
13077 else
13078 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
13079 break;
13080
13081 case OPTION_MLFENCE_AFTER_LOAD:
13082 if (strcasecmp (arg, "yes") == 0)
13083 lfence_after_load = 1;
13084 else if (strcasecmp (arg, "no") == 0)
13085 lfence_after_load = 0;
13086 else
13087 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg);
13088 break;
13089
13090 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH:
13091 if (strcasecmp (arg, "all") == 0)
13092 {
13093 lfence_before_indirect_branch = lfence_branch_all;
13094 if (lfence_before_ret == lfence_before_ret_none)
13095 lfence_before_ret = lfence_before_ret_shl;
13096 }
13097 else if (strcasecmp (arg, "memory") == 0)
13098 lfence_before_indirect_branch = lfence_branch_memory;
13099 else if (strcasecmp (arg, "register") == 0)
13100 lfence_before_indirect_branch = lfence_branch_register;
13101 else if (strcasecmp (arg, "none") == 0)
13102 lfence_before_indirect_branch = lfence_branch_none;
13103 else
13104 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
13105 arg);
13106 break;
13107
13108 case OPTION_MLFENCE_BEFORE_RET:
13109 if (strcasecmp (arg, "or") == 0)
13110 lfence_before_ret = lfence_before_ret_or;
13111 else if (strcasecmp (arg, "not") == 0)
13112 lfence_before_ret = lfence_before_ret_not;
13113 else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0)
13114 lfence_before_ret = lfence_before_ret_shl;
13115 else if (strcasecmp (arg, "none") == 0)
13116 lfence_before_ret = lfence_before_ret_none;
13117 else
13118 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
13119 arg);
13120 break;
13121
13122 case OPTION_MRELAX_RELOCATIONS:
13123 if (strcasecmp (arg, "yes") == 0)
13124 generate_relax_relocations = 1;
13125 else if (strcasecmp (arg, "no") == 0)
13126 generate_relax_relocations = 0;
13127 else
13128 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
13129 break;
13130
13131 case OPTION_MALIGN_BRANCH_BOUNDARY:
13132 {
13133 char *end;
13134 long int align = strtoul (arg, &end, 0);
13135 if (*end == '\0')
13136 {
13137 if (align == 0)
13138 {
13139 align_branch_power = 0;
13140 break;
13141 }
13142 else if (align >= 16)
13143 {
13144 int align_power;
13145 for (align_power = 0;
13146 (align & 1) == 0;
13147 align >>= 1, align_power++)
13148 continue;
13149 /* Limit alignment power to 31. */
13150 if (align == 1 && align_power < 32)
13151 {
13152 align_branch_power = align_power;
13153 break;
13154 }
13155 }
13156 }
13157 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg);
13158 }
13159 break;
13160
13161 case OPTION_MALIGN_BRANCH_PREFIX_SIZE:
13162 {
13163 char *end;
13164 int align = strtoul (arg, &end, 0);
13165 /* Some processors only support 5 prefixes. */
13166 if (*end == '\0' && align >= 0 && align < 6)
13167 {
13168 align_branch_prefix_size = align;
13169 break;
13170 }
13171 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
13172 arg);
13173 }
13174 break;
13175
13176 case OPTION_MALIGN_BRANCH:
13177 align_branch = 0;
13178 saved = xstrdup (arg);
13179 type = saved;
13180 do
13181 {
13182 next = strchr (type, '+');
13183 if (next)
13184 *next++ = '\0';
13185 if (strcasecmp (type, "jcc") == 0)
13186 align_branch |= align_branch_jcc_bit;
13187 else if (strcasecmp (type, "fused") == 0)
13188 align_branch |= align_branch_fused_bit;
13189 else if (strcasecmp (type, "jmp") == 0)
13190 align_branch |= align_branch_jmp_bit;
13191 else if (strcasecmp (type, "call") == 0)
13192 align_branch |= align_branch_call_bit;
13193 else if (strcasecmp (type, "ret") == 0)
13194 align_branch |= align_branch_ret_bit;
13195 else if (strcasecmp (type, "indirect") == 0)
13196 align_branch |= align_branch_indirect_bit;
13197 else
13198 as_fatal (_("invalid -malign-branch= option: `%s'"), arg);
13199 type = next;
13200 }
13201 while (next != NULL);
13202 free (saved);
13203 break;
13204
13205 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES:
13206 align_branch_power = 5;
13207 align_branch_prefix_size = 5;
13208 align_branch = (align_branch_jcc_bit
13209 | align_branch_fused_bit
13210 | align_branch_jmp_bit);
13211 break;
13212
13213 case OPTION_MAMD64:
13214 isa64 = amd64;
13215 break;
13216
13217 case OPTION_MINTEL64:
13218 isa64 = intel64;
13219 break;
13220
13221 case 'O':
13222 if (arg == NULL)
13223 {
13224 optimize = 1;
13225 /* Turn off -Os. */
13226 optimize_for_space = 0;
13227 }
13228 else if (*arg == 's')
13229 {
13230 optimize_for_space = 1;
13231 /* Turn on all encoding optimizations. */
13232 optimize = INT_MAX;
13233 }
13234 else
13235 {
13236 optimize = atoi (arg);
13237 /* Turn off -Os. */
13238 optimize_for_space = 0;
13239 }
13240 break;
13241
13242 default:
13243 return 0;
13244 }
13245 return 1;
13246}
13247
13248#define MESSAGE_TEMPLATE \
13249" "
13250
13251static char *
13252output_message (FILE *stream, char *p, char *message, char *start,
13253 int *left_p, const char *name, int len)
13254{
13255 int size = sizeof (MESSAGE_TEMPLATE);
13256 int left = *left_p;
13257
13258 /* Reserve 2 spaces for ", " or ",\0" */
13259 left -= len + 2;
13260
13261 /* Check if there is any room. */
13262 if (left >= 0)
13263 {
13264 if (p != start)
13265 {
13266 *p++ = ',';
13267 *p++ = ' ';
13268 }
13269 p = mempcpy (p, name, len);
13270 }
13271 else
13272 {
13273 /* Output the current message now and start a new one. */
13274 *p++ = ',';
13275 *p = '\0';
13276 fprintf (stream, "%s\n", message);
13277 p = start;
13278 left = size - (start - message) - len - 2;
13279
13280 gas_assert (left >= 0);
13281
13282 p = mempcpy (p, name, len);
13283 }
13284
13285 *left_p = left;
13286 return p;
13287}
13288
13289static void
13290show_arch (FILE *stream, int ext, int check)
13291{
13292 static char message[] = MESSAGE_TEMPLATE;
13293 char *start = message + 27;
13294 char *p;
13295 int size = sizeof (MESSAGE_TEMPLATE);
13296 int left;
13297 const char *name;
13298 int len;
13299 unsigned int j;
13300
13301 p = start;
13302 left = size - (start - message);
13303 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
13304 {
13305 /* Should it be skipped? */
13306 if (cpu_arch [j].skip)
13307 continue;
13308
13309 name = cpu_arch [j].name;
13310 len = cpu_arch [j].len;
13311 if (*name == '.')
13312 {
13313 /* It is an extension. Skip if we aren't asked to show it. */
13314 if (ext)
13315 {
13316 name++;
13317 len--;
13318 }
13319 else
13320 continue;
13321 }
13322 else if (ext)
13323 {
13324 /* It is an processor. Skip if we show only extension. */
13325 continue;
13326 }
13327 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
13328 {
13329 /* It is an impossible processor - skip. */
13330 continue;
13331 }
13332
13333 p = output_message (stream, p, message, start, &left, name, len);
13334 }
13335
13336 /* Display disabled extensions. */
13337 if (ext)
13338 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
13339 {
13340 name = cpu_noarch [j].name;
13341 len = cpu_noarch [j].len;
13342 p = output_message (stream, p, message, start, &left, name,
13343 len);
13344 }
13345
13346 *p = '\0';
13347 fprintf (stream, "%s\n", message);
13348}
13349
13350void
13351md_show_usage (FILE *stream)
13352{
13353#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13354 fprintf (stream, _("\
13355 -Qy, -Qn ignored\n\
13356 -V print assembler version number\n\
13357 -k ignored\n"));
13358#endif
13359 fprintf (stream, _("\
13360 -n Do not optimize code alignment\n\
13361 -q quieten some warnings\n"));
13362#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13363 fprintf (stream, _("\
13364 -s ignored\n"));
13365#endif
13366#if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13367 || defined (TE_PE) || defined (TE_PEP))
13368 fprintf (stream, _("\
13369 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
13370#endif
13371#ifdef SVR4_COMMENT_CHARS
13372 fprintf (stream, _("\
13373 --divide do not treat `/' as a comment character\n"));
13374#else
13375 fprintf (stream, _("\
13376 --divide ignored\n"));
13377#endif
13378 fprintf (stream, _("\
13379 -march=CPU[,+EXTENSION...]\n\
13380 generate code for CPU and EXTENSION, CPU is one of:\n"));
13381 show_arch (stream, 0, 1);
13382 fprintf (stream, _("\
13383 EXTENSION is combination of:\n"));
13384 show_arch (stream, 1, 0);
13385 fprintf (stream, _("\
13386 -mtune=CPU optimize for CPU, CPU is one of:\n"));
13387 show_arch (stream, 0, 0);
13388 fprintf (stream, _("\
13389 -msse2avx encode SSE instructions with VEX prefix\n"));
13390 fprintf (stream, _("\
13391 -msse-check=[none|error|warning] (default: warning)\n\
13392 check SSE instructions\n"));
13393 fprintf (stream, _("\
13394 -moperand-check=[none|error|warning] (default: warning)\n\
13395 check operand combinations for validity\n"));
13396 fprintf (stream, _("\
13397 -mavxscalar=[128|256] (default: 128)\n\
13398 encode scalar AVX instructions with specific vector\n\
13399 length\n"));
13400 fprintf (stream, _("\
13401 -mvexwig=[0|1] (default: 0)\n\
13402 encode VEX instructions with specific VEX.W value\n\
13403 for VEX.W bit ignored instructions\n"));
13404 fprintf (stream, _("\
13405 -mevexlig=[128|256|512] (default: 128)\n\
13406 encode scalar EVEX instructions with specific vector\n\
13407 length\n"));
13408 fprintf (stream, _("\
13409 -mevexwig=[0|1] (default: 0)\n\
13410 encode EVEX instructions with specific EVEX.W value\n\
13411 for EVEX.W bit ignored instructions\n"));
13412 fprintf (stream, _("\
13413 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
13414 encode EVEX instructions with specific EVEX.RC value\n\
13415 for SAE-only ignored instructions\n"));
13416 fprintf (stream, _("\
13417 -mmnemonic=[att|intel] "));
13418 if (SYSV386_COMPAT)
13419 fprintf (stream, _("(default: att)\n"));
13420 else
13421 fprintf (stream, _("(default: intel)\n"));
13422 fprintf (stream, _("\
13423 use AT&T/Intel mnemonic\n"));
13424 fprintf (stream, _("\
13425 -msyntax=[att|intel] (default: att)\n\
13426 use AT&T/Intel syntax\n"));
13427 fprintf (stream, _("\
13428 -mindex-reg support pseudo index registers\n"));
13429 fprintf (stream, _("\
13430 -mnaked-reg don't require `%%' prefix for registers\n"));
13431 fprintf (stream, _("\
13432 -madd-bnd-prefix add BND prefix for all valid branches\n"));
13433#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13434 fprintf (stream, _("\
13435 -mshared disable branch optimization for shared code\n"));
13436 fprintf (stream, _("\
13437 -mx86-used-note=[no|yes] "));
13438 if (DEFAULT_X86_USED_NOTE)
13439 fprintf (stream, _("(default: yes)\n"));
13440 else
13441 fprintf (stream, _("(default: no)\n"));
13442 fprintf (stream, _("\
13443 generate x86 used ISA and feature properties\n"));
13444#endif
13445#if defined (TE_PE) || defined (TE_PEP)
13446 fprintf (stream, _("\
13447 -mbig-obj generate big object files\n"));
13448#endif
13449 fprintf (stream, _("\
13450 -momit-lock-prefix=[no|yes] (default: no)\n\
13451 strip all lock prefixes\n"));
13452 fprintf (stream, _("\
13453 -mfence-as-lock-add=[no|yes] (default: no)\n\
13454 encode lfence, mfence and sfence as\n\
13455 lock addl $0x0, (%%{re}sp)\n"));
13456 fprintf (stream, _("\
13457 -mrelax-relocations=[no|yes] "));
13458 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
13459 fprintf (stream, _("(default: yes)\n"));
13460 else
13461 fprintf (stream, _("(default: no)\n"));
13462 fprintf (stream, _("\
13463 generate relax relocations\n"));
13464 fprintf (stream, _("\
13465 -malign-branch-boundary=NUM (default: 0)\n\
13466 align branches within NUM byte boundary\n"));
13467 fprintf (stream, _("\
13468 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
13469 TYPE is combination of jcc, fused, jmp, call, ret,\n\
13470 indirect\n\
13471 specify types of branches to align\n"));
13472 fprintf (stream, _("\
13473 -malign-branch-prefix-size=NUM (default: 5)\n\
13474 align branches with NUM prefixes per instruction\n"));
13475 fprintf (stream, _("\
13476 -mbranches-within-32B-boundaries\n\
13477 align branches within 32 byte boundary\n"));
13478 fprintf (stream, _("\
13479 -mlfence-after-load=[no|yes] (default: no)\n\
13480 generate lfence after load\n"));
13481 fprintf (stream, _("\
13482 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
13483 generate lfence before indirect near branch\n"));
13484 fprintf (stream, _("\
13485 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
13486 generate lfence before ret\n"));
13487 fprintf (stream, _("\
13488 -mamd64 accept only AMD64 ISA [default]\n"));
13489 fprintf (stream, _("\
13490 -mintel64 accept only Intel64 ISA\n"));
13491}
13492
13493#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
13494 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
13495 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
13496
13497/* Pick the target format to use. */
13498
13499const char *
13500i386_target_format (void)
13501{
13502 if (!strncmp (default_arch, "x86_64", 6))
13503 {
13504 update_code_flag (CODE_64BIT, 1);
13505 if (default_arch[6] == '\0')
13506 x86_elf_abi = X86_64_ABI;
13507 else
13508 x86_elf_abi = X86_64_X32_ABI;
13509 }
13510 else if (!strcmp (default_arch, "i386"))
13511 update_code_flag (CODE_32BIT, 1);
13512 else if (!strcmp (default_arch, "iamcu"))
13513 {
13514 update_code_flag (CODE_32BIT, 1);
13515 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
13516 {
13517 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
13518 cpu_arch_name = "iamcu";
13519 cpu_sub_arch_name = NULL;
13520 cpu_arch_flags = iamcu_flags;
13521 cpu_arch_isa = PROCESSOR_IAMCU;
13522 cpu_arch_isa_flags = iamcu_flags;
13523 if (!cpu_arch_tune_set)
13524 {
13525 cpu_arch_tune = cpu_arch_isa;
13526 cpu_arch_tune_flags = cpu_arch_isa_flags;
13527 }
13528 }
13529 else if (cpu_arch_isa != PROCESSOR_IAMCU)
13530 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
13531 cpu_arch_name);
13532 }
13533 else
13534 as_fatal (_("unknown architecture"));
13535
13536 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
13537 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
13538 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
13539 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
13540
13541 switch (OUTPUT_FLAVOR)
13542 {
13543#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
13544 case bfd_target_aout_flavour:
13545 return AOUT_TARGET_FORMAT;
13546#endif
13547#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
13548# if defined (TE_PE) || defined (TE_PEP)
13549 case bfd_target_coff_flavour:
13550 if (flag_code == CODE_64BIT)
13551 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
13552 else
13553 return use_big_obj ? "pe-bigobj-i386" : "pe-i386";
13554# elif defined (TE_GO32)
13555 case bfd_target_coff_flavour:
13556 return "coff-go32";
13557# else
13558 case bfd_target_coff_flavour:
13559 return "coff-i386";
13560# endif
13561#endif
13562#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13563 case bfd_target_elf_flavour:
13564 {
13565 const char *format;
13566
13567 switch (x86_elf_abi)
13568 {
13569 default:
13570 format = ELF_TARGET_FORMAT;
13571#ifndef TE_SOLARIS
13572 tls_get_addr = "___tls_get_addr";
13573#endif
13574 break;
13575 case X86_64_ABI:
13576 use_rela_relocations = 1;
13577 object_64bit = 1;
13578#ifndef TE_SOLARIS
13579 tls_get_addr = "__tls_get_addr";
13580#endif
13581 format = ELF_TARGET_FORMAT64;
13582 break;
13583 case X86_64_X32_ABI:
13584 use_rela_relocations = 1;
13585 object_64bit = 1;
13586#ifndef TE_SOLARIS
13587 tls_get_addr = "__tls_get_addr";
13588#endif
13589 disallow_64bit_reloc = 1;
13590 format = ELF_TARGET_FORMAT32;
13591 break;
13592 }
13593 if (cpu_arch_isa == PROCESSOR_L1OM)
13594 {
13595 if (x86_elf_abi != X86_64_ABI)
13596 as_fatal (_("Intel L1OM is 64bit only"));
13597 return ELF_TARGET_L1OM_FORMAT;
13598 }
13599 else if (cpu_arch_isa == PROCESSOR_K1OM)
13600 {
13601 if (x86_elf_abi != X86_64_ABI)
13602 as_fatal (_("Intel K1OM is 64bit only"));
13603 return ELF_TARGET_K1OM_FORMAT;
13604 }
13605 else if (cpu_arch_isa == PROCESSOR_IAMCU)
13606 {
13607 if (x86_elf_abi != I386_ABI)
13608 as_fatal (_("Intel MCU is 32bit only"));
13609 return ELF_TARGET_IAMCU_FORMAT;
13610 }
13611 else
13612 return format;
13613 }
13614#endif
13615#if defined (OBJ_MACH_O)
13616 case bfd_target_mach_o_flavour:
13617 if (flag_code == CODE_64BIT)
13618 {
13619 use_rela_relocations = 1;
13620 object_64bit = 1;
13621 return "mach-o-x86-64";
13622 }
13623 else
13624 return "mach-o-i386";
13625#endif
13626 default:
13627 abort ();
13628 return NULL;
13629 }
13630}
13631
13632#endif /* OBJ_MAYBE_ more than one */
13633\f
13634symbolS *
13635md_undefined_symbol (char *name)
13636{
13637 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
13638 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
13639 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
13640 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
13641 {
13642 if (!GOT_symbol)
13643 {
13644 if (symbol_find (name))
13645 as_bad (_("GOT already in symbol table"));
13646 GOT_symbol = symbol_new (name, undefined_section,
13647 (valueT) 0, &zero_address_frag);
13648 };
13649 return GOT_symbol;
13650 }
13651 return 0;
13652}
13653
13654/* Round up a section size to the appropriate boundary. */
13655
13656valueT
13657md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
13658{
13659#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13660 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
13661 {
13662 /* For a.out, force the section size to be aligned. If we don't do
13663 this, BFD will align it for us, but it will not write out the
13664 final bytes of the section. This may be a bug in BFD, but it is
13665 easier to fix it here since that is how the other a.out targets
13666 work. */
13667 int align;
13668
13669 align = bfd_section_alignment (segment);
13670 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
13671 }
13672#endif
13673
13674 return size;
13675}
13676
13677/* On the i386, PC-relative offsets are relative to the start of the
13678 next instruction. That is, the address of the offset, plus its
13679 size, since the offset is always the last part of the insn. */
13680
13681long
13682md_pcrel_from (fixS *fixP)
13683{
13684 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
13685}
13686
13687#ifndef I386COFF
13688
13689static void
13690s_bss (int ignore ATTRIBUTE_UNUSED)
13691{
13692 int temp;
13693
13694#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13695 if (IS_ELF)
13696 obj_elf_section_change_hook ();
13697#endif
13698 temp = get_absolute_expression ();
13699 subseg_set (bss_section, (subsegT) temp);
13700 demand_empty_rest_of_line ();
13701}
13702
13703#endif
13704
13705/* Remember constant directive. */
13706
13707void
13708i386_cons_align (int ignore ATTRIBUTE_UNUSED)
13709{
13710 if (last_insn.kind != last_insn_directive
13711 && (bfd_section_flags (now_seg) & SEC_CODE))
13712 {
13713 last_insn.seg = now_seg;
13714 last_insn.kind = last_insn_directive;
13715 last_insn.name = "constant directive";
13716 last_insn.file = as_where (&last_insn.line);
13717 if (lfence_before_ret != lfence_before_ret_none)
13718 {
13719 if (lfence_before_indirect_branch != lfence_branch_none)
13720 as_warn (_("constant directive skips -mlfence-before-ret "
13721 "and -mlfence-before-indirect-branch"));
13722 else
13723 as_warn (_("constant directive skips -mlfence-before-ret"));
13724 }
13725 else if (lfence_before_indirect_branch != lfence_branch_none)
13726 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
13727 }
13728}
13729
13730void
13731i386_validate_fix (fixS *fixp)
13732{
13733 if (fixp->fx_subsy)
13734 {
13735 if (fixp->fx_subsy == GOT_symbol)
13736 {
13737 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
13738 {
13739 if (!object_64bit)
13740 abort ();
13741#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13742 if (fixp->fx_tcbit2)
13743 fixp->fx_r_type = (fixp->fx_tcbit
13744 ? BFD_RELOC_X86_64_REX_GOTPCRELX
13745 : BFD_RELOC_X86_64_GOTPCRELX);
13746 else
13747#endif
13748 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
13749 }
13750 else
13751 {
13752 if (!object_64bit)
13753 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
13754 else
13755 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
13756 }
13757 fixp->fx_subsy = 0;
13758 }
13759 }
13760#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13761 else if (!object_64bit)
13762 {
13763 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
13764 && fixp->fx_tcbit2)
13765 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
13766 }
13767#endif
13768}
13769
13770arelent *
13771tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
13772{
13773 arelent *rel;
13774 bfd_reloc_code_real_type code;
13775
13776 switch (fixp->fx_r_type)
13777 {
13778#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13779 case BFD_RELOC_SIZE32:
13780 case BFD_RELOC_SIZE64:
13781 if (S_IS_DEFINED (fixp->fx_addsy)
13782 && !S_IS_EXTERNAL (fixp->fx_addsy))
13783 {
13784 /* Resolve size relocation against local symbol to size of
13785 the symbol plus addend. */
13786 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
13787 if (fixp->fx_r_type == BFD_RELOC_SIZE32
13788 && !fits_in_unsigned_long (value))
13789 as_bad_where (fixp->fx_file, fixp->fx_line,
13790 _("symbol size computation overflow"));
13791 fixp->fx_addsy = NULL;
13792 fixp->fx_subsy = NULL;
13793 md_apply_fix (fixp, (valueT *) &value, NULL);
13794 return NULL;
13795 }
13796#endif
13797 /* Fall through. */
13798
13799 case BFD_RELOC_X86_64_PLT32:
13800 case BFD_RELOC_X86_64_GOT32:
13801 case BFD_RELOC_X86_64_GOTPCREL:
13802 case BFD_RELOC_X86_64_GOTPCRELX:
13803 case BFD_RELOC_X86_64_REX_GOTPCRELX:
13804 case BFD_RELOC_386_PLT32:
13805 case BFD_RELOC_386_GOT32:
13806 case BFD_RELOC_386_GOT32X:
13807 case BFD_RELOC_386_GOTOFF:
13808 case BFD_RELOC_386_GOTPC:
13809 case BFD_RELOC_386_TLS_GD:
13810 case BFD_RELOC_386_TLS_LDM:
13811 case BFD_RELOC_386_TLS_LDO_32:
13812 case BFD_RELOC_386_TLS_IE_32:
13813 case BFD_RELOC_386_TLS_IE:
13814 case BFD_RELOC_386_TLS_GOTIE:
13815 case BFD_RELOC_386_TLS_LE_32:
13816 case BFD_RELOC_386_TLS_LE:
13817 case BFD_RELOC_386_TLS_GOTDESC:
13818 case BFD_RELOC_386_TLS_DESC_CALL:
13819 case BFD_RELOC_X86_64_TLSGD:
13820 case BFD_RELOC_X86_64_TLSLD:
13821 case BFD_RELOC_X86_64_DTPOFF32:
13822 case BFD_RELOC_X86_64_DTPOFF64:
13823 case BFD_RELOC_X86_64_GOTTPOFF:
13824 case BFD_RELOC_X86_64_TPOFF32:
13825 case BFD_RELOC_X86_64_TPOFF64:
13826 case BFD_RELOC_X86_64_GOTOFF64:
13827 case BFD_RELOC_X86_64_GOTPC32:
13828 case BFD_RELOC_X86_64_GOT64:
13829 case BFD_RELOC_X86_64_GOTPCREL64:
13830 case BFD_RELOC_X86_64_GOTPC64:
13831 case BFD_RELOC_X86_64_GOTPLT64:
13832 case BFD_RELOC_X86_64_PLTOFF64:
13833 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
13834 case BFD_RELOC_X86_64_TLSDESC_CALL:
13835 case BFD_RELOC_RVA:
13836 case BFD_RELOC_VTABLE_ENTRY:
13837 case BFD_RELOC_VTABLE_INHERIT:
13838#ifdef TE_PE
13839 case BFD_RELOC_32_SECREL:
13840#endif
13841 code = fixp->fx_r_type;
13842 break;
13843 case BFD_RELOC_X86_64_32S:
13844 if (!fixp->fx_pcrel)
13845 {
13846 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
13847 code = fixp->fx_r_type;
13848 break;
13849 }
13850 /* Fall through. */
13851 default:
13852 if (fixp->fx_pcrel)
13853 {
13854 switch (fixp->fx_size)
13855 {
13856 default:
13857 as_bad_where (fixp->fx_file, fixp->fx_line,
13858 _("can not do %d byte pc-relative relocation"),
13859 fixp->fx_size);
13860 code = BFD_RELOC_32_PCREL;
13861 break;
13862 case 1: code = BFD_RELOC_8_PCREL; break;
13863 case 2: code = BFD_RELOC_16_PCREL; break;
13864 case 4: code = BFD_RELOC_32_PCREL; break;
13865#ifdef BFD64
13866 case 8: code = BFD_RELOC_64_PCREL; break;
13867#endif
13868 }
13869 }
13870 else
13871 {
13872 switch (fixp->fx_size)
13873 {
13874 default:
13875 as_bad_where (fixp->fx_file, fixp->fx_line,
13876 _("can not do %d byte relocation"),
13877 fixp->fx_size);
13878 code = BFD_RELOC_32;
13879 break;
13880 case 1: code = BFD_RELOC_8; break;
13881 case 2: code = BFD_RELOC_16; break;
13882 case 4: code = BFD_RELOC_32; break;
13883#ifdef BFD64
13884 case 8: code = BFD_RELOC_64; break;
13885#endif
13886 }
13887 }
13888 break;
13889 }
13890
13891 if ((code == BFD_RELOC_32
13892 || code == BFD_RELOC_32_PCREL
13893 || code == BFD_RELOC_X86_64_32S)
13894 && GOT_symbol
13895 && fixp->fx_addsy == GOT_symbol)
13896 {
13897 if (!object_64bit)
13898 code = BFD_RELOC_386_GOTPC;
13899 else
13900 code = BFD_RELOC_X86_64_GOTPC32;
13901 }
13902 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
13903 && GOT_symbol
13904 && fixp->fx_addsy == GOT_symbol)
13905 {
13906 code = BFD_RELOC_X86_64_GOTPC64;
13907 }
13908
13909 rel = XNEW (arelent);
13910 rel->sym_ptr_ptr = XNEW (asymbol *);
13911 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13912
13913 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
13914
13915 if (!use_rela_relocations)
13916 {
13917 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
13918 vtable entry to be used in the relocation's section offset. */
13919 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13920 rel->address = fixp->fx_offset;
13921#if defined (OBJ_COFF) && defined (TE_PE)
13922 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
13923 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
13924 else
13925#endif
13926 rel->addend = 0;
13927 }
13928 /* Use the rela in 64bit mode. */
13929 else
13930 {
13931 if (disallow_64bit_reloc)
13932 switch (code)
13933 {
13934 case BFD_RELOC_X86_64_DTPOFF64:
13935 case BFD_RELOC_X86_64_TPOFF64:
13936 case BFD_RELOC_64_PCREL:
13937 case BFD_RELOC_X86_64_GOTOFF64:
13938 case BFD_RELOC_X86_64_GOT64:
13939 case BFD_RELOC_X86_64_GOTPCREL64:
13940 case BFD_RELOC_X86_64_GOTPC64:
13941 case BFD_RELOC_X86_64_GOTPLT64:
13942 case BFD_RELOC_X86_64_PLTOFF64:
13943 as_bad_where (fixp->fx_file, fixp->fx_line,
13944 _("cannot represent relocation type %s in x32 mode"),
13945 bfd_get_reloc_code_name (code));
13946 break;
13947 default:
13948 break;
13949 }
13950
13951 if (!fixp->fx_pcrel)
13952 rel->addend = fixp->fx_offset;
13953 else
13954 switch (code)
13955 {
13956 case BFD_RELOC_X86_64_PLT32:
13957 case BFD_RELOC_X86_64_GOT32:
13958 case BFD_RELOC_X86_64_GOTPCREL:
13959 case BFD_RELOC_X86_64_GOTPCRELX:
13960 case BFD_RELOC_X86_64_REX_GOTPCRELX:
13961 case BFD_RELOC_X86_64_TLSGD:
13962 case BFD_RELOC_X86_64_TLSLD:
13963 case BFD_RELOC_X86_64_GOTTPOFF:
13964 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
13965 case BFD_RELOC_X86_64_TLSDESC_CALL:
13966 rel->addend = fixp->fx_offset - fixp->fx_size;
13967 break;
13968 default:
13969 rel->addend = (section->vma
13970 - fixp->fx_size
13971 + fixp->fx_addnumber
13972 + md_pcrel_from (fixp));
13973 break;
13974 }
13975 }
13976
13977 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
13978 if (rel->howto == NULL)
13979 {
13980 as_bad_where (fixp->fx_file, fixp->fx_line,
13981 _("cannot represent relocation type %s"),
13982 bfd_get_reloc_code_name (code));
13983 /* Set howto to a garbage value so that we can keep going. */
13984 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
13985 gas_assert (rel->howto != NULL);
13986 }
13987
13988 return rel;
13989}
13990
13991#include "tc-i386-intel.c"
13992
13993void
13994tc_x86_parse_to_dw2regnum (expressionS *exp)
13995{
13996 int saved_naked_reg;
13997 char saved_register_dot;
13998
13999 saved_naked_reg = allow_naked_reg;
14000 allow_naked_reg = 1;
14001 saved_register_dot = register_chars['.'];
14002 register_chars['.'] = '.';
14003 allow_pseudo_reg = 1;
14004 expression_and_evaluate (exp);
14005 allow_pseudo_reg = 0;
14006 register_chars['.'] = saved_register_dot;
14007 allow_naked_reg = saved_naked_reg;
14008
14009 if (exp->X_op == O_register && exp->X_add_number >= 0)
14010 {
14011 if ((addressT) exp->X_add_number < i386_regtab_size)
14012 {
14013 exp->X_op = O_constant;
14014 exp->X_add_number = i386_regtab[exp->X_add_number]
14015 .dw2_regnum[flag_code >> 1];
14016 }
14017 else
14018 exp->X_op = O_illegal;
14019 }
14020}
14021
14022void
14023tc_x86_frame_initial_instructions (void)
14024{
14025 static unsigned int sp_regno[2];
14026
14027 if (!sp_regno[flag_code >> 1])
14028 {
14029 char *saved_input = input_line_pointer;
14030 char sp[][4] = {"esp", "rsp"};
14031 expressionS exp;
14032
14033 input_line_pointer = sp[flag_code >> 1];
14034 tc_x86_parse_to_dw2regnum (&exp);
14035 gas_assert (exp.X_op == O_constant);
14036 sp_regno[flag_code >> 1] = exp.X_add_number;
14037 input_line_pointer = saved_input;
14038 }
14039
14040 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
14041 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
14042}
14043
14044int
14045x86_dwarf2_addr_size (void)
14046{
14047#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
14048 if (x86_elf_abi == X86_64_X32_ABI)
14049 return 4;
14050#endif
14051 return bfd_arch_bits_per_address (stdoutput) / 8;
14052}
14053
14054int
14055i386_elf_section_type (const char *str, size_t len)
14056{
14057 if (flag_code == CODE_64BIT
14058 && len == sizeof ("unwind") - 1
14059 && strncmp (str, "unwind", 6) == 0)
14060 return SHT_X86_64_UNWIND;
14061
14062 return -1;
14063}
14064
14065#ifdef TE_SOLARIS
14066void
14067i386_solaris_fix_up_eh_frame (segT sec)
14068{
14069 if (flag_code == CODE_64BIT)
14070 elf_section_type (sec) = SHT_X86_64_UNWIND;
14071}
14072#endif
14073
14074#ifdef TE_PE
14075void
14076tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
14077{
14078 expressionS exp;
14079
14080 exp.X_op = O_secrel;
14081 exp.X_add_symbol = symbol;
14082 exp.X_add_number = 0;
14083 emit_expr (&exp, size);
14084}
14085#endif
14086
14087#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14088/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
14089
14090bfd_vma
14091x86_64_section_letter (int letter, const char **ptr_msg)
14092{
14093 if (flag_code == CODE_64BIT)
14094 {
14095 if (letter == 'l')
14096 return SHF_X86_64_LARGE;
14097
14098 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
14099 }
14100 else
14101 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
14102 return -1;
14103}
14104
14105bfd_vma
14106x86_64_section_word (char *str, size_t len)
14107{
14108 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
14109 return SHF_X86_64_LARGE;
14110
14111 return -1;
14112}
14113
14114static void
14115handle_large_common (int small ATTRIBUTE_UNUSED)
14116{
14117 if (flag_code != CODE_64BIT)
14118 {
14119 s_comm_internal (0, elf_common_parse);
14120 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
14121 }
14122 else
14123 {
14124 static segT lbss_section;
14125 asection *saved_com_section_ptr = elf_com_section_ptr;
14126 asection *saved_bss_section = bss_section;
14127
14128 if (lbss_section == NULL)
14129 {
14130 flagword applicable;
14131 segT seg = now_seg;
14132 subsegT subseg = now_subseg;
14133
14134 /* The .lbss section is for local .largecomm symbols. */
14135 lbss_section = subseg_new (".lbss", 0);
14136 applicable = bfd_applicable_section_flags (stdoutput);
14137 bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC);
14138 seg_info (lbss_section)->bss = 1;
14139
14140 subseg_set (seg, subseg);
14141 }
14142
14143 elf_com_section_ptr = &_bfd_elf_large_com_section;
14144 bss_section = lbss_section;
14145
14146 s_comm_internal (0, elf_common_parse);
14147
14148 elf_com_section_ptr = saved_com_section_ptr;
14149 bss_section = saved_bss_section;
14150 }
14151}
14152#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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