| 1 | /* i386.c -- Assemble code for the Intel 80386 |
| 2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GAS, the GNU Assembler. |
| 6 | |
| 7 | GAS is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | GAS is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to the Free |
| 19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA |
| 20 | 02111-1307, USA. */ |
| 21 | |
| 22 | /* Intel 80386 machine specific gas. |
| 23 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). |
| 24 | Bugs & suggestions are completely welcome. This is free software. |
| 25 | Please help us make it better. */ |
| 26 | |
| 27 | #include <ctype.h> |
| 28 | |
| 29 | #include "as.h" |
| 30 | #include "subsegs.h" |
| 31 | #include "dwarf2dbg.h" |
| 32 | #include "opcode/i386.h" |
| 33 | |
| 34 | #ifndef REGISTER_WARNINGS |
| 35 | #define REGISTER_WARNINGS 1 |
| 36 | #endif |
| 37 | |
| 38 | #ifndef INFER_ADDR_PREFIX |
| 39 | #define INFER_ADDR_PREFIX 1 |
| 40 | #endif |
| 41 | |
| 42 | #ifndef SCALE1_WHEN_NO_INDEX |
| 43 | /* Specifying a scale factor besides 1 when there is no index is |
| 44 | futile. eg. `mov (%ebx,2),%al' does exactly the same as |
| 45 | `mov (%ebx),%al'. To slavishly follow what the programmer |
| 46 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ |
| 47 | #define SCALE1_WHEN_NO_INDEX 1 |
| 48 | #endif |
| 49 | |
| 50 | #define true 1 |
| 51 | #define false 0 |
| 52 | |
| 53 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); |
| 54 | static int fits_in_signed_byte PARAMS ((offsetT)); |
| 55 | static int fits_in_unsigned_byte PARAMS ((offsetT)); |
| 56 | static int fits_in_unsigned_word PARAMS ((offsetT)); |
| 57 | static int fits_in_signed_word PARAMS ((offsetT)); |
| 58 | static int smallest_imm_type PARAMS ((offsetT)); |
| 59 | static offsetT offset_in_range PARAMS ((offsetT, int)); |
| 60 | static int add_prefix PARAMS ((unsigned int)); |
| 61 | static void set_16bit_code_flag PARAMS ((int)); |
| 62 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
| 63 | static void set_intel_syntax PARAMS ((int)); |
| 64 | static void set_cpu_arch PARAMS ((int)); |
| 65 | |
| 66 | #ifdef BFD_ASSEMBLER |
| 67 | static bfd_reloc_code_real_type reloc |
| 68 | PARAMS ((int, int, bfd_reloc_code_real_type)); |
| 69 | #endif |
| 70 | |
| 71 | /* 'md_assemble ()' gathers together information and puts it into a |
| 72 | i386_insn. */ |
| 73 | |
| 74 | union i386_op |
| 75 | { |
| 76 | expressionS *disps; |
| 77 | expressionS *imms; |
| 78 | const reg_entry *regs; |
| 79 | }; |
| 80 | |
| 81 | struct _i386_insn |
| 82 | { |
| 83 | /* TM holds the template for the insn were currently assembling. */ |
| 84 | template tm; |
| 85 | |
| 86 | /* SUFFIX holds the instruction mnemonic suffix if given. |
| 87 | (e.g. 'l' for 'movl') */ |
| 88 | char suffix; |
| 89 | |
| 90 | /* OPERANDS gives the number of given operands. */ |
| 91 | unsigned int operands; |
| 92 | |
| 93 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
| 94 | of given register, displacement, memory operands and immediate |
| 95 | operands. */ |
| 96 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
| 97 | |
| 98 | /* TYPES [i] is the type (see above #defines) which tells us how to |
| 99 | use OP[i] for the corresponding operand. */ |
| 100 | unsigned int types[MAX_OPERANDS]; |
| 101 | |
| 102 | /* Displacement expression, immediate expression, or register for each |
| 103 | operand. */ |
| 104 | union i386_op op[MAX_OPERANDS]; |
| 105 | |
| 106 | /* Relocation type for operand */ |
| 107 | #ifdef BFD_ASSEMBLER |
| 108 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; |
| 109 | #else |
| 110 | int disp_reloc[MAX_OPERANDS]; |
| 111 | #endif |
| 112 | |
| 113 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
| 114 | the base index byte below. */ |
| 115 | const reg_entry *base_reg; |
| 116 | const reg_entry *index_reg; |
| 117 | unsigned int log2_scale_factor; |
| 118 | |
| 119 | /* SEG gives the seg_entries of this insn. They are zero unless |
| 120 | explicit segment overrides are given. */ |
| 121 | const seg_entry *seg[2]; |
| 122 | |
| 123 | /* PREFIX holds all the given prefix opcodes (usually null). |
| 124 | PREFIXES is the number of prefix opcodes. */ |
| 125 | unsigned int prefixes; |
| 126 | unsigned char prefix[MAX_PREFIXES]; |
| 127 | |
| 128 | /* RM and SIB are the modrm byte and the sib byte where the |
| 129 | addressing modes of this insn are encoded. */ |
| 130 | |
| 131 | modrm_byte rm; |
| 132 | sib_byte sib; |
| 133 | }; |
| 134 | |
| 135 | typedef struct _i386_insn i386_insn; |
| 136 | |
| 137 | /* List of chars besides those in app.c:symbol_chars that can start an |
| 138 | operand. Used to prevent the scrubber eating vital white-space. */ |
| 139 | #ifdef LEX_AT |
| 140 | const char extra_symbol_chars[] = "*%-(@"; |
| 141 | #else |
| 142 | const char extra_symbol_chars[] = "*%-("; |
| 143 | #endif |
| 144 | |
| 145 | /* This array holds the chars that always start a comment. If the |
| 146 | pre-processor is disabled, these aren't very useful. */ |
| 147 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
| 148 | /* Putting '/' here makes it impossible to use the divide operator. |
| 149 | However, we need it for compatibility with SVR4 systems. */ |
| 150 | const char comment_chars[] = "#/"; |
| 151 | #define PREFIX_SEPARATOR '\\' |
| 152 | #else |
| 153 | const char comment_chars[] = "#"; |
| 154 | #define PREFIX_SEPARATOR '/' |
| 155 | #endif |
| 156 | |
| 157 | /* This array holds the chars that only start a comment at the beginning of |
| 158 | a line. If the line seems to have the form '# 123 filename' |
| 159 | .line and .file directives will appear in the pre-processed output. |
| 160 | Note that input_file.c hand checks for '#' at the beginning of the |
| 161 | first line of the input file. This is because the compiler outputs |
| 162 | #NO_APP at the beginning of its output. |
| 163 | Also note that comments started like this one will always work if |
| 164 | '/' isn't otherwise defined. */ |
| 165 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
| 166 | const char line_comment_chars[] = ""; |
| 167 | #else |
| 168 | const char line_comment_chars[] = "/"; |
| 169 | #endif |
| 170 | |
| 171 | const char line_separator_chars[] = ";"; |
| 172 | |
| 173 | /* Chars that can be used to separate mant from exp in floating point |
| 174 | nums. */ |
| 175 | const char EXP_CHARS[] = "eE"; |
| 176 | |
| 177 | /* Chars that mean this number is a floating point constant |
| 178 | As in 0f12.456 |
| 179 | or 0d1.2345e12. */ |
| 180 | const char FLT_CHARS[] = "fFdDxX"; |
| 181 | |
| 182 | /* Tables for lexical analysis. */ |
| 183 | static char mnemonic_chars[256]; |
| 184 | static char register_chars[256]; |
| 185 | static char operand_chars[256]; |
| 186 | static char identifier_chars[256]; |
| 187 | static char digit_chars[256]; |
| 188 | |
| 189 | /* Lexical macros. */ |
| 190 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
| 191 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
| 192 | #define is_register_char(x) (register_chars[(unsigned char) x]) |
| 193 | #define is_space_char(x) ((x) == ' ') |
| 194 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) |
| 195 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) |
| 196 | |
| 197 | /* All non-digit non-letter charcters that may occur in an operand. */ |
| 198 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
| 199 | |
| 200 | /* md_assemble() always leaves the strings it's passed unaltered. To |
| 201 | effect this we maintain a stack of saved characters that we've smashed |
| 202 | with '\0's (indicating end of strings for various sub-fields of the |
| 203 | assembler instruction). */ |
| 204 | static char save_stack[32]; |
| 205 | static char *save_stack_p; |
| 206 | #define END_STRING_AND_SAVE(s) \ |
| 207 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) |
| 208 | #define RESTORE_END_STRING(s) \ |
| 209 | do { *(s) = *--save_stack_p; } while (0) |
| 210 | |
| 211 | /* The instruction we're assembling. */ |
| 212 | static i386_insn i; |
| 213 | |
| 214 | /* Possible templates for current insn. */ |
| 215 | static const templates *current_templates; |
| 216 | |
| 217 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
| 218 | static expressionS disp_expressions[2], im_expressions[2]; |
| 219 | |
| 220 | /* Current operand we are working on. */ |
| 221 | static int this_operand; |
| 222 | |
| 223 | /* 1 if we're writing 16-bit code, |
| 224 | 0 if 32-bit. */ |
| 225 | static int flag_16bit_code; |
| 226 | |
| 227 | /* 1 for intel syntax, |
| 228 | 0 if att syntax. */ |
| 229 | static int intel_syntax = 0; |
| 230 | |
| 231 | /* 1 if register prefix % not required. */ |
| 232 | static int allow_naked_reg = 0; |
| 233 | |
| 234 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
| 235 | leave, push, and pop instructions so that gcc has the same stack |
| 236 | frame as in 32 bit mode. */ |
| 237 | static char stackop_size = '\0'; |
| 238 | |
| 239 | /* Non-zero to quieten some warnings. */ |
| 240 | static int quiet_warnings = 0; |
| 241 | |
| 242 | /* CPU name. */ |
| 243 | static const char *cpu_arch_name = NULL; |
| 244 | |
| 245 | /* CPU feature flags. */ |
| 246 | static unsigned int cpu_arch_flags = 0; |
| 247 | |
| 248 | /* Interface to relax_segment. |
| 249 | There are 2 relax states for 386 jump insns: one for conditional & |
| 250 | one for unconditional jumps. This is because these two types of |
| 251 | jumps add different sizes to frags when we're figuring out what |
| 252 | sort of jump to choose to reach a given label. */ |
| 253 | |
| 254 | /* Types. */ |
| 255 | #define COND_JUMP 1 |
| 256 | #define UNCOND_JUMP 2 |
| 257 | /* Sizes. */ |
| 258 | #define CODE16 1 |
| 259 | #define SMALL 0 |
| 260 | #define SMALL16 (SMALL|CODE16) |
| 261 | #define BIG 2 |
| 262 | #define BIG16 (BIG|CODE16) |
| 263 | |
| 264 | #ifndef INLINE |
| 265 | #ifdef __GNUC__ |
| 266 | #define INLINE __inline__ |
| 267 | #else |
| 268 | #define INLINE |
| 269 | #endif |
| 270 | #endif |
| 271 | |
| 272 | #define ENCODE_RELAX_STATE(type,size) \ |
| 273 | ((relax_substateT) ((type<<2) | (size))) |
| 274 | #define SIZE_FROM_RELAX_STATE(s) \ |
| 275 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) |
| 276 | |
| 277 | /* This table is used by relax_frag to promote short jumps to long |
| 278 | ones where necessary. SMALL (short) jumps may be promoted to BIG |
| 279 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We |
| 280 | don't allow a short jump in a 32 bit code segment to be promoted to |
| 281 | a 16 bit offset jump because it's slower (requires data size |
| 282 | prefix), and doesn't work, unless the destination is in the bottom |
| 283 | 64k of the code segment (The top 16 bits of eip are zeroed). */ |
| 284 | |
| 285 | const relax_typeS md_relax_table[] = |
| 286 | { |
| 287 | /* The fields are: |
| 288 | 1) most positive reach of this state, |
| 289 | 2) most negative reach of this state, |
| 290 | 3) how many bytes this mode will add to the size of the current frag |
| 291 | 4) which index into the table to try if we can't fit into this one. */ |
| 292 | {1, 1, 0, 0}, |
| 293 | {1, 1, 0, 0}, |
| 294 | {1, 1, 0, 0}, |
| 295 | {1, 1, 0, 0}, |
| 296 | |
| 297 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, |
| 298 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, |
| 299 | /* dword conditionals adds 4 bytes to frag: |
| 300 | 1 extra opcode byte, 3 extra displacement bytes. */ |
| 301 | {0, 0, 4, 0}, |
| 302 | /* word conditionals add 2 bytes to frag: |
| 303 | 1 extra opcode byte, 1 extra displacement byte. */ |
| 304 | {0, 0, 2, 0}, |
| 305 | |
| 306 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
| 307 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, |
| 308 | /* dword jmp adds 3 bytes to frag: |
| 309 | 0 extra opcode bytes, 3 extra displacement bytes. */ |
| 310 | {0, 0, 3, 0}, |
| 311 | /* word jmp adds 1 byte to frag: |
| 312 | 0 extra opcode bytes, 1 extra displacement byte. */ |
| 313 | {0, 0, 1, 0} |
| 314 | |
| 315 | }; |
| 316 | |
| 317 | static const arch_entry cpu_arch[] = { |
| 318 | {"i8086", Cpu086 }, |
| 319 | {"i186", Cpu086|Cpu186 }, |
| 320 | {"i286", Cpu086|Cpu186|Cpu286 }, |
| 321 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, |
| 322 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, |
| 323 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, |
| 324 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, |
| 325 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, |
| 326 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, |
| 327 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow }, |
| 328 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow }, |
| 329 | {NULL, 0 } |
| 330 | }; |
| 331 | |
| 332 | void |
| 333 | i386_align_code (fragP, count) |
| 334 | fragS *fragP; |
| 335 | int count; |
| 336 | { |
| 337 | /* Various efficient no-op patterns for aligning code labels. |
| 338 | Note: Don't try to assemble the instructions in the comments. |
| 339 | 0L and 0w are not legal. */ |
| 340 | static const char f32_1[] = |
| 341 | {0x90}; /* nop */ |
| 342 | static const char f32_2[] = |
| 343 | {0x89,0xf6}; /* movl %esi,%esi */ |
| 344 | static const char f32_3[] = |
| 345 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ |
| 346 | static const char f32_4[] = |
| 347 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
| 348 | static const char f32_5[] = |
| 349 | {0x90, /* nop */ |
| 350 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
| 351 | static const char f32_6[] = |
| 352 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ |
| 353 | static const char f32_7[] = |
| 354 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
| 355 | static const char f32_8[] = |
| 356 | {0x90, /* nop */ |
| 357 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
| 358 | static const char f32_9[] = |
| 359 | {0x89,0xf6, /* movl %esi,%esi */ |
| 360 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 361 | static const char f32_10[] = |
| 362 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ |
| 363 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 364 | static const char f32_11[] = |
| 365 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ |
| 366 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 367 | static const char f32_12[] = |
| 368 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
| 369 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ |
| 370 | static const char f32_13[] = |
| 371 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
| 372 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 373 | static const char f32_14[] = |
| 374 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ |
| 375 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ |
| 376 | static const char f32_15[] = |
| 377 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ |
| 378 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; |
| 379 | static const char f16_3[] = |
| 380 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ |
| 381 | static const char f16_4[] = |
| 382 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
| 383 | static const char f16_5[] = |
| 384 | {0x90, /* nop */ |
| 385 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
| 386 | static const char f16_6[] = |
| 387 | {0x89,0xf6, /* mov %si,%si */ |
| 388 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
| 389 | static const char f16_7[] = |
| 390 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
| 391 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
| 392 | static const char f16_8[] = |
| 393 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
| 394 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
| 395 | static const char *const f32_patt[] = { |
| 396 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, |
| 397 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 |
| 398 | }; |
| 399 | static const char *const f16_patt[] = { |
| 400 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
| 401 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
| 402 | }; |
| 403 | |
| 404 | if (count > 0 && count <= 15) |
| 405 | { |
| 406 | if (flag_16bit_code) |
| 407 | { |
| 408 | memcpy (fragP->fr_literal + fragP->fr_fix, |
| 409 | f16_patt[count - 1], count); |
| 410 | if (count > 8) |
| 411 | /* Adjust jump offset. */ |
| 412 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
| 413 | } |
| 414 | else |
| 415 | memcpy (fragP->fr_literal + fragP->fr_fix, |
| 416 | f32_patt[count - 1], count); |
| 417 | fragP->fr_var = count; |
| 418 | } |
| 419 | } |
| 420 | |
| 421 | static char *output_invalid PARAMS ((int c)); |
| 422 | static int i386_operand PARAMS ((char *operand_string)); |
| 423 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); |
| 424 | static const reg_entry *parse_register PARAMS ((char *reg_string, |
| 425 | char **end_op)); |
| 426 | |
| 427 | #ifndef I386COFF |
| 428 | static void s_bss PARAMS ((int)); |
| 429 | #endif |
| 430 | |
| 431 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
| 432 | |
| 433 | static INLINE unsigned int |
| 434 | mode_from_disp_size (t) |
| 435 | unsigned int t; |
| 436 | { |
| 437 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32)) ? 2 : 0; |
| 438 | } |
| 439 | |
| 440 | static INLINE int |
| 441 | fits_in_signed_byte (num) |
| 442 | offsetT num; |
| 443 | { |
| 444 | return (num >= -128) && (num <= 127); |
| 445 | } |
| 446 | |
| 447 | static INLINE int |
| 448 | fits_in_unsigned_byte (num) |
| 449 | offsetT num; |
| 450 | { |
| 451 | return (num & 0xff) == num; |
| 452 | } |
| 453 | |
| 454 | static INLINE int |
| 455 | fits_in_unsigned_word (num) |
| 456 | offsetT num; |
| 457 | { |
| 458 | return (num & 0xffff) == num; |
| 459 | } |
| 460 | |
| 461 | static INLINE int |
| 462 | fits_in_signed_word (num) |
| 463 | offsetT num; |
| 464 | { |
| 465 | return (-32768 <= num) && (num <= 32767); |
| 466 | } |
| 467 | |
| 468 | static int |
| 469 | smallest_imm_type (num) |
| 470 | offsetT num; |
| 471 | { |
| 472 | if (cpu_arch_flags != 0 |
| 473 | && cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486)) |
| 474 | { |
| 475 | /* This code is disabled on the 486 because all the Imm1 forms |
| 476 | in the opcode table are slower on the i486. They're the |
| 477 | versions with the implicitly specified single-position |
| 478 | displacement, which has another syntax if you really want to |
| 479 | use that form. */ |
| 480 | if (num == 1) |
| 481 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; |
| 482 | } |
| 483 | return (fits_in_signed_byte (num) |
| 484 | ? (Imm8S | Imm8 | Imm16 | Imm32) |
| 485 | : fits_in_unsigned_byte (num) |
| 486 | ? (Imm8 | Imm16 | Imm32) |
| 487 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
| 488 | ? (Imm16 | Imm32) |
| 489 | : (Imm32)); |
| 490 | } |
| 491 | |
| 492 | static offsetT |
| 493 | offset_in_range (val, size) |
| 494 | offsetT val; |
| 495 | int size; |
| 496 | { |
| 497 | addressT mask; |
| 498 | |
| 499 | switch (size) |
| 500 | { |
| 501 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
| 502 | case 2: mask = ((addressT) 1 << 16) - 1; break; |
| 503 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
| 504 | default: abort (); |
| 505 | } |
| 506 | |
| 507 | /* If BFD64, sign extend val. */ |
| 508 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
| 509 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
| 510 | |
| 511 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
| 512 | { |
| 513 | char buf1[40], buf2[40]; |
| 514 | |
| 515 | sprint_value (buf1, val); |
| 516 | sprint_value (buf2, val & mask); |
| 517 | as_warn (_("%s shortened to %s"), buf1, buf2); |
| 518 | } |
| 519 | return val & mask; |
| 520 | } |
| 521 | |
| 522 | /* Returns 0 if attempting to add a prefix where one from the same |
| 523 | class already exists, 1 if non rep/repne added, 2 if rep/repne |
| 524 | added. */ |
| 525 | static int |
| 526 | add_prefix (prefix) |
| 527 | unsigned int prefix; |
| 528 | { |
| 529 | int ret = 1; |
| 530 | int q; |
| 531 | |
| 532 | switch (prefix) |
| 533 | { |
| 534 | default: |
| 535 | abort (); |
| 536 | |
| 537 | case CS_PREFIX_OPCODE: |
| 538 | case DS_PREFIX_OPCODE: |
| 539 | case ES_PREFIX_OPCODE: |
| 540 | case FS_PREFIX_OPCODE: |
| 541 | case GS_PREFIX_OPCODE: |
| 542 | case SS_PREFIX_OPCODE: |
| 543 | q = SEG_PREFIX; |
| 544 | break; |
| 545 | |
| 546 | case REPNE_PREFIX_OPCODE: |
| 547 | case REPE_PREFIX_OPCODE: |
| 548 | ret = 2; |
| 549 | /* fall thru */ |
| 550 | case LOCK_PREFIX_OPCODE: |
| 551 | q = LOCKREP_PREFIX; |
| 552 | break; |
| 553 | |
| 554 | case FWAIT_OPCODE: |
| 555 | q = WAIT_PREFIX; |
| 556 | break; |
| 557 | |
| 558 | case ADDR_PREFIX_OPCODE: |
| 559 | q = ADDR_PREFIX; |
| 560 | break; |
| 561 | |
| 562 | case DATA_PREFIX_OPCODE: |
| 563 | q = DATA_PREFIX; |
| 564 | break; |
| 565 | } |
| 566 | |
| 567 | if (i.prefix[q]) |
| 568 | { |
| 569 | as_bad (_("same type of prefix used twice")); |
| 570 | return 0; |
| 571 | } |
| 572 | |
| 573 | i.prefixes += 1; |
| 574 | i.prefix[q] = prefix; |
| 575 | return ret; |
| 576 | } |
| 577 | |
| 578 | static void |
| 579 | set_16bit_code_flag (new_16bit_code_flag) |
| 580 | int new_16bit_code_flag; |
| 581 | { |
| 582 | flag_16bit_code = new_16bit_code_flag; |
| 583 | stackop_size = '\0'; |
| 584 | } |
| 585 | |
| 586 | static void |
| 587 | set_16bit_gcc_code_flag (new_16bit_code_flag) |
| 588 | int new_16bit_code_flag; |
| 589 | { |
| 590 | flag_16bit_code = new_16bit_code_flag; |
| 591 | stackop_size = new_16bit_code_flag ? 'l' : '\0'; |
| 592 | } |
| 593 | |
| 594 | static void |
| 595 | set_intel_syntax (syntax_flag) |
| 596 | int syntax_flag; |
| 597 | { |
| 598 | /* Find out if register prefixing is specified. */ |
| 599 | int ask_naked_reg = 0; |
| 600 | |
| 601 | SKIP_WHITESPACE (); |
| 602 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 603 | { |
| 604 | char *string = input_line_pointer; |
| 605 | int e = get_symbol_end (); |
| 606 | |
| 607 | if (strcmp (string, "prefix") == 0) |
| 608 | ask_naked_reg = 1; |
| 609 | else if (strcmp (string, "noprefix") == 0) |
| 610 | ask_naked_reg = -1; |
| 611 | else |
| 612 | as_bad (_("bad argument to syntax directive.")); |
| 613 | *input_line_pointer = e; |
| 614 | } |
| 615 | demand_empty_rest_of_line (); |
| 616 | |
| 617 | intel_syntax = syntax_flag; |
| 618 | |
| 619 | if (ask_naked_reg == 0) |
| 620 | { |
| 621 | #ifdef BFD_ASSEMBLER |
| 622 | allow_naked_reg = (intel_syntax |
| 623 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
| 624 | #else |
| 625 | /* Conservative default. */ |
| 626 | allow_naked_reg = 0; |
| 627 | #endif |
| 628 | } |
| 629 | else |
| 630 | allow_naked_reg = (ask_naked_reg < 0); |
| 631 | } |
| 632 | |
| 633 | static void |
| 634 | set_cpu_arch (dummy) |
| 635 | int dummy ATTRIBUTE_UNUSED; |
| 636 | { |
| 637 | SKIP_WHITESPACE (); |
| 638 | |
| 639 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 640 | { |
| 641 | char *string = input_line_pointer; |
| 642 | int e = get_symbol_end (); |
| 643 | int i; |
| 644 | |
| 645 | for (i = 0; cpu_arch[i].name; i++) |
| 646 | { |
| 647 | if (strcmp (string, cpu_arch[i].name) == 0) |
| 648 | { |
| 649 | cpu_arch_name = cpu_arch[i].name; |
| 650 | cpu_arch_flags = cpu_arch[i].flags; |
| 651 | break; |
| 652 | } |
| 653 | } |
| 654 | if (!cpu_arch[i].name) |
| 655 | as_bad (_("no such architecture: `%s'"), string); |
| 656 | |
| 657 | *input_line_pointer = e; |
| 658 | } |
| 659 | else |
| 660 | as_bad (_("missing cpu architecture")); |
| 661 | |
| 662 | demand_empty_rest_of_line (); |
| 663 | } |
| 664 | |
| 665 | const pseudo_typeS md_pseudo_table[] = |
| 666 | { |
| 667 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
| 668 | {"align", s_align_bytes, 0}, |
| 669 | #else |
| 670 | {"align", s_align_ptwo, 0}, |
| 671 | #endif |
| 672 | {"arch", set_cpu_arch, 0}, |
| 673 | #ifndef I386COFF |
| 674 | {"bss", s_bss, 0}, |
| 675 | #endif |
| 676 | {"ffloat", float_cons, 'f'}, |
| 677 | {"dfloat", float_cons, 'd'}, |
| 678 | {"tfloat", float_cons, 'x'}, |
| 679 | {"value", cons, 2}, |
| 680 | {"noopt", s_ignore, 0}, |
| 681 | {"optim", s_ignore, 0}, |
| 682 | {"code16gcc", set_16bit_gcc_code_flag, 1}, |
| 683 | {"code16", set_16bit_code_flag, 1}, |
| 684 | {"code32", set_16bit_code_flag, 0}, |
| 685 | {"intel_syntax", set_intel_syntax, 1}, |
| 686 | {"att_syntax", set_intel_syntax, 0}, |
| 687 | {"file", dwarf2_directive_file, 0}, |
| 688 | {"loc", dwarf2_directive_loc, 0}, |
| 689 | {0, 0, 0} |
| 690 | }; |
| 691 | |
| 692 | /* For interface with expression (). */ |
| 693 | extern char *input_line_pointer; |
| 694 | |
| 695 | /* Hash table for instruction mnemonic lookup. */ |
| 696 | static struct hash_control *op_hash; |
| 697 | |
| 698 | /* Hash table for register lookup. */ |
| 699 | static struct hash_control *reg_hash; |
| 700 | \f |
| 701 | void |
| 702 | md_begin () |
| 703 | { |
| 704 | const char *hash_err; |
| 705 | |
| 706 | /* Initialize op_hash hash table. */ |
| 707 | op_hash = hash_new (); |
| 708 | |
| 709 | { |
| 710 | register const template *optab; |
| 711 | register templates *core_optab; |
| 712 | |
| 713 | /* Setup for loop. */ |
| 714 | optab = i386_optab; |
| 715 | core_optab = (templates *) xmalloc (sizeof (templates)); |
| 716 | core_optab->start = optab; |
| 717 | |
| 718 | while (1) |
| 719 | { |
| 720 | ++optab; |
| 721 | if (optab->name == NULL |
| 722 | || strcmp (optab->name, (optab - 1)->name) != 0) |
| 723 | { |
| 724 | /* different name --> ship out current template list; |
| 725 | add to hash table; & begin anew. */ |
| 726 | core_optab->end = optab; |
| 727 | hash_err = hash_insert (op_hash, |
| 728 | (optab - 1)->name, |
| 729 | (PTR) core_optab); |
| 730 | if (hash_err) |
| 731 | { |
| 732 | hash_error: |
| 733 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
| 734 | (optab - 1)->name, |
| 735 | hash_err); |
| 736 | } |
| 737 | if (optab->name == NULL) |
| 738 | break; |
| 739 | core_optab = (templates *) xmalloc (sizeof (templates)); |
| 740 | core_optab->start = optab; |
| 741 | } |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | /* Initialize reg_hash hash table. */ |
| 746 | reg_hash = hash_new (); |
| 747 | { |
| 748 | register const reg_entry *regtab; |
| 749 | |
| 750 | for (regtab = i386_regtab; |
| 751 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); |
| 752 | regtab++) |
| 753 | { |
| 754 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); |
| 755 | if (hash_err) |
| 756 | goto hash_error; |
| 757 | } |
| 758 | } |
| 759 | |
| 760 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
| 761 | { |
| 762 | register int c; |
| 763 | register char *p; |
| 764 | |
| 765 | for (c = 0; c < 256; c++) |
| 766 | { |
| 767 | if (isdigit (c)) |
| 768 | { |
| 769 | digit_chars[c] = c; |
| 770 | mnemonic_chars[c] = c; |
| 771 | register_chars[c] = c; |
| 772 | operand_chars[c] = c; |
| 773 | } |
| 774 | else if (islower (c)) |
| 775 | { |
| 776 | mnemonic_chars[c] = c; |
| 777 | register_chars[c] = c; |
| 778 | operand_chars[c] = c; |
| 779 | } |
| 780 | else if (isupper (c)) |
| 781 | { |
| 782 | mnemonic_chars[c] = tolower (c); |
| 783 | register_chars[c] = mnemonic_chars[c]; |
| 784 | operand_chars[c] = c; |
| 785 | } |
| 786 | |
| 787 | if (isalpha (c) || isdigit (c)) |
| 788 | identifier_chars[c] = c; |
| 789 | else if (c >= 128) |
| 790 | { |
| 791 | identifier_chars[c] = c; |
| 792 | operand_chars[c] = c; |
| 793 | } |
| 794 | } |
| 795 | |
| 796 | #ifdef LEX_AT |
| 797 | identifier_chars['@'] = '@'; |
| 798 | #endif |
| 799 | digit_chars['-'] = '-'; |
| 800 | identifier_chars['_'] = '_'; |
| 801 | identifier_chars['.'] = '.'; |
| 802 | |
| 803 | for (p = operand_special_chars; *p != '\0'; p++) |
| 804 | operand_chars[(unsigned char) *p] = *p; |
| 805 | } |
| 806 | |
| 807 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 808 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 809 | { |
| 810 | record_alignment (text_section, 2); |
| 811 | record_alignment (data_section, 2); |
| 812 | record_alignment (bss_section, 2); |
| 813 | } |
| 814 | #endif |
| 815 | } |
| 816 | |
| 817 | void |
| 818 | i386_print_statistics (file) |
| 819 | FILE *file; |
| 820 | { |
| 821 | hash_print_statistics (file, "i386 opcode", op_hash); |
| 822 | hash_print_statistics (file, "i386 register", reg_hash); |
| 823 | } |
| 824 | \f |
| 825 | #ifdef DEBUG386 |
| 826 | |
| 827 | /* Debugging routines for md_assemble. */ |
| 828 | static void pi PARAMS ((char *, i386_insn *)); |
| 829 | static void pte PARAMS ((template *)); |
| 830 | static void pt PARAMS ((unsigned int)); |
| 831 | static void pe PARAMS ((expressionS *)); |
| 832 | static void ps PARAMS ((symbolS *)); |
| 833 | |
| 834 | static void |
| 835 | pi (line, x) |
| 836 | char *line; |
| 837 | i386_insn *x; |
| 838 | { |
| 839 | register template *p; |
| 840 | int i; |
| 841 | |
| 842 | fprintf (stdout, "%s: template ", line); |
| 843 | pte (&x->tm); |
| 844 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", |
| 845 | x->rm.mode, x->rm.reg, x->rm.regmem); |
| 846 | fprintf (stdout, " base %x index %x scale %x\n", |
| 847 | x->bi.base, x->bi.index, x->bi.scale); |
| 848 | for (i = 0; i < x->operands; i++) |
| 849 | { |
| 850 | fprintf (stdout, " #%d: ", i + 1); |
| 851 | pt (x->types[i]); |
| 852 | fprintf (stdout, "\n"); |
| 853 | if (x->types[i] |
| 854 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
| 855 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
| 856 | if (x->types[i] & Imm) |
| 857 | pe (x->op[i].imms); |
| 858 | if (x->types[i] & Disp) |
| 859 | pe (x->op[i].disps); |
| 860 | } |
| 861 | } |
| 862 | |
| 863 | static void |
| 864 | pte (t) |
| 865 | template *t; |
| 866 | { |
| 867 | int i; |
| 868 | fprintf (stdout, " %d operands ", t->operands); |
| 869 | fprintf (stdout, "opcode %x ", t->base_opcode); |
| 870 | if (t->extension_opcode != None) |
| 871 | fprintf (stdout, "ext %x ", t->extension_opcode); |
| 872 | if (t->opcode_modifier & D) |
| 873 | fprintf (stdout, "D"); |
| 874 | if (t->opcode_modifier & W) |
| 875 | fprintf (stdout, "W"); |
| 876 | fprintf (stdout, "\n"); |
| 877 | for (i = 0; i < t->operands; i++) |
| 878 | { |
| 879 | fprintf (stdout, " #%d type ", i + 1); |
| 880 | pt (t->operand_types[i]); |
| 881 | fprintf (stdout, "\n"); |
| 882 | } |
| 883 | } |
| 884 | |
| 885 | static void |
| 886 | pe (e) |
| 887 | expressionS *e; |
| 888 | { |
| 889 | fprintf (stdout, " operation %d\n", e->X_op); |
| 890 | fprintf (stdout, " add_number %ld (%lx)\n", |
| 891 | (long) e->X_add_number, (long) e->X_add_number); |
| 892 | if (e->X_add_symbol) |
| 893 | { |
| 894 | fprintf (stdout, " add_symbol "); |
| 895 | ps (e->X_add_symbol); |
| 896 | fprintf (stdout, "\n"); |
| 897 | } |
| 898 | if (e->X_op_symbol) |
| 899 | { |
| 900 | fprintf (stdout, " op_symbol "); |
| 901 | ps (e->X_op_symbol); |
| 902 | fprintf (stdout, "\n"); |
| 903 | } |
| 904 | } |
| 905 | |
| 906 | static void |
| 907 | ps (s) |
| 908 | symbolS *s; |
| 909 | { |
| 910 | fprintf (stdout, "%s type %s%s", |
| 911 | S_GET_NAME (s), |
| 912 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", |
| 913 | segment_name (S_GET_SEGMENT (s))); |
| 914 | } |
| 915 | |
| 916 | struct type_name |
| 917 | { |
| 918 | unsigned int mask; |
| 919 | char *tname; |
| 920 | } |
| 921 | |
| 922 | type_names[] = |
| 923 | { |
| 924 | { Reg8, "r8" }, |
| 925 | { Reg16, "r16" }, |
| 926 | { Reg32, "r32" }, |
| 927 | { Imm8, "i8" }, |
| 928 | { Imm8S, "i8s" }, |
| 929 | { Imm16, "i16" }, |
| 930 | { Imm32, "i32" }, |
| 931 | { Imm1, "i1" }, |
| 932 | { BaseIndex, "BaseIndex" }, |
| 933 | { Disp8, "d8" }, |
| 934 | { Disp16, "d16" }, |
| 935 | { Disp32, "d32" }, |
| 936 | { InOutPortReg, "InOutPortReg" }, |
| 937 | { ShiftCount, "ShiftCount" }, |
| 938 | { Control, "control reg" }, |
| 939 | { Test, "test reg" }, |
| 940 | { Debug, "debug reg" }, |
| 941 | { FloatReg, "FReg" }, |
| 942 | { FloatAcc, "FAcc" }, |
| 943 | { SReg2, "SReg2" }, |
| 944 | { SReg3, "SReg3" }, |
| 945 | { Acc, "Acc" }, |
| 946 | { JumpAbsolute, "Jump Absolute" }, |
| 947 | { RegMMX, "rMMX" }, |
| 948 | { RegXMM, "rXMM" }, |
| 949 | { EsSeg, "es" }, |
| 950 | { 0, "" } |
| 951 | }; |
| 952 | |
| 953 | static void |
| 954 | pt (t) |
| 955 | unsigned int t; |
| 956 | { |
| 957 | register struct type_name *ty; |
| 958 | |
| 959 | if (t == Unknown) |
| 960 | { |
| 961 | fprintf (stdout, _("Unknown")); |
| 962 | } |
| 963 | else |
| 964 | { |
| 965 | for (ty = type_names; ty->mask; ty++) |
| 966 | if (t & ty->mask) |
| 967 | fprintf (stdout, "%s, ", ty->tname); |
| 968 | } |
| 969 | fflush (stdout); |
| 970 | } |
| 971 | |
| 972 | #endif /* DEBUG386 */ |
| 973 | \f |
| 974 | int |
| 975 | tc_i386_force_relocation (fixp) |
| 976 | struct fix *fixp; |
| 977 | { |
| 978 | #ifdef BFD_ASSEMBLER |
| 979 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 980 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 981 | return 1; |
| 982 | return 0; |
| 983 | #else |
| 984 | /* For COFF. */ |
| 985 | return fixp->fx_r_type == 7; |
| 986 | #endif |
| 987 | } |
| 988 | |
| 989 | #ifdef BFD_ASSEMBLER |
| 990 | static bfd_reloc_code_real_type reloc |
| 991 | PARAMS ((int, int, bfd_reloc_code_real_type)); |
| 992 | |
| 993 | static bfd_reloc_code_real_type |
| 994 | reloc (size, pcrel, other) |
| 995 | int size; |
| 996 | int pcrel; |
| 997 | bfd_reloc_code_real_type other; |
| 998 | { |
| 999 | if (other != NO_RELOC) |
| 1000 | return other; |
| 1001 | |
| 1002 | if (pcrel) |
| 1003 | { |
| 1004 | switch (size) |
| 1005 | { |
| 1006 | case 1: return BFD_RELOC_8_PCREL; |
| 1007 | case 2: return BFD_RELOC_16_PCREL; |
| 1008 | case 4: return BFD_RELOC_32_PCREL; |
| 1009 | } |
| 1010 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
| 1011 | } |
| 1012 | else |
| 1013 | { |
| 1014 | switch (size) |
| 1015 | { |
| 1016 | case 1: return BFD_RELOC_8; |
| 1017 | case 2: return BFD_RELOC_16; |
| 1018 | case 4: return BFD_RELOC_32; |
| 1019 | } |
| 1020 | as_bad (_("can not do %d byte relocation"), size); |
| 1021 | } |
| 1022 | |
| 1023 | return BFD_RELOC_NONE; |
| 1024 | } |
| 1025 | |
| 1026 | /* Here we decide which fixups can be adjusted to make them relative to |
| 1027 | the beginning of the section instead of the symbol. Basically we need |
| 1028 | to make sure that the dynamic relocations are done correctly, so in |
| 1029 | some cases we force the original symbol to be used. */ |
| 1030 | |
| 1031 | int |
| 1032 | tc_i386_fix_adjustable (fixP) |
| 1033 | fixS *fixP; |
| 1034 | { |
| 1035 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 1036 | /* Prevent all adjustments to global symbols, or else dynamic |
| 1037 | linking will not work correctly. */ |
| 1038 | if (S_IS_EXTERNAL (fixP->fx_addsy) |
| 1039 | || S_IS_WEAK (fixP->fx_addsy)) |
| 1040 | return 0; |
| 1041 | #endif |
| 1042 | /* adjust_reloc_syms doesn't know about the GOT. */ |
| 1043 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
| 1044 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
| 1045 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
| 1046 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 1047 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 1048 | return 0; |
| 1049 | return 1; |
| 1050 | } |
| 1051 | #else |
| 1052 | #define reloc(SIZE,PCREL,OTHER) 0 |
| 1053 | #define BFD_RELOC_16 0 |
| 1054 | #define BFD_RELOC_32 0 |
| 1055 | #define BFD_RELOC_16_PCREL 0 |
| 1056 | #define BFD_RELOC_32_PCREL 0 |
| 1057 | #define BFD_RELOC_386_PLT32 0 |
| 1058 | #define BFD_RELOC_386_GOT32 0 |
| 1059 | #define BFD_RELOC_386_GOTOFF 0 |
| 1060 | #endif |
| 1061 | |
| 1062 | static int intel_float_operand PARAMS ((char *mnemonic)); |
| 1063 | |
| 1064 | static int |
| 1065 | intel_float_operand (mnemonic) |
| 1066 | char *mnemonic; |
| 1067 | { |
| 1068 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
| 1069 | return 2; |
| 1070 | |
| 1071 | if (mnemonic[0] == 'f') |
| 1072 | return 1; |
| 1073 | |
| 1074 | return 0; |
| 1075 | } |
| 1076 | |
| 1077 | /* This is the guts of the machine-dependent assembler. LINE points to a |
| 1078 | machine dependent instruction. This function is supposed to emit |
| 1079 | the frags/bytes it assembles to. */ |
| 1080 | |
| 1081 | void |
| 1082 | md_assemble (line) |
| 1083 | char *line; |
| 1084 | { |
| 1085 | /* Points to template once we've found it. */ |
| 1086 | const template *t; |
| 1087 | |
| 1088 | /* Count the size of the instruction generated. */ |
| 1089 | int insn_size = 0; |
| 1090 | |
| 1091 | int j; |
| 1092 | |
| 1093 | char mnemonic[MAX_MNEM_SIZE]; |
| 1094 | |
| 1095 | /* Initialize globals. */ |
| 1096 | memset (&i, '\0', sizeof (i)); |
| 1097 | for (j = 0; j < MAX_OPERANDS; j++) |
| 1098 | i.disp_reloc[j] = NO_RELOC; |
| 1099 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
| 1100 | memset (im_expressions, '\0', sizeof (im_expressions)); |
| 1101 | save_stack_p = save_stack; |
| 1102 | |
| 1103 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
| 1104 | We assume that the scrubber has arranged it so that line[0] is the valid |
| 1105 | start of a (possibly prefixed) mnemonic. */ |
| 1106 | { |
| 1107 | char *l = line; |
| 1108 | char *token_start = l; |
| 1109 | char *mnem_p; |
| 1110 | |
| 1111 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
| 1112 | const char *expecting_string_instruction = NULL; |
| 1113 | |
| 1114 | while (1) |
| 1115 | { |
| 1116 | mnem_p = mnemonic; |
| 1117 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) |
| 1118 | { |
| 1119 | mnem_p++; |
| 1120 | if (mnem_p >= mnemonic + sizeof (mnemonic)) |
| 1121 | { |
| 1122 | as_bad (_("no such instruction: `%s'"), token_start); |
| 1123 | return; |
| 1124 | } |
| 1125 | l++; |
| 1126 | } |
| 1127 | if (!is_space_char (*l) |
| 1128 | && *l != END_OF_INSN |
| 1129 | && *l != PREFIX_SEPARATOR) |
| 1130 | { |
| 1131 | as_bad (_("invalid character %s in mnemonic"), |
| 1132 | output_invalid (*l)); |
| 1133 | return; |
| 1134 | } |
| 1135 | if (token_start == l) |
| 1136 | { |
| 1137 | if (*l == PREFIX_SEPARATOR) |
| 1138 | as_bad (_("expecting prefix; got nothing")); |
| 1139 | else |
| 1140 | as_bad (_("expecting mnemonic; got nothing")); |
| 1141 | return; |
| 1142 | } |
| 1143 | |
| 1144 | /* Look up instruction (or prefix) via hash table. */ |
| 1145 | current_templates = hash_find (op_hash, mnemonic); |
| 1146 | |
| 1147 | if (*l != END_OF_INSN |
| 1148 | && (! is_space_char (*l) || l[1] != END_OF_INSN) |
| 1149 | && current_templates |
| 1150 | && (current_templates->start->opcode_modifier & IsPrefix)) |
| 1151 | { |
| 1152 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
| 1153 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ |
| 1154 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) |
| 1155 | && (((current_templates->start->opcode_modifier & Size32) != 0) |
| 1156 | ^ flag_16bit_code)) |
| 1157 | { |
| 1158 | as_bad (_("redundant %s prefix"), |
| 1159 | current_templates->start->name); |
| 1160 | return; |
| 1161 | } |
| 1162 | /* Add prefix, checking for repeated prefixes. */ |
| 1163 | switch (add_prefix (current_templates->start->base_opcode)) |
| 1164 | { |
| 1165 | case 0: |
| 1166 | return; |
| 1167 | case 2: |
| 1168 | expecting_string_instruction = current_templates->start->name; |
| 1169 | break; |
| 1170 | } |
| 1171 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
| 1172 | token_start = ++l; |
| 1173 | } |
| 1174 | else |
| 1175 | break; |
| 1176 | } |
| 1177 | |
| 1178 | if (!current_templates) |
| 1179 | { |
| 1180 | /* See if we can get a match by trimming off a suffix. */ |
| 1181 | switch (mnem_p[-1]) |
| 1182 | { |
| 1183 | case WORD_MNEM_SUFFIX: |
| 1184 | case BYTE_MNEM_SUFFIX: |
| 1185 | case SHORT_MNEM_SUFFIX: |
| 1186 | case LONG_MNEM_SUFFIX: |
| 1187 | i.suffix = mnem_p[-1]; |
| 1188 | mnem_p[-1] = '\0'; |
| 1189 | current_templates = hash_find (op_hash, mnemonic); |
| 1190 | break; |
| 1191 | |
| 1192 | /* Intel Syntax. */ |
| 1193 | case DWORD_MNEM_SUFFIX: |
| 1194 | if (intel_syntax) |
| 1195 | { |
| 1196 | i.suffix = mnem_p[-1]; |
| 1197 | mnem_p[-1] = '\0'; |
| 1198 | current_templates = hash_find (op_hash, mnemonic); |
| 1199 | break; |
| 1200 | } |
| 1201 | } |
| 1202 | if (!current_templates) |
| 1203 | { |
| 1204 | as_bad (_("no such instruction: `%s'"), token_start); |
| 1205 | return; |
| 1206 | } |
| 1207 | } |
| 1208 | |
| 1209 | /* Check if instruction is supported on specified architecture. */ |
| 1210 | if (cpu_arch_flags != 0) |
| 1211 | { |
| 1212 | if (current_templates->start->cpu_flags & ~cpu_arch_flags) |
| 1213 | { |
| 1214 | as_warn (_("`%s' is not supported on `%s'"), |
| 1215 | current_templates->start->name, cpu_arch_name); |
| 1216 | } |
| 1217 | else if ((Cpu386 & ~cpu_arch_flags) && !flag_16bit_code) |
| 1218 | { |
| 1219 | as_warn (_("use .code16 to ensure correct addressing mode")); |
| 1220 | } |
| 1221 | } |
| 1222 | |
| 1223 | /* Check for rep/repne without a string instruction. */ |
| 1224 | if (expecting_string_instruction |
| 1225 | && !(current_templates->start->opcode_modifier & IsString)) |
| 1226 | { |
| 1227 | as_bad (_("expecting string instruction after `%s'"), |
| 1228 | expecting_string_instruction); |
| 1229 | return; |
| 1230 | } |
| 1231 | |
| 1232 | /* There may be operands to parse. */ |
| 1233 | if (*l != END_OF_INSN) |
| 1234 | { |
| 1235 | /* 1 if operand is pending after ','. */ |
| 1236 | unsigned int expecting_operand = 0; |
| 1237 | |
| 1238 | /* Non-zero if operand parens not balanced. */ |
| 1239 | unsigned int paren_not_balanced; |
| 1240 | |
| 1241 | do |
| 1242 | { |
| 1243 | /* Skip optional white space before operand. */ |
| 1244 | if (is_space_char (*l)) |
| 1245 | ++l; |
| 1246 | if (!is_operand_char (*l) && *l != END_OF_INSN) |
| 1247 | { |
| 1248 | as_bad (_("invalid character %s before operand %d"), |
| 1249 | output_invalid (*l), |
| 1250 | i.operands + 1); |
| 1251 | return; |
| 1252 | } |
| 1253 | token_start = l; /* after white space */ |
| 1254 | paren_not_balanced = 0; |
| 1255 | while (paren_not_balanced || *l != ',') |
| 1256 | { |
| 1257 | if (*l == END_OF_INSN) |
| 1258 | { |
| 1259 | if (paren_not_balanced) |
| 1260 | { |
| 1261 | if (!intel_syntax) |
| 1262 | as_bad (_("unbalanced parenthesis in operand %d."), |
| 1263 | i.operands + 1); |
| 1264 | else |
| 1265 | as_bad (_("unbalanced brackets in operand %d."), |
| 1266 | i.operands + 1); |
| 1267 | return; |
| 1268 | } |
| 1269 | else |
| 1270 | break; /* we are done */ |
| 1271 | } |
| 1272 | else if (!is_operand_char (*l) && !is_space_char (*l)) |
| 1273 | { |
| 1274 | as_bad (_("invalid character %s in operand %d"), |
| 1275 | output_invalid (*l), |
| 1276 | i.operands + 1); |
| 1277 | return; |
| 1278 | } |
| 1279 | if (!intel_syntax) |
| 1280 | { |
| 1281 | if (*l == '(') |
| 1282 | ++paren_not_balanced; |
| 1283 | if (*l == ')') |
| 1284 | --paren_not_balanced; |
| 1285 | } |
| 1286 | else |
| 1287 | { |
| 1288 | if (*l == '[') |
| 1289 | ++paren_not_balanced; |
| 1290 | if (*l == ']') |
| 1291 | --paren_not_balanced; |
| 1292 | } |
| 1293 | l++; |
| 1294 | } |
| 1295 | if (l != token_start) |
| 1296 | { /* Yes, we've read in another operand. */ |
| 1297 | unsigned int operand_ok; |
| 1298 | this_operand = i.operands++; |
| 1299 | if (i.operands > MAX_OPERANDS) |
| 1300 | { |
| 1301 | as_bad (_("spurious operands; (%d operands/instruction max)"), |
| 1302 | MAX_OPERANDS); |
| 1303 | return; |
| 1304 | } |
| 1305 | /* Now parse operand adding info to 'i' as we go along. */ |
| 1306 | END_STRING_AND_SAVE (l); |
| 1307 | |
| 1308 | if (intel_syntax) |
| 1309 | operand_ok = |
| 1310 | i386_intel_operand (token_start, |
| 1311 | intel_float_operand (mnemonic)); |
| 1312 | else |
| 1313 | operand_ok = i386_operand (token_start); |
| 1314 | |
| 1315 | RESTORE_END_STRING (l); |
| 1316 | if (!operand_ok) |
| 1317 | return; |
| 1318 | } |
| 1319 | else |
| 1320 | { |
| 1321 | if (expecting_operand) |
| 1322 | { |
| 1323 | expecting_operand_after_comma: |
| 1324 | as_bad (_("expecting operand after ','; got nothing")); |
| 1325 | return; |
| 1326 | } |
| 1327 | if (*l == ',') |
| 1328 | { |
| 1329 | as_bad (_("expecting operand before ','; got nothing")); |
| 1330 | return; |
| 1331 | } |
| 1332 | } |
| 1333 | |
| 1334 | /* Now *l must be either ',' or END_OF_INSN. */ |
| 1335 | if (*l == ',') |
| 1336 | { |
| 1337 | if (*++l == END_OF_INSN) |
| 1338 | { |
| 1339 | /* Just skip it, if it's \n complain. */ |
| 1340 | goto expecting_operand_after_comma; |
| 1341 | } |
| 1342 | expecting_operand = 1; |
| 1343 | } |
| 1344 | } |
| 1345 | while (*l != END_OF_INSN); |
| 1346 | } |
| 1347 | } |
| 1348 | |
| 1349 | /* Now we've parsed the mnemonic into a set of templates, and have the |
| 1350 | operands at hand. |
| 1351 | |
| 1352 | Next, we find a template that matches the given insn, |
| 1353 | making sure the overlap of the given operands types is consistent |
| 1354 | with the template operand types. */ |
| 1355 | |
| 1356 | #define MATCH(overlap, given, template) \ |
| 1357 | ((overlap & ~JumpAbsolute) \ |
| 1358 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) |
| 1359 | |
| 1360 | /* If given types r0 and r1 are registers they must be of the same type |
| 1361 | unless the expected operand type register overlap is null. |
| 1362 | Note that Acc in a template matches every size of reg. */ |
| 1363 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ |
| 1364 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ |
| 1365 | ((g0) & Reg) == ((g1) & Reg) || \ |
| 1366 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) |
| 1367 | |
| 1368 | { |
| 1369 | register unsigned int overlap0, overlap1; |
| 1370 | unsigned int overlap2; |
| 1371 | unsigned int found_reverse_match; |
| 1372 | int suffix_check; |
| 1373 | |
| 1374 | /* All intel opcodes have reversed operands except for "bound" and |
| 1375 | "enter". We also don't reverse intersegment "jmp" and "call" |
| 1376 | instructions with 2 immediate operands so that the immediate segment |
| 1377 | precedes the offset, as it does when in AT&T mode. "enter" and the |
| 1378 | intersegment "jmp" and "call" instructions are the only ones that |
| 1379 | have two immediate operands. */ |
| 1380 | if (intel_syntax && i.operands > 1 |
| 1381 | && (strcmp (mnemonic, "bound") != 0) |
| 1382 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) |
| 1383 | { |
| 1384 | union i386_op temp_op; |
| 1385 | unsigned int temp_type; |
| 1386 | #ifdef BFD_ASSEMBLER |
| 1387 | enum bfd_reloc_code_real temp_disp_reloc; |
| 1388 | #else |
| 1389 | int temp_disp_reloc; |
| 1390 | #endif |
| 1391 | int xchg1 = 0; |
| 1392 | int xchg2 = 0; |
| 1393 | |
| 1394 | if (i.operands == 2) |
| 1395 | { |
| 1396 | xchg1 = 0; |
| 1397 | xchg2 = 1; |
| 1398 | } |
| 1399 | else if (i.operands == 3) |
| 1400 | { |
| 1401 | xchg1 = 0; |
| 1402 | xchg2 = 2; |
| 1403 | } |
| 1404 | temp_type = i.types[xchg2]; |
| 1405 | i.types[xchg2] = i.types[xchg1]; |
| 1406 | i.types[xchg1] = temp_type; |
| 1407 | temp_op = i.op[xchg2]; |
| 1408 | i.op[xchg2] = i.op[xchg1]; |
| 1409 | i.op[xchg1] = temp_op; |
| 1410 | temp_disp_reloc = i.disp_reloc[xchg2]; |
| 1411 | i.disp_reloc[xchg2] = i.disp_reloc[xchg1]; |
| 1412 | i.disp_reloc[xchg1] = temp_disp_reloc; |
| 1413 | |
| 1414 | if (i.mem_operands == 2) |
| 1415 | { |
| 1416 | const seg_entry *temp_seg; |
| 1417 | temp_seg = i.seg[0]; |
| 1418 | i.seg[0] = i.seg[1]; |
| 1419 | i.seg[1] = temp_seg; |
| 1420 | } |
| 1421 | } |
| 1422 | |
| 1423 | if (i.imm_operands) |
| 1424 | { |
| 1425 | /* Try to ensure constant immediates are represented in the smallest |
| 1426 | opcode possible. */ |
| 1427 | char guess_suffix = 0; |
| 1428 | int op; |
| 1429 | |
| 1430 | if (i.suffix) |
| 1431 | guess_suffix = i.suffix; |
| 1432 | else if (i.reg_operands) |
| 1433 | { |
| 1434 | /* Figure out a suffix from the last register operand specified. |
| 1435 | We can't do this properly yet, ie. excluding InOutPortReg, |
| 1436 | but the following works for instructions with immediates. |
| 1437 | In any case, we can't set i.suffix yet. */ |
| 1438 | for (op = i.operands; --op >= 0;) |
| 1439 | if (i.types[op] & Reg) |
| 1440 | { |
| 1441 | if (i.types[op] & Reg8) |
| 1442 | guess_suffix = BYTE_MNEM_SUFFIX; |
| 1443 | else if (i.types[op] & Reg16) |
| 1444 | guess_suffix = WORD_MNEM_SUFFIX; |
| 1445 | break; |
| 1446 | } |
| 1447 | } |
| 1448 | else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) |
| 1449 | guess_suffix = WORD_MNEM_SUFFIX; |
| 1450 | |
| 1451 | for (op = i.operands; --op >= 0;) |
| 1452 | if ((i.types[op] & Imm) |
| 1453 | && i.op[op].imms->X_op == O_constant) |
| 1454 | { |
| 1455 | /* If a suffix is given, this operand may be shortened. */ |
| 1456 | switch (guess_suffix) |
| 1457 | { |
| 1458 | case WORD_MNEM_SUFFIX: |
| 1459 | i.types[op] |= Imm16; |
| 1460 | break; |
| 1461 | case BYTE_MNEM_SUFFIX: |
| 1462 | i.types[op] |= Imm16 | Imm8 | Imm8S; |
| 1463 | break; |
| 1464 | } |
| 1465 | |
| 1466 | /* If this operand is at most 16 bits, convert it to a |
| 1467 | signed 16 bit number before trying to see whether it will |
| 1468 | fit in an even smaller size. This allows a 16-bit operand |
| 1469 | such as $0xffe0 to be recognised as within Imm8S range. */ |
| 1470 | if ((i.types[op] & Imm16) |
| 1471 | && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0) |
| 1472 | { |
| 1473 | i.op[op].imms->X_add_number = |
| 1474 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); |
| 1475 | } |
| 1476 | i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number); |
| 1477 | } |
| 1478 | } |
| 1479 | |
| 1480 | if (i.disp_operands) |
| 1481 | { |
| 1482 | /* Try to use the smallest displacement type too. */ |
| 1483 | int op; |
| 1484 | |
| 1485 | for (op = i.operands; --op >= 0;) |
| 1486 | if ((i.types[op] & Disp) |
| 1487 | && i.op[op].imms->X_op == O_constant) |
| 1488 | { |
| 1489 | offsetT disp = i.op[op].disps->X_add_number; |
| 1490 | |
| 1491 | if (i.types[op] & Disp16) |
| 1492 | { |
| 1493 | /* We know this operand is at most 16 bits, so |
| 1494 | convert to a signed 16 bit number before trying |
| 1495 | to see whether it will fit in an even smaller |
| 1496 | size. */ |
| 1497 | |
| 1498 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); |
| 1499 | } |
| 1500 | if (fits_in_signed_byte (disp)) |
| 1501 | i.types[op] |= Disp8; |
| 1502 | } |
| 1503 | } |
| 1504 | |
| 1505 | overlap0 = 0; |
| 1506 | overlap1 = 0; |
| 1507 | overlap2 = 0; |
| 1508 | found_reverse_match = 0; |
| 1509 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX |
| 1510 | ? No_bSuf |
| 1511 | : (i.suffix == WORD_MNEM_SUFFIX |
| 1512 | ? No_wSuf |
| 1513 | : (i.suffix == SHORT_MNEM_SUFFIX |
| 1514 | ? No_sSuf |
| 1515 | : (i.suffix == LONG_MNEM_SUFFIX |
| 1516 | ? No_lSuf |
| 1517 | : (i.suffix == DWORD_MNEM_SUFFIX |
| 1518 | ? No_dSuf |
| 1519 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); |
| 1520 | |
| 1521 | for (t = current_templates->start; |
| 1522 | t < current_templates->end; |
| 1523 | t++) |
| 1524 | { |
| 1525 | /* Must have right number of operands. */ |
| 1526 | if (i.operands != t->operands) |
| 1527 | continue; |
| 1528 | |
| 1529 | /* Check the suffix, except for some instructions in intel mode. */ |
| 1530 | if ((t->opcode_modifier & suffix_check) |
| 1531 | && !(intel_syntax |
| 1532 | && (t->opcode_modifier & IgnoreSize)) |
| 1533 | && !(intel_syntax |
| 1534 | && t->base_opcode == 0xd9 |
| 1535 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ |
| 1536 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ |
| 1537 | continue; |
| 1538 | |
| 1539 | else if (!t->operands) |
| 1540 | /* 0 operands always matches. */ |
| 1541 | break; |
| 1542 | |
| 1543 | overlap0 = i.types[0] & t->operand_types[0]; |
| 1544 | switch (t->operands) |
| 1545 | { |
| 1546 | case 1: |
| 1547 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) |
| 1548 | continue; |
| 1549 | break; |
| 1550 | case 2: |
| 1551 | case 3: |
| 1552 | overlap1 = i.types[1] & t->operand_types[1]; |
| 1553 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) |
| 1554 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) |
| 1555 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], |
| 1556 | t->operand_types[0], |
| 1557 | overlap1, i.types[1], |
| 1558 | t->operand_types[1])) |
| 1559 | { |
| 1560 | /* Check if other direction is valid ... */ |
| 1561 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
| 1562 | continue; |
| 1563 | |
| 1564 | /* Try reversing direction of operands. */ |
| 1565 | overlap0 = i.types[0] & t->operand_types[1]; |
| 1566 | overlap1 = i.types[1] & t->operand_types[0]; |
| 1567 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) |
| 1568 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) |
| 1569 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], |
| 1570 | t->operand_types[1], |
| 1571 | overlap1, i.types[1], |
| 1572 | t->operand_types[0])) |
| 1573 | { |
| 1574 | /* Does not match either direction. */ |
| 1575 | continue; |
| 1576 | } |
| 1577 | /* found_reverse_match holds which of D or FloatDR |
| 1578 | we've found. */ |
| 1579 | found_reverse_match = t->opcode_modifier & (D|FloatDR); |
| 1580 | break; |
| 1581 | } |
| 1582 | /* Found a forward 2 operand match here. */ |
| 1583 | if (t->operands == 3) |
| 1584 | { |
| 1585 | /* Here we make use of the fact that there are no |
| 1586 | reverse match 3 operand instructions, and all 3 |
| 1587 | operand instructions only need to be checked for |
| 1588 | register consistency between operands 2 and 3. */ |
| 1589 | overlap2 = i.types[2] & t->operand_types[2]; |
| 1590 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) |
| 1591 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], |
| 1592 | t->operand_types[1], |
| 1593 | overlap2, i.types[2], |
| 1594 | t->operand_types[2])) |
| 1595 | |
| 1596 | continue; |
| 1597 | } |
| 1598 | /* Found either forward/reverse 2 or 3 operand match here: |
| 1599 | slip through to break. */ |
| 1600 | } |
| 1601 | /* We've found a match; break out of loop. */ |
| 1602 | break; |
| 1603 | } |
| 1604 | if (t == current_templates->end) |
| 1605 | { |
| 1606 | /* We found no match. */ |
| 1607 | as_bad (_("suffix or operands invalid for `%s'"), |
| 1608 | current_templates->start->name); |
| 1609 | return; |
| 1610 | } |
| 1611 | |
| 1612 | if (!quiet_warnings) |
| 1613 | { |
| 1614 | if (!intel_syntax |
| 1615 | && ((i.types[0] & JumpAbsolute) |
| 1616 | != (t->operand_types[0] & JumpAbsolute))) |
| 1617 | { |
| 1618 | as_warn (_("indirect %s without `*'"), t->name); |
| 1619 | } |
| 1620 | |
| 1621 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
| 1622 | == (IsPrefix|IgnoreSize)) |
| 1623 | { |
| 1624 | /* Warn them that a data or address size prefix doesn't |
| 1625 | affect assembly of the next line of code. */ |
| 1626 | as_warn (_("stand-alone `%s' prefix"), t->name); |
| 1627 | } |
| 1628 | } |
| 1629 | |
| 1630 | /* Copy the template we found. */ |
| 1631 | i.tm = *t; |
| 1632 | if (found_reverse_match) |
| 1633 | { |
| 1634 | /* If we found a reverse match we must alter the opcode |
| 1635 | direction bit. found_reverse_match holds bits to change |
| 1636 | (different for int & float insns). */ |
| 1637 | |
| 1638 | i.tm.base_opcode ^= found_reverse_match; |
| 1639 | |
| 1640 | i.tm.operand_types[0] = t->operand_types[1]; |
| 1641 | i.tm.operand_types[1] = t->operand_types[0]; |
| 1642 | } |
| 1643 | |
| 1644 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
| 1645 | if (SYSV386_COMPAT |
| 1646 | && intel_syntax |
| 1647 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) |
| 1648 | i.tm.base_opcode ^= FloatR; |
| 1649 | |
| 1650 | if (i.tm.opcode_modifier & FWait) |
| 1651 | if (! add_prefix (FWAIT_OPCODE)) |
| 1652 | return; |
| 1653 | |
| 1654 | /* Check string instruction segment overrides. */ |
| 1655 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) |
| 1656 | { |
| 1657 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; |
| 1658 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) |
| 1659 | { |
| 1660 | if (i.seg[0] != NULL && i.seg[0] != &es) |
| 1661 | { |
| 1662 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
| 1663 | i.tm.name, |
| 1664 | mem_op + 1); |
| 1665 | return; |
| 1666 | } |
| 1667 | /* There's only ever one segment override allowed per instruction. |
| 1668 | This instruction possibly has a legal segment override on the |
| 1669 | second operand, so copy the segment to where non-string |
| 1670 | instructions store it, allowing common code. */ |
| 1671 | i.seg[0] = i.seg[1]; |
| 1672 | } |
| 1673 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) |
| 1674 | { |
| 1675 | if (i.seg[1] != NULL && i.seg[1] != &es) |
| 1676 | { |
| 1677 | as_bad (_("`%s' operand %d must use `%%es' segment"), |
| 1678 | i.tm.name, |
| 1679 | mem_op + 2); |
| 1680 | return; |
| 1681 | } |
| 1682 | } |
| 1683 | } |
| 1684 | |
| 1685 | /* If matched instruction specifies an explicit instruction mnemonic |
| 1686 | suffix, use it. */ |
| 1687 | if (i.tm.opcode_modifier & (Size16 | Size32)) |
| 1688 | { |
| 1689 | if (i.tm.opcode_modifier & Size16) |
| 1690 | i.suffix = WORD_MNEM_SUFFIX; |
| 1691 | else |
| 1692 | i.suffix = LONG_MNEM_SUFFIX; |
| 1693 | } |
| 1694 | else if (i.reg_operands) |
| 1695 | { |
| 1696 | /* If there's no instruction mnemonic suffix we try to invent one |
| 1697 | based on register operands. */ |
| 1698 | if (!i.suffix) |
| 1699 | { |
| 1700 | /* We take i.suffix from the last register operand specified, |
| 1701 | Destination register type is more significant than source |
| 1702 | register type. */ |
| 1703 | int op; |
| 1704 | for (op = i.operands; --op >= 0;) |
| 1705 | if ((i.types[op] & Reg) |
| 1706 | && !(i.tm.operand_types[op] & InOutPortReg)) |
| 1707 | { |
| 1708 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : |
| 1709 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : |
| 1710 | LONG_MNEM_SUFFIX); |
| 1711 | break; |
| 1712 | } |
| 1713 | } |
| 1714 | else if (i.suffix == BYTE_MNEM_SUFFIX) |
| 1715 | { |
| 1716 | int op; |
| 1717 | for (op = i.operands; --op >= 0;) |
| 1718 | { |
| 1719 | /* If this is an eight bit register, it's OK. If it's |
| 1720 | the 16 or 32 bit version of an eight bit register, |
| 1721 | we will just use the low portion, and that's OK too. */ |
| 1722 | if (i.types[op] & Reg8) |
| 1723 | continue; |
| 1724 | |
| 1725 | /* movzx and movsx should not generate this warning. */ |
| 1726 | if (intel_syntax |
| 1727 | && (i.tm.base_opcode == 0xfb7 |
| 1728 | || i.tm.base_opcode == 0xfb6 |
| 1729 | || i.tm.base_opcode == 0xfbe |
| 1730 | || i.tm.base_opcode == 0xfbf)) |
| 1731 | continue; |
| 1732 | |
| 1733 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
| 1734 | #if 0 |
| 1735 | /* Check that the template allows eight bit regs |
| 1736 | This kills insns such as `orb $1,%edx', which |
| 1737 | maybe should be allowed. */ |
| 1738 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) |
| 1739 | #endif |
| 1740 | ) |
| 1741 | { |
| 1742 | #if REGISTER_WARNINGS |
| 1743 | if (!quiet_warnings |
| 1744 | && (i.tm.operand_types[op] & InOutPortReg) == 0) |
| 1745 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
| 1746 | (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name, |
| 1747 | i.op[op].regs->reg_name, |
| 1748 | i.suffix); |
| 1749 | #endif |
| 1750 | continue; |
| 1751 | } |
| 1752 | /* Any other register is bad. */ |
| 1753 | if (i.types[op] & (Reg | RegMMX | RegXMM |
| 1754 | | SReg2 | SReg3 |
| 1755 | | Control | Debug | Test |
| 1756 | | FloatReg | FloatAcc)) |
| 1757 | { |
| 1758 | as_bad (_("`%%%s' not allowed with `%s%c'"), |
| 1759 | i.op[op].regs->reg_name, |
| 1760 | i.tm.name, |
| 1761 | i.suffix); |
| 1762 | return; |
| 1763 | } |
| 1764 | } |
| 1765 | } |
| 1766 | else if (i.suffix == LONG_MNEM_SUFFIX) |
| 1767 | { |
| 1768 | int op; |
| 1769 | |
| 1770 | for (op = i.operands; --op >= 0;) |
| 1771 | /* Reject eight bit registers, except where the template |
| 1772 | requires them. (eg. movzb) */ |
| 1773 | if ((i.types[op] & Reg8) != 0 |
| 1774 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) |
| 1775 | { |
| 1776 | as_bad (_("`%%%s' not allowed with `%s%c'"), |
| 1777 | i.op[op].regs->reg_name, |
| 1778 | i.tm.name, |
| 1779 | i.suffix); |
| 1780 | return; |
| 1781 | } |
| 1782 | #if REGISTER_WARNINGS |
| 1783 | /* Warn if the e prefix on a general reg is missing. */ |
| 1784 | else if (!quiet_warnings |
| 1785 | && (i.types[op] & Reg16) != 0 |
| 1786 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
| 1787 | { |
| 1788 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
| 1789 | (i.op[op].regs + 8)->reg_name, |
| 1790 | i.op[op].regs->reg_name, |
| 1791 | i.suffix); |
| 1792 | } |
| 1793 | #endif |
| 1794 | } |
| 1795 | else if (i.suffix == WORD_MNEM_SUFFIX) |
| 1796 | { |
| 1797 | int op; |
| 1798 | for (op = i.operands; --op >= 0;) |
| 1799 | /* Reject eight bit registers, except where the template |
| 1800 | requires them. (eg. movzb) */ |
| 1801 | if ((i.types[op] & Reg8) != 0 |
| 1802 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) |
| 1803 | { |
| 1804 | as_bad (_("`%%%s' not allowed with `%s%c'"), |
| 1805 | i.op[op].regs->reg_name, |
| 1806 | i.tm.name, |
| 1807 | i.suffix); |
| 1808 | return; |
| 1809 | } |
| 1810 | #if REGISTER_WARNINGS |
| 1811 | /* Warn if the e prefix on a general reg is present. */ |
| 1812 | else if (!quiet_warnings |
| 1813 | && (i.types[op] & Reg32) != 0 |
| 1814 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
| 1815 | { |
| 1816 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
| 1817 | (i.op[op].regs - 8)->reg_name, |
| 1818 | i.op[op].regs->reg_name, |
| 1819 | i.suffix); |
| 1820 | } |
| 1821 | #endif |
| 1822 | } |
| 1823 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) |
| 1824 | /* Do nothing if the instruction is going to ignore the prefix. */ |
| 1825 | ; |
| 1826 | else |
| 1827 | abort (); |
| 1828 | } |
| 1829 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
| 1830 | { |
| 1831 | i.suffix = stackop_size; |
| 1832 | } |
| 1833 | |
| 1834 | /* Make still unresolved immediate matches conform to size of immediate |
| 1835 | given in i.suffix. Note: overlap2 cannot be an immediate! */ |
| 1836 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) |
| 1837 | && overlap0 != Imm8 && overlap0 != Imm8S |
| 1838 | && overlap0 != Imm16 && overlap0 != Imm32) |
| 1839 | { |
| 1840 | if (i.suffix) |
| 1841 | { |
| 1842 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
| 1843 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); |
| 1844 | } |
| 1845 | else if (overlap0 == (Imm16 | Imm32)) |
| 1846 | { |
| 1847 | overlap0 = |
| 1848 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
| 1849 | } |
| 1850 | else |
| 1851 | { |
| 1852 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); |
| 1853 | return; |
| 1854 | } |
| 1855 | } |
| 1856 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) |
| 1857 | && overlap1 != Imm8 && overlap1 != Imm8S |
| 1858 | && overlap1 != Imm16 && overlap1 != Imm32) |
| 1859 | { |
| 1860 | if (i.suffix) |
| 1861 | { |
| 1862 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
| 1863 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); |
| 1864 | } |
| 1865 | else if (overlap1 == (Imm16 | Imm32)) |
| 1866 | { |
| 1867 | overlap1 = |
| 1868 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
| 1869 | } |
| 1870 | else |
| 1871 | { |
| 1872 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); |
| 1873 | return; |
| 1874 | } |
| 1875 | } |
| 1876 | assert ((overlap2 & Imm) == 0); |
| 1877 | |
| 1878 | i.types[0] = overlap0; |
| 1879 | if (overlap0 & ImplicitRegister) |
| 1880 | i.reg_operands--; |
| 1881 | if (overlap0 & Imm1) |
| 1882 | i.imm_operands = 0; /* kludge for shift insns. */ |
| 1883 | |
| 1884 | i.types[1] = overlap1; |
| 1885 | if (overlap1 & ImplicitRegister) |
| 1886 | i.reg_operands--; |
| 1887 | |
| 1888 | i.types[2] = overlap2; |
| 1889 | if (overlap2 & ImplicitRegister) |
| 1890 | i.reg_operands--; |
| 1891 | |
| 1892 | /* Finalize opcode. First, we change the opcode based on the operand |
| 1893 | size given by i.suffix: We need not change things for byte insns. */ |
| 1894 | |
| 1895 | if (!i.suffix && (i.tm.opcode_modifier & W)) |
| 1896 | { |
| 1897 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); |
| 1898 | return; |
| 1899 | } |
| 1900 | |
| 1901 | /* For movzx and movsx, need to check the register type. */ |
| 1902 | if (intel_syntax |
| 1903 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
| 1904 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
| 1905 | { |
| 1906 | unsigned int prefix = DATA_PREFIX_OPCODE; |
| 1907 | |
| 1908 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
| 1909 | if (!add_prefix (prefix)) |
| 1910 | return; |
| 1911 | } |
| 1912 | |
| 1913 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) |
| 1914 | { |
| 1915 | /* It's not a byte, select word/dword operation. */ |
| 1916 | if (i.tm.opcode_modifier & W) |
| 1917 | { |
| 1918 | if (i.tm.opcode_modifier & ShortForm) |
| 1919 | i.tm.base_opcode |= 8; |
| 1920 | else |
| 1921 | i.tm.base_opcode |= 1; |
| 1922 | } |
| 1923 | /* Now select between word & dword operations via the operand |
| 1924 | size prefix, except for instructions that will ignore this |
| 1925 | prefix anyway. */ |
| 1926 | if (((intel_syntax && (i.suffix == DWORD_MNEM_SUFFIX)) |
| 1927 | || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code |
| 1928 | && !(i.tm.opcode_modifier & IgnoreSize)) |
| 1929 | { |
| 1930 | unsigned int prefix = DATA_PREFIX_OPCODE; |
| 1931 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ |
| 1932 | prefix = ADDR_PREFIX_OPCODE; |
| 1933 | |
| 1934 | if (! add_prefix (prefix)) |
| 1935 | return; |
| 1936 | } |
| 1937 | /* Size floating point instruction. */ |
| 1938 | if (i.suffix == LONG_MNEM_SUFFIX |
| 1939 | || (intel_syntax && i.suffix == DWORD_MNEM_SUFFIX)) |
| 1940 | { |
| 1941 | if (i.tm.opcode_modifier & FloatMF) |
| 1942 | i.tm.base_opcode ^= 4; |
| 1943 | } |
| 1944 | } |
| 1945 | |
| 1946 | if (i.tm.opcode_modifier & ImmExt) |
| 1947 | { |
| 1948 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
| 1949 | opcode suffix which is coded in the same place as an 8-bit |
| 1950 | immediate field would be. Here we fake an 8-bit immediate |
| 1951 | operand from the opcode suffix stored in tm.extension_opcode. */ |
| 1952 | |
| 1953 | expressionS *exp; |
| 1954 | |
| 1955 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
| 1956 | |
| 1957 | exp = &im_expressions[i.imm_operands++]; |
| 1958 | i.op[i.operands].imms = exp; |
| 1959 | i.types[i.operands++] = Imm8; |
| 1960 | exp->X_op = O_constant; |
| 1961 | exp->X_add_number = i.tm.extension_opcode; |
| 1962 | i.tm.extension_opcode = None; |
| 1963 | } |
| 1964 | |
| 1965 | /* For insns with operands there are more diddles to do to the opcode. */ |
| 1966 | if (i.operands) |
| 1967 | { |
| 1968 | /* Default segment register this instruction will use |
| 1969 | for memory accesses. 0 means unknown. |
| 1970 | This is only for optimizing out unnecessary segment overrides. */ |
| 1971 | const seg_entry *default_seg = 0; |
| 1972 | |
| 1973 | /* The imul $imm, %reg instruction is converted into |
| 1974 | imul $imm, %reg, %reg, and the clr %reg instruction |
| 1975 | is converted into xor %reg, %reg. */ |
| 1976 | if (i.tm.opcode_modifier & regKludge) |
| 1977 | { |
| 1978 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; |
| 1979 | /* Pretend we saw the extra register operand. */ |
| 1980 | assert (i.op[first_reg_op + 1].regs == 0); |
| 1981 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
| 1982 | i.types[first_reg_op + 1] = i.types[first_reg_op]; |
| 1983 | i.reg_operands = 2; |
| 1984 | } |
| 1985 | |
| 1986 | if (i.tm.opcode_modifier & ShortForm) |
| 1987 | { |
| 1988 | /* The register or float register operand is in operand 0 or 1. */ |
| 1989 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
| 1990 | /* Register goes in low 3 bits of opcode. */ |
| 1991 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
| 1992 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
| 1993 | { |
| 1994 | /* Warn about some common errors, but press on regardless. |
| 1995 | The first case can be generated by gcc (<= 2.8.1). */ |
| 1996 | if (i.operands == 2) |
| 1997 | { |
| 1998 | /* Reversed arguments on faddp, fsubp, etc. */ |
| 1999 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, |
| 2000 | i.op[1].regs->reg_name, |
| 2001 | i.op[0].regs->reg_name); |
| 2002 | } |
| 2003 | else |
| 2004 | { |
| 2005 | /* Extraneous `l' suffix on fp insn. */ |
| 2006 | as_warn (_("translating to `%s %%%s'"), i.tm.name, |
| 2007 | i.op[0].regs->reg_name); |
| 2008 | } |
| 2009 | } |
| 2010 | } |
| 2011 | else if (i.tm.opcode_modifier & Modrm) |
| 2012 | { |
| 2013 | /* The opcode is completed (modulo i.tm.extension_opcode which |
| 2014 | must be put into the modrm byte). |
| 2015 | Now, we make the modrm & index base bytes based on all the |
| 2016 | info we've collected. */ |
| 2017 | |
| 2018 | /* i.reg_operands MUST be the number of real register operands; |
| 2019 | implicit registers do not count. */ |
| 2020 | if (i.reg_operands == 2) |
| 2021 | { |
| 2022 | unsigned int source, dest; |
| 2023 | source = ((i.types[0] |
| 2024 | & (Reg | RegMMX | RegXMM |
| 2025 | | SReg2 | SReg3 |
| 2026 | | Control | Debug | Test)) |
| 2027 | ? 0 : 1); |
| 2028 | dest = source + 1; |
| 2029 | |
| 2030 | i.rm.mode = 3; |
| 2031 | /* One of the register operands will be encoded in the |
| 2032 | i.tm.reg field, the other in the combined i.tm.mode |
| 2033 | and i.tm.regmem fields. If no form of this |
| 2034 | instruction supports a memory destination operand, |
| 2035 | then we assume the source operand may sometimes be |
| 2036 | a memory operand and so we need to store the |
| 2037 | destination in the i.rm.reg field. */ |
| 2038 | if ((i.tm.operand_types[dest] & AnyMem) == 0) |
| 2039 | { |
| 2040 | i.rm.reg = i.op[dest].regs->reg_num; |
| 2041 | i.rm.regmem = i.op[source].regs->reg_num; |
| 2042 | } |
| 2043 | else |
| 2044 | { |
| 2045 | i.rm.reg = i.op[source].regs->reg_num; |
| 2046 | i.rm.regmem = i.op[dest].regs->reg_num; |
| 2047 | } |
| 2048 | } |
| 2049 | else |
| 2050 | { /* If it's not 2 reg operands... */ |
| 2051 | if (i.mem_operands) |
| 2052 | { |
| 2053 | unsigned int fake_zero_displacement = 0; |
| 2054 | unsigned int op = ((i.types[0] & AnyMem) |
| 2055 | ? 0 |
| 2056 | : (i.types[1] & AnyMem) ? 1 : 2); |
| 2057 | |
| 2058 | default_seg = &ds; |
| 2059 | |
| 2060 | if (! i.base_reg) |
| 2061 | { |
| 2062 | i.rm.mode = 0; |
| 2063 | if (! i.disp_operands) |
| 2064 | fake_zero_displacement = 1; |
| 2065 | if (! i.index_reg) |
| 2066 | { |
| 2067 | /* Operand is just <disp> */ |
| 2068 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
| 2069 | { |
| 2070 | i.rm.regmem = NO_BASE_REGISTER_16; |
| 2071 | i.types[op] &= ~Disp; |
| 2072 | i.types[op] |= Disp16; |
| 2073 | } |
| 2074 | else |
| 2075 | { |
| 2076 | i.rm.regmem = NO_BASE_REGISTER; |
| 2077 | i.types[op] &= ~Disp; |
| 2078 | i.types[op] |= Disp32; |
| 2079 | } |
| 2080 | } |
| 2081 | else /* ! i.base_reg && i.index_reg */ |
| 2082 | { |
| 2083 | i.sib.index = i.index_reg->reg_num; |
| 2084 | i.sib.base = NO_BASE_REGISTER; |
| 2085 | i.sib.scale = i.log2_scale_factor; |
| 2086 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 2087 | i.types[op] &= ~Disp; |
| 2088 | i.types[op] |= Disp32; /* Must be 32 bit. */ |
| 2089 | } |
| 2090 | } |
| 2091 | else if (i.base_reg->reg_type & Reg16) |
| 2092 | { |
| 2093 | switch (i.base_reg->reg_num) |
| 2094 | { |
| 2095 | case 3: /* (%bx) */ |
| 2096 | if (! i.index_reg) |
| 2097 | i.rm.regmem = 7; |
| 2098 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
| 2099 | i.rm.regmem = i.index_reg->reg_num - 6; |
| 2100 | break; |
| 2101 | case 5: /* (%bp) */ |
| 2102 | default_seg = &ss; |
| 2103 | if (! i.index_reg) |
| 2104 | { |
| 2105 | i.rm.regmem = 6; |
| 2106 | if ((i.types[op] & Disp) == 0) |
| 2107 | { |
| 2108 | /* fake (%bp) into 0(%bp) */ |
| 2109 | i.types[op] |= Disp8; |
| 2110 | fake_zero_displacement = 1; |
| 2111 | } |
| 2112 | } |
| 2113 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
| 2114 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
| 2115 | break; |
| 2116 | default: /* (%si) -> 4 or (%di) -> 5 */ |
| 2117 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
| 2118 | } |
| 2119 | i.rm.mode = mode_from_disp_size (i.types[op]); |
| 2120 | } |
| 2121 | else /* i.base_reg and 32 bit mode */ |
| 2122 | { |
| 2123 | i.rm.regmem = i.base_reg->reg_num; |
| 2124 | i.sib.base = i.base_reg->reg_num; |
| 2125 | if (i.base_reg->reg_num == EBP_REG_NUM) |
| 2126 | { |
| 2127 | default_seg = &ss; |
| 2128 | if (i.disp_operands == 0) |
| 2129 | { |
| 2130 | fake_zero_displacement = 1; |
| 2131 | i.types[op] |= Disp8; |
| 2132 | } |
| 2133 | } |
| 2134 | else if (i.base_reg->reg_num == ESP_REG_NUM) |
| 2135 | { |
| 2136 | default_seg = &ss; |
| 2137 | } |
| 2138 | i.sib.scale = i.log2_scale_factor; |
| 2139 | if (! i.index_reg) |
| 2140 | { |
| 2141 | /* <disp>(%esp) becomes two byte modrm |
| 2142 | with no index register. We've already |
| 2143 | stored the code for esp in i.rm.regmem |
| 2144 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any |
| 2145 | base register besides %esp will not use |
| 2146 | the extra modrm byte. */ |
| 2147 | i.sib.index = NO_INDEX_REGISTER; |
| 2148 | #if ! SCALE1_WHEN_NO_INDEX |
| 2149 | /* Another case where we force the second |
| 2150 | modrm byte. */ |
| 2151 | if (i.log2_scale_factor) |
| 2152 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 2153 | #endif |
| 2154 | } |
| 2155 | else |
| 2156 | { |
| 2157 | i.sib.index = i.index_reg->reg_num; |
| 2158 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 2159 | } |
| 2160 | i.rm.mode = mode_from_disp_size (i.types[op]); |
| 2161 | } |
| 2162 | |
| 2163 | if (fake_zero_displacement) |
| 2164 | { |
| 2165 | /* Fakes a zero displacement assuming that i.types[op] |
| 2166 | holds the correct displacement size. */ |
| 2167 | expressionS *exp; |
| 2168 | |
| 2169 | assert (i.op[op].disps == 0); |
| 2170 | exp = &disp_expressions[i.disp_operands++]; |
| 2171 | i.op[op].disps = exp; |
| 2172 | exp->X_op = O_constant; |
| 2173 | exp->X_add_number = 0; |
| 2174 | exp->X_add_symbol = (symbolS *) 0; |
| 2175 | exp->X_op_symbol = (symbolS *) 0; |
| 2176 | } |
| 2177 | } |
| 2178 | |
| 2179 | /* Fill in i.rm.reg or i.rm.regmem field with register |
| 2180 | operand (if any) based on i.tm.extension_opcode. |
| 2181 | Again, we must be careful to make sure that |
| 2182 | segment/control/debug/test/MMX registers are coded |
| 2183 | into the i.rm.reg field. */ |
| 2184 | if (i.reg_operands) |
| 2185 | { |
| 2186 | unsigned int op = |
| 2187 | ((i.types[0] |
| 2188 | & (Reg | RegMMX | RegXMM |
| 2189 | | SReg2 | SReg3 |
| 2190 | | Control | Debug | Test)) |
| 2191 | ? 0 |
| 2192 | : ((i.types[1] |
| 2193 | & (Reg | RegMMX | RegXMM |
| 2194 | | SReg2 | SReg3 |
| 2195 | | Control | Debug | Test)) |
| 2196 | ? 1 |
| 2197 | : 2)); |
| 2198 | /* If there is an extension opcode to put here, the |
| 2199 | register number must be put into the regmem field. */ |
| 2200 | if (i.tm.extension_opcode != None) |
| 2201 | i.rm.regmem = i.op[op].regs->reg_num; |
| 2202 | else |
| 2203 | i.rm.reg = i.op[op].regs->reg_num; |
| 2204 | |
| 2205 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 |
| 2206 | we must set it to 3 to indicate this is a register |
| 2207 | operand in the regmem field. */ |
| 2208 | if (!i.mem_operands) |
| 2209 | i.rm.mode = 3; |
| 2210 | } |
| 2211 | |
| 2212 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
| 2213 | if (i.tm.extension_opcode != None) |
| 2214 | i.rm.reg = i.tm.extension_opcode; |
| 2215 | } |
| 2216 | } |
| 2217 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) |
| 2218 | { |
| 2219 | if (i.tm.base_opcode == POP_SEG_SHORT |
| 2220 | && i.op[0].regs->reg_num == 1) |
| 2221 | { |
| 2222 | as_bad (_("you can't `pop %%cs'")); |
| 2223 | return; |
| 2224 | } |
| 2225 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
| 2226 | } |
| 2227 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) |
| 2228 | { |
| 2229 | default_seg = &ds; |
| 2230 | } |
| 2231 | else if ((i.tm.opcode_modifier & IsString) != 0) |
| 2232 | { |
| 2233 | /* For the string instructions that allow a segment override |
| 2234 | on one of their operands, the default segment is ds. */ |
| 2235 | default_seg = &ds; |
| 2236 | } |
| 2237 | |
| 2238 | /* If a segment was explicitly specified, |
| 2239 | and the specified segment is not the default, |
| 2240 | use an opcode prefix to select it. |
| 2241 | If we never figured out what the default segment is, |
| 2242 | then default_seg will be zero at this point, |
| 2243 | and the specified segment prefix will always be used. */ |
| 2244 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
| 2245 | { |
| 2246 | if (! add_prefix (i.seg[0]->seg_prefix)) |
| 2247 | return; |
| 2248 | } |
| 2249 | } |
| 2250 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
| 2251 | { |
| 2252 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
| 2253 | as_warn (_("translating to `%sp'"), i.tm.name); |
| 2254 | } |
| 2255 | } |
| 2256 | |
| 2257 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
| 2258 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
| 2259 | { |
| 2260 | i.tm.base_opcode = INT3_OPCODE; |
| 2261 | i.imm_operands = 0; |
| 2262 | } |
| 2263 | |
| 2264 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
| 2265 | && i.op[0].disps->X_op == O_constant) |
| 2266 | { |
| 2267 | /* Convert "jmp constant" (and "call constant") to a jump (call) to |
| 2268 | the absolute address given by the constant. Since ix86 jumps and |
| 2269 | calls are pc relative, we need to generate a reloc. */ |
| 2270 | i.op[0].disps->X_add_symbol = &abs_symbol; |
| 2271 | i.op[0].disps->X_op = O_symbol; |
| 2272 | } |
| 2273 | |
| 2274 | /* We are ready to output the insn. */ |
| 2275 | { |
| 2276 | register char *p; |
| 2277 | |
| 2278 | /* Output jumps. */ |
| 2279 | if (i.tm.opcode_modifier & Jump) |
| 2280 | { |
| 2281 | int size; |
| 2282 | int code16; |
| 2283 | int prefix; |
| 2284 | |
| 2285 | code16 = 0; |
| 2286 | if (flag_16bit_code) |
| 2287 | code16 = CODE16; |
| 2288 | |
| 2289 | prefix = 0; |
| 2290 | if (i.prefix[DATA_PREFIX]) |
| 2291 | { |
| 2292 | prefix = 1; |
| 2293 | i.prefixes -= 1; |
| 2294 | code16 ^= CODE16; |
| 2295 | } |
| 2296 | |
| 2297 | size = 4; |
| 2298 | if (code16) |
| 2299 | size = 2; |
| 2300 | |
| 2301 | if (i.prefixes != 0 && !intel_syntax) |
| 2302 | as_warn (_("skipping prefixes on this instruction")); |
| 2303 | |
| 2304 | /* It's always a symbol; End frag & setup for relax. |
| 2305 | Make sure there is enough room in this frag for the largest |
| 2306 | instruction we may generate in md_convert_frag. This is 2 |
| 2307 | bytes for the opcode and room for the prefix and largest |
| 2308 | displacement. */ |
| 2309 | frag_grow (prefix + 2 + size); |
| 2310 | insn_size += prefix + 1; |
| 2311 | /* Prefix and 1 opcode byte go in fr_fix. */ |
| 2312 | p = frag_more (prefix + 1); |
| 2313 | if (prefix) |
| 2314 | *p++ = DATA_PREFIX_OPCODE; |
| 2315 | *p = i.tm.base_opcode; |
| 2316 | /* 1 possible extra opcode + displacement go in var part. |
| 2317 | Pass reloc in fr_var. */ |
| 2318 | frag_var (rs_machine_dependent, |
| 2319 | 1 + size, |
| 2320 | i.disp_reloc[0], |
| 2321 | ((unsigned char) *p == JUMP_PC_RELATIVE |
| 2322 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 |
| 2323 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), |
| 2324 | i.op[0].disps->X_add_symbol, |
| 2325 | i.op[0].disps->X_add_number, |
| 2326 | p); |
| 2327 | } |
| 2328 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) |
| 2329 | { |
| 2330 | int size; |
| 2331 | |
| 2332 | if (i.tm.opcode_modifier & JumpByte) |
| 2333 | { |
| 2334 | /* This is a loop or jecxz type instruction. */ |
| 2335 | size = 1; |
| 2336 | if (i.prefix[ADDR_PREFIX]) |
| 2337 | { |
| 2338 | insn_size += 1; |
| 2339 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
| 2340 | i.prefixes -= 1; |
| 2341 | } |
| 2342 | } |
| 2343 | else |
| 2344 | { |
| 2345 | int code16; |
| 2346 | |
| 2347 | code16 = 0; |
| 2348 | if (flag_16bit_code) |
| 2349 | code16 = CODE16; |
| 2350 | |
| 2351 | if (i.prefix[DATA_PREFIX]) |
| 2352 | { |
| 2353 | insn_size += 1; |
| 2354 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); |
| 2355 | i.prefixes -= 1; |
| 2356 | code16 ^= CODE16; |
| 2357 | } |
| 2358 | |
| 2359 | size = 4; |
| 2360 | if (code16) |
| 2361 | size = 2; |
| 2362 | } |
| 2363 | |
| 2364 | if (i.prefixes != 0 && !intel_syntax) |
| 2365 | as_warn (_("skipping prefixes on this instruction")); |
| 2366 | |
| 2367 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
| 2368 | { |
| 2369 | insn_size += 1 + size; |
| 2370 | p = frag_more (1 + size); |
| 2371 | } |
| 2372 | else |
| 2373 | { |
| 2374 | /* Opcode can be at most two bytes. */ |
| 2375 | insn_size += 2 + size; |
| 2376 | p = frag_more (2 + size); |
| 2377 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
| 2378 | } |
| 2379 | *p++ = i.tm.base_opcode & 0xff; |
| 2380 | |
| 2381 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 2382 | i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0])); |
| 2383 | } |
| 2384 | else if (i.tm.opcode_modifier & JumpInterSegment) |
| 2385 | { |
| 2386 | int size; |
| 2387 | int prefix; |
| 2388 | int code16; |
| 2389 | |
| 2390 | code16 = 0; |
| 2391 | if (flag_16bit_code) |
| 2392 | code16 = CODE16; |
| 2393 | |
| 2394 | prefix = 0; |
| 2395 | if (i.prefix[DATA_PREFIX]) |
| 2396 | { |
| 2397 | prefix = 1; |
| 2398 | i.prefixes -= 1; |
| 2399 | code16 ^= CODE16; |
| 2400 | } |
| 2401 | |
| 2402 | size = 4; |
| 2403 | if (code16) |
| 2404 | size = 2; |
| 2405 | |
| 2406 | if (i.prefixes != 0 && !intel_syntax) |
| 2407 | as_warn (_("skipping prefixes on this instruction")); |
| 2408 | |
| 2409 | /* 1 opcode; 2 segment; offset */ |
| 2410 | insn_size += prefix + 1 + 2 + size; |
| 2411 | p = frag_more (prefix + 1 + 2 + size); |
| 2412 | if (prefix) |
| 2413 | *p++ = DATA_PREFIX_OPCODE; |
| 2414 | *p++ = i.tm.base_opcode; |
| 2415 | if (i.op[1].imms->X_op == O_constant) |
| 2416 | { |
| 2417 | offsetT n = i.op[1].imms->X_add_number; |
| 2418 | |
| 2419 | if (size == 2 |
| 2420 | && !fits_in_unsigned_word (n) |
| 2421 | && !fits_in_signed_word (n)) |
| 2422 | { |
| 2423 | as_bad (_("16-bit jump out of range")); |
| 2424 | return; |
| 2425 | } |
| 2426 | md_number_to_chars (p, n, size); |
| 2427 | } |
| 2428 | else |
| 2429 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 2430 | i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0])); |
| 2431 | if (i.op[0].imms->X_op != O_constant) |
| 2432 | as_bad (_("can't handle non absolute segment in `%s'"), |
| 2433 | i.tm.name); |
| 2434 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
| 2435 | } |
| 2436 | else |
| 2437 | { |
| 2438 | /* Output normal instructions here. */ |
| 2439 | unsigned char *q; |
| 2440 | |
| 2441 | /* The prefix bytes. */ |
| 2442 | for (q = i.prefix; |
| 2443 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); |
| 2444 | q++) |
| 2445 | { |
| 2446 | if (*q) |
| 2447 | { |
| 2448 | insn_size += 1; |
| 2449 | p = frag_more (1); |
| 2450 | md_number_to_chars (p, (valueT) *q, 1); |
| 2451 | } |
| 2452 | } |
| 2453 | |
| 2454 | /* Now the opcode; be careful about word order here! */ |
| 2455 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
| 2456 | { |
| 2457 | insn_size += 1; |
| 2458 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
| 2459 | } |
| 2460 | else if (fits_in_unsigned_word (i.tm.base_opcode)) |
| 2461 | { |
| 2462 | insn_size += 2; |
| 2463 | p = frag_more (2); |
| 2464 | /* Put out high byte first: can't use md_number_to_chars! */ |
| 2465 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
| 2466 | *p = i.tm.base_opcode & 0xff; |
| 2467 | } |
| 2468 | else |
| 2469 | { /* Opcode is either 3 or 4 bytes. */ |
| 2470 | if (i.tm.base_opcode & 0xff000000) |
| 2471 | { |
| 2472 | insn_size += 4; |
| 2473 | p = frag_more (4); |
| 2474 | *p++ = (i.tm.base_opcode >> 24) & 0xff; |
| 2475 | } |
| 2476 | else |
| 2477 | { |
| 2478 | insn_size += 3; |
| 2479 | p = frag_more (3); |
| 2480 | } |
| 2481 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
| 2482 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
| 2483 | *p = (i.tm.base_opcode) & 0xff; |
| 2484 | } |
| 2485 | |
| 2486 | /* Now the modrm byte and sib byte (if present). */ |
| 2487 | if (i.tm.opcode_modifier & Modrm) |
| 2488 | { |
| 2489 | insn_size += 1; |
| 2490 | p = frag_more (1); |
| 2491 | md_number_to_chars (p, |
| 2492 | (valueT) (i.rm.regmem << 0 |
| 2493 | | i.rm.reg << 3 |
| 2494 | | i.rm.mode << 6), |
| 2495 | 1); |
| 2496 | /* If i.rm.regmem == ESP (4) |
| 2497 | && i.rm.mode != (Register mode) |
| 2498 | && not 16 bit |
| 2499 | ==> need second modrm byte. */ |
| 2500 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING |
| 2501 | && i.rm.mode != 3 |
| 2502 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) |
| 2503 | { |
| 2504 | insn_size += 1; |
| 2505 | p = frag_more (1); |
| 2506 | md_number_to_chars (p, |
| 2507 | (valueT) (i.sib.base << 0 |
| 2508 | | i.sib.index << 3 |
| 2509 | | i.sib.scale << 6), |
| 2510 | 1); |
| 2511 | } |
| 2512 | } |
| 2513 | |
| 2514 | if (i.disp_operands) |
| 2515 | { |
| 2516 | register unsigned int n; |
| 2517 | |
| 2518 | for (n = 0; n < i.operands; n++) |
| 2519 | { |
| 2520 | if (i.types[n] & Disp) |
| 2521 | { |
| 2522 | if (i.op[n].disps->X_op == O_constant) |
| 2523 | { |
| 2524 | int size; |
| 2525 | offsetT val; |
| 2526 | |
| 2527 | size = 4; |
| 2528 | if (i.types[n] & (Disp8 | Disp16)) |
| 2529 | { |
| 2530 | size = 2; |
| 2531 | if (i.types[n] & Disp8) |
| 2532 | size = 1; |
| 2533 | } |
| 2534 | val = offset_in_range (i.op[n].disps->X_add_number, |
| 2535 | size); |
| 2536 | insn_size += size; |
| 2537 | p = frag_more (size); |
| 2538 | md_number_to_chars (p, val, size); |
| 2539 | } |
| 2540 | else |
| 2541 | { |
| 2542 | int size = 4; |
| 2543 | |
| 2544 | if (i.types[n] & Disp16) |
| 2545 | size = 2; |
| 2546 | |
| 2547 | insn_size += size; |
| 2548 | p = frag_more (size); |
| 2549 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 2550 | i.op[n].disps, 0, |
| 2551 | reloc (size, 0, i.disp_reloc[n])); |
| 2552 | } |
| 2553 | } |
| 2554 | } |
| 2555 | } |
| 2556 | |
| 2557 | /* Output immediate. */ |
| 2558 | if (i.imm_operands) |
| 2559 | { |
| 2560 | register unsigned int n; |
| 2561 | |
| 2562 | for (n = 0; n < i.operands; n++) |
| 2563 | { |
| 2564 | if (i.types[n] & Imm) |
| 2565 | { |
| 2566 | if (i.op[n].imms->X_op == O_constant) |
| 2567 | { |
| 2568 | int size; |
| 2569 | offsetT val; |
| 2570 | |
| 2571 | size = 4; |
| 2572 | if (i.types[n] & (Imm8 | Imm8S | Imm16)) |
| 2573 | { |
| 2574 | size = 2; |
| 2575 | if (i.types[n] & (Imm8 | Imm8S)) |
| 2576 | size = 1; |
| 2577 | } |
| 2578 | val = offset_in_range (i.op[n].imms->X_add_number, |
| 2579 | size); |
| 2580 | insn_size += size; |
| 2581 | p = frag_more (size); |
| 2582 | md_number_to_chars (p, val, size); |
| 2583 | } |
| 2584 | else |
| 2585 | { |
| 2586 | /* Not absolute_section. |
| 2587 | Need a 32-bit fixup (don't support 8bit |
| 2588 | non-absolute imms). Try to support other |
| 2589 | sizes ... */ |
| 2590 | #ifdef BFD_ASSEMBLER |
| 2591 | enum bfd_reloc_code_real reloc_type; |
| 2592 | #else |
| 2593 | int reloc_type; |
| 2594 | #endif |
| 2595 | int size = 4; |
| 2596 | |
| 2597 | if (i.types[n] & Imm16) |
| 2598 | size = 2; |
| 2599 | else if (i.types[n] & (Imm8 | Imm8S)) |
| 2600 | size = 1; |
| 2601 | |
| 2602 | insn_size += size; |
| 2603 | p = frag_more (size); |
| 2604 | reloc_type = reloc (size, 0, i.disp_reloc[0]); |
| 2605 | #ifdef BFD_ASSEMBLER |
| 2606 | if (reloc_type == BFD_RELOC_32 |
| 2607 | && GOT_symbol |
| 2608 | && GOT_symbol == i.op[n].imms->X_add_symbol |
| 2609 | && (i.op[n].imms->X_op == O_symbol |
| 2610 | || (i.op[n].imms->X_op == O_add |
| 2611 | && ((symbol_get_value_expression |
| 2612 | (i.op[n].imms->X_op_symbol)->X_op) |
| 2613 | == O_subtract)))) |
| 2614 | { |
| 2615 | reloc_type = BFD_RELOC_386_GOTPC; |
| 2616 | i.op[n].imms->X_add_number += 3; |
| 2617 | } |
| 2618 | #endif |
| 2619 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 2620 | i.op[n].imms, 0, reloc_type); |
| 2621 | } |
| 2622 | } |
| 2623 | } |
| 2624 | } |
| 2625 | } |
| 2626 | |
| 2627 | dwarf2_emit_insn (insn_size); |
| 2628 | |
| 2629 | #ifdef DEBUG386 |
| 2630 | if (flag_debug) |
| 2631 | { |
| 2632 | pi (line, &i); |
| 2633 | } |
| 2634 | #endif /* DEBUG386 */ |
| 2635 | } |
| 2636 | } |
| 2637 | \f |
| 2638 | static int i386_immediate PARAMS ((char *)); |
| 2639 | |
| 2640 | static int |
| 2641 | i386_immediate (imm_start) |
| 2642 | char *imm_start; |
| 2643 | { |
| 2644 | char *save_input_line_pointer; |
| 2645 | segT exp_seg = 0; |
| 2646 | expressionS *exp; |
| 2647 | |
| 2648 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) |
| 2649 | { |
| 2650 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
| 2651 | return 0; |
| 2652 | } |
| 2653 | |
| 2654 | exp = &im_expressions[i.imm_operands++]; |
| 2655 | i.op[this_operand].imms = exp; |
| 2656 | |
| 2657 | if (is_space_char (*imm_start)) |
| 2658 | ++imm_start; |
| 2659 | |
| 2660 | save_input_line_pointer = input_line_pointer; |
| 2661 | input_line_pointer = imm_start; |
| 2662 | |
| 2663 | #ifndef LEX_AT |
| 2664 | { |
| 2665 | /* We can have operands of the form |
| 2666 | <symbol>@GOTOFF+<nnn> |
| 2667 | Take the easy way out here and copy everything |
| 2668 | into a temporary buffer... */ |
| 2669 | register char *cp; |
| 2670 | |
| 2671 | cp = strchr (input_line_pointer, '@'); |
| 2672 | if (cp != NULL) |
| 2673 | { |
| 2674 | char *tmpbuf; |
| 2675 | int len = 0; |
| 2676 | int first; |
| 2677 | |
| 2678 | /* GOT relocations are not supported in 16 bit mode. */ |
| 2679 | if (flag_16bit_code) |
| 2680 | as_bad (_("GOT relocations not supported in 16 bit mode")); |
| 2681 | |
| 2682 | if (GOT_symbol == NULL) |
| 2683 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
| 2684 | |
| 2685 | if (strncmp (cp + 1, "PLT", 3) == 0) |
| 2686 | { |
| 2687 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; |
| 2688 | len = 3; |
| 2689 | } |
| 2690 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) |
| 2691 | { |
| 2692 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; |
| 2693 | len = 6; |
| 2694 | } |
| 2695 | else if (strncmp (cp + 1, "GOT", 3) == 0) |
| 2696 | { |
| 2697 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; |
| 2698 | len = 3; |
| 2699 | } |
| 2700 | else |
| 2701 | as_bad (_("bad reloc specifier in expression")); |
| 2702 | |
| 2703 | /* Replace the relocation token with ' ', so that errors like |
| 2704 | foo@GOTOFF1 will be detected. */ |
| 2705 | first = cp - input_line_pointer; |
| 2706 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
| 2707 | memcpy (tmpbuf, input_line_pointer, first); |
| 2708 | tmpbuf[first] = ' '; |
| 2709 | strcpy (tmpbuf + first + 1, cp + 1 + len); |
| 2710 | input_line_pointer = tmpbuf; |
| 2711 | } |
| 2712 | } |
| 2713 | #endif |
| 2714 | |
| 2715 | exp_seg = expression (exp); |
| 2716 | |
| 2717 | SKIP_WHITESPACE (); |
| 2718 | if (*input_line_pointer) |
| 2719 | as_bad (_("ignoring junk `%s' after expression"), input_line_pointer); |
| 2720 | |
| 2721 | input_line_pointer = save_input_line_pointer; |
| 2722 | |
| 2723 | if (exp->X_op == O_absent || exp->X_op == O_big) |
| 2724 | { |
| 2725 | /* Missing or bad expr becomes absolute 0. */ |
| 2726 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
| 2727 | imm_start); |
| 2728 | exp->X_op = O_constant; |
| 2729 | exp->X_add_number = 0; |
| 2730 | exp->X_add_symbol = (symbolS *) 0; |
| 2731 | exp->X_op_symbol = (symbolS *) 0; |
| 2732 | } |
| 2733 | |
| 2734 | if (exp->X_op == O_constant) |
| 2735 | { |
| 2736 | /* Size it properly later. */ |
| 2737 | i.types[this_operand] |= Imm32; |
| 2738 | } |
| 2739 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 2740 | else if (1 |
| 2741 | #ifdef BFD_ASSEMBLER |
| 2742 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
| 2743 | #endif |
| 2744 | && exp_seg != text_section |
| 2745 | && exp_seg != data_section |
| 2746 | && exp_seg != bss_section |
| 2747 | && exp_seg != undefined_section |
| 2748 | #ifdef BFD_ASSEMBLER |
| 2749 | && !bfd_is_com_section (exp_seg) |
| 2750 | #endif |
| 2751 | ) |
| 2752 | { |
| 2753 | #ifdef BFD_ASSEMBLER |
| 2754 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
| 2755 | #else |
| 2756 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
| 2757 | #endif |
| 2758 | return 0; |
| 2759 | } |
| 2760 | #endif |
| 2761 | else |
| 2762 | { |
| 2763 | /* This is an address. The size of the address will be |
| 2764 | determined later, depending on destination register, |
| 2765 | suffix, or the default for the section. We exclude |
| 2766 | Imm8S here so that `push $foo' and other instructions |
| 2767 | with an Imm8S form will use Imm16 or Imm32. */ |
| 2768 | i.types[this_operand] |= (Imm8 | Imm16 | Imm32); |
| 2769 | } |
| 2770 | |
| 2771 | return 1; |
| 2772 | } |
| 2773 | |
| 2774 | static int i386_scale PARAMS ((char *)); |
| 2775 | |
| 2776 | static int |
| 2777 | i386_scale (scale) |
| 2778 | char *scale; |
| 2779 | { |
| 2780 | if (!isdigit (*scale)) |
| 2781 | goto bad_scale; |
| 2782 | |
| 2783 | switch (*scale) |
| 2784 | { |
| 2785 | case '0': |
| 2786 | case '1': |
| 2787 | i.log2_scale_factor = 0; |
| 2788 | break; |
| 2789 | case '2': |
| 2790 | i.log2_scale_factor = 1; |
| 2791 | break; |
| 2792 | case '4': |
| 2793 | i.log2_scale_factor = 2; |
| 2794 | break; |
| 2795 | case '8': |
| 2796 | i.log2_scale_factor = 3; |
| 2797 | break; |
| 2798 | default: |
| 2799 | bad_scale: |
| 2800 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
| 2801 | scale); |
| 2802 | return 0; |
| 2803 | } |
| 2804 | if (i.log2_scale_factor != 0 && ! i.index_reg) |
| 2805 | { |
| 2806 | as_warn (_("scale factor of %d without an index register"), |
| 2807 | 1 << i.log2_scale_factor); |
| 2808 | #if SCALE1_WHEN_NO_INDEX |
| 2809 | i.log2_scale_factor = 0; |
| 2810 | #endif |
| 2811 | } |
| 2812 | return 1; |
| 2813 | } |
| 2814 | |
| 2815 | static int i386_displacement PARAMS ((char *, char *)); |
| 2816 | |
| 2817 | static int |
| 2818 | i386_displacement (disp_start, disp_end) |
| 2819 | char *disp_start; |
| 2820 | char *disp_end; |
| 2821 | { |
| 2822 | register expressionS *exp; |
| 2823 | segT exp_seg = 0; |
| 2824 | char *save_input_line_pointer; |
| 2825 | int bigdisp = Disp32; |
| 2826 | |
| 2827 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
| 2828 | bigdisp = Disp16; |
| 2829 | i.types[this_operand] |= bigdisp; |
| 2830 | |
| 2831 | exp = &disp_expressions[i.disp_operands]; |
| 2832 | i.op[this_operand].disps = exp; |
| 2833 | i.disp_operands++; |
| 2834 | save_input_line_pointer = input_line_pointer; |
| 2835 | input_line_pointer = disp_start; |
| 2836 | END_STRING_AND_SAVE (disp_end); |
| 2837 | |
| 2838 | #ifndef GCC_ASM_O_HACK |
| 2839 | #define GCC_ASM_O_HACK 0 |
| 2840 | #endif |
| 2841 | #if GCC_ASM_O_HACK |
| 2842 | END_STRING_AND_SAVE (disp_end + 1); |
| 2843 | if ((i.types[this_operand] & BaseIndex) != 0 |
| 2844 | && displacement_string_end[-1] == '+') |
| 2845 | { |
| 2846 | /* This hack is to avoid a warning when using the "o" |
| 2847 | constraint within gcc asm statements. |
| 2848 | For instance: |
| 2849 | |
| 2850 | #define _set_tssldt_desc(n,addr,limit,type) \ |
| 2851 | __asm__ __volatile__ ( \ |
| 2852 | "movw %w2,%0\n\t" \ |
| 2853 | "movw %w1,2+%0\n\t" \ |
| 2854 | "rorl $16,%1\n\t" \ |
| 2855 | "movb %b1,4+%0\n\t" \ |
| 2856 | "movb %4,5+%0\n\t" \ |
| 2857 | "movb $0,6+%0\n\t" \ |
| 2858 | "movb %h1,7+%0\n\t" \ |
| 2859 | "rorl $16,%1" \ |
| 2860 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) |
| 2861 | |
| 2862 | This works great except that the output assembler ends |
| 2863 | up looking a bit weird if it turns out that there is |
| 2864 | no offset. You end up producing code that looks like: |
| 2865 | |
| 2866 | #APP |
| 2867 | movw $235,(%eax) |
| 2868 | movw %dx,2+(%eax) |
| 2869 | rorl $16,%edx |
| 2870 | movb %dl,4+(%eax) |
| 2871 | movb $137,5+(%eax) |
| 2872 | movb $0,6+(%eax) |
| 2873 | movb %dh,7+(%eax) |
| 2874 | rorl $16,%edx |
| 2875 | #NO_APP |
| 2876 | |
| 2877 | So here we provide the missing zero. */ |
| 2878 | |
| 2879 | *displacement_string_end = '0'; |
| 2880 | } |
| 2881 | #endif |
| 2882 | #ifndef LEX_AT |
| 2883 | { |
| 2884 | /* We can have operands of the form |
| 2885 | <symbol>@GOTOFF+<nnn> |
| 2886 | Take the easy way out here and copy everything |
| 2887 | into a temporary buffer... */ |
| 2888 | register char *cp; |
| 2889 | |
| 2890 | cp = strchr (input_line_pointer, '@'); |
| 2891 | if (cp != NULL) |
| 2892 | { |
| 2893 | char *tmpbuf; |
| 2894 | int len = 0; |
| 2895 | int first; |
| 2896 | |
| 2897 | /* GOT relocations are not supported in 16 bit mode. */ |
| 2898 | if (flag_16bit_code) |
| 2899 | as_bad (_("GOT relocations not supported in 16 bit mode")); |
| 2900 | |
| 2901 | if (GOT_symbol == NULL) |
| 2902 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
| 2903 | |
| 2904 | if (strncmp (cp + 1, "PLT", 3) == 0) |
| 2905 | { |
| 2906 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; |
| 2907 | len = 3; |
| 2908 | } |
| 2909 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) |
| 2910 | { |
| 2911 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; |
| 2912 | len = 6; |
| 2913 | } |
| 2914 | else if (strncmp (cp + 1, "GOT", 3) == 0) |
| 2915 | { |
| 2916 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; |
| 2917 | len = 3; |
| 2918 | } |
| 2919 | else |
| 2920 | as_bad (_("bad reloc specifier in expression")); |
| 2921 | |
| 2922 | /* Replace the relocation token with ' ', so that errors like |
| 2923 | foo@GOTOFF1 will be detected. */ |
| 2924 | first = cp - input_line_pointer; |
| 2925 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
| 2926 | memcpy (tmpbuf, input_line_pointer, first); |
| 2927 | tmpbuf[first] = ' '; |
| 2928 | strcpy (tmpbuf + first + 1, cp + 1 + len); |
| 2929 | input_line_pointer = tmpbuf; |
| 2930 | } |
| 2931 | } |
| 2932 | #endif |
| 2933 | |
| 2934 | exp_seg = expression (exp); |
| 2935 | |
| 2936 | #ifdef BFD_ASSEMBLER |
| 2937 | /* We do this to make sure that the section symbol is in |
| 2938 | the symbol table. We will ultimately change the relocation |
| 2939 | to be relative to the beginning of the section. */ |
| 2940 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) |
| 2941 | { |
| 2942 | if (S_IS_LOCAL(exp->X_add_symbol) |
| 2943 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
| 2944 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
| 2945 | assert (exp->X_op == O_symbol); |
| 2946 | exp->X_op = O_subtract; |
| 2947 | exp->X_op_symbol = GOT_symbol; |
| 2948 | i.disp_reloc[this_operand] = BFD_RELOC_32; |
| 2949 | } |
| 2950 | #endif |
| 2951 | |
| 2952 | SKIP_WHITESPACE (); |
| 2953 | if (*input_line_pointer) |
| 2954 | as_bad (_("ignoring junk `%s' after expression"), |
| 2955 | input_line_pointer); |
| 2956 | #if GCC_ASM_O_HACK |
| 2957 | RESTORE_END_STRING (disp_end + 1); |
| 2958 | #endif |
| 2959 | RESTORE_END_STRING (disp_end); |
| 2960 | input_line_pointer = save_input_line_pointer; |
| 2961 | |
| 2962 | if (exp->X_op == O_absent || exp->X_op == O_big) |
| 2963 | { |
| 2964 | /* Missing or bad expr becomes absolute 0. */ |
| 2965 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
| 2966 | disp_start); |
| 2967 | exp->X_op = O_constant; |
| 2968 | exp->X_add_number = 0; |
| 2969 | exp->X_add_symbol = (symbolS *) 0; |
| 2970 | exp->X_op_symbol = (symbolS *) 0; |
| 2971 | } |
| 2972 | |
| 2973 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 2974 | if (exp->X_op != O_constant |
| 2975 | #ifdef BFD_ASSEMBLER |
| 2976 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
| 2977 | #endif |
| 2978 | && exp_seg != text_section |
| 2979 | && exp_seg != data_section |
| 2980 | && exp_seg != bss_section |
| 2981 | && exp_seg != undefined_section) |
| 2982 | { |
| 2983 | #ifdef BFD_ASSEMBLER |
| 2984 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
| 2985 | #else |
| 2986 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
| 2987 | #endif |
| 2988 | return 0; |
| 2989 | } |
| 2990 | #endif |
| 2991 | return 1; |
| 2992 | } |
| 2993 | |
| 2994 | static int i386_index_check PARAMS((const char *)); |
| 2995 | |
| 2996 | /* Make sure the memory operand we've been dealt is valid. |
| 2997 | Return 1 on success, 0 on a failure. */ |
| 2998 | |
| 2999 | static int |
| 3000 | i386_index_check (operand_string) |
| 3001 | const char *operand_string; |
| 3002 | { |
| 3003 | #if INFER_ADDR_PREFIX |
| 3004 | int fudged = 0; |
| 3005 | |
| 3006 | tryprefix: |
| 3007 | #endif |
| 3008 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) |
| 3009 | /* 16 bit mode checks. */ |
| 3010 | ? ((i.base_reg |
| 3011 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) |
| 3012 | != (Reg16|BaseIndex))) |
| 3013 | || (i.index_reg |
| 3014 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) |
| 3015 | != (Reg16|BaseIndex)) |
| 3016 | || ! (i.base_reg |
| 3017 | && i.base_reg->reg_num < 6 |
| 3018 | && i.index_reg->reg_num >= 6 |
| 3019 | && i.log2_scale_factor == 0)))) |
| 3020 | /* 32 bit mode checks. */ |
| 3021 | : ((i.base_reg |
| 3022 | && (i.base_reg->reg_type & Reg32) == 0) |
| 3023 | || (i.index_reg |
| 3024 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) |
| 3025 | != (Reg32|BaseIndex))))) |
| 3026 | { |
| 3027 | #if INFER_ADDR_PREFIX |
| 3028 | if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') |
| 3029 | { |
| 3030 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; |
| 3031 | i.prefixes += 1; |
| 3032 | /* Change the size of any displacement too. At most one of |
| 3033 | Disp16 or Disp32 is set. |
| 3034 | FIXME. There doesn't seem to be any real need for separate |
| 3035 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. |
| 3036 | Removing them would probably clean up the code quite a lot. */ |
| 3037 | if (i.types[this_operand] & (Disp16|Disp32)) |
| 3038 | i.types[this_operand] ^= (Disp16|Disp32); |
| 3039 | fudged = 1; |
| 3040 | goto tryprefix; |
| 3041 | } |
| 3042 | if (fudged) |
| 3043 | as_bad (_("`%s' is not a valid base/index expression"), |
| 3044 | operand_string); |
| 3045 | else |
| 3046 | #endif |
| 3047 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
| 3048 | operand_string, |
| 3049 | flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32"); |
| 3050 | return 0; |
| 3051 | } |
| 3052 | return 1; |
| 3053 | } |
| 3054 | |
| 3055 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
| 3056 | on error. */ |
| 3057 | |
| 3058 | static int |
| 3059 | i386_operand (operand_string) |
| 3060 | char *operand_string; |
| 3061 | { |
| 3062 | const reg_entry *r; |
| 3063 | char *end_op; |
| 3064 | char *op_string = operand_string; |
| 3065 | |
| 3066 | if (is_space_char (*op_string)) |
| 3067 | ++op_string; |
| 3068 | |
| 3069 | /* We check for an absolute prefix (differentiating, |
| 3070 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
| 3071 | if (*op_string == ABSOLUTE_PREFIX) |
| 3072 | { |
| 3073 | ++op_string; |
| 3074 | if (is_space_char (*op_string)) |
| 3075 | ++op_string; |
| 3076 | i.types[this_operand] |= JumpAbsolute; |
| 3077 | } |
| 3078 | |
| 3079 | /* Check if operand is a register. */ |
| 3080 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
| 3081 | && (r = parse_register (op_string, &end_op)) != NULL) |
| 3082 | { |
| 3083 | /* Check for a segment override by searching for ':' after a |
| 3084 | segment register. */ |
| 3085 | op_string = end_op; |
| 3086 | if (is_space_char (*op_string)) |
| 3087 | ++op_string; |
| 3088 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) |
| 3089 | { |
| 3090 | switch (r->reg_num) |
| 3091 | { |
| 3092 | case 0: |
| 3093 | i.seg[i.mem_operands] = &es; |
| 3094 | break; |
| 3095 | case 1: |
| 3096 | i.seg[i.mem_operands] = &cs; |
| 3097 | break; |
| 3098 | case 2: |
| 3099 | i.seg[i.mem_operands] = &ss; |
| 3100 | break; |
| 3101 | case 3: |
| 3102 | i.seg[i.mem_operands] = &ds; |
| 3103 | break; |
| 3104 | case 4: |
| 3105 | i.seg[i.mem_operands] = &fs; |
| 3106 | break; |
| 3107 | case 5: |
| 3108 | i.seg[i.mem_operands] = &gs; |
| 3109 | break; |
| 3110 | } |
| 3111 | |
| 3112 | /* Skip the ':' and whitespace. */ |
| 3113 | ++op_string; |
| 3114 | if (is_space_char (*op_string)) |
| 3115 | ++op_string; |
| 3116 | |
| 3117 | if (!is_digit_char (*op_string) |
| 3118 | && !is_identifier_char (*op_string) |
| 3119 | && *op_string != '(' |
| 3120 | && *op_string != ABSOLUTE_PREFIX) |
| 3121 | { |
| 3122 | as_bad (_("bad memory operand `%s'"), op_string); |
| 3123 | return 0; |
| 3124 | } |
| 3125 | /* Handle case of %es:*foo. */ |
| 3126 | if (*op_string == ABSOLUTE_PREFIX) |
| 3127 | { |
| 3128 | ++op_string; |
| 3129 | if (is_space_char (*op_string)) |
| 3130 | ++op_string; |
| 3131 | i.types[this_operand] |= JumpAbsolute; |
| 3132 | } |
| 3133 | goto do_memory_reference; |
| 3134 | } |
| 3135 | if (*op_string) |
| 3136 | { |
| 3137 | as_bad (_("junk `%s' after register"), op_string); |
| 3138 | return 0; |
| 3139 | } |
| 3140 | i.types[this_operand] |= r->reg_type & ~BaseIndex; |
| 3141 | i.op[this_operand].regs = r; |
| 3142 | i.reg_operands++; |
| 3143 | } |
| 3144 | else if (*op_string == REGISTER_PREFIX) |
| 3145 | { |
| 3146 | as_bad (_("bad register name `%s'"), op_string); |
| 3147 | return 0; |
| 3148 | } |
| 3149 | else if (*op_string == IMMEDIATE_PREFIX) |
| 3150 | { |
| 3151 | ++op_string; |
| 3152 | if (i.types[this_operand] & JumpAbsolute) |
| 3153 | { |
| 3154 | as_bad (_("immediate operand illegal with absolute jump")); |
| 3155 | return 0; |
| 3156 | } |
| 3157 | if (!i386_immediate (op_string)) |
| 3158 | return 0; |
| 3159 | } |
| 3160 | else if (is_digit_char (*op_string) |
| 3161 | || is_identifier_char (*op_string) |
| 3162 | || *op_string == '(' ) |
| 3163 | { |
| 3164 | /* This is a memory reference of some sort. */ |
| 3165 | char *base_string; |
| 3166 | |
| 3167 | /* Start and end of displacement string expression (if found). */ |
| 3168 | char *displacement_string_start; |
| 3169 | char *displacement_string_end; |
| 3170 | |
| 3171 | do_memory_reference: |
| 3172 | if ((i.mem_operands == 1 |
| 3173 | && (current_templates->start->opcode_modifier & IsString) == 0) |
| 3174 | || i.mem_operands == 2) |
| 3175 | { |
| 3176 | as_bad (_("too many memory references for `%s'"), |
| 3177 | current_templates->start->name); |
| 3178 | return 0; |
| 3179 | } |
| 3180 | |
| 3181 | /* Check for base index form. We detect the base index form by |
| 3182 | looking for an ')' at the end of the operand, searching |
| 3183 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' |
| 3184 | after the '('. */ |
| 3185 | base_string = op_string + strlen (op_string); |
| 3186 | |
| 3187 | --base_string; |
| 3188 | if (is_space_char (*base_string)) |
| 3189 | --base_string; |
| 3190 | |
| 3191 | /* If we only have a displacement, set-up for it to be parsed later. */ |
| 3192 | displacement_string_start = op_string; |
| 3193 | displacement_string_end = base_string + 1; |
| 3194 | |
| 3195 | if (*base_string == ')') |
| 3196 | { |
| 3197 | char *temp_string; |
| 3198 | unsigned int parens_balanced = 1; |
| 3199 | /* We've already checked that the number of left & right ()'s are |
| 3200 | equal, so this loop will not be infinite. */ |
| 3201 | do |
| 3202 | { |
| 3203 | base_string--; |
| 3204 | if (*base_string == ')') |
| 3205 | parens_balanced++; |
| 3206 | if (*base_string == '(') |
| 3207 | parens_balanced--; |
| 3208 | } |
| 3209 | while (parens_balanced); |
| 3210 | |
| 3211 | temp_string = base_string; |
| 3212 | |
| 3213 | /* Skip past '(' and whitespace. */ |
| 3214 | ++base_string; |
| 3215 | if (is_space_char (*base_string)) |
| 3216 | ++base_string; |
| 3217 | |
| 3218 | if (*base_string == ',' |
| 3219 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) |
| 3220 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) |
| 3221 | { |
| 3222 | displacement_string_end = temp_string; |
| 3223 | |
| 3224 | i.types[this_operand] |= BaseIndex; |
| 3225 | |
| 3226 | if (i.base_reg) |
| 3227 | { |
| 3228 | base_string = end_op; |
| 3229 | if (is_space_char (*base_string)) |
| 3230 | ++base_string; |
| 3231 | } |
| 3232 | |
| 3233 | /* There may be an index reg or scale factor here. */ |
| 3234 | if (*base_string == ',') |
| 3235 | { |
| 3236 | ++base_string; |
| 3237 | if (is_space_char (*base_string)) |
| 3238 | ++base_string; |
| 3239 | |
| 3240 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) |
| 3241 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) |
| 3242 | { |
| 3243 | base_string = end_op; |
| 3244 | if (is_space_char (*base_string)) |
| 3245 | ++base_string; |
| 3246 | if (*base_string == ',') |
| 3247 | { |
| 3248 | ++base_string; |
| 3249 | if (is_space_char (*base_string)) |
| 3250 | ++base_string; |
| 3251 | } |
| 3252 | else if (*base_string != ')' ) |
| 3253 | { |
| 3254 | as_bad (_("expecting `,' or `)' after index register in `%s'"), |
| 3255 | operand_string); |
| 3256 | return 0; |
| 3257 | } |
| 3258 | } |
| 3259 | else if (*base_string == REGISTER_PREFIX) |
| 3260 | { |
| 3261 | as_bad (_("bad register name `%s'"), base_string); |
| 3262 | return 0; |
| 3263 | } |
| 3264 | |
| 3265 | /* Check for scale factor. */ |
| 3266 | if (isdigit ((unsigned char) *base_string)) |
| 3267 | { |
| 3268 | if (!i386_scale (base_string)) |
| 3269 | return 0; |
| 3270 | |
| 3271 | ++base_string; |
| 3272 | if (is_space_char (*base_string)) |
| 3273 | ++base_string; |
| 3274 | if (*base_string != ')') |
| 3275 | { |
| 3276 | as_bad (_("expecting `)' after scale factor in `%s'"), |
| 3277 | operand_string); |
| 3278 | return 0; |
| 3279 | } |
| 3280 | } |
| 3281 | else if (!i.index_reg) |
| 3282 | { |
| 3283 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
| 3284 | *base_string); |
| 3285 | return 0; |
| 3286 | } |
| 3287 | } |
| 3288 | else if (*base_string != ')') |
| 3289 | { |
| 3290 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
| 3291 | operand_string); |
| 3292 | return 0; |
| 3293 | } |
| 3294 | } |
| 3295 | else if (*base_string == REGISTER_PREFIX) |
| 3296 | { |
| 3297 | as_bad (_("bad register name `%s'"), base_string); |
| 3298 | return 0; |
| 3299 | } |
| 3300 | } |
| 3301 | |
| 3302 | /* If there's an expression beginning the operand, parse it, |
| 3303 | assuming displacement_string_start and |
| 3304 | displacement_string_end are meaningful. */ |
| 3305 | if (displacement_string_start != displacement_string_end) |
| 3306 | { |
| 3307 | if (!i386_displacement (displacement_string_start, |
| 3308 | displacement_string_end)) |
| 3309 | return 0; |
| 3310 | } |
| 3311 | |
| 3312 | /* Special case for (%dx) while doing input/output op. */ |
| 3313 | if (i.base_reg |
| 3314 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) |
| 3315 | && i.index_reg == 0 |
| 3316 | && i.log2_scale_factor == 0 |
| 3317 | && i.seg[i.mem_operands] == 0 |
| 3318 | && (i.types[this_operand] & Disp) == 0) |
| 3319 | { |
| 3320 | i.types[this_operand] = InOutPortReg; |
| 3321 | return 1; |
| 3322 | } |
| 3323 | |
| 3324 | if (i386_index_check (operand_string) == 0) |
| 3325 | return 0; |
| 3326 | i.mem_operands++; |
| 3327 | } |
| 3328 | else |
| 3329 | { |
| 3330 | /* It's not a memory operand; argh! */ |
| 3331 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
| 3332 | output_invalid (*op_string), |
| 3333 | this_operand + 1, |
| 3334 | op_string); |
| 3335 | return 0; |
| 3336 | } |
| 3337 | return 1; /* Normal return. */ |
| 3338 | } |
| 3339 | \f |
| 3340 | /* md_estimate_size_before_relax() |
| 3341 | |
| 3342 | Called just before relax() for rs_machine_dependent frags. The x86 |
| 3343 | assembler uses these frags to handle variable size jump |
| 3344 | instructions. |
| 3345 | |
| 3346 | Any symbol that is now undefined will not become defined. |
| 3347 | Return the correct fr_subtype in the frag. |
| 3348 | Return the initial "guess for variable size of frag" to caller. |
| 3349 | The guess is actually the growth beyond the fixed part. Whatever |
| 3350 | we do to grow the fixed or variable part contributes to our |
| 3351 | returned value. */ |
| 3352 | |
| 3353 | int |
| 3354 | md_estimate_size_before_relax (fragP, segment) |
| 3355 | register fragS *fragP; |
| 3356 | register segT segment; |
| 3357 | { |
| 3358 | /* We've already got fragP->fr_subtype right; all we have to do is |
| 3359 | check for un-relaxable symbols. On an ELF system, we can't relax |
| 3360 | an externally visible symbol, because it may be overridden by a |
| 3361 | shared library. */ |
| 3362 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
| 3363 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3364 | || S_IS_EXTERNAL (fragP->fr_symbol) |
| 3365 | || S_IS_WEAK (fragP->fr_symbol) |
| 3366 | #endif |
| 3367 | ) |
| 3368 | { |
| 3369 | /* Symbol is undefined in this segment, or we need to keep a |
| 3370 | reloc so that weak symbols can be overridden. */ |
| 3371 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; |
| 3372 | #ifdef BFD_ASSEMBLER |
| 3373 | enum bfd_reloc_code_real reloc_type; |
| 3374 | #else |
| 3375 | int reloc_type; |
| 3376 | #endif |
| 3377 | unsigned char *opcode; |
| 3378 | int old_fr_fix; |
| 3379 | |
| 3380 | if (fragP->fr_var != NO_RELOC) |
| 3381 | reloc_type = fragP->fr_var; |
| 3382 | else if (size == 2) |
| 3383 | reloc_type = BFD_RELOC_16_PCREL; |
| 3384 | else |
| 3385 | reloc_type = BFD_RELOC_32_PCREL; |
| 3386 | |
| 3387 | old_fr_fix = fragP->fr_fix; |
| 3388 | opcode = (unsigned char *) fragP->fr_opcode; |
| 3389 | |
| 3390 | switch (opcode[0]) |
| 3391 | { |
| 3392 | case JUMP_PC_RELATIVE: |
| 3393 | /* Make jmp (0xeb) a dword displacement jump. */ |
| 3394 | opcode[0] = 0xe9; |
| 3395 | fragP->fr_fix += size; |
| 3396 | fix_new (fragP, old_fr_fix, size, |
| 3397 | fragP->fr_symbol, |
| 3398 | fragP->fr_offset, 1, |
| 3399 | reloc_type); |
| 3400 | break; |
| 3401 | |
| 3402 | default: |
| 3403 | /* This changes the byte-displacement jump 0x7N |
| 3404 | to the dword-displacement jump 0x0f,0x8N. */ |
| 3405 | opcode[1] = opcode[0] + 0x10; |
| 3406 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 3407 | /* We've added an opcode byte. */ |
| 3408 | fragP->fr_fix += 1 + size; |
| 3409 | fix_new (fragP, old_fr_fix + 1, size, |
| 3410 | fragP->fr_symbol, |
| 3411 | fragP->fr_offset, 1, |
| 3412 | reloc_type); |
| 3413 | break; |
| 3414 | } |
| 3415 | frag_wane (fragP); |
| 3416 | return fragP->fr_fix - old_fr_fix; |
| 3417 | } |
| 3418 | /* Guess a short jump. */ |
| 3419 | return 1; |
| 3420 | } |
| 3421 | |
| 3422 | /* Called after relax() is finished. |
| 3423 | |
| 3424 | In: Address of frag. |
| 3425 | fr_type == rs_machine_dependent. |
| 3426 | fr_subtype is what the address relaxed to. |
| 3427 | |
| 3428 | Out: Any fixSs and constants are set up. |
| 3429 | Caller will turn frag into a ".space 0". */ |
| 3430 | |
| 3431 | #ifndef BFD_ASSEMBLER |
| 3432 | void |
| 3433 | md_convert_frag (headers, sec, fragP) |
| 3434 | object_headers *headers ATTRIBUTE_UNUSED; |
| 3435 | segT sec ATTRIBUTE_UNUSED; |
| 3436 | register fragS *fragP; |
| 3437 | #else |
| 3438 | void |
| 3439 | md_convert_frag (abfd, sec, fragP) |
| 3440 | bfd *abfd ATTRIBUTE_UNUSED; |
| 3441 | segT sec ATTRIBUTE_UNUSED; |
| 3442 | register fragS *fragP; |
| 3443 | #endif |
| 3444 | { |
| 3445 | register unsigned char *opcode; |
| 3446 | unsigned char *where_to_put_displacement = NULL; |
| 3447 | offsetT target_address; |
| 3448 | offsetT opcode_address; |
| 3449 | unsigned int extension = 0; |
| 3450 | offsetT displacement_from_opcode_start; |
| 3451 | |
| 3452 | opcode = (unsigned char *) fragP->fr_opcode; |
| 3453 | |
| 3454 | /* Address we want to reach in file space. */ |
| 3455 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
| 3456 | #ifdef BFD_ASSEMBLER |
| 3457 | /* Not needed otherwise? */ |
| 3458 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
| 3459 | #endif |
| 3460 | |
| 3461 | /* Address opcode resides at in file space. */ |
| 3462 | opcode_address = fragP->fr_address + fragP->fr_fix; |
| 3463 | |
| 3464 | /* Displacement from opcode start to fill into instruction. */ |
| 3465 | displacement_from_opcode_start = target_address - opcode_address; |
| 3466 | |
| 3467 | switch (fragP->fr_subtype) |
| 3468 | { |
| 3469 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): |
| 3470 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): |
| 3471 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): |
| 3472 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): |
| 3473 | /* Don't have to change opcode. */ |
| 3474 | extension = 1; /* 1 opcode + 1 displacement */ |
| 3475 | where_to_put_displacement = &opcode[1]; |
| 3476 | break; |
| 3477 | |
| 3478 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
| 3479 | extension = 5; /* 2 opcode + 4 displacement */ |
| 3480 | opcode[1] = opcode[0] + 0x10; |
| 3481 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 3482 | where_to_put_displacement = &opcode[2]; |
| 3483 | break; |
| 3484 | |
| 3485 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): |
| 3486 | extension = 4; /* 1 opcode + 4 displacement */ |
| 3487 | opcode[0] = 0xe9; |
| 3488 | where_to_put_displacement = &opcode[1]; |
| 3489 | break; |
| 3490 | |
| 3491 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
| 3492 | extension = 3; /* 2 opcode + 2 displacement */ |
| 3493 | opcode[1] = opcode[0] + 0x10; |
| 3494 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 3495 | where_to_put_displacement = &opcode[2]; |
| 3496 | break; |
| 3497 | |
| 3498 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
| 3499 | extension = 2; /* 1 opcode + 2 displacement */ |
| 3500 | opcode[0] = 0xe9; |
| 3501 | where_to_put_displacement = &opcode[1]; |
| 3502 | break; |
| 3503 | |
| 3504 | default: |
| 3505 | BAD_CASE (fragP->fr_subtype); |
| 3506 | break; |
| 3507 | } |
| 3508 | /* Now put displacement after opcode. */ |
| 3509 | md_number_to_chars ((char *) where_to_put_displacement, |
| 3510 | (valueT) (displacement_from_opcode_start - extension), |
| 3511 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
| 3512 | fragP->fr_fix += extension; |
| 3513 | } |
| 3514 | \f |
| 3515 | /* Size of byte displacement jmp. */ |
| 3516 | int md_short_jump_size = 2; |
| 3517 | |
| 3518 | /* Size of dword displacement jmp. */ |
| 3519 | int md_long_jump_size = 5; |
| 3520 | |
| 3521 | /* Size of relocation record. */ |
| 3522 | const int md_reloc_size = 8; |
| 3523 | |
| 3524 | void |
| 3525 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) |
| 3526 | char *ptr; |
| 3527 | addressT from_addr, to_addr; |
| 3528 | fragS *frag ATTRIBUTE_UNUSED; |
| 3529 | symbolS *to_symbol ATTRIBUTE_UNUSED; |
| 3530 | { |
| 3531 | offsetT offset; |
| 3532 | |
| 3533 | offset = to_addr - (from_addr + 2); |
| 3534 | /* Opcode for byte-disp jump. */ |
| 3535 | md_number_to_chars (ptr, (valueT) 0xeb, 1); |
| 3536 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
| 3537 | } |
| 3538 | |
| 3539 | void |
| 3540 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) |
| 3541 | char *ptr; |
| 3542 | addressT from_addr, to_addr; |
| 3543 | fragS *frag ATTRIBUTE_UNUSED; |
| 3544 | symbolS *to_symbol ATTRIBUTE_UNUSED; |
| 3545 | { |
| 3546 | offsetT offset; |
| 3547 | |
| 3548 | offset = to_addr - (from_addr + 5); |
| 3549 | md_number_to_chars (ptr, (valueT) 0xe9, 1); |
| 3550 | md_number_to_chars (ptr + 1, (valueT) offset, 4); |
| 3551 | } |
| 3552 | \f |
| 3553 | /* Apply a fixup (fixS) to segment data, once it has been determined |
| 3554 | by our caller that we have all the info we need to fix it up. |
| 3555 | |
| 3556 | On the 386, immediates, displacements, and data pointers are all in |
| 3557 | the same (little-endian) format, so we don't need to care about which |
| 3558 | we are handling. */ |
| 3559 | |
| 3560 | int |
| 3561 | md_apply_fix3 (fixP, valp, seg) |
| 3562 | /* The fix we're to put in. */ |
| 3563 | fixS *fixP; |
| 3564 | |
| 3565 | /* Pointer to the value of the bits. */ |
| 3566 | valueT *valp; |
| 3567 | |
| 3568 | /* Segment fix is from. */ |
| 3569 | segT seg ATTRIBUTE_UNUSED; |
| 3570 | { |
| 3571 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
| 3572 | valueT value = *valp; |
| 3573 | |
| 3574 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
| 3575 | if (fixP->fx_pcrel) |
| 3576 | { |
| 3577 | switch (fixP->fx_r_type) |
| 3578 | { |
| 3579 | default: |
| 3580 | break; |
| 3581 | |
| 3582 | case BFD_RELOC_32: |
| 3583 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
| 3584 | break; |
| 3585 | case BFD_RELOC_16: |
| 3586 | fixP->fx_r_type = BFD_RELOC_16_PCREL; |
| 3587 | break; |
| 3588 | case BFD_RELOC_8: |
| 3589 | fixP->fx_r_type = BFD_RELOC_8_PCREL; |
| 3590 | break; |
| 3591 | } |
| 3592 | } |
| 3593 | |
| 3594 | /* This is a hack. There should be a better way to handle this. |
| 3595 | This covers for the fact that bfd_install_relocation will |
| 3596 | subtract the current location (for partial_inplace, PC relative |
| 3597 | relocations); see more below. */ |
| 3598 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
| 3599 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
| 3600 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
| 3601 | && fixP->fx_addsy) |
| 3602 | { |
| 3603 | #ifndef OBJ_AOUT |
| 3604 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 3605 | #ifdef TE_PE |
| 3606 | || OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 3607 | #endif |
| 3608 | ) |
| 3609 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
| 3610 | #endif |
| 3611 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3612 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 3613 | { |
| 3614 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
| 3615 | |
| 3616 | if ((fseg == seg |
| 3617 | || (symbol_section_p (fixP->fx_addsy) |
| 3618 | && fseg != absolute_section)) |
| 3619 | && ! S_IS_EXTERNAL (fixP->fx_addsy) |
| 3620 | && ! S_IS_WEAK (fixP->fx_addsy) |
| 3621 | && S_IS_DEFINED (fixP->fx_addsy) |
| 3622 | && ! S_IS_COMMON (fixP->fx_addsy)) |
| 3623 | { |
| 3624 | /* Yes, we add the values in twice. This is because |
| 3625 | bfd_perform_relocation subtracts them out again. I think |
| 3626 | bfd_perform_relocation is broken, but I don't dare change |
| 3627 | it. FIXME. */ |
| 3628 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
| 3629 | } |
| 3630 | } |
| 3631 | #endif |
| 3632 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 3633 | /* For some reason, the PE format does not store a section |
| 3634 | address offset for a PC relative symbol. */ |
| 3635 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
| 3636 | value += md_pcrel_from (fixP); |
| 3637 | #endif |
| 3638 | } |
| 3639 | |
| 3640 | /* Fix a few things - the dynamic linker expects certain values here, |
| 3641 | and we must not dissappoint it. */ |
| 3642 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3643 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 3644 | && fixP->fx_addsy) |
| 3645 | switch (fixP->fx_r_type) |
| 3646 | { |
| 3647 | case BFD_RELOC_386_PLT32: |
| 3648 | /* Make the jump instruction point to the address of the operand. At |
| 3649 | runtime we merely add the offset to the actual PLT entry. */ |
| 3650 | value = -4; |
| 3651 | break; |
| 3652 | case BFD_RELOC_386_GOTPC: |
| 3653 | |
| 3654 | /* This is tough to explain. We end up with this one if we have |
| 3655 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
| 3656 | * here is to obtain the absolute address of the GOT, and it is strongly |
| 3657 | * preferable from a performance point of view to avoid using a runtime |
| 3658 | * relocation for this. The actual sequence of instructions often look |
| 3659 | * something like: |
| 3660 | * |
| 3661 | * call .L66 |
| 3662 | * .L66: |
| 3663 | * popl %ebx |
| 3664 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx |
| 3665 | * |
| 3666 | * The call and pop essentially return the absolute address of |
| 3667 | * the label .L66 and store it in %ebx. The linker itself will |
| 3668 | * ultimately change the first operand of the addl so that %ebx points to |
| 3669 | * the GOT, but to keep things simple, the .o file must have this operand |
| 3670 | * set so that it generates not the absolute address of .L66, but the |
| 3671 | * absolute address of itself. This allows the linker itself simply |
| 3672 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be |
| 3673 | * added in, and the addend of the relocation is stored in the operand |
| 3674 | * field for the instruction itself. |
| 3675 | * |
| 3676 | * Our job here is to fix the operand so that it would add the correct |
| 3677 | * offset so that %ebx would point to itself. The thing that is tricky is |
| 3678 | * that .-.L66 will point to the beginning of the instruction, so we need |
| 3679 | * to further modify the operand so that it will point to itself. |
| 3680 | * There are other cases where you have something like: |
| 3681 | * |
| 3682 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
| 3683 | * |
| 3684 | * and here no correction would be required. Internally in the assembler |
| 3685 | * we treat operands of this form as not being pcrel since the '.' is |
| 3686 | * explicitly mentioned, and I wonder whether it would simplify matters |
| 3687 | * to do it this way. Who knows. In earlier versions of the PIC patches, |
| 3688 | * the pcrel_adjust field was used to store the correction, but since the |
| 3689 | * expression is not pcrel, I felt it would be confusing to do it this |
| 3690 | * way. */ |
| 3691 | |
| 3692 | value -= 1; |
| 3693 | break; |
| 3694 | case BFD_RELOC_386_GOT32: |
| 3695 | value = 0; /* Fully resolved at runtime. No addend. */ |
| 3696 | break; |
| 3697 | case BFD_RELOC_386_GOTOFF: |
| 3698 | break; |
| 3699 | |
| 3700 | case BFD_RELOC_VTABLE_INHERIT: |
| 3701 | case BFD_RELOC_VTABLE_ENTRY: |
| 3702 | fixP->fx_done = 0; |
| 3703 | return 1; |
| 3704 | |
| 3705 | default: |
| 3706 | break; |
| 3707 | } |
| 3708 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ |
| 3709 | *valp = value; |
| 3710 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ |
| 3711 | md_number_to_chars (p, value, fixP->fx_size); |
| 3712 | |
| 3713 | return 1; |
| 3714 | } |
| 3715 | \f |
| 3716 | #define MAX_LITTLENUMS 6 |
| 3717 | |
| 3718 | /* Turn the string pointed to by litP into a floating point constant |
| 3719 | of type TYPE, and emit the appropriate bytes. The number of |
| 3720 | LITTLENUMS emitted is stored in *SIZEP. An error message is |
| 3721 | returned, or NULL on OK. */ |
| 3722 | |
| 3723 | char * |
| 3724 | md_atof (type, litP, sizeP) |
| 3725 | int type; |
| 3726 | char *litP; |
| 3727 | int *sizeP; |
| 3728 | { |
| 3729 | int prec; |
| 3730 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 3731 | LITTLENUM_TYPE *wordP; |
| 3732 | char *t; |
| 3733 | |
| 3734 | switch (type) |
| 3735 | { |
| 3736 | case 'f': |
| 3737 | case 'F': |
| 3738 | prec = 2; |
| 3739 | break; |
| 3740 | |
| 3741 | case 'd': |
| 3742 | case 'D': |
| 3743 | prec = 4; |
| 3744 | break; |
| 3745 | |
| 3746 | case 'x': |
| 3747 | case 'X': |
| 3748 | prec = 5; |
| 3749 | break; |
| 3750 | |
| 3751 | default: |
| 3752 | *sizeP = 0; |
| 3753 | return _("Bad call to md_atof ()"); |
| 3754 | } |
| 3755 | t = atof_ieee (input_line_pointer, type, words); |
| 3756 | if (t) |
| 3757 | input_line_pointer = t; |
| 3758 | |
| 3759 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
| 3760 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with |
| 3761 | the bigendian 386. */ |
| 3762 | for (wordP = words + prec - 1; prec--;) |
| 3763 | { |
| 3764 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); |
| 3765 | litP += sizeof (LITTLENUM_TYPE); |
| 3766 | } |
| 3767 | return 0; |
| 3768 | } |
| 3769 | \f |
| 3770 | char output_invalid_buf[8]; |
| 3771 | |
| 3772 | static char * |
| 3773 | output_invalid (c) |
| 3774 | int c; |
| 3775 | { |
| 3776 | if (isprint (c)) |
| 3777 | sprintf (output_invalid_buf, "'%c'", c); |
| 3778 | else |
| 3779 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); |
| 3780 | return output_invalid_buf; |
| 3781 | } |
| 3782 | |
| 3783 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
| 3784 | |
| 3785 | static const reg_entry * |
| 3786 | parse_register (reg_string, end_op) |
| 3787 | char *reg_string; |
| 3788 | char **end_op; |
| 3789 | { |
| 3790 | char *s = reg_string; |
| 3791 | char *p; |
| 3792 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
| 3793 | const reg_entry *r; |
| 3794 | |
| 3795 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ |
| 3796 | if (*s == REGISTER_PREFIX) |
| 3797 | ++s; |
| 3798 | |
| 3799 | if (is_space_char (*s)) |
| 3800 | ++s; |
| 3801 | |
| 3802 | p = reg_name_given; |
| 3803 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
| 3804 | { |
| 3805 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
| 3806 | return (const reg_entry *) NULL; |
| 3807 | s++; |
| 3808 | } |
| 3809 | |
| 3810 | /* For naked regs, make sure that we are not dealing with an identifier. |
| 3811 | This prevents confusing an identifier like `eax_var' with register |
| 3812 | `eax'. */ |
| 3813 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) |
| 3814 | return (const reg_entry *) NULL; |
| 3815 | |
| 3816 | *end_op = s; |
| 3817 | |
| 3818 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); |
| 3819 | |
| 3820 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
| 3821 | if (r == i386_regtab /* %st is first entry of table */) |
| 3822 | { |
| 3823 | if (is_space_char (*s)) |
| 3824 | ++s; |
| 3825 | if (*s == '(') |
| 3826 | { |
| 3827 | ++s; |
| 3828 | if (is_space_char (*s)) |
| 3829 | ++s; |
| 3830 | if (*s >= '0' && *s <= '7') |
| 3831 | { |
| 3832 | r = &i386_float_regtab[*s - '0']; |
| 3833 | ++s; |
| 3834 | if (is_space_char (*s)) |
| 3835 | ++s; |
| 3836 | if (*s == ')') |
| 3837 | { |
| 3838 | *end_op = s + 1; |
| 3839 | return r; |
| 3840 | } |
| 3841 | } |
| 3842 | /* We have "%st(" then garbage. */ |
| 3843 | return (const reg_entry *) NULL; |
| 3844 | } |
| 3845 | } |
| 3846 | |
| 3847 | return r; |
| 3848 | } |
| 3849 | \f |
| 3850 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3851 | const char *md_shortopts = "kVQ:sq"; |
| 3852 | #else |
| 3853 | const char *md_shortopts = "q"; |
| 3854 | #endif |
| 3855 | struct option md_longopts[] = { |
| 3856 | {NULL, no_argument, NULL, 0} |
| 3857 | }; |
| 3858 | size_t md_longopts_size = sizeof (md_longopts); |
| 3859 | |
| 3860 | int |
| 3861 | md_parse_option (c, arg) |
| 3862 | int c; |
| 3863 | char *arg ATTRIBUTE_UNUSED; |
| 3864 | { |
| 3865 | switch (c) |
| 3866 | { |
| 3867 | case 'q': |
| 3868 | quiet_warnings = 1; |
| 3869 | break; |
| 3870 | |
| 3871 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3872 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
| 3873 | should be emitted or not. FIXME: Not implemented. */ |
| 3874 | case 'Q': |
| 3875 | break; |
| 3876 | |
| 3877 | /* -V: SVR4 argument to print version ID. */ |
| 3878 | case 'V': |
| 3879 | print_version_id (); |
| 3880 | break; |
| 3881 | |
| 3882 | /* -k: Ignore for FreeBSD compatibility. */ |
| 3883 | case 'k': |
| 3884 | break; |
| 3885 | |
| 3886 | case 's': |
| 3887 | /* -s: On i386 Solaris, this tells the native assembler to use |
| 3888 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
| 3889 | break; |
| 3890 | #endif |
| 3891 | |
| 3892 | default: |
| 3893 | return 0; |
| 3894 | } |
| 3895 | return 1; |
| 3896 | } |
| 3897 | |
| 3898 | void |
| 3899 | md_show_usage (stream) |
| 3900 | FILE *stream; |
| 3901 | { |
| 3902 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3903 | fprintf (stream, _("\ |
| 3904 | -Q ignored\n\ |
| 3905 | -V print assembler version number\n\ |
| 3906 | -k ignored\n\ |
| 3907 | -q quieten some warnings\n\ |
| 3908 | -s ignored\n")); |
| 3909 | #else |
| 3910 | fprintf (stream, _("\ |
| 3911 | -q quieten some warnings\n")); |
| 3912 | #endif |
| 3913 | } |
| 3914 | |
| 3915 | #ifdef BFD_ASSEMBLER |
| 3916 | #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \ |
| 3917 | || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \ |
| 3918 | || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) |
| 3919 | |
| 3920 | /* Pick the target format to use. */ |
| 3921 | |
| 3922 | const char * |
| 3923 | i386_target_format () |
| 3924 | { |
| 3925 | switch (OUTPUT_FLAVOR) |
| 3926 | { |
| 3927 | #ifdef OBJ_MAYBE_AOUT |
| 3928 | case bfd_target_aout_flavour: |
| 3929 | return AOUT_TARGET_FORMAT; |
| 3930 | #endif |
| 3931 | #ifdef OBJ_MAYBE_COFF |
| 3932 | case bfd_target_coff_flavour: |
| 3933 | return "coff-i386"; |
| 3934 | #endif |
| 3935 | #ifdef OBJ_MAYBE_ELF |
| 3936 | case bfd_target_elf_flavour: |
| 3937 | return "elf32-i386"; |
| 3938 | #endif |
| 3939 | default: |
| 3940 | abort (); |
| 3941 | return NULL; |
| 3942 | } |
| 3943 | } |
| 3944 | |
| 3945 | #endif /* OBJ_MAYBE_ more than one */ |
| 3946 | #endif /* BFD_ASSEMBLER */ |
| 3947 | \f |
| 3948 | symbolS * |
| 3949 | md_undefined_symbol (name) |
| 3950 | char *name; |
| 3951 | { |
| 3952 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
| 3953 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] |
| 3954 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] |
| 3955 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) |
| 3956 | { |
| 3957 | if (!GOT_symbol) |
| 3958 | { |
| 3959 | if (symbol_find (name)) |
| 3960 | as_bad (_("GOT already in symbol table")); |
| 3961 | GOT_symbol = symbol_new (name, undefined_section, |
| 3962 | (valueT) 0, &zero_address_frag); |
| 3963 | }; |
| 3964 | return GOT_symbol; |
| 3965 | } |
| 3966 | return 0; |
| 3967 | } |
| 3968 | |
| 3969 | /* Round up a section size to the appropriate boundary. */ |
| 3970 | |
| 3971 | valueT |
| 3972 | md_section_align (segment, size) |
| 3973 | segT segment ATTRIBUTE_UNUSED; |
| 3974 | valueT size; |
| 3975 | { |
| 3976 | #ifdef BFD_ASSEMBLER |
| 3977 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 3978 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) |
| 3979 | { |
| 3980 | /* For a.out, force the section size to be aligned. If we don't do |
| 3981 | this, BFD will align it for us, but it will not write out the |
| 3982 | final bytes of the section. This may be a bug in BFD, but it is |
| 3983 | easier to fix it here since that is how the other a.out targets |
| 3984 | work. */ |
| 3985 | int align; |
| 3986 | |
| 3987 | align = bfd_get_section_alignment (stdoutput, segment); |
| 3988 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); |
| 3989 | } |
| 3990 | #endif |
| 3991 | #endif |
| 3992 | |
| 3993 | return size; |
| 3994 | } |
| 3995 | |
| 3996 | /* On the i386, PC-relative offsets are relative to the start of the |
| 3997 | next instruction. That is, the address of the offset, plus its |
| 3998 | size, since the offset is always the last part of the insn. */ |
| 3999 | |
| 4000 | long |
| 4001 | md_pcrel_from (fixP) |
| 4002 | fixS *fixP; |
| 4003 | { |
| 4004 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
| 4005 | } |
| 4006 | |
| 4007 | #ifndef I386COFF |
| 4008 | |
| 4009 | static void |
| 4010 | s_bss (ignore) |
| 4011 | int ignore ATTRIBUTE_UNUSED; |
| 4012 | { |
| 4013 | register int temp; |
| 4014 | |
| 4015 | temp = get_absolute_expression (); |
| 4016 | subseg_set (bss_section, (subsegT) temp); |
| 4017 | demand_empty_rest_of_line (); |
| 4018 | } |
| 4019 | |
| 4020 | #endif |
| 4021 | |
| 4022 | #ifdef BFD_ASSEMBLER |
| 4023 | |
| 4024 | void |
| 4025 | i386_validate_fix (fixp) |
| 4026 | fixS *fixp; |
| 4027 | { |
| 4028 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) |
| 4029 | { |
| 4030 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
| 4031 | fixp->fx_subsy = 0; |
| 4032 | } |
| 4033 | } |
| 4034 | |
| 4035 | arelent * |
| 4036 | tc_gen_reloc (section, fixp) |
| 4037 | asection *section ATTRIBUTE_UNUSED; |
| 4038 | fixS *fixp; |
| 4039 | { |
| 4040 | arelent *rel; |
| 4041 | bfd_reloc_code_real_type code; |
| 4042 | |
| 4043 | switch (fixp->fx_r_type) |
| 4044 | { |
| 4045 | case BFD_RELOC_386_PLT32: |
| 4046 | case BFD_RELOC_386_GOT32: |
| 4047 | case BFD_RELOC_386_GOTOFF: |
| 4048 | case BFD_RELOC_386_GOTPC: |
| 4049 | case BFD_RELOC_RVA: |
| 4050 | case BFD_RELOC_VTABLE_ENTRY: |
| 4051 | case BFD_RELOC_VTABLE_INHERIT: |
| 4052 | code = fixp->fx_r_type; |
| 4053 | break; |
| 4054 | default: |
| 4055 | if (fixp->fx_pcrel) |
| 4056 | { |
| 4057 | switch (fixp->fx_size) |
| 4058 | { |
| 4059 | default: |
| 4060 | as_bad (_("can not do %d byte pc-relative relocation"), |
| 4061 | fixp->fx_size); |
| 4062 | code = BFD_RELOC_32_PCREL; |
| 4063 | break; |
| 4064 | case 1: code = BFD_RELOC_8_PCREL; break; |
| 4065 | case 2: code = BFD_RELOC_16_PCREL; break; |
| 4066 | case 4: code = BFD_RELOC_32_PCREL; break; |
| 4067 | } |
| 4068 | } |
| 4069 | else |
| 4070 | { |
| 4071 | switch (fixp->fx_size) |
| 4072 | { |
| 4073 | default: |
| 4074 | as_bad (_("can not do %d byte relocation"), fixp->fx_size); |
| 4075 | code = BFD_RELOC_32; |
| 4076 | break; |
| 4077 | case 1: code = BFD_RELOC_8; break; |
| 4078 | case 2: code = BFD_RELOC_16; break; |
| 4079 | case 4: code = BFD_RELOC_32; break; |
| 4080 | } |
| 4081 | } |
| 4082 | break; |
| 4083 | } |
| 4084 | |
| 4085 | if (code == BFD_RELOC_32 |
| 4086 | && GOT_symbol |
| 4087 | && fixp->fx_addsy == GOT_symbol) |
| 4088 | code = BFD_RELOC_386_GOTPC; |
| 4089 | |
| 4090 | rel = (arelent *) xmalloc (sizeof (arelent)); |
| 4091 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 4092 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 4093 | |
| 4094 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 4095 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the |
| 4096 | vtable entry to be used in the relocation's section offset. */ |
| 4097 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 4098 | rel->address = fixp->fx_offset; |
| 4099 | |
| 4100 | if (fixp->fx_pcrel) |
| 4101 | rel->addend = fixp->fx_addnumber; |
| 4102 | else |
| 4103 | rel->addend = 0; |
| 4104 | |
| 4105 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 4106 | if (rel->howto == NULL) |
| 4107 | { |
| 4108 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 4109 | _("cannot represent relocation type %s"), |
| 4110 | bfd_get_reloc_code_name (code)); |
| 4111 | /* Set howto to a garbage value so that we can keep going. */ |
| 4112 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); |
| 4113 | assert (rel->howto != NULL); |
| 4114 | } |
| 4115 | |
| 4116 | return rel; |
| 4117 | } |
| 4118 | |
| 4119 | #else /* ! BFD_ASSEMBLER */ |
| 4120 | |
| 4121 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) |
| 4122 | void |
| 4123 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) |
| 4124 | char *where; |
| 4125 | fixS *fixP; |
| 4126 | relax_addressT segment_address_in_file; |
| 4127 | { |
| 4128 | /* In: length of relocation (or of address) in chars: 1, 2 or 4. |
| 4129 | Out: GNU LD relocation length code: 0, 1, or 2. */ |
| 4130 | |
| 4131 | static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 }; |
| 4132 | long r_symbolnum; |
| 4133 | |
| 4134 | know (fixP->fx_addsy != NULL); |
| 4135 | |
| 4136 | md_number_to_chars (where, |
| 4137 | (valueT) (fixP->fx_frag->fr_address |
| 4138 | + fixP->fx_where - segment_address_in_file), |
| 4139 | 4); |
| 4140 | |
| 4141 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) |
| 4142 | ? S_GET_TYPE (fixP->fx_addsy) |
| 4143 | : fixP->fx_addsy->sy_number); |
| 4144 | |
| 4145 | where[6] = (r_symbolnum >> 16) & 0x0ff; |
| 4146 | where[5] = (r_symbolnum >> 8) & 0x0ff; |
| 4147 | where[4] = r_symbolnum & 0x0ff; |
| 4148 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) |
| 4149 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) |
| 4150 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); |
| 4151 | } |
| 4152 | |
| 4153 | #endif /* OBJ_AOUT or OBJ_BOUT. */ |
| 4154 | |
| 4155 | #if defined (I386COFF) |
| 4156 | |
| 4157 | short |
| 4158 | tc_coff_fix2rtype (fixP) |
| 4159 | fixS *fixP; |
| 4160 | { |
| 4161 | if (fixP->fx_r_type == R_IMAGEBASE) |
| 4162 | return R_IMAGEBASE; |
| 4163 | |
| 4164 | return (fixP->fx_pcrel ? |
| 4165 | (fixP->fx_size == 1 ? R_PCRBYTE : |
| 4166 | fixP->fx_size == 2 ? R_PCRWORD : |
| 4167 | R_PCRLONG) : |
| 4168 | (fixP->fx_size == 1 ? R_RELBYTE : |
| 4169 | fixP->fx_size == 2 ? R_RELWORD : |
| 4170 | R_DIR32)); |
| 4171 | } |
| 4172 | |
| 4173 | int |
| 4174 | tc_coff_sizemachdep (frag) |
| 4175 | fragS *frag; |
| 4176 | { |
| 4177 | if (frag->fr_next) |
| 4178 | return (frag->fr_next->fr_address - frag->fr_address); |
| 4179 | else |
| 4180 | return 0; |
| 4181 | } |
| 4182 | |
| 4183 | #endif /* I386COFF */ |
| 4184 | |
| 4185 | #endif /* ! BFD_ASSEMBLER */ |
| 4186 | \f |
| 4187 | /* Parse operands using Intel syntax. This implements a recursive descent |
| 4188 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 |
| 4189 | Programmer's Guide. |
| 4190 | |
| 4191 | FIXME: We do not recognize the full operand grammar defined in the MASM |
| 4192 | documentation. In particular, all the structure/union and |
| 4193 | high-level macro operands are missing. |
| 4194 | |
| 4195 | Uppercase words are terminals, lower case words are non-terminals. |
| 4196 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical |
| 4197 | bars '|' denote choices. Most grammar productions are implemented in |
| 4198 | functions called 'intel_<production>'. |
| 4199 | |
| 4200 | Initial production is 'expr'. |
| 4201 | |
| 4202 | addOp + | - |
| 4203 | |
| 4204 | alpha [a-zA-Z] |
| 4205 | |
| 4206 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH |
| 4207 | |
| 4208 | constant digits [[ radixOverride ]] |
| 4209 | |
| 4210 | dataType BYTE | WORD | DWORD | QWORD | XWORD |
| 4211 | |
| 4212 | digits decdigit |
| 4213 | | digits decdigit |
| 4214 | | digits hexdigit |
| 4215 | |
| 4216 | decdigit [0-9] |
| 4217 | |
| 4218 | e05 e05 addOp e06 |
| 4219 | | e06 |
| 4220 | |
| 4221 | e06 e06 mulOp e09 |
| 4222 | | e09 |
| 4223 | |
| 4224 | e09 OFFSET e10 |
| 4225 | | e09 PTR e10 |
| 4226 | | e09 : e10 |
| 4227 | | e10 |
| 4228 | |
| 4229 | e10 e10 [ expr ] |
| 4230 | | e11 |
| 4231 | |
| 4232 | e11 ( expr ) |
| 4233 | | [ expr ] |
| 4234 | | constant |
| 4235 | | dataType |
| 4236 | | id |
| 4237 | | $ |
| 4238 | | register |
| 4239 | |
| 4240 | => expr SHORT e05 |
| 4241 | | e05 |
| 4242 | |
| 4243 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX |
| 4244 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
| 4245 | |
| 4246 | hexdigit a | b | c | d | e | f |
| 4247 | | A | B | C | D | E | F |
| 4248 | |
| 4249 | id alpha |
| 4250 | | id alpha |
| 4251 | | id decdigit |
| 4252 | |
| 4253 | mulOp * | / | MOD |
| 4254 | |
| 4255 | quote " | ' |
| 4256 | |
| 4257 | register specialRegister |
| 4258 | | gpRegister |
| 4259 | | byteRegister |
| 4260 | |
| 4261 | segmentRegister CS | DS | ES | FS | GS | SS |
| 4262 | |
| 4263 | specialRegister CR0 | CR2 | CR3 |
| 4264 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
| 4265 | | TR3 | TR4 | TR5 | TR6 | TR7 |
| 4266 | |
| 4267 | We simplify the grammar in obvious places (e.g., register parsing is |
| 4268 | done by calling parse_register) and eliminate immediate left recursion |
| 4269 | to implement a recursive-descent parser. |
| 4270 | |
| 4271 | expr SHORT e05 |
| 4272 | | e05 |
| 4273 | |
| 4274 | e05 e06 e05' |
| 4275 | |
| 4276 | e05' addOp e06 e05' |
| 4277 | | Empty |
| 4278 | |
| 4279 | e06 e09 e06' |
| 4280 | |
| 4281 | e06' mulOp e09 e06' |
| 4282 | | Empty |
| 4283 | |
| 4284 | e09 OFFSET e10 e09' |
| 4285 | | e10 e09' |
| 4286 | |
| 4287 | e09' PTR e10 e09' |
| 4288 | | : e10 e09' |
| 4289 | | Empty |
| 4290 | |
| 4291 | e10 e11 e10' |
| 4292 | |
| 4293 | e10' [ expr ] e10' |
| 4294 | | Empty |
| 4295 | |
| 4296 | e11 ( expr ) |
| 4297 | | [ expr ] |
| 4298 | | BYTE |
| 4299 | | WORD |
| 4300 | | DWORD |
| 4301 | | QWORD |
| 4302 | | XWORD |
| 4303 | | . |
| 4304 | | $ |
| 4305 | | register |
| 4306 | | id |
| 4307 | | constant */ |
| 4308 | |
| 4309 | /* Parsing structure for the intel syntax parser. Used to implement the |
| 4310 | semantic actions for the operand grammar. */ |
| 4311 | struct intel_parser_s |
| 4312 | { |
| 4313 | char *op_string; /* The string being parsed. */ |
| 4314 | int got_a_float; /* Whether the operand is a float. */ |
| 4315 | int op_modifier; /* Operand modifier. */ |
| 4316 | int is_mem; /* 1 if operand is memory reference. */ |
| 4317 | const reg_entry *reg; /* Last register reference found. */ |
| 4318 | char *disp; /* Displacement string being built. */ |
| 4319 | }; |
| 4320 | |
| 4321 | static struct intel_parser_s intel_parser; |
| 4322 | |
| 4323 | /* Token structure for parsing intel syntax. */ |
| 4324 | struct intel_token |
| 4325 | { |
| 4326 | int code; /* Token code. */ |
| 4327 | const reg_entry *reg; /* Register entry for register tokens. */ |
| 4328 | char *str; /* String representation. */ |
| 4329 | }; |
| 4330 | |
| 4331 | static struct intel_token cur_token, prev_token; |
| 4332 | |
| 4333 | /* Token codes for the intel parser. */ |
| 4334 | #define T_NIL -1 |
| 4335 | #define T_CONST 1 |
| 4336 | #define T_REG 2 |
| 4337 | #define T_BYTE 3 |
| 4338 | #define T_WORD 4 |
| 4339 | #define T_DWORD 5 |
| 4340 | #define T_QWORD 6 |
| 4341 | #define T_XWORD 7 |
| 4342 | #define T_SHORT 8 |
| 4343 | #define T_OFFSET 9 |
| 4344 | #define T_PTR 10 |
| 4345 | #define T_ID 11 |
| 4346 | |
| 4347 | /* Prototypes for intel parser functions. */ |
| 4348 | static int intel_match_token PARAMS ((int code)); |
| 4349 | static void intel_get_token PARAMS ((void)); |
| 4350 | static void intel_putback_token PARAMS ((void)); |
| 4351 | static int intel_expr PARAMS ((void)); |
| 4352 | static int intel_e05 PARAMS ((void)); |
| 4353 | static int intel_e05_1 PARAMS ((void)); |
| 4354 | static int intel_e06 PARAMS ((void)); |
| 4355 | static int intel_e06_1 PARAMS ((void)); |
| 4356 | static int intel_e09 PARAMS ((void)); |
| 4357 | static int intel_e09_1 PARAMS ((void)); |
| 4358 | static int intel_e10 PARAMS ((void)); |
| 4359 | static int intel_e10_1 PARAMS ((void)); |
| 4360 | static int intel_e11 PARAMS ((void)); |
| 4361 | |
| 4362 | static int |
| 4363 | i386_intel_operand (operand_string, got_a_float) |
| 4364 | char *operand_string; |
| 4365 | int got_a_float; |
| 4366 | { |
| 4367 | int ret; |
| 4368 | char *p; |
| 4369 | |
| 4370 | /* Initialize token holders. */ |
| 4371 | cur_token.code = prev_token.code = T_NIL; |
| 4372 | cur_token.reg = prev_token.reg = NULL; |
| 4373 | cur_token.str = prev_token.str = NULL; |
| 4374 | |
| 4375 | /* Initialize parser structure. */ |
| 4376 | p = intel_parser.op_string = (char *)malloc (strlen (operand_string) + 1); |
| 4377 | if (p == NULL) |
| 4378 | abort (); |
| 4379 | strcpy (intel_parser.op_string, operand_string); |
| 4380 | intel_parser.got_a_float = got_a_float; |
| 4381 | intel_parser.op_modifier = -1; |
| 4382 | intel_parser.is_mem = 0; |
| 4383 | intel_parser.reg = NULL; |
| 4384 | intel_parser.disp = (char *)malloc (strlen (operand_string) + 1); |
| 4385 | if (intel_parser.disp == NULL) |
| 4386 | abort (); |
| 4387 | intel_parser.disp[0] = '\0'; |
| 4388 | |
| 4389 | /* Read the first token and start the parser. */ |
| 4390 | intel_get_token (); |
| 4391 | ret = intel_expr (); |
| 4392 | |
| 4393 | if (ret) |
| 4394 | { |
| 4395 | /* If we found a memory reference, hand it over to i386_displacement |
| 4396 | to fill in the rest of the operand fields. */ |
| 4397 | if (intel_parser.is_mem) |
| 4398 | { |
| 4399 | if ((i.mem_operands == 1 |
| 4400 | && (current_templates->start->opcode_modifier & IsString) == 0) |
| 4401 | || i.mem_operands == 2) |
| 4402 | { |
| 4403 | as_bad (_("too many memory references for '%s'"), |
| 4404 | current_templates->start->name); |
| 4405 | ret = 0; |
| 4406 | } |
| 4407 | else |
| 4408 | { |
| 4409 | char *s = intel_parser.disp; |
| 4410 | i.mem_operands++; |
| 4411 | |
| 4412 | /* Add the displacement expression. */ |
| 4413 | if (*s != '\0') |
| 4414 | ret = i386_displacement (s, s + strlen (s)) |
| 4415 | && i386_index_check (s); |
| 4416 | } |
| 4417 | } |
| 4418 | |
| 4419 | /* Constant and OFFSET expressions are handled by i386_immediate. */ |
| 4420 | else if (intel_parser.op_modifier == OFFSET_FLAT |
| 4421 | || intel_parser.reg == NULL) |
| 4422 | ret = i386_immediate (intel_parser.disp); |
| 4423 | } |
| 4424 | |
| 4425 | free (p); |
| 4426 | free (intel_parser.disp); |
| 4427 | |
| 4428 | return ret; |
| 4429 | } |
| 4430 | |
| 4431 | /* expr SHORT e05 |
| 4432 | | e05 */ |
| 4433 | static int |
| 4434 | intel_expr () |
| 4435 | { |
| 4436 | /* expr SHORT e05 */ |
| 4437 | if (cur_token.code == T_SHORT) |
| 4438 | { |
| 4439 | intel_parser.op_modifier = SHORT; |
| 4440 | intel_match_token (T_SHORT); |
| 4441 | |
| 4442 | return (intel_e05 ()); |
| 4443 | } |
| 4444 | |
| 4445 | /* expr e05 */ |
| 4446 | else |
| 4447 | return intel_e05 (); |
| 4448 | } |
| 4449 | |
| 4450 | /* e05 e06 e05' |
| 4451 | |
| 4452 | e05' addOp e06 e05' |
| 4453 | | Empty */ |
| 4454 | static int |
| 4455 | intel_e05 () |
| 4456 | { |
| 4457 | return (intel_e06 () && intel_e05_1 ()); |
| 4458 | } |
| 4459 | |
| 4460 | static int |
| 4461 | intel_e05_1 () |
| 4462 | { |
| 4463 | /* e05' addOp e06 e05' */ |
| 4464 | if (cur_token.code == '+' || cur_token.code == '-') |
| 4465 | { |
| 4466 | strcat (intel_parser.disp, cur_token.str); |
| 4467 | intel_match_token (cur_token.code); |
| 4468 | |
| 4469 | return (intel_e06 () && intel_e05_1 ()); |
| 4470 | } |
| 4471 | |
| 4472 | /* e05' Empty */ |
| 4473 | else |
| 4474 | return 1; |
| 4475 | } |
| 4476 | |
| 4477 | /* e06 e09 e06' |
| 4478 | |
| 4479 | e06' mulOp e09 e06' |
| 4480 | | Empty */ |
| 4481 | static int |
| 4482 | intel_e06 () |
| 4483 | { |
| 4484 | return (intel_e09 () && intel_e06_1 ()); |
| 4485 | } |
| 4486 | |
| 4487 | static int |
| 4488 | intel_e06_1 () |
| 4489 | { |
| 4490 | /* e06' mulOp e09 e06' */ |
| 4491 | if (cur_token.code == '*' || cur_token.code == '/') |
| 4492 | { |
| 4493 | strcat (intel_parser.disp, cur_token.str); |
| 4494 | intel_match_token (cur_token.code); |
| 4495 | |
| 4496 | return (intel_e09 () && intel_e06_1 ()); |
| 4497 | } |
| 4498 | |
| 4499 | /* e06' Empty */ |
| 4500 | else |
| 4501 | return 1; |
| 4502 | } |
| 4503 | |
| 4504 | /* e09 OFFSET e10 e09' |
| 4505 | | e10 e09' |
| 4506 | |
| 4507 | e09' PTR e10 e09' |
| 4508 | | : e10 e09' |
| 4509 | | Empty */ |
| 4510 | static int |
| 4511 | intel_e09 () |
| 4512 | { |
| 4513 | /* e09 OFFSET e10 e09' */ |
| 4514 | if (cur_token.code == T_OFFSET) |
| 4515 | { |
| 4516 | intel_parser.is_mem = 0; |
| 4517 | intel_parser.op_modifier = OFFSET_FLAT; |
| 4518 | intel_match_token (T_OFFSET); |
| 4519 | |
| 4520 | return (intel_e10 () && intel_e09_1 ()); |
| 4521 | } |
| 4522 | |
| 4523 | /* e09 e10 e09' */ |
| 4524 | else |
| 4525 | return (intel_e10 () && intel_e09_1 ()); |
| 4526 | } |
| 4527 | |
| 4528 | static int |
| 4529 | intel_e09_1 () |
| 4530 | { |
| 4531 | /* e09' PTR e10 e09' */ |
| 4532 | if (cur_token.code == T_PTR) |
| 4533 | { |
| 4534 | if (prev_token.code == T_BYTE) |
| 4535 | i.suffix = BYTE_MNEM_SUFFIX; |
| 4536 | |
| 4537 | else if (prev_token.code == T_WORD) |
| 4538 | { |
| 4539 | if (intel_parser.got_a_float == 2) /* "fi..." */ |
| 4540 | i.suffix = SHORT_MNEM_SUFFIX; |
| 4541 | else |
| 4542 | i.suffix = WORD_MNEM_SUFFIX; |
| 4543 | } |
| 4544 | |
| 4545 | else if (prev_token.code == T_DWORD) |
| 4546 | { |
| 4547 | if (intel_parser.got_a_float == 1) /* "f..." */ |
| 4548 | i.suffix = SHORT_MNEM_SUFFIX; |
| 4549 | else |
| 4550 | i.suffix = LONG_MNEM_SUFFIX; |
| 4551 | } |
| 4552 | |
| 4553 | else if (prev_token.code == T_QWORD) |
| 4554 | i.suffix = DWORD_MNEM_SUFFIX; |
| 4555 | |
| 4556 | else if (prev_token.code == T_XWORD) |
| 4557 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; |
| 4558 | |
| 4559 | else |
| 4560 | { |
| 4561 | as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str); |
| 4562 | return 0; |
| 4563 | } |
| 4564 | |
| 4565 | intel_match_token (T_PTR); |
| 4566 | |
| 4567 | return (intel_e10 () && intel_e09_1 ()); |
| 4568 | } |
| 4569 | |
| 4570 | /* e09 : e10 e09' */ |
| 4571 | else if (cur_token.code == ':') |
| 4572 | { |
| 4573 | intel_parser.is_mem = 1; |
| 4574 | |
| 4575 | return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); |
| 4576 | } |
| 4577 | |
| 4578 | /* e09' Empty */ |
| 4579 | else |
| 4580 | return 1; |
| 4581 | } |
| 4582 | |
| 4583 | /* e10 e11 e10' |
| 4584 | |
| 4585 | e10' [ expr ] e10' |
| 4586 | | Empty */ |
| 4587 | static int |
| 4588 | intel_e10 () |
| 4589 | { |
| 4590 | return (intel_e11 () && intel_e10_1 ()); |
| 4591 | } |
| 4592 | |
| 4593 | static int |
| 4594 | intel_e10_1 () |
| 4595 | { |
| 4596 | /* e10' [ expr ] e10' */ |
| 4597 | if (cur_token.code == '[') |
| 4598 | { |
| 4599 | intel_match_token ('['); |
| 4600 | intel_parser.is_mem = 1; |
| 4601 | |
| 4602 | /* Add a '+' to the displacement string if necessary. */ |
| 4603 | if (*intel_parser.disp != '\0') |
| 4604 | strcat (intel_parser.disp, "+"); |
| 4605 | |
| 4606 | return (intel_expr () && intel_match_token (']') && intel_e10_1 ()); |
| 4607 | } |
| 4608 | |
| 4609 | /* e10' Empty */ |
| 4610 | else |
| 4611 | return 1; |
| 4612 | } |
| 4613 | |
| 4614 | /* e11 ( expr ) |
| 4615 | | [ expr ] |
| 4616 | | BYTE |
| 4617 | | WORD |
| 4618 | | DWORD |
| 4619 | | QWORD |
| 4620 | | XWORD |
| 4621 | | $ |
| 4622 | | . |
| 4623 | | register |
| 4624 | | id |
| 4625 | | constant */ |
| 4626 | static int |
| 4627 | intel_e11 () |
| 4628 | { |
| 4629 | /* e11 ( expr ) */ |
| 4630 | if (cur_token.code == '(') |
| 4631 | { |
| 4632 | intel_match_token ('('); |
| 4633 | strcat (intel_parser.disp, "("); |
| 4634 | |
| 4635 | if (intel_expr () && intel_match_token (')')) |
| 4636 | { |
| 4637 | strcat (intel_parser.disp, ")"); |
| 4638 | return 1; |
| 4639 | } |
| 4640 | else |
| 4641 | return 0; |
| 4642 | } |
| 4643 | |
| 4644 | /* e11 [ expr ] */ |
| 4645 | else if (cur_token.code == '[') |
| 4646 | { |
| 4647 | intel_match_token ('['); |
| 4648 | intel_parser.is_mem = 1; |
| 4649 | |
| 4650 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
| 4651 | if (current_templates->start->opcode_modifier & Jump |
| 4652 | || current_templates->start->opcode_modifier & JumpDword |
| 4653 | || current_templates->start->opcode_modifier & JumpByte |
| 4654 | || current_templates->start->opcode_modifier & JumpInterSegment) |
| 4655 | i.types[this_operand] |= JumpAbsolute; |
| 4656 | |
| 4657 | /* Add a '+' to the displacement string if necessary. */ |
| 4658 | if (*intel_parser.disp != '\0') |
| 4659 | strcat (intel_parser.disp, "+"); |
| 4660 | |
| 4661 | return (intel_expr () && intel_match_token (']')); |
| 4662 | } |
| 4663 | |
| 4664 | /* e11 BYTE |
| 4665 | | WORD |
| 4666 | | DWORD |
| 4667 | | QWORD |
| 4668 | | XWORD */ |
| 4669 | else if (cur_token.code == T_BYTE |
| 4670 | || cur_token.code == T_WORD |
| 4671 | || cur_token.code == T_DWORD |
| 4672 | || cur_token.code == T_QWORD |
| 4673 | || cur_token.code == T_XWORD) |
| 4674 | { |
| 4675 | intel_match_token (cur_token.code); |
| 4676 | |
| 4677 | return 1; |
| 4678 | } |
| 4679 | |
| 4680 | /* e11 $ |
| 4681 | | . */ |
| 4682 | else if (cur_token.code == '$' || cur_token.code == '.') |
| 4683 | { |
| 4684 | strcat (intel_parser.disp, cur_token.str); |
| 4685 | intel_match_token (cur_token.code); |
| 4686 | intel_parser.is_mem = 1; |
| 4687 | |
| 4688 | return 1; |
| 4689 | } |
| 4690 | |
| 4691 | /* e11 register */ |
| 4692 | else if (cur_token.code == T_REG) |
| 4693 | { |
| 4694 | const reg_entry *reg = intel_parser.reg = cur_token.reg; |
| 4695 | |
| 4696 | intel_match_token (T_REG); |
| 4697 | |
| 4698 | /* Check for segment change. */ |
| 4699 | if (cur_token.code == ':') |
| 4700 | { |
| 4701 | if (reg->reg_type & (SReg2 | SReg3)) |
| 4702 | { |
| 4703 | switch (reg->reg_num) |
| 4704 | { |
| 4705 | case 0: |
| 4706 | i.seg[i.mem_operands] = &es; |
| 4707 | break; |
| 4708 | case 1: |
| 4709 | i.seg[i.mem_operands] = &cs; |
| 4710 | break; |
| 4711 | case 2: |
| 4712 | i.seg[i.mem_operands] = &ss; |
| 4713 | break; |
| 4714 | case 3: |
| 4715 | i.seg[i.mem_operands] = &ds; |
| 4716 | break; |
| 4717 | case 4: |
| 4718 | i.seg[i.mem_operands] = &fs; |
| 4719 | break; |
| 4720 | case 5: |
| 4721 | i.seg[i.mem_operands] = &gs; |
| 4722 | break; |
| 4723 | } |
| 4724 | } |
| 4725 | else |
| 4726 | { |
| 4727 | as_bad (_("`%s' is not a valid segment register"), reg->reg_name); |
| 4728 | return 0; |
| 4729 | } |
| 4730 | } |
| 4731 | |
| 4732 | /* Not a segment register. Check for register scaling. */ |
| 4733 | else if (cur_token.code == '*') |
| 4734 | { |
| 4735 | if (!intel_parser.is_mem) |
| 4736 | { |
| 4737 | as_bad (_("Register scaling only allowed in memory operands.")); |
| 4738 | return 0; |
| 4739 | } |
| 4740 | |
| 4741 | /* What follows must be a valid scale. */ |
| 4742 | if (intel_match_token ('*') |
| 4743 | && strchr ("01248", *cur_token.str)) |
| 4744 | { |
| 4745 | i.index_reg = reg; |
| 4746 | i.types[this_operand] |= BaseIndex; |
| 4747 | |
| 4748 | /* Set the scale after setting the register (otherwise, |
| 4749 | i386_scale will complain) */ |
| 4750 | i386_scale (cur_token.str); |
| 4751 | intel_match_token (T_CONST); |
| 4752 | } |
| 4753 | else |
| 4754 | { |
| 4755 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
| 4756 | cur_token.str); |
| 4757 | return 0; |
| 4758 | } |
| 4759 | } |
| 4760 | |
| 4761 | /* No scaling. If this is a memory operand, the register is either a |
| 4762 | base register (first occurrence) or an index register (second |
| 4763 | occurrence). */ |
| 4764 | else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) |
| 4765 | { |
| 4766 | if (i.base_reg && i.index_reg) |
| 4767 | { |
| 4768 | as_bad (_("Too many register references in memory operand.\n")); |
| 4769 | return 0; |
| 4770 | } |
| 4771 | |
| 4772 | if (i.base_reg == NULL) |
| 4773 | i.base_reg = reg; |
| 4774 | else |
| 4775 | i.index_reg = reg; |
| 4776 | |
| 4777 | i.types[this_operand] |= BaseIndex; |
| 4778 | } |
| 4779 | |
| 4780 | /* Offset modifier. Add the register to the displacement string to be |
| 4781 | parsed as an immediate expression after we're done. */ |
| 4782 | else if (intel_parser.op_modifier == OFFSET_FLAT) |
| 4783 | strcat (intel_parser.disp, reg->reg_name); |
| 4784 | |
| 4785 | /* It's neither base nor index nor offset. */ |
| 4786 | else |
| 4787 | { |
| 4788 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; |
| 4789 | i.op[this_operand].regs = reg; |
| 4790 | i.reg_operands++; |
| 4791 | } |
| 4792 | |
| 4793 | /* Since registers are not part of the displacement string (except |
| 4794 | when we're parsing offset operands), we may need to remove any |
| 4795 | preceding '+' from the displacement string. */ |
| 4796 | if (*intel_parser.disp != '\0' |
| 4797 | && intel_parser.op_modifier != OFFSET_FLAT) |
| 4798 | { |
| 4799 | char *s = intel_parser.disp; |
| 4800 | s += strlen (s) - 1; |
| 4801 | if (*s == '+') |
| 4802 | *s = '\0'; |
| 4803 | } |
| 4804 | |
| 4805 | return 1; |
| 4806 | } |
| 4807 | |
| 4808 | /* e11 id */ |
| 4809 | else if (cur_token.code == T_ID) |
| 4810 | { |
| 4811 | /* Add the identifier to the displacement string. */ |
| 4812 | strcat (intel_parser.disp, cur_token.str); |
| 4813 | intel_match_token (T_ID); |
| 4814 | |
| 4815 | /* The identifier represents a memory reference only if it's not |
| 4816 | preceded by an offset modifier. */ |
| 4817 | if (intel_parser.op_modifier != OFFSET_FLAT |
| 4818 | && intel_parser.op_modifier != FLAT) |
| 4819 | intel_parser.is_mem = 1; |
| 4820 | |
| 4821 | return 1; |
| 4822 | } |
| 4823 | |
| 4824 | /* e11 constant */ |
| 4825 | else if (cur_token.code == T_CONST |
| 4826 | || cur_token.code == '-' |
| 4827 | || cur_token.code == '+') |
| 4828 | { |
| 4829 | char *save_str; |
| 4830 | |
| 4831 | /* Allow constants that start with `+' or `-'. */ |
| 4832 | if (cur_token.code == '-' || cur_token.code == '+') |
| 4833 | { |
| 4834 | strcat (intel_parser.disp, cur_token.str); |
| 4835 | intel_match_token (cur_token.code); |
| 4836 | if (cur_token.code != T_CONST) |
| 4837 | { |
| 4838 | as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"), |
| 4839 | cur_token.str); |
| 4840 | return 0; |
| 4841 | } |
| 4842 | } |
| 4843 | |
| 4844 | save_str = (char *)malloc (strlen (cur_token.str) + 1); |
| 4845 | if (save_str == NULL) |
| 4846 | abort (); |
| 4847 | strcpy (save_str, cur_token.str); |
| 4848 | |
| 4849 | /* Get the next token to check for register scaling. */ |
| 4850 | intel_match_token (cur_token.code); |
| 4851 | |
| 4852 | /* Check if this constant is a scaling factor for an index register. */ |
| 4853 | if (cur_token.code == '*') |
| 4854 | { |
| 4855 | if (intel_match_token ('*') && cur_token.code == T_REG) |
| 4856 | { |
| 4857 | if (!intel_parser.is_mem) |
| 4858 | { |
| 4859 | as_bad (_("Register scaling only allowed in memory operands.")); |
| 4860 | return 0; |
| 4861 | } |
| 4862 | |
| 4863 | /* The constant is followed by `* reg', so it must be |
| 4864 | a valid scale. */ |
| 4865 | if (strchr ("01248", *save_str)) |
| 4866 | { |
| 4867 | i.index_reg = cur_token.reg; |
| 4868 | i.types[this_operand] |= BaseIndex; |
| 4869 | |
| 4870 | /* Set the scale after setting the register (otherwise, |
| 4871 | i386_scale will complain) */ |
| 4872 | i386_scale (save_str); |
| 4873 | intel_match_token (T_REG); |
| 4874 | |
| 4875 | /* Since registers are not part of the displacement |
| 4876 | string, we may need to remove any preceding '+' from |
| 4877 | the displacement string. */ |
| 4878 | if (*intel_parser.disp != '\0') |
| 4879 | { |
| 4880 | char *s = intel_parser.disp; |
| 4881 | s += strlen (s) - 1; |
| 4882 | if (*s == '+') |
| 4883 | *s = '\0'; |
| 4884 | } |
| 4885 | |
| 4886 | free (save_str); |
| 4887 | |
| 4888 | return 1; |
| 4889 | } |
| 4890 | else |
| 4891 | return 0; |
| 4892 | } |
| 4893 | |
| 4894 | /* The constant was not used for register scaling. Since we have |
| 4895 | already consumed the token following `*' we now need to put it |
| 4896 | back in the stream. */ |
| 4897 | else |
| 4898 | intel_putback_token (); |
| 4899 | } |
| 4900 | |
| 4901 | /* Add the constant to the displacement string. */ |
| 4902 | strcat (intel_parser.disp, save_str); |
| 4903 | free (save_str); |
| 4904 | |
| 4905 | return 1; |
| 4906 | } |
| 4907 | |
| 4908 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
| 4909 | return 0; |
| 4910 | } |
| 4911 | |
| 4912 | /* Match the given token against cur_token. If they match, read the next |
| 4913 | token from the operand string. */ |
| 4914 | static int |
| 4915 | intel_match_token (code) |
| 4916 | int code; |
| 4917 | { |
| 4918 | if (cur_token.code == code) |
| 4919 | { |
| 4920 | intel_get_token (); |
| 4921 | return 1; |
| 4922 | } |
| 4923 | else |
| 4924 | { |
| 4925 | as_bad (_("Unexpected token `%s'\n"), cur_token.str); |
| 4926 | return 0; |
| 4927 | } |
| 4928 | } |
| 4929 | |
| 4930 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
| 4931 | static void |
| 4932 | intel_get_token () |
| 4933 | { |
| 4934 | char *end_op; |
| 4935 | const reg_entry *reg; |
| 4936 | struct intel_token new_token; |
| 4937 | |
| 4938 | new_token.code = T_NIL; |
| 4939 | new_token.reg = NULL; |
| 4940 | new_token.str = NULL; |
| 4941 | |
| 4942 | /* Free the memory allocated to the previous token and move |
| 4943 | cur_token to prev_token. */ |
| 4944 | if (prev_token.str) |
| 4945 | free (prev_token.str); |
| 4946 | |
| 4947 | prev_token = cur_token; |
| 4948 | |
| 4949 | /* Skip whitespace. */ |
| 4950 | while (is_space_char (*intel_parser.op_string)) |
| 4951 | intel_parser.op_string++; |
| 4952 | |
| 4953 | /* Return an empty token if we find nothing else on the line. */ |
| 4954 | if (*intel_parser.op_string == '\0') |
| 4955 | { |
| 4956 | cur_token = new_token; |
| 4957 | return; |
| 4958 | } |
| 4959 | |
| 4960 | /* The new token cannot be larger than the remainder of the operand |
| 4961 | string. */ |
| 4962 | new_token.str = (char *)malloc (strlen (intel_parser.op_string) + 1); |
| 4963 | if (new_token.str == NULL) |
| 4964 | abort (); |
| 4965 | new_token.str[0] = '\0'; |
| 4966 | |
| 4967 | if (strchr ("0123456789", *intel_parser.op_string)) |
| 4968 | { |
| 4969 | char *p = new_token.str; |
| 4970 | char *q = intel_parser.op_string; |
| 4971 | new_token.code = T_CONST; |
| 4972 | |
| 4973 | /* Allow any kind of identifier char to encompass floating point and |
| 4974 | hexadecimal numbers. */ |
| 4975 | while (is_identifier_char (*q)) |
| 4976 | *p++ = *q++; |
| 4977 | *p = '\0'; |
| 4978 | |
| 4979 | /* Recognize special symbol names [0-9][bf]. */ |
| 4980 | if (strlen (intel_parser.op_string) == 2 |
| 4981 | && (intel_parser.op_string[1] == 'b' |
| 4982 | || intel_parser.op_string[1] == 'f')) |
| 4983 | new_token.code = T_ID; |
| 4984 | } |
| 4985 | |
| 4986 | else if (strchr ("+-/*:[]()", *intel_parser.op_string)) |
| 4987 | { |
| 4988 | new_token.code = *intel_parser.op_string; |
| 4989 | new_token.str[0] = *intel_parser.op_string; |
| 4990 | new_token.str[1] = '\0'; |
| 4991 | } |
| 4992 | |
| 4993 | else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) |
| 4994 | && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) |
| 4995 | { |
| 4996 | new_token.code = T_REG; |
| 4997 | new_token.reg = reg; |
| 4998 | |
| 4999 | if (*intel_parser.op_string == REGISTER_PREFIX) |
| 5000 | { |
| 5001 | new_token.str[0] = REGISTER_PREFIX; |
| 5002 | new_token.str[1] = '\0'; |
| 5003 | } |
| 5004 | |
| 5005 | strcat (new_token.str, reg->reg_name); |
| 5006 | } |
| 5007 | |
| 5008 | else if (is_identifier_char (*intel_parser.op_string)) |
| 5009 | { |
| 5010 | char *p = new_token.str; |
| 5011 | char *q = intel_parser.op_string; |
| 5012 | |
| 5013 | /* A '.' or '$' followed by an identifier char is an identifier. |
| 5014 | Otherwise, it's operator '.' followed by an expression. */ |
| 5015 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) |
| 5016 | { |
| 5017 | new_token.code = *q; |
| 5018 | new_token.str[0] = *q; |
| 5019 | new_token.str[1] = '\0'; |
| 5020 | } |
| 5021 | else |
| 5022 | { |
| 5023 | while (is_identifier_char (*q) || *q == '@') |
| 5024 | *p++ = *q++; |
| 5025 | *p = '\0'; |
| 5026 | |
| 5027 | if (strcasecmp (new_token.str, "BYTE") == 0) |
| 5028 | new_token.code = T_BYTE; |
| 5029 | |
| 5030 | else if (strcasecmp (new_token.str, "WORD") == 0) |
| 5031 | new_token.code = T_WORD; |
| 5032 | |
| 5033 | else if (strcasecmp (new_token.str, "DWORD") == 0) |
| 5034 | new_token.code = T_DWORD; |
| 5035 | |
| 5036 | else if (strcasecmp (new_token.str, "QWORD") == 0) |
| 5037 | new_token.code = T_QWORD; |
| 5038 | |
| 5039 | else if (strcasecmp (new_token.str, "XWORD") == 0) |
| 5040 | new_token.code = T_XWORD; |
| 5041 | |
| 5042 | else if (strcasecmp (new_token.str, "PTR") == 0) |
| 5043 | new_token.code = T_PTR; |
| 5044 | |
| 5045 | else if (strcasecmp (new_token.str, "SHORT") == 0) |
| 5046 | new_token.code = T_SHORT; |
| 5047 | |
| 5048 | else if (strcasecmp (new_token.str, "OFFSET") == 0) |
| 5049 | { |
| 5050 | new_token.code = T_OFFSET; |
| 5051 | |
| 5052 | /* ??? This is not mentioned in the MASM grammar but gcc |
| 5053 | makes use of it with -mintel-syntax. OFFSET may be |
| 5054 | followed by FLAT: */ |
| 5055 | if (strncasecmp (q, " FLAT:", 6) == 0) |
| 5056 | strcat (new_token.str, " FLAT:"); |
| 5057 | } |
| 5058 | |
| 5059 | /* ??? This is not mentioned in the MASM grammar. */ |
| 5060 | else if (strcasecmp (new_token.str, "FLAT") == 0) |
| 5061 | new_token.code = T_OFFSET; |
| 5062 | |
| 5063 | else |
| 5064 | new_token.code = T_ID; |
| 5065 | } |
| 5066 | } |
| 5067 | |
| 5068 | else |
| 5069 | as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string); |
| 5070 | |
| 5071 | intel_parser.op_string += strlen (new_token.str); |
| 5072 | cur_token = new_token; |
| 5073 | } |
| 5074 | |
| 5075 | /* Put cur_token back into the token stream and make cur_token point to |
| 5076 | prev_token. */ |
| 5077 | static void |
| 5078 | intel_putback_token () |
| 5079 | { |
| 5080 | intel_parser.op_string -= strlen (cur_token.str); |
| 5081 | free (cur_token.str); |
| 5082 | cur_token = prev_token; |
| 5083 | |
| 5084 | /* Forget prev_token. */ |
| 5085 | prev_token.code = T_NIL; |
| 5086 | prev_token.reg = NULL; |
| 5087 | prev_token.str = NULL; |
| 5088 | } |