| 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
| 2 | Copyright (C) 1989-2018 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GAS, the GNU Assembler. |
| 5 | |
| 6 | GAS is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 3, or (at your option) |
| 9 | any later version. |
| 10 | |
| 11 | GAS is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with GAS; see the file COPYING. If not, write to the Free |
| 18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 19 | 02110-1301, USA. */ |
| 20 | |
| 21 | /* Intel 80386 machine specific gas. |
| 22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). |
| 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
| 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
| 25 | Bugs & suggestions are completely welcome. This is free software. |
| 26 | Please help us make it better. */ |
| 27 | |
| 28 | #include "as.h" |
| 29 | #include "safe-ctype.h" |
| 30 | #include "subsegs.h" |
| 31 | #include "dwarf2dbg.h" |
| 32 | #include "dw2gencfi.h" |
| 33 | #include "elf/x86-64.h" |
| 34 | #include "opcodes/i386-init.h" |
| 35 | |
| 36 | #ifndef REGISTER_WARNINGS |
| 37 | #define REGISTER_WARNINGS 1 |
| 38 | #endif |
| 39 | |
| 40 | #ifndef INFER_ADDR_PREFIX |
| 41 | #define INFER_ADDR_PREFIX 1 |
| 42 | #endif |
| 43 | |
| 44 | #ifndef DEFAULT_ARCH |
| 45 | #define DEFAULT_ARCH "i386" |
| 46 | #endif |
| 47 | |
| 48 | #ifndef INLINE |
| 49 | #if __GNUC__ >= 2 |
| 50 | #define INLINE __inline__ |
| 51 | #else |
| 52 | #define INLINE |
| 53 | #endif |
| 54 | #endif |
| 55 | |
| 56 | /* Prefixes will be emitted in the order defined below. |
| 57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an |
| 58 | instruction, and so must come before any prefixes. |
| 59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, |
| 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
| 61 | #define WAIT_PREFIX 0 |
| 62 | #define SEG_PREFIX 1 |
| 63 | #define ADDR_PREFIX 2 |
| 64 | #define DATA_PREFIX 3 |
| 65 | #define REP_PREFIX 4 |
| 66 | #define HLE_PREFIX REP_PREFIX |
| 67 | #define BND_PREFIX REP_PREFIX |
| 68 | #define LOCK_PREFIX 5 |
| 69 | #define REX_PREFIX 6 /* must come last. */ |
| 70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ |
| 71 | |
| 72 | /* we define the syntax here (modulo base,index,scale syntax) */ |
| 73 | #define REGISTER_PREFIX '%' |
| 74 | #define IMMEDIATE_PREFIX '$' |
| 75 | #define ABSOLUTE_PREFIX '*' |
| 76 | |
| 77 | /* these are the instruction mnemonic suffixes in AT&T syntax or |
| 78 | memory operand size in Intel syntax. */ |
| 79 | #define WORD_MNEM_SUFFIX 'w' |
| 80 | #define BYTE_MNEM_SUFFIX 'b' |
| 81 | #define SHORT_MNEM_SUFFIX 's' |
| 82 | #define LONG_MNEM_SUFFIX 'l' |
| 83 | #define QWORD_MNEM_SUFFIX 'q' |
| 84 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
| 85 | in instructions. */ |
| 86 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' |
| 87 | |
| 88 | #define END_OF_INSN '\0' |
| 89 | |
| 90 | /* |
| 91 | 'templates' is for grouping together 'template' structures for opcodes |
| 92 | of the same name. This is only used for storing the insns in the grand |
| 93 | ole hash table of insns. |
| 94 | The templates themselves start at START and range up to (but not including) |
| 95 | END. |
| 96 | */ |
| 97 | typedef struct |
| 98 | { |
| 99 | const insn_template *start; |
| 100 | const insn_template *end; |
| 101 | } |
| 102 | templates; |
| 103 | |
| 104 | /* 386 operand encoding bytes: see 386 book for details of this. */ |
| 105 | typedef struct |
| 106 | { |
| 107 | unsigned int regmem; /* codes register or memory operand */ |
| 108 | unsigned int reg; /* codes register operand (or extended opcode) */ |
| 109 | unsigned int mode; /* how to interpret regmem & reg */ |
| 110 | } |
| 111 | modrm_byte; |
| 112 | |
| 113 | /* x86-64 extension prefix. */ |
| 114 | typedef int rex_byte; |
| 115 | |
| 116 | /* 386 opcode byte to code indirect addressing. */ |
| 117 | typedef struct |
| 118 | { |
| 119 | unsigned base; |
| 120 | unsigned index; |
| 121 | unsigned scale; |
| 122 | } |
| 123 | sib_byte; |
| 124 | |
| 125 | /* x86 arch names, types and features */ |
| 126 | typedef struct |
| 127 | { |
| 128 | const char *name; /* arch name */ |
| 129 | unsigned int len; /* arch string length */ |
| 130 | enum processor_type type; /* arch type */ |
| 131 | i386_cpu_flags flags; /* cpu feature flags */ |
| 132 | unsigned int skip; /* show_arch should skip this. */ |
| 133 | } |
| 134 | arch_entry; |
| 135 | |
| 136 | /* Used to turn off indicated flags. */ |
| 137 | typedef struct |
| 138 | { |
| 139 | const char *name; /* arch name */ |
| 140 | unsigned int len; /* arch string length */ |
| 141 | i386_cpu_flags flags; /* cpu feature flags */ |
| 142 | } |
| 143 | noarch_entry; |
| 144 | |
| 145 | static void update_code_flag (int, int); |
| 146 | static void set_code_flag (int); |
| 147 | static void set_16bit_gcc_code_flag (int); |
| 148 | static void set_intel_syntax (int); |
| 149 | static void set_intel_mnemonic (int); |
| 150 | static void set_allow_index_reg (int); |
| 151 | static void set_check (int); |
| 152 | static void set_cpu_arch (int); |
| 153 | #ifdef TE_PE |
| 154 | static void pe_directive_secrel (int); |
| 155 | #endif |
| 156 | static void signed_cons (int); |
| 157 | static char *output_invalid (int c); |
| 158 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
| 159 | const char *); |
| 160 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, |
| 161 | const char *); |
| 162 | static int i386_att_operand (char *); |
| 163 | static int i386_intel_operand (char *, int); |
| 164 | static int i386_intel_simplify (expressionS *); |
| 165 | static int i386_intel_parse_name (const char *, expressionS *); |
| 166 | static const reg_entry *parse_register (char *, char **); |
| 167 | static char *parse_insn (char *, char *); |
| 168 | static char *parse_operands (char *, const char *); |
| 169 | static void swap_operands (void); |
| 170 | static void swap_2_operands (int, int); |
| 171 | static void optimize_imm (void); |
| 172 | static void optimize_disp (void); |
| 173 | static const insn_template *match_template (char); |
| 174 | static int check_string (void); |
| 175 | static int process_suffix (void); |
| 176 | static int check_byte_reg (void); |
| 177 | static int check_long_reg (void); |
| 178 | static int check_qword_reg (void); |
| 179 | static int check_word_reg (void); |
| 180 | static int finalize_imm (void); |
| 181 | static int process_operands (void); |
| 182 | static const seg_entry *build_modrm_byte (void); |
| 183 | static void output_insn (void); |
| 184 | static void output_imm (fragS *, offsetT); |
| 185 | static void output_disp (fragS *, offsetT); |
| 186 | #ifndef I386COFF |
| 187 | static void s_bss (int); |
| 188 | #endif |
| 189 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 190 | static void handle_large_common (int small ATTRIBUTE_UNUSED); |
| 191 | #endif |
| 192 | |
| 193 | static const char *default_arch = DEFAULT_ARCH; |
| 194 | |
| 195 | /* This struct describes rounding control and SAE in the instruction. */ |
| 196 | struct RC_Operation |
| 197 | { |
| 198 | enum rc_type |
| 199 | { |
| 200 | rne = 0, |
| 201 | rd, |
| 202 | ru, |
| 203 | rz, |
| 204 | saeonly |
| 205 | } type; |
| 206 | int operand; |
| 207 | }; |
| 208 | |
| 209 | static struct RC_Operation rc_op; |
| 210 | |
| 211 | /* The struct describes masking, applied to OPERAND in the instruction. |
| 212 | MASK is a pointer to the corresponding mask register. ZEROING tells |
| 213 | whether merging or zeroing mask is used. */ |
| 214 | struct Mask_Operation |
| 215 | { |
| 216 | const reg_entry *mask; |
| 217 | unsigned int zeroing; |
| 218 | /* The operand where this operation is associated. */ |
| 219 | int operand; |
| 220 | }; |
| 221 | |
| 222 | static struct Mask_Operation mask_op; |
| 223 | |
| 224 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is |
| 225 | broadcast factor. */ |
| 226 | struct Broadcast_Operation |
| 227 | { |
| 228 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
| 229 | int type; |
| 230 | |
| 231 | /* Index of broadcasted operand. */ |
| 232 | int operand; |
| 233 | |
| 234 | /* Number of bytes to broadcast. */ |
| 235 | int bytes; |
| 236 | }; |
| 237 | |
| 238 | static struct Broadcast_Operation broadcast_op; |
| 239 | |
| 240 | /* VEX prefix. */ |
| 241 | typedef struct |
| 242 | { |
| 243 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
| 244 | unsigned char bytes[4]; |
| 245 | unsigned int length; |
| 246 | /* Destination or source register specifier. */ |
| 247 | const reg_entry *register_specifier; |
| 248 | } vex_prefix; |
| 249 | |
| 250 | /* 'md_assemble ()' gathers together information and puts it into a |
| 251 | i386_insn. */ |
| 252 | |
| 253 | union i386_op |
| 254 | { |
| 255 | expressionS *disps; |
| 256 | expressionS *imms; |
| 257 | const reg_entry *regs; |
| 258 | }; |
| 259 | |
| 260 | enum i386_error |
| 261 | { |
| 262 | operand_size_mismatch, |
| 263 | operand_type_mismatch, |
| 264 | register_type_mismatch, |
| 265 | number_of_operands_mismatch, |
| 266 | invalid_instruction_suffix, |
| 267 | bad_imm4, |
| 268 | unsupported_with_intel_mnemonic, |
| 269 | unsupported_syntax, |
| 270 | unsupported, |
| 271 | invalid_vsib_address, |
| 272 | invalid_vector_register_set, |
| 273 | unsupported_vector_index_register, |
| 274 | unsupported_broadcast, |
| 275 | broadcast_needed, |
| 276 | unsupported_masking, |
| 277 | mask_not_on_destination, |
| 278 | no_default_mask, |
| 279 | unsupported_rc_sae, |
| 280 | rc_sae_operand_not_last_imm, |
| 281 | invalid_register_operand, |
| 282 | }; |
| 283 | |
| 284 | struct _i386_insn |
| 285 | { |
| 286 | /* TM holds the template for the insn were currently assembling. */ |
| 287 | insn_template tm; |
| 288 | |
| 289 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
| 290 | or qword, if given. */ |
| 291 | char suffix; |
| 292 | |
| 293 | /* OPERANDS gives the number of given operands. */ |
| 294 | unsigned int operands; |
| 295 | |
| 296 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
| 297 | of given register, displacement, memory operands and immediate |
| 298 | operands. */ |
| 299 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
| 300 | |
| 301 | /* TYPES [i] is the type (see above #defines) which tells us how to |
| 302 | use OP[i] for the corresponding operand. */ |
| 303 | i386_operand_type types[MAX_OPERANDS]; |
| 304 | |
| 305 | /* Displacement expression, immediate expression, or register for each |
| 306 | operand. */ |
| 307 | union i386_op op[MAX_OPERANDS]; |
| 308 | |
| 309 | /* Flags for operands. */ |
| 310 | unsigned int flags[MAX_OPERANDS]; |
| 311 | #define Operand_PCrel 1 |
| 312 | #define Operand_Mem 2 |
| 313 | |
| 314 | /* Relocation type for operand */ |
| 315 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
| 316 | |
| 317 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
| 318 | the base index byte below. */ |
| 319 | const reg_entry *base_reg; |
| 320 | const reg_entry *index_reg; |
| 321 | unsigned int log2_scale_factor; |
| 322 | |
| 323 | /* SEG gives the seg_entries of this insn. They are zero unless |
| 324 | explicit segment overrides are given. */ |
| 325 | const seg_entry *seg[2]; |
| 326 | |
| 327 | /* Copied first memory operand string, for re-checking. */ |
| 328 | char *memop1_string; |
| 329 | |
| 330 | /* PREFIX holds all the given prefix opcodes (usually null). |
| 331 | PREFIXES is the number of prefix opcodes. */ |
| 332 | unsigned int prefixes; |
| 333 | unsigned char prefix[MAX_PREFIXES]; |
| 334 | |
| 335 | /* RM and SIB are the modrm byte and the sib byte where the |
| 336 | addressing modes of this insn are encoded. */ |
| 337 | modrm_byte rm; |
| 338 | rex_byte rex; |
| 339 | rex_byte vrex; |
| 340 | sib_byte sib; |
| 341 | vex_prefix vex; |
| 342 | |
| 343 | /* Masking attributes. */ |
| 344 | struct Mask_Operation *mask; |
| 345 | |
| 346 | /* Rounding control and SAE attributes. */ |
| 347 | struct RC_Operation *rounding; |
| 348 | |
| 349 | /* Broadcasting attributes. */ |
| 350 | struct Broadcast_Operation *broadcast; |
| 351 | |
| 352 | /* Compressed disp8*N attribute. */ |
| 353 | unsigned int memshift; |
| 354 | |
| 355 | /* Prefer load or store in encoding. */ |
| 356 | enum |
| 357 | { |
| 358 | dir_encoding_default = 0, |
| 359 | dir_encoding_load, |
| 360 | dir_encoding_store |
| 361 | } dir_encoding; |
| 362 | |
| 363 | /* Prefer 8bit or 32bit displacement in encoding. */ |
| 364 | enum |
| 365 | { |
| 366 | disp_encoding_default = 0, |
| 367 | disp_encoding_8bit, |
| 368 | disp_encoding_32bit |
| 369 | } disp_encoding; |
| 370 | |
| 371 | /* Prefer the REX byte in encoding. */ |
| 372 | bfd_boolean rex_encoding; |
| 373 | |
| 374 | /* Disable instruction size optimization. */ |
| 375 | bfd_boolean no_optimize; |
| 376 | |
| 377 | /* How to encode vector instructions. */ |
| 378 | enum |
| 379 | { |
| 380 | vex_encoding_default = 0, |
| 381 | vex_encoding_vex2, |
| 382 | vex_encoding_vex3, |
| 383 | vex_encoding_evex |
| 384 | } vec_encoding; |
| 385 | |
| 386 | /* REP prefix. */ |
| 387 | const char *rep_prefix; |
| 388 | |
| 389 | /* HLE prefix. */ |
| 390 | const char *hle_prefix; |
| 391 | |
| 392 | /* Have BND prefix. */ |
| 393 | const char *bnd_prefix; |
| 394 | |
| 395 | /* Have NOTRACK prefix. */ |
| 396 | const char *notrack_prefix; |
| 397 | |
| 398 | /* Error message. */ |
| 399 | enum i386_error error; |
| 400 | }; |
| 401 | |
| 402 | typedef struct _i386_insn i386_insn; |
| 403 | |
| 404 | /* Link RC type with corresponding string, that'll be looked for in |
| 405 | asm. */ |
| 406 | struct RC_name |
| 407 | { |
| 408 | enum rc_type type; |
| 409 | const char *name; |
| 410 | unsigned int len; |
| 411 | }; |
| 412 | |
| 413 | static const struct RC_name RC_NamesTable[] = |
| 414 | { |
| 415 | { rne, STRING_COMMA_LEN ("rn-sae") }, |
| 416 | { rd, STRING_COMMA_LEN ("rd-sae") }, |
| 417 | { ru, STRING_COMMA_LEN ("ru-sae") }, |
| 418 | { rz, STRING_COMMA_LEN ("rz-sae") }, |
| 419 | { saeonly, STRING_COMMA_LEN ("sae") }, |
| 420 | }; |
| 421 | |
| 422 | /* List of chars besides those in app.c:symbol_chars that can start an |
| 423 | operand. Used to prevent the scrubber eating vital white-space. */ |
| 424 | const char extra_symbol_chars[] = "*%-([{}" |
| 425 | #ifdef LEX_AT |
| 426 | "@" |
| 427 | #endif |
| 428 | #ifdef LEX_QM |
| 429 | "?" |
| 430 | #endif |
| 431 | ; |
| 432 | |
| 433 | #if (defined (TE_I386AIX) \ |
| 434 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
| 435 | && !defined (TE_GNU) \ |
| 436 | && !defined (TE_LINUX) \ |
| 437 | && !defined (TE_NACL) \ |
| 438 | && !defined (TE_FreeBSD) \ |
| 439 | && !defined (TE_DragonFly) \ |
| 440 | && !defined (TE_NetBSD))) |
| 441 | /* This array holds the chars that always start a comment. If the |
| 442 | pre-processor is disabled, these aren't very useful. The option |
| 443 | --divide will remove '/' from this list. */ |
| 444 | const char *i386_comment_chars = "#/"; |
| 445 | #define SVR4_COMMENT_CHARS 1 |
| 446 | #define PREFIX_SEPARATOR '\\' |
| 447 | |
| 448 | #else |
| 449 | const char *i386_comment_chars = "#"; |
| 450 | #define PREFIX_SEPARATOR '/' |
| 451 | #endif |
| 452 | |
| 453 | /* This array holds the chars that only start a comment at the beginning of |
| 454 | a line. If the line seems to have the form '# 123 filename' |
| 455 | .line and .file directives will appear in the pre-processed output. |
| 456 | Note that input_file.c hand checks for '#' at the beginning of the |
| 457 | first line of the input file. This is because the compiler outputs |
| 458 | #NO_APP at the beginning of its output. |
| 459 | Also note that comments started like this one will always work if |
| 460 | '/' isn't otherwise defined. */ |
| 461 | const char line_comment_chars[] = "#/"; |
| 462 | |
| 463 | const char line_separator_chars[] = ";"; |
| 464 | |
| 465 | /* Chars that can be used to separate mant from exp in floating point |
| 466 | nums. */ |
| 467 | const char EXP_CHARS[] = "eE"; |
| 468 | |
| 469 | /* Chars that mean this number is a floating point constant |
| 470 | As in 0f12.456 |
| 471 | or 0d1.2345e12. */ |
| 472 | const char FLT_CHARS[] = "fFdDxX"; |
| 473 | |
| 474 | /* Tables for lexical analysis. */ |
| 475 | static char mnemonic_chars[256]; |
| 476 | static char register_chars[256]; |
| 477 | static char operand_chars[256]; |
| 478 | static char identifier_chars[256]; |
| 479 | static char digit_chars[256]; |
| 480 | |
| 481 | /* Lexical macros. */ |
| 482 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
| 483 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
| 484 | #define is_register_char(x) (register_chars[(unsigned char) x]) |
| 485 | #define is_space_char(x) ((x) == ' ') |
| 486 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) |
| 487 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) |
| 488 | |
| 489 | /* All non-digit non-letter characters that may occur in an operand. */ |
| 490 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
| 491 | |
| 492 | /* md_assemble() always leaves the strings it's passed unaltered. To |
| 493 | effect this we maintain a stack of saved characters that we've smashed |
| 494 | with '\0's (indicating end of strings for various sub-fields of the |
| 495 | assembler instruction). */ |
| 496 | static char save_stack[32]; |
| 497 | static char *save_stack_p; |
| 498 | #define END_STRING_AND_SAVE(s) \ |
| 499 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) |
| 500 | #define RESTORE_END_STRING(s) \ |
| 501 | do { *(s) = *--save_stack_p; } while (0) |
| 502 | |
| 503 | /* The instruction we're assembling. */ |
| 504 | static i386_insn i; |
| 505 | |
| 506 | /* Possible templates for current insn. */ |
| 507 | static const templates *current_templates; |
| 508 | |
| 509 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
| 510 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; |
| 511 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; |
| 512 | |
| 513 | /* Current operand we are working on. */ |
| 514 | static int this_operand = -1; |
| 515 | |
| 516 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
| 517 | these. */ |
| 518 | |
| 519 | enum flag_code { |
| 520 | CODE_32BIT, |
| 521 | CODE_16BIT, |
| 522 | CODE_64BIT }; |
| 523 | |
| 524 | static enum flag_code flag_code; |
| 525 | static unsigned int object_64bit; |
| 526 | static unsigned int disallow_64bit_reloc; |
| 527 | static int use_rela_relocations = 0; |
| 528 | |
| 529 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
| 530 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 531 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 532 | |
| 533 | /* The ELF ABI to use. */ |
| 534 | enum x86_elf_abi |
| 535 | { |
| 536 | I386_ABI, |
| 537 | X86_64_ABI, |
| 538 | X86_64_X32_ABI |
| 539 | }; |
| 540 | |
| 541 | static enum x86_elf_abi x86_elf_abi = I386_ABI; |
| 542 | #endif |
| 543 | |
| 544 | #if defined (TE_PE) || defined (TE_PEP) |
| 545 | /* Use big object file format. */ |
| 546 | static int use_big_obj = 0; |
| 547 | #endif |
| 548 | |
| 549 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 550 | /* 1 if generating code for a shared library. */ |
| 551 | static int shared = 0; |
| 552 | #endif |
| 553 | |
| 554 | /* 1 for intel syntax, |
| 555 | 0 if att syntax. */ |
| 556 | static int intel_syntax = 0; |
| 557 | |
| 558 | /* 1 for Intel64 ISA, |
| 559 | 0 if AMD64 ISA. */ |
| 560 | static int intel64; |
| 561 | |
| 562 | /* 1 for intel mnemonic, |
| 563 | 0 if att mnemonic. */ |
| 564 | static int intel_mnemonic = !SYSV386_COMPAT; |
| 565 | |
| 566 | /* 1 if pseudo registers are permitted. */ |
| 567 | static int allow_pseudo_reg = 0; |
| 568 | |
| 569 | /* 1 if register prefix % not required. */ |
| 570 | static int allow_naked_reg = 0; |
| 571 | |
| 572 | /* 1 if the assembler should add BND prefix for all control-transferring |
| 573 | instructions supporting it, even if this prefix wasn't specified |
| 574 | explicitly. */ |
| 575 | static int add_bnd_prefix = 0; |
| 576 | |
| 577 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
| 578 | static int allow_index_reg = 0; |
| 579 | |
| 580 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
| 581 | specified explicitly. */ |
| 582 | static int omit_lock_prefix = 0; |
| 583 | |
| 584 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
| 585 | "lock addl $0, (%{re}sp)". */ |
| 586 | static int avoid_fence = 0; |
| 587 | |
| 588 | /* 1 if the assembler should generate relax relocations. */ |
| 589 | |
| 590 | static int generate_relax_relocations |
| 591 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; |
| 592 | |
| 593 | static enum check_kind |
| 594 | { |
| 595 | check_none = 0, |
| 596 | check_warning, |
| 597 | check_error |
| 598 | } |
| 599 | sse_check, operand_check = check_warning; |
| 600 | |
| 601 | /* Optimization: |
| 602 | 1. Clear the REX_W bit with register operand if possible. |
| 603 | 2. Above plus use 128bit vector instruction to clear the full vector |
| 604 | register. |
| 605 | */ |
| 606 | static int optimize = 0; |
| 607 | |
| 608 | /* Optimization: |
| 609 | 1. Clear the REX_W bit with register operand if possible. |
| 610 | 2. Above plus use 128bit vector instruction to clear the full vector |
| 611 | register. |
| 612 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to |
| 613 | "testb $imm7,%r8". |
| 614 | */ |
| 615 | static int optimize_for_space = 0; |
| 616 | |
| 617 | /* Register prefix used for error message. */ |
| 618 | static const char *register_prefix = "%"; |
| 619 | |
| 620 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
| 621 | leave, push, and pop instructions so that gcc has the same stack |
| 622 | frame as in 32 bit mode. */ |
| 623 | static char stackop_size = '\0'; |
| 624 | |
| 625 | /* Non-zero to optimize code alignment. */ |
| 626 | int optimize_align_code = 1; |
| 627 | |
| 628 | /* Non-zero to quieten some warnings. */ |
| 629 | static int quiet_warnings = 0; |
| 630 | |
| 631 | /* CPU name. */ |
| 632 | static const char *cpu_arch_name = NULL; |
| 633 | static char *cpu_sub_arch_name = NULL; |
| 634 | |
| 635 | /* CPU feature flags. */ |
| 636 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
| 637 | |
| 638 | /* If we have selected a cpu we are generating instructions for. */ |
| 639 | static int cpu_arch_tune_set = 0; |
| 640 | |
| 641 | /* Cpu we are generating instructions for. */ |
| 642 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
| 643 | |
| 644 | /* CPU feature flags of cpu we are generating instructions for. */ |
| 645 | static i386_cpu_flags cpu_arch_tune_flags; |
| 646 | |
| 647 | /* CPU instruction set architecture used. */ |
| 648 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
| 649 | |
| 650 | /* CPU feature flags of instruction set architecture used. */ |
| 651 | i386_cpu_flags cpu_arch_isa_flags; |
| 652 | |
| 653 | /* If set, conditional jumps are not automatically promoted to handle |
| 654 | larger than a byte offset. */ |
| 655 | static unsigned int no_cond_jump_promotion = 0; |
| 656 | |
| 657 | /* Encode SSE instructions with VEX prefix. */ |
| 658 | static unsigned int sse2avx; |
| 659 | |
| 660 | /* Encode scalar AVX instructions with specific vector length. */ |
| 661 | static enum |
| 662 | { |
| 663 | vex128 = 0, |
| 664 | vex256 |
| 665 | } avxscalar; |
| 666 | |
| 667 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
| 668 | static enum |
| 669 | { |
| 670 | evexl128 = 0, |
| 671 | evexl256, |
| 672 | evexl512 |
| 673 | } evexlig; |
| 674 | |
| 675 | /* Encode EVEX WIG instructions with specific evex.w. */ |
| 676 | static enum |
| 677 | { |
| 678 | evexw0 = 0, |
| 679 | evexw1 |
| 680 | } evexwig; |
| 681 | |
| 682 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
| 683 | static enum rc_type evexrcig = rne; |
| 684 | |
| 685 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
| 686 | static symbolS *GOT_symbol; |
| 687 | |
| 688 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
| 689 | unsigned int x86_dwarf2_return_column; |
| 690 | |
| 691 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
| 692 | int x86_cie_data_alignment; |
| 693 | |
| 694 | /* Interface to relax_segment. |
| 695 | There are 3 major relax states for 386 jump insns because the |
| 696 | different types of jumps add different sizes to frags when we're |
| 697 | figuring out what sort of jump to choose to reach a given label. */ |
| 698 | |
| 699 | /* Types. */ |
| 700 | #define UNCOND_JUMP 0 |
| 701 | #define COND_JUMP 1 |
| 702 | #define COND_JUMP86 2 |
| 703 | |
| 704 | /* Sizes. */ |
| 705 | #define CODE16 1 |
| 706 | #define SMALL 0 |
| 707 | #define SMALL16 (SMALL | CODE16) |
| 708 | #define BIG 2 |
| 709 | #define BIG16 (BIG | CODE16) |
| 710 | |
| 711 | #ifndef INLINE |
| 712 | #ifdef __GNUC__ |
| 713 | #define INLINE __inline__ |
| 714 | #else |
| 715 | #define INLINE |
| 716 | #endif |
| 717 | #endif |
| 718 | |
| 719 | #define ENCODE_RELAX_STATE(type, size) \ |
| 720 | ((relax_substateT) (((type) << 2) | (size))) |
| 721 | #define TYPE_FROM_RELAX_STATE(s) \ |
| 722 | ((s) >> 2) |
| 723 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ |
| 724 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) |
| 725 | |
| 726 | /* This table is used by relax_frag to promote short jumps to long |
| 727 | ones where necessary. SMALL (short) jumps may be promoted to BIG |
| 728 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We |
| 729 | don't allow a short jump in a 32 bit code segment to be promoted to |
| 730 | a 16 bit offset jump because it's slower (requires data size |
| 731 | prefix), and doesn't work, unless the destination is in the bottom |
| 732 | 64k of the code segment (The top 16 bits of eip are zeroed). */ |
| 733 | |
| 734 | const relax_typeS md_relax_table[] = |
| 735 | { |
| 736 | /* The fields are: |
| 737 | 1) most positive reach of this state, |
| 738 | 2) most negative reach of this state, |
| 739 | 3) how many bytes this mode will have in the variable part of the frag |
| 740 | 4) which index into the table to try if we can't fit into this one. */ |
| 741 | |
| 742 | /* UNCOND_JUMP states. */ |
| 743 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
| 744 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, |
| 745 | /* dword jmp adds 4 bytes to frag: |
| 746 | 0 extra opcode bytes, 4 displacement bytes. */ |
| 747 | {0, 0, 4, 0}, |
| 748 | /* word jmp adds 2 byte2 to frag: |
| 749 | 0 extra opcode bytes, 2 displacement bytes. */ |
| 750 | {0, 0, 2, 0}, |
| 751 | |
| 752 | /* COND_JUMP states. */ |
| 753 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, |
| 754 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, |
| 755 | /* dword conditionals adds 5 bytes to frag: |
| 756 | 1 extra opcode byte, 4 displacement bytes. */ |
| 757 | {0, 0, 5, 0}, |
| 758 | /* word conditionals add 3 bytes to frag: |
| 759 | 1 extra opcode byte, 2 displacement bytes. */ |
| 760 | {0, 0, 3, 0}, |
| 761 | |
| 762 | /* COND_JUMP86 states. */ |
| 763 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, |
| 764 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, |
| 765 | /* dword conditionals adds 5 bytes to frag: |
| 766 | 1 extra opcode byte, 4 displacement bytes. */ |
| 767 | {0, 0, 5, 0}, |
| 768 | /* word conditionals add 4 bytes to frag: |
| 769 | 1 displacement byte and a 3 byte long branch insn. */ |
| 770 | {0, 0, 4, 0} |
| 771 | }; |
| 772 | |
| 773 | static const arch_entry cpu_arch[] = |
| 774 | { |
| 775 | /* Do not replace the first two entries - i386_target_format() |
| 776 | relies on them being there in this order. */ |
| 777 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
| 778 | CPU_GENERIC32_FLAGS, 0 }, |
| 779 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
| 780 | CPU_GENERIC64_FLAGS, 0 }, |
| 781 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
| 782 | CPU_NONE_FLAGS, 0 }, |
| 783 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
| 784 | CPU_I186_FLAGS, 0 }, |
| 785 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
| 786 | CPU_I286_FLAGS, 0 }, |
| 787 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
| 788 | CPU_I386_FLAGS, 0 }, |
| 789 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
| 790 | CPU_I486_FLAGS, 0 }, |
| 791 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
| 792 | CPU_I586_FLAGS, 0 }, |
| 793 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
| 794 | CPU_I686_FLAGS, 0 }, |
| 795 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
| 796 | CPU_I586_FLAGS, 0 }, |
| 797 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
| 798 | CPU_PENTIUMPRO_FLAGS, 0 }, |
| 799 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
| 800 | CPU_P2_FLAGS, 0 }, |
| 801 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
| 802 | CPU_P3_FLAGS, 0 }, |
| 803 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
| 804 | CPU_P4_FLAGS, 0 }, |
| 805 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
| 806 | CPU_CORE_FLAGS, 0 }, |
| 807 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
| 808 | CPU_NOCONA_FLAGS, 0 }, |
| 809 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
| 810 | CPU_CORE_FLAGS, 1 }, |
| 811 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
| 812 | CPU_CORE_FLAGS, 0 }, |
| 813 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
| 814 | CPU_CORE2_FLAGS, 1 }, |
| 815 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
| 816 | CPU_CORE2_FLAGS, 0 }, |
| 817 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
| 818 | CPU_COREI7_FLAGS, 0 }, |
| 819 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
| 820 | CPU_L1OM_FLAGS, 0 }, |
| 821 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
| 822 | CPU_K1OM_FLAGS, 0 }, |
| 823 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
| 824 | CPU_IAMCU_FLAGS, 0 }, |
| 825 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
| 826 | CPU_K6_FLAGS, 0 }, |
| 827 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
| 828 | CPU_K6_2_FLAGS, 0 }, |
| 829 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
| 830 | CPU_ATHLON_FLAGS, 0 }, |
| 831 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
| 832 | CPU_K8_FLAGS, 1 }, |
| 833 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
| 834 | CPU_K8_FLAGS, 0 }, |
| 835 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
| 836 | CPU_K8_FLAGS, 0 }, |
| 837 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
| 838 | CPU_AMDFAM10_FLAGS, 0 }, |
| 839 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
| 840 | CPU_BDVER1_FLAGS, 0 }, |
| 841 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
| 842 | CPU_BDVER2_FLAGS, 0 }, |
| 843 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
| 844 | CPU_BDVER3_FLAGS, 0 }, |
| 845 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
| 846 | CPU_BDVER4_FLAGS, 0 }, |
| 847 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
| 848 | CPU_ZNVER1_FLAGS, 0 }, |
| 849 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
| 850 | CPU_ZNVER2_FLAGS, 0 }, |
| 851 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
| 852 | CPU_BTVER1_FLAGS, 0 }, |
| 853 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
| 854 | CPU_BTVER2_FLAGS, 0 }, |
| 855 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
| 856 | CPU_8087_FLAGS, 0 }, |
| 857 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
| 858 | CPU_287_FLAGS, 0 }, |
| 859 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
| 860 | CPU_387_FLAGS, 0 }, |
| 861 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
| 862 | CPU_687_FLAGS, 0 }, |
| 863 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
| 864 | CPU_MMX_FLAGS, 0 }, |
| 865 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
| 866 | CPU_SSE_FLAGS, 0 }, |
| 867 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
| 868 | CPU_SSE2_FLAGS, 0 }, |
| 869 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
| 870 | CPU_SSE3_FLAGS, 0 }, |
| 871 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
| 872 | CPU_SSSE3_FLAGS, 0 }, |
| 873 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
| 874 | CPU_SSE4_1_FLAGS, 0 }, |
| 875 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
| 876 | CPU_SSE4_2_FLAGS, 0 }, |
| 877 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
| 878 | CPU_SSE4_2_FLAGS, 0 }, |
| 879 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
| 880 | CPU_AVX_FLAGS, 0 }, |
| 881 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
| 882 | CPU_AVX2_FLAGS, 0 }, |
| 883 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
| 884 | CPU_AVX512F_FLAGS, 0 }, |
| 885 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
| 886 | CPU_AVX512CD_FLAGS, 0 }, |
| 887 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
| 888 | CPU_AVX512ER_FLAGS, 0 }, |
| 889 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
| 890 | CPU_AVX512PF_FLAGS, 0 }, |
| 891 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
| 892 | CPU_AVX512DQ_FLAGS, 0 }, |
| 893 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
| 894 | CPU_AVX512BW_FLAGS, 0 }, |
| 895 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
| 896 | CPU_AVX512VL_FLAGS, 0 }, |
| 897 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
| 898 | CPU_VMX_FLAGS, 0 }, |
| 899 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
| 900 | CPU_VMFUNC_FLAGS, 0 }, |
| 901 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
| 902 | CPU_SMX_FLAGS, 0 }, |
| 903 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
| 904 | CPU_XSAVE_FLAGS, 0 }, |
| 905 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
| 906 | CPU_XSAVEOPT_FLAGS, 0 }, |
| 907 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
| 908 | CPU_XSAVEC_FLAGS, 0 }, |
| 909 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
| 910 | CPU_XSAVES_FLAGS, 0 }, |
| 911 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
| 912 | CPU_AES_FLAGS, 0 }, |
| 913 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
| 914 | CPU_PCLMUL_FLAGS, 0 }, |
| 915 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
| 916 | CPU_PCLMUL_FLAGS, 1 }, |
| 917 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
| 918 | CPU_FSGSBASE_FLAGS, 0 }, |
| 919 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
| 920 | CPU_RDRND_FLAGS, 0 }, |
| 921 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
| 922 | CPU_F16C_FLAGS, 0 }, |
| 923 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
| 924 | CPU_BMI2_FLAGS, 0 }, |
| 925 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
| 926 | CPU_FMA_FLAGS, 0 }, |
| 927 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
| 928 | CPU_FMA4_FLAGS, 0 }, |
| 929 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
| 930 | CPU_XOP_FLAGS, 0 }, |
| 931 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
| 932 | CPU_LWP_FLAGS, 0 }, |
| 933 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
| 934 | CPU_MOVBE_FLAGS, 0 }, |
| 935 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
| 936 | CPU_CX16_FLAGS, 0 }, |
| 937 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
| 938 | CPU_EPT_FLAGS, 0 }, |
| 939 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
| 940 | CPU_LZCNT_FLAGS, 0 }, |
| 941 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
| 942 | CPU_HLE_FLAGS, 0 }, |
| 943 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
| 944 | CPU_RTM_FLAGS, 0 }, |
| 945 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
| 946 | CPU_INVPCID_FLAGS, 0 }, |
| 947 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
| 948 | CPU_CLFLUSH_FLAGS, 0 }, |
| 949 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
| 950 | CPU_NOP_FLAGS, 0 }, |
| 951 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
| 952 | CPU_SYSCALL_FLAGS, 0 }, |
| 953 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
| 954 | CPU_RDTSCP_FLAGS, 0 }, |
| 955 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
| 956 | CPU_3DNOW_FLAGS, 0 }, |
| 957 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
| 958 | CPU_3DNOWA_FLAGS, 0 }, |
| 959 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
| 960 | CPU_PADLOCK_FLAGS, 0 }, |
| 961 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
| 962 | CPU_SVME_FLAGS, 1 }, |
| 963 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
| 964 | CPU_SVME_FLAGS, 0 }, |
| 965 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
| 966 | CPU_SSE4A_FLAGS, 0 }, |
| 967 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
| 968 | CPU_ABM_FLAGS, 0 }, |
| 969 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
| 970 | CPU_BMI_FLAGS, 0 }, |
| 971 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
| 972 | CPU_TBM_FLAGS, 0 }, |
| 973 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
| 974 | CPU_ADX_FLAGS, 0 }, |
| 975 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
| 976 | CPU_RDSEED_FLAGS, 0 }, |
| 977 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
| 978 | CPU_PRFCHW_FLAGS, 0 }, |
| 979 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
| 980 | CPU_SMAP_FLAGS, 0 }, |
| 981 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
| 982 | CPU_MPX_FLAGS, 0 }, |
| 983 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
| 984 | CPU_SHA_FLAGS, 0 }, |
| 985 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
| 986 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
| 987 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
| 988 | CPU_PREFETCHWT1_FLAGS, 0 }, |
| 989 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
| 990 | CPU_SE1_FLAGS, 0 }, |
| 991 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
| 992 | CPU_CLWB_FLAGS, 0 }, |
| 993 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
| 994 | CPU_AVX512IFMA_FLAGS, 0 }, |
| 995 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
| 996 | CPU_AVX512VBMI_FLAGS, 0 }, |
| 997 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
| 998 | CPU_AVX512_4FMAPS_FLAGS, 0 }, |
| 999 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
| 1000 | CPU_AVX512_4VNNIW_FLAGS, 0 }, |
| 1001 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
| 1002 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, |
| 1003 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
| 1004 | CPU_AVX512_VBMI2_FLAGS, 0 }, |
| 1005 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
| 1006 | CPU_AVX512_VNNI_FLAGS, 0 }, |
| 1007 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
| 1008 | CPU_AVX512_BITALG_FLAGS, 0 }, |
| 1009 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
| 1010 | CPU_CLZERO_FLAGS, 0 }, |
| 1011 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
| 1012 | CPU_MWAITX_FLAGS, 0 }, |
| 1013 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
| 1014 | CPU_OSPKE_FLAGS, 0 }, |
| 1015 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
| 1016 | CPU_RDPID_FLAGS, 0 }, |
| 1017 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
| 1018 | CPU_PTWRITE_FLAGS, 0 }, |
| 1019 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
| 1020 | CPU_IBT_FLAGS, 0 }, |
| 1021 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, |
| 1022 | CPU_SHSTK_FLAGS, 0 }, |
| 1023 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
| 1024 | CPU_GFNI_FLAGS, 0 }, |
| 1025 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
| 1026 | CPU_VAES_FLAGS, 0 }, |
| 1027 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
| 1028 | CPU_VPCLMULQDQ_FLAGS, 0 }, |
| 1029 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
| 1030 | CPU_WBNOINVD_FLAGS, 0 }, |
| 1031 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
| 1032 | CPU_PCONFIG_FLAGS, 0 }, |
| 1033 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
| 1034 | CPU_WAITPKG_FLAGS, 0 }, |
| 1035 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
| 1036 | CPU_CLDEMOTE_FLAGS, 0 }, |
| 1037 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
| 1038 | CPU_MOVDIRI_FLAGS, 0 }, |
| 1039 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, |
| 1040 | CPU_MOVDIR64B_FLAGS, 0 }, |
| 1041 | }; |
| 1042 | |
| 1043 | static const noarch_entry cpu_noarch[] = |
| 1044 | { |
| 1045 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, |
| 1046 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
| 1047 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, |
| 1048 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, |
| 1049 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
| 1050 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, |
| 1051 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
| 1052 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, |
| 1053 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, |
| 1054 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, |
| 1055 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, |
| 1056 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, |
| 1057 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
| 1058 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
| 1059 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
| 1060 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, |
| 1061 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, |
| 1062 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, |
| 1063 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, |
| 1064 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, |
| 1065 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, |
| 1066 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, |
| 1067 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, |
| 1068 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
| 1069 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
| 1070 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
| 1071 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
| 1072 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
| 1073 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
| 1074 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
| 1075 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, |
| 1076 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
| 1077 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, |
| 1078 | }; |
| 1079 | |
| 1080 | #ifdef I386COFF |
| 1081 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
| 1082 | is allowed to be optional. */ |
| 1083 | |
| 1084 | static symbolS * |
| 1085 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) |
| 1086 | { |
| 1087 | addressT align = 0; |
| 1088 | |
| 1089 | SKIP_WHITESPACE (); |
| 1090 | |
| 1091 | if (needs_align |
| 1092 | && *input_line_pointer == ',') |
| 1093 | { |
| 1094 | align = parse_align (needs_align - 1); |
| 1095 | |
| 1096 | if (align == (addressT) -1) |
| 1097 | return NULL; |
| 1098 | } |
| 1099 | else |
| 1100 | { |
| 1101 | if (size >= 8) |
| 1102 | align = 3; |
| 1103 | else if (size >= 4) |
| 1104 | align = 2; |
| 1105 | else if (size >= 2) |
| 1106 | align = 1; |
| 1107 | else |
| 1108 | align = 0; |
| 1109 | } |
| 1110 | |
| 1111 | bss_alloc (symbolP, size, align); |
| 1112 | return symbolP; |
| 1113 | } |
| 1114 | |
| 1115 | static void |
| 1116 | pe_lcomm (int needs_align) |
| 1117 | { |
| 1118 | s_comm_internal (needs_align * 2, pe_lcomm_internal); |
| 1119 | } |
| 1120 | #endif |
| 1121 | |
| 1122 | const pseudo_typeS md_pseudo_table[] = |
| 1123 | { |
| 1124 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
| 1125 | {"align", s_align_bytes, 0}, |
| 1126 | #else |
| 1127 | {"align", s_align_ptwo, 0}, |
| 1128 | #endif |
| 1129 | {"arch", set_cpu_arch, 0}, |
| 1130 | #ifndef I386COFF |
| 1131 | {"bss", s_bss, 0}, |
| 1132 | #else |
| 1133 | {"lcomm", pe_lcomm, 1}, |
| 1134 | #endif |
| 1135 | {"ffloat", float_cons, 'f'}, |
| 1136 | {"dfloat", float_cons, 'd'}, |
| 1137 | {"tfloat", float_cons, 'x'}, |
| 1138 | {"value", cons, 2}, |
| 1139 | {"slong", signed_cons, 4}, |
| 1140 | {"noopt", s_ignore, 0}, |
| 1141 | {"optim", s_ignore, 0}, |
| 1142 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, |
| 1143 | {"code16", set_code_flag, CODE_16BIT}, |
| 1144 | {"code32", set_code_flag, CODE_32BIT}, |
| 1145 | #ifdef BFD64 |
| 1146 | {"code64", set_code_flag, CODE_64BIT}, |
| 1147 | #endif |
| 1148 | {"intel_syntax", set_intel_syntax, 1}, |
| 1149 | {"att_syntax", set_intel_syntax, 0}, |
| 1150 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
| 1151 | {"att_mnemonic", set_intel_mnemonic, 0}, |
| 1152 | {"allow_index_reg", set_allow_index_reg, 1}, |
| 1153 | {"disallow_index_reg", set_allow_index_reg, 0}, |
| 1154 | {"sse_check", set_check, 0}, |
| 1155 | {"operand_check", set_check, 1}, |
| 1156 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 1157 | {"largecomm", handle_large_common, 0}, |
| 1158 | #else |
| 1159 | {"file", dwarf2_directive_file, 0}, |
| 1160 | {"loc", dwarf2_directive_loc, 0}, |
| 1161 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, |
| 1162 | #endif |
| 1163 | #ifdef TE_PE |
| 1164 | {"secrel32", pe_directive_secrel, 0}, |
| 1165 | #endif |
| 1166 | {0, 0, 0} |
| 1167 | }; |
| 1168 | |
| 1169 | /* For interface with expression (). */ |
| 1170 | extern char *input_line_pointer; |
| 1171 | |
| 1172 | /* Hash table for instruction mnemonic lookup. */ |
| 1173 | static struct hash_control *op_hash; |
| 1174 | |
| 1175 | /* Hash table for register lookup. */ |
| 1176 | static struct hash_control *reg_hash; |
| 1177 | \f |
| 1178 | /* Various efficient no-op patterns for aligning code labels. |
| 1179 | Note: Don't try to assemble the instructions in the comments. |
| 1180 | 0L and 0w are not legal. */ |
| 1181 | static const unsigned char f32_1[] = |
| 1182 | {0x90}; /* nop */ |
| 1183 | static const unsigned char f32_2[] = |
| 1184 | {0x66,0x90}; /* xchg %ax,%ax */ |
| 1185 | static const unsigned char f32_3[] = |
| 1186 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ |
| 1187 | static const unsigned char f32_4[] = |
| 1188 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
| 1189 | static const unsigned char f32_6[] = |
| 1190 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ |
| 1191 | static const unsigned char f32_7[] = |
| 1192 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
| 1193 | static const unsigned char f16_3[] = |
| 1194 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
| 1195 | static const unsigned char f16_4[] = |
| 1196 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
| 1197 | static const unsigned char jump_disp8[] = |
| 1198 | {0xeb}; /* jmp disp8 */ |
| 1199 | static const unsigned char jump32_disp32[] = |
| 1200 | {0xe9}; /* jmp disp32 */ |
| 1201 | static const unsigned char jump16_disp32[] = |
| 1202 | {0x66,0xe9}; /* jmp disp32 */ |
| 1203 | /* 32-bit NOPs patterns. */ |
| 1204 | static const unsigned char *const f32_patt[] = { |
| 1205 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
| 1206 | }; |
| 1207 | /* 16-bit NOPs patterns. */ |
| 1208 | static const unsigned char *const f16_patt[] = { |
| 1209 | f32_1, f32_2, f16_3, f16_4 |
| 1210 | }; |
| 1211 | /* nopl (%[re]ax) */ |
| 1212 | static const unsigned char alt_3[] = |
| 1213 | {0x0f,0x1f,0x00}; |
| 1214 | /* nopl 0(%[re]ax) */ |
| 1215 | static const unsigned char alt_4[] = |
| 1216 | {0x0f,0x1f,0x40,0x00}; |
| 1217 | /* nopl 0(%[re]ax,%[re]ax,1) */ |
| 1218 | static const unsigned char alt_5[] = |
| 1219 | {0x0f,0x1f,0x44,0x00,0x00}; |
| 1220 | /* nopw 0(%[re]ax,%[re]ax,1) */ |
| 1221 | static const unsigned char alt_6[] = |
| 1222 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; |
| 1223 | /* nopl 0L(%[re]ax) */ |
| 1224 | static const unsigned char alt_7[] = |
| 1225 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; |
| 1226 | /* nopl 0L(%[re]ax,%[re]ax,1) */ |
| 1227 | static const unsigned char alt_8[] = |
| 1228 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 1229 | /* nopw 0L(%[re]ax,%[re]ax,1) */ |
| 1230 | static const unsigned char alt_9[] = |
| 1231 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 1232 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ |
| 1233 | static const unsigned char alt_10[] = |
| 1234 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 1235 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
| 1236 | static const unsigned char alt_11[] = |
| 1237 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
| 1238 | /* 32-bit and 64-bit NOPs patterns. */ |
| 1239 | static const unsigned char *const alt_patt[] = { |
| 1240 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, |
| 1241 | alt_9, alt_10, alt_11 |
| 1242 | }; |
| 1243 | |
| 1244 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum |
| 1245 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ |
| 1246 | |
| 1247 | static void |
| 1248 | i386_output_nops (char *where, const unsigned char *const *patt, |
| 1249 | int count, int max_single_nop_size) |
| 1250 | |
| 1251 | { |
| 1252 | /* Place the longer NOP first. */ |
| 1253 | int last; |
| 1254 | int offset; |
| 1255 | const unsigned char *nops = patt[max_single_nop_size - 1]; |
| 1256 | |
| 1257 | /* Use the smaller one if the requsted one isn't available. */ |
| 1258 | if (nops == NULL) |
| 1259 | { |
| 1260 | max_single_nop_size--; |
| 1261 | nops = patt[max_single_nop_size - 1]; |
| 1262 | } |
| 1263 | |
| 1264 | last = count % max_single_nop_size; |
| 1265 | |
| 1266 | count -= last; |
| 1267 | for (offset = 0; offset < count; offset += max_single_nop_size) |
| 1268 | memcpy (where + offset, nops, max_single_nop_size); |
| 1269 | |
| 1270 | if (last) |
| 1271 | { |
| 1272 | nops = patt[last - 1]; |
| 1273 | if (nops == NULL) |
| 1274 | { |
| 1275 | /* Use the smaller one plus one-byte NOP if the needed one |
| 1276 | isn't available. */ |
| 1277 | last--; |
| 1278 | nops = patt[last - 1]; |
| 1279 | memcpy (where + offset, nops, last); |
| 1280 | where[offset + last] = *patt[0]; |
| 1281 | } |
| 1282 | else |
| 1283 | memcpy (where + offset, nops, last); |
| 1284 | } |
| 1285 | } |
| 1286 | |
| 1287 | static INLINE int |
| 1288 | fits_in_imm7 (offsetT num) |
| 1289 | { |
| 1290 | return (num & 0x7f) == num; |
| 1291 | } |
| 1292 | |
| 1293 | static INLINE int |
| 1294 | fits_in_imm31 (offsetT num) |
| 1295 | { |
| 1296 | return (num & 0x7fffffff) == num; |
| 1297 | } |
| 1298 | |
| 1299 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a |
| 1300 | single NOP instruction LIMIT. */ |
| 1301 | |
| 1302 | void |
| 1303 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
| 1304 | { |
| 1305 | const unsigned char *const *patt = NULL; |
| 1306 | int max_single_nop_size; |
| 1307 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
| 1308 | int max_number_of_nops; |
| 1309 | |
| 1310 | switch (fragP->fr_type) |
| 1311 | { |
| 1312 | case rs_fill_nop: |
| 1313 | case rs_align_code: |
| 1314 | break; |
| 1315 | default: |
| 1316 | return; |
| 1317 | } |
| 1318 | |
| 1319 | /* We need to decide which NOP sequence to use for 32bit and |
| 1320 | 64bit. When -mtune= is used: |
| 1321 | |
| 1322 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
| 1323 | PROCESSOR_GENERIC32, f32_patt will be used. |
| 1324 | 2. For the rest, alt_patt will be used. |
| 1325 | |
| 1326 | When -mtune= isn't used, alt_patt will be used if |
| 1327 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
| 1328 | be used. |
| 1329 | |
| 1330 | When -march= or .arch is used, we can't use anything beyond |
| 1331 | cpu_arch_isa_flags. */ |
| 1332 | |
| 1333 | if (flag_code == CODE_16BIT) |
| 1334 | { |
| 1335 | patt = f16_patt; |
| 1336 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); |
| 1337 | /* Limit number of NOPs to 2 in 16-bit mode. */ |
| 1338 | max_number_of_nops = 2; |
| 1339 | } |
| 1340 | else |
| 1341 | { |
| 1342 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
| 1343 | { |
| 1344 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ |
| 1345 | switch (cpu_arch_tune) |
| 1346 | { |
| 1347 | case PROCESSOR_UNKNOWN: |
| 1348 | /* We use cpu_arch_isa_flags to check if we SHOULD |
| 1349 | optimize with nops. */ |
| 1350 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
| 1351 | patt = alt_patt; |
| 1352 | else |
| 1353 | patt = f32_patt; |
| 1354 | break; |
| 1355 | case PROCESSOR_PENTIUM4: |
| 1356 | case PROCESSOR_NOCONA: |
| 1357 | case PROCESSOR_CORE: |
| 1358 | case PROCESSOR_CORE2: |
| 1359 | case PROCESSOR_COREI7: |
| 1360 | case PROCESSOR_L1OM: |
| 1361 | case PROCESSOR_K1OM: |
| 1362 | case PROCESSOR_GENERIC64: |
| 1363 | case PROCESSOR_K6: |
| 1364 | case PROCESSOR_ATHLON: |
| 1365 | case PROCESSOR_K8: |
| 1366 | case PROCESSOR_AMDFAM10: |
| 1367 | case PROCESSOR_BD: |
| 1368 | case PROCESSOR_ZNVER: |
| 1369 | case PROCESSOR_BT: |
| 1370 | patt = alt_patt; |
| 1371 | break; |
| 1372 | case PROCESSOR_I386: |
| 1373 | case PROCESSOR_I486: |
| 1374 | case PROCESSOR_PENTIUM: |
| 1375 | case PROCESSOR_PENTIUMPRO: |
| 1376 | case PROCESSOR_IAMCU: |
| 1377 | case PROCESSOR_GENERIC32: |
| 1378 | patt = f32_patt; |
| 1379 | break; |
| 1380 | } |
| 1381 | } |
| 1382 | else |
| 1383 | { |
| 1384 | switch (fragP->tc_frag_data.tune) |
| 1385 | { |
| 1386 | case PROCESSOR_UNKNOWN: |
| 1387 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
| 1388 | PROCESSOR_UNKNOWN. */ |
| 1389 | abort (); |
| 1390 | break; |
| 1391 | |
| 1392 | case PROCESSOR_I386: |
| 1393 | case PROCESSOR_I486: |
| 1394 | case PROCESSOR_PENTIUM: |
| 1395 | case PROCESSOR_IAMCU: |
| 1396 | case PROCESSOR_K6: |
| 1397 | case PROCESSOR_ATHLON: |
| 1398 | case PROCESSOR_K8: |
| 1399 | case PROCESSOR_AMDFAM10: |
| 1400 | case PROCESSOR_BD: |
| 1401 | case PROCESSOR_ZNVER: |
| 1402 | case PROCESSOR_BT: |
| 1403 | case PROCESSOR_GENERIC32: |
| 1404 | /* We use cpu_arch_isa_flags to check if we CAN optimize |
| 1405 | with nops. */ |
| 1406 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
| 1407 | patt = alt_patt; |
| 1408 | else |
| 1409 | patt = f32_patt; |
| 1410 | break; |
| 1411 | case PROCESSOR_PENTIUMPRO: |
| 1412 | case PROCESSOR_PENTIUM4: |
| 1413 | case PROCESSOR_NOCONA: |
| 1414 | case PROCESSOR_CORE: |
| 1415 | case PROCESSOR_CORE2: |
| 1416 | case PROCESSOR_COREI7: |
| 1417 | case PROCESSOR_L1OM: |
| 1418 | case PROCESSOR_K1OM: |
| 1419 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
| 1420 | patt = alt_patt; |
| 1421 | else |
| 1422 | patt = f32_patt; |
| 1423 | break; |
| 1424 | case PROCESSOR_GENERIC64: |
| 1425 | patt = alt_patt; |
| 1426 | break; |
| 1427 | } |
| 1428 | } |
| 1429 | |
| 1430 | if (patt == f32_patt) |
| 1431 | { |
| 1432 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
| 1433 | /* Limit number of NOPs to 2 for older processors. */ |
| 1434 | max_number_of_nops = 2; |
| 1435 | } |
| 1436 | else |
| 1437 | { |
| 1438 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
| 1439 | /* Limit number of NOPs to 7 for newer processors. */ |
| 1440 | max_number_of_nops = 7; |
| 1441 | } |
| 1442 | } |
| 1443 | |
| 1444 | if (limit == 0) |
| 1445 | limit = max_single_nop_size; |
| 1446 | |
| 1447 | if (fragP->fr_type == rs_fill_nop) |
| 1448 | { |
| 1449 | /* Output NOPs for .nop directive. */ |
| 1450 | if (limit > max_single_nop_size) |
| 1451 | { |
| 1452 | as_bad_where (fragP->fr_file, fragP->fr_line, |
| 1453 | _("invalid single nop size: %d " |
| 1454 | "(expect within [0, %d])"), |
| 1455 | limit, max_single_nop_size); |
| 1456 | return; |
| 1457 | } |
| 1458 | } |
| 1459 | else |
| 1460 | fragP->fr_var = count; |
| 1461 | |
| 1462 | if ((count / max_single_nop_size) > max_number_of_nops) |
| 1463 | { |
| 1464 | /* Generate jump over NOPs. */ |
| 1465 | offsetT disp = count - 2; |
| 1466 | if (fits_in_imm7 (disp)) |
| 1467 | { |
| 1468 | /* Use "jmp disp8" if possible. */ |
| 1469 | count = disp; |
| 1470 | where[0] = jump_disp8[0]; |
| 1471 | where[1] = count; |
| 1472 | where += 2; |
| 1473 | } |
| 1474 | else |
| 1475 | { |
| 1476 | unsigned int size_of_jump; |
| 1477 | |
| 1478 | if (flag_code == CODE_16BIT) |
| 1479 | { |
| 1480 | where[0] = jump16_disp32[0]; |
| 1481 | where[1] = jump16_disp32[1]; |
| 1482 | size_of_jump = 2; |
| 1483 | } |
| 1484 | else |
| 1485 | { |
| 1486 | where[0] = jump32_disp32[0]; |
| 1487 | size_of_jump = 1; |
| 1488 | } |
| 1489 | |
| 1490 | count -= size_of_jump + 4; |
| 1491 | if (!fits_in_imm31 (count)) |
| 1492 | { |
| 1493 | as_bad_where (fragP->fr_file, fragP->fr_line, |
| 1494 | _("jump over nop padding out of range")); |
| 1495 | return; |
| 1496 | } |
| 1497 | |
| 1498 | md_number_to_chars (where + size_of_jump, count, 4); |
| 1499 | where += size_of_jump + 4; |
| 1500 | } |
| 1501 | } |
| 1502 | |
| 1503 | /* Generate multiple NOPs. */ |
| 1504 | i386_output_nops (where, patt, count, limit); |
| 1505 | } |
| 1506 | |
| 1507 | static INLINE int |
| 1508 | operand_type_all_zero (const union i386_operand_type *x) |
| 1509 | { |
| 1510 | switch (ARRAY_SIZE(x->array)) |
| 1511 | { |
| 1512 | case 3: |
| 1513 | if (x->array[2]) |
| 1514 | return 0; |
| 1515 | /* Fall through. */ |
| 1516 | case 2: |
| 1517 | if (x->array[1]) |
| 1518 | return 0; |
| 1519 | /* Fall through. */ |
| 1520 | case 1: |
| 1521 | return !x->array[0]; |
| 1522 | default: |
| 1523 | abort (); |
| 1524 | } |
| 1525 | } |
| 1526 | |
| 1527 | static INLINE void |
| 1528 | operand_type_set (union i386_operand_type *x, unsigned int v) |
| 1529 | { |
| 1530 | switch (ARRAY_SIZE(x->array)) |
| 1531 | { |
| 1532 | case 3: |
| 1533 | x->array[2] = v; |
| 1534 | /* Fall through. */ |
| 1535 | case 2: |
| 1536 | x->array[1] = v; |
| 1537 | /* Fall through. */ |
| 1538 | case 1: |
| 1539 | x->array[0] = v; |
| 1540 | /* Fall through. */ |
| 1541 | break; |
| 1542 | default: |
| 1543 | abort (); |
| 1544 | } |
| 1545 | } |
| 1546 | |
| 1547 | static INLINE int |
| 1548 | operand_type_equal (const union i386_operand_type *x, |
| 1549 | const union i386_operand_type *y) |
| 1550 | { |
| 1551 | switch (ARRAY_SIZE(x->array)) |
| 1552 | { |
| 1553 | case 3: |
| 1554 | if (x->array[2] != y->array[2]) |
| 1555 | return 0; |
| 1556 | /* Fall through. */ |
| 1557 | case 2: |
| 1558 | if (x->array[1] != y->array[1]) |
| 1559 | return 0; |
| 1560 | /* Fall through. */ |
| 1561 | case 1: |
| 1562 | return x->array[0] == y->array[0]; |
| 1563 | break; |
| 1564 | default: |
| 1565 | abort (); |
| 1566 | } |
| 1567 | } |
| 1568 | |
| 1569 | static INLINE int |
| 1570 | cpu_flags_all_zero (const union i386_cpu_flags *x) |
| 1571 | { |
| 1572 | switch (ARRAY_SIZE(x->array)) |
| 1573 | { |
| 1574 | case 4: |
| 1575 | if (x->array[3]) |
| 1576 | return 0; |
| 1577 | /* Fall through. */ |
| 1578 | case 3: |
| 1579 | if (x->array[2]) |
| 1580 | return 0; |
| 1581 | /* Fall through. */ |
| 1582 | case 2: |
| 1583 | if (x->array[1]) |
| 1584 | return 0; |
| 1585 | /* Fall through. */ |
| 1586 | case 1: |
| 1587 | return !x->array[0]; |
| 1588 | default: |
| 1589 | abort (); |
| 1590 | } |
| 1591 | } |
| 1592 | |
| 1593 | static INLINE int |
| 1594 | cpu_flags_equal (const union i386_cpu_flags *x, |
| 1595 | const union i386_cpu_flags *y) |
| 1596 | { |
| 1597 | switch (ARRAY_SIZE(x->array)) |
| 1598 | { |
| 1599 | case 4: |
| 1600 | if (x->array[3] != y->array[3]) |
| 1601 | return 0; |
| 1602 | /* Fall through. */ |
| 1603 | case 3: |
| 1604 | if (x->array[2] != y->array[2]) |
| 1605 | return 0; |
| 1606 | /* Fall through. */ |
| 1607 | case 2: |
| 1608 | if (x->array[1] != y->array[1]) |
| 1609 | return 0; |
| 1610 | /* Fall through. */ |
| 1611 | case 1: |
| 1612 | return x->array[0] == y->array[0]; |
| 1613 | break; |
| 1614 | default: |
| 1615 | abort (); |
| 1616 | } |
| 1617 | } |
| 1618 | |
| 1619 | static INLINE int |
| 1620 | cpu_flags_check_cpu64 (i386_cpu_flags f) |
| 1621 | { |
| 1622 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) |
| 1623 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); |
| 1624 | } |
| 1625 | |
| 1626 | static INLINE i386_cpu_flags |
| 1627 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) |
| 1628 | { |
| 1629 | switch (ARRAY_SIZE (x.array)) |
| 1630 | { |
| 1631 | case 4: |
| 1632 | x.array [3] &= y.array [3]; |
| 1633 | /* Fall through. */ |
| 1634 | case 3: |
| 1635 | x.array [2] &= y.array [2]; |
| 1636 | /* Fall through. */ |
| 1637 | case 2: |
| 1638 | x.array [1] &= y.array [1]; |
| 1639 | /* Fall through. */ |
| 1640 | case 1: |
| 1641 | x.array [0] &= y.array [0]; |
| 1642 | break; |
| 1643 | default: |
| 1644 | abort (); |
| 1645 | } |
| 1646 | return x; |
| 1647 | } |
| 1648 | |
| 1649 | static INLINE i386_cpu_flags |
| 1650 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) |
| 1651 | { |
| 1652 | switch (ARRAY_SIZE (x.array)) |
| 1653 | { |
| 1654 | case 4: |
| 1655 | x.array [3] |= y.array [3]; |
| 1656 | /* Fall through. */ |
| 1657 | case 3: |
| 1658 | x.array [2] |= y.array [2]; |
| 1659 | /* Fall through. */ |
| 1660 | case 2: |
| 1661 | x.array [1] |= y.array [1]; |
| 1662 | /* Fall through. */ |
| 1663 | case 1: |
| 1664 | x.array [0] |= y.array [0]; |
| 1665 | break; |
| 1666 | default: |
| 1667 | abort (); |
| 1668 | } |
| 1669 | return x; |
| 1670 | } |
| 1671 | |
| 1672 | static INLINE i386_cpu_flags |
| 1673 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) |
| 1674 | { |
| 1675 | switch (ARRAY_SIZE (x.array)) |
| 1676 | { |
| 1677 | case 4: |
| 1678 | x.array [3] &= ~y.array [3]; |
| 1679 | /* Fall through. */ |
| 1680 | case 3: |
| 1681 | x.array [2] &= ~y.array [2]; |
| 1682 | /* Fall through. */ |
| 1683 | case 2: |
| 1684 | x.array [1] &= ~y.array [1]; |
| 1685 | /* Fall through. */ |
| 1686 | case 1: |
| 1687 | x.array [0] &= ~y.array [0]; |
| 1688 | break; |
| 1689 | default: |
| 1690 | abort (); |
| 1691 | } |
| 1692 | return x; |
| 1693 | } |
| 1694 | |
| 1695 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
| 1696 | #define CPU_FLAGS_64BIT_MATCH 0x2 |
| 1697 | |
| 1698 | #define CPU_FLAGS_PERFECT_MATCH \ |
| 1699 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
| 1700 | |
| 1701 | /* Return CPU flags match bits. */ |
| 1702 | |
| 1703 | static int |
| 1704 | cpu_flags_match (const insn_template *t) |
| 1705 | { |
| 1706 | i386_cpu_flags x = t->cpu_flags; |
| 1707 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; |
| 1708 | |
| 1709 | x.bitfield.cpu64 = 0; |
| 1710 | x.bitfield.cpuno64 = 0; |
| 1711 | |
| 1712 | if (cpu_flags_all_zero (&x)) |
| 1713 | { |
| 1714 | /* This instruction is available on all archs. */ |
| 1715 | match |= CPU_FLAGS_ARCH_MATCH; |
| 1716 | } |
| 1717 | else |
| 1718 | { |
| 1719 | /* This instruction is available only on some archs. */ |
| 1720 | i386_cpu_flags cpu = cpu_arch_flags; |
| 1721 | |
| 1722 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
| 1723 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) |
| 1724 | return match; |
| 1725 | x.bitfield.cpuavx512vl = 0; |
| 1726 | |
| 1727 | cpu = cpu_flags_and (x, cpu); |
| 1728 | if (!cpu_flags_all_zero (&cpu)) |
| 1729 | { |
| 1730 | if (x.bitfield.cpuavx) |
| 1731 | { |
| 1732 | /* We need to check a few extra flags with AVX. */ |
| 1733 | if (cpu.bitfield.cpuavx |
| 1734 | && (!t->opcode_modifier.sse2avx || sse2avx) |
| 1735 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) |
| 1736 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
| 1737 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
| 1738 | match |= CPU_FLAGS_ARCH_MATCH; |
| 1739 | } |
| 1740 | else if (x.bitfield.cpuavx512f) |
| 1741 | { |
| 1742 | /* We need to check a few extra flags with AVX512F. */ |
| 1743 | if (cpu.bitfield.cpuavx512f |
| 1744 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
| 1745 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) |
| 1746 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) |
| 1747 | match |= CPU_FLAGS_ARCH_MATCH; |
| 1748 | } |
| 1749 | else |
| 1750 | match |= CPU_FLAGS_ARCH_MATCH; |
| 1751 | } |
| 1752 | } |
| 1753 | return match; |
| 1754 | } |
| 1755 | |
| 1756 | static INLINE i386_operand_type |
| 1757 | operand_type_and (i386_operand_type x, i386_operand_type y) |
| 1758 | { |
| 1759 | switch (ARRAY_SIZE (x.array)) |
| 1760 | { |
| 1761 | case 3: |
| 1762 | x.array [2] &= y.array [2]; |
| 1763 | /* Fall through. */ |
| 1764 | case 2: |
| 1765 | x.array [1] &= y.array [1]; |
| 1766 | /* Fall through. */ |
| 1767 | case 1: |
| 1768 | x.array [0] &= y.array [0]; |
| 1769 | break; |
| 1770 | default: |
| 1771 | abort (); |
| 1772 | } |
| 1773 | return x; |
| 1774 | } |
| 1775 | |
| 1776 | static INLINE i386_operand_type |
| 1777 | operand_type_and_not (i386_operand_type x, i386_operand_type y) |
| 1778 | { |
| 1779 | switch (ARRAY_SIZE (x.array)) |
| 1780 | { |
| 1781 | case 3: |
| 1782 | x.array [2] &= ~y.array [2]; |
| 1783 | /* Fall through. */ |
| 1784 | case 2: |
| 1785 | x.array [1] &= ~y.array [1]; |
| 1786 | /* Fall through. */ |
| 1787 | case 1: |
| 1788 | x.array [0] &= ~y.array [0]; |
| 1789 | break; |
| 1790 | default: |
| 1791 | abort (); |
| 1792 | } |
| 1793 | return x; |
| 1794 | } |
| 1795 | |
| 1796 | static INLINE i386_operand_type |
| 1797 | operand_type_or (i386_operand_type x, i386_operand_type y) |
| 1798 | { |
| 1799 | switch (ARRAY_SIZE (x.array)) |
| 1800 | { |
| 1801 | case 3: |
| 1802 | x.array [2] |= y.array [2]; |
| 1803 | /* Fall through. */ |
| 1804 | case 2: |
| 1805 | x.array [1] |= y.array [1]; |
| 1806 | /* Fall through. */ |
| 1807 | case 1: |
| 1808 | x.array [0] |= y.array [0]; |
| 1809 | break; |
| 1810 | default: |
| 1811 | abort (); |
| 1812 | } |
| 1813 | return x; |
| 1814 | } |
| 1815 | |
| 1816 | static INLINE i386_operand_type |
| 1817 | operand_type_xor (i386_operand_type x, i386_operand_type y) |
| 1818 | { |
| 1819 | switch (ARRAY_SIZE (x.array)) |
| 1820 | { |
| 1821 | case 3: |
| 1822 | x.array [2] ^= y.array [2]; |
| 1823 | /* Fall through. */ |
| 1824 | case 2: |
| 1825 | x.array [1] ^= y.array [1]; |
| 1826 | /* Fall through. */ |
| 1827 | case 1: |
| 1828 | x.array [0] ^= y.array [0]; |
| 1829 | break; |
| 1830 | default: |
| 1831 | abort (); |
| 1832 | } |
| 1833 | return x; |
| 1834 | } |
| 1835 | |
| 1836 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; |
| 1837 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; |
| 1838 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
| 1839 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; |
| 1840 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; |
| 1841 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; |
| 1842 | static const i386_operand_type anydisp |
| 1843 | = OPERAND_TYPE_ANYDISP; |
| 1844 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
| 1845 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
| 1846 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
| 1847 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; |
| 1848 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; |
| 1849 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; |
| 1850 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; |
| 1851 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; |
| 1852 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; |
| 1853 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; |
| 1854 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; |
| 1855 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
| 1856 | |
| 1857 | enum operand_type |
| 1858 | { |
| 1859 | reg, |
| 1860 | imm, |
| 1861 | disp, |
| 1862 | anymem |
| 1863 | }; |
| 1864 | |
| 1865 | static INLINE int |
| 1866 | operand_type_check (i386_operand_type t, enum operand_type c) |
| 1867 | { |
| 1868 | switch (c) |
| 1869 | { |
| 1870 | case reg: |
| 1871 | return t.bitfield.reg; |
| 1872 | |
| 1873 | case imm: |
| 1874 | return (t.bitfield.imm8 |
| 1875 | || t.bitfield.imm8s |
| 1876 | || t.bitfield.imm16 |
| 1877 | || t.bitfield.imm32 |
| 1878 | || t.bitfield.imm32s |
| 1879 | || t.bitfield.imm64); |
| 1880 | |
| 1881 | case disp: |
| 1882 | return (t.bitfield.disp8 |
| 1883 | || t.bitfield.disp16 |
| 1884 | || t.bitfield.disp32 |
| 1885 | || t.bitfield.disp32s |
| 1886 | || t.bitfield.disp64); |
| 1887 | |
| 1888 | case anymem: |
| 1889 | return (t.bitfield.disp8 |
| 1890 | || t.bitfield.disp16 |
| 1891 | || t.bitfield.disp32 |
| 1892 | || t.bitfield.disp32s |
| 1893 | || t.bitfield.disp64 |
| 1894 | || t.bitfield.baseindex); |
| 1895 | |
| 1896 | default: |
| 1897 | abort (); |
| 1898 | } |
| 1899 | |
| 1900 | return 0; |
| 1901 | } |
| 1902 | |
| 1903 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
| 1904 | between operand GIVEN and opeand WANTED for instruction template T. */ |
| 1905 | |
| 1906 | static INLINE int |
| 1907 | match_operand_size (const insn_template *t, unsigned int wanted, |
| 1908 | unsigned int given) |
| 1909 | { |
| 1910 | return !((i.types[given].bitfield.byte |
| 1911 | && !t->operand_types[wanted].bitfield.byte) |
| 1912 | || (i.types[given].bitfield.word |
| 1913 | && !t->operand_types[wanted].bitfield.word) |
| 1914 | || (i.types[given].bitfield.dword |
| 1915 | && !t->operand_types[wanted].bitfield.dword) |
| 1916 | || (i.types[given].bitfield.qword |
| 1917 | && !t->operand_types[wanted].bitfield.qword) |
| 1918 | || (i.types[given].bitfield.tbyte |
| 1919 | && !t->operand_types[wanted].bitfield.tbyte)); |
| 1920 | } |
| 1921 | |
| 1922 | /* Return 1 if there is no conflict in SIMD register between operand |
| 1923 | GIVEN and opeand WANTED for instruction template T. */ |
| 1924 | |
| 1925 | static INLINE int |
| 1926 | match_simd_size (const insn_template *t, unsigned int wanted, |
| 1927 | unsigned int given) |
| 1928 | { |
| 1929 | return !((i.types[given].bitfield.xmmword |
| 1930 | && !t->operand_types[wanted].bitfield.xmmword) |
| 1931 | || (i.types[given].bitfield.ymmword |
| 1932 | && !t->operand_types[wanted].bitfield.ymmword) |
| 1933 | || (i.types[given].bitfield.zmmword |
| 1934 | && !t->operand_types[wanted].bitfield.zmmword)); |
| 1935 | } |
| 1936 | |
| 1937 | /* Return 1 if there is no conflict in any size between operand GIVEN |
| 1938 | and opeand WANTED for instruction template T. */ |
| 1939 | |
| 1940 | static INLINE int |
| 1941 | match_mem_size (const insn_template *t, unsigned int wanted, |
| 1942 | unsigned int given) |
| 1943 | { |
| 1944 | return (match_operand_size (t, wanted, given) |
| 1945 | && !((i.types[given].bitfield.unspecified |
| 1946 | && !i.broadcast |
| 1947 | && !t->operand_types[wanted].bitfield.unspecified) |
| 1948 | || (i.types[given].bitfield.fword |
| 1949 | && !t->operand_types[wanted].bitfield.fword) |
| 1950 | /* For scalar opcode templates to allow register and memory |
| 1951 | operands at the same time, some special casing is needed |
| 1952 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
| 1953 | down-conversion vpmov*. */ |
| 1954 | || ((t->operand_types[wanted].bitfield.regsimd |
| 1955 | && !t->opcode_modifier.broadcast |
| 1956 | && (t->operand_types[wanted].bitfield.byte |
| 1957 | || t->operand_types[wanted].bitfield.word |
| 1958 | || t->operand_types[wanted].bitfield.dword |
| 1959 | || t->operand_types[wanted].bitfield.qword)) |
| 1960 | ? (i.types[given].bitfield.xmmword |
| 1961 | || i.types[given].bitfield.ymmword |
| 1962 | || i.types[given].bitfield.zmmword) |
| 1963 | : !match_simd_size(t, wanted, given)))); |
| 1964 | } |
| 1965 | |
| 1966 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
| 1967 | operands for instruction template T, and it has MATCH_REVERSE set if there |
| 1968 | is no size conflict on any operands for the template with operands reversed |
| 1969 | (and the template allows for reversing in the first place). */ |
| 1970 | |
| 1971 | #define MATCH_STRAIGHT 1 |
| 1972 | #define MATCH_REVERSE 2 |
| 1973 | |
| 1974 | static INLINE unsigned int |
| 1975 | operand_size_match (const insn_template *t) |
| 1976 | { |
| 1977 | unsigned int j, match = MATCH_STRAIGHT; |
| 1978 | |
| 1979 | /* Don't check jump instructions. */ |
| 1980 | if (t->opcode_modifier.jump |
| 1981 | || t->opcode_modifier.jumpbyte |
| 1982 | || t->opcode_modifier.jumpdword |
| 1983 | || t->opcode_modifier.jumpintersegment) |
| 1984 | return match; |
| 1985 | |
| 1986 | /* Check memory and accumulator operand size. */ |
| 1987 | for (j = 0; j < i.operands; j++) |
| 1988 | { |
| 1989 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
| 1990 | && t->operand_types[j].bitfield.anysize) |
| 1991 | continue; |
| 1992 | |
| 1993 | if (t->operand_types[j].bitfield.reg |
| 1994 | && !match_operand_size (t, j, j)) |
| 1995 | { |
| 1996 | match = 0; |
| 1997 | break; |
| 1998 | } |
| 1999 | |
| 2000 | if (t->operand_types[j].bitfield.regsimd |
| 2001 | && !match_simd_size (t, j, j)) |
| 2002 | { |
| 2003 | match = 0; |
| 2004 | break; |
| 2005 | } |
| 2006 | |
| 2007 | if (t->operand_types[j].bitfield.acc |
| 2008 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
| 2009 | { |
| 2010 | match = 0; |
| 2011 | break; |
| 2012 | } |
| 2013 | |
| 2014 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
| 2015 | { |
| 2016 | match = 0; |
| 2017 | break; |
| 2018 | } |
| 2019 | } |
| 2020 | |
| 2021 | if (!t->opcode_modifier.d) |
| 2022 | { |
| 2023 | mismatch: |
| 2024 | if (!match) |
| 2025 | i.error = operand_size_mismatch; |
| 2026 | return match; |
| 2027 | } |
| 2028 | |
| 2029 | /* Check reverse. */ |
| 2030 | gas_assert (i.operands == 2); |
| 2031 | |
| 2032 | for (j = 0; j < 2; j++) |
| 2033 | { |
| 2034 | if ((t->operand_types[j].bitfield.reg |
| 2035 | || t->operand_types[j].bitfield.acc) |
| 2036 | && !match_operand_size (t, j, !j)) |
| 2037 | goto mismatch; |
| 2038 | |
| 2039 | if ((i.flags[!j] & Operand_Mem) && !match_mem_size (t, j, !j)) |
| 2040 | goto mismatch; |
| 2041 | } |
| 2042 | |
| 2043 | return match | MATCH_REVERSE; |
| 2044 | } |
| 2045 | |
| 2046 | static INLINE int |
| 2047 | operand_type_match (i386_operand_type overlap, |
| 2048 | i386_operand_type given) |
| 2049 | { |
| 2050 | i386_operand_type temp = overlap; |
| 2051 | |
| 2052 | temp.bitfield.jumpabsolute = 0; |
| 2053 | temp.bitfield.unspecified = 0; |
| 2054 | temp.bitfield.byte = 0; |
| 2055 | temp.bitfield.word = 0; |
| 2056 | temp.bitfield.dword = 0; |
| 2057 | temp.bitfield.fword = 0; |
| 2058 | temp.bitfield.qword = 0; |
| 2059 | temp.bitfield.tbyte = 0; |
| 2060 | temp.bitfield.xmmword = 0; |
| 2061 | temp.bitfield.ymmword = 0; |
| 2062 | temp.bitfield.zmmword = 0; |
| 2063 | if (operand_type_all_zero (&temp)) |
| 2064 | goto mismatch; |
| 2065 | |
| 2066 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
| 2067 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) |
| 2068 | return 1; |
| 2069 | |
| 2070 | mismatch: |
| 2071 | i.error = operand_type_mismatch; |
| 2072 | return 0; |
| 2073 | } |
| 2074 | |
| 2075 | /* If given types g0 and g1 are registers they must be of the same type |
| 2076 | unless the expected operand type register overlap is null. |
| 2077 | Memory operand size of certain SIMD instructions is also being checked |
| 2078 | here. */ |
| 2079 | |
| 2080 | static INLINE int |
| 2081 | operand_type_register_match (i386_operand_type g0, |
| 2082 | i386_operand_type t0, |
| 2083 | i386_operand_type g1, |
| 2084 | i386_operand_type t1) |
| 2085 | { |
| 2086 | if (!g0.bitfield.reg |
| 2087 | && !g0.bitfield.regsimd |
| 2088 | && (!operand_type_check (g0, anymem) |
| 2089 | || g0.bitfield.unspecified |
| 2090 | || !t0.bitfield.regsimd)) |
| 2091 | return 1; |
| 2092 | |
| 2093 | if (!g1.bitfield.reg |
| 2094 | && !g1.bitfield.regsimd |
| 2095 | && (!operand_type_check (g1, anymem) |
| 2096 | || g1.bitfield.unspecified |
| 2097 | || !t1.bitfield.regsimd)) |
| 2098 | return 1; |
| 2099 | |
| 2100 | if (g0.bitfield.byte == g1.bitfield.byte |
| 2101 | && g0.bitfield.word == g1.bitfield.word |
| 2102 | && g0.bitfield.dword == g1.bitfield.dword |
| 2103 | && g0.bitfield.qword == g1.bitfield.qword |
| 2104 | && g0.bitfield.xmmword == g1.bitfield.xmmword |
| 2105 | && g0.bitfield.ymmword == g1.bitfield.ymmword |
| 2106 | && g0.bitfield.zmmword == g1.bitfield.zmmword) |
| 2107 | return 1; |
| 2108 | |
| 2109 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
| 2110 | && !(t0.bitfield.word & t1.bitfield.word) |
| 2111 | && !(t0.bitfield.dword & t1.bitfield.dword) |
| 2112 | && !(t0.bitfield.qword & t1.bitfield.qword) |
| 2113 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) |
| 2114 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) |
| 2115 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) |
| 2116 | return 1; |
| 2117 | |
| 2118 | i.error = register_type_mismatch; |
| 2119 | |
| 2120 | return 0; |
| 2121 | } |
| 2122 | |
| 2123 | static INLINE unsigned int |
| 2124 | register_number (const reg_entry *r) |
| 2125 | { |
| 2126 | unsigned int nr = r->reg_num; |
| 2127 | |
| 2128 | if (r->reg_flags & RegRex) |
| 2129 | nr += 8; |
| 2130 | |
| 2131 | if (r->reg_flags & RegVRex) |
| 2132 | nr += 16; |
| 2133 | |
| 2134 | return nr; |
| 2135 | } |
| 2136 | |
| 2137 | static INLINE unsigned int |
| 2138 | mode_from_disp_size (i386_operand_type t) |
| 2139 | { |
| 2140 | if (t.bitfield.disp8) |
| 2141 | return 1; |
| 2142 | else if (t.bitfield.disp16 |
| 2143 | || t.bitfield.disp32 |
| 2144 | || t.bitfield.disp32s) |
| 2145 | return 2; |
| 2146 | else |
| 2147 | return 0; |
| 2148 | } |
| 2149 | |
| 2150 | static INLINE int |
| 2151 | fits_in_signed_byte (addressT num) |
| 2152 | { |
| 2153 | return num + 0x80 <= 0xff; |
| 2154 | } |
| 2155 | |
| 2156 | static INLINE int |
| 2157 | fits_in_unsigned_byte (addressT num) |
| 2158 | { |
| 2159 | return num <= 0xff; |
| 2160 | } |
| 2161 | |
| 2162 | static INLINE int |
| 2163 | fits_in_unsigned_word (addressT num) |
| 2164 | { |
| 2165 | return num <= 0xffff; |
| 2166 | } |
| 2167 | |
| 2168 | static INLINE int |
| 2169 | fits_in_signed_word (addressT num) |
| 2170 | { |
| 2171 | return num + 0x8000 <= 0xffff; |
| 2172 | } |
| 2173 | |
| 2174 | static INLINE int |
| 2175 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
| 2176 | { |
| 2177 | #ifndef BFD64 |
| 2178 | return 1; |
| 2179 | #else |
| 2180 | return num + 0x80000000 <= 0xffffffff; |
| 2181 | #endif |
| 2182 | } /* fits_in_signed_long() */ |
| 2183 | |
| 2184 | static INLINE int |
| 2185 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
| 2186 | { |
| 2187 | #ifndef BFD64 |
| 2188 | return 1; |
| 2189 | #else |
| 2190 | return num <= 0xffffffff; |
| 2191 | #endif |
| 2192 | } /* fits_in_unsigned_long() */ |
| 2193 | |
| 2194 | static INLINE int |
| 2195 | fits_in_disp8 (offsetT num) |
| 2196 | { |
| 2197 | int shift = i.memshift; |
| 2198 | unsigned int mask; |
| 2199 | |
| 2200 | if (shift == -1) |
| 2201 | abort (); |
| 2202 | |
| 2203 | mask = (1 << shift) - 1; |
| 2204 | |
| 2205 | /* Return 0 if NUM isn't properly aligned. */ |
| 2206 | if ((num & mask)) |
| 2207 | return 0; |
| 2208 | |
| 2209 | /* Check if NUM will fit in 8bit after shift. */ |
| 2210 | return fits_in_signed_byte (num >> shift); |
| 2211 | } |
| 2212 | |
| 2213 | static INLINE int |
| 2214 | fits_in_imm4 (offsetT num) |
| 2215 | { |
| 2216 | return (num & 0xf) == num; |
| 2217 | } |
| 2218 | |
| 2219 | static i386_operand_type |
| 2220 | smallest_imm_type (offsetT num) |
| 2221 | { |
| 2222 | i386_operand_type t; |
| 2223 | |
| 2224 | operand_type_set (&t, 0); |
| 2225 | t.bitfield.imm64 = 1; |
| 2226 | |
| 2227 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) |
| 2228 | { |
| 2229 | /* This code is disabled on the 486 because all the Imm1 forms |
| 2230 | in the opcode table are slower on the i486. They're the |
| 2231 | versions with the implicitly specified single-position |
| 2232 | displacement, which has another syntax if you really want to |
| 2233 | use that form. */ |
| 2234 | t.bitfield.imm1 = 1; |
| 2235 | t.bitfield.imm8 = 1; |
| 2236 | t.bitfield.imm8s = 1; |
| 2237 | t.bitfield.imm16 = 1; |
| 2238 | t.bitfield.imm32 = 1; |
| 2239 | t.bitfield.imm32s = 1; |
| 2240 | } |
| 2241 | else if (fits_in_signed_byte (num)) |
| 2242 | { |
| 2243 | t.bitfield.imm8 = 1; |
| 2244 | t.bitfield.imm8s = 1; |
| 2245 | t.bitfield.imm16 = 1; |
| 2246 | t.bitfield.imm32 = 1; |
| 2247 | t.bitfield.imm32s = 1; |
| 2248 | } |
| 2249 | else if (fits_in_unsigned_byte (num)) |
| 2250 | { |
| 2251 | t.bitfield.imm8 = 1; |
| 2252 | t.bitfield.imm16 = 1; |
| 2253 | t.bitfield.imm32 = 1; |
| 2254 | t.bitfield.imm32s = 1; |
| 2255 | } |
| 2256 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
| 2257 | { |
| 2258 | t.bitfield.imm16 = 1; |
| 2259 | t.bitfield.imm32 = 1; |
| 2260 | t.bitfield.imm32s = 1; |
| 2261 | } |
| 2262 | else if (fits_in_signed_long (num)) |
| 2263 | { |
| 2264 | t.bitfield.imm32 = 1; |
| 2265 | t.bitfield.imm32s = 1; |
| 2266 | } |
| 2267 | else if (fits_in_unsigned_long (num)) |
| 2268 | t.bitfield.imm32 = 1; |
| 2269 | |
| 2270 | return t; |
| 2271 | } |
| 2272 | |
| 2273 | static offsetT |
| 2274 | offset_in_range (offsetT val, int size) |
| 2275 | { |
| 2276 | addressT mask; |
| 2277 | |
| 2278 | switch (size) |
| 2279 | { |
| 2280 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
| 2281 | case 2: mask = ((addressT) 1 << 16) - 1; break; |
| 2282 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
| 2283 | #ifdef BFD64 |
| 2284 | case 8: mask = ((addressT) 2 << 63) - 1; break; |
| 2285 | #endif |
| 2286 | default: abort (); |
| 2287 | } |
| 2288 | |
| 2289 | #ifdef BFD64 |
| 2290 | /* If BFD64, sign extend val for 32bit address mode. */ |
| 2291 | if (flag_code != CODE_64BIT |
| 2292 | || i.prefix[ADDR_PREFIX]) |
| 2293 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
| 2294 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
| 2295 | #endif |
| 2296 | |
| 2297 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
| 2298 | { |
| 2299 | char buf1[40], buf2[40]; |
| 2300 | |
| 2301 | sprint_value (buf1, val); |
| 2302 | sprint_value (buf2, val & mask); |
| 2303 | as_warn (_("%s shortened to %s"), buf1, buf2); |
| 2304 | } |
| 2305 | return val & mask; |
| 2306 | } |
| 2307 | |
| 2308 | enum PREFIX_GROUP |
| 2309 | { |
| 2310 | PREFIX_EXIST = 0, |
| 2311 | PREFIX_LOCK, |
| 2312 | PREFIX_REP, |
| 2313 | PREFIX_DS, |
| 2314 | PREFIX_OTHER |
| 2315 | }; |
| 2316 | |
| 2317 | /* Returns |
| 2318 | a. PREFIX_EXIST if attempting to add a prefix where one from the |
| 2319 | same class already exists. |
| 2320 | b. PREFIX_LOCK if lock prefix is added. |
| 2321 | c. PREFIX_REP if rep/repne prefix is added. |
| 2322 | d. PREFIX_DS if ds prefix is added. |
| 2323 | e. PREFIX_OTHER if other prefix is added. |
| 2324 | */ |
| 2325 | |
| 2326 | static enum PREFIX_GROUP |
| 2327 | add_prefix (unsigned int prefix) |
| 2328 | { |
| 2329 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
| 2330 | unsigned int q; |
| 2331 | |
| 2332 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
| 2333 | && flag_code == CODE_64BIT) |
| 2334 | { |
| 2335 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
| 2336 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
| 2337 | || (i.prefix[REX_PREFIX] & prefix & REX_X) |
| 2338 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) |
| 2339 | ret = PREFIX_EXIST; |
| 2340 | q = REX_PREFIX; |
| 2341 | } |
| 2342 | else |
| 2343 | { |
| 2344 | switch (prefix) |
| 2345 | { |
| 2346 | default: |
| 2347 | abort (); |
| 2348 | |
| 2349 | case DS_PREFIX_OPCODE: |
| 2350 | ret = PREFIX_DS; |
| 2351 | /* Fall through. */ |
| 2352 | case CS_PREFIX_OPCODE: |
| 2353 | case ES_PREFIX_OPCODE: |
| 2354 | case FS_PREFIX_OPCODE: |
| 2355 | case GS_PREFIX_OPCODE: |
| 2356 | case SS_PREFIX_OPCODE: |
| 2357 | q = SEG_PREFIX; |
| 2358 | break; |
| 2359 | |
| 2360 | case REPNE_PREFIX_OPCODE: |
| 2361 | case REPE_PREFIX_OPCODE: |
| 2362 | q = REP_PREFIX; |
| 2363 | ret = PREFIX_REP; |
| 2364 | break; |
| 2365 | |
| 2366 | case LOCK_PREFIX_OPCODE: |
| 2367 | q = LOCK_PREFIX; |
| 2368 | ret = PREFIX_LOCK; |
| 2369 | break; |
| 2370 | |
| 2371 | case FWAIT_OPCODE: |
| 2372 | q = WAIT_PREFIX; |
| 2373 | break; |
| 2374 | |
| 2375 | case ADDR_PREFIX_OPCODE: |
| 2376 | q = ADDR_PREFIX; |
| 2377 | break; |
| 2378 | |
| 2379 | case DATA_PREFIX_OPCODE: |
| 2380 | q = DATA_PREFIX; |
| 2381 | break; |
| 2382 | } |
| 2383 | if (i.prefix[q] != 0) |
| 2384 | ret = PREFIX_EXIST; |
| 2385 | } |
| 2386 | |
| 2387 | if (ret) |
| 2388 | { |
| 2389 | if (!i.prefix[q]) |
| 2390 | ++i.prefixes; |
| 2391 | i.prefix[q] |= prefix; |
| 2392 | } |
| 2393 | else |
| 2394 | as_bad (_("same type of prefix used twice")); |
| 2395 | |
| 2396 | return ret; |
| 2397 | } |
| 2398 | |
| 2399 | static void |
| 2400 | update_code_flag (int value, int check) |
| 2401 | { |
| 2402 | PRINTF_LIKE ((*as_error)); |
| 2403 | |
| 2404 | flag_code = (enum flag_code) value; |
| 2405 | if (flag_code == CODE_64BIT) |
| 2406 | { |
| 2407 | cpu_arch_flags.bitfield.cpu64 = 1; |
| 2408 | cpu_arch_flags.bitfield.cpuno64 = 0; |
| 2409 | } |
| 2410 | else |
| 2411 | { |
| 2412 | cpu_arch_flags.bitfield.cpu64 = 0; |
| 2413 | cpu_arch_flags.bitfield.cpuno64 = 1; |
| 2414 | } |
| 2415 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) |
| 2416 | { |
| 2417 | if (check) |
| 2418 | as_error = as_fatal; |
| 2419 | else |
| 2420 | as_error = as_bad; |
| 2421 | (*as_error) (_("64bit mode not supported on `%s'."), |
| 2422 | cpu_arch_name ? cpu_arch_name : default_arch); |
| 2423 | } |
| 2424 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
| 2425 | { |
| 2426 | if (check) |
| 2427 | as_error = as_fatal; |
| 2428 | else |
| 2429 | as_error = as_bad; |
| 2430 | (*as_error) (_("32bit mode not supported on `%s'."), |
| 2431 | cpu_arch_name ? cpu_arch_name : default_arch); |
| 2432 | } |
| 2433 | stackop_size = '\0'; |
| 2434 | } |
| 2435 | |
| 2436 | static void |
| 2437 | set_code_flag (int value) |
| 2438 | { |
| 2439 | update_code_flag (value, 0); |
| 2440 | } |
| 2441 | |
| 2442 | static void |
| 2443 | set_16bit_gcc_code_flag (int new_code_flag) |
| 2444 | { |
| 2445 | flag_code = (enum flag_code) new_code_flag; |
| 2446 | if (flag_code != CODE_16BIT) |
| 2447 | abort (); |
| 2448 | cpu_arch_flags.bitfield.cpu64 = 0; |
| 2449 | cpu_arch_flags.bitfield.cpuno64 = 1; |
| 2450 | stackop_size = LONG_MNEM_SUFFIX; |
| 2451 | } |
| 2452 | |
| 2453 | static void |
| 2454 | set_intel_syntax (int syntax_flag) |
| 2455 | { |
| 2456 | /* Find out if register prefixing is specified. */ |
| 2457 | int ask_naked_reg = 0; |
| 2458 | |
| 2459 | SKIP_WHITESPACE (); |
| 2460 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 2461 | { |
| 2462 | char *string; |
| 2463 | int e = get_symbol_name (&string); |
| 2464 | |
| 2465 | if (strcmp (string, "prefix") == 0) |
| 2466 | ask_naked_reg = 1; |
| 2467 | else if (strcmp (string, "noprefix") == 0) |
| 2468 | ask_naked_reg = -1; |
| 2469 | else |
| 2470 | as_bad (_("bad argument to syntax directive.")); |
| 2471 | (void) restore_line_pointer (e); |
| 2472 | } |
| 2473 | demand_empty_rest_of_line (); |
| 2474 | |
| 2475 | intel_syntax = syntax_flag; |
| 2476 | |
| 2477 | if (ask_naked_reg == 0) |
| 2478 | allow_naked_reg = (intel_syntax |
| 2479 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
| 2480 | else |
| 2481 | allow_naked_reg = (ask_naked_reg < 0); |
| 2482 | |
| 2483 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
| 2484 | |
| 2485 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
| 2486 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
| 2487 | register_prefix = allow_naked_reg ? "" : "%"; |
| 2488 | } |
| 2489 | |
| 2490 | static void |
| 2491 | set_intel_mnemonic (int mnemonic_flag) |
| 2492 | { |
| 2493 | intel_mnemonic = mnemonic_flag; |
| 2494 | } |
| 2495 | |
| 2496 | static void |
| 2497 | set_allow_index_reg (int flag) |
| 2498 | { |
| 2499 | allow_index_reg = flag; |
| 2500 | } |
| 2501 | |
| 2502 | static void |
| 2503 | set_check (int what) |
| 2504 | { |
| 2505 | enum check_kind *kind; |
| 2506 | const char *str; |
| 2507 | |
| 2508 | if (what) |
| 2509 | { |
| 2510 | kind = &operand_check; |
| 2511 | str = "operand"; |
| 2512 | } |
| 2513 | else |
| 2514 | { |
| 2515 | kind = &sse_check; |
| 2516 | str = "sse"; |
| 2517 | } |
| 2518 | |
| 2519 | SKIP_WHITESPACE (); |
| 2520 | |
| 2521 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 2522 | { |
| 2523 | char *string; |
| 2524 | int e = get_symbol_name (&string); |
| 2525 | |
| 2526 | if (strcmp (string, "none") == 0) |
| 2527 | *kind = check_none; |
| 2528 | else if (strcmp (string, "warning") == 0) |
| 2529 | *kind = check_warning; |
| 2530 | else if (strcmp (string, "error") == 0) |
| 2531 | *kind = check_error; |
| 2532 | else |
| 2533 | as_bad (_("bad argument to %s_check directive."), str); |
| 2534 | (void) restore_line_pointer (e); |
| 2535 | } |
| 2536 | else |
| 2537 | as_bad (_("missing argument for %s_check directive"), str); |
| 2538 | |
| 2539 | demand_empty_rest_of_line (); |
| 2540 | } |
| 2541 | |
| 2542 | static void |
| 2543 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, |
| 2544 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
| 2545 | { |
| 2546 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 2547 | static const char *arch; |
| 2548 | |
| 2549 | /* Intel LIOM is only supported on ELF. */ |
| 2550 | if (!IS_ELF) |
| 2551 | return; |
| 2552 | |
| 2553 | if (!arch) |
| 2554 | { |
| 2555 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise |
| 2556 | use default_arch. */ |
| 2557 | arch = cpu_arch_name; |
| 2558 | if (!arch) |
| 2559 | arch = default_arch; |
| 2560 | } |
| 2561 | |
| 2562 | /* If we are targeting Intel MCU, we must enable it. */ |
| 2563 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU |
| 2564 | || new_flag.bitfield.cpuiamcu) |
| 2565 | return; |
| 2566 | |
| 2567 | /* If we are targeting Intel L1OM, we must enable it. */ |
| 2568 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
| 2569 | || new_flag.bitfield.cpul1om) |
| 2570 | return; |
| 2571 | |
| 2572 | /* If we are targeting Intel K1OM, we must enable it. */ |
| 2573 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM |
| 2574 | || new_flag.bitfield.cpuk1om) |
| 2575 | return; |
| 2576 | |
| 2577 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
| 2578 | #endif |
| 2579 | } |
| 2580 | |
| 2581 | static void |
| 2582 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
| 2583 | { |
| 2584 | SKIP_WHITESPACE (); |
| 2585 | |
| 2586 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 2587 | { |
| 2588 | char *string; |
| 2589 | int e = get_symbol_name (&string); |
| 2590 | unsigned int j; |
| 2591 | i386_cpu_flags flags; |
| 2592 | |
| 2593 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 2594 | { |
| 2595 | if (strcmp (string, cpu_arch[j].name) == 0) |
| 2596 | { |
| 2597 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
| 2598 | |
| 2599 | if (*string != '.') |
| 2600 | { |
| 2601 | cpu_arch_name = cpu_arch[j].name; |
| 2602 | cpu_sub_arch_name = NULL; |
| 2603 | cpu_arch_flags = cpu_arch[j].flags; |
| 2604 | if (flag_code == CODE_64BIT) |
| 2605 | { |
| 2606 | cpu_arch_flags.bitfield.cpu64 = 1; |
| 2607 | cpu_arch_flags.bitfield.cpuno64 = 0; |
| 2608 | } |
| 2609 | else |
| 2610 | { |
| 2611 | cpu_arch_flags.bitfield.cpu64 = 0; |
| 2612 | cpu_arch_flags.bitfield.cpuno64 = 1; |
| 2613 | } |
| 2614 | cpu_arch_isa = cpu_arch[j].type; |
| 2615 | cpu_arch_isa_flags = cpu_arch[j].flags; |
| 2616 | if (!cpu_arch_tune_set) |
| 2617 | { |
| 2618 | cpu_arch_tune = cpu_arch_isa; |
| 2619 | cpu_arch_tune_flags = cpu_arch_isa_flags; |
| 2620 | } |
| 2621 | break; |
| 2622 | } |
| 2623 | |
| 2624 | flags = cpu_flags_or (cpu_arch_flags, |
| 2625 | cpu_arch[j].flags); |
| 2626 | |
| 2627 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 2628 | { |
| 2629 | if (cpu_sub_arch_name) |
| 2630 | { |
| 2631 | char *name = cpu_sub_arch_name; |
| 2632 | cpu_sub_arch_name = concat (name, |
| 2633 | cpu_arch[j].name, |
| 2634 | (const char *) NULL); |
| 2635 | free (name); |
| 2636 | } |
| 2637 | else |
| 2638 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
| 2639 | cpu_arch_flags = flags; |
| 2640 | cpu_arch_isa_flags = flags; |
| 2641 | } |
| 2642 | else |
| 2643 | cpu_arch_isa_flags |
| 2644 | = cpu_flags_or (cpu_arch_isa_flags, |
| 2645 | cpu_arch[j].flags); |
| 2646 | (void) restore_line_pointer (e); |
| 2647 | demand_empty_rest_of_line (); |
| 2648 | return; |
| 2649 | } |
| 2650 | } |
| 2651 | |
| 2652 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) |
| 2653 | { |
| 2654 | /* Disable an ISA extension. */ |
| 2655 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
| 2656 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) |
| 2657 | { |
| 2658 | flags = cpu_flags_and_not (cpu_arch_flags, |
| 2659 | cpu_noarch[j].flags); |
| 2660 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 2661 | { |
| 2662 | if (cpu_sub_arch_name) |
| 2663 | { |
| 2664 | char *name = cpu_sub_arch_name; |
| 2665 | cpu_sub_arch_name = concat (name, string, |
| 2666 | (const char *) NULL); |
| 2667 | free (name); |
| 2668 | } |
| 2669 | else |
| 2670 | cpu_sub_arch_name = xstrdup (string); |
| 2671 | cpu_arch_flags = flags; |
| 2672 | cpu_arch_isa_flags = flags; |
| 2673 | } |
| 2674 | (void) restore_line_pointer (e); |
| 2675 | demand_empty_rest_of_line (); |
| 2676 | return; |
| 2677 | } |
| 2678 | |
| 2679 | j = ARRAY_SIZE (cpu_arch); |
| 2680 | } |
| 2681 | |
| 2682 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 2683 | as_bad (_("no such architecture: `%s'"), string); |
| 2684 | |
| 2685 | *input_line_pointer = e; |
| 2686 | } |
| 2687 | else |
| 2688 | as_bad (_("missing cpu architecture")); |
| 2689 | |
| 2690 | no_cond_jump_promotion = 0; |
| 2691 | if (*input_line_pointer == ',' |
| 2692 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
| 2693 | { |
| 2694 | char *string; |
| 2695 | char e; |
| 2696 | |
| 2697 | ++input_line_pointer; |
| 2698 | e = get_symbol_name (&string); |
| 2699 | |
| 2700 | if (strcmp (string, "nojumps") == 0) |
| 2701 | no_cond_jump_promotion = 1; |
| 2702 | else if (strcmp (string, "jumps") == 0) |
| 2703 | ; |
| 2704 | else |
| 2705 | as_bad (_("no such architecture modifier: `%s'"), string); |
| 2706 | |
| 2707 | (void) restore_line_pointer (e); |
| 2708 | } |
| 2709 | |
| 2710 | demand_empty_rest_of_line (); |
| 2711 | } |
| 2712 | |
| 2713 | enum bfd_architecture |
| 2714 | i386_arch (void) |
| 2715 | { |
| 2716 | if (cpu_arch_isa == PROCESSOR_L1OM) |
| 2717 | { |
| 2718 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2719 | || flag_code != CODE_64BIT) |
| 2720 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
| 2721 | return bfd_arch_l1om; |
| 2722 | } |
| 2723 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
| 2724 | { |
| 2725 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2726 | || flag_code != CODE_64BIT) |
| 2727 | as_fatal (_("Intel K1OM is 64bit ELF only")); |
| 2728 | return bfd_arch_k1om; |
| 2729 | } |
| 2730 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
| 2731 | { |
| 2732 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2733 | || flag_code == CODE_64BIT) |
| 2734 | as_fatal (_("Intel MCU is 32bit ELF only")); |
| 2735 | return bfd_arch_iamcu; |
| 2736 | } |
| 2737 | else |
| 2738 | return bfd_arch_i386; |
| 2739 | } |
| 2740 | |
| 2741 | unsigned long |
| 2742 | i386_mach (void) |
| 2743 | { |
| 2744 | if (!strncmp (default_arch, "x86_64", 6)) |
| 2745 | { |
| 2746 | if (cpu_arch_isa == PROCESSOR_L1OM) |
| 2747 | { |
| 2748 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2749 | || default_arch[6] != '\0') |
| 2750 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
| 2751 | return bfd_mach_l1om; |
| 2752 | } |
| 2753 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
| 2754 | { |
| 2755 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
| 2756 | || default_arch[6] != '\0') |
| 2757 | as_fatal (_("Intel K1OM is 64bit ELF only")); |
| 2758 | return bfd_mach_k1om; |
| 2759 | } |
| 2760 | else if (default_arch[6] == '\0') |
| 2761 | return bfd_mach_x86_64; |
| 2762 | else |
| 2763 | return bfd_mach_x64_32; |
| 2764 | } |
| 2765 | else if (!strcmp (default_arch, "i386") |
| 2766 | || !strcmp (default_arch, "iamcu")) |
| 2767 | { |
| 2768 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
| 2769 | { |
| 2770 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 2771 | as_fatal (_("Intel MCU is 32bit ELF only")); |
| 2772 | return bfd_mach_i386_iamcu; |
| 2773 | } |
| 2774 | else |
| 2775 | return bfd_mach_i386_i386; |
| 2776 | } |
| 2777 | else |
| 2778 | as_fatal (_("unknown architecture")); |
| 2779 | } |
| 2780 | \f |
| 2781 | void |
| 2782 | md_begin (void) |
| 2783 | { |
| 2784 | const char *hash_err; |
| 2785 | |
| 2786 | /* Support pseudo prefixes like {disp32}. */ |
| 2787 | lex_type ['{'] = LEX_BEGIN_NAME; |
| 2788 | |
| 2789 | /* Initialize op_hash hash table. */ |
| 2790 | op_hash = hash_new (); |
| 2791 | |
| 2792 | { |
| 2793 | const insn_template *optab; |
| 2794 | templates *core_optab; |
| 2795 | |
| 2796 | /* Setup for loop. */ |
| 2797 | optab = i386_optab; |
| 2798 | core_optab = XNEW (templates); |
| 2799 | core_optab->start = optab; |
| 2800 | |
| 2801 | while (1) |
| 2802 | { |
| 2803 | ++optab; |
| 2804 | if (optab->name == NULL |
| 2805 | || strcmp (optab->name, (optab - 1)->name) != 0) |
| 2806 | { |
| 2807 | /* different name --> ship out current template list; |
| 2808 | add to hash table; & begin anew. */ |
| 2809 | core_optab->end = optab; |
| 2810 | hash_err = hash_insert (op_hash, |
| 2811 | (optab - 1)->name, |
| 2812 | (void *) core_optab); |
| 2813 | if (hash_err) |
| 2814 | { |
| 2815 | as_fatal (_("can't hash %s: %s"), |
| 2816 | (optab - 1)->name, |
| 2817 | hash_err); |
| 2818 | } |
| 2819 | if (optab->name == NULL) |
| 2820 | break; |
| 2821 | core_optab = XNEW (templates); |
| 2822 | core_optab->start = optab; |
| 2823 | } |
| 2824 | } |
| 2825 | } |
| 2826 | |
| 2827 | /* Initialize reg_hash hash table. */ |
| 2828 | reg_hash = hash_new (); |
| 2829 | { |
| 2830 | const reg_entry *regtab; |
| 2831 | unsigned int regtab_size = i386_regtab_size; |
| 2832 | |
| 2833 | for (regtab = i386_regtab; regtab_size--; regtab++) |
| 2834 | { |
| 2835 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
| 2836 | if (hash_err) |
| 2837 | as_fatal (_("can't hash %s: %s"), |
| 2838 | regtab->reg_name, |
| 2839 | hash_err); |
| 2840 | } |
| 2841 | } |
| 2842 | |
| 2843 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
| 2844 | { |
| 2845 | int c; |
| 2846 | char *p; |
| 2847 | |
| 2848 | for (c = 0; c < 256; c++) |
| 2849 | { |
| 2850 | if (ISDIGIT (c)) |
| 2851 | { |
| 2852 | digit_chars[c] = c; |
| 2853 | mnemonic_chars[c] = c; |
| 2854 | register_chars[c] = c; |
| 2855 | operand_chars[c] = c; |
| 2856 | } |
| 2857 | else if (ISLOWER (c)) |
| 2858 | { |
| 2859 | mnemonic_chars[c] = c; |
| 2860 | register_chars[c] = c; |
| 2861 | operand_chars[c] = c; |
| 2862 | } |
| 2863 | else if (ISUPPER (c)) |
| 2864 | { |
| 2865 | mnemonic_chars[c] = TOLOWER (c); |
| 2866 | register_chars[c] = mnemonic_chars[c]; |
| 2867 | operand_chars[c] = c; |
| 2868 | } |
| 2869 | else if (c == '{' || c == '}') |
| 2870 | { |
| 2871 | mnemonic_chars[c] = c; |
| 2872 | operand_chars[c] = c; |
| 2873 | } |
| 2874 | |
| 2875 | if (ISALPHA (c) || ISDIGIT (c)) |
| 2876 | identifier_chars[c] = c; |
| 2877 | else if (c >= 128) |
| 2878 | { |
| 2879 | identifier_chars[c] = c; |
| 2880 | operand_chars[c] = c; |
| 2881 | } |
| 2882 | } |
| 2883 | |
| 2884 | #ifdef LEX_AT |
| 2885 | identifier_chars['@'] = '@'; |
| 2886 | #endif |
| 2887 | #ifdef LEX_QM |
| 2888 | identifier_chars['?'] = '?'; |
| 2889 | operand_chars['?'] = '?'; |
| 2890 | #endif |
| 2891 | digit_chars['-'] = '-'; |
| 2892 | mnemonic_chars['_'] = '_'; |
| 2893 | mnemonic_chars['-'] = '-'; |
| 2894 | mnemonic_chars['.'] = '.'; |
| 2895 | identifier_chars['_'] = '_'; |
| 2896 | identifier_chars['.'] = '.'; |
| 2897 | |
| 2898 | for (p = operand_special_chars; *p != '\0'; p++) |
| 2899 | operand_chars[(unsigned char) *p] = *p; |
| 2900 | } |
| 2901 | |
| 2902 | if (flag_code == CODE_64BIT) |
| 2903 | { |
| 2904 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 2905 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 2906 | ? 32 : 16); |
| 2907 | #else |
| 2908 | x86_dwarf2_return_column = 16; |
| 2909 | #endif |
| 2910 | x86_cie_data_alignment = -8; |
| 2911 | } |
| 2912 | else |
| 2913 | { |
| 2914 | x86_dwarf2_return_column = 8; |
| 2915 | x86_cie_data_alignment = -4; |
| 2916 | } |
| 2917 | } |
| 2918 | |
| 2919 | void |
| 2920 | i386_print_statistics (FILE *file) |
| 2921 | { |
| 2922 | hash_print_statistics (file, "i386 opcode", op_hash); |
| 2923 | hash_print_statistics (file, "i386 register", reg_hash); |
| 2924 | } |
| 2925 | \f |
| 2926 | #ifdef DEBUG386 |
| 2927 | |
| 2928 | /* Debugging routines for md_assemble. */ |
| 2929 | static void pte (insn_template *); |
| 2930 | static void pt (i386_operand_type); |
| 2931 | static void pe (expressionS *); |
| 2932 | static void ps (symbolS *); |
| 2933 | |
| 2934 | static void |
| 2935 | pi (char *line, i386_insn *x) |
| 2936 | { |
| 2937 | unsigned int j; |
| 2938 | |
| 2939 | fprintf (stdout, "%s: template ", line); |
| 2940 | pte (&x->tm); |
| 2941 | fprintf (stdout, " address: base %s index %s scale %x\n", |
| 2942 | x->base_reg ? x->base_reg->reg_name : "none", |
| 2943 | x->index_reg ? x->index_reg->reg_name : "none", |
| 2944 | x->log2_scale_factor); |
| 2945 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", |
| 2946 | x->rm.mode, x->rm.reg, x->rm.regmem); |
| 2947 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
| 2948 | x->sib.base, x->sib.index, x->sib.scale); |
| 2949 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", |
| 2950 | (x->rex & REX_W) != 0, |
| 2951 | (x->rex & REX_R) != 0, |
| 2952 | (x->rex & REX_X) != 0, |
| 2953 | (x->rex & REX_B) != 0); |
| 2954 | for (j = 0; j < x->operands; j++) |
| 2955 | { |
| 2956 | fprintf (stdout, " #%d: ", j + 1); |
| 2957 | pt (x->types[j]); |
| 2958 | fprintf (stdout, "\n"); |
| 2959 | if (x->types[j].bitfield.reg |
| 2960 | || x->types[j].bitfield.regmmx |
| 2961 | || x->types[j].bitfield.regsimd |
| 2962 | || x->types[j].bitfield.sreg2 |
| 2963 | || x->types[j].bitfield.sreg3 |
| 2964 | || x->types[j].bitfield.control |
| 2965 | || x->types[j].bitfield.debug |
| 2966 | || x->types[j].bitfield.test) |
| 2967 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
| 2968 | if (operand_type_check (x->types[j], imm)) |
| 2969 | pe (x->op[j].imms); |
| 2970 | if (operand_type_check (x->types[j], disp)) |
| 2971 | pe (x->op[j].disps); |
| 2972 | } |
| 2973 | } |
| 2974 | |
| 2975 | static void |
| 2976 | pte (insn_template *t) |
| 2977 | { |
| 2978 | unsigned int j; |
| 2979 | fprintf (stdout, " %d operands ", t->operands); |
| 2980 | fprintf (stdout, "opcode %x ", t->base_opcode); |
| 2981 | if (t->extension_opcode != None) |
| 2982 | fprintf (stdout, "ext %x ", t->extension_opcode); |
| 2983 | if (t->opcode_modifier.d) |
| 2984 | fprintf (stdout, "D"); |
| 2985 | if (t->opcode_modifier.w) |
| 2986 | fprintf (stdout, "W"); |
| 2987 | fprintf (stdout, "\n"); |
| 2988 | for (j = 0; j < t->operands; j++) |
| 2989 | { |
| 2990 | fprintf (stdout, " #%d type ", j + 1); |
| 2991 | pt (t->operand_types[j]); |
| 2992 | fprintf (stdout, "\n"); |
| 2993 | } |
| 2994 | } |
| 2995 | |
| 2996 | static void |
| 2997 | pe (expressionS *e) |
| 2998 | { |
| 2999 | fprintf (stdout, " operation %d\n", e->X_op); |
| 3000 | fprintf (stdout, " add_number %ld (%lx)\n", |
| 3001 | (long) e->X_add_number, (long) e->X_add_number); |
| 3002 | if (e->X_add_symbol) |
| 3003 | { |
| 3004 | fprintf (stdout, " add_symbol "); |
| 3005 | ps (e->X_add_symbol); |
| 3006 | fprintf (stdout, "\n"); |
| 3007 | } |
| 3008 | if (e->X_op_symbol) |
| 3009 | { |
| 3010 | fprintf (stdout, " op_symbol "); |
| 3011 | ps (e->X_op_symbol); |
| 3012 | fprintf (stdout, "\n"); |
| 3013 | } |
| 3014 | } |
| 3015 | |
| 3016 | static void |
| 3017 | ps (symbolS *s) |
| 3018 | { |
| 3019 | fprintf (stdout, "%s type %s%s", |
| 3020 | S_GET_NAME (s), |
| 3021 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", |
| 3022 | segment_name (S_GET_SEGMENT (s))); |
| 3023 | } |
| 3024 | |
| 3025 | static struct type_name |
| 3026 | { |
| 3027 | i386_operand_type mask; |
| 3028 | const char *name; |
| 3029 | } |
| 3030 | const type_names[] = |
| 3031 | { |
| 3032 | { OPERAND_TYPE_REG8, "r8" }, |
| 3033 | { OPERAND_TYPE_REG16, "r16" }, |
| 3034 | { OPERAND_TYPE_REG32, "r32" }, |
| 3035 | { OPERAND_TYPE_REG64, "r64" }, |
| 3036 | { OPERAND_TYPE_IMM8, "i8" }, |
| 3037 | { OPERAND_TYPE_IMM8, "i8s" }, |
| 3038 | { OPERAND_TYPE_IMM16, "i16" }, |
| 3039 | { OPERAND_TYPE_IMM32, "i32" }, |
| 3040 | { OPERAND_TYPE_IMM32S, "i32s" }, |
| 3041 | { OPERAND_TYPE_IMM64, "i64" }, |
| 3042 | { OPERAND_TYPE_IMM1, "i1" }, |
| 3043 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, |
| 3044 | { OPERAND_TYPE_DISP8, "d8" }, |
| 3045 | { OPERAND_TYPE_DISP16, "d16" }, |
| 3046 | { OPERAND_TYPE_DISP32, "d32" }, |
| 3047 | { OPERAND_TYPE_DISP32S, "d32s" }, |
| 3048 | { OPERAND_TYPE_DISP64, "d64" }, |
| 3049 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, |
| 3050 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, |
| 3051 | { OPERAND_TYPE_CONTROL, "control reg" }, |
| 3052 | { OPERAND_TYPE_TEST, "test reg" }, |
| 3053 | { OPERAND_TYPE_DEBUG, "debug reg" }, |
| 3054 | { OPERAND_TYPE_FLOATREG, "FReg" }, |
| 3055 | { OPERAND_TYPE_FLOATACC, "FAcc" }, |
| 3056 | { OPERAND_TYPE_SREG2, "SReg2" }, |
| 3057 | { OPERAND_TYPE_SREG3, "SReg3" }, |
| 3058 | { OPERAND_TYPE_ACC, "Acc" }, |
| 3059 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, |
| 3060 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
| 3061 | { OPERAND_TYPE_REGXMM, "rXMM" }, |
| 3062 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
| 3063 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
| 3064 | { OPERAND_TYPE_REGMASK, "Mask reg" }, |
| 3065 | { OPERAND_TYPE_ESSEG, "es" }, |
| 3066 | }; |
| 3067 | |
| 3068 | static void |
| 3069 | pt (i386_operand_type t) |
| 3070 | { |
| 3071 | unsigned int j; |
| 3072 | i386_operand_type a; |
| 3073 | |
| 3074 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
| 3075 | { |
| 3076 | a = operand_type_and (t, type_names[j].mask); |
| 3077 | if (!operand_type_all_zero (&a)) |
| 3078 | fprintf (stdout, "%s, ", type_names[j].name); |
| 3079 | } |
| 3080 | fflush (stdout); |
| 3081 | } |
| 3082 | |
| 3083 | #endif /* DEBUG386 */ |
| 3084 | \f |
| 3085 | static bfd_reloc_code_real_type |
| 3086 | reloc (unsigned int size, |
| 3087 | int pcrel, |
| 3088 | int sign, |
| 3089 | bfd_reloc_code_real_type other) |
| 3090 | { |
| 3091 | if (other != NO_RELOC) |
| 3092 | { |
| 3093 | reloc_howto_type *rel; |
| 3094 | |
| 3095 | if (size == 8) |
| 3096 | switch (other) |
| 3097 | { |
| 3098 | case BFD_RELOC_X86_64_GOT32: |
| 3099 | return BFD_RELOC_X86_64_GOT64; |
| 3100 | break; |
| 3101 | case BFD_RELOC_X86_64_GOTPLT64: |
| 3102 | return BFD_RELOC_X86_64_GOTPLT64; |
| 3103 | break; |
| 3104 | case BFD_RELOC_X86_64_PLTOFF64: |
| 3105 | return BFD_RELOC_X86_64_PLTOFF64; |
| 3106 | break; |
| 3107 | case BFD_RELOC_X86_64_GOTPC32: |
| 3108 | other = BFD_RELOC_X86_64_GOTPC64; |
| 3109 | break; |
| 3110 | case BFD_RELOC_X86_64_GOTPCREL: |
| 3111 | other = BFD_RELOC_X86_64_GOTPCREL64; |
| 3112 | break; |
| 3113 | case BFD_RELOC_X86_64_TPOFF32: |
| 3114 | other = BFD_RELOC_X86_64_TPOFF64; |
| 3115 | break; |
| 3116 | case BFD_RELOC_X86_64_DTPOFF32: |
| 3117 | other = BFD_RELOC_X86_64_DTPOFF64; |
| 3118 | break; |
| 3119 | default: |
| 3120 | break; |
| 3121 | } |
| 3122 | |
| 3123 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3124 | if (other == BFD_RELOC_SIZE32) |
| 3125 | { |
| 3126 | if (size == 8) |
| 3127 | other = BFD_RELOC_SIZE64; |
| 3128 | if (pcrel) |
| 3129 | { |
| 3130 | as_bad (_("there are no pc-relative size relocations")); |
| 3131 | return NO_RELOC; |
| 3132 | } |
| 3133 | } |
| 3134 | #endif |
| 3135 | |
| 3136 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
| 3137 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
| 3138 | sign = -1; |
| 3139 | |
| 3140 | rel = bfd_reloc_type_lookup (stdoutput, other); |
| 3141 | if (!rel) |
| 3142 | as_bad (_("unknown relocation (%u)"), other); |
| 3143 | else if (size != bfd_get_reloc_size (rel)) |
| 3144 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
| 3145 | bfd_get_reloc_size (rel), |
| 3146 | size); |
| 3147 | else if (pcrel && !rel->pc_relative) |
| 3148 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
| 3149 | else if ((rel->complain_on_overflow == complain_overflow_signed |
| 3150 | && !sign) |
| 3151 | || (rel->complain_on_overflow == complain_overflow_unsigned |
| 3152 | && sign > 0)) |
| 3153 | as_bad (_("relocated field and relocation type differ in signedness")); |
| 3154 | else |
| 3155 | return other; |
| 3156 | return NO_RELOC; |
| 3157 | } |
| 3158 | |
| 3159 | if (pcrel) |
| 3160 | { |
| 3161 | if (!sign) |
| 3162 | as_bad (_("there are no unsigned pc-relative relocations")); |
| 3163 | switch (size) |
| 3164 | { |
| 3165 | case 1: return BFD_RELOC_8_PCREL; |
| 3166 | case 2: return BFD_RELOC_16_PCREL; |
| 3167 | case 4: return BFD_RELOC_32_PCREL; |
| 3168 | case 8: return BFD_RELOC_64_PCREL; |
| 3169 | } |
| 3170 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
| 3171 | } |
| 3172 | else |
| 3173 | { |
| 3174 | if (sign > 0) |
| 3175 | switch (size) |
| 3176 | { |
| 3177 | case 4: return BFD_RELOC_X86_64_32S; |
| 3178 | } |
| 3179 | else |
| 3180 | switch (size) |
| 3181 | { |
| 3182 | case 1: return BFD_RELOC_8; |
| 3183 | case 2: return BFD_RELOC_16; |
| 3184 | case 4: return BFD_RELOC_32; |
| 3185 | case 8: return BFD_RELOC_64; |
| 3186 | } |
| 3187 | as_bad (_("cannot do %s %u byte relocation"), |
| 3188 | sign > 0 ? "signed" : "unsigned", size); |
| 3189 | } |
| 3190 | |
| 3191 | return NO_RELOC; |
| 3192 | } |
| 3193 | |
| 3194 | /* Here we decide which fixups can be adjusted to make them relative to |
| 3195 | the beginning of the section instead of the symbol. Basically we need |
| 3196 | to make sure that the dynamic relocations are done correctly, so in |
| 3197 | some cases we force the original symbol to be used. */ |
| 3198 | |
| 3199 | int |
| 3200 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
| 3201 | { |
| 3202 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 3203 | if (!IS_ELF) |
| 3204 | return 1; |
| 3205 | |
| 3206 | /* Don't adjust pc-relative references to merge sections in 64-bit |
| 3207 | mode. */ |
| 3208 | if (use_rela_relocations |
| 3209 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 |
| 3210 | && fixP->fx_pcrel) |
| 3211 | return 0; |
| 3212 | |
| 3213 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
| 3214 | and changed later by validate_fix. */ |
| 3215 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol |
| 3216 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) |
| 3217 | return 0; |
| 3218 | |
| 3219 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
| 3220 | for size relocations. */ |
| 3221 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 |
| 3222 | || fixP->fx_r_type == BFD_RELOC_SIZE64 |
| 3223 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
| 3224 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
| 3225 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
| 3226 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
| 3227 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
| 3228 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM |
| 3229 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 |
| 3230 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 |
| 3231 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
| 3232 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE |
| 3233 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
| 3234 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE |
| 3235 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
| 3236 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL |
| 3237 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
| 3238 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
| 3239 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
| 3240 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
| 3241 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX |
| 3242 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
| 3243 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD |
| 3244 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 |
| 3245 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
| 3246 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
| 3247 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 |
| 3248 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
| 3249 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 |
| 3250 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
| 3251 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL |
| 3252 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 3253 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 3254 | return 0; |
| 3255 | #endif |
| 3256 | return 1; |
| 3257 | } |
| 3258 | |
| 3259 | static int |
| 3260 | intel_float_operand (const char *mnemonic) |
| 3261 | { |
| 3262 | /* Note that the value returned is meaningful only for opcodes with (memory) |
| 3263 | operands, hence the code here is free to improperly handle opcodes that |
| 3264 | have no operands (for better performance and smaller code). */ |
| 3265 | |
| 3266 | if (mnemonic[0] != 'f') |
| 3267 | return 0; /* non-math */ |
| 3268 | |
| 3269 | switch (mnemonic[1]) |
| 3270 | { |
| 3271 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and |
| 3272 | the fs segment override prefix not currently handled because no |
| 3273 | call path can make opcodes without operands get here */ |
| 3274 | case 'i': |
| 3275 | return 2 /* integer op */; |
| 3276 | case 'l': |
| 3277 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) |
| 3278 | return 3; /* fldcw/fldenv */ |
| 3279 | break; |
| 3280 | case 'n': |
| 3281 | if (mnemonic[2] != 'o' /* fnop */) |
| 3282 | return 3; /* non-waiting control op */ |
| 3283 | break; |
| 3284 | case 'r': |
| 3285 | if (mnemonic[2] == 's') |
| 3286 | return 3; /* frstor/frstpm */ |
| 3287 | break; |
| 3288 | case 's': |
| 3289 | if (mnemonic[2] == 'a') |
| 3290 | return 3; /* fsave */ |
| 3291 | if (mnemonic[2] == 't') |
| 3292 | { |
| 3293 | switch (mnemonic[3]) |
| 3294 | { |
| 3295 | case 'c': /* fstcw */ |
| 3296 | case 'd': /* fstdw */ |
| 3297 | case 'e': /* fstenv */ |
| 3298 | case 's': /* fsts[gw] */ |
| 3299 | return 3; |
| 3300 | } |
| 3301 | } |
| 3302 | break; |
| 3303 | case 'x': |
| 3304 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') |
| 3305 | return 0; /* fxsave/fxrstor are not really math ops */ |
| 3306 | break; |
| 3307 | } |
| 3308 | |
| 3309 | return 1; |
| 3310 | } |
| 3311 | |
| 3312 | /* Build the VEX prefix. */ |
| 3313 | |
| 3314 | static void |
| 3315 | build_vex_prefix (const insn_template *t) |
| 3316 | { |
| 3317 | unsigned int register_specifier; |
| 3318 | unsigned int implied_prefix; |
| 3319 | unsigned int vector_length; |
| 3320 | |
| 3321 | /* Check register specifier. */ |
| 3322 | if (i.vex.register_specifier) |
| 3323 | { |
| 3324 | register_specifier = |
| 3325 | ~register_number (i.vex.register_specifier) & 0xf; |
| 3326 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); |
| 3327 | } |
| 3328 | else |
| 3329 | register_specifier = 0xf; |
| 3330 | |
| 3331 | /* Use 2-byte VEX prefix by swapping destination and source |
| 3332 | operand. */ |
| 3333 | if (i.vec_encoding != vex_encoding_vex3 |
| 3334 | && i.dir_encoding == dir_encoding_default |
| 3335 | && i.operands == i.reg_operands |
| 3336 | && i.tm.opcode_modifier.vexopcode == VEX0F |
| 3337 | && i.tm.opcode_modifier.load |
| 3338 | && i.rex == REX_B) |
| 3339 | { |
| 3340 | unsigned int xchg = i.operands - 1; |
| 3341 | union i386_op temp_op; |
| 3342 | i386_operand_type temp_type; |
| 3343 | |
| 3344 | temp_type = i.types[xchg]; |
| 3345 | i.types[xchg] = i.types[0]; |
| 3346 | i.types[0] = temp_type; |
| 3347 | temp_op = i.op[xchg]; |
| 3348 | i.op[xchg] = i.op[0]; |
| 3349 | i.op[0] = temp_op; |
| 3350 | |
| 3351 | gas_assert (i.rm.mode == 3); |
| 3352 | |
| 3353 | i.rex = REX_R; |
| 3354 | xchg = i.rm.regmem; |
| 3355 | i.rm.regmem = i.rm.reg; |
| 3356 | i.rm.reg = xchg; |
| 3357 | |
| 3358 | /* Use the next insn. */ |
| 3359 | i.tm = t[1]; |
| 3360 | } |
| 3361 | |
| 3362 | if (i.tm.opcode_modifier.vex == VEXScalar) |
| 3363 | vector_length = avxscalar; |
| 3364 | else if (i.tm.opcode_modifier.vex == VEX256) |
| 3365 | vector_length = 1; |
| 3366 | else |
| 3367 | { |
| 3368 | unsigned int op; |
| 3369 | |
| 3370 | /* Determine vector length from the last multi-length vector |
| 3371 | operand. */ |
| 3372 | vector_length = 0; |
| 3373 | for (op = t->operands; op--;) |
| 3374 | if (t->operand_types[op].bitfield.xmmword |
| 3375 | && t->operand_types[op].bitfield.ymmword |
| 3376 | && i.types[op].bitfield.ymmword) |
| 3377 | { |
| 3378 | vector_length = 1; |
| 3379 | break; |
| 3380 | } |
| 3381 | } |
| 3382 | |
| 3383 | switch ((i.tm.base_opcode >> 8) & 0xff) |
| 3384 | { |
| 3385 | case 0: |
| 3386 | implied_prefix = 0; |
| 3387 | break; |
| 3388 | case DATA_PREFIX_OPCODE: |
| 3389 | implied_prefix = 1; |
| 3390 | break; |
| 3391 | case REPE_PREFIX_OPCODE: |
| 3392 | implied_prefix = 2; |
| 3393 | break; |
| 3394 | case REPNE_PREFIX_OPCODE: |
| 3395 | implied_prefix = 3; |
| 3396 | break; |
| 3397 | default: |
| 3398 | abort (); |
| 3399 | } |
| 3400 | |
| 3401 | /* Use 2-byte VEX prefix if possible. */ |
| 3402 | if (i.vec_encoding != vex_encoding_vex3 |
| 3403 | && i.tm.opcode_modifier.vexopcode == VEX0F |
| 3404 | && i.tm.opcode_modifier.vexw != VEXW1 |
| 3405 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
| 3406 | { |
| 3407 | /* 2-byte VEX prefix. */ |
| 3408 | unsigned int r; |
| 3409 | |
| 3410 | i.vex.length = 2; |
| 3411 | i.vex.bytes[0] = 0xc5; |
| 3412 | |
| 3413 | /* Check the REX.R bit. */ |
| 3414 | r = (i.rex & REX_R) ? 0 : 1; |
| 3415 | i.vex.bytes[1] = (r << 7 |
| 3416 | | register_specifier << 3 |
| 3417 | | vector_length << 2 |
| 3418 | | implied_prefix); |
| 3419 | } |
| 3420 | else |
| 3421 | { |
| 3422 | /* 3-byte VEX prefix. */ |
| 3423 | unsigned int m, w; |
| 3424 | |
| 3425 | i.vex.length = 3; |
| 3426 | |
| 3427 | switch (i.tm.opcode_modifier.vexopcode) |
| 3428 | { |
| 3429 | case VEX0F: |
| 3430 | m = 0x1; |
| 3431 | i.vex.bytes[0] = 0xc4; |
| 3432 | break; |
| 3433 | case VEX0F38: |
| 3434 | m = 0x2; |
| 3435 | i.vex.bytes[0] = 0xc4; |
| 3436 | break; |
| 3437 | case VEX0F3A: |
| 3438 | m = 0x3; |
| 3439 | i.vex.bytes[0] = 0xc4; |
| 3440 | break; |
| 3441 | case XOP08: |
| 3442 | m = 0x8; |
| 3443 | i.vex.bytes[0] = 0x8f; |
| 3444 | break; |
| 3445 | case XOP09: |
| 3446 | m = 0x9; |
| 3447 | i.vex.bytes[0] = 0x8f; |
| 3448 | break; |
| 3449 | case XOP0A: |
| 3450 | m = 0xa; |
| 3451 | i.vex.bytes[0] = 0x8f; |
| 3452 | break; |
| 3453 | default: |
| 3454 | abort (); |
| 3455 | } |
| 3456 | |
| 3457 | /* The high 3 bits of the second VEX byte are 1's compliment |
| 3458 | of RXB bits from REX. */ |
| 3459 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; |
| 3460 | |
| 3461 | /* Check the REX.W bit. */ |
| 3462 | w = (i.rex & REX_W) ? 1 : 0; |
| 3463 | if (i.tm.opcode_modifier.vexw == VEXW1) |
| 3464 | w = 1; |
| 3465 | |
| 3466 | i.vex.bytes[2] = (w << 7 |
| 3467 | | register_specifier << 3 |
| 3468 | | vector_length << 2 |
| 3469 | | implied_prefix); |
| 3470 | } |
| 3471 | } |
| 3472 | |
| 3473 | static INLINE bfd_boolean |
| 3474 | is_evex_encoding (const insn_template *t) |
| 3475 | { |
| 3476 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
| 3477 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
| 3478 | || t->opcode_modifier.staticrounding || t->opcode_modifier.sae; |
| 3479 | } |
| 3480 | |
| 3481 | static INLINE bfd_boolean |
| 3482 | is_any_vex_encoding (const insn_template *t) |
| 3483 | { |
| 3484 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode |
| 3485 | || is_evex_encoding (t); |
| 3486 | } |
| 3487 | |
| 3488 | /* Build the EVEX prefix. */ |
| 3489 | |
| 3490 | static void |
| 3491 | build_evex_prefix (void) |
| 3492 | { |
| 3493 | unsigned int register_specifier; |
| 3494 | unsigned int implied_prefix; |
| 3495 | unsigned int m, w; |
| 3496 | rex_byte vrex_used = 0; |
| 3497 | |
| 3498 | /* Check register specifier. */ |
| 3499 | if (i.vex.register_specifier) |
| 3500 | { |
| 3501 | gas_assert ((i.vrex & REX_X) == 0); |
| 3502 | |
| 3503 | register_specifier = i.vex.register_specifier->reg_num; |
| 3504 | if ((i.vex.register_specifier->reg_flags & RegRex)) |
| 3505 | register_specifier += 8; |
| 3506 | /* The upper 16 registers are encoded in the fourth byte of the |
| 3507 | EVEX prefix. */ |
| 3508 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) |
| 3509 | i.vex.bytes[3] = 0x8; |
| 3510 | register_specifier = ~register_specifier & 0xf; |
| 3511 | } |
| 3512 | else |
| 3513 | { |
| 3514 | register_specifier = 0xf; |
| 3515 | |
| 3516 | /* Encode upper 16 vector index register in the fourth byte of |
| 3517 | the EVEX prefix. */ |
| 3518 | if (!(i.vrex & REX_X)) |
| 3519 | i.vex.bytes[3] = 0x8; |
| 3520 | else |
| 3521 | vrex_used |= REX_X; |
| 3522 | } |
| 3523 | |
| 3524 | switch ((i.tm.base_opcode >> 8) & 0xff) |
| 3525 | { |
| 3526 | case 0: |
| 3527 | implied_prefix = 0; |
| 3528 | break; |
| 3529 | case DATA_PREFIX_OPCODE: |
| 3530 | implied_prefix = 1; |
| 3531 | break; |
| 3532 | case REPE_PREFIX_OPCODE: |
| 3533 | implied_prefix = 2; |
| 3534 | break; |
| 3535 | case REPNE_PREFIX_OPCODE: |
| 3536 | implied_prefix = 3; |
| 3537 | break; |
| 3538 | default: |
| 3539 | abort (); |
| 3540 | } |
| 3541 | |
| 3542 | /* 4 byte EVEX prefix. */ |
| 3543 | i.vex.length = 4; |
| 3544 | i.vex.bytes[0] = 0x62; |
| 3545 | |
| 3546 | /* mmmm bits. */ |
| 3547 | switch (i.tm.opcode_modifier.vexopcode) |
| 3548 | { |
| 3549 | case VEX0F: |
| 3550 | m = 1; |
| 3551 | break; |
| 3552 | case VEX0F38: |
| 3553 | m = 2; |
| 3554 | break; |
| 3555 | case VEX0F3A: |
| 3556 | m = 3; |
| 3557 | break; |
| 3558 | default: |
| 3559 | abort (); |
| 3560 | break; |
| 3561 | } |
| 3562 | |
| 3563 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
| 3564 | bits from REX. */ |
| 3565 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; |
| 3566 | |
| 3567 | /* The fifth bit of the second EVEX byte is 1's compliment of the |
| 3568 | REX_R bit in VREX. */ |
| 3569 | if (!(i.vrex & REX_R)) |
| 3570 | i.vex.bytes[1] |= 0x10; |
| 3571 | else |
| 3572 | vrex_used |= REX_R; |
| 3573 | |
| 3574 | if ((i.reg_operands + i.imm_operands) == i.operands) |
| 3575 | { |
| 3576 | /* When all operands are registers, the REX_X bit in REX is not |
| 3577 | used. We reuse it to encode the upper 16 registers, which is |
| 3578 | indicated by the REX_B bit in VREX. The REX_X bit is encoded |
| 3579 | as 1's compliment. */ |
| 3580 | if ((i.vrex & REX_B)) |
| 3581 | { |
| 3582 | vrex_used |= REX_B; |
| 3583 | i.vex.bytes[1] &= ~0x40; |
| 3584 | } |
| 3585 | } |
| 3586 | |
| 3587 | /* EVEX instructions shouldn't need the REX prefix. */ |
| 3588 | i.vrex &= ~vrex_used; |
| 3589 | gas_assert (i.vrex == 0); |
| 3590 | |
| 3591 | /* Check the REX.W bit. */ |
| 3592 | w = (i.rex & REX_W) ? 1 : 0; |
| 3593 | if (i.tm.opcode_modifier.vexw) |
| 3594 | { |
| 3595 | if (i.tm.opcode_modifier.vexw == VEXW1) |
| 3596 | w = 1; |
| 3597 | } |
| 3598 | /* If w is not set it means we are dealing with WIG instruction. */ |
| 3599 | else if (!w) |
| 3600 | { |
| 3601 | if (evexwig == evexw1) |
| 3602 | w = 1; |
| 3603 | } |
| 3604 | |
| 3605 | /* Encode the U bit. */ |
| 3606 | implied_prefix |= 0x4; |
| 3607 | |
| 3608 | /* The third byte of the EVEX prefix. */ |
| 3609 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); |
| 3610 | |
| 3611 | /* The fourth byte of the EVEX prefix. */ |
| 3612 | /* The zeroing-masking bit. */ |
| 3613 | if (i.mask && i.mask->zeroing) |
| 3614 | i.vex.bytes[3] |= 0x80; |
| 3615 | |
| 3616 | /* Don't always set the broadcast bit if there is no RC. */ |
| 3617 | if (!i.rounding) |
| 3618 | { |
| 3619 | /* Encode the vector length. */ |
| 3620 | unsigned int vec_length; |
| 3621 | |
| 3622 | if (!i.tm.opcode_modifier.evex |
| 3623 | || i.tm.opcode_modifier.evex == EVEXDYN) |
| 3624 | { |
| 3625 | unsigned int op; |
| 3626 | |
| 3627 | /* Determine vector length from the last multi-length vector |
| 3628 | operand. */ |
| 3629 | vec_length = 0; |
| 3630 | for (op = i.operands; op--;) |
| 3631 | if (i.tm.operand_types[op].bitfield.xmmword |
| 3632 | + i.tm.operand_types[op].bitfield.ymmword |
| 3633 | + i.tm.operand_types[op].bitfield.zmmword > 1) |
| 3634 | { |
| 3635 | if (i.types[op].bitfield.zmmword) |
| 3636 | { |
| 3637 | i.tm.opcode_modifier.evex = EVEX512; |
| 3638 | break; |
| 3639 | } |
| 3640 | else if (i.types[op].bitfield.ymmword) |
| 3641 | { |
| 3642 | i.tm.opcode_modifier.evex = EVEX256; |
| 3643 | break; |
| 3644 | } |
| 3645 | else if (i.types[op].bitfield.xmmword) |
| 3646 | { |
| 3647 | i.tm.opcode_modifier.evex = EVEX128; |
| 3648 | break; |
| 3649 | } |
| 3650 | else if (i.broadcast && (int) op == i.broadcast->operand) |
| 3651 | { |
| 3652 | switch (i.broadcast->bytes) |
| 3653 | { |
| 3654 | case 64: |
| 3655 | i.tm.opcode_modifier.evex = EVEX512; |
| 3656 | break; |
| 3657 | case 32: |
| 3658 | i.tm.opcode_modifier.evex = EVEX256; |
| 3659 | break; |
| 3660 | case 16: |
| 3661 | i.tm.opcode_modifier.evex = EVEX128; |
| 3662 | break; |
| 3663 | default: |
| 3664 | abort (); |
| 3665 | } |
| 3666 | break; |
| 3667 | } |
| 3668 | } |
| 3669 | |
| 3670 | if (op >= MAX_OPERANDS) |
| 3671 | abort (); |
| 3672 | } |
| 3673 | |
| 3674 | switch (i.tm.opcode_modifier.evex) |
| 3675 | { |
| 3676 | case EVEXLIG: /* LL' is ignored */ |
| 3677 | vec_length = evexlig << 5; |
| 3678 | break; |
| 3679 | case EVEX128: |
| 3680 | vec_length = 0 << 5; |
| 3681 | break; |
| 3682 | case EVEX256: |
| 3683 | vec_length = 1 << 5; |
| 3684 | break; |
| 3685 | case EVEX512: |
| 3686 | vec_length = 2 << 5; |
| 3687 | break; |
| 3688 | default: |
| 3689 | abort (); |
| 3690 | break; |
| 3691 | } |
| 3692 | i.vex.bytes[3] |= vec_length; |
| 3693 | /* Encode the broadcast bit. */ |
| 3694 | if (i.broadcast) |
| 3695 | i.vex.bytes[3] |= 0x10; |
| 3696 | } |
| 3697 | else |
| 3698 | { |
| 3699 | if (i.rounding->type != saeonly) |
| 3700 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); |
| 3701 | else |
| 3702 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
| 3703 | } |
| 3704 | |
| 3705 | if (i.mask && i.mask->mask) |
| 3706 | i.vex.bytes[3] |= i.mask->mask->reg_num; |
| 3707 | } |
| 3708 | |
| 3709 | static void |
| 3710 | process_immext (void) |
| 3711 | { |
| 3712 | expressionS *exp; |
| 3713 | |
| 3714 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
| 3715 | && i.operands > 0) |
| 3716 | { |
| 3717 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
| 3718 | with an opcode suffix which is coded in the same place as an |
| 3719 | 8-bit immediate field would be. |
| 3720 | Here we check those operands and remove them afterwards. */ |
| 3721 | unsigned int x; |
| 3722 | |
| 3723 | for (x = 0; x < i.operands; x++) |
| 3724 | if (register_number (i.op[x].regs) != x) |
| 3725 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
| 3726 | register_prefix, i.op[x].regs->reg_name, x + 1, |
| 3727 | i.tm.name); |
| 3728 | |
| 3729 | i.operands = 0; |
| 3730 | } |
| 3731 | |
| 3732 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
| 3733 | { |
| 3734 | /* MONITORX/MWAITX instructions have fixed operands with an opcode |
| 3735 | suffix which is coded in the same place as an 8-bit immediate |
| 3736 | field would be. |
| 3737 | Here we check those operands and remove them afterwards. */ |
| 3738 | unsigned int x; |
| 3739 | |
| 3740 | if (i.operands != 3) |
| 3741 | abort(); |
| 3742 | |
| 3743 | for (x = 0; x < 2; x++) |
| 3744 | if (register_number (i.op[x].regs) != x) |
| 3745 | goto bad_register_operand; |
| 3746 | |
| 3747 | /* Check for third operand for mwaitx/monitorx insn. */ |
| 3748 | if (register_number (i.op[x].regs) |
| 3749 | != (x + (i.tm.extension_opcode == 0xfb))) |
| 3750 | { |
| 3751 | bad_register_operand: |
| 3752 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
| 3753 | register_prefix, i.op[x].regs->reg_name, x+1, |
| 3754 | i.tm.name); |
| 3755 | } |
| 3756 | |
| 3757 | i.operands = 0; |
| 3758 | } |
| 3759 | |
| 3760 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
| 3761 | which is coded in the same place as an 8-bit immediate field |
| 3762 | would be. Here we fake an 8-bit immediate operand from the |
| 3763 | opcode suffix stored in tm.extension_opcode. |
| 3764 | |
| 3765 | AVX instructions also use this encoding, for some of |
| 3766 | 3 argument instructions. */ |
| 3767 | |
| 3768 | gas_assert (i.imm_operands <= 1 |
| 3769 | && (i.operands <= 2 |
| 3770 | || (is_any_vex_encoding (&i.tm) |
| 3771 | && i.operands <= 4))); |
| 3772 | |
| 3773 | exp = &im_expressions[i.imm_operands++]; |
| 3774 | i.op[i.operands].imms = exp; |
| 3775 | i.types[i.operands] = imm8; |
| 3776 | i.operands++; |
| 3777 | exp->X_op = O_constant; |
| 3778 | exp->X_add_number = i.tm.extension_opcode; |
| 3779 | i.tm.extension_opcode = None; |
| 3780 | } |
| 3781 | |
| 3782 | |
| 3783 | static int |
| 3784 | check_hle (void) |
| 3785 | { |
| 3786 | switch (i.tm.opcode_modifier.hleprefixok) |
| 3787 | { |
| 3788 | default: |
| 3789 | abort (); |
| 3790 | case HLEPrefixNone: |
| 3791 | as_bad (_("invalid instruction `%s' after `%s'"), |
| 3792 | i.tm.name, i.hle_prefix); |
| 3793 | return 0; |
| 3794 | case HLEPrefixLock: |
| 3795 | if (i.prefix[LOCK_PREFIX]) |
| 3796 | return 1; |
| 3797 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
| 3798 | return 0; |
| 3799 | case HLEPrefixAny: |
| 3800 | return 1; |
| 3801 | case HLEPrefixRelease: |
| 3802 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
| 3803 | { |
| 3804 | as_bad (_("instruction `%s' after `xacquire' not allowed"), |
| 3805 | i.tm.name); |
| 3806 | return 0; |
| 3807 | } |
| 3808 | if (i.mem_operands == 0 |
| 3809 | || !operand_type_check (i.types[i.operands - 1], anymem)) |
| 3810 | { |
| 3811 | as_bad (_("memory destination needed for instruction `%s'" |
| 3812 | " after `xrelease'"), i.tm.name); |
| 3813 | return 0; |
| 3814 | } |
| 3815 | return 1; |
| 3816 | } |
| 3817 | } |
| 3818 | |
| 3819 | /* Try the shortest encoding by shortening operand size. */ |
| 3820 | |
| 3821 | static void |
| 3822 | optimize_encoding (void) |
| 3823 | { |
| 3824 | int j; |
| 3825 | |
| 3826 | if (optimize_for_space |
| 3827 | && i.reg_operands == 1 |
| 3828 | && i.imm_operands == 1 |
| 3829 | && !i.types[1].bitfield.byte |
| 3830 | && i.op[0].imms->X_op == O_constant |
| 3831 | && fits_in_imm7 (i.op[0].imms->X_add_number) |
| 3832 | && ((i.tm.base_opcode == 0xa8 |
| 3833 | && i.tm.extension_opcode == None) |
| 3834 | || (i.tm.base_opcode == 0xf6 |
| 3835 | && i.tm.extension_opcode == 0x0))) |
| 3836 | { |
| 3837 | /* Optimize: -Os: |
| 3838 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 |
| 3839 | */ |
| 3840 | unsigned int base_regnum = i.op[1].regs->reg_num; |
| 3841 | if (flag_code == CODE_64BIT || base_regnum < 4) |
| 3842 | { |
| 3843 | i.types[1].bitfield.byte = 1; |
| 3844 | /* Ignore the suffix. */ |
| 3845 | i.suffix = 0; |
| 3846 | if (base_regnum >= 4 |
| 3847 | && !(i.op[1].regs->reg_flags & RegRex)) |
| 3848 | { |
| 3849 | /* Handle SP, BP, SI and DI registers. */ |
| 3850 | if (i.types[1].bitfield.word) |
| 3851 | j = 16; |
| 3852 | else if (i.types[1].bitfield.dword) |
| 3853 | j = 32; |
| 3854 | else |
| 3855 | j = 48; |
| 3856 | i.op[1].regs -= j; |
| 3857 | } |
| 3858 | } |
| 3859 | } |
| 3860 | else if (flag_code == CODE_64BIT |
| 3861 | && ((i.types[1].bitfield.qword |
| 3862 | && i.reg_operands == 1 |
| 3863 | && i.imm_operands == 1 |
| 3864 | && i.op[0].imms->X_op == O_constant |
| 3865 | && ((i.tm.base_opcode == 0xb0 |
| 3866 | && i.tm.extension_opcode == None |
| 3867 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) |
| 3868 | || (fits_in_imm31 (i.op[0].imms->X_add_number) |
| 3869 | && (((i.tm.base_opcode == 0x24 |
| 3870 | || i.tm.base_opcode == 0xa8) |
| 3871 | && i.tm.extension_opcode == None) |
| 3872 | || (i.tm.base_opcode == 0x80 |
| 3873 | && i.tm.extension_opcode == 0x4) |
| 3874 | || ((i.tm.base_opcode == 0xf6 |
| 3875 | || i.tm.base_opcode == 0xc6) |
| 3876 | && i.tm.extension_opcode == 0x0))))) |
| 3877 | || (i.types[0].bitfield.qword |
| 3878 | && ((i.reg_operands == 2 |
| 3879 | && i.op[0].regs == i.op[1].regs |
| 3880 | && ((i.tm.base_opcode == 0x30 |
| 3881 | || i.tm.base_opcode == 0x28) |
| 3882 | && i.tm.extension_opcode == None)) |
| 3883 | || (i.reg_operands == 1 |
| 3884 | && i.operands == 1 |
| 3885 | && i.tm.base_opcode == 0x30 |
| 3886 | && i.tm.extension_opcode == None))))) |
| 3887 | { |
| 3888 | /* Optimize: -O: |
| 3889 | andq $imm31, %r64 -> andl $imm31, %r32 |
| 3890 | testq $imm31, %r64 -> testl $imm31, %r32 |
| 3891 | xorq %r64, %r64 -> xorl %r32, %r32 |
| 3892 | subq %r64, %r64 -> subl %r32, %r32 |
| 3893 | movq $imm31, %r64 -> movl $imm31, %r32 |
| 3894 | movq $imm32, %r64 -> movl $imm32, %r32 |
| 3895 | */ |
| 3896 | i.tm.opcode_modifier.norex64 = 1; |
| 3897 | if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6) |
| 3898 | { |
| 3899 | /* Handle |
| 3900 | movq $imm31, %r64 -> movl $imm31, %r32 |
| 3901 | movq $imm32, %r64 -> movl $imm32, %r32 |
| 3902 | */ |
| 3903 | i.tm.operand_types[0].bitfield.imm32 = 1; |
| 3904 | i.tm.operand_types[0].bitfield.imm32s = 0; |
| 3905 | i.tm.operand_types[0].bitfield.imm64 = 0; |
| 3906 | i.types[0].bitfield.imm32 = 1; |
| 3907 | i.types[0].bitfield.imm32s = 0; |
| 3908 | i.types[0].bitfield.imm64 = 0; |
| 3909 | i.types[1].bitfield.dword = 1; |
| 3910 | i.types[1].bitfield.qword = 0; |
| 3911 | if (i.tm.base_opcode == 0xc6) |
| 3912 | { |
| 3913 | /* Handle |
| 3914 | movq $imm31, %r64 -> movl $imm31, %r32 |
| 3915 | */ |
| 3916 | i.tm.base_opcode = 0xb0; |
| 3917 | i.tm.extension_opcode = None; |
| 3918 | i.tm.opcode_modifier.shortform = 1; |
| 3919 | i.tm.opcode_modifier.modrm = 0; |
| 3920 | } |
| 3921 | } |
| 3922 | } |
| 3923 | else if (optimize > 1 |
| 3924 | && i.reg_operands == 3 |
| 3925 | && i.op[0].regs == i.op[1].regs |
| 3926 | && !i.types[2].bitfield.xmmword |
| 3927 | && (i.tm.opcode_modifier.vex |
| 3928 | || ((!i.mask || i.mask->zeroing) |
| 3929 | && !i.rounding |
| 3930 | && is_evex_encoding (&i.tm) |
| 3931 | && (i.vec_encoding != vex_encoding_evex |
| 3932 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
| 3933 | || (i.tm.operand_types[2].bitfield.zmmword |
| 3934 | && i.types[2].bitfield.ymmword) |
| 3935 | || cpu_arch_isa_flags.bitfield.cpuavx512vl))) |
| 3936 | && ((i.tm.base_opcode == 0x55 |
| 3937 | || i.tm.base_opcode == 0x6655 |
| 3938 | || i.tm.base_opcode == 0x66df |
| 3939 | || i.tm.base_opcode == 0x57 |
| 3940 | || i.tm.base_opcode == 0x6657 |
| 3941 | || i.tm.base_opcode == 0x66ef |
| 3942 | || i.tm.base_opcode == 0x66f8 |
| 3943 | || i.tm.base_opcode == 0x66f9 |
| 3944 | || i.tm.base_opcode == 0x66fa |
| 3945 | || i.tm.base_opcode == 0x66fb |
| 3946 | || i.tm.base_opcode == 0x42 |
| 3947 | || i.tm.base_opcode == 0x6642 |
| 3948 | || i.tm.base_opcode == 0x47 |
| 3949 | || i.tm.base_opcode == 0x6647) |
| 3950 | && i.tm.extension_opcode == None)) |
| 3951 | { |
| 3952 | /* Optimize: -O2: |
| 3953 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
| 3954 | vpsubq and vpsubw: |
| 3955 | EVEX VOP %zmmM, %zmmM, %zmmN |
| 3956 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) |
| 3957 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) |
| 3958 | EVEX VOP %ymmM, %ymmM, %ymmN |
| 3959 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) |
| 3960 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) |
| 3961 | VEX VOP %ymmM, %ymmM, %ymmN |
| 3962 | -> VEX VOP %xmmM, %xmmM, %xmmN |
| 3963 | VOP, one of vpandn and vpxor: |
| 3964 | VEX VOP %ymmM, %ymmM, %ymmN |
| 3965 | -> VEX VOP %xmmM, %xmmM, %xmmN |
| 3966 | VOP, one of vpandnd and vpandnq: |
| 3967 | EVEX VOP %zmmM, %zmmM, %zmmN |
| 3968 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) |
| 3969 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) |
| 3970 | EVEX VOP %ymmM, %ymmM, %ymmN |
| 3971 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) |
| 3972 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) |
| 3973 | VOP, one of vpxord and vpxorq: |
| 3974 | EVEX VOP %zmmM, %zmmM, %zmmN |
| 3975 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) |
| 3976 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) |
| 3977 | EVEX VOP %ymmM, %ymmM, %ymmN |
| 3978 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) |
| 3979 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) |
| 3980 | VOP, one of kxord and kxorq: |
| 3981 | VEX VOP %kM, %kM, %kN |
| 3982 | -> VEX kxorw %kM, %kM, %kN |
| 3983 | VOP, one of kandnd and kandnq: |
| 3984 | VEX VOP %kM, %kM, %kN |
| 3985 | -> VEX kandnw %kM, %kM, %kN |
| 3986 | */ |
| 3987 | if (is_evex_encoding (&i.tm)) |
| 3988 | { |
| 3989 | if (i.vec_encoding == vex_encoding_evex) |
| 3990 | i.tm.opcode_modifier.evex = EVEX128; |
| 3991 | else |
| 3992 | { |
| 3993 | i.tm.opcode_modifier.vex = VEX128; |
| 3994 | i.tm.opcode_modifier.vexw = VEXW0; |
| 3995 | i.tm.opcode_modifier.evex = 0; |
| 3996 | } |
| 3997 | } |
| 3998 | else if (i.tm.operand_types[0].bitfield.regmask) |
| 3999 | { |
| 4000 | i.tm.base_opcode &= 0xff; |
| 4001 | i.tm.opcode_modifier.vexw = VEXW0; |
| 4002 | } |
| 4003 | else |
| 4004 | i.tm.opcode_modifier.vex = VEX128; |
| 4005 | |
| 4006 | if (i.tm.opcode_modifier.vex) |
| 4007 | for (j = 0; j < 3; j++) |
| 4008 | { |
| 4009 | i.types[j].bitfield.xmmword = 1; |
| 4010 | i.types[j].bitfield.ymmword = 0; |
| 4011 | } |
| 4012 | } |
| 4013 | } |
| 4014 | |
| 4015 | /* This is the guts of the machine-dependent assembler. LINE points to a |
| 4016 | machine dependent instruction. This function is supposed to emit |
| 4017 | the frags/bytes it assembles to. */ |
| 4018 | |
| 4019 | void |
| 4020 | md_assemble (char *line) |
| 4021 | { |
| 4022 | unsigned int j; |
| 4023 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
| 4024 | const insn_template *t; |
| 4025 | |
| 4026 | /* Initialize globals. */ |
| 4027 | memset (&i, '\0', sizeof (i)); |
| 4028 | for (j = 0; j < MAX_OPERANDS; j++) |
| 4029 | i.reloc[j] = NO_RELOC; |
| 4030 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
| 4031 | memset (im_expressions, '\0', sizeof (im_expressions)); |
| 4032 | save_stack_p = save_stack; |
| 4033 | |
| 4034 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
| 4035 | We assume that the scrubber has arranged it so that line[0] is the valid |
| 4036 | start of a (possibly prefixed) mnemonic. */ |
| 4037 | |
| 4038 | line = parse_insn (line, mnemonic); |
| 4039 | if (line == NULL) |
| 4040 | return; |
| 4041 | mnem_suffix = i.suffix; |
| 4042 | |
| 4043 | line = parse_operands (line, mnemonic); |
| 4044 | this_operand = -1; |
| 4045 | xfree (i.memop1_string); |
| 4046 | i.memop1_string = NULL; |
| 4047 | if (line == NULL) |
| 4048 | return; |
| 4049 | |
| 4050 | /* Now we've parsed the mnemonic into a set of templates, and have the |
| 4051 | operands at hand. */ |
| 4052 | |
| 4053 | /* All intel opcodes have reversed operands except for "bound" and |
| 4054 | "enter". We also don't reverse intersegment "jmp" and "call" |
| 4055 | instructions with 2 immediate operands so that the immediate segment |
| 4056 | precedes the offset, as it does when in AT&T mode. */ |
| 4057 | if (intel_syntax |
| 4058 | && i.operands > 1 |
| 4059 | && (strcmp (mnemonic, "bound") != 0) |
| 4060 | && (strcmp (mnemonic, "invlpga") != 0) |
| 4061 | && !(operand_type_check (i.types[0], imm) |
| 4062 | && operand_type_check (i.types[1], imm))) |
| 4063 | swap_operands (); |
| 4064 | |
| 4065 | /* The order of the immediates should be reversed |
| 4066 | for 2 immediates extrq and insertq instructions */ |
| 4067 | if (i.imm_operands == 2 |
| 4068 | && (strcmp (mnemonic, "extrq") == 0 |
| 4069 | || strcmp (mnemonic, "insertq") == 0)) |
| 4070 | swap_2_operands (0, 1); |
| 4071 | |
| 4072 | if (i.imm_operands) |
| 4073 | optimize_imm (); |
| 4074 | |
| 4075 | /* Don't optimize displacement for movabs since it only takes 64bit |
| 4076 | displacement. */ |
| 4077 | if (i.disp_operands |
| 4078 | && i.disp_encoding != disp_encoding_32bit |
| 4079 | && (flag_code != CODE_64BIT |
| 4080 | || strcmp (mnemonic, "movabs") != 0)) |
| 4081 | optimize_disp (); |
| 4082 | |
| 4083 | /* Next, we find a template that matches the given insn, |
| 4084 | making sure the overlap of the given operands types is consistent |
| 4085 | with the template operand types. */ |
| 4086 | |
| 4087 | if (!(t = match_template (mnem_suffix))) |
| 4088 | return; |
| 4089 | |
| 4090 | if (sse_check != check_none |
| 4091 | && !i.tm.opcode_modifier.noavx |
| 4092 | && !i.tm.cpu_flags.bitfield.cpuavx |
| 4093 | && (i.tm.cpu_flags.bitfield.cpusse |
| 4094 | || i.tm.cpu_flags.bitfield.cpusse2 |
| 4095 | || i.tm.cpu_flags.bitfield.cpusse3 |
| 4096 | || i.tm.cpu_flags.bitfield.cpussse3 |
| 4097 | || i.tm.cpu_flags.bitfield.cpusse4_1 |
| 4098 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
| 4099 | || i.tm.cpu_flags.bitfield.cpupclmul |
| 4100 | || i.tm.cpu_flags.bitfield.cpuaes |
| 4101 | || i.tm.cpu_flags.bitfield.cpugfni)) |
| 4102 | { |
| 4103 | (sse_check == check_warning |
| 4104 | ? as_warn |
| 4105 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); |
| 4106 | } |
| 4107 | |
| 4108 | /* Zap movzx and movsx suffix. The suffix has been set from |
| 4109 | "word ptr" or "byte ptr" on the source operand in Intel syntax |
| 4110 | or extracted from mnemonic in AT&T syntax. But we'll use |
| 4111 | the destination register to choose the suffix for encoding. */ |
| 4112 | if ((i.tm.base_opcode & ~9) == 0x0fb6) |
| 4113 | { |
| 4114 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
| 4115 | there is no suffix, the default will be byte extension. */ |
| 4116 | if (i.reg_operands != 2 |
| 4117 | && !i.suffix |
| 4118 | && intel_syntax) |
| 4119 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
| 4120 | |
| 4121 | i.suffix = 0; |
| 4122 | } |
| 4123 | |
| 4124 | if (i.tm.opcode_modifier.fwait) |
| 4125 | if (!add_prefix (FWAIT_OPCODE)) |
| 4126 | return; |
| 4127 | |
| 4128 | /* Check if REP prefix is OK. */ |
| 4129 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) |
| 4130 | { |
| 4131 | as_bad (_("invalid instruction `%s' after `%s'"), |
| 4132 | i.tm.name, i.rep_prefix); |
| 4133 | return; |
| 4134 | } |
| 4135 | |
| 4136 | /* Check for lock without a lockable instruction. Destination operand |
| 4137 | must be memory unless it is xchg (0x86). */ |
| 4138 | if (i.prefix[LOCK_PREFIX] |
| 4139 | && (!i.tm.opcode_modifier.islockable |
| 4140 | || i.mem_operands == 0 |
| 4141 | || (i.tm.base_opcode != 0x86 |
| 4142 | && !operand_type_check (i.types[i.operands - 1], anymem)))) |
| 4143 | { |
| 4144 | as_bad (_("expecting lockable instruction after `lock'")); |
| 4145 | return; |
| 4146 | } |
| 4147 | |
| 4148 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
| 4149 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) |
| 4150 | { |
| 4151 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); |
| 4152 | return; |
| 4153 | } |
| 4154 | |
| 4155 | /* Check if HLE prefix is OK. */ |
| 4156 | if (i.hle_prefix && !check_hle ()) |
| 4157 | return; |
| 4158 | |
| 4159 | /* Check BND prefix. */ |
| 4160 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) |
| 4161 | as_bad (_("expecting valid branch instruction after `bnd'")); |
| 4162 | |
| 4163 | /* Check NOTRACK prefix. */ |
| 4164 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
| 4165 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
| 4166 | |
| 4167 | if (i.tm.cpu_flags.bitfield.cpumpx) |
| 4168 | { |
| 4169 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) |
| 4170 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); |
| 4171 | else if (flag_code != CODE_16BIT |
| 4172 | ? i.prefix[ADDR_PREFIX] |
| 4173 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) |
| 4174 | as_bad (_("16-bit address isn't allowed in MPX instructions")); |
| 4175 | } |
| 4176 | |
| 4177 | /* Insert BND prefix. */ |
| 4178 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
| 4179 | { |
| 4180 | if (!i.prefix[BND_PREFIX]) |
| 4181 | add_prefix (BND_PREFIX_OPCODE); |
| 4182 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) |
| 4183 | { |
| 4184 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); |
| 4185 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; |
| 4186 | } |
| 4187 | } |
| 4188 | |
| 4189 | /* Check string instruction segment overrides. */ |
| 4190 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
| 4191 | { |
| 4192 | if (!check_string ()) |
| 4193 | return; |
| 4194 | i.disp_operands = 0; |
| 4195 | } |
| 4196 | |
| 4197 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
| 4198 | optimize_encoding (); |
| 4199 | |
| 4200 | if (!process_suffix ()) |
| 4201 | return; |
| 4202 | |
| 4203 | /* Update operand types. */ |
| 4204 | for (j = 0; j < i.operands; j++) |
| 4205 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); |
| 4206 | |
| 4207 | /* Make still unresolved immediate matches conform to size of immediate |
| 4208 | given in i.suffix. */ |
| 4209 | if (!finalize_imm ()) |
| 4210 | return; |
| 4211 | |
| 4212 | if (i.types[0].bitfield.imm1) |
| 4213 | i.imm_operands = 0; /* kludge for shift insns. */ |
| 4214 | |
| 4215 | /* We only need to check those implicit registers for instructions |
| 4216 | with 3 operands or less. */ |
| 4217 | if (i.operands <= 3) |
| 4218 | for (j = 0; j < i.operands; j++) |
| 4219 | if (i.types[j].bitfield.inoutportreg |
| 4220 | || i.types[j].bitfield.shiftcount |
| 4221 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
| 4222 | i.reg_operands--; |
| 4223 | |
| 4224 | /* ImmExt should be processed after SSE2AVX. */ |
| 4225 | if (!i.tm.opcode_modifier.sse2avx |
| 4226 | && i.tm.opcode_modifier.immext) |
| 4227 | process_immext (); |
| 4228 | |
| 4229 | /* For insns with operands there are more diddles to do to the opcode. */ |
| 4230 | if (i.operands) |
| 4231 | { |
| 4232 | if (!process_operands ()) |
| 4233 | return; |
| 4234 | } |
| 4235 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
| 4236 | { |
| 4237 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
| 4238 | as_warn (_("translating to `%sp'"), i.tm.name); |
| 4239 | } |
| 4240 | |
| 4241 | if (is_any_vex_encoding (&i.tm)) |
| 4242 | { |
| 4243 | if (flag_code == CODE_16BIT) |
| 4244 | { |
| 4245 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), |
| 4246 | i.tm.name); |
| 4247 | return; |
| 4248 | } |
| 4249 | |
| 4250 | if (i.tm.opcode_modifier.vex) |
| 4251 | build_vex_prefix (t); |
| 4252 | else |
| 4253 | build_evex_prefix (); |
| 4254 | } |
| 4255 | |
| 4256 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
| 4257 | instructions may define INT_OPCODE as well, so avoid this corner |
| 4258 | case for those instructions that use MODRM. */ |
| 4259 | if (i.tm.base_opcode == INT_OPCODE |
| 4260 | && !i.tm.opcode_modifier.modrm |
| 4261 | && i.op[0].imms->X_add_number == 3) |
| 4262 | { |
| 4263 | i.tm.base_opcode = INT3_OPCODE; |
| 4264 | i.imm_operands = 0; |
| 4265 | } |
| 4266 | |
| 4267 | if ((i.tm.opcode_modifier.jump |
| 4268 | || i.tm.opcode_modifier.jumpbyte |
| 4269 | || i.tm.opcode_modifier.jumpdword) |
| 4270 | && i.op[0].disps->X_op == O_constant) |
| 4271 | { |
| 4272 | /* Convert "jmp constant" (and "call constant") to a jump (call) to |
| 4273 | the absolute address given by the constant. Since ix86 jumps and |
| 4274 | calls are pc relative, we need to generate a reloc. */ |
| 4275 | i.op[0].disps->X_add_symbol = &abs_symbol; |
| 4276 | i.op[0].disps->X_op = O_symbol; |
| 4277 | } |
| 4278 | |
| 4279 | if (i.tm.opcode_modifier.rex64) |
| 4280 | i.rex |= REX_W; |
| 4281 | |
| 4282 | /* For 8 bit registers we need an empty rex prefix. Also if the |
| 4283 | instruction already has a prefix, we need to convert old |
| 4284 | registers to new ones. */ |
| 4285 | |
| 4286 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
| 4287 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
| 4288 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
| 4289 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
| 4290 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
| 4291 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) |
| 4292 | && i.rex != 0)) |
| 4293 | { |
| 4294 | int x; |
| 4295 | |
| 4296 | i.rex |= REX_OPCODE; |
| 4297 | for (x = 0; x < 2; x++) |
| 4298 | { |
| 4299 | /* Look for 8 bit operand that uses old registers. */ |
| 4300 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
| 4301 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
| 4302 | { |
| 4303 | /* In case it is "hi" register, give up. */ |
| 4304 | if (i.op[x].regs->reg_num > 3) |
| 4305 | as_bad (_("can't encode register '%s%s' in an " |
| 4306 | "instruction requiring REX prefix."), |
| 4307 | register_prefix, i.op[x].regs->reg_name); |
| 4308 | |
| 4309 | /* Otherwise it is equivalent to the extended register. |
| 4310 | Since the encoding doesn't change this is merely |
| 4311 | cosmetic cleanup for debug output. */ |
| 4312 | |
| 4313 | i.op[x].regs = i.op[x].regs + 8; |
| 4314 | } |
| 4315 | } |
| 4316 | } |
| 4317 | |
| 4318 | if (i.rex == 0 && i.rex_encoding) |
| 4319 | { |
| 4320 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand |
| 4321 | that uses legacy register. If it is "hi" register, don't add |
| 4322 | the REX_OPCODE byte. */ |
| 4323 | int x; |
| 4324 | for (x = 0; x < 2; x++) |
| 4325 | if (i.types[x].bitfield.reg |
| 4326 | && i.types[x].bitfield.byte |
| 4327 | && (i.op[x].regs->reg_flags & RegRex64) == 0 |
| 4328 | && i.op[x].regs->reg_num > 3) |
| 4329 | { |
| 4330 | i.rex_encoding = FALSE; |
| 4331 | break; |
| 4332 | } |
| 4333 | |
| 4334 | if (i.rex_encoding) |
| 4335 | i.rex = REX_OPCODE; |
| 4336 | } |
| 4337 | |
| 4338 | if (i.rex != 0) |
| 4339 | add_prefix (REX_OPCODE | i.rex); |
| 4340 | |
| 4341 | /* We are ready to output the insn. */ |
| 4342 | output_insn (); |
| 4343 | } |
| 4344 | |
| 4345 | static char * |
| 4346 | parse_insn (char *line, char *mnemonic) |
| 4347 | { |
| 4348 | char *l = line; |
| 4349 | char *token_start = l; |
| 4350 | char *mnem_p; |
| 4351 | int supported; |
| 4352 | const insn_template *t; |
| 4353 | char *dot_p = NULL; |
| 4354 | |
| 4355 | while (1) |
| 4356 | { |
| 4357 | mnem_p = mnemonic; |
| 4358 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) |
| 4359 | { |
| 4360 | if (*mnem_p == '.') |
| 4361 | dot_p = mnem_p; |
| 4362 | mnem_p++; |
| 4363 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) |
| 4364 | { |
| 4365 | as_bad (_("no such instruction: `%s'"), token_start); |
| 4366 | return NULL; |
| 4367 | } |
| 4368 | l++; |
| 4369 | } |
| 4370 | if (!is_space_char (*l) |
| 4371 | && *l != END_OF_INSN |
| 4372 | && (intel_syntax |
| 4373 | || (*l != PREFIX_SEPARATOR |
| 4374 | && *l != ','))) |
| 4375 | { |
| 4376 | as_bad (_("invalid character %s in mnemonic"), |
| 4377 | output_invalid (*l)); |
| 4378 | return NULL; |
| 4379 | } |
| 4380 | if (token_start == l) |
| 4381 | { |
| 4382 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
| 4383 | as_bad (_("expecting prefix; got nothing")); |
| 4384 | else |
| 4385 | as_bad (_("expecting mnemonic; got nothing")); |
| 4386 | return NULL; |
| 4387 | } |
| 4388 | |
| 4389 | /* Look up instruction (or prefix) via hash table. */ |
| 4390 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
| 4391 | |
| 4392 | if (*l != END_OF_INSN |
| 4393 | && (!is_space_char (*l) || l[1] != END_OF_INSN) |
| 4394 | && current_templates |
| 4395 | && current_templates->start->opcode_modifier.isprefix) |
| 4396 | { |
| 4397 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
| 4398 | { |
| 4399 | as_bad ((flag_code != CODE_64BIT |
| 4400 | ? _("`%s' is only supported in 64-bit mode") |
| 4401 | : _("`%s' is not supported in 64-bit mode")), |
| 4402 | current_templates->start->name); |
| 4403 | return NULL; |
| 4404 | } |
| 4405 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
| 4406 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ |
| 4407 | if ((current_templates->start->opcode_modifier.size16 |
| 4408 | || current_templates->start->opcode_modifier.size32) |
| 4409 | && flag_code != CODE_64BIT |
| 4410 | && (current_templates->start->opcode_modifier.size32 |
| 4411 | ^ (flag_code == CODE_16BIT))) |
| 4412 | { |
| 4413 | as_bad (_("redundant %s prefix"), |
| 4414 | current_templates->start->name); |
| 4415 | return NULL; |
| 4416 | } |
| 4417 | if (current_templates->start->opcode_length == 0) |
| 4418 | { |
| 4419 | /* Handle pseudo prefixes. */ |
| 4420 | switch (current_templates->start->base_opcode) |
| 4421 | { |
| 4422 | case 0x0: |
| 4423 | /* {disp8} */ |
| 4424 | i.disp_encoding = disp_encoding_8bit; |
| 4425 | break; |
| 4426 | case 0x1: |
| 4427 | /* {disp32} */ |
| 4428 | i.disp_encoding = disp_encoding_32bit; |
| 4429 | break; |
| 4430 | case 0x2: |
| 4431 | /* {load} */ |
| 4432 | i.dir_encoding = dir_encoding_load; |
| 4433 | break; |
| 4434 | case 0x3: |
| 4435 | /* {store} */ |
| 4436 | i.dir_encoding = dir_encoding_store; |
| 4437 | break; |
| 4438 | case 0x4: |
| 4439 | /* {vex2} */ |
| 4440 | i.vec_encoding = vex_encoding_vex2; |
| 4441 | break; |
| 4442 | case 0x5: |
| 4443 | /* {vex3} */ |
| 4444 | i.vec_encoding = vex_encoding_vex3; |
| 4445 | break; |
| 4446 | case 0x6: |
| 4447 | /* {evex} */ |
| 4448 | i.vec_encoding = vex_encoding_evex; |
| 4449 | break; |
| 4450 | case 0x7: |
| 4451 | /* {rex} */ |
| 4452 | i.rex_encoding = TRUE; |
| 4453 | break; |
| 4454 | case 0x8: |
| 4455 | /* {nooptimize} */ |
| 4456 | i.no_optimize = TRUE; |
| 4457 | break; |
| 4458 | default: |
| 4459 | abort (); |
| 4460 | } |
| 4461 | } |
| 4462 | else |
| 4463 | { |
| 4464 | /* Add prefix, checking for repeated prefixes. */ |
| 4465 | switch (add_prefix (current_templates->start->base_opcode)) |
| 4466 | { |
| 4467 | case PREFIX_EXIST: |
| 4468 | return NULL; |
| 4469 | case PREFIX_DS: |
| 4470 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
| 4471 | i.notrack_prefix = current_templates->start->name; |
| 4472 | break; |
| 4473 | case PREFIX_REP: |
| 4474 | if (current_templates->start->cpu_flags.bitfield.cpuhle) |
| 4475 | i.hle_prefix = current_templates->start->name; |
| 4476 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) |
| 4477 | i.bnd_prefix = current_templates->start->name; |
| 4478 | else |
| 4479 | i.rep_prefix = current_templates->start->name; |
| 4480 | break; |
| 4481 | default: |
| 4482 | break; |
| 4483 | } |
| 4484 | } |
| 4485 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
| 4486 | token_start = ++l; |
| 4487 | } |
| 4488 | else |
| 4489 | break; |
| 4490 | } |
| 4491 | |
| 4492 | if (!current_templates) |
| 4493 | { |
| 4494 | /* Check if we should swap operand or force 32bit displacement in |
| 4495 | encoding. */ |
| 4496 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
| 4497 | i.dir_encoding = dir_encoding_store; |
| 4498 | else if (mnem_p - 3 == dot_p |
| 4499 | && dot_p[1] == 'd' |
| 4500 | && dot_p[2] == '8') |
| 4501 | i.disp_encoding = disp_encoding_8bit; |
| 4502 | else if (mnem_p - 4 == dot_p |
| 4503 | && dot_p[1] == 'd' |
| 4504 | && dot_p[2] == '3' |
| 4505 | && dot_p[3] == '2') |
| 4506 | i.disp_encoding = disp_encoding_32bit; |
| 4507 | else |
| 4508 | goto check_suffix; |
| 4509 | mnem_p = dot_p; |
| 4510 | *dot_p = '\0'; |
| 4511 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
| 4512 | } |
| 4513 | |
| 4514 | if (!current_templates) |
| 4515 | { |
| 4516 | check_suffix: |
| 4517 | /* See if we can get a match by trimming off a suffix. */ |
| 4518 | switch (mnem_p[-1]) |
| 4519 | { |
| 4520 | case WORD_MNEM_SUFFIX: |
| 4521 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
| 4522 | i.suffix = SHORT_MNEM_SUFFIX; |
| 4523 | else |
| 4524 | /* Fall through. */ |
| 4525 | case BYTE_MNEM_SUFFIX: |
| 4526 | case QWORD_MNEM_SUFFIX: |
| 4527 | i.suffix = mnem_p[-1]; |
| 4528 | mnem_p[-1] = '\0'; |
| 4529 | current_templates = (const templates *) hash_find (op_hash, |
| 4530 | mnemonic); |
| 4531 | break; |
| 4532 | case SHORT_MNEM_SUFFIX: |
| 4533 | case LONG_MNEM_SUFFIX: |
| 4534 | if (!intel_syntax) |
| 4535 | { |
| 4536 | i.suffix = mnem_p[-1]; |
| 4537 | mnem_p[-1] = '\0'; |
| 4538 | current_templates = (const templates *) hash_find (op_hash, |
| 4539 | mnemonic); |
| 4540 | } |
| 4541 | break; |
| 4542 | |
| 4543 | /* Intel Syntax. */ |
| 4544 | case 'd': |
| 4545 | if (intel_syntax) |
| 4546 | { |
| 4547 | if (intel_float_operand (mnemonic) == 1) |
| 4548 | i.suffix = SHORT_MNEM_SUFFIX; |
| 4549 | else |
| 4550 | i.suffix = LONG_MNEM_SUFFIX; |
| 4551 | mnem_p[-1] = '\0'; |
| 4552 | current_templates = (const templates *) hash_find (op_hash, |
| 4553 | mnemonic); |
| 4554 | } |
| 4555 | break; |
| 4556 | } |
| 4557 | if (!current_templates) |
| 4558 | { |
| 4559 | as_bad (_("no such instruction: `%s'"), token_start); |
| 4560 | return NULL; |
| 4561 | } |
| 4562 | } |
| 4563 | |
| 4564 | if (current_templates->start->opcode_modifier.jump |
| 4565 | || current_templates->start->opcode_modifier.jumpbyte) |
| 4566 | { |
| 4567 | /* Check for a branch hint. We allow ",pt" and ",pn" for |
| 4568 | predict taken and predict not taken respectively. |
| 4569 | I'm not sure that branch hints actually do anything on loop |
| 4570 | and jcxz insns (JumpByte) for current Pentium4 chips. They |
| 4571 | may work in the future and it doesn't hurt to accept them |
| 4572 | now. */ |
| 4573 | if (l[0] == ',' && l[1] == 'p') |
| 4574 | { |
| 4575 | if (l[2] == 't') |
| 4576 | { |
| 4577 | if (!add_prefix (DS_PREFIX_OPCODE)) |
| 4578 | return NULL; |
| 4579 | l += 3; |
| 4580 | } |
| 4581 | else if (l[2] == 'n') |
| 4582 | { |
| 4583 | if (!add_prefix (CS_PREFIX_OPCODE)) |
| 4584 | return NULL; |
| 4585 | l += 3; |
| 4586 | } |
| 4587 | } |
| 4588 | } |
| 4589 | /* Any other comma loses. */ |
| 4590 | if (*l == ',') |
| 4591 | { |
| 4592 | as_bad (_("invalid character %s in mnemonic"), |
| 4593 | output_invalid (*l)); |
| 4594 | return NULL; |
| 4595 | } |
| 4596 | |
| 4597 | /* Check if instruction is supported on specified architecture. */ |
| 4598 | supported = 0; |
| 4599 | for (t = current_templates->start; t < current_templates->end; ++t) |
| 4600 | { |
| 4601 | supported |= cpu_flags_match (t); |
| 4602 | if (supported == CPU_FLAGS_PERFECT_MATCH) |
| 4603 | { |
| 4604 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) |
| 4605 | as_warn (_("use .code16 to ensure correct addressing mode")); |
| 4606 | |
| 4607 | return l; |
| 4608 | } |
| 4609 | } |
| 4610 | |
| 4611 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
| 4612 | as_bad (flag_code == CODE_64BIT |
| 4613 | ? _("`%s' is not supported in 64-bit mode") |
| 4614 | : _("`%s' is only supported in 64-bit mode"), |
| 4615 | current_templates->start->name); |
| 4616 | else |
| 4617 | as_bad (_("`%s' is not supported on `%s%s'"), |
| 4618 | current_templates->start->name, |
| 4619 | cpu_arch_name ? cpu_arch_name : default_arch, |
| 4620 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
| 4621 | |
| 4622 | return NULL; |
| 4623 | } |
| 4624 | |
| 4625 | static char * |
| 4626 | parse_operands (char *l, const char *mnemonic) |
| 4627 | { |
| 4628 | char *token_start; |
| 4629 | |
| 4630 | /* 1 if operand is pending after ','. */ |
| 4631 | unsigned int expecting_operand = 0; |
| 4632 | |
| 4633 | /* Non-zero if operand parens not balanced. */ |
| 4634 | unsigned int paren_not_balanced; |
| 4635 | |
| 4636 | while (*l != END_OF_INSN) |
| 4637 | { |
| 4638 | /* Skip optional white space before operand. */ |
| 4639 | if (is_space_char (*l)) |
| 4640 | ++l; |
| 4641 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
| 4642 | { |
| 4643 | as_bad (_("invalid character %s before operand %d"), |
| 4644 | output_invalid (*l), |
| 4645 | i.operands + 1); |
| 4646 | return NULL; |
| 4647 | } |
| 4648 | token_start = l; /* After white space. */ |
| 4649 | paren_not_balanced = 0; |
| 4650 | while (paren_not_balanced || *l != ',') |
| 4651 | { |
| 4652 | if (*l == END_OF_INSN) |
| 4653 | { |
| 4654 | if (paren_not_balanced) |
| 4655 | { |
| 4656 | if (!intel_syntax) |
| 4657 | as_bad (_("unbalanced parenthesis in operand %d."), |
| 4658 | i.operands + 1); |
| 4659 | else |
| 4660 | as_bad (_("unbalanced brackets in operand %d."), |
| 4661 | i.operands + 1); |
| 4662 | return NULL; |
| 4663 | } |
| 4664 | else |
| 4665 | break; /* we are done */ |
| 4666 | } |
| 4667 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
| 4668 | { |
| 4669 | as_bad (_("invalid character %s in operand %d"), |
| 4670 | output_invalid (*l), |
| 4671 | i.operands + 1); |
| 4672 | return NULL; |
| 4673 | } |
| 4674 | if (!intel_syntax) |
| 4675 | { |
| 4676 | if (*l == '(') |
| 4677 | ++paren_not_balanced; |
| 4678 | if (*l == ')') |
| 4679 | --paren_not_balanced; |
| 4680 | } |
| 4681 | else |
| 4682 | { |
| 4683 | if (*l == '[') |
| 4684 | ++paren_not_balanced; |
| 4685 | if (*l == ']') |
| 4686 | --paren_not_balanced; |
| 4687 | } |
| 4688 | l++; |
| 4689 | } |
| 4690 | if (l != token_start) |
| 4691 | { /* Yes, we've read in another operand. */ |
| 4692 | unsigned int operand_ok; |
| 4693 | this_operand = i.operands++; |
| 4694 | if (i.operands > MAX_OPERANDS) |
| 4695 | { |
| 4696 | as_bad (_("spurious operands; (%d operands/instruction max)"), |
| 4697 | MAX_OPERANDS); |
| 4698 | return NULL; |
| 4699 | } |
| 4700 | i.types[this_operand].bitfield.unspecified = 1; |
| 4701 | /* Now parse operand adding info to 'i' as we go along. */ |
| 4702 | END_STRING_AND_SAVE (l); |
| 4703 | |
| 4704 | if (i.mem_operands > 1) |
| 4705 | { |
| 4706 | as_bad (_("too many memory references for `%s'"), |
| 4707 | mnemonic); |
| 4708 | return 0; |
| 4709 | } |
| 4710 | |
| 4711 | if (intel_syntax) |
| 4712 | operand_ok = |
| 4713 | i386_intel_operand (token_start, |
| 4714 | intel_float_operand (mnemonic)); |
| 4715 | else |
| 4716 | operand_ok = i386_att_operand (token_start); |
| 4717 | |
| 4718 | RESTORE_END_STRING (l); |
| 4719 | if (!operand_ok) |
| 4720 | return NULL; |
| 4721 | } |
| 4722 | else |
| 4723 | { |
| 4724 | if (expecting_operand) |
| 4725 | { |
| 4726 | expecting_operand_after_comma: |
| 4727 | as_bad (_("expecting operand after ','; got nothing")); |
| 4728 | return NULL; |
| 4729 | } |
| 4730 | if (*l == ',') |
| 4731 | { |
| 4732 | as_bad (_("expecting operand before ','; got nothing")); |
| 4733 | return NULL; |
| 4734 | } |
| 4735 | } |
| 4736 | |
| 4737 | /* Now *l must be either ',' or END_OF_INSN. */ |
| 4738 | if (*l == ',') |
| 4739 | { |
| 4740 | if (*++l == END_OF_INSN) |
| 4741 | { |
| 4742 | /* Just skip it, if it's \n complain. */ |
| 4743 | goto expecting_operand_after_comma; |
| 4744 | } |
| 4745 | expecting_operand = 1; |
| 4746 | } |
| 4747 | } |
| 4748 | return l; |
| 4749 | } |
| 4750 | |
| 4751 | static void |
| 4752 | swap_2_operands (int xchg1, int xchg2) |
| 4753 | { |
| 4754 | union i386_op temp_op; |
| 4755 | i386_operand_type temp_type; |
| 4756 | unsigned int temp_flags; |
| 4757 | enum bfd_reloc_code_real temp_reloc; |
| 4758 | |
| 4759 | temp_type = i.types[xchg2]; |
| 4760 | i.types[xchg2] = i.types[xchg1]; |
| 4761 | i.types[xchg1] = temp_type; |
| 4762 | |
| 4763 | temp_flags = i.flags[xchg2]; |
| 4764 | i.flags[xchg2] = i.flags[xchg1]; |
| 4765 | i.flags[xchg1] = temp_flags; |
| 4766 | |
| 4767 | temp_op = i.op[xchg2]; |
| 4768 | i.op[xchg2] = i.op[xchg1]; |
| 4769 | i.op[xchg1] = temp_op; |
| 4770 | |
| 4771 | temp_reloc = i.reloc[xchg2]; |
| 4772 | i.reloc[xchg2] = i.reloc[xchg1]; |
| 4773 | i.reloc[xchg1] = temp_reloc; |
| 4774 | |
| 4775 | if (i.mask) |
| 4776 | { |
| 4777 | if (i.mask->operand == xchg1) |
| 4778 | i.mask->operand = xchg2; |
| 4779 | else if (i.mask->operand == xchg2) |
| 4780 | i.mask->operand = xchg1; |
| 4781 | } |
| 4782 | if (i.broadcast) |
| 4783 | { |
| 4784 | if (i.broadcast->operand == xchg1) |
| 4785 | i.broadcast->operand = xchg2; |
| 4786 | else if (i.broadcast->operand == xchg2) |
| 4787 | i.broadcast->operand = xchg1; |
| 4788 | } |
| 4789 | if (i.rounding) |
| 4790 | { |
| 4791 | if (i.rounding->operand == xchg1) |
| 4792 | i.rounding->operand = xchg2; |
| 4793 | else if (i.rounding->operand == xchg2) |
| 4794 | i.rounding->operand = xchg1; |
| 4795 | } |
| 4796 | } |
| 4797 | |
| 4798 | static void |
| 4799 | swap_operands (void) |
| 4800 | { |
| 4801 | switch (i.operands) |
| 4802 | { |
| 4803 | case 5: |
| 4804 | case 4: |
| 4805 | swap_2_operands (1, i.operands - 2); |
| 4806 | /* Fall through. */ |
| 4807 | case 3: |
| 4808 | case 2: |
| 4809 | swap_2_operands (0, i.operands - 1); |
| 4810 | break; |
| 4811 | default: |
| 4812 | abort (); |
| 4813 | } |
| 4814 | |
| 4815 | if (i.mem_operands == 2) |
| 4816 | { |
| 4817 | const seg_entry *temp_seg; |
| 4818 | temp_seg = i.seg[0]; |
| 4819 | i.seg[0] = i.seg[1]; |
| 4820 | i.seg[1] = temp_seg; |
| 4821 | } |
| 4822 | } |
| 4823 | |
| 4824 | /* Try to ensure constant immediates are represented in the smallest |
| 4825 | opcode possible. */ |
| 4826 | static void |
| 4827 | optimize_imm (void) |
| 4828 | { |
| 4829 | char guess_suffix = 0; |
| 4830 | int op; |
| 4831 | |
| 4832 | if (i.suffix) |
| 4833 | guess_suffix = i.suffix; |
| 4834 | else if (i.reg_operands) |
| 4835 | { |
| 4836 | /* Figure out a suffix from the last register operand specified. |
| 4837 | We can't do this properly yet, ie. excluding InOutPortReg, |
| 4838 | but the following works for instructions with immediates. |
| 4839 | In any case, we can't set i.suffix yet. */ |
| 4840 | for (op = i.operands; --op >= 0;) |
| 4841 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
| 4842 | { |
| 4843 | guess_suffix = BYTE_MNEM_SUFFIX; |
| 4844 | break; |
| 4845 | } |
| 4846 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
| 4847 | { |
| 4848 | guess_suffix = WORD_MNEM_SUFFIX; |
| 4849 | break; |
| 4850 | } |
| 4851 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
| 4852 | { |
| 4853 | guess_suffix = LONG_MNEM_SUFFIX; |
| 4854 | break; |
| 4855 | } |
| 4856 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
| 4857 | { |
| 4858 | guess_suffix = QWORD_MNEM_SUFFIX; |
| 4859 | break; |
| 4860 | } |
| 4861 | } |
| 4862 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
| 4863 | guess_suffix = WORD_MNEM_SUFFIX; |
| 4864 | |
| 4865 | for (op = i.operands; --op >= 0;) |
| 4866 | if (operand_type_check (i.types[op], imm)) |
| 4867 | { |
| 4868 | switch (i.op[op].imms->X_op) |
| 4869 | { |
| 4870 | case O_constant: |
| 4871 | /* If a suffix is given, this operand may be shortened. */ |
| 4872 | switch (guess_suffix) |
| 4873 | { |
| 4874 | case LONG_MNEM_SUFFIX: |
| 4875 | i.types[op].bitfield.imm32 = 1; |
| 4876 | i.types[op].bitfield.imm64 = 1; |
| 4877 | break; |
| 4878 | case WORD_MNEM_SUFFIX: |
| 4879 | i.types[op].bitfield.imm16 = 1; |
| 4880 | i.types[op].bitfield.imm32 = 1; |
| 4881 | i.types[op].bitfield.imm32s = 1; |
| 4882 | i.types[op].bitfield.imm64 = 1; |
| 4883 | break; |
| 4884 | case BYTE_MNEM_SUFFIX: |
| 4885 | i.types[op].bitfield.imm8 = 1; |
| 4886 | i.types[op].bitfield.imm8s = 1; |
| 4887 | i.types[op].bitfield.imm16 = 1; |
| 4888 | i.types[op].bitfield.imm32 = 1; |
| 4889 | i.types[op].bitfield.imm32s = 1; |
| 4890 | i.types[op].bitfield.imm64 = 1; |
| 4891 | break; |
| 4892 | } |
| 4893 | |
| 4894 | /* If this operand is at most 16 bits, convert it |
| 4895 | to a signed 16 bit number before trying to see |
| 4896 | whether it will fit in an even smaller size. |
| 4897 | This allows a 16-bit operand such as $0xffe0 to |
| 4898 | be recognised as within Imm8S range. */ |
| 4899 | if ((i.types[op].bitfield.imm16) |
| 4900 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
| 4901 | { |
| 4902 | i.op[op].imms->X_add_number = |
| 4903 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); |
| 4904 | } |
| 4905 | #ifdef BFD64 |
| 4906 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ |
| 4907 | if ((i.types[op].bitfield.imm32) |
| 4908 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
| 4909 | == 0)) |
| 4910 | { |
| 4911 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
| 4912 | ^ ((offsetT) 1 << 31)) |
| 4913 | - ((offsetT) 1 << 31)); |
| 4914 | } |
| 4915 | #endif |
| 4916 | i.types[op] |
| 4917 | = operand_type_or (i.types[op], |
| 4918 | smallest_imm_type (i.op[op].imms->X_add_number)); |
| 4919 | |
| 4920 | /* We must avoid matching of Imm32 templates when 64bit |
| 4921 | only immediate is available. */ |
| 4922 | if (guess_suffix == QWORD_MNEM_SUFFIX) |
| 4923 | i.types[op].bitfield.imm32 = 0; |
| 4924 | break; |
| 4925 | |
| 4926 | case O_absent: |
| 4927 | case O_register: |
| 4928 | abort (); |
| 4929 | |
| 4930 | /* Symbols and expressions. */ |
| 4931 | default: |
| 4932 | /* Convert symbolic operand to proper sizes for matching, but don't |
| 4933 | prevent matching a set of insns that only supports sizes other |
| 4934 | than those matching the insn suffix. */ |
| 4935 | { |
| 4936 | i386_operand_type mask, allowed; |
| 4937 | const insn_template *t; |
| 4938 | |
| 4939 | operand_type_set (&mask, 0); |
| 4940 | operand_type_set (&allowed, 0); |
| 4941 | |
| 4942 | for (t = current_templates->start; |
| 4943 | t < current_templates->end; |
| 4944 | ++t) |
| 4945 | allowed = operand_type_or (allowed, |
| 4946 | t->operand_types[op]); |
| 4947 | switch (guess_suffix) |
| 4948 | { |
| 4949 | case QWORD_MNEM_SUFFIX: |
| 4950 | mask.bitfield.imm64 = 1; |
| 4951 | mask.bitfield.imm32s = 1; |
| 4952 | break; |
| 4953 | case LONG_MNEM_SUFFIX: |
| 4954 | mask.bitfield.imm32 = 1; |
| 4955 | break; |
| 4956 | case WORD_MNEM_SUFFIX: |
| 4957 | mask.bitfield.imm16 = 1; |
| 4958 | break; |
| 4959 | case BYTE_MNEM_SUFFIX: |
| 4960 | mask.bitfield.imm8 = 1; |
| 4961 | break; |
| 4962 | default: |
| 4963 | break; |
| 4964 | } |
| 4965 | allowed = operand_type_and (mask, allowed); |
| 4966 | if (!operand_type_all_zero (&allowed)) |
| 4967 | i.types[op] = operand_type_and (i.types[op], mask); |
| 4968 | } |
| 4969 | break; |
| 4970 | } |
| 4971 | } |
| 4972 | } |
| 4973 | |
| 4974 | /* Try to use the smallest displacement type too. */ |
| 4975 | static void |
| 4976 | optimize_disp (void) |
| 4977 | { |
| 4978 | int op; |
| 4979 | |
| 4980 | for (op = i.operands; --op >= 0;) |
| 4981 | if (operand_type_check (i.types[op], disp)) |
| 4982 | { |
| 4983 | if (i.op[op].disps->X_op == O_constant) |
| 4984 | { |
| 4985 | offsetT op_disp = i.op[op].disps->X_add_number; |
| 4986 | |
| 4987 | if (i.types[op].bitfield.disp16 |
| 4988 | && (op_disp & ~(offsetT) 0xffff) == 0) |
| 4989 | { |
| 4990 | /* If this operand is at most 16 bits, convert |
| 4991 | to a signed 16 bit number and don't use 64bit |
| 4992 | displacement. */ |
| 4993 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
| 4994 | i.types[op].bitfield.disp64 = 0; |
| 4995 | } |
| 4996 | #ifdef BFD64 |
| 4997 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ |
| 4998 | if (i.types[op].bitfield.disp32 |
| 4999 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
| 5000 | { |
| 5001 | /* If this operand is at most 32 bits, convert |
| 5002 | to a signed 32 bit number and don't use 64bit |
| 5003 | displacement. */ |
| 5004 | op_disp &= (((offsetT) 2 << 31) - 1); |
| 5005 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); |
| 5006 | i.types[op].bitfield.disp64 = 0; |
| 5007 | } |
| 5008 | #endif |
| 5009 | if (!op_disp && i.types[op].bitfield.baseindex) |
| 5010 | { |
| 5011 | i.types[op].bitfield.disp8 = 0; |
| 5012 | i.types[op].bitfield.disp16 = 0; |
| 5013 | i.types[op].bitfield.disp32 = 0; |
| 5014 | i.types[op].bitfield.disp32s = 0; |
| 5015 | i.types[op].bitfield.disp64 = 0; |
| 5016 | i.op[op].disps = 0; |
| 5017 | i.disp_operands--; |
| 5018 | } |
| 5019 | else if (flag_code == CODE_64BIT) |
| 5020 | { |
| 5021 | if (fits_in_signed_long (op_disp)) |
| 5022 | { |
| 5023 | i.types[op].bitfield.disp64 = 0; |
| 5024 | i.types[op].bitfield.disp32s = 1; |
| 5025 | } |
| 5026 | if (i.prefix[ADDR_PREFIX] |
| 5027 | && fits_in_unsigned_long (op_disp)) |
| 5028 | i.types[op].bitfield.disp32 = 1; |
| 5029 | } |
| 5030 | if ((i.types[op].bitfield.disp32 |
| 5031 | || i.types[op].bitfield.disp32s |
| 5032 | || i.types[op].bitfield.disp16) |
| 5033 | && fits_in_disp8 (op_disp)) |
| 5034 | i.types[op].bitfield.disp8 = 1; |
| 5035 | } |
| 5036 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
| 5037 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) |
| 5038 | { |
| 5039 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, |
| 5040 | i.op[op].disps, 0, i.reloc[op]); |
| 5041 | i.types[op].bitfield.disp8 = 0; |
| 5042 | i.types[op].bitfield.disp16 = 0; |
| 5043 | i.types[op].bitfield.disp32 = 0; |
| 5044 | i.types[op].bitfield.disp32s = 0; |
| 5045 | i.types[op].bitfield.disp64 = 0; |
| 5046 | } |
| 5047 | else |
| 5048 | /* We only support 64bit displacement on constants. */ |
| 5049 | i.types[op].bitfield.disp64 = 0; |
| 5050 | } |
| 5051 | } |
| 5052 | |
| 5053 | /* Return 1 if there is a match in broadcast bytes between operand |
| 5054 | GIVEN and instruction template T. */ |
| 5055 | |
| 5056 | static INLINE int |
| 5057 | match_broadcast_size (const insn_template *t, unsigned int given) |
| 5058 | { |
| 5059 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST |
| 5060 | && i.types[given].bitfield.byte) |
| 5061 | || (t->opcode_modifier.broadcast == WORD_BROADCAST |
| 5062 | && i.types[given].bitfield.word) |
| 5063 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST |
| 5064 | && i.types[given].bitfield.dword) |
| 5065 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST |
| 5066 | && i.types[given].bitfield.qword)); |
| 5067 | } |
| 5068 | |
| 5069 | /* Check if operands are valid for the instruction. */ |
| 5070 | |
| 5071 | static int |
| 5072 | check_VecOperands (const insn_template *t) |
| 5073 | { |
| 5074 | unsigned int op; |
| 5075 | i386_cpu_flags cpu; |
| 5076 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
| 5077 | |
| 5078 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for |
| 5079 | any one operand are implicity requiring AVX512VL support if the actual |
| 5080 | operand size is YMMword or XMMword. Since this function runs after |
| 5081 | template matching, there's no need to check for YMMword/XMMword in |
| 5082 | the template. */ |
| 5083 | cpu = cpu_flags_and (t->cpu_flags, avx512); |
| 5084 | if (!cpu_flags_all_zero (&cpu) |
| 5085 | && !t->cpu_flags.bitfield.cpuavx512vl |
| 5086 | && !cpu_arch_flags.bitfield.cpuavx512vl) |
| 5087 | { |
| 5088 | for (op = 0; op < t->operands; ++op) |
| 5089 | { |
| 5090 | if (t->operand_types[op].bitfield.zmmword |
| 5091 | && (i.types[op].bitfield.ymmword |
| 5092 | || i.types[op].bitfield.xmmword)) |
| 5093 | { |
| 5094 | i.error = unsupported; |
| 5095 | return 1; |
| 5096 | } |
| 5097 | } |
| 5098 | } |
| 5099 | |
| 5100 | /* Without VSIB byte, we can't have a vector register for index. */ |
| 5101 | if (!t->opcode_modifier.vecsib |
| 5102 | && i.index_reg |
| 5103 | && (i.index_reg->reg_type.bitfield.xmmword |
| 5104 | || i.index_reg->reg_type.bitfield.ymmword |
| 5105 | || i.index_reg->reg_type.bitfield.zmmword)) |
| 5106 | { |
| 5107 | i.error = unsupported_vector_index_register; |
| 5108 | return 1; |
| 5109 | } |
| 5110 | |
| 5111 | /* Check if default mask is allowed. */ |
| 5112 | if (t->opcode_modifier.nodefmask |
| 5113 | && (!i.mask || i.mask->mask->reg_num == 0)) |
| 5114 | { |
| 5115 | i.error = no_default_mask; |
| 5116 | return 1; |
| 5117 | } |
| 5118 | |
| 5119 | /* For VSIB byte, we need a vector register for index, and all vector |
| 5120 | registers must be distinct. */ |
| 5121 | if (t->opcode_modifier.vecsib) |
| 5122 | { |
| 5123 | if (!i.index_reg |
| 5124 | || !((t->opcode_modifier.vecsib == VecSIB128 |
| 5125 | && i.index_reg->reg_type.bitfield.xmmword) |
| 5126 | || (t->opcode_modifier.vecsib == VecSIB256 |
| 5127 | && i.index_reg->reg_type.bitfield.ymmword) |
| 5128 | || (t->opcode_modifier.vecsib == VecSIB512 |
| 5129 | && i.index_reg->reg_type.bitfield.zmmword))) |
| 5130 | { |
| 5131 | i.error = invalid_vsib_address; |
| 5132 | return 1; |
| 5133 | } |
| 5134 | |
| 5135 | gas_assert (i.reg_operands == 2 || i.mask); |
| 5136 | if (i.reg_operands == 2 && !i.mask) |
| 5137 | { |
| 5138 | gas_assert (i.types[0].bitfield.regsimd); |
| 5139 | gas_assert (i.types[0].bitfield.xmmword |
| 5140 | || i.types[0].bitfield.ymmword); |
| 5141 | gas_assert (i.types[2].bitfield.regsimd); |
| 5142 | gas_assert (i.types[2].bitfield.xmmword |
| 5143 | || i.types[2].bitfield.ymmword); |
| 5144 | if (operand_check == check_none) |
| 5145 | return 0; |
| 5146 | if (register_number (i.op[0].regs) |
| 5147 | != register_number (i.index_reg) |
| 5148 | && register_number (i.op[2].regs) |
| 5149 | != register_number (i.index_reg) |
| 5150 | && register_number (i.op[0].regs) |
| 5151 | != register_number (i.op[2].regs)) |
| 5152 | return 0; |
| 5153 | if (operand_check == check_error) |
| 5154 | { |
| 5155 | i.error = invalid_vector_register_set; |
| 5156 | return 1; |
| 5157 | } |
| 5158 | as_warn (_("mask, index, and destination registers should be distinct")); |
| 5159 | } |
| 5160 | else if (i.reg_operands == 1 && i.mask) |
| 5161 | { |
| 5162 | if (i.types[1].bitfield.regsimd |
| 5163 | && (i.types[1].bitfield.xmmword |
| 5164 | || i.types[1].bitfield.ymmword |
| 5165 | || i.types[1].bitfield.zmmword) |
| 5166 | && (register_number (i.op[1].regs) |
| 5167 | == register_number (i.index_reg))) |
| 5168 | { |
| 5169 | if (operand_check == check_error) |
| 5170 | { |
| 5171 | i.error = invalid_vector_register_set; |
| 5172 | return 1; |
| 5173 | } |
| 5174 | if (operand_check != check_none) |
| 5175 | as_warn (_("index and destination registers should be distinct")); |
| 5176 | } |
| 5177 | } |
| 5178 | } |
| 5179 | |
| 5180 | /* Check if broadcast is supported by the instruction and is applied |
| 5181 | to the memory operand. */ |
| 5182 | if (i.broadcast) |
| 5183 | { |
| 5184 | i386_operand_type type, overlap; |
| 5185 | |
| 5186 | /* Check if specified broadcast is supported in this instruction, |
| 5187 | and its broadcast bytes match the memory operand. */ |
| 5188 | op = i.broadcast->operand; |
| 5189 | if (!t->opcode_modifier.broadcast |
| 5190 | || !(i.flags[op] & Operand_Mem) |
| 5191 | || (!i.types[op].bitfield.unspecified |
| 5192 | && !match_broadcast_size (t, op))) |
| 5193 | { |
| 5194 | bad_broadcast: |
| 5195 | i.error = unsupported_broadcast; |
| 5196 | return 1; |
| 5197 | } |
| 5198 | |
| 5199 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
| 5200 | * i.broadcast->type); |
| 5201 | operand_type_set (&type, 0); |
| 5202 | switch (i.broadcast->bytes) |
| 5203 | { |
| 5204 | case 2: |
| 5205 | type.bitfield.word = 1; |
| 5206 | break; |
| 5207 | case 4: |
| 5208 | type.bitfield.dword = 1; |
| 5209 | break; |
| 5210 | case 8: |
| 5211 | type.bitfield.qword = 1; |
| 5212 | break; |
| 5213 | case 16: |
| 5214 | type.bitfield.xmmword = 1; |
| 5215 | break; |
| 5216 | case 32: |
| 5217 | type.bitfield.ymmword = 1; |
| 5218 | break; |
| 5219 | case 64: |
| 5220 | type.bitfield.zmmword = 1; |
| 5221 | break; |
| 5222 | default: |
| 5223 | goto bad_broadcast; |
| 5224 | } |
| 5225 | |
| 5226 | overlap = operand_type_and (type, t->operand_types[op]); |
| 5227 | if (operand_type_all_zero (&overlap)) |
| 5228 | goto bad_broadcast; |
| 5229 | |
| 5230 | if (t->opcode_modifier.checkregsize) |
| 5231 | { |
| 5232 | unsigned int j; |
| 5233 | |
| 5234 | type.bitfield.baseindex = 1; |
| 5235 | for (j = 0; j < i.operands; ++j) |
| 5236 | { |
| 5237 | if (j != op |
| 5238 | && !operand_type_register_match(i.types[j], |
| 5239 | t->operand_types[j], |
| 5240 | type, |
| 5241 | t->operand_types[op])) |
| 5242 | goto bad_broadcast; |
| 5243 | } |
| 5244 | } |
| 5245 | } |
| 5246 | /* If broadcast is supported in this instruction, we need to check if |
| 5247 | operand of one-element size isn't specified without broadcast. */ |
| 5248 | else if (t->opcode_modifier.broadcast && i.mem_operands) |
| 5249 | { |
| 5250 | /* Find memory operand. */ |
| 5251 | for (op = 0; op < i.operands; op++) |
| 5252 | if (operand_type_check (i.types[op], anymem)) |
| 5253 | break; |
| 5254 | gas_assert (op < i.operands); |
| 5255 | /* Check size of the memory operand. */ |
| 5256 | if (match_broadcast_size (t, op)) |
| 5257 | { |
| 5258 | i.error = broadcast_needed; |
| 5259 | return 1; |
| 5260 | } |
| 5261 | } |
| 5262 | else |
| 5263 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ |
| 5264 | |
| 5265 | /* Check if requested masking is supported. */ |
| 5266 | if (i.mask) |
| 5267 | { |
| 5268 | switch (t->opcode_modifier.masking) |
| 5269 | { |
| 5270 | case BOTH_MASKING: |
| 5271 | break; |
| 5272 | case MERGING_MASKING: |
| 5273 | if (i.mask->zeroing) |
| 5274 | { |
| 5275 | case 0: |
| 5276 | i.error = unsupported_masking; |
| 5277 | return 1; |
| 5278 | } |
| 5279 | break; |
| 5280 | case DYNAMIC_MASKING: |
| 5281 | /* Memory destinations allow only merging masking. */ |
| 5282 | if (i.mask->zeroing && i.mem_operands) |
| 5283 | { |
| 5284 | /* Find memory operand. */ |
| 5285 | for (op = 0; op < i.operands; op++) |
| 5286 | if (i.flags[op] & Operand_Mem) |
| 5287 | break; |
| 5288 | gas_assert (op < i.operands); |
| 5289 | if (op == i.operands - 1) |
| 5290 | { |
| 5291 | i.error = unsupported_masking; |
| 5292 | return 1; |
| 5293 | } |
| 5294 | } |
| 5295 | break; |
| 5296 | default: |
| 5297 | abort (); |
| 5298 | } |
| 5299 | } |
| 5300 | |
| 5301 | /* Check if masking is applied to dest operand. */ |
| 5302 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) |
| 5303 | { |
| 5304 | i.error = mask_not_on_destination; |
| 5305 | return 1; |
| 5306 | } |
| 5307 | |
| 5308 | /* Check RC/SAE. */ |
| 5309 | if (i.rounding) |
| 5310 | { |
| 5311 | if ((i.rounding->type != saeonly |
| 5312 | && !t->opcode_modifier.staticrounding) |
| 5313 | || (i.rounding->type == saeonly |
| 5314 | && (t->opcode_modifier.staticrounding |
| 5315 | || !t->opcode_modifier.sae))) |
| 5316 | { |
| 5317 | i.error = unsupported_rc_sae; |
| 5318 | return 1; |
| 5319 | } |
| 5320 | /* If the instruction has several immediate operands and one of |
| 5321 | them is rounding, the rounding operand should be the last |
| 5322 | immediate operand. */ |
| 5323 | if (i.imm_operands > 1 |
| 5324 | && i.rounding->operand != (int) (i.imm_operands - 1)) |
| 5325 | { |
| 5326 | i.error = rc_sae_operand_not_last_imm; |
| 5327 | return 1; |
| 5328 | } |
| 5329 | } |
| 5330 | |
| 5331 | /* Check vector Disp8 operand. */ |
| 5332 | if (t->opcode_modifier.disp8memshift |
| 5333 | && i.disp_encoding != disp_encoding_32bit) |
| 5334 | { |
| 5335 | if (i.broadcast) |
| 5336 | i.memshift = t->opcode_modifier.broadcast - 1; |
| 5337 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
| 5338 | i.memshift = t->opcode_modifier.disp8memshift; |
| 5339 | else |
| 5340 | { |
| 5341 | const i386_operand_type *type = NULL; |
| 5342 | |
| 5343 | i.memshift = 0; |
| 5344 | for (op = 0; op < i.operands; op++) |
| 5345 | if (operand_type_check (i.types[op], anymem)) |
| 5346 | { |
| 5347 | if (t->opcode_modifier.evex == EVEXLIG) |
| 5348 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); |
| 5349 | else if (t->operand_types[op].bitfield.xmmword |
| 5350 | + t->operand_types[op].bitfield.ymmword |
| 5351 | + t->operand_types[op].bitfield.zmmword <= 1) |
| 5352 | type = &t->operand_types[op]; |
| 5353 | else if (!i.types[op].bitfield.unspecified) |
| 5354 | type = &i.types[op]; |
| 5355 | } |
| 5356 | else if (i.types[op].bitfield.regsimd |
| 5357 | && t->opcode_modifier.evex != EVEXLIG) |
| 5358 | { |
| 5359 | if (i.types[op].bitfield.zmmword) |
| 5360 | i.memshift = 6; |
| 5361 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) |
| 5362 | i.memshift = 5; |
| 5363 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) |
| 5364 | i.memshift = 4; |
| 5365 | } |
| 5366 | |
| 5367 | if (type) |
| 5368 | { |
| 5369 | if (type->bitfield.zmmword) |
| 5370 | i.memshift = 6; |
| 5371 | else if (type->bitfield.ymmword) |
| 5372 | i.memshift = 5; |
| 5373 | else if (type->bitfield.xmmword) |
| 5374 | i.memshift = 4; |
| 5375 | } |
| 5376 | |
| 5377 | /* For the check in fits_in_disp8(). */ |
| 5378 | if (i.memshift == 0) |
| 5379 | i.memshift = -1; |
| 5380 | } |
| 5381 | |
| 5382 | for (op = 0; op < i.operands; op++) |
| 5383 | if (operand_type_check (i.types[op], disp) |
| 5384 | && i.op[op].disps->X_op == O_constant) |
| 5385 | { |
| 5386 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
| 5387 | { |
| 5388 | i.types[op].bitfield.disp8 = 1; |
| 5389 | return 0; |
| 5390 | } |
| 5391 | i.types[op].bitfield.disp8 = 0; |
| 5392 | } |
| 5393 | } |
| 5394 | |
| 5395 | i.memshift = 0; |
| 5396 | |
| 5397 | return 0; |
| 5398 | } |
| 5399 | |
| 5400 | /* Check if operands are valid for the instruction. Update VEX |
| 5401 | operand types. */ |
| 5402 | |
| 5403 | static int |
| 5404 | VEX_check_operands (const insn_template *t) |
| 5405 | { |
| 5406 | if (i.vec_encoding == vex_encoding_evex) |
| 5407 | { |
| 5408 | /* This instruction must be encoded with EVEX prefix. */ |
| 5409 | if (!is_evex_encoding (t)) |
| 5410 | { |
| 5411 | i.error = unsupported; |
| 5412 | return 1; |
| 5413 | } |
| 5414 | return 0; |
| 5415 | } |
| 5416 | |
| 5417 | if (!t->opcode_modifier.vex) |
| 5418 | { |
| 5419 | /* This instruction template doesn't have VEX prefix. */ |
| 5420 | if (i.vec_encoding != vex_encoding_default) |
| 5421 | { |
| 5422 | i.error = unsupported; |
| 5423 | return 1; |
| 5424 | } |
| 5425 | return 0; |
| 5426 | } |
| 5427 | |
| 5428 | /* Only check VEX_Imm4, which must be the first operand. */ |
| 5429 | if (t->operand_types[0].bitfield.vec_imm4) |
| 5430 | { |
| 5431 | if (i.op[0].imms->X_op != O_constant |
| 5432 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) |
| 5433 | { |
| 5434 | i.error = bad_imm4; |
| 5435 | return 1; |
| 5436 | } |
| 5437 | |
| 5438 | /* Turn off Imm8 so that update_imm won't complain. */ |
| 5439 | i.types[0] = vec_imm4; |
| 5440 | } |
| 5441 | |
| 5442 | return 0; |
| 5443 | } |
| 5444 | |
| 5445 | static const insn_template * |
| 5446 | match_template (char mnem_suffix) |
| 5447 | { |
| 5448 | /* Points to template once we've found it. */ |
| 5449 | const insn_template *t; |
| 5450 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
| 5451 | i386_operand_type overlap4; |
| 5452 | unsigned int found_reverse_match; |
| 5453 | i386_opcode_modifier suffix_check, mnemsuf_check; |
| 5454 | i386_operand_type operand_types [MAX_OPERANDS]; |
| 5455 | int addr_prefix_disp; |
| 5456 | unsigned int j; |
| 5457 | unsigned int found_cpu_match, size_match; |
| 5458 | unsigned int check_register; |
| 5459 | enum i386_error specific_error = 0; |
| 5460 | |
| 5461 | #if MAX_OPERANDS != 5 |
| 5462 | # error "MAX_OPERANDS must be 5." |
| 5463 | #endif |
| 5464 | |
| 5465 | found_reverse_match = 0; |
| 5466 | addr_prefix_disp = -1; |
| 5467 | |
| 5468 | memset (&suffix_check, 0, sizeof (suffix_check)); |
| 5469 | if (intel_syntax && i.broadcast) |
| 5470 | /* nothing */; |
| 5471 | else if (i.suffix == BYTE_MNEM_SUFFIX) |
| 5472 | suffix_check.no_bsuf = 1; |
| 5473 | else if (i.suffix == WORD_MNEM_SUFFIX) |
| 5474 | suffix_check.no_wsuf = 1; |
| 5475 | else if (i.suffix == SHORT_MNEM_SUFFIX) |
| 5476 | suffix_check.no_ssuf = 1; |
| 5477 | else if (i.suffix == LONG_MNEM_SUFFIX) |
| 5478 | suffix_check.no_lsuf = 1; |
| 5479 | else if (i.suffix == QWORD_MNEM_SUFFIX) |
| 5480 | suffix_check.no_qsuf = 1; |
| 5481 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) |
| 5482 | suffix_check.no_ldsuf = 1; |
| 5483 | |
| 5484 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
| 5485 | if (intel_syntax) |
| 5486 | { |
| 5487 | switch (mnem_suffix) |
| 5488 | { |
| 5489 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; |
| 5490 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; |
| 5491 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; |
| 5492 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; |
| 5493 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; |
| 5494 | } |
| 5495 | } |
| 5496 | |
| 5497 | /* Must have right number of operands. */ |
| 5498 | i.error = number_of_operands_mismatch; |
| 5499 | |
| 5500 | for (t = current_templates->start; t < current_templates->end; t++) |
| 5501 | { |
| 5502 | addr_prefix_disp = -1; |
| 5503 | |
| 5504 | if (i.operands != t->operands) |
| 5505 | continue; |
| 5506 | |
| 5507 | /* Check processor support. */ |
| 5508 | i.error = unsupported; |
| 5509 | found_cpu_match = (cpu_flags_match (t) |
| 5510 | == CPU_FLAGS_PERFECT_MATCH); |
| 5511 | if (!found_cpu_match) |
| 5512 | continue; |
| 5513 | |
| 5514 | /* Check AT&T mnemonic. */ |
| 5515 | i.error = unsupported_with_intel_mnemonic; |
| 5516 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
| 5517 | continue; |
| 5518 | |
| 5519 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
| 5520 | i.error = unsupported_syntax; |
| 5521 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
| 5522 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
| 5523 | || (intel64 && t->opcode_modifier.amd64) |
| 5524 | || (!intel64 && t->opcode_modifier.intel64)) |
| 5525 | continue; |
| 5526 | |
| 5527 | /* Check the suffix, except for some instructions in intel mode. */ |
| 5528 | i.error = invalid_instruction_suffix; |
| 5529 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
| 5530 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
| 5531 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) |
| 5532 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) |
| 5533 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) |
| 5534 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) |
| 5535 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) |
| 5536 | continue; |
| 5537 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
| 5538 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) |
| 5539 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) |
| 5540 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) |
| 5541 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) |
| 5542 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) |
| 5543 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) |
| 5544 | continue; |
| 5545 | |
| 5546 | size_match = operand_size_match (t); |
| 5547 | if (!size_match) |
| 5548 | continue; |
| 5549 | |
| 5550 | for (j = 0; j < MAX_OPERANDS; j++) |
| 5551 | operand_types[j] = t->operand_types[j]; |
| 5552 | |
| 5553 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
| 5554 | if (i.suffix == QWORD_MNEM_SUFFIX |
| 5555 | && flag_code != CODE_64BIT |
| 5556 | && (intel_syntax |
| 5557 | ? (!t->opcode_modifier.ignoresize |
| 5558 | && !t->opcode_modifier.broadcast |
| 5559 | && !intel_float_operand (t->name)) |
| 5560 | : intel_float_operand (t->name) != 2) |
| 5561 | && ((!operand_types[0].bitfield.regmmx |
| 5562 | && !operand_types[0].bitfield.regsimd) |
| 5563 | || (!operand_types[t->operands > 1].bitfield.regmmx |
| 5564 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
| 5565 | && (t->base_opcode != 0x0fc7 |
| 5566 | || t->extension_opcode != 1 /* cmpxchg8b */)) |
| 5567 | continue; |
| 5568 | |
| 5569 | /* In general, don't allow 32-bit operands on pre-386. */ |
| 5570 | else if (i.suffix == LONG_MNEM_SUFFIX |
| 5571 | && !cpu_arch_flags.bitfield.cpui386 |
| 5572 | && (intel_syntax |
| 5573 | ? (!t->opcode_modifier.ignoresize |
| 5574 | && !intel_float_operand (t->name)) |
| 5575 | : intel_float_operand (t->name) != 2) |
| 5576 | && ((!operand_types[0].bitfield.regmmx |
| 5577 | && !operand_types[0].bitfield.regsimd) |
| 5578 | || (!operand_types[t->operands > 1].bitfield.regmmx |
| 5579 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
| 5580 | continue; |
| 5581 | |
| 5582 | /* Do not verify operands when there are none. */ |
| 5583 | else |
| 5584 | { |
| 5585 | if (!t->operands) |
| 5586 | /* We've found a match; break out of loop. */ |
| 5587 | break; |
| 5588 | } |
| 5589 | |
| 5590 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
| 5591 | into Disp32/Disp16/Disp32 operand. */ |
| 5592 | if (i.prefix[ADDR_PREFIX] != 0) |
| 5593 | { |
| 5594 | /* There should be only one Disp operand. */ |
| 5595 | switch (flag_code) |
| 5596 | { |
| 5597 | case CODE_16BIT: |
| 5598 | for (j = 0; j < MAX_OPERANDS; j++) |
| 5599 | { |
| 5600 | if (operand_types[j].bitfield.disp16) |
| 5601 | { |
| 5602 | addr_prefix_disp = j; |
| 5603 | operand_types[j].bitfield.disp32 = 1; |
| 5604 | operand_types[j].bitfield.disp16 = 0; |
| 5605 | break; |
| 5606 | } |
| 5607 | } |
| 5608 | break; |
| 5609 | case CODE_32BIT: |
| 5610 | for (j = 0; j < MAX_OPERANDS; j++) |
| 5611 | { |
| 5612 | if (operand_types[j].bitfield.disp32) |
| 5613 | { |
| 5614 | addr_prefix_disp = j; |
| 5615 | operand_types[j].bitfield.disp32 = 0; |
| 5616 | operand_types[j].bitfield.disp16 = 1; |
| 5617 | break; |
| 5618 | } |
| 5619 | } |
| 5620 | break; |
| 5621 | case CODE_64BIT: |
| 5622 | for (j = 0; j < MAX_OPERANDS; j++) |
| 5623 | { |
| 5624 | if (operand_types[j].bitfield.disp64) |
| 5625 | { |
| 5626 | addr_prefix_disp = j; |
| 5627 | operand_types[j].bitfield.disp64 = 0; |
| 5628 | operand_types[j].bitfield.disp32 = 1; |
| 5629 | break; |
| 5630 | } |
| 5631 | } |
| 5632 | break; |
| 5633 | } |
| 5634 | } |
| 5635 | |
| 5636 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
| 5637 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) |
| 5638 | continue; |
| 5639 | |
| 5640 | /* We check register size if needed. */ |
| 5641 | if (t->opcode_modifier.checkregsize) |
| 5642 | { |
| 5643 | check_register = (1 << t->operands) - 1; |
| 5644 | if (i.broadcast) |
| 5645 | check_register &= ~(1 << i.broadcast->operand); |
| 5646 | } |
| 5647 | else |
| 5648 | check_register = 0; |
| 5649 | |
| 5650 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
| 5651 | switch (t->operands) |
| 5652 | { |
| 5653 | case 1: |
| 5654 | if (!operand_type_match (overlap0, i.types[0])) |
| 5655 | continue; |
| 5656 | break; |
| 5657 | case 2: |
| 5658 | /* xchg %eax, %eax is a special case. It is an alias for nop |
| 5659 | only in 32bit mode and we can use opcode 0x90. In 64bit |
| 5660 | mode, we can't use 0x90 for xchg %eax, %eax since it should |
| 5661 | zero-extend %eax to %rax. */ |
| 5662 | if (flag_code == CODE_64BIT |
| 5663 | && t->base_opcode == 0x90 |
| 5664 | && operand_type_equal (&i.types [0], &acc32) |
| 5665 | && operand_type_equal (&i.types [1], &acc32)) |
| 5666 | continue; |
| 5667 | /* xrelease mov %eax, <disp> is another special case. It must not |
| 5668 | match the accumulator-only encoding of mov. */ |
| 5669 | if (flag_code != CODE_64BIT |
| 5670 | && i.hle_prefix |
| 5671 | && t->base_opcode == 0xa0 |
| 5672 | && i.types[0].bitfield.acc |
| 5673 | && operand_type_check (i.types[1], anymem)) |
| 5674 | continue; |
| 5675 | if (!(size_match & MATCH_STRAIGHT)) |
| 5676 | goto check_reverse; |
| 5677 | /* If we want store form, we reverse direction of operands. */ |
| 5678 | if (i.dir_encoding == dir_encoding_store |
| 5679 | && t->opcode_modifier.d) |
| 5680 | goto check_reverse; |
| 5681 | /* Fall through. */ |
| 5682 | |
| 5683 | case 3: |
| 5684 | /* If we want store form, we skip the current load. */ |
| 5685 | if (i.dir_encoding == dir_encoding_store |
| 5686 | && i.mem_operands == 0 |
| 5687 | && t->opcode_modifier.load) |
| 5688 | continue; |
| 5689 | /* Fall through. */ |
| 5690 | case 4: |
| 5691 | case 5: |
| 5692 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
| 5693 | if (!operand_type_match (overlap0, i.types[0]) |
| 5694 | || !operand_type_match (overlap1, i.types[1]) |
| 5695 | || ((check_register & 3) == 3 |
| 5696 | && !operand_type_register_match (i.types[0], |
| 5697 | operand_types[0], |
| 5698 | i.types[1], |
| 5699 | operand_types[1]))) |
| 5700 | { |
| 5701 | /* Check if other direction is valid ... */ |
| 5702 | if (!t->opcode_modifier.d) |
| 5703 | continue; |
| 5704 | |
| 5705 | check_reverse: |
| 5706 | if (!(size_match & MATCH_REVERSE)) |
| 5707 | continue; |
| 5708 | /* Try reversing direction of operands. */ |
| 5709 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
| 5710 | overlap1 = operand_type_and (i.types[1], operand_types[0]); |
| 5711 | if (!operand_type_match (overlap0, i.types[0]) |
| 5712 | || !operand_type_match (overlap1, i.types[1]) |
| 5713 | || (check_register |
| 5714 | && !operand_type_register_match (i.types[0], |
| 5715 | operand_types[1], |
| 5716 | i.types[1], |
| 5717 | operand_types[0]))) |
| 5718 | { |
| 5719 | /* Does not match either direction. */ |
| 5720 | continue; |
| 5721 | } |
| 5722 | /* found_reverse_match holds which of D or FloatR |
| 5723 | we've found. */ |
| 5724 | if (!t->opcode_modifier.d) |
| 5725 | found_reverse_match = 0; |
| 5726 | else if (operand_types[0].bitfield.tbyte) |
| 5727 | found_reverse_match = Opcode_FloatD; |
| 5728 | else |
| 5729 | found_reverse_match = Opcode_D; |
| 5730 | if (t->opcode_modifier.floatr) |
| 5731 | found_reverse_match |= Opcode_FloatR; |
| 5732 | } |
| 5733 | else |
| 5734 | { |
| 5735 | /* Found a forward 2 operand match here. */ |
| 5736 | switch (t->operands) |
| 5737 | { |
| 5738 | case 5: |
| 5739 | overlap4 = operand_type_and (i.types[4], |
| 5740 | operand_types[4]); |
| 5741 | /* Fall through. */ |
| 5742 | case 4: |
| 5743 | overlap3 = operand_type_and (i.types[3], |
| 5744 | operand_types[3]); |
| 5745 | /* Fall through. */ |
| 5746 | case 3: |
| 5747 | overlap2 = operand_type_and (i.types[2], |
| 5748 | operand_types[2]); |
| 5749 | break; |
| 5750 | } |
| 5751 | |
| 5752 | switch (t->operands) |
| 5753 | { |
| 5754 | case 5: |
| 5755 | if (!operand_type_match (overlap4, i.types[4]) |
| 5756 | || !operand_type_register_match (i.types[3], |
| 5757 | operand_types[3], |
| 5758 | i.types[4], |
| 5759 | operand_types[4])) |
| 5760 | continue; |
| 5761 | /* Fall through. */ |
| 5762 | case 4: |
| 5763 | if (!operand_type_match (overlap3, i.types[3]) |
| 5764 | || ((check_register & 0xa) == 0xa |
| 5765 | && !operand_type_register_match (i.types[1], |
| 5766 | operand_types[1], |
| 5767 | i.types[3], |
| 5768 | operand_types[3])) |
| 5769 | || ((check_register & 0xc) == 0xc |
| 5770 | && !operand_type_register_match (i.types[2], |
| 5771 | operand_types[2], |
| 5772 | i.types[3], |
| 5773 | operand_types[3]))) |
| 5774 | continue; |
| 5775 | /* Fall through. */ |
| 5776 | case 3: |
| 5777 | /* Here we make use of the fact that there are no |
| 5778 | reverse match 3 operand instructions. */ |
| 5779 | if (!operand_type_match (overlap2, i.types[2]) |
| 5780 | || ((check_register & 5) == 5 |
| 5781 | && !operand_type_register_match (i.types[0], |
| 5782 | operand_types[0], |
| 5783 | i.types[2], |
| 5784 | operand_types[2])) |
| 5785 | || ((check_register & 6) == 6 |
| 5786 | && !operand_type_register_match (i.types[1], |
| 5787 | operand_types[1], |
| 5788 | i.types[2], |
| 5789 | operand_types[2]))) |
| 5790 | continue; |
| 5791 | break; |
| 5792 | } |
| 5793 | } |
| 5794 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
| 5795 | slip through to break. */ |
| 5796 | } |
| 5797 | if (!found_cpu_match) |
| 5798 | { |
| 5799 | found_reverse_match = 0; |
| 5800 | continue; |
| 5801 | } |
| 5802 | |
| 5803 | /* Check if vector and VEX operands are valid. */ |
| 5804 | if (check_VecOperands (t) || VEX_check_operands (t)) |
| 5805 | { |
| 5806 | specific_error = i.error; |
| 5807 | continue; |
| 5808 | } |
| 5809 | |
| 5810 | /* We've found a match; break out of loop. */ |
| 5811 | break; |
| 5812 | } |
| 5813 | |
| 5814 | if (t == current_templates->end) |
| 5815 | { |
| 5816 | /* We found no match. */ |
| 5817 | const char *err_msg; |
| 5818 | switch (specific_error ? specific_error : i.error) |
| 5819 | { |
| 5820 | default: |
| 5821 | abort (); |
| 5822 | case operand_size_mismatch: |
| 5823 | err_msg = _("operand size mismatch"); |
| 5824 | break; |
| 5825 | case operand_type_mismatch: |
| 5826 | err_msg = _("operand type mismatch"); |
| 5827 | break; |
| 5828 | case register_type_mismatch: |
| 5829 | err_msg = _("register type mismatch"); |
| 5830 | break; |
| 5831 | case number_of_operands_mismatch: |
| 5832 | err_msg = _("number of operands mismatch"); |
| 5833 | break; |
| 5834 | case invalid_instruction_suffix: |
| 5835 | err_msg = _("invalid instruction suffix"); |
| 5836 | break; |
| 5837 | case bad_imm4: |
| 5838 | err_msg = _("constant doesn't fit in 4 bits"); |
| 5839 | break; |
| 5840 | case unsupported_with_intel_mnemonic: |
| 5841 | err_msg = _("unsupported with Intel mnemonic"); |
| 5842 | break; |
| 5843 | case unsupported_syntax: |
| 5844 | err_msg = _("unsupported syntax"); |
| 5845 | break; |
| 5846 | case unsupported: |
| 5847 | as_bad (_("unsupported instruction `%s'"), |
| 5848 | current_templates->start->name); |
| 5849 | return NULL; |
| 5850 | case invalid_vsib_address: |
| 5851 | err_msg = _("invalid VSIB address"); |
| 5852 | break; |
| 5853 | case invalid_vector_register_set: |
| 5854 | err_msg = _("mask, index, and destination registers must be distinct"); |
| 5855 | break; |
| 5856 | case unsupported_vector_index_register: |
| 5857 | err_msg = _("unsupported vector index register"); |
| 5858 | break; |
| 5859 | case unsupported_broadcast: |
| 5860 | err_msg = _("unsupported broadcast"); |
| 5861 | break; |
| 5862 | case broadcast_needed: |
| 5863 | err_msg = _("broadcast is needed for operand of such type"); |
| 5864 | break; |
| 5865 | case unsupported_masking: |
| 5866 | err_msg = _("unsupported masking"); |
| 5867 | break; |
| 5868 | case mask_not_on_destination: |
| 5869 | err_msg = _("mask not on destination operand"); |
| 5870 | break; |
| 5871 | case no_default_mask: |
| 5872 | err_msg = _("default mask isn't allowed"); |
| 5873 | break; |
| 5874 | case unsupported_rc_sae: |
| 5875 | err_msg = _("unsupported static rounding/sae"); |
| 5876 | break; |
| 5877 | case rc_sae_operand_not_last_imm: |
| 5878 | if (intel_syntax) |
| 5879 | err_msg = _("RC/SAE operand must precede immediate operands"); |
| 5880 | else |
| 5881 | err_msg = _("RC/SAE operand must follow immediate operands"); |
| 5882 | break; |
| 5883 | case invalid_register_operand: |
| 5884 | err_msg = _("invalid register operand"); |
| 5885 | break; |
| 5886 | } |
| 5887 | as_bad (_("%s for `%s'"), err_msg, |
| 5888 | current_templates->start->name); |
| 5889 | return NULL; |
| 5890 | } |
| 5891 | |
| 5892 | if (!quiet_warnings) |
| 5893 | { |
| 5894 | if (!intel_syntax |
| 5895 | && (i.types[0].bitfield.jumpabsolute |
| 5896 | != operand_types[0].bitfield.jumpabsolute)) |
| 5897 | { |
| 5898 | as_warn (_("indirect %s without `*'"), t->name); |
| 5899 | } |
| 5900 | |
| 5901 | if (t->opcode_modifier.isprefix |
| 5902 | && t->opcode_modifier.ignoresize) |
| 5903 | { |
| 5904 | /* Warn them that a data or address size prefix doesn't |
| 5905 | affect assembly of the next line of code. */ |
| 5906 | as_warn (_("stand-alone `%s' prefix"), t->name); |
| 5907 | } |
| 5908 | } |
| 5909 | |
| 5910 | /* Copy the template we found. */ |
| 5911 | i.tm = *t; |
| 5912 | |
| 5913 | if (addr_prefix_disp != -1) |
| 5914 | i.tm.operand_types[addr_prefix_disp] |
| 5915 | = operand_types[addr_prefix_disp]; |
| 5916 | |
| 5917 | if (found_reverse_match) |
| 5918 | { |
| 5919 | /* If we found a reverse match we must alter the opcode |
| 5920 | direction bit. found_reverse_match holds bits to change |
| 5921 | (different for int & float insns). */ |
| 5922 | |
| 5923 | i.tm.base_opcode ^= found_reverse_match; |
| 5924 | |
| 5925 | i.tm.operand_types[0] = operand_types[1]; |
| 5926 | i.tm.operand_types[1] = operand_types[0]; |
| 5927 | } |
| 5928 | |
| 5929 | return t; |
| 5930 | } |
| 5931 | |
| 5932 | static int |
| 5933 | check_string (void) |
| 5934 | { |
| 5935 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
| 5936 | if (i.tm.operand_types[mem_op].bitfield.esseg) |
| 5937 | { |
| 5938 | if (i.seg[0] != NULL && i.seg[0] != &es) |
| 5939 | { |
| 5940 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
| 5941 | i.tm.name, |
| 5942 | mem_op + 1, |
| 5943 | register_prefix); |
| 5944 | return 0; |
| 5945 | } |
| 5946 | /* There's only ever one segment override allowed per instruction. |
| 5947 | This instruction possibly has a legal segment override on the |
| 5948 | second operand, so copy the segment to where non-string |
| 5949 | instructions store it, allowing common code. */ |
| 5950 | i.seg[0] = i.seg[1]; |
| 5951 | } |
| 5952 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
| 5953 | { |
| 5954 | if (i.seg[1] != NULL && i.seg[1] != &es) |
| 5955 | { |
| 5956 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
| 5957 | i.tm.name, |
| 5958 | mem_op + 2, |
| 5959 | register_prefix); |
| 5960 | return 0; |
| 5961 | } |
| 5962 | } |
| 5963 | return 1; |
| 5964 | } |
| 5965 | |
| 5966 | static int |
| 5967 | process_suffix (void) |
| 5968 | { |
| 5969 | /* If matched instruction specifies an explicit instruction mnemonic |
| 5970 | suffix, use it. */ |
| 5971 | if (i.tm.opcode_modifier.size16) |
| 5972 | i.suffix = WORD_MNEM_SUFFIX; |
| 5973 | else if (i.tm.opcode_modifier.size32) |
| 5974 | i.suffix = LONG_MNEM_SUFFIX; |
| 5975 | else if (i.tm.opcode_modifier.size64) |
| 5976 | i.suffix = QWORD_MNEM_SUFFIX; |
| 5977 | else if (i.reg_operands) |
| 5978 | { |
| 5979 | /* If there's no instruction mnemonic suffix we try to invent one |
| 5980 | based on register operands. */ |
| 5981 | if (!i.suffix) |
| 5982 | { |
| 5983 | /* We take i.suffix from the last register operand specified, |
| 5984 | Destination register type is more significant than source |
| 5985 | register type. crc32 in SSE4.2 prefers source register |
| 5986 | type. */ |
| 5987 | if (i.tm.base_opcode == 0xf20f38f1) |
| 5988 | { |
| 5989 | if (i.types[0].bitfield.reg && i.types[0].bitfield.word) |
| 5990 | i.suffix = WORD_MNEM_SUFFIX; |
| 5991 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword) |
| 5992 | i.suffix = LONG_MNEM_SUFFIX; |
| 5993 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword) |
| 5994 | i.suffix = QWORD_MNEM_SUFFIX; |
| 5995 | } |
| 5996 | else if (i.tm.base_opcode == 0xf20f38f0) |
| 5997 | { |
| 5998 | if (i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
| 5999 | i.suffix = BYTE_MNEM_SUFFIX; |
| 6000 | } |
| 6001 | |
| 6002 | if (!i.suffix) |
| 6003 | { |
| 6004 | int op; |
| 6005 | |
| 6006 | if (i.tm.base_opcode == 0xf20f38f1 |
| 6007 | || i.tm.base_opcode == 0xf20f38f0) |
| 6008 | { |
| 6009 | /* We have to know the operand size for crc32. */ |
| 6010 | as_bad (_("ambiguous memory operand size for `%s`"), |
| 6011 | i.tm.name); |
| 6012 | return 0; |
| 6013 | } |
| 6014 | |
| 6015 | for (op = i.operands; --op >= 0;) |
| 6016 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
| 6017 | && !i.tm.operand_types[op].bitfield.shiftcount) |
| 6018 | { |
| 6019 | if (!i.types[op].bitfield.reg) |
| 6020 | continue; |
| 6021 | if (i.types[op].bitfield.byte) |
| 6022 | i.suffix = BYTE_MNEM_SUFFIX; |
| 6023 | else if (i.types[op].bitfield.word) |
| 6024 | i.suffix = WORD_MNEM_SUFFIX; |
| 6025 | else if (i.types[op].bitfield.dword) |
| 6026 | i.suffix = LONG_MNEM_SUFFIX; |
| 6027 | else if (i.types[op].bitfield.qword) |
| 6028 | i.suffix = QWORD_MNEM_SUFFIX; |
| 6029 | else |
| 6030 | continue; |
| 6031 | break; |
| 6032 | } |
| 6033 | } |
| 6034 | } |
| 6035 | else if (i.suffix == BYTE_MNEM_SUFFIX) |
| 6036 | { |
| 6037 | if (intel_syntax |
| 6038 | && i.tm.opcode_modifier.ignoresize |
| 6039 | && i.tm.opcode_modifier.no_bsuf) |
| 6040 | i.suffix = 0; |
| 6041 | else if (!check_byte_reg ()) |
| 6042 | return 0; |
| 6043 | } |
| 6044 | else if (i.suffix == LONG_MNEM_SUFFIX) |
| 6045 | { |
| 6046 | if (intel_syntax |
| 6047 | && i.tm.opcode_modifier.ignoresize |
| 6048 | && i.tm.opcode_modifier.no_lsuf |
| 6049 | && !i.tm.opcode_modifier.todword |
| 6050 | && !i.tm.opcode_modifier.toqword) |
| 6051 | i.suffix = 0; |
| 6052 | else if (!check_long_reg ()) |
| 6053 | return 0; |
| 6054 | } |
| 6055 | else if (i.suffix == QWORD_MNEM_SUFFIX) |
| 6056 | { |
| 6057 | if (intel_syntax |
| 6058 | && i.tm.opcode_modifier.ignoresize |
| 6059 | && i.tm.opcode_modifier.no_qsuf |
| 6060 | && !i.tm.opcode_modifier.todword |
| 6061 | && !i.tm.opcode_modifier.toqword) |
| 6062 | i.suffix = 0; |
| 6063 | else if (!check_qword_reg ()) |
| 6064 | return 0; |
| 6065 | } |
| 6066 | else if (i.suffix == WORD_MNEM_SUFFIX) |
| 6067 | { |
| 6068 | if (intel_syntax |
| 6069 | && i.tm.opcode_modifier.ignoresize |
| 6070 | && i.tm.opcode_modifier.no_wsuf) |
| 6071 | i.suffix = 0; |
| 6072 | else if (!check_word_reg ()) |
| 6073 | return 0; |
| 6074 | } |
| 6075 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
| 6076 | /* Do nothing if the instruction is going to ignore the prefix. */ |
| 6077 | ; |
| 6078 | else |
| 6079 | abort (); |
| 6080 | } |
| 6081 | else if (i.tm.opcode_modifier.defaultsize |
| 6082 | && !i.suffix |
| 6083 | /* exclude fldenv/frstor/fsave/fstenv */ |
| 6084 | && i.tm.opcode_modifier.no_ssuf) |
| 6085 | { |
| 6086 | i.suffix = stackop_size; |
| 6087 | } |
| 6088 | else if (intel_syntax |
| 6089 | && !i.suffix |
| 6090 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
| 6091 | || i.tm.opcode_modifier.jumpbyte |
| 6092 | || i.tm.opcode_modifier.jumpintersegment |
| 6093 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
| 6094 | && i.tm.extension_opcode <= 3))) |
| 6095 | { |
| 6096 | switch (flag_code) |
| 6097 | { |
| 6098 | case CODE_64BIT: |
| 6099 | if (!i.tm.opcode_modifier.no_qsuf) |
| 6100 | { |
| 6101 | i.suffix = QWORD_MNEM_SUFFIX; |
| 6102 | break; |
| 6103 | } |
| 6104 | /* Fall through. */ |
| 6105 | case CODE_32BIT: |
| 6106 | if (!i.tm.opcode_modifier.no_lsuf) |
| 6107 | i.suffix = LONG_MNEM_SUFFIX; |
| 6108 | break; |
| 6109 | case CODE_16BIT: |
| 6110 | if (!i.tm.opcode_modifier.no_wsuf) |
| 6111 | i.suffix = WORD_MNEM_SUFFIX; |
| 6112 | break; |
| 6113 | } |
| 6114 | } |
| 6115 | |
| 6116 | if (!i.suffix) |
| 6117 | { |
| 6118 | if (!intel_syntax) |
| 6119 | { |
| 6120 | if (i.tm.opcode_modifier.w) |
| 6121 | { |
| 6122 | as_bad (_("no instruction mnemonic suffix given and " |
| 6123 | "no register operands; can't size instruction")); |
| 6124 | return 0; |
| 6125 | } |
| 6126 | } |
| 6127 | else |
| 6128 | { |
| 6129 | unsigned int suffixes; |
| 6130 | |
| 6131 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
| 6132 | if (!i.tm.opcode_modifier.no_wsuf) |
| 6133 | suffixes |= 1 << 1; |
| 6134 | if (!i.tm.opcode_modifier.no_lsuf) |
| 6135 | suffixes |= 1 << 2; |
| 6136 | if (!i.tm.opcode_modifier.no_ldsuf) |
| 6137 | suffixes |= 1 << 3; |
| 6138 | if (!i.tm.opcode_modifier.no_ssuf) |
| 6139 | suffixes |= 1 << 4; |
| 6140 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
| 6141 | suffixes |= 1 << 5; |
| 6142 | |
| 6143 | /* There are more than suffix matches. */ |
| 6144 | if (i.tm.opcode_modifier.w |
| 6145 | || ((suffixes & (suffixes - 1)) |
| 6146 | && !i.tm.opcode_modifier.defaultsize |
| 6147 | && !i.tm.opcode_modifier.ignoresize)) |
| 6148 | { |
| 6149 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
| 6150 | return 0; |
| 6151 | } |
| 6152 | } |
| 6153 | } |
| 6154 | |
| 6155 | /* Change the opcode based on the operand size given by i.suffix. */ |
| 6156 | switch (i.suffix) |
| 6157 | { |
| 6158 | /* Size floating point instruction. */ |
| 6159 | case LONG_MNEM_SUFFIX: |
| 6160 | if (i.tm.opcode_modifier.floatmf) |
| 6161 | { |
| 6162 | i.tm.base_opcode ^= 4; |
| 6163 | break; |
| 6164 | } |
| 6165 | /* fall through */ |
| 6166 | case WORD_MNEM_SUFFIX: |
| 6167 | case QWORD_MNEM_SUFFIX: |
| 6168 | /* It's not a byte, select word/dword operation. */ |
| 6169 | if (i.tm.opcode_modifier.w) |
| 6170 | { |
| 6171 | if (i.tm.opcode_modifier.shortform) |
| 6172 | i.tm.base_opcode |= 8; |
| 6173 | else |
| 6174 | i.tm.base_opcode |= 1; |
| 6175 | } |
| 6176 | /* fall through */ |
| 6177 | case SHORT_MNEM_SUFFIX: |
| 6178 | /* Now select between word & dword operations via the operand |
| 6179 | size prefix, except for instructions that will ignore this |
| 6180 | prefix anyway. */ |
| 6181 | if (i.reg_operands > 0 |
| 6182 | && i.types[0].bitfield.reg |
| 6183 | && i.tm.opcode_modifier.addrprefixopreg |
| 6184 | && (i.tm.opcode_modifier.immext |
| 6185 | || i.operands == 1)) |
| 6186 | { |
| 6187 | /* The address size override prefix changes the size of the |
| 6188 | first operand. */ |
| 6189 | if ((flag_code == CODE_32BIT |
| 6190 | && i.op[0].regs->reg_type.bitfield.word) |
| 6191 | || (flag_code != CODE_32BIT |
| 6192 | && i.op[0].regs->reg_type.bitfield.dword)) |
| 6193 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
| 6194 | return 0; |
| 6195 | } |
| 6196 | else if (i.suffix != QWORD_MNEM_SUFFIX |
| 6197 | && !i.tm.opcode_modifier.ignoresize |
| 6198 | && !i.tm.opcode_modifier.floatmf |
| 6199 | && !i.tm.opcode_modifier.vex |
| 6200 | && !i.tm.opcode_modifier.vexopcode |
| 6201 | && !is_evex_encoding (&i.tm) |
| 6202 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
| 6203 | || (flag_code == CODE_64BIT |
| 6204 | && i.tm.opcode_modifier.jumpbyte))) |
| 6205 | { |
| 6206 | unsigned int prefix = DATA_PREFIX_OPCODE; |
| 6207 | |
| 6208 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
| 6209 | prefix = ADDR_PREFIX_OPCODE; |
| 6210 | |
| 6211 | if (!add_prefix (prefix)) |
| 6212 | return 0; |
| 6213 | } |
| 6214 | |
| 6215 | /* Set mode64 for an operand. */ |
| 6216 | if (i.suffix == QWORD_MNEM_SUFFIX |
| 6217 | && flag_code == CODE_64BIT |
| 6218 | && !i.tm.opcode_modifier.norex64 |
| 6219 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
| 6220 | need rex64. */ |
| 6221 | && ! (i.operands == 2 |
| 6222 | && i.tm.base_opcode == 0x90 |
| 6223 | && i.tm.extension_opcode == None |
| 6224 | && operand_type_equal (&i.types [0], &acc64) |
| 6225 | && operand_type_equal (&i.types [1], &acc64))) |
| 6226 | i.rex |= REX_W; |
| 6227 | |
| 6228 | break; |
| 6229 | } |
| 6230 | |
| 6231 | if (i.reg_operands != 0 |
| 6232 | && i.operands > 1 |
| 6233 | && i.tm.opcode_modifier.addrprefixopreg |
| 6234 | && !i.tm.opcode_modifier.immext) |
| 6235 | { |
| 6236 | /* Check invalid register operand when the address size override |
| 6237 | prefix changes the size of register operands. */ |
| 6238 | unsigned int op; |
| 6239 | enum { need_word, need_dword, need_qword } need; |
| 6240 | |
| 6241 | if (flag_code == CODE_32BIT) |
| 6242 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; |
| 6243 | else |
| 6244 | { |
| 6245 | if (i.prefix[ADDR_PREFIX]) |
| 6246 | need = need_dword; |
| 6247 | else |
| 6248 | need = flag_code == CODE_64BIT ? need_qword : need_word; |
| 6249 | } |
| 6250 | |
| 6251 | for (op = 0; op < i.operands; op++) |
| 6252 | if (i.types[op].bitfield.reg |
| 6253 | && ((need == need_word |
| 6254 | && !i.op[op].regs->reg_type.bitfield.word) |
| 6255 | || (need == need_dword |
| 6256 | && !i.op[op].regs->reg_type.bitfield.dword) |
| 6257 | || (need == need_qword |
| 6258 | && !i.op[op].regs->reg_type.bitfield.qword))) |
| 6259 | { |
| 6260 | as_bad (_("invalid register operand size for `%s'"), |
| 6261 | i.tm.name); |
| 6262 | return 0; |
| 6263 | } |
| 6264 | } |
| 6265 | |
| 6266 | return 1; |
| 6267 | } |
| 6268 | |
| 6269 | static int |
| 6270 | check_byte_reg (void) |
| 6271 | { |
| 6272 | int op; |
| 6273 | |
| 6274 | for (op = i.operands; --op >= 0;) |
| 6275 | { |
| 6276 | /* Skip non-register operands. */ |
| 6277 | if (!i.types[op].bitfield.reg) |
| 6278 | continue; |
| 6279 | |
| 6280 | /* If this is an eight bit register, it's OK. If it's the 16 or |
| 6281 | 32 bit version of an eight bit register, we will just use the |
| 6282 | low portion, and that's OK too. */ |
| 6283 | if (i.types[op].bitfield.byte) |
| 6284 | continue; |
| 6285 | |
| 6286 | /* I/O port address operands are OK too. */ |
| 6287 | if (i.tm.operand_types[op].bitfield.inoutportreg) |
| 6288 | continue; |
| 6289 | |
| 6290 | /* crc32 doesn't generate this warning. */ |
| 6291 | if (i.tm.base_opcode == 0xf20f38f0) |
| 6292 | continue; |
| 6293 | |
| 6294 | if ((i.types[op].bitfield.word |
| 6295 | || i.types[op].bitfield.dword |
| 6296 | || i.types[op].bitfield.qword) |
| 6297 | && i.op[op].regs->reg_num < 4 |
| 6298 | /* Prohibit these changes in 64bit mode, since the lowering |
| 6299 | would be more complicated. */ |
| 6300 | && flag_code != CODE_64BIT) |
| 6301 | { |
| 6302 | #if REGISTER_WARNINGS |
| 6303 | if (!quiet_warnings) |
| 6304 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
| 6305 | register_prefix, |
| 6306 | (i.op[op].regs + (i.types[op].bitfield.word |
| 6307 | ? REGNAM_AL - REGNAM_AX |
| 6308 | : REGNAM_AL - REGNAM_EAX))->reg_name, |
| 6309 | register_prefix, |
| 6310 | i.op[op].regs->reg_name, |
| 6311 | i.suffix); |
| 6312 | #endif |
| 6313 | continue; |
| 6314 | } |
| 6315 | /* Any other register is bad. */ |
| 6316 | if (i.types[op].bitfield.reg |
| 6317 | || i.types[op].bitfield.regmmx |
| 6318 | || i.types[op].bitfield.regsimd |
| 6319 | || i.types[op].bitfield.sreg2 |
| 6320 | || i.types[op].bitfield.sreg3 |
| 6321 | || i.types[op].bitfield.control |
| 6322 | || i.types[op].bitfield.debug |
| 6323 | || i.types[op].bitfield.test) |
| 6324 | { |
| 6325 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 6326 | register_prefix, |
| 6327 | i.op[op].regs->reg_name, |
| 6328 | i.tm.name, |
| 6329 | i.suffix); |
| 6330 | return 0; |
| 6331 | } |
| 6332 | } |
| 6333 | return 1; |
| 6334 | } |
| 6335 | |
| 6336 | static int |
| 6337 | check_long_reg (void) |
| 6338 | { |
| 6339 | int op; |
| 6340 | |
| 6341 | for (op = i.operands; --op >= 0;) |
| 6342 | /* Skip non-register operands. */ |
| 6343 | if (!i.types[op].bitfield.reg) |
| 6344 | continue; |
| 6345 | /* Reject eight bit registers, except where the template requires |
| 6346 | them. (eg. movzb) */ |
| 6347 | else if (i.types[op].bitfield.byte |
| 6348 | && (i.tm.operand_types[op].bitfield.reg |
| 6349 | || i.tm.operand_types[op].bitfield.acc) |
| 6350 | && (i.tm.operand_types[op].bitfield.word |
| 6351 | || i.tm.operand_types[op].bitfield.dword)) |
| 6352 | { |
| 6353 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 6354 | register_prefix, |
| 6355 | i.op[op].regs->reg_name, |
| 6356 | i.tm.name, |
| 6357 | i.suffix); |
| 6358 | return 0; |
| 6359 | } |
| 6360 | /* Warn if the e prefix on a general reg is missing. */ |
| 6361 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
| 6362 | && i.types[op].bitfield.word |
| 6363 | && (i.tm.operand_types[op].bitfield.reg |
| 6364 | || i.tm.operand_types[op].bitfield.acc) |
| 6365 | && i.tm.operand_types[op].bitfield.dword) |
| 6366 | { |
| 6367 | /* Prohibit these changes in the 64bit mode, since the |
| 6368 | lowering is more complicated. */ |
| 6369 | if (flag_code == CODE_64BIT) |
| 6370 | { |
| 6371 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
| 6372 | register_prefix, i.op[op].regs->reg_name, |
| 6373 | i.suffix); |
| 6374 | return 0; |
| 6375 | } |
| 6376 | #if REGISTER_WARNINGS |
| 6377 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
| 6378 | register_prefix, |
| 6379 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
| 6380 | register_prefix, i.op[op].regs->reg_name, i.suffix); |
| 6381 | #endif |
| 6382 | } |
| 6383 | /* Warn if the r prefix on a general reg is present. */ |
| 6384 | else if (i.types[op].bitfield.qword |
| 6385 | && (i.tm.operand_types[op].bitfield.reg |
| 6386 | || i.tm.operand_types[op].bitfield.acc) |
| 6387 | && i.tm.operand_types[op].bitfield.dword) |
| 6388 | { |
| 6389 | if (intel_syntax |
| 6390 | && i.tm.opcode_modifier.toqword |
| 6391 | && !i.types[0].bitfield.regsimd) |
| 6392 | { |
| 6393 | /* Convert to QWORD. We want REX byte. */ |
| 6394 | i.suffix = QWORD_MNEM_SUFFIX; |
| 6395 | } |
| 6396 | else |
| 6397 | { |
| 6398 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
| 6399 | register_prefix, i.op[op].regs->reg_name, |
| 6400 | i.suffix); |
| 6401 | return 0; |
| 6402 | } |
| 6403 | } |
| 6404 | return 1; |
| 6405 | } |
| 6406 | |
| 6407 | static int |
| 6408 | check_qword_reg (void) |
| 6409 | { |
| 6410 | int op; |
| 6411 | |
| 6412 | for (op = i.operands; --op >= 0; ) |
| 6413 | /* Skip non-register operands. */ |
| 6414 | if (!i.types[op].bitfield.reg) |
| 6415 | continue; |
| 6416 | /* Reject eight bit registers, except where the template requires |
| 6417 | them. (eg. movzb) */ |
| 6418 | else if (i.types[op].bitfield.byte |
| 6419 | && (i.tm.operand_types[op].bitfield.reg |
| 6420 | || i.tm.operand_types[op].bitfield.acc) |
| 6421 | && (i.tm.operand_types[op].bitfield.word |
| 6422 | || i.tm.operand_types[op].bitfield.dword)) |
| 6423 | { |
| 6424 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 6425 | register_prefix, |
| 6426 | i.op[op].regs->reg_name, |
| 6427 | i.tm.name, |
| 6428 | i.suffix); |
| 6429 | return 0; |
| 6430 | } |
| 6431 | /* Warn if the r prefix on a general reg is missing. */ |
| 6432 | else if ((i.types[op].bitfield.word |
| 6433 | || i.types[op].bitfield.dword) |
| 6434 | && (i.tm.operand_types[op].bitfield.reg |
| 6435 | || i.tm.operand_types[op].bitfield.acc) |
| 6436 | && i.tm.operand_types[op].bitfield.qword) |
| 6437 | { |
| 6438 | /* Prohibit these changes in the 64bit mode, since the |
| 6439 | lowering is more complicated. */ |
| 6440 | if (intel_syntax |
| 6441 | && i.tm.opcode_modifier.todword |
| 6442 | && !i.types[0].bitfield.regsimd) |
| 6443 | { |
| 6444 | /* Convert to DWORD. We don't want REX byte. */ |
| 6445 | i.suffix = LONG_MNEM_SUFFIX; |
| 6446 | } |
| 6447 | else |
| 6448 | { |
| 6449 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
| 6450 | register_prefix, i.op[op].regs->reg_name, |
| 6451 | i.suffix); |
| 6452 | return 0; |
| 6453 | } |
| 6454 | } |
| 6455 | return 1; |
| 6456 | } |
| 6457 | |
| 6458 | static int |
| 6459 | check_word_reg (void) |
| 6460 | { |
| 6461 | int op; |
| 6462 | for (op = i.operands; --op >= 0;) |
| 6463 | /* Skip non-register operands. */ |
| 6464 | if (!i.types[op].bitfield.reg) |
| 6465 | continue; |
| 6466 | /* Reject eight bit registers, except where the template requires |
| 6467 | them. (eg. movzb) */ |
| 6468 | else if (i.types[op].bitfield.byte |
| 6469 | && (i.tm.operand_types[op].bitfield.reg |
| 6470 | || i.tm.operand_types[op].bitfield.acc) |
| 6471 | && (i.tm.operand_types[op].bitfield.word |
| 6472 | || i.tm.operand_types[op].bitfield.dword)) |
| 6473 | { |
| 6474 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
| 6475 | register_prefix, |
| 6476 | i.op[op].regs->reg_name, |
| 6477 | i.tm.name, |
| 6478 | i.suffix); |
| 6479 | return 0; |
| 6480 | } |
| 6481 | /* Warn if the e or r prefix on a general reg is present. */ |
| 6482 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
| 6483 | && (i.types[op].bitfield.dword |
| 6484 | || i.types[op].bitfield.qword) |
| 6485 | && (i.tm.operand_types[op].bitfield.reg |
| 6486 | || i.tm.operand_types[op].bitfield.acc) |
| 6487 | && i.tm.operand_types[op].bitfield.word) |
| 6488 | { |
| 6489 | /* Prohibit these changes in the 64bit mode, since the |
| 6490 | lowering is more complicated. */ |
| 6491 | if (flag_code == CODE_64BIT) |
| 6492 | { |
| 6493 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
| 6494 | register_prefix, i.op[op].regs->reg_name, |
| 6495 | i.suffix); |
| 6496 | return 0; |
| 6497 | } |
| 6498 | #if REGISTER_WARNINGS |
| 6499 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
| 6500 | register_prefix, |
| 6501 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
| 6502 | register_prefix, i.op[op].regs->reg_name, i.suffix); |
| 6503 | #endif |
| 6504 | } |
| 6505 | return 1; |
| 6506 | } |
| 6507 | |
| 6508 | static int |
| 6509 | update_imm (unsigned int j) |
| 6510 | { |
| 6511 | i386_operand_type overlap = i.types[j]; |
| 6512 | if ((overlap.bitfield.imm8 |
| 6513 | || overlap.bitfield.imm8s |
| 6514 | || overlap.bitfield.imm16 |
| 6515 | || overlap.bitfield.imm32 |
| 6516 | || overlap.bitfield.imm32s |
| 6517 | || overlap.bitfield.imm64) |
| 6518 | && !operand_type_equal (&overlap, &imm8) |
| 6519 | && !operand_type_equal (&overlap, &imm8s) |
| 6520 | && !operand_type_equal (&overlap, &imm16) |
| 6521 | && !operand_type_equal (&overlap, &imm32) |
| 6522 | && !operand_type_equal (&overlap, &imm32s) |
| 6523 | && !operand_type_equal (&overlap, &imm64)) |
| 6524 | { |
| 6525 | if (i.suffix) |
| 6526 | { |
| 6527 | i386_operand_type temp; |
| 6528 | |
| 6529 | operand_type_set (&temp, 0); |
| 6530 | if (i.suffix == BYTE_MNEM_SUFFIX) |
| 6531 | { |
| 6532 | temp.bitfield.imm8 = overlap.bitfield.imm8; |
| 6533 | temp.bitfield.imm8s = overlap.bitfield.imm8s; |
| 6534 | } |
| 6535 | else if (i.suffix == WORD_MNEM_SUFFIX) |
| 6536 | temp.bitfield.imm16 = overlap.bitfield.imm16; |
| 6537 | else if (i.suffix == QWORD_MNEM_SUFFIX) |
| 6538 | { |
| 6539 | temp.bitfield.imm64 = overlap.bitfield.imm64; |
| 6540 | temp.bitfield.imm32s = overlap.bitfield.imm32s; |
| 6541 | } |
| 6542 | else |
| 6543 | temp.bitfield.imm32 = overlap.bitfield.imm32; |
| 6544 | overlap = temp; |
| 6545 | } |
| 6546 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
| 6547 | || operand_type_equal (&overlap, &imm16_32) |
| 6548 | || operand_type_equal (&overlap, &imm16_32s)) |
| 6549 | { |
| 6550 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
| 6551 | overlap = imm16; |
| 6552 | else |
| 6553 | overlap = imm32s; |
| 6554 | } |
| 6555 | if (!operand_type_equal (&overlap, &imm8) |
| 6556 | && !operand_type_equal (&overlap, &imm8s) |
| 6557 | && !operand_type_equal (&overlap, &imm16) |
| 6558 | && !operand_type_equal (&overlap, &imm32) |
| 6559 | && !operand_type_equal (&overlap, &imm32s) |
| 6560 | && !operand_type_equal (&overlap, &imm64)) |
| 6561 | { |
| 6562 | as_bad (_("no instruction mnemonic suffix given; " |
| 6563 | "can't determine immediate size")); |
| 6564 | return 0; |
| 6565 | } |
| 6566 | } |
| 6567 | i.types[j] = overlap; |
| 6568 | |
| 6569 | return 1; |
| 6570 | } |
| 6571 | |
| 6572 | static int |
| 6573 | finalize_imm (void) |
| 6574 | { |
| 6575 | unsigned int j, n; |
| 6576 | |
| 6577 | /* Update the first 2 immediate operands. */ |
| 6578 | n = i.operands > 2 ? 2 : i.operands; |
| 6579 | if (n) |
| 6580 | { |
| 6581 | for (j = 0; j < n; j++) |
| 6582 | if (update_imm (j) == 0) |
| 6583 | return 0; |
| 6584 | |
| 6585 | /* The 3rd operand can't be immediate operand. */ |
| 6586 | gas_assert (operand_type_check (i.types[2], imm) == 0); |
| 6587 | } |
| 6588 | |
| 6589 | return 1; |
| 6590 | } |
| 6591 | |
| 6592 | static int |
| 6593 | process_operands (void) |
| 6594 | { |
| 6595 | /* Default segment register this instruction will use for memory |
| 6596 | accesses. 0 means unknown. This is only for optimizing out |
| 6597 | unnecessary segment overrides. */ |
| 6598 | const seg_entry *default_seg = 0; |
| 6599 | |
| 6600 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
| 6601 | { |
| 6602 | unsigned int dupl = i.operands; |
| 6603 | unsigned int dest = dupl - 1; |
| 6604 | unsigned int j; |
| 6605 | |
| 6606 | /* The destination must be an xmm register. */ |
| 6607 | gas_assert (i.reg_operands |
| 6608 | && MAX_OPERANDS > dupl |
| 6609 | && operand_type_equal (&i.types[dest], ®xmm)); |
| 6610 | |
| 6611 | if (i.tm.operand_types[0].bitfield.acc |
| 6612 | && i.tm.operand_types[0].bitfield.xmmword) |
| 6613 | { |
| 6614 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
| 6615 | { |
| 6616 | /* Keep xmm0 for instructions with VEX prefix and 3 |
| 6617 | sources. */ |
| 6618 | i.tm.operand_types[0].bitfield.acc = 0; |
| 6619 | i.tm.operand_types[0].bitfield.regsimd = 1; |
| 6620 | goto duplicate; |
| 6621 | } |
| 6622 | else |
| 6623 | { |
| 6624 | /* We remove the first xmm0 and keep the number of |
| 6625 | operands unchanged, which in fact duplicates the |
| 6626 | destination. */ |
| 6627 | for (j = 1; j < i.operands; j++) |
| 6628 | { |
| 6629 | i.op[j - 1] = i.op[j]; |
| 6630 | i.types[j - 1] = i.types[j]; |
| 6631 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; |
| 6632 | } |
| 6633 | } |
| 6634 | } |
| 6635 | else if (i.tm.opcode_modifier.implicit1stxmm0) |
| 6636 | { |
| 6637 | gas_assert ((MAX_OPERANDS - 1) > dupl |
| 6638 | && (i.tm.opcode_modifier.vexsources |
| 6639 | == VEX3SOURCES)); |
| 6640 | |
| 6641 | /* Add the implicit xmm0 for instructions with VEX prefix |
| 6642 | and 3 sources. */ |
| 6643 | for (j = i.operands; j > 0; j--) |
| 6644 | { |
| 6645 | i.op[j] = i.op[j - 1]; |
| 6646 | i.types[j] = i.types[j - 1]; |
| 6647 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; |
| 6648 | } |
| 6649 | i.op[0].regs |
| 6650 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); |
| 6651 | i.types[0] = regxmm; |
| 6652 | i.tm.operand_types[0] = regxmm; |
| 6653 | |
| 6654 | i.operands += 2; |
| 6655 | i.reg_operands += 2; |
| 6656 | i.tm.operands += 2; |
| 6657 | |
| 6658 | dupl++; |
| 6659 | dest++; |
| 6660 | i.op[dupl] = i.op[dest]; |
| 6661 | i.types[dupl] = i.types[dest]; |
| 6662 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; |
| 6663 | } |
| 6664 | else |
| 6665 | { |
| 6666 | duplicate: |
| 6667 | i.operands++; |
| 6668 | i.reg_operands++; |
| 6669 | i.tm.operands++; |
| 6670 | |
| 6671 | i.op[dupl] = i.op[dest]; |
| 6672 | i.types[dupl] = i.types[dest]; |
| 6673 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; |
| 6674 | } |
| 6675 | |
| 6676 | if (i.tm.opcode_modifier.immext) |
| 6677 | process_immext (); |
| 6678 | } |
| 6679 | else if (i.tm.operand_types[0].bitfield.acc |
| 6680 | && i.tm.operand_types[0].bitfield.xmmword) |
| 6681 | { |
| 6682 | unsigned int j; |
| 6683 | |
| 6684 | for (j = 1; j < i.operands; j++) |
| 6685 | { |
| 6686 | i.op[j - 1] = i.op[j]; |
| 6687 | i.types[j - 1] = i.types[j]; |
| 6688 | |
| 6689 | /* We need to adjust fields in i.tm since they are used by |
| 6690 | build_modrm_byte. */ |
| 6691 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; |
| 6692 | } |
| 6693 | |
| 6694 | i.operands--; |
| 6695 | i.reg_operands--; |
| 6696 | i.tm.operands--; |
| 6697 | } |
| 6698 | else if (i.tm.opcode_modifier.implicitquadgroup) |
| 6699 | { |
| 6700 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
| 6701 | |
| 6702 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
| 6703 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
| 6704 | regnum = register_number (i.op[1].regs); |
| 6705 | first_reg_in_group = regnum & ~3; |
| 6706 | last_reg_in_group = first_reg_in_group + 3; |
| 6707 | if (regnum != first_reg_in_group) |
| 6708 | as_warn (_("source register `%s%s' implicitly denotes" |
| 6709 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), |
| 6710 | register_prefix, i.op[1].regs->reg_name, |
| 6711 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, |
| 6712 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, |
| 6713 | i.tm.name); |
| 6714 | } |
| 6715 | else if (i.tm.opcode_modifier.regkludge) |
| 6716 | { |
| 6717 | /* The imul $imm, %reg instruction is converted into |
| 6718 | imul $imm, %reg, %reg, and the clr %reg instruction |
| 6719 | is converted into xor %reg, %reg. */ |
| 6720 | |
| 6721 | unsigned int first_reg_op; |
| 6722 | |
| 6723 | if (operand_type_check (i.types[0], reg)) |
| 6724 | first_reg_op = 0; |
| 6725 | else |
| 6726 | first_reg_op = 1; |
| 6727 | /* Pretend we saw the extra register operand. */ |
| 6728 | gas_assert (i.reg_operands == 1 |
| 6729 | && i.op[first_reg_op + 1].regs == 0); |
| 6730 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
| 6731 | i.types[first_reg_op + 1] = i.types[first_reg_op]; |
| 6732 | i.operands++; |
| 6733 | i.reg_operands++; |
| 6734 | } |
| 6735 | |
| 6736 | if (i.tm.opcode_modifier.shortform) |
| 6737 | { |
| 6738 | if (i.types[0].bitfield.sreg2 |
| 6739 | || i.types[0].bitfield.sreg3) |
| 6740 | { |
| 6741 | if (i.tm.base_opcode == POP_SEG_SHORT |
| 6742 | && i.op[0].regs->reg_num == 1) |
| 6743 | { |
| 6744 | as_bad (_("you can't `pop %scs'"), register_prefix); |
| 6745 | return 0; |
| 6746 | } |
| 6747 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
| 6748 | if ((i.op[0].regs->reg_flags & RegRex) != 0) |
| 6749 | i.rex |= REX_B; |
| 6750 | } |
| 6751 | else |
| 6752 | { |
| 6753 | /* The register or float register operand is in operand |
| 6754 | 0 or 1. */ |
| 6755 | unsigned int op; |
| 6756 | |
| 6757 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
| 6758 | || operand_type_check (i.types[0], reg)) |
| 6759 | op = 0; |
| 6760 | else |
| 6761 | op = 1; |
| 6762 | /* Register goes in low 3 bits of opcode. */ |
| 6763 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
| 6764 | if ((i.op[op].regs->reg_flags & RegRex) != 0) |
| 6765 | i.rex |= REX_B; |
| 6766 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
| 6767 | { |
| 6768 | /* Warn about some common errors, but press on regardless. |
| 6769 | The first case can be generated by gcc (<= 2.8.1). */ |
| 6770 | if (i.operands == 2) |
| 6771 | { |
| 6772 | /* Reversed arguments on faddp, fsubp, etc. */ |
| 6773 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
| 6774 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
| 6775 | register_prefix, i.op[intel_syntax].regs->reg_name); |
| 6776 | } |
| 6777 | else |
| 6778 | { |
| 6779 | /* Extraneous `l' suffix on fp insn. */ |
| 6780 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
| 6781 | register_prefix, i.op[0].regs->reg_name); |
| 6782 | } |
| 6783 | } |
| 6784 | } |
| 6785 | } |
| 6786 | else if (i.tm.opcode_modifier.modrm) |
| 6787 | { |
| 6788 | /* The opcode is completed (modulo i.tm.extension_opcode which |
| 6789 | must be put into the modrm byte). Now, we make the modrm and |
| 6790 | index base bytes based on all the info we've collected. */ |
| 6791 | |
| 6792 | default_seg = build_modrm_byte (); |
| 6793 | } |
| 6794 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
| 6795 | { |
| 6796 | default_seg = &ds; |
| 6797 | } |
| 6798 | else if (i.tm.opcode_modifier.isstring) |
| 6799 | { |
| 6800 | /* For the string instructions that allow a segment override |
| 6801 | on one of their operands, the default segment is ds. */ |
| 6802 | default_seg = &ds; |
| 6803 | } |
| 6804 | |
| 6805 | if (i.tm.base_opcode == 0x8d /* lea */ |
| 6806 | && i.seg[0] |
| 6807 | && !quiet_warnings) |
| 6808 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
| 6809 | |
| 6810 | /* If a segment was explicitly specified, and the specified segment |
| 6811 | is not the default, use an opcode prefix to select it. If we |
| 6812 | never figured out what the default segment is, then default_seg |
| 6813 | will be zero at this point, and the specified segment prefix will |
| 6814 | always be used. */ |
| 6815 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
| 6816 | { |
| 6817 | if (!add_prefix (i.seg[0]->seg_prefix)) |
| 6818 | return 0; |
| 6819 | } |
| 6820 | return 1; |
| 6821 | } |
| 6822 | |
| 6823 | static const seg_entry * |
| 6824 | build_modrm_byte (void) |
| 6825 | { |
| 6826 | const seg_entry *default_seg = 0; |
| 6827 | unsigned int source, dest; |
| 6828 | int vex_3_sources; |
| 6829 | |
| 6830 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
| 6831 | if (vex_3_sources) |
| 6832 | { |
| 6833 | unsigned int nds, reg_slot; |
| 6834 | expressionS *exp; |
| 6835 | |
| 6836 | dest = i.operands - 1; |
| 6837 | nds = dest - 1; |
| 6838 | |
| 6839 | /* There are 2 kinds of instructions: |
| 6840 | 1. 5 operands: 4 register operands or 3 register operands |
| 6841 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and |
| 6842 | VexW0 or VexW1. The destination must be either XMM, YMM or |
| 6843 | ZMM register. |
| 6844 | 2. 4 operands: 4 register operands or 3 register operands |
| 6845 | plus 1 memory operand, with VexXDS. */ |
| 6846 | gas_assert ((i.reg_operands == 4 |
| 6847 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
| 6848 | && i.tm.opcode_modifier.vexvvvv == VEXXDS |
| 6849 | && i.tm.opcode_modifier.vexw |
| 6850 | && i.tm.operand_types[dest].bitfield.regsimd); |
| 6851 | |
| 6852 | /* If VexW1 is set, the first non-immediate operand is the source and |
| 6853 | the second non-immediate one is encoded in the immediate operand. */ |
| 6854 | if (i.tm.opcode_modifier.vexw == VEXW1) |
| 6855 | { |
| 6856 | source = i.imm_operands; |
| 6857 | reg_slot = i.imm_operands + 1; |
| 6858 | } |
| 6859 | else |
| 6860 | { |
| 6861 | source = i.imm_operands + 1; |
| 6862 | reg_slot = i.imm_operands; |
| 6863 | } |
| 6864 | |
| 6865 | if (i.imm_operands == 0) |
| 6866 | { |
| 6867 | /* When there is no immediate operand, generate an 8bit |
| 6868 | immediate operand to encode the first operand. */ |
| 6869 | exp = &im_expressions[i.imm_operands++]; |
| 6870 | i.op[i.operands].imms = exp; |
| 6871 | i.types[i.operands] = imm8; |
| 6872 | i.operands++; |
| 6873 | |
| 6874 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
| 6875 | exp->X_op = O_constant; |
| 6876 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
| 6877 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
| 6878 | } |
| 6879 | else |
| 6880 | { |
| 6881 | unsigned int imm_slot; |
| 6882 | |
| 6883 | gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4); |
| 6884 | |
| 6885 | if (i.tm.opcode_modifier.immext) |
| 6886 | { |
| 6887 | /* When ImmExt is set, the immediate byte is the last |
| 6888 | operand. */ |
| 6889 | imm_slot = i.operands - 1; |
| 6890 | source--; |
| 6891 | reg_slot--; |
| 6892 | } |
| 6893 | else |
| 6894 | { |
| 6895 | imm_slot = 0; |
| 6896 | |
| 6897 | /* Turn on Imm8 so that output_imm will generate it. */ |
| 6898 | i.types[imm_slot].bitfield.imm8 = 1; |
| 6899 | } |
| 6900 | |
| 6901 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
| 6902 | i.op[imm_slot].imms->X_add_number |
| 6903 | |= register_number (i.op[reg_slot].regs) << 4; |
| 6904 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
| 6905 | } |
| 6906 | |
| 6907 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
| 6908 | i.vex.register_specifier = i.op[nds].regs; |
| 6909 | } |
| 6910 | else |
| 6911 | source = dest = 0; |
| 6912 | |
| 6913 | /* i.reg_operands MUST be the number of real register operands; |
| 6914 | implicit registers do not count. If there are 3 register |
| 6915 | operands, it must be a instruction with VexNDS. For a |
| 6916 | instruction with VexNDD, the destination register is encoded |
| 6917 | in VEX prefix. If there are 4 register operands, it must be |
| 6918 | a instruction with VEX prefix and 3 sources. */ |
| 6919 | if (i.mem_operands == 0 |
| 6920 | && ((i.reg_operands == 2 |
| 6921 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
| 6922 | || (i.reg_operands == 3 |
| 6923 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
| 6924 | || (i.reg_operands == 4 && vex_3_sources))) |
| 6925 | { |
| 6926 | switch (i.operands) |
| 6927 | { |
| 6928 | case 2: |
| 6929 | source = 0; |
| 6930 | break; |
| 6931 | case 3: |
| 6932 | /* When there are 3 operands, one of them may be immediate, |
| 6933 | which may be the first or the last operand. Otherwise, |
| 6934 | the first operand must be shift count register (cl) or it |
| 6935 | is an instruction with VexNDS. */ |
| 6936 | gas_assert (i.imm_operands == 1 |
| 6937 | || (i.imm_operands == 0 |
| 6938 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
| 6939 | || i.types[0].bitfield.shiftcount))); |
| 6940 | if (operand_type_check (i.types[0], imm) |
| 6941 | || i.types[0].bitfield.shiftcount) |
| 6942 | source = 1; |
| 6943 | else |
| 6944 | source = 0; |
| 6945 | break; |
| 6946 | case 4: |
| 6947 | /* When there are 4 operands, the first two must be 8bit |
| 6948 | immediate operands. The source operand will be the 3rd |
| 6949 | one. |
| 6950 | |
| 6951 | For instructions with VexNDS, if the first operand |
| 6952 | an imm8, the source operand is the 2nd one. If the last |
| 6953 | operand is imm8, the source operand is the first one. */ |
| 6954 | gas_assert ((i.imm_operands == 2 |
| 6955 | && i.types[0].bitfield.imm8 |
| 6956 | && i.types[1].bitfield.imm8) |
| 6957 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
| 6958 | && i.imm_operands == 1 |
| 6959 | && (i.types[0].bitfield.imm8 |
| 6960 | || i.types[i.operands - 1].bitfield.imm8 |
| 6961 | || i.rounding))); |
| 6962 | if (i.imm_operands == 2) |
| 6963 | source = 2; |
| 6964 | else |
| 6965 | { |
| 6966 | if (i.types[0].bitfield.imm8) |
| 6967 | source = 1; |
| 6968 | else |
| 6969 | source = 0; |
| 6970 | } |
| 6971 | break; |
| 6972 | case 5: |
| 6973 | if (is_evex_encoding (&i.tm)) |
| 6974 | { |
| 6975 | /* For EVEX instructions, when there are 5 operands, the |
| 6976 | first one must be immediate operand. If the second one |
| 6977 | is immediate operand, the source operand is the 3th |
| 6978 | one. If the last one is immediate operand, the source |
| 6979 | operand is the 2nd one. */ |
| 6980 | gas_assert (i.imm_operands == 2 |
| 6981 | && i.tm.opcode_modifier.sae |
| 6982 | && operand_type_check (i.types[0], imm)); |
| 6983 | if (operand_type_check (i.types[1], imm)) |
| 6984 | source = 2; |
| 6985 | else if (operand_type_check (i.types[4], imm)) |
| 6986 | source = 1; |
| 6987 | else |
| 6988 | abort (); |
| 6989 | } |
| 6990 | break; |
| 6991 | default: |
| 6992 | abort (); |
| 6993 | } |
| 6994 | |
| 6995 | if (!vex_3_sources) |
| 6996 | { |
| 6997 | dest = source + 1; |
| 6998 | |
| 6999 | /* RC/SAE operand could be between DEST and SRC. That happens |
| 7000 | when one operand is GPR and the other one is XMM/YMM/ZMM |
| 7001 | register. */ |
| 7002 | if (i.rounding && i.rounding->operand == (int) dest) |
| 7003 | dest++; |
| 7004 | |
| 7005 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
| 7006 | { |
| 7007 | /* For instructions with VexNDS, the register-only source |
| 7008 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
| 7009 | register. It is encoded in VEX prefix. We need to |
| 7010 | clear RegMem bit before calling operand_type_equal. */ |
| 7011 | |
| 7012 | i386_operand_type op; |
| 7013 | unsigned int vvvv; |
| 7014 | |
| 7015 | /* Check register-only source operand when two source |
| 7016 | operands are swapped. */ |
| 7017 | if (!i.tm.operand_types[source].bitfield.baseindex |
| 7018 | && i.tm.operand_types[dest].bitfield.baseindex) |
| 7019 | { |
| 7020 | vvvv = source; |
| 7021 | source = dest; |
| 7022 | } |
| 7023 | else |
| 7024 | vvvv = dest; |
| 7025 | |
| 7026 | op = i.tm.operand_types[vvvv]; |
| 7027 | op.bitfield.regmem = 0; |
| 7028 | if ((dest + 1) >= i.operands |
| 7029 | || ((!op.bitfield.reg |
| 7030 | || (!op.bitfield.dword && !op.bitfield.qword)) |
| 7031 | && !op.bitfield.regsimd |
| 7032 | && !operand_type_equal (&op, ®mask))) |
| 7033 | abort (); |
| 7034 | i.vex.register_specifier = i.op[vvvv].regs; |
| 7035 | dest++; |
| 7036 | } |
| 7037 | } |
| 7038 | |
| 7039 | i.rm.mode = 3; |
| 7040 | /* One of the register operands will be encoded in the i.tm.reg |
| 7041 | field, the other in the combined i.tm.mode and i.tm.regmem |
| 7042 | fields. If no form of this instruction supports a memory |
| 7043 | destination operand, then we assume the source operand may |
| 7044 | sometimes be a memory operand and so we need to store the |
| 7045 | destination in the i.rm.reg field. */ |
| 7046 | if (!i.tm.operand_types[dest].bitfield.regmem |
| 7047 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
| 7048 | { |
| 7049 | i.rm.reg = i.op[dest].regs->reg_num; |
| 7050 | i.rm.regmem = i.op[source].regs->reg_num; |
| 7051 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
| 7052 | i.rex |= REX_R; |
| 7053 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
| 7054 | i.vrex |= REX_R; |
| 7055 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
| 7056 | i.rex |= REX_B; |
| 7057 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
| 7058 | i.vrex |= REX_B; |
| 7059 | } |
| 7060 | else |
| 7061 | { |
| 7062 | i.rm.reg = i.op[source].regs->reg_num; |
| 7063 | i.rm.regmem = i.op[dest].regs->reg_num; |
| 7064 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
| 7065 | i.rex |= REX_B; |
| 7066 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
| 7067 | i.vrex |= REX_B; |
| 7068 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
| 7069 | i.rex |= REX_R; |
| 7070 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
| 7071 | i.vrex |= REX_R; |
| 7072 | } |
| 7073 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
| 7074 | { |
| 7075 | if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control) |
| 7076 | abort (); |
| 7077 | i.rex &= ~REX_R; |
| 7078 | add_prefix (LOCK_PREFIX_OPCODE); |
| 7079 | } |
| 7080 | } |
| 7081 | else |
| 7082 | { /* If it's not 2 reg operands... */ |
| 7083 | unsigned int mem; |
| 7084 | |
| 7085 | if (i.mem_operands) |
| 7086 | { |
| 7087 | unsigned int fake_zero_displacement = 0; |
| 7088 | unsigned int op; |
| 7089 | |
| 7090 | for (op = 0; op < i.operands; op++) |
| 7091 | if (operand_type_check (i.types[op], anymem)) |
| 7092 | break; |
| 7093 | gas_assert (op < i.operands); |
| 7094 | |
| 7095 | if (i.tm.opcode_modifier.vecsib) |
| 7096 | { |
| 7097 | if (i.index_reg->reg_num == RegIZ) |
| 7098 | abort (); |
| 7099 | |
| 7100 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 7101 | if (!i.base_reg) |
| 7102 | { |
| 7103 | i.sib.base = NO_BASE_REGISTER; |
| 7104 | i.sib.scale = i.log2_scale_factor; |
| 7105 | i.types[op].bitfield.disp8 = 0; |
| 7106 | i.types[op].bitfield.disp16 = 0; |
| 7107 | i.types[op].bitfield.disp64 = 0; |
| 7108 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
| 7109 | { |
| 7110 | /* Must be 32 bit */ |
| 7111 | i.types[op].bitfield.disp32 = 1; |
| 7112 | i.types[op].bitfield.disp32s = 0; |
| 7113 | } |
| 7114 | else |
| 7115 | { |
| 7116 | i.types[op].bitfield.disp32 = 0; |
| 7117 | i.types[op].bitfield.disp32s = 1; |
| 7118 | } |
| 7119 | } |
| 7120 | i.sib.index = i.index_reg->reg_num; |
| 7121 | if ((i.index_reg->reg_flags & RegRex) != 0) |
| 7122 | i.rex |= REX_X; |
| 7123 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
| 7124 | i.vrex |= REX_X; |
| 7125 | } |
| 7126 | |
| 7127 | default_seg = &ds; |
| 7128 | |
| 7129 | if (i.base_reg == 0) |
| 7130 | { |
| 7131 | i.rm.mode = 0; |
| 7132 | if (!i.disp_operands) |
| 7133 | fake_zero_displacement = 1; |
| 7134 | if (i.index_reg == 0) |
| 7135 | { |
| 7136 | i386_operand_type newdisp; |
| 7137 | |
| 7138 | gas_assert (!i.tm.opcode_modifier.vecsib); |
| 7139 | /* Operand is just <disp> */ |
| 7140 | if (flag_code == CODE_64BIT) |
| 7141 | { |
| 7142 | /* 64bit mode overwrites the 32bit absolute |
| 7143 | addressing by RIP relative addressing and |
| 7144 | absolute addressing is encoded by one of the |
| 7145 | redundant SIB forms. */ |
| 7146 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 7147 | i.sib.base = NO_BASE_REGISTER; |
| 7148 | i.sib.index = NO_INDEX_REGISTER; |
| 7149 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
| 7150 | } |
| 7151 | else if ((flag_code == CODE_16BIT) |
| 7152 | ^ (i.prefix[ADDR_PREFIX] != 0)) |
| 7153 | { |
| 7154 | i.rm.regmem = NO_BASE_REGISTER_16; |
| 7155 | newdisp = disp16; |
| 7156 | } |
| 7157 | else |
| 7158 | { |
| 7159 | i.rm.regmem = NO_BASE_REGISTER; |
| 7160 | newdisp = disp32; |
| 7161 | } |
| 7162 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
| 7163 | i.types[op] = operand_type_or (i.types[op], newdisp); |
| 7164 | } |
| 7165 | else if (!i.tm.opcode_modifier.vecsib) |
| 7166 | { |
| 7167 | /* !i.base_reg && i.index_reg */ |
| 7168 | if (i.index_reg->reg_num == RegIZ) |
| 7169 | i.sib.index = NO_INDEX_REGISTER; |
| 7170 | else |
| 7171 | i.sib.index = i.index_reg->reg_num; |
| 7172 | i.sib.base = NO_BASE_REGISTER; |
| 7173 | i.sib.scale = i.log2_scale_factor; |
| 7174 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 7175 | i.types[op].bitfield.disp8 = 0; |
| 7176 | i.types[op].bitfield.disp16 = 0; |
| 7177 | i.types[op].bitfield.disp64 = 0; |
| 7178 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
| 7179 | { |
| 7180 | /* Must be 32 bit */ |
| 7181 | i.types[op].bitfield.disp32 = 1; |
| 7182 | i.types[op].bitfield.disp32s = 0; |
| 7183 | } |
| 7184 | else |
| 7185 | { |
| 7186 | i.types[op].bitfield.disp32 = 0; |
| 7187 | i.types[op].bitfield.disp32s = 1; |
| 7188 | } |
| 7189 | if ((i.index_reg->reg_flags & RegRex) != 0) |
| 7190 | i.rex |= REX_X; |
| 7191 | } |
| 7192 | } |
| 7193 | /* RIP addressing for 64bit mode. */ |
| 7194 | else if (i.base_reg->reg_num == RegIP) |
| 7195 | { |
| 7196 | gas_assert (!i.tm.opcode_modifier.vecsib); |
| 7197 | i.rm.regmem = NO_BASE_REGISTER; |
| 7198 | i.types[op].bitfield.disp8 = 0; |
| 7199 | i.types[op].bitfield.disp16 = 0; |
| 7200 | i.types[op].bitfield.disp32 = 0; |
| 7201 | i.types[op].bitfield.disp32s = 1; |
| 7202 | i.types[op].bitfield.disp64 = 0; |
| 7203 | i.flags[op] |= Operand_PCrel; |
| 7204 | if (! i.disp_operands) |
| 7205 | fake_zero_displacement = 1; |
| 7206 | } |
| 7207 | else if (i.base_reg->reg_type.bitfield.word) |
| 7208 | { |
| 7209 | gas_assert (!i.tm.opcode_modifier.vecsib); |
| 7210 | switch (i.base_reg->reg_num) |
| 7211 | { |
| 7212 | case 3: /* (%bx) */ |
| 7213 | if (i.index_reg == 0) |
| 7214 | i.rm.regmem = 7; |
| 7215 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
| 7216 | i.rm.regmem = i.index_reg->reg_num - 6; |
| 7217 | break; |
| 7218 | case 5: /* (%bp) */ |
| 7219 | default_seg = &ss; |
| 7220 | if (i.index_reg == 0) |
| 7221 | { |
| 7222 | i.rm.regmem = 6; |
| 7223 | if (operand_type_check (i.types[op], disp) == 0) |
| 7224 | { |
| 7225 | /* fake (%bp) into 0(%bp) */ |
| 7226 | i.types[op].bitfield.disp8 = 1; |
| 7227 | fake_zero_displacement = 1; |
| 7228 | } |
| 7229 | } |
| 7230 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
| 7231 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
| 7232 | break; |
| 7233 | default: /* (%si) -> 4 or (%di) -> 5 */ |
| 7234 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
| 7235 | } |
| 7236 | i.rm.mode = mode_from_disp_size (i.types[op]); |
| 7237 | } |
| 7238 | else /* i.base_reg and 32/64 bit mode */ |
| 7239 | { |
| 7240 | if (flag_code == CODE_64BIT |
| 7241 | && operand_type_check (i.types[op], disp)) |
| 7242 | { |
| 7243 | i.types[op].bitfield.disp16 = 0; |
| 7244 | i.types[op].bitfield.disp64 = 0; |
| 7245 | if (i.prefix[ADDR_PREFIX] == 0) |
| 7246 | { |
| 7247 | i.types[op].bitfield.disp32 = 0; |
| 7248 | i.types[op].bitfield.disp32s = 1; |
| 7249 | } |
| 7250 | else |
| 7251 | { |
| 7252 | i.types[op].bitfield.disp32 = 1; |
| 7253 | i.types[op].bitfield.disp32s = 0; |
| 7254 | } |
| 7255 | } |
| 7256 | |
| 7257 | if (!i.tm.opcode_modifier.vecsib) |
| 7258 | i.rm.regmem = i.base_reg->reg_num; |
| 7259 | if ((i.base_reg->reg_flags & RegRex) != 0) |
| 7260 | i.rex |= REX_B; |
| 7261 | i.sib.base = i.base_reg->reg_num; |
| 7262 | /* x86-64 ignores REX prefix bit here to avoid decoder |
| 7263 | complications. */ |
| 7264 | if (!(i.base_reg->reg_flags & RegRex) |
| 7265 | && (i.base_reg->reg_num == EBP_REG_NUM |
| 7266 | || i.base_reg->reg_num == ESP_REG_NUM)) |
| 7267 | default_seg = &ss; |
| 7268 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
| 7269 | { |
| 7270 | fake_zero_displacement = 1; |
| 7271 | i.types[op].bitfield.disp8 = 1; |
| 7272 | } |
| 7273 | i.sib.scale = i.log2_scale_factor; |
| 7274 | if (i.index_reg == 0) |
| 7275 | { |
| 7276 | gas_assert (!i.tm.opcode_modifier.vecsib); |
| 7277 | /* <disp>(%esp) becomes two byte modrm with no index |
| 7278 | register. We've already stored the code for esp |
| 7279 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. |
| 7280 | Any base register besides %esp will not use the |
| 7281 | extra modrm byte. */ |
| 7282 | i.sib.index = NO_INDEX_REGISTER; |
| 7283 | } |
| 7284 | else if (!i.tm.opcode_modifier.vecsib) |
| 7285 | { |
| 7286 | if (i.index_reg->reg_num == RegIZ) |
| 7287 | i.sib.index = NO_INDEX_REGISTER; |
| 7288 | else |
| 7289 | i.sib.index = i.index_reg->reg_num; |
| 7290 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
| 7291 | if ((i.index_reg->reg_flags & RegRex) != 0) |
| 7292 | i.rex |= REX_X; |
| 7293 | } |
| 7294 | |
| 7295 | if (i.disp_operands |
| 7296 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
| 7297 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) |
| 7298 | i.rm.mode = 0; |
| 7299 | else |
| 7300 | { |
| 7301 | if (!fake_zero_displacement |
| 7302 | && !i.disp_operands |
| 7303 | && i.disp_encoding) |
| 7304 | { |
| 7305 | fake_zero_displacement = 1; |
| 7306 | if (i.disp_encoding == disp_encoding_8bit) |
| 7307 | i.types[op].bitfield.disp8 = 1; |
| 7308 | else |
| 7309 | i.types[op].bitfield.disp32 = 1; |
| 7310 | } |
| 7311 | i.rm.mode = mode_from_disp_size (i.types[op]); |
| 7312 | } |
| 7313 | } |
| 7314 | |
| 7315 | if (fake_zero_displacement) |
| 7316 | { |
| 7317 | /* Fakes a zero displacement assuming that i.types[op] |
| 7318 | holds the correct displacement size. */ |
| 7319 | expressionS *exp; |
| 7320 | |
| 7321 | gas_assert (i.op[op].disps == 0); |
| 7322 | exp = &disp_expressions[i.disp_operands++]; |
| 7323 | i.op[op].disps = exp; |
| 7324 | exp->X_op = O_constant; |
| 7325 | exp->X_add_number = 0; |
| 7326 | exp->X_add_symbol = (symbolS *) 0; |
| 7327 | exp->X_op_symbol = (symbolS *) 0; |
| 7328 | } |
| 7329 | |
| 7330 | mem = op; |
| 7331 | } |
| 7332 | else |
| 7333 | mem = ~0; |
| 7334 | |
| 7335 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
| 7336 | { |
| 7337 | if (operand_type_check (i.types[0], imm)) |
| 7338 | i.vex.register_specifier = NULL; |
| 7339 | else |
| 7340 | { |
| 7341 | /* VEX.vvvv encodes one of the sources when the first |
| 7342 | operand is not an immediate. */ |
| 7343 | if (i.tm.opcode_modifier.vexw == VEXW0) |
| 7344 | i.vex.register_specifier = i.op[0].regs; |
| 7345 | else |
| 7346 | i.vex.register_specifier = i.op[1].regs; |
| 7347 | } |
| 7348 | |
| 7349 | /* Destination is a XMM register encoded in the ModRM.reg |
| 7350 | and VEX.R bit. */ |
| 7351 | i.rm.reg = i.op[2].regs->reg_num; |
| 7352 | if ((i.op[2].regs->reg_flags & RegRex) != 0) |
| 7353 | i.rex |= REX_R; |
| 7354 | |
| 7355 | /* ModRM.rm and VEX.B encodes the other source. */ |
| 7356 | if (!i.mem_operands) |
| 7357 | { |
| 7358 | i.rm.mode = 3; |
| 7359 | |
| 7360 | if (i.tm.opcode_modifier.vexw == VEXW0) |
| 7361 | i.rm.regmem = i.op[1].regs->reg_num; |
| 7362 | else |
| 7363 | i.rm.regmem = i.op[0].regs->reg_num; |
| 7364 | |
| 7365 | if ((i.op[1].regs->reg_flags & RegRex) != 0) |
| 7366 | i.rex |= REX_B; |
| 7367 | } |
| 7368 | } |
| 7369 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
| 7370 | { |
| 7371 | i.vex.register_specifier = i.op[2].regs; |
| 7372 | if (!i.mem_operands) |
| 7373 | { |
| 7374 | i.rm.mode = 3; |
| 7375 | i.rm.regmem = i.op[1].regs->reg_num; |
| 7376 | if ((i.op[1].regs->reg_flags & RegRex) != 0) |
| 7377 | i.rex |= REX_B; |
| 7378 | } |
| 7379 | } |
| 7380 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
| 7381 | (if any) based on i.tm.extension_opcode. Again, we must be |
| 7382 | careful to make sure that segment/control/debug/test/MMX |
| 7383 | registers are coded into the i.rm.reg field. */ |
| 7384 | else if (i.reg_operands) |
| 7385 | { |
| 7386 | unsigned int op; |
| 7387 | unsigned int vex_reg = ~0; |
| 7388 | |
| 7389 | for (op = 0; op < i.operands; op++) |
| 7390 | if (i.types[op].bitfield.reg |
| 7391 | || i.types[op].bitfield.regmmx |
| 7392 | || i.types[op].bitfield.regsimd |
| 7393 | || i.types[op].bitfield.regbnd |
| 7394 | || i.types[op].bitfield.regmask |
| 7395 | || i.types[op].bitfield.sreg2 |
| 7396 | || i.types[op].bitfield.sreg3 |
| 7397 | || i.types[op].bitfield.control |
| 7398 | || i.types[op].bitfield.debug |
| 7399 | || i.types[op].bitfield.test) |
| 7400 | break; |
| 7401 | |
| 7402 | if (vex_3_sources) |
| 7403 | op = dest; |
| 7404 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
| 7405 | { |
| 7406 | /* For instructions with VexNDS, the register-only |
| 7407 | source operand is encoded in VEX prefix. */ |
| 7408 | gas_assert (mem != (unsigned int) ~0); |
| 7409 | |
| 7410 | if (op > mem) |
| 7411 | { |
| 7412 | vex_reg = op++; |
| 7413 | gas_assert (op < i.operands); |
| 7414 | } |
| 7415 | else |
| 7416 | { |
| 7417 | /* Check register-only source operand when two source |
| 7418 | operands are swapped. */ |
| 7419 | if (!i.tm.operand_types[op].bitfield.baseindex |
| 7420 | && i.tm.operand_types[op + 1].bitfield.baseindex) |
| 7421 | { |
| 7422 | vex_reg = op; |
| 7423 | op += 2; |
| 7424 | gas_assert (mem == (vex_reg + 1) |
| 7425 | && op < i.operands); |
| 7426 | } |
| 7427 | else |
| 7428 | { |
| 7429 | vex_reg = op + 1; |
| 7430 | gas_assert (vex_reg < i.operands); |
| 7431 | } |
| 7432 | } |
| 7433 | } |
| 7434 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
| 7435 | { |
| 7436 | /* For instructions with VexNDD, the register destination |
| 7437 | is encoded in VEX prefix. */ |
| 7438 | if (i.mem_operands == 0) |
| 7439 | { |
| 7440 | /* There is no memory operand. */ |
| 7441 | gas_assert ((op + 2) == i.operands); |
| 7442 | vex_reg = op + 1; |
| 7443 | } |
| 7444 | else |
| 7445 | { |
| 7446 | /* There are only 2 non-immediate operands. */ |
| 7447 | gas_assert (op < i.imm_operands + 2 |
| 7448 | && i.operands == i.imm_operands + 2); |
| 7449 | vex_reg = i.imm_operands + 1; |
| 7450 | } |
| 7451 | } |
| 7452 | else |
| 7453 | gas_assert (op < i.operands); |
| 7454 | |
| 7455 | if (vex_reg != (unsigned int) ~0) |
| 7456 | { |
| 7457 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
| 7458 | |
| 7459 | if ((!type->bitfield.reg |
| 7460 | || (!type->bitfield.dword && !type->bitfield.qword)) |
| 7461 | && !type->bitfield.regsimd |
| 7462 | && !operand_type_equal (type, ®mask)) |
| 7463 | abort (); |
| 7464 | |
| 7465 | i.vex.register_specifier = i.op[vex_reg].regs; |
| 7466 | } |
| 7467 | |
| 7468 | /* Don't set OP operand twice. */ |
| 7469 | if (vex_reg != op) |
| 7470 | { |
| 7471 | /* If there is an extension opcode to put here, the |
| 7472 | register number must be put into the regmem field. */ |
| 7473 | if (i.tm.extension_opcode != None) |
| 7474 | { |
| 7475 | i.rm.regmem = i.op[op].regs->reg_num; |
| 7476 | if ((i.op[op].regs->reg_flags & RegRex) != 0) |
| 7477 | i.rex |= REX_B; |
| 7478 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
| 7479 | i.vrex |= REX_B; |
| 7480 | } |
| 7481 | else |
| 7482 | { |
| 7483 | i.rm.reg = i.op[op].regs->reg_num; |
| 7484 | if ((i.op[op].regs->reg_flags & RegRex) != 0) |
| 7485 | i.rex |= REX_R; |
| 7486 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
| 7487 | i.vrex |= REX_R; |
| 7488 | } |
| 7489 | } |
| 7490 | |
| 7491 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
| 7492 | must set it to 3 to indicate this is a register operand |
| 7493 | in the regmem field. */ |
| 7494 | if (!i.mem_operands) |
| 7495 | i.rm.mode = 3; |
| 7496 | } |
| 7497 | |
| 7498 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
| 7499 | if (i.tm.extension_opcode != None) |
| 7500 | i.rm.reg = i.tm.extension_opcode; |
| 7501 | } |
| 7502 | return default_seg; |
| 7503 | } |
| 7504 | |
| 7505 | static void |
| 7506 | output_branch (void) |
| 7507 | { |
| 7508 | char *p; |
| 7509 | int size; |
| 7510 | int code16; |
| 7511 | int prefix; |
| 7512 | relax_substateT subtype; |
| 7513 | symbolS *sym; |
| 7514 | offsetT off; |
| 7515 | |
| 7516 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
| 7517 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
| 7518 | |
| 7519 | prefix = 0; |
| 7520 | if (i.prefix[DATA_PREFIX] != 0) |
| 7521 | { |
| 7522 | prefix = 1; |
| 7523 | i.prefixes -= 1; |
| 7524 | code16 ^= CODE16; |
| 7525 | } |
| 7526 | /* Pentium4 branch hints. */ |
| 7527 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ |
| 7528 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) |
| 7529 | { |
| 7530 | prefix++; |
| 7531 | i.prefixes--; |
| 7532 | } |
| 7533 | if (i.prefix[REX_PREFIX] != 0) |
| 7534 | { |
| 7535 | prefix++; |
| 7536 | i.prefixes--; |
| 7537 | } |
| 7538 | |
| 7539 | /* BND prefixed jump. */ |
| 7540 | if (i.prefix[BND_PREFIX] != 0) |
| 7541 | { |
| 7542 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); |
| 7543 | i.prefixes -= 1; |
| 7544 | } |
| 7545 | |
| 7546 | if (i.prefixes != 0 && !intel_syntax) |
| 7547 | as_warn (_("skipping prefixes on this instruction")); |
| 7548 | |
| 7549 | /* It's always a symbol; End frag & setup for relax. |
| 7550 | Make sure there is enough room in this frag for the largest |
| 7551 | instruction we may generate in md_convert_frag. This is 2 |
| 7552 | bytes for the opcode and room for the prefix and largest |
| 7553 | displacement. */ |
| 7554 | frag_grow (prefix + 2 + 4); |
| 7555 | /* Prefix and 1 opcode byte go in fr_fix. */ |
| 7556 | p = frag_more (prefix + 1); |
| 7557 | if (i.prefix[DATA_PREFIX] != 0) |
| 7558 | *p++ = DATA_PREFIX_OPCODE; |
| 7559 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE |
| 7560 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) |
| 7561 | *p++ = i.prefix[SEG_PREFIX]; |
| 7562 | if (i.prefix[REX_PREFIX] != 0) |
| 7563 | *p++ = i.prefix[REX_PREFIX]; |
| 7564 | *p = i.tm.base_opcode; |
| 7565 | |
| 7566 | if ((unsigned char) *p == JUMP_PC_RELATIVE) |
| 7567 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
| 7568 | else if (cpu_arch_flags.bitfield.cpui386) |
| 7569 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
| 7570 | else |
| 7571 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
| 7572 | subtype |= code16; |
| 7573 | |
| 7574 | sym = i.op[0].disps->X_add_symbol; |
| 7575 | off = i.op[0].disps->X_add_number; |
| 7576 | |
| 7577 | if (i.op[0].disps->X_op != O_constant |
| 7578 | && i.op[0].disps->X_op != O_symbol) |
| 7579 | { |
| 7580 | /* Handle complex expressions. */ |
| 7581 | sym = make_expr_symbol (i.op[0].disps); |
| 7582 | off = 0; |
| 7583 | } |
| 7584 | |
| 7585 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
| 7586 | Pass reloc in fr_var. */ |
| 7587 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
| 7588 | } |
| 7589 | |
| 7590 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 7591 | /* Return TRUE iff PLT32 relocation should be used for branching to |
| 7592 | symbol S. */ |
| 7593 | |
| 7594 | static bfd_boolean |
| 7595 | need_plt32_p (symbolS *s) |
| 7596 | { |
| 7597 | /* PLT32 relocation is ELF only. */ |
| 7598 | if (!IS_ELF) |
| 7599 | return FALSE; |
| 7600 | |
| 7601 | /* Since there is no need to prepare for PLT branch on x86-64, we |
| 7602 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can |
| 7603 | be used as a marker for 32-bit PC-relative branches. */ |
| 7604 | if (!object_64bit) |
| 7605 | return FALSE; |
| 7606 | |
| 7607 | /* Weak or undefined symbol need PLT32 relocation. */ |
| 7608 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) |
| 7609 | return TRUE; |
| 7610 | |
| 7611 | /* Non-global symbol doesn't need PLT32 relocation. */ |
| 7612 | if (! S_IS_EXTERNAL (s)) |
| 7613 | return FALSE; |
| 7614 | |
| 7615 | /* Other global symbols need PLT32 relocation. NB: Symbol with |
| 7616 | non-default visibilities are treated as normal global symbol |
| 7617 | so that PLT32 relocation can be used as a marker for 32-bit |
| 7618 | PC-relative branches. It is useful for linker relaxation. */ |
| 7619 | return TRUE; |
| 7620 | } |
| 7621 | #endif |
| 7622 | |
| 7623 | static void |
| 7624 | output_jump (void) |
| 7625 | { |
| 7626 | char *p; |
| 7627 | int size; |
| 7628 | fixS *fixP; |
| 7629 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
| 7630 | |
| 7631 | if (i.tm.opcode_modifier.jumpbyte) |
| 7632 | { |
| 7633 | /* This is a loop or jecxz type instruction. */ |
| 7634 | size = 1; |
| 7635 | if (i.prefix[ADDR_PREFIX] != 0) |
| 7636 | { |
| 7637 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
| 7638 | i.prefixes -= 1; |
| 7639 | } |
| 7640 | /* Pentium4 branch hints. */ |
| 7641 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ |
| 7642 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) |
| 7643 | { |
| 7644 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); |
| 7645 | i.prefixes--; |
| 7646 | } |
| 7647 | } |
| 7648 | else |
| 7649 | { |
| 7650 | int code16; |
| 7651 | |
| 7652 | code16 = 0; |
| 7653 | if (flag_code == CODE_16BIT) |
| 7654 | code16 = CODE16; |
| 7655 | |
| 7656 | if (i.prefix[DATA_PREFIX] != 0) |
| 7657 | { |
| 7658 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); |
| 7659 | i.prefixes -= 1; |
| 7660 | code16 ^= CODE16; |
| 7661 | } |
| 7662 | |
| 7663 | size = 4; |
| 7664 | if (code16) |
| 7665 | size = 2; |
| 7666 | } |
| 7667 | |
| 7668 | if (i.prefix[REX_PREFIX] != 0) |
| 7669 | { |
| 7670 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); |
| 7671 | i.prefixes -= 1; |
| 7672 | } |
| 7673 | |
| 7674 | /* BND prefixed jump. */ |
| 7675 | if (i.prefix[BND_PREFIX] != 0) |
| 7676 | { |
| 7677 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); |
| 7678 | i.prefixes -= 1; |
| 7679 | } |
| 7680 | |
| 7681 | if (i.prefixes != 0 && !intel_syntax) |
| 7682 | as_warn (_("skipping prefixes on this instruction")); |
| 7683 | |
| 7684 | p = frag_more (i.tm.opcode_length + size); |
| 7685 | switch (i.tm.opcode_length) |
| 7686 | { |
| 7687 | case 2: |
| 7688 | *p++ = i.tm.base_opcode >> 8; |
| 7689 | /* Fall through. */ |
| 7690 | case 1: |
| 7691 | *p++ = i.tm.base_opcode; |
| 7692 | break; |
| 7693 | default: |
| 7694 | abort (); |
| 7695 | } |
| 7696 | |
| 7697 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 7698 | if (size == 4 |
| 7699 | && jump_reloc == NO_RELOC |
| 7700 | && need_plt32_p (i.op[0].disps->X_add_symbol)) |
| 7701 | jump_reloc = BFD_RELOC_X86_64_PLT32; |
| 7702 | #endif |
| 7703 | |
| 7704 | jump_reloc = reloc (size, 1, 1, jump_reloc); |
| 7705 | |
| 7706 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 7707 | i.op[0].disps, 1, jump_reloc); |
| 7708 | |
| 7709 | /* All jumps handled here are signed, but don't use a signed limit |
| 7710 | check for 32 and 16 bit jumps as we want to allow wrap around at |
| 7711 | 4G and 64k respectively. */ |
| 7712 | if (size == 1) |
| 7713 | fixP->fx_signed = 1; |
| 7714 | } |
| 7715 | |
| 7716 | static void |
| 7717 | output_interseg_jump (void) |
| 7718 | { |
| 7719 | char *p; |
| 7720 | int size; |
| 7721 | int prefix; |
| 7722 | int code16; |
| 7723 | |
| 7724 | code16 = 0; |
| 7725 | if (flag_code == CODE_16BIT) |
| 7726 | code16 = CODE16; |
| 7727 | |
| 7728 | prefix = 0; |
| 7729 | if (i.prefix[DATA_PREFIX] != 0) |
| 7730 | { |
| 7731 | prefix = 1; |
| 7732 | i.prefixes -= 1; |
| 7733 | code16 ^= CODE16; |
| 7734 | } |
| 7735 | if (i.prefix[REX_PREFIX] != 0) |
| 7736 | { |
| 7737 | prefix++; |
| 7738 | i.prefixes -= 1; |
| 7739 | } |
| 7740 | |
| 7741 | size = 4; |
| 7742 | if (code16) |
| 7743 | size = 2; |
| 7744 | |
| 7745 | if (i.prefixes != 0 && !intel_syntax) |
| 7746 | as_warn (_("skipping prefixes on this instruction")); |
| 7747 | |
| 7748 | /* 1 opcode; 2 segment; offset */ |
| 7749 | p = frag_more (prefix + 1 + 2 + size); |
| 7750 | |
| 7751 | if (i.prefix[DATA_PREFIX] != 0) |
| 7752 | *p++ = DATA_PREFIX_OPCODE; |
| 7753 | |
| 7754 | if (i.prefix[REX_PREFIX] != 0) |
| 7755 | *p++ = i.prefix[REX_PREFIX]; |
| 7756 | |
| 7757 | *p++ = i.tm.base_opcode; |
| 7758 | if (i.op[1].imms->X_op == O_constant) |
| 7759 | { |
| 7760 | offsetT n = i.op[1].imms->X_add_number; |
| 7761 | |
| 7762 | if (size == 2 |
| 7763 | && !fits_in_unsigned_word (n) |
| 7764 | && !fits_in_signed_word (n)) |
| 7765 | { |
| 7766 | as_bad (_("16-bit jump out of range")); |
| 7767 | return; |
| 7768 | } |
| 7769 | md_number_to_chars (p, n, size); |
| 7770 | } |
| 7771 | else |
| 7772 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 7773 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
| 7774 | if (i.op[0].imms->X_op != O_constant) |
| 7775 | as_bad (_("can't handle non absolute segment in `%s'"), |
| 7776 | i.tm.name); |
| 7777 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
| 7778 | } |
| 7779 | |
| 7780 | static void |
| 7781 | output_insn (void) |
| 7782 | { |
| 7783 | fragS *insn_start_frag; |
| 7784 | offsetT insn_start_off; |
| 7785 | |
| 7786 | /* Tie dwarf2 debug info to the address at the start of the insn. |
| 7787 | We can't do this after the insn has been output as the current |
| 7788 | frag may have been closed off. eg. by frag_var. */ |
| 7789 | dwarf2_emit_insn (0); |
| 7790 | |
| 7791 | insn_start_frag = frag_now; |
| 7792 | insn_start_off = frag_now_fix (); |
| 7793 | |
| 7794 | /* Output jumps. */ |
| 7795 | if (i.tm.opcode_modifier.jump) |
| 7796 | output_branch (); |
| 7797 | else if (i.tm.opcode_modifier.jumpbyte |
| 7798 | || i.tm.opcode_modifier.jumpdword) |
| 7799 | output_jump (); |
| 7800 | else if (i.tm.opcode_modifier.jumpintersegment) |
| 7801 | output_interseg_jump (); |
| 7802 | else |
| 7803 | { |
| 7804 | /* Output normal instructions here. */ |
| 7805 | char *p; |
| 7806 | unsigned char *q; |
| 7807 | unsigned int j; |
| 7808 | unsigned int prefix; |
| 7809 | |
| 7810 | if (avoid_fence |
| 7811 | && i.tm.base_opcode == 0xfae |
| 7812 | && i.operands == 1 |
| 7813 | && i.imm_operands == 1 |
| 7814 | && (i.op[0].imms->X_add_number == 0xe8 |
| 7815 | || i.op[0].imms->X_add_number == 0xf0 |
| 7816 | || i.op[0].imms->X_add_number == 0xf8)) |
| 7817 | { |
| 7818 | /* Encode lfence, mfence, and sfence as |
| 7819 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ |
| 7820 | offsetT val = 0x240483f0ULL; |
| 7821 | p = frag_more (5); |
| 7822 | md_number_to_chars (p, val, 5); |
| 7823 | return; |
| 7824 | } |
| 7825 | |
| 7826 | /* Some processors fail on LOCK prefix. This options makes |
| 7827 | assembler ignore LOCK prefix and serves as a workaround. */ |
| 7828 | if (omit_lock_prefix) |
| 7829 | { |
| 7830 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) |
| 7831 | return; |
| 7832 | i.prefix[LOCK_PREFIX] = 0; |
| 7833 | } |
| 7834 | |
| 7835 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
| 7836 | don't need the explicit prefix. */ |
| 7837 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) |
| 7838 | { |
| 7839 | switch (i.tm.opcode_length) |
| 7840 | { |
| 7841 | case 3: |
| 7842 | if (i.tm.base_opcode & 0xff000000) |
| 7843 | { |
| 7844 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
| 7845 | add_prefix (prefix); |
| 7846 | } |
| 7847 | break; |
| 7848 | case 2: |
| 7849 | if ((i.tm.base_opcode & 0xff0000) != 0) |
| 7850 | { |
| 7851 | prefix = (i.tm.base_opcode >> 16) & 0xff; |
| 7852 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
| 7853 | || prefix != REPE_PREFIX_OPCODE |
| 7854 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) |
| 7855 | add_prefix (prefix); |
| 7856 | } |
| 7857 | break; |
| 7858 | case 1: |
| 7859 | break; |
| 7860 | case 0: |
| 7861 | /* Check for pseudo prefixes. */ |
| 7862 | as_bad_where (insn_start_frag->fr_file, |
| 7863 | insn_start_frag->fr_line, |
| 7864 | _("pseudo prefix without instruction")); |
| 7865 | return; |
| 7866 | default: |
| 7867 | abort (); |
| 7868 | } |
| 7869 | |
| 7870 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
| 7871 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
| 7872 | R_X86_64_GOTTPOFF relocation so that linker can safely |
| 7873 | perform IE->LE optimization. */ |
| 7874 | if (x86_elf_abi == X86_64_X32_ABI |
| 7875 | && i.operands == 2 |
| 7876 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
| 7877 | && i.prefix[REX_PREFIX] == 0) |
| 7878 | add_prefix (REX_OPCODE); |
| 7879 | #endif |
| 7880 | |
| 7881 | /* The prefix bytes. */ |
| 7882 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) |
| 7883 | if (*q) |
| 7884 | FRAG_APPEND_1_CHAR (*q); |
| 7885 | } |
| 7886 | else |
| 7887 | { |
| 7888 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) |
| 7889 | if (*q) |
| 7890 | switch (j) |
| 7891 | { |
| 7892 | case REX_PREFIX: |
| 7893 | /* REX byte is encoded in VEX prefix. */ |
| 7894 | break; |
| 7895 | case SEG_PREFIX: |
| 7896 | case ADDR_PREFIX: |
| 7897 | FRAG_APPEND_1_CHAR (*q); |
| 7898 | break; |
| 7899 | default: |
| 7900 | /* There should be no other prefixes for instructions |
| 7901 | with VEX prefix. */ |
| 7902 | abort (); |
| 7903 | } |
| 7904 | |
| 7905 | /* For EVEX instructions i.vrex should become 0 after |
| 7906 | build_evex_prefix. For VEX instructions upper 16 registers |
| 7907 | aren't available, so VREX should be 0. */ |
| 7908 | if (i.vrex) |
| 7909 | abort (); |
| 7910 | /* Now the VEX prefix. */ |
| 7911 | p = frag_more (i.vex.length); |
| 7912 | for (j = 0; j < i.vex.length; j++) |
| 7913 | p[j] = i.vex.bytes[j]; |
| 7914 | } |
| 7915 | |
| 7916 | /* Now the opcode; be careful about word order here! */ |
| 7917 | if (i.tm.opcode_length == 1) |
| 7918 | { |
| 7919 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
| 7920 | } |
| 7921 | else |
| 7922 | { |
| 7923 | switch (i.tm.opcode_length) |
| 7924 | { |
| 7925 | case 4: |
| 7926 | p = frag_more (4); |
| 7927 | *p++ = (i.tm.base_opcode >> 24) & 0xff; |
| 7928 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
| 7929 | break; |
| 7930 | case 3: |
| 7931 | p = frag_more (3); |
| 7932 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
| 7933 | break; |
| 7934 | case 2: |
| 7935 | p = frag_more (2); |
| 7936 | break; |
| 7937 | default: |
| 7938 | abort (); |
| 7939 | break; |
| 7940 | } |
| 7941 | |
| 7942 | /* Put out high byte first: can't use md_number_to_chars! */ |
| 7943 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
| 7944 | *p = i.tm.base_opcode & 0xff; |
| 7945 | } |
| 7946 | |
| 7947 | /* Now the modrm byte and sib byte (if present). */ |
| 7948 | if (i.tm.opcode_modifier.modrm) |
| 7949 | { |
| 7950 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
| 7951 | | i.rm.reg << 3 |
| 7952 | | i.rm.mode << 6)); |
| 7953 | /* If i.rm.regmem == ESP (4) |
| 7954 | && i.rm.mode != (Register mode) |
| 7955 | && not 16 bit |
| 7956 | ==> need second modrm byte. */ |
| 7957 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING |
| 7958 | && i.rm.mode != 3 |
| 7959 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
| 7960 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
| 7961 | | i.sib.index << 3 |
| 7962 | | i.sib.scale << 6)); |
| 7963 | } |
| 7964 | |
| 7965 | if (i.disp_operands) |
| 7966 | output_disp (insn_start_frag, insn_start_off); |
| 7967 | |
| 7968 | if (i.imm_operands) |
| 7969 | output_imm (insn_start_frag, insn_start_off); |
| 7970 | } |
| 7971 | |
| 7972 | #ifdef DEBUG386 |
| 7973 | if (flag_debug) |
| 7974 | { |
| 7975 | pi ("" /*line*/, &i); |
| 7976 | } |
| 7977 | #endif /* DEBUG386 */ |
| 7978 | } |
| 7979 | |
| 7980 | /* Return the size of the displacement operand N. */ |
| 7981 | |
| 7982 | static int |
| 7983 | disp_size (unsigned int n) |
| 7984 | { |
| 7985 | int size = 4; |
| 7986 | |
| 7987 | if (i.types[n].bitfield.disp64) |
| 7988 | size = 8; |
| 7989 | else if (i.types[n].bitfield.disp8) |
| 7990 | size = 1; |
| 7991 | else if (i.types[n].bitfield.disp16) |
| 7992 | size = 2; |
| 7993 | return size; |
| 7994 | } |
| 7995 | |
| 7996 | /* Return the size of the immediate operand N. */ |
| 7997 | |
| 7998 | static int |
| 7999 | imm_size (unsigned int n) |
| 8000 | { |
| 8001 | int size = 4; |
| 8002 | if (i.types[n].bitfield.imm64) |
| 8003 | size = 8; |
| 8004 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) |
| 8005 | size = 1; |
| 8006 | else if (i.types[n].bitfield.imm16) |
| 8007 | size = 2; |
| 8008 | return size; |
| 8009 | } |
| 8010 | |
| 8011 | static void |
| 8012 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
| 8013 | { |
| 8014 | char *p; |
| 8015 | unsigned int n; |
| 8016 | |
| 8017 | for (n = 0; n < i.operands; n++) |
| 8018 | { |
| 8019 | if (operand_type_check (i.types[n], disp)) |
| 8020 | { |
| 8021 | if (i.op[n].disps->X_op == O_constant) |
| 8022 | { |
| 8023 | int size = disp_size (n); |
| 8024 | offsetT val = i.op[n].disps->X_add_number; |
| 8025 | |
| 8026 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
| 8027 | size); |
| 8028 | p = frag_more (size); |
| 8029 | md_number_to_chars (p, val, size); |
| 8030 | } |
| 8031 | else |
| 8032 | { |
| 8033 | enum bfd_reloc_code_real reloc_type; |
| 8034 | int size = disp_size (n); |
| 8035 | int sign = i.types[n].bitfield.disp32s; |
| 8036 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
| 8037 | fixS *fixP; |
| 8038 | |
| 8039 | /* We can't have 8 bit displacement here. */ |
| 8040 | gas_assert (!i.types[n].bitfield.disp8); |
| 8041 | |
| 8042 | /* The PC relative address is computed relative |
| 8043 | to the instruction boundary, so in case immediate |
| 8044 | fields follows, we need to adjust the value. */ |
| 8045 | if (pcrel && i.imm_operands) |
| 8046 | { |
| 8047 | unsigned int n1; |
| 8048 | int sz = 0; |
| 8049 | |
| 8050 | for (n1 = 0; n1 < i.operands; n1++) |
| 8051 | if (operand_type_check (i.types[n1], imm)) |
| 8052 | { |
| 8053 | /* Only one immediate is allowed for PC |
| 8054 | relative address. */ |
| 8055 | gas_assert (sz == 0); |
| 8056 | sz = imm_size (n1); |
| 8057 | i.op[n].disps->X_add_number -= sz; |
| 8058 | } |
| 8059 | /* We should find the immediate. */ |
| 8060 | gas_assert (sz != 0); |
| 8061 | } |
| 8062 | |
| 8063 | p = frag_more (size); |
| 8064 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
| 8065 | if (GOT_symbol |
| 8066 | && GOT_symbol == i.op[n].disps->X_add_symbol |
| 8067 | && (((reloc_type == BFD_RELOC_32 |
| 8068 | || reloc_type == BFD_RELOC_X86_64_32S |
| 8069 | || (reloc_type == BFD_RELOC_64 |
| 8070 | && object_64bit)) |
| 8071 | && (i.op[n].disps->X_op == O_symbol |
| 8072 | || (i.op[n].disps->X_op == O_add |
| 8073 | && ((symbol_get_value_expression |
| 8074 | (i.op[n].disps->X_op_symbol)->X_op) |
| 8075 | == O_subtract)))) |
| 8076 | || reloc_type == BFD_RELOC_32_PCREL)) |
| 8077 | { |
| 8078 | offsetT add; |
| 8079 | |
| 8080 | if (insn_start_frag == frag_now) |
| 8081 | add = (p - frag_now->fr_literal) - insn_start_off; |
| 8082 | else |
| 8083 | { |
| 8084 | fragS *fr; |
| 8085 | |
| 8086 | add = insn_start_frag->fr_fix - insn_start_off; |
| 8087 | for (fr = insn_start_frag->fr_next; |
| 8088 | fr && fr != frag_now; fr = fr->fr_next) |
| 8089 | add += fr->fr_fix; |
| 8090 | add += p - frag_now->fr_literal; |
| 8091 | } |
| 8092 | |
| 8093 | if (!object_64bit) |
| 8094 | { |
| 8095 | reloc_type = BFD_RELOC_386_GOTPC; |
| 8096 | i.op[n].imms->X_add_number += add; |
| 8097 | } |
| 8098 | else if (reloc_type == BFD_RELOC_64) |
| 8099 | reloc_type = BFD_RELOC_X86_64_GOTPC64; |
| 8100 | else |
| 8101 | /* Don't do the adjustment for x86-64, as there |
| 8102 | the pcrel addressing is relative to the _next_ |
| 8103 | insn, and that is taken care of in other code. */ |
| 8104 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
| 8105 | } |
| 8106 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
| 8107 | size, i.op[n].disps, pcrel, |
| 8108 | reloc_type); |
| 8109 | /* Check for "call/jmp *mem", "mov mem, %reg", |
| 8110 | "test %reg, mem" and "binop mem, %reg" where binop |
| 8111 | is one of adc, add, and, cmp, or, sbb, sub, xor |
| 8112 | instructions. Always generate R_386_GOT32X for |
| 8113 | "sym*GOT" operand in 32-bit mode. */ |
| 8114 | if ((generate_relax_relocations |
| 8115 | || (!object_64bit |
| 8116 | && i.rm.mode == 0 |
| 8117 | && i.rm.regmem == 5)) |
| 8118 | && (i.rm.mode == 2 |
| 8119 | || (i.rm.mode == 0 && i.rm.regmem == 5)) |
| 8120 | && ((i.operands == 1 |
| 8121 | && i.tm.base_opcode == 0xff |
| 8122 | && (i.rm.reg == 2 || i.rm.reg == 4)) |
| 8123 | || (i.operands == 2 |
| 8124 | && (i.tm.base_opcode == 0x8b |
| 8125 | || i.tm.base_opcode == 0x85 |
| 8126 | || (i.tm.base_opcode & 0xc7) == 0x03)))) |
| 8127 | { |
| 8128 | if (object_64bit) |
| 8129 | { |
| 8130 | fixP->fx_tcbit = i.rex != 0; |
| 8131 | if (i.base_reg |
| 8132 | && (i.base_reg->reg_num == RegIP)) |
| 8133 | fixP->fx_tcbit2 = 1; |
| 8134 | } |
| 8135 | else |
| 8136 | fixP->fx_tcbit2 = 1; |
| 8137 | } |
| 8138 | } |
| 8139 | } |
| 8140 | } |
| 8141 | } |
| 8142 | |
| 8143 | static void |
| 8144 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
| 8145 | { |
| 8146 | char *p; |
| 8147 | unsigned int n; |
| 8148 | |
| 8149 | for (n = 0; n < i.operands; n++) |
| 8150 | { |
| 8151 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
| 8152 | if (i.rounding && (int) n == i.rounding->operand) |
| 8153 | continue; |
| 8154 | |
| 8155 | if (operand_type_check (i.types[n], imm)) |
| 8156 | { |
| 8157 | if (i.op[n].imms->X_op == O_constant) |
| 8158 | { |
| 8159 | int size = imm_size (n); |
| 8160 | offsetT val; |
| 8161 | |
| 8162 | val = offset_in_range (i.op[n].imms->X_add_number, |
| 8163 | size); |
| 8164 | p = frag_more (size); |
| 8165 | md_number_to_chars (p, val, size); |
| 8166 | } |
| 8167 | else |
| 8168 | { |
| 8169 | /* Not absolute_section. |
| 8170 | Need a 32-bit fixup (don't support 8bit |
| 8171 | non-absolute imms). Try to support other |
| 8172 | sizes ... */ |
| 8173 | enum bfd_reloc_code_real reloc_type; |
| 8174 | int size = imm_size (n); |
| 8175 | int sign; |
| 8176 | |
| 8177 | if (i.types[n].bitfield.imm32s |
| 8178 | && (i.suffix == QWORD_MNEM_SUFFIX |
| 8179 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
| 8180 | sign = 1; |
| 8181 | else |
| 8182 | sign = 0; |
| 8183 | |
| 8184 | p = frag_more (size); |
| 8185 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
| 8186 | |
| 8187 | /* This is tough to explain. We end up with this one if we |
| 8188 | * have operands that look like |
| 8189 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to |
| 8190 | * obtain the absolute address of the GOT, and it is strongly |
| 8191 | * preferable from a performance point of view to avoid using |
| 8192 | * a runtime relocation for this. The actual sequence of |
| 8193 | * instructions often look something like: |
| 8194 | * |
| 8195 | * call .L66 |
| 8196 | * .L66: |
| 8197 | * popl %ebx |
| 8198 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx |
| 8199 | * |
| 8200 | * The call and pop essentially return the absolute address |
| 8201 | * of the label .L66 and store it in %ebx. The linker itself |
| 8202 | * will ultimately change the first operand of the addl so |
| 8203 | * that %ebx points to the GOT, but to keep things simple, the |
| 8204 | * .o file must have this operand set so that it generates not |
| 8205 | * the absolute address of .L66, but the absolute address of |
| 8206 | * itself. This allows the linker itself simply treat a GOTPC |
| 8207 | * relocation as asking for a pcrel offset to the GOT to be |
| 8208 | * added in, and the addend of the relocation is stored in the |
| 8209 | * operand field for the instruction itself. |
| 8210 | * |
| 8211 | * Our job here is to fix the operand so that it would add |
| 8212 | * the correct offset so that %ebx would point to itself. The |
| 8213 | * thing that is tricky is that .-.L66 will point to the |
| 8214 | * beginning of the instruction, so we need to further modify |
| 8215 | * the operand so that it will point to itself. There are |
| 8216 | * other cases where you have something like: |
| 8217 | * |
| 8218 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
| 8219 | * |
| 8220 | * and here no correction would be required. Internally in |
| 8221 | * the assembler we treat operands of this form as not being |
| 8222 | * pcrel since the '.' is explicitly mentioned, and I wonder |
| 8223 | * whether it would simplify matters to do it this way. Who |
| 8224 | * knows. In earlier versions of the PIC patches, the |
| 8225 | * pcrel_adjust field was used to store the correction, but |
| 8226 | * since the expression is not pcrel, I felt it would be |
| 8227 | * confusing to do it this way. */ |
| 8228 | |
| 8229 | if ((reloc_type == BFD_RELOC_32 |
| 8230 | || reloc_type == BFD_RELOC_X86_64_32S |
| 8231 | || reloc_type == BFD_RELOC_64) |
| 8232 | && GOT_symbol |
| 8233 | && GOT_symbol == i.op[n].imms->X_add_symbol |
| 8234 | && (i.op[n].imms->X_op == O_symbol |
| 8235 | || (i.op[n].imms->X_op == O_add |
| 8236 | && ((symbol_get_value_expression |
| 8237 | (i.op[n].imms->X_op_symbol)->X_op) |
| 8238 | == O_subtract)))) |
| 8239 | { |
| 8240 | offsetT add; |
| 8241 | |
| 8242 | if (insn_start_frag == frag_now) |
| 8243 | add = (p - frag_now->fr_literal) - insn_start_off; |
| 8244 | else |
| 8245 | { |
| 8246 | fragS *fr; |
| 8247 | |
| 8248 | add = insn_start_frag->fr_fix - insn_start_off; |
| 8249 | for (fr = insn_start_frag->fr_next; |
| 8250 | fr && fr != frag_now; fr = fr->fr_next) |
| 8251 | add += fr->fr_fix; |
| 8252 | add += p - frag_now->fr_literal; |
| 8253 | } |
| 8254 | |
| 8255 | if (!object_64bit) |
| 8256 | reloc_type = BFD_RELOC_386_GOTPC; |
| 8257 | else if (size == 4) |
| 8258 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
| 8259 | else if (size == 8) |
| 8260 | reloc_type = BFD_RELOC_X86_64_GOTPC64; |
| 8261 | i.op[n].imms->X_add_number += add; |
| 8262 | } |
| 8263 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
| 8264 | i.op[n].imms, 0, reloc_type); |
| 8265 | } |
| 8266 | } |
| 8267 | } |
| 8268 | } |
| 8269 | \f |
| 8270 | /* x86_cons_fix_new is called via the expression parsing code when a |
| 8271 | reloc is needed. We use this hook to get the correct .got reloc. */ |
| 8272 | static int cons_sign = -1; |
| 8273 | |
| 8274 | void |
| 8275 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
| 8276 | expressionS *exp, bfd_reloc_code_real_type r) |
| 8277 | { |
| 8278 | r = reloc (len, 0, cons_sign, r); |
| 8279 | |
| 8280 | #ifdef TE_PE |
| 8281 | if (exp->X_op == O_secrel) |
| 8282 | { |
| 8283 | exp->X_op = O_symbol; |
| 8284 | r = BFD_RELOC_32_SECREL; |
| 8285 | } |
| 8286 | #endif |
| 8287 | |
| 8288 | fix_new_exp (frag, off, len, exp, 0, r); |
| 8289 | } |
| 8290 | |
| 8291 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
| 8292 | purpose of the `.dc.a' internal pseudo-op. */ |
| 8293 | |
| 8294 | int |
| 8295 | x86_address_bytes (void) |
| 8296 | { |
| 8297 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) |
| 8298 | return 4; |
| 8299 | return stdoutput->arch_info->bits_per_address / 8; |
| 8300 | } |
| 8301 | |
| 8302 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
| 8303 | || defined (LEX_AT) |
| 8304 | # define lex_got(reloc, adjust, types) NULL |
| 8305 | #else |
| 8306 | /* Parse operands of the form |
| 8307 | <symbol>@GOTOFF+<nnn> |
| 8308 | and similar .plt or .got references. |
| 8309 | |
| 8310 | If we find one, set up the correct relocation in RELOC and copy the |
| 8311 | input string, minus the `@GOTOFF' into a malloc'd buffer for |
| 8312 | parsing by the calling routine. Return this buffer, and if ADJUST |
| 8313 | is non-null set it to the length of the string we removed from the |
| 8314 | input line. Otherwise return NULL. */ |
| 8315 | static char * |
| 8316 | lex_got (enum bfd_reloc_code_real *rel, |
| 8317 | int *adjust, |
| 8318 | i386_operand_type *types) |
| 8319 | { |
| 8320 | /* Some of the relocations depend on the size of what field is to |
| 8321 | be relocated. But in our callers i386_immediate and i386_displacement |
| 8322 | we don't yet know the operand size (this will be set by insn |
| 8323 | matching). Hence we record the word32 relocation here, |
| 8324 | and adjust the reloc according to the real size in reloc(). */ |
| 8325 | static const struct { |
| 8326 | const char *str; |
| 8327 | int len; |
| 8328 | const enum bfd_reloc_code_real rel[2]; |
| 8329 | const i386_operand_type types64; |
| 8330 | } gotrel[] = { |
| 8331 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 8332 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
| 8333 | BFD_RELOC_SIZE32 }, |
| 8334 | OPERAND_TYPE_IMM32_64 }, |
| 8335 | #endif |
| 8336 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
| 8337 | BFD_RELOC_X86_64_PLTOFF64 }, |
| 8338 | OPERAND_TYPE_IMM64 }, |
| 8339 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
| 8340 | BFD_RELOC_X86_64_PLT32 }, |
| 8341 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 8342 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
| 8343 | BFD_RELOC_X86_64_GOTPLT64 }, |
| 8344 | OPERAND_TYPE_IMM64_DISP64 }, |
| 8345 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
| 8346 | BFD_RELOC_X86_64_GOTOFF64 }, |
| 8347 | OPERAND_TYPE_IMM64_DISP64 }, |
| 8348 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
| 8349 | BFD_RELOC_X86_64_GOTPCREL }, |
| 8350 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 8351 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
| 8352 | BFD_RELOC_X86_64_TLSGD }, |
| 8353 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 8354 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
| 8355 | _dummy_first_bfd_reloc_code_real }, |
| 8356 | OPERAND_TYPE_NONE }, |
| 8357 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
| 8358 | BFD_RELOC_X86_64_TLSLD }, |
| 8359 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 8360 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
| 8361 | BFD_RELOC_X86_64_GOTTPOFF }, |
| 8362 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 8363 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
| 8364 | BFD_RELOC_X86_64_TPOFF32 }, |
| 8365 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
| 8366 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
| 8367 | _dummy_first_bfd_reloc_code_real }, |
| 8368 | OPERAND_TYPE_NONE }, |
| 8369 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
| 8370 | BFD_RELOC_X86_64_DTPOFF32 }, |
| 8371 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
| 8372 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
| 8373 | _dummy_first_bfd_reloc_code_real }, |
| 8374 | OPERAND_TYPE_NONE }, |
| 8375 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
| 8376 | _dummy_first_bfd_reloc_code_real }, |
| 8377 | OPERAND_TYPE_NONE }, |
| 8378 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
| 8379 | BFD_RELOC_X86_64_GOT32 }, |
| 8380 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
| 8381 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
| 8382 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, |
| 8383 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 8384 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
| 8385 | BFD_RELOC_X86_64_TLSDESC_CALL }, |
| 8386 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
| 8387 | }; |
| 8388 | char *cp; |
| 8389 | unsigned int j; |
| 8390 | |
| 8391 | #if defined (OBJ_MAYBE_ELF) |
| 8392 | if (!IS_ELF) |
| 8393 | return NULL; |
| 8394 | #endif |
| 8395 | |
| 8396 | for (cp = input_line_pointer; *cp != '@'; cp++) |
| 8397 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
| 8398 | return NULL; |
| 8399 | |
| 8400 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
| 8401 | { |
| 8402 | int len = gotrel[j].len; |
| 8403 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
| 8404 | { |
| 8405 | if (gotrel[j].rel[object_64bit] != 0) |
| 8406 | { |
| 8407 | int first, second; |
| 8408 | char *tmpbuf, *past_reloc; |
| 8409 | |
| 8410 | *rel = gotrel[j].rel[object_64bit]; |
| 8411 | |
| 8412 | if (types) |
| 8413 | { |
| 8414 | if (flag_code != CODE_64BIT) |
| 8415 | { |
| 8416 | types->bitfield.imm32 = 1; |
| 8417 | types->bitfield.disp32 = 1; |
| 8418 | } |
| 8419 | else |
| 8420 | *types = gotrel[j].types64; |
| 8421 | } |
| 8422 | |
| 8423 | if (j != 0 && GOT_symbol == NULL) |
| 8424 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
| 8425 | |
| 8426 | /* The length of the first part of our input line. */ |
| 8427 | first = cp - input_line_pointer; |
| 8428 | |
| 8429 | /* The second part goes from after the reloc token until |
| 8430 | (and including) an end_of_line char or comma. */ |
| 8431 | past_reloc = cp + 1 + len; |
| 8432 | cp = past_reloc; |
| 8433 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') |
| 8434 | ++cp; |
| 8435 | second = cp + 1 - past_reloc; |
| 8436 | |
| 8437 | /* Allocate and copy string. The trailing NUL shouldn't |
| 8438 | be necessary, but be safe. */ |
| 8439 | tmpbuf = XNEWVEC (char, first + second + 2); |
| 8440 | memcpy (tmpbuf, input_line_pointer, first); |
| 8441 | if (second != 0 && *past_reloc != ' ') |
| 8442 | /* Replace the relocation token with ' ', so that |
| 8443 | errors like foo@GOTOFF1 will be detected. */ |
| 8444 | tmpbuf[first++] = ' '; |
| 8445 | else |
| 8446 | /* Increment length by 1 if the relocation token is |
| 8447 | removed. */ |
| 8448 | len++; |
| 8449 | if (adjust) |
| 8450 | *adjust = len; |
| 8451 | memcpy (tmpbuf + first, past_reloc, second); |
| 8452 | tmpbuf[first + second] = '\0'; |
| 8453 | return tmpbuf; |
| 8454 | } |
| 8455 | |
| 8456 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
| 8457 | gotrel[j].str, 1 << (5 + object_64bit)); |
| 8458 | return NULL; |
| 8459 | } |
| 8460 | } |
| 8461 | |
| 8462 | /* Might be a symbol version string. Don't as_bad here. */ |
| 8463 | return NULL; |
| 8464 | } |
| 8465 | #endif |
| 8466 | |
| 8467 | #ifdef TE_PE |
| 8468 | #ifdef lex_got |
| 8469 | #undef lex_got |
| 8470 | #endif |
| 8471 | /* Parse operands of the form |
| 8472 | <symbol>@SECREL32+<nnn> |
| 8473 | |
| 8474 | If we find one, set up the correct relocation in RELOC and copy the |
| 8475 | input string, minus the `@SECREL32' into a malloc'd buffer for |
| 8476 | parsing by the calling routine. Return this buffer, and if ADJUST |
| 8477 | is non-null set it to the length of the string we removed from the |
| 8478 | input line. Otherwise return NULL. |
| 8479 | |
| 8480 | This function is copied from the ELF version above adjusted for PE targets. */ |
| 8481 | |
| 8482 | static char * |
| 8483 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, |
| 8484 | int *adjust ATTRIBUTE_UNUSED, |
| 8485 | i386_operand_type *types) |
| 8486 | { |
| 8487 | static const struct |
| 8488 | { |
| 8489 | const char *str; |
| 8490 | int len; |
| 8491 | const enum bfd_reloc_code_real rel[2]; |
| 8492 | const i386_operand_type types64; |
| 8493 | } |
| 8494 | gotrel[] = |
| 8495 | { |
| 8496 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, |
| 8497 | BFD_RELOC_32_SECREL }, |
| 8498 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
| 8499 | }; |
| 8500 | |
| 8501 | char *cp; |
| 8502 | unsigned j; |
| 8503 | |
| 8504 | for (cp = input_line_pointer; *cp != '@'; cp++) |
| 8505 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
| 8506 | return NULL; |
| 8507 | |
| 8508 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
| 8509 | { |
| 8510 | int len = gotrel[j].len; |
| 8511 | |
| 8512 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
| 8513 | { |
| 8514 | if (gotrel[j].rel[object_64bit] != 0) |
| 8515 | { |
| 8516 | int first, second; |
| 8517 | char *tmpbuf, *past_reloc; |
| 8518 | |
| 8519 | *rel = gotrel[j].rel[object_64bit]; |
| 8520 | if (adjust) |
| 8521 | *adjust = len; |
| 8522 | |
| 8523 | if (types) |
| 8524 | { |
| 8525 | if (flag_code != CODE_64BIT) |
| 8526 | { |
| 8527 | types->bitfield.imm32 = 1; |
| 8528 | types->bitfield.disp32 = 1; |
| 8529 | } |
| 8530 | else |
| 8531 | *types = gotrel[j].types64; |
| 8532 | } |
| 8533 | |
| 8534 | /* The length of the first part of our input line. */ |
| 8535 | first = cp - input_line_pointer; |
| 8536 | |
| 8537 | /* The second part goes from after the reloc token until |
| 8538 | (and including) an end_of_line char or comma. */ |
| 8539 | past_reloc = cp + 1 + len; |
| 8540 | cp = past_reloc; |
| 8541 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') |
| 8542 | ++cp; |
| 8543 | second = cp + 1 - past_reloc; |
| 8544 | |
| 8545 | /* Allocate and copy string. The trailing NUL shouldn't |
| 8546 | be necessary, but be safe. */ |
| 8547 | tmpbuf = XNEWVEC (char, first + second + 2); |
| 8548 | memcpy (tmpbuf, input_line_pointer, first); |
| 8549 | if (second != 0 && *past_reloc != ' ') |
| 8550 | /* Replace the relocation token with ' ', so that |
| 8551 | errors like foo@SECLREL321 will be detected. */ |
| 8552 | tmpbuf[first++] = ' '; |
| 8553 | memcpy (tmpbuf + first, past_reloc, second); |
| 8554 | tmpbuf[first + second] = '\0'; |
| 8555 | return tmpbuf; |
| 8556 | } |
| 8557 | |
| 8558 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
| 8559 | gotrel[j].str, 1 << (5 + object_64bit)); |
| 8560 | return NULL; |
| 8561 | } |
| 8562 | } |
| 8563 | |
| 8564 | /* Might be a symbol version string. Don't as_bad here. */ |
| 8565 | return NULL; |
| 8566 | } |
| 8567 | |
| 8568 | #endif /* TE_PE */ |
| 8569 | |
| 8570 | bfd_reloc_code_real_type |
| 8571 | x86_cons (expressionS *exp, int size) |
| 8572 | { |
| 8573 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
| 8574 | |
| 8575 | intel_syntax = -intel_syntax; |
| 8576 | |
| 8577 | exp->X_md = 0; |
| 8578 | if (size == 4 || (object_64bit && size == 8)) |
| 8579 | { |
| 8580 | /* Handle @GOTOFF and the like in an expression. */ |
| 8581 | char *save; |
| 8582 | char *gotfree_input_line; |
| 8583 | int adjust = 0; |
| 8584 | |
| 8585 | save = input_line_pointer; |
| 8586 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
| 8587 | if (gotfree_input_line) |
| 8588 | input_line_pointer = gotfree_input_line; |
| 8589 | |
| 8590 | expression (exp); |
| 8591 | |
| 8592 | if (gotfree_input_line) |
| 8593 | { |
| 8594 | /* expression () has merrily parsed up to the end of line, |
| 8595 | or a comma - in the wrong buffer. Transfer how far |
| 8596 | input_line_pointer has moved to the right buffer. */ |
| 8597 | input_line_pointer = (save |
| 8598 | + (input_line_pointer - gotfree_input_line) |
| 8599 | + adjust); |
| 8600 | free (gotfree_input_line); |
| 8601 | if (exp->X_op == O_constant |
| 8602 | || exp->X_op == O_absent |
| 8603 | || exp->X_op == O_illegal |
| 8604 | || exp->X_op == O_register |
| 8605 | || exp->X_op == O_big) |
| 8606 | { |
| 8607 | char c = *input_line_pointer; |
| 8608 | *input_line_pointer = 0; |
| 8609 | as_bad (_("missing or invalid expression `%s'"), save); |
| 8610 | *input_line_pointer = c; |
| 8611 | } |
| 8612 | } |
| 8613 | } |
| 8614 | else |
| 8615 | expression (exp); |
| 8616 | |
| 8617 | intel_syntax = -intel_syntax; |
| 8618 | |
| 8619 | if (intel_syntax) |
| 8620 | i386_intel_simplify (exp); |
| 8621 | |
| 8622 | return got_reloc; |
| 8623 | } |
| 8624 | |
| 8625 | static void |
| 8626 | signed_cons (int size) |
| 8627 | { |
| 8628 | if (flag_code == CODE_64BIT) |
| 8629 | cons_sign = 1; |
| 8630 | cons (size); |
| 8631 | cons_sign = -1; |
| 8632 | } |
| 8633 | |
| 8634 | #ifdef TE_PE |
| 8635 | static void |
| 8636 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
| 8637 | { |
| 8638 | expressionS exp; |
| 8639 | |
| 8640 | do |
| 8641 | { |
| 8642 | expression (&exp); |
| 8643 | if (exp.X_op == O_symbol) |
| 8644 | exp.X_op = O_secrel; |
| 8645 | |
| 8646 | emit_expr (&exp, 4); |
| 8647 | } |
| 8648 | while (*input_line_pointer++ == ','); |
| 8649 | |
| 8650 | input_line_pointer--; |
| 8651 | demand_empty_rest_of_line (); |
| 8652 | } |
| 8653 | #endif |
| 8654 | |
| 8655 | /* Handle Vector operations. */ |
| 8656 | |
| 8657 | static char * |
| 8658 | check_VecOperations (char *op_string, char *op_end) |
| 8659 | { |
| 8660 | const reg_entry *mask; |
| 8661 | const char *saved; |
| 8662 | char *end_op; |
| 8663 | |
| 8664 | while (*op_string |
| 8665 | && (op_end == NULL || op_string < op_end)) |
| 8666 | { |
| 8667 | saved = op_string; |
| 8668 | if (*op_string == '{') |
| 8669 | { |
| 8670 | op_string++; |
| 8671 | |
| 8672 | /* Check broadcasts. */ |
| 8673 | if (strncmp (op_string, "1to", 3) == 0) |
| 8674 | { |
| 8675 | int bcst_type; |
| 8676 | |
| 8677 | if (i.broadcast) |
| 8678 | goto duplicated_vec_op; |
| 8679 | |
| 8680 | op_string += 3; |
| 8681 | if (*op_string == '8') |
| 8682 | bcst_type = 8; |
| 8683 | else if (*op_string == '4') |
| 8684 | bcst_type = 4; |
| 8685 | else if (*op_string == '2') |
| 8686 | bcst_type = 2; |
| 8687 | else if (*op_string == '1' |
| 8688 | && *(op_string+1) == '6') |
| 8689 | { |
| 8690 | bcst_type = 16; |
| 8691 | op_string++; |
| 8692 | } |
| 8693 | else |
| 8694 | { |
| 8695 | as_bad (_("Unsupported broadcast: `%s'"), saved); |
| 8696 | return NULL; |
| 8697 | } |
| 8698 | op_string++; |
| 8699 | |
| 8700 | broadcast_op.type = bcst_type; |
| 8701 | broadcast_op.operand = this_operand; |
| 8702 | broadcast_op.bytes = 0; |
| 8703 | i.broadcast = &broadcast_op; |
| 8704 | } |
| 8705 | /* Check masking operation. */ |
| 8706 | else if ((mask = parse_register (op_string, &end_op)) != NULL) |
| 8707 | { |
| 8708 | /* k0 can't be used for write mask. */ |
| 8709 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
| 8710 | { |
| 8711 | as_bad (_("`%s%s' can't be used for write mask"), |
| 8712 | register_prefix, mask->reg_name); |
| 8713 | return NULL; |
| 8714 | } |
| 8715 | |
| 8716 | if (!i.mask) |
| 8717 | { |
| 8718 | mask_op.mask = mask; |
| 8719 | mask_op.zeroing = 0; |
| 8720 | mask_op.operand = this_operand; |
| 8721 | i.mask = &mask_op; |
| 8722 | } |
| 8723 | else |
| 8724 | { |
| 8725 | if (i.mask->mask) |
| 8726 | goto duplicated_vec_op; |
| 8727 | |
| 8728 | i.mask->mask = mask; |
| 8729 | |
| 8730 | /* Only "{z}" is allowed here. No need to check |
| 8731 | zeroing mask explicitly. */ |
| 8732 | if (i.mask->operand != this_operand) |
| 8733 | { |
| 8734 | as_bad (_("invalid write mask `%s'"), saved); |
| 8735 | return NULL; |
| 8736 | } |
| 8737 | } |
| 8738 | |
| 8739 | op_string = end_op; |
| 8740 | } |
| 8741 | /* Check zeroing-flag for masking operation. */ |
| 8742 | else if (*op_string == 'z') |
| 8743 | { |
| 8744 | if (!i.mask) |
| 8745 | { |
| 8746 | mask_op.mask = NULL; |
| 8747 | mask_op.zeroing = 1; |
| 8748 | mask_op.operand = this_operand; |
| 8749 | i.mask = &mask_op; |
| 8750 | } |
| 8751 | else |
| 8752 | { |
| 8753 | if (i.mask->zeroing) |
| 8754 | { |
| 8755 | duplicated_vec_op: |
| 8756 | as_bad (_("duplicated `%s'"), saved); |
| 8757 | return NULL; |
| 8758 | } |
| 8759 | |
| 8760 | i.mask->zeroing = 1; |
| 8761 | |
| 8762 | /* Only "{%k}" is allowed here. No need to check mask |
| 8763 | register explicitly. */ |
| 8764 | if (i.mask->operand != this_operand) |
| 8765 | { |
| 8766 | as_bad (_("invalid zeroing-masking `%s'"), |
| 8767 | saved); |
| 8768 | return NULL; |
| 8769 | } |
| 8770 | } |
| 8771 | |
| 8772 | op_string++; |
| 8773 | } |
| 8774 | else |
| 8775 | goto unknown_vec_op; |
| 8776 | |
| 8777 | if (*op_string != '}') |
| 8778 | { |
| 8779 | as_bad (_("missing `}' in `%s'"), saved); |
| 8780 | return NULL; |
| 8781 | } |
| 8782 | op_string++; |
| 8783 | |
| 8784 | /* Strip whitespace since the addition of pseudo prefixes |
| 8785 | changed how the scrubber treats '{'. */ |
| 8786 | if (is_space_char (*op_string)) |
| 8787 | ++op_string; |
| 8788 | |
| 8789 | continue; |
| 8790 | } |
| 8791 | unknown_vec_op: |
| 8792 | /* We don't know this one. */ |
| 8793 | as_bad (_("unknown vector operation: `%s'"), saved); |
| 8794 | return NULL; |
| 8795 | } |
| 8796 | |
| 8797 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
| 8798 | { |
| 8799 | as_bad (_("zeroing-masking only allowed with write mask")); |
| 8800 | return NULL; |
| 8801 | } |
| 8802 | |
| 8803 | return op_string; |
| 8804 | } |
| 8805 | |
| 8806 | static int |
| 8807 | i386_immediate (char *imm_start) |
| 8808 | { |
| 8809 | char *save_input_line_pointer; |
| 8810 | char *gotfree_input_line; |
| 8811 | segT exp_seg = 0; |
| 8812 | expressionS *exp; |
| 8813 | i386_operand_type types; |
| 8814 | |
| 8815 | operand_type_set (&types, ~0); |
| 8816 | |
| 8817 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) |
| 8818 | { |
| 8819 | as_bad (_("at most %d immediate operands are allowed"), |
| 8820 | MAX_IMMEDIATE_OPERANDS); |
| 8821 | return 0; |
| 8822 | } |
| 8823 | |
| 8824 | exp = &im_expressions[i.imm_operands++]; |
| 8825 | i.op[this_operand].imms = exp; |
| 8826 | |
| 8827 | if (is_space_char (*imm_start)) |
| 8828 | ++imm_start; |
| 8829 | |
| 8830 | save_input_line_pointer = input_line_pointer; |
| 8831 | input_line_pointer = imm_start; |
| 8832 | |
| 8833 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
| 8834 | if (gotfree_input_line) |
| 8835 | input_line_pointer = gotfree_input_line; |
| 8836 | |
| 8837 | exp_seg = expression (exp); |
| 8838 | |
| 8839 | SKIP_WHITESPACE (); |
| 8840 | |
| 8841 | /* Handle vector operations. */ |
| 8842 | if (*input_line_pointer == '{') |
| 8843 | { |
| 8844 | input_line_pointer = check_VecOperations (input_line_pointer, |
| 8845 | NULL); |
| 8846 | if (input_line_pointer == NULL) |
| 8847 | return 0; |
| 8848 | } |
| 8849 | |
| 8850 | if (*input_line_pointer) |
| 8851 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
| 8852 | |
| 8853 | input_line_pointer = save_input_line_pointer; |
| 8854 | if (gotfree_input_line) |
| 8855 | { |
| 8856 | free (gotfree_input_line); |
| 8857 | |
| 8858 | if (exp->X_op == O_constant || exp->X_op == O_register) |
| 8859 | exp->X_op = O_illegal; |
| 8860 | } |
| 8861 | |
| 8862 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
| 8863 | } |
| 8864 | |
| 8865 | static int |
| 8866 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, |
| 8867 | i386_operand_type types, const char *imm_start) |
| 8868 | { |
| 8869 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) |
| 8870 | { |
| 8871 | if (imm_start) |
| 8872 | as_bad (_("missing or invalid immediate expression `%s'"), |
| 8873 | imm_start); |
| 8874 | return 0; |
| 8875 | } |
| 8876 | else if (exp->X_op == O_constant) |
| 8877 | { |
| 8878 | /* Size it properly later. */ |
| 8879 | i.types[this_operand].bitfield.imm64 = 1; |
| 8880 | /* If not 64bit, sign extend val. */ |
| 8881 | if (flag_code != CODE_64BIT |
| 8882 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
| 8883 | exp->X_add_number |
| 8884 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
| 8885 | } |
| 8886 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 8887 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
| 8888 | && exp_seg != absolute_section |
| 8889 | && exp_seg != text_section |
| 8890 | && exp_seg != data_section |
| 8891 | && exp_seg != bss_section |
| 8892 | && exp_seg != undefined_section |
| 8893 | && !bfd_is_com_section (exp_seg)) |
| 8894 | { |
| 8895 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
| 8896 | return 0; |
| 8897 | } |
| 8898 | #endif |
| 8899 | else if (!intel_syntax && exp_seg == reg_section) |
| 8900 | { |
| 8901 | if (imm_start) |
| 8902 | as_bad (_("illegal immediate register operand %s"), imm_start); |
| 8903 | return 0; |
| 8904 | } |
| 8905 | else |
| 8906 | { |
| 8907 | /* This is an address. The size of the address will be |
| 8908 | determined later, depending on destination register, |
| 8909 | suffix, or the default for the section. */ |
| 8910 | i.types[this_operand].bitfield.imm8 = 1; |
| 8911 | i.types[this_operand].bitfield.imm16 = 1; |
| 8912 | i.types[this_operand].bitfield.imm32 = 1; |
| 8913 | i.types[this_operand].bitfield.imm32s = 1; |
| 8914 | i.types[this_operand].bitfield.imm64 = 1; |
| 8915 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
| 8916 | types); |
| 8917 | } |
| 8918 | |
| 8919 | return 1; |
| 8920 | } |
| 8921 | |
| 8922 | static char * |
| 8923 | i386_scale (char *scale) |
| 8924 | { |
| 8925 | offsetT val; |
| 8926 | char *save = input_line_pointer; |
| 8927 | |
| 8928 | input_line_pointer = scale; |
| 8929 | val = get_absolute_expression (); |
| 8930 | |
| 8931 | switch (val) |
| 8932 | { |
| 8933 | case 1: |
| 8934 | i.log2_scale_factor = 0; |
| 8935 | break; |
| 8936 | case 2: |
| 8937 | i.log2_scale_factor = 1; |
| 8938 | break; |
| 8939 | case 4: |
| 8940 | i.log2_scale_factor = 2; |
| 8941 | break; |
| 8942 | case 8: |
| 8943 | i.log2_scale_factor = 3; |
| 8944 | break; |
| 8945 | default: |
| 8946 | { |
| 8947 | char sep = *input_line_pointer; |
| 8948 | |
| 8949 | *input_line_pointer = '\0'; |
| 8950 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
| 8951 | scale); |
| 8952 | *input_line_pointer = sep; |
| 8953 | input_line_pointer = save; |
| 8954 | return NULL; |
| 8955 | } |
| 8956 | } |
| 8957 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
| 8958 | { |
| 8959 | as_warn (_("scale factor of %d without an index register"), |
| 8960 | 1 << i.log2_scale_factor); |
| 8961 | i.log2_scale_factor = 0; |
| 8962 | } |
| 8963 | scale = input_line_pointer; |
| 8964 | input_line_pointer = save; |
| 8965 | return scale; |
| 8966 | } |
| 8967 | |
| 8968 | static int |
| 8969 | i386_displacement (char *disp_start, char *disp_end) |
| 8970 | { |
| 8971 | expressionS *exp; |
| 8972 | segT exp_seg = 0; |
| 8973 | char *save_input_line_pointer; |
| 8974 | char *gotfree_input_line; |
| 8975 | int override; |
| 8976 | i386_operand_type bigdisp, types = anydisp; |
| 8977 | int ret; |
| 8978 | |
| 8979 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
| 8980 | { |
| 8981 | as_bad (_("at most %d displacement operands are allowed"), |
| 8982 | MAX_MEMORY_OPERANDS); |
| 8983 | return 0; |
| 8984 | } |
| 8985 | |
| 8986 | operand_type_set (&bigdisp, 0); |
| 8987 | if ((i.types[this_operand].bitfield.jumpabsolute) |
| 8988 | || (!current_templates->start->opcode_modifier.jump |
| 8989 | && !current_templates->start->opcode_modifier.jumpdword)) |
| 8990 | { |
| 8991 | bigdisp.bitfield.disp32 = 1; |
| 8992 | override = (i.prefix[ADDR_PREFIX] != 0); |
| 8993 | if (flag_code == CODE_64BIT) |
| 8994 | { |
| 8995 | if (!override) |
| 8996 | { |
| 8997 | bigdisp.bitfield.disp32s = 1; |
| 8998 | bigdisp.bitfield.disp64 = 1; |
| 8999 | } |
| 9000 | } |
| 9001 | else if ((flag_code == CODE_16BIT) ^ override) |
| 9002 | { |
| 9003 | bigdisp.bitfield.disp32 = 0; |
| 9004 | bigdisp.bitfield.disp16 = 1; |
| 9005 | } |
| 9006 | } |
| 9007 | else |
| 9008 | { |
| 9009 | /* For PC-relative branches, the width of the displacement |
| 9010 | is dependent upon data size, not address size. */ |
| 9011 | override = (i.prefix[DATA_PREFIX] != 0); |
| 9012 | if (flag_code == CODE_64BIT) |
| 9013 | { |
| 9014 | if (override || i.suffix == WORD_MNEM_SUFFIX) |
| 9015 | bigdisp.bitfield.disp16 = 1; |
| 9016 | else |
| 9017 | { |
| 9018 | bigdisp.bitfield.disp32 = 1; |
| 9019 | bigdisp.bitfield.disp32s = 1; |
| 9020 | } |
| 9021 | } |
| 9022 | else |
| 9023 | { |
| 9024 | if (!override) |
| 9025 | override = (i.suffix == (flag_code != CODE_16BIT |
| 9026 | ? WORD_MNEM_SUFFIX |
| 9027 | : LONG_MNEM_SUFFIX)); |
| 9028 | bigdisp.bitfield.disp32 = 1; |
| 9029 | if ((flag_code == CODE_16BIT) ^ override) |
| 9030 | { |
| 9031 | bigdisp.bitfield.disp32 = 0; |
| 9032 | bigdisp.bitfield.disp16 = 1; |
| 9033 | } |
| 9034 | } |
| 9035 | } |
| 9036 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
| 9037 | bigdisp); |
| 9038 | |
| 9039 | exp = &disp_expressions[i.disp_operands]; |
| 9040 | i.op[this_operand].disps = exp; |
| 9041 | i.disp_operands++; |
| 9042 | save_input_line_pointer = input_line_pointer; |
| 9043 | input_line_pointer = disp_start; |
| 9044 | END_STRING_AND_SAVE (disp_end); |
| 9045 | |
| 9046 | #ifndef GCC_ASM_O_HACK |
| 9047 | #define GCC_ASM_O_HACK 0 |
| 9048 | #endif |
| 9049 | #if GCC_ASM_O_HACK |
| 9050 | END_STRING_AND_SAVE (disp_end + 1); |
| 9051 | if (i.types[this_operand].bitfield.baseIndex |
| 9052 | && displacement_string_end[-1] == '+') |
| 9053 | { |
| 9054 | /* This hack is to avoid a warning when using the "o" |
| 9055 | constraint within gcc asm statements. |
| 9056 | For instance: |
| 9057 | |
| 9058 | #define _set_tssldt_desc(n,addr,limit,type) \ |
| 9059 | __asm__ __volatile__ ( \ |
| 9060 | "movw %w2,%0\n\t" \ |
| 9061 | "movw %w1,2+%0\n\t" \ |
| 9062 | "rorl $16,%1\n\t" \ |
| 9063 | "movb %b1,4+%0\n\t" \ |
| 9064 | "movb %4,5+%0\n\t" \ |
| 9065 | "movb $0,6+%0\n\t" \ |
| 9066 | "movb %h1,7+%0\n\t" \ |
| 9067 | "rorl $16,%1" \ |
| 9068 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) |
| 9069 | |
| 9070 | This works great except that the output assembler ends |
| 9071 | up looking a bit weird if it turns out that there is |
| 9072 | no offset. You end up producing code that looks like: |
| 9073 | |
| 9074 | #APP |
| 9075 | movw $235,(%eax) |
| 9076 | movw %dx,2+(%eax) |
| 9077 | rorl $16,%edx |
| 9078 | movb %dl,4+(%eax) |
| 9079 | movb $137,5+(%eax) |
| 9080 | movb $0,6+(%eax) |
| 9081 | movb %dh,7+(%eax) |
| 9082 | rorl $16,%edx |
| 9083 | #NO_APP |
| 9084 | |
| 9085 | So here we provide the missing zero. */ |
| 9086 | |
| 9087 | *displacement_string_end = '0'; |
| 9088 | } |
| 9089 | #endif |
| 9090 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
| 9091 | if (gotfree_input_line) |
| 9092 | input_line_pointer = gotfree_input_line; |
| 9093 | |
| 9094 | exp_seg = expression (exp); |
| 9095 | |
| 9096 | SKIP_WHITESPACE (); |
| 9097 | if (*input_line_pointer) |
| 9098 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
| 9099 | #if GCC_ASM_O_HACK |
| 9100 | RESTORE_END_STRING (disp_end + 1); |
| 9101 | #endif |
| 9102 | input_line_pointer = save_input_line_pointer; |
| 9103 | if (gotfree_input_line) |
| 9104 | { |
| 9105 | free (gotfree_input_line); |
| 9106 | |
| 9107 | if (exp->X_op == O_constant || exp->X_op == O_register) |
| 9108 | exp->X_op = O_illegal; |
| 9109 | } |
| 9110 | |
| 9111 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); |
| 9112 | |
| 9113 | RESTORE_END_STRING (disp_end); |
| 9114 | |
| 9115 | return ret; |
| 9116 | } |
| 9117 | |
| 9118 | static int |
| 9119 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, |
| 9120 | i386_operand_type types, const char *disp_start) |
| 9121 | { |
| 9122 | i386_operand_type bigdisp; |
| 9123 | int ret = 1; |
| 9124 | |
| 9125 | /* We do this to make sure that the section symbol is in |
| 9126 | the symbol table. We will ultimately change the relocation |
| 9127 | to be relative to the beginning of the section. */ |
| 9128 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
| 9129 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
| 9130 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
| 9131 | { |
| 9132 | if (exp->X_op != O_symbol) |
| 9133 | goto inv_disp; |
| 9134 | |
| 9135 | if (S_IS_LOCAL (exp->X_add_symbol) |
| 9136 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
| 9137 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) |
| 9138 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
| 9139 | exp->X_op = O_subtract; |
| 9140 | exp->X_op_symbol = GOT_symbol; |
| 9141 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
| 9142 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
| 9143 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
| 9144 | i.reloc[this_operand] = BFD_RELOC_64; |
| 9145 | else |
| 9146 | i.reloc[this_operand] = BFD_RELOC_32; |
| 9147 | } |
| 9148 | |
| 9149 | else if (exp->X_op == O_absent |
| 9150 | || exp->X_op == O_illegal |
| 9151 | || exp->X_op == O_big) |
| 9152 | { |
| 9153 | inv_disp: |
| 9154 | as_bad (_("missing or invalid displacement expression `%s'"), |
| 9155 | disp_start); |
| 9156 | ret = 0; |
| 9157 | } |
| 9158 | |
| 9159 | else if (flag_code == CODE_64BIT |
| 9160 | && !i.prefix[ADDR_PREFIX] |
| 9161 | && exp->X_op == O_constant) |
| 9162 | { |
| 9163 | /* Since displacement is signed extended to 64bit, don't allow |
| 9164 | disp32 and turn off disp32s if they are out of range. */ |
| 9165 | i.types[this_operand].bitfield.disp32 = 0; |
| 9166 | if (!fits_in_signed_long (exp->X_add_number)) |
| 9167 | { |
| 9168 | i.types[this_operand].bitfield.disp32s = 0; |
| 9169 | if (i.types[this_operand].bitfield.baseindex) |
| 9170 | { |
| 9171 | as_bad (_("0x%lx out range of signed 32bit displacement"), |
| 9172 | (long) exp->X_add_number); |
| 9173 | ret = 0; |
| 9174 | } |
| 9175 | } |
| 9176 | } |
| 9177 | |
| 9178 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 9179 | else if (exp->X_op != O_constant |
| 9180 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
| 9181 | && exp_seg != absolute_section |
| 9182 | && exp_seg != text_section |
| 9183 | && exp_seg != data_section |
| 9184 | && exp_seg != bss_section |
| 9185 | && exp_seg != undefined_section |
| 9186 | && !bfd_is_com_section (exp_seg)) |
| 9187 | { |
| 9188 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
| 9189 | ret = 0; |
| 9190 | } |
| 9191 | #endif |
| 9192 | |
| 9193 | /* Check if this is a displacement only operand. */ |
| 9194 | bigdisp = i.types[this_operand]; |
| 9195 | bigdisp.bitfield.disp8 = 0; |
| 9196 | bigdisp.bitfield.disp16 = 0; |
| 9197 | bigdisp.bitfield.disp32 = 0; |
| 9198 | bigdisp.bitfield.disp32s = 0; |
| 9199 | bigdisp.bitfield.disp64 = 0; |
| 9200 | if (operand_type_all_zero (&bigdisp)) |
| 9201 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
| 9202 | types); |
| 9203 | |
| 9204 | return ret; |
| 9205 | } |
| 9206 | |
| 9207 | /* Return the active addressing mode, taking address override and |
| 9208 | registers forming the address into consideration. Update the |
| 9209 | address override prefix if necessary. */ |
| 9210 | |
| 9211 | static enum flag_code |
| 9212 | i386_addressing_mode (void) |
| 9213 | { |
| 9214 | enum flag_code addr_mode; |
| 9215 | |
| 9216 | if (i.prefix[ADDR_PREFIX]) |
| 9217 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; |
| 9218 | else |
| 9219 | { |
| 9220 | addr_mode = flag_code; |
| 9221 | |
| 9222 | #if INFER_ADDR_PREFIX |
| 9223 | if (i.mem_operands == 0) |
| 9224 | { |
| 9225 | /* Infer address prefix from the first memory operand. */ |
| 9226 | const reg_entry *addr_reg = i.base_reg; |
| 9227 | |
| 9228 | if (addr_reg == NULL) |
| 9229 | addr_reg = i.index_reg; |
| 9230 | |
| 9231 | if (addr_reg) |
| 9232 | { |
| 9233 | if (addr_reg->reg_type.bitfield.dword) |
| 9234 | addr_mode = CODE_32BIT; |
| 9235 | else if (flag_code != CODE_64BIT |
| 9236 | && addr_reg->reg_type.bitfield.word) |
| 9237 | addr_mode = CODE_16BIT; |
| 9238 | |
| 9239 | if (addr_mode != flag_code) |
| 9240 | { |
| 9241 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; |
| 9242 | i.prefixes += 1; |
| 9243 | /* Change the size of any displacement too. At most one |
| 9244 | of Disp16 or Disp32 is set. |
| 9245 | FIXME. There doesn't seem to be any real need for |
| 9246 | separate Disp16 and Disp32 flags. The same goes for |
| 9247 | Imm16 and Imm32. Removing them would probably clean |
| 9248 | up the code quite a lot. */ |
| 9249 | if (flag_code != CODE_64BIT |
| 9250 | && (i.types[this_operand].bitfield.disp16 |
| 9251 | || i.types[this_operand].bitfield.disp32)) |
| 9252 | i.types[this_operand] |
| 9253 | = operand_type_xor (i.types[this_operand], disp16_32); |
| 9254 | } |
| 9255 | } |
| 9256 | } |
| 9257 | #endif |
| 9258 | } |
| 9259 | |
| 9260 | return addr_mode; |
| 9261 | } |
| 9262 | |
| 9263 | /* Make sure the memory operand we've been dealt is valid. |
| 9264 | Return 1 on success, 0 on a failure. */ |
| 9265 | |
| 9266 | static int |
| 9267 | i386_index_check (const char *operand_string) |
| 9268 | { |
| 9269 | const char *kind = "base/index"; |
| 9270 | enum flag_code addr_mode = i386_addressing_mode (); |
| 9271 | |
| 9272 | if (current_templates->start->opcode_modifier.isstring |
| 9273 | && !current_templates->start->opcode_modifier.immext |
| 9274 | && (current_templates->end[-1].opcode_modifier.isstring |
| 9275 | || i.mem_operands)) |
| 9276 | { |
| 9277 | /* Memory operands of string insns are special in that they only allow |
| 9278 | a single register (rDI, rSI, or rBX) as their memory address. */ |
| 9279 | const reg_entry *expected_reg; |
| 9280 | static const char *di_si[][2] = |
| 9281 | { |
| 9282 | { "esi", "edi" }, |
| 9283 | { "si", "di" }, |
| 9284 | { "rsi", "rdi" } |
| 9285 | }; |
| 9286 | static const char *bx[] = { "ebx", "bx", "rbx" }; |
| 9287 | |
| 9288 | kind = "string address"; |
| 9289 | |
| 9290 | if (current_templates->start->opcode_modifier.repprefixok) |
| 9291 | { |
| 9292 | i386_operand_type type = current_templates->end[-1].operand_types[0]; |
| 9293 | |
| 9294 | if (!type.bitfield.baseindex |
| 9295 | || ((!i.mem_operands != !intel_syntax) |
| 9296 | && current_templates->end[-1].operand_types[1] |
| 9297 | .bitfield.baseindex)) |
| 9298 | type = current_templates->end[-1].operand_types[1]; |
| 9299 | expected_reg = hash_find (reg_hash, |
| 9300 | di_si[addr_mode][type.bitfield.esseg]); |
| 9301 | |
| 9302 | } |
| 9303 | else |
| 9304 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
| 9305 | |
| 9306 | if (i.base_reg != expected_reg |
| 9307 | || i.index_reg |
| 9308 | || operand_type_check (i.types[this_operand], disp)) |
| 9309 | { |
| 9310 | /* The second memory operand must have the same size as |
| 9311 | the first one. */ |
| 9312 | if (i.mem_operands |
| 9313 | && i.base_reg |
| 9314 | && !((addr_mode == CODE_64BIT |
| 9315 | && i.base_reg->reg_type.bitfield.qword) |
| 9316 | || (addr_mode == CODE_32BIT |
| 9317 | ? i.base_reg->reg_type.bitfield.dword |
| 9318 | : i.base_reg->reg_type.bitfield.word))) |
| 9319 | goto bad_address; |
| 9320 | |
| 9321 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
| 9322 | operand_string, |
| 9323 | intel_syntax ? '[' : '(', |
| 9324 | register_prefix, |
| 9325 | expected_reg->reg_name, |
| 9326 | intel_syntax ? ']' : ')'); |
| 9327 | return 1; |
| 9328 | } |
| 9329 | else |
| 9330 | return 1; |
| 9331 | |
| 9332 | bad_address: |
| 9333 | as_bad (_("`%s' is not a valid %s expression"), |
| 9334 | operand_string, kind); |
| 9335 | return 0; |
| 9336 | } |
| 9337 | else |
| 9338 | { |
| 9339 | if (addr_mode != CODE_16BIT) |
| 9340 | { |
| 9341 | /* 32-bit/64-bit checks. */ |
| 9342 | if ((i.base_reg |
| 9343 | && ((addr_mode == CODE_64BIT |
| 9344 | ? !i.base_reg->reg_type.bitfield.qword |
| 9345 | : !i.base_reg->reg_type.bitfield.dword) |
| 9346 | || (i.index_reg && i.base_reg->reg_num == RegIP) |
| 9347 | || i.base_reg->reg_num == RegIZ)) |
| 9348 | || (i.index_reg |
| 9349 | && !i.index_reg->reg_type.bitfield.xmmword |
| 9350 | && !i.index_reg->reg_type.bitfield.ymmword |
| 9351 | && !i.index_reg->reg_type.bitfield.zmmword |
| 9352 | && ((addr_mode == CODE_64BIT |
| 9353 | ? !i.index_reg->reg_type.bitfield.qword |
| 9354 | : !i.index_reg->reg_type.bitfield.dword) |
| 9355 | || !i.index_reg->reg_type.bitfield.baseindex))) |
| 9356 | goto bad_address; |
| 9357 | |
| 9358 | /* bndmk, bndldx, and bndstx have special restrictions. */ |
| 9359 | if (current_templates->start->base_opcode == 0xf30f1b |
| 9360 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) |
| 9361 | { |
| 9362 | /* They cannot use RIP-relative addressing. */ |
| 9363 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
| 9364 | { |
| 9365 | as_bad (_("`%s' cannot be used here"), operand_string); |
| 9366 | return 0; |
| 9367 | } |
| 9368 | |
| 9369 | /* bndldx and bndstx ignore their scale factor. */ |
| 9370 | if (current_templates->start->base_opcode != 0xf30f1b |
| 9371 | && i.log2_scale_factor) |
| 9372 | as_warn (_("register scaling is being ignored here")); |
| 9373 | } |
| 9374 | } |
| 9375 | else |
| 9376 | { |
| 9377 | /* 16-bit checks. */ |
| 9378 | if ((i.base_reg |
| 9379 | && (!i.base_reg->reg_type.bitfield.word |
| 9380 | || !i.base_reg->reg_type.bitfield.baseindex)) |
| 9381 | || (i.index_reg |
| 9382 | && (!i.index_reg->reg_type.bitfield.word |
| 9383 | || !i.index_reg->reg_type.bitfield.baseindex |
| 9384 | || !(i.base_reg |
| 9385 | && i.base_reg->reg_num < 6 |
| 9386 | && i.index_reg->reg_num >= 6 |
| 9387 | && i.log2_scale_factor == 0)))) |
| 9388 | goto bad_address; |
| 9389 | } |
| 9390 | } |
| 9391 | return 1; |
| 9392 | } |
| 9393 | |
| 9394 | /* Handle vector immediates. */ |
| 9395 | |
| 9396 | static int |
| 9397 | RC_SAE_immediate (const char *imm_start) |
| 9398 | { |
| 9399 | unsigned int match_found, j; |
| 9400 | const char *pstr = imm_start; |
| 9401 | expressionS *exp; |
| 9402 | |
| 9403 | if (*pstr != '{') |
| 9404 | return 0; |
| 9405 | |
| 9406 | pstr++; |
| 9407 | match_found = 0; |
| 9408 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) |
| 9409 | { |
| 9410 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) |
| 9411 | { |
| 9412 | if (!i.rounding) |
| 9413 | { |
| 9414 | rc_op.type = RC_NamesTable[j].type; |
| 9415 | rc_op.operand = this_operand; |
| 9416 | i.rounding = &rc_op; |
| 9417 | } |
| 9418 | else |
| 9419 | { |
| 9420 | as_bad (_("duplicated `%s'"), imm_start); |
| 9421 | return 0; |
| 9422 | } |
| 9423 | pstr += RC_NamesTable[j].len; |
| 9424 | match_found = 1; |
| 9425 | break; |
| 9426 | } |
| 9427 | } |
| 9428 | if (!match_found) |
| 9429 | return 0; |
| 9430 | |
| 9431 | if (*pstr++ != '}') |
| 9432 | { |
| 9433 | as_bad (_("Missing '}': '%s'"), imm_start); |
| 9434 | return 0; |
| 9435 | } |
| 9436 | /* RC/SAE immediate string should contain nothing more. */; |
| 9437 | if (*pstr != 0) |
| 9438 | { |
| 9439 | as_bad (_("Junk after '}': '%s'"), imm_start); |
| 9440 | return 0; |
| 9441 | } |
| 9442 | |
| 9443 | exp = &im_expressions[i.imm_operands++]; |
| 9444 | i.op[this_operand].imms = exp; |
| 9445 | |
| 9446 | exp->X_op = O_constant; |
| 9447 | exp->X_add_number = 0; |
| 9448 | exp->X_add_symbol = (symbolS *) 0; |
| 9449 | exp->X_op_symbol = (symbolS *) 0; |
| 9450 | |
| 9451 | i.types[this_operand].bitfield.imm8 = 1; |
| 9452 | return 1; |
| 9453 | } |
| 9454 | |
| 9455 | /* Only string instructions can have a second memory operand, so |
| 9456 | reduce current_templates to just those if it contains any. */ |
| 9457 | static int |
| 9458 | maybe_adjust_templates (void) |
| 9459 | { |
| 9460 | const insn_template *t; |
| 9461 | |
| 9462 | gas_assert (i.mem_operands == 1); |
| 9463 | |
| 9464 | for (t = current_templates->start; t < current_templates->end; ++t) |
| 9465 | if (t->opcode_modifier.isstring) |
| 9466 | break; |
| 9467 | |
| 9468 | if (t < current_templates->end) |
| 9469 | { |
| 9470 | static templates aux_templates; |
| 9471 | bfd_boolean recheck; |
| 9472 | |
| 9473 | aux_templates.start = t; |
| 9474 | for (; t < current_templates->end; ++t) |
| 9475 | if (!t->opcode_modifier.isstring) |
| 9476 | break; |
| 9477 | aux_templates.end = t; |
| 9478 | |
| 9479 | /* Determine whether to re-check the first memory operand. */ |
| 9480 | recheck = (aux_templates.start != current_templates->start |
| 9481 | || t != current_templates->end); |
| 9482 | |
| 9483 | current_templates = &aux_templates; |
| 9484 | |
| 9485 | if (recheck) |
| 9486 | { |
| 9487 | i.mem_operands = 0; |
| 9488 | if (i.memop1_string != NULL |
| 9489 | && i386_index_check (i.memop1_string) == 0) |
| 9490 | return 0; |
| 9491 | i.mem_operands = 1; |
| 9492 | } |
| 9493 | } |
| 9494 | |
| 9495 | return 1; |
| 9496 | } |
| 9497 | |
| 9498 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
| 9499 | on error. */ |
| 9500 | |
| 9501 | static int |
| 9502 | i386_att_operand (char *operand_string) |
| 9503 | { |
| 9504 | const reg_entry *r; |
| 9505 | char *end_op; |
| 9506 | char *op_string = operand_string; |
| 9507 | |
| 9508 | if (is_space_char (*op_string)) |
| 9509 | ++op_string; |
| 9510 | |
| 9511 | /* We check for an absolute prefix (differentiating, |
| 9512 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
| 9513 | if (*op_string == ABSOLUTE_PREFIX) |
| 9514 | { |
| 9515 | ++op_string; |
| 9516 | if (is_space_char (*op_string)) |
| 9517 | ++op_string; |
| 9518 | i.types[this_operand].bitfield.jumpabsolute = 1; |
| 9519 | } |
| 9520 | |
| 9521 | /* Check if operand is a register. */ |
| 9522 | if ((r = parse_register (op_string, &end_op)) != NULL) |
| 9523 | { |
| 9524 | i386_operand_type temp; |
| 9525 | |
| 9526 | /* Check for a segment override by searching for ':' after a |
| 9527 | segment register. */ |
| 9528 | op_string = end_op; |
| 9529 | if (is_space_char (*op_string)) |
| 9530 | ++op_string; |
| 9531 | if (*op_string == ':' |
| 9532 | && (r->reg_type.bitfield.sreg2 |
| 9533 | || r->reg_type.bitfield.sreg3)) |
| 9534 | { |
| 9535 | switch (r->reg_num) |
| 9536 | { |
| 9537 | case 0: |
| 9538 | i.seg[i.mem_operands] = &es; |
| 9539 | break; |
| 9540 | case 1: |
| 9541 | i.seg[i.mem_operands] = &cs; |
| 9542 | break; |
| 9543 | case 2: |
| 9544 | i.seg[i.mem_operands] = &ss; |
| 9545 | break; |
| 9546 | case 3: |
| 9547 | i.seg[i.mem_operands] = &ds; |
| 9548 | break; |
| 9549 | case 4: |
| 9550 | i.seg[i.mem_operands] = &fs; |
| 9551 | break; |
| 9552 | case 5: |
| 9553 | i.seg[i.mem_operands] = &gs; |
| 9554 | break; |
| 9555 | } |
| 9556 | |
| 9557 | /* Skip the ':' and whitespace. */ |
| 9558 | ++op_string; |
| 9559 | if (is_space_char (*op_string)) |
| 9560 | ++op_string; |
| 9561 | |
| 9562 | if (!is_digit_char (*op_string) |
| 9563 | && !is_identifier_char (*op_string) |
| 9564 | && *op_string != '(' |
| 9565 | && *op_string != ABSOLUTE_PREFIX) |
| 9566 | { |
| 9567 | as_bad (_("bad memory operand `%s'"), op_string); |
| 9568 | return 0; |
| 9569 | } |
| 9570 | /* Handle case of %es:*foo. */ |
| 9571 | if (*op_string == ABSOLUTE_PREFIX) |
| 9572 | { |
| 9573 | ++op_string; |
| 9574 | if (is_space_char (*op_string)) |
| 9575 | ++op_string; |
| 9576 | i.types[this_operand].bitfield.jumpabsolute = 1; |
| 9577 | } |
| 9578 | goto do_memory_reference; |
| 9579 | } |
| 9580 | |
| 9581 | /* Handle vector operations. */ |
| 9582 | if (*op_string == '{') |
| 9583 | { |
| 9584 | op_string = check_VecOperations (op_string, NULL); |
| 9585 | if (op_string == NULL) |
| 9586 | return 0; |
| 9587 | } |
| 9588 | |
| 9589 | if (*op_string) |
| 9590 | { |
| 9591 | as_bad (_("junk `%s' after register"), op_string); |
| 9592 | return 0; |
| 9593 | } |
| 9594 | temp = r->reg_type; |
| 9595 | temp.bitfield.baseindex = 0; |
| 9596 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
| 9597 | temp); |
| 9598 | i.types[this_operand].bitfield.unspecified = 0; |
| 9599 | i.op[this_operand].regs = r; |
| 9600 | i.reg_operands++; |
| 9601 | } |
| 9602 | else if (*op_string == REGISTER_PREFIX) |
| 9603 | { |
| 9604 | as_bad (_("bad register name `%s'"), op_string); |
| 9605 | return 0; |
| 9606 | } |
| 9607 | else if (*op_string == IMMEDIATE_PREFIX) |
| 9608 | { |
| 9609 | ++op_string; |
| 9610 | if (i.types[this_operand].bitfield.jumpabsolute) |
| 9611 | { |
| 9612 | as_bad (_("immediate operand illegal with absolute jump")); |
| 9613 | return 0; |
| 9614 | } |
| 9615 | if (!i386_immediate (op_string)) |
| 9616 | return 0; |
| 9617 | } |
| 9618 | else if (RC_SAE_immediate (operand_string)) |
| 9619 | { |
| 9620 | /* If it is a RC or SAE immediate, do nothing. */ |
| 9621 | ; |
| 9622 | } |
| 9623 | else if (is_digit_char (*op_string) |
| 9624 | || is_identifier_char (*op_string) |
| 9625 | || *op_string == '"' |
| 9626 | || *op_string == '(') |
| 9627 | { |
| 9628 | /* This is a memory reference of some sort. */ |
| 9629 | char *base_string; |
| 9630 | |
| 9631 | /* Start and end of displacement string expression (if found). */ |
| 9632 | char *displacement_string_start; |
| 9633 | char *displacement_string_end; |
| 9634 | char *vop_start; |
| 9635 | |
| 9636 | do_memory_reference: |
| 9637 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
| 9638 | return 0; |
| 9639 | if ((i.mem_operands == 1 |
| 9640 | && !current_templates->start->opcode_modifier.isstring) |
| 9641 | || i.mem_operands == 2) |
| 9642 | { |
| 9643 | as_bad (_("too many memory references for `%s'"), |
| 9644 | current_templates->start->name); |
| 9645 | return 0; |
| 9646 | } |
| 9647 | |
| 9648 | /* Check for base index form. We detect the base index form by |
| 9649 | looking for an ')' at the end of the operand, searching |
| 9650 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' |
| 9651 | after the '('. */ |
| 9652 | base_string = op_string + strlen (op_string); |
| 9653 | |
| 9654 | /* Handle vector operations. */ |
| 9655 | vop_start = strchr (op_string, '{'); |
| 9656 | if (vop_start && vop_start < base_string) |
| 9657 | { |
| 9658 | if (check_VecOperations (vop_start, base_string) == NULL) |
| 9659 | return 0; |
| 9660 | base_string = vop_start; |
| 9661 | } |
| 9662 | |
| 9663 | --base_string; |
| 9664 | if (is_space_char (*base_string)) |
| 9665 | --base_string; |
| 9666 | |
| 9667 | /* If we only have a displacement, set-up for it to be parsed later. */ |
| 9668 | displacement_string_start = op_string; |
| 9669 | displacement_string_end = base_string + 1; |
| 9670 | |
| 9671 | if (*base_string == ')') |
| 9672 | { |
| 9673 | char *temp_string; |
| 9674 | unsigned int parens_balanced = 1; |
| 9675 | /* We've already checked that the number of left & right ()'s are |
| 9676 | equal, so this loop will not be infinite. */ |
| 9677 | do |
| 9678 | { |
| 9679 | base_string--; |
| 9680 | if (*base_string == ')') |
| 9681 | parens_balanced++; |
| 9682 | if (*base_string == '(') |
| 9683 | parens_balanced--; |
| 9684 | } |
| 9685 | while (parens_balanced); |
| 9686 | |
| 9687 | temp_string = base_string; |
| 9688 | |
| 9689 | /* Skip past '(' and whitespace. */ |
| 9690 | ++base_string; |
| 9691 | if (is_space_char (*base_string)) |
| 9692 | ++base_string; |
| 9693 | |
| 9694 | if (*base_string == ',' |
| 9695 | || ((i.base_reg = parse_register (base_string, &end_op)) |
| 9696 | != NULL)) |
| 9697 | { |
| 9698 | displacement_string_end = temp_string; |
| 9699 | |
| 9700 | i.types[this_operand].bitfield.baseindex = 1; |
| 9701 | |
| 9702 | if (i.base_reg) |
| 9703 | { |
| 9704 | base_string = end_op; |
| 9705 | if (is_space_char (*base_string)) |
| 9706 | ++base_string; |
| 9707 | } |
| 9708 | |
| 9709 | /* There may be an index reg or scale factor here. */ |
| 9710 | if (*base_string == ',') |
| 9711 | { |
| 9712 | ++base_string; |
| 9713 | if (is_space_char (*base_string)) |
| 9714 | ++base_string; |
| 9715 | |
| 9716 | if ((i.index_reg = parse_register (base_string, &end_op)) |
| 9717 | != NULL) |
| 9718 | { |
| 9719 | base_string = end_op; |
| 9720 | if (is_space_char (*base_string)) |
| 9721 | ++base_string; |
| 9722 | if (*base_string == ',') |
| 9723 | { |
| 9724 | ++base_string; |
| 9725 | if (is_space_char (*base_string)) |
| 9726 | ++base_string; |
| 9727 | } |
| 9728 | else if (*base_string != ')') |
| 9729 | { |
| 9730 | as_bad (_("expecting `,' or `)' " |
| 9731 | "after index register in `%s'"), |
| 9732 | operand_string); |
| 9733 | return 0; |
| 9734 | } |
| 9735 | } |
| 9736 | else if (*base_string == REGISTER_PREFIX) |
| 9737 | { |
| 9738 | end_op = strchr (base_string, ','); |
| 9739 | if (end_op) |
| 9740 | *end_op = '\0'; |
| 9741 | as_bad (_("bad register name `%s'"), base_string); |
| 9742 | return 0; |
| 9743 | } |
| 9744 | |
| 9745 | /* Check for scale factor. */ |
| 9746 | if (*base_string != ')') |
| 9747 | { |
| 9748 | char *end_scale = i386_scale (base_string); |
| 9749 | |
| 9750 | if (!end_scale) |
| 9751 | return 0; |
| 9752 | |
| 9753 | base_string = end_scale; |
| 9754 | if (is_space_char (*base_string)) |
| 9755 | ++base_string; |
| 9756 | if (*base_string != ')') |
| 9757 | { |
| 9758 | as_bad (_("expecting `)' " |
| 9759 | "after scale factor in `%s'"), |
| 9760 | operand_string); |
| 9761 | return 0; |
| 9762 | } |
| 9763 | } |
| 9764 | else if (!i.index_reg) |
| 9765 | { |
| 9766 | as_bad (_("expecting index register or scale factor " |
| 9767 | "after `,'; got '%c'"), |
| 9768 | *base_string); |
| 9769 | return 0; |
| 9770 | } |
| 9771 | } |
| 9772 | else if (*base_string != ')') |
| 9773 | { |
| 9774 | as_bad (_("expecting `,' or `)' " |
| 9775 | "after base register in `%s'"), |
| 9776 | operand_string); |
| 9777 | return 0; |
| 9778 | } |
| 9779 | } |
| 9780 | else if (*base_string == REGISTER_PREFIX) |
| 9781 | { |
| 9782 | end_op = strchr (base_string, ','); |
| 9783 | if (end_op) |
| 9784 | *end_op = '\0'; |
| 9785 | as_bad (_("bad register name `%s'"), base_string); |
| 9786 | return 0; |
| 9787 | } |
| 9788 | } |
| 9789 | |
| 9790 | /* If there's an expression beginning the operand, parse it, |
| 9791 | assuming displacement_string_start and |
| 9792 | displacement_string_end are meaningful. */ |
| 9793 | if (displacement_string_start != displacement_string_end) |
| 9794 | { |
| 9795 | if (!i386_displacement (displacement_string_start, |
| 9796 | displacement_string_end)) |
| 9797 | return 0; |
| 9798 | } |
| 9799 | |
| 9800 | /* Special case for (%dx) while doing input/output op. */ |
| 9801 | if (i.base_reg |
| 9802 | && i.base_reg->reg_type.bitfield.inoutportreg |
| 9803 | && i.index_reg == 0 |
| 9804 | && i.log2_scale_factor == 0 |
| 9805 | && i.seg[i.mem_operands] == 0 |
| 9806 | && !operand_type_check (i.types[this_operand], disp)) |
| 9807 | { |
| 9808 | i.types[this_operand] = i.base_reg->reg_type; |
| 9809 | return 1; |
| 9810 | } |
| 9811 | |
| 9812 | if (i386_index_check (operand_string) == 0) |
| 9813 | return 0; |
| 9814 | i.flags[this_operand] |= Operand_Mem; |
| 9815 | if (i.mem_operands == 0) |
| 9816 | i.memop1_string = xstrdup (operand_string); |
| 9817 | i.mem_operands++; |
| 9818 | } |
| 9819 | else |
| 9820 | { |
| 9821 | /* It's not a memory operand; argh! */ |
| 9822 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
| 9823 | output_invalid (*op_string), |
| 9824 | this_operand + 1, |
| 9825 | op_string); |
| 9826 | return 0; |
| 9827 | } |
| 9828 | return 1; /* Normal return. */ |
| 9829 | } |
| 9830 | \f |
| 9831 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
| 9832 | that an rs_machine_dependent frag may reach. */ |
| 9833 | |
| 9834 | unsigned int |
| 9835 | i386_frag_max_var (fragS *frag) |
| 9836 | { |
| 9837 | /* The only relaxable frags are for jumps. |
| 9838 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ |
| 9839 | gas_assert (frag->fr_type == rs_machine_dependent); |
| 9840 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; |
| 9841 | } |
| 9842 | |
| 9843 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 9844 | static int |
| 9845 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
| 9846 | { |
| 9847 | /* STT_GNU_IFUNC symbol must go through PLT. */ |
| 9848 | if ((symbol_get_bfdsym (fr_symbol)->flags |
| 9849 | & BSF_GNU_INDIRECT_FUNCTION) != 0) |
| 9850 | return 0; |
| 9851 | |
| 9852 | if (!S_IS_EXTERNAL (fr_symbol)) |
| 9853 | /* Symbol may be weak or local. */ |
| 9854 | return !S_IS_WEAK (fr_symbol); |
| 9855 | |
| 9856 | /* Global symbols with non-default visibility can't be preempted. */ |
| 9857 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) |
| 9858 | return 1; |
| 9859 | |
| 9860 | if (fr_var != NO_RELOC) |
| 9861 | switch ((enum bfd_reloc_code_real) fr_var) |
| 9862 | { |
| 9863 | case BFD_RELOC_386_PLT32: |
| 9864 | case BFD_RELOC_X86_64_PLT32: |
| 9865 | /* Symbol with PLT relocation may be preempted. */ |
| 9866 | return 0; |
| 9867 | default: |
| 9868 | abort (); |
| 9869 | } |
| 9870 | |
| 9871 | /* Global symbols with default visibility in a shared library may be |
| 9872 | preempted by another definition. */ |
| 9873 | return !shared; |
| 9874 | } |
| 9875 | #endif |
| 9876 | |
| 9877 | /* md_estimate_size_before_relax() |
| 9878 | |
| 9879 | Called just before relax() for rs_machine_dependent frags. The x86 |
| 9880 | assembler uses these frags to handle variable size jump |
| 9881 | instructions. |
| 9882 | |
| 9883 | Any symbol that is now undefined will not become defined. |
| 9884 | Return the correct fr_subtype in the frag. |
| 9885 | Return the initial "guess for variable size of frag" to caller. |
| 9886 | The guess is actually the growth beyond the fixed part. Whatever |
| 9887 | we do to grow the fixed or variable part contributes to our |
| 9888 | returned value. */ |
| 9889 | |
| 9890 | int |
| 9891 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
| 9892 | { |
| 9893 | /* We've already got fragP->fr_subtype right; all we have to do is |
| 9894 | check for un-relaxable symbols. On an ELF system, we can't relax |
| 9895 | an externally visible symbol, because it may be overridden by a |
| 9896 | shared library. */ |
| 9897 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
| 9898 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 9899 | || (IS_ELF |
| 9900 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
| 9901 | fragP->fr_var)) |
| 9902 | #endif |
| 9903 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 9904 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 9905 | && S_IS_WEAK (fragP->fr_symbol)) |
| 9906 | #endif |
| 9907 | ) |
| 9908 | { |
| 9909 | /* Symbol is undefined in this segment, or we need to keep a |
| 9910 | reloc so that weak symbols can be overridden. */ |
| 9911 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; |
| 9912 | enum bfd_reloc_code_real reloc_type; |
| 9913 | unsigned char *opcode; |
| 9914 | int old_fr_fix; |
| 9915 | |
| 9916 | if (fragP->fr_var != NO_RELOC) |
| 9917 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
| 9918 | else if (size == 2) |
| 9919 | reloc_type = BFD_RELOC_16_PCREL; |
| 9920 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 9921 | else if (need_plt32_p (fragP->fr_symbol)) |
| 9922 | reloc_type = BFD_RELOC_X86_64_PLT32; |
| 9923 | #endif |
| 9924 | else |
| 9925 | reloc_type = BFD_RELOC_32_PCREL; |
| 9926 | |
| 9927 | old_fr_fix = fragP->fr_fix; |
| 9928 | opcode = (unsigned char *) fragP->fr_opcode; |
| 9929 | |
| 9930 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
| 9931 | { |
| 9932 | case UNCOND_JUMP: |
| 9933 | /* Make jmp (0xeb) a (d)word displacement jump. */ |
| 9934 | opcode[0] = 0xe9; |
| 9935 | fragP->fr_fix += size; |
| 9936 | fix_new (fragP, old_fr_fix, size, |
| 9937 | fragP->fr_symbol, |
| 9938 | fragP->fr_offset, 1, |
| 9939 | reloc_type); |
| 9940 | break; |
| 9941 | |
| 9942 | case COND_JUMP86: |
| 9943 | if (size == 2 |
| 9944 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) |
| 9945 | { |
| 9946 | /* Negate the condition, and branch past an |
| 9947 | unconditional jump. */ |
| 9948 | opcode[0] ^= 1; |
| 9949 | opcode[1] = 3; |
| 9950 | /* Insert an unconditional jump. */ |
| 9951 | opcode[2] = 0xe9; |
| 9952 | /* We added two extra opcode bytes, and have a two byte |
| 9953 | offset. */ |
| 9954 | fragP->fr_fix += 2 + 2; |
| 9955 | fix_new (fragP, old_fr_fix + 2, 2, |
| 9956 | fragP->fr_symbol, |
| 9957 | fragP->fr_offset, 1, |
| 9958 | reloc_type); |
| 9959 | break; |
| 9960 | } |
| 9961 | /* Fall through. */ |
| 9962 | |
| 9963 | case COND_JUMP: |
| 9964 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
| 9965 | { |
| 9966 | fixS *fixP; |
| 9967 | |
| 9968 | fragP->fr_fix += 1; |
| 9969 | fixP = fix_new (fragP, old_fr_fix, 1, |
| 9970 | fragP->fr_symbol, |
| 9971 | fragP->fr_offset, 1, |
| 9972 | BFD_RELOC_8_PCREL); |
| 9973 | fixP->fx_signed = 1; |
| 9974 | break; |
| 9975 | } |
| 9976 | |
| 9977 | /* This changes the byte-displacement jump 0x7N |
| 9978 | to the (d)word-displacement jump 0x0f,0x8N. */ |
| 9979 | opcode[1] = opcode[0] + 0x10; |
| 9980 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 9981 | /* We've added an opcode byte. */ |
| 9982 | fragP->fr_fix += 1 + size; |
| 9983 | fix_new (fragP, old_fr_fix + 1, size, |
| 9984 | fragP->fr_symbol, |
| 9985 | fragP->fr_offset, 1, |
| 9986 | reloc_type); |
| 9987 | break; |
| 9988 | |
| 9989 | default: |
| 9990 | BAD_CASE (fragP->fr_subtype); |
| 9991 | break; |
| 9992 | } |
| 9993 | frag_wane (fragP); |
| 9994 | return fragP->fr_fix - old_fr_fix; |
| 9995 | } |
| 9996 | |
| 9997 | /* Guess size depending on current relax state. Initially the relax |
| 9998 | state will correspond to a short jump and we return 1, because |
| 9999 | the variable part of the frag (the branch offset) is one byte |
| 10000 | long. However, we can relax a section more than once and in that |
| 10001 | case we must either set fr_subtype back to the unrelaxed state, |
| 10002 | or return the value for the appropriate branch. */ |
| 10003 | return md_relax_table[fragP->fr_subtype].rlx_length; |
| 10004 | } |
| 10005 | |
| 10006 | /* Called after relax() is finished. |
| 10007 | |
| 10008 | In: Address of frag. |
| 10009 | fr_type == rs_machine_dependent. |
| 10010 | fr_subtype is what the address relaxed to. |
| 10011 | |
| 10012 | Out: Any fixSs and constants are set up. |
| 10013 | Caller will turn frag into a ".space 0". */ |
| 10014 | |
| 10015 | void |
| 10016 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
| 10017 | fragS *fragP) |
| 10018 | { |
| 10019 | unsigned char *opcode; |
| 10020 | unsigned char *where_to_put_displacement = NULL; |
| 10021 | offsetT target_address; |
| 10022 | offsetT opcode_address; |
| 10023 | unsigned int extension = 0; |
| 10024 | offsetT displacement_from_opcode_start; |
| 10025 | |
| 10026 | opcode = (unsigned char *) fragP->fr_opcode; |
| 10027 | |
| 10028 | /* Address we want to reach in file space. */ |
| 10029 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
| 10030 | |
| 10031 | /* Address opcode resides at in file space. */ |
| 10032 | opcode_address = fragP->fr_address + fragP->fr_fix; |
| 10033 | |
| 10034 | /* Displacement from opcode start to fill into instruction. */ |
| 10035 | displacement_from_opcode_start = target_address - opcode_address; |
| 10036 | |
| 10037 | if ((fragP->fr_subtype & BIG) == 0) |
| 10038 | { |
| 10039 | /* Don't have to change opcode. */ |
| 10040 | extension = 1; /* 1 opcode + 1 displacement */ |
| 10041 | where_to_put_displacement = &opcode[1]; |
| 10042 | } |
| 10043 | else |
| 10044 | { |
| 10045 | if (no_cond_jump_promotion |
| 10046 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) |
| 10047 | as_warn_where (fragP->fr_file, fragP->fr_line, |
| 10048 | _("long jump required")); |
| 10049 | |
| 10050 | switch (fragP->fr_subtype) |
| 10051 | { |
| 10052 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): |
| 10053 | extension = 4; /* 1 opcode + 4 displacement */ |
| 10054 | opcode[0] = 0xe9; |
| 10055 | where_to_put_displacement = &opcode[1]; |
| 10056 | break; |
| 10057 | |
| 10058 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
| 10059 | extension = 2; /* 1 opcode + 2 displacement */ |
| 10060 | opcode[0] = 0xe9; |
| 10061 | where_to_put_displacement = &opcode[1]; |
| 10062 | break; |
| 10063 | |
| 10064 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
| 10065 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): |
| 10066 | extension = 5; /* 2 opcode + 4 displacement */ |
| 10067 | opcode[1] = opcode[0] + 0x10; |
| 10068 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 10069 | where_to_put_displacement = &opcode[2]; |
| 10070 | break; |
| 10071 | |
| 10072 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
| 10073 | extension = 3; /* 2 opcode + 2 displacement */ |
| 10074 | opcode[1] = opcode[0] + 0x10; |
| 10075 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
| 10076 | where_to_put_displacement = &opcode[2]; |
| 10077 | break; |
| 10078 | |
| 10079 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
| 10080 | extension = 4; |
| 10081 | opcode[0] ^= 1; |
| 10082 | opcode[1] = 3; |
| 10083 | opcode[2] = 0xe9; |
| 10084 | where_to_put_displacement = &opcode[3]; |
| 10085 | break; |
| 10086 | |
| 10087 | default: |
| 10088 | BAD_CASE (fragP->fr_subtype); |
| 10089 | break; |
| 10090 | } |
| 10091 | } |
| 10092 | |
| 10093 | /* If size if less then four we are sure that the operand fits, |
| 10094 | but if it's 4, then it could be that the displacement is larger |
| 10095 | then -/+ 2GB. */ |
| 10096 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 |
| 10097 | && object_64bit |
| 10098 | && ((addressT) (displacement_from_opcode_start - extension |
| 10099 | + ((addressT) 1 << 31)) |
| 10100 | > (((addressT) 2 << 31) - 1))) |
| 10101 | { |
| 10102 | as_bad_where (fragP->fr_file, fragP->fr_line, |
| 10103 | _("jump target out of range")); |
| 10104 | /* Make us emit 0. */ |
| 10105 | displacement_from_opcode_start = extension; |
| 10106 | } |
| 10107 | /* Now put displacement after opcode. */ |
| 10108 | md_number_to_chars ((char *) where_to_put_displacement, |
| 10109 | (valueT) (displacement_from_opcode_start - extension), |
| 10110 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
| 10111 | fragP->fr_fix += extension; |
| 10112 | } |
| 10113 | \f |
| 10114 | /* Apply a fixup (fixP) to segment data, once it has been determined |
| 10115 | by our caller that we have all the info we need to fix it up. |
| 10116 | |
| 10117 | Parameter valP is the pointer to the value of the bits. |
| 10118 | |
| 10119 | On the 386, immediates, displacements, and data pointers are all in |
| 10120 | the same (little-endian) format, so we don't need to care about which |
| 10121 | we are handling. */ |
| 10122 | |
| 10123 | void |
| 10124 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
| 10125 | { |
| 10126 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
| 10127 | valueT value = *valP; |
| 10128 | |
| 10129 | #if !defined (TE_Mach) |
| 10130 | if (fixP->fx_pcrel) |
| 10131 | { |
| 10132 | switch (fixP->fx_r_type) |
| 10133 | { |
| 10134 | default: |
| 10135 | break; |
| 10136 | |
| 10137 | case BFD_RELOC_64: |
| 10138 | fixP->fx_r_type = BFD_RELOC_64_PCREL; |
| 10139 | break; |
| 10140 | case BFD_RELOC_32: |
| 10141 | case BFD_RELOC_X86_64_32S: |
| 10142 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
| 10143 | break; |
| 10144 | case BFD_RELOC_16: |
| 10145 | fixP->fx_r_type = BFD_RELOC_16_PCREL; |
| 10146 | break; |
| 10147 | case BFD_RELOC_8: |
| 10148 | fixP->fx_r_type = BFD_RELOC_8_PCREL; |
| 10149 | break; |
| 10150 | } |
| 10151 | } |
| 10152 | |
| 10153 | if (fixP->fx_addsy != NULL |
| 10154 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
| 10155 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
| 10156 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
| 10157 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
| 10158 | && !use_rela_relocations) |
| 10159 | { |
| 10160 | /* This is a hack. There should be a better way to handle this. |
| 10161 | This covers for the fact that bfd_install_relocation will |
| 10162 | subtract the current location (for partial_inplace, PC relative |
| 10163 | relocations); see more below. */ |
| 10164 | #ifndef OBJ_AOUT |
| 10165 | if (IS_ELF |
| 10166 | #ifdef TE_PE |
| 10167 | || OUTPUT_FLAVOR == bfd_target_coff_flavour |
| 10168 | #endif |
| 10169 | ) |
| 10170 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
| 10171 | #endif |
| 10172 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 10173 | if (IS_ELF) |
| 10174 | { |
| 10175 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
| 10176 | |
| 10177 | if ((sym_seg == seg |
| 10178 | || (symbol_section_p (fixP->fx_addsy) |
| 10179 | && sym_seg != absolute_section)) |
| 10180 | && !generic_force_reloc (fixP)) |
| 10181 | { |
| 10182 | /* Yes, we add the values in twice. This is because |
| 10183 | bfd_install_relocation subtracts them out again. I think |
| 10184 | bfd_install_relocation is broken, but I don't dare change |
| 10185 | it. FIXME. */ |
| 10186 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
| 10187 | } |
| 10188 | } |
| 10189 | #endif |
| 10190 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 10191 | /* For some reason, the PE format does not store a |
| 10192 | section address offset for a PC relative symbol. */ |
| 10193 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg |
| 10194 | || S_IS_WEAK (fixP->fx_addsy)) |
| 10195 | value += md_pcrel_from (fixP); |
| 10196 | #endif |
| 10197 | } |
| 10198 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 10199 | if (fixP->fx_addsy != NULL |
| 10200 | && S_IS_WEAK (fixP->fx_addsy) |
| 10201 | /* PR 16858: Do not modify weak function references. */ |
| 10202 | && ! fixP->fx_pcrel) |
| 10203 | { |
| 10204 | #if !defined (TE_PEP) |
| 10205 | /* For x86 PE weak function symbols are neither PC-relative |
| 10206 | nor do they set S_IS_FUNCTION. So the only reliable way |
| 10207 | to detect them is to check the flags of their containing |
| 10208 | section. */ |
| 10209 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL |
| 10210 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) |
| 10211 | ; |
| 10212 | else |
| 10213 | #endif |
| 10214 | value -= S_GET_VALUE (fixP->fx_addsy); |
| 10215 | } |
| 10216 | #endif |
| 10217 | |
| 10218 | /* Fix a few things - the dynamic linker expects certain values here, |
| 10219 | and we must not disappoint it. */ |
| 10220 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 10221 | if (IS_ELF && fixP->fx_addsy) |
| 10222 | switch (fixP->fx_r_type) |
| 10223 | { |
| 10224 | case BFD_RELOC_386_PLT32: |
| 10225 | case BFD_RELOC_X86_64_PLT32: |
| 10226 | /* Make the jump instruction point to the address of the operand. At |
| 10227 | runtime we merely add the offset to the actual PLT entry. */ |
| 10228 | value = -4; |
| 10229 | break; |
| 10230 | |
| 10231 | case BFD_RELOC_386_TLS_GD: |
| 10232 | case BFD_RELOC_386_TLS_LDM: |
| 10233 | case BFD_RELOC_386_TLS_IE_32: |
| 10234 | case BFD_RELOC_386_TLS_IE: |
| 10235 | case BFD_RELOC_386_TLS_GOTIE: |
| 10236 | case BFD_RELOC_386_TLS_GOTDESC: |
| 10237 | case BFD_RELOC_X86_64_TLSGD: |
| 10238 | case BFD_RELOC_X86_64_TLSLD: |
| 10239 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 10240 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 10241 | value = 0; /* Fully resolved at runtime. No addend. */ |
| 10242 | /* Fallthrough */ |
| 10243 | case BFD_RELOC_386_TLS_LE: |
| 10244 | case BFD_RELOC_386_TLS_LDO_32: |
| 10245 | case BFD_RELOC_386_TLS_LE_32: |
| 10246 | case BFD_RELOC_X86_64_DTPOFF32: |
| 10247 | case BFD_RELOC_X86_64_DTPOFF64: |
| 10248 | case BFD_RELOC_X86_64_TPOFF32: |
| 10249 | case BFD_RELOC_X86_64_TPOFF64: |
| 10250 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 10251 | break; |
| 10252 | |
| 10253 | case BFD_RELOC_386_TLS_DESC_CALL: |
| 10254 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 10255 | value = 0; /* Fully resolved at runtime. No addend. */ |
| 10256 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 10257 | fixP->fx_done = 0; |
| 10258 | return; |
| 10259 | |
| 10260 | case BFD_RELOC_VTABLE_INHERIT: |
| 10261 | case BFD_RELOC_VTABLE_ENTRY: |
| 10262 | fixP->fx_done = 0; |
| 10263 | return; |
| 10264 | |
| 10265 | default: |
| 10266 | break; |
| 10267 | } |
| 10268 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ |
| 10269 | *valP = value; |
| 10270 | #endif /* !defined (TE_Mach) */ |
| 10271 | |
| 10272 | /* Are we finished with this relocation now? */ |
| 10273 | if (fixP->fx_addsy == NULL) |
| 10274 | fixP->fx_done = 1; |
| 10275 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 10276 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) |
| 10277 | { |
| 10278 | fixP->fx_done = 0; |
| 10279 | /* Remember value for tc_gen_reloc. */ |
| 10280 | fixP->fx_addnumber = value; |
| 10281 | /* Clear out the frag for now. */ |
| 10282 | value = 0; |
| 10283 | } |
| 10284 | #endif |
| 10285 | else if (use_rela_relocations) |
| 10286 | { |
| 10287 | fixP->fx_no_overflow = 1; |
| 10288 | /* Remember value for tc_gen_reloc. */ |
| 10289 | fixP->fx_addnumber = value; |
| 10290 | value = 0; |
| 10291 | } |
| 10292 | |
| 10293 | md_number_to_chars (p, value, fixP->fx_size); |
| 10294 | } |
| 10295 | \f |
| 10296 | const char * |
| 10297 | md_atof (int type, char *litP, int *sizeP) |
| 10298 | { |
| 10299 | /* This outputs the LITTLENUMs in REVERSE order; |
| 10300 | in accord with the bigendian 386. */ |
| 10301 | return ieee_md_atof (type, litP, sizeP, FALSE); |
| 10302 | } |
| 10303 | \f |
| 10304 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
| 10305 | |
| 10306 | static char * |
| 10307 | output_invalid (int c) |
| 10308 | { |
| 10309 | if (ISPRINT (c)) |
| 10310 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
| 10311 | "'%c'", c); |
| 10312 | else |
| 10313 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
| 10314 | "(0x%x)", (unsigned char) c); |
| 10315 | return output_invalid_buf; |
| 10316 | } |
| 10317 | |
| 10318 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
| 10319 | |
| 10320 | static const reg_entry * |
| 10321 | parse_real_register (char *reg_string, char **end_op) |
| 10322 | { |
| 10323 | char *s = reg_string; |
| 10324 | char *p; |
| 10325 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
| 10326 | const reg_entry *r; |
| 10327 | |
| 10328 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ |
| 10329 | if (*s == REGISTER_PREFIX) |
| 10330 | ++s; |
| 10331 | |
| 10332 | if (is_space_char (*s)) |
| 10333 | ++s; |
| 10334 | |
| 10335 | p = reg_name_given; |
| 10336 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
| 10337 | { |
| 10338 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
| 10339 | return (const reg_entry *) NULL; |
| 10340 | s++; |
| 10341 | } |
| 10342 | |
| 10343 | /* For naked regs, make sure that we are not dealing with an identifier. |
| 10344 | This prevents confusing an identifier like `eax_var' with register |
| 10345 | `eax'. */ |
| 10346 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) |
| 10347 | return (const reg_entry *) NULL; |
| 10348 | |
| 10349 | *end_op = s; |
| 10350 | |
| 10351 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); |
| 10352 | |
| 10353 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
| 10354 | if (r == i386_regtab /* %st is first entry of table */) |
| 10355 | { |
| 10356 | if (!cpu_arch_flags.bitfield.cpu8087 |
| 10357 | && !cpu_arch_flags.bitfield.cpu287 |
| 10358 | && !cpu_arch_flags.bitfield.cpu387) |
| 10359 | return (const reg_entry *) NULL; |
| 10360 | |
| 10361 | if (is_space_char (*s)) |
| 10362 | ++s; |
| 10363 | if (*s == '(') |
| 10364 | { |
| 10365 | ++s; |
| 10366 | if (is_space_char (*s)) |
| 10367 | ++s; |
| 10368 | if (*s >= '0' && *s <= '7') |
| 10369 | { |
| 10370 | int fpr = *s - '0'; |
| 10371 | ++s; |
| 10372 | if (is_space_char (*s)) |
| 10373 | ++s; |
| 10374 | if (*s == ')') |
| 10375 | { |
| 10376 | *end_op = s + 1; |
| 10377 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
| 10378 | know (r); |
| 10379 | return r + fpr; |
| 10380 | } |
| 10381 | } |
| 10382 | /* We have "%st(" then garbage. */ |
| 10383 | return (const reg_entry *) NULL; |
| 10384 | } |
| 10385 | } |
| 10386 | |
| 10387 | if (r == NULL || allow_pseudo_reg) |
| 10388 | return r; |
| 10389 | |
| 10390 | if (operand_type_all_zero (&r->reg_type)) |
| 10391 | return (const reg_entry *) NULL; |
| 10392 | |
| 10393 | if ((r->reg_type.bitfield.dword |
| 10394 | || r->reg_type.bitfield.sreg3 |
| 10395 | || r->reg_type.bitfield.control |
| 10396 | || r->reg_type.bitfield.debug |
| 10397 | || r->reg_type.bitfield.test) |
| 10398 | && !cpu_arch_flags.bitfield.cpui386) |
| 10399 | return (const reg_entry *) NULL; |
| 10400 | |
| 10401 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
| 10402 | return (const reg_entry *) NULL; |
| 10403 | |
| 10404 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
| 10405 | { |
| 10406 | if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask) |
| 10407 | return (const reg_entry *) NULL; |
| 10408 | |
| 10409 | if (!cpu_arch_flags.bitfield.cpuavx) |
| 10410 | { |
| 10411 | if (r->reg_type.bitfield.ymmword) |
| 10412 | return (const reg_entry *) NULL; |
| 10413 | |
| 10414 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
| 10415 | return (const reg_entry *) NULL; |
| 10416 | } |
| 10417 | } |
| 10418 | |
| 10419 | if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx) |
| 10420 | return (const reg_entry *) NULL; |
| 10421 | |
| 10422 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
| 10423 | if (!allow_index_reg && r->reg_num == RegIZ) |
| 10424 | return (const reg_entry *) NULL; |
| 10425 | |
| 10426 | /* Upper 16 vector registers are only available with VREX in 64bit |
| 10427 | mode, and require EVEX encoding. */ |
| 10428 | if (r->reg_flags & RegVRex) |
| 10429 | { |
| 10430 | if (!cpu_arch_flags.bitfield.cpuavx512f |
| 10431 | || flag_code != CODE_64BIT) |
| 10432 | return (const reg_entry *) NULL; |
| 10433 | |
| 10434 | i.vec_encoding = vex_encoding_evex; |
| 10435 | } |
| 10436 | |
| 10437 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
| 10438 | && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control) |
| 10439 | && flag_code != CODE_64BIT) |
| 10440 | return (const reg_entry *) NULL; |
| 10441 | |
| 10442 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
| 10443 | return (const reg_entry *) NULL; |
| 10444 | |
| 10445 | return r; |
| 10446 | } |
| 10447 | |
| 10448 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
| 10449 | |
| 10450 | static const reg_entry * |
| 10451 | parse_register (char *reg_string, char **end_op) |
| 10452 | { |
| 10453 | const reg_entry *r; |
| 10454 | |
| 10455 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) |
| 10456 | r = parse_real_register (reg_string, end_op); |
| 10457 | else |
| 10458 | r = NULL; |
| 10459 | if (!r) |
| 10460 | { |
| 10461 | char *save = input_line_pointer; |
| 10462 | char c; |
| 10463 | symbolS *symbolP; |
| 10464 | |
| 10465 | input_line_pointer = reg_string; |
| 10466 | c = get_symbol_name (®_string); |
| 10467 | symbolP = symbol_find (reg_string); |
| 10468 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
| 10469 | { |
| 10470 | const expressionS *e = symbol_get_value_expression (symbolP); |
| 10471 | |
| 10472 | know (e->X_op == O_register); |
| 10473 | know (e->X_add_number >= 0 |
| 10474 | && (valueT) e->X_add_number < i386_regtab_size); |
| 10475 | r = i386_regtab + e->X_add_number; |
| 10476 | if ((r->reg_flags & RegVRex)) |
| 10477 | i.vec_encoding = vex_encoding_evex; |
| 10478 | *end_op = input_line_pointer; |
| 10479 | } |
| 10480 | *input_line_pointer = c; |
| 10481 | input_line_pointer = save; |
| 10482 | } |
| 10483 | return r; |
| 10484 | } |
| 10485 | |
| 10486 | int |
| 10487 | i386_parse_name (char *name, expressionS *e, char *nextcharP) |
| 10488 | { |
| 10489 | const reg_entry *r; |
| 10490 | char *end = input_line_pointer; |
| 10491 | |
| 10492 | *end = *nextcharP; |
| 10493 | r = parse_register (name, &input_line_pointer); |
| 10494 | if (r && end <= input_line_pointer) |
| 10495 | { |
| 10496 | *nextcharP = *input_line_pointer; |
| 10497 | *input_line_pointer = 0; |
| 10498 | e->X_op = O_register; |
| 10499 | e->X_add_number = r - i386_regtab; |
| 10500 | return 1; |
| 10501 | } |
| 10502 | input_line_pointer = end; |
| 10503 | *end = 0; |
| 10504 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
| 10505 | } |
| 10506 | |
| 10507 | void |
| 10508 | md_operand (expressionS *e) |
| 10509 | { |
| 10510 | char *end; |
| 10511 | const reg_entry *r; |
| 10512 | |
| 10513 | switch (*input_line_pointer) |
| 10514 | { |
| 10515 | case REGISTER_PREFIX: |
| 10516 | r = parse_real_register (input_line_pointer, &end); |
| 10517 | if (r) |
| 10518 | { |
| 10519 | e->X_op = O_register; |
| 10520 | e->X_add_number = r - i386_regtab; |
| 10521 | input_line_pointer = end; |
| 10522 | } |
| 10523 | break; |
| 10524 | |
| 10525 | case '[': |
| 10526 | gas_assert (intel_syntax); |
| 10527 | end = input_line_pointer++; |
| 10528 | expression (e); |
| 10529 | if (*input_line_pointer == ']') |
| 10530 | { |
| 10531 | ++input_line_pointer; |
| 10532 | e->X_op_symbol = make_expr_symbol (e); |
| 10533 | e->X_add_symbol = NULL; |
| 10534 | e->X_add_number = 0; |
| 10535 | e->X_op = O_index; |
| 10536 | } |
| 10537 | else |
| 10538 | { |
| 10539 | e->X_op = O_absent; |
| 10540 | input_line_pointer = end; |
| 10541 | } |
| 10542 | break; |
| 10543 | } |
| 10544 | } |
| 10545 | |
| 10546 | \f |
| 10547 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 10548 | const char *md_shortopts = "kVQ:sqnO::"; |
| 10549 | #else |
| 10550 | const char *md_shortopts = "qnO::"; |
| 10551 | #endif |
| 10552 | |
| 10553 | #define OPTION_32 (OPTION_MD_BASE + 0) |
| 10554 | #define OPTION_64 (OPTION_MD_BASE + 1) |
| 10555 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) |
| 10556 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
| 10557 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) |
| 10558 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
| 10559 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) |
| 10560 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) |
| 10561 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) |
| 10562 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
| 10563 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
| 10564 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
| 10565 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
| 10566 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) |
| 10567 | #define OPTION_X32 (OPTION_MD_BASE + 14) |
| 10568 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
| 10569 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
| 10570 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) |
| 10571 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
| 10572 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
| 10573 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
| 10574 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
| 10575 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
| 10576 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) |
| 10577 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
| 10578 | |
| 10579 | struct option md_longopts[] = |
| 10580 | { |
| 10581 | {"32", no_argument, NULL, OPTION_32}, |
| 10582 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 10583 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 10584 | {"64", no_argument, NULL, OPTION_64}, |
| 10585 | #endif |
| 10586 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 10587 | {"x32", no_argument, NULL, OPTION_X32}, |
| 10588 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
| 10589 | #endif |
| 10590 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
| 10591 | {"march", required_argument, NULL, OPTION_MARCH}, |
| 10592 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
| 10593 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
| 10594 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, |
| 10595 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, |
| 10596 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, |
| 10597 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
| 10598 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
| 10599 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
| 10600 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
| 10601 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
| 10602 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
| 10603 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, |
| 10604 | # if defined (TE_PE) || defined (TE_PEP) |
| 10605 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, |
| 10606 | #endif |
| 10607 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
| 10608 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
| 10609 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
| 10610 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
| 10611 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
| 10612 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, |
| 10613 | {NULL, no_argument, NULL, 0} |
| 10614 | }; |
| 10615 | size_t md_longopts_size = sizeof (md_longopts); |
| 10616 | |
| 10617 | int |
| 10618 | md_parse_option (int c, const char *arg) |
| 10619 | { |
| 10620 | unsigned int j; |
| 10621 | char *arch, *next, *saved; |
| 10622 | |
| 10623 | switch (c) |
| 10624 | { |
| 10625 | case 'n': |
| 10626 | optimize_align_code = 0; |
| 10627 | break; |
| 10628 | |
| 10629 | case 'q': |
| 10630 | quiet_warnings = 1; |
| 10631 | break; |
| 10632 | |
| 10633 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 10634 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
| 10635 | should be emitted or not. FIXME: Not implemented. */ |
| 10636 | case 'Q': |
| 10637 | break; |
| 10638 | |
| 10639 | /* -V: SVR4 argument to print version ID. */ |
| 10640 | case 'V': |
| 10641 | print_version_id (); |
| 10642 | break; |
| 10643 | |
| 10644 | /* -k: Ignore for FreeBSD compatibility. */ |
| 10645 | case 'k': |
| 10646 | break; |
| 10647 | |
| 10648 | case 's': |
| 10649 | /* -s: On i386 Solaris, this tells the native assembler to use |
| 10650 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
| 10651 | break; |
| 10652 | |
| 10653 | case OPTION_MSHARED: |
| 10654 | shared = 1; |
| 10655 | break; |
| 10656 | #endif |
| 10657 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 10658 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 10659 | case OPTION_64: |
| 10660 | { |
| 10661 | const char **list, **l; |
| 10662 | |
| 10663 | list = bfd_target_list (); |
| 10664 | for (l = list; *l != NULL; l++) |
| 10665 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
| 10666 | || strcmp (*l, "coff-x86-64") == 0 |
| 10667 | || strcmp (*l, "pe-x86-64") == 0 |
| 10668 | || strcmp (*l, "pei-x86-64") == 0 |
| 10669 | || strcmp (*l, "mach-o-x86-64") == 0) |
| 10670 | { |
| 10671 | default_arch = "x86_64"; |
| 10672 | break; |
| 10673 | } |
| 10674 | if (*l == NULL) |
| 10675 | as_fatal (_("no compiled in support for x86_64")); |
| 10676 | free (list); |
| 10677 | } |
| 10678 | break; |
| 10679 | #endif |
| 10680 | |
| 10681 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 10682 | case OPTION_X32: |
| 10683 | if (IS_ELF) |
| 10684 | { |
| 10685 | const char **list, **l; |
| 10686 | |
| 10687 | list = bfd_target_list (); |
| 10688 | for (l = list; *l != NULL; l++) |
| 10689 | if (CONST_STRNEQ (*l, "elf32-x86-64")) |
| 10690 | { |
| 10691 | default_arch = "x86_64:32"; |
| 10692 | break; |
| 10693 | } |
| 10694 | if (*l == NULL) |
| 10695 | as_fatal (_("no compiled in support for 32bit x86_64")); |
| 10696 | free (list); |
| 10697 | } |
| 10698 | else |
| 10699 | as_fatal (_("32bit x86_64 is only supported for ELF")); |
| 10700 | break; |
| 10701 | #endif |
| 10702 | |
| 10703 | case OPTION_32: |
| 10704 | default_arch = "i386"; |
| 10705 | break; |
| 10706 | |
| 10707 | case OPTION_DIVIDE: |
| 10708 | #ifdef SVR4_COMMENT_CHARS |
| 10709 | { |
| 10710 | char *n, *t; |
| 10711 | const char *s; |
| 10712 | |
| 10713 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
| 10714 | t = n; |
| 10715 | for (s = i386_comment_chars; *s != '\0'; s++) |
| 10716 | if (*s != '/') |
| 10717 | *t++ = *s; |
| 10718 | *t = '\0'; |
| 10719 | i386_comment_chars = n; |
| 10720 | } |
| 10721 | #endif |
| 10722 | break; |
| 10723 | |
| 10724 | case OPTION_MARCH: |
| 10725 | saved = xstrdup (arg); |
| 10726 | arch = saved; |
| 10727 | /* Allow -march=+nosse. */ |
| 10728 | if (*arch == '+') |
| 10729 | arch++; |
| 10730 | do |
| 10731 | { |
| 10732 | if (*arch == '.') |
| 10733 | as_fatal (_("invalid -march= option: `%s'"), arg); |
| 10734 | next = strchr (arch, '+'); |
| 10735 | if (next) |
| 10736 | *next++ = '\0'; |
| 10737 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 10738 | { |
| 10739 | if (strcmp (arch, cpu_arch [j].name) == 0) |
| 10740 | { |
| 10741 | /* Processor. */ |
| 10742 | if (! cpu_arch[j].flags.bitfield.cpui386) |
| 10743 | continue; |
| 10744 | |
| 10745 | cpu_arch_name = cpu_arch[j].name; |
| 10746 | cpu_sub_arch_name = NULL; |
| 10747 | cpu_arch_flags = cpu_arch[j].flags; |
| 10748 | cpu_arch_isa = cpu_arch[j].type; |
| 10749 | cpu_arch_isa_flags = cpu_arch[j].flags; |
| 10750 | if (!cpu_arch_tune_set) |
| 10751 | { |
| 10752 | cpu_arch_tune = cpu_arch_isa; |
| 10753 | cpu_arch_tune_flags = cpu_arch_isa_flags; |
| 10754 | } |
| 10755 | break; |
| 10756 | } |
| 10757 | else if (*cpu_arch [j].name == '.' |
| 10758 | && strcmp (arch, cpu_arch [j].name + 1) == 0) |
| 10759 | { |
| 10760 | /* ISA extension. */ |
| 10761 | i386_cpu_flags flags; |
| 10762 | |
| 10763 | flags = cpu_flags_or (cpu_arch_flags, |
| 10764 | cpu_arch[j].flags); |
| 10765 | |
| 10766 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 10767 | { |
| 10768 | if (cpu_sub_arch_name) |
| 10769 | { |
| 10770 | char *name = cpu_sub_arch_name; |
| 10771 | cpu_sub_arch_name = concat (name, |
| 10772 | cpu_arch[j].name, |
| 10773 | (const char *) NULL); |
| 10774 | free (name); |
| 10775 | } |
| 10776 | else |
| 10777 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
| 10778 | cpu_arch_flags = flags; |
| 10779 | cpu_arch_isa_flags = flags; |
| 10780 | } |
| 10781 | else |
| 10782 | cpu_arch_isa_flags |
| 10783 | = cpu_flags_or (cpu_arch_isa_flags, |
| 10784 | cpu_arch[j].flags); |
| 10785 | break; |
| 10786 | } |
| 10787 | } |
| 10788 | |
| 10789 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 10790 | { |
| 10791 | /* Disable an ISA extension. */ |
| 10792 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
| 10793 | if (strcmp (arch, cpu_noarch [j].name) == 0) |
| 10794 | { |
| 10795 | i386_cpu_flags flags; |
| 10796 | |
| 10797 | flags = cpu_flags_and_not (cpu_arch_flags, |
| 10798 | cpu_noarch[j].flags); |
| 10799 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
| 10800 | { |
| 10801 | if (cpu_sub_arch_name) |
| 10802 | { |
| 10803 | char *name = cpu_sub_arch_name; |
| 10804 | cpu_sub_arch_name = concat (arch, |
| 10805 | (const char *) NULL); |
| 10806 | free (name); |
| 10807 | } |
| 10808 | else |
| 10809 | cpu_sub_arch_name = xstrdup (arch); |
| 10810 | cpu_arch_flags = flags; |
| 10811 | cpu_arch_isa_flags = flags; |
| 10812 | } |
| 10813 | break; |
| 10814 | } |
| 10815 | |
| 10816 | if (j >= ARRAY_SIZE (cpu_noarch)) |
| 10817 | j = ARRAY_SIZE (cpu_arch); |
| 10818 | } |
| 10819 | |
| 10820 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 10821 | as_fatal (_("invalid -march= option: `%s'"), arg); |
| 10822 | |
| 10823 | arch = next; |
| 10824 | } |
| 10825 | while (next != NULL); |
| 10826 | free (saved); |
| 10827 | break; |
| 10828 | |
| 10829 | case OPTION_MTUNE: |
| 10830 | if (*arg == '.') |
| 10831 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
| 10832 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 10833 | { |
| 10834 | if (strcmp (arg, cpu_arch [j].name) == 0) |
| 10835 | { |
| 10836 | cpu_arch_tune_set = 1; |
| 10837 | cpu_arch_tune = cpu_arch [j].type; |
| 10838 | cpu_arch_tune_flags = cpu_arch[j].flags; |
| 10839 | break; |
| 10840 | } |
| 10841 | } |
| 10842 | if (j >= ARRAY_SIZE (cpu_arch)) |
| 10843 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
| 10844 | break; |
| 10845 | |
| 10846 | case OPTION_MMNEMONIC: |
| 10847 | if (strcasecmp (arg, "att") == 0) |
| 10848 | intel_mnemonic = 0; |
| 10849 | else if (strcasecmp (arg, "intel") == 0) |
| 10850 | intel_mnemonic = 1; |
| 10851 | else |
| 10852 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
| 10853 | break; |
| 10854 | |
| 10855 | case OPTION_MSYNTAX: |
| 10856 | if (strcasecmp (arg, "att") == 0) |
| 10857 | intel_syntax = 0; |
| 10858 | else if (strcasecmp (arg, "intel") == 0) |
| 10859 | intel_syntax = 1; |
| 10860 | else |
| 10861 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
| 10862 | break; |
| 10863 | |
| 10864 | case OPTION_MINDEX_REG: |
| 10865 | allow_index_reg = 1; |
| 10866 | break; |
| 10867 | |
| 10868 | case OPTION_MNAKED_REG: |
| 10869 | allow_naked_reg = 1; |
| 10870 | break; |
| 10871 | |
| 10872 | case OPTION_MSSE2AVX: |
| 10873 | sse2avx = 1; |
| 10874 | break; |
| 10875 | |
| 10876 | case OPTION_MSSE_CHECK: |
| 10877 | if (strcasecmp (arg, "error") == 0) |
| 10878 | sse_check = check_error; |
| 10879 | else if (strcasecmp (arg, "warning") == 0) |
| 10880 | sse_check = check_warning; |
| 10881 | else if (strcasecmp (arg, "none") == 0) |
| 10882 | sse_check = check_none; |
| 10883 | else |
| 10884 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
| 10885 | break; |
| 10886 | |
| 10887 | case OPTION_MOPERAND_CHECK: |
| 10888 | if (strcasecmp (arg, "error") == 0) |
| 10889 | operand_check = check_error; |
| 10890 | else if (strcasecmp (arg, "warning") == 0) |
| 10891 | operand_check = check_warning; |
| 10892 | else if (strcasecmp (arg, "none") == 0) |
| 10893 | operand_check = check_none; |
| 10894 | else |
| 10895 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); |
| 10896 | break; |
| 10897 | |
| 10898 | case OPTION_MAVXSCALAR: |
| 10899 | if (strcasecmp (arg, "128") == 0) |
| 10900 | avxscalar = vex128; |
| 10901 | else if (strcasecmp (arg, "256") == 0) |
| 10902 | avxscalar = vex256; |
| 10903 | else |
| 10904 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
| 10905 | break; |
| 10906 | |
| 10907 | case OPTION_MADD_BND_PREFIX: |
| 10908 | add_bnd_prefix = 1; |
| 10909 | break; |
| 10910 | |
| 10911 | case OPTION_MEVEXLIG: |
| 10912 | if (strcmp (arg, "128") == 0) |
| 10913 | evexlig = evexl128; |
| 10914 | else if (strcmp (arg, "256") == 0) |
| 10915 | evexlig = evexl256; |
| 10916 | else if (strcmp (arg, "512") == 0) |
| 10917 | evexlig = evexl512; |
| 10918 | else |
| 10919 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); |
| 10920 | break; |
| 10921 | |
| 10922 | case OPTION_MEVEXRCIG: |
| 10923 | if (strcmp (arg, "rne") == 0) |
| 10924 | evexrcig = rne; |
| 10925 | else if (strcmp (arg, "rd") == 0) |
| 10926 | evexrcig = rd; |
| 10927 | else if (strcmp (arg, "ru") == 0) |
| 10928 | evexrcig = ru; |
| 10929 | else if (strcmp (arg, "rz") == 0) |
| 10930 | evexrcig = rz; |
| 10931 | else |
| 10932 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); |
| 10933 | break; |
| 10934 | |
| 10935 | case OPTION_MEVEXWIG: |
| 10936 | if (strcmp (arg, "0") == 0) |
| 10937 | evexwig = evexw0; |
| 10938 | else if (strcmp (arg, "1") == 0) |
| 10939 | evexwig = evexw1; |
| 10940 | else |
| 10941 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); |
| 10942 | break; |
| 10943 | |
| 10944 | # if defined (TE_PE) || defined (TE_PEP) |
| 10945 | case OPTION_MBIG_OBJ: |
| 10946 | use_big_obj = 1; |
| 10947 | break; |
| 10948 | #endif |
| 10949 | |
| 10950 | case OPTION_MOMIT_LOCK_PREFIX: |
| 10951 | if (strcasecmp (arg, "yes") == 0) |
| 10952 | omit_lock_prefix = 1; |
| 10953 | else if (strcasecmp (arg, "no") == 0) |
| 10954 | omit_lock_prefix = 0; |
| 10955 | else |
| 10956 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); |
| 10957 | break; |
| 10958 | |
| 10959 | case OPTION_MFENCE_AS_LOCK_ADD: |
| 10960 | if (strcasecmp (arg, "yes") == 0) |
| 10961 | avoid_fence = 1; |
| 10962 | else if (strcasecmp (arg, "no") == 0) |
| 10963 | avoid_fence = 0; |
| 10964 | else |
| 10965 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); |
| 10966 | break; |
| 10967 | |
| 10968 | case OPTION_MRELAX_RELOCATIONS: |
| 10969 | if (strcasecmp (arg, "yes") == 0) |
| 10970 | generate_relax_relocations = 1; |
| 10971 | else if (strcasecmp (arg, "no") == 0) |
| 10972 | generate_relax_relocations = 0; |
| 10973 | else |
| 10974 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); |
| 10975 | break; |
| 10976 | |
| 10977 | case OPTION_MAMD64: |
| 10978 | intel64 = 0; |
| 10979 | break; |
| 10980 | |
| 10981 | case OPTION_MINTEL64: |
| 10982 | intel64 = 1; |
| 10983 | break; |
| 10984 | |
| 10985 | case 'O': |
| 10986 | if (arg == NULL) |
| 10987 | { |
| 10988 | optimize = 1; |
| 10989 | /* Turn off -Os. */ |
| 10990 | optimize_for_space = 0; |
| 10991 | } |
| 10992 | else if (*arg == 's') |
| 10993 | { |
| 10994 | optimize_for_space = 1; |
| 10995 | /* Turn on all encoding optimizations. */ |
| 10996 | optimize = -1; |
| 10997 | } |
| 10998 | else |
| 10999 | { |
| 11000 | optimize = atoi (arg); |
| 11001 | /* Turn off -Os. */ |
| 11002 | optimize_for_space = 0; |
| 11003 | } |
| 11004 | break; |
| 11005 | |
| 11006 | default: |
| 11007 | return 0; |
| 11008 | } |
| 11009 | return 1; |
| 11010 | } |
| 11011 | |
| 11012 | #define MESSAGE_TEMPLATE \ |
| 11013 | " " |
| 11014 | |
| 11015 | static char * |
| 11016 | output_message (FILE *stream, char *p, char *message, char *start, |
| 11017 | int *left_p, const char *name, int len) |
| 11018 | { |
| 11019 | int size = sizeof (MESSAGE_TEMPLATE); |
| 11020 | int left = *left_p; |
| 11021 | |
| 11022 | /* Reserve 2 spaces for ", " or ",\0" */ |
| 11023 | left -= len + 2; |
| 11024 | |
| 11025 | /* Check if there is any room. */ |
| 11026 | if (left >= 0) |
| 11027 | { |
| 11028 | if (p != start) |
| 11029 | { |
| 11030 | *p++ = ','; |
| 11031 | *p++ = ' '; |
| 11032 | } |
| 11033 | p = mempcpy (p, name, len); |
| 11034 | } |
| 11035 | else |
| 11036 | { |
| 11037 | /* Output the current message now and start a new one. */ |
| 11038 | *p++ = ','; |
| 11039 | *p = '\0'; |
| 11040 | fprintf (stream, "%s\n", message); |
| 11041 | p = start; |
| 11042 | left = size - (start - message) - len - 2; |
| 11043 | |
| 11044 | gas_assert (left >= 0); |
| 11045 | |
| 11046 | p = mempcpy (p, name, len); |
| 11047 | } |
| 11048 | |
| 11049 | *left_p = left; |
| 11050 | return p; |
| 11051 | } |
| 11052 | |
| 11053 | static void |
| 11054 | show_arch (FILE *stream, int ext, int check) |
| 11055 | { |
| 11056 | static char message[] = MESSAGE_TEMPLATE; |
| 11057 | char *start = message + 27; |
| 11058 | char *p; |
| 11059 | int size = sizeof (MESSAGE_TEMPLATE); |
| 11060 | int left; |
| 11061 | const char *name; |
| 11062 | int len; |
| 11063 | unsigned int j; |
| 11064 | |
| 11065 | p = start; |
| 11066 | left = size - (start - message); |
| 11067 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
| 11068 | { |
| 11069 | /* Should it be skipped? */ |
| 11070 | if (cpu_arch [j].skip) |
| 11071 | continue; |
| 11072 | |
| 11073 | name = cpu_arch [j].name; |
| 11074 | len = cpu_arch [j].len; |
| 11075 | if (*name == '.') |
| 11076 | { |
| 11077 | /* It is an extension. Skip if we aren't asked to show it. */ |
| 11078 | if (ext) |
| 11079 | { |
| 11080 | name++; |
| 11081 | len--; |
| 11082 | } |
| 11083 | else |
| 11084 | continue; |
| 11085 | } |
| 11086 | else if (ext) |
| 11087 | { |
| 11088 | /* It is an processor. Skip if we show only extension. */ |
| 11089 | continue; |
| 11090 | } |
| 11091 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
| 11092 | { |
| 11093 | /* It is an impossible processor - skip. */ |
| 11094 | continue; |
| 11095 | } |
| 11096 | |
| 11097 | p = output_message (stream, p, message, start, &left, name, len); |
| 11098 | } |
| 11099 | |
| 11100 | /* Display disabled extensions. */ |
| 11101 | if (ext) |
| 11102 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
| 11103 | { |
| 11104 | name = cpu_noarch [j].name; |
| 11105 | len = cpu_noarch [j].len; |
| 11106 | p = output_message (stream, p, message, start, &left, name, |
| 11107 | len); |
| 11108 | } |
| 11109 | |
| 11110 | *p = '\0'; |
| 11111 | fprintf (stream, "%s\n", message); |
| 11112 | } |
| 11113 | |
| 11114 | void |
| 11115 | md_show_usage (FILE *stream) |
| 11116 | { |
| 11117 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11118 | fprintf (stream, _("\ |
| 11119 | -Q ignored\n\ |
| 11120 | -V print assembler version number\n\ |
| 11121 | -k ignored\n")); |
| 11122 | #endif |
| 11123 | fprintf (stream, _("\ |
| 11124 | -n Do not optimize code alignment\n\ |
| 11125 | -q quieten some warnings\n")); |
| 11126 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11127 | fprintf (stream, _("\ |
| 11128 | -s ignored\n")); |
| 11129 | #endif |
| 11130 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 11131 | || defined (TE_PE) || defined (TE_PEP)) |
| 11132 | fprintf (stream, _("\ |
| 11133 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
| 11134 | #endif |
| 11135 | #ifdef SVR4_COMMENT_CHARS |
| 11136 | fprintf (stream, _("\ |
| 11137 | --divide do not treat `/' as a comment character\n")); |
| 11138 | #else |
| 11139 | fprintf (stream, _("\ |
| 11140 | --divide ignored\n")); |
| 11141 | #endif |
| 11142 | fprintf (stream, _("\ |
| 11143 | -march=CPU[,+EXTENSION...]\n\ |
| 11144 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
| 11145 | show_arch (stream, 0, 1); |
| 11146 | fprintf (stream, _("\ |
| 11147 | EXTENSION is combination of:\n")); |
| 11148 | show_arch (stream, 1, 0); |
| 11149 | fprintf (stream, _("\ |
| 11150 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
| 11151 | show_arch (stream, 0, 0); |
| 11152 | fprintf (stream, _("\ |
| 11153 | -msse2avx encode SSE instructions with VEX prefix\n")); |
| 11154 | fprintf (stream, _("\ |
| 11155 | -msse-check=[none|error|warning]\n\ |
| 11156 | check SSE instructions\n")); |
| 11157 | fprintf (stream, _("\ |
| 11158 | -moperand-check=[none|error|warning]\n\ |
| 11159 | check operand combinations for validity\n")); |
| 11160 | fprintf (stream, _("\ |
| 11161 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
| 11162 | length\n")); |
| 11163 | fprintf (stream, _("\ |
| 11164 | -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ |
| 11165 | length\n")); |
| 11166 | fprintf (stream, _("\ |
| 11167 | -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ |
| 11168 | for EVEX.W bit ignored instructions\n")); |
| 11169 | fprintf (stream, _("\ |
| 11170 | -mevexrcig=[rne|rd|ru|rz]\n\ |
| 11171 | encode EVEX instructions with specific EVEX.RC value\n\ |
| 11172 | for SAE-only ignored instructions\n")); |
| 11173 | fprintf (stream, _("\ |
| 11174 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
| 11175 | fprintf (stream, _("\ |
| 11176 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); |
| 11177 | fprintf (stream, _("\ |
| 11178 | -mindex-reg support pseudo index registers\n")); |
| 11179 | fprintf (stream, _("\ |
| 11180 | -mnaked-reg don't require `%%' prefix for registers\n")); |
| 11181 | fprintf (stream, _("\ |
| 11182 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
| 11183 | fprintf (stream, _("\ |
| 11184 | -mshared disable branch optimization for shared code\n")); |
| 11185 | # if defined (TE_PE) || defined (TE_PEP) |
| 11186 | fprintf (stream, _("\ |
| 11187 | -mbig-obj generate big object files\n")); |
| 11188 | #endif |
| 11189 | fprintf (stream, _("\ |
| 11190 | -momit-lock-prefix=[no|yes]\n\ |
| 11191 | strip all lock prefixes\n")); |
| 11192 | fprintf (stream, _("\ |
| 11193 | -mfence-as-lock-add=[no|yes]\n\ |
| 11194 | encode lfence, mfence and sfence as\n\ |
| 11195 | lock addl $0x0, (%%{re}sp)\n")); |
| 11196 | fprintf (stream, _("\ |
| 11197 | -mrelax-relocations=[no|yes]\n\ |
| 11198 | generate relax relocations\n")); |
| 11199 | fprintf (stream, _("\ |
| 11200 | -mamd64 accept only AMD64 ISA\n")); |
| 11201 | fprintf (stream, _("\ |
| 11202 | -mintel64 accept only Intel64 ISA\n")); |
| 11203 | } |
| 11204 | |
| 11205 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
| 11206 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
| 11207 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
| 11208 | |
| 11209 | /* Pick the target format to use. */ |
| 11210 | |
| 11211 | const char * |
| 11212 | i386_target_format (void) |
| 11213 | { |
| 11214 | if (!strncmp (default_arch, "x86_64", 6)) |
| 11215 | { |
| 11216 | update_code_flag (CODE_64BIT, 1); |
| 11217 | if (default_arch[6] == '\0') |
| 11218 | x86_elf_abi = X86_64_ABI; |
| 11219 | else |
| 11220 | x86_elf_abi = X86_64_X32_ABI; |
| 11221 | } |
| 11222 | else if (!strcmp (default_arch, "i386")) |
| 11223 | update_code_flag (CODE_32BIT, 1); |
| 11224 | else if (!strcmp (default_arch, "iamcu")) |
| 11225 | { |
| 11226 | update_code_flag (CODE_32BIT, 1); |
| 11227 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) |
| 11228 | { |
| 11229 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; |
| 11230 | cpu_arch_name = "iamcu"; |
| 11231 | cpu_sub_arch_name = NULL; |
| 11232 | cpu_arch_flags = iamcu_flags; |
| 11233 | cpu_arch_isa = PROCESSOR_IAMCU; |
| 11234 | cpu_arch_isa_flags = iamcu_flags; |
| 11235 | if (!cpu_arch_tune_set) |
| 11236 | { |
| 11237 | cpu_arch_tune = cpu_arch_isa; |
| 11238 | cpu_arch_tune_flags = cpu_arch_isa_flags; |
| 11239 | } |
| 11240 | } |
| 11241 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
| 11242 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
| 11243 | cpu_arch_name); |
| 11244 | } |
| 11245 | else |
| 11246 | as_fatal (_("unknown architecture")); |
| 11247 | |
| 11248 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
| 11249 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; |
| 11250 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
| 11251 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; |
| 11252 | |
| 11253 | switch (OUTPUT_FLAVOR) |
| 11254 | { |
| 11255 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
| 11256 | case bfd_target_aout_flavour: |
| 11257 | return AOUT_TARGET_FORMAT; |
| 11258 | #endif |
| 11259 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
| 11260 | # if defined (TE_PE) || defined (TE_PEP) |
| 11261 | case bfd_target_coff_flavour: |
| 11262 | if (flag_code == CODE_64BIT) |
| 11263 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; |
| 11264 | else |
| 11265 | return "pe-i386"; |
| 11266 | # elif defined (TE_GO32) |
| 11267 | case bfd_target_coff_flavour: |
| 11268 | return "coff-go32"; |
| 11269 | # else |
| 11270 | case bfd_target_coff_flavour: |
| 11271 | return "coff-i386"; |
| 11272 | # endif |
| 11273 | #endif |
| 11274 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
| 11275 | case bfd_target_elf_flavour: |
| 11276 | { |
| 11277 | const char *format; |
| 11278 | |
| 11279 | switch (x86_elf_abi) |
| 11280 | { |
| 11281 | default: |
| 11282 | format = ELF_TARGET_FORMAT; |
| 11283 | break; |
| 11284 | case X86_64_ABI: |
| 11285 | use_rela_relocations = 1; |
| 11286 | object_64bit = 1; |
| 11287 | format = ELF_TARGET_FORMAT64; |
| 11288 | break; |
| 11289 | case X86_64_X32_ABI: |
| 11290 | use_rela_relocations = 1; |
| 11291 | object_64bit = 1; |
| 11292 | disallow_64bit_reloc = 1; |
| 11293 | format = ELF_TARGET_FORMAT32; |
| 11294 | break; |
| 11295 | } |
| 11296 | if (cpu_arch_isa == PROCESSOR_L1OM) |
| 11297 | { |
| 11298 | if (x86_elf_abi != X86_64_ABI) |
| 11299 | as_fatal (_("Intel L1OM is 64bit only")); |
| 11300 | return ELF_TARGET_L1OM_FORMAT; |
| 11301 | } |
| 11302 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
| 11303 | { |
| 11304 | if (x86_elf_abi != X86_64_ABI) |
| 11305 | as_fatal (_("Intel K1OM is 64bit only")); |
| 11306 | return ELF_TARGET_K1OM_FORMAT; |
| 11307 | } |
| 11308 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
| 11309 | { |
| 11310 | if (x86_elf_abi != I386_ABI) |
| 11311 | as_fatal (_("Intel MCU is 32bit only")); |
| 11312 | return ELF_TARGET_IAMCU_FORMAT; |
| 11313 | } |
| 11314 | else |
| 11315 | return format; |
| 11316 | } |
| 11317 | #endif |
| 11318 | #if defined (OBJ_MACH_O) |
| 11319 | case bfd_target_mach_o_flavour: |
| 11320 | if (flag_code == CODE_64BIT) |
| 11321 | { |
| 11322 | use_rela_relocations = 1; |
| 11323 | object_64bit = 1; |
| 11324 | return "mach-o-x86-64"; |
| 11325 | } |
| 11326 | else |
| 11327 | return "mach-o-i386"; |
| 11328 | #endif |
| 11329 | default: |
| 11330 | abort (); |
| 11331 | return NULL; |
| 11332 | } |
| 11333 | } |
| 11334 | |
| 11335 | #endif /* OBJ_MAYBE_ more than one */ |
| 11336 | \f |
| 11337 | symbolS * |
| 11338 | md_undefined_symbol (char *name) |
| 11339 | { |
| 11340 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
| 11341 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] |
| 11342 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] |
| 11343 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) |
| 11344 | { |
| 11345 | if (!GOT_symbol) |
| 11346 | { |
| 11347 | if (symbol_find (name)) |
| 11348 | as_bad (_("GOT already in symbol table")); |
| 11349 | GOT_symbol = symbol_new (name, undefined_section, |
| 11350 | (valueT) 0, &zero_address_frag); |
| 11351 | }; |
| 11352 | return GOT_symbol; |
| 11353 | } |
| 11354 | return 0; |
| 11355 | } |
| 11356 | |
| 11357 | /* Round up a section size to the appropriate boundary. */ |
| 11358 | |
| 11359 | valueT |
| 11360 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
| 11361 | { |
| 11362 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
| 11363 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) |
| 11364 | { |
| 11365 | /* For a.out, force the section size to be aligned. If we don't do |
| 11366 | this, BFD will align it for us, but it will not write out the |
| 11367 | final bytes of the section. This may be a bug in BFD, but it is |
| 11368 | easier to fix it here since that is how the other a.out targets |
| 11369 | work. */ |
| 11370 | int align; |
| 11371 | |
| 11372 | align = bfd_get_section_alignment (stdoutput, segment); |
| 11373 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
| 11374 | } |
| 11375 | #endif |
| 11376 | |
| 11377 | return size; |
| 11378 | } |
| 11379 | |
| 11380 | /* On the i386, PC-relative offsets are relative to the start of the |
| 11381 | next instruction. That is, the address of the offset, plus its |
| 11382 | size, since the offset is always the last part of the insn. */ |
| 11383 | |
| 11384 | long |
| 11385 | md_pcrel_from (fixS *fixP) |
| 11386 | { |
| 11387 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
| 11388 | } |
| 11389 | |
| 11390 | #ifndef I386COFF |
| 11391 | |
| 11392 | static void |
| 11393 | s_bss (int ignore ATTRIBUTE_UNUSED) |
| 11394 | { |
| 11395 | int temp; |
| 11396 | |
| 11397 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11398 | if (IS_ELF) |
| 11399 | obj_elf_section_change_hook (); |
| 11400 | #endif |
| 11401 | temp = get_absolute_expression (); |
| 11402 | subseg_set (bss_section, (subsegT) temp); |
| 11403 | demand_empty_rest_of_line (); |
| 11404 | } |
| 11405 | |
| 11406 | #endif |
| 11407 | |
| 11408 | void |
| 11409 | i386_validate_fix (fixS *fixp) |
| 11410 | { |
| 11411 | if (fixp->fx_subsy) |
| 11412 | { |
| 11413 | if (fixp->fx_subsy == GOT_symbol) |
| 11414 | { |
| 11415 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
| 11416 | { |
| 11417 | if (!object_64bit) |
| 11418 | abort (); |
| 11419 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11420 | if (fixp->fx_tcbit2) |
| 11421 | fixp->fx_r_type = (fixp->fx_tcbit |
| 11422 | ? BFD_RELOC_X86_64_REX_GOTPCRELX |
| 11423 | : BFD_RELOC_X86_64_GOTPCRELX); |
| 11424 | else |
| 11425 | #endif |
| 11426 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; |
| 11427 | } |
| 11428 | else |
| 11429 | { |
| 11430 | if (!object_64bit) |
| 11431 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
| 11432 | else |
| 11433 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; |
| 11434 | } |
| 11435 | fixp->fx_subsy = 0; |
| 11436 | } |
| 11437 | } |
| 11438 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11439 | else if (!object_64bit) |
| 11440 | { |
| 11441 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 |
| 11442 | && fixp->fx_tcbit2) |
| 11443 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; |
| 11444 | } |
| 11445 | #endif |
| 11446 | } |
| 11447 | |
| 11448 | arelent * |
| 11449 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
| 11450 | { |
| 11451 | arelent *rel; |
| 11452 | bfd_reloc_code_real_type code; |
| 11453 | |
| 11454 | switch (fixp->fx_r_type) |
| 11455 | { |
| 11456 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11457 | case BFD_RELOC_SIZE32: |
| 11458 | case BFD_RELOC_SIZE64: |
| 11459 | if (S_IS_DEFINED (fixp->fx_addsy) |
| 11460 | && !S_IS_EXTERNAL (fixp->fx_addsy)) |
| 11461 | { |
| 11462 | /* Resolve size relocation against local symbol to size of |
| 11463 | the symbol plus addend. */ |
| 11464 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; |
| 11465 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
| 11466 | && !fits_in_unsigned_long (value)) |
| 11467 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 11468 | _("symbol size computation overflow")); |
| 11469 | fixp->fx_addsy = NULL; |
| 11470 | fixp->fx_subsy = NULL; |
| 11471 | md_apply_fix (fixp, (valueT *) &value, NULL); |
| 11472 | return NULL; |
| 11473 | } |
| 11474 | #endif |
| 11475 | /* Fall through. */ |
| 11476 | |
| 11477 | case BFD_RELOC_X86_64_PLT32: |
| 11478 | case BFD_RELOC_X86_64_GOT32: |
| 11479 | case BFD_RELOC_X86_64_GOTPCREL: |
| 11480 | case BFD_RELOC_X86_64_GOTPCRELX: |
| 11481 | case BFD_RELOC_X86_64_REX_GOTPCRELX: |
| 11482 | case BFD_RELOC_386_PLT32: |
| 11483 | case BFD_RELOC_386_GOT32: |
| 11484 | case BFD_RELOC_386_GOT32X: |
| 11485 | case BFD_RELOC_386_GOTOFF: |
| 11486 | case BFD_RELOC_386_GOTPC: |
| 11487 | case BFD_RELOC_386_TLS_GD: |
| 11488 | case BFD_RELOC_386_TLS_LDM: |
| 11489 | case BFD_RELOC_386_TLS_LDO_32: |
| 11490 | case BFD_RELOC_386_TLS_IE_32: |
| 11491 | case BFD_RELOC_386_TLS_IE: |
| 11492 | case BFD_RELOC_386_TLS_GOTIE: |
| 11493 | case BFD_RELOC_386_TLS_LE_32: |
| 11494 | case BFD_RELOC_386_TLS_LE: |
| 11495 | case BFD_RELOC_386_TLS_GOTDESC: |
| 11496 | case BFD_RELOC_386_TLS_DESC_CALL: |
| 11497 | case BFD_RELOC_X86_64_TLSGD: |
| 11498 | case BFD_RELOC_X86_64_TLSLD: |
| 11499 | case BFD_RELOC_X86_64_DTPOFF32: |
| 11500 | case BFD_RELOC_X86_64_DTPOFF64: |
| 11501 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 11502 | case BFD_RELOC_X86_64_TPOFF32: |
| 11503 | case BFD_RELOC_X86_64_TPOFF64: |
| 11504 | case BFD_RELOC_X86_64_GOTOFF64: |
| 11505 | case BFD_RELOC_X86_64_GOTPC32: |
| 11506 | case BFD_RELOC_X86_64_GOT64: |
| 11507 | case BFD_RELOC_X86_64_GOTPCREL64: |
| 11508 | case BFD_RELOC_X86_64_GOTPC64: |
| 11509 | case BFD_RELOC_X86_64_GOTPLT64: |
| 11510 | case BFD_RELOC_X86_64_PLTOFF64: |
| 11511 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 11512 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 11513 | case BFD_RELOC_RVA: |
| 11514 | case BFD_RELOC_VTABLE_ENTRY: |
| 11515 | case BFD_RELOC_VTABLE_INHERIT: |
| 11516 | #ifdef TE_PE |
| 11517 | case BFD_RELOC_32_SECREL: |
| 11518 | #endif |
| 11519 | code = fixp->fx_r_type; |
| 11520 | break; |
| 11521 | case BFD_RELOC_X86_64_32S: |
| 11522 | if (!fixp->fx_pcrel) |
| 11523 | { |
| 11524 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ |
| 11525 | code = fixp->fx_r_type; |
| 11526 | break; |
| 11527 | } |
| 11528 | /* Fall through. */ |
| 11529 | default: |
| 11530 | if (fixp->fx_pcrel) |
| 11531 | { |
| 11532 | switch (fixp->fx_size) |
| 11533 | { |
| 11534 | default: |
| 11535 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 11536 | _("can not do %d byte pc-relative relocation"), |
| 11537 | fixp->fx_size); |
| 11538 | code = BFD_RELOC_32_PCREL; |
| 11539 | break; |
| 11540 | case 1: code = BFD_RELOC_8_PCREL; break; |
| 11541 | case 2: code = BFD_RELOC_16_PCREL; break; |
| 11542 | case 4: code = BFD_RELOC_32_PCREL; break; |
| 11543 | #ifdef BFD64 |
| 11544 | case 8: code = BFD_RELOC_64_PCREL; break; |
| 11545 | #endif |
| 11546 | } |
| 11547 | } |
| 11548 | else |
| 11549 | { |
| 11550 | switch (fixp->fx_size) |
| 11551 | { |
| 11552 | default: |
| 11553 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 11554 | _("can not do %d byte relocation"), |
| 11555 | fixp->fx_size); |
| 11556 | code = BFD_RELOC_32; |
| 11557 | break; |
| 11558 | case 1: code = BFD_RELOC_8; break; |
| 11559 | case 2: code = BFD_RELOC_16; break; |
| 11560 | case 4: code = BFD_RELOC_32; break; |
| 11561 | #ifdef BFD64 |
| 11562 | case 8: code = BFD_RELOC_64; break; |
| 11563 | #endif |
| 11564 | } |
| 11565 | } |
| 11566 | break; |
| 11567 | } |
| 11568 | |
| 11569 | if ((code == BFD_RELOC_32 |
| 11570 | || code == BFD_RELOC_32_PCREL |
| 11571 | || code == BFD_RELOC_X86_64_32S) |
| 11572 | && GOT_symbol |
| 11573 | && fixp->fx_addsy == GOT_symbol) |
| 11574 | { |
| 11575 | if (!object_64bit) |
| 11576 | code = BFD_RELOC_386_GOTPC; |
| 11577 | else |
| 11578 | code = BFD_RELOC_X86_64_GOTPC32; |
| 11579 | } |
| 11580 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
| 11581 | && GOT_symbol |
| 11582 | && fixp->fx_addsy == GOT_symbol) |
| 11583 | { |
| 11584 | code = BFD_RELOC_X86_64_GOTPC64; |
| 11585 | } |
| 11586 | |
| 11587 | rel = XNEW (arelent); |
| 11588 | rel->sym_ptr_ptr = XNEW (asymbol *); |
| 11589 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 11590 | |
| 11591 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 11592 | |
| 11593 | if (!use_rela_relocations) |
| 11594 | { |
| 11595 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the |
| 11596 | vtable entry to be used in the relocation's section offset. */ |
| 11597 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 11598 | rel->address = fixp->fx_offset; |
| 11599 | #if defined (OBJ_COFF) && defined (TE_PE) |
| 11600 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) |
| 11601 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); |
| 11602 | else |
| 11603 | #endif |
| 11604 | rel->addend = 0; |
| 11605 | } |
| 11606 | /* Use the rela in 64bit mode. */ |
| 11607 | else |
| 11608 | { |
| 11609 | if (disallow_64bit_reloc) |
| 11610 | switch (code) |
| 11611 | { |
| 11612 | case BFD_RELOC_X86_64_DTPOFF64: |
| 11613 | case BFD_RELOC_X86_64_TPOFF64: |
| 11614 | case BFD_RELOC_64_PCREL: |
| 11615 | case BFD_RELOC_X86_64_GOTOFF64: |
| 11616 | case BFD_RELOC_X86_64_GOT64: |
| 11617 | case BFD_RELOC_X86_64_GOTPCREL64: |
| 11618 | case BFD_RELOC_X86_64_GOTPC64: |
| 11619 | case BFD_RELOC_X86_64_GOTPLT64: |
| 11620 | case BFD_RELOC_X86_64_PLTOFF64: |
| 11621 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 11622 | _("cannot represent relocation type %s in x32 mode"), |
| 11623 | bfd_get_reloc_code_name (code)); |
| 11624 | break; |
| 11625 | default: |
| 11626 | break; |
| 11627 | } |
| 11628 | |
| 11629 | if (!fixp->fx_pcrel) |
| 11630 | rel->addend = fixp->fx_offset; |
| 11631 | else |
| 11632 | switch (code) |
| 11633 | { |
| 11634 | case BFD_RELOC_X86_64_PLT32: |
| 11635 | case BFD_RELOC_X86_64_GOT32: |
| 11636 | case BFD_RELOC_X86_64_GOTPCREL: |
| 11637 | case BFD_RELOC_X86_64_GOTPCRELX: |
| 11638 | case BFD_RELOC_X86_64_REX_GOTPCRELX: |
| 11639 | case BFD_RELOC_X86_64_TLSGD: |
| 11640 | case BFD_RELOC_X86_64_TLSLD: |
| 11641 | case BFD_RELOC_X86_64_GOTTPOFF: |
| 11642 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
| 11643 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
| 11644 | rel->addend = fixp->fx_offset - fixp->fx_size; |
| 11645 | break; |
| 11646 | default: |
| 11647 | rel->addend = (section->vma |
| 11648 | - fixp->fx_size |
| 11649 | + fixp->fx_addnumber |
| 11650 | + md_pcrel_from (fixp)); |
| 11651 | break; |
| 11652 | } |
| 11653 | } |
| 11654 | |
| 11655 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 11656 | if (rel->howto == NULL) |
| 11657 | { |
| 11658 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 11659 | _("cannot represent relocation type %s"), |
| 11660 | bfd_get_reloc_code_name (code)); |
| 11661 | /* Set howto to a garbage value so that we can keep going. */ |
| 11662 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); |
| 11663 | gas_assert (rel->howto != NULL); |
| 11664 | } |
| 11665 | |
| 11666 | return rel; |
| 11667 | } |
| 11668 | |
| 11669 | #include "tc-i386-intel.c" |
| 11670 | |
| 11671 | void |
| 11672 | tc_x86_parse_to_dw2regnum (expressionS *exp) |
| 11673 | { |
| 11674 | int saved_naked_reg; |
| 11675 | char saved_register_dot; |
| 11676 | |
| 11677 | saved_naked_reg = allow_naked_reg; |
| 11678 | allow_naked_reg = 1; |
| 11679 | saved_register_dot = register_chars['.']; |
| 11680 | register_chars['.'] = '.'; |
| 11681 | allow_pseudo_reg = 1; |
| 11682 | expression_and_evaluate (exp); |
| 11683 | allow_pseudo_reg = 0; |
| 11684 | register_chars['.'] = saved_register_dot; |
| 11685 | allow_naked_reg = saved_naked_reg; |
| 11686 | |
| 11687 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
| 11688 | { |
| 11689 | if ((addressT) exp->X_add_number < i386_regtab_size) |
| 11690 | { |
| 11691 | exp->X_op = O_constant; |
| 11692 | exp->X_add_number = i386_regtab[exp->X_add_number] |
| 11693 | .dw2_regnum[flag_code >> 1]; |
| 11694 | } |
| 11695 | else |
| 11696 | exp->X_op = O_illegal; |
| 11697 | } |
| 11698 | } |
| 11699 | |
| 11700 | void |
| 11701 | tc_x86_frame_initial_instructions (void) |
| 11702 | { |
| 11703 | static unsigned int sp_regno[2]; |
| 11704 | |
| 11705 | if (!sp_regno[flag_code >> 1]) |
| 11706 | { |
| 11707 | char *saved_input = input_line_pointer; |
| 11708 | char sp[][4] = {"esp", "rsp"}; |
| 11709 | expressionS exp; |
| 11710 | |
| 11711 | input_line_pointer = sp[flag_code >> 1]; |
| 11712 | tc_x86_parse_to_dw2regnum (&exp); |
| 11713 | gas_assert (exp.X_op == O_constant); |
| 11714 | sp_regno[flag_code >> 1] = exp.X_add_number; |
| 11715 | input_line_pointer = saved_input; |
| 11716 | } |
| 11717 | |
| 11718 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
| 11719 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
| 11720 | } |
| 11721 | |
| 11722 | int |
| 11723 | x86_dwarf2_addr_size (void) |
| 11724 | { |
| 11725 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
| 11726 | if (x86_elf_abi == X86_64_X32_ABI) |
| 11727 | return 4; |
| 11728 | #endif |
| 11729 | return bfd_arch_bits_per_address (stdoutput) / 8; |
| 11730 | } |
| 11731 | |
| 11732 | int |
| 11733 | i386_elf_section_type (const char *str, size_t len) |
| 11734 | { |
| 11735 | if (flag_code == CODE_64BIT |
| 11736 | && len == sizeof ("unwind") - 1 |
| 11737 | && strncmp (str, "unwind", 6) == 0) |
| 11738 | return SHT_X86_64_UNWIND; |
| 11739 | |
| 11740 | return -1; |
| 11741 | } |
| 11742 | |
| 11743 | #ifdef TE_SOLARIS |
| 11744 | void |
| 11745 | i386_solaris_fix_up_eh_frame (segT sec) |
| 11746 | { |
| 11747 | if (flag_code == CODE_64BIT) |
| 11748 | elf_section_type (sec) = SHT_X86_64_UNWIND; |
| 11749 | } |
| 11750 | #endif |
| 11751 | |
| 11752 | #ifdef TE_PE |
| 11753 | void |
| 11754 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
| 11755 | { |
| 11756 | expressionS exp; |
| 11757 | |
| 11758 | exp.X_op = O_secrel; |
| 11759 | exp.X_add_symbol = symbol; |
| 11760 | exp.X_add_number = 0; |
| 11761 | emit_expr (&exp, size); |
| 11762 | } |
| 11763 | #endif |
| 11764 | |
| 11765 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11766 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ |
| 11767 | |
| 11768 | bfd_vma |
| 11769 | x86_64_section_letter (int letter, const char **ptr_msg) |
| 11770 | { |
| 11771 | if (flag_code == CODE_64BIT) |
| 11772 | { |
| 11773 | if (letter == 'l') |
| 11774 | return SHF_X86_64_LARGE; |
| 11775 | |
| 11776 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
| 11777 | } |
| 11778 | else |
| 11779 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
| 11780 | return -1; |
| 11781 | } |
| 11782 | |
| 11783 | bfd_vma |
| 11784 | x86_64_section_word (char *str, size_t len) |
| 11785 | { |
| 11786 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
| 11787 | return SHF_X86_64_LARGE; |
| 11788 | |
| 11789 | return -1; |
| 11790 | } |
| 11791 | |
| 11792 | static void |
| 11793 | handle_large_common (int small ATTRIBUTE_UNUSED) |
| 11794 | { |
| 11795 | if (flag_code != CODE_64BIT) |
| 11796 | { |
| 11797 | s_comm_internal (0, elf_common_parse); |
| 11798 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); |
| 11799 | } |
| 11800 | else |
| 11801 | { |
| 11802 | static segT lbss_section; |
| 11803 | asection *saved_com_section_ptr = elf_com_section_ptr; |
| 11804 | asection *saved_bss_section = bss_section; |
| 11805 | |
| 11806 | if (lbss_section == NULL) |
| 11807 | { |
| 11808 | flagword applicable; |
| 11809 | segT seg = now_seg; |
| 11810 | subsegT subseg = now_subseg; |
| 11811 | |
| 11812 | /* The .lbss section is for local .largecomm symbols. */ |
| 11813 | lbss_section = subseg_new (".lbss", 0); |
| 11814 | applicable = bfd_applicable_section_flags (stdoutput); |
| 11815 | bfd_set_section_flags (stdoutput, lbss_section, |
| 11816 | applicable & SEC_ALLOC); |
| 11817 | seg_info (lbss_section)->bss = 1; |
| 11818 | |
| 11819 | subseg_set (seg, subseg); |
| 11820 | } |
| 11821 | |
| 11822 | elf_com_section_ptr = &_bfd_elf_large_com_section; |
| 11823 | bss_section = lbss_section; |
| 11824 | |
| 11825 | s_comm_internal (0, elf_common_parse); |
| 11826 | |
| 11827 | elf_com_section_ptr = saved_com_section_ptr; |
| 11828 | bss_section = saved_bss_section; |
| 11829 | } |
| 11830 | } |
| 11831 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |