| 1 | /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. |
| 2 | Copyright 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
| 3 | Contributed by David Mosberger-Tang <davidm@hpl.hp.com> |
| 4 | |
| 5 | This file is part of GAS, the GNU Assembler. |
| 6 | |
| 7 | GAS is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | GAS is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to |
| 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | /* |
| 23 | TODO: |
| 24 | |
| 25 | - optional operands |
| 26 | - directives: |
| 27 | .eb |
| 28 | .estate |
| 29 | .lb |
| 30 | .popsection |
| 31 | .previous |
| 32 | .psr |
| 33 | .pushsection |
| 34 | - labels are wrong if automatic alignment is introduced |
| 35 | (e.g., checkout the second real10 definition in test-data.s) |
| 36 | - DV-related stuff: |
| 37 | <reg>.safe_across_calls and any other DV-related directives I don't |
| 38 | have documentation for. |
| 39 | verify mod-sched-brs reads/writes are checked/marked (and other |
| 40 | notes) |
| 41 | |
| 42 | */ |
| 43 | |
| 44 | #include "as.h" |
| 45 | #include "safe-ctype.h" |
| 46 | #include "dwarf2dbg.h" |
| 47 | #include "subsegs.h" |
| 48 | |
| 49 | #include "opcode/ia64.h" |
| 50 | |
| 51 | #include "elf/ia64.h" |
| 52 | |
| 53 | #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) |
| 54 | #define MIN(a,b) ((a) < (b) ? (a) : (b)) |
| 55 | |
| 56 | #define NUM_SLOTS 4 |
| 57 | #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] |
| 58 | #define CURR_SLOT md.slot[md.curr_slot] |
| 59 | |
| 60 | #define O_pseudo_fixup (O_max + 1) |
| 61 | |
| 62 | enum special_section |
| 63 | { |
| 64 | /* IA-64 ABI section pseudo-ops. */ |
| 65 | SPECIAL_SECTION_BSS = 0, |
| 66 | SPECIAL_SECTION_SBSS, |
| 67 | SPECIAL_SECTION_SDATA, |
| 68 | SPECIAL_SECTION_RODATA, |
| 69 | SPECIAL_SECTION_COMMENT, |
| 70 | SPECIAL_SECTION_UNWIND, |
| 71 | SPECIAL_SECTION_UNWIND_INFO, |
| 72 | /* HPUX specific section pseudo-ops. */ |
| 73 | SPECIAL_SECTION_INIT_ARRAY, |
| 74 | SPECIAL_SECTION_FINI_ARRAY, |
| 75 | }; |
| 76 | |
| 77 | enum reloc_func |
| 78 | { |
| 79 | FUNC_DTP_MODULE, |
| 80 | FUNC_DTP_RELATIVE, |
| 81 | FUNC_FPTR_RELATIVE, |
| 82 | FUNC_GP_RELATIVE, |
| 83 | FUNC_LT_RELATIVE, |
| 84 | FUNC_LT_RELATIVE_X, |
| 85 | FUNC_PC_RELATIVE, |
| 86 | FUNC_PLT_RELATIVE, |
| 87 | FUNC_SEC_RELATIVE, |
| 88 | FUNC_SEG_RELATIVE, |
| 89 | FUNC_TP_RELATIVE, |
| 90 | FUNC_LTV_RELATIVE, |
| 91 | FUNC_LT_FPTR_RELATIVE, |
| 92 | FUNC_LT_DTP_MODULE, |
| 93 | FUNC_LT_DTP_RELATIVE, |
| 94 | FUNC_LT_TP_RELATIVE, |
| 95 | FUNC_IPLT_RELOC, |
| 96 | }; |
| 97 | |
| 98 | enum reg_symbol |
| 99 | { |
| 100 | REG_GR = 0, |
| 101 | REG_FR = (REG_GR + 128), |
| 102 | REG_AR = (REG_FR + 128), |
| 103 | REG_CR = (REG_AR + 128), |
| 104 | REG_P = (REG_CR + 128), |
| 105 | REG_BR = (REG_P + 64), |
| 106 | REG_IP = (REG_BR + 8), |
| 107 | REG_CFM, |
| 108 | REG_PR, |
| 109 | REG_PR_ROT, |
| 110 | REG_PSR, |
| 111 | REG_PSR_L, |
| 112 | REG_PSR_UM, |
| 113 | /* The following are pseudo-registers for use by gas only. */ |
| 114 | IND_CPUID, |
| 115 | IND_DBR, |
| 116 | IND_DTR, |
| 117 | IND_ITR, |
| 118 | IND_IBR, |
| 119 | IND_MEM, |
| 120 | IND_MSR, |
| 121 | IND_PKR, |
| 122 | IND_PMC, |
| 123 | IND_PMD, |
| 124 | IND_RR, |
| 125 | /* The following pseudo-registers are used for unwind directives only: */ |
| 126 | REG_PSP, |
| 127 | REG_PRIUNAT, |
| 128 | REG_NUM |
| 129 | }; |
| 130 | |
| 131 | enum dynreg_type |
| 132 | { |
| 133 | DYNREG_GR = 0, /* dynamic general purpose register */ |
| 134 | DYNREG_FR, /* dynamic floating point register */ |
| 135 | DYNREG_PR, /* dynamic predicate register */ |
| 136 | DYNREG_NUM_TYPES |
| 137 | }; |
| 138 | |
| 139 | enum operand_match_result |
| 140 | { |
| 141 | OPERAND_MATCH, |
| 142 | OPERAND_OUT_OF_RANGE, |
| 143 | OPERAND_MISMATCH |
| 144 | }; |
| 145 | |
| 146 | /* On the ia64, we can't know the address of a text label until the |
| 147 | instructions are packed into a bundle. To handle this, we keep |
| 148 | track of the list of labels that appear in front of each |
| 149 | instruction. */ |
| 150 | struct label_fix |
| 151 | { |
| 152 | struct label_fix *next; |
| 153 | struct symbol *sym; |
| 154 | }; |
| 155 | |
| 156 | extern int target_big_endian; |
| 157 | |
| 158 | void (*ia64_number_to_chars) PARAMS ((char *, valueT, int)); |
| 159 | |
| 160 | static void ia64_float_to_chars_bigendian |
| 161 | PARAMS ((char *, LITTLENUM_TYPE *, int)); |
| 162 | static void ia64_float_to_chars_littleendian |
| 163 | PARAMS ((char *, LITTLENUM_TYPE *, int)); |
| 164 | static void (*ia64_float_to_chars) |
| 165 | PARAMS ((char *, LITTLENUM_TYPE *, int)); |
| 166 | |
| 167 | static struct hash_control *alias_hash; |
| 168 | static struct hash_control *alias_name_hash; |
| 169 | static struct hash_control *secalias_hash; |
| 170 | static struct hash_control *secalias_name_hash; |
| 171 | |
| 172 | /* Characters which always start a comment. */ |
| 173 | const char comment_chars[] = ""; |
| 174 | |
| 175 | /* Characters which start a comment at the beginning of a line. */ |
| 176 | const char line_comment_chars[] = "#"; |
| 177 | |
| 178 | /* Characters which may be used to separate multiple commands on a |
| 179 | single line. */ |
| 180 | const char line_separator_chars[] = ";"; |
| 181 | |
| 182 | /* Characters which are used to indicate an exponent in a floating |
| 183 | point number. */ |
| 184 | const char EXP_CHARS[] = "eE"; |
| 185 | |
| 186 | /* Characters which mean that a number is a floating point constant, |
| 187 | as in 0d1.0. */ |
| 188 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
| 189 | |
| 190 | /* ia64-specific option processing: */ |
| 191 | |
| 192 | const char *md_shortopts = "m:N:x::"; |
| 193 | |
| 194 | struct option md_longopts[] = |
| 195 | { |
| 196 | #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) |
| 197 | {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, |
| 198 | #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) |
| 199 | {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} |
| 200 | }; |
| 201 | |
| 202 | size_t md_longopts_size = sizeof (md_longopts); |
| 203 | |
| 204 | static struct |
| 205 | { |
| 206 | struct hash_control *pseudo_hash; /* pseudo opcode hash table */ |
| 207 | struct hash_control *reg_hash; /* register name hash table */ |
| 208 | struct hash_control *dynreg_hash; /* dynamic register hash table */ |
| 209 | struct hash_control *const_hash; /* constant hash table */ |
| 210 | struct hash_control *entry_hash; /* code entry hint hash table */ |
| 211 | |
| 212 | symbolS *regsym[REG_NUM]; |
| 213 | |
| 214 | /* If X_op is != O_absent, the registername for the instruction's |
| 215 | qualifying predicate. If NULL, p0 is assumed for instructions |
| 216 | that are predicatable. */ |
| 217 | expressionS qp; |
| 218 | |
| 219 | unsigned int |
| 220 | manual_bundling : 1, |
| 221 | debug_dv: 1, |
| 222 | detect_dv: 1, |
| 223 | explicit_mode : 1, /* which mode we're in */ |
| 224 | default_explicit_mode : 1, /* which mode is the default */ |
| 225 | mode_explicitly_set : 1, /* was the current mode explicitly set? */ |
| 226 | auto_align : 1, |
| 227 | keep_pending_output : 1; |
| 228 | |
| 229 | /* Each bundle consists of up to three instructions. We keep |
| 230 | track of four most recent instructions so we can correctly set |
| 231 | the end_of_insn_group for the last instruction in a bundle. */ |
| 232 | int curr_slot; |
| 233 | int num_slots_in_use; |
| 234 | struct slot |
| 235 | { |
| 236 | unsigned int |
| 237 | end_of_insn_group : 1, |
| 238 | manual_bundling_on : 1, |
| 239 | manual_bundling_off : 1; |
| 240 | signed char user_template; /* user-selected template, if any */ |
| 241 | unsigned char qp_regno; /* qualifying predicate */ |
| 242 | /* This duplicates a good fraction of "struct fix" but we |
| 243 | can't use a "struct fix" instead since we can't call |
| 244 | fix_new_exp() until we know the address of the instruction. */ |
| 245 | int num_fixups; |
| 246 | struct insn_fix |
| 247 | { |
| 248 | bfd_reloc_code_real_type code; |
| 249 | enum ia64_opnd opnd; /* type of operand in need of fix */ |
| 250 | unsigned int is_pcrel : 1; /* is operand pc-relative? */ |
| 251 | expressionS expr; /* the value to be inserted */ |
| 252 | } |
| 253 | fixup[2]; /* at most two fixups per insn */ |
| 254 | struct ia64_opcode *idesc; |
| 255 | struct label_fix *label_fixups; |
| 256 | struct label_fix *tag_fixups; |
| 257 | struct unw_rec_list *unwind_record; /* Unwind directive. */ |
| 258 | expressionS opnd[6]; |
| 259 | char *src_file; |
| 260 | unsigned int src_line; |
| 261 | struct dwarf2_line_info debug_line; |
| 262 | } |
| 263 | slot[NUM_SLOTS]; |
| 264 | |
| 265 | segT last_text_seg; |
| 266 | |
| 267 | struct dynreg |
| 268 | { |
| 269 | struct dynreg *next; /* next dynamic register */ |
| 270 | const char *name; |
| 271 | unsigned short base; /* the base register number */ |
| 272 | unsigned short num_regs; /* # of registers in this set */ |
| 273 | } |
| 274 | *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; |
| 275 | |
| 276 | flagword flags; /* ELF-header flags */ |
| 277 | |
| 278 | struct mem_offset { |
| 279 | unsigned hint:1; /* is this hint currently valid? */ |
| 280 | bfd_vma offset; /* mem.offset offset */ |
| 281 | bfd_vma base; /* mem.offset base */ |
| 282 | } mem_offset; |
| 283 | |
| 284 | int path; /* number of alt. entry points seen */ |
| 285 | const char **entry_labels; /* labels of all alternate paths in |
| 286 | the current DV-checking block. */ |
| 287 | int maxpaths; /* size currently allocated for |
| 288 | entry_labels */ |
| 289 | /* Support for hardware errata workarounds. */ |
| 290 | |
| 291 | /* Record data about the last three insn groups. */ |
| 292 | struct group |
| 293 | { |
| 294 | /* B-step workaround. |
| 295 | For each predicate register, this is set if the corresponding insn |
| 296 | group conditionally sets this register with one of the affected |
| 297 | instructions. */ |
| 298 | int p_reg_set[64]; |
| 299 | /* B-step workaround. |
| 300 | For each general register, this is set if the corresponding insn |
| 301 | a) is conditional one one of the predicate registers for which |
| 302 | P_REG_SET is 1 in the corresponding entry of the previous group, |
| 303 | b) sets this general register with one of the affected |
| 304 | instructions. */ |
| 305 | int g_reg_set_conditionally[128]; |
| 306 | } last_groups[3]; |
| 307 | int group_idx; |
| 308 | |
| 309 | int pointer_size; /* size in bytes of a pointer */ |
| 310 | int pointer_size_shift; /* shift size of a pointer for alignment */ |
| 311 | } |
| 312 | md; |
| 313 | |
| 314 | /* application registers: */ |
| 315 | |
| 316 | #define AR_K0 0 |
| 317 | #define AR_K7 7 |
| 318 | #define AR_RSC 16 |
| 319 | #define AR_BSP 17 |
| 320 | #define AR_BSPSTORE 18 |
| 321 | #define AR_RNAT 19 |
| 322 | #define AR_UNAT 36 |
| 323 | #define AR_FPSR 40 |
| 324 | #define AR_ITC 44 |
| 325 | #define AR_PFS 64 |
| 326 | #define AR_LC 65 |
| 327 | |
| 328 | static const struct |
| 329 | { |
| 330 | const char *name; |
| 331 | int regnum; |
| 332 | } |
| 333 | ar[] = |
| 334 | { |
| 335 | {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, |
| 336 | {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, |
| 337 | {"ar.rsc", 16}, {"ar.bsp", 17}, |
| 338 | {"ar.bspstore", 18}, {"ar.rnat", 19}, |
| 339 | {"ar.fcr", 21}, {"ar.eflag", 24}, |
| 340 | {"ar.csd", 25}, {"ar.ssd", 26}, |
| 341 | {"ar.cflg", 27}, {"ar.fsr", 28}, |
| 342 | {"ar.fir", 29}, {"ar.fdr", 30}, |
| 343 | {"ar.ccv", 32}, {"ar.unat", 36}, |
| 344 | {"ar.fpsr", 40}, {"ar.itc", 44}, |
| 345 | {"ar.pfs", 64}, {"ar.lc", 65}, |
| 346 | {"ar.ec", 66}, |
| 347 | }; |
| 348 | |
| 349 | #define CR_IPSR 16 |
| 350 | #define CR_ISR 17 |
| 351 | #define CR_IIP 19 |
| 352 | #define CR_IFA 20 |
| 353 | #define CR_ITIR 21 |
| 354 | #define CR_IIPA 22 |
| 355 | #define CR_IFS 23 |
| 356 | #define CR_IIM 24 |
| 357 | #define CR_IHA 25 |
| 358 | #define CR_IVR 65 |
| 359 | #define CR_TPR 66 |
| 360 | #define CR_EOI 67 |
| 361 | #define CR_IRR0 68 |
| 362 | #define CR_IRR3 71 |
| 363 | #define CR_LRR0 80 |
| 364 | #define CR_LRR1 81 |
| 365 | |
| 366 | /* control registers: */ |
| 367 | static const struct |
| 368 | { |
| 369 | const char *name; |
| 370 | int regnum; |
| 371 | } |
| 372 | cr[] = |
| 373 | { |
| 374 | {"cr.dcr", 0}, |
| 375 | {"cr.itm", 1}, |
| 376 | {"cr.iva", 2}, |
| 377 | {"cr.pta", 8}, |
| 378 | {"cr.gpta", 9}, |
| 379 | {"cr.ipsr", 16}, |
| 380 | {"cr.isr", 17}, |
| 381 | {"cr.iip", 19}, |
| 382 | {"cr.ifa", 20}, |
| 383 | {"cr.itir", 21}, |
| 384 | {"cr.iipa", 22}, |
| 385 | {"cr.ifs", 23}, |
| 386 | {"cr.iim", 24}, |
| 387 | {"cr.iha", 25}, |
| 388 | {"cr.lid", 64}, |
| 389 | {"cr.ivr", 65}, |
| 390 | {"cr.tpr", 66}, |
| 391 | {"cr.eoi", 67}, |
| 392 | {"cr.irr0", 68}, |
| 393 | {"cr.irr1", 69}, |
| 394 | {"cr.irr2", 70}, |
| 395 | {"cr.irr3", 71}, |
| 396 | {"cr.itv", 72}, |
| 397 | {"cr.pmv", 73}, |
| 398 | {"cr.cmcv", 74}, |
| 399 | {"cr.lrr0", 80}, |
| 400 | {"cr.lrr1", 81} |
| 401 | }; |
| 402 | |
| 403 | #define PSR_MFL 4 |
| 404 | #define PSR_IC 13 |
| 405 | #define PSR_DFL 18 |
| 406 | #define PSR_CPL 32 |
| 407 | |
| 408 | static const struct const_desc |
| 409 | { |
| 410 | const char *name; |
| 411 | valueT value; |
| 412 | } |
| 413 | const_bits[] = |
| 414 | { |
| 415 | /* PSR constant masks: */ |
| 416 | |
| 417 | /* 0: reserved */ |
| 418 | {"psr.be", ((valueT) 1) << 1}, |
| 419 | {"psr.up", ((valueT) 1) << 2}, |
| 420 | {"psr.ac", ((valueT) 1) << 3}, |
| 421 | {"psr.mfl", ((valueT) 1) << 4}, |
| 422 | {"psr.mfh", ((valueT) 1) << 5}, |
| 423 | /* 6-12: reserved */ |
| 424 | {"psr.ic", ((valueT) 1) << 13}, |
| 425 | {"psr.i", ((valueT) 1) << 14}, |
| 426 | {"psr.pk", ((valueT) 1) << 15}, |
| 427 | /* 16: reserved */ |
| 428 | {"psr.dt", ((valueT) 1) << 17}, |
| 429 | {"psr.dfl", ((valueT) 1) << 18}, |
| 430 | {"psr.dfh", ((valueT) 1) << 19}, |
| 431 | {"psr.sp", ((valueT) 1) << 20}, |
| 432 | {"psr.pp", ((valueT) 1) << 21}, |
| 433 | {"psr.di", ((valueT) 1) << 22}, |
| 434 | {"psr.si", ((valueT) 1) << 23}, |
| 435 | {"psr.db", ((valueT) 1) << 24}, |
| 436 | {"psr.lp", ((valueT) 1) << 25}, |
| 437 | {"psr.tb", ((valueT) 1) << 26}, |
| 438 | {"psr.rt", ((valueT) 1) << 27}, |
| 439 | /* 28-31: reserved */ |
| 440 | /* 32-33: cpl (current privilege level) */ |
| 441 | {"psr.is", ((valueT) 1) << 34}, |
| 442 | {"psr.mc", ((valueT) 1) << 35}, |
| 443 | {"psr.it", ((valueT) 1) << 36}, |
| 444 | {"psr.id", ((valueT) 1) << 37}, |
| 445 | {"psr.da", ((valueT) 1) << 38}, |
| 446 | {"psr.dd", ((valueT) 1) << 39}, |
| 447 | {"psr.ss", ((valueT) 1) << 40}, |
| 448 | /* 41-42: ri (restart instruction) */ |
| 449 | {"psr.ed", ((valueT) 1) << 43}, |
| 450 | {"psr.bn", ((valueT) 1) << 44}, |
| 451 | }; |
| 452 | |
| 453 | /* indirect register-sets/memory: */ |
| 454 | |
| 455 | static const struct |
| 456 | { |
| 457 | const char *name; |
| 458 | int regnum; |
| 459 | } |
| 460 | indirect_reg[] = |
| 461 | { |
| 462 | { "CPUID", IND_CPUID }, |
| 463 | { "cpuid", IND_CPUID }, |
| 464 | { "dbr", IND_DBR }, |
| 465 | { "dtr", IND_DTR }, |
| 466 | { "itr", IND_ITR }, |
| 467 | { "ibr", IND_IBR }, |
| 468 | { "msr", IND_MSR }, |
| 469 | { "pkr", IND_PKR }, |
| 470 | { "pmc", IND_PMC }, |
| 471 | { "pmd", IND_PMD }, |
| 472 | { "rr", IND_RR }, |
| 473 | }; |
| 474 | |
| 475 | /* Pseudo functions used to indicate relocation types (these functions |
| 476 | start with an at sign (@). */ |
| 477 | static struct |
| 478 | { |
| 479 | const char *name; |
| 480 | enum pseudo_type |
| 481 | { |
| 482 | PSEUDO_FUNC_NONE, |
| 483 | PSEUDO_FUNC_RELOC, |
| 484 | PSEUDO_FUNC_CONST, |
| 485 | PSEUDO_FUNC_REG, |
| 486 | PSEUDO_FUNC_FLOAT |
| 487 | } |
| 488 | type; |
| 489 | union |
| 490 | { |
| 491 | unsigned long ival; |
| 492 | symbolS *sym; |
| 493 | } |
| 494 | u; |
| 495 | } |
| 496 | pseudo_func[] = |
| 497 | { |
| 498 | /* reloc pseudo functions (these must come first!): */ |
| 499 | { "dtpmod", PSEUDO_FUNC_RELOC, { 0 } }, |
| 500 | { "dtprel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 501 | { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, |
| 502 | { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 503 | { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, |
| 504 | { "ltoffx", PSEUDO_FUNC_RELOC, { 0 } }, |
| 505 | { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 506 | { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, |
| 507 | { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 508 | { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 509 | { "tprel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 510 | { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, |
| 511 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ |
| 512 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */ |
| 513 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */ |
| 514 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */ |
| 515 | { "iplt", PSEUDO_FUNC_RELOC, { 0 } }, |
| 516 | |
| 517 | /* mbtype4 constants: */ |
| 518 | { "alt", PSEUDO_FUNC_CONST, { 0xa } }, |
| 519 | { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, |
| 520 | { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, |
| 521 | { "rev", PSEUDO_FUNC_CONST, { 0xb } }, |
| 522 | { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, |
| 523 | |
| 524 | /* fclass constants: */ |
| 525 | { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, |
| 526 | { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, |
| 527 | { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, |
| 528 | { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, |
| 529 | { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, |
| 530 | { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, |
| 531 | { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, |
| 532 | { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, |
| 533 | { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, |
| 534 | |
| 535 | { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ |
| 536 | |
| 537 | /* hint constants: */ |
| 538 | { "pause", PSEUDO_FUNC_CONST, { 0x0 } }, |
| 539 | |
| 540 | /* unwind-related constants: */ |
| 541 | { "svr4", PSEUDO_FUNC_CONST, { ELFOSABI_NONE } }, |
| 542 | { "hpux", PSEUDO_FUNC_CONST, { ELFOSABI_HPUX } }, |
| 543 | { "nt", PSEUDO_FUNC_CONST, { 2 } }, /* conflicts w/ELFOSABI_NETBSD */ |
| 544 | { "linux", PSEUDO_FUNC_CONST, { ELFOSABI_LINUX } }, |
| 545 | { "freebsd", PSEUDO_FUNC_CONST, { ELFOSABI_FREEBSD } }, |
| 546 | { "openvms", PSEUDO_FUNC_CONST, { ELFOSABI_OPENVMS } }, |
| 547 | { "nsk", PSEUDO_FUNC_CONST, { ELFOSABI_NSK } }, |
| 548 | |
| 549 | /* unwind-related registers: */ |
| 550 | { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } |
| 551 | }; |
| 552 | |
| 553 | /* 41-bit nop opcodes (one per unit): */ |
| 554 | static const bfd_vma nop[IA64_NUM_UNITS] = |
| 555 | { |
| 556 | 0x0000000000LL, /* NIL => break 0 */ |
| 557 | 0x0008000000LL, /* I-unit nop */ |
| 558 | 0x0008000000LL, /* M-unit nop */ |
| 559 | 0x4000000000LL, /* B-unit nop */ |
| 560 | 0x0008000000LL, /* F-unit nop */ |
| 561 | 0x0008000000LL, /* L-"unit" nop */ |
| 562 | 0x0008000000LL, /* X-unit nop */ |
| 563 | }; |
| 564 | |
| 565 | /* Can't be `const' as it's passed to input routines (which have the |
| 566 | habit of setting temporary sentinels. */ |
| 567 | static char special_section_name[][20] = |
| 568 | { |
| 569 | {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, |
| 570 | {".IA_64.unwind"}, {".IA_64.unwind_info"}, |
| 571 | {".init_array"}, {".fini_array"} |
| 572 | }; |
| 573 | |
| 574 | static char *special_linkonce_name[] = |
| 575 | { |
| 576 | ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi." |
| 577 | }; |
| 578 | |
| 579 | /* The best template for a particular sequence of up to three |
| 580 | instructions: */ |
| 581 | #define N IA64_NUM_TYPES |
| 582 | static unsigned char best_template[N][N][N]; |
| 583 | #undef N |
| 584 | |
| 585 | /* Resource dependencies currently in effect */ |
| 586 | static struct rsrc { |
| 587 | int depind; /* dependency index */ |
| 588 | const struct ia64_dependency *dependency; /* actual dependency */ |
| 589 | unsigned specific:1, /* is this a specific bit/regno? */ |
| 590 | link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ |
| 591 | int index; /* specific regno/bit within dependency */ |
| 592 | int note; /* optional qualifying note (0 if none) */ |
| 593 | #define STATE_NONE 0 |
| 594 | #define STATE_STOP 1 |
| 595 | #define STATE_SRLZ 2 |
| 596 | int insn_srlz; /* current insn serialization state */ |
| 597 | int data_srlz; /* current data serialization state */ |
| 598 | int qp_regno; /* qualifying predicate for this usage */ |
| 599 | char *file; /* what file marked this dependency */ |
| 600 | unsigned int line; /* what line marked this dependency */ |
| 601 | struct mem_offset mem_offset; /* optional memory offset hint */ |
| 602 | enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ |
| 603 | int path; /* corresponding code entry index */ |
| 604 | } *regdeps = NULL; |
| 605 | static int regdepslen = 0; |
| 606 | static int regdepstotlen = 0; |
| 607 | static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; |
| 608 | static const char *dv_sem[] = { "none", "implied", "impliedf", |
| 609 | "data", "instr", "specific", "stop", "other" }; |
| 610 | static const char *dv_cmp_type[] = { "none", "OR", "AND" }; |
| 611 | |
| 612 | /* Current state of PR mutexation */ |
| 613 | static struct qpmutex { |
| 614 | valueT prmask; |
| 615 | int path; |
| 616 | } *qp_mutexes = NULL; /* QP mutex bitmasks */ |
| 617 | static int qp_mutexeslen = 0; |
| 618 | static int qp_mutexestotlen = 0; |
| 619 | static valueT qp_safe_across_calls = 0; |
| 620 | |
| 621 | /* Current state of PR implications */ |
| 622 | static struct qp_imply { |
| 623 | unsigned p1:6; |
| 624 | unsigned p2:6; |
| 625 | unsigned p2_branched:1; |
| 626 | int path; |
| 627 | } *qp_implies = NULL; |
| 628 | static int qp_implieslen = 0; |
| 629 | static int qp_impliestotlen = 0; |
| 630 | |
| 631 | /* Keep track of static GR values so that indirect register usage can |
| 632 | sometimes be tracked. */ |
| 633 | static struct gr { |
| 634 | unsigned known:1; |
| 635 | int path; |
| 636 | valueT value; |
| 637 | } gr_values[128] = {{ 1, 0, 0 }}; |
| 638 | |
| 639 | /* These are the routines required to output the various types of |
| 640 | unwind records. */ |
| 641 | |
| 642 | /* A slot_number is a frag address plus the slot index (0-2). We use the |
| 643 | frag address here so that if there is a section switch in the middle of |
| 644 | a function, then instructions emitted to a different section are not |
| 645 | counted. Since there may be more than one frag for a function, this |
| 646 | means we also need to keep track of which frag this address belongs to |
| 647 | so we can compute inter-frag distances. This also nicely solves the |
| 648 | problem with nops emitted for align directives, which can't easily be |
| 649 | counted, but can easily be derived from frag sizes. */ |
| 650 | |
| 651 | typedef struct unw_rec_list { |
| 652 | unwind_record r; |
| 653 | unsigned long slot_number; |
| 654 | fragS *slot_frag; |
| 655 | struct unw_rec_list *next; |
| 656 | } unw_rec_list; |
| 657 | |
| 658 | #define SLOT_NUM_NOT_SET (unsigned)-1 |
| 659 | |
| 660 | /* Linked list of saved prologue counts. A very poor |
| 661 | implementation of a map from label numbers to prologue counts. */ |
| 662 | typedef struct label_prologue_count |
| 663 | { |
| 664 | struct label_prologue_count *next; |
| 665 | unsigned long label_number; |
| 666 | unsigned int prologue_count; |
| 667 | } label_prologue_count; |
| 668 | |
| 669 | static struct |
| 670 | { |
| 671 | unsigned long next_slot_number; |
| 672 | fragS *next_slot_frag; |
| 673 | |
| 674 | /* Maintain a list of unwind entries for the current function. */ |
| 675 | unw_rec_list *list; |
| 676 | unw_rec_list *tail; |
| 677 | |
| 678 | /* Any unwind entires that should be attached to the current slot |
| 679 | that an insn is being constructed for. */ |
| 680 | unw_rec_list *current_entry; |
| 681 | |
| 682 | /* These are used to create the unwind table entry for this function. */ |
| 683 | symbolS *proc_start; |
| 684 | symbolS *proc_end; |
| 685 | symbolS *info; /* pointer to unwind info */ |
| 686 | symbolS *personality_routine; |
| 687 | segT saved_text_seg; |
| 688 | subsegT saved_text_subseg; |
| 689 | unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */ |
| 690 | |
| 691 | /* TRUE if processing unwind directives in a prologue region. */ |
| 692 | int prologue; |
| 693 | int prologue_mask; |
| 694 | unsigned int prologue_count; /* number of .prologues seen so far */ |
| 695 | /* Prologue counts at previous .label_state directives. */ |
| 696 | struct label_prologue_count * saved_prologue_counts; |
| 697 | } unwind; |
| 698 | |
| 699 | typedef void (*vbyte_func) PARAMS ((int, char *, char *)); |
| 700 | |
| 701 | /* Forward delarations: */ |
| 702 | static int ar_is_in_integer_unit PARAMS ((int regnum)); |
| 703 | static void set_section PARAMS ((char *name)); |
| 704 | static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, |
| 705 | unsigned int, unsigned int)); |
| 706 | static void dot_radix PARAMS ((int)); |
| 707 | static void dot_special_section PARAMS ((int)); |
| 708 | static void dot_proc PARAMS ((int)); |
| 709 | static void dot_fframe PARAMS ((int)); |
| 710 | static void dot_vframe PARAMS ((int)); |
| 711 | static void dot_vframesp PARAMS ((int)); |
| 712 | static void dot_vframepsp PARAMS ((int)); |
| 713 | static void dot_save PARAMS ((int)); |
| 714 | static void dot_restore PARAMS ((int)); |
| 715 | static void dot_restorereg PARAMS ((int)); |
| 716 | static void dot_restorereg_p PARAMS ((int)); |
| 717 | static void dot_handlerdata PARAMS ((int)); |
| 718 | static void dot_unwentry PARAMS ((int)); |
| 719 | static void dot_altrp PARAMS ((int)); |
| 720 | static void dot_savemem PARAMS ((int)); |
| 721 | static void dot_saveg PARAMS ((int)); |
| 722 | static void dot_savef PARAMS ((int)); |
| 723 | static void dot_saveb PARAMS ((int)); |
| 724 | static void dot_savegf PARAMS ((int)); |
| 725 | static void dot_spill PARAMS ((int)); |
| 726 | static void dot_spillreg PARAMS ((int)); |
| 727 | static void dot_spillmem PARAMS ((int)); |
| 728 | static void dot_spillreg_p PARAMS ((int)); |
| 729 | static void dot_spillmem_p PARAMS ((int)); |
| 730 | static void dot_label_state PARAMS ((int)); |
| 731 | static void dot_copy_state PARAMS ((int)); |
| 732 | static void dot_unwabi PARAMS ((int)); |
| 733 | static void dot_personality PARAMS ((int)); |
| 734 | static void dot_body PARAMS ((int)); |
| 735 | static void dot_prologue PARAMS ((int)); |
| 736 | static void dot_endp PARAMS ((int)); |
| 737 | static void dot_template PARAMS ((int)); |
| 738 | static void dot_regstk PARAMS ((int)); |
| 739 | static void dot_rot PARAMS ((int)); |
| 740 | static void dot_byteorder PARAMS ((int)); |
| 741 | static void dot_psr PARAMS ((int)); |
| 742 | static void dot_alias PARAMS ((int)); |
| 743 | static void dot_ln PARAMS ((int)); |
| 744 | static char *parse_section_name PARAMS ((void)); |
| 745 | static void dot_xdata PARAMS ((int)); |
| 746 | static void stmt_float_cons PARAMS ((int)); |
| 747 | static void stmt_cons_ua PARAMS ((int)); |
| 748 | static void dot_xfloat_cons PARAMS ((int)); |
| 749 | static void dot_xstringer PARAMS ((int)); |
| 750 | static void dot_xdata_ua PARAMS ((int)); |
| 751 | static void dot_xfloat_cons_ua PARAMS ((int)); |
| 752 | static void print_prmask PARAMS ((valueT mask)); |
| 753 | static void dot_pred_rel PARAMS ((int)); |
| 754 | static void dot_reg_val PARAMS ((int)); |
| 755 | static void dot_dv_mode PARAMS ((int)); |
| 756 | static void dot_entry PARAMS ((int)); |
| 757 | static void dot_mem_offset PARAMS ((int)); |
| 758 | static void add_unwind_entry PARAMS((unw_rec_list *ptr)); |
| 759 | static symbolS *declare_register PARAMS ((const char *name, int regnum)); |
| 760 | static void declare_register_set PARAMS ((const char *, int, int)); |
| 761 | static unsigned int operand_width PARAMS ((enum ia64_opnd)); |
| 762 | static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc, |
| 763 | int index, |
| 764 | expressionS *e)); |
| 765 | static int parse_operand PARAMS ((expressionS *e)); |
| 766 | static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); |
| 767 | static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit)); |
| 768 | static void build_insn PARAMS ((struct slot *, bfd_vma *)); |
| 769 | static void emit_one_bundle PARAMS ((void)); |
| 770 | static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); |
| 771 | static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, |
| 772 | bfd_reloc_code_real_type r_type)); |
| 773 | static void insn_group_break PARAMS ((int, int, int)); |
| 774 | static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, |
| 775 | struct rsrc *, int depind, int path)); |
| 776 | static void add_qp_mutex PARAMS((valueT mask)); |
| 777 | static void add_qp_imply PARAMS((int p1, int p2)); |
| 778 | static void clear_qp_branch_flag PARAMS((valueT mask)); |
| 779 | static void clear_qp_mutex PARAMS((valueT mask)); |
| 780 | static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); |
| 781 | static int has_suffix_p PARAMS((const char *, const char *)); |
| 782 | static void clear_register_values PARAMS ((void)); |
| 783 | static void print_dependency PARAMS ((const char *action, int depind)); |
| 784 | static void instruction_serialization PARAMS ((void)); |
| 785 | static void data_serialization PARAMS ((void)); |
| 786 | static void remove_marked_resource PARAMS ((struct rsrc *)); |
| 787 | static int is_conditional_branch PARAMS ((struct ia64_opcode *)); |
| 788 | static int is_taken_branch PARAMS ((struct ia64_opcode *)); |
| 789 | static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); |
| 790 | static int depends_on PARAMS ((int, struct ia64_opcode *)); |
| 791 | static int specify_resource PARAMS ((const struct ia64_dependency *, |
| 792 | struct ia64_opcode *, int, struct rsrc [], int, int)); |
| 793 | static int check_dv PARAMS((struct ia64_opcode *idesc)); |
| 794 | static void check_dependencies PARAMS((struct ia64_opcode *)); |
| 795 | static void mark_resources PARAMS((struct ia64_opcode *)); |
| 796 | static void update_dependencies PARAMS((struct ia64_opcode *)); |
| 797 | static void note_register_values PARAMS((struct ia64_opcode *)); |
| 798 | static int qp_mutex PARAMS ((int, int, int)); |
| 799 | static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); |
| 800 | static void output_vbyte_mem PARAMS ((int, char *, char *)); |
| 801 | static void count_output PARAMS ((int, char *, char *)); |
| 802 | static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); |
| 803 | static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); |
| 804 | static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
| 805 | static void output_P1_format PARAMS ((vbyte_func, int)); |
| 806 | static void output_P2_format PARAMS ((vbyte_func, int, int)); |
| 807 | static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); |
| 808 | static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); |
| 809 | static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); |
| 810 | static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); |
| 811 | static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); |
| 812 | static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
| 813 | static void output_P9_format PARAMS ((vbyte_func, int, int)); |
| 814 | static void output_P10_format PARAMS ((vbyte_func, int, int)); |
| 815 | static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
| 816 | static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); |
| 817 | static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); |
| 818 | static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
| 819 | static char format_ab_reg PARAMS ((int, int)); |
| 820 | static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, |
| 821 | unsigned long)); |
| 822 | static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); |
| 823 | static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, |
| 824 | unsigned long)); |
| 825 | static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); |
| 826 | static void free_list_records PARAMS ((unw_rec_list *)); |
| 827 | static unw_rec_list *output_prologue PARAMS ((void)); |
| 828 | static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); |
| 829 | static unw_rec_list *output_body PARAMS ((void)); |
| 830 | static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); |
| 831 | static unw_rec_list *output_mem_stack_v PARAMS ((void)); |
| 832 | static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); |
| 833 | static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); |
| 834 | static unw_rec_list *output_rp_when PARAMS ((void)); |
| 835 | static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); |
| 836 | static unw_rec_list *output_rp_br PARAMS ((unsigned int)); |
| 837 | static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); |
| 838 | static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); |
| 839 | static unw_rec_list *output_pfs_when PARAMS ((void)); |
| 840 | static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); |
| 841 | static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); |
| 842 | static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); |
| 843 | static unw_rec_list *output_preds_when PARAMS ((void)); |
| 844 | static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); |
| 845 | static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); |
| 846 | static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); |
| 847 | static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); |
| 848 | static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); |
| 849 | static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); |
| 850 | static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); |
| 851 | static unw_rec_list *output_br_mem PARAMS ((unsigned int)); |
| 852 | static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); |
| 853 | static unw_rec_list *output_spill_base PARAMS ((unsigned int)); |
| 854 | static unw_rec_list *output_unat_when PARAMS ((void)); |
| 855 | static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); |
| 856 | static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); |
| 857 | static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); |
| 858 | static unw_rec_list *output_lc_when PARAMS ((void)); |
| 859 | static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); |
| 860 | static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); |
| 861 | static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); |
| 862 | static unw_rec_list *output_fpsr_when PARAMS ((void)); |
| 863 | static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); |
| 864 | static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); |
| 865 | static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); |
| 866 | static unw_rec_list *output_priunat_when_gr PARAMS ((void)); |
| 867 | static unw_rec_list *output_priunat_when_mem PARAMS ((void)); |
| 868 | static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); |
| 869 | static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); |
| 870 | static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); |
| 871 | static unw_rec_list *output_bsp_when PARAMS ((void)); |
| 872 | static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); |
| 873 | static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); |
| 874 | static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); |
| 875 | static unw_rec_list *output_bspstore_when PARAMS ((void)); |
| 876 | static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); |
| 877 | static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); |
| 878 | static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); |
| 879 | static unw_rec_list *output_rnat_when PARAMS ((void)); |
| 880 | static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); |
| 881 | static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); |
| 882 | static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); |
| 883 | static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); |
| 884 | static unw_rec_list *output_epilogue PARAMS ((unsigned long)); |
| 885 | static unw_rec_list *output_label_state PARAMS ((unsigned long)); |
| 886 | static unw_rec_list *output_copy_state PARAMS ((unsigned long)); |
| 887 | static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); |
| 888 | static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); |
| 889 | static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, |
| 890 | unsigned int)); |
| 891 | static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, |
| 892 | unsigned int)); |
| 893 | static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, |
| 894 | unsigned int)); |
| 895 | static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, |
| 896 | unsigned int, unsigned int)); |
| 897 | static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); |
| 898 | static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); |
| 899 | static int calc_record_size PARAMS ((unw_rec_list *)); |
| 900 | static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); |
| 901 | static int count_bits PARAMS ((unsigned long)); |
| 902 | static unsigned long slot_index PARAMS ((unsigned long, fragS *, |
| 903 | unsigned long, fragS *)); |
| 904 | static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *)); |
| 905 | static void fixup_unw_records PARAMS ((unw_rec_list *)); |
| 906 | static int output_unw_records PARAMS ((unw_rec_list *, void **)); |
| 907 | static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); |
| 908 | static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); |
| 909 | static int generate_unwind_image PARAMS ((const char *)); |
| 910 | static unsigned int get_saved_prologue_count PARAMS ((unsigned long)); |
| 911 | static void save_prologue_count PARAMS ((unsigned long, unsigned int)); |
| 912 | static void free_saved_prologue_counts PARAMS ((void)); |
| 913 | |
| 914 | /* Build the unwind section name by appending the (possibly stripped) |
| 915 | text section NAME to the unwind PREFIX. The resulting string |
| 916 | pointer is assigned to RESULT. The string is allocated on the |
| 917 | stack, so this must be a macro... */ |
| 918 | #define make_unw_section_name(special, text_name, result) \ |
| 919 | { \ |
| 920 | const char *_prefix = special_section_name[special]; \ |
| 921 | const char *_suffix = text_name; \ |
| 922 | size_t _prefix_len, _suffix_len; \ |
| 923 | char *_result; \ |
| 924 | if (strncmp (text_name, ".gnu.linkonce.t.", \ |
| 925 | sizeof (".gnu.linkonce.t.") - 1) == 0) \ |
| 926 | { \ |
| 927 | _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \ |
| 928 | _suffix += sizeof (".gnu.linkonce.t.") - 1; \ |
| 929 | } \ |
| 930 | _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \ |
| 931 | _result = alloca (_prefix_len + _suffix_len + 1); \ |
| 932 | memcpy (_result, _prefix, _prefix_len); \ |
| 933 | memcpy (_result + _prefix_len, _suffix, _suffix_len); \ |
| 934 | _result[_prefix_len + _suffix_len] = '\0'; \ |
| 935 | result = _result; \ |
| 936 | } \ |
| 937 | while (0) |
| 938 | |
| 939 | /* Determine if application register REGNUM resides in the integer |
| 940 | unit (as opposed to the memory unit). */ |
| 941 | static int |
| 942 | ar_is_in_integer_unit (reg) |
| 943 | int reg; |
| 944 | { |
| 945 | reg -= REG_AR; |
| 946 | |
| 947 | return (reg == 64 /* pfs */ |
| 948 | || reg == 65 /* lc */ |
| 949 | || reg == 66 /* ec */ |
| 950 | /* ??? ias accepts and puts these in the integer unit. */ |
| 951 | || (reg >= 112 && reg <= 127)); |
| 952 | } |
| 953 | |
| 954 | /* Switch to section NAME and create section if necessary. It's |
| 955 | rather ugly that we have to manipulate input_line_pointer but I |
| 956 | don't see any other way to accomplish the same thing without |
| 957 | changing obj-elf.c (which may be the Right Thing, in the end). */ |
| 958 | static void |
| 959 | set_section (name) |
| 960 | char *name; |
| 961 | { |
| 962 | char *saved_input_line_pointer; |
| 963 | |
| 964 | saved_input_line_pointer = input_line_pointer; |
| 965 | input_line_pointer = name; |
| 966 | obj_elf_section (0); |
| 967 | input_line_pointer = saved_input_line_pointer; |
| 968 | } |
| 969 | |
| 970 | /* Map 's' to SHF_IA_64_SHORT. */ |
| 971 | |
| 972 | int |
| 973 | ia64_elf_section_letter (letter, ptr_msg) |
| 974 | int letter; |
| 975 | char **ptr_msg; |
| 976 | { |
| 977 | if (letter == 's') |
| 978 | return SHF_IA_64_SHORT; |
| 979 | else if (letter == 'o') |
| 980 | return SHF_LINK_ORDER; |
| 981 | |
| 982 | *ptr_msg = _("Bad .section directive: want a,o,s,w,x,M,S,G,T in string"); |
| 983 | return -1; |
| 984 | } |
| 985 | |
| 986 | /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ |
| 987 | |
| 988 | flagword |
| 989 | ia64_elf_section_flags (flags, attr, type) |
| 990 | flagword flags; |
| 991 | int attr, type ATTRIBUTE_UNUSED; |
| 992 | { |
| 993 | if (attr & SHF_IA_64_SHORT) |
| 994 | flags |= SEC_SMALL_DATA; |
| 995 | return flags; |
| 996 | } |
| 997 | |
| 998 | int |
| 999 | ia64_elf_section_type (str, len) |
| 1000 | const char *str; |
| 1001 | size_t len; |
| 1002 | { |
| 1003 | #define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0)) |
| 1004 | |
| 1005 | if (STREQ (ELF_STRING_ia64_unwind_info)) |
| 1006 | return SHT_PROGBITS; |
| 1007 | |
| 1008 | if (STREQ (ELF_STRING_ia64_unwind_info_once)) |
| 1009 | return SHT_PROGBITS; |
| 1010 | |
| 1011 | if (STREQ (ELF_STRING_ia64_unwind)) |
| 1012 | return SHT_IA_64_UNWIND; |
| 1013 | |
| 1014 | if (STREQ (ELF_STRING_ia64_unwind_once)) |
| 1015 | return SHT_IA_64_UNWIND; |
| 1016 | |
| 1017 | if (STREQ ("unwind")) |
| 1018 | return SHT_IA_64_UNWIND; |
| 1019 | |
| 1020 | if (STREQ ("init_array")) |
| 1021 | return SHT_INIT_ARRAY; |
| 1022 | |
| 1023 | if (STREQ ("fini_array")) |
| 1024 | return SHT_FINI_ARRAY; |
| 1025 | |
| 1026 | return -1; |
| 1027 | #undef STREQ |
| 1028 | } |
| 1029 | |
| 1030 | static unsigned int |
| 1031 | set_regstack (ins, locs, outs, rots) |
| 1032 | unsigned int ins, locs, outs, rots; |
| 1033 | { |
| 1034 | /* Size of frame. */ |
| 1035 | unsigned int sof; |
| 1036 | |
| 1037 | sof = ins + locs + outs; |
| 1038 | if (sof > 96) |
| 1039 | { |
| 1040 | as_bad ("Size of frame exceeds maximum of 96 registers"); |
| 1041 | return 0; |
| 1042 | } |
| 1043 | if (rots > sof) |
| 1044 | { |
| 1045 | as_warn ("Size of rotating registers exceeds frame size"); |
| 1046 | return 0; |
| 1047 | } |
| 1048 | md.in.base = REG_GR + 32; |
| 1049 | md.loc.base = md.in.base + ins; |
| 1050 | md.out.base = md.loc.base + locs; |
| 1051 | |
| 1052 | md.in.num_regs = ins; |
| 1053 | md.loc.num_regs = locs; |
| 1054 | md.out.num_regs = outs; |
| 1055 | md.rot.num_regs = rots; |
| 1056 | return sof; |
| 1057 | } |
| 1058 | |
| 1059 | void |
| 1060 | ia64_flush_insns () |
| 1061 | { |
| 1062 | struct label_fix *lfix; |
| 1063 | segT saved_seg; |
| 1064 | subsegT saved_subseg; |
| 1065 | unw_rec_list *ptr; |
| 1066 | |
| 1067 | if (!md.last_text_seg) |
| 1068 | return; |
| 1069 | |
| 1070 | saved_seg = now_seg; |
| 1071 | saved_subseg = now_subseg; |
| 1072 | |
| 1073 | subseg_set (md.last_text_seg, 0); |
| 1074 | |
| 1075 | while (md.num_slots_in_use > 0) |
| 1076 | emit_one_bundle (); /* force out queued instructions */ |
| 1077 | |
| 1078 | /* In case there are labels following the last instruction, resolve |
| 1079 | those now: */ |
| 1080 | for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) |
| 1081 | { |
| 1082 | S_SET_VALUE (lfix->sym, frag_now_fix ()); |
| 1083 | symbol_set_frag (lfix->sym, frag_now); |
| 1084 | } |
| 1085 | CURR_SLOT.label_fixups = 0; |
| 1086 | for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) |
| 1087 | { |
| 1088 | S_SET_VALUE (lfix->sym, frag_now_fix ()); |
| 1089 | symbol_set_frag (lfix->sym, frag_now); |
| 1090 | } |
| 1091 | CURR_SLOT.tag_fixups = 0; |
| 1092 | |
| 1093 | /* In case there are unwind directives following the last instruction, |
| 1094 | resolve those now. We only handle body and prologue directives here. |
| 1095 | Give an error for others. */ |
| 1096 | for (ptr = unwind.current_entry; ptr; ptr = ptr->next) |
| 1097 | { |
| 1098 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr |
| 1099 | || ptr->r.type == body) |
| 1100 | { |
| 1101 | ptr->slot_number = (unsigned long) frag_more (0); |
| 1102 | ptr->slot_frag = frag_now; |
| 1103 | } |
| 1104 | else |
| 1105 | as_bad (_("Unwind directive not followed by an instruction.")); |
| 1106 | } |
| 1107 | unwind.current_entry = NULL; |
| 1108 | |
| 1109 | subseg_set (saved_seg, saved_subseg); |
| 1110 | |
| 1111 | if (md.qp.X_op == O_register) |
| 1112 | as_bad ("qualifying predicate not followed by instruction"); |
| 1113 | } |
| 1114 | |
| 1115 | void |
| 1116 | ia64_do_align (nbytes) |
| 1117 | int nbytes; |
| 1118 | { |
| 1119 | char *saved_input_line_pointer = input_line_pointer; |
| 1120 | |
| 1121 | input_line_pointer = ""; |
| 1122 | s_align_bytes (nbytes); |
| 1123 | input_line_pointer = saved_input_line_pointer; |
| 1124 | } |
| 1125 | |
| 1126 | void |
| 1127 | ia64_cons_align (nbytes) |
| 1128 | int nbytes; |
| 1129 | { |
| 1130 | if (md.auto_align) |
| 1131 | { |
| 1132 | char *saved_input_line_pointer = input_line_pointer; |
| 1133 | input_line_pointer = ""; |
| 1134 | s_align_bytes (nbytes); |
| 1135 | input_line_pointer = saved_input_line_pointer; |
| 1136 | } |
| 1137 | } |
| 1138 | |
| 1139 | /* Output COUNT bytes to a memory location. */ |
| 1140 | static unsigned char *vbyte_mem_ptr = NULL; |
| 1141 | |
| 1142 | void |
| 1143 | output_vbyte_mem (count, ptr, comment) |
| 1144 | int count; |
| 1145 | char *ptr; |
| 1146 | char *comment ATTRIBUTE_UNUSED; |
| 1147 | { |
| 1148 | int x; |
| 1149 | if (vbyte_mem_ptr == NULL) |
| 1150 | abort (); |
| 1151 | |
| 1152 | if (count == 0) |
| 1153 | return; |
| 1154 | for (x = 0; x < count; x++) |
| 1155 | *(vbyte_mem_ptr++) = ptr[x]; |
| 1156 | } |
| 1157 | |
| 1158 | /* Count the number of bytes required for records. */ |
| 1159 | static int vbyte_count = 0; |
| 1160 | void |
| 1161 | count_output (count, ptr, comment) |
| 1162 | int count; |
| 1163 | char *ptr ATTRIBUTE_UNUSED; |
| 1164 | char *comment ATTRIBUTE_UNUSED; |
| 1165 | { |
| 1166 | vbyte_count += count; |
| 1167 | } |
| 1168 | |
| 1169 | static void |
| 1170 | output_R1_format (f, rtype, rlen) |
| 1171 | vbyte_func f; |
| 1172 | unw_record_type rtype; |
| 1173 | int rlen; |
| 1174 | { |
| 1175 | int r = 0; |
| 1176 | char byte; |
| 1177 | if (rlen > 0x1f) |
| 1178 | { |
| 1179 | output_R3_format (f, rtype, rlen); |
| 1180 | return; |
| 1181 | } |
| 1182 | |
| 1183 | if (rtype == body) |
| 1184 | r = 1; |
| 1185 | else if (rtype != prologue) |
| 1186 | as_bad ("record type is not valid"); |
| 1187 | |
| 1188 | byte = UNW_R1 | (r << 5) | (rlen & 0x1f); |
| 1189 | (*f) (1, &byte, NULL); |
| 1190 | } |
| 1191 | |
| 1192 | static void |
| 1193 | output_R2_format (f, mask, grsave, rlen) |
| 1194 | vbyte_func f; |
| 1195 | int mask, grsave; |
| 1196 | unsigned long rlen; |
| 1197 | { |
| 1198 | char bytes[20]; |
| 1199 | int count = 2; |
| 1200 | mask = (mask & 0x0f); |
| 1201 | grsave = (grsave & 0x7f); |
| 1202 | |
| 1203 | bytes[0] = (UNW_R2 | (mask >> 1)); |
| 1204 | bytes[1] = (((mask & 0x01) << 7) | grsave); |
| 1205 | count += output_leb128 (bytes + 2, rlen, 0); |
| 1206 | (*f) (count, bytes, NULL); |
| 1207 | } |
| 1208 | |
| 1209 | static void |
| 1210 | output_R3_format (f, rtype, rlen) |
| 1211 | vbyte_func f; |
| 1212 | unw_record_type rtype; |
| 1213 | unsigned long rlen; |
| 1214 | { |
| 1215 | int r = 0, count; |
| 1216 | char bytes[20]; |
| 1217 | if (rlen <= 0x1f) |
| 1218 | { |
| 1219 | output_R1_format (f, rtype, rlen); |
| 1220 | return; |
| 1221 | } |
| 1222 | |
| 1223 | if (rtype == body) |
| 1224 | r = 1; |
| 1225 | else if (rtype != prologue) |
| 1226 | as_bad ("record type is not valid"); |
| 1227 | bytes[0] = (UNW_R3 | r); |
| 1228 | count = output_leb128 (bytes + 1, rlen, 0); |
| 1229 | (*f) (count + 1, bytes, NULL); |
| 1230 | } |
| 1231 | |
| 1232 | static void |
| 1233 | output_P1_format (f, brmask) |
| 1234 | vbyte_func f; |
| 1235 | int brmask; |
| 1236 | { |
| 1237 | char byte; |
| 1238 | byte = UNW_P1 | (brmask & 0x1f); |
| 1239 | (*f) (1, &byte, NULL); |
| 1240 | } |
| 1241 | |
| 1242 | static void |
| 1243 | output_P2_format (f, brmask, gr) |
| 1244 | vbyte_func f; |
| 1245 | int brmask; |
| 1246 | int gr; |
| 1247 | { |
| 1248 | char bytes[2]; |
| 1249 | brmask = (brmask & 0x1f); |
| 1250 | bytes[0] = UNW_P2 | (brmask >> 1); |
| 1251 | bytes[1] = (((brmask & 1) << 7) | gr); |
| 1252 | (*f) (2, bytes, NULL); |
| 1253 | } |
| 1254 | |
| 1255 | static void |
| 1256 | output_P3_format (f, rtype, reg) |
| 1257 | vbyte_func f; |
| 1258 | unw_record_type rtype; |
| 1259 | int reg; |
| 1260 | { |
| 1261 | char bytes[2]; |
| 1262 | int r = 0; |
| 1263 | reg = (reg & 0x7f); |
| 1264 | switch (rtype) |
| 1265 | { |
| 1266 | case psp_gr: |
| 1267 | r = 0; |
| 1268 | break; |
| 1269 | case rp_gr: |
| 1270 | r = 1; |
| 1271 | break; |
| 1272 | case pfs_gr: |
| 1273 | r = 2; |
| 1274 | break; |
| 1275 | case preds_gr: |
| 1276 | r = 3; |
| 1277 | break; |
| 1278 | case unat_gr: |
| 1279 | r = 4; |
| 1280 | break; |
| 1281 | case lc_gr: |
| 1282 | r = 5; |
| 1283 | break; |
| 1284 | case rp_br: |
| 1285 | r = 6; |
| 1286 | break; |
| 1287 | case rnat_gr: |
| 1288 | r = 7; |
| 1289 | break; |
| 1290 | case bsp_gr: |
| 1291 | r = 8; |
| 1292 | break; |
| 1293 | case bspstore_gr: |
| 1294 | r = 9; |
| 1295 | break; |
| 1296 | case fpsr_gr: |
| 1297 | r = 10; |
| 1298 | break; |
| 1299 | case priunat_gr: |
| 1300 | r = 11; |
| 1301 | break; |
| 1302 | default: |
| 1303 | as_bad ("Invalid record type for P3 format."); |
| 1304 | } |
| 1305 | bytes[0] = (UNW_P3 | (r >> 1)); |
| 1306 | bytes[1] = (((r & 1) << 7) | reg); |
| 1307 | (*f) (2, bytes, NULL); |
| 1308 | } |
| 1309 | |
| 1310 | static void |
| 1311 | output_P4_format (f, imask, imask_size) |
| 1312 | vbyte_func f; |
| 1313 | unsigned char *imask; |
| 1314 | unsigned long imask_size; |
| 1315 | { |
| 1316 | imask[0] = UNW_P4; |
| 1317 | (*f) (imask_size, imask, NULL); |
| 1318 | } |
| 1319 | |
| 1320 | static void |
| 1321 | output_P5_format (f, grmask, frmask) |
| 1322 | vbyte_func f; |
| 1323 | int grmask; |
| 1324 | unsigned long frmask; |
| 1325 | { |
| 1326 | char bytes[4]; |
| 1327 | grmask = (grmask & 0x0f); |
| 1328 | |
| 1329 | bytes[0] = UNW_P5; |
| 1330 | bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); |
| 1331 | bytes[2] = ((frmask & 0x0000ff00) >> 8); |
| 1332 | bytes[3] = (frmask & 0x000000ff); |
| 1333 | (*f) (4, bytes, NULL); |
| 1334 | } |
| 1335 | |
| 1336 | static void |
| 1337 | output_P6_format (f, rtype, rmask) |
| 1338 | vbyte_func f; |
| 1339 | unw_record_type rtype; |
| 1340 | int rmask; |
| 1341 | { |
| 1342 | char byte; |
| 1343 | int r = 0; |
| 1344 | |
| 1345 | if (rtype == gr_mem) |
| 1346 | r = 1; |
| 1347 | else if (rtype != fr_mem) |
| 1348 | as_bad ("Invalid record type for format P6"); |
| 1349 | byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); |
| 1350 | (*f) (1, &byte, NULL); |
| 1351 | } |
| 1352 | |
| 1353 | static void |
| 1354 | output_P7_format (f, rtype, w1, w2) |
| 1355 | vbyte_func f; |
| 1356 | unw_record_type rtype; |
| 1357 | unsigned long w1; |
| 1358 | unsigned long w2; |
| 1359 | { |
| 1360 | char bytes[20]; |
| 1361 | int count = 1; |
| 1362 | int r = 0; |
| 1363 | count += output_leb128 (bytes + 1, w1, 0); |
| 1364 | switch (rtype) |
| 1365 | { |
| 1366 | case mem_stack_f: |
| 1367 | r = 0; |
| 1368 | count += output_leb128 (bytes + count, w2 >> 4, 0); |
| 1369 | break; |
| 1370 | case mem_stack_v: |
| 1371 | r = 1; |
| 1372 | break; |
| 1373 | case spill_base: |
| 1374 | r = 2; |
| 1375 | break; |
| 1376 | case psp_sprel: |
| 1377 | r = 3; |
| 1378 | break; |
| 1379 | case rp_when: |
| 1380 | r = 4; |
| 1381 | break; |
| 1382 | case rp_psprel: |
| 1383 | r = 5; |
| 1384 | break; |
| 1385 | case pfs_when: |
| 1386 | r = 6; |
| 1387 | break; |
| 1388 | case pfs_psprel: |
| 1389 | r = 7; |
| 1390 | break; |
| 1391 | case preds_when: |
| 1392 | r = 8; |
| 1393 | break; |
| 1394 | case preds_psprel: |
| 1395 | r = 9; |
| 1396 | break; |
| 1397 | case lc_when: |
| 1398 | r = 10; |
| 1399 | break; |
| 1400 | case lc_psprel: |
| 1401 | r = 11; |
| 1402 | break; |
| 1403 | case unat_when: |
| 1404 | r = 12; |
| 1405 | break; |
| 1406 | case unat_psprel: |
| 1407 | r = 13; |
| 1408 | break; |
| 1409 | case fpsr_when: |
| 1410 | r = 14; |
| 1411 | break; |
| 1412 | case fpsr_psprel: |
| 1413 | r = 15; |
| 1414 | break; |
| 1415 | default: |
| 1416 | break; |
| 1417 | } |
| 1418 | bytes[0] = (UNW_P7 | r); |
| 1419 | (*f) (count, bytes, NULL); |
| 1420 | } |
| 1421 | |
| 1422 | static void |
| 1423 | output_P8_format (f, rtype, t) |
| 1424 | vbyte_func f; |
| 1425 | unw_record_type rtype; |
| 1426 | unsigned long t; |
| 1427 | { |
| 1428 | char bytes[20]; |
| 1429 | int r = 0; |
| 1430 | int count = 2; |
| 1431 | bytes[0] = UNW_P8; |
| 1432 | switch (rtype) |
| 1433 | { |
| 1434 | case rp_sprel: |
| 1435 | r = 1; |
| 1436 | break; |
| 1437 | case pfs_sprel: |
| 1438 | r = 2; |
| 1439 | break; |
| 1440 | case preds_sprel: |
| 1441 | r = 3; |
| 1442 | break; |
| 1443 | case lc_sprel: |
| 1444 | r = 4; |
| 1445 | break; |
| 1446 | case unat_sprel: |
| 1447 | r = 5; |
| 1448 | break; |
| 1449 | case fpsr_sprel: |
| 1450 | r = 6; |
| 1451 | break; |
| 1452 | case bsp_when: |
| 1453 | r = 7; |
| 1454 | break; |
| 1455 | case bsp_psprel: |
| 1456 | r = 8; |
| 1457 | break; |
| 1458 | case bsp_sprel: |
| 1459 | r = 9; |
| 1460 | break; |
| 1461 | case bspstore_when: |
| 1462 | r = 10; |
| 1463 | break; |
| 1464 | case bspstore_psprel: |
| 1465 | r = 11; |
| 1466 | break; |
| 1467 | case bspstore_sprel: |
| 1468 | r = 12; |
| 1469 | break; |
| 1470 | case rnat_when: |
| 1471 | r = 13; |
| 1472 | break; |
| 1473 | case rnat_psprel: |
| 1474 | r = 14; |
| 1475 | break; |
| 1476 | case rnat_sprel: |
| 1477 | r = 15; |
| 1478 | break; |
| 1479 | case priunat_when_gr: |
| 1480 | r = 16; |
| 1481 | break; |
| 1482 | case priunat_psprel: |
| 1483 | r = 17; |
| 1484 | break; |
| 1485 | case priunat_sprel: |
| 1486 | r = 18; |
| 1487 | break; |
| 1488 | case priunat_when_mem: |
| 1489 | r = 19; |
| 1490 | break; |
| 1491 | default: |
| 1492 | break; |
| 1493 | } |
| 1494 | bytes[1] = r; |
| 1495 | count += output_leb128 (bytes + 2, t, 0); |
| 1496 | (*f) (count, bytes, NULL); |
| 1497 | } |
| 1498 | |
| 1499 | static void |
| 1500 | output_P9_format (f, grmask, gr) |
| 1501 | vbyte_func f; |
| 1502 | int grmask; |
| 1503 | int gr; |
| 1504 | { |
| 1505 | char bytes[3]; |
| 1506 | bytes[0] = UNW_P9; |
| 1507 | bytes[1] = (grmask & 0x0f); |
| 1508 | bytes[2] = (gr & 0x7f); |
| 1509 | (*f) (3, bytes, NULL); |
| 1510 | } |
| 1511 | |
| 1512 | static void |
| 1513 | output_P10_format (f, abi, context) |
| 1514 | vbyte_func f; |
| 1515 | int abi; |
| 1516 | int context; |
| 1517 | { |
| 1518 | char bytes[3]; |
| 1519 | bytes[0] = UNW_P10; |
| 1520 | bytes[1] = (abi & 0xff); |
| 1521 | bytes[2] = (context & 0xff); |
| 1522 | (*f) (3, bytes, NULL); |
| 1523 | } |
| 1524 | |
| 1525 | static void |
| 1526 | output_B1_format (f, rtype, label) |
| 1527 | vbyte_func f; |
| 1528 | unw_record_type rtype; |
| 1529 | unsigned long label; |
| 1530 | { |
| 1531 | char byte; |
| 1532 | int r = 0; |
| 1533 | if (label > 0x1f) |
| 1534 | { |
| 1535 | output_B4_format (f, rtype, label); |
| 1536 | return; |
| 1537 | } |
| 1538 | if (rtype == copy_state) |
| 1539 | r = 1; |
| 1540 | else if (rtype != label_state) |
| 1541 | as_bad ("Invalid record type for format B1"); |
| 1542 | |
| 1543 | byte = (UNW_B1 | (r << 5) | (label & 0x1f)); |
| 1544 | (*f) (1, &byte, NULL); |
| 1545 | } |
| 1546 | |
| 1547 | static void |
| 1548 | output_B2_format (f, ecount, t) |
| 1549 | vbyte_func f; |
| 1550 | unsigned long ecount; |
| 1551 | unsigned long t; |
| 1552 | { |
| 1553 | char bytes[20]; |
| 1554 | int count = 1; |
| 1555 | if (ecount > 0x1f) |
| 1556 | { |
| 1557 | output_B3_format (f, ecount, t); |
| 1558 | return; |
| 1559 | } |
| 1560 | bytes[0] = (UNW_B2 | (ecount & 0x1f)); |
| 1561 | count += output_leb128 (bytes + 1, t, 0); |
| 1562 | (*f) (count, bytes, NULL); |
| 1563 | } |
| 1564 | |
| 1565 | static void |
| 1566 | output_B3_format (f, ecount, t) |
| 1567 | vbyte_func f; |
| 1568 | unsigned long ecount; |
| 1569 | unsigned long t; |
| 1570 | { |
| 1571 | char bytes[20]; |
| 1572 | int count = 1; |
| 1573 | if (ecount <= 0x1f) |
| 1574 | { |
| 1575 | output_B2_format (f, ecount, t); |
| 1576 | return; |
| 1577 | } |
| 1578 | bytes[0] = UNW_B3; |
| 1579 | count += output_leb128 (bytes + 1, t, 0); |
| 1580 | count += output_leb128 (bytes + count, ecount, 0); |
| 1581 | (*f) (count, bytes, NULL); |
| 1582 | } |
| 1583 | |
| 1584 | static void |
| 1585 | output_B4_format (f, rtype, label) |
| 1586 | vbyte_func f; |
| 1587 | unw_record_type rtype; |
| 1588 | unsigned long label; |
| 1589 | { |
| 1590 | char bytes[20]; |
| 1591 | int r = 0; |
| 1592 | int count = 1; |
| 1593 | if (label <= 0x1f) |
| 1594 | { |
| 1595 | output_B1_format (f, rtype, label); |
| 1596 | return; |
| 1597 | } |
| 1598 | |
| 1599 | if (rtype == copy_state) |
| 1600 | r = 1; |
| 1601 | else if (rtype != label_state) |
| 1602 | as_bad ("Invalid record type for format B1"); |
| 1603 | |
| 1604 | bytes[0] = (UNW_B4 | (r << 3)); |
| 1605 | count += output_leb128 (bytes + 1, label, 0); |
| 1606 | (*f) (count, bytes, NULL); |
| 1607 | } |
| 1608 | |
| 1609 | static char |
| 1610 | format_ab_reg (ab, reg) |
| 1611 | int ab; |
| 1612 | int reg; |
| 1613 | { |
| 1614 | int ret; |
| 1615 | ab = (ab & 3); |
| 1616 | reg = (reg & 0x1f); |
| 1617 | ret = (ab << 5) | reg; |
| 1618 | return ret; |
| 1619 | } |
| 1620 | |
| 1621 | static void |
| 1622 | output_X1_format (f, rtype, ab, reg, t, w1) |
| 1623 | vbyte_func f; |
| 1624 | unw_record_type rtype; |
| 1625 | int ab, reg; |
| 1626 | unsigned long t; |
| 1627 | unsigned long w1; |
| 1628 | { |
| 1629 | char bytes[20]; |
| 1630 | int r = 0; |
| 1631 | int count = 2; |
| 1632 | bytes[0] = UNW_X1; |
| 1633 | |
| 1634 | if (rtype == spill_sprel) |
| 1635 | r = 1; |
| 1636 | else if (rtype != spill_psprel) |
| 1637 | as_bad ("Invalid record type for format X1"); |
| 1638 | bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); |
| 1639 | count += output_leb128 (bytes + 2, t, 0); |
| 1640 | count += output_leb128 (bytes + count, w1, 0); |
| 1641 | (*f) (count, bytes, NULL); |
| 1642 | } |
| 1643 | |
| 1644 | static void |
| 1645 | output_X2_format (f, ab, reg, x, y, treg, t) |
| 1646 | vbyte_func f; |
| 1647 | int ab, reg; |
| 1648 | int x, y, treg; |
| 1649 | unsigned long t; |
| 1650 | { |
| 1651 | char bytes[20]; |
| 1652 | int count = 3; |
| 1653 | bytes[0] = UNW_X2; |
| 1654 | bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
| 1655 | bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); |
| 1656 | count += output_leb128 (bytes + 3, t, 0); |
| 1657 | (*f) (count, bytes, NULL); |
| 1658 | } |
| 1659 | |
| 1660 | static void |
| 1661 | output_X3_format (f, rtype, qp, ab, reg, t, w1) |
| 1662 | vbyte_func f; |
| 1663 | unw_record_type rtype; |
| 1664 | int qp; |
| 1665 | int ab, reg; |
| 1666 | unsigned long t; |
| 1667 | unsigned long w1; |
| 1668 | { |
| 1669 | char bytes[20]; |
| 1670 | int r = 0; |
| 1671 | int count = 3; |
| 1672 | bytes[0] = UNW_X3; |
| 1673 | |
| 1674 | if (rtype == spill_sprel_p) |
| 1675 | r = 1; |
| 1676 | else if (rtype != spill_psprel_p) |
| 1677 | as_bad ("Invalid record type for format X3"); |
| 1678 | bytes[1] = ((r << 7) | (qp & 0x3f)); |
| 1679 | bytes[2] = format_ab_reg (ab, reg); |
| 1680 | count += output_leb128 (bytes + 3, t, 0); |
| 1681 | count += output_leb128 (bytes + count, w1, 0); |
| 1682 | (*f) (count, bytes, NULL); |
| 1683 | } |
| 1684 | |
| 1685 | static void |
| 1686 | output_X4_format (f, qp, ab, reg, x, y, treg, t) |
| 1687 | vbyte_func f; |
| 1688 | int qp; |
| 1689 | int ab, reg; |
| 1690 | int x, y, treg; |
| 1691 | unsigned long t; |
| 1692 | { |
| 1693 | char bytes[20]; |
| 1694 | int count = 4; |
| 1695 | bytes[0] = UNW_X4; |
| 1696 | bytes[1] = (qp & 0x3f); |
| 1697 | bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
| 1698 | bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); |
| 1699 | count += output_leb128 (bytes + 4, t, 0); |
| 1700 | (*f) (count, bytes, NULL); |
| 1701 | } |
| 1702 | |
| 1703 | /* This function allocates a record list structure, and initializes fields. */ |
| 1704 | |
| 1705 | static unw_rec_list * |
| 1706 | alloc_record (unw_record_type t) |
| 1707 | { |
| 1708 | unw_rec_list *ptr; |
| 1709 | ptr = xmalloc (sizeof (*ptr)); |
| 1710 | ptr->next = NULL; |
| 1711 | ptr->slot_number = SLOT_NUM_NOT_SET; |
| 1712 | ptr->r.type = t; |
| 1713 | return ptr; |
| 1714 | } |
| 1715 | |
| 1716 | /* This function frees an entire list of record structures. */ |
| 1717 | |
| 1718 | void |
| 1719 | free_list_records (unw_rec_list *first) |
| 1720 | { |
| 1721 | unw_rec_list *ptr; |
| 1722 | for (ptr = first; ptr != NULL;) |
| 1723 | { |
| 1724 | unw_rec_list *tmp = ptr; |
| 1725 | |
| 1726 | if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) |
| 1727 | && tmp->r.record.r.mask.i) |
| 1728 | free (tmp->r.record.r.mask.i); |
| 1729 | |
| 1730 | ptr = ptr->next; |
| 1731 | free (tmp); |
| 1732 | } |
| 1733 | } |
| 1734 | |
| 1735 | static unw_rec_list * |
| 1736 | output_prologue () |
| 1737 | { |
| 1738 | unw_rec_list *ptr = alloc_record (prologue); |
| 1739 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
| 1740 | return ptr; |
| 1741 | } |
| 1742 | |
| 1743 | static unw_rec_list * |
| 1744 | output_prologue_gr (saved_mask, reg) |
| 1745 | unsigned int saved_mask; |
| 1746 | unsigned int reg; |
| 1747 | { |
| 1748 | unw_rec_list *ptr = alloc_record (prologue_gr); |
| 1749 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
| 1750 | ptr->r.record.r.grmask = saved_mask; |
| 1751 | ptr->r.record.r.grsave = reg; |
| 1752 | return ptr; |
| 1753 | } |
| 1754 | |
| 1755 | static unw_rec_list * |
| 1756 | output_body () |
| 1757 | { |
| 1758 | unw_rec_list *ptr = alloc_record (body); |
| 1759 | return ptr; |
| 1760 | } |
| 1761 | |
| 1762 | static unw_rec_list * |
| 1763 | output_mem_stack_f (size) |
| 1764 | unsigned int size; |
| 1765 | { |
| 1766 | unw_rec_list *ptr = alloc_record (mem_stack_f); |
| 1767 | ptr->r.record.p.size = size; |
| 1768 | return ptr; |
| 1769 | } |
| 1770 | |
| 1771 | static unw_rec_list * |
| 1772 | output_mem_stack_v () |
| 1773 | { |
| 1774 | unw_rec_list *ptr = alloc_record (mem_stack_v); |
| 1775 | return ptr; |
| 1776 | } |
| 1777 | |
| 1778 | static unw_rec_list * |
| 1779 | output_psp_gr (gr) |
| 1780 | unsigned int gr; |
| 1781 | { |
| 1782 | unw_rec_list *ptr = alloc_record (psp_gr); |
| 1783 | ptr->r.record.p.gr = gr; |
| 1784 | return ptr; |
| 1785 | } |
| 1786 | |
| 1787 | static unw_rec_list * |
| 1788 | output_psp_sprel (offset) |
| 1789 | unsigned int offset; |
| 1790 | { |
| 1791 | unw_rec_list *ptr = alloc_record (psp_sprel); |
| 1792 | ptr->r.record.p.spoff = offset / 4; |
| 1793 | return ptr; |
| 1794 | } |
| 1795 | |
| 1796 | static unw_rec_list * |
| 1797 | output_rp_when () |
| 1798 | { |
| 1799 | unw_rec_list *ptr = alloc_record (rp_when); |
| 1800 | return ptr; |
| 1801 | } |
| 1802 | |
| 1803 | static unw_rec_list * |
| 1804 | output_rp_gr (gr) |
| 1805 | unsigned int gr; |
| 1806 | { |
| 1807 | unw_rec_list *ptr = alloc_record (rp_gr); |
| 1808 | ptr->r.record.p.gr = gr; |
| 1809 | return ptr; |
| 1810 | } |
| 1811 | |
| 1812 | static unw_rec_list * |
| 1813 | output_rp_br (br) |
| 1814 | unsigned int br; |
| 1815 | { |
| 1816 | unw_rec_list *ptr = alloc_record (rp_br); |
| 1817 | ptr->r.record.p.br = br; |
| 1818 | return ptr; |
| 1819 | } |
| 1820 | |
| 1821 | static unw_rec_list * |
| 1822 | output_rp_psprel (offset) |
| 1823 | unsigned int offset; |
| 1824 | { |
| 1825 | unw_rec_list *ptr = alloc_record (rp_psprel); |
| 1826 | ptr->r.record.p.pspoff = offset / 4; |
| 1827 | return ptr; |
| 1828 | } |
| 1829 | |
| 1830 | static unw_rec_list * |
| 1831 | output_rp_sprel (offset) |
| 1832 | unsigned int offset; |
| 1833 | { |
| 1834 | unw_rec_list *ptr = alloc_record (rp_sprel); |
| 1835 | ptr->r.record.p.spoff = offset / 4; |
| 1836 | return ptr; |
| 1837 | } |
| 1838 | |
| 1839 | static unw_rec_list * |
| 1840 | output_pfs_when () |
| 1841 | { |
| 1842 | unw_rec_list *ptr = alloc_record (pfs_when); |
| 1843 | return ptr; |
| 1844 | } |
| 1845 | |
| 1846 | static unw_rec_list * |
| 1847 | output_pfs_gr (gr) |
| 1848 | unsigned int gr; |
| 1849 | { |
| 1850 | unw_rec_list *ptr = alloc_record (pfs_gr); |
| 1851 | ptr->r.record.p.gr = gr; |
| 1852 | return ptr; |
| 1853 | } |
| 1854 | |
| 1855 | static unw_rec_list * |
| 1856 | output_pfs_psprel (offset) |
| 1857 | unsigned int offset; |
| 1858 | { |
| 1859 | unw_rec_list *ptr = alloc_record (pfs_psprel); |
| 1860 | ptr->r.record.p.pspoff = offset / 4; |
| 1861 | return ptr; |
| 1862 | } |
| 1863 | |
| 1864 | static unw_rec_list * |
| 1865 | output_pfs_sprel (offset) |
| 1866 | unsigned int offset; |
| 1867 | { |
| 1868 | unw_rec_list *ptr = alloc_record (pfs_sprel); |
| 1869 | ptr->r.record.p.spoff = offset / 4; |
| 1870 | return ptr; |
| 1871 | } |
| 1872 | |
| 1873 | static unw_rec_list * |
| 1874 | output_preds_when () |
| 1875 | { |
| 1876 | unw_rec_list *ptr = alloc_record (preds_when); |
| 1877 | return ptr; |
| 1878 | } |
| 1879 | |
| 1880 | static unw_rec_list * |
| 1881 | output_preds_gr (gr) |
| 1882 | unsigned int gr; |
| 1883 | { |
| 1884 | unw_rec_list *ptr = alloc_record (preds_gr); |
| 1885 | ptr->r.record.p.gr = gr; |
| 1886 | return ptr; |
| 1887 | } |
| 1888 | |
| 1889 | static unw_rec_list * |
| 1890 | output_preds_psprel (offset) |
| 1891 | unsigned int offset; |
| 1892 | { |
| 1893 | unw_rec_list *ptr = alloc_record (preds_psprel); |
| 1894 | ptr->r.record.p.pspoff = offset / 4; |
| 1895 | return ptr; |
| 1896 | } |
| 1897 | |
| 1898 | static unw_rec_list * |
| 1899 | output_preds_sprel (offset) |
| 1900 | unsigned int offset; |
| 1901 | { |
| 1902 | unw_rec_list *ptr = alloc_record (preds_sprel); |
| 1903 | ptr->r.record.p.spoff = offset / 4; |
| 1904 | return ptr; |
| 1905 | } |
| 1906 | |
| 1907 | static unw_rec_list * |
| 1908 | output_fr_mem (mask) |
| 1909 | unsigned int mask; |
| 1910 | { |
| 1911 | unw_rec_list *ptr = alloc_record (fr_mem); |
| 1912 | ptr->r.record.p.rmask = mask; |
| 1913 | return ptr; |
| 1914 | } |
| 1915 | |
| 1916 | static unw_rec_list * |
| 1917 | output_frgr_mem (gr_mask, fr_mask) |
| 1918 | unsigned int gr_mask; |
| 1919 | unsigned int fr_mask; |
| 1920 | { |
| 1921 | unw_rec_list *ptr = alloc_record (frgr_mem); |
| 1922 | ptr->r.record.p.grmask = gr_mask; |
| 1923 | ptr->r.record.p.frmask = fr_mask; |
| 1924 | return ptr; |
| 1925 | } |
| 1926 | |
| 1927 | static unw_rec_list * |
| 1928 | output_gr_gr (mask, reg) |
| 1929 | unsigned int mask; |
| 1930 | unsigned int reg; |
| 1931 | { |
| 1932 | unw_rec_list *ptr = alloc_record (gr_gr); |
| 1933 | ptr->r.record.p.grmask = mask; |
| 1934 | ptr->r.record.p.gr = reg; |
| 1935 | return ptr; |
| 1936 | } |
| 1937 | |
| 1938 | static unw_rec_list * |
| 1939 | output_gr_mem (mask) |
| 1940 | unsigned int mask; |
| 1941 | { |
| 1942 | unw_rec_list *ptr = alloc_record (gr_mem); |
| 1943 | ptr->r.record.p.rmask = mask; |
| 1944 | return ptr; |
| 1945 | } |
| 1946 | |
| 1947 | static unw_rec_list * |
| 1948 | output_br_mem (unsigned int mask) |
| 1949 | { |
| 1950 | unw_rec_list *ptr = alloc_record (br_mem); |
| 1951 | ptr->r.record.p.brmask = mask; |
| 1952 | return ptr; |
| 1953 | } |
| 1954 | |
| 1955 | static unw_rec_list * |
| 1956 | output_br_gr (save_mask, reg) |
| 1957 | unsigned int save_mask; |
| 1958 | unsigned int reg; |
| 1959 | { |
| 1960 | unw_rec_list *ptr = alloc_record (br_gr); |
| 1961 | ptr->r.record.p.brmask = save_mask; |
| 1962 | ptr->r.record.p.gr = reg; |
| 1963 | return ptr; |
| 1964 | } |
| 1965 | |
| 1966 | static unw_rec_list * |
| 1967 | output_spill_base (offset) |
| 1968 | unsigned int offset; |
| 1969 | { |
| 1970 | unw_rec_list *ptr = alloc_record (spill_base); |
| 1971 | ptr->r.record.p.pspoff = offset / 4; |
| 1972 | return ptr; |
| 1973 | } |
| 1974 | |
| 1975 | static unw_rec_list * |
| 1976 | output_unat_when () |
| 1977 | { |
| 1978 | unw_rec_list *ptr = alloc_record (unat_when); |
| 1979 | return ptr; |
| 1980 | } |
| 1981 | |
| 1982 | static unw_rec_list * |
| 1983 | output_unat_gr (gr) |
| 1984 | unsigned int gr; |
| 1985 | { |
| 1986 | unw_rec_list *ptr = alloc_record (unat_gr); |
| 1987 | ptr->r.record.p.gr = gr; |
| 1988 | return ptr; |
| 1989 | } |
| 1990 | |
| 1991 | static unw_rec_list * |
| 1992 | output_unat_psprel (offset) |
| 1993 | unsigned int offset; |
| 1994 | { |
| 1995 | unw_rec_list *ptr = alloc_record (unat_psprel); |
| 1996 | ptr->r.record.p.pspoff = offset / 4; |
| 1997 | return ptr; |
| 1998 | } |
| 1999 | |
| 2000 | static unw_rec_list * |
| 2001 | output_unat_sprel (offset) |
| 2002 | unsigned int offset; |
| 2003 | { |
| 2004 | unw_rec_list *ptr = alloc_record (unat_sprel); |
| 2005 | ptr->r.record.p.spoff = offset / 4; |
| 2006 | return ptr; |
| 2007 | } |
| 2008 | |
| 2009 | static unw_rec_list * |
| 2010 | output_lc_when () |
| 2011 | { |
| 2012 | unw_rec_list *ptr = alloc_record (lc_when); |
| 2013 | return ptr; |
| 2014 | } |
| 2015 | |
| 2016 | static unw_rec_list * |
| 2017 | output_lc_gr (gr) |
| 2018 | unsigned int gr; |
| 2019 | { |
| 2020 | unw_rec_list *ptr = alloc_record (lc_gr); |
| 2021 | ptr->r.record.p.gr = gr; |
| 2022 | return ptr; |
| 2023 | } |
| 2024 | |
| 2025 | static unw_rec_list * |
| 2026 | output_lc_psprel (offset) |
| 2027 | unsigned int offset; |
| 2028 | { |
| 2029 | unw_rec_list *ptr = alloc_record (lc_psprel); |
| 2030 | ptr->r.record.p.pspoff = offset / 4; |
| 2031 | return ptr; |
| 2032 | } |
| 2033 | |
| 2034 | static unw_rec_list * |
| 2035 | output_lc_sprel (offset) |
| 2036 | unsigned int offset; |
| 2037 | { |
| 2038 | unw_rec_list *ptr = alloc_record (lc_sprel); |
| 2039 | ptr->r.record.p.spoff = offset / 4; |
| 2040 | return ptr; |
| 2041 | } |
| 2042 | |
| 2043 | static unw_rec_list * |
| 2044 | output_fpsr_when () |
| 2045 | { |
| 2046 | unw_rec_list *ptr = alloc_record (fpsr_when); |
| 2047 | return ptr; |
| 2048 | } |
| 2049 | |
| 2050 | static unw_rec_list * |
| 2051 | output_fpsr_gr (gr) |
| 2052 | unsigned int gr; |
| 2053 | { |
| 2054 | unw_rec_list *ptr = alloc_record (fpsr_gr); |
| 2055 | ptr->r.record.p.gr = gr; |
| 2056 | return ptr; |
| 2057 | } |
| 2058 | |
| 2059 | static unw_rec_list * |
| 2060 | output_fpsr_psprel (offset) |
| 2061 | unsigned int offset; |
| 2062 | { |
| 2063 | unw_rec_list *ptr = alloc_record (fpsr_psprel); |
| 2064 | ptr->r.record.p.pspoff = offset / 4; |
| 2065 | return ptr; |
| 2066 | } |
| 2067 | |
| 2068 | static unw_rec_list * |
| 2069 | output_fpsr_sprel (offset) |
| 2070 | unsigned int offset; |
| 2071 | { |
| 2072 | unw_rec_list *ptr = alloc_record (fpsr_sprel); |
| 2073 | ptr->r.record.p.spoff = offset / 4; |
| 2074 | return ptr; |
| 2075 | } |
| 2076 | |
| 2077 | static unw_rec_list * |
| 2078 | output_priunat_when_gr () |
| 2079 | { |
| 2080 | unw_rec_list *ptr = alloc_record (priunat_when_gr); |
| 2081 | return ptr; |
| 2082 | } |
| 2083 | |
| 2084 | static unw_rec_list * |
| 2085 | output_priunat_when_mem () |
| 2086 | { |
| 2087 | unw_rec_list *ptr = alloc_record (priunat_when_mem); |
| 2088 | return ptr; |
| 2089 | } |
| 2090 | |
| 2091 | static unw_rec_list * |
| 2092 | output_priunat_gr (gr) |
| 2093 | unsigned int gr; |
| 2094 | { |
| 2095 | unw_rec_list *ptr = alloc_record (priunat_gr); |
| 2096 | ptr->r.record.p.gr = gr; |
| 2097 | return ptr; |
| 2098 | } |
| 2099 | |
| 2100 | static unw_rec_list * |
| 2101 | output_priunat_psprel (offset) |
| 2102 | unsigned int offset; |
| 2103 | { |
| 2104 | unw_rec_list *ptr = alloc_record (priunat_psprel); |
| 2105 | ptr->r.record.p.pspoff = offset / 4; |
| 2106 | return ptr; |
| 2107 | } |
| 2108 | |
| 2109 | static unw_rec_list * |
| 2110 | output_priunat_sprel (offset) |
| 2111 | unsigned int offset; |
| 2112 | { |
| 2113 | unw_rec_list *ptr = alloc_record (priunat_sprel); |
| 2114 | ptr->r.record.p.spoff = offset / 4; |
| 2115 | return ptr; |
| 2116 | } |
| 2117 | |
| 2118 | static unw_rec_list * |
| 2119 | output_bsp_when () |
| 2120 | { |
| 2121 | unw_rec_list *ptr = alloc_record (bsp_when); |
| 2122 | return ptr; |
| 2123 | } |
| 2124 | |
| 2125 | static unw_rec_list * |
| 2126 | output_bsp_gr (gr) |
| 2127 | unsigned int gr; |
| 2128 | { |
| 2129 | unw_rec_list *ptr = alloc_record (bsp_gr); |
| 2130 | ptr->r.record.p.gr = gr; |
| 2131 | return ptr; |
| 2132 | } |
| 2133 | |
| 2134 | static unw_rec_list * |
| 2135 | output_bsp_psprel (offset) |
| 2136 | unsigned int offset; |
| 2137 | { |
| 2138 | unw_rec_list *ptr = alloc_record (bsp_psprel); |
| 2139 | ptr->r.record.p.pspoff = offset / 4; |
| 2140 | return ptr; |
| 2141 | } |
| 2142 | |
| 2143 | static unw_rec_list * |
| 2144 | output_bsp_sprel (offset) |
| 2145 | unsigned int offset; |
| 2146 | { |
| 2147 | unw_rec_list *ptr = alloc_record (bsp_sprel); |
| 2148 | ptr->r.record.p.spoff = offset / 4; |
| 2149 | return ptr; |
| 2150 | } |
| 2151 | |
| 2152 | static unw_rec_list * |
| 2153 | output_bspstore_when () |
| 2154 | { |
| 2155 | unw_rec_list *ptr = alloc_record (bspstore_when); |
| 2156 | return ptr; |
| 2157 | } |
| 2158 | |
| 2159 | static unw_rec_list * |
| 2160 | output_bspstore_gr (gr) |
| 2161 | unsigned int gr; |
| 2162 | { |
| 2163 | unw_rec_list *ptr = alloc_record (bspstore_gr); |
| 2164 | ptr->r.record.p.gr = gr; |
| 2165 | return ptr; |
| 2166 | } |
| 2167 | |
| 2168 | static unw_rec_list * |
| 2169 | output_bspstore_psprel (offset) |
| 2170 | unsigned int offset; |
| 2171 | { |
| 2172 | unw_rec_list *ptr = alloc_record (bspstore_psprel); |
| 2173 | ptr->r.record.p.pspoff = offset / 4; |
| 2174 | return ptr; |
| 2175 | } |
| 2176 | |
| 2177 | static unw_rec_list * |
| 2178 | output_bspstore_sprel (offset) |
| 2179 | unsigned int offset; |
| 2180 | { |
| 2181 | unw_rec_list *ptr = alloc_record (bspstore_sprel); |
| 2182 | ptr->r.record.p.spoff = offset / 4; |
| 2183 | return ptr; |
| 2184 | } |
| 2185 | |
| 2186 | static unw_rec_list * |
| 2187 | output_rnat_when () |
| 2188 | { |
| 2189 | unw_rec_list *ptr = alloc_record (rnat_when); |
| 2190 | return ptr; |
| 2191 | } |
| 2192 | |
| 2193 | static unw_rec_list * |
| 2194 | output_rnat_gr (gr) |
| 2195 | unsigned int gr; |
| 2196 | { |
| 2197 | unw_rec_list *ptr = alloc_record (rnat_gr); |
| 2198 | ptr->r.record.p.gr = gr; |
| 2199 | return ptr; |
| 2200 | } |
| 2201 | |
| 2202 | static unw_rec_list * |
| 2203 | output_rnat_psprel (offset) |
| 2204 | unsigned int offset; |
| 2205 | { |
| 2206 | unw_rec_list *ptr = alloc_record (rnat_psprel); |
| 2207 | ptr->r.record.p.pspoff = offset / 4; |
| 2208 | return ptr; |
| 2209 | } |
| 2210 | |
| 2211 | static unw_rec_list * |
| 2212 | output_rnat_sprel (offset) |
| 2213 | unsigned int offset; |
| 2214 | { |
| 2215 | unw_rec_list *ptr = alloc_record (rnat_sprel); |
| 2216 | ptr->r.record.p.spoff = offset / 4; |
| 2217 | return ptr; |
| 2218 | } |
| 2219 | |
| 2220 | static unw_rec_list * |
| 2221 | output_unwabi (abi, context) |
| 2222 | unsigned long abi; |
| 2223 | unsigned long context; |
| 2224 | { |
| 2225 | unw_rec_list *ptr = alloc_record (unwabi); |
| 2226 | ptr->r.record.p.abi = abi; |
| 2227 | ptr->r.record.p.context = context; |
| 2228 | return ptr; |
| 2229 | } |
| 2230 | |
| 2231 | static unw_rec_list * |
| 2232 | output_epilogue (unsigned long ecount) |
| 2233 | { |
| 2234 | unw_rec_list *ptr = alloc_record (epilogue); |
| 2235 | ptr->r.record.b.ecount = ecount; |
| 2236 | return ptr; |
| 2237 | } |
| 2238 | |
| 2239 | static unw_rec_list * |
| 2240 | output_label_state (unsigned long label) |
| 2241 | { |
| 2242 | unw_rec_list *ptr = alloc_record (label_state); |
| 2243 | ptr->r.record.b.label = label; |
| 2244 | return ptr; |
| 2245 | } |
| 2246 | |
| 2247 | static unw_rec_list * |
| 2248 | output_copy_state (unsigned long label) |
| 2249 | { |
| 2250 | unw_rec_list *ptr = alloc_record (copy_state); |
| 2251 | ptr->r.record.b.label = label; |
| 2252 | return ptr; |
| 2253 | } |
| 2254 | |
| 2255 | static unw_rec_list * |
| 2256 | output_spill_psprel (ab, reg, offset) |
| 2257 | unsigned int ab; |
| 2258 | unsigned int reg; |
| 2259 | unsigned int offset; |
| 2260 | { |
| 2261 | unw_rec_list *ptr = alloc_record (spill_psprel); |
| 2262 | ptr->r.record.x.ab = ab; |
| 2263 | ptr->r.record.x.reg = reg; |
| 2264 | ptr->r.record.x.pspoff = offset / 4; |
| 2265 | return ptr; |
| 2266 | } |
| 2267 | |
| 2268 | static unw_rec_list * |
| 2269 | output_spill_sprel (ab, reg, offset) |
| 2270 | unsigned int ab; |
| 2271 | unsigned int reg; |
| 2272 | unsigned int offset; |
| 2273 | { |
| 2274 | unw_rec_list *ptr = alloc_record (spill_sprel); |
| 2275 | ptr->r.record.x.ab = ab; |
| 2276 | ptr->r.record.x.reg = reg; |
| 2277 | ptr->r.record.x.spoff = offset / 4; |
| 2278 | return ptr; |
| 2279 | } |
| 2280 | |
| 2281 | static unw_rec_list * |
| 2282 | output_spill_psprel_p (ab, reg, offset, predicate) |
| 2283 | unsigned int ab; |
| 2284 | unsigned int reg; |
| 2285 | unsigned int offset; |
| 2286 | unsigned int predicate; |
| 2287 | { |
| 2288 | unw_rec_list *ptr = alloc_record (spill_psprel_p); |
| 2289 | ptr->r.record.x.ab = ab; |
| 2290 | ptr->r.record.x.reg = reg; |
| 2291 | ptr->r.record.x.pspoff = offset / 4; |
| 2292 | ptr->r.record.x.qp = predicate; |
| 2293 | return ptr; |
| 2294 | } |
| 2295 | |
| 2296 | static unw_rec_list * |
| 2297 | output_spill_sprel_p (ab, reg, offset, predicate) |
| 2298 | unsigned int ab; |
| 2299 | unsigned int reg; |
| 2300 | unsigned int offset; |
| 2301 | unsigned int predicate; |
| 2302 | { |
| 2303 | unw_rec_list *ptr = alloc_record (spill_sprel_p); |
| 2304 | ptr->r.record.x.ab = ab; |
| 2305 | ptr->r.record.x.reg = reg; |
| 2306 | ptr->r.record.x.spoff = offset / 4; |
| 2307 | ptr->r.record.x.qp = predicate; |
| 2308 | return ptr; |
| 2309 | } |
| 2310 | |
| 2311 | static unw_rec_list * |
| 2312 | output_spill_reg (ab, reg, targ_reg, xy) |
| 2313 | unsigned int ab; |
| 2314 | unsigned int reg; |
| 2315 | unsigned int targ_reg; |
| 2316 | unsigned int xy; |
| 2317 | { |
| 2318 | unw_rec_list *ptr = alloc_record (spill_reg); |
| 2319 | ptr->r.record.x.ab = ab; |
| 2320 | ptr->r.record.x.reg = reg; |
| 2321 | ptr->r.record.x.treg = targ_reg; |
| 2322 | ptr->r.record.x.xy = xy; |
| 2323 | return ptr; |
| 2324 | } |
| 2325 | |
| 2326 | static unw_rec_list * |
| 2327 | output_spill_reg_p (ab, reg, targ_reg, xy, predicate) |
| 2328 | unsigned int ab; |
| 2329 | unsigned int reg; |
| 2330 | unsigned int targ_reg; |
| 2331 | unsigned int xy; |
| 2332 | unsigned int predicate; |
| 2333 | { |
| 2334 | unw_rec_list *ptr = alloc_record (spill_reg_p); |
| 2335 | ptr->r.record.x.ab = ab; |
| 2336 | ptr->r.record.x.reg = reg; |
| 2337 | ptr->r.record.x.treg = targ_reg; |
| 2338 | ptr->r.record.x.xy = xy; |
| 2339 | ptr->r.record.x.qp = predicate; |
| 2340 | return ptr; |
| 2341 | } |
| 2342 | |
| 2343 | /* Given a unw_rec_list process the correct format with the |
| 2344 | specified function. */ |
| 2345 | |
| 2346 | static void |
| 2347 | process_one_record (ptr, f) |
| 2348 | unw_rec_list *ptr; |
| 2349 | vbyte_func f; |
| 2350 | { |
| 2351 | unsigned long fr_mask, gr_mask; |
| 2352 | |
| 2353 | switch (ptr->r.type) |
| 2354 | { |
| 2355 | case gr_mem: |
| 2356 | case fr_mem: |
| 2357 | case br_mem: |
| 2358 | case frgr_mem: |
| 2359 | /* These are taken care of by prologue/prologue_gr. */ |
| 2360 | break; |
| 2361 | |
| 2362 | case prologue_gr: |
| 2363 | case prologue: |
| 2364 | if (ptr->r.type == prologue_gr) |
| 2365 | output_R2_format (f, ptr->r.record.r.grmask, |
| 2366 | ptr->r.record.r.grsave, ptr->r.record.r.rlen); |
| 2367 | else |
| 2368 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); |
| 2369 | |
| 2370 | /* Output descriptor(s) for union of register spills (if any). */ |
| 2371 | gr_mask = ptr->r.record.r.mask.gr_mem; |
| 2372 | fr_mask = ptr->r.record.r.mask.fr_mem; |
| 2373 | if (fr_mask) |
| 2374 | { |
| 2375 | if ((fr_mask & ~0xfUL) == 0) |
| 2376 | output_P6_format (f, fr_mem, fr_mask); |
| 2377 | else |
| 2378 | { |
| 2379 | output_P5_format (f, gr_mask, fr_mask); |
| 2380 | gr_mask = 0; |
| 2381 | } |
| 2382 | } |
| 2383 | if (gr_mask) |
| 2384 | output_P6_format (f, gr_mem, gr_mask); |
| 2385 | if (ptr->r.record.r.mask.br_mem) |
| 2386 | output_P1_format (f, ptr->r.record.r.mask.br_mem); |
| 2387 | |
| 2388 | /* output imask descriptor if necessary: */ |
| 2389 | if (ptr->r.record.r.mask.i) |
| 2390 | output_P4_format (f, ptr->r.record.r.mask.i, |
| 2391 | ptr->r.record.r.imask_size); |
| 2392 | break; |
| 2393 | |
| 2394 | case body: |
| 2395 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); |
| 2396 | break; |
| 2397 | case mem_stack_f: |
| 2398 | case mem_stack_v: |
| 2399 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, |
| 2400 | ptr->r.record.p.size); |
| 2401 | break; |
| 2402 | case psp_gr: |
| 2403 | case rp_gr: |
| 2404 | case pfs_gr: |
| 2405 | case preds_gr: |
| 2406 | case unat_gr: |
| 2407 | case lc_gr: |
| 2408 | case fpsr_gr: |
| 2409 | case priunat_gr: |
| 2410 | case bsp_gr: |
| 2411 | case bspstore_gr: |
| 2412 | case rnat_gr: |
| 2413 | output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); |
| 2414 | break; |
| 2415 | case rp_br: |
| 2416 | output_P3_format (f, rp_br, ptr->r.record.p.br); |
| 2417 | break; |
| 2418 | case psp_sprel: |
| 2419 | output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); |
| 2420 | break; |
| 2421 | case rp_when: |
| 2422 | case pfs_when: |
| 2423 | case preds_when: |
| 2424 | case unat_when: |
| 2425 | case lc_when: |
| 2426 | case fpsr_when: |
| 2427 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); |
| 2428 | break; |
| 2429 | case rp_psprel: |
| 2430 | case pfs_psprel: |
| 2431 | case preds_psprel: |
| 2432 | case unat_psprel: |
| 2433 | case lc_psprel: |
| 2434 | case fpsr_psprel: |
| 2435 | case spill_base: |
| 2436 | output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); |
| 2437 | break; |
| 2438 | case rp_sprel: |
| 2439 | case pfs_sprel: |
| 2440 | case preds_sprel: |
| 2441 | case unat_sprel: |
| 2442 | case lc_sprel: |
| 2443 | case fpsr_sprel: |
| 2444 | case priunat_sprel: |
| 2445 | case bsp_sprel: |
| 2446 | case bspstore_sprel: |
| 2447 | case rnat_sprel: |
| 2448 | output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); |
| 2449 | break; |
| 2450 | case gr_gr: |
| 2451 | output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); |
| 2452 | break; |
| 2453 | case br_gr: |
| 2454 | output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); |
| 2455 | break; |
| 2456 | case spill_mask: |
| 2457 | as_bad ("spill_mask record unimplemented."); |
| 2458 | break; |
| 2459 | case priunat_when_gr: |
| 2460 | case priunat_when_mem: |
| 2461 | case bsp_when: |
| 2462 | case bspstore_when: |
| 2463 | case rnat_when: |
| 2464 | output_P8_format (f, ptr->r.type, ptr->r.record.p.t); |
| 2465 | break; |
| 2466 | case priunat_psprel: |
| 2467 | case bsp_psprel: |
| 2468 | case bspstore_psprel: |
| 2469 | case rnat_psprel: |
| 2470 | output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); |
| 2471 | break; |
| 2472 | case unwabi: |
| 2473 | output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); |
| 2474 | break; |
| 2475 | case epilogue: |
| 2476 | output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); |
| 2477 | break; |
| 2478 | case label_state: |
| 2479 | case copy_state: |
| 2480 | output_B4_format (f, ptr->r.type, ptr->r.record.b.label); |
| 2481 | break; |
| 2482 | case spill_psprel: |
| 2483 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, |
| 2484 | ptr->r.record.x.reg, ptr->r.record.x.t, |
| 2485 | ptr->r.record.x.pspoff); |
| 2486 | break; |
| 2487 | case spill_sprel: |
| 2488 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, |
| 2489 | ptr->r.record.x.reg, ptr->r.record.x.t, |
| 2490 | ptr->r.record.x.spoff); |
| 2491 | break; |
| 2492 | case spill_reg: |
| 2493 | output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, |
| 2494 | ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, |
| 2495 | ptr->r.record.x.treg, ptr->r.record.x.t); |
| 2496 | break; |
| 2497 | case spill_psprel_p: |
| 2498 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, |
| 2499 | ptr->r.record.x.ab, ptr->r.record.x.reg, |
| 2500 | ptr->r.record.x.t, ptr->r.record.x.pspoff); |
| 2501 | break; |
| 2502 | case spill_sprel_p: |
| 2503 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, |
| 2504 | ptr->r.record.x.ab, ptr->r.record.x.reg, |
| 2505 | ptr->r.record.x.t, ptr->r.record.x.spoff); |
| 2506 | break; |
| 2507 | case spill_reg_p: |
| 2508 | output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, |
| 2509 | ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, |
| 2510 | ptr->r.record.x.xy, ptr->r.record.x.treg, |
| 2511 | ptr->r.record.x.t); |
| 2512 | break; |
| 2513 | default: |
| 2514 | as_bad ("record_type_not_valid"); |
| 2515 | break; |
| 2516 | } |
| 2517 | } |
| 2518 | |
| 2519 | /* Given a unw_rec_list list, process all the records with |
| 2520 | the specified function. */ |
| 2521 | static void |
| 2522 | process_unw_records (list, f) |
| 2523 | unw_rec_list *list; |
| 2524 | vbyte_func f; |
| 2525 | { |
| 2526 | unw_rec_list *ptr; |
| 2527 | for (ptr = list; ptr; ptr = ptr->next) |
| 2528 | process_one_record (ptr, f); |
| 2529 | } |
| 2530 | |
| 2531 | /* Determine the size of a record list in bytes. */ |
| 2532 | static int |
| 2533 | calc_record_size (list) |
| 2534 | unw_rec_list *list; |
| 2535 | { |
| 2536 | vbyte_count = 0; |
| 2537 | process_unw_records (list, count_output); |
| 2538 | return vbyte_count; |
| 2539 | } |
| 2540 | |
| 2541 | /* Update IMASK bitmask to reflect the fact that one or more registers |
| 2542 | of type TYPE are saved starting at instruction with index T. If N |
| 2543 | bits are set in REGMASK, it is assumed that instructions T through |
| 2544 | T+N-1 save these registers. |
| 2545 | |
| 2546 | TYPE values: |
| 2547 | 0: no save |
| 2548 | 1: instruction saves next fp reg |
| 2549 | 2: instruction saves next general reg |
| 2550 | 3: instruction saves next branch reg */ |
| 2551 | static void |
| 2552 | set_imask (region, regmask, t, type) |
| 2553 | unw_rec_list *region; |
| 2554 | unsigned long regmask; |
| 2555 | unsigned long t; |
| 2556 | unsigned int type; |
| 2557 | { |
| 2558 | unsigned char *imask; |
| 2559 | unsigned long imask_size; |
| 2560 | unsigned int i; |
| 2561 | int pos; |
| 2562 | |
| 2563 | imask = region->r.record.r.mask.i; |
| 2564 | imask_size = region->r.record.r.imask_size; |
| 2565 | if (!imask) |
| 2566 | { |
| 2567 | imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; |
| 2568 | imask = xmalloc (imask_size); |
| 2569 | memset (imask, 0, imask_size); |
| 2570 | |
| 2571 | region->r.record.r.imask_size = imask_size; |
| 2572 | region->r.record.r.mask.i = imask; |
| 2573 | } |
| 2574 | |
| 2575 | i = (t / 4) + 1; |
| 2576 | pos = 2 * (3 - t % 4); |
| 2577 | while (regmask) |
| 2578 | { |
| 2579 | if (i >= imask_size) |
| 2580 | { |
| 2581 | as_bad ("Ignoring attempt to spill beyond end of region"); |
| 2582 | return; |
| 2583 | } |
| 2584 | |
| 2585 | imask[i] |= (type & 0x3) << pos; |
| 2586 | |
| 2587 | regmask &= (regmask - 1); |
| 2588 | pos -= 2; |
| 2589 | if (pos < 0) |
| 2590 | { |
| 2591 | pos = 0; |
| 2592 | ++i; |
| 2593 | } |
| 2594 | } |
| 2595 | } |
| 2596 | |
| 2597 | static int |
| 2598 | count_bits (unsigned long mask) |
| 2599 | { |
| 2600 | int n = 0; |
| 2601 | |
| 2602 | while (mask) |
| 2603 | { |
| 2604 | mask &= mask - 1; |
| 2605 | ++n; |
| 2606 | } |
| 2607 | return n; |
| 2608 | } |
| 2609 | |
| 2610 | /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. |
| 2611 | SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag |
| 2612 | containing FIRST_ADDR. */ |
| 2613 | |
| 2614 | unsigned long |
| 2615 | slot_index (slot_addr, slot_frag, first_addr, first_frag) |
| 2616 | unsigned long slot_addr; |
| 2617 | fragS *slot_frag; |
| 2618 | unsigned long first_addr; |
| 2619 | fragS *first_frag; |
| 2620 | { |
| 2621 | unsigned long index = 0; |
| 2622 | |
| 2623 | /* First time we are called, the initial address and frag are invalid. */ |
| 2624 | if (first_addr == 0) |
| 2625 | return 0; |
| 2626 | |
| 2627 | /* If the two addresses are in different frags, then we need to add in |
| 2628 | the remaining size of this frag, and then the entire size of intermediate |
| 2629 | frags. */ |
| 2630 | while (slot_frag != first_frag) |
| 2631 | { |
| 2632 | unsigned long start_addr = (unsigned long) &first_frag->fr_literal; |
| 2633 | |
| 2634 | /* Add in the full size of the frag converted to instruction slots. */ |
| 2635 | index += 3 * (first_frag->fr_fix >> 4); |
| 2636 | /* Subtract away the initial part before first_addr. */ |
| 2637 | index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) |
| 2638 | + ((first_addr & 0x3) - (start_addr & 0x3))); |
| 2639 | |
| 2640 | /* Move to the beginning of the next frag. */ |
| 2641 | first_frag = first_frag->fr_next; |
| 2642 | first_addr = (unsigned long) &first_frag->fr_literal; |
| 2643 | } |
| 2644 | |
| 2645 | /* Add in the used part of the last frag. */ |
| 2646 | index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) |
| 2647 | + ((slot_addr & 0x3) - (first_addr & 0x3))); |
| 2648 | return index; |
| 2649 | } |
| 2650 | |
| 2651 | /* Optimize unwind record directives. */ |
| 2652 | |
| 2653 | static unw_rec_list * |
| 2654 | optimize_unw_records (list) |
| 2655 | unw_rec_list *list; |
| 2656 | { |
| 2657 | if (!list) |
| 2658 | return NULL; |
| 2659 | |
| 2660 | /* If the only unwind record is ".prologue" or ".prologue" followed |
| 2661 | by ".body", then we can optimize the unwind directives away. */ |
| 2662 | if (list->r.type == prologue |
| 2663 | && (list->next == NULL |
| 2664 | || (list->next->r.type == body && list->next->next == NULL))) |
| 2665 | return NULL; |
| 2666 | |
| 2667 | return list; |
| 2668 | } |
| 2669 | |
| 2670 | /* Given a complete record list, process any records which have |
| 2671 | unresolved fields, (ie length counts for a prologue). After |
| 2672 | this has been run, all neccessary information should be available |
| 2673 | within each record to generate an image. */ |
| 2674 | |
| 2675 | static void |
| 2676 | fixup_unw_records (list) |
| 2677 | unw_rec_list *list; |
| 2678 | { |
| 2679 | unw_rec_list *ptr, *region = 0; |
| 2680 | unsigned long first_addr = 0, rlen = 0, t; |
| 2681 | fragS *first_frag = 0; |
| 2682 | |
| 2683 | for (ptr = list; ptr; ptr = ptr->next) |
| 2684 | { |
| 2685 | if (ptr->slot_number == SLOT_NUM_NOT_SET) |
| 2686 | as_bad (" Insn slot not set in unwind record."); |
| 2687 | t = slot_index (ptr->slot_number, ptr->slot_frag, |
| 2688 | first_addr, first_frag); |
| 2689 | switch (ptr->r.type) |
| 2690 | { |
| 2691 | case prologue: |
| 2692 | case prologue_gr: |
| 2693 | case body: |
| 2694 | { |
| 2695 | unw_rec_list *last; |
| 2696 | int size, dir_len = 0; |
| 2697 | unsigned long last_addr; |
| 2698 | fragS *last_frag; |
| 2699 | |
| 2700 | first_addr = ptr->slot_number; |
| 2701 | first_frag = ptr->slot_frag; |
| 2702 | ptr->slot_number = 0; |
| 2703 | /* Find either the next body/prologue start, or the end of |
| 2704 | the list, and determine the size of the region. */ |
| 2705 | last_addr = unwind.next_slot_number; |
| 2706 | last_frag = unwind.next_slot_frag; |
| 2707 | for (last = ptr->next; last != NULL; last = last->next) |
| 2708 | if (last->r.type == prologue || last->r.type == prologue_gr |
| 2709 | || last->r.type == body) |
| 2710 | { |
| 2711 | last_addr = last->slot_number; |
| 2712 | last_frag = last->slot_frag; |
| 2713 | break; |
| 2714 | } |
| 2715 | else if (!last->next) |
| 2716 | { |
| 2717 | /* In the absence of an explicit .body directive, |
| 2718 | the prologue ends after the last instruction |
| 2719 | covered by an unwind directive. */ |
| 2720 | if (ptr->r.type != body) |
| 2721 | { |
| 2722 | last_addr = last->slot_number; |
| 2723 | last_frag = last->slot_frag; |
| 2724 | switch (last->r.type) |
| 2725 | { |
| 2726 | case frgr_mem: |
| 2727 | dir_len = (count_bits (last->r.record.p.frmask) |
| 2728 | + count_bits (last->r.record.p.grmask)); |
| 2729 | break; |
| 2730 | case fr_mem: |
| 2731 | case gr_mem: |
| 2732 | dir_len += count_bits (last->r.record.p.rmask); |
| 2733 | break; |
| 2734 | case br_mem: |
| 2735 | case br_gr: |
| 2736 | dir_len += count_bits (last->r.record.p.brmask); |
| 2737 | break; |
| 2738 | case gr_gr: |
| 2739 | dir_len += count_bits (last->r.record.p.grmask); |
| 2740 | break; |
| 2741 | default: |
| 2742 | dir_len = 1; |
| 2743 | break; |
| 2744 | } |
| 2745 | } |
| 2746 | break; |
| 2747 | } |
| 2748 | size = (slot_index (last_addr, last_frag, first_addr, first_frag) |
| 2749 | + dir_len); |
| 2750 | rlen = ptr->r.record.r.rlen = size; |
| 2751 | if (ptr->r.type == body) |
| 2752 | /* End of region. */ |
| 2753 | region = 0; |
| 2754 | else |
| 2755 | region = ptr; |
| 2756 | break; |
| 2757 | } |
| 2758 | case epilogue: |
| 2759 | ptr->r.record.b.t = rlen - 1 - t; |
| 2760 | break; |
| 2761 | |
| 2762 | case mem_stack_f: |
| 2763 | case mem_stack_v: |
| 2764 | case rp_when: |
| 2765 | case pfs_when: |
| 2766 | case preds_when: |
| 2767 | case unat_when: |
| 2768 | case lc_when: |
| 2769 | case fpsr_when: |
| 2770 | case priunat_when_gr: |
| 2771 | case priunat_when_mem: |
| 2772 | case bsp_when: |
| 2773 | case bspstore_when: |
| 2774 | case rnat_when: |
| 2775 | ptr->r.record.p.t = t; |
| 2776 | break; |
| 2777 | |
| 2778 | case spill_reg: |
| 2779 | case spill_sprel: |
| 2780 | case spill_psprel: |
| 2781 | case spill_reg_p: |
| 2782 | case spill_sprel_p: |
| 2783 | case spill_psprel_p: |
| 2784 | ptr->r.record.x.t = t; |
| 2785 | break; |
| 2786 | |
| 2787 | case frgr_mem: |
| 2788 | if (!region) |
| 2789 | { |
| 2790 | as_bad ("frgr_mem record before region record!\n"); |
| 2791 | return; |
| 2792 | } |
| 2793 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; |
| 2794 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; |
| 2795 | set_imask (region, ptr->r.record.p.frmask, t, 1); |
| 2796 | set_imask (region, ptr->r.record.p.grmask, t, 2); |
| 2797 | break; |
| 2798 | case fr_mem: |
| 2799 | if (!region) |
| 2800 | { |
| 2801 | as_bad ("fr_mem record before region record!\n"); |
| 2802 | return; |
| 2803 | } |
| 2804 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; |
| 2805 | set_imask (region, ptr->r.record.p.rmask, t, 1); |
| 2806 | break; |
| 2807 | case gr_mem: |
| 2808 | if (!region) |
| 2809 | { |
| 2810 | as_bad ("gr_mem record before region record!\n"); |
| 2811 | return; |
| 2812 | } |
| 2813 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; |
| 2814 | set_imask (region, ptr->r.record.p.rmask, t, 2); |
| 2815 | break; |
| 2816 | case br_mem: |
| 2817 | if (!region) |
| 2818 | { |
| 2819 | as_bad ("br_mem record before region record!\n"); |
| 2820 | return; |
| 2821 | } |
| 2822 | region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; |
| 2823 | set_imask (region, ptr->r.record.p.brmask, t, 3); |
| 2824 | break; |
| 2825 | |
| 2826 | case gr_gr: |
| 2827 | if (!region) |
| 2828 | { |
| 2829 | as_bad ("gr_gr record before region record!\n"); |
| 2830 | return; |
| 2831 | } |
| 2832 | set_imask (region, ptr->r.record.p.grmask, t, 2); |
| 2833 | break; |
| 2834 | case br_gr: |
| 2835 | if (!region) |
| 2836 | { |
| 2837 | as_bad ("br_gr record before region record!\n"); |
| 2838 | return; |
| 2839 | } |
| 2840 | set_imask (region, ptr->r.record.p.brmask, t, 3); |
| 2841 | break; |
| 2842 | |
| 2843 | default: |
| 2844 | break; |
| 2845 | } |
| 2846 | } |
| 2847 | } |
| 2848 | |
| 2849 | /* Helper routine for output_unw_records. Emits the header for the unwind |
| 2850 | info. */ |
| 2851 | |
| 2852 | static int |
| 2853 | setup_unwind_header (int size, unsigned char **mem) |
| 2854 | { |
| 2855 | int x, extra = 0; |
| 2856 | valueT flag_value; |
| 2857 | |
| 2858 | /* pad to pointer-size boundry. */ |
| 2859 | x = size % md.pointer_size; |
| 2860 | if (x != 0) |
| 2861 | extra = md.pointer_size - x; |
| 2862 | |
| 2863 | /* Add 8 for the header + a pointer for the |
| 2864 | personality offset. */ |
| 2865 | *mem = xmalloc (size + extra + 8 + md.pointer_size); |
| 2866 | |
| 2867 | /* Clear the padding area and personality. */ |
| 2868 | memset (*mem + 8 + size, 0, extra + md.pointer_size); |
| 2869 | |
| 2870 | /* Initialize the header area. */ |
| 2871 | if (unwind.personality_routine) |
| 2872 | { |
| 2873 | if (md.flags & EF_IA_64_ABI64) |
| 2874 | flag_value = (bfd_vma) 3 << 32; |
| 2875 | else |
| 2876 | /* 32-bit unwind info block. */ |
| 2877 | flag_value = (bfd_vma) 0x1003 << 32; |
| 2878 | } |
| 2879 | else |
| 2880 | flag_value = 0; |
| 2881 | |
| 2882 | md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* Version. */ |
| 2883 | | flag_value /* U & E handler flags. */ |
| 2884 | | ((size + extra) / md.pointer_size)), /* Length. */ |
| 2885 | 8); |
| 2886 | |
| 2887 | return extra; |
| 2888 | } |
| 2889 | |
| 2890 | /* Generate an unwind image from a record list. Returns the number of |
| 2891 | bytes in the resulting image. The memory image itselof is returned |
| 2892 | in the 'ptr' parameter. */ |
| 2893 | static int |
| 2894 | output_unw_records (list, ptr) |
| 2895 | unw_rec_list *list; |
| 2896 | void **ptr; |
| 2897 | { |
| 2898 | int size, extra; |
| 2899 | unsigned char *mem; |
| 2900 | |
| 2901 | *ptr = NULL; |
| 2902 | |
| 2903 | list = optimize_unw_records (list); |
| 2904 | fixup_unw_records (list); |
| 2905 | size = calc_record_size (list); |
| 2906 | |
| 2907 | if (size > 0 || unwind.force_unwind_entry) |
| 2908 | { |
| 2909 | unwind.force_unwind_entry = 0; |
| 2910 | extra = setup_unwind_header (size, &mem); |
| 2911 | |
| 2912 | vbyte_mem_ptr = mem + 8; |
| 2913 | process_unw_records (list, output_vbyte_mem); |
| 2914 | |
| 2915 | *ptr = mem; |
| 2916 | |
| 2917 | size += extra + 8 + md.pointer_size; |
| 2918 | } |
| 2919 | return size; |
| 2920 | } |
| 2921 | |
| 2922 | static int |
| 2923 | convert_expr_to_ab_reg (e, ab, regp) |
| 2924 | expressionS *e; |
| 2925 | unsigned int *ab; |
| 2926 | unsigned int *regp; |
| 2927 | { |
| 2928 | unsigned int reg; |
| 2929 | |
| 2930 | if (e->X_op != O_register) |
| 2931 | return 0; |
| 2932 | |
| 2933 | reg = e->X_add_number; |
| 2934 | if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) |
| 2935 | { |
| 2936 | *ab = 0; |
| 2937 | *regp = reg - REG_GR; |
| 2938 | } |
| 2939 | else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) |
| 2940 | || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) |
| 2941 | { |
| 2942 | *ab = 1; |
| 2943 | *regp = reg - REG_FR; |
| 2944 | } |
| 2945 | else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) |
| 2946 | { |
| 2947 | *ab = 2; |
| 2948 | *regp = reg - REG_BR; |
| 2949 | } |
| 2950 | else |
| 2951 | { |
| 2952 | *ab = 3; |
| 2953 | switch (reg) |
| 2954 | { |
| 2955 | case REG_PR: *regp = 0; break; |
| 2956 | case REG_PSP: *regp = 1; break; |
| 2957 | case REG_PRIUNAT: *regp = 2; break; |
| 2958 | case REG_BR + 0: *regp = 3; break; |
| 2959 | case REG_AR + AR_BSP: *regp = 4; break; |
| 2960 | case REG_AR + AR_BSPSTORE: *regp = 5; break; |
| 2961 | case REG_AR + AR_RNAT: *regp = 6; break; |
| 2962 | case REG_AR + AR_UNAT: *regp = 7; break; |
| 2963 | case REG_AR + AR_FPSR: *regp = 8; break; |
| 2964 | case REG_AR + AR_PFS: *regp = 9; break; |
| 2965 | case REG_AR + AR_LC: *regp = 10; break; |
| 2966 | |
| 2967 | default: |
| 2968 | return 0; |
| 2969 | } |
| 2970 | } |
| 2971 | return 1; |
| 2972 | } |
| 2973 | |
| 2974 | static int |
| 2975 | convert_expr_to_xy_reg (e, xy, regp) |
| 2976 | expressionS *e; |
| 2977 | unsigned int *xy; |
| 2978 | unsigned int *regp; |
| 2979 | { |
| 2980 | unsigned int reg; |
| 2981 | |
| 2982 | if (e->X_op != O_register) |
| 2983 | return 0; |
| 2984 | |
| 2985 | reg = e->X_add_number; |
| 2986 | |
| 2987 | if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) |
| 2988 | { |
| 2989 | *xy = 0; |
| 2990 | *regp = reg - REG_GR; |
| 2991 | } |
| 2992 | else if (reg >= REG_FR && reg <= (REG_FR + 127)) |
| 2993 | { |
| 2994 | *xy = 1; |
| 2995 | *regp = reg - REG_FR; |
| 2996 | } |
| 2997 | else if (reg >= REG_BR && reg <= (REG_BR + 7)) |
| 2998 | { |
| 2999 | *xy = 2; |
| 3000 | *regp = reg - REG_BR; |
| 3001 | } |
| 3002 | else |
| 3003 | return -1; |
| 3004 | return 1; |
| 3005 | } |
| 3006 | |
| 3007 | static void |
| 3008 | dot_radix (dummy) |
| 3009 | int dummy ATTRIBUTE_UNUSED; |
| 3010 | { |
| 3011 | int radix; |
| 3012 | |
| 3013 | SKIP_WHITESPACE (); |
| 3014 | radix = *input_line_pointer++; |
| 3015 | |
| 3016 | if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) |
| 3017 | { |
| 3018 | as_bad ("Radix `%c' unsupported", *input_line_pointer); |
| 3019 | ignore_rest_of_line (); |
| 3020 | return; |
| 3021 | } |
| 3022 | } |
| 3023 | |
| 3024 | /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ |
| 3025 | static void |
| 3026 | dot_special_section (which) |
| 3027 | int which; |
| 3028 | { |
| 3029 | set_section ((char *) special_section_name[which]); |
| 3030 | } |
| 3031 | |
| 3032 | static void |
| 3033 | add_unwind_entry (ptr) |
| 3034 | unw_rec_list *ptr; |
| 3035 | { |
| 3036 | if (unwind.tail) |
| 3037 | unwind.tail->next = ptr; |
| 3038 | else |
| 3039 | unwind.list = ptr; |
| 3040 | unwind.tail = ptr; |
| 3041 | |
| 3042 | /* The current entry can in fact be a chain of unwind entries. */ |
| 3043 | if (unwind.current_entry == NULL) |
| 3044 | unwind.current_entry = ptr; |
| 3045 | } |
| 3046 | |
| 3047 | static void |
| 3048 | dot_fframe (dummy) |
| 3049 | int dummy ATTRIBUTE_UNUSED; |
| 3050 | { |
| 3051 | expressionS e; |
| 3052 | |
| 3053 | parse_operand (&e); |
| 3054 | |
| 3055 | if (e.X_op != O_constant) |
| 3056 | as_bad ("Operand to .fframe must be a constant"); |
| 3057 | else |
| 3058 | add_unwind_entry (output_mem_stack_f (e.X_add_number)); |
| 3059 | } |
| 3060 | |
| 3061 | static void |
| 3062 | dot_vframe (dummy) |
| 3063 | int dummy ATTRIBUTE_UNUSED; |
| 3064 | { |
| 3065 | expressionS e; |
| 3066 | unsigned reg; |
| 3067 | |
| 3068 | parse_operand (&e); |
| 3069 | reg = e.X_add_number - REG_GR; |
| 3070 | if (e.X_op == O_register && reg < 128) |
| 3071 | { |
| 3072 | add_unwind_entry (output_mem_stack_v ()); |
| 3073 | if (! (unwind.prologue_mask & 2)) |
| 3074 | add_unwind_entry (output_psp_gr (reg)); |
| 3075 | } |
| 3076 | else |
| 3077 | as_bad ("First operand to .vframe must be a general register"); |
| 3078 | } |
| 3079 | |
| 3080 | static void |
| 3081 | dot_vframesp (dummy) |
| 3082 | int dummy ATTRIBUTE_UNUSED; |
| 3083 | { |
| 3084 | expressionS e; |
| 3085 | |
| 3086 | parse_operand (&e); |
| 3087 | if (e.X_op == O_constant) |
| 3088 | { |
| 3089 | add_unwind_entry (output_mem_stack_v ()); |
| 3090 | add_unwind_entry (output_psp_sprel (e.X_add_number)); |
| 3091 | } |
| 3092 | else |
| 3093 | as_bad ("Operand to .vframesp must be a constant (sp-relative offset)"); |
| 3094 | } |
| 3095 | |
| 3096 | static void |
| 3097 | dot_vframepsp (dummy) |
| 3098 | int dummy ATTRIBUTE_UNUSED; |
| 3099 | { |
| 3100 | expressionS e; |
| 3101 | |
| 3102 | parse_operand (&e); |
| 3103 | if (e.X_op == O_constant) |
| 3104 | { |
| 3105 | add_unwind_entry (output_mem_stack_v ()); |
| 3106 | add_unwind_entry (output_psp_sprel (e.X_add_number)); |
| 3107 | } |
| 3108 | else |
| 3109 | as_bad ("Operand to .vframepsp must be a constant (psp-relative offset)"); |
| 3110 | } |
| 3111 | |
| 3112 | static void |
| 3113 | dot_save (dummy) |
| 3114 | int dummy ATTRIBUTE_UNUSED; |
| 3115 | { |
| 3116 | expressionS e1, e2; |
| 3117 | int sep; |
| 3118 | int reg1, reg2; |
| 3119 | |
| 3120 | sep = parse_operand (&e1); |
| 3121 | if (sep != ',') |
| 3122 | as_bad ("No second operand to .save"); |
| 3123 | sep = parse_operand (&e2); |
| 3124 | |
| 3125 | reg1 = e1.X_add_number; |
| 3126 | reg2 = e2.X_add_number - REG_GR; |
| 3127 | |
| 3128 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
| 3129 | if (e1.X_op == O_register) |
| 3130 | { |
| 3131 | if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) |
| 3132 | { |
| 3133 | switch (reg1) |
| 3134 | { |
| 3135 | case REG_AR + AR_BSP: |
| 3136 | add_unwind_entry (output_bsp_when ()); |
| 3137 | add_unwind_entry (output_bsp_gr (reg2)); |
| 3138 | break; |
| 3139 | case REG_AR + AR_BSPSTORE: |
| 3140 | add_unwind_entry (output_bspstore_when ()); |
| 3141 | add_unwind_entry (output_bspstore_gr (reg2)); |
| 3142 | break; |
| 3143 | case REG_AR + AR_RNAT: |
| 3144 | add_unwind_entry (output_rnat_when ()); |
| 3145 | add_unwind_entry (output_rnat_gr (reg2)); |
| 3146 | break; |
| 3147 | case REG_AR + AR_UNAT: |
| 3148 | add_unwind_entry (output_unat_when ()); |
| 3149 | add_unwind_entry (output_unat_gr (reg2)); |
| 3150 | break; |
| 3151 | case REG_AR + AR_FPSR: |
| 3152 | add_unwind_entry (output_fpsr_when ()); |
| 3153 | add_unwind_entry (output_fpsr_gr (reg2)); |
| 3154 | break; |
| 3155 | case REG_AR + AR_PFS: |
| 3156 | add_unwind_entry (output_pfs_when ()); |
| 3157 | if (! (unwind.prologue_mask & 4)) |
| 3158 | add_unwind_entry (output_pfs_gr (reg2)); |
| 3159 | break; |
| 3160 | case REG_AR + AR_LC: |
| 3161 | add_unwind_entry (output_lc_when ()); |
| 3162 | add_unwind_entry (output_lc_gr (reg2)); |
| 3163 | break; |
| 3164 | case REG_BR: |
| 3165 | add_unwind_entry (output_rp_when ()); |
| 3166 | if (! (unwind.prologue_mask & 8)) |
| 3167 | add_unwind_entry (output_rp_gr (reg2)); |
| 3168 | break; |
| 3169 | case REG_PR: |
| 3170 | add_unwind_entry (output_preds_when ()); |
| 3171 | if (! (unwind.prologue_mask & 1)) |
| 3172 | add_unwind_entry (output_preds_gr (reg2)); |
| 3173 | break; |
| 3174 | case REG_PRIUNAT: |
| 3175 | add_unwind_entry (output_priunat_when_gr ()); |
| 3176 | add_unwind_entry (output_priunat_gr (reg2)); |
| 3177 | break; |
| 3178 | default: |
| 3179 | as_bad ("First operand not a valid register"); |
| 3180 | } |
| 3181 | } |
| 3182 | else |
| 3183 | as_bad (" Second operand not a valid register"); |
| 3184 | } |
| 3185 | else |
| 3186 | as_bad ("First operand not a register"); |
| 3187 | } |
| 3188 | |
| 3189 | static void |
| 3190 | dot_restore (dummy) |
| 3191 | int dummy ATTRIBUTE_UNUSED; |
| 3192 | { |
| 3193 | expressionS e1, e2; |
| 3194 | unsigned long ecount; /* # of _additional_ regions to pop */ |
| 3195 | int sep; |
| 3196 | |
| 3197 | sep = parse_operand (&e1); |
| 3198 | if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) |
| 3199 | { |
| 3200 | as_bad ("First operand to .restore must be stack pointer (sp)"); |
| 3201 | return; |
| 3202 | } |
| 3203 | |
| 3204 | if (sep == ',') |
| 3205 | { |
| 3206 | parse_operand (&e2); |
| 3207 | if (e2.X_op != O_constant || e2.X_add_number < 0) |
| 3208 | { |
| 3209 | as_bad ("Second operand to .restore must be a constant >= 0"); |
| 3210 | return; |
| 3211 | } |
| 3212 | ecount = e2.X_add_number; |
| 3213 | } |
| 3214 | else |
| 3215 | ecount = unwind.prologue_count - 1; |
| 3216 | |
| 3217 | if (ecount >= unwind.prologue_count) |
| 3218 | { |
| 3219 | as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)", |
| 3220 | ecount + 1, unwind.prologue_count); |
| 3221 | return; |
| 3222 | } |
| 3223 | |
| 3224 | add_unwind_entry (output_epilogue (ecount)); |
| 3225 | |
| 3226 | if (ecount < unwind.prologue_count) |
| 3227 | unwind.prologue_count -= ecount + 1; |
| 3228 | else |
| 3229 | unwind.prologue_count = 0; |
| 3230 | } |
| 3231 | |
| 3232 | static void |
| 3233 | dot_restorereg (dummy) |
| 3234 | int dummy ATTRIBUTE_UNUSED; |
| 3235 | { |
| 3236 | unsigned int ab, reg; |
| 3237 | expressionS e; |
| 3238 | |
| 3239 | parse_operand (&e); |
| 3240 | |
| 3241 | if (!convert_expr_to_ab_reg (&e, &ab, ®)) |
| 3242 | { |
| 3243 | as_bad ("First operand to .restorereg must be a preserved register"); |
| 3244 | return; |
| 3245 | } |
| 3246 | add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); |
| 3247 | } |
| 3248 | |
| 3249 | static void |
| 3250 | dot_restorereg_p (dummy) |
| 3251 | int dummy ATTRIBUTE_UNUSED; |
| 3252 | { |
| 3253 | unsigned int qp, ab, reg; |
| 3254 | expressionS e1, e2; |
| 3255 | int sep; |
| 3256 | |
| 3257 | sep = parse_operand (&e1); |
| 3258 | if (sep != ',') |
| 3259 | { |
| 3260 | as_bad ("No second operand to .restorereg.p"); |
| 3261 | return; |
| 3262 | } |
| 3263 | |
| 3264 | parse_operand (&e2); |
| 3265 | |
| 3266 | qp = e1.X_add_number - REG_P; |
| 3267 | if (e1.X_op != O_register || qp > 63) |
| 3268 | { |
| 3269 | as_bad ("First operand to .restorereg.p must be a predicate"); |
| 3270 | return; |
| 3271 | } |
| 3272 | |
| 3273 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) |
| 3274 | { |
| 3275 | as_bad ("Second operand to .restorereg.p must be a preserved register"); |
| 3276 | return; |
| 3277 | } |
| 3278 | add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); |
| 3279 | } |
| 3280 | |
| 3281 | static int |
| 3282 | generate_unwind_image (text_name) |
| 3283 | const char *text_name; |
| 3284 | { |
| 3285 | int size; |
| 3286 | void *unw_rec; |
| 3287 | |
| 3288 | /* Force out pending instructions, to make sure all unwind records have |
| 3289 | a valid slot_number field. */ |
| 3290 | ia64_flush_insns (); |
| 3291 | |
| 3292 | /* Generate the unwind record. */ |
| 3293 | size = output_unw_records (unwind.list, &unw_rec); |
| 3294 | if (size % md.pointer_size != 0) |
| 3295 | as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size); |
| 3296 | |
| 3297 | /* If there are unwind records, switch sections, and output the info. */ |
| 3298 | if (size != 0) |
| 3299 | { |
| 3300 | unsigned char *where; |
| 3301 | char *sec_name; |
| 3302 | expressionS exp; |
| 3303 | bfd_reloc_code_real_type reloc; |
| 3304 | |
| 3305 | make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name); |
| 3306 | set_section (sec_name); |
| 3307 | bfd_set_section_flags (stdoutput, now_seg, |
| 3308 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); |
| 3309 | |
| 3310 | /* Make sure the section has 4 byte alignment for ILP32 and |
| 3311 | 8 byte alignment for LP64. */ |
| 3312 | frag_align (md.pointer_size_shift, 0, 0); |
| 3313 | record_alignment (now_seg, md.pointer_size_shift); |
| 3314 | |
| 3315 | /* Set expression which points to start of unwind descriptor area. */ |
| 3316 | unwind.info = expr_build_dot (); |
| 3317 | |
| 3318 | where = (unsigned char *) frag_more (size); |
| 3319 | |
| 3320 | /* Issue a label for this address, and keep track of it to put it |
| 3321 | in the unwind section. */ |
| 3322 | |
| 3323 | /* Copy the information from the unwind record into this section. The |
| 3324 | data is already in the correct byte order. */ |
| 3325 | memcpy (where, unw_rec, size); |
| 3326 | |
| 3327 | /* Add the personality address to the image. */ |
| 3328 | if (unwind.personality_routine != 0) |
| 3329 | { |
| 3330 | exp.X_op = O_symbol; |
| 3331 | exp.X_add_symbol = unwind.personality_routine; |
| 3332 | exp.X_add_number = 0; |
| 3333 | |
| 3334 | if (md.flags & EF_IA_64_BE) |
| 3335 | { |
| 3336 | if (md.flags & EF_IA_64_ABI64) |
| 3337 | reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB; |
| 3338 | else |
| 3339 | reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB; |
| 3340 | } |
| 3341 | else |
| 3342 | { |
| 3343 | if (md.flags & EF_IA_64_ABI64) |
| 3344 | reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB; |
| 3345 | else |
| 3346 | reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB; |
| 3347 | } |
| 3348 | |
| 3349 | fix_new_exp (frag_now, frag_now_fix () - md.pointer_size, |
| 3350 | md.pointer_size, &exp, 0, reloc); |
| 3351 | unwind.personality_routine = 0; |
| 3352 | } |
| 3353 | } |
| 3354 | |
| 3355 | free_list_records (unwind.list); |
| 3356 | free_saved_prologue_counts (); |
| 3357 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
| 3358 | |
| 3359 | return size; |
| 3360 | } |
| 3361 | |
| 3362 | static void |
| 3363 | dot_handlerdata (dummy) |
| 3364 | int dummy ATTRIBUTE_UNUSED; |
| 3365 | { |
| 3366 | const char *text_name = segment_name (now_seg); |
| 3367 | |
| 3368 | /* If text section name starts with ".text" (which it should), |
| 3369 | strip this prefix off. */ |
| 3370 | if (strcmp (text_name, ".text") == 0) |
| 3371 | text_name = ""; |
| 3372 | |
| 3373 | unwind.force_unwind_entry = 1; |
| 3374 | |
| 3375 | /* Remember which segment we're in so we can switch back after .endp */ |
| 3376 | unwind.saved_text_seg = now_seg; |
| 3377 | unwind.saved_text_subseg = now_subseg; |
| 3378 | |
| 3379 | /* Generate unwind info into unwind-info section and then leave that |
| 3380 | section as the currently active one so dataXX directives go into |
| 3381 | the language specific data area of the unwind info block. */ |
| 3382 | generate_unwind_image (text_name); |
| 3383 | demand_empty_rest_of_line (); |
| 3384 | } |
| 3385 | |
| 3386 | static void |
| 3387 | dot_unwentry (dummy) |
| 3388 | int dummy ATTRIBUTE_UNUSED; |
| 3389 | { |
| 3390 | unwind.force_unwind_entry = 1; |
| 3391 | demand_empty_rest_of_line (); |
| 3392 | } |
| 3393 | |
| 3394 | static void |
| 3395 | dot_altrp (dummy) |
| 3396 | int dummy ATTRIBUTE_UNUSED; |
| 3397 | { |
| 3398 | expressionS e; |
| 3399 | unsigned reg; |
| 3400 | |
| 3401 | parse_operand (&e); |
| 3402 | reg = e.X_add_number - REG_BR; |
| 3403 | if (e.X_op == O_register && reg < 8) |
| 3404 | add_unwind_entry (output_rp_br (reg)); |
| 3405 | else |
| 3406 | as_bad ("First operand not a valid branch register"); |
| 3407 | } |
| 3408 | |
| 3409 | static void |
| 3410 | dot_savemem (psprel) |
| 3411 | int psprel; |
| 3412 | { |
| 3413 | expressionS e1, e2; |
| 3414 | int sep; |
| 3415 | int reg1, val; |
| 3416 | |
| 3417 | sep = parse_operand (&e1); |
| 3418 | if (sep != ',') |
| 3419 | as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); |
| 3420 | sep = parse_operand (&e2); |
| 3421 | |
| 3422 | reg1 = e1.X_add_number; |
| 3423 | val = e2.X_add_number; |
| 3424 | |
| 3425 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
| 3426 | if (e1.X_op == O_register) |
| 3427 | { |
| 3428 | if (e2.X_op == O_constant) |
| 3429 | { |
| 3430 | switch (reg1) |
| 3431 | { |
| 3432 | case REG_AR + AR_BSP: |
| 3433 | add_unwind_entry (output_bsp_when ()); |
| 3434 | add_unwind_entry ((psprel |
| 3435 | ? output_bsp_psprel |
| 3436 | : output_bsp_sprel) (val)); |
| 3437 | break; |
| 3438 | case REG_AR + AR_BSPSTORE: |
| 3439 | add_unwind_entry (output_bspstore_when ()); |
| 3440 | add_unwind_entry ((psprel |
| 3441 | ? output_bspstore_psprel |
| 3442 | : output_bspstore_sprel) (val)); |
| 3443 | break; |
| 3444 | case REG_AR + AR_RNAT: |
| 3445 | add_unwind_entry (output_rnat_when ()); |
| 3446 | add_unwind_entry ((psprel |
| 3447 | ? output_rnat_psprel |
| 3448 | : output_rnat_sprel) (val)); |
| 3449 | break; |
| 3450 | case REG_AR + AR_UNAT: |
| 3451 | add_unwind_entry (output_unat_when ()); |
| 3452 | add_unwind_entry ((psprel |
| 3453 | ? output_unat_psprel |
| 3454 | : output_unat_sprel) (val)); |
| 3455 | break; |
| 3456 | case REG_AR + AR_FPSR: |
| 3457 | add_unwind_entry (output_fpsr_when ()); |
| 3458 | add_unwind_entry ((psprel |
| 3459 | ? output_fpsr_psprel |
| 3460 | : output_fpsr_sprel) (val)); |
| 3461 | break; |
| 3462 | case REG_AR + AR_PFS: |
| 3463 | add_unwind_entry (output_pfs_when ()); |
| 3464 | add_unwind_entry ((psprel |
| 3465 | ? output_pfs_psprel |
| 3466 | : output_pfs_sprel) (val)); |
| 3467 | break; |
| 3468 | case REG_AR + AR_LC: |
| 3469 | add_unwind_entry (output_lc_when ()); |
| 3470 | add_unwind_entry ((psprel |
| 3471 | ? output_lc_psprel |
| 3472 | : output_lc_sprel) (val)); |
| 3473 | break; |
| 3474 | case REG_BR: |
| 3475 | add_unwind_entry (output_rp_when ()); |
| 3476 | add_unwind_entry ((psprel |
| 3477 | ? output_rp_psprel |
| 3478 | : output_rp_sprel) (val)); |
| 3479 | break; |
| 3480 | case REG_PR: |
| 3481 | add_unwind_entry (output_preds_when ()); |
| 3482 | add_unwind_entry ((psprel |
| 3483 | ? output_preds_psprel |
| 3484 | : output_preds_sprel) (val)); |
| 3485 | break; |
| 3486 | case REG_PRIUNAT: |
| 3487 | add_unwind_entry (output_priunat_when_mem ()); |
| 3488 | add_unwind_entry ((psprel |
| 3489 | ? output_priunat_psprel |
| 3490 | : output_priunat_sprel) (val)); |
| 3491 | break; |
| 3492 | default: |
| 3493 | as_bad ("First operand not a valid register"); |
| 3494 | } |
| 3495 | } |
| 3496 | else |
| 3497 | as_bad (" Second operand not a valid constant"); |
| 3498 | } |
| 3499 | else |
| 3500 | as_bad ("First operand not a register"); |
| 3501 | } |
| 3502 | |
| 3503 | static void |
| 3504 | dot_saveg (dummy) |
| 3505 | int dummy ATTRIBUTE_UNUSED; |
| 3506 | { |
| 3507 | expressionS e1, e2; |
| 3508 | int sep; |
| 3509 | sep = parse_operand (&e1); |
| 3510 | if (sep == ',') |
| 3511 | parse_operand (&e2); |
| 3512 | |
| 3513 | if (e1.X_op != O_constant) |
| 3514 | as_bad ("First operand to .save.g must be a constant."); |
| 3515 | else |
| 3516 | { |
| 3517 | int grmask = e1.X_add_number; |
| 3518 | if (sep != ',') |
| 3519 | add_unwind_entry (output_gr_mem (grmask)); |
| 3520 | else |
| 3521 | { |
| 3522 | int reg = e2.X_add_number - REG_GR; |
| 3523 | if (e2.X_op == O_register && reg >= 0 && reg < 128) |
| 3524 | add_unwind_entry (output_gr_gr (grmask, reg)); |
| 3525 | else |
| 3526 | as_bad ("Second operand is an invalid register."); |
| 3527 | } |
| 3528 | } |
| 3529 | } |
| 3530 | |
| 3531 | static void |
| 3532 | dot_savef (dummy) |
| 3533 | int dummy ATTRIBUTE_UNUSED; |
| 3534 | { |
| 3535 | expressionS e1; |
| 3536 | int sep; |
| 3537 | sep = parse_operand (&e1); |
| 3538 | |
| 3539 | if (e1.X_op != O_constant) |
| 3540 | as_bad ("Operand to .save.f must be a constant."); |
| 3541 | else |
| 3542 | add_unwind_entry (output_fr_mem (e1.X_add_number)); |
| 3543 | } |
| 3544 | |
| 3545 | static void |
| 3546 | dot_saveb (dummy) |
| 3547 | int dummy ATTRIBUTE_UNUSED; |
| 3548 | { |
| 3549 | expressionS e1, e2; |
| 3550 | unsigned int reg; |
| 3551 | unsigned char sep; |
| 3552 | int brmask; |
| 3553 | |
| 3554 | sep = parse_operand (&e1); |
| 3555 | if (e1.X_op != O_constant) |
| 3556 | { |
| 3557 | as_bad ("First operand to .save.b must be a constant."); |
| 3558 | return; |
| 3559 | } |
| 3560 | brmask = e1.X_add_number; |
| 3561 | |
| 3562 | if (sep == ',') |
| 3563 | { |
| 3564 | sep = parse_operand (&e2); |
| 3565 | reg = e2.X_add_number - REG_GR; |
| 3566 | if (e2.X_op != O_register || reg > 127) |
| 3567 | { |
| 3568 | as_bad ("Second operand to .save.b must be a general register."); |
| 3569 | return; |
| 3570 | } |
| 3571 | add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); |
| 3572 | } |
| 3573 | else |
| 3574 | add_unwind_entry (output_br_mem (brmask)); |
| 3575 | |
| 3576 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
| 3577 | ignore_rest_of_line (); |
| 3578 | } |
| 3579 | |
| 3580 | static void |
| 3581 | dot_savegf (dummy) |
| 3582 | int dummy ATTRIBUTE_UNUSED; |
| 3583 | { |
| 3584 | expressionS e1, e2; |
| 3585 | int sep; |
| 3586 | sep = parse_operand (&e1); |
| 3587 | if (sep == ',') |
| 3588 | parse_operand (&e2); |
| 3589 | |
| 3590 | if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) |
| 3591 | as_bad ("Both operands of .save.gf must be constants."); |
| 3592 | else |
| 3593 | { |
| 3594 | int grmask = e1.X_add_number; |
| 3595 | int frmask = e2.X_add_number; |
| 3596 | add_unwind_entry (output_frgr_mem (grmask, frmask)); |
| 3597 | } |
| 3598 | } |
| 3599 | |
| 3600 | static void |
| 3601 | dot_spill (dummy) |
| 3602 | int dummy ATTRIBUTE_UNUSED; |
| 3603 | { |
| 3604 | expressionS e; |
| 3605 | unsigned char sep; |
| 3606 | |
| 3607 | sep = parse_operand (&e); |
| 3608 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
| 3609 | ignore_rest_of_line (); |
| 3610 | |
| 3611 | if (e.X_op != O_constant) |
| 3612 | as_bad ("Operand to .spill must be a constant"); |
| 3613 | else |
| 3614 | add_unwind_entry (output_spill_base (e.X_add_number)); |
| 3615 | } |
| 3616 | |
| 3617 | static void |
| 3618 | dot_spillreg (dummy) |
| 3619 | int dummy ATTRIBUTE_UNUSED; |
| 3620 | { |
| 3621 | int sep, ab, xy, reg, treg; |
| 3622 | expressionS e1, e2; |
| 3623 | |
| 3624 | sep = parse_operand (&e1); |
| 3625 | if (sep != ',') |
| 3626 | { |
| 3627 | as_bad ("No second operand to .spillreg"); |
| 3628 | return; |
| 3629 | } |
| 3630 | |
| 3631 | parse_operand (&e2); |
| 3632 | |
| 3633 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) |
| 3634 | { |
| 3635 | as_bad ("First operand to .spillreg must be a preserved register"); |
| 3636 | return; |
| 3637 | } |
| 3638 | |
| 3639 | if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) |
| 3640 | { |
| 3641 | as_bad ("Second operand to .spillreg must be a register"); |
| 3642 | return; |
| 3643 | } |
| 3644 | |
| 3645 | add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); |
| 3646 | } |
| 3647 | |
| 3648 | static void |
| 3649 | dot_spillmem (psprel) |
| 3650 | int psprel; |
| 3651 | { |
| 3652 | expressionS e1, e2; |
| 3653 | int sep, ab, reg; |
| 3654 | |
| 3655 | sep = parse_operand (&e1); |
| 3656 | if (sep != ',') |
| 3657 | { |
| 3658 | as_bad ("Second operand missing"); |
| 3659 | return; |
| 3660 | } |
| 3661 | |
| 3662 | parse_operand (&e2); |
| 3663 | |
| 3664 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) |
| 3665 | { |
| 3666 | as_bad ("First operand to .spill%s must be a preserved register", |
| 3667 | psprel ? "psp" : "sp"); |
| 3668 | return; |
| 3669 | } |
| 3670 | |
| 3671 | if (e2.X_op != O_constant) |
| 3672 | { |
| 3673 | as_bad ("Second operand to .spill%s must be a constant", |
| 3674 | psprel ? "psp" : "sp"); |
| 3675 | return; |
| 3676 | } |
| 3677 | |
| 3678 | if (psprel) |
| 3679 | add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); |
| 3680 | else |
| 3681 | add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); |
| 3682 | } |
| 3683 | |
| 3684 | static void |
| 3685 | dot_spillreg_p (dummy) |
| 3686 | int dummy ATTRIBUTE_UNUSED; |
| 3687 | { |
| 3688 | int sep, ab, xy, reg, treg; |
| 3689 | expressionS e1, e2, e3; |
| 3690 | unsigned int qp; |
| 3691 | |
| 3692 | sep = parse_operand (&e1); |
| 3693 | if (sep != ',') |
| 3694 | { |
| 3695 | as_bad ("No second and third operand to .spillreg.p"); |
| 3696 | return; |
| 3697 | } |
| 3698 | |
| 3699 | sep = parse_operand (&e2); |
| 3700 | if (sep != ',') |
| 3701 | { |
| 3702 | as_bad ("No third operand to .spillreg.p"); |
| 3703 | return; |
| 3704 | } |
| 3705 | |
| 3706 | parse_operand (&e3); |
| 3707 | |
| 3708 | qp = e1.X_add_number - REG_P; |
| 3709 | |
| 3710 | if (e1.X_op != O_register || qp > 63) |
| 3711 | { |
| 3712 | as_bad ("First operand to .spillreg.p must be a predicate"); |
| 3713 | return; |
| 3714 | } |
| 3715 | |
| 3716 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) |
| 3717 | { |
| 3718 | as_bad ("Second operand to .spillreg.p must be a preserved register"); |
| 3719 | return; |
| 3720 | } |
| 3721 | |
| 3722 | if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) |
| 3723 | { |
| 3724 | as_bad ("Third operand to .spillreg.p must be a register"); |
| 3725 | return; |
| 3726 | } |
| 3727 | |
| 3728 | add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); |
| 3729 | } |
| 3730 | |
| 3731 | static void |
| 3732 | dot_spillmem_p (psprel) |
| 3733 | int psprel; |
| 3734 | { |
| 3735 | expressionS e1, e2, e3; |
| 3736 | int sep, ab, reg; |
| 3737 | unsigned int qp; |
| 3738 | |
| 3739 | sep = parse_operand (&e1); |
| 3740 | if (sep != ',') |
| 3741 | { |
| 3742 | as_bad ("Second operand missing"); |
| 3743 | return; |
| 3744 | } |
| 3745 | |
| 3746 | parse_operand (&e2); |
| 3747 | if (sep != ',') |
| 3748 | { |
| 3749 | as_bad ("Second operand missing"); |
| 3750 | return; |
| 3751 | } |
| 3752 | |
| 3753 | parse_operand (&e3); |
| 3754 | |
| 3755 | qp = e1.X_add_number - REG_P; |
| 3756 | if (e1.X_op != O_register || qp > 63) |
| 3757 | { |
| 3758 | as_bad ("First operand to .spill%s_p must be a predicate", |
| 3759 | psprel ? "psp" : "sp"); |
| 3760 | return; |
| 3761 | } |
| 3762 | |
| 3763 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) |
| 3764 | { |
| 3765 | as_bad ("Second operand to .spill%s_p must be a preserved register", |
| 3766 | psprel ? "psp" : "sp"); |
| 3767 | return; |
| 3768 | } |
| 3769 | |
| 3770 | if (e3.X_op != O_constant) |
| 3771 | { |
| 3772 | as_bad ("Third operand to .spill%s_p must be a constant", |
| 3773 | psprel ? "psp" : "sp"); |
| 3774 | return; |
| 3775 | } |
| 3776 | |
| 3777 | if (psprel) |
| 3778 | add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp)); |
| 3779 | else |
| 3780 | add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp)); |
| 3781 | } |
| 3782 | |
| 3783 | static unsigned int |
| 3784 | get_saved_prologue_count (lbl) |
| 3785 | unsigned long lbl; |
| 3786 | { |
| 3787 | label_prologue_count *lpc = unwind.saved_prologue_counts; |
| 3788 | |
| 3789 | while (lpc != NULL && lpc->label_number != lbl) |
| 3790 | lpc = lpc->next; |
| 3791 | |
| 3792 | if (lpc != NULL) |
| 3793 | return lpc->prologue_count; |
| 3794 | |
| 3795 | as_bad ("Missing .label_state %ld", lbl); |
| 3796 | return 1; |
| 3797 | } |
| 3798 | |
| 3799 | static void |
| 3800 | save_prologue_count (lbl, count) |
| 3801 | unsigned long lbl; |
| 3802 | unsigned int count; |
| 3803 | { |
| 3804 | label_prologue_count *lpc = unwind.saved_prologue_counts; |
| 3805 | |
| 3806 | while (lpc != NULL && lpc->label_number != lbl) |
| 3807 | lpc = lpc->next; |
| 3808 | |
| 3809 | if (lpc != NULL) |
| 3810 | lpc->prologue_count = count; |
| 3811 | else |
| 3812 | { |
| 3813 | label_prologue_count *new_lpc = xmalloc (sizeof (* new_lpc)); |
| 3814 | |
| 3815 | new_lpc->next = unwind.saved_prologue_counts; |
| 3816 | new_lpc->label_number = lbl; |
| 3817 | new_lpc->prologue_count = count; |
| 3818 | unwind.saved_prologue_counts = new_lpc; |
| 3819 | } |
| 3820 | } |
| 3821 | |
| 3822 | static void |
| 3823 | free_saved_prologue_counts () |
| 3824 | { |
| 3825 | label_prologue_count *lpc = unwind.saved_prologue_counts; |
| 3826 | label_prologue_count *next; |
| 3827 | |
| 3828 | while (lpc != NULL) |
| 3829 | { |
| 3830 | next = lpc->next; |
| 3831 | free (lpc); |
| 3832 | lpc = next; |
| 3833 | } |
| 3834 | |
| 3835 | unwind.saved_prologue_counts = NULL; |
| 3836 | } |
| 3837 | |
| 3838 | static void |
| 3839 | dot_label_state (dummy) |
| 3840 | int dummy ATTRIBUTE_UNUSED; |
| 3841 | { |
| 3842 | expressionS e; |
| 3843 | |
| 3844 | parse_operand (&e); |
| 3845 | if (e.X_op != O_constant) |
| 3846 | { |
| 3847 | as_bad ("Operand to .label_state must be a constant"); |
| 3848 | return; |
| 3849 | } |
| 3850 | add_unwind_entry (output_label_state (e.X_add_number)); |
| 3851 | save_prologue_count (e.X_add_number, unwind.prologue_count); |
| 3852 | } |
| 3853 | |
| 3854 | static void |
| 3855 | dot_copy_state (dummy) |
| 3856 | int dummy ATTRIBUTE_UNUSED; |
| 3857 | { |
| 3858 | expressionS e; |
| 3859 | |
| 3860 | parse_operand (&e); |
| 3861 | if (e.X_op != O_constant) |
| 3862 | { |
| 3863 | as_bad ("Operand to .copy_state must be a constant"); |
| 3864 | return; |
| 3865 | } |
| 3866 | add_unwind_entry (output_copy_state (e.X_add_number)); |
| 3867 | unwind.prologue_count = get_saved_prologue_count (e.X_add_number); |
| 3868 | } |
| 3869 | |
| 3870 | static void |
| 3871 | dot_unwabi (dummy) |
| 3872 | int dummy ATTRIBUTE_UNUSED; |
| 3873 | { |
| 3874 | expressionS e1, e2; |
| 3875 | unsigned char sep; |
| 3876 | |
| 3877 | sep = parse_operand (&e1); |
| 3878 | if (sep != ',') |
| 3879 | { |
| 3880 | as_bad ("Second operand to .unwabi missing"); |
| 3881 | return; |
| 3882 | } |
| 3883 | sep = parse_operand (&e2); |
| 3884 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
| 3885 | ignore_rest_of_line (); |
| 3886 | |
| 3887 | if (e1.X_op != O_constant) |
| 3888 | { |
| 3889 | as_bad ("First operand to .unwabi must be a constant"); |
| 3890 | return; |
| 3891 | } |
| 3892 | |
| 3893 | if (e2.X_op != O_constant) |
| 3894 | { |
| 3895 | as_bad ("Second operand to .unwabi must be a constant"); |
| 3896 | return; |
| 3897 | } |
| 3898 | |
| 3899 | add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); |
| 3900 | } |
| 3901 | |
| 3902 | static void |
| 3903 | dot_personality (dummy) |
| 3904 | int dummy ATTRIBUTE_UNUSED; |
| 3905 | { |
| 3906 | char *name, *p, c; |
| 3907 | SKIP_WHITESPACE (); |
| 3908 | name = input_line_pointer; |
| 3909 | c = get_symbol_end (); |
| 3910 | p = input_line_pointer; |
| 3911 | unwind.personality_routine = symbol_find_or_make (name); |
| 3912 | unwind.force_unwind_entry = 1; |
| 3913 | *p = c; |
| 3914 | SKIP_WHITESPACE (); |
| 3915 | demand_empty_rest_of_line (); |
| 3916 | } |
| 3917 | |
| 3918 | static void |
| 3919 | dot_proc (dummy) |
| 3920 | int dummy ATTRIBUTE_UNUSED; |
| 3921 | { |
| 3922 | char *name, *p, c; |
| 3923 | symbolS *sym; |
| 3924 | |
| 3925 | unwind.proc_start = expr_build_dot (); |
| 3926 | /* Parse names of main and alternate entry points and mark them as |
| 3927 | function symbols: */ |
| 3928 | while (1) |
| 3929 | { |
| 3930 | SKIP_WHITESPACE (); |
| 3931 | name = input_line_pointer; |
| 3932 | c = get_symbol_end (); |
| 3933 | p = input_line_pointer; |
| 3934 | sym = symbol_find_or_make (name); |
| 3935 | if (unwind.proc_start == 0) |
| 3936 | { |
| 3937 | unwind.proc_start = sym; |
| 3938 | } |
| 3939 | symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; |
| 3940 | *p = c; |
| 3941 | SKIP_WHITESPACE (); |
| 3942 | if (*input_line_pointer != ',') |
| 3943 | break; |
| 3944 | ++input_line_pointer; |
| 3945 | } |
| 3946 | demand_empty_rest_of_line (); |
| 3947 | ia64_do_align (16); |
| 3948 | |
| 3949 | unwind.prologue_count = 0; |
| 3950 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
| 3951 | unwind.personality_routine = 0; |
| 3952 | } |
| 3953 | |
| 3954 | static void |
| 3955 | dot_body (dummy) |
| 3956 | int dummy ATTRIBUTE_UNUSED; |
| 3957 | { |
| 3958 | unwind.prologue = 0; |
| 3959 | unwind.prologue_mask = 0; |
| 3960 | |
| 3961 | add_unwind_entry (output_body ()); |
| 3962 | demand_empty_rest_of_line (); |
| 3963 | } |
| 3964 | |
| 3965 | static void |
| 3966 | dot_prologue (dummy) |
| 3967 | int dummy ATTRIBUTE_UNUSED; |
| 3968 | { |
| 3969 | unsigned char sep; |
| 3970 | int mask = 0, grsave = 0; |
| 3971 | |
| 3972 | if (!is_it_end_of_statement ()) |
| 3973 | { |
| 3974 | expressionS e1, e2; |
| 3975 | sep = parse_operand (&e1); |
| 3976 | if (sep != ',') |
| 3977 | as_bad ("No second operand to .prologue"); |
| 3978 | sep = parse_operand (&e2); |
| 3979 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
| 3980 | ignore_rest_of_line (); |
| 3981 | |
| 3982 | if (e1.X_op == O_constant) |
| 3983 | { |
| 3984 | mask = e1.X_add_number; |
| 3985 | |
| 3986 | if (e2.X_op == O_constant) |
| 3987 | grsave = e2.X_add_number; |
| 3988 | else if (e2.X_op == O_register |
| 3989 | && (grsave = e2.X_add_number - REG_GR) < 128) |
| 3990 | ; |
| 3991 | else |
| 3992 | as_bad ("Second operand not a constant or general register"); |
| 3993 | |
| 3994 | add_unwind_entry (output_prologue_gr (mask, grsave)); |
| 3995 | } |
| 3996 | else |
| 3997 | as_bad ("First operand not a constant"); |
| 3998 | } |
| 3999 | else |
| 4000 | add_unwind_entry (output_prologue ()); |
| 4001 | |
| 4002 | unwind.prologue = 1; |
| 4003 | unwind.prologue_mask = mask; |
| 4004 | ++unwind.prologue_count; |
| 4005 | } |
| 4006 | |
| 4007 | static void |
| 4008 | dot_endp (dummy) |
| 4009 | int dummy ATTRIBUTE_UNUSED; |
| 4010 | { |
| 4011 | expressionS e; |
| 4012 | unsigned char *ptr; |
| 4013 | int bytes_per_address; |
| 4014 | long where; |
| 4015 | segT saved_seg; |
| 4016 | subsegT saved_subseg; |
| 4017 | const char *sec_name, *text_name; |
| 4018 | char *name, *p, c; |
| 4019 | symbolS *sym; |
| 4020 | |
| 4021 | if (unwind.saved_text_seg) |
| 4022 | { |
| 4023 | saved_seg = unwind.saved_text_seg; |
| 4024 | saved_subseg = unwind.saved_text_subseg; |
| 4025 | unwind.saved_text_seg = NULL; |
| 4026 | } |
| 4027 | else |
| 4028 | { |
| 4029 | saved_seg = now_seg; |
| 4030 | saved_subseg = now_subseg; |
| 4031 | } |
| 4032 | |
| 4033 | /* |
| 4034 | Use a slightly ugly scheme to derive the unwind section names from |
| 4035 | the text section name: |
| 4036 | |
| 4037 | text sect. unwind table sect. |
| 4038 | name: name: comments: |
| 4039 | ---------- ----------------- -------------------------------- |
| 4040 | .text .IA_64.unwind |
| 4041 | .text.foo .IA_64.unwind.text.foo |
| 4042 | .foo .IA_64.unwind.foo |
| 4043 | .gnu.linkonce.t.foo |
| 4044 | .gnu.linkonce.ia64unw.foo |
| 4045 | _info .IA_64.unwind_info gas issues error message (ditto) |
| 4046 | _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) |
| 4047 | |
| 4048 | This mapping is done so that: |
| 4049 | |
| 4050 | (a) An object file with unwind info only in .text will use |
| 4051 | unwind section names .IA_64.unwind and .IA_64.unwind_info. |
| 4052 | This follows the letter of the ABI and also ensures backwards |
| 4053 | compatibility with older toolchains. |
| 4054 | |
| 4055 | (b) An object file with unwind info in multiple text sections |
| 4056 | will use separate unwind sections for each text section. |
| 4057 | This allows us to properly set the "sh_info" and "sh_link" |
| 4058 | fields in SHT_IA_64_UNWIND as required by the ABI and also |
| 4059 | lets GNU ld support programs with multiple segments |
| 4060 | containing unwind info (as might be the case for certain |
| 4061 | embedded applications). |
| 4062 | |
| 4063 | (c) An error is issued if there would be a name clash. |
| 4064 | */ |
| 4065 | text_name = segment_name (saved_seg); |
| 4066 | if (strncmp (text_name, "_info", 5) == 0) |
| 4067 | { |
| 4068 | as_bad ("Illegal section name `%s' (causes unwind section name clash)", |
| 4069 | text_name); |
| 4070 | ignore_rest_of_line (); |
| 4071 | return; |
| 4072 | } |
| 4073 | if (strcmp (text_name, ".text") == 0) |
| 4074 | text_name = ""; |
| 4075 | |
| 4076 | insn_group_break (1, 0, 0); |
| 4077 | |
| 4078 | /* If there wasn't a .handlerdata, we haven't generated an image yet. */ |
| 4079 | if (!unwind.info) |
| 4080 | generate_unwind_image (text_name); |
| 4081 | |
| 4082 | if (unwind.info || unwind.force_unwind_entry) |
| 4083 | { |
| 4084 | subseg_set (md.last_text_seg, 0); |
| 4085 | unwind.proc_end = expr_build_dot (); |
| 4086 | |
| 4087 | make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name); |
| 4088 | set_section ((char *) sec_name); |
| 4089 | bfd_set_section_flags (stdoutput, now_seg, |
| 4090 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); |
| 4091 | |
| 4092 | /* Make sure that section has 4 byte alignment for ILP32 and |
| 4093 | 8 byte alignment for LP64. */ |
| 4094 | record_alignment (now_seg, md.pointer_size_shift); |
| 4095 | |
| 4096 | /* Need space for 3 pointers for procedure start, procedure end, |
| 4097 | and unwind info. */ |
| 4098 | ptr = frag_more (3 * md.pointer_size); |
| 4099 | where = frag_now_fix () - (3 * md.pointer_size); |
| 4100 | bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; |
| 4101 | |
| 4102 | /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ |
| 4103 | e.X_op = O_pseudo_fixup; |
| 4104 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; |
| 4105 | e.X_add_number = 0; |
| 4106 | e.X_add_symbol = unwind.proc_start; |
| 4107 | ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); |
| 4108 | |
| 4109 | e.X_op = O_pseudo_fixup; |
| 4110 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; |
| 4111 | e.X_add_number = 0; |
| 4112 | e.X_add_symbol = unwind.proc_end; |
| 4113 | ia64_cons_fix_new (frag_now, where + bytes_per_address, |
| 4114 | bytes_per_address, &e); |
| 4115 | |
| 4116 | if (unwind.info) |
| 4117 | { |
| 4118 | e.X_op = O_pseudo_fixup; |
| 4119 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; |
| 4120 | e.X_add_number = 0; |
| 4121 | e.X_add_symbol = unwind.info; |
| 4122 | ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), |
| 4123 | bytes_per_address, &e); |
| 4124 | } |
| 4125 | else |
| 4126 | md_number_to_chars (ptr + (bytes_per_address * 2), 0, |
| 4127 | bytes_per_address); |
| 4128 | |
| 4129 | } |
| 4130 | subseg_set (saved_seg, saved_subseg); |
| 4131 | |
| 4132 | /* Parse names of main and alternate entry points and set symbol sizes. */ |
| 4133 | while (1) |
| 4134 | { |
| 4135 | SKIP_WHITESPACE (); |
| 4136 | name = input_line_pointer; |
| 4137 | c = get_symbol_end (); |
| 4138 | p = input_line_pointer; |
| 4139 | sym = symbol_find (name); |
| 4140 | if (sym && unwind.proc_start |
| 4141 | && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION) |
| 4142 | && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL) |
| 4143 | { |
| 4144 | fragS *fr = symbol_get_frag (unwind.proc_start); |
| 4145 | fragS *frag = symbol_get_frag (sym); |
| 4146 | |
| 4147 | /* Check whether the function label is at or beyond last |
| 4148 | .proc directive. */ |
| 4149 | while (fr && fr != frag) |
| 4150 | fr = fr->fr_next; |
| 4151 | if (fr) |
| 4152 | { |
| 4153 | if (frag == frag_now && SEG_NORMAL (now_seg)) |
| 4154 | S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym)); |
| 4155 | else |
| 4156 | { |
| 4157 | symbol_get_obj (sym)->size = |
| 4158 | (expressionS *) xmalloc (sizeof (expressionS)); |
| 4159 | symbol_get_obj (sym)->size->X_op = O_subtract; |
| 4160 | symbol_get_obj (sym)->size->X_add_symbol |
| 4161 | = symbol_new (FAKE_LABEL_NAME, now_seg, |
| 4162 | frag_now_fix (), frag_now); |
| 4163 | symbol_get_obj (sym)->size->X_op_symbol = sym; |
| 4164 | symbol_get_obj (sym)->size->X_add_number = 0; |
| 4165 | } |
| 4166 | } |
| 4167 | } |
| 4168 | *p = c; |
| 4169 | SKIP_WHITESPACE (); |
| 4170 | if (*input_line_pointer != ',') |
| 4171 | break; |
| 4172 | ++input_line_pointer; |
| 4173 | } |
| 4174 | demand_empty_rest_of_line (); |
| 4175 | unwind.proc_start = unwind.proc_end = unwind.info = 0; |
| 4176 | } |
| 4177 | |
| 4178 | static void |
| 4179 | dot_template (template) |
| 4180 | int template; |
| 4181 | { |
| 4182 | CURR_SLOT.user_template = template; |
| 4183 | } |
| 4184 | |
| 4185 | static void |
| 4186 | dot_regstk (dummy) |
| 4187 | int dummy ATTRIBUTE_UNUSED; |
| 4188 | { |
| 4189 | int ins, locs, outs, rots; |
| 4190 | |
| 4191 | if (is_it_end_of_statement ()) |
| 4192 | ins = locs = outs = rots = 0; |
| 4193 | else |
| 4194 | { |
| 4195 | ins = get_absolute_expression (); |
| 4196 | if (*input_line_pointer++ != ',') |
| 4197 | goto err; |
| 4198 | locs = get_absolute_expression (); |
| 4199 | if (*input_line_pointer++ != ',') |
| 4200 | goto err; |
| 4201 | outs = get_absolute_expression (); |
| 4202 | if (*input_line_pointer++ != ',') |
| 4203 | goto err; |
| 4204 | rots = get_absolute_expression (); |
| 4205 | } |
| 4206 | set_regstack (ins, locs, outs, rots); |
| 4207 | return; |
| 4208 | |
| 4209 | err: |
| 4210 | as_bad ("Comma expected"); |
| 4211 | ignore_rest_of_line (); |
| 4212 | } |
| 4213 | |
| 4214 | static void |
| 4215 | dot_rot (type) |
| 4216 | int type; |
| 4217 | { |
| 4218 | unsigned num_regs, num_alloced = 0; |
| 4219 | struct dynreg **drpp, *dr; |
| 4220 | int ch, base_reg = 0; |
| 4221 | char *name, *start; |
| 4222 | size_t len; |
| 4223 | |
| 4224 | switch (type) |
| 4225 | { |
| 4226 | case DYNREG_GR: base_reg = REG_GR + 32; break; |
| 4227 | case DYNREG_FR: base_reg = REG_FR + 32; break; |
| 4228 | case DYNREG_PR: base_reg = REG_P + 16; break; |
| 4229 | default: break; |
| 4230 | } |
| 4231 | |
| 4232 | /* First, remove existing names from hash table. */ |
| 4233 | for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) |
| 4234 | { |
| 4235 | hash_delete (md.dynreg_hash, dr->name); |
| 4236 | dr->num_regs = 0; |
| 4237 | } |
| 4238 | |
| 4239 | drpp = &md.dynreg[type]; |
| 4240 | while (1) |
| 4241 | { |
| 4242 | start = input_line_pointer; |
| 4243 | ch = get_symbol_end (); |
| 4244 | *input_line_pointer = ch; |
| 4245 | len = (input_line_pointer - start); |
| 4246 | |
| 4247 | SKIP_WHITESPACE (); |
| 4248 | if (*input_line_pointer != '[') |
| 4249 | { |
| 4250 | as_bad ("Expected '['"); |
| 4251 | goto err; |
| 4252 | } |
| 4253 | ++input_line_pointer; /* skip '[' */ |
| 4254 | |
| 4255 | num_regs = get_absolute_expression (); |
| 4256 | |
| 4257 | if (*input_line_pointer++ != ']') |
| 4258 | { |
| 4259 | as_bad ("Expected ']'"); |
| 4260 | goto err; |
| 4261 | } |
| 4262 | SKIP_WHITESPACE (); |
| 4263 | |
| 4264 | num_alloced += num_regs; |
| 4265 | switch (type) |
| 4266 | { |
| 4267 | case DYNREG_GR: |
| 4268 | if (num_alloced > md.rot.num_regs) |
| 4269 | { |
| 4270 | as_bad ("Used more than the declared %d rotating registers", |
| 4271 | md.rot.num_regs); |
| 4272 | goto err; |
| 4273 | } |
| 4274 | break; |
| 4275 | case DYNREG_FR: |
| 4276 | if (num_alloced > 96) |
| 4277 | { |
| 4278 | as_bad ("Used more than the available 96 rotating registers"); |
| 4279 | goto err; |
| 4280 | } |
| 4281 | break; |
| 4282 | case DYNREG_PR: |
| 4283 | if (num_alloced > 48) |
| 4284 | { |
| 4285 | as_bad ("Used more than the available 48 rotating registers"); |
| 4286 | goto err; |
| 4287 | } |
| 4288 | break; |
| 4289 | |
| 4290 | default: |
| 4291 | break; |
| 4292 | } |
| 4293 | |
| 4294 | name = obstack_alloc (¬es, len + 1); |
| 4295 | memcpy (name, start, len); |
| 4296 | name[len] = '\0'; |
| 4297 | |
| 4298 | if (!*drpp) |
| 4299 | { |
| 4300 | *drpp = obstack_alloc (¬es, sizeof (*dr)); |
| 4301 | memset (*drpp, 0, sizeof (*dr)); |
| 4302 | } |
| 4303 | |
| 4304 | dr = *drpp; |
| 4305 | dr->name = name; |
| 4306 | dr->num_regs = num_regs; |
| 4307 | dr->base = base_reg; |
| 4308 | drpp = &dr->next; |
| 4309 | base_reg += num_regs; |
| 4310 | |
| 4311 | if (hash_insert (md.dynreg_hash, name, dr)) |
| 4312 | { |
| 4313 | as_bad ("Attempt to redefine register set `%s'", name); |
| 4314 | goto err; |
| 4315 | } |
| 4316 | |
| 4317 | if (*input_line_pointer != ',') |
| 4318 | break; |
| 4319 | ++input_line_pointer; /* skip comma */ |
| 4320 | SKIP_WHITESPACE (); |
| 4321 | } |
| 4322 | demand_empty_rest_of_line (); |
| 4323 | return; |
| 4324 | |
| 4325 | err: |
| 4326 | ignore_rest_of_line (); |
| 4327 | } |
| 4328 | |
| 4329 | static void |
| 4330 | dot_byteorder (byteorder) |
| 4331 | int byteorder; |
| 4332 | { |
| 4333 | segment_info_type *seginfo = seg_info (now_seg); |
| 4334 | |
| 4335 | if (byteorder == -1) |
| 4336 | { |
| 4337 | if (seginfo->tc_segment_info_data.endian == 0) |
| 4338 | seginfo->tc_segment_info_data.endian |
| 4339 | = TARGET_BYTES_BIG_ENDIAN ? 1 : 2; |
| 4340 | byteorder = seginfo->tc_segment_info_data.endian == 1; |
| 4341 | } |
| 4342 | else |
| 4343 | seginfo->tc_segment_info_data.endian = byteorder ? 1 : 2; |
| 4344 | |
| 4345 | if (target_big_endian != byteorder) |
| 4346 | { |
| 4347 | target_big_endian = byteorder; |
| 4348 | if (target_big_endian) |
| 4349 | { |
| 4350 | ia64_number_to_chars = number_to_chars_bigendian; |
| 4351 | ia64_float_to_chars = ia64_float_to_chars_bigendian; |
| 4352 | } |
| 4353 | else |
| 4354 | { |
| 4355 | ia64_number_to_chars = number_to_chars_littleendian; |
| 4356 | ia64_float_to_chars = ia64_float_to_chars_littleendian; |
| 4357 | } |
| 4358 | } |
| 4359 | } |
| 4360 | |
| 4361 | static void |
| 4362 | dot_psr (dummy) |
| 4363 | int dummy ATTRIBUTE_UNUSED; |
| 4364 | { |
| 4365 | char *option; |
| 4366 | int ch; |
| 4367 | |
| 4368 | while (1) |
| 4369 | { |
| 4370 | option = input_line_pointer; |
| 4371 | ch = get_symbol_end (); |
| 4372 | if (strcmp (option, "lsb") == 0) |
| 4373 | md.flags &= ~EF_IA_64_BE; |
| 4374 | else if (strcmp (option, "msb") == 0) |
| 4375 | md.flags |= EF_IA_64_BE; |
| 4376 | else if (strcmp (option, "abi32") == 0) |
| 4377 | md.flags &= ~EF_IA_64_ABI64; |
| 4378 | else if (strcmp (option, "abi64") == 0) |
| 4379 | md.flags |= EF_IA_64_ABI64; |
| 4380 | else |
| 4381 | as_bad ("Unknown psr option `%s'", option); |
| 4382 | *input_line_pointer = ch; |
| 4383 | |
| 4384 | SKIP_WHITESPACE (); |
| 4385 | if (*input_line_pointer != ',') |
| 4386 | break; |
| 4387 | |
| 4388 | ++input_line_pointer; |
| 4389 | SKIP_WHITESPACE (); |
| 4390 | } |
| 4391 | demand_empty_rest_of_line (); |
| 4392 | } |
| 4393 | |
| 4394 | static void |
| 4395 | dot_ln (dummy) |
| 4396 | int dummy ATTRIBUTE_UNUSED; |
| 4397 | { |
| 4398 | new_logical_line (0, get_absolute_expression ()); |
| 4399 | demand_empty_rest_of_line (); |
| 4400 | } |
| 4401 | |
| 4402 | static char * |
| 4403 | parse_section_name () |
| 4404 | { |
| 4405 | char *name; |
| 4406 | int len; |
| 4407 | |
| 4408 | SKIP_WHITESPACE (); |
| 4409 | if (*input_line_pointer != '"') |
| 4410 | { |
| 4411 | as_bad ("Missing section name"); |
| 4412 | ignore_rest_of_line (); |
| 4413 | return 0; |
| 4414 | } |
| 4415 | name = demand_copy_C_string (&len); |
| 4416 | if (!name) |
| 4417 | { |
| 4418 | ignore_rest_of_line (); |
| 4419 | return 0; |
| 4420 | } |
| 4421 | SKIP_WHITESPACE (); |
| 4422 | if (*input_line_pointer != ',') |
| 4423 | { |
| 4424 | as_bad ("Comma expected after section name"); |
| 4425 | ignore_rest_of_line (); |
| 4426 | return 0; |
| 4427 | } |
| 4428 | ++input_line_pointer; /* skip comma */ |
| 4429 | return name; |
| 4430 | } |
| 4431 | |
| 4432 | static void |
| 4433 | dot_xdata (size) |
| 4434 | int size; |
| 4435 | { |
| 4436 | char *name = parse_section_name (); |
| 4437 | if (!name) |
| 4438 | return; |
| 4439 | |
| 4440 | md.keep_pending_output = 1; |
| 4441 | set_section (name); |
| 4442 | cons (size); |
| 4443 | obj_elf_previous (0); |
| 4444 | md.keep_pending_output = 0; |
| 4445 | } |
| 4446 | |
| 4447 | /* Why doesn't float_cons() call md_cons_align() the way cons() does? */ |
| 4448 | |
| 4449 | static void |
| 4450 | stmt_float_cons (kind) |
| 4451 | int kind; |
| 4452 | { |
| 4453 | size_t alignment; |
| 4454 | |
| 4455 | switch (kind) |
| 4456 | { |
| 4457 | case 'd': |
| 4458 | alignment = 8; |
| 4459 | break; |
| 4460 | |
| 4461 | case 'x': |
| 4462 | case 'X': |
| 4463 | alignment = 16; |
| 4464 | break; |
| 4465 | |
| 4466 | case 'f': |
| 4467 | default: |
| 4468 | alignment = 4; |
| 4469 | break; |
| 4470 | } |
| 4471 | ia64_do_align (alignment); |
| 4472 | float_cons (kind); |
| 4473 | } |
| 4474 | |
| 4475 | static void |
| 4476 | stmt_cons_ua (size) |
| 4477 | int size; |
| 4478 | { |
| 4479 | int saved_auto_align = md.auto_align; |
| 4480 | |
| 4481 | md.auto_align = 0; |
| 4482 | cons (size); |
| 4483 | md.auto_align = saved_auto_align; |
| 4484 | } |
| 4485 | |
| 4486 | static void |
| 4487 | dot_xfloat_cons (kind) |
| 4488 | int kind; |
| 4489 | { |
| 4490 | char *name = parse_section_name (); |
| 4491 | if (!name) |
| 4492 | return; |
| 4493 | |
| 4494 | md.keep_pending_output = 1; |
| 4495 | set_section (name); |
| 4496 | stmt_float_cons (kind); |
| 4497 | obj_elf_previous (0); |
| 4498 | md.keep_pending_output = 0; |
| 4499 | } |
| 4500 | |
| 4501 | static void |
| 4502 | dot_xstringer (zero) |
| 4503 | int zero; |
| 4504 | { |
| 4505 | char *name = parse_section_name (); |
| 4506 | if (!name) |
| 4507 | return; |
| 4508 | |
| 4509 | md.keep_pending_output = 1; |
| 4510 | set_section (name); |
| 4511 | stringer (zero); |
| 4512 | obj_elf_previous (0); |
| 4513 | md.keep_pending_output = 0; |
| 4514 | } |
| 4515 | |
| 4516 | static void |
| 4517 | dot_xdata_ua (size) |
| 4518 | int size; |
| 4519 | { |
| 4520 | int saved_auto_align = md.auto_align; |
| 4521 | char *name = parse_section_name (); |
| 4522 | if (!name) |
| 4523 | return; |
| 4524 | |
| 4525 | md.keep_pending_output = 1; |
| 4526 | set_section (name); |
| 4527 | md.auto_align = 0; |
| 4528 | cons (size); |
| 4529 | md.auto_align = saved_auto_align; |
| 4530 | obj_elf_previous (0); |
| 4531 | md.keep_pending_output = 0; |
| 4532 | } |
| 4533 | |
| 4534 | static void |
| 4535 | dot_xfloat_cons_ua (kind) |
| 4536 | int kind; |
| 4537 | { |
| 4538 | int saved_auto_align = md.auto_align; |
| 4539 | char *name = parse_section_name (); |
| 4540 | if (!name) |
| 4541 | return; |
| 4542 | |
| 4543 | md.keep_pending_output = 1; |
| 4544 | set_section (name); |
| 4545 | md.auto_align = 0; |
| 4546 | stmt_float_cons (kind); |
| 4547 | md.auto_align = saved_auto_align; |
| 4548 | obj_elf_previous (0); |
| 4549 | md.keep_pending_output = 0; |
| 4550 | } |
| 4551 | |
| 4552 | /* .reg.val <regname>,value */ |
| 4553 | |
| 4554 | static void |
| 4555 | dot_reg_val (dummy) |
| 4556 | int dummy ATTRIBUTE_UNUSED; |
| 4557 | { |
| 4558 | expressionS reg; |
| 4559 | |
| 4560 | expression (®); |
| 4561 | if (reg.X_op != O_register) |
| 4562 | { |
| 4563 | as_bad (_("Register name expected")); |
| 4564 | ignore_rest_of_line (); |
| 4565 | } |
| 4566 | else if (*input_line_pointer++ != ',') |
| 4567 | { |
| 4568 | as_bad (_("Comma expected")); |
| 4569 | ignore_rest_of_line (); |
| 4570 | } |
| 4571 | else |
| 4572 | { |
| 4573 | valueT value = get_absolute_expression (); |
| 4574 | int regno = reg.X_add_number; |
| 4575 | if (regno < REG_GR || regno > REG_GR + 128) |
| 4576 | as_warn (_("Register value annotation ignored")); |
| 4577 | else |
| 4578 | { |
| 4579 | gr_values[regno - REG_GR].known = 1; |
| 4580 | gr_values[regno - REG_GR].value = value; |
| 4581 | gr_values[regno - REG_GR].path = md.path; |
| 4582 | } |
| 4583 | } |
| 4584 | demand_empty_rest_of_line (); |
| 4585 | } |
| 4586 | |
| 4587 | /* select dv checking mode |
| 4588 | .auto |
| 4589 | .explicit |
| 4590 | .default |
| 4591 | |
| 4592 | A stop is inserted when changing modes |
| 4593 | */ |
| 4594 | |
| 4595 | static void |
| 4596 | dot_dv_mode (type) |
| 4597 | int type; |
| 4598 | { |
| 4599 | if (md.manual_bundling) |
| 4600 | as_warn (_("Directive invalid within a bundle")); |
| 4601 | |
| 4602 | if (type == 'E' || type == 'A') |
| 4603 | md.mode_explicitly_set = 0; |
| 4604 | else |
| 4605 | md.mode_explicitly_set = 1; |
| 4606 | |
| 4607 | md.detect_dv = 1; |
| 4608 | switch (type) |
| 4609 | { |
| 4610 | case 'A': |
| 4611 | case 'a': |
| 4612 | if (md.explicit_mode) |
| 4613 | insn_group_break (1, 0, 0); |
| 4614 | md.explicit_mode = 0; |
| 4615 | break; |
| 4616 | case 'E': |
| 4617 | case 'e': |
| 4618 | if (!md.explicit_mode) |
| 4619 | insn_group_break (1, 0, 0); |
| 4620 | md.explicit_mode = 1; |
| 4621 | break; |
| 4622 | default: |
| 4623 | case 'd': |
| 4624 | if (md.explicit_mode != md.default_explicit_mode) |
| 4625 | insn_group_break (1, 0, 0); |
| 4626 | md.explicit_mode = md.default_explicit_mode; |
| 4627 | md.mode_explicitly_set = 0; |
| 4628 | break; |
| 4629 | } |
| 4630 | } |
| 4631 | |
| 4632 | static void |
| 4633 | print_prmask (mask) |
| 4634 | valueT mask; |
| 4635 | { |
| 4636 | int regno; |
| 4637 | char *comma = ""; |
| 4638 | for (regno = 0; regno < 64; regno++) |
| 4639 | { |
| 4640 | if (mask & ((valueT) 1 << regno)) |
| 4641 | { |
| 4642 | fprintf (stderr, "%s p%d", comma, regno); |
| 4643 | comma = ","; |
| 4644 | } |
| 4645 | } |
| 4646 | } |
| 4647 | |
| 4648 | /* |
| 4649 | .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") |
| 4650 | .pred.rel.imply p1, p2 (also .pred.rel "imply") |
| 4651 | .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") |
| 4652 | .pred.safe_across_calls p1 [, p2 [,...]] |
| 4653 | */ |
| 4654 | |
| 4655 | static void |
| 4656 | dot_pred_rel (type) |
| 4657 | int type; |
| 4658 | { |
| 4659 | valueT mask = 0; |
| 4660 | int count = 0; |
| 4661 | int p1 = -1, p2 = -1; |
| 4662 | |
| 4663 | if (type == 0) |
| 4664 | { |
| 4665 | if (*input_line_pointer != '"') |
| 4666 | { |
| 4667 | as_bad (_("Missing predicate relation type")); |
| 4668 | ignore_rest_of_line (); |
| 4669 | return; |
| 4670 | } |
| 4671 | else |
| 4672 | { |
| 4673 | int len; |
| 4674 | char *form = demand_copy_C_string (&len); |
| 4675 | if (strcmp (form, "mutex") == 0) |
| 4676 | type = 'm'; |
| 4677 | else if (strcmp (form, "clear") == 0) |
| 4678 | type = 'c'; |
| 4679 | else if (strcmp (form, "imply") == 0) |
| 4680 | type = 'i'; |
| 4681 | else |
| 4682 | { |
| 4683 | as_bad (_("Unrecognized predicate relation type")); |
| 4684 | ignore_rest_of_line (); |
| 4685 | return; |
| 4686 | } |
| 4687 | } |
| 4688 | if (*input_line_pointer == ',') |
| 4689 | ++input_line_pointer; |
| 4690 | SKIP_WHITESPACE (); |
| 4691 | } |
| 4692 | |
| 4693 | SKIP_WHITESPACE (); |
| 4694 | while (1) |
| 4695 | { |
| 4696 | valueT bit = 1; |
| 4697 | int regno; |
| 4698 | |
| 4699 | if (TOUPPER (*input_line_pointer) != 'P' |
| 4700 | || (regno = atoi (++input_line_pointer)) < 0 |
| 4701 | || regno > 63) |
| 4702 | { |
| 4703 | as_bad (_("Predicate register expected")); |
| 4704 | ignore_rest_of_line (); |
| 4705 | return; |
| 4706 | } |
| 4707 | while (ISDIGIT (*input_line_pointer)) |
| 4708 | ++input_line_pointer; |
| 4709 | if (p1 == -1) |
| 4710 | p1 = regno; |
| 4711 | else if (p2 == -1) |
| 4712 | p2 = regno; |
| 4713 | bit <<= regno; |
| 4714 | if (mask & bit) |
| 4715 | as_warn (_("Duplicate predicate register ignored")); |
| 4716 | mask |= bit; |
| 4717 | count++; |
| 4718 | /* See if it's a range. */ |
| 4719 | if (*input_line_pointer == '-') |
| 4720 | { |
| 4721 | valueT stop = 1; |
| 4722 | ++input_line_pointer; |
| 4723 | |
| 4724 | if (TOUPPER (*input_line_pointer) != 'P' |
| 4725 | || (regno = atoi (++input_line_pointer)) < 0 |
| 4726 | || regno > 63) |
| 4727 | { |
| 4728 | as_bad (_("Predicate register expected")); |
| 4729 | ignore_rest_of_line (); |
| 4730 | return; |
| 4731 | } |
| 4732 | while (ISDIGIT (*input_line_pointer)) |
| 4733 | ++input_line_pointer; |
| 4734 | stop <<= regno; |
| 4735 | if (bit >= stop) |
| 4736 | { |
| 4737 | as_bad (_("Bad register range")); |
| 4738 | ignore_rest_of_line (); |
| 4739 | return; |
| 4740 | } |
| 4741 | while (bit < stop) |
| 4742 | { |
| 4743 | bit <<= 1; |
| 4744 | mask |= bit; |
| 4745 | count++; |
| 4746 | } |
| 4747 | SKIP_WHITESPACE (); |
| 4748 | } |
| 4749 | if (*input_line_pointer != ',') |
| 4750 | break; |
| 4751 | ++input_line_pointer; |
| 4752 | SKIP_WHITESPACE (); |
| 4753 | } |
| 4754 | |
| 4755 | switch (type) |
| 4756 | { |
| 4757 | case 'c': |
| 4758 | if (count == 0) |
| 4759 | mask = ~(valueT) 0; |
| 4760 | clear_qp_mutex (mask); |
| 4761 | clear_qp_implies (mask, (valueT) 0); |
| 4762 | break; |
| 4763 | case 'i': |
| 4764 | if (count != 2 || p1 == -1 || p2 == -1) |
| 4765 | as_bad (_("Predicate source and target required")); |
| 4766 | else if (p1 == 0 || p2 == 0) |
| 4767 | as_bad (_("Use of p0 is not valid in this context")); |
| 4768 | else |
| 4769 | add_qp_imply (p1, p2); |
| 4770 | break; |
| 4771 | case 'm': |
| 4772 | if (count < 2) |
| 4773 | { |
| 4774 | as_bad (_("At least two PR arguments expected")); |
| 4775 | break; |
| 4776 | } |
| 4777 | else if (mask & 1) |
| 4778 | { |
| 4779 | as_bad (_("Use of p0 is not valid in this context")); |
| 4780 | break; |
| 4781 | } |
| 4782 | add_qp_mutex (mask); |
| 4783 | break; |
| 4784 | case 's': |
| 4785 | /* note that we don't override any existing relations */ |
| 4786 | if (count == 0) |
| 4787 | { |
| 4788 | as_bad (_("At least one PR argument expected")); |
| 4789 | break; |
| 4790 | } |
| 4791 | if (md.debug_dv) |
| 4792 | { |
| 4793 | fprintf (stderr, "Safe across calls: "); |
| 4794 | print_prmask (mask); |
| 4795 | fprintf (stderr, "\n"); |
| 4796 | } |
| 4797 | qp_safe_across_calls = mask; |
| 4798 | break; |
| 4799 | } |
| 4800 | demand_empty_rest_of_line (); |
| 4801 | } |
| 4802 | |
| 4803 | /* .entry label [, label [, ...]] |
| 4804 | Hint to DV code that the given labels are to be considered entry points. |
| 4805 | Otherwise, only global labels are considered entry points. */ |
| 4806 | |
| 4807 | static void |
| 4808 | dot_entry (dummy) |
| 4809 | int dummy ATTRIBUTE_UNUSED; |
| 4810 | { |
| 4811 | const char *err; |
| 4812 | char *name; |
| 4813 | int c; |
| 4814 | symbolS *symbolP; |
| 4815 | |
| 4816 | do |
| 4817 | { |
| 4818 | name = input_line_pointer; |
| 4819 | c = get_symbol_end (); |
| 4820 | symbolP = symbol_find_or_make (name); |
| 4821 | |
| 4822 | err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); |
| 4823 | if (err) |
| 4824 | as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), |
| 4825 | name, err); |
| 4826 | |
| 4827 | *input_line_pointer = c; |
| 4828 | SKIP_WHITESPACE (); |
| 4829 | c = *input_line_pointer; |
| 4830 | if (c == ',') |
| 4831 | { |
| 4832 | input_line_pointer++; |
| 4833 | SKIP_WHITESPACE (); |
| 4834 | if (*input_line_pointer == '\n') |
| 4835 | c = '\n'; |
| 4836 | } |
| 4837 | } |
| 4838 | while (c == ','); |
| 4839 | |
| 4840 | demand_empty_rest_of_line (); |
| 4841 | } |
| 4842 | |
| 4843 | /* .mem.offset offset, base |
| 4844 | "base" is used to distinguish between offsets from a different base. */ |
| 4845 | |
| 4846 | static void |
| 4847 | dot_mem_offset (dummy) |
| 4848 | int dummy ATTRIBUTE_UNUSED; |
| 4849 | { |
| 4850 | md.mem_offset.hint = 1; |
| 4851 | md.mem_offset.offset = get_absolute_expression (); |
| 4852 | if (*input_line_pointer != ',') |
| 4853 | { |
| 4854 | as_bad (_("Comma expected")); |
| 4855 | ignore_rest_of_line (); |
| 4856 | return; |
| 4857 | } |
| 4858 | ++input_line_pointer; |
| 4859 | md.mem_offset.base = get_absolute_expression (); |
| 4860 | demand_empty_rest_of_line (); |
| 4861 | } |
| 4862 | |
| 4863 | /* ia64-specific pseudo-ops: */ |
| 4864 | const pseudo_typeS md_pseudo_table[] = |
| 4865 | { |
| 4866 | { "radix", dot_radix, 0 }, |
| 4867 | { "lcomm", s_lcomm_bytes, 1 }, |
| 4868 | { "bss", dot_special_section, SPECIAL_SECTION_BSS }, |
| 4869 | { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, |
| 4870 | { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, |
| 4871 | { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, |
| 4872 | { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, |
| 4873 | { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, |
| 4874 | { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, |
| 4875 | { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY }, |
| 4876 | { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY }, |
| 4877 | { "proc", dot_proc, 0 }, |
| 4878 | { "body", dot_body, 0 }, |
| 4879 | { "prologue", dot_prologue, 0 }, |
| 4880 | { "endp", dot_endp, 0 }, |
| 4881 | |
| 4882 | { "fframe", dot_fframe, 0 }, |
| 4883 | { "vframe", dot_vframe, 0 }, |
| 4884 | { "vframesp", dot_vframesp, 0 }, |
| 4885 | { "vframepsp", dot_vframepsp, 0 }, |
| 4886 | { "save", dot_save, 0 }, |
| 4887 | { "restore", dot_restore, 0 }, |
| 4888 | { "restorereg", dot_restorereg, 0 }, |
| 4889 | { "restorereg.p", dot_restorereg_p, 0 }, |
| 4890 | { "handlerdata", dot_handlerdata, 0 }, |
| 4891 | { "unwentry", dot_unwentry, 0 }, |
| 4892 | { "altrp", dot_altrp, 0 }, |
| 4893 | { "savesp", dot_savemem, 0 }, |
| 4894 | { "savepsp", dot_savemem, 1 }, |
| 4895 | { "save.g", dot_saveg, 0 }, |
| 4896 | { "save.f", dot_savef, 0 }, |
| 4897 | { "save.b", dot_saveb, 0 }, |
| 4898 | { "save.gf", dot_savegf, 0 }, |
| 4899 | { "spill", dot_spill, 0 }, |
| 4900 | { "spillreg", dot_spillreg, 0 }, |
| 4901 | { "spillsp", dot_spillmem, 0 }, |
| 4902 | { "spillpsp", dot_spillmem, 1 }, |
| 4903 | { "spillreg.p", dot_spillreg_p, 0 }, |
| 4904 | { "spillsp.p", dot_spillmem_p, 0 }, |
| 4905 | { "spillpsp.p", dot_spillmem_p, 1 }, |
| 4906 | { "label_state", dot_label_state, 0 }, |
| 4907 | { "copy_state", dot_copy_state, 0 }, |
| 4908 | { "unwabi", dot_unwabi, 0 }, |
| 4909 | { "personality", dot_personality, 0 }, |
| 4910 | #if 0 |
| 4911 | { "estate", dot_estate, 0 }, |
| 4912 | #endif |
| 4913 | { "mii", dot_template, 0x0 }, |
| 4914 | { "mli", dot_template, 0x2 }, /* old format, for compatibility */ |
| 4915 | { "mlx", dot_template, 0x2 }, |
| 4916 | { "mmi", dot_template, 0x4 }, |
| 4917 | { "mfi", dot_template, 0x6 }, |
| 4918 | { "mmf", dot_template, 0x7 }, |
| 4919 | { "mib", dot_template, 0x8 }, |
| 4920 | { "mbb", dot_template, 0x9 }, |
| 4921 | { "bbb", dot_template, 0xb }, |
| 4922 | { "mmb", dot_template, 0xc }, |
| 4923 | { "mfb", dot_template, 0xe }, |
| 4924 | #if 0 |
| 4925 | { "lb", dot_scope, 0 }, |
| 4926 | { "le", dot_scope, 1 }, |
| 4927 | #endif |
| 4928 | { "align", s_align_bytes, 0 }, |
| 4929 | { "regstk", dot_regstk, 0 }, |
| 4930 | { "rotr", dot_rot, DYNREG_GR }, |
| 4931 | { "rotf", dot_rot, DYNREG_FR }, |
| 4932 | { "rotp", dot_rot, DYNREG_PR }, |
| 4933 | { "lsb", dot_byteorder, 0 }, |
| 4934 | { "msb", dot_byteorder, 1 }, |
| 4935 | { "psr", dot_psr, 0 }, |
| 4936 | { "alias", dot_alias, 0 }, |
| 4937 | { "secalias", dot_alias, 1 }, |
| 4938 | { "ln", dot_ln, 0 }, /* source line info (for debugging) */ |
| 4939 | |
| 4940 | { "xdata1", dot_xdata, 1 }, |
| 4941 | { "xdata2", dot_xdata, 2 }, |
| 4942 | { "xdata4", dot_xdata, 4 }, |
| 4943 | { "xdata8", dot_xdata, 8 }, |
| 4944 | { "xreal4", dot_xfloat_cons, 'f' }, |
| 4945 | { "xreal8", dot_xfloat_cons, 'd' }, |
| 4946 | { "xreal10", dot_xfloat_cons, 'x' }, |
| 4947 | { "xreal16", dot_xfloat_cons, 'X' }, |
| 4948 | { "xstring", dot_xstringer, 0 }, |
| 4949 | { "xstringz", dot_xstringer, 1 }, |
| 4950 | |
| 4951 | /* unaligned versions: */ |
| 4952 | { "xdata2.ua", dot_xdata_ua, 2 }, |
| 4953 | { "xdata4.ua", dot_xdata_ua, 4 }, |
| 4954 | { "xdata8.ua", dot_xdata_ua, 8 }, |
| 4955 | { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, |
| 4956 | { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, |
| 4957 | { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, |
| 4958 | { "xreal16.ua", dot_xfloat_cons_ua, 'X' }, |
| 4959 | |
| 4960 | /* annotations/DV checking support */ |
| 4961 | { "entry", dot_entry, 0 }, |
| 4962 | { "mem.offset", dot_mem_offset, 0 }, |
| 4963 | { "pred.rel", dot_pred_rel, 0 }, |
| 4964 | { "pred.rel.clear", dot_pred_rel, 'c' }, |
| 4965 | { "pred.rel.imply", dot_pred_rel, 'i' }, |
| 4966 | { "pred.rel.mutex", dot_pred_rel, 'm' }, |
| 4967 | { "pred.safe_across_calls", dot_pred_rel, 's' }, |
| 4968 | { "reg.val", dot_reg_val, 0 }, |
| 4969 | { "auto", dot_dv_mode, 'a' }, |
| 4970 | { "explicit", dot_dv_mode, 'e' }, |
| 4971 | { "default", dot_dv_mode, 'd' }, |
| 4972 | |
| 4973 | /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work. |
| 4974 | IA-64 aligns data allocation pseudo-ops by default, so we have to |
| 4975 | tell it that these ones are supposed to be unaligned. Long term, |
| 4976 | should rewrite so that only IA-64 specific data allocation pseudo-ops |
| 4977 | are aligned by default. */ |
| 4978 | {"2byte", stmt_cons_ua, 2}, |
| 4979 | {"4byte", stmt_cons_ua, 4}, |
| 4980 | {"8byte", stmt_cons_ua, 8}, |
| 4981 | |
| 4982 | { NULL, 0, 0 } |
| 4983 | }; |
| 4984 | |
| 4985 | static const struct pseudo_opcode |
| 4986 | { |
| 4987 | const char *name; |
| 4988 | void (*handler) (int); |
| 4989 | int arg; |
| 4990 | } |
| 4991 | pseudo_opcode[] = |
| 4992 | { |
| 4993 | /* these are more like pseudo-ops, but don't start with a dot */ |
| 4994 | { "data1", cons, 1 }, |
| 4995 | { "data2", cons, 2 }, |
| 4996 | { "data4", cons, 4 }, |
| 4997 | { "data8", cons, 8 }, |
| 4998 | { "data16", cons, 16 }, |
| 4999 | { "real4", stmt_float_cons, 'f' }, |
| 5000 | { "real8", stmt_float_cons, 'd' }, |
| 5001 | { "real10", stmt_float_cons, 'x' }, |
| 5002 | { "real16", stmt_float_cons, 'X' }, |
| 5003 | { "string", stringer, 0 }, |
| 5004 | { "stringz", stringer, 1 }, |
| 5005 | |
| 5006 | /* unaligned versions: */ |
| 5007 | { "data2.ua", stmt_cons_ua, 2 }, |
| 5008 | { "data4.ua", stmt_cons_ua, 4 }, |
| 5009 | { "data8.ua", stmt_cons_ua, 8 }, |
| 5010 | { "data16.ua", stmt_cons_ua, 16 }, |
| 5011 | { "real4.ua", float_cons, 'f' }, |
| 5012 | { "real8.ua", float_cons, 'd' }, |
| 5013 | { "real10.ua", float_cons, 'x' }, |
| 5014 | { "real16.ua", float_cons, 'X' }, |
| 5015 | }; |
| 5016 | |
| 5017 | /* Declare a register by creating a symbol for it and entering it in |
| 5018 | the symbol table. */ |
| 5019 | |
| 5020 | static symbolS * |
| 5021 | declare_register (name, regnum) |
| 5022 | const char *name; |
| 5023 | int regnum; |
| 5024 | { |
| 5025 | const char *err; |
| 5026 | symbolS *sym; |
| 5027 | |
| 5028 | sym = symbol_new (name, reg_section, regnum, &zero_address_frag); |
| 5029 | |
| 5030 | err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); |
| 5031 | if (err) |
| 5032 | as_fatal ("Inserting \"%s\" into register table failed: %s", |
| 5033 | name, err); |
| 5034 | |
| 5035 | return sym; |
| 5036 | } |
| 5037 | |
| 5038 | static void |
| 5039 | declare_register_set (prefix, num_regs, base_regnum) |
| 5040 | const char *prefix; |
| 5041 | int num_regs; |
| 5042 | int base_regnum; |
| 5043 | { |
| 5044 | char name[8]; |
| 5045 | int i; |
| 5046 | |
| 5047 | for (i = 0; i < num_regs; ++i) |
| 5048 | { |
| 5049 | sprintf (name, "%s%u", prefix, i); |
| 5050 | declare_register (name, base_regnum + i); |
| 5051 | } |
| 5052 | } |
| 5053 | |
| 5054 | static unsigned int |
| 5055 | operand_width (opnd) |
| 5056 | enum ia64_opnd opnd; |
| 5057 | { |
| 5058 | const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; |
| 5059 | unsigned int bits = 0; |
| 5060 | int i; |
| 5061 | |
| 5062 | bits = 0; |
| 5063 | for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) |
| 5064 | bits += odesc->field[i].bits; |
| 5065 | |
| 5066 | return bits; |
| 5067 | } |
| 5068 | |
| 5069 | static enum operand_match_result |
| 5070 | operand_match (idesc, index, e) |
| 5071 | const struct ia64_opcode *idesc; |
| 5072 | int index; |
| 5073 | expressionS *e; |
| 5074 | { |
| 5075 | enum ia64_opnd opnd = idesc->operands[index]; |
| 5076 | int bits, relocatable = 0; |
| 5077 | struct insn_fix *fix; |
| 5078 | bfd_signed_vma val; |
| 5079 | |
| 5080 | switch (opnd) |
| 5081 | { |
| 5082 | /* constants: */ |
| 5083 | |
| 5084 | case IA64_OPND_AR_CCV: |
| 5085 | if (e->X_op == O_register && e->X_add_number == REG_AR + 32) |
| 5086 | return OPERAND_MATCH; |
| 5087 | break; |
| 5088 | |
| 5089 | case IA64_OPND_AR_CSD: |
| 5090 | if (e->X_op == O_register && e->X_add_number == REG_AR + 25) |
| 5091 | return OPERAND_MATCH; |
| 5092 | break; |
| 5093 | |
| 5094 | case IA64_OPND_AR_PFS: |
| 5095 | if (e->X_op == O_register && e->X_add_number == REG_AR + 64) |
| 5096 | return OPERAND_MATCH; |
| 5097 | break; |
| 5098 | |
| 5099 | case IA64_OPND_GR0: |
| 5100 | if (e->X_op == O_register && e->X_add_number == REG_GR + 0) |
| 5101 | return OPERAND_MATCH; |
| 5102 | break; |
| 5103 | |
| 5104 | case IA64_OPND_IP: |
| 5105 | if (e->X_op == O_register && e->X_add_number == REG_IP) |
| 5106 | return OPERAND_MATCH; |
| 5107 | break; |
| 5108 | |
| 5109 | case IA64_OPND_PR: |
| 5110 | if (e->X_op == O_register && e->X_add_number == REG_PR) |
| 5111 | return OPERAND_MATCH; |
| 5112 | break; |
| 5113 | |
| 5114 | case IA64_OPND_PR_ROT: |
| 5115 | if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) |
| 5116 | return OPERAND_MATCH; |
| 5117 | break; |
| 5118 | |
| 5119 | case IA64_OPND_PSR: |
| 5120 | if (e->X_op == O_register && e->X_add_number == REG_PSR) |
| 5121 | return OPERAND_MATCH; |
| 5122 | break; |
| 5123 | |
| 5124 | case IA64_OPND_PSR_L: |
| 5125 | if (e->X_op == O_register && e->X_add_number == REG_PSR_L) |
| 5126 | return OPERAND_MATCH; |
| 5127 | break; |
| 5128 | |
| 5129 | case IA64_OPND_PSR_UM: |
| 5130 | if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) |
| 5131 | return OPERAND_MATCH; |
| 5132 | break; |
| 5133 | |
| 5134 | case IA64_OPND_C1: |
| 5135 | if (e->X_op == O_constant) |
| 5136 | { |
| 5137 | if (e->X_add_number == 1) |
| 5138 | return OPERAND_MATCH; |
| 5139 | else |
| 5140 | return OPERAND_OUT_OF_RANGE; |
| 5141 | } |
| 5142 | break; |
| 5143 | |
| 5144 | case IA64_OPND_C8: |
| 5145 | if (e->X_op == O_constant) |
| 5146 | { |
| 5147 | if (e->X_add_number == 8) |
| 5148 | return OPERAND_MATCH; |
| 5149 | else |
| 5150 | return OPERAND_OUT_OF_RANGE; |
| 5151 | } |
| 5152 | break; |
| 5153 | |
| 5154 | case IA64_OPND_C16: |
| 5155 | if (e->X_op == O_constant) |
| 5156 | { |
| 5157 | if (e->X_add_number == 16) |
| 5158 | return OPERAND_MATCH; |
| 5159 | else |
| 5160 | return OPERAND_OUT_OF_RANGE; |
| 5161 | } |
| 5162 | break; |
| 5163 | |
| 5164 | /* register operands: */ |
| 5165 | |
| 5166 | case IA64_OPND_AR3: |
| 5167 | if (e->X_op == O_register && e->X_add_number >= REG_AR |
| 5168 | && e->X_add_number < REG_AR + 128) |
| 5169 | return OPERAND_MATCH; |
| 5170 | break; |
| 5171 | |
| 5172 | case IA64_OPND_B1: |
| 5173 | case IA64_OPND_B2: |
| 5174 | if (e->X_op == O_register && e->X_add_number >= REG_BR |
| 5175 | && e->X_add_number < REG_BR + 8) |
| 5176 | return OPERAND_MATCH; |
| 5177 | break; |
| 5178 | |
| 5179 | case IA64_OPND_CR3: |
| 5180 | if (e->X_op == O_register && e->X_add_number >= REG_CR |
| 5181 | && e->X_add_number < REG_CR + 128) |
| 5182 | return OPERAND_MATCH; |
| 5183 | break; |
| 5184 | |
| 5185 | case IA64_OPND_F1: |
| 5186 | case IA64_OPND_F2: |
| 5187 | case IA64_OPND_F3: |
| 5188 | case IA64_OPND_F4: |
| 5189 | if (e->X_op == O_register && e->X_add_number >= REG_FR |
| 5190 | && e->X_add_number < REG_FR + 128) |
| 5191 | return OPERAND_MATCH; |
| 5192 | break; |
| 5193 | |
| 5194 | case IA64_OPND_P1: |
| 5195 | case IA64_OPND_P2: |
| 5196 | if (e->X_op == O_register && e->X_add_number >= REG_P |
| 5197 | && e->X_add_number < REG_P + 64) |
| 5198 | return OPERAND_MATCH; |
| 5199 | break; |
| 5200 | |
| 5201 | case IA64_OPND_R1: |
| 5202 | case IA64_OPND_R2: |
| 5203 | case IA64_OPND_R3: |
| 5204 | if (e->X_op == O_register && e->X_add_number >= REG_GR |
| 5205 | && e->X_add_number < REG_GR + 128) |
| 5206 | return OPERAND_MATCH; |
| 5207 | break; |
| 5208 | |
| 5209 | case IA64_OPND_R3_2: |
| 5210 | if (e->X_op == O_register && e->X_add_number >= REG_GR) |
| 5211 | { |
| 5212 | if (e->X_add_number < REG_GR + 4) |
| 5213 | return OPERAND_MATCH; |
| 5214 | else if (e->X_add_number < REG_GR + 128) |
| 5215 | return OPERAND_OUT_OF_RANGE; |
| 5216 | } |
| 5217 | break; |
| 5218 | |
| 5219 | /* indirect operands: */ |
| 5220 | case IA64_OPND_CPUID_R3: |
| 5221 | case IA64_OPND_DBR_R3: |
| 5222 | case IA64_OPND_DTR_R3: |
| 5223 | case IA64_OPND_ITR_R3: |
| 5224 | case IA64_OPND_IBR_R3: |
| 5225 | case IA64_OPND_MSR_R3: |
| 5226 | case IA64_OPND_PKR_R3: |
| 5227 | case IA64_OPND_PMC_R3: |
| 5228 | case IA64_OPND_PMD_R3: |
| 5229 | case IA64_OPND_RR_R3: |
| 5230 | if (e->X_op == O_index && e->X_op_symbol |
| 5231 | && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID |
| 5232 | == opnd - IA64_OPND_CPUID_R3)) |
| 5233 | return OPERAND_MATCH; |
| 5234 | break; |
| 5235 | |
| 5236 | case IA64_OPND_MR3: |
| 5237 | if (e->X_op == O_index && !e->X_op_symbol) |
| 5238 | return OPERAND_MATCH; |
| 5239 | break; |
| 5240 | |
| 5241 | /* immediate operands: */ |
| 5242 | case IA64_OPND_CNT2a: |
| 5243 | case IA64_OPND_LEN4: |
| 5244 | case IA64_OPND_LEN6: |
| 5245 | bits = operand_width (idesc->operands[index]); |
| 5246 | if (e->X_op == O_constant) |
| 5247 | { |
| 5248 | if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) |
| 5249 | return OPERAND_MATCH; |
| 5250 | else |
| 5251 | return OPERAND_OUT_OF_RANGE; |
| 5252 | } |
| 5253 | break; |
| 5254 | |
| 5255 | case IA64_OPND_CNT2b: |
| 5256 | if (e->X_op == O_constant) |
| 5257 | { |
| 5258 | if ((bfd_vma) (e->X_add_number - 1) < 3) |
| 5259 | return OPERAND_MATCH; |
| 5260 | else |
| 5261 | return OPERAND_OUT_OF_RANGE; |
| 5262 | } |
| 5263 | break; |
| 5264 | |
| 5265 | case IA64_OPND_CNT2c: |
| 5266 | val = e->X_add_number; |
| 5267 | if (e->X_op == O_constant) |
| 5268 | { |
| 5269 | if ((val == 0 || val == 7 || val == 15 || val == 16)) |
| 5270 | return OPERAND_MATCH; |
| 5271 | else |
| 5272 | return OPERAND_OUT_OF_RANGE; |
| 5273 | } |
| 5274 | break; |
| 5275 | |
| 5276 | case IA64_OPND_SOR: |
| 5277 | /* SOR must be an integer multiple of 8 */ |
| 5278 | if (e->X_op == O_constant && e->X_add_number & 0x7) |
| 5279 | return OPERAND_OUT_OF_RANGE; |
| 5280 | case IA64_OPND_SOF: |
| 5281 | case IA64_OPND_SOL: |
| 5282 | if (e->X_op == O_constant) |
| 5283 | { |
| 5284 | if ((bfd_vma) e->X_add_number <= 96) |
| 5285 | return OPERAND_MATCH; |
| 5286 | else |
| 5287 | return OPERAND_OUT_OF_RANGE; |
| 5288 | } |
| 5289 | break; |
| 5290 | |
| 5291 | case IA64_OPND_IMMU62: |
| 5292 | if (e->X_op == O_constant) |
| 5293 | { |
| 5294 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) |
| 5295 | return OPERAND_MATCH; |
| 5296 | else |
| 5297 | return OPERAND_OUT_OF_RANGE; |
| 5298 | } |
| 5299 | else |
| 5300 | { |
| 5301 | /* FIXME -- need 62-bit relocation type */ |
| 5302 | as_bad (_("62-bit relocation not yet implemented")); |
| 5303 | } |
| 5304 | break; |
| 5305 | |
| 5306 | case IA64_OPND_IMMU64: |
| 5307 | if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup |
| 5308 | || e->X_op == O_subtract) |
| 5309 | { |
| 5310 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; |
| 5311 | fix->code = BFD_RELOC_IA64_IMM64; |
| 5312 | if (e->X_op != O_subtract) |
| 5313 | { |
| 5314 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
| 5315 | if (e->X_op == O_pseudo_fixup) |
| 5316 | e->X_op = O_symbol; |
| 5317 | } |
| 5318 | |
| 5319 | fix->opnd = idesc->operands[index]; |
| 5320 | fix->expr = *e; |
| 5321 | fix->is_pcrel = 0; |
| 5322 | ++CURR_SLOT.num_fixups; |
| 5323 | return OPERAND_MATCH; |
| 5324 | } |
| 5325 | else if (e->X_op == O_constant) |
| 5326 | return OPERAND_MATCH; |
| 5327 | break; |
| 5328 | |
| 5329 | case IA64_OPND_CCNT5: |
| 5330 | case IA64_OPND_CNT5: |
| 5331 | case IA64_OPND_CNT6: |
| 5332 | case IA64_OPND_CPOS6a: |
| 5333 | case IA64_OPND_CPOS6b: |
| 5334 | case IA64_OPND_CPOS6c: |
| 5335 | case IA64_OPND_IMMU2: |
| 5336 | case IA64_OPND_IMMU7a: |
| 5337 | case IA64_OPND_IMMU7b: |
| 5338 | case IA64_OPND_IMMU21: |
| 5339 | case IA64_OPND_IMMU24: |
| 5340 | case IA64_OPND_MBTYPE4: |
| 5341 | case IA64_OPND_MHTYPE8: |
| 5342 | case IA64_OPND_POS6: |
| 5343 | bits = operand_width (idesc->operands[index]); |
| 5344 | if (e->X_op == O_constant) |
| 5345 | { |
| 5346 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) |
| 5347 | return OPERAND_MATCH; |
| 5348 | else |
| 5349 | return OPERAND_OUT_OF_RANGE; |
| 5350 | } |
| 5351 | break; |
| 5352 | |
| 5353 | case IA64_OPND_IMMU9: |
| 5354 | bits = operand_width (idesc->operands[index]); |
| 5355 | if (e->X_op == O_constant) |
| 5356 | { |
| 5357 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) |
| 5358 | { |
| 5359 | int lobits = e->X_add_number & 0x3; |
| 5360 | if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) |
| 5361 | e->X_add_number |= (bfd_vma) 0x3; |
| 5362 | return OPERAND_MATCH; |
| 5363 | } |
| 5364 | else |
| 5365 | return OPERAND_OUT_OF_RANGE; |
| 5366 | } |
| 5367 | break; |
| 5368 | |
| 5369 | case IA64_OPND_IMM44: |
| 5370 | /* least 16 bits must be zero */ |
| 5371 | if ((e->X_add_number & 0xffff) != 0) |
| 5372 | /* XXX technically, this is wrong: we should not be issuing warning |
| 5373 | messages until we're sure this instruction pattern is going to |
| 5374 | be used! */ |
| 5375 | as_warn (_("lower 16 bits of mask ignored")); |
| 5376 | |
| 5377 | if (e->X_op == O_constant) |
| 5378 | { |
| 5379 | if (((e->X_add_number >= 0 |
| 5380 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) |
| 5381 | || (e->X_add_number < 0 |
| 5382 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) |
| 5383 | { |
| 5384 | /* sign-extend */ |
| 5385 | if (e->X_add_number >= 0 |
| 5386 | && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) |
| 5387 | { |
| 5388 | e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); |
| 5389 | } |
| 5390 | return OPERAND_MATCH; |
| 5391 | } |
| 5392 | else |
| 5393 | return OPERAND_OUT_OF_RANGE; |
| 5394 | } |
| 5395 | break; |
| 5396 | |
| 5397 | case IA64_OPND_IMM17: |
| 5398 | /* bit 0 is a don't care (pr0 is hardwired to 1) */ |
| 5399 | if (e->X_op == O_constant) |
| 5400 | { |
| 5401 | if (((e->X_add_number >= 0 |
| 5402 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) |
| 5403 | || (e->X_add_number < 0 |
| 5404 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) |
| 5405 | { |
| 5406 | /* sign-extend */ |
| 5407 | if (e->X_add_number >= 0 |
| 5408 | && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) |
| 5409 | { |
| 5410 | e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); |
| 5411 | } |
| 5412 | return OPERAND_MATCH; |
| 5413 | } |
| 5414 | else |
| 5415 | return OPERAND_OUT_OF_RANGE; |
| 5416 | } |
| 5417 | break; |
| 5418 | |
| 5419 | case IA64_OPND_IMM14: |
| 5420 | case IA64_OPND_IMM22: |
| 5421 | relocatable = 1; |
| 5422 | case IA64_OPND_IMM1: |
| 5423 | case IA64_OPND_IMM8: |
| 5424 | case IA64_OPND_IMM8U4: |
| 5425 | case IA64_OPND_IMM8M1: |
| 5426 | case IA64_OPND_IMM8M1U4: |
| 5427 | case IA64_OPND_IMM8M1U8: |
| 5428 | case IA64_OPND_IMM9a: |
| 5429 | case IA64_OPND_IMM9b: |
| 5430 | bits = operand_width (idesc->operands[index]); |
| 5431 | if (relocatable && (e->X_op == O_symbol |
| 5432 | || e->X_op == O_subtract |
| 5433 | || e->X_op == O_pseudo_fixup)) |
| 5434 | { |
| 5435 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; |
| 5436 | |
| 5437 | if (idesc->operands[index] == IA64_OPND_IMM14) |
| 5438 | fix->code = BFD_RELOC_IA64_IMM14; |
| 5439 | else |
| 5440 | fix->code = BFD_RELOC_IA64_IMM22; |
| 5441 | |
| 5442 | if (e->X_op != O_subtract) |
| 5443 | { |
| 5444 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
| 5445 | if (e->X_op == O_pseudo_fixup) |
| 5446 | e->X_op = O_symbol; |
| 5447 | } |
| 5448 | |
| 5449 | fix->opnd = idesc->operands[index]; |
| 5450 | fix->expr = *e; |
| 5451 | fix->is_pcrel = 0; |
| 5452 | ++CURR_SLOT.num_fixups; |
| 5453 | return OPERAND_MATCH; |
| 5454 | } |
| 5455 | else if (e->X_op != O_constant |
| 5456 | && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) |
| 5457 | return OPERAND_MISMATCH; |
| 5458 | |
| 5459 | if (opnd == IA64_OPND_IMM8M1U4) |
| 5460 | { |
| 5461 | /* Zero is not valid for unsigned compares that take an adjusted |
| 5462 | constant immediate range. */ |
| 5463 | if (e->X_add_number == 0) |
| 5464 | return OPERAND_OUT_OF_RANGE; |
| 5465 | |
| 5466 | /* Sign-extend 32-bit unsigned numbers, so that the following range |
| 5467 | checks will work. */ |
| 5468 | val = e->X_add_number; |
| 5469 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
| 5470 | && ((val & ((bfd_vma) 1 << 31)) != 0)) |
| 5471 | val = ((val << 32) >> 32); |
| 5472 | |
| 5473 | /* Check for 0x100000000. This is valid because |
| 5474 | 0x100000000-1 is the same as ((uint32_t) -1). */ |
| 5475 | if (val == ((bfd_signed_vma) 1 << 32)) |
| 5476 | return OPERAND_MATCH; |
| 5477 | |
| 5478 | val = val - 1; |
| 5479 | } |
| 5480 | else if (opnd == IA64_OPND_IMM8M1U8) |
| 5481 | { |
| 5482 | /* Zero is not valid for unsigned compares that take an adjusted |
| 5483 | constant immediate range. */ |
| 5484 | if (e->X_add_number == 0) |
| 5485 | return OPERAND_OUT_OF_RANGE; |
| 5486 | |
| 5487 | /* Check for 0x10000000000000000. */ |
| 5488 | if (e->X_op == O_big) |
| 5489 | { |
| 5490 | if (generic_bignum[0] == 0 |
| 5491 | && generic_bignum[1] == 0 |
| 5492 | && generic_bignum[2] == 0 |
| 5493 | && generic_bignum[3] == 0 |
| 5494 | && generic_bignum[4] == 1) |
| 5495 | return OPERAND_MATCH; |
| 5496 | else |
| 5497 | return OPERAND_OUT_OF_RANGE; |
| 5498 | } |
| 5499 | else |
| 5500 | val = e->X_add_number - 1; |
| 5501 | } |
| 5502 | else if (opnd == IA64_OPND_IMM8M1) |
| 5503 | val = e->X_add_number - 1; |
| 5504 | else if (opnd == IA64_OPND_IMM8U4) |
| 5505 | { |
| 5506 | /* Sign-extend 32-bit unsigned numbers, so that the following range |
| 5507 | checks will work. */ |
| 5508 | val = e->X_add_number; |
| 5509 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
| 5510 | && ((val & ((bfd_vma) 1 << 31)) != 0)) |
| 5511 | val = ((val << 32) >> 32); |
| 5512 | } |
| 5513 | else |
| 5514 | val = e->X_add_number; |
| 5515 | |
| 5516 | if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) |
| 5517 | || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) |
| 5518 | return OPERAND_MATCH; |
| 5519 | else |
| 5520 | return OPERAND_OUT_OF_RANGE; |
| 5521 | |
| 5522 | case IA64_OPND_INC3: |
| 5523 | /* +/- 1, 4, 8, 16 */ |
| 5524 | val = e->X_add_number; |
| 5525 | if (val < 0) |
| 5526 | val = -val; |
| 5527 | if (e->X_op == O_constant) |
| 5528 | { |
| 5529 | if ((val == 1 || val == 4 || val == 8 || val == 16)) |
| 5530 | return OPERAND_MATCH; |
| 5531 | else |
| 5532 | return OPERAND_OUT_OF_RANGE; |
| 5533 | } |
| 5534 | break; |
| 5535 | |
| 5536 | case IA64_OPND_TGT25: |
| 5537 | case IA64_OPND_TGT25b: |
| 5538 | case IA64_OPND_TGT25c: |
| 5539 | case IA64_OPND_TGT64: |
| 5540 | if (e->X_op == O_symbol) |
| 5541 | { |
| 5542 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; |
| 5543 | if (opnd == IA64_OPND_TGT25) |
| 5544 | fix->code = BFD_RELOC_IA64_PCREL21F; |
| 5545 | else if (opnd == IA64_OPND_TGT25b) |
| 5546 | fix->code = BFD_RELOC_IA64_PCREL21M; |
| 5547 | else if (opnd == IA64_OPND_TGT25c) |
| 5548 | fix->code = BFD_RELOC_IA64_PCREL21B; |
| 5549 | else if (opnd == IA64_OPND_TGT64) |
| 5550 | fix->code = BFD_RELOC_IA64_PCREL60B; |
| 5551 | else |
| 5552 | abort (); |
| 5553 | |
| 5554 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
| 5555 | fix->opnd = idesc->operands[index]; |
| 5556 | fix->expr = *e; |
| 5557 | fix->is_pcrel = 1; |
| 5558 | ++CURR_SLOT.num_fixups; |
| 5559 | return OPERAND_MATCH; |
| 5560 | } |
| 5561 | case IA64_OPND_TAG13: |
| 5562 | case IA64_OPND_TAG13b: |
| 5563 | switch (e->X_op) |
| 5564 | { |
| 5565 | case O_constant: |
| 5566 | return OPERAND_MATCH; |
| 5567 | |
| 5568 | case O_symbol: |
| 5569 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; |
| 5570 | /* There are no external relocs for TAG13/TAG13b fields, so we |
| 5571 | create a dummy reloc. This will not live past md_apply_fix3. */ |
| 5572 | fix->code = BFD_RELOC_UNUSED; |
| 5573 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
| 5574 | fix->opnd = idesc->operands[index]; |
| 5575 | fix->expr = *e; |
| 5576 | fix->is_pcrel = 1; |
| 5577 | ++CURR_SLOT.num_fixups; |
| 5578 | return OPERAND_MATCH; |
| 5579 | |
| 5580 | default: |
| 5581 | break; |
| 5582 | } |
| 5583 | break; |
| 5584 | |
| 5585 | case IA64_OPND_LDXMOV: |
| 5586 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; |
| 5587 | fix->code = BFD_RELOC_IA64_LDXMOV; |
| 5588 | fix->opnd = idesc->operands[index]; |
| 5589 | fix->expr = *e; |
| 5590 | fix->is_pcrel = 0; |
| 5591 | ++CURR_SLOT.num_fixups; |
| 5592 | return OPERAND_MATCH; |
| 5593 | |
| 5594 | default: |
| 5595 | break; |
| 5596 | } |
| 5597 | return OPERAND_MISMATCH; |
| 5598 | } |
| 5599 | |
| 5600 | static int |
| 5601 | parse_operand (e) |
| 5602 | expressionS *e; |
| 5603 | { |
| 5604 | int sep = '\0'; |
| 5605 | |
| 5606 | memset (e, 0, sizeof (*e)); |
| 5607 | e->X_op = O_absent; |
| 5608 | SKIP_WHITESPACE (); |
| 5609 | if (*input_line_pointer != '}') |
| 5610 | expression (e); |
| 5611 | sep = *input_line_pointer++; |
| 5612 | |
| 5613 | if (sep == '}') |
| 5614 | { |
| 5615 | if (!md.manual_bundling) |
| 5616 | as_warn ("Found '}' when manual bundling is off"); |
| 5617 | else |
| 5618 | CURR_SLOT.manual_bundling_off = 1; |
| 5619 | md.manual_bundling = 0; |
| 5620 | sep = '\0'; |
| 5621 | } |
| 5622 | return sep; |
| 5623 | } |
| 5624 | |
| 5625 | /* Returns the next entry in the opcode table that matches the one in |
| 5626 | IDESC, and frees the entry in IDESC. If no matching entry is |
| 5627 | found, NULL is returned instead. */ |
| 5628 | |
| 5629 | static struct ia64_opcode * |
| 5630 | get_next_opcode (struct ia64_opcode *idesc) |
| 5631 | { |
| 5632 | struct ia64_opcode *next = ia64_find_next_opcode (idesc); |
| 5633 | ia64_free_opcode (idesc); |
| 5634 | return next; |
| 5635 | } |
| 5636 | |
| 5637 | /* Parse the operands for the opcode and find the opcode variant that |
| 5638 | matches the specified operands, or NULL if no match is possible. */ |
| 5639 | |
| 5640 | static struct ia64_opcode * |
| 5641 | parse_operands (idesc) |
| 5642 | struct ia64_opcode *idesc; |
| 5643 | { |
| 5644 | int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; |
| 5645 | int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0; |
| 5646 | enum ia64_opnd expected_operand = IA64_OPND_NIL; |
| 5647 | enum operand_match_result result; |
| 5648 | char mnemonic[129]; |
| 5649 | char *first_arg = 0, *end, *saved_input_pointer; |
| 5650 | unsigned int sof; |
| 5651 | |
| 5652 | assert (strlen (idesc->name) <= 128); |
| 5653 | |
| 5654 | strcpy (mnemonic, idesc->name); |
| 5655 | if (idesc->operands[2] == IA64_OPND_SOF) |
| 5656 | { |
| 5657 | /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we |
| 5658 | can't parse the first operand until we have parsed the |
| 5659 | remaining operands of the "alloc" instruction. */ |
| 5660 | SKIP_WHITESPACE (); |
| 5661 | first_arg = input_line_pointer; |
| 5662 | end = strchr (input_line_pointer, '='); |
| 5663 | if (!end) |
| 5664 | { |
| 5665 | as_bad ("Expected separator `='"); |
| 5666 | return 0; |
| 5667 | } |
| 5668 | input_line_pointer = end + 1; |
| 5669 | ++i; |
| 5670 | ++num_outputs; |
| 5671 | } |
| 5672 | |
| 5673 | for (; i < NELEMS (CURR_SLOT.opnd); ++i) |
| 5674 | { |
| 5675 | sep = parse_operand (CURR_SLOT.opnd + i); |
| 5676 | if (CURR_SLOT.opnd[i].X_op == O_absent) |
| 5677 | break; |
| 5678 | |
| 5679 | ++num_operands; |
| 5680 | |
| 5681 | if (sep != '=' && sep != ',') |
| 5682 | break; |
| 5683 | |
| 5684 | if (sep == '=') |
| 5685 | { |
| 5686 | if (num_outputs > 0) |
| 5687 | as_bad ("Duplicate equal sign (=) in instruction"); |
| 5688 | else |
| 5689 | num_outputs = i + 1; |
| 5690 | } |
| 5691 | } |
| 5692 | if (sep != '\0') |
| 5693 | { |
| 5694 | as_bad ("Illegal operand separator `%c'", sep); |
| 5695 | return 0; |
| 5696 | } |
| 5697 | |
| 5698 | if (idesc->operands[2] == IA64_OPND_SOF) |
| 5699 | { |
| 5700 | /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ |
| 5701 | know (strcmp (idesc->name, "alloc") == 0); |
| 5702 | if (num_operands == 5 /* first_arg not included in this count! */ |
| 5703 | && CURR_SLOT.opnd[2].X_op == O_constant |
| 5704 | && CURR_SLOT.opnd[3].X_op == O_constant |
| 5705 | && CURR_SLOT.opnd[4].X_op == O_constant |
| 5706 | && CURR_SLOT.opnd[5].X_op == O_constant) |
| 5707 | { |
| 5708 | sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, |
| 5709 | CURR_SLOT.opnd[3].X_add_number, |
| 5710 | CURR_SLOT.opnd[4].X_add_number, |
| 5711 | CURR_SLOT.opnd[5].X_add_number); |
| 5712 | |
| 5713 | /* now we can parse the first arg: */ |
| 5714 | saved_input_pointer = input_line_pointer; |
| 5715 | input_line_pointer = first_arg; |
| 5716 | sep = parse_operand (CURR_SLOT.opnd + 0); |
| 5717 | if (sep != '=') |
| 5718 | --num_outputs; /* force error */ |
| 5719 | input_line_pointer = saved_input_pointer; |
| 5720 | |
| 5721 | CURR_SLOT.opnd[2].X_add_number = sof; |
| 5722 | CURR_SLOT.opnd[3].X_add_number |
| 5723 | = sof - CURR_SLOT.opnd[4].X_add_number; |
| 5724 | CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; |
| 5725 | } |
| 5726 | } |
| 5727 | |
| 5728 | highest_unmatched_operand = 0; |
| 5729 | curr_out_of_range_pos = -1; |
| 5730 | error_pos = 0; |
| 5731 | expected_operand = idesc->operands[0]; |
| 5732 | for (; idesc; idesc = get_next_opcode (idesc)) |
| 5733 | { |
| 5734 | if (num_outputs != idesc->num_outputs) |
| 5735 | continue; /* mismatch in # of outputs */ |
| 5736 | |
| 5737 | CURR_SLOT.num_fixups = 0; |
| 5738 | |
| 5739 | /* Try to match all operands. If we see an out-of-range operand, |
| 5740 | then continue trying to match the rest of the operands, since if |
| 5741 | the rest match, then this idesc will give the best error message. */ |
| 5742 | |
| 5743 | out_of_range_pos = -1; |
| 5744 | for (i = 0; i < num_operands && idesc->operands[i]; ++i) |
| 5745 | { |
| 5746 | result = operand_match (idesc, i, CURR_SLOT.opnd + i); |
| 5747 | if (result != OPERAND_MATCH) |
| 5748 | { |
| 5749 | if (result != OPERAND_OUT_OF_RANGE) |
| 5750 | break; |
| 5751 | if (out_of_range_pos < 0) |
| 5752 | /* remember position of the first out-of-range operand: */ |
| 5753 | out_of_range_pos = i; |
| 5754 | } |
| 5755 | } |
| 5756 | |
| 5757 | /* If we did not match all operands, or if at least one operand was |
| 5758 | out-of-range, then this idesc does not match. Keep track of which |
| 5759 | idesc matched the most operands before failing. If we have two |
| 5760 | idescs that failed at the same position, and one had an out-of-range |
| 5761 | operand, then prefer the out-of-range operand. Thus if we have |
| 5762 | "add r0=0x1000000,r1" we get an error saying the constant is out |
| 5763 | of range instead of an error saying that the constant should have been |
| 5764 | a register. */ |
| 5765 | |
| 5766 | if (i != num_operands || out_of_range_pos >= 0) |
| 5767 | { |
| 5768 | if (i > highest_unmatched_operand |
| 5769 | || (i == highest_unmatched_operand |
| 5770 | && out_of_range_pos > curr_out_of_range_pos)) |
| 5771 | { |
| 5772 | highest_unmatched_operand = i; |
| 5773 | if (out_of_range_pos >= 0) |
| 5774 | { |
| 5775 | expected_operand = idesc->operands[out_of_range_pos]; |
| 5776 | error_pos = out_of_range_pos; |
| 5777 | } |
| 5778 | else |
| 5779 | { |
| 5780 | expected_operand = idesc->operands[i]; |
| 5781 | error_pos = i; |
| 5782 | } |
| 5783 | curr_out_of_range_pos = out_of_range_pos; |
| 5784 | } |
| 5785 | continue; |
| 5786 | } |
| 5787 | |
| 5788 | if (num_operands < NELEMS (idesc->operands) |
| 5789 | && idesc->operands[num_operands]) |
| 5790 | continue; /* mismatch in number of arguments */ |
| 5791 | |
| 5792 | break; |
| 5793 | } |
| 5794 | if (!idesc) |
| 5795 | { |
| 5796 | if (expected_operand) |
| 5797 | as_bad ("Operand %u of `%s' should be %s", |
| 5798 | error_pos + 1, mnemonic, |
| 5799 | elf64_ia64_operands[expected_operand].desc); |
| 5800 | else |
| 5801 | as_bad ("Operand mismatch"); |
| 5802 | return 0; |
| 5803 | } |
| 5804 | return idesc; |
| 5805 | } |
| 5806 | |
| 5807 | /* Keep track of state necessary to determine whether a NOP is necessary |
| 5808 | to avoid an erratum in A and B step Itanium chips, and return 1 if we |
| 5809 | detect a case where additional NOPs may be necessary. */ |
| 5810 | static int |
| 5811 | errata_nop_necessary_p (slot, insn_unit) |
| 5812 | struct slot *slot; |
| 5813 | enum ia64_unit insn_unit; |
| 5814 | { |
| 5815 | int i; |
| 5816 | struct group *this_group = md.last_groups + md.group_idx; |
| 5817 | struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3; |
| 5818 | struct ia64_opcode *idesc = slot->idesc; |
| 5819 | |
| 5820 | /* Test whether this could be the first insn in a problematic sequence. */ |
| 5821 | if (insn_unit == IA64_UNIT_F) |
| 5822 | { |
| 5823 | for (i = 0; i < idesc->num_outputs; i++) |
| 5824 | if (idesc->operands[i] == IA64_OPND_P1 |
| 5825 | || idesc->operands[i] == IA64_OPND_P2) |
| 5826 | { |
| 5827 | int regno = slot->opnd[i].X_add_number - REG_P; |
| 5828 | /* Ignore invalid operands; they generate errors elsewhere. */ |
| 5829 | if (regno >= 64) |
| 5830 | return 0; |
| 5831 | this_group->p_reg_set[regno] = 1; |
| 5832 | } |
| 5833 | } |
| 5834 | |
| 5835 | /* Test whether this could be the second insn in a problematic sequence. */ |
| 5836 | if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0 |
| 5837 | && prev_group->p_reg_set[slot->qp_regno]) |
| 5838 | { |
| 5839 | for (i = 0; i < idesc->num_outputs; i++) |
| 5840 | if (idesc->operands[i] == IA64_OPND_R1 |
| 5841 | || idesc->operands[i] == IA64_OPND_R2 |
| 5842 | || idesc->operands[i] == IA64_OPND_R3) |
| 5843 | { |
| 5844 | int regno = slot->opnd[i].X_add_number - REG_GR; |
| 5845 | /* Ignore invalid operands; they generate errors elsewhere. */ |
| 5846 | if (regno >= 128) |
| 5847 | return 0; |
| 5848 | if (strncmp (idesc->name, "add", 3) != 0 |
| 5849 | && strncmp (idesc->name, "sub", 3) != 0 |
| 5850 | && strncmp (idesc->name, "shladd", 6) != 0 |
| 5851 | && (idesc->flags & IA64_OPCODE_POSTINC) == 0) |
| 5852 | this_group->g_reg_set_conditionally[regno] = 1; |
| 5853 | } |
| 5854 | } |
| 5855 | |
| 5856 | /* Test whether this could be the third insn in a problematic sequence. */ |
| 5857 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++) |
| 5858 | { |
| 5859 | if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */ |
| 5860 | idesc->operands[i] == IA64_OPND_R3 |
| 5861 | /* For mov indirect. */ |
| 5862 | || idesc->operands[i] == IA64_OPND_RR_R3 |
| 5863 | || idesc->operands[i] == IA64_OPND_DBR_R3 |
| 5864 | || idesc->operands[i] == IA64_OPND_IBR_R3 |
| 5865 | || idesc->operands[i] == IA64_OPND_PKR_R3 |
| 5866 | || idesc->operands[i] == IA64_OPND_PMC_R3 |
| 5867 | || idesc->operands[i] == IA64_OPND_PMD_R3 |
| 5868 | || idesc->operands[i] == IA64_OPND_MSR_R3 |
| 5869 | || idesc->operands[i] == IA64_OPND_CPUID_R3 |
| 5870 | /* For itr. */ |
| 5871 | || idesc->operands[i] == IA64_OPND_ITR_R3 |
| 5872 | || idesc->operands[i] == IA64_OPND_DTR_R3 |
| 5873 | /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */ |
| 5874 | || idesc->operands[i] == IA64_OPND_MR3) |
| 5875 | { |
| 5876 | int regno = slot->opnd[i].X_add_number - REG_GR; |
| 5877 | /* Ignore invalid operands; they generate errors elsewhere. */ |
| 5878 | if (regno >= 128) |
| 5879 | return 0; |
| 5880 | if (idesc->operands[i] == IA64_OPND_R3) |
| 5881 | { |
| 5882 | if (strcmp (idesc->name, "fc") != 0 |
| 5883 | && strcmp (idesc->name, "tak") != 0 |
| 5884 | && strcmp (idesc->name, "thash") != 0 |
| 5885 | && strcmp (idesc->name, "tpa") != 0 |
| 5886 | && strcmp (idesc->name, "ttag") != 0 |
| 5887 | && strncmp (idesc->name, "ptr", 3) != 0 |
| 5888 | && strncmp (idesc->name, "ptc", 3) != 0 |
| 5889 | && strncmp (idesc->name, "probe", 5) != 0) |
| 5890 | return 0; |
| 5891 | } |
| 5892 | if (prev_group->g_reg_set_conditionally[regno]) |
| 5893 | return 1; |
| 5894 | } |
| 5895 | } |
| 5896 | return 0; |
| 5897 | } |
| 5898 | |
| 5899 | static void |
| 5900 | build_insn (slot, insnp) |
| 5901 | struct slot *slot; |
| 5902 | bfd_vma *insnp; |
| 5903 | { |
| 5904 | const struct ia64_operand *odesc, *o2desc; |
| 5905 | struct ia64_opcode *idesc = slot->idesc; |
| 5906 | bfd_signed_vma insn, val; |
| 5907 | const char *err; |
| 5908 | int i; |
| 5909 | |
| 5910 | insn = idesc->opcode | slot->qp_regno; |
| 5911 | |
| 5912 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) |
| 5913 | { |
| 5914 | if (slot->opnd[i].X_op == O_register |
| 5915 | || slot->opnd[i].X_op == O_constant |
| 5916 | || slot->opnd[i].X_op == O_index) |
| 5917 | val = slot->opnd[i].X_add_number; |
| 5918 | else if (slot->opnd[i].X_op == O_big) |
| 5919 | { |
| 5920 | /* This must be the value 0x10000000000000000. */ |
| 5921 | assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); |
| 5922 | val = 0; |
| 5923 | } |
| 5924 | else |
| 5925 | val = 0; |
| 5926 | |
| 5927 | switch (idesc->operands[i]) |
| 5928 | { |
| 5929 | case IA64_OPND_IMMU64: |
| 5930 | *insnp++ = (val >> 22) & 0x1ffffffffffLL; |
| 5931 | insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) |
| 5932 | | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) |
| 5933 | | (((val >> 63) & 0x1) << 36)); |
| 5934 | continue; |
| 5935 | |
| 5936 | case IA64_OPND_IMMU62: |
| 5937 | val &= 0x3fffffffffffffffULL; |
| 5938 | if (val != slot->opnd[i].X_add_number) |
| 5939 | as_warn (_("Value truncated to 62 bits")); |
| 5940 | *insnp++ = (val >> 21) & 0x1ffffffffffLL; |
| 5941 | insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); |
| 5942 | continue; |
| 5943 | |
| 5944 | case IA64_OPND_TGT64: |
| 5945 | val >>= 4; |
| 5946 | *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; |
| 5947 | insn |= ((((val >> 59) & 0x1) << 36) |
| 5948 | | (((val >> 0) & 0xfffff) << 13)); |
| 5949 | continue; |
| 5950 | |
| 5951 | case IA64_OPND_AR3: |
| 5952 | val -= REG_AR; |
| 5953 | break; |
| 5954 | |
| 5955 | case IA64_OPND_B1: |
| 5956 | case IA64_OPND_B2: |
| 5957 | val -= REG_BR; |
| 5958 | break; |
| 5959 | |
| 5960 | case IA64_OPND_CR3: |
| 5961 | val -= REG_CR; |
| 5962 | break; |
| 5963 | |
| 5964 | case IA64_OPND_F1: |
| 5965 | case IA64_OPND_F2: |
| 5966 | case IA64_OPND_F3: |
| 5967 | case IA64_OPND_F4: |
| 5968 | val -= REG_FR; |
| 5969 | break; |
| 5970 | |
| 5971 | case IA64_OPND_P1: |
| 5972 | case IA64_OPND_P2: |
| 5973 | val -= REG_P; |
| 5974 | break; |
| 5975 | |
| 5976 | case IA64_OPND_R1: |
| 5977 | case IA64_OPND_R2: |
| 5978 | case IA64_OPND_R3: |
| 5979 | case IA64_OPND_R3_2: |
| 5980 | case IA64_OPND_CPUID_R3: |
| 5981 | case IA64_OPND_DBR_R3: |
| 5982 | case IA64_OPND_DTR_R3: |
| 5983 | case IA64_OPND_ITR_R3: |
| 5984 | case IA64_OPND_IBR_R3: |
| 5985 | case IA64_OPND_MR3: |
| 5986 | case IA64_OPND_MSR_R3: |
| 5987 | case IA64_OPND_PKR_R3: |
| 5988 | case IA64_OPND_PMC_R3: |
| 5989 | case IA64_OPND_PMD_R3: |
| 5990 | case IA64_OPND_RR_R3: |
| 5991 | val -= REG_GR; |
| 5992 | break; |
| 5993 | |
| 5994 | default: |
| 5995 | break; |
| 5996 | } |
| 5997 | |
| 5998 | odesc = elf64_ia64_operands + idesc->operands[i]; |
| 5999 | err = (*odesc->insert) (odesc, val, &insn); |
| 6000 | if (err) |
| 6001 | as_bad_where (slot->src_file, slot->src_line, |
| 6002 | "Bad operand value: %s", err); |
| 6003 | if (idesc->flags & IA64_OPCODE_PSEUDO) |
| 6004 | { |
| 6005 | if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) |
| 6006 | && odesc == elf64_ia64_operands + IA64_OPND_F3) |
| 6007 | { |
| 6008 | o2desc = elf64_ia64_operands + IA64_OPND_F2; |
| 6009 | (*o2desc->insert) (o2desc, val, &insn); |
| 6010 | } |
| 6011 | if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) |
| 6012 | && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a |
| 6013 | || odesc == elf64_ia64_operands + IA64_OPND_POS6)) |
| 6014 | { |
| 6015 | o2desc = elf64_ia64_operands + IA64_OPND_LEN6; |
| 6016 | (*o2desc->insert) (o2desc, 64 - val, &insn); |
| 6017 | } |
| 6018 | } |
| 6019 | } |
| 6020 | *insnp = insn; |
| 6021 | } |
| 6022 | |
| 6023 | static void |
| 6024 | emit_one_bundle () |
| 6025 | { |
| 6026 | unsigned int manual_bundling_on = 0, manual_bundling_off = 0; |
| 6027 | unsigned int manual_bundling = 0; |
| 6028 | enum ia64_unit required_unit, insn_unit = 0; |
| 6029 | enum ia64_insn_type type[3], insn_type; |
| 6030 | unsigned int template, orig_template; |
| 6031 | bfd_vma insn[3] = { -1, -1, -1 }; |
| 6032 | struct ia64_opcode *idesc; |
| 6033 | int end_of_insn_group = 0, user_template = -1; |
| 6034 | int n, i, j, first, curr; |
| 6035 | unw_rec_list *ptr; |
| 6036 | bfd_vma t0 = 0, t1 = 0; |
| 6037 | struct label_fix *lfix; |
| 6038 | struct insn_fix *ifix; |
| 6039 | char mnemonic[16]; |
| 6040 | fixS *fix; |
| 6041 | char *f; |
| 6042 | |
| 6043 | first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; |
| 6044 | know (first >= 0 & first < NUM_SLOTS); |
| 6045 | n = MIN (3, md.num_slots_in_use); |
| 6046 | |
| 6047 | /* Determine template: user user_template if specified, best match |
| 6048 | otherwise: */ |
| 6049 | |
| 6050 | if (md.slot[first].user_template >= 0) |
| 6051 | user_template = template = md.slot[first].user_template; |
| 6052 | else |
| 6053 | { |
| 6054 | /* Auto select appropriate template. */ |
| 6055 | memset (type, 0, sizeof (type)); |
| 6056 | curr = first; |
| 6057 | for (i = 0; i < n; ++i) |
| 6058 | { |
| 6059 | if (md.slot[curr].label_fixups && i != 0) |
| 6060 | break; |
| 6061 | type[i] = md.slot[curr].idesc->type; |
| 6062 | curr = (curr + 1) % NUM_SLOTS; |
| 6063 | } |
| 6064 | template = best_template[type[0]][type[1]][type[2]]; |
| 6065 | } |
| 6066 | |
| 6067 | /* initialize instructions with appropriate nops: */ |
| 6068 | for (i = 0; i < 3; ++i) |
| 6069 | insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; |
| 6070 | |
| 6071 | f = frag_more (16); |
| 6072 | |
| 6073 | /* now fill in slots with as many insns as possible: */ |
| 6074 | curr = first; |
| 6075 | idesc = md.slot[curr].idesc; |
| 6076 | end_of_insn_group = 0; |
| 6077 | for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) |
| 6078 | { |
| 6079 | /* Set the slot number for prologue/body records now as those |
| 6080 | refer to the current point, not the point after the |
| 6081 | instruction has been issued: */ |
| 6082 | /* Don't try to delete prologue/body records here, as that will cause |
| 6083 | them to also be deleted from the master list of unwind records. */ |
| 6084 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) |
| 6085 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr |
| 6086 | || ptr->r.type == body) |
| 6087 | { |
| 6088 | ptr->slot_number = (unsigned long) f + i; |
| 6089 | ptr->slot_frag = frag_now; |
| 6090 | } |
| 6091 | |
| 6092 | if (idesc->flags & IA64_OPCODE_SLOT2) |
| 6093 | { |
| 6094 | if (manual_bundling && i != 2) |
| 6095 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 6096 | "`%s' must be last in bundle", idesc->name); |
| 6097 | else |
| 6098 | i = 2; |
| 6099 | } |
| 6100 | if (idesc->flags & IA64_OPCODE_LAST) |
| 6101 | { |
| 6102 | int required_slot; |
| 6103 | unsigned int required_template; |
| 6104 | |
| 6105 | /* If we need a stop bit after an M slot, our only choice is |
| 6106 | template 5 (M;;MI). If we need a stop bit after a B |
| 6107 | slot, our only choice is to place it at the end of the |
| 6108 | bundle, because the only available templates are MIB, |
| 6109 | MBB, BBB, MMB, and MFB. We don't handle anything other |
| 6110 | than M and B slots because these are the only kind of |
| 6111 | instructions that can have the IA64_OPCODE_LAST bit set. */ |
| 6112 | required_template = template; |
| 6113 | switch (idesc->type) |
| 6114 | { |
| 6115 | case IA64_TYPE_M: |
| 6116 | required_slot = 0; |
| 6117 | required_template = 5; |
| 6118 | break; |
| 6119 | |
| 6120 | case IA64_TYPE_B: |
| 6121 | required_slot = 2; |
| 6122 | break; |
| 6123 | |
| 6124 | default: |
| 6125 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 6126 | "Internal error: don't know how to force %s to end" |
| 6127 | "of instruction group", idesc->name); |
| 6128 | required_slot = i; |
| 6129 | break; |
| 6130 | } |
| 6131 | if (manual_bundling && i != required_slot) |
| 6132 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 6133 | "`%s' must be last in instruction group", |
| 6134 | idesc->name); |
| 6135 | if (required_slot < i) |
| 6136 | /* Can't fit this instruction. */ |
| 6137 | break; |
| 6138 | |
| 6139 | i = required_slot; |
| 6140 | if (required_template != template) |
| 6141 | { |
| 6142 | /* If we switch the template, we need to reset the NOPs |
| 6143 | after slot i. The slot-types of the instructions ahead |
| 6144 | of i never change, so we don't need to worry about |
| 6145 | changing NOPs in front of this slot. */ |
| 6146 | for (j = i; j < 3; ++j) |
| 6147 | insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; |
| 6148 | } |
| 6149 | template = required_template; |
| 6150 | } |
| 6151 | if (curr != first && md.slot[curr].label_fixups) |
| 6152 | { |
| 6153 | if (manual_bundling_on) |
| 6154 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 6155 | "Label must be first in a bundle"); |
| 6156 | /* This insn must go into the first slot of a bundle. */ |
| 6157 | break; |
| 6158 | } |
| 6159 | |
| 6160 | manual_bundling_on = md.slot[curr].manual_bundling_on; |
| 6161 | manual_bundling_off = md.slot[curr].manual_bundling_off; |
| 6162 | |
| 6163 | if (manual_bundling_on) |
| 6164 | { |
| 6165 | if (curr == first) |
| 6166 | manual_bundling = 1; |
| 6167 | else |
| 6168 | break; /* need to start a new bundle */ |
| 6169 | } |
| 6170 | |
| 6171 | if (end_of_insn_group && md.num_slots_in_use >= 1) |
| 6172 | { |
| 6173 | /* We need an instruction group boundary in the middle of a |
| 6174 | bundle. See if we can switch to an other template with |
| 6175 | an appropriate boundary. */ |
| 6176 | |
| 6177 | orig_template = template; |
| 6178 | if (i == 1 && (user_template == 4 |
| 6179 | || (user_template < 0 |
| 6180 | && (ia64_templ_desc[template].exec_unit[0] |
| 6181 | == IA64_UNIT_M)))) |
| 6182 | { |
| 6183 | template = 5; |
| 6184 | end_of_insn_group = 0; |
| 6185 | } |
| 6186 | else if (i == 2 && (user_template == 0 |
| 6187 | || (user_template < 0 |
| 6188 | && (ia64_templ_desc[template].exec_unit[1] |
| 6189 | == IA64_UNIT_I))) |
| 6190 | /* This test makes sure we don't switch the template if |
| 6191 | the next instruction is one that needs to be first in |
| 6192 | an instruction group. Since all those instructions are |
| 6193 | in the M group, there is no way such an instruction can |
| 6194 | fit in this bundle even if we switch the template. The |
| 6195 | reason we have to check for this is that otherwise we |
| 6196 | may end up generating "MI;;I M.." which has the deadly |
| 6197 | effect that the second M instruction is no longer the |
| 6198 | first in the bundle! --davidm 99/12/16 */ |
| 6199 | && (idesc->flags & IA64_OPCODE_FIRST) == 0) |
| 6200 | { |
| 6201 | template = 1; |
| 6202 | end_of_insn_group = 0; |
| 6203 | } |
| 6204 | else if (curr != first) |
| 6205 | /* can't fit this insn */ |
| 6206 | break; |
| 6207 | |
| 6208 | if (template != orig_template) |
| 6209 | /* if we switch the template, we need to reset the NOPs |
| 6210 | after slot i. The slot-types of the instructions ahead |
| 6211 | of i never change, so we don't need to worry about |
| 6212 | changing NOPs in front of this slot. */ |
| 6213 | for (j = i; j < 3; ++j) |
| 6214 | insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; |
| 6215 | } |
| 6216 | required_unit = ia64_templ_desc[template].exec_unit[i]; |
| 6217 | |
| 6218 | /* resolve dynamic opcodes such as "break", "hint", and "nop": */ |
| 6219 | if (idesc->type == IA64_TYPE_DYN) |
| 6220 | { |
| 6221 | if ((strcmp (idesc->name, "nop") == 0) |
| 6222 | || (strcmp (idesc->name, "hint") == 0) |
| 6223 | || (strcmp (idesc->name, "break") == 0)) |
| 6224 | insn_unit = required_unit; |
| 6225 | else if (strcmp (idesc->name, "chk.s") == 0) |
| 6226 | { |
| 6227 | insn_unit = IA64_UNIT_M; |
| 6228 | if (required_unit == IA64_UNIT_I) |
| 6229 | insn_unit = IA64_UNIT_I; |
| 6230 | } |
| 6231 | else |
| 6232 | as_fatal ("emit_one_bundle: unexpected dynamic op"); |
| 6233 | |
| 6234 | sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); |
| 6235 | ia64_free_opcode (idesc); |
| 6236 | md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); |
| 6237 | #if 0 |
| 6238 | know (!idesc->next); /* no resolved dynamic ops have collisions */ |
| 6239 | #endif |
| 6240 | } |
| 6241 | else |
| 6242 | { |
| 6243 | insn_type = idesc->type; |
| 6244 | insn_unit = IA64_UNIT_NIL; |
| 6245 | switch (insn_type) |
| 6246 | { |
| 6247 | case IA64_TYPE_A: |
| 6248 | if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) |
| 6249 | insn_unit = required_unit; |
| 6250 | break; |
| 6251 | case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; |
| 6252 | case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; |
| 6253 | case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; |
| 6254 | case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; |
| 6255 | case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; |
| 6256 | default: break; |
| 6257 | } |
| 6258 | } |
| 6259 | |
| 6260 | if (insn_unit != required_unit) |
| 6261 | { |
| 6262 | if (required_unit == IA64_UNIT_L |
| 6263 | && insn_unit == IA64_UNIT_I |
| 6264 | && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) |
| 6265 | { |
| 6266 | /* we got ourselves an MLX template but the current |
| 6267 | instruction isn't an X-unit, or an I-unit instruction |
| 6268 | that can go into the X slot of an MLX template. Duh. */ |
| 6269 | if (md.num_slots_in_use >= NUM_SLOTS) |
| 6270 | { |
| 6271 | as_bad_where (md.slot[curr].src_file, |
| 6272 | md.slot[curr].src_line, |
| 6273 | "`%s' can't go in X slot of " |
| 6274 | "MLX template", idesc->name); |
| 6275 | /* drop this insn so we don't livelock: */ |
| 6276 | --md.num_slots_in_use; |
| 6277 | } |
| 6278 | break; |
| 6279 | } |
| 6280 | continue; /* try next slot */ |
| 6281 | } |
| 6282 | |
| 6283 | { |
| 6284 | bfd_vma addr; |
| 6285 | |
| 6286 | addr = frag_now->fr_address + frag_now_fix () - 16 + i; |
| 6287 | dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); |
| 6288 | } |
| 6289 | |
| 6290 | if (errata_nop_necessary_p (md.slot + curr, insn_unit)) |
| 6291 | as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata")); |
| 6292 | |
| 6293 | build_insn (md.slot + curr, insn + i); |
| 6294 | |
| 6295 | /* Set slot counts for non prologue/body unwind records. */ |
| 6296 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) |
| 6297 | if (ptr->r.type != prologue && ptr->r.type != prologue_gr |
| 6298 | && ptr->r.type != body) |
| 6299 | { |
| 6300 | ptr->slot_number = (unsigned long) f + i; |
| 6301 | ptr->slot_frag = frag_now; |
| 6302 | } |
| 6303 | md.slot[curr].unwind_record = NULL; |
| 6304 | |
| 6305 | if (required_unit == IA64_UNIT_L) |
| 6306 | { |
| 6307 | know (i == 1); |
| 6308 | /* skip one slot for long/X-unit instructions */ |
| 6309 | ++i; |
| 6310 | } |
| 6311 | --md.num_slots_in_use; |
| 6312 | |
| 6313 | /* now is a good time to fix up the labels for this insn: */ |
| 6314 | for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) |
| 6315 | { |
| 6316 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16); |
| 6317 | symbol_set_frag (lfix->sym, frag_now); |
| 6318 | } |
| 6319 | /* and fix up the tags also. */ |
| 6320 | for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) |
| 6321 | { |
| 6322 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); |
| 6323 | symbol_set_frag (lfix->sym, frag_now); |
| 6324 | } |
| 6325 | |
| 6326 | for (j = 0; j < md.slot[curr].num_fixups; ++j) |
| 6327 | { |
| 6328 | ifix = md.slot[curr].fixup + j; |
| 6329 | fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, |
| 6330 | &ifix->expr, ifix->is_pcrel, ifix->code); |
| 6331 | fix->tc_fix_data.opnd = ifix->opnd; |
| 6332 | fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); |
| 6333 | fix->fx_file = md.slot[curr].src_file; |
| 6334 | fix->fx_line = md.slot[curr].src_line; |
| 6335 | } |
| 6336 | |
| 6337 | end_of_insn_group = md.slot[curr].end_of_insn_group; |
| 6338 | |
| 6339 | if (end_of_insn_group) |
| 6340 | { |
| 6341 | md.group_idx = (md.group_idx + 1) % 3; |
| 6342 | memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]); |
| 6343 | } |
| 6344 | |
| 6345 | /* clear slot: */ |
| 6346 | ia64_free_opcode (md.slot[curr].idesc); |
| 6347 | memset (md.slot + curr, 0, sizeof (md.slot[curr])); |
| 6348 | md.slot[curr].user_template = -1; |
| 6349 | |
| 6350 | if (manual_bundling_off) |
| 6351 | { |
| 6352 | manual_bundling = 0; |
| 6353 | break; |
| 6354 | } |
| 6355 | curr = (curr + 1) % NUM_SLOTS; |
| 6356 | idesc = md.slot[curr].idesc; |
| 6357 | } |
| 6358 | if (manual_bundling) |
| 6359 | { |
| 6360 | if (md.num_slots_in_use > 0) |
| 6361 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 6362 | "`%s' does not fit into %s template", |
| 6363 | idesc->name, ia64_templ_desc[template].name); |
| 6364 | else |
| 6365 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 6366 | "Missing '}' at end of file"); |
| 6367 | } |
| 6368 | know (md.num_slots_in_use < NUM_SLOTS); |
| 6369 | |
| 6370 | t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); |
| 6371 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); |
| 6372 | |
| 6373 | number_to_chars_littleendian (f + 0, t0, 8); |
| 6374 | number_to_chars_littleendian (f + 8, t1, 8); |
| 6375 | |
| 6376 | unwind.next_slot_number = (unsigned long) f + 16; |
| 6377 | unwind.next_slot_frag = frag_now; |
| 6378 | } |
| 6379 | |
| 6380 | int |
| 6381 | md_parse_option (c, arg) |
| 6382 | int c; |
| 6383 | char *arg; |
| 6384 | { |
| 6385 | |
| 6386 | switch (c) |
| 6387 | { |
| 6388 | /* Switches from the Intel assembler. */ |
| 6389 | case 'm': |
| 6390 | if (strcmp (arg, "ilp64") == 0 |
| 6391 | || strcmp (arg, "lp64") == 0 |
| 6392 | || strcmp (arg, "p64") == 0) |
| 6393 | { |
| 6394 | md.flags |= EF_IA_64_ABI64; |
| 6395 | } |
| 6396 | else if (strcmp (arg, "ilp32") == 0) |
| 6397 | { |
| 6398 | md.flags &= ~EF_IA_64_ABI64; |
| 6399 | } |
| 6400 | else if (strcmp (arg, "le") == 0) |
| 6401 | { |
| 6402 | md.flags &= ~EF_IA_64_BE; |
| 6403 | } |
| 6404 | else if (strcmp (arg, "be") == 0) |
| 6405 | { |
| 6406 | md.flags |= EF_IA_64_BE; |
| 6407 | } |
| 6408 | else |
| 6409 | return 0; |
| 6410 | break; |
| 6411 | |
| 6412 | case 'N': |
| 6413 | if (strcmp (arg, "so") == 0) |
| 6414 | { |
| 6415 | /* Suppress signon message. */ |
| 6416 | } |
| 6417 | else if (strcmp (arg, "pi") == 0) |
| 6418 | { |
| 6419 | /* Reject privileged instructions. FIXME */ |
| 6420 | } |
| 6421 | else if (strcmp (arg, "us") == 0) |
| 6422 | { |
| 6423 | /* Allow union of signed and unsigned range. FIXME */ |
| 6424 | } |
| 6425 | else if (strcmp (arg, "close_fcalls") == 0) |
| 6426 | { |
| 6427 | /* Do not resolve global function calls. */ |
| 6428 | } |
| 6429 | else |
| 6430 | return 0; |
| 6431 | break; |
| 6432 | |
| 6433 | case 'C': |
| 6434 | /* temp[="prefix"] Insert temporary labels into the object file |
| 6435 | symbol table prefixed by "prefix". |
| 6436 | Default prefix is ":temp:". |
| 6437 | */ |
| 6438 | break; |
| 6439 | |
| 6440 | case 'a': |
| 6441 | /* indirect=<tgt> Assume unannotated indirect branches behavior |
| 6442 | according to <tgt> -- |
| 6443 | exit: branch out from the current context (default) |
| 6444 | labels: all labels in context may be branch targets |
| 6445 | */ |
| 6446 | if (strncmp (arg, "indirect=", 9) != 0) |
| 6447 | return 0; |
| 6448 | break; |
| 6449 | |
| 6450 | case 'x': |
| 6451 | /* -X conflicts with an ignored option, use -x instead */ |
| 6452 | md.detect_dv = 1; |
| 6453 | if (!arg || strcmp (arg, "explicit") == 0) |
| 6454 | { |
| 6455 | /* set default mode to explicit */ |
| 6456 | md.default_explicit_mode = 1; |
| 6457 | break; |
| 6458 | } |
| 6459 | else if (strcmp (arg, "auto") == 0) |
| 6460 | { |
| 6461 | md.default_explicit_mode = 0; |
| 6462 | } |
| 6463 | else if (strcmp (arg, "debug") == 0) |
| 6464 | { |
| 6465 | md.debug_dv = 1; |
| 6466 | } |
| 6467 | else if (strcmp (arg, "debugx") == 0) |
| 6468 | { |
| 6469 | md.default_explicit_mode = 1; |
| 6470 | md.debug_dv = 1; |
| 6471 | } |
| 6472 | else |
| 6473 | { |
| 6474 | as_bad (_("Unrecognized option '-x%s'"), arg); |
| 6475 | } |
| 6476 | break; |
| 6477 | |
| 6478 | case 'S': |
| 6479 | /* nops Print nops statistics. */ |
| 6480 | break; |
| 6481 | |
| 6482 | /* GNU specific switches for gcc. */ |
| 6483 | case OPTION_MCONSTANT_GP: |
| 6484 | md.flags |= EF_IA_64_CONS_GP; |
| 6485 | break; |
| 6486 | |
| 6487 | case OPTION_MAUTO_PIC: |
| 6488 | md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; |
| 6489 | break; |
| 6490 | |
| 6491 | default: |
| 6492 | return 0; |
| 6493 | } |
| 6494 | |
| 6495 | return 1; |
| 6496 | } |
| 6497 | |
| 6498 | void |
| 6499 | md_show_usage (stream) |
| 6500 | FILE *stream; |
| 6501 | { |
| 6502 | fputs (_("\ |
| 6503 | IA-64 options:\n\ |
| 6504 | --mconstant-gp mark output file as using the constant-GP model\n\ |
| 6505 | (sets ELF header flag EF_IA_64_CONS_GP)\n\ |
| 6506 | --mauto-pic mark output file as using the constant-GP model\n\ |
| 6507 | without function descriptors (sets ELF header flag\n\ |
| 6508 | EF_IA_64_NOFUNCDESC_CONS_GP)\n\ |
| 6509 | -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ |
| 6510 | -mle | -mbe select little- or big-endian byte order (default -mle)\n\ |
| 6511 | -x | -xexplicit turn on dependency violation checking (default)\n\ |
| 6512 | -xauto automagically remove dependency violations\n\ |
| 6513 | -xdebug debug dependency violation checker\n"), |
| 6514 | stream); |
| 6515 | } |
| 6516 | |
| 6517 | void |
| 6518 | ia64_after_parse_args () |
| 6519 | { |
| 6520 | if (debug_type == DEBUG_STABS) |
| 6521 | as_fatal (_("--gstabs is not supported for ia64")); |
| 6522 | } |
| 6523 | |
| 6524 | /* Return true if TYPE fits in TEMPL at SLOT. */ |
| 6525 | |
| 6526 | static int |
| 6527 | match (int templ, int type, int slot) |
| 6528 | { |
| 6529 | enum ia64_unit unit; |
| 6530 | int result; |
| 6531 | |
| 6532 | unit = ia64_templ_desc[templ].exec_unit[slot]; |
| 6533 | switch (type) |
| 6534 | { |
| 6535 | case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ |
| 6536 | case IA64_TYPE_A: |
| 6537 | result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); |
| 6538 | break; |
| 6539 | case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; |
| 6540 | case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; |
| 6541 | case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; |
| 6542 | case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; |
| 6543 | case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; |
| 6544 | default: result = 0; break; |
| 6545 | } |
| 6546 | return result; |
| 6547 | } |
| 6548 | |
| 6549 | /* Add a bit of extra goodness if a nop of type F or B would fit |
| 6550 | in TEMPL at SLOT. */ |
| 6551 | |
| 6552 | static inline int |
| 6553 | extra_goodness (int templ, int slot) |
| 6554 | { |
| 6555 | if (slot == 1 && match (templ, IA64_TYPE_F, slot)) |
| 6556 | return 2; |
| 6557 | if (slot == 2 && match (templ, IA64_TYPE_B, slot)) |
| 6558 | return 1; |
| 6559 | return 0; |
| 6560 | } |
| 6561 | |
| 6562 | /* This function is called once, at assembler startup time. It sets |
| 6563 | up all the tables, etc. that the MD part of the assembler will need |
| 6564 | that can be determined before arguments are parsed. */ |
| 6565 | void |
| 6566 | md_begin () |
| 6567 | { |
| 6568 | int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; |
| 6569 | const char *err; |
| 6570 | char name[8]; |
| 6571 | |
| 6572 | md.auto_align = 1; |
| 6573 | md.explicit_mode = md.default_explicit_mode; |
| 6574 | |
| 6575 | bfd_set_section_alignment (stdoutput, text_section, 4); |
| 6576 | |
| 6577 | /* Make sure fucntion pointers get initialized. */ |
| 6578 | target_big_endian = -1; |
| 6579 | dot_byteorder (TARGET_BYTES_BIG_ENDIAN); |
| 6580 | |
| 6581 | alias_hash = hash_new (); |
| 6582 | alias_name_hash = hash_new (); |
| 6583 | secalias_hash = hash_new (); |
| 6584 | secalias_name_hash = hash_new (); |
| 6585 | |
| 6586 | pseudo_func[FUNC_DTP_MODULE].u.sym = |
| 6587 | symbol_new (".<dtpmod>", undefined_section, FUNC_DTP_MODULE, |
| 6588 | &zero_address_frag); |
| 6589 | |
| 6590 | pseudo_func[FUNC_DTP_RELATIVE].u.sym = |
| 6591 | symbol_new (".<dtprel>", undefined_section, FUNC_DTP_RELATIVE, |
| 6592 | &zero_address_frag); |
| 6593 | |
| 6594 | pseudo_func[FUNC_FPTR_RELATIVE].u.sym = |
| 6595 | symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, |
| 6596 | &zero_address_frag); |
| 6597 | |
| 6598 | pseudo_func[FUNC_GP_RELATIVE].u.sym = |
| 6599 | symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, |
| 6600 | &zero_address_frag); |
| 6601 | |
| 6602 | pseudo_func[FUNC_LT_RELATIVE].u.sym = |
| 6603 | symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, |
| 6604 | &zero_address_frag); |
| 6605 | |
| 6606 | pseudo_func[FUNC_LT_RELATIVE_X].u.sym = |
| 6607 | symbol_new (".<ltoffx>", undefined_section, FUNC_LT_RELATIVE_X, |
| 6608 | &zero_address_frag); |
| 6609 | |
| 6610 | pseudo_func[FUNC_PC_RELATIVE].u.sym = |
| 6611 | symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, |
| 6612 | &zero_address_frag); |
| 6613 | |
| 6614 | pseudo_func[FUNC_PLT_RELATIVE].u.sym = |
| 6615 | symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, |
| 6616 | &zero_address_frag); |
| 6617 | |
| 6618 | pseudo_func[FUNC_SEC_RELATIVE].u.sym = |
| 6619 | symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, |
| 6620 | &zero_address_frag); |
| 6621 | |
| 6622 | pseudo_func[FUNC_SEG_RELATIVE].u.sym = |
| 6623 | symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, |
| 6624 | &zero_address_frag); |
| 6625 | |
| 6626 | pseudo_func[FUNC_TP_RELATIVE].u.sym = |
| 6627 | symbol_new (".<tprel>", undefined_section, FUNC_TP_RELATIVE, |
| 6628 | &zero_address_frag); |
| 6629 | |
| 6630 | pseudo_func[FUNC_LTV_RELATIVE].u.sym = |
| 6631 | symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, |
| 6632 | &zero_address_frag); |
| 6633 | |
| 6634 | pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = |
| 6635 | symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, |
| 6636 | &zero_address_frag); |
| 6637 | |
| 6638 | pseudo_func[FUNC_LT_DTP_MODULE].u.sym = |
| 6639 | symbol_new (".<ltoff.dtpmod>", undefined_section, FUNC_LT_DTP_MODULE, |
| 6640 | &zero_address_frag); |
| 6641 | |
| 6642 | pseudo_func[FUNC_LT_DTP_RELATIVE].u.sym = |
| 6643 | symbol_new (".<ltoff.dptrel>", undefined_section, FUNC_LT_DTP_RELATIVE, |
| 6644 | &zero_address_frag); |
| 6645 | |
| 6646 | pseudo_func[FUNC_LT_TP_RELATIVE].u.sym = |
| 6647 | symbol_new (".<ltoff.tprel>", undefined_section, FUNC_LT_TP_RELATIVE, |
| 6648 | &zero_address_frag); |
| 6649 | |
| 6650 | pseudo_func[FUNC_IPLT_RELOC].u.sym = |
| 6651 | symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC, |
| 6652 | &zero_address_frag); |
| 6653 | |
| 6654 | /* Compute the table of best templates. We compute goodness as a |
| 6655 | base 4 value, in which each match counts for 3, each F counts |
| 6656 | for 2, each B counts for 1. This should maximize the number of |
| 6657 | F and B nops in the chosen bundles, which is good because these |
| 6658 | pipelines are least likely to be overcommitted. */ |
| 6659 | for (i = 0; i < IA64_NUM_TYPES; ++i) |
| 6660 | for (j = 0; j < IA64_NUM_TYPES; ++j) |
| 6661 | for (k = 0; k < IA64_NUM_TYPES; ++k) |
| 6662 | { |
| 6663 | best = 0; |
| 6664 | for (t = 0; t < NELEMS (ia64_templ_desc); ++t) |
| 6665 | { |
| 6666 | goodness = 0; |
| 6667 | if (match (t, i, 0)) |
| 6668 | { |
| 6669 | if (match (t, j, 1)) |
| 6670 | { |
| 6671 | if (match (t, k, 2)) |
| 6672 | goodness = 3 + 3 + 3; |
| 6673 | else |
| 6674 | goodness = 3 + 3 + extra_goodness (t, 2); |
| 6675 | } |
| 6676 | else if (match (t, j, 2)) |
| 6677 | goodness = 3 + 3 + extra_goodness (t, 1); |
| 6678 | else |
| 6679 | { |
| 6680 | goodness = 3; |
| 6681 | goodness += extra_goodness (t, 1); |
| 6682 | goodness += extra_goodness (t, 2); |
| 6683 | } |
| 6684 | } |
| 6685 | else if (match (t, i, 1)) |
| 6686 | { |
| 6687 | if (match (t, j, 2)) |
| 6688 | goodness = 3 + 3; |
| 6689 | else |
| 6690 | goodness = 3 + extra_goodness (t, 2); |
| 6691 | } |
| 6692 | else if (match (t, i, 2)) |
| 6693 | goodness = 3 + extra_goodness (t, 1); |
| 6694 | |
| 6695 | if (goodness > best) |
| 6696 | { |
| 6697 | best = goodness; |
| 6698 | best_template[i][j][k] = t; |
| 6699 | } |
| 6700 | } |
| 6701 | } |
| 6702 | |
| 6703 | for (i = 0; i < NUM_SLOTS; ++i) |
| 6704 | md.slot[i].user_template = -1; |
| 6705 | |
| 6706 | md.pseudo_hash = hash_new (); |
| 6707 | for (i = 0; i < NELEMS (pseudo_opcode); ++i) |
| 6708 | { |
| 6709 | err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, |
| 6710 | (void *) (pseudo_opcode + i)); |
| 6711 | if (err) |
| 6712 | as_fatal ("ia64.md_begin: can't hash `%s': %s", |
| 6713 | pseudo_opcode[i].name, err); |
| 6714 | } |
| 6715 | |
| 6716 | md.reg_hash = hash_new (); |
| 6717 | md.dynreg_hash = hash_new (); |
| 6718 | md.const_hash = hash_new (); |
| 6719 | md.entry_hash = hash_new (); |
| 6720 | |
| 6721 | /* general registers: */ |
| 6722 | |
| 6723 | total = 128; |
| 6724 | for (i = 0; i < total; ++i) |
| 6725 | { |
| 6726 | sprintf (name, "r%d", i - REG_GR); |
| 6727 | md.regsym[i] = declare_register (name, i); |
| 6728 | } |
| 6729 | |
| 6730 | /* floating point registers: */ |
| 6731 | total += 128; |
| 6732 | for (; i < total; ++i) |
| 6733 | { |
| 6734 | sprintf (name, "f%d", i - REG_FR); |
| 6735 | md.regsym[i] = declare_register (name, i); |
| 6736 | } |
| 6737 | |
| 6738 | /* application registers: */ |
| 6739 | total += 128; |
| 6740 | ar_base = i; |
| 6741 | for (; i < total; ++i) |
| 6742 | { |
| 6743 | sprintf (name, "ar%d", i - REG_AR); |
| 6744 | md.regsym[i] = declare_register (name, i); |
| 6745 | } |
| 6746 | |
| 6747 | /* control registers: */ |
| 6748 | total += 128; |
| 6749 | cr_base = i; |
| 6750 | for (; i < total; ++i) |
| 6751 | { |
| 6752 | sprintf (name, "cr%d", i - REG_CR); |
| 6753 | md.regsym[i] = declare_register (name, i); |
| 6754 | } |
| 6755 | |
| 6756 | /* predicate registers: */ |
| 6757 | total += 64; |
| 6758 | for (; i < total; ++i) |
| 6759 | { |
| 6760 | sprintf (name, "p%d", i - REG_P); |
| 6761 | md.regsym[i] = declare_register (name, i); |
| 6762 | } |
| 6763 | |
| 6764 | /* branch registers: */ |
| 6765 | total += 8; |
| 6766 | for (; i < total; ++i) |
| 6767 | { |
| 6768 | sprintf (name, "b%d", i - REG_BR); |
| 6769 | md.regsym[i] = declare_register (name, i); |
| 6770 | } |
| 6771 | |
| 6772 | md.regsym[REG_IP] = declare_register ("ip", REG_IP); |
| 6773 | md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); |
| 6774 | md.regsym[REG_PR] = declare_register ("pr", REG_PR); |
| 6775 | md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); |
| 6776 | md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); |
| 6777 | md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); |
| 6778 | md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); |
| 6779 | |
| 6780 | for (i = 0; i < NELEMS (indirect_reg); ++i) |
| 6781 | { |
| 6782 | regnum = indirect_reg[i].regnum; |
| 6783 | md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); |
| 6784 | } |
| 6785 | |
| 6786 | /* define synonyms for application registers: */ |
| 6787 | for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) |
| 6788 | md.regsym[i] = declare_register (ar[i - REG_AR].name, |
| 6789 | REG_AR + ar[i - REG_AR].regnum); |
| 6790 | |
| 6791 | /* define synonyms for control registers: */ |
| 6792 | for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) |
| 6793 | md.regsym[i] = declare_register (cr[i - REG_CR].name, |
| 6794 | REG_CR + cr[i - REG_CR].regnum); |
| 6795 | |
| 6796 | declare_register ("gp", REG_GR + 1); |
| 6797 | declare_register ("sp", REG_GR + 12); |
| 6798 | declare_register ("rp", REG_BR + 0); |
| 6799 | |
| 6800 | /* pseudo-registers used to specify unwind info: */ |
| 6801 | declare_register ("psp", REG_PSP); |
| 6802 | |
| 6803 | declare_register_set ("ret", 4, REG_GR + 8); |
| 6804 | declare_register_set ("farg", 8, REG_FR + 8); |
| 6805 | declare_register_set ("fret", 8, REG_FR + 8); |
| 6806 | |
| 6807 | for (i = 0; i < NELEMS (const_bits); ++i) |
| 6808 | { |
| 6809 | err = hash_insert (md.const_hash, const_bits[i].name, |
| 6810 | (PTR) (const_bits + i)); |
| 6811 | if (err) |
| 6812 | as_fatal ("Inserting \"%s\" into constant hash table failed: %s", |
| 6813 | name, err); |
| 6814 | } |
| 6815 | |
| 6816 | /* Set the architecture and machine depending on defaults and command line |
| 6817 | options. */ |
| 6818 | if (md.flags & EF_IA_64_ABI64) |
| 6819 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); |
| 6820 | else |
| 6821 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); |
| 6822 | |
| 6823 | if (! ok) |
| 6824 | as_warn (_("Could not set architecture and machine")); |
| 6825 | |
| 6826 | /* Set the pointer size and pointer shift size depending on md.flags */ |
| 6827 | |
| 6828 | if (md.flags & EF_IA_64_ABI64) |
| 6829 | { |
| 6830 | md.pointer_size = 8; /* pointers are 8 bytes */ |
| 6831 | md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */ |
| 6832 | } |
| 6833 | else |
| 6834 | { |
| 6835 | md.pointer_size = 4; /* pointers are 4 bytes */ |
| 6836 | md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */ |
| 6837 | } |
| 6838 | |
| 6839 | md.mem_offset.hint = 0; |
| 6840 | md.path = 0; |
| 6841 | md.maxpaths = 0; |
| 6842 | md.entry_labels = NULL; |
| 6843 | } |
| 6844 | |
| 6845 | /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin |
| 6846 | because that is called after md_parse_option which is where we do the |
| 6847 | dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the |
| 6848 | default endianness. */ |
| 6849 | |
| 6850 | void |
| 6851 | ia64_init (argc, argv) |
| 6852 | int argc ATTRIBUTE_UNUSED; |
| 6853 | char **argv ATTRIBUTE_UNUSED; |
| 6854 | { |
| 6855 | md.flags = MD_FLAGS_DEFAULT; |
| 6856 | } |
| 6857 | |
| 6858 | /* Return a string for the target object file format. */ |
| 6859 | |
| 6860 | const char * |
| 6861 | ia64_target_format () |
| 6862 | { |
| 6863 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 6864 | { |
| 6865 | if (md.flags & EF_IA_64_BE) |
| 6866 | { |
| 6867 | if (md.flags & EF_IA_64_ABI64) |
| 6868 | #if defined(TE_AIX50) |
| 6869 | return "elf64-ia64-aix-big"; |
| 6870 | #elif defined(TE_HPUX) |
| 6871 | return "elf64-ia64-hpux-big"; |
| 6872 | #else |
| 6873 | return "elf64-ia64-big"; |
| 6874 | #endif |
| 6875 | else |
| 6876 | #if defined(TE_AIX50) |
| 6877 | return "elf32-ia64-aix-big"; |
| 6878 | #elif defined(TE_HPUX) |
| 6879 | return "elf32-ia64-hpux-big"; |
| 6880 | #else |
| 6881 | return "elf32-ia64-big"; |
| 6882 | #endif |
| 6883 | } |
| 6884 | else |
| 6885 | { |
| 6886 | if (md.flags & EF_IA_64_ABI64) |
| 6887 | #ifdef TE_AIX50 |
| 6888 | return "elf64-ia64-aix-little"; |
| 6889 | #else |
| 6890 | return "elf64-ia64-little"; |
| 6891 | #endif |
| 6892 | else |
| 6893 | #ifdef TE_AIX50 |
| 6894 | return "elf32-ia64-aix-little"; |
| 6895 | #else |
| 6896 | return "elf32-ia64-little"; |
| 6897 | #endif |
| 6898 | } |
| 6899 | } |
| 6900 | else |
| 6901 | return "unknown-format"; |
| 6902 | } |
| 6903 | |
| 6904 | void |
| 6905 | ia64_end_of_source () |
| 6906 | { |
| 6907 | /* terminate insn group upon reaching end of file: */ |
| 6908 | insn_group_break (1, 0, 0); |
| 6909 | |
| 6910 | /* emits slots we haven't written yet: */ |
| 6911 | ia64_flush_insns (); |
| 6912 | |
| 6913 | bfd_set_private_flags (stdoutput, md.flags); |
| 6914 | |
| 6915 | md.mem_offset.hint = 0; |
| 6916 | } |
| 6917 | |
| 6918 | void |
| 6919 | ia64_start_line () |
| 6920 | { |
| 6921 | if (md.qp.X_op == O_register) |
| 6922 | as_bad ("qualifying predicate not followed by instruction"); |
| 6923 | md.qp.X_op = O_absent; |
| 6924 | |
| 6925 | if (ignore_input ()) |
| 6926 | return; |
| 6927 | |
| 6928 | if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') |
| 6929 | { |
| 6930 | if (md.detect_dv && !md.explicit_mode) |
| 6931 | as_warn (_("Explicit stops are ignored in auto mode")); |
| 6932 | else |
| 6933 | insn_group_break (1, 0, 0); |
| 6934 | } |
| 6935 | } |
| 6936 | |
| 6937 | /* This is a hook for ia64_frob_label, so that it can distinguish tags from |
| 6938 | labels. */ |
| 6939 | static int defining_tag = 0; |
| 6940 | |
| 6941 | int |
| 6942 | ia64_unrecognized_line (ch) |
| 6943 | int ch; |
| 6944 | { |
| 6945 | switch (ch) |
| 6946 | { |
| 6947 | case '(': |
| 6948 | expression (&md.qp); |
| 6949 | if (*input_line_pointer++ != ')') |
| 6950 | { |
| 6951 | as_bad ("Expected ')'"); |
| 6952 | return 0; |
| 6953 | } |
| 6954 | if (md.qp.X_op != O_register) |
| 6955 | { |
| 6956 | as_bad ("Qualifying predicate expected"); |
| 6957 | return 0; |
| 6958 | } |
| 6959 | if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) |
| 6960 | { |
| 6961 | as_bad ("Predicate register expected"); |
| 6962 | return 0; |
| 6963 | } |
| 6964 | return 1; |
| 6965 | |
| 6966 | case '{': |
| 6967 | if (md.manual_bundling) |
| 6968 | as_warn ("Found '{' when manual bundling is already turned on"); |
| 6969 | else |
| 6970 | CURR_SLOT.manual_bundling_on = 1; |
| 6971 | md.manual_bundling = 1; |
| 6972 | |
| 6973 | /* Bundling is only acceptable in explicit mode |
| 6974 | or when in default automatic mode. */ |
| 6975 | if (md.detect_dv && !md.explicit_mode) |
| 6976 | { |
| 6977 | if (!md.mode_explicitly_set |
| 6978 | && !md.default_explicit_mode) |
| 6979 | dot_dv_mode ('E'); |
| 6980 | else |
| 6981 | as_warn (_("Found '{' after explicit switch to automatic mode")); |
| 6982 | } |
| 6983 | return 1; |
| 6984 | |
| 6985 | case '}': |
| 6986 | if (!md.manual_bundling) |
| 6987 | as_warn ("Found '}' when manual bundling is off"); |
| 6988 | else |
| 6989 | PREV_SLOT.manual_bundling_off = 1; |
| 6990 | md.manual_bundling = 0; |
| 6991 | |
| 6992 | /* switch back to automatic mode, if applicable */ |
| 6993 | if (md.detect_dv |
| 6994 | && md.explicit_mode |
| 6995 | && !md.mode_explicitly_set |
| 6996 | && !md.default_explicit_mode) |
| 6997 | dot_dv_mode ('A'); |
| 6998 | |
| 6999 | /* Allow '{' to follow on the same line. We also allow ";;", but that |
| 7000 | happens automatically because ';' is an end of line marker. */ |
| 7001 | SKIP_WHITESPACE (); |
| 7002 | if (input_line_pointer[0] == '{') |
| 7003 | { |
| 7004 | input_line_pointer++; |
| 7005 | return ia64_unrecognized_line ('{'); |
| 7006 | } |
| 7007 | |
| 7008 | demand_empty_rest_of_line (); |
| 7009 | return 1; |
| 7010 | |
| 7011 | case '[': |
| 7012 | { |
| 7013 | char *s; |
| 7014 | char c; |
| 7015 | symbolS *tag; |
| 7016 | int temp; |
| 7017 | |
| 7018 | if (md.qp.X_op == O_register) |
| 7019 | { |
| 7020 | as_bad ("Tag must come before qualifying predicate."); |
| 7021 | return 0; |
| 7022 | } |
| 7023 | |
| 7024 | /* This implements just enough of read_a_source_file in read.c to |
| 7025 | recognize labels. */ |
| 7026 | if (is_name_beginner (*input_line_pointer)) |
| 7027 | { |
| 7028 | s = input_line_pointer; |
| 7029 | c = get_symbol_end (); |
| 7030 | } |
| 7031 | else if (LOCAL_LABELS_FB |
| 7032 | && ISDIGIT (*input_line_pointer)) |
| 7033 | { |
| 7034 | temp = 0; |
| 7035 | while (ISDIGIT (*input_line_pointer)) |
| 7036 | temp = (temp * 10) + *input_line_pointer++ - '0'; |
| 7037 | fb_label_instance_inc (temp); |
| 7038 | s = fb_label_name (temp, 0); |
| 7039 | c = *input_line_pointer; |
| 7040 | } |
| 7041 | else |
| 7042 | { |
| 7043 | s = NULL; |
| 7044 | c = '\0'; |
| 7045 | } |
| 7046 | if (c != ':') |
| 7047 | { |
| 7048 | /* Put ':' back for error messages' sake. */ |
| 7049 | *input_line_pointer++ = ':'; |
| 7050 | as_bad ("Expected ':'"); |
| 7051 | return 0; |
| 7052 | } |
| 7053 | |
| 7054 | defining_tag = 1; |
| 7055 | tag = colon (s); |
| 7056 | defining_tag = 0; |
| 7057 | /* Put ':' back for error messages' sake. */ |
| 7058 | *input_line_pointer++ = ':'; |
| 7059 | if (*input_line_pointer++ != ']') |
| 7060 | { |
| 7061 | as_bad ("Expected ']'"); |
| 7062 | return 0; |
| 7063 | } |
| 7064 | if (! tag) |
| 7065 | { |
| 7066 | as_bad ("Tag name expected"); |
| 7067 | return 0; |
| 7068 | } |
| 7069 | return 1; |
| 7070 | } |
| 7071 | |
| 7072 | default: |
| 7073 | break; |
| 7074 | } |
| 7075 | |
| 7076 | /* Not a valid line. */ |
| 7077 | return 0; |
| 7078 | } |
| 7079 | |
| 7080 | void |
| 7081 | ia64_frob_label (sym) |
| 7082 | struct symbol *sym; |
| 7083 | { |
| 7084 | struct label_fix *fix; |
| 7085 | |
| 7086 | /* Tags need special handling since they are not bundle breaks like |
| 7087 | labels. */ |
| 7088 | if (defining_tag) |
| 7089 | { |
| 7090 | fix = obstack_alloc (¬es, sizeof (*fix)); |
| 7091 | fix->sym = sym; |
| 7092 | fix->next = CURR_SLOT.tag_fixups; |
| 7093 | CURR_SLOT.tag_fixups = fix; |
| 7094 | |
| 7095 | return; |
| 7096 | } |
| 7097 | |
| 7098 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
| 7099 | { |
| 7100 | md.last_text_seg = now_seg; |
| 7101 | fix = obstack_alloc (¬es, sizeof (*fix)); |
| 7102 | fix->sym = sym; |
| 7103 | fix->next = CURR_SLOT.label_fixups; |
| 7104 | CURR_SLOT.label_fixups = fix; |
| 7105 | |
| 7106 | /* Keep track of how many code entry points we've seen. */ |
| 7107 | if (md.path == md.maxpaths) |
| 7108 | { |
| 7109 | md.maxpaths += 20; |
| 7110 | md.entry_labels = (const char **) |
| 7111 | xrealloc ((void *) md.entry_labels, |
| 7112 | md.maxpaths * sizeof (char *)); |
| 7113 | } |
| 7114 | md.entry_labels[md.path++] = S_GET_NAME (sym); |
| 7115 | } |
| 7116 | } |
| 7117 | |
| 7118 | void |
| 7119 | ia64_flush_pending_output () |
| 7120 | { |
| 7121 | if (!md.keep_pending_output |
| 7122 | && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
| 7123 | { |
| 7124 | /* ??? This causes many unnecessary stop bits to be emitted. |
| 7125 | Unfortunately, it isn't clear if it is safe to remove this. */ |
| 7126 | insn_group_break (1, 0, 0); |
| 7127 | ia64_flush_insns (); |
| 7128 | } |
| 7129 | } |
| 7130 | |
| 7131 | /* Do ia64-specific expression optimization. All that's done here is |
| 7132 | to transform index expressions that are either due to the indexing |
| 7133 | of rotating registers or due to the indexing of indirect register |
| 7134 | sets. */ |
| 7135 | int |
| 7136 | ia64_optimize_expr (l, op, r) |
| 7137 | expressionS *l; |
| 7138 | operatorT op; |
| 7139 | expressionS *r; |
| 7140 | { |
| 7141 | unsigned num_regs; |
| 7142 | |
| 7143 | if (op == O_index) |
| 7144 | { |
| 7145 | if (l->X_op == O_register && r->X_op == O_constant) |
| 7146 | { |
| 7147 | num_regs = (l->X_add_number >> 16); |
| 7148 | if ((unsigned) r->X_add_number >= num_regs) |
| 7149 | { |
| 7150 | if (!num_regs) |
| 7151 | as_bad ("No current frame"); |
| 7152 | else |
| 7153 | as_bad ("Index out of range 0..%u", num_regs - 1); |
| 7154 | r->X_add_number = 0; |
| 7155 | } |
| 7156 | l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; |
| 7157 | return 1; |
| 7158 | } |
| 7159 | else if (l->X_op == O_register && r->X_op == O_register) |
| 7160 | { |
| 7161 | if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR |
| 7162 | || l->X_add_number == IND_MEM) |
| 7163 | { |
| 7164 | as_bad ("Indirect register set name expected"); |
| 7165 | l->X_add_number = IND_CPUID; |
| 7166 | } |
| 7167 | l->X_op = O_index; |
| 7168 | l->X_op_symbol = md.regsym[l->X_add_number]; |
| 7169 | l->X_add_number = r->X_add_number; |
| 7170 | return 1; |
| 7171 | } |
| 7172 | } |
| 7173 | return 0; |
| 7174 | } |
| 7175 | |
| 7176 | int |
| 7177 | ia64_parse_name (name, e) |
| 7178 | char *name; |
| 7179 | expressionS *e; |
| 7180 | { |
| 7181 | struct const_desc *cdesc; |
| 7182 | struct dynreg *dr = 0; |
| 7183 | unsigned int regnum; |
| 7184 | struct symbol *sym; |
| 7185 | char *end; |
| 7186 | |
| 7187 | /* first see if NAME is a known register name: */ |
| 7188 | sym = hash_find (md.reg_hash, name); |
| 7189 | if (sym) |
| 7190 | { |
| 7191 | e->X_op = O_register; |
| 7192 | e->X_add_number = S_GET_VALUE (sym); |
| 7193 | return 1; |
| 7194 | } |
| 7195 | |
| 7196 | cdesc = hash_find (md.const_hash, name); |
| 7197 | if (cdesc) |
| 7198 | { |
| 7199 | e->X_op = O_constant; |
| 7200 | e->X_add_number = cdesc->value; |
| 7201 | return 1; |
| 7202 | } |
| 7203 | |
| 7204 | /* check for inN, locN, or outN: */ |
| 7205 | switch (name[0]) |
| 7206 | { |
| 7207 | case 'i': |
| 7208 | if (name[1] == 'n' && ISDIGIT (name[2])) |
| 7209 | { |
| 7210 | dr = &md.in; |
| 7211 | name += 2; |
| 7212 | } |
| 7213 | break; |
| 7214 | |
| 7215 | case 'l': |
| 7216 | if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3])) |
| 7217 | { |
| 7218 | dr = &md.loc; |
| 7219 | name += 3; |
| 7220 | } |
| 7221 | break; |
| 7222 | |
| 7223 | case 'o': |
| 7224 | if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3])) |
| 7225 | { |
| 7226 | dr = &md.out; |
| 7227 | name += 3; |
| 7228 | } |
| 7229 | break; |
| 7230 | |
| 7231 | default: |
| 7232 | break; |
| 7233 | } |
| 7234 | |
| 7235 | if (dr) |
| 7236 | { |
| 7237 | /* The name is inN, locN, or outN; parse the register number. */ |
| 7238 | regnum = strtoul (name, &end, 10); |
| 7239 | if (end > name && *end == '\0') |
| 7240 | { |
| 7241 | if ((unsigned) regnum >= dr->num_regs) |
| 7242 | { |
| 7243 | if (!dr->num_regs) |
| 7244 | as_bad ("No current frame"); |
| 7245 | else |
| 7246 | as_bad ("Register number out of range 0..%u", |
| 7247 | dr->num_regs - 1); |
| 7248 | regnum = 0; |
| 7249 | } |
| 7250 | e->X_op = O_register; |
| 7251 | e->X_add_number = dr->base + regnum; |
| 7252 | return 1; |
| 7253 | } |
| 7254 | } |
| 7255 | |
| 7256 | if ((dr = hash_find (md.dynreg_hash, name))) |
| 7257 | { |
| 7258 | /* We've got ourselves the name of a rotating register set. |
| 7259 | Store the base register number in the low 16 bits of |
| 7260 | X_add_number and the size of the register set in the top 16 |
| 7261 | bits. */ |
| 7262 | e->X_op = O_register; |
| 7263 | e->X_add_number = dr->base | (dr->num_regs << 16); |
| 7264 | return 1; |
| 7265 | } |
| 7266 | return 0; |
| 7267 | } |
| 7268 | |
| 7269 | /* Remove the '#' suffix that indicates a symbol as opposed to a register. */ |
| 7270 | |
| 7271 | char * |
| 7272 | ia64_canonicalize_symbol_name (name) |
| 7273 | char *name; |
| 7274 | { |
| 7275 | size_t len = strlen (name); |
| 7276 | if (len > 1 && name[len - 1] == '#') |
| 7277 | name[len - 1] = '\0'; |
| 7278 | return name; |
| 7279 | } |
| 7280 | |
| 7281 | /* Return true if idesc is a conditional branch instruction. This excludes |
| 7282 | the modulo scheduled branches, and br.ia. Mod-sched branches are excluded |
| 7283 | because they always read/write resources regardless of the value of the |
| 7284 | qualifying predicate. br.ia must always use p0, and hence is always |
| 7285 | taken. Thus this function returns true for branches which can fall |
| 7286 | through, and which use no resources if they do fall through. */ |
| 7287 | |
| 7288 | static int |
| 7289 | is_conditional_branch (idesc) |
| 7290 | struct ia64_opcode *idesc; |
| 7291 | { |
| 7292 | /* br is a conditional branch. Everything that starts with br. except |
| 7293 | br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch. |
| 7294 | Everything that starts with brl is a conditional branch. */ |
| 7295 | return (idesc->name[0] == 'b' && idesc->name[1] == 'r' |
| 7296 | && (idesc->name[2] == '\0' |
| 7297 | || (idesc->name[2] == '.' && idesc->name[3] != 'i' |
| 7298 | && idesc->name[3] != 'c' && idesc->name[3] != 'w') |
| 7299 | || idesc->name[2] == 'l' |
| 7300 | /* br.cond, br.call, br.clr */ |
| 7301 | || (idesc->name[2] == '.' && idesc->name[3] == 'c' |
| 7302 | && (idesc->name[4] == 'a' || idesc->name[4] == 'o' |
| 7303 | || (idesc->name[4] == 'l' && idesc->name[5] == 'r'))))); |
| 7304 | } |
| 7305 | |
| 7306 | /* Return whether the given opcode is a taken branch. If there's any doubt, |
| 7307 | returns zero. */ |
| 7308 | |
| 7309 | static int |
| 7310 | is_taken_branch (idesc) |
| 7311 | struct ia64_opcode *idesc; |
| 7312 | { |
| 7313 | return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) |
| 7314 | || strncmp (idesc->name, "br.ia", 5) == 0); |
| 7315 | } |
| 7316 | |
| 7317 | /* Return whether the given opcode is an interruption or rfi. If there's any |
| 7318 | doubt, returns zero. */ |
| 7319 | |
| 7320 | static int |
| 7321 | is_interruption_or_rfi (idesc) |
| 7322 | struct ia64_opcode *idesc; |
| 7323 | { |
| 7324 | if (strcmp (idesc->name, "rfi") == 0) |
| 7325 | return 1; |
| 7326 | return 0; |
| 7327 | } |
| 7328 | |
| 7329 | /* Returns the index of the given dependency in the opcode's list of chks, or |
| 7330 | -1 if there is no dependency. */ |
| 7331 | |
| 7332 | static int |
| 7333 | depends_on (depind, idesc) |
| 7334 | int depind; |
| 7335 | struct ia64_opcode *idesc; |
| 7336 | { |
| 7337 | int i; |
| 7338 | const struct ia64_opcode_dependency *dep = idesc->dependencies; |
| 7339 | for (i = 0; i < dep->nchks; i++) |
| 7340 | { |
| 7341 | if (depind == DEP (dep->chks[i])) |
| 7342 | return i; |
| 7343 | } |
| 7344 | return -1; |
| 7345 | } |
| 7346 | |
| 7347 | /* Determine a set of specific resources used for a particular resource |
| 7348 | class. Returns the number of specific resources identified For those |
| 7349 | cases which are not determinable statically, the resource returned is |
| 7350 | marked nonspecific. |
| 7351 | |
| 7352 | Meanings of value in 'NOTE': |
| 7353 | 1) only read/write when the register number is explicitly encoded in the |
| 7354 | insn. |
| 7355 | 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only |
| 7356 | accesses CFM when qualifying predicate is in the rotating region. |
| 7357 | 3) general register value is used to specify an indirect register; not |
| 7358 | determinable statically. |
| 7359 | 4) only read the given resource when bits 7:0 of the indirect index |
| 7360 | register value does not match the register number of the resource; not |
| 7361 | determinable statically. |
| 7362 | 5) all rules are implementation specific. |
| 7363 | 6) only when both the index specified by the reader and the index specified |
| 7364 | by the writer have the same value in bits 63:61; not determinable |
| 7365 | statically. |
| 7366 | 7) only access the specified resource when the corresponding mask bit is |
| 7367 | set |
| 7368 | 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is |
| 7369 | only read when these insns reference FR2-31 |
| 7370 | 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only |
| 7371 | written when these insns write FR32-127 |
| 7372 | 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the |
| 7373 | instruction |
| 7374 | 11) The target predicates are written independently of PR[qp], but source |
| 7375 | registers are only read if PR[qp] is true. Since the state of PR[qp] |
| 7376 | cannot statically be determined, all source registers are marked used. |
| 7377 | 12) This insn only reads the specified predicate register when that |
| 7378 | register is the PR[qp]. |
| 7379 | 13) This reference to ld-c only applies to teh GR whose value is loaded |
| 7380 | with data returned from memory, not the post-incremented address register. |
| 7381 | 14) The RSE resource includes the implementation-specific RSE internal |
| 7382 | state resources. At least one (and possibly more) of these resources are |
| 7383 | read by each instruction listed in IC:rse-readers. At least one (and |
| 7384 | possibly more) of these resources are written by each insn listed in |
| 7385 | IC:rse-writers. |
| 7386 | 15+16) Represents reserved instructions, which the assembler does not |
| 7387 | generate. |
| 7388 | |
| 7389 | Memory resources (i.e. locations in memory) are *not* marked or tracked by |
| 7390 | this code; there are no dependency violations based on memory access. |
| 7391 | */ |
| 7392 | |
| 7393 | #define MAX_SPECS 256 |
| 7394 | #define DV_CHK 1 |
| 7395 | #define DV_REG 0 |
| 7396 | |
| 7397 | static int |
| 7398 | specify_resource (dep, idesc, type, specs, note, path) |
| 7399 | const struct ia64_dependency *dep; |
| 7400 | struct ia64_opcode *idesc; |
| 7401 | int type; /* is this a DV chk or a DV reg? */ |
| 7402 | struct rsrc specs[MAX_SPECS]; /* returned specific resources */ |
| 7403 | int note; /* resource note for this insn's usage */ |
| 7404 | int path; /* which execution path to examine */ |
| 7405 | { |
| 7406 | int count = 0; |
| 7407 | int i; |
| 7408 | int rsrc_write = 0; |
| 7409 | struct rsrc tmpl; |
| 7410 | |
| 7411 | if (dep->mode == IA64_DV_WAW |
| 7412 | || (dep->mode == IA64_DV_RAW && type == DV_REG) |
| 7413 | || (dep->mode == IA64_DV_WAR && type == DV_CHK)) |
| 7414 | rsrc_write = 1; |
| 7415 | |
| 7416 | /* template for any resources we identify */ |
| 7417 | tmpl.dependency = dep; |
| 7418 | tmpl.note = note; |
| 7419 | tmpl.insn_srlz = tmpl.data_srlz = 0; |
| 7420 | tmpl.qp_regno = CURR_SLOT.qp_regno; |
| 7421 | tmpl.link_to_qp_branch = 1; |
| 7422 | tmpl.mem_offset.hint = 0; |
| 7423 | tmpl.specific = 1; |
| 7424 | tmpl.index = 0; |
| 7425 | tmpl.cmp_type = CMP_NONE; |
| 7426 | |
| 7427 | #define UNHANDLED \ |
| 7428 | as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ |
| 7429 | dep->name, idesc->name, (rsrc_write?"write":"read"), note) |
| 7430 | #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) |
| 7431 | |
| 7432 | /* we don't need to track these */ |
| 7433 | if (dep->semantics == IA64_DVS_NONE) |
| 7434 | return 0; |
| 7435 | |
| 7436 | switch (dep->specifier) |
| 7437 | { |
| 7438 | case IA64_RS_AR_K: |
| 7439 | if (note == 1) |
| 7440 | { |
| 7441 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 7442 | { |
| 7443 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7444 | if (regno >= 0 && regno <= 7) |
| 7445 | { |
| 7446 | specs[count] = tmpl; |
| 7447 | specs[count++].index = regno; |
| 7448 | } |
| 7449 | } |
| 7450 | } |
| 7451 | else if (note == 0) |
| 7452 | { |
| 7453 | for (i = 0; i < 8; i++) |
| 7454 | { |
| 7455 | specs[count] = tmpl; |
| 7456 | specs[count++].index = i; |
| 7457 | } |
| 7458 | } |
| 7459 | else |
| 7460 | { |
| 7461 | UNHANDLED; |
| 7462 | } |
| 7463 | break; |
| 7464 | |
| 7465 | case IA64_RS_AR_UNAT: |
| 7466 | /* This is a mov =AR or mov AR= instruction. */ |
| 7467 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 7468 | { |
| 7469 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7470 | if (regno == AR_UNAT) |
| 7471 | { |
| 7472 | specs[count++] = tmpl; |
| 7473 | } |
| 7474 | } |
| 7475 | else |
| 7476 | { |
| 7477 | /* This is a spill/fill, or other instruction that modifies the |
| 7478 | unat register. */ |
| 7479 | |
| 7480 | /* Unless we can determine the specific bits used, mark the whole |
| 7481 | thing; bits 8:3 of the memory address indicate the bit used in |
| 7482 | UNAT. The .mem.offset hint may be used to eliminate a small |
| 7483 | subset of conflicts. */ |
| 7484 | specs[count] = tmpl; |
| 7485 | if (md.mem_offset.hint) |
| 7486 | { |
| 7487 | if (md.debug_dv) |
| 7488 | fprintf (stderr, " Using hint for spill/fill\n"); |
| 7489 | /* The index isn't actually used, just set it to something |
| 7490 | approximating the bit index. */ |
| 7491 | specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; |
| 7492 | specs[count].mem_offset.hint = 1; |
| 7493 | specs[count].mem_offset.offset = md.mem_offset.offset; |
| 7494 | specs[count++].mem_offset.base = md.mem_offset.base; |
| 7495 | } |
| 7496 | else |
| 7497 | { |
| 7498 | specs[count++].specific = 0; |
| 7499 | } |
| 7500 | } |
| 7501 | break; |
| 7502 | |
| 7503 | case IA64_RS_AR: |
| 7504 | if (note == 1) |
| 7505 | { |
| 7506 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 7507 | { |
| 7508 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7509 | if ((regno >= 8 && regno <= 15) |
| 7510 | || (regno >= 20 && regno <= 23) |
| 7511 | || (regno >= 31 && regno <= 39) |
| 7512 | || (regno >= 41 && regno <= 47) |
| 7513 | || (regno >= 67 && regno <= 111)) |
| 7514 | { |
| 7515 | specs[count] = tmpl; |
| 7516 | specs[count++].index = regno; |
| 7517 | } |
| 7518 | } |
| 7519 | } |
| 7520 | else |
| 7521 | { |
| 7522 | UNHANDLED; |
| 7523 | } |
| 7524 | break; |
| 7525 | |
| 7526 | case IA64_RS_ARb: |
| 7527 | if (note == 1) |
| 7528 | { |
| 7529 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 7530 | { |
| 7531 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7532 | if ((regno >= 48 && regno <= 63) |
| 7533 | || (regno >= 112 && regno <= 127)) |
| 7534 | { |
| 7535 | specs[count] = tmpl; |
| 7536 | specs[count++].index = regno; |
| 7537 | } |
| 7538 | } |
| 7539 | } |
| 7540 | else if (note == 0) |
| 7541 | { |
| 7542 | for (i = 48; i < 64; i++) |
| 7543 | { |
| 7544 | specs[count] = tmpl; |
| 7545 | specs[count++].index = i; |
| 7546 | } |
| 7547 | for (i = 112; i < 128; i++) |
| 7548 | { |
| 7549 | specs[count] = tmpl; |
| 7550 | specs[count++].index = i; |
| 7551 | } |
| 7552 | } |
| 7553 | else |
| 7554 | { |
| 7555 | UNHANDLED; |
| 7556 | } |
| 7557 | break; |
| 7558 | |
| 7559 | case IA64_RS_BR: |
| 7560 | if (note != 1) |
| 7561 | { |
| 7562 | UNHANDLED; |
| 7563 | } |
| 7564 | else |
| 7565 | { |
| 7566 | if (rsrc_write) |
| 7567 | { |
| 7568 | for (i = 0; i < idesc->num_outputs; i++) |
| 7569 | if (idesc->operands[i] == IA64_OPND_B1 |
| 7570 | || idesc->operands[i] == IA64_OPND_B2) |
| 7571 | { |
| 7572 | specs[count] = tmpl; |
| 7573 | specs[count++].index = |
| 7574 | CURR_SLOT.opnd[i].X_add_number - REG_BR; |
| 7575 | } |
| 7576 | } |
| 7577 | else |
| 7578 | { |
| 7579 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) |
| 7580 | if (idesc->operands[i] == IA64_OPND_B1 |
| 7581 | || idesc->operands[i] == IA64_OPND_B2) |
| 7582 | { |
| 7583 | specs[count] = tmpl; |
| 7584 | specs[count++].index = |
| 7585 | CURR_SLOT.opnd[i].X_add_number - REG_BR; |
| 7586 | } |
| 7587 | } |
| 7588 | } |
| 7589 | break; |
| 7590 | |
| 7591 | case IA64_RS_CPUID: /* four or more registers */ |
| 7592 | if (note == 3) |
| 7593 | { |
| 7594 | if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) |
| 7595 | { |
| 7596 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7597 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7598 | && KNOWN (regno)) |
| 7599 | { |
| 7600 | specs[count] = tmpl; |
| 7601 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7602 | } |
| 7603 | else |
| 7604 | { |
| 7605 | specs[count] = tmpl; |
| 7606 | specs[count++].specific = 0; |
| 7607 | } |
| 7608 | } |
| 7609 | } |
| 7610 | else |
| 7611 | { |
| 7612 | UNHANDLED; |
| 7613 | } |
| 7614 | break; |
| 7615 | |
| 7616 | case IA64_RS_DBR: /* four or more registers */ |
| 7617 | if (note == 3) |
| 7618 | { |
| 7619 | if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) |
| 7620 | { |
| 7621 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7622 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7623 | && KNOWN (regno)) |
| 7624 | { |
| 7625 | specs[count] = tmpl; |
| 7626 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7627 | } |
| 7628 | else |
| 7629 | { |
| 7630 | specs[count] = tmpl; |
| 7631 | specs[count++].specific = 0; |
| 7632 | } |
| 7633 | } |
| 7634 | } |
| 7635 | else if (note == 0 && !rsrc_write) |
| 7636 | { |
| 7637 | specs[count] = tmpl; |
| 7638 | specs[count++].specific = 0; |
| 7639 | } |
| 7640 | else |
| 7641 | { |
| 7642 | UNHANDLED; |
| 7643 | } |
| 7644 | break; |
| 7645 | |
| 7646 | case IA64_RS_IBR: /* four or more registers */ |
| 7647 | if (note == 3) |
| 7648 | { |
| 7649 | if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) |
| 7650 | { |
| 7651 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7652 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7653 | && KNOWN (regno)) |
| 7654 | { |
| 7655 | specs[count] = tmpl; |
| 7656 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7657 | } |
| 7658 | else |
| 7659 | { |
| 7660 | specs[count] = tmpl; |
| 7661 | specs[count++].specific = 0; |
| 7662 | } |
| 7663 | } |
| 7664 | } |
| 7665 | else |
| 7666 | { |
| 7667 | UNHANDLED; |
| 7668 | } |
| 7669 | break; |
| 7670 | |
| 7671 | case IA64_RS_MSR: |
| 7672 | if (note == 5) |
| 7673 | { |
| 7674 | /* These are implementation specific. Force all references to |
| 7675 | conflict with all other references. */ |
| 7676 | specs[count] = tmpl; |
| 7677 | specs[count++].specific = 0; |
| 7678 | } |
| 7679 | else |
| 7680 | { |
| 7681 | UNHANDLED; |
| 7682 | } |
| 7683 | break; |
| 7684 | |
| 7685 | case IA64_RS_PKR: /* 16 or more registers */ |
| 7686 | if (note == 3 || note == 4) |
| 7687 | { |
| 7688 | if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) |
| 7689 | { |
| 7690 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7691 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7692 | && KNOWN (regno)) |
| 7693 | { |
| 7694 | if (note == 3) |
| 7695 | { |
| 7696 | specs[count] = tmpl; |
| 7697 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7698 | } |
| 7699 | else |
| 7700 | for (i = 0; i < NELEMS (gr_values); i++) |
| 7701 | { |
| 7702 | /* Uses all registers *except* the one in R3. */ |
| 7703 | if ((unsigned)i != (gr_values[regno].value & 0xFF)) |
| 7704 | { |
| 7705 | specs[count] = tmpl; |
| 7706 | specs[count++].index = i; |
| 7707 | } |
| 7708 | } |
| 7709 | } |
| 7710 | else |
| 7711 | { |
| 7712 | specs[count] = tmpl; |
| 7713 | specs[count++].specific = 0; |
| 7714 | } |
| 7715 | } |
| 7716 | } |
| 7717 | else if (note == 0) |
| 7718 | { |
| 7719 | /* probe et al. */ |
| 7720 | specs[count] = tmpl; |
| 7721 | specs[count++].specific = 0; |
| 7722 | } |
| 7723 | break; |
| 7724 | |
| 7725 | case IA64_RS_PMC: /* four or more registers */ |
| 7726 | if (note == 3) |
| 7727 | { |
| 7728 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 |
| 7729 | || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) |
| 7730 | |
| 7731 | { |
| 7732 | int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) |
| 7733 | ? 1 : !rsrc_write); |
| 7734 | int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; |
| 7735 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7736 | && KNOWN (regno)) |
| 7737 | { |
| 7738 | specs[count] = tmpl; |
| 7739 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7740 | } |
| 7741 | else |
| 7742 | { |
| 7743 | specs[count] = tmpl; |
| 7744 | specs[count++].specific = 0; |
| 7745 | } |
| 7746 | } |
| 7747 | } |
| 7748 | else |
| 7749 | { |
| 7750 | UNHANDLED; |
| 7751 | } |
| 7752 | break; |
| 7753 | |
| 7754 | case IA64_RS_PMD: /* four or more registers */ |
| 7755 | if (note == 3) |
| 7756 | { |
| 7757 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) |
| 7758 | { |
| 7759 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7760 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7761 | && KNOWN (regno)) |
| 7762 | { |
| 7763 | specs[count] = tmpl; |
| 7764 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7765 | } |
| 7766 | else |
| 7767 | { |
| 7768 | specs[count] = tmpl; |
| 7769 | specs[count++].specific = 0; |
| 7770 | } |
| 7771 | } |
| 7772 | } |
| 7773 | else |
| 7774 | { |
| 7775 | UNHANDLED; |
| 7776 | } |
| 7777 | break; |
| 7778 | |
| 7779 | case IA64_RS_RR: /* eight registers */ |
| 7780 | if (note == 6) |
| 7781 | { |
| 7782 | if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) |
| 7783 | { |
| 7784 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7785 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7786 | && KNOWN (regno)) |
| 7787 | { |
| 7788 | specs[count] = tmpl; |
| 7789 | specs[count++].index = (gr_values[regno].value >> 61) & 0x7; |
| 7790 | } |
| 7791 | else |
| 7792 | { |
| 7793 | specs[count] = tmpl; |
| 7794 | specs[count++].specific = 0; |
| 7795 | } |
| 7796 | } |
| 7797 | } |
| 7798 | else if (note == 0 && !rsrc_write) |
| 7799 | { |
| 7800 | specs[count] = tmpl; |
| 7801 | specs[count++].specific = 0; |
| 7802 | } |
| 7803 | else |
| 7804 | { |
| 7805 | UNHANDLED; |
| 7806 | } |
| 7807 | break; |
| 7808 | |
| 7809 | case IA64_RS_CR_IRR: |
| 7810 | if (note == 0) |
| 7811 | { |
| 7812 | /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ |
| 7813 | int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; |
| 7814 | if (rsrc_write |
| 7815 | && idesc->operands[1] == IA64_OPND_CR3 |
| 7816 | && regno == CR_IVR) |
| 7817 | { |
| 7818 | for (i = 0; i < 4; i++) |
| 7819 | { |
| 7820 | specs[count] = tmpl; |
| 7821 | specs[count++].index = CR_IRR0 + i; |
| 7822 | } |
| 7823 | } |
| 7824 | } |
| 7825 | else if (note == 1) |
| 7826 | { |
| 7827 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; |
| 7828 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 |
| 7829 | && regno >= CR_IRR0 |
| 7830 | && regno <= CR_IRR3) |
| 7831 | { |
| 7832 | specs[count] = tmpl; |
| 7833 | specs[count++].index = regno; |
| 7834 | } |
| 7835 | } |
| 7836 | else |
| 7837 | { |
| 7838 | UNHANDLED; |
| 7839 | } |
| 7840 | break; |
| 7841 | |
| 7842 | case IA64_RS_CR_LRR: |
| 7843 | if (note != 1) |
| 7844 | { |
| 7845 | UNHANDLED; |
| 7846 | } |
| 7847 | else |
| 7848 | { |
| 7849 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; |
| 7850 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 |
| 7851 | && (regno == CR_LRR0 || regno == CR_LRR1)) |
| 7852 | { |
| 7853 | specs[count] = tmpl; |
| 7854 | specs[count++].index = regno; |
| 7855 | } |
| 7856 | } |
| 7857 | break; |
| 7858 | |
| 7859 | case IA64_RS_CR: |
| 7860 | if (note == 1) |
| 7861 | { |
| 7862 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) |
| 7863 | { |
| 7864 | specs[count] = tmpl; |
| 7865 | specs[count++].index = |
| 7866 | CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; |
| 7867 | } |
| 7868 | } |
| 7869 | else |
| 7870 | { |
| 7871 | UNHANDLED; |
| 7872 | } |
| 7873 | break; |
| 7874 | |
| 7875 | case IA64_RS_FR: |
| 7876 | case IA64_RS_FRb: |
| 7877 | if (note != 1) |
| 7878 | { |
| 7879 | UNHANDLED; |
| 7880 | } |
| 7881 | else if (rsrc_write) |
| 7882 | { |
| 7883 | if (dep->specifier == IA64_RS_FRb |
| 7884 | && idesc->operands[0] == IA64_OPND_F1) |
| 7885 | { |
| 7886 | specs[count] = tmpl; |
| 7887 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; |
| 7888 | } |
| 7889 | } |
| 7890 | else |
| 7891 | { |
| 7892 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) |
| 7893 | { |
| 7894 | if (idesc->operands[i] == IA64_OPND_F2 |
| 7895 | || idesc->operands[i] == IA64_OPND_F3 |
| 7896 | || idesc->operands[i] == IA64_OPND_F4) |
| 7897 | { |
| 7898 | specs[count] = tmpl; |
| 7899 | specs[count++].index = |
| 7900 | CURR_SLOT.opnd[i].X_add_number - REG_FR; |
| 7901 | } |
| 7902 | } |
| 7903 | } |
| 7904 | break; |
| 7905 | |
| 7906 | case IA64_RS_GR: |
| 7907 | if (note == 13) |
| 7908 | { |
| 7909 | /* This reference applies only to the GR whose value is loaded with |
| 7910 | data returned from memory. */ |
| 7911 | specs[count] = tmpl; |
| 7912 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; |
| 7913 | } |
| 7914 | else if (note == 1) |
| 7915 | { |
| 7916 | if (rsrc_write) |
| 7917 | { |
| 7918 | for (i = 0; i < idesc->num_outputs; i++) |
| 7919 | if (idesc->operands[i] == IA64_OPND_R1 |
| 7920 | || idesc->operands[i] == IA64_OPND_R2 |
| 7921 | || idesc->operands[i] == IA64_OPND_R3) |
| 7922 | { |
| 7923 | specs[count] = tmpl; |
| 7924 | specs[count++].index = |
| 7925 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 7926 | } |
| 7927 | if (idesc->flags & IA64_OPCODE_POSTINC) |
| 7928 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 7929 | if (idesc->operands[i] == IA64_OPND_MR3) |
| 7930 | { |
| 7931 | specs[count] = tmpl; |
| 7932 | specs[count++].index = |
| 7933 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 7934 | } |
| 7935 | } |
| 7936 | else |
| 7937 | { |
| 7938 | /* Look for anything that reads a GR. */ |
| 7939 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 7940 | { |
| 7941 | if (idesc->operands[i] == IA64_OPND_MR3 |
| 7942 | || idesc->operands[i] == IA64_OPND_CPUID_R3 |
| 7943 | || idesc->operands[i] == IA64_OPND_DBR_R3 |
| 7944 | || idesc->operands[i] == IA64_OPND_IBR_R3 |
| 7945 | || idesc->operands[i] == IA64_OPND_MSR_R3 |
| 7946 | || idesc->operands[i] == IA64_OPND_PKR_R3 |
| 7947 | || idesc->operands[i] == IA64_OPND_PMC_R3 |
| 7948 | || idesc->operands[i] == IA64_OPND_PMD_R3 |
| 7949 | || idesc->operands[i] == IA64_OPND_RR_R3 |
| 7950 | || ((i >= idesc->num_outputs) |
| 7951 | && (idesc->operands[i] == IA64_OPND_R1 |
| 7952 | || idesc->operands[i] == IA64_OPND_R2 |
| 7953 | || idesc->operands[i] == IA64_OPND_R3 |
| 7954 | /* addl source register. */ |
| 7955 | || idesc->operands[i] == IA64_OPND_R3_2))) |
| 7956 | { |
| 7957 | specs[count] = tmpl; |
| 7958 | specs[count++].index = |
| 7959 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 7960 | } |
| 7961 | } |
| 7962 | } |
| 7963 | } |
| 7964 | else |
| 7965 | { |
| 7966 | UNHANDLED; |
| 7967 | } |
| 7968 | break; |
| 7969 | |
| 7970 | /* This is the same as IA64_RS_PRr, except that the register range is |
| 7971 | from 1 - 15, and there are no rotating register reads/writes here. */ |
| 7972 | case IA64_RS_PR: |
| 7973 | if (note == 0) |
| 7974 | { |
| 7975 | for (i = 1; i < 16; i++) |
| 7976 | { |
| 7977 | specs[count] = tmpl; |
| 7978 | specs[count++].index = i; |
| 7979 | } |
| 7980 | } |
| 7981 | else if (note == 7) |
| 7982 | { |
| 7983 | valueT mask = 0; |
| 7984 | /* Mark only those registers indicated by the mask. */ |
| 7985 | if (rsrc_write) |
| 7986 | { |
| 7987 | mask = CURR_SLOT.opnd[2].X_add_number; |
| 7988 | for (i = 1; i < 16; i++) |
| 7989 | if (mask & ((valueT) 1 << i)) |
| 7990 | { |
| 7991 | specs[count] = tmpl; |
| 7992 | specs[count++].index = i; |
| 7993 | } |
| 7994 | } |
| 7995 | else |
| 7996 | { |
| 7997 | UNHANDLED; |
| 7998 | } |
| 7999 | } |
| 8000 | else if (note == 11) /* note 11 implies note 1 as well */ |
| 8001 | { |
| 8002 | if (rsrc_write) |
| 8003 | { |
| 8004 | for (i = 0; i < idesc->num_outputs; i++) |
| 8005 | { |
| 8006 | if (idesc->operands[i] == IA64_OPND_P1 |
| 8007 | || idesc->operands[i] == IA64_OPND_P2) |
| 8008 | { |
| 8009 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; |
| 8010 | if (regno >= 1 && regno < 16) |
| 8011 | { |
| 8012 | specs[count] = tmpl; |
| 8013 | specs[count++].index = regno; |
| 8014 | } |
| 8015 | } |
| 8016 | } |
| 8017 | } |
| 8018 | else |
| 8019 | { |
| 8020 | UNHANDLED; |
| 8021 | } |
| 8022 | } |
| 8023 | else if (note == 12) |
| 8024 | { |
| 8025 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) |
| 8026 | { |
| 8027 | specs[count] = tmpl; |
| 8028 | specs[count++].index = CURR_SLOT.qp_regno; |
| 8029 | } |
| 8030 | } |
| 8031 | else if (note == 1) |
| 8032 | { |
| 8033 | if (rsrc_write) |
| 8034 | { |
| 8035 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
| 8036 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
| 8037 | int or_andcm = strstr (idesc->name, "or.andcm") != NULL; |
| 8038 | int and_orcm = strstr (idesc->name, "and.orcm") != NULL; |
| 8039 | |
| 8040 | if ((idesc->operands[0] == IA64_OPND_P1 |
| 8041 | || idesc->operands[0] == IA64_OPND_P2) |
| 8042 | && p1 >= 1 && p1 < 16) |
| 8043 | { |
| 8044 | specs[count] = tmpl; |
| 8045 | specs[count].cmp_type = |
| 8046 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
| 8047 | specs[count++].index = p1; |
| 8048 | } |
| 8049 | if ((idesc->operands[1] == IA64_OPND_P1 |
| 8050 | || idesc->operands[1] == IA64_OPND_P2) |
| 8051 | && p2 >= 1 && p2 < 16) |
| 8052 | { |
| 8053 | specs[count] = tmpl; |
| 8054 | specs[count].cmp_type = |
| 8055 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
| 8056 | specs[count++].index = p2; |
| 8057 | } |
| 8058 | } |
| 8059 | else |
| 8060 | { |
| 8061 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) |
| 8062 | { |
| 8063 | specs[count] = tmpl; |
| 8064 | specs[count++].index = CURR_SLOT.qp_regno; |
| 8065 | } |
| 8066 | if (idesc->operands[1] == IA64_OPND_PR) |
| 8067 | { |
| 8068 | for (i = 1; i < 16; i++) |
| 8069 | { |
| 8070 | specs[count] = tmpl; |
| 8071 | specs[count++].index = i; |
| 8072 | } |
| 8073 | } |
| 8074 | } |
| 8075 | } |
| 8076 | else |
| 8077 | { |
| 8078 | UNHANDLED; |
| 8079 | } |
| 8080 | break; |
| 8081 | |
| 8082 | /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are |
| 8083 | simplified cases of this. */ |
| 8084 | case IA64_RS_PRr: |
| 8085 | if (note == 0) |
| 8086 | { |
| 8087 | for (i = 16; i < 63; i++) |
| 8088 | { |
| 8089 | specs[count] = tmpl; |
| 8090 | specs[count++].index = i; |
| 8091 | } |
| 8092 | } |
| 8093 | else if (note == 7) |
| 8094 | { |
| 8095 | valueT mask = 0; |
| 8096 | /* Mark only those registers indicated by the mask. */ |
| 8097 | if (rsrc_write |
| 8098 | && idesc->operands[0] == IA64_OPND_PR) |
| 8099 | { |
| 8100 | mask = CURR_SLOT.opnd[2].X_add_number; |
| 8101 | if (mask & ((valueT) 1 << 16)) |
| 8102 | for (i = 16; i < 63; i++) |
| 8103 | { |
| 8104 | specs[count] = tmpl; |
| 8105 | specs[count++].index = i; |
| 8106 | } |
| 8107 | } |
| 8108 | else if (rsrc_write |
| 8109 | && idesc->operands[0] == IA64_OPND_PR_ROT) |
| 8110 | { |
| 8111 | for (i = 16; i < 63; i++) |
| 8112 | { |
| 8113 | specs[count] = tmpl; |
| 8114 | specs[count++].index = i; |
| 8115 | } |
| 8116 | } |
| 8117 | else |
| 8118 | { |
| 8119 | UNHANDLED; |
| 8120 | } |
| 8121 | } |
| 8122 | else if (note == 11) /* note 11 implies note 1 as well */ |
| 8123 | { |
| 8124 | if (rsrc_write) |
| 8125 | { |
| 8126 | for (i = 0; i < idesc->num_outputs; i++) |
| 8127 | { |
| 8128 | if (idesc->operands[i] == IA64_OPND_P1 |
| 8129 | || idesc->operands[i] == IA64_OPND_P2) |
| 8130 | { |
| 8131 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; |
| 8132 | if (regno >= 16 && regno < 63) |
| 8133 | { |
| 8134 | specs[count] = tmpl; |
| 8135 | specs[count++].index = regno; |
| 8136 | } |
| 8137 | } |
| 8138 | } |
| 8139 | } |
| 8140 | else |
| 8141 | { |
| 8142 | UNHANDLED; |
| 8143 | } |
| 8144 | } |
| 8145 | else if (note == 12) |
| 8146 | { |
| 8147 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
| 8148 | { |
| 8149 | specs[count] = tmpl; |
| 8150 | specs[count++].index = CURR_SLOT.qp_regno; |
| 8151 | } |
| 8152 | } |
| 8153 | else if (note == 1) |
| 8154 | { |
| 8155 | if (rsrc_write) |
| 8156 | { |
| 8157 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
| 8158 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
| 8159 | int or_andcm = strstr (idesc->name, "or.andcm") != NULL; |
| 8160 | int and_orcm = strstr (idesc->name, "and.orcm") != NULL; |
| 8161 | |
| 8162 | if ((idesc->operands[0] == IA64_OPND_P1 |
| 8163 | || idesc->operands[0] == IA64_OPND_P2) |
| 8164 | && p1 >= 16 && p1 < 63) |
| 8165 | { |
| 8166 | specs[count] = tmpl; |
| 8167 | specs[count].cmp_type = |
| 8168 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
| 8169 | specs[count++].index = p1; |
| 8170 | } |
| 8171 | if ((idesc->operands[1] == IA64_OPND_P1 |
| 8172 | || idesc->operands[1] == IA64_OPND_P2) |
| 8173 | && p2 >= 16 && p2 < 63) |
| 8174 | { |
| 8175 | specs[count] = tmpl; |
| 8176 | specs[count].cmp_type = |
| 8177 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
| 8178 | specs[count++].index = p2; |
| 8179 | } |
| 8180 | } |
| 8181 | else |
| 8182 | { |
| 8183 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
| 8184 | { |
| 8185 | specs[count] = tmpl; |
| 8186 | specs[count++].index = CURR_SLOT.qp_regno; |
| 8187 | } |
| 8188 | if (idesc->operands[1] == IA64_OPND_PR) |
| 8189 | { |
| 8190 | for (i = 16; i < 63; i++) |
| 8191 | { |
| 8192 | specs[count] = tmpl; |
| 8193 | specs[count++].index = i; |
| 8194 | } |
| 8195 | } |
| 8196 | } |
| 8197 | } |
| 8198 | else |
| 8199 | { |
| 8200 | UNHANDLED; |
| 8201 | } |
| 8202 | break; |
| 8203 | |
| 8204 | case IA64_RS_PSR: |
| 8205 | /* Verify that the instruction is using the PSR bit indicated in |
| 8206 | dep->regindex. */ |
| 8207 | if (note == 0) |
| 8208 | { |
| 8209 | if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) |
| 8210 | { |
| 8211 | if (dep->regindex < 6) |
| 8212 | { |
| 8213 | specs[count++] = tmpl; |
| 8214 | } |
| 8215 | } |
| 8216 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) |
| 8217 | { |
| 8218 | if (dep->regindex < 32 |
| 8219 | || dep->regindex == 35 |
| 8220 | || dep->regindex == 36 |
| 8221 | || (!rsrc_write && dep->regindex == PSR_CPL)) |
| 8222 | { |
| 8223 | specs[count++] = tmpl; |
| 8224 | } |
| 8225 | } |
| 8226 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) |
| 8227 | { |
| 8228 | if (dep->regindex < 32 |
| 8229 | || dep->regindex == 35 |
| 8230 | || dep->regindex == 36 |
| 8231 | || (rsrc_write && dep->regindex == PSR_CPL)) |
| 8232 | { |
| 8233 | specs[count++] = tmpl; |
| 8234 | } |
| 8235 | } |
| 8236 | else |
| 8237 | { |
| 8238 | /* Several PSR bits have very specific dependencies. */ |
| 8239 | switch (dep->regindex) |
| 8240 | { |
| 8241 | default: |
| 8242 | specs[count++] = tmpl; |
| 8243 | break; |
| 8244 | case PSR_IC: |
| 8245 | if (rsrc_write) |
| 8246 | { |
| 8247 | specs[count++] = tmpl; |
| 8248 | } |
| 8249 | else |
| 8250 | { |
| 8251 | /* Only certain CR accesses use PSR.ic */ |
| 8252 | if (idesc->operands[0] == IA64_OPND_CR3 |
| 8253 | || idesc->operands[1] == IA64_OPND_CR3) |
| 8254 | { |
| 8255 | int index = |
| 8256 | ((idesc->operands[0] == IA64_OPND_CR3) |
| 8257 | ? 0 : 1); |
| 8258 | int regno = |
| 8259 | CURR_SLOT.opnd[index].X_add_number - REG_CR; |
| 8260 | |
| 8261 | switch (regno) |
| 8262 | { |
| 8263 | default: |
| 8264 | break; |
| 8265 | case CR_ITIR: |
| 8266 | case CR_IFS: |
| 8267 | case CR_IIM: |
| 8268 | case CR_IIP: |
| 8269 | case CR_IPSR: |
| 8270 | case CR_ISR: |
| 8271 | case CR_IFA: |
| 8272 | case CR_IHA: |
| 8273 | case CR_IIPA: |
| 8274 | specs[count++] = tmpl; |
| 8275 | break; |
| 8276 | } |
| 8277 | } |
| 8278 | } |
| 8279 | break; |
| 8280 | case PSR_CPL: |
| 8281 | if (rsrc_write) |
| 8282 | { |
| 8283 | specs[count++] = tmpl; |
| 8284 | } |
| 8285 | else |
| 8286 | { |
| 8287 | /* Only some AR accesses use cpl */ |
| 8288 | if (idesc->operands[0] == IA64_OPND_AR3 |
| 8289 | || idesc->operands[1] == IA64_OPND_AR3) |
| 8290 | { |
| 8291 | int index = |
| 8292 | ((idesc->operands[0] == IA64_OPND_AR3) |
| 8293 | ? 0 : 1); |
| 8294 | int regno = |
| 8295 | CURR_SLOT.opnd[index].X_add_number - REG_AR; |
| 8296 | |
| 8297 | if (regno == AR_ITC |
| 8298 | || (index == 0 |
| 8299 | && (regno == AR_ITC |
| 8300 | || regno == AR_RSC |
| 8301 | || (regno >= AR_K0 |
| 8302 | && regno <= AR_K7)))) |
| 8303 | { |
| 8304 | specs[count++] = tmpl; |
| 8305 | } |
| 8306 | } |
| 8307 | else |
| 8308 | { |
| 8309 | specs[count++] = tmpl; |
| 8310 | } |
| 8311 | break; |
| 8312 | } |
| 8313 | } |
| 8314 | } |
| 8315 | } |
| 8316 | else if (note == 7) |
| 8317 | { |
| 8318 | valueT mask = 0; |
| 8319 | if (idesc->operands[0] == IA64_OPND_IMMU24) |
| 8320 | { |
| 8321 | mask = CURR_SLOT.opnd[0].X_add_number; |
| 8322 | } |
| 8323 | else |
| 8324 | { |
| 8325 | UNHANDLED; |
| 8326 | } |
| 8327 | if (mask & ((valueT) 1 << dep->regindex)) |
| 8328 | { |
| 8329 | specs[count++] = tmpl; |
| 8330 | } |
| 8331 | } |
| 8332 | else if (note == 8) |
| 8333 | { |
| 8334 | int min = dep->regindex == PSR_DFL ? 2 : 32; |
| 8335 | int max = dep->regindex == PSR_DFL ? 31 : 127; |
| 8336 | /* dfh is read on FR32-127; dfl is read on FR2-31 */ |
| 8337 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 8338 | { |
| 8339 | if (idesc->operands[i] == IA64_OPND_F1 |
| 8340 | || idesc->operands[i] == IA64_OPND_F2 |
| 8341 | || idesc->operands[i] == IA64_OPND_F3 |
| 8342 | || idesc->operands[i] == IA64_OPND_F4) |
| 8343 | { |
| 8344 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; |
| 8345 | if (reg >= min && reg <= max) |
| 8346 | { |
| 8347 | specs[count++] = tmpl; |
| 8348 | } |
| 8349 | } |
| 8350 | } |
| 8351 | } |
| 8352 | else if (note == 9) |
| 8353 | { |
| 8354 | int min = dep->regindex == PSR_MFL ? 2 : 32; |
| 8355 | int max = dep->regindex == PSR_MFL ? 31 : 127; |
| 8356 | /* mfh is read on writes to FR32-127; mfl is read on writes to |
| 8357 | FR2-31 */ |
| 8358 | for (i = 0; i < idesc->num_outputs; i++) |
| 8359 | { |
| 8360 | if (idesc->operands[i] == IA64_OPND_F1) |
| 8361 | { |
| 8362 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; |
| 8363 | if (reg >= min && reg <= max) |
| 8364 | { |
| 8365 | specs[count++] = tmpl; |
| 8366 | } |
| 8367 | } |
| 8368 | } |
| 8369 | } |
| 8370 | else if (note == 10) |
| 8371 | { |
| 8372 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 8373 | { |
| 8374 | if (idesc->operands[i] == IA64_OPND_R1 |
| 8375 | || idesc->operands[i] == IA64_OPND_R2 |
| 8376 | || idesc->operands[i] == IA64_OPND_R3) |
| 8377 | { |
| 8378 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 8379 | if (regno >= 16 && regno <= 31) |
| 8380 | { |
| 8381 | specs[count++] = tmpl; |
| 8382 | } |
| 8383 | } |
| 8384 | } |
| 8385 | } |
| 8386 | else |
| 8387 | { |
| 8388 | UNHANDLED; |
| 8389 | } |
| 8390 | break; |
| 8391 | |
| 8392 | case IA64_RS_AR_FPSR: |
| 8393 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 8394 | { |
| 8395 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 8396 | if (regno == AR_FPSR) |
| 8397 | { |
| 8398 | specs[count++] = tmpl; |
| 8399 | } |
| 8400 | } |
| 8401 | else |
| 8402 | { |
| 8403 | specs[count++] = tmpl; |
| 8404 | } |
| 8405 | break; |
| 8406 | |
| 8407 | case IA64_RS_ARX: |
| 8408 | /* Handle all AR[REG] resources */ |
| 8409 | if (note == 0 || note == 1) |
| 8410 | { |
| 8411 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 8412 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 |
| 8413 | && regno == dep->regindex) |
| 8414 | { |
| 8415 | specs[count++] = tmpl; |
| 8416 | } |
| 8417 | /* other AR[REG] resources may be affected by AR accesses */ |
| 8418 | else if (idesc->operands[0] == IA64_OPND_AR3) |
| 8419 | { |
| 8420 | /* AR[] writes */ |
| 8421 | regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; |
| 8422 | switch (dep->regindex) |
| 8423 | { |
| 8424 | default: |
| 8425 | break; |
| 8426 | case AR_BSP: |
| 8427 | case AR_RNAT: |
| 8428 | if (regno == AR_BSPSTORE) |
| 8429 | { |
| 8430 | specs[count++] = tmpl; |
| 8431 | } |
| 8432 | case AR_RSC: |
| 8433 | if (!rsrc_write && |
| 8434 | (regno == AR_BSPSTORE |
| 8435 | || regno == AR_RNAT)) |
| 8436 | { |
| 8437 | specs[count++] = tmpl; |
| 8438 | } |
| 8439 | break; |
| 8440 | } |
| 8441 | } |
| 8442 | else if (idesc->operands[1] == IA64_OPND_AR3) |
| 8443 | { |
| 8444 | /* AR[] reads */ |
| 8445 | regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; |
| 8446 | switch (dep->regindex) |
| 8447 | { |
| 8448 | default: |
| 8449 | break; |
| 8450 | case AR_RSC: |
| 8451 | if (regno == AR_BSPSTORE || regno == AR_RNAT) |
| 8452 | { |
| 8453 | specs[count++] = tmpl; |
| 8454 | } |
| 8455 | break; |
| 8456 | } |
| 8457 | } |
| 8458 | else |
| 8459 | { |
| 8460 | specs[count++] = tmpl; |
| 8461 | } |
| 8462 | } |
| 8463 | else |
| 8464 | { |
| 8465 | UNHANDLED; |
| 8466 | } |
| 8467 | break; |
| 8468 | |
| 8469 | case IA64_RS_CRX: |
| 8470 | /* Handle all CR[REG] resources */ |
| 8471 | if (note == 0 || note == 1) |
| 8472 | { |
| 8473 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) |
| 8474 | { |
| 8475 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; |
| 8476 | if (regno == dep->regindex) |
| 8477 | { |
| 8478 | specs[count++] = tmpl; |
| 8479 | } |
| 8480 | else if (!rsrc_write) |
| 8481 | { |
| 8482 | /* Reads from CR[IVR] affect other resources. */ |
| 8483 | if (regno == CR_IVR) |
| 8484 | { |
| 8485 | if ((dep->regindex >= CR_IRR0 |
| 8486 | && dep->regindex <= CR_IRR3) |
| 8487 | || dep->regindex == CR_TPR) |
| 8488 | { |
| 8489 | specs[count++] = tmpl; |
| 8490 | } |
| 8491 | } |
| 8492 | } |
| 8493 | } |
| 8494 | else |
| 8495 | { |
| 8496 | specs[count++] = tmpl; |
| 8497 | } |
| 8498 | } |
| 8499 | else |
| 8500 | { |
| 8501 | UNHANDLED; |
| 8502 | } |
| 8503 | break; |
| 8504 | |
| 8505 | case IA64_RS_INSERVICE: |
| 8506 | /* look for write of EOI (67) or read of IVR (65) */ |
| 8507 | if ((idesc->operands[0] == IA64_OPND_CR3 |
| 8508 | && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) |
| 8509 | || (idesc->operands[1] == IA64_OPND_CR3 |
| 8510 | && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) |
| 8511 | { |
| 8512 | specs[count++] = tmpl; |
| 8513 | } |
| 8514 | break; |
| 8515 | |
| 8516 | case IA64_RS_GR0: |
| 8517 | if (note == 1) |
| 8518 | { |
| 8519 | specs[count++] = tmpl; |
| 8520 | } |
| 8521 | else |
| 8522 | { |
| 8523 | UNHANDLED; |
| 8524 | } |
| 8525 | break; |
| 8526 | |
| 8527 | case IA64_RS_CFM: |
| 8528 | if (note != 2) |
| 8529 | { |
| 8530 | specs[count++] = tmpl; |
| 8531 | } |
| 8532 | else |
| 8533 | { |
| 8534 | /* Check if any of the registers accessed are in the rotating region. |
| 8535 | mov to/from pr accesses CFM only when qp_regno is in the rotating |
| 8536 | region */ |
| 8537 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 8538 | { |
| 8539 | if (idesc->operands[i] == IA64_OPND_R1 |
| 8540 | || idesc->operands[i] == IA64_OPND_R2 |
| 8541 | || idesc->operands[i] == IA64_OPND_R3) |
| 8542 | { |
| 8543 | int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 8544 | /* Assumes that md.rot.num_regs is always valid */ |
| 8545 | if (md.rot.num_regs > 0 |
| 8546 | && num > 31 |
| 8547 | && num < 31 + md.rot.num_regs) |
| 8548 | { |
| 8549 | specs[count] = tmpl; |
| 8550 | specs[count++].specific = 0; |
| 8551 | } |
| 8552 | } |
| 8553 | else if (idesc->operands[i] == IA64_OPND_F1 |
| 8554 | || idesc->operands[i] == IA64_OPND_F2 |
| 8555 | || idesc->operands[i] == IA64_OPND_F3 |
| 8556 | || idesc->operands[i] == IA64_OPND_F4) |
| 8557 | { |
| 8558 | int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; |
| 8559 | if (num > 31) |
| 8560 | { |
| 8561 | specs[count] = tmpl; |
| 8562 | specs[count++].specific = 0; |
| 8563 | } |
| 8564 | } |
| 8565 | else if (idesc->operands[i] == IA64_OPND_P1 |
| 8566 | || idesc->operands[i] == IA64_OPND_P2) |
| 8567 | { |
| 8568 | int num = CURR_SLOT.opnd[i].X_add_number - REG_P; |
| 8569 | if (num > 15) |
| 8570 | { |
| 8571 | specs[count] = tmpl; |
| 8572 | specs[count++].specific = 0; |
| 8573 | } |
| 8574 | } |
| 8575 | } |
| 8576 | if (CURR_SLOT.qp_regno > 15) |
| 8577 | { |
| 8578 | specs[count] = tmpl; |
| 8579 | specs[count++].specific = 0; |
| 8580 | } |
| 8581 | } |
| 8582 | break; |
| 8583 | |
| 8584 | /* This is the same as IA64_RS_PRr, except simplified to account for |
| 8585 | the fact that there is only one register. */ |
| 8586 | case IA64_RS_PR63: |
| 8587 | if (note == 0) |
| 8588 | { |
| 8589 | specs[count++] = tmpl; |
| 8590 | } |
| 8591 | else if (note == 7) |
| 8592 | { |
| 8593 | valueT mask = 0; |
| 8594 | if (idesc->operands[2] == IA64_OPND_IMM17) |
| 8595 | mask = CURR_SLOT.opnd[2].X_add_number; |
| 8596 | if (mask & ((valueT) 1 << 63)) |
| 8597 | specs[count++] = tmpl; |
| 8598 | } |
| 8599 | else if (note == 11) |
| 8600 | { |
| 8601 | if ((idesc->operands[0] == IA64_OPND_P1 |
| 8602 | && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) |
| 8603 | || (idesc->operands[1] == IA64_OPND_P2 |
| 8604 | && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) |
| 8605 | { |
| 8606 | specs[count++] = tmpl; |
| 8607 | } |
| 8608 | } |
| 8609 | else if (note == 12) |
| 8610 | { |
| 8611 | if (CURR_SLOT.qp_regno == 63) |
| 8612 | { |
| 8613 | specs[count++] = tmpl; |
| 8614 | } |
| 8615 | } |
| 8616 | else if (note == 1) |
| 8617 | { |
| 8618 | if (rsrc_write) |
| 8619 | { |
| 8620 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
| 8621 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
| 8622 | int or_andcm = strstr (idesc->name, "or.andcm") != NULL; |
| 8623 | int and_orcm = strstr (idesc->name, "and.orcm") != NULL; |
| 8624 | |
| 8625 | if (p1 == 63 |
| 8626 | && (idesc->operands[0] == IA64_OPND_P1 |
| 8627 | || idesc->operands[0] == IA64_OPND_P2)) |
| 8628 | { |
| 8629 | specs[count] = tmpl; |
| 8630 | specs[count++].cmp_type = |
| 8631 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
| 8632 | } |
| 8633 | if (p2 == 63 |
| 8634 | && (idesc->operands[1] == IA64_OPND_P1 |
| 8635 | || idesc->operands[1] == IA64_OPND_P2)) |
| 8636 | { |
| 8637 | specs[count] = tmpl; |
| 8638 | specs[count++].cmp_type = |
| 8639 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
| 8640 | } |
| 8641 | } |
| 8642 | else |
| 8643 | { |
| 8644 | if (CURR_SLOT.qp_regno == 63) |
| 8645 | { |
| 8646 | specs[count++] = tmpl; |
| 8647 | } |
| 8648 | } |
| 8649 | } |
| 8650 | else |
| 8651 | { |
| 8652 | UNHANDLED; |
| 8653 | } |
| 8654 | break; |
| 8655 | |
| 8656 | case IA64_RS_RSE: |
| 8657 | /* FIXME we can identify some individual RSE written resources, but RSE |
| 8658 | read resources have not yet been completely identified, so for now |
| 8659 | treat RSE as a single resource */ |
| 8660 | if (strncmp (idesc->name, "mov", 3) == 0) |
| 8661 | { |
| 8662 | if (rsrc_write) |
| 8663 | { |
| 8664 | if (idesc->operands[0] == IA64_OPND_AR3 |
| 8665 | && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) |
| 8666 | { |
| 8667 | specs[count] = tmpl; |
| 8668 | specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ |
| 8669 | } |
| 8670 | } |
| 8671 | else |
| 8672 | { |
| 8673 | if (idesc->operands[0] == IA64_OPND_AR3) |
| 8674 | { |
| 8675 | if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE |
| 8676 | || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) |
| 8677 | { |
| 8678 | specs[count++] = tmpl; |
| 8679 | } |
| 8680 | } |
| 8681 | else if (idesc->operands[1] == IA64_OPND_AR3) |
| 8682 | { |
| 8683 | if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP |
| 8684 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE |
| 8685 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) |
| 8686 | { |
| 8687 | specs[count++] = tmpl; |
| 8688 | } |
| 8689 | } |
| 8690 | } |
| 8691 | } |
| 8692 | else |
| 8693 | { |
| 8694 | specs[count++] = tmpl; |
| 8695 | } |
| 8696 | break; |
| 8697 | |
| 8698 | case IA64_RS_ANY: |
| 8699 | /* FIXME -- do any of these need to be non-specific? */ |
| 8700 | specs[count++] = tmpl; |
| 8701 | break; |
| 8702 | |
| 8703 | default: |
| 8704 | as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); |
| 8705 | break; |
| 8706 | } |
| 8707 | |
| 8708 | return count; |
| 8709 | } |
| 8710 | |
| 8711 | /* Clear branch flags on marked resources. This breaks the link between the |
| 8712 | QP of the marking instruction and a subsequent branch on the same QP. */ |
| 8713 | |
| 8714 | static void |
| 8715 | clear_qp_branch_flag (mask) |
| 8716 | valueT mask; |
| 8717 | { |
| 8718 | int i; |
| 8719 | for (i = 0; i < regdepslen; i++) |
| 8720 | { |
| 8721 | valueT bit = ((valueT) 1 << regdeps[i].qp_regno); |
| 8722 | if ((bit & mask) != 0) |
| 8723 | { |
| 8724 | regdeps[i].link_to_qp_branch = 0; |
| 8725 | } |
| 8726 | } |
| 8727 | } |
| 8728 | |
| 8729 | /* Remove any mutexes which contain any of the PRs indicated in the mask. |
| 8730 | |
| 8731 | Any changes to a PR clears the mutex relations which include that PR. */ |
| 8732 | |
| 8733 | static void |
| 8734 | clear_qp_mutex (mask) |
| 8735 | valueT mask; |
| 8736 | { |
| 8737 | int i; |
| 8738 | |
| 8739 | i = 0; |
| 8740 | while (i < qp_mutexeslen) |
| 8741 | { |
| 8742 | if ((qp_mutexes[i].prmask & mask) != 0) |
| 8743 | { |
| 8744 | if (md.debug_dv) |
| 8745 | { |
| 8746 | fprintf (stderr, " Clearing mutex relation"); |
| 8747 | print_prmask (qp_mutexes[i].prmask); |
| 8748 | fprintf (stderr, "\n"); |
| 8749 | } |
| 8750 | qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; |
| 8751 | } |
| 8752 | else |
| 8753 | ++i; |
| 8754 | } |
| 8755 | } |
| 8756 | |
| 8757 | /* Clear implies relations which contain PRs in the given masks. |
| 8758 | P1_MASK indicates the source of the implies relation, while P2_MASK |
| 8759 | indicates the implied PR. */ |
| 8760 | |
| 8761 | static void |
| 8762 | clear_qp_implies (p1_mask, p2_mask) |
| 8763 | valueT p1_mask; |
| 8764 | valueT p2_mask; |
| 8765 | { |
| 8766 | int i; |
| 8767 | |
| 8768 | i = 0; |
| 8769 | while (i < qp_implieslen) |
| 8770 | { |
| 8771 | if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 |
| 8772 | || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) |
| 8773 | { |
| 8774 | if (md.debug_dv) |
| 8775 | fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", |
| 8776 | qp_implies[i].p1, qp_implies[i].p2); |
| 8777 | qp_implies[i] = qp_implies[--qp_implieslen]; |
| 8778 | } |
| 8779 | else |
| 8780 | ++i; |
| 8781 | } |
| 8782 | } |
| 8783 | |
| 8784 | /* Add the PRs specified to the list of implied relations. */ |
| 8785 | |
| 8786 | static void |
| 8787 | add_qp_imply (p1, p2) |
| 8788 | int p1, p2; |
| 8789 | { |
| 8790 | valueT mask; |
| 8791 | valueT bit; |
| 8792 | int i; |
| 8793 | |
| 8794 | /* p0 is not meaningful here. */ |
| 8795 | if (p1 == 0 || p2 == 0) |
| 8796 | abort (); |
| 8797 | |
| 8798 | if (p1 == p2) |
| 8799 | return; |
| 8800 | |
| 8801 | /* If it exists already, ignore it. */ |
| 8802 | for (i = 0; i < qp_implieslen; i++) |
| 8803 | { |
| 8804 | if (qp_implies[i].p1 == p1 |
| 8805 | && qp_implies[i].p2 == p2 |
| 8806 | && qp_implies[i].path == md.path |
| 8807 | && !qp_implies[i].p2_branched) |
| 8808 | return; |
| 8809 | } |
| 8810 | |
| 8811 | if (qp_implieslen == qp_impliestotlen) |
| 8812 | { |
| 8813 | qp_impliestotlen += 20; |
| 8814 | qp_implies = (struct qp_imply *) |
| 8815 | xrealloc ((void *) qp_implies, |
| 8816 | qp_impliestotlen * sizeof (struct qp_imply)); |
| 8817 | } |
| 8818 | if (md.debug_dv) |
| 8819 | fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); |
| 8820 | qp_implies[qp_implieslen].p1 = p1; |
| 8821 | qp_implies[qp_implieslen].p2 = p2; |
| 8822 | qp_implies[qp_implieslen].path = md.path; |
| 8823 | qp_implies[qp_implieslen++].p2_branched = 0; |
| 8824 | |
| 8825 | /* Add in the implied transitive relations; for everything that p2 implies, |
| 8826 | make p1 imply that, too; for everything that implies p1, make it imply p2 |
| 8827 | as well. */ |
| 8828 | for (i = 0; i < qp_implieslen; i++) |
| 8829 | { |
| 8830 | if (qp_implies[i].p1 == p2) |
| 8831 | add_qp_imply (p1, qp_implies[i].p2); |
| 8832 | if (qp_implies[i].p2 == p1) |
| 8833 | add_qp_imply (qp_implies[i].p1, p2); |
| 8834 | } |
| 8835 | /* Add in mutex relations implied by this implies relation; for each mutex |
| 8836 | relation containing p2, duplicate it and replace p2 with p1. */ |
| 8837 | bit = (valueT) 1 << p1; |
| 8838 | mask = (valueT) 1 << p2; |
| 8839 | for (i = 0; i < qp_mutexeslen; i++) |
| 8840 | { |
| 8841 | if (qp_mutexes[i].prmask & mask) |
| 8842 | add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); |
| 8843 | } |
| 8844 | } |
| 8845 | |
| 8846 | /* Add the PRs specified in the mask to the mutex list; this means that only |
| 8847 | one of the PRs can be true at any time. PR0 should never be included in |
| 8848 | the mask. */ |
| 8849 | |
| 8850 | static void |
| 8851 | add_qp_mutex (mask) |
| 8852 | valueT mask; |
| 8853 | { |
| 8854 | if (mask & 0x1) |
| 8855 | abort (); |
| 8856 | |
| 8857 | if (qp_mutexeslen == qp_mutexestotlen) |
| 8858 | { |
| 8859 | qp_mutexestotlen += 20; |
| 8860 | qp_mutexes = (struct qpmutex *) |
| 8861 | xrealloc ((void *) qp_mutexes, |
| 8862 | qp_mutexestotlen * sizeof (struct qpmutex)); |
| 8863 | } |
| 8864 | if (md.debug_dv) |
| 8865 | { |
| 8866 | fprintf (stderr, " Registering mutex on"); |
| 8867 | print_prmask (mask); |
| 8868 | fprintf (stderr, "\n"); |
| 8869 | } |
| 8870 | qp_mutexes[qp_mutexeslen].path = md.path; |
| 8871 | qp_mutexes[qp_mutexeslen++].prmask = mask; |
| 8872 | } |
| 8873 | |
| 8874 | static int |
| 8875 | has_suffix_p (name, suffix) |
| 8876 | const char *name; |
| 8877 | const char *suffix; |
| 8878 | { |
| 8879 | size_t namelen = strlen (name); |
| 8880 | size_t sufflen = strlen (suffix); |
| 8881 | |
| 8882 | if (namelen <= sufflen) |
| 8883 | return 0; |
| 8884 | return strcmp (name + namelen - sufflen, suffix) == 0; |
| 8885 | } |
| 8886 | |
| 8887 | static void |
| 8888 | clear_register_values () |
| 8889 | { |
| 8890 | int i; |
| 8891 | if (md.debug_dv) |
| 8892 | fprintf (stderr, " Clearing register values\n"); |
| 8893 | for (i = 1; i < NELEMS (gr_values); i++) |
| 8894 | gr_values[i].known = 0; |
| 8895 | } |
| 8896 | |
| 8897 | /* Keep track of register values/changes which affect DV tracking. |
| 8898 | |
| 8899 | optimization note: should add a flag to classes of insns where otherwise we |
| 8900 | have to examine a group of strings to identify them. */ |
| 8901 | |
| 8902 | static void |
| 8903 | note_register_values (idesc) |
| 8904 | struct ia64_opcode *idesc; |
| 8905 | { |
| 8906 | valueT qp_changemask = 0; |
| 8907 | int i; |
| 8908 | |
| 8909 | /* Invalidate values for registers being written to. */ |
| 8910 | for (i = 0; i < idesc->num_outputs; i++) |
| 8911 | { |
| 8912 | if (idesc->operands[i] == IA64_OPND_R1 |
| 8913 | || idesc->operands[i] == IA64_OPND_R2 |
| 8914 | || idesc->operands[i] == IA64_OPND_R3) |
| 8915 | { |
| 8916 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 8917 | if (regno > 0 && regno < NELEMS (gr_values)) |
| 8918 | gr_values[regno].known = 0; |
| 8919 | } |
| 8920 | else if (idesc->operands[i] == IA64_OPND_R3_2) |
| 8921 | { |
| 8922 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 8923 | if (regno > 0 && regno < 4) |
| 8924 | gr_values[regno].known = 0; |
| 8925 | } |
| 8926 | else if (idesc->operands[i] == IA64_OPND_P1 |
| 8927 | || idesc->operands[i] == IA64_OPND_P2) |
| 8928 | { |
| 8929 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; |
| 8930 | qp_changemask |= (valueT) 1 << regno; |
| 8931 | } |
| 8932 | else if (idesc->operands[i] == IA64_OPND_PR) |
| 8933 | { |
| 8934 | if (idesc->operands[2] & (valueT) 0x10000) |
| 8935 | qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; |
| 8936 | else |
| 8937 | qp_changemask = idesc->operands[2]; |
| 8938 | break; |
| 8939 | } |
| 8940 | else if (idesc->operands[i] == IA64_OPND_PR_ROT) |
| 8941 | { |
| 8942 | if (idesc->operands[1] & ((valueT) 1 << 43)) |
| 8943 | qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; |
| 8944 | else |
| 8945 | qp_changemask = idesc->operands[1]; |
| 8946 | qp_changemask &= ~(valueT) 0xFFFF; |
| 8947 | break; |
| 8948 | } |
| 8949 | } |
| 8950 | |
| 8951 | /* Always clear qp branch flags on any PR change. */ |
| 8952 | /* FIXME there may be exceptions for certain compares. */ |
| 8953 | clear_qp_branch_flag (qp_changemask); |
| 8954 | |
| 8955 | /* Invalidate rotating registers on insns which affect RRBs in CFM. */ |
| 8956 | if (idesc->flags & IA64_OPCODE_MOD_RRBS) |
| 8957 | { |
| 8958 | qp_changemask |= ~(valueT) 0xFFFF; |
| 8959 | if (strcmp (idesc->name, "clrrrb.pr") != 0) |
| 8960 | { |
| 8961 | for (i = 32; i < 32 + md.rot.num_regs; i++) |
| 8962 | gr_values[i].known = 0; |
| 8963 | } |
| 8964 | clear_qp_mutex (qp_changemask); |
| 8965 | clear_qp_implies (qp_changemask, qp_changemask); |
| 8966 | } |
| 8967 | /* After a call, all register values are undefined, except those marked |
| 8968 | as "safe". */ |
| 8969 | else if (strncmp (idesc->name, "br.call", 6) == 0 |
| 8970 | || strncmp (idesc->name, "brl.call", 7) == 0) |
| 8971 | { |
| 8972 | /* FIXME keep GR values which are marked as "safe_across_calls" */ |
| 8973 | clear_register_values (); |
| 8974 | clear_qp_mutex (~qp_safe_across_calls); |
| 8975 | clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); |
| 8976 | clear_qp_branch_flag (~qp_safe_across_calls); |
| 8977 | } |
| 8978 | else if (is_interruption_or_rfi (idesc) |
| 8979 | || is_taken_branch (idesc)) |
| 8980 | { |
| 8981 | clear_register_values (); |
| 8982 | clear_qp_mutex (~(valueT) 0); |
| 8983 | clear_qp_implies (~(valueT) 0, ~(valueT) 0); |
| 8984 | } |
| 8985 | /* Look for mutex and implies relations. */ |
| 8986 | else if ((idesc->operands[0] == IA64_OPND_P1 |
| 8987 | || idesc->operands[0] == IA64_OPND_P2) |
| 8988 | && (idesc->operands[1] == IA64_OPND_P1 |
| 8989 | || idesc->operands[1] == IA64_OPND_P2)) |
| 8990 | { |
| 8991 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
| 8992 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
| 8993 | valueT p1mask = (valueT) 1 << p1; |
| 8994 | valueT p2mask = (valueT) 1 << p2; |
| 8995 | |
| 8996 | /* If one of the PRs is PR0, we can't really do anything. */ |
| 8997 | if (p1 == 0 || p2 == 0) |
| 8998 | { |
| 8999 | if (md.debug_dv) |
| 9000 | fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); |
| 9001 | } |
| 9002 | /* In general, clear mutexes and implies which include P1 or P2, |
| 9003 | with the following exceptions. */ |
| 9004 | else if (has_suffix_p (idesc->name, ".or.andcm") |
| 9005 | || has_suffix_p (idesc->name, ".and.orcm")) |
| 9006 | { |
| 9007 | add_qp_mutex (p1mask | p2mask); |
| 9008 | clear_qp_implies (p2mask, p1mask); |
| 9009 | } |
| 9010 | else if (has_suffix_p (idesc->name, ".andcm") |
| 9011 | || has_suffix_p (idesc->name, ".and")) |
| 9012 | { |
| 9013 | clear_qp_implies (0, p1mask | p2mask); |
| 9014 | } |
| 9015 | else if (has_suffix_p (idesc->name, ".orcm") |
| 9016 | || has_suffix_p (idesc->name, ".or")) |
| 9017 | { |
| 9018 | clear_qp_mutex (p1mask | p2mask); |
| 9019 | clear_qp_implies (p1mask | p2mask, 0); |
| 9020 | } |
| 9021 | else |
| 9022 | { |
| 9023 | clear_qp_implies (p1mask | p2mask, p1mask | p2mask); |
| 9024 | if (has_suffix_p (idesc->name, ".unc")) |
| 9025 | { |
| 9026 | add_qp_mutex (p1mask | p2mask); |
| 9027 | if (CURR_SLOT.qp_regno != 0) |
| 9028 | { |
| 9029 | add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, |
| 9030 | CURR_SLOT.qp_regno); |
| 9031 | add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, |
| 9032 | CURR_SLOT.qp_regno); |
| 9033 | } |
| 9034 | } |
| 9035 | else if (CURR_SLOT.qp_regno == 0) |
| 9036 | { |
| 9037 | add_qp_mutex (p1mask | p2mask); |
| 9038 | } |
| 9039 | else |
| 9040 | { |
| 9041 | clear_qp_mutex (p1mask | p2mask); |
| 9042 | } |
| 9043 | } |
| 9044 | } |
| 9045 | /* Look for mov imm insns into GRs. */ |
| 9046 | else if (idesc->operands[0] == IA64_OPND_R1 |
| 9047 | && (idesc->operands[1] == IA64_OPND_IMM22 |
| 9048 | || idesc->operands[1] == IA64_OPND_IMMU64) |
| 9049 | && (strcmp (idesc->name, "mov") == 0 |
| 9050 | || strcmp (idesc->name, "movl") == 0)) |
| 9051 | { |
| 9052 | int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; |
| 9053 | if (regno > 0 && regno < NELEMS (gr_values)) |
| 9054 | { |
| 9055 | gr_values[regno].known = 1; |
| 9056 | gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; |
| 9057 | gr_values[regno].path = md.path; |
| 9058 | if (md.debug_dv) |
| 9059 | { |
| 9060 | fprintf (stderr, " Know gr%d = ", regno); |
| 9061 | fprintf_vma (stderr, gr_values[regno].value); |
| 9062 | fputs ("\n", stderr); |
| 9063 | } |
| 9064 | } |
| 9065 | } |
| 9066 | else |
| 9067 | { |
| 9068 | clear_qp_mutex (qp_changemask); |
| 9069 | clear_qp_implies (qp_changemask, qp_changemask); |
| 9070 | } |
| 9071 | } |
| 9072 | |
| 9073 | /* Return whether the given predicate registers are currently mutex. */ |
| 9074 | |
| 9075 | static int |
| 9076 | qp_mutex (p1, p2, path) |
| 9077 | int p1; |
| 9078 | int p2; |
| 9079 | int path; |
| 9080 | { |
| 9081 | int i; |
| 9082 | valueT mask; |
| 9083 | |
| 9084 | if (p1 != p2) |
| 9085 | { |
| 9086 | mask = ((valueT) 1 << p1) | (valueT) 1 << p2; |
| 9087 | for (i = 0; i < qp_mutexeslen; i++) |
| 9088 | { |
| 9089 | if (qp_mutexes[i].path >= path |
| 9090 | && (qp_mutexes[i].prmask & mask) == mask) |
| 9091 | return 1; |
| 9092 | } |
| 9093 | } |
| 9094 | return 0; |
| 9095 | } |
| 9096 | |
| 9097 | /* Return whether the given resource is in the given insn's list of chks |
| 9098 | Return 1 if the conflict is absolutely determined, 2 if it's a potential |
| 9099 | conflict. */ |
| 9100 | |
| 9101 | static int |
| 9102 | resources_match (rs, idesc, note, qp_regno, path) |
| 9103 | struct rsrc *rs; |
| 9104 | struct ia64_opcode *idesc; |
| 9105 | int note; |
| 9106 | int qp_regno; |
| 9107 | int path; |
| 9108 | { |
| 9109 | struct rsrc specs[MAX_SPECS]; |
| 9110 | int count; |
| 9111 | |
| 9112 | /* If the marked resource's qp_regno and the given qp_regno are mutex, |
| 9113 | we don't need to check. One exception is note 11, which indicates that |
| 9114 | target predicates are written regardless of PR[qp]. */ |
| 9115 | if (qp_mutex (rs->qp_regno, qp_regno, path) |
| 9116 | && note != 11) |
| 9117 | return 0; |
| 9118 | |
| 9119 | count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); |
| 9120 | while (count-- > 0) |
| 9121 | { |
| 9122 | /* UNAT checking is a bit more specific than other resources */ |
| 9123 | if (rs->dependency->specifier == IA64_RS_AR_UNAT |
| 9124 | && specs[count].mem_offset.hint |
| 9125 | && rs->mem_offset.hint) |
| 9126 | { |
| 9127 | if (rs->mem_offset.base == specs[count].mem_offset.base) |
| 9128 | { |
| 9129 | if (((rs->mem_offset.offset >> 3) & 0x3F) == |
| 9130 | ((specs[count].mem_offset.offset >> 3) & 0x3F)) |
| 9131 | return 1; |
| 9132 | else |
| 9133 | continue; |
| 9134 | } |
| 9135 | } |
| 9136 | |
| 9137 | /* Skip apparent PR write conflicts where both writes are an AND or both |
| 9138 | writes are an OR. */ |
| 9139 | if (rs->dependency->specifier == IA64_RS_PR |
| 9140 | || rs->dependency->specifier == IA64_RS_PRr |
| 9141 | || rs->dependency->specifier == IA64_RS_PR63) |
| 9142 | { |
| 9143 | if (specs[count].cmp_type != CMP_NONE |
| 9144 | && specs[count].cmp_type == rs->cmp_type) |
| 9145 | { |
| 9146 | if (md.debug_dv) |
| 9147 | fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", |
| 9148 | dv_mode[rs->dependency->mode], |
| 9149 | rs->dependency->specifier != IA64_RS_PR63 ? |
| 9150 | specs[count].index : 63); |
| 9151 | continue; |
| 9152 | } |
| 9153 | if (md.debug_dv) |
| 9154 | fprintf (stderr, |
| 9155 | " %s on parallel compare conflict %s vs %s on PR%d\n", |
| 9156 | dv_mode[rs->dependency->mode], |
| 9157 | dv_cmp_type[rs->cmp_type], |
| 9158 | dv_cmp_type[specs[count].cmp_type], |
| 9159 | rs->dependency->specifier != IA64_RS_PR63 ? |
| 9160 | specs[count].index : 63); |
| 9161 | |
| 9162 | } |
| 9163 | |
| 9164 | /* If either resource is not specific, conservatively assume a conflict |
| 9165 | */ |
| 9166 | if (!specs[count].specific || !rs->specific) |
| 9167 | return 2; |
| 9168 | else if (specs[count].index == rs->index) |
| 9169 | return 1; |
| 9170 | } |
| 9171 | #if 0 |
| 9172 | if (md.debug_dv) |
| 9173 | fprintf (stderr, " No %s conflicts\n", rs->dependency->name); |
| 9174 | #endif |
| 9175 | |
| 9176 | return 0; |
| 9177 | } |
| 9178 | |
| 9179 | /* Indicate an instruction group break; if INSERT_STOP is non-zero, then |
| 9180 | insert a stop to create the break. Update all resource dependencies |
| 9181 | appropriately. If QP_REGNO is non-zero, only apply the break to resources |
| 9182 | which use the same QP_REGNO and have the link_to_qp_branch flag set. |
| 9183 | If SAVE_CURRENT is non-zero, don't affect resources marked by the current |
| 9184 | instruction. */ |
| 9185 | |
| 9186 | static void |
| 9187 | insn_group_break (insert_stop, qp_regno, save_current) |
| 9188 | int insert_stop; |
| 9189 | int qp_regno; |
| 9190 | int save_current; |
| 9191 | { |
| 9192 | int i; |
| 9193 | |
| 9194 | if (insert_stop && md.num_slots_in_use > 0) |
| 9195 | PREV_SLOT.end_of_insn_group = 1; |
| 9196 | |
| 9197 | if (md.debug_dv) |
| 9198 | { |
| 9199 | fprintf (stderr, " Insn group break%s", |
| 9200 | (insert_stop ? " (w/stop)" : "")); |
| 9201 | if (qp_regno != 0) |
| 9202 | fprintf (stderr, " effective for QP=%d", qp_regno); |
| 9203 | fprintf (stderr, "\n"); |
| 9204 | } |
| 9205 | |
| 9206 | i = 0; |
| 9207 | while (i < regdepslen) |
| 9208 | { |
| 9209 | const struct ia64_dependency *dep = regdeps[i].dependency; |
| 9210 | |
| 9211 | if (qp_regno != 0 |
| 9212 | && regdeps[i].qp_regno != qp_regno) |
| 9213 | { |
| 9214 | ++i; |
| 9215 | continue; |
| 9216 | } |
| 9217 | |
| 9218 | if (save_current |
| 9219 | && CURR_SLOT.src_file == regdeps[i].file |
| 9220 | && CURR_SLOT.src_line == regdeps[i].line) |
| 9221 | { |
| 9222 | ++i; |
| 9223 | continue; |
| 9224 | } |
| 9225 | |
| 9226 | /* clear dependencies which are automatically cleared by a stop, or |
| 9227 | those that have reached the appropriate state of insn serialization */ |
| 9228 | if (dep->semantics == IA64_DVS_IMPLIED |
| 9229 | || dep->semantics == IA64_DVS_IMPLIEDF |
| 9230 | || regdeps[i].insn_srlz == STATE_SRLZ) |
| 9231 | { |
| 9232 | print_dependency ("Removing", i); |
| 9233 | regdeps[i] = regdeps[--regdepslen]; |
| 9234 | } |
| 9235 | else |
| 9236 | { |
| 9237 | if (dep->semantics == IA64_DVS_DATA |
| 9238 | || dep->semantics == IA64_DVS_INSTR |
| 9239 | || dep->semantics == IA64_DVS_SPECIFIC) |
| 9240 | { |
| 9241 | if (regdeps[i].insn_srlz == STATE_NONE) |
| 9242 | regdeps[i].insn_srlz = STATE_STOP; |
| 9243 | if (regdeps[i].data_srlz == STATE_NONE) |
| 9244 | regdeps[i].data_srlz = STATE_STOP; |
| 9245 | } |
| 9246 | ++i; |
| 9247 | } |
| 9248 | } |
| 9249 | } |
| 9250 | |
| 9251 | /* Add the given resource usage spec to the list of active dependencies. */ |
| 9252 | |
| 9253 | static void |
| 9254 | mark_resource (idesc, dep, spec, depind, path) |
| 9255 | struct ia64_opcode *idesc ATTRIBUTE_UNUSED; |
| 9256 | const struct ia64_dependency *dep ATTRIBUTE_UNUSED; |
| 9257 | struct rsrc *spec; |
| 9258 | int depind; |
| 9259 | int path; |
| 9260 | { |
| 9261 | if (regdepslen == regdepstotlen) |
| 9262 | { |
| 9263 | regdepstotlen += 20; |
| 9264 | regdeps = (struct rsrc *) |
| 9265 | xrealloc ((void *) regdeps, |
| 9266 | regdepstotlen * sizeof (struct rsrc)); |
| 9267 | } |
| 9268 | |
| 9269 | regdeps[regdepslen] = *spec; |
| 9270 | regdeps[regdepslen].depind = depind; |
| 9271 | regdeps[regdepslen].path = path; |
| 9272 | regdeps[regdepslen].file = CURR_SLOT.src_file; |
| 9273 | regdeps[regdepslen].line = CURR_SLOT.src_line; |
| 9274 | |
| 9275 | print_dependency ("Adding", regdepslen); |
| 9276 | |
| 9277 | ++regdepslen; |
| 9278 | } |
| 9279 | |
| 9280 | static void |
| 9281 | print_dependency (action, depind) |
| 9282 | const char *action; |
| 9283 | int depind; |
| 9284 | { |
| 9285 | if (md.debug_dv) |
| 9286 | { |
| 9287 | fprintf (stderr, " %s %s '%s'", |
| 9288 | action, dv_mode[(regdeps[depind].dependency)->mode], |
| 9289 | (regdeps[depind].dependency)->name); |
| 9290 | if (regdeps[depind].specific && regdeps[depind].index != 0) |
| 9291 | fprintf (stderr, " (%d)", regdeps[depind].index); |
| 9292 | if (regdeps[depind].mem_offset.hint) |
| 9293 | { |
| 9294 | fputs (" ", stderr); |
| 9295 | fprintf_vma (stderr, regdeps[depind].mem_offset.base); |
| 9296 | fputs ("+", stderr); |
| 9297 | fprintf_vma (stderr, regdeps[depind].mem_offset.offset); |
| 9298 | } |
| 9299 | fprintf (stderr, "\n"); |
| 9300 | } |
| 9301 | } |
| 9302 | |
| 9303 | static void |
| 9304 | instruction_serialization () |
| 9305 | { |
| 9306 | int i; |
| 9307 | if (md.debug_dv) |
| 9308 | fprintf (stderr, " Instruction serialization\n"); |
| 9309 | for (i = 0; i < regdepslen; i++) |
| 9310 | if (regdeps[i].insn_srlz == STATE_STOP) |
| 9311 | regdeps[i].insn_srlz = STATE_SRLZ; |
| 9312 | } |
| 9313 | |
| 9314 | static void |
| 9315 | data_serialization () |
| 9316 | { |
| 9317 | int i = 0; |
| 9318 | if (md.debug_dv) |
| 9319 | fprintf (stderr, " Data serialization\n"); |
| 9320 | while (i < regdepslen) |
| 9321 | { |
| 9322 | if (regdeps[i].data_srlz == STATE_STOP |
| 9323 | /* Note: as of 991210, all "other" dependencies are cleared by a |
| 9324 | data serialization. This might change with new tables */ |
| 9325 | || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) |
| 9326 | { |
| 9327 | print_dependency ("Removing", i); |
| 9328 | regdeps[i] = regdeps[--regdepslen]; |
| 9329 | } |
| 9330 | else |
| 9331 | ++i; |
| 9332 | } |
| 9333 | } |
| 9334 | |
| 9335 | /* Insert stops and serializations as needed to avoid DVs. */ |
| 9336 | |
| 9337 | static void |
| 9338 | remove_marked_resource (rs) |
| 9339 | struct rsrc *rs; |
| 9340 | { |
| 9341 | switch (rs->dependency->semantics) |
| 9342 | { |
| 9343 | case IA64_DVS_SPECIFIC: |
| 9344 | if (md.debug_dv) |
| 9345 | fprintf (stderr, "Implementation-specific, assume worst case...\n"); |
| 9346 | /* ...fall through... */ |
| 9347 | case IA64_DVS_INSTR: |
| 9348 | if (md.debug_dv) |
| 9349 | fprintf (stderr, "Inserting instr serialization\n"); |
| 9350 | if (rs->insn_srlz < STATE_STOP) |
| 9351 | insn_group_break (1, 0, 0); |
| 9352 | if (rs->insn_srlz < STATE_SRLZ) |
| 9353 | { |
| 9354 | int oldqp = CURR_SLOT.qp_regno; |
| 9355 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; |
| 9356 | /* Manually jam a srlz.i insn into the stream */ |
| 9357 | CURR_SLOT.qp_regno = 0; |
| 9358 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); |
| 9359 | instruction_serialization (); |
| 9360 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; |
| 9361 | if (++md.num_slots_in_use >= NUM_SLOTS) |
| 9362 | emit_one_bundle (); |
| 9363 | CURR_SLOT.qp_regno = oldqp; |
| 9364 | CURR_SLOT.idesc = oldidesc; |
| 9365 | } |
| 9366 | insn_group_break (1, 0, 0); |
| 9367 | break; |
| 9368 | case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all |
| 9369 | "other" types of DV are eliminated |
| 9370 | by a data serialization */ |
| 9371 | case IA64_DVS_DATA: |
| 9372 | if (md.debug_dv) |
| 9373 | fprintf (stderr, "Inserting data serialization\n"); |
| 9374 | if (rs->data_srlz < STATE_STOP) |
| 9375 | insn_group_break (1, 0, 0); |
| 9376 | { |
| 9377 | int oldqp = CURR_SLOT.qp_regno; |
| 9378 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; |
| 9379 | /* Manually jam a srlz.d insn into the stream */ |
| 9380 | CURR_SLOT.qp_regno = 0; |
| 9381 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); |
| 9382 | data_serialization (); |
| 9383 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; |
| 9384 | if (++md.num_slots_in_use >= NUM_SLOTS) |
| 9385 | emit_one_bundle (); |
| 9386 | CURR_SLOT.qp_regno = oldqp; |
| 9387 | CURR_SLOT.idesc = oldidesc; |
| 9388 | } |
| 9389 | break; |
| 9390 | case IA64_DVS_IMPLIED: |
| 9391 | case IA64_DVS_IMPLIEDF: |
| 9392 | if (md.debug_dv) |
| 9393 | fprintf (stderr, "Inserting stop\n"); |
| 9394 | insn_group_break (1, 0, 0); |
| 9395 | break; |
| 9396 | default: |
| 9397 | break; |
| 9398 | } |
| 9399 | } |
| 9400 | |
| 9401 | /* Check the resources used by the given opcode against the current dependency |
| 9402 | list. |
| 9403 | |
| 9404 | The check is run once for each execution path encountered. In this case, |
| 9405 | a unique execution path is the sequence of instructions following a code |
| 9406 | entry point, e.g. the following has three execution paths, one starting |
| 9407 | at L0, one at L1, and one at L2. |
| 9408 | |
| 9409 | L0: nop |
| 9410 | L1: add |
| 9411 | L2: add |
| 9412 | br.ret |
| 9413 | */ |
| 9414 | |
| 9415 | static void |
| 9416 | check_dependencies (idesc) |
| 9417 | struct ia64_opcode *idesc; |
| 9418 | { |
| 9419 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; |
| 9420 | int path; |
| 9421 | int i; |
| 9422 | |
| 9423 | /* Note that the number of marked resources may change within the |
| 9424 | loop if in auto mode. */ |
| 9425 | i = 0; |
| 9426 | while (i < regdepslen) |
| 9427 | { |
| 9428 | struct rsrc *rs = ®deps[i]; |
| 9429 | const struct ia64_dependency *dep = rs->dependency; |
| 9430 | int chkind; |
| 9431 | int note; |
| 9432 | int start_over = 0; |
| 9433 | |
| 9434 | if (dep->semantics == IA64_DVS_NONE |
| 9435 | || (chkind = depends_on (rs->depind, idesc)) == -1) |
| 9436 | { |
| 9437 | ++i; |
| 9438 | continue; |
| 9439 | } |
| 9440 | |
| 9441 | note = NOTE (opdeps->chks[chkind]); |
| 9442 | |
| 9443 | /* Check this resource against each execution path seen thus far. */ |
| 9444 | for (path = 0; path <= md.path; path++) |
| 9445 | { |
| 9446 | int matchtype; |
| 9447 | |
| 9448 | /* If the dependency wasn't on the path being checked, ignore it. */ |
| 9449 | if (rs->path < path) |
| 9450 | continue; |
| 9451 | |
| 9452 | /* If the QP for this insn implies a QP which has branched, don't |
| 9453 | bother checking. Ed. NOTE: I don't think this check is terribly |
| 9454 | useful; what's the point of generating code which will only be |
| 9455 | reached if its QP is zero? |
| 9456 | This code was specifically inserted to handle the following code, |
| 9457 | based on notes from Intel's DV checking code, where p1 implies p2. |
| 9458 | |
| 9459 | mov r4 = 2 |
| 9460 | (p2) br.cond L |
| 9461 | (p1) mov r4 = 7 |
| 9462 | */ |
| 9463 | if (CURR_SLOT.qp_regno != 0) |
| 9464 | { |
| 9465 | int skip = 0; |
| 9466 | int implies; |
| 9467 | for (implies = 0; implies < qp_implieslen; implies++) |
| 9468 | { |
| 9469 | if (qp_implies[implies].path >= path |
| 9470 | && qp_implies[implies].p1 == CURR_SLOT.qp_regno |
| 9471 | && qp_implies[implies].p2_branched) |
| 9472 | { |
| 9473 | skip = 1; |
| 9474 | break; |
| 9475 | } |
| 9476 | } |
| 9477 | if (skip) |
| 9478 | continue; |
| 9479 | } |
| 9480 | |
| 9481 | if ((matchtype = resources_match (rs, idesc, note, |
| 9482 | CURR_SLOT.qp_regno, path)) != 0) |
| 9483 | { |
| 9484 | char msg[1024]; |
| 9485 | char pathmsg[256] = ""; |
| 9486 | char indexmsg[256] = ""; |
| 9487 | int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); |
| 9488 | |
| 9489 | if (path != 0) |
| 9490 | sprintf (pathmsg, " when entry is at label '%s'", |
| 9491 | md.entry_labels[path - 1]); |
| 9492 | if (rs->specific && rs->index != 0) |
| 9493 | sprintf (indexmsg, ", specific resource number is %d", |
| 9494 | rs->index); |
| 9495 | sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", |
| 9496 | idesc->name, |
| 9497 | (certain ? "violates" : "may violate"), |
| 9498 | dv_mode[dep->mode], dep->name, |
| 9499 | dv_sem[dep->semantics], |
| 9500 | pathmsg, indexmsg); |
| 9501 | |
| 9502 | if (md.explicit_mode) |
| 9503 | { |
| 9504 | as_warn ("%s", msg); |
| 9505 | if (path < md.path) |
| 9506 | as_warn (_("Only the first path encountering the conflict " |
| 9507 | "is reported")); |
| 9508 | as_warn_where (rs->file, rs->line, |
| 9509 | _("This is the location of the " |
| 9510 | "conflicting usage")); |
| 9511 | /* Don't bother checking other paths, to avoid duplicating |
| 9512 | the same warning */ |
| 9513 | break; |
| 9514 | } |
| 9515 | else |
| 9516 | { |
| 9517 | if (md.debug_dv) |
| 9518 | fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); |
| 9519 | |
| 9520 | remove_marked_resource (rs); |
| 9521 | |
| 9522 | /* since the set of dependencies has changed, start over */ |
| 9523 | /* FIXME -- since we're removing dvs as we go, we |
| 9524 | probably don't really need to start over... */ |
| 9525 | start_over = 1; |
| 9526 | break; |
| 9527 | } |
| 9528 | } |
| 9529 | } |
| 9530 | if (start_over) |
| 9531 | i = 0; |
| 9532 | else |
| 9533 | ++i; |
| 9534 | } |
| 9535 | } |
| 9536 | |
| 9537 | /* Register new dependencies based on the given opcode. */ |
| 9538 | |
| 9539 | static void |
| 9540 | mark_resources (idesc) |
| 9541 | struct ia64_opcode *idesc; |
| 9542 | { |
| 9543 | int i; |
| 9544 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; |
| 9545 | int add_only_qp_reads = 0; |
| 9546 | |
| 9547 | /* A conditional branch only uses its resources if it is taken; if it is |
| 9548 | taken, we stop following that path. The other branch types effectively |
| 9549 | *always* write their resources. If it's not taken, register only QP |
| 9550 | reads. */ |
| 9551 | if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) |
| 9552 | { |
| 9553 | add_only_qp_reads = 1; |
| 9554 | } |
| 9555 | |
| 9556 | if (md.debug_dv) |
| 9557 | fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); |
| 9558 | |
| 9559 | for (i = 0; i < opdeps->nregs; i++) |
| 9560 | { |
| 9561 | const struct ia64_dependency *dep; |
| 9562 | struct rsrc specs[MAX_SPECS]; |
| 9563 | int note; |
| 9564 | int path; |
| 9565 | int count; |
| 9566 | |
| 9567 | dep = ia64_find_dependency (opdeps->regs[i]); |
| 9568 | note = NOTE (opdeps->regs[i]); |
| 9569 | |
| 9570 | if (add_only_qp_reads |
| 9571 | && !(dep->mode == IA64_DV_WAR |
| 9572 | && (dep->specifier == IA64_RS_PR |
| 9573 | || dep->specifier == IA64_RS_PRr |
| 9574 | || dep->specifier == IA64_RS_PR63))) |
| 9575 | continue; |
| 9576 | |
| 9577 | count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); |
| 9578 | |
| 9579 | #if 0 |
| 9580 | if (md.debug_dv && !count) |
| 9581 | fprintf (stderr, " No %s %s usage found (path %d)\n", |
| 9582 | dv_mode[dep->mode], dep->name, md.path); |
| 9583 | #endif |
| 9584 | |
| 9585 | while (count-- > 0) |
| 9586 | { |
| 9587 | mark_resource (idesc, dep, &specs[count], |
| 9588 | DEP (opdeps->regs[i]), md.path); |
| 9589 | } |
| 9590 | |
| 9591 | /* The execution path may affect register values, which may in turn |
| 9592 | affect which indirect-access resources are accessed. */ |
| 9593 | switch (dep->specifier) |
| 9594 | { |
| 9595 | default: |
| 9596 | break; |
| 9597 | case IA64_RS_CPUID: |
| 9598 | case IA64_RS_DBR: |
| 9599 | case IA64_RS_IBR: |
| 9600 | case IA64_RS_MSR: |
| 9601 | case IA64_RS_PKR: |
| 9602 | case IA64_RS_PMC: |
| 9603 | case IA64_RS_PMD: |
| 9604 | case IA64_RS_RR: |
| 9605 | for (path = 0; path < md.path; path++) |
| 9606 | { |
| 9607 | count = specify_resource (dep, idesc, DV_REG, specs, note, path); |
| 9608 | while (count-- > 0) |
| 9609 | mark_resource (idesc, dep, &specs[count], |
| 9610 | DEP (opdeps->regs[i]), path); |
| 9611 | } |
| 9612 | break; |
| 9613 | } |
| 9614 | } |
| 9615 | } |
| 9616 | |
| 9617 | /* Remove dependencies when they no longer apply. */ |
| 9618 | |
| 9619 | static void |
| 9620 | update_dependencies (idesc) |
| 9621 | struct ia64_opcode *idesc; |
| 9622 | { |
| 9623 | int i; |
| 9624 | |
| 9625 | if (strcmp (idesc->name, "srlz.i") == 0) |
| 9626 | { |
| 9627 | instruction_serialization (); |
| 9628 | } |
| 9629 | else if (strcmp (idesc->name, "srlz.d") == 0) |
| 9630 | { |
| 9631 | data_serialization (); |
| 9632 | } |
| 9633 | else if (is_interruption_or_rfi (idesc) |
| 9634 | || is_taken_branch (idesc)) |
| 9635 | { |
| 9636 | /* Although technically the taken branch doesn't clear dependencies |
| 9637 | which require a srlz.[id], we don't follow the branch; the next |
| 9638 | instruction is assumed to start with a clean slate. */ |
| 9639 | regdepslen = 0; |
| 9640 | md.path = 0; |
| 9641 | } |
| 9642 | else if (is_conditional_branch (idesc) |
| 9643 | && CURR_SLOT.qp_regno != 0) |
| 9644 | { |
| 9645 | int is_call = strstr (idesc->name, ".call") != NULL; |
| 9646 | |
| 9647 | for (i = 0; i < qp_implieslen; i++) |
| 9648 | { |
| 9649 | /* If the conditional branch's predicate is implied by the predicate |
| 9650 | in an existing dependency, remove that dependency. */ |
| 9651 | if (qp_implies[i].p2 == CURR_SLOT.qp_regno) |
| 9652 | { |
| 9653 | int depind = 0; |
| 9654 | /* Note that this implied predicate takes a branch so that if |
| 9655 | a later insn generates a DV but its predicate implies this |
| 9656 | one, we can avoid the false DV warning. */ |
| 9657 | qp_implies[i].p2_branched = 1; |
| 9658 | while (depind < regdepslen) |
| 9659 | { |
| 9660 | if (regdeps[depind].qp_regno == qp_implies[i].p1) |
| 9661 | { |
| 9662 | print_dependency ("Removing", depind); |
| 9663 | regdeps[depind] = regdeps[--regdepslen]; |
| 9664 | } |
| 9665 | else |
| 9666 | ++depind; |
| 9667 | } |
| 9668 | } |
| 9669 | } |
| 9670 | /* Any marked resources which have this same predicate should be |
| 9671 | cleared, provided that the QP hasn't been modified between the |
| 9672 | marking instruction and the branch. */ |
| 9673 | if (is_call) |
| 9674 | { |
| 9675 | insn_group_break (0, CURR_SLOT.qp_regno, 1); |
| 9676 | } |
| 9677 | else |
| 9678 | { |
| 9679 | i = 0; |
| 9680 | while (i < regdepslen) |
| 9681 | { |
| 9682 | if (regdeps[i].qp_regno == CURR_SLOT.qp_regno |
| 9683 | && regdeps[i].link_to_qp_branch |
| 9684 | && (regdeps[i].file != CURR_SLOT.src_file |
| 9685 | || regdeps[i].line != CURR_SLOT.src_line)) |
| 9686 | { |
| 9687 | /* Treat like a taken branch */ |
| 9688 | print_dependency ("Removing", i); |
| 9689 | regdeps[i] = regdeps[--regdepslen]; |
| 9690 | } |
| 9691 | else |
| 9692 | ++i; |
| 9693 | } |
| 9694 | } |
| 9695 | } |
| 9696 | } |
| 9697 | |
| 9698 | /* Examine the current instruction for dependency violations. */ |
| 9699 | |
| 9700 | static int |
| 9701 | check_dv (idesc) |
| 9702 | struct ia64_opcode *idesc; |
| 9703 | { |
| 9704 | if (md.debug_dv) |
| 9705 | { |
| 9706 | fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", |
| 9707 | idesc->name, CURR_SLOT.src_line, |
| 9708 | idesc->dependencies->nchks, |
| 9709 | idesc->dependencies->nregs); |
| 9710 | } |
| 9711 | |
| 9712 | /* Look through the list of currently marked resources; if the current |
| 9713 | instruction has the dependency in its chks list which uses that resource, |
| 9714 | check against the specific resources used. */ |
| 9715 | check_dependencies (idesc); |
| 9716 | |
| 9717 | /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), |
| 9718 | then add them to the list of marked resources. */ |
| 9719 | mark_resources (idesc); |
| 9720 | |
| 9721 | /* There are several types of dependency semantics, and each has its own |
| 9722 | requirements for being cleared |
| 9723 | |
| 9724 | Instruction serialization (insns separated by interruption, rfi, or |
| 9725 | writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. |
| 9726 | |
| 9727 | Data serialization (instruction serialization, or writer + srlz.d + |
| 9728 | reader, where writer and srlz.d are in separate groups) clears |
| 9729 | DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to |
| 9730 | always be the case). |
| 9731 | |
| 9732 | Instruction group break (groups separated by stop, taken branch, |
| 9733 | interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. |
| 9734 | */ |
| 9735 | update_dependencies (idesc); |
| 9736 | |
| 9737 | /* Sometimes, knowing a register value allows us to avoid giving a false DV |
| 9738 | warning. Keep track of as many as possible that are useful. */ |
| 9739 | note_register_values (idesc); |
| 9740 | |
| 9741 | /* We don't need or want this anymore. */ |
| 9742 | md.mem_offset.hint = 0; |
| 9743 | |
| 9744 | return 0; |
| 9745 | } |
| 9746 | |
| 9747 | /* Translate one line of assembly. Pseudo ops and labels do not show |
| 9748 | here. */ |
| 9749 | void |
| 9750 | md_assemble (str) |
| 9751 | char *str; |
| 9752 | { |
| 9753 | char *saved_input_line_pointer, *mnemonic; |
| 9754 | const struct pseudo_opcode *pdesc; |
| 9755 | struct ia64_opcode *idesc; |
| 9756 | unsigned char qp_regno; |
| 9757 | unsigned int flags; |
| 9758 | int ch; |
| 9759 | |
| 9760 | saved_input_line_pointer = input_line_pointer; |
| 9761 | input_line_pointer = str; |
| 9762 | |
| 9763 | /* extract the opcode (mnemonic): */ |
| 9764 | |
| 9765 | mnemonic = input_line_pointer; |
| 9766 | ch = get_symbol_end (); |
| 9767 | pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); |
| 9768 | if (pdesc) |
| 9769 | { |
| 9770 | *input_line_pointer = ch; |
| 9771 | (*pdesc->handler) (pdesc->arg); |
| 9772 | goto done; |
| 9773 | } |
| 9774 | |
| 9775 | /* Find the instruction descriptor matching the arguments. */ |
| 9776 | |
| 9777 | idesc = ia64_find_opcode (mnemonic); |
| 9778 | *input_line_pointer = ch; |
| 9779 | if (!idesc) |
| 9780 | { |
| 9781 | as_bad ("Unknown opcode `%s'", mnemonic); |
| 9782 | goto done; |
| 9783 | } |
| 9784 | |
| 9785 | idesc = parse_operands (idesc); |
| 9786 | if (!idesc) |
| 9787 | goto done; |
| 9788 | |
| 9789 | /* Handle the dynamic ops we can handle now: */ |
| 9790 | if (idesc->type == IA64_TYPE_DYN) |
| 9791 | { |
| 9792 | if (strcmp (idesc->name, "add") == 0) |
| 9793 | { |
| 9794 | if (CURR_SLOT.opnd[2].X_op == O_register |
| 9795 | && CURR_SLOT.opnd[2].X_add_number < 4) |
| 9796 | mnemonic = "addl"; |
| 9797 | else |
| 9798 | mnemonic = "adds"; |
| 9799 | ia64_free_opcode (idesc); |
| 9800 | idesc = ia64_find_opcode (mnemonic); |
| 9801 | #if 0 |
| 9802 | know (!idesc->next); |
| 9803 | #endif |
| 9804 | } |
| 9805 | else if (strcmp (idesc->name, "mov") == 0) |
| 9806 | { |
| 9807 | enum ia64_opnd opnd1, opnd2; |
| 9808 | int rop; |
| 9809 | |
| 9810 | opnd1 = idesc->operands[0]; |
| 9811 | opnd2 = idesc->operands[1]; |
| 9812 | if (opnd1 == IA64_OPND_AR3) |
| 9813 | rop = 0; |
| 9814 | else if (opnd2 == IA64_OPND_AR3) |
| 9815 | rop = 1; |
| 9816 | else |
| 9817 | abort (); |
| 9818 | if (CURR_SLOT.opnd[rop].X_op == O_register |
| 9819 | && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) |
| 9820 | mnemonic = "mov.i"; |
| 9821 | else |
| 9822 | mnemonic = "mov.m"; |
| 9823 | ia64_free_opcode (idesc); |
| 9824 | idesc = ia64_find_opcode (mnemonic); |
| 9825 | while (idesc != NULL |
| 9826 | && (idesc->operands[0] != opnd1 |
| 9827 | || idesc->operands[1] != opnd2)) |
| 9828 | idesc = get_next_opcode (idesc); |
| 9829 | } |
| 9830 | } |
| 9831 | |
| 9832 | qp_regno = 0; |
| 9833 | if (md.qp.X_op == O_register) |
| 9834 | { |
| 9835 | qp_regno = md.qp.X_add_number - REG_P; |
| 9836 | md.qp.X_op = O_absent; |
| 9837 | } |
| 9838 | |
| 9839 | flags = idesc->flags; |
| 9840 | |
| 9841 | if ((flags & IA64_OPCODE_FIRST) != 0) |
| 9842 | insn_group_break (1, 0, 0); |
| 9843 | |
| 9844 | if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) |
| 9845 | { |
| 9846 | as_bad ("`%s' cannot be predicated", idesc->name); |
| 9847 | goto done; |
| 9848 | } |
| 9849 | |
| 9850 | /* Build the instruction. */ |
| 9851 | CURR_SLOT.qp_regno = qp_regno; |
| 9852 | CURR_SLOT.idesc = idesc; |
| 9853 | as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); |
| 9854 | dwarf2_where (&CURR_SLOT.debug_line); |
| 9855 | |
| 9856 | /* Add unwind entry, if there is one. */ |
| 9857 | if (unwind.current_entry) |
| 9858 | { |
| 9859 | CURR_SLOT.unwind_record = unwind.current_entry; |
| 9860 | unwind.current_entry = NULL; |
| 9861 | } |
| 9862 | |
| 9863 | /* Check for dependency violations. */ |
| 9864 | if (md.detect_dv) |
| 9865 | check_dv (idesc); |
| 9866 | |
| 9867 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; |
| 9868 | if (++md.num_slots_in_use >= NUM_SLOTS) |
| 9869 | emit_one_bundle (); |
| 9870 | |
| 9871 | if ((flags & IA64_OPCODE_LAST) != 0) |
| 9872 | insn_group_break (1, 0, 0); |
| 9873 | |
| 9874 | md.last_text_seg = now_seg; |
| 9875 | |
| 9876 | done: |
| 9877 | input_line_pointer = saved_input_line_pointer; |
| 9878 | } |
| 9879 | |
| 9880 | /* Called when symbol NAME cannot be found in the symbol table. |
| 9881 | Should be used for dynamic valued symbols only. */ |
| 9882 | |
| 9883 | symbolS * |
| 9884 | md_undefined_symbol (name) |
| 9885 | char *name ATTRIBUTE_UNUSED; |
| 9886 | { |
| 9887 | return 0; |
| 9888 | } |
| 9889 | |
| 9890 | /* Called for any expression that can not be recognized. When the |
| 9891 | function is called, `input_line_pointer' will point to the start of |
| 9892 | the expression. */ |
| 9893 | |
| 9894 | void |
| 9895 | md_operand (e) |
| 9896 | expressionS *e; |
| 9897 | { |
| 9898 | enum pseudo_type pseudo_type; |
| 9899 | const char *name; |
| 9900 | size_t len; |
| 9901 | int ch, i; |
| 9902 | |
| 9903 | switch (*input_line_pointer) |
| 9904 | { |
| 9905 | case '@': |
| 9906 | /* Find what relocation pseudo-function we're dealing with. */ |
| 9907 | pseudo_type = 0; |
| 9908 | ch = *++input_line_pointer; |
| 9909 | for (i = 0; i < NELEMS (pseudo_func); ++i) |
| 9910 | if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) |
| 9911 | { |
| 9912 | len = strlen (pseudo_func[i].name); |
| 9913 | if (strncmp (pseudo_func[i].name + 1, |
| 9914 | input_line_pointer + 1, len - 1) == 0 |
| 9915 | && !is_part_of_name (input_line_pointer[len])) |
| 9916 | { |
| 9917 | input_line_pointer += len; |
| 9918 | pseudo_type = pseudo_func[i].type; |
| 9919 | break; |
| 9920 | } |
| 9921 | } |
| 9922 | switch (pseudo_type) |
| 9923 | { |
| 9924 | case PSEUDO_FUNC_RELOC: |
| 9925 | SKIP_WHITESPACE (); |
| 9926 | if (*input_line_pointer != '(') |
| 9927 | { |
| 9928 | as_bad ("Expected '('"); |
| 9929 | goto err; |
| 9930 | } |
| 9931 | /* Skip '('. */ |
| 9932 | ++input_line_pointer; |
| 9933 | expression (e); |
| 9934 | if (*input_line_pointer++ != ')') |
| 9935 | { |
| 9936 | as_bad ("Missing ')'"); |
| 9937 | goto err; |
| 9938 | } |
| 9939 | if (e->X_op != O_symbol) |
| 9940 | { |
| 9941 | if (e->X_op != O_pseudo_fixup) |
| 9942 | { |
| 9943 | as_bad ("Not a symbolic expression"); |
| 9944 | goto err; |
| 9945 | } |
| 9946 | if (i != FUNC_LT_RELATIVE) |
| 9947 | { |
| 9948 | as_bad ("Illegal combination of relocation functions"); |
| 9949 | goto err; |
| 9950 | } |
| 9951 | switch (S_GET_VALUE (e->X_op_symbol)) |
| 9952 | { |
| 9953 | case FUNC_FPTR_RELATIVE: |
| 9954 | i = FUNC_LT_FPTR_RELATIVE; break; |
| 9955 | case FUNC_DTP_MODULE: |
| 9956 | i = FUNC_LT_DTP_MODULE; break; |
| 9957 | case FUNC_DTP_RELATIVE: |
| 9958 | i = FUNC_LT_DTP_RELATIVE; break; |
| 9959 | case FUNC_TP_RELATIVE: |
| 9960 | i = FUNC_LT_TP_RELATIVE; break; |
| 9961 | default: |
| 9962 | as_bad ("Illegal combination of relocation functions"); |
| 9963 | goto err; |
| 9964 | } |
| 9965 | } |
| 9966 | /* Make sure gas doesn't get rid of local symbols that are used |
| 9967 | in relocs. */ |
| 9968 | e->X_op = O_pseudo_fixup; |
| 9969 | e->X_op_symbol = pseudo_func[i].u.sym; |
| 9970 | break; |
| 9971 | |
| 9972 | case PSEUDO_FUNC_CONST: |
| 9973 | e->X_op = O_constant; |
| 9974 | e->X_add_number = pseudo_func[i].u.ival; |
| 9975 | break; |
| 9976 | |
| 9977 | case PSEUDO_FUNC_REG: |
| 9978 | e->X_op = O_register; |
| 9979 | e->X_add_number = pseudo_func[i].u.ival; |
| 9980 | break; |
| 9981 | |
| 9982 | default: |
| 9983 | name = input_line_pointer - 1; |
| 9984 | get_symbol_end (); |
| 9985 | as_bad ("Unknown pseudo function `%s'", name); |
| 9986 | goto err; |
| 9987 | } |
| 9988 | break; |
| 9989 | |
| 9990 | case '[': |
| 9991 | ++input_line_pointer; |
| 9992 | expression (e); |
| 9993 | if (*input_line_pointer != ']') |
| 9994 | { |
| 9995 | as_bad ("Closing bracket misssing"); |
| 9996 | goto err; |
| 9997 | } |
| 9998 | else |
| 9999 | { |
| 10000 | if (e->X_op != O_register) |
| 10001 | as_bad ("Register expected as index"); |
| 10002 | |
| 10003 | ++input_line_pointer; |
| 10004 | e->X_op = O_index; |
| 10005 | } |
| 10006 | break; |
| 10007 | |
| 10008 | default: |
| 10009 | break; |
| 10010 | } |
| 10011 | return; |
| 10012 | |
| 10013 | err: |
| 10014 | ignore_rest_of_line (); |
| 10015 | } |
| 10016 | |
| 10017 | /* Return 1 if it's OK to adjust a reloc by replacing the symbol with |
| 10018 | a section symbol plus some offset. For relocs involving @fptr(), |
| 10019 | directives we don't want such adjustments since we need to have the |
| 10020 | original symbol's name in the reloc. */ |
| 10021 | int |
| 10022 | ia64_fix_adjustable (fix) |
| 10023 | fixS *fix; |
| 10024 | { |
| 10025 | /* Prevent all adjustments to global symbols */ |
| 10026 | if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) |
| 10027 | return 0; |
| 10028 | |
| 10029 | switch (fix->fx_r_type) |
| 10030 | { |
| 10031 | case BFD_RELOC_IA64_FPTR64I: |
| 10032 | case BFD_RELOC_IA64_FPTR32MSB: |
| 10033 | case BFD_RELOC_IA64_FPTR32LSB: |
| 10034 | case BFD_RELOC_IA64_FPTR64MSB: |
| 10035 | case BFD_RELOC_IA64_FPTR64LSB: |
| 10036 | case BFD_RELOC_IA64_LTOFF_FPTR22: |
| 10037 | case BFD_RELOC_IA64_LTOFF_FPTR64I: |
| 10038 | return 0; |
| 10039 | default: |
| 10040 | break; |
| 10041 | } |
| 10042 | |
| 10043 | return 1; |
| 10044 | } |
| 10045 | |
| 10046 | int |
| 10047 | ia64_force_relocation (fix) |
| 10048 | fixS *fix; |
| 10049 | { |
| 10050 | switch (fix->fx_r_type) |
| 10051 | { |
| 10052 | case BFD_RELOC_IA64_FPTR64I: |
| 10053 | case BFD_RELOC_IA64_FPTR32MSB: |
| 10054 | case BFD_RELOC_IA64_FPTR32LSB: |
| 10055 | case BFD_RELOC_IA64_FPTR64MSB: |
| 10056 | case BFD_RELOC_IA64_FPTR64LSB: |
| 10057 | |
| 10058 | case BFD_RELOC_IA64_LTOFF22: |
| 10059 | case BFD_RELOC_IA64_LTOFF64I: |
| 10060 | case BFD_RELOC_IA64_LTOFF_FPTR22: |
| 10061 | case BFD_RELOC_IA64_LTOFF_FPTR64I: |
| 10062 | case BFD_RELOC_IA64_PLTOFF22: |
| 10063 | case BFD_RELOC_IA64_PLTOFF64I: |
| 10064 | case BFD_RELOC_IA64_PLTOFF64MSB: |
| 10065 | case BFD_RELOC_IA64_PLTOFF64LSB: |
| 10066 | |
| 10067 | case BFD_RELOC_IA64_LTOFF22X: |
| 10068 | case BFD_RELOC_IA64_LDXMOV: |
| 10069 | return 1; |
| 10070 | |
| 10071 | default: |
| 10072 | break; |
| 10073 | } |
| 10074 | |
| 10075 | return generic_force_reloc (fix); |
| 10076 | } |
| 10077 | |
| 10078 | /* Decide from what point a pc-relative relocation is relative to, |
| 10079 | relative to the pc-relative fixup. Er, relatively speaking. */ |
| 10080 | long |
| 10081 | ia64_pcrel_from_section (fix, sec) |
| 10082 | fixS *fix; |
| 10083 | segT sec; |
| 10084 | { |
| 10085 | unsigned long off = fix->fx_frag->fr_address + fix->fx_where; |
| 10086 | |
| 10087 | if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) |
| 10088 | off &= ~0xfUL; |
| 10089 | |
| 10090 | return off; |
| 10091 | } |
| 10092 | |
| 10093 | |
| 10094 | /* Used to emit section-relative relocs for the dwarf2 debug data. */ |
| 10095 | void |
| 10096 | ia64_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
| 10097 | { |
| 10098 | expressionS expr; |
| 10099 | |
| 10100 | expr.X_op = O_pseudo_fixup; |
| 10101 | expr.X_op_symbol = pseudo_func[FUNC_SEC_RELATIVE].u.sym; |
| 10102 | expr.X_add_number = 0; |
| 10103 | expr.X_add_symbol = symbol; |
| 10104 | emit_expr (&expr, size); |
| 10105 | } |
| 10106 | |
| 10107 | /* This is called whenever some data item (not an instruction) needs a |
| 10108 | fixup. We pick the right reloc code depending on the byteorder |
| 10109 | currently in effect. */ |
| 10110 | void |
| 10111 | ia64_cons_fix_new (f, where, nbytes, exp) |
| 10112 | fragS *f; |
| 10113 | int where; |
| 10114 | int nbytes; |
| 10115 | expressionS *exp; |
| 10116 | { |
| 10117 | bfd_reloc_code_real_type code; |
| 10118 | fixS *fix; |
| 10119 | |
| 10120 | switch (nbytes) |
| 10121 | { |
| 10122 | /* There are no reloc for 8 and 16 bit quantities, but we allow |
| 10123 | them here since they will work fine as long as the expression |
| 10124 | is fully defined at the end of the pass over the source file. */ |
| 10125 | case 1: code = BFD_RELOC_8; break; |
| 10126 | case 2: code = BFD_RELOC_16; break; |
| 10127 | case 4: |
| 10128 | if (target_big_endian) |
| 10129 | code = BFD_RELOC_IA64_DIR32MSB; |
| 10130 | else |
| 10131 | code = BFD_RELOC_IA64_DIR32LSB; |
| 10132 | break; |
| 10133 | |
| 10134 | case 8: |
| 10135 | /* In 32-bit mode, data8 could mean function descriptors too. */ |
| 10136 | if (exp->X_op == O_pseudo_fixup |
| 10137 | && exp->X_op_symbol |
| 10138 | && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC |
| 10139 | && !(md.flags & EF_IA_64_ABI64)) |
| 10140 | { |
| 10141 | if (target_big_endian) |
| 10142 | code = BFD_RELOC_IA64_IPLTMSB; |
| 10143 | else |
| 10144 | code = BFD_RELOC_IA64_IPLTLSB; |
| 10145 | exp->X_op = O_symbol; |
| 10146 | break; |
| 10147 | } |
| 10148 | else |
| 10149 | { |
| 10150 | if (target_big_endian) |
| 10151 | code = BFD_RELOC_IA64_DIR64MSB; |
| 10152 | else |
| 10153 | code = BFD_RELOC_IA64_DIR64LSB; |
| 10154 | break; |
| 10155 | } |
| 10156 | |
| 10157 | case 16: |
| 10158 | if (exp->X_op == O_pseudo_fixup |
| 10159 | && exp->X_op_symbol |
| 10160 | && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC) |
| 10161 | { |
| 10162 | if (target_big_endian) |
| 10163 | code = BFD_RELOC_IA64_IPLTMSB; |
| 10164 | else |
| 10165 | code = BFD_RELOC_IA64_IPLTLSB; |
| 10166 | exp->X_op = O_symbol; |
| 10167 | break; |
| 10168 | } |
| 10169 | /* FALLTHRU */ |
| 10170 | |
| 10171 | default: |
| 10172 | as_bad ("Unsupported fixup size %d", nbytes); |
| 10173 | ignore_rest_of_line (); |
| 10174 | return; |
| 10175 | } |
| 10176 | |
| 10177 | if (exp->X_op == O_pseudo_fixup) |
| 10178 | { |
| 10179 | exp->X_op = O_symbol; |
| 10180 | code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); |
| 10181 | /* ??? If code unchanged, unsupported. */ |
| 10182 | } |
| 10183 | |
| 10184 | fix = fix_new_exp (f, where, nbytes, exp, 0, code); |
| 10185 | /* We need to store the byte order in effect in case we're going |
| 10186 | to fix an 8 or 16 bit relocation (for which there no real |
| 10187 | relocs available). See md_apply_fix3(). */ |
| 10188 | fix->tc_fix_data.bigendian = target_big_endian; |
| 10189 | } |
| 10190 | |
| 10191 | /* Return the actual relocation we wish to associate with the pseudo |
| 10192 | reloc described by SYM and R_TYPE. SYM should be one of the |
| 10193 | symbols in the pseudo_func array, or NULL. */ |
| 10194 | |
| 10195 | static bfd_reloc_code_real_type |
| 10196 | ia64_gen_real_reloc_type (sym, r_type) |
| 10197 | struct symbol *sym; |
| 10198 | bfd_reloc_code_real_type r_type; |
| 10199 | { |
| 10200 | bfd_reloc_code_real_type new = 0; |
| 10201 | |
| 10202 | if (sym == NULL) |
| 10203 | { |
| 10204 | return r_type; |
| 10205 | } |
| 10206 | |
| 10207 | switch (S_GET_VALUE (sym)) |
| 10208 | { |
| 10209 | case FUNC_FPTR_RELATIVE: |
| 10210 | switch (r_type) |
| 10211 | { |
| 10212 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; |
| 10213 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; |
| 10214 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; |
| 10215 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; |
| 10216 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; |
| 10217 | default: break; |
| 10218 | } |
| 10219 | break; |
| 10220 | |
| 10221 | case FUNC_GP_RELATIVE: |
| 10222 | switch (r_type) |
| 10223 | { |
| 10224 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; |
| 10225 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; |
| 10226 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; |
| 10227 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; |
| 10228 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; |
| 10229 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; |
| 10230 | default: break; |
| 10231 | } |
| 10232 | break; |
| 10233 | |
| 10234 | case FUNC_LT_RELATIVE: |
| 10235 | switch (r_type) |
| 10236 | { |
| 10237 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; |
| 10238 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; |
| 10239 | default: break; |
| 10240 | } |
| 10241 | break; |
| 10242 | |
| 10243 | case FUNC_LT_RELATIVE_X: |
| 10244 | switch (r_type) |
| 10245 | { |
| 10246 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22X; break; |
| 10247 | default: break; |
| 10248 | } |
| 10249 | break; |
| 10250 | |
| 10251 | case FUNC_PC_RELATIVE: |
| 10252 | switch (r_type) |
| 10253 | { |
| 10254 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; |
| 10255 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; |
| 10256 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; |
| 10257 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; |
| 10258 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; |
| 10259 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; |
| 10260 | default: break; |
| 10261 | } |
| 10262 | break; |
| 10263 | |
| 10264 | case FUNC_PLT_RELATIVE: |
| 10265 | switch (r_type) |
| 10266 | { |
| 10267 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; |
| 10268 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; |
| 10269 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; |
| 10270 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; |
| 10271 | default: break; |
| 10272 | } |
| 10273 | break; |
| 10274 | |
| 10275 | case FUNC_SEC_RELATIVE: |
| 10276 | switch (r_type) |
| 10277 | { |
| 10278 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; |
| 10279 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; |
| 10280 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; |
| 10281 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; |
| 10282 | default: break; |
| 10283 | } |
| 10284 | break; |
| 10285 | |
| 10286 | case FUNC_SEG_RELATIVE: |
| 10287 | switch (r_type) |
| 10288 | { |
| 10289 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; |
| 10290 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; |
| 10291 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; |
| 10292 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; |
| 10293 | default: break; |
| 10294 | } |
| 10295 | break; |
| 10296 | |
| 10297 | case FUNC_LTV_RELATIVE: |
| 10298 | switch (r_type) |
| 10299 | { |
| 10300 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; |
| 10301 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; |
| 10302 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; |
| 10303 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; |
| 10304 | default: break; |
| 10305 | } |
| 10306 | break; |
| 10307 | |
| 10308 | case FUNC_LT_FPTR_RELATIVE: |
| 10309 | switch (r_type) |
| 10310 | { |
| 10311 | case BFD_RELOC_IA64_IMM22: |
| 10312 | new = BFD_RELOC_IA64_LTOFF_FPTR22; break; |
| 10313 | case BFD_RELOC_IA64_IMM64: |
| 10314 | new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; |
| 10315 | default: |
| 10316 | break; |
| 10317 | } |
| 10318 | break; |
| 10319 | |
| 10320 | case FUNC_TP_RELATIVE: |
| 10321 | switch (r_type) |
| 10322 | { |
| 10323 | case BFD_RELOC_IA64_IMM14: |
| 10324 | new = BFD_RELOC_IA64_TPREL14; break; |
| 10325 | case BFD_RELOC_IA64_IMM22: |
| 10326 | new = BFD_RELOC_IA64_TPREL22; break; |
| 10327 | case BFD_RELOC_IA64_IMM64: |
| 10328 | new = BFD_RELOC_IA64_TPREL64I; break; |
| 10329 | default: |
| 10330 | break; |
| 10331 | } |
| 10332 | break; |
| 10333 | |
| 10334 | case FUNC_LT_TP_RELATIVE: |
| 10335 | switch (r_type) |
| 10336 | { |
| 10337 | case BFD_RELOC_IA64_IMM22: |
| 10338 | new = BFD_RELOC_IA64_LTOFF_TPREL22; break; |
| 10339 | default: |
| 10340 | break; |
| 10341 | } |
| 10342 | break; |
| 10343 | |
| 10344 | case FUNC_LT_DTP_MODULE: |
| 10345 | switch (r_type) |
| 10346 | { |
| 10347 | case BFD_RELOC_IA64_IMM22: |
| 10348 | new = BFD_RELOC_IA64_LTOFF_DTPMOD22; break; |
| 10349 | default: |
| 10350 | break; |
| 10351 | } |
| 10352 | break; |
| 10353 | |
| 10354 | case FUNC_DTP_RELATIVE: |
| 10355 | switch (r_type) |
| 10356 | { |
| 10357 | case BFD_RELOC_IA64_DIR64MSB: |
| 10358 | new = BFD_RELOC_IA64_DTPREL64MSB; break; |
| 10359 | case BFD_RELOC_IA64_DIR64LSB: |
| 10360 | new = BFD_RELOC_IA64_DTPREL64LSB; break; |
| 10361 | case BFD_RELOC_IA64_IMM14: |
| 10362 | new = BFD_RELOC_IA64_DTPREL14; break; |
| 10363 | case BFD_RELOC_IA64_IMM22: |
| 10364 | new = BFD_RELOC_IA64_DTPREL22; break; |
| 10365 | case BFD_RELOC_IA64_IMM64: |
| 10366 | new = BFD_RELOC_IA64_DTPREL64I; break; |
| 10367 | default: |
| 10368 | break; |
| 10369 | } |
| 10370 | break; |
| 10371 | |
| 10372 | case FUNC_LT_DTP_RELATIVE: |
| 10373 | switch (r_type) |
| 10374 | { |
| 10375 | case BFD_RELOC_IA64_IMM22: |
| 10376 | new = BFD_RELOC_IA64_LTOFF_DTPREL22; break; |
| 10377 | default: |
| 10378 | break; |
| 10379 | } |
| 10380 | break; |
| 10381 | |
| 10382 | case FUNC_IPLT_RELOC: |
| 10383 | break; |
| 10384 | |
| 10385 | default: |
| 10386 | abort (); |
| 10387 | } |
| 10388 | |
| 10389 | /* Hmmmm. Should this ever occur? */ |
| 10390 | if (new) |
| 10391 | return new; |
| 10392 | else |
| 10393 | return r_type; |
| 10394 | } |
| 10395 | |
| 10396 | /* Here is where generate the appropriate reloc for pseudo relocation |
| 10397 | functions. */ |
| 10398 | void |
| 10399 | ia64_validate_fix (fix) |
| 10400 | fixS *fix; |
| 10401 | { |
| 10402 | switch (fix->fx_r_type) |
| 10403 | { |
| 10404 | case BFD_RELOC_IA64_FPTR64I: |
| 10405 | case BFD_RELOC_IA64_FPTR32MSB: |
| 10406 | case BFD_RELOC_IA64_FPTR64LSB: |
| 10407 | case BFD_RELOC_IA64_LTOFF_FPTR22: |
| 10408 | case BFD_RELOC_IA64_LTOFF_FPTR64I: |
| 10409 | if (fix->fx_offset != 0) |
| 10410 | as_bad_where (fix->fx_file, fix->fx_line, |
| 10411 | "No addend allowed in @fptr() relocation"); |
| 10412 | break; |
| 10413 | default: |
| 10414 | break; |
| 10415 | } |
| 10416 | |
| 10417 | return; |
| 10418 | } |
| 10419 | |
| 10420 | static void |
| 10421 | fix_insn (fix, odesc, value) |
| 10422 | fixS *fix; |
| 10423 | const struct ia64_operand *odesc; |
| 10424 | valueT value; |
| 10425 | { |
| 10426 | bfd_vma insn[3], t0, t1, control_bits; |
| 10427 | const char *err; |
| 10428 | char *fixpos; |
| 10429 | long slot; |
| 10430 | |
| 10431 | slot = fix->fx_where & 0x3; |
| 10432 | fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); |
| 10433 | |
| 10434 | /* Bundles are always in little-endian byte order */ |
| 10435 | t0 = bfd_getl64 (fixpos); |
| 10436 | t1 = bfd_getl64 (fixpos + 8); |
| 10437 | control_bits = t0 & 0x1f; |
| 10438 | insn[0] = (t0 >> 5) & 0x1ffffffffffLL; |
| 10439 | insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); |
| 10440 | insn[2] = (t1 >> 23) & 0x1ffffffffffLL; |
| 10441 | |
| 10442 | err = NULL; |
| 10443 | if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) |
| 10444 | { |
| 10445 | insn[1] = (value >> 22) & 0x1ffffffffffLL; |
| 10446 | insn[2] |= (((value & 0x7f) << 13) |
| 10447 | | (((value >> 7) & 0x1ff) << 27) |
| 10448 | | (((value >> 16) & 0x1f) << 22) |
| 10449 | | (((value >> 21) & 0x1) << 21) |
| 10450 | | (((value >> 63) & 0x1) << 36)); |
| 10451 | } |
| 10452 | else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) |
| 10453 | { |
| 10454 | if (value & ~0x3fffffffffffffffULL) |
| 10455 | err = "integer operand out of range"; |
| 10456 | insn[1] = (value >> 21) & 0x1ffffffffffLL; |
| 10457 | insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); |
| 10458 | } |
| 10459 | else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) |
| 10460 | { |
| 10461 | value >>= 4; |
| 10462 | insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; |
| 10463 | insn[2] |= ((((value >> 59) & 0x1) << 36) |
| 10464 | | (((value >> 0) & 0xfffff) << 13)); |
| 10465 | } |
| 10466 | else |
| 10467 | err = (*odesc->insert) (odesc, value, insn + slot); |
| 10468 | |
| 10469 | if (err) |
| 10470 | as_bad_where (fix->fx_file, fix->fx_line, err); |
| 10471 | |
| 10472 | t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); |
| 10473 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); |
| 10474 | number_to_chars_littleendian (fixpos + 0, t0, 8); |
| 10475 | number_to_chars_littleendian (fixpos + 8, t1, 8); |
| 10476 | } |
| 10477 | |
| 10478 | /* Attempt to simplify or even eliminate a fixup. The return value is |
| 10479 | ignored; perhaps it was once meaningful, but now it is historical. |
| 10480 | To indicate that a fixup has been eliminated, set FIXP->FX_DONE. |
| 10481 | |
| 10482 | If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry |
| 10483 | (if possible). */ |
| 10484 | |
| 10485 | void |
| 10486 | md_apply_fix3 (fix, valP, seg) |
| 10487 | fixS *fix; |
| 10488 | valueT *valP; |
| 10489 | segT seg ATTRIBUTE_UNUSED; |
| 10490 | { |
| 10491 | char *fixpos; |
| 10492 | valueT value = *valP; |
| 10493 | |
| 10494 | fixpos = fix->fx_frag->fr_literal + fix->fx_where; |
| 10495 | |
| 10496 | if (fix->fx_pcrel) |
| 10497 | { |
| 10498 | switch (fix->fx_r_type) |
| 10499 | { |
| 10500 | case BFD_RELOC_IA64_DIR32MSB: |
| 10501 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; |
| 10502 | break; |
| 10503 | |
| 10504 | case BFD_RELOC_IA64_DIR32LSB: |
| 10505 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; |
| 10506 | break; |
| 10507 | |
| 10508 | case BFD_RELOC_IA64_DIR64MSB: |
| 10509 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; |
| 10510 | break; |
| 10511 | |
| 10512 | case BFD_RELOC_IA64_DIR64LSB: |
| 10513 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; |
| 10514 | break; |
| 10515 | |
| 10516 | default: |
| 10517 | break; |
| 10518 | } |
| 10519 | } |
| 10520 | if (fix->fx_addsy) |
| 10521 | { |
| 10522 | switch (fix->fx_r_type) |
| 10523 | { |
| 10524 | case BFD_RELOC_UNUSED: |
| 10525 | /* This must be a TAG13 or TAG13b operand. There are no external |
| 10526 | relocs defined for them, so we must give an error. */ |
| 10527 | as_bad_where (fix->fx_file, fix->fx_line, |
| 10528 | "%s must have a constant value", |
| 10529 | elf64_ia64_operands[fix->tc_fix_data.opnd].desc); |
| 10530 | fix->fx_done = 1; |
| 10531 | return; |
| 10532 | |
| 10533 | case BFD_RELOC_IA64_TPREL14: |
| 10534 | case BFD_RELOC_IA64_TPREL22: |
| 10535 | case BFD_RELOC_IA64_TPREL64I: |
| 10536 | case BFD_RELOC_IA64_LTOFF_TPREL22: |
| 10537 | case BFD_RELOC_IA64_LTOFF_DTPMOD22: |
| 10538 | case BFD_RELOC_IA64_DTPREL14: |
| 10539 | case BFD_RELOC_IA64_DTPREL22: |
| 10540 | case BFD_RELOC_IA64_DTPREL64I: |
| 10541 | case BFD_RELOC_IA64_LTOFF_DTPREL22: |
| 10542 | S_SET_THREAD_LOCAL (fix->fx_addsy); |
| 10543 | break; |
| 10544 | |
| 10545 | default: |
| 10546 | break; |
| 10547 | } |
| 10548 | } |
| 10549 | else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) |
| 10550 | { |
| 10551 | if (fix->tc_fix_data.bigendian) |
| 10552 | number_to_chars_bigendian (fixpos, value, fix->fx_size); |
| 10553 | else |
| 10554 | number_to_chars_littleendian (fixpos, value, fix->fx_size); |
| 10555 | fix->fx_done = 1; |
| 10556 | } |
| 10557 | else |
| 10558 | { |
| 10559 | fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); |
| 10560 | fix->fx_done = 1; |
| 10561 | } |
| 10562 | } |
| 10563 | |
| 10564 | /* Generate the BFD reloc to be stuck in the object file from the |
| 10565 | fixup used internally in the assembler. */ |
| 10566 | |
| 10567 | arelent * |
| 10568 | tc_gen_reloc (sec, fixp) |
| 10569 | asection *sec ATTRIBUTE_UNUSED; |
| 10570 | fixS *fixp; |
| 10571 | { |
| 10572 | arelent *reloc; |
| 10573 | |
| 10574 | reloc = xmalloc (sizeof (*reloc)); |
| 10575 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 10576 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 10577 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 10578 | reloc->addend = fixp->fx_offset; |
| 10579 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
| 10580 | |
| 10581 | if (!reloc->howto) |
| 10582 | { |
| 10583 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 10584 | "Cannot represent %s relocation in object file", |
| 10585 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
| 10586 | } |
| 10587 | return reloc; |
| 10588 | } |
| 10589 | |
| 10590 | /* Turn a string in input_line_pointer into a floating point constant |
| 10591 | of type TYPE, and store the appropriate bytes in *LIT. The number |
| 10592 | of LITTLENUMS emitted is stored in *SIZE. An error message is |
| 10593 | returned, or NULL on OK. */ |
| 10594 | |
| 10595 | #define MAX_LITTLENUMS 5 |
| 10596 | |
| 10597 | char * |
| 10598 | md_atof (type, lit, size) |
| 10599 | int type; |
| 10600 | char *lit; |
| 10601 | int *size; |
| 10602 | { |
| 10603 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 10604 | char *t; |
| 10605 | int prec; |
| 10606 | |
| 10607 | switch (type) |
| 10608 | { |
| 10609 | /* IEEE floats */ |
| 10610 | case 'f': |
| 10611 | case 'F': |
| 10612 | case 's': |
| 10613 | case 'S': |
| 10614 | prec = 2; |
| 10615 | break; |
| 10616 | |
| 10617 | case 'd': |
| 10618 | case 'D': |
| 10619 | case 'r': |
| 10620 | case 'R': |
| 10621 | prec = 4; |
| 10622 | break; |
| 10623 | |
| 10624 | case 'x': |
| 10625 | case 'X': |
| 10626 | case 'p': |
| 10627 | case 'P': |
| 10628 | prec = 5; |
| 10629 | break; |
| 10630 | |
| 10631 | default: |
| 10632 | *size = 0; |
| 10633 | return "Bad call to MD_ATOF()"; |
| 10634 | } |
| 10635 | t = atof_ieee (input_line_pointer, type, words); |
| 10636 | if (t) |
| 10637 | input_line_pointer = t; |
| 10638 | |
| 10639 | (*ia64_float_to_chars) (lit, words, prec); |
| 10640 | |
| 10641 | if (type == 'X') |
| 10642 | { |
| 10643 | /* It is 10 byte floating point with 6 byte padding. */ |
| 10644 | memset (&lit [10], 0, 6); |
| 10645 | *size = 8 * sizeof (LITTLENUM_TYPE); |
| 10646 | } |
| 10647 | else |
| 10648 | *size = prec * sizeof (LITTLENUM_TYPE); |
| 10649 | |
| 10650 | return 0; |
| 10651 | } |
| 10652 | |
| 10653 | /* Handle ia64 specific semantics of the align directive. */ |
| 10654 | |
| 10655 | void |
| 10656 | ia64_md_do_align (n, fill, len, max) |
| 10657 | int n ATTRIBUTE_UNUSED; |
| 10658 | const char *fill ATTRIBUTE_UNUSED; |
| 10659 | int len ATTRIBUTE_UNUSED; |
| 10660 | int max ATTRIBUTE_UNUSED; |
| 10661 | { |
| 10662 | if (subseg_text_p (now_seg)) |
| 10663 | ia64_flush_insns (); |
| 10664 | } |
| 10665 | |
| 10666 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
| 10667 | of an rs_align_code fragment. */ |
| 10668 | |
| 10669 | void |
| 10670 | ia64_handle_align (fragp) |
| 10671 | fragS *fragp; |
| 10672 | { |
| 10673 | /* Use mfi bundle of nops with no stop bits. */ |
| 10674 | static const unsigned char be_nop[] |
| 10675 | = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, |
| 10676 | 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; |
| 10677 | static const unsigned char le_nop[] |
| 10678 | = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, |
| 10679 | 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; |
| 10680 | |
| 10681 | int bytes; |
| 10682 | char *p; |
| 10683 | |
| 10684 | if (fragp->fr_type != rs_align_code) |
| 10685 | return; |
| 10686 | |
| 10687 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
| 10688 | p = fragp->fr_literal + fragp->fr_fix; |
| 10689 | |
| 10690 | /* Make sure we are on a 16-byte boundary, in case someone has been |
| 10691 | putting data into a text section. */ |
| 10692 | if (bytes & 15) |
| 10693 | { |
| 10694 | int fix = bytes & 15; |
| 10695 | memset (p, 0, fix); |
| 10696 | p += fix; |
| 10697 | bytes -= fix; |
| 10698 | fragp->fr_fix += fix; |
| 10699 | } |
| 10700 | |
| 10701 | memcpy (p, (target_big_endian ? be_nop : le_nop), 16); |
| 10702 | fragp->fr_var = 16; |
| 10703 | } |
| 10704 | |
| 10705 | static void |
| 10706 | ia64_float_to_chars_bigendian (char *lit, LITTLENUM_TYPE *words, |
| 10707 | int prec) |
| 10708 | { |
| 10709 | while (prec--) |
| 10710 | { |
| 10711 | number_to_chars_bigendian (lit, (long) (*words++), |
| 10712 | sizeof (LITTLENUM_TYPE)); |
| 10713 | lit += sizeof (LITTLENUM_TYPE); |
| 10714 | } |
| 10715 | } |
| 10716 | |
| 10717 | static void |
| 10718 | ia64_float_to_chars_littleendian (char *lit, LITTLENUM_TYPE *words, |
| 10719 | int prec) |
| 10720 | { |
| 10721 | while (prec--) |
| 10722 | { |
| 10723 | number_to_chars_littleendian (lit, (long) (words[prec]), |
| 10724 | sizeof (LITTLENUM_TYPE)); |
| 10725 | lit += sizeof (LITTLENUM_TYPE); |
| 10726 | } |
| 10727 | } |
| 10728 | |
| 10729 | void |
| 10730 | ia64_elf_section_change_hook (void) |
| 10731 | { |
| 10732 | dot_byteorder (-1); |
| 10733 | } |
| 10734 | |
| 10735 | /* Check if a label should be made global. */ |
| 10736 | void |
| 10737 | ia64_check_label (symbolS *label) |
| 10738 | { |
| 10739 | if (*input_line_pointer == ':') |
| 10740 | { |
| 10741 | S_SET_EXTERNAL (label); |
| 10742 | input_line_pointer++; |
| 10743 | } |
| 10744 | } |
| 10745 | |
| 10746 | /* Used to remember where .alias and .secalias directives are seen. We |
| 10747 | will rename symbol and section names when we are about to output |
| 10748 | the relocatable file. */ |
| 10749 | struct alias |
| 10750 | { |
| 10751 | char *file; /* The file where the directive is seen. */ |
| 10752 | unsigned int line; /* The line number the directive is at. */ |
| 10753 | const char *name; /* The orignale name of the symbol. */ |
| 10754 | }; |
| 10755 | |
| 10756 | /* Called for .alias and .secalias directives. If SECTION is 1, it is |
| 10757 | .secalias. Otherwise, it is .alias. */ |
| 10758 | static void |
| 10759 | dot_alias (int section) |
| 10760 | { |
| 10761 | char *name, *alias; |
| 10762 | char delim; |
| 10763 | char *end_name; |
| 10764 | int len; |
| 10765 | const char *error_string; |
| 10766 | struct alias *h; |
| 10767 | const char *a; |
| 10768 | struct hash_control *ahash, *nhash; |
| 10769 | const char *kind; |
| 10770 | |
| 10771 | name = input_line_pointer; |
| 10772 | delim = get_symbol_end (); |
| 10773 | end_name = input_line_pointer; |
| 10774 | *end_name = delim; |
| 10775 | |
| 10776 | if (name == end_name) |
| 10777 | { |
| 10778 | as_bad (_("expected symbol name")); |
| 10779 | discard_rest_of_line (); |
| 10780 | return; |
| 10781 | } |
| 10782 | |
| 10783 | SKIP_WHITESPACE (); |
| 10784 | |
| 10785 | if (*input_line_pointer != ',') |
| 10786 | { |
| 10787 | *end_name = 0; |
| 10788 | as_bad (_("expected comma after \"%s\""), name); |
| 10789 | *end_name = delim; |
| 10790 | ignore_rest_of_line (); |
| 10791 | return; |
| 10792 | } |
| 10793 | |
| 10794 | input_line_pointer++; |
| 10795 | *end_name = 0; |
| 10796 | |
| 10797 | /* We call demand_copy_C_string to check if alias string is valid. |
| 10798 | There should be a closing `"' and no `\0' in the string. */ |
| 10799 | alias = demand_copy_C_string (&len); |
| 10800 | if (alias == NULL) |
| 10801 | { |
| 10802 | ignore_rest_of_line (); |
| 10803 | return; |
| 10804 | } |
| 10805 | |
| 10806 | /* Make a copy of name string. */ |
| 10807 | len = strlen (name) + 1; |
| 10808 | obstack_grow (¬es, name, len); |
| 10809 | name = obstack_finish (¬es); |
| 10810 | |
| 10811 | if (section) |
| 10812 | { |
| 10813 | kind = "section"; |
| 10814 | ahash = secalias_hash; |
| 10815 | nhash = secalias_name_hash; |
| 10816 | } |
| 10817 | else |
| 10818 | { |
| 10819 | kind = "symbol"; |
| 10820 | ahash = alias_hash; |
| 10821 | nhash = alias_name_hash; |
| 10822 | } |
| 10823 | |
| 10824 | /* Check if alias has been used before. */ |
| 10825 | h = (struct alias *) hash_find (ahash, alias); |
| 10826 | if (h) |
| 10827 | { |
| 10828 | if (strcmp (h->name, name)) |
| 10829 | as_bad (_("`%s' is already the alias of %s `%s'"), |
| 10830 | alias, kind, h->name); |
| 10831 | goto out; |
| 10832 | } |
| 10833 | |
| 10834 | /* Check if name already has an alias. */ |
| 10835 | a = (const char *) hash_find (nhash, name); |
| 10836 | if (a) |
| 10837 | { |
| 10838 | if (strcmp (a, alias)) |
| 10839 | as_bad (_("%s `%s' already has an alias `%s'"), kind, name, a); |
| 10840 | goto out; |
| 10841 | } |
| 10842 | |
| 10843 | h = (struct alias *) xmalloc (sizeof (struct alias)); |
| 10844 | as_where (&h->file, &h->line); |
| 10845 | h->name = name; |
| 10846 | |
| 10847 | error_string = hash_jam (ahash, alias, (PTR) h); |
| 10848 | if (error_string) |
| 10849 | { |
| 10850 | as_fatal (_("inserting \"%s\" into %s alias hash table failed: %s"), |
| 10851 | alias, kind, error_string); |
| 10852 | goto out; |
| 10853 | } |
| 10854 | |
| 10855 | error_string = hash_jam (nhash, name, (PTR) alias); |
| 10856 | if (error_string) |
| 10857 | { |
| 10858 | as_fatal (_("inserting \"%s\" into %s name hash table failed: %s"), |
| 10859 | alias, kind, error_string); |
| 10860 | out: |
| 10861 | obstack_free (¬es, name); |
| 10862 | obstack_free (¬es, alias); |
| 10863 | } |
| 10864 | |
| 10865 | demand_empty_rest_of_line (); |
| 10866 | } |
| 10867 | |
| 10868 | /* It renames the original symbol name to its alias. */ |
| 10869 | static void |
| 10870 | do_alias (const char *alias, PTR value) |
| 10871 | { |
| 10872 | struct alias *h = (struct alias *) value; |
| 10873 | symbolS *sym = symbol_find (h->name); |
| 10874 | |
| 10875 | if (sym == NULL) |
| 10876 | as_warn_where (h->file, h->line, |
| 10877 | _("symbol `%s' aliased to `%s' is not used"), |
| 10878 | h->name, alias); |
| 10879 | else |
| 10880 | S_SET_NAME (sym, (char *) alias); |
| 10881 | } |
| 10882 | |
| 10883 | /* Called from write_object_file. */ |
| 10884 | void |
| 10885 | ia64_adjust_symtab (void) |
| 10886 | { |
| 10887 | hash_traverse (alias_hash, do_alias); |
| 10888 | } |
| 10889 | |
| 10890 | /* It renames the original section name to its alias. */ |
| 10891 | static void |
| 10892 | do_secalias (const char *alias, PTR value) |
| 10893 | { |
| 10894 | struct alias *h = (struct alias *) value; |
| 10895 | segT sec = bfd_get_section_by_name (stdoutput, h->name); |
| 10896 | |
| 10897 | if (sec == NULL) |
| 10898 | as_warn_where (h->file, h->line, |
| 10899 | _("section `%s' aliased to `%s' is not used"), |
| 10900 | h->name, alias); |
| 10901 | else |
| 10902 | sec->name = alias; |
| 10903 | } |
| 10904 | |
| 10905 | /* Called from write_object_file. */ |
| 10906 | void |
| 10907 | ia64_frob_file (void) |
| 10908 | { |
| 10909 | hash_traverse (secalias_hash, do_secalias); |
| 10910 | } |