| 1 | /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. |
| 2 | Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation. |
| 3 | Contributed by David Mosberger-Tang <davidm@hpl.hp.com> |
| 4 | |
| 5 | This file is part of GAS, the GNU Assembler. |
| 6 | |
| 7 | GAS is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | GAS is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to |
| 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | /* |
| 23 | TODO: |
| 24 | |
| 25 | - optional operands |
| 26 | - directives: |
| 27 | .alias |
| 28 | .eb |
| 29 | .estate |
| 30 | .lb |
| 31 | .popsection |
| 32 | .previous |
| 33 | .psr |
| 34 | .pushsection |
| 35 | - labels are wrong if automatic alignment is introduced |
| 36 | (e.g., checkout the second real10 definition in test-data.s) |
| 37 | - DV-related stuff: |
| 38 | <reg>.safe_across_calls and any other DV-related directives I don't |
| 39 | have documentation for. |
| 40 | verify mod-sched-brs reads/writes are checked/marked (and other |
| 41 | notes) |
| 42 | |
| 43 | */ |
| 44 | |
| 45 | #include "as.h" |
| 46 | #include "dwarf2dbg.h" |
| 47 | #include "subsegs.h" |
| 48 | |
| 49 | #include "opcode/ia64.h" |
| 50 | |
| 51 | #include "elf/ia64.h" |
| 52 | |
| 53 | #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) |
| 54 | #define MIN(a,b) ((a) < (b) ? (a) : (b)) |
| 55 | |
| 56 | #define NUM_SLOTS 4 |
| 57 | #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] |
| 58 | #define CURR_SLOT md.slot[md.curr_slot] |
| 59 | |
| 60 | #define O_pseudo_fixup (O_max + 1) |
| 61 | |
| 62 | enum special_section |
| 63 | { |
| 64 | SPECIAL_SECTION_BSS = 0, |
| 65 | SPECIAL_SECTION_SBSS, |
| 66 | SPECIAL_SECTION_SDATA, |
| 67 | SPECIAL_SECTION_RODATA, |
| 68 | SPECIAL_SECTION_COMMENT, |
| 69 | SPECIAL_SECTION_UNWIND, |
| 70 | SPECIAL_SECTION_UNWIND_INFO |
| 71 | }; |
| 72 | |
| 73 | enum reloc_func |
| 74 | { |
| 75 | FUNC_FPTR_RELATIVE, |
| 76 | FUNC_GP_RELATIVE, |
| 77 | FUNC_LT_RELATIVE, |
| 78 | FUNC_PC_RELATIVE, |
| 79 | FUNC_PLT_RELATIVE, |
| 80 | FUNC_SEC_RELATIVE, |
| 81 | FUNC_SEG_RELATIVE, |
| 82 | FUNC_LTV_RELATIVE, |
| 83 | FUNC_LT_FPTR_RELATIVE, |
| 84 | }; |
| 85 | |
| 86 | enum reg_symbol |
| 87 | { |
| 88 | REG_GR = 0, |
| 89 | REG_FR = (REG_GR + 128), |
| 90 | REG_AR = (REG_FR + 128), |
| 91 | REG_CR = (REG_AR + 128), |
| 92 | REG_P = (REG_CR + 128), |
| 93 | REG_BR = (REG_P + 64), |
| 94 | REG_IP = (REG_BR + 8), |
| 95 | REG_CFM, |
| 96 | REG_PR, |
| 97 | REG_PR_ROT, |
| 98 | REG_PSR, |
| 99 | REG_PSR_L, |
| 100 | REG_PSR_UM, |
| 101 | /* The following are pseudo-registers for use by gas only. */ |
| 102 | IND_CPUID, |
| 103 | IND_DBR, |
| 104 | IND_DTR, |
| 105 | IND_ITR, |
| 106 | IND_IBR, |
| 107 | IND_MEM, |
| 108 | IND_MSR, |
| 109 | IND_PKR, |
| 110 | IND_PMC, |
| 111 | IND_PMD, |
| 112 | IND_RR, |
| 113 | /* The following pseudo-registers are used for unwind directives only: */ |
| 114 | REG_PSP, |
| 115 | REG_PRIUNAT, |
| 116 | REG_NUM |
| 117 | }; |
| 118 | |
| 119 | enum dynreg_type |
| 120 | { |
| 121 | DYNREG_GR = 0, /* dynamic general purpose register */ |
| 122 | DYNREG_FR, /* dynamic floating point register */ |
| 123 | DYNREG_PR, /* dynamic predicate register */ |
| 124 | DYNREG_NUM_TYPES |
| 125 | }; |
| 126 | |
| 127 | enum operand_match_result |
| 128 | { |
| 129 | OPERAND_MATCH, |
| 130 | OPERAND_OUT_OF_RANGE, |
| 131 | OPERAND_MISMATCH |
| 132 | }; |
| 133 | |
| 134 | /* On the ia64, we can't know the address of a text label until the |
| 135 | instructions are packed into a bundle. To handle this, we keep |
| 136 | track of the list of labels that appear in front of each |
| 137 | instruction. */ |
| 138 | struct label_fix |
| 139 | { |
| 140 | struct label_fix *next; |
| 141 | struct symbol *sym; |
| 142 | }; |
| 143 | |
| 144 | extern int target_big_endian; |
| 145 | |
| 146 | /* Characters which always start a comment. */ |
| 147 | const char comment_chars[] = ""; |
| 148 | |
| 149 | /* Characters which start a comment at the beginning of a line. */ |
| 150 | const char line_comment_chars[] = "#"; |
| 151 | |
| 152 | /* Characters which may be used to separate multiple commands on a |
| 153 | single line. */ |
| 154 | const char line_separator_chars[] = ";"; |
| 155 | |
| 156 | /* Characters which are used to indicate an exponent in a floating |
| 157 | point number. */ |
| 158 | const char EXP_CHARS[] = "eE"; |
| 159 | |
| 160 | /* Characters which mean that a number is a floating point constant, |
| 161 | as in 0d1.0. */ |
| 162 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
| 163 | |
| 164 | /* ia64-specific option processing: */ |
| 165 | |
| 166 | const char *md_shortopts = "m:N:x::"; |
| 167 | |
| 168 | struct option md_longopts[] = |
| 169 | { |
| 170 | #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) |
| 171 | {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, |
| 172 | #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) |
| 173 | {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} |
| 174 | }; |
| 175 | |
| 176 | size_t md_longopts_size = sizeof (md_longopts); |
| 177 | |
| 178 | static struct |
| 179 | { |
| 180 | struct hash_control *pseudo_hash; /* pseudo opcode hash table */ |
| 181 | struct hash_control *reg_hash; /* register name hash table */ |
| 182 | struct hash_control *dynreg_hash; /* dynamic register hash table */ |
| 183 | struct hash_control *const_hash; /* constant hash table */ |
| 184 | struct hash_control *entry_hash; /* code entry hint hash table */ |
| 185 | |
| 186 | symbolS *regsym[REG_NUM]; |
| 187 | |
| 188 | /* If X_op is != O_absent, the registername for the instruction's |
| 189 | qualifying predicate. If NULL, p0 is assumed for instructions |
| 190 | that are predicatable. */ |
| 191 | expressionS qp; |
| 192 | |
| 193 | unsigned int |
| 194 | manual_bundling : 1, |
| 195 | debug_dv: 1, |
| 196 | detect_dv: 1, |
| 197 | explicit_mode : 1, /* which mode we're in */ |
| 198 | default_explicit_mode : 1, /* which mode is the default */ |
| 199 | mode_explicitly_set : 1, /* was the current mode explicitly set? */ |
| 200 | auto_align : 1; |
| 201 | |
| 202 | /* Each bundle consists of up to three instructions. We keep |
| 203 | track of four most recent instructions so we can correctly set |
| 204 | the end_of_insn_group for the last instruction in a bundle. */ |
| 205 | int curr_slot; |
| 206 | int num_slots_in_use; |
| 207 | struct slot |
| 208 | { |
| 209 | unsigned int |
| 210 | end_of_insn_group : 1, |
| 211 | manual_bundling_on : 1, |
| 212 | manual_bundling_off : 1; |
| 213 | signed char user_template; /* user-selected template, if any */ |
| 214 | unsigned char qp_regno; /* qualifying predicate */ |
| 215 | /* This duplicates a good fraction of "struct fix" but we |
| 216 | can't use a "struct fix" instead since we can't call |
| 217 | fix_new_exp() until we know the address of the instruction. */ |
| 218 | int num_fixups; |
| 219 | struct insn_fix |
| 220 | { |
| 221 | bfd_reloc_code_real_type code; |
| 222 | enum ia64_opnd opnd; /* type of operand in need of fix */ |
| 223 | unsigned int is_pcrel : 1; /* is operand pc-relative? */ |
| 224 | expressionS expr; /* the value to be inserted */ |
| 225 | } |
| 226 | fixup[2]; /* at most two fixups per insn */ |
| 227 | struct ia64_opcode *idesc; |
| 228 | struct label_fix *label_fixups; |
| 229 | struct label_fix *tag_fixups; |
| 230 | struct unw_rec_list *unwind_record; /* Unwind directive. */ |
| 231 | expressionS opnd[6]; |
| 232 | char *src_file; |
| 233 | unsigned int src_line; |
| 234 | struct dwarf2_line_info debug_line; |
| 235 | } |
| 236 | slot[NUM_SLOTS]; |
| 237 | |
| 238 | segT last_text_seg; |
| 239 | |
| 240 | struct dynreg |
| 241 | { |
| 242 | struct dynreg *next; /* next dynamic register */ |
| 243 | const char *name; |
| 244 | unsigned short base; /* the base register number */ |
| 245 | unsigned short num_regs; /* # of registers in this set */ |
| 246 | } |
| 247 | *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; |
| 248 | |
| 249 | flagword flags; /* ELF-header flags */ |
| 250 | |
| 251 | struct mem_offset { |
| 252 | unsigned hint:1; /* is this hint currently valid? */ |
| 253 | bfd_vma offset; /* mem.offset offset */ |
| 254 | bfd_vma base; /* mem.offset base */ |
| 255 | } mem_offset; |
| 256 | |
| 257 | int path; /* number of alt. entry points seen */ |
| 258 | const char **entry_labels; /* labels of all alternate paths in |
| 259 | the current DV-checking block. */ |
| 260 | int maxpaths; /* size currently allocated for |
| 261 | entry_labels */ |
| 262 | /* Support for hardware errata workarounds. */ |
| 263 | |
| 264 | /* Record data about the last three insn groups. */ |
| 265 | struct group |
| 266 | { |
| 267 | /* B-step workaround. |
| 268 | For each predicate register, this is set if the corresponding insn |
| 269 | group conditionally sets this register with one of the affected |
| 270 | instructions. */ |
| 271 | int p_reg_set[64]; |
| 272 | /* B-step workaround. |
| 273 | For each general register, this is set if the corresponding insn |
| 274 | a) is conditional one one of the predicate registers for which |
| 275 | P_REG_SET is 1 in the corresponding entry of the previous group, |
| 276 | b) sets this general register with one of the affected |
| 277 | instructions. */ |
| 278 | int g_reg_set_conditionally[128]; |
| 279 | } last_groups[3]; |
| 280 | int group_idx; |
| 281 | } |
| 282 | md; |
| 283 | |
| 284 | /* application registers: */ |
| 285 | |
| 286 | #define AR_K0 0 |
| 287 | #define AR_K7 7 |
| 288 | #define AR_RSC 16 |
| 289 | #define AR_BSP 17 |
| 290 | #define AR_BSPSTORE 18 |
| 291 | #define AR_RNAT 19 |
| 292 | #define AR_UNAT 36 |
| 293 | #define AR_FPSR 40 |
| 294 | #define AR_ITC 44 |
| 295 | #define AR_PFS 64 |
| 296 | #define AR_LC 65 |
| 297 | |
| 298 | static const struct |
| 299 | { |
| 300 | const char *name; |
| 301 | int regnum; |
| 302 | } |
| 303 | ar[] = |
| 304 | { |
| 305 | {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, |
| 306 | {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, |
| 307 | {"ar.rsc", 16}, {"ar.bsp", 17}, |
| 308 | {"ar.bspstore", 18}, {"ar.rnat", 19}, |
| 309 | {"ar.fcr", 21}, {"ar.eflag", 24}, |
| 310 | {"ar.csd", 25}, {"ar.ssd", 26}, |
| 311 | {"ar.cflg", 27}, {"ar.fsr", 28}, |
| 312 | {"ar.fir", 29}, {"ar.fdr", 30}, |
| 313 | {"ar.ccv", 32}, {"ar.unat", 36}, |
| 314 | {"ar.fpsr", 40}, {"ar.itc", 44}, |
| 315 | {"ar.pfs", 64}, {"ar.lc", 65}, |
| 316 | {"ar.ec", 66}, |
| 317 | }; |
| 318 | |
| 319 | #define CR_IPSR 16 |
| 320 | #define CR_ISR 17 |
| 321 | #define CR_IIP 19 |
| 322 | #define CR_IFA 20 |
| 323 | #define CR_ITIR 21 |
| 324 | #define CR_IIPA 22 |
| 325 | #define CR_IFS 23 |
| 326 | #define CR_IIM 24 |
| 327 | #define CR_IHA 25 |
| 328 | #define CR_IVR 65 |
| 329 | #define CR_TPR 66 |
| 330 | #define CR_EOI 67 |
| 331 | #define CR_IRR0 68 |
| 332 | #define CR_IRR3 71 |
| 333 | #define CR_LRR0 80 |
| 334 | #define CR_LRR1 81 |
| 335 | |
| 336 | /* control registers: */ |
| 337 | static const struct |
| 338 | { |
| 339 | const char *name; |
| 340 | int regnum; |
| 341 | } |
| 342 | cr[] = |
| 343 | { |
| 344 | {"cr.dcr", 0}, |
| 345 | {"cr.itm", 1}, |
| 346 | {"cr.iva", 2}, |
| 347 | {"cr.pta", 8}, |
| 348 | {"cr.gpta", 9}, |
| 349 | {"cr.ipsr", 16}, |
| 350 | {"cr.isr", 17}, |
| 351 | {"cr.iip", 19}, |
| 352 | {"cr.ifa", 20}, |
| 353 | {"cr.itir", 21}, |
| 354 | {"cr.iipa", 22}, |
| 355 | {"cr.ifs", 23}, |
| 356 | {"cr.iim", 24}, |
| 357 | {"cr.iha", 25}, |
| 358 | {"cr.lid", 64}, |
| 359 | {"cr.ivr", 65}, |
| 360 | {"cr.tpr", 66}, |
| 361 | {"cr.eoi", 67}, |
| 362 | {"cr.irr0", 68}, |
| 363 | {"cr.irr1", 69}, |
| 364 | {"cr.irr2", 70}, |
| 365 | {"cr.irr3", 71}, |
| 366 | {"cr.itv", 72}, |
| 367 | {"cr.pmv", 73}, |
| 368 | {"cr.cmcv", 74}, |
| 369 | {"cr.lrr0", 80}, |
| 370 | {"cr.lrr1", 81} |
| 371 | }; |
| 372 | |
| 373 | #define PSR_MFL 4 |
| 374 | #define PSR_IC 13 |
| 375 | #define PSR_DFL 18 |
| 376 | #define PSR_CPL 32 |
| 377 | |
| 378 | static const struct const_desc |
| 379 | { |
| 380 | const char *name; |
| 381 | valueT value; |
| 382 | } |
| 383 | const_bits[] = |
| 384 | { |
| 385 | /* PSR constant masks: */ |
| 386 | |
| 387 | /* 0: reserved */ |
| 388 | {"psr.be", ((valueT) 1) << 1}, |
| 389 | {"psr.up", ((valueT) 1) << 2}, |
| 390 | {"psr.ac", ((valueT) 1) << 3}, |
| 391 | {"psr.mfl", ((valueT) 1) << 4}, |
| 392 | {"psr.mfh", ((valueT) 1) << 5}, |
| 393 | /* 6-12: reserved */ |
| 394 | {"psr.ic", ((valueT) 1) << 13}, |
| 395 | {"psr.i", ((valueT) 1) << 14}, |
| 396 | {"psr.pk", ((valueT) 1) << 15}, |
| 397 | /* 16: reserved */ |
| 398 | {"psr.dt", ((valueT) 1) << 17}, |
| 399 | {"psr.dfl", ((valueT) 1) << 18}, |
| 400 | {"psr.dfh", ((valueT) 1) << 19}, |
| 401 | {"psr.sp", ((valueT) 1) << 20}, |
| 402 | {"psr.pp", ((valueT) 1) << 21}, |
| 403 | {"psr.di", ((valueT) 1) << 22}, |
| 404 | {"psr.si", ((valueT) 1) << 23}, |
| 405 | {"psr.db", ((valueT) 1) << 24}, |
| 406 | {"psr.lp", ((valueT) 1) << 25}, |
| 407 | {"psr.tb", ((valueT) 1) << 26}, |
| 408 | {"psr.rt", ((valueT) 1) << 27}, |
| 409 | /* 28-31: reserved */ |
| 410 | /* 32-33: cpl (current privilege level) */ |
| 411 | {"psr.is", ((valueT) 1) << 34}, |
| 412 | {"psr.mc", ((valueT) 1) << 35}, |
| 413 | {"psr.it", ((valueT) 1) << 36}, |
| 414 | {"psr.id", ((valueT) 1) << 37}, |
| 415 | {"psr.da", ((valueT) 1) << 38}, |
| 416 | {"psr.dd", ((valueT) 1) << 39}, |
| 417 | {"psr.ss", ((valueT) 1) << 40}, |
| 418 | /* 41-42: ri (restart instruction) */ |
| 419 | {"psr.ed", ((valueT) 1) << 43}, |
| 420 | {"psr.bn", ((valueT) 1) << 44}, |
| 421 | }; |
| 422 | |
| 423 | /* indirect register-sets/memory: */ |
| 424 | |
| 425 | static const struct |
| 426 | { |
| 427 | const char *name; |
| 428 | int regnum; |
| 429 | } |
| 430 | indirect_reg[] = |
| 431 | { |
| 432 | { "CPUID", IND_CPUID }, |
| 433 | { "cpuid", IND_CPUID }, |
| 434 | { "dbr", IND_DBR }, |
| 435 | { "dtr", IND_DTR }, |
| 436 | { "itr", IND_ITR }, |
| 437 | { "ibr", IND_IBR }, |
| 438 | { "msr", IND_MSR }, |
| 439 | { "pkr", IND_PKR }, |
| 440 | { "pmc", IND_PMC }, |
| 441 | { "pmd", IND_PMD }, |
| 442 | { "rr", IND_RR }, |
| 443 | }; |
| 444 | |
| 445 | /* Pseudo functions used to indicate relocation types (these functions |
| 446 | start with an at sign (@). */ |
| 447 | static struct |
| 448 | { |
| 449 | const char *name; |
| 450 | enum pseudo_type |
| 451 | { |
| 452 | PSEUDO_FUNC_NONE, |
| 453 | PSEUDO_FUNC_RELOC, |
| 454 | PSEUDO_FUNC_CONST, |
| 455 | PSEUDO_FUNC_REG, |
| 456 | PSEUDO_FUNC_FLOAT |
| 457 | } |
| 458 | type; |
| 459 | union |
| 460 | { |
| 461 | unsigned long ival; |
| 462 | symbolS *sym; |
| 463 | } |
| 464 | u; |
| 465 | } |
| 466 | pseudo_func[] = |
| 467 | { |
| 468 | /* reloc pseudo functions (these must come first!): */ |
| 469 | { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, |
| 470 | { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 471 | { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, |
| 472 | { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 473 | { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, |
| 474 | { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 475 | { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, |
| 476 | { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, |
| 477 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ |
| 478 | |
| 479 | /* mbtype4 constants: */ |
| 480 | { "alt", PSEUDO_FUNC_CONST, { 0xa } }, |
| 481 | { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, |
| 482 | { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, |
| 483 | { "rev", PSEUDO_FUNC_CONST, { 0xb } }, |
| 484 | { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, |
| 485 | |
| 486 | /* fclass constants: */ |
| 487 | { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, |
| 488 | { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, |
| 489 | { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, |
| 490 | { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, |
| 491 | { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, |
| 492 | { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, |
| 493 | { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, |
| 494 | { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, |
| 495 | { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, |
| 496 | |
| 497 | { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ |
| 498 | |
| 499 | /* unwind-related constants: */ |
| 500 | { "svr4", PSEUDO_FUNC_CONST, { 0 } }, |
| 501 | { "hpux", PSEUDO_FUNC_CONST, { 1 } }, |
| 502 | { "nt", PSEUDO_FUNC_CONST, { 2 } }, |
| 503 | |
| 504 | /* unwind-related registers: */ |
| 505 | { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } |
| 506 | }; |
| 507 | |
| 508 | /* 41-bit nop opcodes (one per unit): */ |
| 509 | static const bfd_vma nop[IA64_NUM_UNITS] = |
| 510 | { |
| 511 | 0x0000000000LL, /* NIL => break 0 */ |
| 512 | 0x0008000000LL, /* I-unit nop */ |
| 513 | 0x0008000000LL, /* M-unit nop */ |
| 514 | 0x4000000000LL, /* B-unit nop */ |
| 515 | 0x0008000000LL, /* F-unit nop */ |
| 516 | 0x0008000000LL, /* L-"unit" nop */ |
| 517 | 0x0008000000LL, /* X-unit nop */ |
| 518 | }; |
| 519 | |
| 520 | /* Can't be `const' as it's passed to input routines (which have the |
| 521 | habit of setting temporary sentinels. */ |
| 522 | static char special_section_name[][20] = |
| 523 | { |
| 524 | {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, |
| 525 | {".IA_64.unwind"}, {".IA_64.unwind_info"} |
| 526 | }; |
| 527 | |
| 528 | /* The best template for a particular sequence of up to three |
| 529 | instructions: */ |
| 530 | #define N IA64_NUM_TYPES |
| 531 | static unsigned char best_template[N][N][N]; |
| 532 | #undef N |
| 533 | |
| 534 | /* Resource dependencies currently in effect */ |
| 535 | static struct rsrc { |
| 536 | int depind; /* dependency index */ |
| 537 | const struct ia64_dependency *dependency; /* actual dependency */ |
| 538 | unsigned specific:1, /* is this a specific bit/regno? */ |
| 539 | link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ |
| 540 | int index; /* specific regno/bit within dependency */ |
| 541 | int note; /* optional qualifying note (0 if none) */ |
| 542 | #define STATE_NONE 0 |
| 543 | #define STATE_STOP 1 |
| 544 | #define STATE_SRLZ 2 |
| 545 | int insn_srlz; /* current insn serialization state */ |
| 546 | int data_srlz; /* current data serialization state */ |
| 547 | int qp_regno; /* qualifying predicate for this usage */ |
| 548 | char *file; /* what file marked this dependency */ |
| 549 | unsigned int line; /* what line marked this dependency */ |
| 550 | struct mem_offset mem_offset; /* optional memory offset hint */ |
| 551 | enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ |
| 552 | int path; /* corresponding code entry index */ |
| 553 | } *regdeps = NULL; |
| 554 | static int regdepslen = 0; |
| 555 | static int regdepstotlen = 0; |
| 556 | static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; |
| 557 | static const char *dv_sem[] = { "none", "implied", "impliedf", |
| 558 | "data", "instr", "specific", "stop", "other" }; |
| 559 | static const char *dv_cmp_type[] = { "none", "OR", "AND" }; |
| 560 | |
| 561 | /* Current state of PR mutexation */ |
| 562 | static struct qpmutex { |
| 563 | valueT prmask; |
| 564 | int path; |
| 565 | } *qp_mutexes = NULL; /* QP mutex bitmasks */ |
| 566 | static int qp_mutexeslen = 0; |
| 567 | static int qp_mutexestotlen = 0; |
| 568 | static valueT qp_safe_across_calls = 0; |
| 569 | |
| 570 | /* Current state of PR implications */ |
| 571 | static struct qp_imply { |
| 572 | unsigned p1:6; |
| 573 | unsigned p2:6; |
| 574 | unsigned p2_branched:1; |
| 575 | int path; |
| 576 | } *qp_implies = NULL; |
| 577 | static int qp_implieslen = 0; |
| 578 | static int qp_impliestotlen = 0; |
| 579 | |
| 580 | /* Keep track of static GR values so that indirect register usage can |
| 581 | sometimes be tracked. */ |
| 582 | static struct gr { |
| 583 | unsigned known:1; |
| 584 | int path; |
| 585 | valueT value; |
| 586 | } gr_values[128] = {{ 1, 0, 0 }}; |
| 587 | |
| 588 | /* These are the routines required to output the various types of |
| 589 | unwind records. */ |
| 590 | |
| 591 | /* A slot_number is a frag address plus the slot index (0-2). We use the |
| 592 | frag address here so that if there is a section switch in the middle of |
| 593 | a function, then instructions emitted to a different section are not |
| 594 | counted. Since there may be more than one frag for a function, this |
| 595 | means we also need to keep track of which frag this address belongs to |
| 596 | so we can compute inter-frag distances. This also nicely solves the |
| 597 | problem with nops emitted for align directives, which can't easily be |
| 598 | counted, but can easily be derived from frag sizes. */ |
| 599 | |
| 600 | typedef struct unw_rec_list { |
| 601 | unwind_record r; |
| 602 | unsigned long slot_number; |
| 603 | fragS *slot_frag; |
| 604 | struct unw_rec_list *next; |
| 605 | } unw_rec_list; |
| 606 | |
| 607 | #define SLOT_NUM_NOT_SET (unsigned)-1 |
| 608 | |
| 609 | static struct |
| 610 | { |
| 611 | unsigned long next_slot_number; |
| 612 | fragS *next_slot_frag; |
| 613 | |
| 614 | /* Maintain a list of unwind entries for the current function. */ |
| 615 | unw_rec_list *list; |
| 616 | unw_rec_list *tail; |
| 617 | |
| 618 | /* Any unwind entires that should be attached to the current slot |
| 619 | that an insn is being constructed for. */ |
| 620 | unw_rec_list *current_entry; |
| 621 | |
| 622 | /* These are used to create the unwind table entry for this function. */ |
| 623 | symbolS *proc_start; |
| 624 | symbolS *proc_end; |
| 625 | symbolS *info; /* pointer to unwind info */ |
| 626 | symbolS *personality_routine; |
| 627 | segT saved_text_seg; |
| 628 | subsegT saved_text_subseg; |
| 629 | unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */ |
| 630 | |
| 631 | /* TRUE if processing unwind directives in a prologue region. */ |
| 632 | int prologue; |
| 633 | int prologue_mask; |
| 634 | unsigned int prologue_count; /* number of .prologues seen so far */ |
| 635 | } unwind; |
| 636 | |
| 637 | typedef void (*vbyte_func) PARAMS ((int, char *, char *)); |
| 638 | |
| 639 | /* Forward delarations: */ |
| 640 | static int ar_is_in_integer_unit PARAMS ((int regnum)); |
| 641 | static void set_section PARAMS ((char *name)); |
| 642 | static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, |
| 643 | unsigned int, unsigned int)); |
| 644 | static void dot_radix PARAMS ((int)); |
| 645 | static void dot_special_section PARAMS ((int)); |
| 646 | static void dot_proc PARAMS ((int)); |
| 647 | static void dot_fframe PARAMS ((int)); |
| 648 | static void dot_vframe PARAMS ((int)); |
| 649 | static void dot_vframesp PARAMS ((int)); |
| 650 | static void dot_vframepsp PARAMS ((int)); |
| 651 | static void dot_save PARAMS ((int)); |
| 652 | static void dot_restore PARAMS ((int)); |
| 653 | static void dot_restorereg PARAMS ((int)); |
| 654 | static void dot_restorereg_p PARAMS ((int)); |
| 655 | static void dot_handlerdata PARAMS ((int)); |
| 656 | static void dot_unwentry PARAMS ((int)); |
| 657 | static void dot_altrp PARAMS ((int)); |
| 658 | static void dot_savemem PARAMS ((int)); |
| 659 | static void dot_saveg PARAMS ((int)); |
| 660 | static void dot_savef PARAMS ((int)); |
| 661 | static void dot_saveb PARAMS ((int)); |
| 662 | static void dot_savegf PARAMS ((int)); |
| 663 | static void dot_spill PARAMS ((int)); |
| 664 | static void dot_spillreg PARAMS ((int)); |
| 665 | static void dot_spillmem PARAMS ((int)); |
| 666 | static void dot_spillreg_p PARAMS ((int)); |
| 667 | static void dot_spillmem_p PARAMS ((int)); |
| 668 | static void dot_label_state PARAMS ((int)); |
| 669 | static void dot_copy_state PARAMS ((int)); |
| 670 | static void dot_unwabi PARAMS ((int)); |
| 671 | static void dot_personality PARAMS ((int)); |
| 672 | static void dot_body PARAMS ((int)); |
| 673 | static void dot_prologue PARAMS ((int)); |
| 674 | static void dot_endp PARAMS ((int)); |
| 675 | static void dot_template PARAMS ((int)); |
| 676 | static void dot_regstk PARAMS ((int)); |
| 677 | static void dot_rot PARAMS ((int)); |
| 678 | static void dot_byteorder PARAMS ((int)); |
| 679 | static void dot_psr PARAMS ((int)); |
| 680 | static void dot_alias PARAMS ((int)); |
| 681 | static void dot_ln PARAMS ((int)); |
| 682 | static char *parse_section_name PARAMS ((void)); |
| 683 | static void dot_xdata PARAMS ((int)); |
| 684 | static void stmt_float_cons PARAMS ((int)); |
| 685 | static void stmt_cons_ua PARAMS ((int)); |
| 686 | static void dot_xfloat_cons PARAMS ((int)); |
| 687 | static void dot_xstringer PARAMS ((int)); |
| 688 | static void dot_xdata_ua PARAMS ((int)); |
| 689 | static void dot_xfloat_cons_ua PARAMS ((int)); |
| 690 | static void print_prmask PARAMS ((valueT mask)); |
| 691 | static void dot_pred_rel PARAMS ((int)); |
| 692 | static void dot_reg_val PARAMS ((int)); |
| 693 | static void dot_dv_mode PARAMS ((int)); |
| 694 | static void dot_entry PARAMS ((int)); |
| 695 | static void dot_mem_offset PARAMS ((int)); |
| 696 | static void add_unwind_entry PARAMS((unw_rec_list *ptr)); |
| 697 | static symbolS *declare_register PARAMS ((const char *name, int regnum)); |
| 698 | static void declare_register_set PARAMS ((const char *, int, int)); |
| 699 | static unsigned int operand_width PARAMS ((enum ia64_opnd)); |
| 700 | static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc, |
| 701 | int index, |
| 702 | expressionS *e)); |
| 703 | static int parse_operand PARAMS ((expressionS *e)); |
| 704 | static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); |
| 705 | static void build_insn PARAMS ((struct slot *, bfd_vma *)); |
| 706 | static void emit_one_bundle PARAMS ((void)); |
| 707 | static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); |
| 708 | static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, |
| 709 | bfd_reloc_code_real_type r_type)); |
| 710 | static void insn_group_break PARAMS ((int, int, int)); |
| 711 | static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, |
| 712 | struct rsrc *, int depind, int path)); |
| 713 | static void add_qp_mutex PARAMS((valueT mask)); |
| 714 | static void add_qp_imply PARAMS((int p1, int p2)); |
| 715 | static void clear_qp_branch_flag PARAMS((valueT mask)); |
| 716 | static void clear_qp_mutex PARAMS((valueT mask)); |
| 717 | static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); |
| 718 | static void clear_register_values PARAMS ((void)); |
| 719 | static void print_dependency PARAMS ((const char *action, int depind)); |
| 720 | static void instruction_serialization PARAMS ((void)); |
| 721 | static void data_serialization PARAMS ((void)); |
| 722 | static void remove_marked_resource PARAMS ((struct rsrc *)); |
| 723 | static int is_conditional_branch PARAMS ((struct ia64_opcode *)); |
| 724 | static int is_taken_branch PARAMS ((struct ia64_opcode *)); |
| 725 | static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); |
| 726 | static int depends_on PARAMS ((int, struct ia64_opcode *)); |
| 727 | static int specify_resource PARAMS ((const struct ia64_dependency *, |
| 728 | struct ia64_opcode *, int, struct rsrc [], int, int)); |
| 729 | static int check_dv PARAMS((struct ia64_opcode *idesc)); |
| 730 | static void check_dependencies PARAMS((struct ia64_opcode *)); |
| 731 | static void mark_resources PARAMS((struct ia64_opcode *)); |
| 732 | static void update_dependencies PARAMS((struct ia64_opcode *)); |
| 733 | static void note_register_values PARAMS((struct ia64_opcode *)); |
| 734 | static int qp_mutex PARAMS ((int, int, int)); |
| 735 | static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); |
| 736 | static void output_vbyte_mem PARAMS ((int, char *, char *)); |
| 737 | static void count_output PARAMS ((int, char *, char *)); |
| 738 | static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); |
| 739 | static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); |
| 740 | static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
| 741 | static void output_P1_format PARAMS ((vbyte_func, int)); |
| 742 | static void output_P2_format PARAMS ((vbyte_func, int, int)); |
| 743 | static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); |
| 744 | static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); |
| 745 | static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); |
| 746 | static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); |
| 747 | static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); |
| 748 | static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
| 749 | static void output_P9_format PARAMS ((vbyte_func, int, int)); |
| 750 | static void output_P10_format PARAMS ((vbyte_func, int, int)); |
| 751 | static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
| 752 | static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); |
| 753 | static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); |
| 754 | static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
| 755 | static char format_ab_reg PARAMS ((int, int)); |
| 756 | static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, |
| 757 | unsigned long)); |
| 758 | static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); |
| 759 | static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, |
| 760 | unsigned long)); |
| 761 | static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); |
| 762 | static void free_list_records PARAMS ((unw_rec_list *)); |
| 763 | static unw_rec_list *output_prologue PARAMS ((void)); |
| 764 | static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); |
| 765 | static unw_rec_list *output_body PARAMS ((void)); |
| 766 | static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); |
| 767 | static unw_rec_list *output_mem_stack_v PARAMS ((void)); |
| 768 | static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); |
| 769 | static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); |
| 770 | static unw_rec_list *output_rp_when PARAMS ((void)); |
| 771 | static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); |
| 772 | static unw_rec_list *output_rp_br PARAMS ((unsigned int)); |
| 773 | static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); |
| 774 | static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); |
| 775 | static unw_rec_list *output_pfs_when PARAMS ((void)); |
| 776 | static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); |
| 777 | static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); |
| 778 | static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); |
| 779 | static unw_rec_list *output_preds_when PARAMS ((void)); |
| 780 | static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); |
| 781 | static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); |
| 782 | static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); |
| 783 | static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); |
| 784 | static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); |
| 785 | static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); |
| 786 | static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); |
| 787 | static unw_rec_list *output_br_mem PARAMS ((unsigned int)); |
| 788 | static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); |
| 789 | static unw_rec_list *output_spill_base PARAMS ((unsigned int)); |
| 790 | static unw_rec_list *output_unat_when PARAMS ((void)); |
| 791 | static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); |
| 792 | static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); |
| 793 | static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); |
| 794 | static unw_rec_list *output_lc_when PARAMS ((void)); |
| 795 | static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); |
| 796 | static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); |
| 797 | static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); |
| 798 | static unw_rec_list *output_fpsr_when PARAMS ((void)); |
| 799 | static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); |
| 800 | static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); |
| 801 | static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); |
| 802 | static unw_rec_list *output_priunat_when_gr PARAMS ((void)); |
| 803 | static unw_rec_list *output_priunat_when_mem PARAMS ((void)); |
| 804 | static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); |
| 805 | static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); |
| 806 | static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); |
| 807 | static unw_rec_list *output_bsp_when PARAMS ((void)); |
| 808 | static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); |
| 809 | static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); |
| 810 | static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); |
| 811 | static unw_rec_list *output_bspstore_when PARAMS ((void)); |
| 812 | static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); |
| 813 | static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); |
| 814 | static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); |
| 815 | static unw_rec_list *output_rnat_when PARAMS ((void)); |
| 816 | static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); |
| 817 | static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); |
| 818 | static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); |
| 819 | static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); |
| 820 | static unw_rec_list *output_epilogue PARAMS ((unsigned long)); |
| 821 | static unw_rec_list *output_label_state PARAMS ((unsigned long)); |
| 822 | static unw_rec_list *output_copy_state PARAMS ((unsigned long)); |
| 823 | static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); |
| 824 | static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); |
| 825 | static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, |
| 826 | unsigned int)); |
| 827 | static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, |
| 828 | unsigned int)); |
| 829 | static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, |
| 830 | unsigned int)); |
| 831 | static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, |
| 832 | unsigned int, unsigned int)); |
| 833 | static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); |
| 834 | static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); |
| 835 | static int calc_record_size PARAMS ((unw_rec_list *)); |
| 836 | static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); |
| 837 | static int count_bits PARAMS ((unsigned long)); |
| 838 | static unsigned long slot_index PARAMS ((unsigned long, fragS *, |
| 839 | unsigned long, fragS *)); |
| 840 | static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *)); |
| 841 | static void fixup_unw_records PARAMS ((unw_rec_list *)); |
| 842 | static int output_unw_records PARAMS ((unw_rec_list *, void **)); |
| 843 | static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); |
| 844 | static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); |
| 845 | static int generate_unwind_image PARAMS ((const char *)); |
| 846 | |
| 847 | /* Build the unwind section name by appending the (possibly stripped) |
| 848 | text section NAME to the unwind PREFIX. The resulting string |
| 849 | pointer is assigned to RESULT. The string is allocated on the |
| 850 | stack, so this must be a macro... */ |
| 851 | #define make_unw_section_name(special, text_name, result) \ |
| 852 | { \ |
| 853 | char *_prefix = special_section_name[special]; \ |
| 854 | size_t _prefix_len = strlen (_prefix), _text_len = strlen (text_name); \ |
| 855 | char *_result = alloca (_prefix_len + _text_len + 1); \ |
| 856 | memcpy(_result, _prefix, _prefix_len); \ |
| 857 | memcpy(_result + _prefix_len, text_name, _text_len); \ |
| 858 | _result[_prefix_len + _text_len] = '\0'; \ |
| 859 | result = _result; \ |
| 860 | } \ |
| 861 | while (0) |
| 862 | |
| 863 | /* Determine if application register REGNUM resides in the integer |
| 864 | unit (as opposed to the memory unit). */ |
| 865 | static int |
| 866 | ar_is_in_integer_unit (reg) |
| 867 | int reg; |
| 868 | { |
| 869 | reg -= REG_AR; |
| 870 | |
| 871 | return (reg == 64 /* pfs */ |
| 872 | || reg == 65 /* lc */ |
| 873 | || reg == 66 /* ec */ |
| 874 | /* ??? ias accepts and puts these in the integer unit. */ |
| 875 | || (reg >= 112 && reg <= 127)); |
| 876 | } |
| 877 | |
| 878 | /* Switch to section NAME and create section if necessary. It's |
| 879 | rather ugly that we have to manipulate input_line_pointer but I |
| 880 | don't see any other way to accomplish the same thing without |
| 881 | changing obj-elf.c (which may be the Right Thing, in the end). */ |
| 882 | static void |
| 883 | set_section (name) |
| 884 | char *name; |
| 885 | { |
| 886 | char *saved_input_line_pointer; |
| 887 | |
| 888 | saved_input_line_pointer = input_line_pointer; |
| 889 | input_line_pointer = name; |
| 890 | obj_elf_section (0); |
| 891 | input_line_pointer = saved_input_line_pointer; |
| 892 | } |
| 893 | |
| 894 | /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ |
| 895 | |
| 896 | flagword |
| 897 | ia64_elf_section_flags (flags, attr, type) |
| 898 | flagword flags; |
| 899 | int attr, type ATTRIBUTE_UNUSED; |
| 900 | { |
| 901 | if (attr & SHF_IA_64_SHORT) |
| 902 | flags |= SEC_SMALL_DATA; |
| 903 | return flags; |
| 904 | } |
| 905 | |
| 906 | int |
| 907 | ia64_elf_section_type (str, len) |
| 908 | const char *str; |
| 909 | size_t len; |
| 910 | { |
| 911 | len = sizeof (ELF_STRING_ia64_unwind_info) - 1; |
| 912 | if (strncmp (str, ELF_STRING_ia64_unwind_info, len) == 0) |
| 913 | return SHT_PROGBITS; |
| 914 | |
| 915 | len = sizeof (ELF_STRING_ia64_unwind) - 1; |
| 916 | if (strncmp (str, ELF_STRING_ia64_unwind, len) == 0) |
| 917 | return SHT_IA_64_UNWIND; |
| 918 | |
| 919 | return -1; |
| 920 | } |
| 921 | |
| 922 | static unsigned int |
| 923 | set_regstack (ins, locs, outs, rots) |
| 924 | unsigned int ins, locs, outs, rots; |
| 925 | { |
| 926 | /* Size of frame. */ |
| 927 | unsigned int sof; |
| 928 | |
| 929 | sof = ins + locs + outs; |
| 930 | if (sof > 96) |
| 931 | { |
| 932 | as_bad ("Size of frame exceeds maximum of 96 registers"); |
| 933 | return 0; |
| 934 | } |
| 935 | if (rots > sof) |
| 936 | { |
| 937 | as_warn ("Size of rotating registers exceeds frame size"); |
| 938 | return 0; |
| 939 | } |
| 940 | md.in.base = REG_GR + 32; |
| 941 | md.loc.base = md.in.base + ins; |
| 942 | md.out.base = md.loc.base + locs; |
| 943 | |
| 944 | md.in.num_regs = ins; |
| 945 | md.loc.num_regs = locs; |
| 946 | md.out.num_regs = outs; |
| 947 | md.rot.num_regs = rots; |
| 948 | return sof; |
| 949 | } |
| 950 | |
| 951 | void |
| 952 | ia64_flush_insns () |
| 953 | { |
| 954 | struct label_fix *lfix; |
| 955 | segT saved_seg; |
| 956 | subsegT saved_subseg; |
| 957 | unw_rec_list *ptr; |
| 958 | |
| 959 | if (!md.last_text_seg) |
| 960 | return; |
| 961 | |
| 962 | saved_seg = now_seg; |
| 963 | saved_subseg = now_subseg; |
| 964 | |
| 965 | subseg_set (md.last_text_seg, 0); |
| 966 | |
| 967 | while (md.num_slots_in_use > 0) |
| 968 | emit_one_bundle (); /* force out queued instructions */ |
| 969 | |
| 970 | /* In case there are labels following the last instruction, resolve |
| 971 | those now: */ |
| 972 | for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) |
| 973 | { |
| 974 | S_SET_VALUE (lfix->sym, frag_now_fix ()); |
| 975 | symbol_set_frag (lfix->sym, frag_now); |
| 976 | } |
| 977 | CURR_SLOT.label_fixups = 0; |
| 978 | for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) |
| 979 | { |
| 980 | S_SET_VALUE (lfix->sym, frag_now_fix ()); |
| 981 | symbol_set_frag (lfix->sym, frag_now); |
| 982 | } |
| 983 | CURR_SLOT.tag_fixups = 0; |
| 984 | |
| 985 | /* In case there are unwind directives following the last instruction, |
| 986 | resolve those now. We only handle body and prologue directives here. |
| 987 | Give an error for others. */ |
| 988 | for (ptr = unwind.current_entry; ptr; ptr = ptr->next) |
| 989 | { |
| 990 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr |
| 991 | || ptr->r.type == body) |
| 992 | { |
| 993 | ptr->slot_number = (unsigned long) frag_more (0); |
| 994 | ptr->slot_frag = frag_now; |
| 995 | } |
| 996 | else |
| 997 | as_bad (_("Unwind directive not followed by an instruction.")); |
| 998 | } |
| 999 | unwind.current_entry = NULL; |
| 1000 | |
| 1001 | subseg_set (saved_seg, saved_subseg); |
| 1002 | |
| 1003 | if (md.qp.X_op == O_register) |
| 1004 | as_bad ("qualifying predicate not followed by instruction"); |
| 1005 | } |
| 1006 | |
| 1007 | void |
| 1008 | ia64_do_align (nbytes) |
| 1009 | int nbytes; |
| 1010 | { |
| 1011 | char *saved_input_line_pointer = input_line_pointer; |
| 1012 | |
| 1013 | input_line_pointer = ""; |
| 1014 | s_align_bytes (nbytes); |
| 1015 | input_line_pointer = saved_input_line_pointer; |
| 1016 | } |
| 1017 | |
| 1018 | void |
| 1019 | ia64_cons_align (nbytes) |
| 1020 | int nbytes; |
| 1021 | { |
| 1022 | if (md.auto_align) |
| 1023 | { |
| 1024 | char *saved_input_line_pointer = input_line_pointer; |
| 1025 | input_line_pointer = ""; |
| 1026 | s_align_bytes (nbytes); |
| 1027 | input_line_pointer = saved_input_line_pointer; |
| 1028 | } |
| 1029 | } |
| 1030 | |
| 1031 | /* Output COUNT bytes to a memory location. */ |
| 1032 | static unsigned char *vbyte_mem_ptr = NULL; |
| 1033 | |
| 1034 | void |
| 1035 | output_vbyte_mem (count, ptr, comment) |
| 1036 | int count; |
| 1037 | char *ptr; |
| 1038 | char *comment ATTRIBUTE_UNUSED; |
| 1039 | { |
| 1040 | int x; |
| 1041 | if (vbyte_mem_ptr == NULL) |
| 1042 | abort (); |
| 1043 | |
| 1044 | if (count == 0) |
| 1045 | return; |
| 1046 | for (x = 0; x < count; x++) |
| 1047 | *(vbyte_mem_ptr++) = ptr[x]; |
| 1048 | } |
| 1049 | |
| 1050 | /* Count the number of bytes required for records. */ |
| 1051 | static int vbyte_count = 0; |
| 1052 | void |
| 1053 | count_output (count, ptr, comment) |
| 1054 | int count; |
| 1055 | char *ptr ATTRIBUTE_UNUSED; |
| 1056 | char *comment ATTRIBUTE_UNUSED; |
| 1057 | { |
| 1058 | vbyte_count += count; |
| 1059 | } |
| 1060 | |
| 1061 | static void |
| 1062 | output_R1_format (f, rtype, rlen) |
| 1063 | vbyte_func f; |
| 1064 | unw_record_type rtype; |
| 1065 | int rlen; |
| 1066 | { |
| 1067 | int r = 0; |
| 1068 | char byte; |
| 1069 | if (rlen > 0x1f) |
| 1070 | { |
| 1071 | output_R3_format (f, rtype, rlen); |
| 1072 | return; |
| 1073 | } |
| 1074 | |
| 1075 | if (rtype == body) |
| 1076 | r = 1; |
| 1077 | else if (rtype != prologue) |
| 1078 | as_bad ("record type is not valid"); |
| 1079 | |
| 1080 | byte = UNW_R1 | (r << 5) | (rlen & 0x1f); |
| 1081 | (*f) (1, &byte, NULL); |
| 1082 | } |
| 1083 | |
| 1084 | static void |
| 1085 | output_R2_format (f, mask, grsave, rlen) |
| 1086 | vbyte_func f; |
| 1087 | int mask, grsave; |
| 1088 | unsigned long rlen; |
| 1089 | { |
| 1090 | char bytes[20]; |
| 1091 | int count = 2; |
| 1092 | mask = (mask & 0x0f); |
| 1093 | grsave = (grsave & 0x7f); |
| 1094 | |
| 1095 | bytes[0] = (UNW_R2 | (mask >> 1)); |
| 1096 | bytes[1] = (((mask & 0x01) << 7) | grsave); |
| 1097 | count += output_leb128 (bytes + 2, rlen, 0); |
| 1098 | (*f) (count, bytes, NULL); |
| 1099 | } |
| 1100 | |
| 1101 | static void |
| 1102 | output_R3_format (f, rtype, rlen) |
| 1103 | vbyte_func f; |
| 1104 | unw_record_type rtype; |
| 1105 | unsigned long rlen; |
| 1106 | { |
| 1107 | int r = 0, count; |
| 1108 | char bytes[20]; |
| 1109 | if (rlen <= 0x1f) |
| 1110 | { |
| 1111 | output_R1_format (f, rtype, rlen); |
| 1112 | return; |
| 1113 | } |
| 1114 | |
| 1115 | if (rtype == body) |
| 1116 | r = 1; |
| 1117 | else if (rtype != prologue) |
| 1118 | as_bad ("record type is not valid"); |
| 1119 | bytes[0] = (UNW_R3 | r); |
| 1120 | count = output_leb128 (bytes + 1, rlen, 0); |
| 1121 | (*f) (count + 1, bytes, NULL); |
| 1122 | } |
| 1123 | |
| 1124 | static void |
| 1125 | output_P1_format (f, brmask) |
| 1126 | vbyte_func f; |
| 1127 | int brmask; |
| 1128 | { |
| 1129 | char byte; |
| 1130 | byte = UNW_P1 | (brmask & 0x1f); |
| 1131 | (*f) (1, &byte, NULL); |
| 1132 | } |
| 1133 | |
| 1134 | static void |
| 1135 | output_P2_format (f, brmask, gr) |
| 1136 | vbyte_func f; |
| 1137 | int brmask; |
| 1138 | int gr; |
| 1139 | { |
| 1140 | char bytes[2]; |
| 1141 | brmask = (brmask & 0x1f); |
| 1142 | bytes[0] = UNW_P2 | (brmask >> 1); |
| 1143 | bytes[1] = (((brmask & 1) << 7) | gr); |
| 1144 | (*f) (2, bytes, NULL); |
| 1145 | } |
| 1146 | |
| 1147 | static void |
| 1148 | output_P3_format (f, rtype, reg) |
| 1149 | vbyte_func f; |
| 1150 | unw_record_type rtype; |
| 1151 | int reg; |
| 1152 | { |
| 1153 | char bytes[2]; |
| 1154 | int r = 0; |
| 1155 | reg = (reg & 0x7f); |
| 1156 | switch (rtype) |
| 1157 | { |
| 1158 | case psp_gr: |
| 1159 | r = 0; |
| 1160 | break; |
| 1161 | case rp_gr: |
| 1162 | r = 1; |
| 1163 | break; |
| 1164 | case pfs_gr: |
| 1165 | r = 2; |
| 1166 | break; |
| 1167 | case preds_gr: |
| 1168 | r = 3; |
| 1169 | break; |
| 1170 | case unat_gr: |
| 1171 | r = 4; |
| 1172 | break; |
| 1173 | case lc_gr: |
| 1174 | r = 5; |
| 1175 | break; |
| 1176 | case rp_br: |
| 1177 | r = 6; |
| 1178 | break; |
| 1179 | case rnat_gr: |
| 1180 | r = 7; |
| 1181 | break; |
| 1182 | case bsp_gr: |
| 1183 | r = 8; |
| 1184 | break; |
| 1185 | case bspstore_gr: |
| 1186 | r = 9; |
| 1187 | break; |
| 1188 | case fpsr_gr: |
| 1189 | r = 10; |
| 1190 | break; |
| 1191 | case priunat_gr: |
| 1192 | r = 11; |
| 1193 | break; |
| 1194 | default: |
| 1195 | as_bad ("Invalid record type for P3 format."); |
| 1196 | } |
| 1197 | bytes[0] = (UNW_P3 | (r >> 1)); |
| 1198 | bytes[1] = (((r & 1) << 7) | reg); |
| 1199 | (*f) (2, bytes, NULL); |
| 1200 | } |
| 1201 | |
| 1202 | static void |
| 1203 | output_P4_format (f, imask, imask_size) |
| 1204 | vbyte_func f; |
| 1205 | unsigned char *imask; |
| 1206 | unsigned long imask_size; |
| 1207 | { |
| 1208 | imask[0] = UNW_P4; |
| 1209 | (*f) (imask_size, imask, NULL); |
| 1210 | } |
| 1211 | |
| 1212 | static void |
| 1213 | output_P5_format (f, grmask, frmask) |
| 1214 | vbyte_func f; |
| 1215 | int grmask; |
| 1216 | unsigned long frmask; |
| 1217 | { |
| 1218 | char bytes[4]; |
| 1219 | grmask = (grmask & 0x0f); |
| 1220 | |
| 1221 | bytes[0] = UNW_P5; |
| 1222 | bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); |
| 1223 | bytes[2] = ((frmask & 0x0000ff00) >> 8); |
| 1224 | bytes[3] = (frmask & 0x000000ff); |
| 1225 | (*f) (4, bytes, NULL); |
| 1226 | } |
| 1227 | |
| 1228 | static void |
| 1229 | output_P6_format (f, rtype, rmask) |
| 1230 | vbyte_func f; |
| 1231 | unw_record_type rtype; |
| 1232 | int rmask; |
| 1233 | { |
| 1234 | char byte; |
| 1235 | int r = 0; |
| 1236 | |
| 1237 | if (rtype == gr_mem) |
| 1238 | r = 1; |
| 1239 | else if (rtype != fr_mem) |
| 1240 | as_bad ("Invalid record type for format P6"); |
| 1241 | byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); |
| 1242 | (*f) (1, &byte, NULL); |
| 1243 | } |
| 1244 | |
| 1245 | static void |
| 1246 | output_P7_format (f, rtype, w1, w2) |
| 1247 | vbyte_func f; |
| 1248 | unw_record_type rtype; |
| 1249 | unsigned long w1; |
| 1250 | unsigned long w2; |
| 1251 | { |
| 1252 | char bytes[20]; |
| 1253 | int count = 1; |
| 1254 | int r = 0; |
| 1255 | count += output_leb128 (bytes + 1, w1, 0); |
| 1256 | switch (rtype) |
| 1257 | { |
| 1258 | case mem_stack_f: |
| 1259 | r = 0; |
| 1260 | count += output_leb128 (bytes + count, w2 >> 4, 0); |
| 1261 | break; |
| 1262 | case mem_stack_v: |
| 1263 | r = 1; |
| 1264 | break; |
| 1265 | case spill_base: |
| 1266 | r = 2; |
| 1267 | break; |
| 1268 | case psp_sprel: |
| 1269 | r = 3; |
| 1270 | break; |
| 1271 | case rp_when: |
| 1272 | r = 4; |
| 1273 | break; |
| 1274 | case rp_psprel: |
| 1275 | r = 5; |
| 1276 | break; |
| 1277 | case pfs_when: |
| 1278 | r = 6; |
| 1279 | break; |
| 1280 | case pfs_psprel: |
| 1281 | r = 7; |
| 1282 | break; |
| 1283 | case preds_when: |
| 1284 | r = 8; |
| 1285 | break; |
| 1286 | case preds_psprel: |
| 1287 | r = 9; |
| 1288 | break; |
| 1289 | case lc_when: |
| 1290 | r = 10; |
| 1291 | break; |
| 1292 | case lc_psprel: |
| 1293 | r = 11; |
| 1294 | break; |
| 1295 | case unat_when: |
| 1296 | r = 12; |
| 1297 | break; |
| 1298 | case unat_psprel: |
| 1299 | r = 13; |
| 1300 | break; |
| 1301 | case fpsr_when: |
| 1302 | r = 14; |
| 1303 | break; |
| 1304 | case fpsr_psprel: |
| 1305 | r = 15; |
| 1306 | break; |
| 1307 | default: |
| 1308 | break; |
| 1309 | } |
| 1310 | bytes[0] = (UNW_P7 | r); |
| 1311 | (*f) (count, bytes, NULL); |
| 1312 | } |
| 1313 | |
| 1314 | static void |
| 1315 | output_P8_format (f, rtype, t) |
| 1316 | vbyte_func f; |
| 1317 | unw_record_type rtype; |
| 1318 | unsigned long t; |
| 1319 | { |
| 1320 | char bytes[20]; |
| 1321 | int r = 0; |
| 1322 | int count = 2; |
| 1323 | bytes[0] = UNW_P8; |
| 1324 | switch (rtype) |
| 1325 | { |
| 1326 | case rp_sprel: |
| 1327 | r = 1; |
| 1328 | break; |
| 1329 | case pfs_sprel: |
| 1330 | r = 2; |
| 1331 | break; |
| 1332 | case preds_sprel: |
| 1333 | r = 3; |
| 1334 | break; |
| 1335 | case lc_sprel: |
| 1336 | r = 4; |
| 1337 | break; |
| 1338 | case unat_sprel: |
| 1339 | r = 5; |
| 1340 | break; |
| 1341 | case fpsr_sprel: |
| 1342 | r = 6; |
| 1343 | break; |
| 1344 | case bsp_when: |
| 1345 | r = 7; |
| 1346 | break; |
| 1347 | case bsp_psprel: |
| 1348 | r = 8; |
| 1349 | break; |
| 1350 | case bsp_sprel: |
| 1351 | r = 9; |
| 1352 | break; |
| 1353 | case bspstore_when: |
| 1354 | r = 10; |
| 1355 | break; |
| 1356 | case bspstore_psprel: |
| 1357 | r = 11; |
| 1358 | break; |
| 1359 | case bspstore_sprel: |
| 1360 | r = 12; |
| 1361 | break; |
| 1362 | case rnat_when: |
| 1363 | r = 13; |
| 1364 | break; |
| 1365 | case rnat_psprel: |
| 1366 | r = 14; |
| 1367 | break; |
| 1368 | case rnat_sprel: |
| 1369 | r = 15; |
| 1370 | break; |
| 1371 | case priunat_when_gr: |
| 1372 | r = 16; |
| 1373 | break; |
| 1374 | case priunat_psprel: |
| 1375 | r = 17; |
| 1376 | break; |
| 1377 | case priunat_sprel: |
| 1378 | r = 18; |
| 1379 | break; |
| 1380 | case priunat_when_mem: |
| 1381 | r = 19; |
| 1382 | break; |
| 1383 | default: |
| 1384 | break; |
| 1385 | } |
| 1386 | bytes[1] = r; |
| 1387 | count += output_leb128 (bytes + 2, t, 0); |
| 1388 | (*f) (count, bytes, NULL); |
| 1389 | } |
| 1390 | |
| 1391 | static void |
| 1392 | output_P9_format (f, grmask, gr) |
| 1393 | vbyte_func f; |
| 1394 | int grmask; |
| 1395 | int gr; |
| 1396 | { |
| 1397 | char bytes[3]; |
| 1398 | bytes[0] = UNW_P9; |
| 1399 | bytes[1] = (grmask & 0x0f); |
| 1400 | bytes[2] = (gr & 0x7f); |
| 1401 | (*f) (3, bytes, NULL); |
| 1402 | } |
| 1403 | |
| 1404 | static void |
| 1405 | output_P10_format (f, abi, context) |
| 1406 | vbyte_func f; |
| 1407 | int abi; |
| 1408 | int context; |
| 1409 | { |
| 1410 | char bytes[3]; |
| 1411 | bytes[0] = UNW_P10; |
| 1412 | bytes[1] = (abi & 0xff); |
| 1413 | bytes[2] = (context & 0xff); |
| 1414 | (*f) (3, bytes, NULL); |
| 1415 | } |
| 1416 | |
| 1417 | static void |
| 1418 | output_B1_format (f, rtype, label) |
| 1419 | vbyte_func f; |
| 1420 | unw_record_type rtype; |
| 1421 | unsigned long label; |
| 1422 | { |
| 1423 | char byte; |
| 1424 | int r = 0; |
| 1425 | if (label > 0x1f) |
| 1426 | { |
| 1427 | output_B4_format (f, rtype, label); |
| 1428 | return; |
| 1429 | } |
| 1430 | if (rtype == copy_state) |
| 1431 | r = 1; |
| 1432 | else if (rtype != label_state) |
| 1433 | as_bad ("Invalid record type for format B1"); |
| 1434 | |
| 1435 | byte = (UNW_B1 | (r << 5) | (label & 0x1f)); |
| 1436 | (*f) (1, &byte, NULL); |
| 1437 | } |
| 1438 | |
| 1439 | static void |
| 1440 | output_B2_format (f, ecount, t) |
| 1441 | vbyte_func f; |
| 1442 | unsigned long ecount; |
| 1443 | unsigned long t; |
| 1444 | { |
| 1445 | char bytes[20]; |
| 1446 | int count = 1; |
| 1447 | if (ecount > 0x1f) |
| 1448 | { |
| 1449 | output_B3_format (f, ecount, t); |
| 1450 | return; |
| 1451 | } |
| 1452 | bytes[0] = (UNW_B2 | (ecount & 0x1f)); |
| 1453 | count += output_leb128 (bytes + 1, t, 0); |
| 1454 | (*f) (count, bytes, NULL); |
| 1455 | } |
| 1456 | |
| 1457 | static void |
| 1458 | output_B3_format (f, ecount, t) |
| 1459 | vbyte_func f; |
| 1460 | unsigned long ecount; |
| 1461 | unsigned long t; |
| 1462 | { |
| 1463 | char bytes[20]; |
| 1464 | int count = 1; |
| 1465 | if (ecount <= 0x1f) |
| 1466 | { |
| 1467 | output_B2_format (f, ecount, t); |
| 1468 | return; |
| 1469 | } |
| 1470 | bytes[0] = UNW_B3; |
| 1471 | count += output_leb128 (bytes + 1, t, 0); |
| 1472 | count += output_leb128 (bytes + count, ecount, 0); |
| 1473 | (*f) (count, bytes, NULL); |
| 1474 | } |
| 1475 | |
| 1476 | static void |
| 1477 | output_B4_format (f, rtype, label) |
| 1478 | vbyte_func f; |
| 1479 | unw_record_type rtype; |
| 1480 | unsigned long label; |
| 1481 | { |
| 1482 | char bytes[20]; |
| 1483 | int r = 0; |
| 1484 | int count = 1; |
| 1485 | if (label <= 0x1f) |
| 1486 | { |
| 1487 | output_B1_format (f, rtype, label); |
| 1488 | return; |
| 1489 | } |
| 1490 | |
| 1491 | if (rtype == copy_state) |
| 1492 | r = 1; |
| 1493 | else if (rtype != label_state) |
| 1494 | as_bad ("Invalid record type for format B1"); |
| 1495 | |
| 1496 | bytes[0] = (UNW_B4 | (r << 3)); |
| 1497 | count += output_leb128 (bytes + 1, label, 0); |
| 1498 | (*f) (count, bytes, NULL); |
| 1499 | } |
| 1500 | |
| 1501 | static char |
| 1502 | format_ab_reg (ab, reg) |
| 1503 | int ab; |
| 1504 | int reg; |
| 1505 | { |
| 1506 | int ret; |
| 1507 | ab = (ab & 3); |
| 1508 | reg = (reg & 0x1f); |
| 1509 | ret = (ab << 5) | reg; |
| 1510 | return ret; |
| 1511 | } |
| 1512 | |
| 1513 | static void |
| 1514 | output_X1_format (f, rtype, ab, reg, t, w1) |
| 1515 | vbyte_func f; |
| 1516 | unw_record_type rtype; |
| 1517 | int ab, reg; |
| 1518 | unsigned long t; |
| 1519 | unsigned long w1; |
| 1520 | { |
| 1521 | char bytes[20]; |
| 1522 | int r = 0; |
| 1523 | int count = 2; |
| 1524 | bytes[0] = UNW_X1; |
| 1525 | |
| 1526 | if (rtype == spill_sprel) |
| 1527 | r = 1; |
| 1528 | else if (rtype != spill_psprel) |
| 1529 | as_bad ("Invalid record type for format X1"); |
| 1530 | bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); |
| 1531 | count += output_leb128 (bytes + 2, t, 0); |
| 1532 | count += output_leb128 (bytes + count, w1, 0); |
| 1533 | (*f) (count, bytes, NULL); |
| 1534 | } |
| 1535 | |
| 1536 | static void |
| 1537 | output_X2_format (f, ab, reg, x, y, treg, t) |
| 1538 | vbyte_func f; |
| 1539 | int ab, reg; |
| 1540 | int x, y, treg; |
| 1541 | unsigned long t; |
| 1542 | { |
| 1543 | char bytes[20]; |
| 1544 | int count = 3; |
| 1545 | bytes[0] = UNW_X2; |
| 1546 | bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
| 1547 | bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); |
| 1548 | count += output_leb128 (bytes + 3, t, 0); |
| 1549 | (*f) (count, bytes, NULL); |
| 1550 | } |
| 1551 | |
| 1552 | static void |
| 1553 | output_X3_format (f, rtype, qp, ab, reg, t, w1) |
| 1554 | vbyte_func f; |
| 1555 | unw_record_type rtype; |
| 1556 | int qp; |
| 1557 | int ab, reg; |
| 1558 | unsigned long t; |
| 1559 | unsigned long w1; |
| 1560 | { |
| 1561 | char bytes[20]; |
| 1562 | int r = 0; |
| 1563 | int count = 3; |
| 1564 | bytes[0] = UNW_X3; |
| 1565 | |
| 1566 | if (rtype == spill_sprel_p) |
| 1567 | r = 1; |
| 1568 | else if (rtype != spill_psprel_p) |
| 1569 | as_bad ("Invalid record type for format X3"); |
| 1570 | bytes[1] = ((r << 7) | (qp & 0x3f)); |
| 1571 | bytes[2] = format_ab_reg (ab, reg); |
| 1572 | count += output_leb128 (bytes + 3, t, 0); |
| 1573 | count += output_leb128 (bytes + count, w1, 0); |
| 1574 | (*f) (count, bytes, NULL); |
| 1575 | } |
| 1576 | |
| 1577 | static void |
| 1578 | output_X4_format (f, qp, ab, reg, x, y, treg, t) |
| 1579 | vbyte_func f; |
| 1580 | int qp; |
| 1581 | int ab, reg; |
| 1582 | int x, y, treg; |
| 1583 | unsigned long t; |
| 1584 | { |
| 1585 | char bytes[20]; |
| 1586 | int count = 4; |
| 1587 | bytes[0] = UNW_X4; |
| 1588 | bytes[1] = (qp & 0x3f); |
| 1589 | bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
| 1590 | bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); |
| 1591 | count += output_leb128 (bytes + 4, t, 0); |
| 1592 | (*f) (count, bytes, NULL); |
| 1593 | } |
| 1594 | |
| 1595 | /* This function allocates a record list structure, and initializes fields. */ |
| 1596 | |
| 1597 | static unw_rec_list * |
| 1598 | alloc_record (unw_record_type t) |
| 1599 | { |
| 1600 | unw_rec_list *ptr; |
| 1601 | ptr = xmalloc (sizeof (*ptr)); |
| 1602 | ptr->next = NULL; |
| 1603 | ptr->slot_number = SLOT_NUM_NOT_SET; |
| 1604 | ptr->r.type = t; |
| 1605 | return ptr; |
| 1606 | } |
| 1607 | |
| 1608 | /* This function frees an entire list of record structures. */ |
| 1609 | |
| 1610 | void |
| 1611 | free_list_records (unw_rec_list *first) |
| 1612 | { |
| 1613 | unw_rec_list *ptr; |
| 1614 | for (ptr = first; ptr != NULL;) |
| 1615 | { |
| 1616 | unw_rec_list *tmp = ptr; |
| 1617 | |
| 1618 | if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) |
| 1619 | && tmp->r.record.r.mask.i) |
| 1620 | free (tmp->r.record.r.mask.i); |
| 1621 | |
| 1622 | ptr = ptr->next; |
| 1623 | free (tmp); |
| 1624 | } |
| 1625 | } |
| 1626 | |
| 1627 | static unw_rec_list * |
| 1628 | output_prologue () |
| 1629 | { |
| 1630 | unw_rec_list *ptr = alloc_record (prologue); |
| 1631 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
| 1632 | return ptr; |
| 1633 | } |
| 1634 | |
| 1635 | static unw_rec_list * |
| 1636 | output_prologue_gr (saved_mask, reg) |
| 1637 | unsigned int saved_mask; |
| 1638 | unsigned int reg; |
| 1639 | { |
| 1640 | unw_rec_list *ptr = alloc_record (prologue_gr); |
| 1641 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
| 1642 | ptr->r.record.r.grmask = saved_mask; |
| 1643 | ptr->r.record.r.grsave = reg; |
| 1644 | return ptr; |
| 1645 | } |
| 1646 | |
| 1647 | static unw_rec_list * |
| 1648 | output_body () |
| 1649 | { |
| 1650 | unw_rec_list *ptr = alloc_record (body); |
| 1651 | return ptr; |
| 1652 | } |
| 1653 | |
| 1654 | static unw_rec_list * |
| 1655 | output_mem_stack_f (size) |
| 1656 | unsigned int size; |
| 1657 | { |
| 1658 | unw_rec_list *ptr = alloc_record (mem_stack_f); |
| 1659 | ptr->r.record.p.size = size; |
| 1660 | return ptr; |
| 1661 | } |
| 1662 | |
| 1663 | static unw_rec_list * |
| 1664 | output_mem_stack_v () |
| 1665 | { |
| 1666 | unw_rec_list *ptr = alloc_record (mem_stack_v); |
| 1667 | return ptr; |
| 1668 | } |
| 1669 | |
| 1670 | static unw_rec_list * |
| 1671 | output_psp_gr (gr) |
| 1672 | unsigned int gr; |
| 1673 | { |
| 1674 | unw_rec_list *ptr = alloc_record (psp_gr); |
| 1675 | ptr->r.record.p.gr = gr; |
| 1676 | return ptr; |
| 1677 | } |
| 1678 | |
| 1679 | static unw_rec_list * |
| 1680 | output_psp_sprel (offset) |
| 1681 | unsigned int offset; |
| 1682 | { |
| 1683 | unw_rec_list *ptr = alloc_record (psp_sprel); |
| 1684 | ptr->r.record.p.spoff = offset / 4; |
| 1685 | return ptr; |
| 1686 | } |
| 1687 | |
| 1688 | static unw_rec_list * |
| 1689 | output_rp_when () |
| 1690 | { |
| 1691 | unw_rec_list *ptr = alloc_record (rp_when); |
| 1692 | return ptr; |
| 1693 | } |
| 1694 | |
| 1695 | static unw_rec_list * |
| 1696 | output_rp_gr (gr) |
| 1697 | unsigned int gr; |
| 1698 | { |
| 1699 | unw_rec_list *ptr = alloc_record (rp_gr); |
| 1700 | ptr->r.record.p.gr = gr; |
| 1701 | return ptr; |
| 1702 | } |
| 1703 | |
| 1704 | static unw_rec_list * |
| 1705 | output_rp_br (br) |
| 1706 | unsigned int br; |
| 1707 | { |
| 1708 | unw_rec_list *ptr = alloc_record (rp_br); |
| 1709 | ptr->r.record.p.br = br; |
| 1710 | return ptr; |
| 1711 | } |
| 1712 | |
| 1713 | static unw_rec_list * |
| 1714 | output_rp_psprel (offset) |
| 1715 | unsigned int offset; |
| 1716 | { |
| 1717 | unw_rec_list *ptr = alloc_record (rp_psprel); |
| 1718 | ptr->r.record.p.pspoff = offset / 4; |
| 1719 | return ptr; |
| 1720 | } |
| 1721 | |
| 1722 | static unw_rec_list * |
| 1723 | output_rp_sprel (offset) |
| 1724 | unsigned int offset; |
| 1725 | { |
| 1726 | unw_rec_list *ptr = alloc_record (rp_sprel); |
| 1727 | ptr->r.record.p.spoff = offset / 4; |
| 1728 | return ptr; |
| 1729 | } |
| 1730 | |
| 1731 | static unw_rec_list * |
| 1732 | output_pfs_when () |
| 1733 | { |
| 1734 | unw_rec_list *ptr = alloc_record (pfs_when); |
| 1735 | return ptr; |
| 1736 | } |
| 1737 | |
| 1738 | static unw_rec_list * |
| 1739 | output_pfs_gr (gr) |
| 1740 | unsigned int gr; |
| 1741 | { |
| 1742 | unw_rec_list *ptr = alloc_record (pfs_gr); |
| 1743 | ptr->r.record.p.gr = gr; |
| 1744 | return ptr; |
| 1745 | } |
| 1746 | |
| 1747 | static unw_rec_list * |
| 1748 | output_pfs_psprel (offset) |
| 1749 | unsigned int offset; |
| 1750 | { |
| 1751 | unw_rec_list *ptr = alloc_record (pfs_psprel); |
| 1752 | ptr->r.record.p.pspoff = offset / 4; |
| 1753 | return ptr; |
| 1754 | } |
| 1755 | |
| 1756 | static unw_rec_list * |
| 1757 | output_pfs_sprel (offset) |
| 1758 | unsigned int offset; |
| 1759 | { |
| 1760 | unw_rec_list *ptr = alloc_record (pfs_sprel); |
| 1761 | ptr->r.record.p.spoff = offset / 4; |
| 1762 | return ptr; |
| 1763 | } |
| 1764 | |
| 1765 | static unw_rec_list * |
| 1766 | output_preds_when () |
| 1767 | { |
| 1768 | unw_rec_list *ptr = alloc_record (preds_when); |
| 1769 | return ptr; |
| 1770 | } |
| 1771 | |
| 1772 | static unw_rec_list * |
| 1773 | output_preds_gr (gr) |
| 1774 | unsigned int gr; |
| 1775 | { |
| 1776 | unw_rec_list *ptr = alloc_record (preds_gr); |
| 1777 | ptr->r.record.p.gr = gr; |
| 1778 | return ptr; |
| 1779 | } |
| 1780 | |
| 1781 | static unw_rec_list * |
| 1782 | output_preds_psprel (offset) |
| 1783 | unsigned int offset; |
| 1784 | { |
| 1785 | unw_rec_list *ptr = alloc_record (preds_psprel); |
| 1786 | ptr->r.record.p.pspoff = offset / 4; |
| 1787 | return ptr; |
| 1788 | } |
| 1789 | |
| 1790 | static unw_rec_list * |
| 1791 | output_preds_sprel (offset) |
| 1792 | unsigned int offset; |
| 1793 | { |
| 1794 | unw_rec_list *ptr = alloc_record (preds_sprel); |
| 1795 | ptr->r.record.p.spoff = offset / 4; |
| 1796 | return ptr; |
| 1797 | } |
| 1798 | |
| 1799 | static unw_rec_list * |
| 1800 | output_fr_mem (mask) |
| 1801 | unsigned int mask; |
| 1802 | { |
| 1803 | unw_rec_list *ptr = alloc_record (fr_mem); |
| 1804 | ptr->r.record.p.rmask = mask; |
| 1805 | return ptr; |
| 1806 | } |
| 1807 | |
| 1808 | static unw_rec_list * |
| 1809 | output_frgr_mem (gr_mask, fr_mask) |
| 1810 | unsigned int gr_mask; |
| 1811 | unsigned int fr_mask; |
| 1812 | { |
| 1813 | unw_rec_list *ptr = alloc_record (frgr_mem); |
| 1814 | ptr->r.record.p.grmask = gr_mask; |
| 1815 | ptr->r.record.p.frmask = fr_mask; |
| 1816 | return ptr; |
| 1817 | } |
| 1818 | |
| 1819 | static unw_rec_list * |
| 1820 | output_gr_gr (mask, reg) |
| 1821 | unsigned int mask; |
| 1822 | unsigned int reg; |
| 1823 | { |
| 1824 | unw_rec_list *ptr = alloc_record (gr_gr); |
| 1825 | ptr->r.record.p.grmask = mask; |
| 1826 | ptr->r.record.p.gr = reg; |
| 1827 | return ptr; |
| 1828 | } |
| 1829 | |
| 1830 | static unw_rec_list * |
| 1831 | output_gr_mem (mask) |
| 1832 | unsigned int mask; |
| 1833 | { |
| 1834 | unw_rec_list *ptr = alloc_record (gr_mem); |
| 1835 | ptr->r.record.p.rmask = mask; |
| 1836 | return ptr; |
| 1837 | } |
| 1838 | |
| 1839 | static unw_rec_list * |
| 1840 | output_br_mem (unsigned int mask) |
| 1841 | { |
| 1842 | unw_rec_list *ptr = alloc_record (br_mem); |
| 1843 | ptr->r.record.p.brmask = mask; |
| 1844 | return ptr; |
| 1845 | } |
| 1846 | |
| 1847 | static unw_rec_list * |
| 1848 | output_br_gr (save_mask, reg) |
| 1849 | unsigned int save_mask; |
| 1850 | unsigned int reg; |
| 1851 | { |
| 1852 | unw_rec_list *ptr = alloc_record (br_gr); |
| 1853 | ptr->r.record.p.brmask = save_mask; |
| 1854 | ptr->r.record.p.gr = reg; |
| 1855 | return ptr; |
| 1856 | } |
| 1857 | |
| 1858 | static unw_rec_list * |
| 1859 | output_spill_base (offset) |
| 1860 | unsigned int offset; |
| 1861 | { |
| 1862 | unw_rec_list *ptr = alloc_record (spill_base); |
| 1863 | ptr->r.record.p.pspoff = offset / 4; |
| 1864 | return ptr; |
| 1865 | } |
| 1866 | |
| 1867 | static unw_rec_list * |
| 1868 | output_unat_when () |
| 1869 | { |
| 1870 | unw_rec_list *ptr = alloc_record (unat_when); |
| 1871 | return ptr; |
| 1872 | } |
| 1873 | |
| 1874 | static unw_rec_list * |
| 1875 | output_unat_gr (gr) |
| 1876 | unsigned int gr; |
| 1877 | { |
| 1878 | unw_rec_list *ptr = alloc_record (unat_gr); |
| 1879 | ptr->r.record.p.gr = gr; |
| 1880 | return ptr; |
| 1881 | } |
| 1882 | |
| 1883 | static unw_rec_list * |
| 1884 | output_unat_psprel (offset) |
| 1885 | unsigned int offset; |
| 1886 | { |
| 1887 | unw_rec_list *ptr = alloc_record (unat_psprel); |
| 1888 | ptr->r.record.p.pspoff = offset / 4; |
| 1889 | return ptr; |
| 1890 | } |
| 1891 | |
| 1892 | static unw_rec_list * |
| 1893 | output_unat_sprel (offset) |
| 1894 | unsigned int offset; |
| 1895 | { |
| 1896 | unw_rec_list *ptr = alloc_record (unat_sprel); |
| 1897 | ptr->r.record.p.spoff = offset / 4; |
| 1898 | return ptr; |
| 1899 | } |
| 1900 | |
| 1901 | static unw_rec_list * |
| 1902 | output_lc_when () |
| 1903 | { |
| 1904 | unw_rec_list *ptr = alloc_record (lc_when); |
| 1905 | return ptr; |
| 1906 | } |
| 1907 | |
| 1908 | static unw_rec_list * |
| 1909 | output_lc_gr (gr) |
| 1910 | unsigned int gr; |
| 1911 | { |
| 1912 | unw_rec_list *ptr = alloc_record (lc_gr); |
| 1913 | ptr->r.record.p.gr = gr; |
| 1914 | return ptr; |
| 1915 | } |
| 1916 | |
| 1917 | static unw_rec_list * |
| 1918 | output_lc_psprel (offset) |
| 1919 | unsigned int offset; |
| 1920 | { |
| 1921 | unw_rec_list *ptr = alloc_record (lc_psprel); |
| 1922 | ptr->r.record.p.pspoff = offset / 4; |
| 1923 | return ptr; |
| 1924 | } |
| 1925 | |
| 1926 | static unw_rec_list * |
| 1927 | output_lc_sprel (offset) |
| 1928 | unsigned int offset; |
| 1929 | { |
| 1930 | unw_rec_list *ptr = alloc_record (lc_sprel); |
| 1931 | ptr->r.record.p.spoff = offset / 4; |
| 1932 | return ptr; |
| 1933 | } |
| 1934 | |
| 1935 | static unw_rec_list * |
| 1936 | output_fpsr_when () |
| 1937 | { |
| 1938 | unw_rec_list *ptr = alloc_record (fpsr_when); |
| 1939 | return ptr; |
| 1940 | } |
| 1941 | |
| 1942 | static unw_rec_list * |
| 1943 | output_fpsr_gr (gr) |
| 1944 | unsigned int gr; |
| 1945 | { |
| 1946 | unw_rec_list *ptr = alloc_record (fpsr_gr); |
| 1947 | ptr->r.record.p.gr = gr; |
| 1948 | return ptr; |
| 1949 | } |
| 1950 | |
| 1951 | static unw_rec_list * |
| 1952 | output_fpsr_psprel (offset) |
| 1953 | unsigned int offset; |
| 1954 | { |
| 1955 | unw_rec_list *ptr = alloc_record (fpsr_psprel); |
| 1956 | ptr->r.record.p.pspoff = offset / 4; |
| 1957 | return ptr; |
| 1958 | } |
| 1959 | |
| 1960 | static unw_rec_list * |
| 1961 | output_fpsr_sprel (offset) |
| 1962 | unsigned int offset; |
| 1963 | { |
| 1964 | unw_rec_list *ptr = alloc_record (fpsr_sprel); |
| 1965 | ptr->r.record.p.spoff = offset / 4; |
| 1966 | return ptr; |
| 1967 | } |
| 1968 | |
| 1969 | static unw_rec_list * |
| 1970 | output_priunat_when_gr () |
| 1971 | { |
| 1972 | unw_rec_list *ptr = alloc_record (priunat_when_gr); |
| 1973 | return ptr; |
| 1974 | } |
| 1975 | |
| 1976 | static unw_rec_list * |
| 1977 | output_priunat_when_mem () |
| 1978 | { |
| 1979 | unw_rec_list *ptr = alloc_record (priunat_when_mem); |
| 1980 | return ptr; |
| 1981 | } |
| 1982 | |
| 1983 | static unw_rec_list * |
| 1984 | output_priunat_gr (gr) |
| 1985 | unsigned int gr; |
| 1986 | { |
| 1987 | unw_rec_list *ptr = alloc_record (priunat_gr); |
| 1988 | ptr->r.record.p.gr = gr; |
| 1989 | return ptr; |
| 1990 | } |
| 1991 | |
| 1992 | static unw_rec_list * |
| 1993 | output_priunat_psprel (offset) |
| 1994 | unsigned int offset; |
| 1995 | { |
| 1996 | unw_rec_list *ptr = alloc_record (priunat_psprel); |
| 1997 | ptr->r.record.p.pspoff = offset / 4; |
| 1998 | return ptr; |
| 1999 | } |
| 2000 | |
| 2001 | static unw_rec_list * |
| 2002 | output_priunat_sprel (offset) |
| 2003 | unsigned int offset; |
| 2004 | { |
| 2005 | unw_rec_list *ptr = alloc_record (priunat_sprel); |
| 2006 | ptr->r.record.p.spoff = offset / 4; |
| 2007 | return ptr; |
| 2008 | } |
| 2009 | |
| 2010 | static unw_rec_list * |
| 2011 | output_bsp_when () |
| 2012 | { |
| 2013 | unw_rec_list *ptr = alloc_record (bsp_when); |
| 2014 | return ptr; |
| 2015 | } |
| 2016 | |
| 2017 | static unw_rec_list * |
| 2018 | output_bsp_gr (gr) |
| 2019 | unsigned int gr; |
| 2020 | { |
| 2021 | unw_rec_list *ptr = alloc_record (bsp_gr); |
| 2022 | ptr->r.record.p.gr = gr; |
| 2023 | return ptr; |
| 2024 | } |
| 2025 | |
| 2026 | static unw_rec_list * |
| 2027 | output_bsp_psprel (offset) |
| 2028 | unsigned int offset; |
| 2029 | { |
| 2030 | unw_rec_list *ptr = alloc_record (bsp_psprel); |
| 2031 | ptr->r.record.p.pspoff = offset / 4; |
| 2032 | return ptr; |
| 2033 | } |
| 2034 | |
| 2035 | static unw_rec_list * |
| 2036 | output_bsp_sprel (offset) |
| 2037 | unsigned int offset; |
| 2038 | { |
| 2039 | unw_rec_list *ptr = alloc_record (bsp_sprel); |
| 2040 | ptr->r.record.p.spoff = offset / 4; |
| 2041 | return ptr; |
| 2042 | } |
| 2043 | |
| 2044 | static unw_rec_list * |
| 2045 | output_bspstore_when () |
| 2046 | { |
| 2047 | unw_rec_list *ptr = alloc_record (bspstore_when); |
| 2048 | return ptr; |
| 2049 | } |
| 2050 | |
| 2051 | static unw_rec_list * |
| 2052 | output_bspstore_gr (gr) |
| 2053 | unsigned int gr; |
| 2054 | { |
| 2055 | unw_rec_list *ptr = alloc_record (bspstore_gr); |
| 2056 | ptr->r.record.p.gr = gr; |
| 2057 | return ptr; |
| 2058 | } |
| 2059 | |
| 2060 | static unw_rec_list * |
| 2061 | output_bspstore_psprel (offset) |
| 2062 | unsigned int offset; |
| 2063 | { |
| 2064 | unw_rec_list *ptr = alloc_record (bspstore_psprel); |
| 2065 | ptr->r.record.p.pspoff = offset / 4; |
| 2066 | return ptr; |
| 2067 | } |
| 2068 | |
| 2069 | static unw_rec_list * |
| 2070 | output_bspstore_sprel (offset) |
| 2071 | unsigned int offset; |
| 2072 | { |
| 2073 | unw_rec_list *ptr = alloc_record (bspstore_sprel); |
| 2074 | ptr->r.record.p.spoff = offset / 4; |
| 2075 | return ptr; |
| 2076 | } |
| 2077 | |
| 2078 | static unw_rec_list * |
| 2079 | output_rnat_when () |
| 2080 | { |
| 2081 | unw_rec_list *ptr = alloc_record (rnat_when); |
| 2082 | return ptr; |
| 2083 | } |
| 2084 | |
| 2085 | static unw_rec_list * |
| 2086 | output_rnat_gr (gr) |
| 2087 | unsigned int gr; |
| 2088 | { |
| 2089 | unw_rec_list *ptr = alloc_record (rnat_gr); |
| 2090 | ptr->r.record.p.gr = gr; |
| 2091 | return ptr; |
| 2092 | } |
| 2093 | |
| 2094 | static unw_rec_list * |
| 2095 | output_rnat_psprel (offset) |
| 2096 | unsigned int offset; |
| 2097 | { |
| 2098 | unw_rec_list *ptr = alloc_record (rnat_psprel); |
| 2099 | ptr->r.record.p.pspoff = offset / 4; |
| 2100 | return ptr; |
| 2101 | } |
| 2102 | |
| 2103 | static unw_rec_list * |
| 2104 | output_rnat_sprel (offset) |
| 2105 | unsigned int offset; |
| 2106 | { |
| 2107 | unw_rec_list *ptr = alloc_record (rnat_sprel); |
| 2108 | ptr->r.record.p.spoff = offset / 4; |
| 2109 | return ptr; |
| 2110 | } |
| 2111 | |
| 2112 | static unw_rec_list * |
| 2113 | output_unwabi (abi, context) |
| 2114 | unsigned long abi; |
| 2115 | unsigned long context; |
| 2116 | { |
| 2117 | unw_rec_list *ptr = alloc_record (unwabi); |
| 2118 | ptr->r.record.p.abi = abi; |
| 2119 | ptr->r.record.p.context = context; |
| 2120 | return ptr; |
| 2121 | } |
| 2122 | |
| 2123 | static unw_rec_list * |
| 2124 | output_epilogue (unsigned long ecount) |
| 2125 | { |
| 2126 | unw_rec_list *ptr = alloc_record (epilogue); |
| 2127 | ptr->r.record.b.ecount = ecount; |
| 2128 | return ptr; |
| 2129 | } |
| 2130 | |
| 2131 | static unw_rec_list * |
| 2132 | output_label_state (unsigned long label) |
| 2133 | { |
| 2134 | unw_rec_list *ptr = alloc_record (label_state); |
| 2135 | ptr->r.record.b.label = label; |
| 2136 | return ptr; |
| 2137 | } |
| 2138 | |
| 2139 | static unw_rec_list * |
| 2140 | output_copy_state (unsigned long label) |
| 2141 | { |
| 2142 | unw_rec_list *ptr = alloc_record (copy_state); |
| 2143 | ptr->r.record.b.label = label; |
| 2144 | return ptr; |
| 2145 | } |
| 2146 | |
| 2147 | static unw_rec_list * |
| 2148 | output_spill_psprel (ab, reg, offset) |
| 2149 | unsigned int ab; |
| 2150 | unsigned int reg; |
| 2151 | unsigned int offset; |
| 2152 | { |
| 2153 | unw_rec_list *ptr = alloc_record (spill_psprel); |
| 2154 | ptr->r.record.x.ab = ab; |
| 2155 | ptr->r.record.x.reg = reg; |
| 2156 | ptr->r.record.x.pspoff = offset / 4; |
| 2157 | return ptr; |
| 2158 | } |
| 2159 | |
| 2160 | static unw_rec_list * |
| 2161 | output_spill_sprel (ab, reg, offset) |
| 2162 | unsigned int ab; |
| 2163 | unsigned int reg; |
| 2164 | unsigned int offset; |
| 2165 | { |
| 2166 | unw_rec_list *ptr = alloc_record (spill_sprel); |
| 2167 | ptr->r.record.x.ab = ab; |
| 2168 | ptr->r.record.x.reg = reg; |
| 2169 | ptr->r.record.x.spoff = offset / 4; |
| 2170 | return ptr; |
| 2171 | } |
| 2172 | |
| 2173 | static unw_rec_list * |
| 2174 | output_spill_psprel_p (ab, reg, offset, predicate) |
| 2175 | unsigned int ab; |
| 2176 | unsigned int reg; |
| 2177 | unsigned int offset; |
| 2178 | unsigned int predicate; |
| 2179 | { |
| 2180 | unw_rec_list *ptr = alloc_record (spill_psprel_p); |
| 2181 | ptr->r.record.x.ab = ab; |
| 2182 | ptr->r.record.x.reg = reg; |
| 2183 | ptr->r.record.x.pspoff = offset / 4; |
| 2184 | ptr->r.record.x.qp = predicate; |
| 2185 | return ptr; |
| 2186 | } |
| 2187 | |
| 2188 | static unw_rec_list * |
| 2189 | output_spill_sprel_p (ab, reg, offset, predicate) |
| 2190 | unsigned int ab; |
| 2191 | unsigned int reg; |
| 2192 | unsigned int offset; |
| 2193 | unsigned int predicate; |
| 2194 | { |
| 2195 | unw_rec_list *ptr = alloc_record (spill_sprel_p); |
| 2196 | ptr->r.record.x.ab = ab; |
| 2197 | ptr->r.record.x.reg = reg; |
| 2198 | ptr->r.record.x.spoff = offset / 4; |
| 2199 | ptr->r.record.x.qp = predicate; |
| 2200 | return ptr; |
| 2201 | } |
| 2202 | |
| 2203 | static unw_rec_list * |
| 2204 | output_spill_reg (ab, reg, targ_reg, xy) |
| 2205 | unsigned int ab; |
| 2206 | unsigned int reg; |
| 2207 | unsigned int targ_reg; |
| 2208 | unsigned int xy; |
| 2209 | { |
| 2210 | unw_rec_list *ptr = alloc_record (spill_reg); |
| 2211 | ptr->r.record.x.ab = ab; |
| 2212 | ptr->r.record.x.reg = reg; |
| 2213 | ptr->r.record.x.treg = targ_reg; |
| 2214 | ptr->r.record.x.xy = xy; |
| 2215 | return ptr; |
| 2216 | } |
| 2217 | |
| 2218 | static unw_rec_list * |
| 2219 | output_spill_reg_p (ab, reg, targ_reg, xy, predicate) |
| 2220 | unsigned int ab; |
| 2221 | unsigned int reg; |
| 2222 | unsigned int targ_reg; |
| 2223 | unsigned int xy; |
| 2224 | unsigned int predicate; |
| 2225 | { |
| 2226 | unw_rec_list *ptr = alloc_record (spill_reg_p); |
| 2227 | ptr->r.record.x.ab = ab; |
| 2228 | ptr->r.record.x.reg = reg; |
| 2229 | ptr->r.record.x.treg = targ_reg; |
| 2230 | ptr->r.record.x.xy = xy; |
| 2231 | ptr->r.record.x.qp = predicate; |
| 2232 | return ptr; |
| 2233 | } |
| 2234 | |
| 2235 | /* Given a unw_rec_list process the correct format with the |
| 2236 | specified function. */ |
| 2237 | |
| 2238 | static void |
| 2239 | process_one_record (ptr, f) |
| 2240 | unw_rec_list *ptr; |
| 2241 | vbyte_func f; |
| 2242 | { |
| 2243 | unsigned long fr_mask, gr_mask; |
| 2244 | |
| 2245 | switch (ptr->r.type) |
| 2246 | { |
| 2247 | case gr_mem: |
| 2248 | case fr_mem: |
| 2249 | case br_mem: |
| 2250 | case frgr_mem: |
| 2251 | /* These are taken care of by prologue/prologue_gr. */ |
| 2252 | break; |
| 2253 | |
| 2254 | case prologue_gr: |
| 2255 | case prologue: |
| 2256 | if (ptr->r.type == prologue_gr) |
| 2257 | output_R2_format (f, ptr->r.record.r.grmask, |
| 2258 | ptr->r.record.r.grsave, ptr->r.record.r.rlen); |
| 2259 | else |
| 2260 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); |
| 2261 | |
| 2262 | /* Output descriptor(s) for union of register spills (if any). */ |
| 2263 | gr_mask = ptr->r.record.r.mask.gr_mem; |
| 2264 | fr_mask = ptr->r.record.r.mask.fr_mem; |
| 2265 | if (fr_mask) |
| 2266 | { |
| 2267 | if ((fr_mask & ~0xfUL) == 0) |
| 2268 | output_P6_format (f, fr_mem, fr_mask); |
| 2269 | else |
| 2270 | { |
| 2271 | output_P5_format (f, gr_mask, fr_mask); |
| 2272 | gr_mask = 0; |
| 2273 | } |
| 2274 | } |
| 2275 | if (gr_mask) |
| 2276 | output_P6_format (f, gr_mem, gr_mask); |
| 2277 | if (ptr->r.record.r.mask.br_mem) |
| 2278 | output_P1_format (f, ptr->r.record.r.mask.br_mem); |
| 2279 | |
| 2280 | /* output imask descriptor if necessary: */ |
| 2281 | if (ptr->r.record.r.mask.i) |
| 2282 | output_P4_format (f, ptr->r.record.r.mask.i, |
| 2283 | ptr->r.record.r.imask_size); |
| 2284 | break; |
| 2285 | |
| 2286 | case body: |
| 2287 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); |
| 2288 | break; |
| 2289 | case mem_stack_f: |
| 2290 | case mem_stack_v: |
| 2291 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, |
| 2292 | ptr->r.record.p.size); |
| 2293 | break; |
| 2294 | case psp_gr: |
| 2295 | case rp_gr: |
| 2296 | case pfs_gr: |
| 2297 | case preds_gr: |
| 2298 | case unat_gr: |
| 2299 | case lc_gr: |
| 2300 | case fpsr_gr: |
| 2301 | case priunat_gr: |
| 2302 | case bsp_gr: |
| 2303 | case bspstore_gr: |
| 2304 | case rnat_gr: |
| 2305 | output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); |
| 2306 | break; |
| 2307 | case rp_br: |
| 2308 | output_P3_format (f, rp_br, ptr->r.record.p.br); |
| 2309 | break; |
| 2310 | case psp_sprel: |
| 2311 | output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); |
| 2312 | break; |
| 2313 | case rp_when: |
| 2314 | case pfs_when: |
| 2315 | case preds_when: |
| 2316 | case unat_when: |
| 2317 | case lc_when: |
| 2318 | case fpsr_when: |
| 2319 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); |
| 2320 | break; |
| 2321 | case rp_psprel: |
| 2322 | case pfs_psprel: |
| 2323 | case preds_psprel: |
| 2324 | case unat_psprel: |
| 2325 | case lc_psprel: |
| 2326 | case fpsr_psprel: |
| 2327 | case spill_base: |
| 2328 | output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); |
| 2329 | break; |
| 2330 | case rp_sprel: |
| 2331 | case pfs_sprel: |
| 2332 | case preds_sprel: |
| 2333 | case unat_sprel: |
| 2334 | case lc_sprel: |
| 2335 | case fpsr_sprel: |
| 2336 | case priunat_sprel: |
| 2337 | case bsp_sprel: |
| 2338 | case bspstore_sprel: |
| 2339 | case rnat_sprel: |
| 2340 | output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); |
| 2341 | break; |
| 2342 | case gr_gr: |
| 2343 | output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); |
| 2344 | break; |
| 2345 | case br_gr: |
| 2346 | output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); |
| 2347 | break; |
| 2348 | case spill_mask: |
| 2349 | as_bad ("spill_mask record unimplemented."); |
| 2350 | break; |
| 2351 | case priunat_when_gr: |
| 2352 | case priunat_when_mem: |
| 2353 | case bsp_when: |
| 2354 | case bspstore_when: |
| 2355 | case rnat_when: |
| 2356 | output_P8_format (f, ptr->r.type, ptr->r.record.p.t); |
| 2357 | break; |
| 2358 | case priunat_psprel: |
| 2359 | case bsp_psprel: |
| 2360 | case bspstore_psprel: |
| 2361 | case rnat_psprel: |
| 2362 | output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); |
| 2363 | break; |
| 2364 | case unwabi: |
| 2365 | output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); |
| 2366 | break; |
| 2367 | case epilogue: |
| 2368 | output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); |
| 2369 | break; |
| 2370 | case label_state: |
| 2371 | case copy_state: |
| 2372 | output_B4_format (f, ptr->r.type, ptr->r.record.b.label); |
| 2373 | break; |
| 2374 | case spill_psprel: |
| 2375 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, |
| 2376 | ptr->r.record.x.reg, ptr->r.record.x.t, |
| 2377 | ptr->r.record.x.pspoff); |
| 2378 | break; |
| 2379 | case spill_sprel: |
| 2380 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, |
| 2381 | ptr->r.record.x.reg, ptr->r.record.x.t, |
| 2382 | ptr->r.record.x.spoff); |
| 2383 | break; |
| 2384 | case spill_reg: |
| 2385 | output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, |
| 2386 | ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, |
| 2387 | ptr->r.record.x.treg, ptr->r.record.x.t); |
| 2388 | break; |
| 2389 | case spill_psprel_p: |
| 2390 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, |
| 2391 | ptr->r.record.x.ab, ptr->r.record.x.reg, |
| 2392 | ptr->r.record.x.t, ptr->r.record.x.pspoff); |
| 2393 | break; |
| 2394 | case spill_sprel_p: |
| 2395 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, |
| 2396 | ptr->r.record.x.ab, ptr->r.record.x.reg, |
| 2397 | ptr->r.record.x.t, ptr->r.record.x.spoff); |
| 2398 | break; |
| 2399 | case spill_reg_p: |
| 2400 | output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, |
| 2401 | ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, |
| 2402 | ptr->r.record.x.xy, ptr->r.record.x.treg, |
| 2403 | ptr->r.record.x.t); |
| 2404 | break; |
| 2405 | default: |
| 2406 | as_bad ("record_type_not_valid"); |
| 2407 | break; |
| 2408 | } |
| 2409 | } |
| 2410 | |
| 2411 | /* Given a unw_rec_list list, process all the records with |
| 2412 | the specified function. */ |
| 2413 | static void |
| 2414 | process_unw_records (list, f) |
| 2415 | unw_rec_list *list; |
| 2416 | vbyte_func f; |
| 2417 | { |
| 2418 | unw_rec_list *ptr; |
| 2419 | for (ptr = list; ptr; ptr = ptr->next) |
| 2420 | process_one_record (ptr, f); |
| 2421 | } |
| 2422 | |
| 2423 | /* Determine the size of a record list in bytes. */ |
| 2424 | static int |
| 2425 | calc_record_size (list) |
| 2426 | unw_rec_list *list; |
| 2427 | { |
| 2428 | vbyte_count = 0; |
| 2429 | process_unw_records (list, count_output); |
| 2430 | return vbyte_count; |
| 2431 | } |
| 2432 | |
| 2433 | /* Update IMASK bitmask to reflect the fact that one or more registers |
| 2434 | of type TYPE are saved starting at instruction with index T. If N |
| 2435 | bits are set in REGMASK, it is assumed that instructions T through |
| 2436 | T+N-1 save these registers. |
| 2437 | |
| 2438 | TYPE values: |
| 2439 | 0: no save |
| 2440 | 1: instruction saves next fp reg |
| 2441 | 2: instruction saves next general reg |
| 2442 | 3: instruction saves next branch reg */ |
| 2443 | static void |
| 2444 | set_imask (region, regmask, t, type) |
| 2445 | unw_rec_list *region; |
| 2446 | unsigned long regmask; |
| 2447 | unsigned long t; |
| 2448 | unsigned int type; |
| 2449 | { |
| 2450 | unsigned char *imask; |
| 2451 | unsigned long imask_size; |
| 2452 | unsigned int i; |
| 2453 | int pos; |
| 2454 | |
| 2455 | imask = region->r.record.r.mask.i; |
| 2456 | imask_size = region->r.record.r.imask_size; |
| 2457 | if (!imask) |
| 2458 | { |
| 2459 | imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; |
| 2460 | imask = xmalloc (imask_size); |
| 2461 | memset (imask, 0, imask_size); |
| 2462 | |
| 2463 | region->r.record.r.imask_size = imask_size; |
| 2464 | region->r.record.r.mask.i = imask; |
| 2465 | } |
| 2466 | |
| 2467 | i = (t / 4) + 1; |
| 2468 | pos = 2 * (3 - t % 4); |
| 2469 | while (regmask) |
| 2470 | { |
| 2471 | if (i >= imask_size) |
| 2472 | { |
| 2473 | as_bad ("Ignoring attempt to spill beyond end of region"); |
| 2474 | return; |
| 2475 | } |
| 2476 | |
| 2477 | imask[i] |= (type & 0x3) << pos; |
| 2478 | |
| 2479 | regmask &= (regmask - 1); |
| 2480 | pos -= 2; |
| 2481 | if (pos < 0) |
| 2482 | { |
| 2483 | pos = 0; |
| 2484 | ++i; |
| 2485 | } |
| 2486 | } |
| 2487 | } |
| 2488 | |
| 2489 | static int |
| 2490 | count_bits (unsigned long mask) |
| 2491 | { |
| 2492 | int n = 0; |
| 2493 | |
| 2494 | while (mask) |
| 2495 | { |
| 2496 | mask &= mask - 1; |
| 2497 | ++n; |
| 2498 | } |
| 2499 | return n; |
| 2500 | } |
| 2501 | |
| 2502 | /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. |
| 2503 | SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag |
| 2504 | containing FIRST_ADDR. */ |
| 2505 | |
| 2506 | unsigned long |
| 2507 | slot_index (slot_addr, slot_frag, first_addr, first_frag) |
| 2508 | unsigned long slot_addr; |
| 2509 | fragS *slot_frag; |
| 2510 | unsigned long first_addr; |
| 2511 | fragS *first_frag; |
| 2512 | { |
| 2513 | unsigned long index = 0; |
| 2514 | |
| 2515 | /* First time we are called, the initial address and frag are invalid. */ |
| 2516 | if (first_addr == 0) |
| 2517 | return 0; |
| 2518 | |
| 2519 | /* If the two addresses are in different frags, then we need to add in |
| 2520 | the remaining size of this frag, and then the entire size of intermediate |
| 2521 | frags. */ |
| 2522 | while (slot_frag != first_frag) |
| 2523 | { |
| 2524 | unsigned long start_addr = (unsigned long) &first_frag->fr_literal; |
| 2525 | |
| 2526 | /* Add in the full size of the frag converted to instruction slots. */ |
| 2527 | index += 3 * (first_frag->fr_fix >> 4); |
| 2528 | /* Subtract away the initial part before first_addr. */ |
| 2529 | index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) |
| 2530 | + ((first_addr & 0x3) - (start_addr & 0x3))); |
| 2531 | |
| 2532 | /* Move to the beginning of the next frag. */ |
| 2533 | first_frag = first_frag->fr_next; |
| 2534 | first_addr = (unsigned long) &first_frag->fr_literal; |
| 2535 | } |
| 2536 | |
| 2537 | /* Add in the used part of the last frag. */ |
| 2538 | index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) |
| 2539 | + ((slot_addr & 0x3) - (first_addr & 0x3))); |
| 2540 | return index; |
| 2541 | } |
| 2542 | |
| 2543 | /* Optimize unwind record directives. */ |
| 2544 | |
| 2545 | static unw_rec_list * |
| 2546 | optimize_unw_records (list) |
| 2547 | unw_rec_list *list; |
| 2548 | { |
| 2549 | if (!list) |
| 2550 | return NULL; |
| 2551 | |
| 2552 | /* If the only unwind record is ".prologue" or ".prologue" followed |
| 2553 | by ".body", then we can optimize the unwind directives away. */ |
| 2554 | if (list->r.type == prologue |
| 2555 | && (list->next == NULL |
| 2556 | || (list->next->r.type == body && list->next->next == NULL))) |
| 2557 | return NULL; |
| 2558 | |
| 2559 | return list; |
| 2560 | } |
| 2561 | |
| 2562 | /* Given a complete record list, process any records which have |
| 2563 | unresolved fields, (ie length counts for a prologue). After |
| 2564 | this has been run, all neccessary information should be available |
| 2565 | within each record to generate an image. */ |
| 2566 | |
| 2567 | static void |
| 2568 | fixup_unw_records (list) |
| 2569 | unw_rec_list *list; |
| 2570 | { |
| 2571 | unw_rec_list *ptr, *region = 0; |
| 2572 | unsigned long first_addr = 0, rlen = 0, t; |
| 2573 | fragS *first_frag = 0; |
| 2574 | |
| 2575 | for (ptr = list; ptr; ptr = ptr->next) |
| 2576 | { |
| 2577 | if (ptr->slot_number == SLOT_NUM_NOT_SET) |
| 2578 | as_bad (" Insn slot not set in unwind record."); |
| 2579 | t = slot_index (ptr->slot_number, ptr->slot_frag, |
| 2580 | first_addr, first_frag); |
| 2581 | switch (ptr->r.type) |
| 2582 | { |
| 2583 | case prologue: |
| 2584 | case prologue_gr: |
| 2585 | case body: |
| 2586 | { |
| 2587 | unw_rec_list *last; |
| 2588 | int size, dir_len = 0; |
| 2589 | unsigned long last_addr; |
| 2590 | fragS *last_frag; |
| 2591 | |
| 2592 | first_addr = ptr->slot_number; |
| 2593 | first_frag = ptr->slot_frag; |
| 2594 | ptr->slot_number = 0; |
| 2595 | /* Find either the next body/prologue start, or the end of |
| 2596 | the list, and determine the size of the region. */ |
| 2597 | last_addr = unwind.next_slot_number; |
| 2598 | last_frag = unwind.next_slot_frag; |
| 2599 | for (last = ptr->next; last != NULL; last = last->next) |
| 2600 | if (last->r.type == prologue || last->r.type == prologue_gr |
| 2601 | || last->r.type == body) |
| 2602 | { |
| 2603 | last_addr = last->slot_number; |
| 2604 | last_frag = last->slot_frag; |
| 2605 | break; |
| 2606 | } |
| 2607 | else if (!last->next) |
| 2608 | { |
| 2609 | /* In the absence of an explicit .body directive, |
| 2610 | the prologue ends after the last instruction |
| 2611 | covered by an unwind directive. */ |
| 2612 | if (ptr->r.type != body) |
| 2613 | { |
| 2614 | last_addr = last->slot_number; |
| 2615 | last_frag = last->slot_frag; |
| 2616 | switch (last->r.type) |
| 2617 | { |
| 2618 | case frgr_mem: |
| 2619 | dir_len = (count_bits (last->r.record.p.frmask) |
| 2620 | + count_bits (last->r.record.p.grmask)); |
| 2621 | break; |
| 2622 | case fr_mem: |
| 2623 | case gr_mem: |
| 2624 | dir_len += count_bits (last->r.record.p.rmask); |
| 2625 | break; |
| 2626 | case br_mem: |
| 2627 | case br_gr: |
| 2628 | dir_len += count_bits (last->r.record.p.brmask); |
| 2629 | break; |
| 2630 | case gr_gr: |
| 2631 | dir_len += count_bits (last->r.record.p.grmask); |
| 2632 | break; |
| 2633 | default: |
| 2634 | dir_len = 1; |
| 2635 | break; |
| 2636 | } |
| 2637 | } |
| 2638 | break; |
| 2639 | } |
| 2640 | size = (slot_index (last_addr, last_frag, first_addr, first_frag) |
| 2641 | + dir_len); |
| 2642 | rlen = ptr->r.record.r.rlen = size; |
| 2643 | region = ptr; |
| 2644 | break; |
| 2645 | } |
| 2646 | case epilogue: |
| 2647 | ptr->r.record.b.t = rlen - 1 - t; |
| 2648 | break; |
| 2649 | |
| 2650 | case mem_stack_f: |
| 2651 | case mem_stack_v: |
| 2652 | case rp_when: |
| 2653 | case pfs_when: |
| 2654 | case preds_when: |
| 2655 | case unat_when: |
| 2656 | case lc_when: |
| 2657 | case fpsr_when: |
| 2658 | case priunat_when_gr: |
| 2659 | case priunat_when_mem: |
| 2660 | case bsp_when: |
| 2661 | case bspstore_when: |
| 2662 | case rnat_when: |
| 2663 | ptr->r.record.p.t = t; |
| 2664 | break; |
| 2665 | |
| 2666 | case spill_reg: |
| 2667 | case spill_sprel: |
| 2668 | case spill_psprel: |
| 2669 | case spill_reg_p: |
| 2670 | case spill_sprel_p: |
| 2671 | case spill_psprel_p: |
| 2672 | ptr->r.record.x.t = t; |
| 2673 | break; |
| 2674 | |
| 2675 | case frgr_mem: |
| 2676 | if (!region) |
| 2677 | { |
| 2678 | as_bad ("frgr_mem record before region record!\n"); |
| 2679 | return; |
| 2680 | } |
| 2681 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; |
| 2682 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; |
| 2683 | set_imask (region, ptr->r.record.p.frmask, t, 1); |
| 2684 | set_imask (region, ptr->r.record.p.grmask, t, 2); |
| 2685 | break; |
| 2686 | case fr_mem: |
| 2687 | if (!region) |
| 2688 | { |
| 2689 | as_bad ("fr_mem record before region record!\n"); |
| 2690 | return; |
| 2691 | } |
| 2692 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; |
| 2693 | set_imask (region, ptr->r.record.p.rmask, t, 1); |
| 2694 | break; |
| 2695 | case gr_mem: |
| 2696 | if (!region) |
| 2697 | { |
| 2698 | as_bad ("gr_mem record before region record!\n"); |
| 2699 | return; |
| 2700 | } |
| 2701 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; |
| 2702 | set_imask (region, ptr->r.record.p.rmask, t, 2); |
| 2703 | break; |
| 2704 | case br_mem: |
| 2705 | if (!region) |
| 2706 | { |
| 2707 | as_bad ("br_mem record before region record!\n"); |
| 2708 | return; |
| 2709 | } |
| 2710 | region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; |
| 2711 | set_imask (region, ptr->r.record.p.brmask, t, 3); |
| 2712 | break; |
| 2713 | |
| 2714 | case gr_gr: |
| 2715 | if (!region) |
| 2716 | { |
| 2717 | as_bad ("gr_gr record before region record!\n"); |
| 2718 | return; |
| 2719 | } |
| 2720 | set_imask (region, ptr->r.record.p.grmask, t, 2); |
| 2721 | break; |
| 2722 | case br_gr: |
| 2723 | if (!region) |
| 2724 | { |
| 2725 | as_bad ("br_gr record before region record!\n"); |
| 2726 | return; |
| 2727 | } |
| 2728 | set_imask (region, ptr->r.record.p.brmask, t, 3); |
| 2729 | break; |
| 2730 | |
| 2731 | default: |
| 2732 | break; |
| 2733 | } |
| 2734 | } |
| 2735 | } |
| 2736 | |
| 2737 | /* Generate an unwind image from a record list. Returns the number of |
| 2738 | bytes in the resulting image. The memory image itselof is returned |
| 2739 | in the 'ptr' parameter. */ |
| 2740 | static int |
| 2741 | output_unw_records (list, ptr) |
| 2742 | unw_rec_list *list; |
| 2743 | void **ptr; |
| 2744 | { |
| 2745 | int size, x, extra = 0; |
| 2746 | unsigned char *mem; |
| 2747 | |
| 2748 | *ptr = NULL; |
| 2749 | |
| 2750 | list = optimize_unw_records (list); |
| 2751 | fixup_unw_records (list); |
| 2752 | size = calc_record_size (list); |
| 2753 | |
| 2754 | /* pad to 8 byte boundry. */ |
| 2755 | x = size % 8; |
| 2756 | if (x != 0) |
| 2757 | extra = 8 - x; |
| 2758 | |
| 2759 | if (size > 0 || unwind.force_unwind_entry) |
| 2760 | { |
| 2761 | unwind.force_unwind_entry = 0; |
| 2762 | |
| 2763 | /* Add 8 for the header + 8 more bytes for the personality offset. */ |
| 2764 | mem = xmalloc (size + extra + 16); |
| 2765 | |
| 2766 | vbyte_mem_ptr = mem + 8; |
| 2767 | /* Clear the padding area and personality. */ |
| 2768 | memset (mem + 8 + size, 0 , extra + 8); |
| 2769 | /* Initialize the header area. */ |
| 2770 | md_number_to_chars (mem, |
| 2771 | (((bfd_vma) 1 << 48) /* version */ |
| 2772 | | (unwind.personality_routine |
| 2773 | ? ((bfd_vma) 3 << 32) /* U & E handler flags */ |
| 2774 | : 0) |
| 2775 | | ((size + extra) / 8)), /* length (dwords) */ |
| 2776 | 8); |
| 2777 | |
| 2778 | process_unw_records (list, output_vbyte_mem); |
| 2779 | |
| 2780 | *ptr = mem; |
| 2781 | |
| 2782 | size += extra + 16; |
| 2783 | } |
| 2784 | return size; |
| 2785 | } |
| 2786 | |
| 2787 | static int |
| 2788 | convert_expr_to_ab_reg (e, ab, regp) |
| 2789 | expressionS *e; |
| 2790 | unsigned int *ab; |
| 2791 | unsigned int *regp; |
| 2792 | { |
| 2793 | unsigned int reg; |
| 2794 | |
| 2795 | if (e->X_op != O_register) |
| 2796 | return 0; |
| 2797 | |
| 2798 | reg = e->X_add_number; |
| 2799 | if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) |
| 2800 | { |
| 2801 | *ab = 0; |
| 2802 | *regp = reg - REG_GR; |
| 2803 | } |
| 2804 | else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) |
| 2805 | || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) |
| 2806 | { |
| 2807 | *ab = 1; |
| 2808 | *regp = reg - REG_FR; |
| 2809 | } |
| 2810 | else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) |
| 2811 | { |
| 2812 | *ab = 2; |
| 2813 | *regp = reg - REG_BR; |
| 2814 | } |
| 2815 | else |
| 2816 | { |
| 2817 | *ab = 3; |
| 2818 | switch (reg) |
| 2819 | { |
| 2820 | case REG_PR: *regp = 0; break; |
| 2821 | case REG_PSP: *regp = 1; break; |
| 2822 | case REG_PRIUNAT: *regp = 2; break; |
| 2823 | case REG_BR + 0: *regp = 3; break; |
| 2824 | case REG_AR + AR_BSP: *regp = 4; break; |
| 2825 | case REG_AR + AR_BSPSTORE: *regp = 5; break; |
| 2826 | case REG_AR + AR_RNAT: *regp = 6; break; |
| 2827 | case REG_AR + AR_UNAT: *regp = 7; break; |
| 2828 | case REG_AR + AR_FPSR: *regp = 8; break; |
| 2829 | case REG_AR + AR_PFS: *regp = 9; break; |
| 2830 | case REG_AR + AR_LC: *regp = 10; break; |
| 2831 | |
| 2832 | default: |
| 2833 | return 0; |
| 2834 | } |
| 2835 | } |
| 2836 | return 1; |
| 2837 | } |
| 2838 | |
| 2839 | static int |
| 2840 | convert_expr_to_xy_reg (e, xy, regp) |
| 2841 | expressionS *e; |
| 2842 | unsigned int *xy; |
| 2843 | unsigned int *regp; |
| 2844 | { |
| 2845 | unsigned int reg; |
| 2846 | |
| 2847 | if (e->X_op != O_register) |
| 2848 | return 0; |
| 2849 | |
| 2850 | reg = e->X_add_number; |
| 2851 | |
| 2852 | if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) |
| 2853 | { |
| 2854 | *xy = 0; |
| 2855 | *regp = reg - REG_GR; |
| 2856 | } |
| 2857 | else if (reg >= REG_FR && reg <= (REG_FR + 127)) |
| 2858 | { |
| 2859 | *xy = 1; |
| 2860 | *regp = reg - REG_FR; |
| 2861 | } |
| 2862 | else if (reg >= REG_BR && reg <= (REG_BR + 7)) |
| 2863 | { |
| 2864 | *xy = 2; |
| 2865 | *regp = reg - REG_BR; |
| 2866 | } |
| 2867 | else |
| 2868 | return -1; |
| 2869 | return 1; |
| 2870 | } |
| 2871 | |
| 2872 | static void |
| 2873 | dot_radix (dummy) |
| 2874 | int dummy ATTRIBUTE_UNUSED; |
| 2875 | { |
| 2876 | int radix; |
| 2877 | |
| 2878 | SKIP_WHITESPACE (); |
| 2879 | radix = *input_line_pointer++; |
| 2880 | |
| 2881 | if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) |
| 2882 | { |
| 2883 | as_bad ("Radix `%c' unsupported", *input_line_pointer); |
| 2884 | ignore_rest_of_line (); |
| 2885 | return; |
| 2886 | } |
| 2887 | } |
| 2888 | |
| 2889 | /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ |
| 2890 | static void |
| 2891 | dot_special_section (which) |
| 2892 | int which; |
| 2893 | { |
| 2894 | set_section ((char *) special_section_name[which]); |
| 2895 | } |
| 2896 | |
| 2897 | static void |
| 2898 | add_unwind_entry (ptr) |
| 2899 | unw_rec_list *ptr; |
| 2900 | { |
| 2901 | if (unwind.tail) |
| 2902 | unwind.tail->next = ptr; |
| 2903 | else |
| 2904 | unwind.list = ptr; |
| 2905 | unwind.tail = ptr; |
| 2906 | |
| 2907 | /* The current entry can in fact be a chain of unwind entries. */ |
| 2908 | if (unwind.current_entry == NULL) |
| 2909 | unwind.current_entry = ptr; |
| 2910 | } |
| 2911 | |
| 2912 | static void |
| 2913 | dot_fframe (dummy) |
| 2914 | int dummy ATTRIBUTE_UNUSED; |
| 2915 | { |
| 2916 | expressionS e; |
| 2917 | |
| 2918 | parse_operand (&e); |
| 2919 | |
| 2920 | if (e.X_op != O_constant) |
| 2921 | as_bad ("Operand to .fframe must be a constant"); |
| 2922 | else |
| 2923 | add_unwind_entry (output_mem_stack_f (e.X_add_number)); |
| 2924 | } |
| 2925 | |
| 2926 | static void |
| 2927 | dot_vframe (dummy) |
| 2928 | int dummy ATTRIBUTE_UNUSED; |
| 2929 | { |
| 2930 | expressionS e; |
| 2931 | unsigned reg; |
| 2932 | |
| 2933 | parse_operand (&e); |
| 2934 | reg = e.X_add_number - REG_GR; |
| 2935 | if (e.X_op == O_register && reg < 128) |
| 2936 | { |
| 2937 | add_unwind_entry (output_mem_stack_v ()); |
| 2938 | if (! (unwind.prologue_mask & 2)) |
| 2939 | add_unwind_entry (output_psp_gr (reg)); |
| 2940 | } |
| 2941 | else |
| 2942 | as_bad ("First operand to .vframe must be a general register"); |
| 2943 | } |
| 2944 | |
| 2945 | static void |
| 2946 | dot_vframesp (dummy) |
| 2947 | int dummy ATTRIBUTE_UNUSED; |
| 2948 | { |
| 2949 | expressionS e; |
| 2950 | |
| 2951 | parse_operand (&e); |
| 2952 | if (e.X_op == O_constant) |
| 2953 | { |
| 2954 | add_unwind_entry (output_mem_stack_v ()); |
| 2955 | add_unwind_entry (output_psp_sprel (e.X_add_number)); |
| 2956 | } |
| 2957 | else |
| 2958 | as_bad ("First operand to .vframesp must be a general register"); |
| 2959 | } |
| 2960 | |
| 2961 | static void |
| 2962 | dot_vframepsp (dummy) |
| 2963 | int dummy ATTRIBUTE_UNUSED; |
| 2964 | { |
| 2965 | expressionS e; |
| 2966 | |
| 2967 | parse_operand (&e); |
| 2968 | if (e.X_op == O_constant) |
| 2969 | { |
| 2970 | add_unwind_entry (output_mem_stack_v ()); |
| 2971 | add_unwind_entry (output_psp_sprel (e.X_add_number)); |
| 2972 | } |
| 2973 | else |
| 2974 | as_bad ("First operand to .vframepsp must be a general register"); |
| 2975 | } |
| 2976 | |
| 2977 | static void |
| 2978 | dot_save (dummy) |
| 2979 | int dummy ATTRIBUTE_UNUSED; |
| 2980 | { |
| 2981 | expressionS e1, e2; |
| 2982 | int sep; |
| 2983 | int reg1, reg2; |
| 2984 | |
| 2985 | sep = parse_operand (&e1); |
| 2986 | if (sep != ',') |
| 2987 | as_bad ("No second operand to .save"); |
| 2988 | sep = parse_operand (&e2); |
| 2989 | |
| 2990 | reg1 = e1.X_add_number; |
| 2991 | reg2 = e2.X_add_number - REG_GR; |
| 2992 | |
| 2993 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
| 2994 | if (e1.X_op == O_register) |
| 2995 | { |
| 2996 | if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) |
| 2997 | { |
| 2998 | switch (reg1) |
| 2999 | { |
| 3000 | case REG_AR + AR_BSP: |
| 3001 | add_unwind_entry (output_bsp_when ()); |
| 3002 | add_unwind_entry (output_bsp_gr (reg2)); |
| 3003 | break; |
| 3004 | case REG_AR + AR_BSPSTORE: |
| 3005 | add_unwind_entry (output_bspstore_when ()); |
| 3006 | add_unwind_entry (output_bspstore_gr (reg2)); |
| 3007 | break; |
| 3008 | case REG_AR + AR_RNAT: |
| 3009 | add_unwind_entry (output_rnat_when ()); |
| 3010 | add_unwind_entry (output_rnat_gr (reg2)); |
| 3011 | break; |
| 3012 | case REG_AR + AR_UNAT: |
| 3013 | add_unwind_entry (output_unat_when ()); |
| 3014 | add_unwind_entry (output_unat_gr (reg2)); |
| 3015 | break; |
| 3016 | case REG_AR + AR_FPSR: |
| 3017 | add_unwind_entry (output_fpsr_when ()); |
| 3018 | add_unwind_entry (output_fpsr_gr (reg2)); |
| 3019 | break; |
| 3020 | case REG_AR + AR_PFS: |
| 3021 | add_unwind_entry (output_pfs_when ()); |
| 3022 | if (! (unwind.prologue_mask & 4)) |
| 3023 | add_unwind_entry (output_pfs_gr (reg2)); |
| 3024 | break; |
| 3025 | case REG_AR + AR_LC: |
| 3026 | add_unwind_entry (output_lc_when ()); |
| 3027 | add_unwind_entry (output_lc_gr (reg2)); |
| 3028 | break; |
| 3029 | case REG_BR: |
| 3030 | add_unwind_entry (output_rp_when ()); |
| 3031 | if (! (unwind.prologue_mask & 8)) |
| 3032 | add_unwind_entry (output_rp_gr (reg2)); |
| 3033 | break; |
| 3034 | case REG_PR: |
| 3035 | add_unwind_entry (output_preds_when ()); |
| 3036 | if (! (unwind.prologue_mask & 1)) |
| 3037 | add_unwind_entry (output_preds_gr (reg2)); |
| 3038 | break; |
| 3039 | case REG_PRIUNAT: |
| 3040 | add_unwind_entry (output_priunat_when_gr ()); |
| 3041 | add_unwind_entry (output_priunat_gr (reg2)); |
| 3042 | break; |
| 3043 | default: |
| 3044 | as_bad ("First operand not a valid register"); |
| 3045 | } |
| 3046 | } |
| 3047 | else |
| 3048 | as_bad (" Second operand not a valid register"); |
| 3049 | } |
| 3050 | else |
| 3051 | as_bad ("First operand not a register"); |
| 3052 | } |
| 3053 | |
| 3054 | static void |
| 3055 | dot_restore (dummy) |
| 3056 | int dummy ATTRIBUTE_UNUSED; |
| 3057 | { |
| 3058 | expressionS e1, e2; |
| 3059 | unsigned long ecount; /* # of _additional_ regions to pop */ |
| 3060 | int sep; |
| 3061 | |
| 3062 | sep = parse_operand (&e1); |
| 3063 | if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) |
| 3064 | { |
| 3065 | as_bad ("First operand to .restore must be stack pointer (sp)"); |
| 3066 | return; |
| 3067 | } |
| 3068 | |
| 3069 | if (sep == ',') |
| 3070 | { |
| 3071 | parse_operand (&e2); |
| 3072 | if (e2.X_op != O_constant || e2.X_add_number < 0) |
| 3073 | { |
| 3074 | as_bad ("Second operand to .restore must be a constant >= 0"); |
| 3075 | return; |
| 3076 | } |
| 3077 | ecount = e2.X_add_number; |
| 3078 | } |
| 3079 | else |
| 3080 | ecount = unwind.prologue_count - 1; |
| 3081 | add_unwind_entry (output_epilogue (ecount)); |
| 3082 | |
| 3083 | if (ecount < unwind.prologue_count) |
| 3084 | unwind.prologue_count -= ecount + 1; |
| 3085 | else |
| 3086 | unwind.prologue_count = 0; |
| 3087 | } |
| 3088 | |
| 3089 | static void |
| 3090 | dot_restorereg (dummy) |
| 3091 | int dummy ATTRIBUTE_UNUSED; |
| 3092 | { |
| 3093 | unsigned int ab, reg; |
| 3094 | expressionS e; |
| 3095 | |
| 3096 | parse_operand (&e); |
| 3097 | |
| 3098 | if (!convert_expr_to_ab_reg (&e, &ab, ®)) |
| 3099 | { |
| 3100 | as_bad ("First operand to .restorereg must be a preserved register"); |
| 3101 | return; |
| 3102 | } |
| 3103 | add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); |
| 3104 | } |
| 3105 | |
| 3106 | static void |
| 3107 | dot_restorereg_p (dummy) |
| 3108 | int dummy ATTRIBUTE_UNUSED; |
| 3109 | { |
| 3110 | unsigned int qp, ab, reg; |
| 3111 | expressionS e1, e2; |
| 3112 | int sep; |
| 3113 | |
| 3114 | sep = parse_operand (&e1); |
| 3115 | if (sep != ',') |
| 3116 | { |
| 3117 | as_bad ("No second operand to .restorereg.p"); |
| 3118 | return; |
| 3119 | } |
| 3120 | |
| 3121 | parse_operand (&e2); |
| 3122 | |
| 3123 | qp = e1.X_add_number - REG_P; |
| 3124 | if (e1.X_op != O_register || qp > 63) |
| 3125 | { |
| 3126 | as_bad ("First operand to .restorereg.p must be a predicate"); |
| 3127 | return; |
| 3128 | } |
| 3129 | |
| 3130 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) |
| 3131 | { |
| 3132 | as_bad ("Second operand to .restorereg.p must be a preserved register"); |
| 3133 | return; |
| 3134 | } |
| 3135 | add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); |
| 3136 | } |
| 3137 | |
| 3138 | static int |
| 3139 | generate_unwind_image (text_name) |
| 3140 | const char *text_name; |
| 3141 | { |
| 3142 | int size; |
| 3143 | unsigned char *unw_rec; |
| 3144 | |
| 3145 | /* Force out pending instructions, to make sure all unwind records have |
| 3146 | a valid slot_number field. */ |
| 3147 | ia64_flush_insns (); |
| 3148 | |
| 3149 | /* Generate the unwind record. */ |
| 3150 | size = output_unw_records (unwind.list, (void **) &unw_rec); |
| 3151 | if (size % 8 != 0) |
| 3152 | as_bad ("Unwind record is not a multiple of 8 bytes."); |
| 3153 | |
| 3154 | /* If there are unwind records, switch sections, and output the info. */ |
| 3155 | if (size != 0) |
| 3156 | { |
| 3157 | unsigned char *where; |
| 3158 | char *sec_name; |
| 3159 | expressionS exp; |
| 3160 | |
| 3161 | make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name); |
| 3162 | set_section (sec_name); |
| 3163 | bfd_set_section_flags (stdoutput, now_seg, |
| 3164 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); |
| 3165 | |
| 3166 | /* Make sure the section has 8 byte alignment. */ |
| 3167 | record_alignment (now_seg, 3); |
| 3168 | |
| 3169 | /* Set expression which points to start of unwind descriptor area. */ |
| 3170 | unwind.info = expr_build_dot (); |
| 3171 | |
| 3172 | where = (unsigned char *) frag_more (size); |
| 3173 | |
| 3174 | /* Issue a label for this address, and keep track of it to put it |
| 3175 | in the unwind section. */ |
| 3176 | |
| 3177 | /* Copy the information from the unwind record into this section. The |
| 3178 | data is already in the correct byte order. */ |
| 3179 | memcpy (where, unw_rec, size); |
| 3180 | |
| 3181 | /* Add the personality address to the image. */ |
| 3182 | if (unwind.personality_routine != 0) |
| 3183 | { |
| 3184 | exp.X_op = O_symbol; |
| 3185 | exp.X_add_symbol = unwind.personality_routine; |
| 3186 | exp.X_add_number = 0; |
| 3187 | fix_new_exp (frag_now, frag_now_fix () - 8, 8, |
| 3188 | &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB); |
| 3189 | unwind.personality_routine = 0; |
| 3190 | } |
| 3191 | } |
| 3192 | |
| 3193 | free_list_records (unwind.list); |
| 3194 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
| 3195 | |
| 3196 | return size; |
| 3197 | } |
| 3198 | |
| 3199 | static void |
| 3200 | dot_handlerdata (dummy) |
| 3201 | int dummy ATTRIBUTE_UNUSED; |
| 3202 | { |
| 3203 | const char *text_name = segment_name (now_seg); |
| 3204 | |
| 3205 | /* If text section name starts with ".text" (which it should), |
| 3206 | strip this prefix off. */ |
| 3207 | if (strcmp (text_name, ".text") == 0) |
| 3208 | text_name = ""; |
| 3209 | |
| 3210 | unwind.force_unwind_entry = 1; |
| 3211 | |
| 3212 | /* Remember which segment we're in so we can switch back after .endp */ |
| 3213 | unwind.saved_text_seg = now_seg; |
| 3214 | unwind.saved_text_subseg = now_subseg; |
| 3215 | |
| 3216 | /* Generate unwind info into unwind-info section and then leave that |
| 3217 | section as the currently active one so dataXX directives go into |
| 3218 | the language specific data area of the unwind info block. */ |
| 3219 | generate_unwind_image (text_name); |
| 3220 | demand_empty_rest_of_line (); |
| 3221 | } |
| 3222 | |
| 3223 | static void |
| 3224 | dot_unwentry (dummy) |
| 3225 | int dummy ATTRIBUTE_UNUSED; |
| 3226 | { |
| 3227 | unwind.force_unwind_entry = 1; |
| 3228 | demand_empty_rest_of_line (); |
| 3229 | } |
| 3230 | |
| 3231 | static void |
| 3232 | dot_altrp (dummy) |
| 3233 | int dummy ATTRIBUTE_UNUSED; |
| 3234 | { |
| 3235 | expressionS e; |
| 3236 | unsigned reg; |
| 3237 | |
| 3238 | parse_operand (&e); |
| 3239 | reg = e.X_add_number - REG_BR; |
| 3240 | if (e.X_op == O_register && reg < 8) |
| 3241 | add_unwind_entry (output_rp_br (reg)); |
| 3242 | else |
| 3243 | as_bad ("First operand not a valid branch register"); |
| 3244 | } |
| 3245 | |
| 3246 | static void |
| 3247 | dot_savemem (psprel) |
| 3248 | int psprel; |
| 3249 | { |
| 3250 | expressionS e1, e2; |
| 3251 | int sep; |
| 3252 | int reg1, val; |
| 3253 | |
| 3254 | sep = parse_operand (&e1); |
| 3255 | if (sep != ',') |
| 3256 | as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); |
| 3257 | sep = parse_operand (&e2); |
| 3258 | |
| 3259 | reg1 = e1.X_add_number; |
| 3260 | val = e2.X_add_number; |
| 3261 | |
| 3262 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
| 3263 | if (e1.X_op == O_register) |
| 3264 | { |
| 3265 | if (e2.X_op == O_constant) |
| 3266 | { |
| 3267 | switch (reg1) |
| 3268 | { |
| 3269 | case REG_AR + AR_BSP: |
| 3270 | add_unwind_entry (output_bsp_when ()); |
| 3271 | add_unwind_entry ((psprel |
| 3272 | ? output_bsp_psprel |
| 3273 | : output_bsp_sprel) (val)); |
| 3274 | break; |
| 3275 | case REG_AR + AR_BSPSTORE: |
| 3276 | add_unwind_entry (output_bspstore_when ()); |
| 3277 | add_unwind_entry ((psprel |
| 3278 | ? output_bspstore_psprel |
| 3279 | : output_bspstore_sprel) (val)); |
| 3280 | break; |
| 3281 | case REG_AR + AR_RNAT: |
| 3282 | add_unwind_entry (output_rnat_when ()); |
| 3283 | add_unwind_entry ((psprel |
| 3284 | ? output_rnat_psprel |
| 3285 | : output_rnat_sprel) (val)); |
| 3286 | break; |
| 3287 | case REG_AR + AR_UNAT: |
| 3288 | add_unwind_entry (output_unat_when ()); |
| 3289 | add_unwind_entry ((psprel |
| 3290 | ? output_unat_psprel |
| 3291 | : output_unat_sprel) (val)); |
| 3292 | break; |
| 3293 | case REG_AR + AR_FPSR: |
| 3294 | add_unwind_entry (output_fpsr_when ()); |
| 3295 | add_unwind_entry ((psprel |
| 3296 | ? output_fpsr_psprel |
| 3297 | : output_fpsr_sprel) (val)); |
| 3298 | break; |
| 3299 | case REG_AR + AR_PFS: |
| 3300 | add_unwind_entry (output_pfs_when ()); |
| 3301 | add_unwind_entry ((psprel |
| 3302 | ? output_pfs_psprel |
| 3303 | : output_pfs_sprel) (val)); |
| 3304 | break; |
| 3305 | case REG_AR + AR_LC: |
| 3306 | add_unwind_entry (output_lc_when ()); |
| 3307 | add_unwind_entry ((psprel |
| 3308 | ? output_lc_psprel |
| 3309 | : output_lc_sprel) (val)); |
| 3310 | break; |
| 3311 | case REG_BR: |
| 3312 | add_unwind_entry (output_rp_when ()); |
| 3313 | add_unwind_entry ((psprel |
| 3314 | ? output_rp_psprel |
| 3315 | : output_rp_sprel) (val)); |
| 3316 | break; |
| 3317 | case REG_PR: |
| 3318 | add_unwind_entry (output_preds_when ()); |
| 3319 | add_unwind_entry ((psprel |
| 3320 | ? output_preds_psprel |
| 3321 | : output_preds_sprel) (val)); |
| 3322 | break; |
| 3323 | case REG_PRIUNAT: |
| 3324 | add_unwind_entry (output_priunat_when_mem ()); |
| 3325 | add_unwind_entry ((psprel |
| 3326 | ? output_priunat_psprel |
| 3327 | : output_priunat_sprel) (val)); |
| 3328 | break; |
| 3329 | default: |
| 3330 | as_bad ("First operand not a valid register"); |
| 3331 | } |
| 3332 | } |
| 3333 | else |
| 3334 | as_bad (" Second operand not a valid constant"); |
| 3335 | } |
| 3336 | else |
| 3337 | as_bad ("First operand not a register"); |
| 3338 | } |
| 3339 | |
| 3340 | static void |
| 3341 | dot_saveg (dummy) |
| 3342 | int dummy ATTRIBUTE_UNUSED; |
| 3343 | { |
| 3344 | expressionS e1, e2; |
| 3345 | int sep; |
| 3346 | sep = parse_operand (&e1); |
| 3347 | if (sep == ',') |
| 3348 | parse_operand (&e2); |
| 3349 | |
| 3350 | if (e1.X_op != O_constant) |
| 3351 | as_bad ("First operand to .save.g must be a constant."); |
| 3352 | else |
| 3353 | { |
| 3354 | int grmask = e1.X_add_number; |
| 3355 | if (sep != ',') |
| 3356 | add_unwind_entry (output_gr_mem (grmask)); |
| 3357 | else |
| 3358 | { |
| 3359 | int reg = e2.X_add_number - REG_GR; |
| 3360 | if (e2.X_op == O_register && reg >= 0 && reg < 128) |
| 3361 | add_unwind_entry (output_gr_gr (grmask, reg)); |
| 3362 | else |
| 3363 | as_bad ("Second operand is an invalid register."); |
| 3364 | } |
| 3365 | } |
| 3366 | } |
| 3367 | |
| 3368 | static void |
| 3369 | dot_savef (dummy) |
| 3370 | int dummy ATTRIBUTE_UNUSED; |
| 3371 | { |
| 3372 | expressionS e1; |
| 3373 | int sep; |
| 3374 | sep = parse_operand (&e1); |
| 3375 | |
| 3376 | if (e1.X_op != O_constant) |
| 3377 | as_bad ("Operand to .save.f must be a constant."); |
| 3378 | else |
| 3379 | add_unwind_entry (output_fr_mem (e1.X_add_number)); |
| 3380 | } |
| 3381 | |
| 3382 | static void |
| 3383 | dot_saveb (dummy) |
| 3384 | int dummy ATTRIBUTE_UNUSED; |
| 3385 | { |
| 3386 | expressionS e1, e2; |
| 3387 | unsigned int reg; |
| 3388 | unsigned char sep; |
| 3389 | int brmask; |
| 3390 | |
| 3391 | sep = parse_operand (&e1); |
| 3392 | if (e1.X_op != O_constant) |
| 3393 | { |
| 3394 | as_bad ("First operand to .save.b must be a constant."); |
| 3395 | return; |
| 3396 | } |
| 3397 | brmask = e1.X_add_number; |
| 3398 | |
| 3399 | if (sep == ',') |
| 3400 | { |
| 3401 | sep = parse_operand (&e2); |
| 3402 | reg = e2.X_add_number - REG_GR; |
| 3403 | if (e2.X_op != O_register || reg > 127) |
| 3404 | { |
| 3405 | as_bad ("Second operand to .save.b must be a general register."); |
| 3406 | return; |
| 3407 | } |
| 3408 | add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); |
| 3409 | } |
| 3410 | else |
| 3411 | add_unwind_entry (output_br_mem (brmask)); |
| 3412 | |
| 3413 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
| 3414 | ignore_rest_of_line (); |
| 3415 | } |
| 3416 | |
| 3417 | static void |
| 3418 | dot_savegf (dummy) |
| 3419 | int dummy ATTRIBUTE_UNUSED; |
| 3420 | { |
| 3421 | expressionS e1, e2; |
| 3422 | int sep; |
| 3423 | sep = parse_operand (&e1); |
| 3424 | if (sep == ',') |
| 3425 | parse_operand (&e2); |
| 3426 | |
| 3427 | if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) |
| 3428 | as_bad ("Both operands of .save.gf must be constants."); |
| 3429 | else |
| 3430 | { |
| 3431 | int grmask = e1.X_add_number; |
| 3432 | int frmask = e2.X_add_number; |
| 3433 | add_unwind_entry (output_frgr_mem (grmask, frmask)); |
| 3434 | } |
| 3435 | } |
| 3436 | |
| 3437 | static void |
| 3438 | dot_spill (dummy) |
| 3439 | int dummy ATTRIBUTE_UNUSED; |
| 3440 | { |
| 3441 | expressionS e; |
| 3442 | unsigned char sep; |
| 3443 | |
| 3444 | sep = parse_operand (&e); |
| 3445 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
| 3446 | ignore_rest_of_line (); |
| 3447 | |
| 3448 | if (e.X_op != O_constant) |
| 3449 | as_bad ("Operand to .spill must be a constant"); |
| 3450 | else |
| 3451 | add_unwind_entry (output_spill_base (e.X_add_number)); |
| 3452 | } |
| 3453 | |
| 3454 | static void |
| 3455 | dot_spillreg (dummy) |
| 3456 | int dummy ATTRIBUTE_UNUSED; |
| 3457 | { |
| 3458 | int sep, ab, xy, reg, treg; |
| 3459 | expressionS e1, e2; |
| 3460 | |
| 3461 | sep = parse_operand (&e1); |
| 3462 | if (sep != ',') |
| 3463 | { |
| 3464 | as_bad ("No second operand to .spillreg"); |
| 3465 | return; |
| 3466 | } |
| 3467 | |
| 3468 | parse_operand (&e2); |
| 3469 | |
| 3470 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) |
| 3471 | { |
| 3472 | as_bad ("First operand to .spillreg must be a preserved register"); |
| 3473 | return; |
| 3474 | } |
| 3475 | |
| 3476 | if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) |
| 3477 | { |
| 3478 | as_bad ("Second operand to .spillreg must be a register"); |
| 3479 | return; |
| 3480 | } |
| 3481 | |
| 3482 | add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); |
| 3483 | } |
| 3484 | |
| 3485 | static void |
| 3486 | dot_spillmem (psprel) |
| 3487 | int psprel; |
| 3488 | { |
| 3489 | expressionS e1, e2; |
| 3490 | int sep, ab, reg; |
| 3491 | |
| 3492 | sep = parse_operand (&e1); |
| 3493 | if (sep != ',') |
| 3494 | { |
| 3495 | as_bad ("Second operand missing"); |
| 3496 | return; |
| 3497 | } |
| 3498 | |
| 3499 | parse_operand (&e2); |
| 3500 | |
| 3501 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) |
| 3502 | { |
| 3503 | as_bad ("First operand to .spill%s must be a preserved register", |
| 3504 | psprel ? "psp" : "sp"); |
| 3505 | return; |
| 3506 | } |
| 3507 | |
| 3508 | if (e2.X_op != O_constant) |
| 3509 | { |
| 3510 | as_bad ("Second operand to .spill%s must be a constant", |
| 3511 | psprel ? "psp" : "sp"); |
| 3512 | return; |
| 3513 | } |
| 3514 | |
| 3515 | if (psprel) |
| 3516 | add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); |
| 3517 | else |
| 3518 | add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); |
| 3519 | } |
| 3520 | |
| 3521 | static void |
| 3522 | dot_spillreg_p (dummy) |
| 3523 | int dummy ATTRIBUTE_UNUSED; |
| 3524 | { |
| 3525 | int sep, ab, xy, reg, treg; |
| 3526 | expressionS e1, e2, e3; |
| 3527 | unsigned int qp; |
| 3528 | |
| 3529 | sep = parse_operand (&e1); |
| 3530 | if (sep != ',') |
| 3531 | { |
| 3532 | as_bad ("No second and third operand to .spillreg.p"); |
| 3533 | return; |
| 3534 | } |
| 3535 | |
| 3536 | sep = parse_operand (&e2); |
| 3537 | if (sep != ',') |
| 3538 | { |
| 3539 | as_bad ("No third operand to .spillreg.p"); |
| 3540 | return; |
| 3541 | } |
| 3542 | |
| 3543 | parse_operand (&e3); |
| 3544 | |
| 3545 | qp = e1.X_add_number - REG_P; |
| 3546 | |
| 3547 | if (e1.X_op != O_register || qp > 63) |
| 3548 | { |
| 3549 | as_bad ("First operand to .spillreg.p must be a predicate"); |
| 3550 | return; |
| 3551 | } |
| 3552 | |
| 3553 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) |
| 3554 | { |
| 3555 | as_bad ("Second operand to .spillreg.p must be a preserved register"); |
| 3556 | return; |
| 3557 | } |
| 3558 | |
| 3559 | if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) |
| 3560 | { |
| 3561 | as_bad ("Third operand to .spillreg.p must be a register"); |
| 3562 | return; |
| 3563 | } |
| 3564 | |
| 3565 | add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); |
| 3566 | } |
| 3567 | |
| 3568 | static void |
| 3569 | dot_spillmem_p (psprel) |
| 3570 | int psprel; |
| 3571 | { |
| 3572 | expressionS e1, e2, e3; |
| 3573 | int sep, ab, reg; |
| 3574 | unsigned int qp; |
| 3575 | |
| 3576 | sep = parse_operand (&e1); |
| 3577 | if (sep != ',') |
| 3578 | { |
| 3579 | as_bad ("Second operand missing"); |
| 3580 | return; |
| 3581 | } |
| 3582 | |
| 3583 | parse_operand (&e2); |
| 3584 | if (sep != ',') |
| 3585 | { |
| 3586 | as_bad ("Second operand missing"); |
| 3587 | return; |
| 3588 | } |
| 3589 | |
| 3590 | parse_operand (&e3); |
| 3591 | |
| 3592 | qp = e1.X_add_number - REG_P; |
| 3593 | if (e1.X_op != O_register || qp > 63) |
| 3594 | { |
| 3595 | as_bad ("First operand to .spill%s_p must be a predicate", |
| 3596 | psprel ? "psp" : "sp"); |
| 3597 | return; |
| 3598 | } |
| 3599 | |
| 3600 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) |
| 3601 | { |
| 3602 | as_bad ("Second operand to .spill%s_p must be a preserved register", |
| 3603 | psprel ? "psp" : "sp"); |
| 3604 | return; |
| 3605 | } |
| 3606 | |
| 3607 | if (e3.X_op != O_constant) |
| 3608 | { |
| 3609 | as_bad ("Third operand to .spill%s_p must be a constant", |
| 3610 | psprel ? "psp" : "sp"); |
| 3611 | return; |
| 3612 | } |
| 3613 | |
| 3614 | if (psprel) |
| 3615 | add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number)); |
| 3616 | else |
| 3617 | add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number)); |
| 3618 | } |
| 3619 | |
| 3620 | static void |
| 3621 | dot_label_state (dummy) |
| 3622 | int dummy ATTRIBUTE_UNUSED; |
| 3623 | { |
| 3624 | expressionS e; |
| 3625 | |
| 3626 | parse_operand (&e); |
| 3627 | if (e.X_op != O_constant) |
| 3628 | { |
| 3629 | as_bad ("Operand to .label_state must be a constant"); |
| 3630 | return; |
| 3631 | } |
| 3632 | add_unwind_entry (output_label_state (e.X_add_number)); |
| 3633 | } |
| 3634 | |
| 3635 | static void |
| 3636 | dot_copy_state (dummy) |
| 3637 | int dummy ATTRIBUTE_UNUSED; |
| 3638 | { |
| 3639 | expressionS e; |
| 3640 | |
| 3641 | parse_operand (&e); |
| 3642 | if (e.X_op != O_constant) |
| 3643 | { |
| 3644 | as_bad ("Operand to .copy_state must be a constant"); |
| 3645 | return; |
| 3646 | } |
| 3647 | add_unwind_entry (output_copy_state (e.X_add_number)); |
| 3648 | } |
| 3649 | |
| 3650 | static void |
| 3651 | dot_unwabi (dummy) |
| 3652 | int dummy ATTRIBUTE_UNUSED; |
| 3653 | { |
| 3654 | expressionS e1, e2; |
| 3655 | unsigned char sep; |
| 3656 | |
| 3657 | sep = parse_operand (&e1); |
| 3658 | if (sep != ',') |
| 3659 | { |
| 3660 | as_bad ("Second operand to .unwabi missing"); |
| 3661 | return; |
| 3662 | } |
| 3663 | sep = parse_operand (&e2); |
| 3664 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
| 3665 | ignore_rest_of_line (); |
| 3666 | |
| 3667 | if (e1.X_op != O_constant) |
| 3668 | { |
| 3669 | as_bad ("First operand to .unwabi must be a constant"); |
| 3670 | return; |
| 3671 | } |
| 3672 | |
| 3673 | if (e2.X_op != O_constant) |
| 3674 | { |
| 3675 | as_bad ("Second operand to .unwabi must be a constant"); |
| 3676 | return; |
| 3677 | } |
| 3678 | |
| 3679 | add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); |
| 3680 | } |
| 3681 | |
| 3682 | static void |
| 3683 | dot_personality (dummy) |
| 3684 | int dummy ATTRIBUTE_UNUSED; |
| 3685 | { |
| 3686 | char *name, *p, c; |
| 3687 | SKIP_WHITESPACE (); |
| 3688 | name = input_line_pointer; |
| 3689 | c = get_symbol_end (); |
| 3690 | p = input_line_pointer; |
| 3691 | unwind.personality_routine = symbol_find_or_make (name); |
| 3692 | unwind.force_unwind_entry = 1; |
| 3693 | *p = c; |
| 3694 | SKIP_WHITESPACE (); |
| 3695 | demand_empty_rest_of_line (); |
| 3696 | } |
| 3697 | |
| 3698 | static void |
| 3699 | dot_proc (dummy) |
| 3700 | int dummy ATTRIBUTE_UNUSED; |
| 3701 | { |
| 3702 | char *name, *p, c; |
| 3703 | symbolS *sym; |
| 3704 | |
| 3705 | unwind.proc_start = expr_build_dot (); |
| 3706 | /* Parse names of main and alternate entry points and mark them as |
| 3707 | function symbols: */ |
| 3708 | while (1) |
| 3709 | { |
| 3710 | SKIP_WHITESPACE (); |
| 3711 | name = input_line_pointer; |
| 3712 | c = get_symbol_end (); |
| 3713 | p = input_line_pointer; |
| 3714 | sym = symbol_find_or_make (name); |
| 3715 | if (unwind.proc_start == 0) |
| 3716 | { |
| 3717 | unwind.proc_start = sym; |
| 3718 | } |
| 3719 | symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; |
| 3720 | *p = c; |
| 3721 | SKIP_WHITESPACE (); |
| 3722 | if (*input_line_pointer != ',') |
| 3723 | break; |
| 3724 | ++input_line_pointer; |
| 3725 | } |
| 3726 | demand_empty_rest_of_line (); |
| 3727 | ia64_do_align (16); |
| 3728 | |
| 3729 | unwind.prologue_count = 0; |
| 3730 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
| 3731 | unwind.personality_routine = 0; |
| 3732 | } |
| 3733 | |
| 3734 | static void |
| 3735 | dot_body (dummy) |
| 3736 | int dummy ATTRIBUTE_UNUSED; |
| 3737 | { |
| 3738 | unwind.prologue = 0; |
| 3739 | unwind.prologue_mask = 0; |
| 3740 | |
| 3741 | add_unwind_entry (output_body ()); |
| 3742 | demand_empty_rest_of_line (); |
| 3743 | } |
| 3744 | |
| 3745 | static void |
| 3746 | dot_prologue (dummy) |
| 3747 | int dummy ATTRIBUTE_UNUSED; |
| 3748 | { |
| 3749 | unsigned char sep; |
| 3750 | int mask = 0, grsave = 0; |
| 3751 | |
| 3752 | if (!is_it_end_of_statement ()) |
| 3753 | { |
| 3754 | expressionS e1, e2; |
| 3755 | sep = parse_operand (&e1); |
| 3756 | if (sep != ',') |
| 3757 | as_bad ("No second operand to .prologue"); |
| 3758 | sep = parse_operand (&e2); |
| 3759 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
| 3760 | ignore_rest_of_line (); |
| 3761 | |
| 3762 | if (e1.X_op == O_constant) |
| 3763 | { |
| 3764 | mask = e1.X_add_number; |
| 3765 | |
| 3766 | if (e2.X_op == O_constant) |
| 3767 | grsave = e2.X_add_number; |
| 3768 | else if (e2.X_op == O_register |
| 3769 | && (grsave = e2.X_add_number - REG_GR) < 128) |
| 3770 | ; |
| 3771 | else |
| 3772 | as_bad ("Second operand not a constant or general register"); |
| 3773 | |
| 3774 | add_unwind_entry (output_prologue_gr (mask, grsave)); |
| 3775 | } |
| 3776 | else |
| 3777 | as_bad ("First operand not a constant"); |
| 3778 | } |
| 3779 | else |
| 3780 | add_unwind_entry (output_prologue ()); |
| 3781 | |
| 3782 | unwind.prologue = 1; |
| 3783 | unwind.prologue_mask = mask; |
| 3784 | ++unwind.prologue_count; |
| 3785 | } |
| 3786 | |
| 3787 | static void |
| 3788 | dot_endp (dummy) |
| 3789 | int dummy ATTRIBUTE_UNUSED; |
| 3790 | { |
| 3791 | expressionS e; |
| 3792 | unsigned char *ptr; |
| 3793 | int bytes_per_address; |
| 3794 | long where; |
| 3795 | segT saved_seg; |
| 3796 | subsegT saved_subseg; |
| 3797 | const char *sec_name, *text_name; |
| 3798 | |
| 3799 | if (unwind.saved_text_seg) |
| 3800 | { |
| 3801 | saved_seg = unwind.saved_text_seg; |
| 3802 | saved_subseg = unwind.saved_text_subseg; |
| 3803 | unwind.saved_text_seg = NULL; |
| 3804 | } |
| 3805 | else |
| 3806 | { |
| 3807 | saved_seg = now_seg; |
| 3808 | saved_subseg = now_subseg; |
| 3809 | } |
| 3810 | |
| 3811 | /* |
| 3812 | Use a slightly ugly scheme to derive the unwind section names from |
| 3813 | the text section name: |
| 3814 | |
| 3815 | text sect. unwind table sect. |
| 3816 | name: name: comments: |
| 3817 | ---------- ----------------- -------------------------------- |
| 3818 | .text .IA_64.unwind |
| 3819 | .text.foo .IA_64.unwind.text.foo |
| 3820 | .foo .IA_64.unwind.foo |
| 3821 | _info .IA_64.unwind_info gas issues error message (ditto) |
| 3822 | _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) |
| 3823 | |
| 3824 | This mapping is done so that: |
| 3825 | |
| 3826 | (a) An object file with unwind info only in .text will use |
| 3827 | unwind section names .IA_64.unwind and .IA_64.unwind_info. |
| 3828 | This follows the letter of the ABI and also ensures backwards |
| 3829 | compatibility with older toolchains. |
| 3830 | |
| 3831 | (b) An object file with unwind info in multiple text sections |
| 3832 | will use separate unwind sections for each text section. |
| 3833 | This allows us to properly set the "sh_info" and "sh_link" |
| 3834 | fields in SHT_IA_64_UNWIND as required by the ABI and also |
| 3835 | lets GNU ld support programs with multiple segments |
| 3836 | containing unwind info (as might be the case for certain |
| 3837 | embedded applications). |
| 3838 | |
| 3839 | (c) An error is issued if there would be a name clash. |
| 3840 | */ |
| 3841 | text_name = segment_name (saved_seg); |
| 3842 | if (strncmp (text_name, "_info", 5) == 0) |
| 3843 | { |
| 3844 | as_bad ("Illegal section name `%s' (causes unwind section name clash)", |
| 3845 | text_name); |
| 3846 | ignore_rest_of_line (); |
| 3847 | return; |
| 3848 | } |
| 3849 | if (strcmp (text_name, ".text") == 0) |
| 3850 | text_name = ""; |
| 3851 | |
| 3852 | expression (&e); |
| 3853 | demand_empty_rest_of_line (); |
| 3854 | |
| 3855 | insn_group_break (1, 0, 0); |
| 3856 | |
| 3857 | /* If there wasn't a .handlerdata, we haven't generated an image yet. */ |
| 3858 | if (!unwind.info) |
| 3859 | generate_unwind_image (text_name); |
| 3860 | |
| 3861 | if (unwind.info || unwind.force_unwind_entry) |
| 3862 | { |
| 3863 | subseg_set (md.last_text_seg, 0); |
| 3864 | unwind.proc_end = expr_build_dot (); |
| 3865 | |
| 3866 | make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name); |
| 3867 | set_section ((char *) sec_name); |
| 3868 | bfd_set_section_flags (stdoutput, now_seg, |
| 3869 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); |
| 3870 | |
| 3871 | /* Make sure the section has 8 byte alignment. */ |
| 3872 | record_alignment (now_seg, 3); |
| 3873 | |
| 3874 | ptr = frag_more (24); |
| 3875 | where = frag_now_fix () - 24; |
| 3876 | bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; |
| 3877 | |
| 3878 | /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ |
| 3879 | e.X_op = O_pseudo_fixup; |
| 3880 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; |
| 3881 | e.X_add_number = 0; |
| 3882 | e.X_add_symbol = unwind.proc_start; |
| 3883 | ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); |
| 3884 | |
| 3885 | e.X_op = O_pseudo_fixup; |
| 3886 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; |
| 3887 | e.X_add_number = 0; |
| 3888 | e.X_add_symbol = unwind.proc_end; |
| 3889 | ia64_cons_fix_new (frag_now, where + bytes_per_address, |
| 3890 | bytes_per_address, &e); |
| 3891 | |
| 3892 | if (unwind.info) |
| 3893 | { |
| 3894 | e.X_op = O_pseudo_fixup; |
| 3895 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; |
| 3896 | e.X_add_number = 0; |
| 3897 | e.X_add_symbol = unwind.info; |
| 3898 | ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), |
| 3899 | bytes_per_address, &e); |
| 3900 | } |
| 3901 | else |
| 3902 | md_number_to_chars (ptr + (bytes_per_address * 2), 0, |
| 3903 | bytes_per_address); |
| 3904 | |
| 3905 | } |
| 3906 | subseg_set (saved_seg, saved_subseg); |
| 3907 | unwind.proc_start = unwind.proc_end = unwind.info = 0; |
| 3908 | } |
| 3909 | |
| 3910 | static void |
| 3911 | dot_template (template) |
| 3912 | int template; |
| 3913 | { |
| 3914 | CURR_SLOT.user_template = template; |
| 3915 | } |
| 3916 | |
| 3917 | static void |
| 3918 | dot_regstk (dummy) |
| 3919 | int dummy ATTRIBUTE_UNUSED; |
| 3920 | { |
| 3921 | int ins, locs, outs, rots; |
| 3922 | |
| 3923 | if (is_it_end_of_statement ()) |
| 3924 | ins = locs = outs = rots = 0; |
| 3925 | else |
| 3926 | { |
| 3927 | ins = get_absolute_expression (); |
| 3928 | if (*input_line_pointer++ != ',') |
| 3929 | goto err; |
| 3930 | locs = get_absolute_expression (); |
| 3931 | if (*input_line_pointer++ != ',') |
| 3932 | goto err; |
| 3933 | outs = get_absolute_expression (); |
| 3934 | if (*input_line_pointer++ != ',') |
| 3935 | goto err; |
| 3936 | rots = get_absolute_expression (); |
| 3937 | } |
| 3938 | set_regstack (ins, locs, outs, rots); |
| 3939 | return; |
| 3940 | |
| 3941 | err: |
| 3942 | as_bad ("Comma expected"); |
| 3943 | ignore_rest_of_line (); |
| 3944 | } |
| 3945 | |
| 3946 | static void |
| 3947 | dot_rot (type) |
| 3948 | int type; |
| 3949 | { |
| 3950 | unsigned num_regs, num_alloced = 0; |
| 3951 | struct dynreg **drpp, *dr; |
| 3952 | int ch, base_reg = 0; |
| 3953 | char *name, *start; |
| 3954 | size_t len; |
| 3955 | |
| 3956 | switch (type) |
| 3957 | { |
| 3958 | case DYNREG_GR: base_reg = REG_GR + 32; break; |
| 3959 | case DYNREG_FR: base_reg = REG_FR + 32; break; |
| 3960 | case DYNREG_PR: base_reg = REG_P + 16; break; |
| 3961 | default: break; |
| 3962 | } |
| 3963 | |
| 3964 | /* First, remove existing names from hash table. */ |
| 3965 | for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) |
| 3966 | { |
| 3967 | hash_delete (md.dynreg_hash, dr->name); |
| 3968 | dr->num_regs = 0; |
| 3969 | } |
| 3970 | |
| 3971 | drpp = &md.dynreg[type]; |
| 3972 | while (1) |
| 3973 | { |
| 3974 | start = input_line_pointer; |
| 3975 | ch = get_symbol_end (); |
| 3976 | *input_line_pointer = ch; |
| 3977 | len = (input_line_pointer - start); |
| 3978 | |
| 3979 | SKIP_WHITESPACE (); |
| 3980 | if (*input_line_pointer != '[') |
| 3981 | { |
| 3982 | as_bad ("Expected '['"); |
| 3983 | goto err; |
| 3984 | } |
| 3985 | ++input_line_pointer; /* skip '[' */ |
| 3986 | |
| 3987 | num_regs = get_absolute_expression (); |
| 3988 | |
| 3989 | if (*input_line_pointer++ != ']') |
| 3990 | { |
| 3991 | as_bad ("Expected ']'"); |
| 3992 | goto err; |
| 3993 | } |
| 3994 | SKIP_WHITESPACE (); |
| 3995 | |
| 3996 | num_alloced += num_regs; |
| 3997 | switch (type) |
| 3998 | { |
| 3999 | case DYNREG_GR: |
| 4000 | if (num_alloced > md.rot.num_regs) |
| 4001 | { |
| 4002 | as_bad ("Used more than the declared %d rotating registers", |
| 4003 | md.rot.num_regs); |
| 4004 | goto err; |
| 4005 | } |
| 4006 | break; |
| 4007 | case DYNREG_FR: |
| 4008 | if (num_alloced > 96) |
| 4009 | { |
| 4010 | as_bad ("Used more than the available 96 rotating registers"); |
| 4011 | goto err; |
| 4012 | } |
| 4013 | break; |
| 4014 | case DYNREG_PR: |
| 4015 | if (num_alloced > 48) |
| 4016 | { |
| 4017 | as_bad ("Used more than the available 48 rotating registers"); |
| 4018 | goto err; |
| 4019 | } |
| 4020 | break; |
| 4021 | |
| 4022 | default: |
| 4023 | break; |
| 4024 | } |
| 4025 | |
| 4026 | name = obstack_alloc (¬es, len + 1); |
| 4027 | memcpy (name, start, len); |
| 4028 | name[len] = '\0'; |
| 4029 | |
| 4030 | if (!*drpp) |
| 4031 | { |
| 4032 | *drpp = obstack_alloc (¬es, sizeof (*dr)); |
| 4033 | memset (*drpp, 0, sizeof (*dr)); |
| 4034 | } |
| 4035 | |
| 4036 | dr = *drpp; |
| 4037 | dr->name = name; |
| 4038 | dr->num_regs = num_regs; |
| 4039 | dr->base = base_reg; |
| 4040 | drpp = &dr->next; |
| 4041 | base_reg += num_regs; |
| 4042 | |
| 4043 | if (hash_insert (md.dynreg_hash, name, dr)) |
| 4044 | { |
| 4045 | as_bad ("Attempt to redefine register set `%s'", name); |
| 4046 | goto err; |
| 4047 | } |
| 4048 | |
| 4049 | if (*input_line_pointer != ',') |
| 4050 | break; |
| 4051 | ++input_line_pointer; /* skip comma */ |
| 4052 | SKIP_WHITESPACE (); |
| 4053 | } |
| 4054 | demand_empty_rest_of_line (); |
| 4055 | return; |
| 4056 | |
| 4057 | err: |
| 4058 | ignore_rest_of_line (); |
| 4059 | } |
| 4060 | |
| 4061 | static void |
| 4062 | dot_byteorder (byteorder) |
| 4063 | int byteorder; |
| 4064 | { |
| 4065 | target_big_endian = byteorder; |
| 4066 | } |
| 4067 | |
| 4068 | static void |
| 4069 | dot_psr (dummy) |
| 4070 | int dummy ATTRIBUTE_UNUSED; |
| 4071 | { |
| 4072 | char *option; |
| 4073 | int ch; |
| 4074 | |
| 4075 | while (1) |
| 4076 | { |
| 4077 | option = input_line_pointer; |
| 4078 | ch = get_symbol_end (); |
| 4079 | if (strcmp (option, "lsb") == 0) |
| 4080 | md.flags &= ~EF_IA_64_BE; |
| 4081 | else if (strcmp (option, "msb") == 0) |
| 4082 | md.flags |= EF_IA_64_BE; |
| 4083 | else if (strcmp (option, "abi32") == 0) |
| 4084 | md.flags &= ~EF_IA_64_ABI64; |
| 4085 | else if (strcmp (option, "abi64") == 0) |
| 4086 | md.flags |= EF_IA_64_ABI64; |
| 4087 | else |
| 4088 | as_bad ("Unknown psr option `%s'", option); |
| 4089 | *input_line_pointer = ch; |
| 4090 | |
| 4091 | SKIP_WHITESPACE (); |
| 4092 | if (*input_line_pointer != ',') |
| 4093 | break; |
| 4094 | |
| 4095 | ++input_line_pointer; |
| 4096 | SKIP_WHITESPACE (); |
| 4097 | } |
| 4098 | demand_empty_rest_of_line (); |
| 4099 | } |
| 4100 | |
| 4101 | static void |
| 4102 | dot_alias (dummy) |
| 4103 | int dummy ATTRIBUTE_UNUSED; |
| 4104 | { |
| 4105 | as_bad (".alias not implemented yet"); |
| 4106 | } |
| 4107 | |
| 4108 | static void |
| 4109 | dot_ln (dummy) |
| 4110 | int dummy ATTRIBUTE_UNUSED; |
| 4111 | { |
| 4112 | new_logical_line (0, get_absolute_expression ()); |
| 4113 | demand_empty_rest_of_line (); |
| 4114 | } |
| 4115 | |
| 4116 | static char * |
| 4117 | parse_section_name () |
| 4118 | { |
| 4119 | char *name; |
| 4120 | int len; |
| 4121 | |
| 4122 | SKIP_WHITESPACE (); |
| 4123 | if (*input_line_pointer != '"') |
| 4124 | { |
| 4125 | as_bad ("Missing section name"); |
| 4126 | ignore_rest_of_line (); |
| 4127 | return 0; |
| 4128 | } |
| 4129 | name = demand_copy_C_string (&len); |
| 4130 | if (!name) |
| 4131 | { |
| 4132 | ignore_rest_of_line (); |
| 4133 | return 0; |
| 4134 | } |
| 4135 | SKIP_WHITESPACE (); |
| 4136 | if (*input_line_pointer != ',') |
| 4137 | { |
| 4138 | as_bad ("Comma expected after section name"); |
| 4139 | ignore_rest_of_line (); |
| 4140 | return 0; |
| 4141 | } |
| 4142 | ++input_line_pointer; /* skip comma */ |
| 4143 | return name; |
| 4144 | } |
| 4145 | |
| 4146 | static void |
| 4147 | dot_xdata (size) |
| 4148 | int size; |
| 4149 | { |
| 4150 | char *name = parse_section_name (); |
| 4151 | if (!name) |
| 4152 | return; |
| 4153 | |
| 4154 | set_section (name); |
| 4155 | cons (size); |
| 4156 | obj_elf_previous (0); |
| 4157 | } |
| 4158 | |
| 4159 | /* Why doesn't float_cons() call md_cons_align() the way cons() does? */ |
| 4160 | |
| 4161 | static void |
| 4162 | stmt_float_cons (kind) |
| 4163 | int kind; |
| 4164 | { |
| 4165 | size_t size; |
| 4166 | |
| 4167 | switch (kind) |
| 4168 | { |
| 4169 | case 'd': size = 8; break; |
| 4170 | case 'x': size = 10; break; |
| 4171 | |
| 4172 | case 'f': |
| 4173 | default: |
| 4174 | size = 4; |
| 4175 | break; |
| 4176 | } |
| 4177 | ia64_do_align (size); |
| 4178 | float_cons (kind); |
| 4179 | } |
| 4180 | |
| 4181 | static void |
| 4182 | stmt_cons_ua (size) |
| 4183 | int size; |
| 4184 | { |
| 4185 | int saved_auto_align = md.auto_align; |
| 4186 | |
| 4187 | md.auto_align = 0; |
| 4188 | cons (size); |
| 4189 | md.auto_align = saved_auto_align; |
| 4190 | } |
| 4191 | |
| 4192 | static void |
| 4193 | dot_xfloat_cons (kind) |
| 4194 | int kind; |
| 4195 | { |
| 4196 | char *name = parse_section_name (); |
| 4197 | if (!name) |
| 4198 | return; |
| 4199 | |
| 4200 | set_section (name); |
| 4201 | stmt_float_cons (kind); |
| 4202 | obj_elf_previous (0); |
| 4203 | } |
| 4204 | |
| 4205 | static void |
| 4206 | dot_xstringer (zero) |
| 4207 | int zero; |
| 4208 | { |
| 4209 | char *name = parse_section_name (); |
| 4210 | if (!name) |
| 4211 | return; |
| 4212 | |
| 4213 | set_section (name); |
| 4214 | stringer (zero); |
| 4215 | obj_elf_previous (0); |
| 4216 | } |
| 4217 | |
| 4218 | static void |
| 4219 | dot_xdata_ua (size) |
| 4220 | int size; |
| 4221 | { |
| 4222 | int saved_auto_align = md.auto_align; |
| 4223 | char *name = parse_section_name (); |
| 4224 | if (!name) |
| 4225 | return; |
| 4226 | |
| 4227 | set_section (name); |
| 4228 | md.auto_align = 0; |
| 4229 | cons (size); |
| 4230 | md.auto_align = saved_auto_align; |
| 4231 | obj_elf_previous (0); |
| 4232 | } |
| 4233 | |
| 4234 | static void |
| 4235 | dot_xfloat_cons_ua (kind) |
| 4236 | int kind; |
| 4237 | { |
| 4238 | int saved_auto_align = md.auto_align; |
| 4239 | char *name = parse_section_name (); |
| 4240 | if (!name) |
| 4241 | return; |
| 4242 | |
| 4243 | set_section (name); |
| 4244 | md.auto_align = 0; |
| 4245 | stmt_float_cons (kind); |
| 4246 | md.auto_align = saved_auto_align; |
| 4247 | obj_elf_previous (0); |
| 4248 | } |
| 4249 | |
| 4250 | /* .reg.val <regname>,value */ |
| 4251 | |
| 4252 | static void |
| 4253 | dot_reg_val (dummy) |
| 4254 | int dummy ATTRIBUTE_UNUSED; |
| 4255 | { |
| 4256 | expressionS reg; |
| 4257 | |
| 4258 | expression (®); |
| 4259 | if (reg.X_op != O_register) |
| 4260 | { |
| 4261 | as_bad (_("Register name expected")); |
| 4262 | ignore_rest_of_line (); |
| 4263 | } |
| 4264 | else if (*input_line_pointer++ != ',') |
| 4265 | { |
| 4266 | as_bad (_("Comma expected")); |
| 4267 | ignore_rest_of_line (); |
| 4268 | } |
| 4269 | else |
| 4270 | { |
| 4271 | valueT value = get_absolute_expression (); |
| 4272 | int regno = reg.X_add_number; |
| 4273 | if (regno < REG_GR || regno > REG_GR + 128) |
| 4274 | as_warn (_("Register value annotation ignored")); |
| 4275 | else |
| 4276 | { |
| 4277 | gr_values[regno - REG_GR].known = 1; |
| 4278 | gr_values[regno - REG_GR].value = value; |
| 4279 | gr_values[regno - REG_GR].path = md.path; |
| 4280 | } |
| 4281 | } |
| 4282 | demand_empty_rest_of_line (); |
| 4283 | } |
| 4284 | |
| 4285 | /* select dv checking mode |
| 4286 | .auto |
| 4287 | .explicit |
| 4288 | .default |
| 4289 | |
| 4290 | A stop is inserted when changing modes |
| 4291 | */ |
| 4292 | |
| 4293 | static void |
| 4294 | dot_dv_mode (type) |
| 4295 | int type; |
| 4296 | { |
| 4297 | if (md.manual_bundling) |
| 4298 | as_warn (_("Directive invalid within a bundle")); |
| 4299 | |
| 4300 | if (type == 'E' || type == 'A') |
| 4301 | md.mode_explicitly_set = 0; |
| 4302 | else |
| 4303 | md.mode_explicitly_set = 1; |
| 4304 | |
| 4305 | md.detect_dv = 1; |
| 4306 | switch (type) |
| 4307 | { |
| 4308 | case 'A': |
| 4309 | case 'a': |
| 4310 | if (md.explicit_mode) |
| 4311 | insn_group_break (1, 0, 0); |
| 4312 | md.explicit_mode = 0; |
| 4313 | break; |
| 4314 | case 'E': |
| 4315 | case 'e': |
| 4316 | if (!md.explicit_mode) |
| 4317 | insn_group_break (1, 0, 0); |
| 4318 | md.explicit_mode = 1; |
| 4319 | break; |
| 4320 | default: |
| 4321 | case 'd': |
| 4322 | if (md.explicit_mode != md.default_explicit_mode) |
| 4323 | insn_group_break (1, 0, 0); |
| 4324 | md.explicit_mode = md.default_explicit_mode; |
| 4325 | md.mode_explicitly_set = 0; |
| 4326 | break; |
| 4327 | } |
| 4328 | } |
| 4329 | |
| 4330 | static void |
| 4331 | print_prmask (mask) |
| 4332 | valueT mask; |
| 4333 | { |
| 4334 | int regno; |
| 4335 | char *comma = ""; |
| 4336 | for (regno = 0; regno < 64; regno++) |
| 4337 | { |
| 4338 | if (mask & ((valueT) 1 << regno)) |
| 4339 | { |
| 4340 | fprintf (stderr, "%s p%d", comma, regno); |
| 4341 | comma = ","; |
| 4342 | } |
| 4343 | } |
| 4344 | } |
| 4345 | |
| 4346 | /* |
| 4347 | .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") |
| 4348 | .pred.rel.imply p1, p2 (also .pred.rel "imply") |
| 4349 | .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") |
| 4350 | .pred.safe_across_calls p1 [, p2 [,...]] |
| 4351 | */ |
| 4352 | |
| 4353 | static void |
| 4354 | dot_pred_rel (type) |
| 4355 | int type; |
| 4356 | { |
| 4357 | valueT mask = 0; |
| 4358 | int count = 0; |
| 4359 | int p1 = -1, p2 = -1; |
| 4360 | |
| 4361 | if (type == 0) |
| 4362 | { |
| 4363 | if (*input_line_pointer != '"') |
| 4364 | { |
| 4365 | as_bad (_("Missing predicate relation type")); |
| 4366 | ignore_rest_of_line (); |
| 4367 | return; |
| 4368 | } |
| 4369 | else |
| 4370 | { |
| 4371 | int len; |
| 4372 | char *form = demand_copy_C_string (&len); |
| 4373 | if (strcmp (form, "mutex") == 0) |
| 4374 | type = 'm'; |
| 4375 | else if (strcmp (form, "clear") == 0) |
| 4376 | type = 'c'; |
| 4377 | else if (strcmp (form, "imply") == 0) |
| 4378 | type = 'i'; |
| 4379 | else |
| 4380 | { |
| 4381 | as_bad (_("Unrecognized predicate relation type")); |
| 4382 | ignore_rest_of_line (); |
| 4383 | return; |
| 4384 | } |
| 4385 | } |
| 4386 | if (*input_line_pointer == ',') |
| 4387 | ++input_line_pointer; |
| 4388 | SKIP_WHITESPACE (); |
| 4389 | } |
| 4390 | |
| 4391 | SKIP_WHITESPACE (); |
| 4392 | while (1) |
| 4393 | { |
| 4394 | valueT bit = 1; |
| 4395 | int regno; |
| 4396 | |
| 4397 | if (toupper (*input_line_pointer) != 'P' |
| 4398 | || (regno = atoi (++input_line_pointer)) < 0 |
| 4399 | || regno > 63) |
| 4400 | { |
| 4401 | as_bad (_("Predicate register expected")); |
| 4402 | ignore_rest_of_line (); |
| 4403 | return; |
| 4404 | } |
| 4405 | while (isdigit (*input_line_pointer)) |
| 4406 | ++input_line_pointer; |
| 4407 | if (p1 == -1) |
| 4408 | p1 = regno; |
| 4409 | else if (p2 == -1) |
| 4410 | p2 = regno; |
| 4411 | bit <<= regno; |
| 4412 | if (mask & bit) |
| 4413 | as_warn (_("Duplicate predicate register ignored")); |
| 4414 | mask |= bit; |
| 4415 | count++; |
| 4416 | /* See if it's a range. */ |
| 4417 | if (*input_line_pointer == '-') |
| 4418 | { |
| 4419 | valueT stop = 1; |
| 4420 | ++input_line_pointer; |
| 4421 | |
| 4422 | if (toupper (*input_line_pointer) != 'P' |
| 4423 | || (regno = atoi (++input_line_pointer)) < 0 |
| 4424 | || regno > 63) |
| 4425 | { |
| 4426 | as_bad (_("Predicate register expected")); |
| 4427 | ignore_rest_of_line (); |
| 4428 | return; |
| 4429 | } |
| 4430 | while (isdigit (*input_line_pointer)) |
| 4431 | ++input_line_pointer; |
| 4432 | stop <<= regno; |
| 4433 | if (bit >= stop) |
| 4434 | { |
| 4435 | as_bad (_("Bad register range")); |
| 4436 | ignore_rest_of_line (); |
| 4437 | return; |
| 4438 | } |
| 4439 | while (bit < stop) |
| 4440 | { |
| 4441 | bit <<= 1; |
| 4442 | mask |= bit; |
| 4443 | count++; |
| 4444 | } |
| 4445 | SKIP_WHITESPACE (); |
| 4446 | } |
| 4447 | if (*input_line_pointer != ',') |
| 4448 | break; |
| 4449 | ++input_line_pointer; |
| 4450 | SKIP_WHITESPACE (); |
| 4451 | } |
| 4452 | |
| 4453 | switch (type) |
| 4454 | { |
| 4455 | case 'c': |
| 4456 | if (count == 0) |
| 4457 | mask = ~(valueT) 0; |
| 4458 | clear_qp_mutex (mask); |
| 4459 | clear_qp_implies (mask, (valueT) 0); |
| 4460 | break; |
| 4461 | case 'i': |
| 4462 | if (count != 2 || p1 == -1 || p2 == -1) |
| 4463 | as_bad (_("Predicate source and target required")); |
| 4464 | else if (p1 == 0 || p2 == 0) |
| 4465 | as_bad (_("Use of p0 is not valid in this context")); |
| 4466 | else |
| 4467 | add_qp_imply (p1, p2); |
| 4468 | break; |
| 4469 | case 'm': |
| 4470 | if (count < 2) |
| 4471 | { |
| 4472 | as_bad (_("At least two PR arguments expected")); |
| 4473 | break; |
| 4474 | } |
| 4475 | else if (mask & 1) |
| 4476 | { |
| 4477 | as_bad (_("Use of p0 is not valid in this context")); |
| 4478 | break; |
| 4479 | } |
| 4480 | add_qp_mutex (mask); |
| 4481 | break; |
| 4482 | case 's': |
| 4483 | /* note that we don't override any existing relations */ |
| 4484 | if (count == 0) |
| 4485 | { |
| 4486 | as_bad (_("At least one PR argument expected")); |
| 4487 | break; |
| 4488 | } |
| 4489 | if (md.debug_dv) |
| 4490 | { |
| 4491 | fprintf (stderr, "Safe across calls: "); |
| 4492 | print_prmask (mask); |
| 4493 | fprintf (stderr, "\n"); |
| 4494 | } |
| 4495 | qp_safe_across_calls = mask; |
| 4496 | break; |
| 4497 | } |
| 4498 | demand_empty_rest_of_line (); |
| 4499 | } |
| 4500 | |
| 4501 | /* .entry label [, label [, ...]] |
| 4502 | Hint to DV code that the given labels are to be considered entry points. |
| 4503 | Otherwise, only global labels are considered entry points. */ |
| 4504 | |
| 4505 | static void |
| 4506 | dot_entry (dummy) |
| 4507 | int dummy ATTRIBUTE_UNUSED; |
| 4508 | { |
| 4509 | const char *err; |
| 4510 | char *name; |
| 4511 | int c; |
| 4512 | symbolS *symbolP; |
| 4513 | |
| 4514 | do |
| 4515 | { |
| 4516 | name = input_line_pointer; |
| 4517 | c = get_symbol_end (); |
| 4518 | symbolP = symbol_find_or_make (name); |
| 4519 | |
| 4520 | err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); |
| 4521 | if (err) |
| 4522 | as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), |
| 4523 | name, err); |
| 4524 | |
| 4525 | *input_line_pointer = c; |
| 4526 | SKIP_WHITESPACE (); |
| 4527 | c = *input_line_pointer; |
| 4528 | if (c == ',') |
| 4529 | { |
| 4530 | input_line_pointer++; |
| 4531 | SKIP_WHITESPACE (); |
| 4532 | if (*input_line_pointer == '\n') |
| 4533 | c = '\n'; |
| 4534 | } |
| 4535 | } |
| 4536 | while (c == ','); |
| 4537 | |
| 4538 | demand_empty_rest_of_line (); |
| 4539 | } |
| 4540 | |
| 4541 | /* .mem.offset offset, base |
| 4542 | "base" is used to distinguish between offsets from a different base. */ |
| 4543 | |
| 4544 | static void |
| 4545 | dot_mem_offset (dummy) |
| 4546 | int dummy ATTRIBUTE_UNUSED; |
| 4547 | { |
| 4548 | md.mem_offset.hint = 1; |
| 4549 | md.mem_offset.offset = get_absolute_expression (); |
| 4550 | if (*input_line_pointer != ',') |
| 4551 | { |
| 4552 | as_bad (_("Comma expected")); |
| 4553 | ignore_rest_of_line (); |
| 4554 | return; |
| 4555 | } |
| 4556 | ++input_line_pointer; |
| 4557 | md.mem_offset.base = get_absolute_expression (); |
| 4558 | demand_empty_rest_of_line (); |
| 4559 | } |
| 4560 | |
| 4561 | /* ia64-specific pseudo-ops: */ |
| 4562 | const pseudo_typeS md_pseudo_table[] = |
| 4563 | { |
| 4564 | { "radix", dot_radix, 0 }, |
| 4565 | { "lcomm", s_lcomm_bytes, 1 }, |
| 4566 | { "bss", dot_special_section, SPECIAL_SECTION_BSS }, |
| 4567 | { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, |
| 4568 | { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, |
| 4569 | { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, |
| 4570 | { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, |
| 4571 | { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, |
| 4572 | { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, |
| 4573 | { "proc", dot_proc, 0 }, |
| 4574 | { "body", dot_body, 0 }, |
| 4575 | { "prologue", dot_prologue, 0 }, |
| 4576 | { "endp", dot_endp, 0 }, |
| 4577 | { "file", dwarf2_directive_file, 0 }, |
| 4578 | { "loc", dwarf2_directive_loc, 0 }, |
| 4579 | |
| 4580 | { "fframe", dot_fframe, 0 }, |
| 4581 | { "vframe", dot_vframe, 0 }, |
| 4582 | { "vframesp", dot_vframesp, 0 }, |
| 4583 | { "vframepsp", dot_vframepsp, 0 }, |
| 4584 | { "save", dot_save, 0 }, |
| 4585 | { "restore", dot_restore, 0 }, |
| 4586 | { "restorereg", dot_restorereg, 0 }, |
| 4587 | { "restorereg.p", dot_restorereg_p, 0 }, |
| 4588 | { "handlerdata", dot_handlerdata, 0 }, |
| 4589 | { "unwentry", dot_unwentry, 0 }, |
| 4590 | { "altrp", dot_altrp, 0 }, |
| 4591 | { "savesp", dot_savemem, 0 }, |
| 4592 | { "savepsp", dot_savemem, 1 }, |
| 4593 | { "save.g", dot_saveg, 0 }, |
| 4594 | { "save.f", dot_savef, 0 }, |
| 4595 | { "save.b", dot_saveb, 0 }, |
| 4596 | { "save.gf", dot_savegf, 0 }, |
| 4597 | { "spill", dot_spill, 0 }, |
| 4598 | { "spillreg", dot_spillreg, 0 }, |
| 4599 | { "spillsp", dot_spillmem, 0 }, |
| 4600 | { "spillpsp", dot_spillmem, 1 }, |
| 4601 | { "spillreg.p", dot_spillreg_p, 0 }, |
| 4602 | { "spillsp.p", dot_spillmem_p, 0 }, |
| 4603 | { "spillpsp.p", dot_spillmem_p, 1 }, |
| 4604 | { "label_state", dot_label_state, 0 }, |
| 4605 | { "copy_state", dot_copy_state, 0 }, |
| 4606 | { "unwabi", dot_unwabi, 0 }, |
| 4607 | { "personality", dot_personality, 0 }, |
| 4608 | #if 0 |
| 4609 | { "estate", dot_estate, 0 }, |
| 4610 | #endif |
| 4611 | { "mii", dot_template, 0x0 }, |
| 4612 | { "mli", dot_template, 0x2 }, /* old format, for compatibility */ |
| 4613 | { "mlx", dot_template, 0x2 }, |
| 4614 | { "mmi", dot_template, 0x4 }, |
| 4615 | { "mfi", dot_template, 0x6 }, |
| 4616 | { "mmf", dot_template, 0x7 }, |
| 4617 | { "mib", dot_template, 0x8 }, |
| 4618 | { "mbb", dot_template, 0x9 }, |
| 4619 | { "bbb", dot_template, 0xb }, |
| 4620 | { "mmb", dot_template, 0xc }, |
| 4621 | { "mfb", dot_template, 0xe }, |
| 4622 | #if 0 |
| 4623 | { "lb", dot_scope, 0 }, |
| 4624 | { "le", dot_scope, 1 }, |
| 4625 | #endif |
| 4626 | { "align", s_align_bytes, 0 }, |
| 4627 | { "regstk", dot_regstk, 0 }, |
| 4628 | { "rotr", dot_rot, DYNREG_GR }, |
| 4629 | { "rotf", dot_rot, DYNREG_FR }, |
| 4630 | { "rotp", dot_rot, DYNREG_PR }, |
| 4631 | { "lsb", dot_byteorder, 0 }, |
| 4632 | { "msb", dot_byteorder, 1 }, |
| 4633 | { "psr", dot_psr, 0 }, |
| 4634 | { "alias", dot_alias, 0 }, |
| 4635 | { "ln", dot_ln, 0 }, /* source line info (for debugging) */ |
| 4636 | |
| 4637 | { "xdata1", dot_xdata, 1 }, |
| 4638 | { "xdata2", dot_xdata, 2 }, |
| 4639 | { "xdata4", dot_xdata, 4 }, |
| 4640 | { "xdata8", dot_xdata, 8 }, |
| 4641 | { "xreal4", dot_xfloat_cons, 'f' }, |
| 4642 | { "xreal8", dot_xfloat_cons, 'd' }, |
| 4643 | { "xreal10", dot_xfloat_cons, 'x' }, |
| 4644 | { "xstring", dot_xstringer, 0 }, |
| 4645 | { "xstringz", dot_xstringer, 1 }, |
| 4646 | |
| 4647 | /* unaligned versions: */ |
| 4648 | { "xdata2.ua", dot_xdata_ua, 2 }, |
| 4649 | { "xdata4.ua", dot_xdata_ua, 4 }, |
| 4650 | { "xdata8.ua", dot_xdata_ua, 8 }, |
| 4651 | { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, |
| 4652 | { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, |
| 4653 | { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, |
| 4654 | |
| 4655 | /* annotations/DV checking support */ |
| 4656 | { "entry", dot_entry, 0 }, |
| 4657 | { "mem.offset", dot_mem_offset, 0 }, |
| 4658 | { "pred.rel", dot_pred_rel, 0 }, |
| 4659 | { "pred.rel.clear", dot_pred_rel, 'c' }, |
| 4660 | { "pred.rel.imply", dot_pred_rel, 'i' }, |
| 4661 | { "pred.rel.mutex", dot_pred_rel, 'm' }, |
| 4662 | { "pred.safe_across_calls", dot_pred_rel, 's' }, |
| 4663 | { "reg.val", dot_reg_val, 0 }, |
| 4664 | { "auto", dot_dv_mode, 'a' }, |
| 4665 | { "explicit", dot_dv_mode, 'e' }, |
| 4666 | { "default", dot_dv_mode, 'd' }, |
| 4667 | |
| 4668 | { NULL, 0, 0 } |
| 4669 | }; |
| 4670 | |
| 4671 | static const struct pseudo_opcode |
| 4672 | { |
| 4673 | const char *name; |
| 4674 | void (*handler) (int); |
| 4675 | int arg; |
| 4676 | } |
| 4677 | pseudo_opcode[] = |
| 4678 | { |
| 4679 | /* these are more like pseudo-ops, but don't start with a dot */ |
| 4680 | { "data1", cons, 1 }, |
| 4681 | { "data2", cons, 2 }, |
| 4682 | { "data4", cons, 4 }, |
| 4683 | { "data8", cons, 8 }, |
| 4684 | { "real4", stmt_float_cons, 'f' }, |
| 4685 | { "real8", stmt_float_cons, 'd' }, |
| 4686 | { "real10", stmt_float_cons, 'x' }, |
| 4687 | { "string", stringer, 0 }, |
| 4688 | { "stringz", stringer, 1 }, |
| 4689 | |
| 4690 | /* unaligned versions: */ |
| 4691 | { "data2.ua", stmt_cons_ua, 2 }, |
| 4692 | { "data4.ua", stmt_cons_ua, 4 }, |
| 4693 | { "data8.ua", stmt_cons_ua, 8 }, |
| 4694 | { "real4.ua", float_cons, 'f' }, |
| 4695 | { "real8.ua", float_cons, 'd' }, |
| 4696 | { "real10.ua", float_cons, 'x' }, |
| 4697 | }; |
| 4698 | |
| 4699 | /* Declare a register by creating a symbol for it and entering it in |
| 4700 | the symbol table. */ |
| 4701 | |
| 4702 | static symbolS * |
| 4703 | declare_register (name, regnum) |
| 4704 | const char *name; |
| 4705 | int regnum; |
| 4706 | { |
| 4707 | const char *err; |
| 4708 | symbolS *sym; |
| 4709 | |
| 4710 | sym = symbol_new (name, reg_section, regnum, &zero_address_frag); |
| 4711 | |
| 4712 | err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); |
| 4713 | if (err) |
| 4714 | as_fatal ("Inserting \"%s\" into register table failed: %s", |
| 4715 | name, err); |
| 4716 | |
| 4717 | return sym; |
| 4718 | } |
| 4719 | |
| 4720 | static void |
| 4721 | declare_register_set (prefix, num_regs, base_regnum) |
| 4722 | const char *prefix; |
| 4723 | int num_regs; |
| 4724 | int base_regnum; |
| 4725 | { |
| 4726 | char name[8]; |
| 4727 | int i; |
| 4728 | |
| 4729 | for (i = 0; i < num_regs; ++i) |
| 4730 | { |
| 4731 | sprintf (name, "%s%u", prefix, i); |
| 4732 | declare_register (name, base_regnum + i); |
| 4733 | } |
| 4734 | } |
| 4735 | |
| 4736 | static unsigned int |
| 4737 | operand_width (opnd) |
| 4738 | enum ia64_opnd opnd; |
| 4739 | { |
| 4740 | const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; |
| 4741 | unsigned int bits = 0; |
| 4742 | int i; |
| 4743 | |
| 4744 | bits = 0; |
| 4745 | for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) |
| 4746 | bits += odesc->field[i].bits; |
| 4747 | |
| 4748 | return bits; |
| 4749 | } |
| 4750 | |
| 4751 | static enum operand_match_result |
| 4752 | operand_match (idesc, index, e) |
| 4753 | const struct ia64_opcode *idesc; |
| 4754 | int index; |
| 4755 | expressionS *e; |
| 4756 | { |
| 4757 | enum ia64_opnd opnd = idesc->operands[index]; |
| 4758 | int bits, relocatable = 0; |
| 4759 | struct insn_fix *fix; |
| 4760 | bfd_signed_vma val; |
| 4761 | |
| 4762 | switch (opnd) |
| 4763 | { |
| 4764 | /* constants: */ |
| 4765 | |
| 4766 | case IA64_OPND_AR_CCV: |
| 4767 | if (e->X_op == O_register && e->X_add_number == REG_AR + 32) |
| 4768 | return OPERAND_MATCH; |
| 4769 | break; |
| 4770 | |
| 4771 | case IA64_OPND_AR_PFS: |
| 4772 | if (e->X_op == O_register && e->X_add_number == REG_AR + 64) |
| 4773 | return OPERAND_MATCH; |
| 4774 | break; |
| 4775 | |
| 4776 | case IA64_OPND_GR0: |
| 4777 | if (e->X_op == O_register && e->X_add_number == REG_GR + 0) |
| 4778 | return OPERAND_MATCH; |
| 4779 | break; |
| 4780 | |
| 4781 | case IA64_OPND_IP: |
| 4782 | if (e->X_op == O_register && e->X_add_number == REG_IP) |
| 4783 | return OPERAND_MATCH; |
| 4784 | break; |
| 4785 | |
| 4786 | case IA64_OPND_PR: |
| 4787 | if (e->X_op == O_register && e->X_add_number == REG_PR) |
| 4788 | return OPERAND_MATCH; |
| 4789 | break; |
| 4790 | |
| 4791 | case IA64_OPND_PR_ROT: |
| 4792 | if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) |
| 4793 | return OPERAND_MATCH; |
| 4794 | break; |
| 4795 | |
| 4796 | case IA64_OPND_PSR: |
| 4797 | if (e->X_op == O_register && e->X_add_number == REG_PSR) |
| 4798 | return OPERAND_MATCH; |
| 4799 | break; |
| 4800 | |
| 4801 | case IA64_OPND_PSR_L: |
| 4802 | if (e->X_op == O_register && e->X_add_number == REG_PSR_L) |
| 4803 | return OPERAND_MATCH; |
| 4804 | break; |
| 4805 | |
| 4806 | case IA64_OPND_PSR_UM: |
| 4807 | if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) |
| 4808 | return OPERAND_MATCH; |
| 4809 | break; |
| 4810 | |
| 4811 | case IA64_OPND_C1: |
| 4812 | if (e->X_op == O_constant) |
| 4813 | { |
| 4814 | if (e->X_add_number == 1) |
| 4815 | return OPERAND_MATCH; |
| 4816 | else |
| 4817 | return OPERAND_OUT_OF_RANGE; |
| 4818 | } |
| 4819 | break; |
| 4820 | |
| 4821 | case IA64_OPND_C8: |
| 4822 | if (e->X_op == O_constant) |
| 4823 | { |
| 4824 | if (e->X_add_number == 8) |
| 4825 | return OPERAND_MATCH; |
| 4826 | else |
| 4827 | return OPERAND_OUT_OF_RANGE; |
| 4828 | } |
| 4829 | break; |
| 4830 | |
| 4831 | case IA64_OPND_C16: |
| 4832 | if (e->X_op == O_constant) |
| 4833 | { |
| 4834 | if (e->X_add_number == 16) |
| 4835 | return OPERAND_MATCH; |
| 4836 | else |
| 4837 | return OPERAND_OUT_OF_RANGE; |
| 4838 | } |
| 4839 | break; |
| 4840 | |
| 4841 | /* register operands: */ |
| 4842 | |
| 4843 | case IA64_OPND_AR3: |
| 4844 | if (e->X_op == O_register && e->X_add_number >= REG_AR |
| 4845 | && e->X_add_number < REG_AR + 128) |
| 4846 | return OPERAND_MATCH; |
| 4847 | break; |
| 4848 | |
| 4849 | case IA64_OPND_B1: |
| 4850 | case IA64_OPND_B2: |
| 4851 | if (e->X_op == O_register && e->X_add_number >= REG_BR |
| 4852 | && e->X_add_number < REG_BR + 8) |
| 4853 | return OPERAND_MATCH; |
| 4854 | break; |
| 4855 | |
| 4856 | case IA64_OPND_CR3: |
| 4857 | if (e->X_op == O_register && e->X_add_number >= REG_CR |
| 4858 | && e->X_add_number < REG_CR + 128) |
| 4859 | return OPERAND_MATCH; |
| 4860 | break; |
| 4861 | |
| 4862 | case IA64_OPND_F1: |
| 4863 | case IA64_OPND_F2: |
| 4864 | case IA64_OPND_F3: |
| 4865 | case IA64_OPND_F4: |
| 4866 | if (e->X_op == O_register && e->X_add_number >= REG_FR |
| 4867 | && e->X_add_number < REG_FR + 128) |
| 4868 | return OPERAND_MATCH; |
| 4869 | break; |
| 4870 | |
| 4871 | case IA64_OPND_P1: |
| 4872 | case IA64_OPND_P2: |
| 4873 | if (e->X_op == O_register && e->X_add_number >= REG_P |
| 4874 | && e->X_add_number < REG_P + 64) |
| 4875 | return OPERAND_MATCH; |
| 4876 | break; |
| 4877 | |
| 4878 | case IA64_OPND_R1: |
| 4879 | case IA64_OPND_R2: |
| 4880 | case IA64_OPND_R3: |
| 4881 | if (e->X_op == O_register && e->X_add_number >= REG_GR |
| 4882 | && e->X_add_number < REG_GR + 128) |
| 4883 | return OPERAND_MATCH; |
| 4884 | break; |
| 4885 | |
| 4886 | case IA64_OPND_R3_2: |
| 4887 | if (e->X_op == O_register && e->X_add_number >= REG_GR) |
| 4888 | { |
| 4889 | if (e->X_add_number < REG_GR + 4) |
| 4890 | return OPERAND_MATCH; |
| 4891 | else if (e->X_add_number < REG_GR + 128) |
| 4892 | return OPERAND_OUT_OF_RANGE; |
| 4893 | } |
| 4894 | break; |
| 4895 | |
| 4896 | /* indirect operands: */ |
| 4897 | case IA64_OPND_CPUID_R3: |
| 4898 | case IA64_OPND_DBR_R3: |
| 4899 | case IA64_OPND_DTR_R3: |
| 4900 | case IA64_OPND_ITR_R3: |
| 4901 | case IA64_OPND_IBR_R3: |
| 4902 | case IA64_OPND_MSR_R3: |
| 4903 | case IA64_OPND_PKR_R3: |
| 4904 | case IA64_OPND_PMC_R3: |
| 4905 | case IA64_OPND_PMD_R3: |
| 4906 | case IA64_OPND_RR_R3: |
| 4907 | if (e->X_op == O_index && e->X_op_symbol |
| 4908 | && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID |
| 4909 | == opnd - IA64_OPND_CPUID_R3)) |
| 4910 | return OPERAND_MATCH; |
| 4911 | break; |
| 4912 | |
| 4913 | case IA64_OPND_MR3: |
| 4914 | if (e->X_op == O_index && !e->X_op_symbol) |
| 4915 | return OPERAND_MATCH; |
| 4916 | break; |
| 4917 | |
| 4918 | /* immediate operands: */ |
| 4919 | case IA64_OPND_CNT2a: |
| 4920 | case IA64_OPND_LEN4: |
| 4921 | case IA64_OPND_LEN6: |
| 4922 | bits = operand_width (idesc->operands[index]); |
| 4923 | if (e->X_op == O_constant) |
| 4924 | { |
| 4925 | if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) |
| 4926 | return OPERAND_MATCH; |
| 4927 | else |
| 4928 | return OPERAND_OUT_OF_RANGE; |
| 4929 | } |
| 4930 | break; |
| 4931 | |
| 4932 | case IA64_OPND_CNT2b: |
| 4933 | if (e->X_op == O_constant) |
| 4934 | { |
| 4935 | if ((bfd_vma) (e->X_add_number - 1) < 3) |
| 4936 | return OPERAND_MATCH; |
| 4937 | else |
| 4938 | return OPERAND_OUT_OF_RANGE; |
| 4939 | } |
| 4940 | break; |
| 4941 | |
| 4942 | case IA64_OPND_CNT2c: |
| 4943 | val = e->X_add_number; |
| 4944 | if (e->X_op == O_constant) |
| 4945 | { |
| 4946 | if ((val == 0 || val == 7 || val == 15 || val == 16)) |
| 4947 | return OPERAND_MATCH; |
| 4948 | else |
| 4949 | return OPERAND_OUT_OF_RANGE; |
| 4950 | } |
| 4951 | break; |
| 4952 | |
| 4953 | case IA64_OPND_SOR: |
| 4954 | /* SOR must be an integer multiple of 8 */ |
| 4955 | if (e->X_op == O_constant && e->X_add_number & 0x7) |
| 4956 | return OPERAND_OUT_OF_RANGE; |
| 4957 | case IA64_OPND_SOF: |
| 4958 | case IA64_OPND_SOL: |
| 4959 | if (e->X_op == O_constant) |
| 4960 | { |
| 4961 | if ((bfd_vma) e->X_add_number <= 96) |
| 4962 | return OPERAND_MATCH; |
| 4963 | else |
| 4964 | return OPERAND_OUT_OF_RANGE; |
| 4965 | } |
| 4966 | break; |
| 4967 | |
| 4968 | case IA64_OPND_IMMU62: |
| 4969 | if (e->X_op == O_constant) |
| 4970 | { |
| 4971 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) |
| 4972 | return OPERAND_MATCH; |
| 4973 | else |
| 4974 | return OPERAND_OUT_OF_RANGE; |
| 4975 | } |
| 4976 | else |
| 4977 | { |
| 4978 | /* FIXME -- need 62-bit relocation type */ |
| 4979 | as_bad (_("62-bit relocation not yet implemented")); |
| 4980 | } |
| 4981 | break; |
| 4982 | |
| 4983 | case IA64_OPND_IMMU64: |
| 4984 | if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup |
| 4985 | || e->X_op == O_subtract) |
| 4986 | { |
| 4987 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; |
| 4988 | fix->code = BFD_RELOC_IA64_IMM64; |
| 4989 | if (e->X_op != O_subtract) |
| 4990 | { |
| 4991 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
| 4992 | if (e->X_op == O_pseudo_fixup) |
| 4993 | e->X_op = O_symbol; |
| 4994 | } |
| 4995 | |
| 4996 | fix->opnd = idesc->operands[index]; |
| 4997 | fix->expr = *e; |
| 4998 | fix->is_pcrel = 0; |
| 4999 | ++CURR_SLOT.num_fixups; |
| 5000 | return OPERAND_MATCH; |
| 5001 | } |
| 5002 | else if (e->X_op == O_constant) |
| 5003 | return OPERAND_MATCH; |
| 5004 | break; |
| 5005 | |
| 5006 | case IA64_OPND_CCNT5: |
| 5007 | case IA64_OPND_CNT5: |
| 5008 | case IA64_OPND_CNT6: |
| 5009 | case IA64_OPND_CPOS6a: |
| 5010 | case IA64_OPND_CPOS6b: |
| 5011 | case IA64_OPND_CPOS6c: |
| 5012 | case IA64_OPND_IMMU2: |
| 5013 | case IA64_OPND_IMMU7a: |
| 5014 | case IA64_OPND_IMMU7b: |
| 5015 | case IA64_OPND_IMMU21: |
| 5016 | case IA64_OPND_IMMU24: |
| 5017 | case IA64_OPND_MBTYPE4: |
| 5018 | case IA64_OPND_MHTYPE8: |
| 5019 | case IA64_OPND_POS6: |
| 5020 | bits = operand_width (idesc->operands[index]); |
| 5021 | if (e->X_op == O_constant) |
| 5022 | { |
| 5023 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) |
| 5024 | return OPERAND_MATCH; |
| 5025 | else |
| 5026 | return OPERAND_OUT_OF_RANGE; |
| 5027 | } |
| 5028 | break; |
| 5029 | |
| 5030 | case IA64_OPND_IMMU9: |
| 5031 | bits = operand_width (idesc->operands[index]); |
| 5032 | if (e->X_op == O_constant) |
| 5033 | { |
| 5034 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) |
| 5035 | { |
| 5036 | int lobits = e->X_add_number & 0x3; |
| 5037 | if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) |
| 5038 | e->X_add_number |= (bfd_vma) 0x3; |
| 5039 | return OPERAND_MATCH; |
| 5040 | } |
| 5041 | else |
| 5042 | return OPERAND_OUT_OF_RANGE; |
| 5043 | } |
| 5044 | break; |
| 5045 | |
| 5046 | case IA64_OPND_IMM44: |
| 5047 | /* least 16 bits must be zero */ |
| 5048 | if ((e->X_add_number & 0xffff) != 0) |
| 5049 | /* XXX technically, this is wrong: we should not be issuing warning |
| 5050 | messages until we're sure this instruction pattern is going to |
| 5051 | be used! */ |
| 5052 | as_warn (_("lower 16 bits of mask ignored")); |
| 5053 | |
| 5054 | if (e->X_op == O_constant) |
| 5055 | { |
| 5056 | if (((e->X_add_number >= 0 |
| 5057 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) |
| 5058 | || (e->X_add_number < 0 |
| 5059 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) |
| 5060 | { |
| 5061 | /* sign-extend */ |
| 5062 | if (e->X_add_number >= 0 |
| 5063 | && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) |
| 5064 | { |
| 5065 | e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); |
| 5066 | } |
| 5067 | return OPERAND_MATCH; |
| 5068 | } |
| 5069 | else |
| 5070 | return OPERAND_OUT_OF_RANGE; |
| 5071 | } |
| 5072 | break; |
| 5073 | |
| 5074 | case IA64_OPND_IMM17: |
| 5075 | /* bit 0 is a don't care (pr0 is hardwired to 1) */ |
| 5076 | if (e->X_op == O_constant) |
| 5077 | { |
| 5078 | if (((e->X_add_number >= 0 |
| 5079 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) |
| 5080 | || (e->X_add_number < 0 |
| 5081 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) |
| 5082 | { |
| 5083 | /* sign-extend */ |
| 5084 | if (e->X_add_number >= 0 |
| 5085 | && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) |
| 5086 | { |
| 5087 | e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); |
| 5088 | } |
| 5089 | return OPERAND_MATCH; |
| 5090 | } |
| 5091 | else |
| 5092 | return OPERAND_OUT_OF_RANGE; |
| 5093 | } |
| 5094 | break; |
| 5095 | |
| 5096 | case IA64_OPND_IMM14: |
| 5097 | case IA64_OPND_IMM22: |
| 5098 | relocatable = 1; |
| 5099 | case IA64_OPND_IMM1: |
| 5100 | case IA64_OPND_IMM8: |
| 5101 | case IA64_OPND_IMM8U4: |
| 5102 | case IA64_OPND_IMM8M1: |
| 5103 | case IA64_OPND_IMM8M1U4: |
| 5104 | case IA64_OPND_IMM8M1U8: |
| 5105 | case IA64_OPND_IMM9a: |
| 5106 | case IA64_OPND_IMM9b: |
| 5107 | bits = operand_width (idesc->operands[index]); |
| 5108 | if (relocatable && (e->X_op == O_symbol |
| 5109 | || e->X_op == O_subtract |
| 5110 | || e->X_op == O_pseudo_fixup)) |
| 5111 | { |
| 5112 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; |
| 5113 | |
| 5114 | if (idesc->operands[index] == IA64_OPND_IMM14) |
| 5115 | fix->code = BFD_RELOC_IA64_IMM14; |
| 5116 | else |
| 5117 | fix->code = BFD_RELOC_IA64_IMM22; |
| 5118 | |
| 5119 | if (e->X_op != O_subtract) |
| 5120 | { |
| 5121 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
| 5122 | if (e->X_op == O_pseudo_fixup) |
| 5123 | e->X_op = O_symbol; |
| 5124 | } |
| 5125 | |
| 5126 | fix->opnd = idesc->operands[index]; |
| 5127 | fix->expr = *e; |
| 5128 | fix->is_pcrel = 0; |
| 5129 | ++CURR_SLOT.num_fixups; |
| 5130 | return OPERAND_MATCH; |
| 5131 | } |
| 5132 | else if (e->X_op != O_constant |
| 5133 | && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) |
| 5134 | return OPERAND_MISMATCH; |
| 5135 | |
| 5136 | if (opnd == IA64_OPND_IMM8M1U4) |
| 5137 | { |
| 5138 | /* Zero is not valid for unsigned compares that take an adjusted |
| 5139 | constant immediate range. */ |
| 5140 | if (e->X_add_number == 0) |
| 5141 | return OPERAND_OUT_OF_RANGE; |
| 5142 | |
| 5143 | /* Sign-extend 32-bit unsigned numbers, so that the following range |
| 5144 | checks will work. */ |
| 5145 | val = e->X_add_number; |
| 5146 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
| 5147 | && ((val & ((bfd_vma) 1 << 31)) != 0)) |
| 5148 | val = ((val << 32) >> 32); |
| 5149 | |
| 5150 | /* Check for 0x100000000. This is valid because |
| 5151 | 0x100000000-1 is the same as ((uint32_t) -1). */ |
| 5152 | if (val == ((bfd_signed_vma) 1 << 32)) |
| 5153 | return OPERAND_MATCH; |
| 5154 | |
| 5155 | val = val - 1; |
| 5156 | } |
| 5157 | else if (opnd == IA64_OPND_IMM8M1U8) |
| 5158 | { |
| 5159 | /* Zero is not valid for unsigned compares that take an adjusted |
| 5160 | constant immediate range. */ |
| 5161 | if (e->X_add_number == 0) |
| 5162 | return OPERAND_OUT_OF_RANGE; |
| 5163 | |
| 5164 | /* Check for 0x10000000000000000. */ |
| 5165 | if (e->X_op == O_big) |
| 5166 | { |
| 5167 | if (generic_bignum[0] == 0 |
| 5168 | && generic_bignum[1] == 0 |
| 5169 | && generic_bignum[2] == 0 |
| 5170 | && generic_bignum[3] == 0 |
| 5171 | && generic_bignum[4] == 1) |
| 5172 | return OPERAND_MATCH; |
| 5173 | else |
| 5174 | return OPERAND_OUT_OF_RANGE; |
| 5175 | } |
| 5176 | else |
| 5177 | val = e->X_add_number - 1; |
| 5178 | } |
| 5179 | else if (opnd == IA64_OPND_IMM8M1) |
| 5180 | val = e->X_add_number - 1; |
| 5181 | else if (opnd == IA64_OPND_IMM8U4) |
| 5182 | { |
| 5183 | /* Sign-extend 32-bit unsigned numbers, so that the following range |
| 5184 | checks will work. */ |
| 5185 | val = e->X_add_number; |
| 5186 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
| 5187 | && ((val & ((bfd_vma) 1 << 31)) != 0)) |
| 5188 | val = ((val << 32) >> 32); |
| 5189 | } |
| 5190 | else |
| 5191 | val = e->X_add_number; |
| 5192 | |
| 5193 | if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) |
| 5194 | || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) |
| 5195 | return OPERAND_MATCH; |
| 5196 | else |
| 5197 | return OPERAND_OUT_OF_RANGE; |
| 5198 | |
| 5199 | case IA64_OPND_INC3: |
| 5200 | /* +/- 1, 4, 8, 16 */ |
| 5201 | val = e->X_add_number; |
| 5202 | if (val < 0) |
| 5203 | val = -val; |
| 5204 | if (e->X_op == O_constant) |
| 5205 | { |
| 5206 | if ((val == 1 || val == 4 || val == 8 || val == 16)) |
| 5207 | return OPERAND_MATCH; |
| 5208 | else |
| 5209 | return OPERAND_OUT_OF_RANGE; |
| 5210 | } |
| 5211 | break; |
| 5212 | |
| 5213 | case IA64_OPND_TGT25: |
| 5214 | case IA64_OPND_TGT25b: |
| 5215 | case IA64_OPND_TGT25c: |
| 5216 | case IA64_OPND_TGT64: |
| 5217 | if (e->X_op == O_symbol) |
| 5218 | { |
| 5219 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; |
| 5220 | if (opnd == IA64_OPND_TGT25) |
| 5221 | fix->code = BFD_RELOC_IA64_PCREL21F; |
| 5222 | else if (opnd == IA64_OPND_TGT25b) |
| 5223 | fix->code = BFD_RELOC_IA64_PCREL21M; |
| 5224 | else if (opnd == IA64_OPND_TGT25c) |
| 5225 | fix->code = BFD_RELOC_IA64_PCREL21B; |
| 5226 | else if (opnd == IA64_OPND_TGT64) |
| 5227 | fix->code = BFD_RELOC_IA64_PCREL60B; |
| 5228 | else |
| 5229 | abort (); |
| 5230 | |
| 5231 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
| 5232 | fix->opnd = idesc->operands[index]; |
| 5233 | fix->expr = *e; |
| 5234 | fix->is_pcrel = 1; |
| 5235 | ++CURR_SLOT.num_fixups; |
| 5236 | return OPERAND_MATCH; |
| 5237 | } |
| 5238 | case IA64_OPND_TAG13: |
| 5239 | case IA64_OPND_TAG13b: |
| 5240 | switch (e->X_op) |
| 5241 | { |
| 5242 | case O_constant: |
| 5243 | return OPERAND_MATCH; |
| 5244 | |
| 5245 | case O_symbol: |
| 5246 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; |
| 5247 | /* There are no external relocs for TAG13/TAG13b fields, so we |
| 5248 | create a dummy reloc. This will not live past md_apply_fix3. */ |
| 5249 | fix->code = BFD_RELOC_UNUSED; |
| 5250 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
| 5251 | fix->opnd = idesc->operands[index]; |
| 5252 | fix->expr = *e; |
| 5253 | fix->is_pcrel = 1; |
| 5254 | ++CURR_SLOT.num_fixups; |
| 5255 | return OPERAND_MATCH; |
| 5256 | |
| 5257 | default: |
| 5258 | break; |
| 5259 | } |
| 5260 | break; |
| 5261 | |
| 5262 | default: |
| 5263 | break; |
| 5264 | } |
| 5265 | return OPERAND_MISMATCH; |
| 5266 | } |
| 5267 | |
| 5268 | static int |
| 5269 | parse_operand (e) |
| 5270 | expressionS *e; |
| 5271 | { |
| 5272 | int sep = '\0'; |
| 5273 | |
| 5274 | memset (e, 0, sizeof (*e)); |
| 5275 | e->X_op = O_absent; |
| 5276 | SKIP_WHITESPACE (); |
| 5277 | if (*input_line_pointer != '}') |
| 5278 | expression (e); |
| 5279 | sep = *input_line_pointer++; |
| 5280 | |
| 5281 | if (sep == '}') |
| 5282 | { |
| 5283 | if (!md.manual_bundling) |
| 5284 | as_warn ("Found '}' when manual bundling is off"); |
| 5285 | else |
| 5286 | CURR_SLOT.manual_bundling_off = 1; |
| 5287 | md.manual_bundling = 0; |
| 5288 | sep = '\0'; |
| 5289 | } |
| 5290 | return sep; |
| 5291 | } |
| 5292 | |
| 5293 | /* Returns the next entry in the opcode table that matches the one in |
| 5294 | IDESC, and frees the entry in IDESC. If no matching entry is |
| 5295 | found, NULL is returned instead. */ |
| 5296 | |
| 5297 | static struct ia64_opcode * |
| 5298 | get_next_opcode (struct ia64_opcode *idesc) |
| 5299 | { |
| 5300 | struct ia64_opcode *next = ia64_find_next_opcode (idesc); |
| 5301 | ia64_free_opcode (idesc); |
| 5302 | return next; |
| 5303 | } |
| 5304 | |
| 5305 | /* Parse the operands for the opcode and find the opcode variant that |
| 5306 | matches the specified operands, or NULL if no match is possible. */ |
| 5307 | |
| 5308 | static struct ia64_opcode * |
| 5309 | parse_operands (idesc) |
| 5310 | struct ia64_opcode *idesc; |
| 5311 | { |
| 5312 | int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; |
| 5313 | int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0; |
| 5314 | enum ia64_opnd expected_operand = IA64_OPND_NIL; |
| 5315 | enum operand_match_result result; |
| 5316 | char mnemonic[129]; |
| 5317 | char *first_arg = 0, *end, *saved_input_pointer; |
| 5318 | unsigned int sof; |
| 5319 | |
| 5320 | assert (strlen (idesc->name) <= 128); |
| 5321 | |
| 5322 | strcpy (mnemonic, idesc->name); |
| 5323 | if (idesc->operands[2] == IA64_OPND_SOF) |
| 5324 | { |
| 5325 | /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we |
| 5326 | can't parse the first operand until we have parsed the |
| 5327 | remaining operands of the "alloc" instruction. */ |
| 5328 | SKIP_WHITESPACE (); |
| 5329 | first_arg = input_line_pointer; |
| 5330 | end = strchr (input_line_pointer, '='); |
| 5331 | if (!end) |
| 5332 | { |
| 5333 | as_bad ("Expected separator `='"); |
| 5334 | return 0; |
| 5335 | } |
| 5336 | input_line_pointer = end + 1; |
| 5337 | ++i; |
| 5338 | ++num_outputs; |
| 5339 | } |
| 5340 | |
| 5341 | for (; i < NELEMS (CURR_SLOT.opnd); ++i) |
| 5342 | { |
| 5343 | sep = parse_operand (CURR_SLOT.opnd + i); |
| 5344 | if (CURR_SLOT.opnd[i].X_op == O_absent) |
| 5345 | break; |
| 5346 | |
| 5347 | ++num_operands; |
| 5348 | |
| 5349 | if (sep != '=' && sep != ',') |
| 5350 | break; |
| 5351 | |
| 5352 | if (sep == '=') |
| 5353 | { |
| 5354 | if (num_outputs > 0) |
| 5355 | as_bad ("Duplicate equal sign (=) in instruction"); |
| 5356 | else |
| 5357 | num_outputs = i + 1; |
| 5358 | } |
| 5359 | } |
| 5360 | if (sep != '\0') |
| 5361 | { |
| 5362 | as_bad ("Illegal operand separator `%c'", sep); |
| 5363 | return 0; |
| 5364 | } |
| 5365 | |
| 5366 | if (idesc->operands[2] == IA64_OPND_SOF) |
| 5367 | { |
| 5368 | /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ |
| 5369 | know (strcmp (idesc->name, "alloc") == 0); |
| 5370 | if (num_operands == 5 /* first_arg not included in this count! */ |
| 5371 | && CURR_SLOT.opnd[2].X_op == O_constant |
| 5372 | && CURR_SLOT.opnd[3].X_op == O_constant |
| 5373 | && CURR_SLOT.opnd[4].X_op == O_constant |
| 5374 | && CURR_SLOT.opnd[5].X_op == O_constant) |
| 5375 | { |
| 5376 | sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, |
| 5377 | CURR_SLOT.opnd[3].X_add_number, |
| 5378 | CURR_SLOT.opnd[4].X_add_number, |
| 5379 | CURR_SLOT.opnd[5].X_add_number); |
| 5380 | |
| 5381 | /* now we can parse the first arg: */ |
| 5382 | saved_input_pointer = input_line_pointer; |
| 5383 | input_line_pointer = first_arg; |
| 5384 | sep = parse_operand (CURR_SLOT.opnd + 0); |
| 5385 | if (sep != '=') |
| 5386 | --num_outputs; /* force error */ |
| 5387 | input_line_pointer = saved_input_pointer; |
| 5388 | |
| 5389 | CURR_SLOT.opnd[2].X_add_number = sof; |
| 5390 | CURR_SLOT.opnd[3].X_add_number |
| 5391 | = sof - CURR_SLOT.opnd[4].X_add_number; |
| 5392 | CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; |
| 5393 | } |
| 5394 | } |
| 5395 | |
| 5396 | highest_unmatched_operand = 0; |
| 5397 | curr_out_of_range_pos = -1; |
| 5398 | error_pos = 0; |
| 5399 | expected_operand = idesc->operands[0]; |
| 5400 | for (; idesc; idesc = get_next_opcode (idesc)) |
| 5401 | { |
| 5402 | if (num_outputs != idesc->num_outputs) |
| 5403 | continue; /* mismatch in # of outputs */ |
| 5404 | |
| 5405 | CURR_SLOT.num_fixups = 0; |
| 5406 | |
| 5407 | /* Try to match all operands. If we see an out-of-range operand, |
| 5408 | then continue trying to match the rest of the operands, since if |
| 5409 | the rest match, then this idesc will give the best error message. */ |
| 5410 | |
| 5411 | out_of_range_pos = -1; |
| 5412 | for (i = 0; i < num_operands && idesc->operands[i]; ++i) |
| 5413 | { |
| 5414 | result = operand_match (idesc, i, CURR_SLOT.opnd + i); |
| 5415 | if (result != OPERAND_MATCH) |
| 5416 | { |
| 5417 | if (result != OPERAND_OUT_OF_RANGE) |
| 5418 | break; |
| 5419 | if (out_of_range_pos < 0) |
| 5420 | /* remember position of the first out-of-range operand: */ |
| 5421 | out_of_range_pos = i; |
| 5422 | } |
| 5423 | } |
| 5424 | |
| 5425 | /* If we did not match all operands, or if at least one operand was |
| 5426 | out-of-range, then this idesc does not match. Keep track of which |
| 5427 | idesc matched the most operands before failing. If we have two |
| 5428 | idescs that failed at the same position, and one had an out-of-range |
| 5429 | operand, then prefer the out-of-range operand. Thus if we have |
| 5430 | "add r0=0x1000000,r1" we get an error saying the constant is out |
| 5431 | of range instead of an error saying that the constant should have been |
| 5432 | a register. */ |
| 5433 | |
| 5434 | if (i != num_operands || out_of_range_pos >= 0) |
| 5435 | { |
| 5436 | if (i > highest_unmatched_operand |
| 5437 | || (i == highest_unmatched_operand |
| 5438 | && out_of_range_pos > curr_out_of_range_pos)) |
| 5439 | { |
| 5440 | highest_unmatched_operand = i; |
| 5441 | if (out_of_range_pos >= 0) |
| 5442 | { |
| 5443 | expected_operand = idesc->operands[out_of_range_pos]; |
| 5444 | error_pos = out_of_range_pos; |
| 5445 | } |
| 5446 | else |
| 5447 | { |
| 5448 | expected_operand = idesc->operands[i]; |
| 5449 | error_pos = i; |
| 5450 | } |
| 5451 | curr_out_of_range_pos = out_of_range_pos; |
| 5452 | } |
| 5453 | continue; |
| 5454 | } |
| 5455 | |
| 5456 | if (num_operands < NELEMS (idesc->operands) |
| 5457 | && idesc->operands[num_operands]) |
| 5458 | continue; /* mismatch in number of arguments */ |
| 5459 | |
| 5460 | break; |
| 5461 | } |
| 5462 | if (!idesc) |
| 5463 | { |
| 5464 | if (expected_operand) |
| 5465 | as_bad ("Operand %u of `%s' should be %s", |
| 5466 | error_pos + 1, mnemonic, |
| 5467 | elf64_ia64_operands[expected_operand].desc); |
| 5468 | else |
| 5469 | as_bad ("Operand mismatch"); |
| 5470 | return 0; |
| 5471 | } |
| 5472 | return idesc; |
| 5473 | } |
| 5474 | |
| 5475 | /* Keep track of state necessary to determine whether a NOP is necessary |
| 5476 | to avoid an erratum in A and B step Itanium chips, and return 1 if we |
| 5477 | detect a case where additional NOPs may be necessary. */ |
| 5478 | static int |
| 5479 | errata_nop_necessary_p (slot, insn_unit) |
| 5480 | struct slot *slot; |
| 5481 | enum ia64_unit insn_unit; |
| 5482 | { |
| 5483 | int i; |
| 5484 | struct group *this_group = md.last_groups + md.group_idx; |
| 5485 | struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3; |
| 5486 | struct ia64_opcode *idesc = slot->idesc; |
| 5487 | |
| 5488 | /* Test whether this could be the first insn in a problematic sequence. */ |
| 5489 | if (insn_unit == IA64_UNIT_F) |
| 5490 | { |
| 5491 | for (i = 0; i < idesc->num_outputs; i++) |
| 5492 | if (idesc->operands[i] == IA64_OPND_P1 |
| 5493 | || idesc->operands[i] == IA64_OPND_P2) |
| 5494 | { |
| 5495 | int regno = slot->opnd[i].X_add_number - REG_P; |
| 5496 | /* Ignore invalid operands; they generate errors elsewhere. */ |
| 5497 | if (regno >= 64) |
| 5498 | return 0; |
| 5499 | this_group->p_reg_set[regno] = 1; |
| 5500 | } |
| 5501 | } |
| 5502 | |
| 5503 | /* Test whether this could be the second insn in a problematic sequence. */ |
| 5504 | if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0 |
| 5505 | && prev_group->p_reg_set[slot->qp_regno]) |
| 5506 | { |
| 5507 | for (i = 0; i < idesc->num_outputs; i++) |
| 5508 | if (idesc->operands[i] == IA64_OPND_R1 |
| 5509 | || idesc->operands[i] == IA64_OPND_R2 |
| 5510 | || idesc->operands[i] == IA64_OPND_R3) |
| 5511 | { |
| 5512 | int regno = slot->opnd[i].X_add_number - REG_GR; |
| 5513 | /* Ignore invalid operands; they generate errors elsewhere. */ |
| 5514 | if (regno >= 128) |
| 5515 | return 0; |
| 5516 | if (strncmp (idesc->name, "add", 3) != 0 |
| 5517 | && strncmp (idesc->name, "sub", 3) != 0 |
| 5518 | && strncmp (idesc->name, "shladd", 6) != 0 |
| 5519 | && (idesc->flags & IA64_OPCODE_POSTINC) == 0) |
| 5520 | this_group->g_reg_set_conditionally[regno] = 1; |
| 5521 | } |
| 5522 | } |
| 5523 | |
| 5524 | /* Test whether this could be the third insn in a problematic sequence. */ |
| 5525 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++) |
| 5526 | { |
| 5527 | if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */ |
| 5528 | idesc->operands[i] == IA64_OPND_R3 |
| 5529 | /* For mov indirect. */ |
| 5530 | || idesc->operands[i] == IA64_OPND_RR_R3 |
| 5531 | || idesc->operands[i] == IA64_OPND_DBR_R3 |
| 5532 | || idesc->operands[i] == IA64_OPND_IBR_R3 |
| 5533 | || idesc->operands[i] == IA64_OPND_PKR_R3 |
| 5534 | || idesc->operands[i] == IA64_OPND_PMC_R3 |
| 5535 | || idesc->operands[i] == IA64_OPND_PMD_R3 |
| 5536 | || idesc->operands[i] == IA64_OPND_MSR_R3 |
| 5537 | || idesc->operands[i] == IA64_OPND_CPUID_R3 |
| 5538 | /* For itr. */ |
| 5539 | || idesc->operands[i] == IA64_OPND_ITR_R3 |
| 5540 | || idesc->operands[i] == IA64_OPND_DTR_R3 |
| 5541 | /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */ |
| 5542 | || idesc->operands[i] == IA64_OPND_MR3) |
| 5543 | { |
| 5544 | int regno = slot->opnd[i].X_add_number - REG_GR; |
| 5545 | /* Ignore invalid operands; they generate errors elsewhere. */ |
| 5546 | if (regno >= 128) |
| 5547 | return 0; |
| 5548 | if (idesc->operands[i] == IA64_OPND_R3) |
| 5549 | { |
| 5550 | if (strcmp (idesc->name, "fc") != 0 |
| 5551 | && strcmp (idesc->name, "tak") != 0 |
| 5552 | && strcmp (idesc->name, "thash") != 0 |
| 5553 | && strcmp (idesc->name, "tpa") != 0 |
| 5554 | && strcmp (idesc->name, "ttag") != 0 |
| 5555 | && strncmp (idesc->name, "ptr", 3) != 0 |
| 5556 | && strncmp (idesc->name, "ptc", 3) != 0 |
| 5557 | && strncmp (idesc->name, "probe", 5) != 0) |
| 5558 | return 0; |
| 5559 | } |
| 5560 | if (prev_group->g_reg_set_conditionally[regno]) |
| 5561 | return 1; |
| 5562 | } |
| 5563 | } |
| 5564 | return 0; |
| 5565 | } |
| 5566 | |
| 5567 | static void |
| 5568 | build_insn (slot, insnp) |
| 5569 | struct slot *slot; |
| 5570 | bfd_vma *insnp; |
| 5571 | { |
| 5572 | const struct ia64_operand *odesc, *o2desc; |
| 5573 | struct ia64_opcode *idesc = slot->idesc; |
| 5574 | bfd_signed_vma insn, val; |
| 5575 | const char *err; |
| 5576 | int i; |
| 5577 | |
| 5578 | insn = idesc->opcode | slot->qp_regno; |
| 5579 | |
| 5580 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) |
| 5581 | { |
| 5582 | if (slot->opnd[i].X_op == O_register |
| 5583 | || slot->opnd[i].X_op == O_constant |
| 5584 | || slot->opnd[i].X_op == O_index) |
| 5585 | val = slot->opnd[i].X_add_number; |
| 5586 | else if (slot->opnd[i].X_op == O_big) |
| 5587 | { |
| 5588 | /* This must be the value 0x10000000000000000. */ |
| 5589 | assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); |
| 5590 | val = 0; |
| 5591 | } |
| 5592 | else |
| 5593 | val = 0; |
| 5594 | |
| 5595 | switch (idesc->operands[i]) |
| 5596 | { |
| 5597 | case IA64_OPND_IMMU64: |
| 5598 | *insnp++ = (val >> 22) & 0x1ffffffffffLL; |
| 5599 | insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) |
| 5600 | | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) |
| 5601 | | (((val >> 63) & 0x1) << 36)); |
| 5602 | continue; |
| 5603 | |
| 5604 | case IA64_OPND_IMMU62: |
| 5605 | val &= 0x3fffffffffffffffULL; |
| 5606 | if (val != slot->opnd[i].X_add_number) |
| 5607 | as_warn (_("Value truncated to 62 bits")); |
| 5608 | *insnp++ = (val >> 21) & 0x1ffffffffffLL; |
| 5609 | insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); |
| 5610 | continue; |
| 5611 | |
| 5612 | case IA64_OPND_TGT64: |
| 5613 | val >>= 4; |
| 5614 | *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; |
| 5615 | insn |= ((((val >> 59) & 0x1) << 36) |
| 5616 | | (((val >> 0) & 0xfffff) << 13)); |
| 5617 | continue; |
| 5618 | |
| 5619 | case IA64_OPND_AR3: |
| 5620 | val -= REG_AR; |
| 5621 | break; |
| 5622 | |
| 5623 | case IA64_OPND_B1: |
| 5624 | case IA64_OPND_B2: |
| 5625 | val -= REG_BR; |
| 5626 | break; |
| 5627 | |
| 5628 | case IA64_OPND_CR3: |
| 5629 | val -= REG_CR; |
| 5630 | break; |
| 5631 | |
| 5632 | case IA64_OPND_F1: |
| 5633 | case IA64_OPND_F2: |
| 5634 | case IA64_OPND_F3: |
| 5635 | case IA64_OPND_F4: |
| 5636 | val -= REG_FR; |
| 5637 | break; |
| 5638 | |
| 5639 | case IA64_OPND_P1: |
| 5640 | case IA64_OPND_P2: |
| 5641 | val -= REG_P; |
| 5642 | break; |
| 5643 | |
| 5644 | case IA64_OPND_R1: |
| 5645 | case IA64_OPND_R2: |
| 5646 | case IA64_OPND_R3: |
| 5647 | case IA64_OPND_R3_2: |
| 5648 | case IA64_OPND_CPUID_R3: |
| 5649 | case IA64_OPND_DBR_R3: |
| 5650 | case IA64_OPND_DTR_R3: |
| 5651 | case IA64_OPND_ITR_R3: |
| 5652 | case IA64_OPND_IBR_R3: |
| 5653 | case IA64_OPND_MR3: |
| 5654 | case IA64_OPND_MSR_R3: |
| 5655 | case IA64_OPND_PKR_R3: |
| 5656 | case IA64_OPND_PMC_R3: |
| 5657 | case IA64_OPND_PMD_R3: |
| 5658 | case IA64_OPND_RR_R3: |
| 5659 | val -= REG_GR; |
| 5660 | break; |
| 5661 | |
| 5662 | default: |
| 5663 | break; |
| 5664 | } |
| 5665 | |
| 5666 | odesc = elf64_ia64_operands + idesc->operands[i]; |
| 5667 | err = (*odesc->insert) (odesc, val, &insn); |
| 5668 | if (err) |
| 5669 | as_bad_where (slot->src_file, slot->src_line, |
| 5670 | "Bad operand value: %s", err); |
| 5671 | if (idesc->flags & IA64_OPCODE_PSEUDO) |
| 5672 | { |
| 5673 | if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) |
| 5674 | && odesc == elf64_ia64_operands + IA64_OPND_F3) |
| 5675 | { |
| 5676 | o2desc = elf64_ia64_operands + IA64_OPND_F2; |
| 5677 | (*o2desc->insert) (o2desc, val, &insn); |
| 5678 | } |
| 5679 | if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) |
| 5680 | && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a |
| 5681 | || odesc == elf64_ia64_operands + IA64_OPND_POS6)) |
| 5682 | { |
| 5683 | o2desc = elf64_ia64_operands + IA64_OPND_LEN6; |
| 5684 | (*o2desc->insert) (o2desc, 64 - val, &insn); |
| 5685 | } |
| 5686 | } |
| 5687 | } |
| 5688 | *insnp = insn; |
| 5689 | } |
| 5690 | |
| 5691 | static void |
| 5692 | emit_one_bundle () |
| 5693 | { |
| 5694 | unsigned int manual_bundling_on = 0, manual_bundling_off = 0; |
| 5695 | unsigned int manual_bundling = 0; |
| 5696 | enum ia64_unit required_unit, insn_unit = 0; |
| 5697 | enum ia64_insn_type type[3], insn_type; |
| 5698 | unsigned int template, orig_template; |
| 5699 | bfd_vma insn[3] = { -1, -1, -1 }; |
| 5700 | struct ia64_opcode *idesc; |
| 5701 | int end_of_insn_group = 0, user_template = -1; |
| 5702 | int n, i, j, first, curr; |
| 5703 | unw_rec_list *ptr; |
| 5704 | bfd_vma t0 = 0, t1 = 0; |
| 5705 | struct label_fix *lfix; |
| 5706 | struct insn_fix *ifix; |
| 5707 | char mnemonic[16]; |
| 5708 | fixS *fix; |
| 5709 | char *f; |
| 5710 | |
| 5711 | first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; |
| 5712 | know (first >= 0 & first < NUM_SLOTS); |
| 5713 | n = MIN (3, md.num_slots_in_use); |
| 5714 | |
| 5715 | /* Determine template: user user_template if specified, best match |
| 5716 | otherwise: */ |
| 5717 | |
| 5718 | if (md.slot[first].user_template >= 0) |
| 5719 | user_template = template = md.slot[first].user_template; |
| 5720 | else |
| 5721 | { |
| 5722 | /* Auto select appropriate template. */ |
| 5723 | memset (type, 0, sizeof (type)); |
| 5724 | curr = first; |
| 5725 | for (i = 0; i < n; ++i) |
| 5726 | { |
| 5727 | if (md.slot[curr].label_fixups && i != 0) |
| 5728 | break; |
| 5729 | type[i] = md.slot[curr].idesc->type; |
| 5730 | curr = (curr + 1) % NUM_SLOTS; |
| 5731 | } |
| 5732 | template = best_template[type[0]][type[1]][type[2]]; |
| 5733 | } |
| 5734 | |
| 5735 | /* initialize instructions with appropriate nops: */ |
| 5736 | for (i = 0; i < 3; ++i) |
| 5737 | insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; |
| 5738 | |
| 5739 | f = frag_more (16); |
| 5740 | |
| 5741 | /* now fill in slots with as many insns as possible: */ |
| 5742 | curr = first; |
| 5743 | idesc = md.slot[curr].idesc; |
| 5744 | end_of_insn_group = 0; |
| 5745 | for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) |
| 5746 | { |
| 5747 | /* Set the slot number for prologue/body records now as those |
| 5748 | refer to the current point, not the point after the |
| 5749 | instruction has been issued: */ |
| 5750 | /* Don't try to delete prologue/body records here, as that will cause |
| 5751 | them to also be deleted from the master list of unwind records. */ |
| 5752 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) |
| 5753 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr |
| 5754 | || ptr->r.type == body) |
| 5755 | { |
| 5756 | ptr->slot_number = (unsigned long) f + i; |
| 5757 | ptr->slot_frag = frag_now; |
| 5758 | } |
| 5759 | |
| 5760 | if (idesc->flags & IA64_OPCODE_SLOT2) |
| 5761 | { |
| 5762 | if (manual_bundling && i != 2) |
| 5763 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 5764 | "`%s' must be last in bundle", idesc->name); |
| 5765 | else |
| 5766 | i = 2; |
| 5767 | } |
| 5768 | if (idesc->flags & IA64_OPCODE_LAST) |
| 5769 | { |
| 5770 | int required_slot; |
| 5771 | unsigned int required_template; |
| 5772 | |
| 5773 | /* If we need a stop bit after an M slot, our only choice is |
| 5774 | template 5 (M;;MI). If we need a stop bit after a B |
| 5775 | slot, our only choice is to place it at the end of the |
| 5776 | bundle, because the only available templates are MIB, |
| 5777 | MBB, BBB, MMB, and MFB. We don't handle anything other |
| 5778 | than M and B slots because these are the only kind of |
| 5779 | instructions that can have the IA64_OPCODE_LAST bit set. */ |
| 5780 | required_template = template; |
| 5781 | switch (idesc->type) |
| 5782 | { |
| 5783 | case IA64_TYPE_M: |
| 5784 | required_slot = 0; |
| 5785 | required_template = 5; |
| 5786 | break; |
| 5787 | |
| 5788 | case IA64_TYPE_B: |
| 5789 | required_slot = 2; |
| 5790 | break; |
| 5791 | |
| 5792 | default: |
| 5793 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 5794 | "Internal error: don't know how to force %s to end" |
| 5795 | "of instruction group", idesc->name); |
| 5796 | required_slot = i; |
| 5797 | break; |
| 5798 | } |
| 5799 | if (manual_bundling && i != required_slot) |
| 5800 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 5801 | "`%s' must be last in instruction group", |
| 5802 | idesc->name); |
| 5803 | if (required_slot < i) |
| 5804 | /* Can't fit this instruction. */ |
| 5805 | break; |
| 5806 | |
| 5807 | i = required_slot; |
| 5808 | if (required_template != template) |
| 5809 | { |
| 5810 | /* If we switch the template, we need to reset the NOPs |
| 5811 | after slot i. The slot-types of the instructions ahead |
| 5812 | of i never change, so we don't need to worry about |
| 5813 | changing NOPs in front of this slot. */ |
| 5814 | for (j = i; j < 3; ++j) |
| 5815 | insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; |
| 5816 | } |
| 5817 | template = required_template; |
| 5818 | } |
| 5819 | if (curr != first && md.slot[curr].label_fixups) |
| 5820 | { |
| 5821 | if (manual_bundling_on) |
| 5822 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 5823 | "Label must be first in a bundle"); |
| 5824 | /* This insn must go into the first slot of a bundle. */ |
| 5825 | break; |
| 5826 | } |
| 5827 | |
| 5828 | manual_bundling_on = md.slot[curr].manual_bundling_on; |
| 5829 | manual_bundling_off = md.slot[curr].manual_bundling_off; |
| 5830 | |
| 5831 | if (manual_bundling_on) |
| 5832 | { |
| 5833 | if (curr == first) |
| 5834 | manual_bundling = 1; |
| 5835 | else |
| 5836 | break; /* need to start a new bundle */ |
| 5837 | } |
| 5838 | |
| 5839 | if (end_of_insn_group && md.num_slots_in_use >= 1) |
| 5840 | { |
| 5841 | /* We need an instruction group boundary in the middle of a |
| 5842 | bundle. See if we can switch to an other template with |
| 5843 | an appropriate boundary. */ |
| 5844 | |
| 5845 | orig_template = template; |
| 5846 | if (i == 1 && (user_template == 4 |
| 5847 | || (user_template < 0 |
| 5848 | && (ia64_templ_desc[template].exec_unit[0] |
| 5849 | == IA64_UNIT_M)))) |
| 5850 | { |
| 5851 | template = 5; |
| 5852 | end_of_insn_group = 0; |
| 5853 | } |
| 5854 | else if (i == 2 && (user_template == 0 |
| 5855 | || (user_template < 0 |
| 5856 | && (ia64_templ_desc[template].exec_unit[1] |
| 5857 | == IA64_UNIT_I))) |
| 5858 | /* This test makes sure we don't switch the template if |
| 5859 | the next instruction is one that needs to be first in |
| 5860 | an instruction group. Since all those instructions are |
| 5861 | in the M group, there is no way such an instruction can |
| 5862 | fit in this bundle even if we switch the template. The |
| 5863 | reason we have to check for this is that otherwise we |
| 5864 | may end up generating "MI;;I M.." which has the deadly |
| 5865 | effect that the second M instruction is no longer the |
| 5866 | first in the bundle! --davidm 99/12/16 */ |
| 5867 | && (idesc->flags & IA64_OPCODE_FIRST) == 0) |
| 5868 | { |
| 5869 | template = 1; |
| 5870 | end_of_insn_group = 0; |
| 5871 | } |
| 5872 | else if (curr != first) |
| 5873 | /* can't fit this insn */ |
| 5874 | break; |
| 5875 | |
| 5876 | if (template != orig_template) |
| 5877 | /* if we switch the template, we need to reset the NOPs |
| 5878 | after slot i. The slot-types of the instructions ahead |
| 5879 | of i never change, so we don't need to worry about |
| 5880 | changing NOPs in front of this slot. */ |
| 5881 | for (j = i; j < 3; ++j) |
| 5882 | insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; |
| 5883 | } |
| 5884 | required_unit = ia64_templ_desc[template].exec_unit[i]; |
| 5885 | |
| 5886 | /* resolve dynamic opcodes such as "break" and "nop": */ |
| 5887 | if (idesc->type == IA64_TYPE_DYN) |
| 5888 | { |
| 5889 | if ((strcmp (idesc->name, "nop") == 0) |
| 5890 | || (strcmp (idesc->name, "break") == 0)) |
| 5891 | insn_unit = required_unit; |
| 5892 | else if (strcmp (idesc->name, "chk.s") == 0) |
| 5893 | { |
| 5894 | insn_unit = IA64_UNIT_M; |
| 5895 | if (required_unit == IA64_UNIT_I) |
| 5896 | insn_unit = IA64_UNIT_I; |
| 5897 | } |
| 5898 | else |
| 5899 | as_fatal ("emit_one_bundle: unexpected dynamic op"); |
| 5900 | |
| 5901 | sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); |
| 5902 | ia64_free_opcode (idesc); |
| 5903 | md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); |
| 5904 | #if 0 |
| 5905 | know (!idesc->next); /* no resolved dynamic ops have collisions */ |
| 5906 | #endif |
| 5907 | } |
| 5908 | else |
| 5909 | { |
| 5910 | insn_type = idesc->type; |
| 5911 | insn_unit = IA64_UNIT_NIL; |
| 5912 | switch (insn_type) |
| 5913 | { |
| 5914 | case IA64_TYPE_A: |
| 5915 | if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) |
| 5916 | insn_unit = required_unit; |
| 5917 | break; |
| 5918 | case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; |
| 5919 | case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; |
| 5920 | case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; |
| 5921 | case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; |
| 5922 | case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; |
| 5923 | default: break; |
| 5924 | } |
| 5925 | } |
| 5926 | |
| 5927 | if (insn_unit != required_unit) |
| 5928 | { |
| 5929 | if (required_unit == IA64_UNIT_L |
| 5930 | && insn_unit == IA64_UNIT_I |
| 5931 | && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) |
| 5932 | { |
| 5933 | /* we got ourselves an MLX template but the current |
| 5934 | instruction isn't an X-unit, or an I-unit instruction |
| 5935 | that can go into the X slot of an MLX template. Duh. */ |
| 5936 | if (md.num_slots_in_use >= NUM_SLOTS) |
| 5937 | { |
| 5938 | as_bad_where (md.slot[curr].src_file, |
| 5939 | md.slot[curr].src_line, |
| 5940 | "`%s' can't go in X slot of " |
| 5941 | "MLX template", idesc->name); |
| 5942 | /* drop this insn so we don't livelock: */ |
| 5943 | --md.num_slots_in_use; |
| 5944 | } |
| 5945 | break; |
| 5946 | } |
| 5947 | continue; /* try next slot */ |
| 5948 | } |
| 5949 | |
| 5950 | { |
| 5951 | bfd_vma addr; |
| 5952 | |
| 5953 | addr = frag_now->fr_address + frag_now_fix () - 16 + i; |
| 5954 | dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); |
| 5955 | } |
| 5956 | |
| 5957 | if (errata_nop_necessary_p (md.slot + curr, insn_unit)) |
| 5958 | as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata")); |
| 5959 | |
| 5960 | build_insn (md.slot + curr, insn + i); |
| 5961 | |
| 5962 | /* Set slot counts for non prologue/body unwind records. */ |
| 5963 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) |
| 5964 | if (ptr->r.type != prologue && ptr->r.type != prologue_gr |
| 5965 | && ptr->r.type != body) |
| 5966 | { |
| 5967 | ptr->slot_number = (unsigned long) f + i; |
| 5968 | ptr->slot_frag = frag_now; |
| 5969 | } |
| 5970 | md.slot[curr].unwind_record = NULL; |
| 5971 | |
| 5972 | if (required_unit == IA64_UNIT_L) |
| 5973 | { |
| 5974 | know (i == 1); |
| 5975 | /* skip one slot for long/X-unit instructions */ |
| 5976 | ++i; |
| 5977 | } |
| 5978 | --md.num_slots_in_use; |
| 5979 | |
| 5980 | /* now is a good time to fix up the labels for this insn: */ |
| 5981 | for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) |
| 5982 | { |
| 5983 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16); |
| 5984 | symbol_set_frag (lfix->sym, frag_now); |
| 5985 | } |
| 5986 | /* and fix up the tags also. */ |
| 5987 | for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) |
| 5988 | { |
| 5989 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); |
| 5990 | symbol_set_frag (lfix->sym, frag_now); |
| 5991 | } |
| 5992 | |
| 5993 | for (j = 0; j < md.slot[curr].num_fixups; ++j) |
| 5994 | { |
| 5995 | ifix = md.slot[curr].fixup + j; |
| 5996 | fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, |
| 5997 | &ifix->expr, ifix->is_pcrel, ifix->code); |
| 5998 | fix->tc_fix_data.opnd = ifix->opnd; |
| 5999 | fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); |
| 6000 | fix->fx_file = md.slot[curr].src_file; |
| 6001 | fix->fx_line = md.slot[curr].src_line; |
| 6002 | } |
| 6003 | |
| 6004 | end_of_insn_group = md.slot[curr].end_of_insn_group; |
| 6005 | |
| 6006 | if (end_of_insn_group) |
| 6007 | { |
| 6008 | md.group_idx = (md.group_idx + 1) % 3; |
| 6009 | memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]); |
| 6010 | } |
| 6011 | |
| 6012 | /* clear slot: */ |
| 6013 | ia64_free_opcode (md.slot[curr].idesc); |
| 6014 | memset (md.slot + curr, 0, sizeof (md.slot[curr])); |
| 6015 | md.slot[curr].user_template = -1; |
| 6016 | |
| 6017 | if (manual_bundling_off) |
| 6018 | { |
| 6019 | manual_bundling = 0; |
| 6020 | break; |
| 6021 | } |
| 6022 | curr = (curr + 1) % NUM_SLOTS; |
| 6023 | idesc = md.slot[curr].idesc; |
| 6024 | } |
| 6025 | if (manual_bundling) |
| 6026 | { |
| 6027 | if (md.num_slots_in_use > 0) |
| 6028 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 6029 | "`%s' does not fit into %s template", |
| 6030 | idesc->name, ia64_templ_desc[template].name); |
| 6031 | else |
| 6032 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, |
| 6033 | "Missing '}' at end of file"); |
| 6034 | } |
| 6035 | know (md.num_slots_in_use < NUM_SLOTS); |
| 6036 | |
| 6037 | t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); |
| 6038 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); |
| 6039 | |
| 6040 | number_to_chars_littleendian (f + 0, t0, 8); |
| 6041 | number_to_chars_littleendian (f + 8, t1, 8); |
| 6042 | |
| 6043 | unwind.next_slot_number = (unsigned long) f + 16; |
| 6044 | unwind.next_slot_frag = frag_now; |
| 6045 | } |
| 6046 | |
| 6047 | int |
| 6048 | md_parse_option (c, arg) |
| 6049 | int c; |
| 6050 | char *arg; |
| 6051 | { |
| 6052 | |
| 6053 | switch (c) |
| 6054 | { |
| 6055 | /* Switches from the Intel assembler. */ |
| 6056 | case 'm': |
| 6057 | if (strcmp (arg, "ilp64") == 0 |
| 6058 | || strcmp (arg, "lp64") == 0 |
| 6059 | || strcmp (arg, "p64") == 0) |
| 6060 | { |
| 6061 | md.flags |= EF_IA_64_ABI64; |
| 6062 | } |
| 6063 | else if (strcmp (arg, "ilp32") == 0) |
| 6064 | { |
| 6065 | md.flags &= ~EF_IA_64_ABI64; |
| 6066 | } |
| 6067 | else if (strcmp (arg, "le") == 0) |
| 6068 | { |
| 6069 | md.flags &= ~EF_IA_64_BE; |
| 6070 | } |
| 6071 | else if (strcmp (arg, "be") == 0) |
| 6072 | { |
| 6073 | md.flags |= EF_IA_64_BE; |
| 6074 | } |
| 6075 | else |
| 6076 | return 0; |
| 6077 | break; |
| 6078 | |
| 6079 | case 'N': |
| 6080 | if (strcmp (arg, "so") == 0) |
| 6081 | { |
| 6082 | /* Suppress signon message. */ |
| 6083 | } |
| 6084 | else if (strcmp (arg, "pi") == 0) |
| 6085 | { |
| 6086 | /* Reject privileged instructions. FIXME */ |
| 6087 | } |
| 6088 | else if (strcmp (arg, "us") == 0) |
| 6089 | { |
| 6090 | /* Allow union of signed and unsigned range. FIXME */ |
| 6091 | } |
| 6092 | else if (strcmp (arg, "close_fcalls") == 0) |
| 6093 | { |
| 6094 | /* Do not resolve global function calls. */ |
| 6095 | } |
| 6096 | else |
| 6097 | return 0; |
| 6098 | break; |
| 6099 | |
| 6100 | case 'C': |
| 6101 | /* temp[="prefix"] Insert temporary labels into the object file |
| 6102 | symbol table prefixed by "prefix". |
| 6103 | Default prefix is ":temp:". |
| 6104 | */ |
| 6105 | break; |
| 6106 | |
| 6107 | case 'a': |
| 6108 | /* indirect=<tgt> Assume unannotated indirect branches behavior |
| 6109 | according to <tgt> -- |
| 6110 | exit: branch out from the current context (default) |
| 6111 | labels: all labels in context may be branch targets |
| 6112 | */ |
| 6113 | if (strncmp (arg, "indirect=", 9) != 0) |
| 6114 | return 0; |
| 6115 | break; |
| 6116 | |
| 6117 | case 'x': |
| 6118 | /* -X conflicts with an ignored option, use -x instead */ |
| 6119 | md.detect_dv = 1; |
| 6120 | if (!arg || strcmp (arg, "explicit") == 0) |
| 6121 | { |
| 6122 | /* set default mode to explicit */ |
| 6123 | md.default_explicit_mode = 1; |
| 6124 | break; |
| 6125 | } |
| 6126 | else if (strcmp (arg, "auto") == 0) |
| 6127 | { |
| 6128 | md.default_explicit_mode = 0; |
| 6129 | } |
| 6130 | else if (strcmp (arg, "debug") == 0) |
| 6131 | { |
| 6132 | md.debug_dv = 1; |
| 6133 | } |
| 6134 | else if (strcmp (arg, "debugx") == 0) |
| 6135 | { |
| 6136 | md.default_explicit_mode = 1; |
| 6137 | md.debug_dv = 1; |
| 6138 | } |
| 6139 | else |
| 6140 | { |
| 6141 | as_bad (_("Unrecognized option '-x%s'"), arg); |
| 6142 | } |
| 6143 | break; |
| 6144 | |
| 6145 | case 'S': |
| 6146 | /* nops Print nops statistics. */ |
| 6147 | break; |
| 6148 | |
| 6149 | /* GNU specific switches for gcc. */ |
| 6150 | case OPTION_MCONSTANT_GP: |
| 6151 | md.flags |= EF_IA_64_CONS_GP; |
| 6152 | break; |
| 6153 | |
| 6154 | case OPTION_MAUTO_PIC: |
| 6155 | md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; |
| 6156 | break; |
| 6157 | |
| 6158 | default: |
| 6159 | return 0; |
| 6160 | } |
| 6161 | |
| 6162 | return 1; |
| 6163 | } |
| 6164 | |
| 6165 | void |
| 6166 | md_show_usage (stream) |
| 6167 | FILE *stream; |
| 6168 | { |
| 6169 | fputs (_("\ |
| 6170 | IA-64 options:\n\ |
| 6171 | -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ |
| 6172 | -mle | -mbe select little- or big-endian byte order (default -mle)\n\ |
| 6173 | -x | -xexplicit turn on dependency violation checking (default)\n\ |
| 6174 | -xauto automagically remove dependency violations\n\ |
| 6175 | -xdebug debug dependency violation checker\n"), |
| 6176 | stream); |
| 6177 | } |
| 6178 | |
| 6179 | /* Return true if TYPE fits in TEMPL at SLOT. */ |
| 6180 | |
| 6181 | static int |
| 6182 | match (int templ, int type, int slot) |
| 6183 | { |
| 6184 | enum ia64_unit unit; |
| 6185 | int result; |
| 6186 | |
| 6187 | unit = ia64_templ_desc[templ].exec_unit[slot]; |
| 6188 | switch (type) |
| 6189 | { |
| 6190 | case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ |
| 6191 | case IA64_TYPE_A: |
| 6192 | result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); |
| 6193 | break; |
| 6194 | case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; |
| 6195 | case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; |
| 6196 | case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; |
| 6197 | case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; |
| 6198 | case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; |
| 6199 | default: result = 0; break; |
| 6200 | } |
| 6201 | return result; |
| 6202 | } |
| 6203 | |
| 6204 | /* Add a bit of extra goodness if a nop of type F or B would fit |
| 6205 | in TEMPL at SLOT. */ |
| 6206 | |
| 6207 | static inline int |
| 6208 | extra_goodness (int templ, int slot) |
| 6209 | { |
| 6210 | if (slot == 1 && match (templ, IA64_TYPE_F, slot)) |
| 6211 | return 2; |
| 6212 | if (slot == 2 && match (templ, IA64_TYPE_B, slot)) |
| 6213 | return 1; |
| 6214 | return 0; |
| 6215 | } |
| 6216 | |
| 6217 | /* This function is called once, at assembler startup time. It sets |
| 6218 | up all the tables, etc. that the MD part of the assembler will need |
| 6219 | that can be determined before arguments are parsed. */ |
| 6220 | void |
| 6221 | md_begin () |
| 6222 | { |
| 6223 | int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; |
| 6224 | const char *err; |
| 6225 | char name[8]; |
| 6226 | |
| 6227 | md.auto_align = 1; |
| 6228 | md.explicit_mode = md.default_explicit_mode; |
| 6229 | |
| 6230 | bfd_set_section_alignment (stdoutput, text_section, 4); |
| 6231 | |
| 6232 | target_big_endian = TARGET_BYTES_BIG_ENDIAN; |
| 6233 | pseudo_func[FUNC_FPTR_RELATIVE].u.sym = |
| 6234 | symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, |
| 6235 | &zero_address_frag); |
| 6236 | |
| 6237 | pseudo_func[FUNC_GP_RELATIVE].u.sym = |
| 6238 | symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, |
| 6239 | &zero_address_frag); |
| 6240 | |
| 6241 | pseudo_func[FUNC_LT_RELATIVE].u.sym = |
| 6242 | symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, |
| 6243 | &zero_address_frag); |
| 6244 | |
| 6245 | pseudo_func[FUNC_PC_RELATIVE].u.sym = |
| 6246 | symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, |
| 6247 | &zero_address_frag); |
| 6248 | |
| 6249 | pseudo_func[FUNC_PLT_RELATIVE].u.sym = |
| 6250 | symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, |
| 6251 | &zero_address_frag); |
| 6252 | |
| 6253 | pseudo_func[FUNC_SEC_RELATIVE].u.sym = |
| 6254 | symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, |
| 6255 | &zero_address_frag); |
| 6256 | |
| 6257 | pseudo_func[FUNC_SEG_RELATIVE].u.sym = |
| 6258 | symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, |
| 6259 | &zero_address_frag); |
| 6260 | |
| 6261 | pseudo_func[FUNC_LTV_RELATIVE].u.sym = |
| 6262 | symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, |
| 6263 | &zero_address_frag); |
| 6264 | |
| 6265 | pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = |
| 6266 | symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, |
| 6267 | &zero_address_frag); |
| 6268 | |
| 6269 | /* Compute the table of best templates. We compute goodness as a |
| 6270 | base 4 value, in which each match counts for 3, each F counts |
| 6271 | for 2, each B counts for 1. This should maximize the number of |
| 6272 | F and B nops in the chosen bundles, which is good because these |
| 6273 | pipelines are least likely to be overcommitted. */ |
| 6274 | for (i = 0; i < IA64_NUM_TYPES; ++i) |
| 6275 | for (j = 0; j < IA64_NUM_TYPES; ++j) |
| 6276 | for (k = 0; k < IA64_NUM_TYPES; ++k) |
| 6277 | { |
| 6278 | best = 0; |
| 6279 | for (t = 0; t < NELEMS (ia64_templ_desc); ++t) |
| 6280 | { |
| 6281 | goodness = 0; |
| 6282 | if (match (t, i, 0)) |
| 6283 | { |
| 6284 | if (match (t, j, 1)) |
| 6285 | { |
| 6286 | if (match (t, k, 2)) |
| 6287 | goodness = 3 + 3 + 3; |
| 6288 | else |
| 6289 | goodness = 3 + 3 + extra_goodness (t, 2); |
| 6290 | } |
| 6291 | else if (match (t, j, 2)) |
| 6292 | goodness = 3 + 3 + extra_goodness (t, 1); |
| 6293 | else |
| 6294 | { |
| 6295 | goodness = 3; |
| 6296 | goodness += extra_goodness (t, 1); |
| 6297 | goodness += extra_goodness (t, 2); |
| 6298 | } |
| 6299 | } |
| 6300 | else if (match (t, i, 1)) |
| 6301 | { |
| 6302 | if (match (t, j, 2)) |
| 6303 | goodness = 3 + 3; |
| 6304 | else |
| 6305 | goodness = 3 + extra_goodness (t, 2); |
| 6306 | } |
| 6307 | else if (match (t, i, 2)) |
| 6308 | goodness = 3 + extra_goodness (t, 1); |
| 6309 | |
| 6310 | if (goodness > best) |
| 6311 | { |
| 6312 | best = goodness; |
| 6313 | best_template[i][j][k] = t; |
| 6314 | } |
| 6315 | } |
| 6316 | } |
| 6317 | |
| 6318 | for (i = 0; i < NUM_SLOTS; ++i) |
| 6319 | md.slot[i].user_template = -1; |
| 6320 | |
| 6321 | md.pseudo_hash = hash_new (); |
| 6322 | for (i = 0; i < NELEMS (pseudo_opcode); ++i) |
| 6323 | { |
| 6324 | err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, |
| 6325 | (void *) (pseudo_opcode + i)); |
| 6326 | if (err) |
| 6327 | as_fatal ("ia64.md_begin: can't hash `%s': %s", |
| 6328 | pseudo_opcode[i].name, err); |
| 6329 | } |
| 6330 | |
| 6331 | md.reg_hash = hash_new (); |
| 6332 | md.dynreg_hash = hash_new (); |
| 6333 | md.const_hash = hash_new (); |
| 6334 | md.entry_hash = hash_new (); |
| 6335 | |
| 6336 | /* general registers: */ |
| 6337 | |
| 6338 | total = 128; |
| 6339 | for (i = 0; i < total; ++i) |
| 6340 | { |
| 6341 | sprintf (name, "r%d", i - REG_GR); |
| 6342 | md.regsym[i] = declare_register (name, i); |
| 6343 | } |
| 6344 | |
| 6345 | /* floating point registers: */ |
| 6346 | total += 128; |
| 6347 | for (; i < total; ++i) |
| 6348 | { |
| 6349 | sprintf (name, "f%d", i - REG_FR); |
| 6350 | md.regsym[i] = declare_register (name, i); |
| 6351 | } |
| 6352 | |
| 6353 | /* application registers: */ |
| 6354 | total += 128; |
| 6355 | ar_base = i; |
| 6356 | for (; i < total; ++i) |
| 6357 | { |
| 6358 | sprintf (name, "ar%d", i - REG_AR); |
| 6359 | md.regsym[i] = declare_register (name, i); |
| 6360 | } |
| 6361 | |
| 6362 | /* control registers: */ |
| 6363 | total += 128; |
| 6364 | cr_base = i; |
| 6365 | for (; i < total; ++i) |
| 6366 | { |
| 6367 | sprintf (name, "cr%d", i - REG_CR); |
| 6368 | md.regsym[i] = declare_register (name, i); |
| 6369 | } |
| 6370 | |
| 6371 | /* predicate registers: */ |
| 6372 | total += 64; |
| 6373 | for (; i < total; ++i) |
| 6374 | { |
| 6375 | sprintf (name, "p%d", i - REG_P); |
| 6376 | md.regsym[i] = declare_register (name, i); |
| 6377 | } |
| 6378 | |
| 6379 | /* branch registers: */ |
| 6380 | total += 8; |
| 6381 | for (; i < total; ++i) |
| 6382 | { |
| 6383 | sprintf (name, "b%d", i - REG_BR); |
| 6384 | md.regsym[i] = declare_register (name, i); |
| 6385 | } |
| 6386 | |
| 6387 | md.regsym[REG_IP] = declare_register ("ip", REG_IP); |
| 6388 | md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); |
| 6389 | md.regsym[REG_PR] = declare_register ("pr", REG_PR); |
| 6390 | md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); |
| 6391 | md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); |
| 6392 | md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); |
| 6393 | md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); |
| 6394 | |
| 6395 | for (i = 0; i < NELEMS (indirect_reg); ++i) |
| 6396 | { |
| 6397 | regnum = indirect_reg[i].regnum; |
| 6398 | md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); |
| 6399 | } |
| 6400 | |
| 6401 | /* define synonyms for application registers: */ |
| 6402 | for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) |
| 6403 | md.regsym[i] = declare_register (ar[i - REG_AR].name, |
| 6404 | REG_AR + ar[i - REG_AR].regnum); |
| 6405 | |
| 6406 | /* define synonyms for control registers: */ |
| 6407 | for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) |
| 6408 | md.regsym[i] = declare_register (cr[i - REG_CR].name, |
| 6409 | REG_CR + cr[i - REG_CR].regnum); |
| 6410 | |
| 6411 | declare_register ("gp", REG_GR + 1); |
| 6412 | declare_register ("sp", REG_GR + 12); |
| 6413 | declare_register ("rp", REG_BR + 0); |
| 6414 | |
| 6415 | /* pseudo-registers used to specify unwind info: */ |
| 6416 | declare_register ("psp", REG_PSP); |
| 6417 | |
| 6418 | declare_register_set ("ret", 4, REG_GR + 8); |
| 6419 | declare_register_set ("farg", 8, REG_FR + 8); |
| 6420 | declare_register_set ("fret", 8, REG_FR + 8); |
| 6421 | |
| 6422 | for (i = 0; i < NELEMS (const_bits); ++i) |
| 6423 | { |
| 6424 | err = hash_insert (md.const_hash, const_bits[i].name, |
| 6425 | (PTR) (const_bits + i)); |
| 6426 | if (err) |
| 6427 | as_fatal ("Inserting \"%s\" into constant hash table failed: %s", |
| 6428 | name, err); |
| 6429 | } |
| 6430 | |
| 6431 | /* Set the architecture and machine depending on defaults and command line |
| 6432 | options. */ |
| 6433 | if (md.flags & EF_IA_64_ABI64) |
| 6434 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); |
| 6435 | else |
| 6436 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); |
| 6437 | |
| 6438 | if (! ok) |
| 6439 | as_warn (_("Could not set architecture and machine")); |
| 6440 | |
| 6441 | md.mem_offset.hint = 0; |
| 6442 | md.path = 0; |
| 6443 | md.maxpaths = 0; |
| 6444 | md.entry_labels = NULL; |
| 6445 | } |
| 6446 | |
| 6447 | /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin |
| 6448 | because that is called after md_parse_option which is where we do the |
| 6449 | dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the |
| 6450 | default endianness. */ |
| 6451 | |
| 6452 | void |
| 6453 | ia64_init (argc, argv) |
| 6454 | int argc ATTRIBUTE_UNUSED; |
| 6455 | char **argv ATTRIBUTE_UNUSED; |
| 6456 | { |
| 6457 | md.flags = EF_IA_64_ABI64; |
| 6458 | if (TARGET_BYTES_BIG_ENDIAN) |
| 6459 | md.flags |= EF_IA_64_BE; |
| 6460 | } |
| 6461 | |
| 6462 | /* Return a string for the target object file format. */ |
| 6463 | |
| 6464 | const char * |
| 6465 | ia64_target_format () |
| 6466 | { |
| 6467 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 6468 | { |
| 6469 | if (md.flags & EF_IA_64_BE) |
| 6470 | { |
| 6471 | if (md.flags & EF_IA_64_ABI64) |
| 6472 | #ifdef TE_AIX50 |
| 6473 | return "elf64-ia64-aix-big"; |
| 6474 | #else |
| 6475 | return "elf64-ia64-big"; |
| 6476 | #endif |
| 6477 | else |
| 6478 | #ifdef TE_AIX50 |
| 6479 | return "elf32-ia64-aix-big"; |
| 6480 | #else |
| 6481 | return "elf32-ia64-big"; |
| 6482 | #endif |
| 6483 | } |
| 6484 | else |
| 6485 | { |
| 6486 | if (md.flags & EF_IA_64_ABI64) |
| 6487 | #ifdef TE_AIX50 |
| 6488 | return "elf64-ia64-aix-little"; |
| 6489 | #else |
| 6490 | return "elf64-ia64-little"; |
| 6491 | #endif |
| 6492 | else |
| 6493 | #ifdef TE_AIX50 |
| 6494 | return "elf32-ia64-aix-little"; |
| 6495 | #else |
| 6496 | return "elf32-ia64-little"; |
| 6497 | #endif |
| 6498 | } |
| 6499 | } |
| 6500 | else |
| 6501 | return "unknown-format"; |
| 6502 | } |
| 6503 | |
| 6504 | void |
| 6505 | ia64_end_of_source () |
| 6506 | { |
| 6507 | /* terminate insn group upon reaching end of file: */ |
| 6508 | insn_group_break (1, 0, 0); |
| 6509 | |
| 6510 | /* emits slots we haven't written yet: */ |
| 6511 | ia64_flush_insns (); |
| 6512 | |
| 6513 | bfd_set_private_flags (stdoutput, md.flags); |
| 6514 | |
| 6515 | md.mem_offset.hint = 0; |
| 6516 | } |
| 6517 | |
| 6518 | void |
| 6519 | ia64_start_line () |
| 6520 | { |
| 6521 | if (md.qp.X_op == O_register) |
| 6522 | as_bad ("qualifying predicate not followed by instruction"); |
| 6523 | md.qp.X_op = O_absent; |
| 6524 | |
| 6525 | if (ignore_input ()) |
| 6526 | return; |
| 6527 | |
| 6528 | if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') |
| 6529 | { |
| 6530 | if (md.detect_dv && !md.explicit_mode) |
| 6531 | as_warn (_("Explicit stops are ignored in auto mode")); |
| 6532 | else |
| 6533 | insn_group_break (1, 0, 0); |
| 6534 | } |
| 6535 | } |
| 6536 | |
| 6537 | /* This is a hook for ia64_frob_label, so that it can distinguish tags from |
| 6538 | labels. */ |
| 6539 | static int defining_tag = 0; |
| 6540 | |
| 6541 | int |
| 6542 | ia64_unrecognized_line (ch) |
| 6543 | int ch; |
| 6544 | { |
| 6545 | switch (ch) |
| 6546 | { |
| 6547 | case '(': |
| 6548 | expression (&md.qp); |
| 6549 | if (*input_line_pointer++ != ')') |
| 6550 | { |
| 6551 | as_bad ("Expected ')'"); |
| 6552 | return 0; |
| 6553 | } |
| 6554 | if (md.qp.X_op != O_register) |
| 6555 | { |
| 6556 | as_bad ("Qualifying predicate expected"); |
| 6557 | return 0; |
| 6558 | } |
| 6559 | if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) |
| 6560 | { |
| 6561 | as_bad ("Predicate register expected"); |
| 6562 | return 0; |
| 6563 | } |
| 6564 | return 1; |
| 6565 | |
| 6566 | case '{': |
| 6567 | if (md.manual_bundling) |
| 6568 | as_warn ("Found '{' when manual bundling is already turned on"); |
| 6569 | else |
| 6570 | CURR_SLOT.manual_bundling_on = 1; |
| 6571 | md.manual_bundling = 1; |
| 6572 | |
| 6573 | /* Bundling is only acceptable in explicit mode |
| 6574 | or when in default automatic mode. */ |
| 6575 | if (md.detect_dv && !md.explicit_mode) |
| 6576 | { |
| 6577 | if (!md.mode_explicitly_set |
| 6578 | && !md.default_explicit_mode) |
| 6579 | dot_dv_mode ('E'); |
| 6580 | else |
| 6581 | as_warn (_("Found '{' after explicit switch to automatic mode")); |
| 6582 | } |
| 6583 | return 1; |
| 6584 | |
| 6585 | case '}': |
| 6586 | if (!md.manual_bundling) |
| 6587 | as_warn ("Found '}' when manual bundling is off"); |
| 6588 | else |
| 6589 | PREV_SLOT.manual_bundling_off = 1; |
| 6590 | md.manual_bundling = 0; |
| 6591 | |
| 6592 | /* switch back to automatic mode, if applicable */ |
| 6593 | if (md.detect_dv |
| 6594 | && md.explicit_mode |
| 6595 | && !md.mode_explicitly_set |
| 6596 | && !md.default_explicit_mode) |
| 6597 | dot_dv_mode ('A'); |
| 6598 | |
| 6599 | /* Allow '{' to follow on the same line. We also allow ";;", but that |
| 6600 | happens automatically because ';' is an end of line marker. */ |
| 6601 | SKIP_WHITESPACE (); |
| 6602 | if (input_line_pointer[0] == '{') |
| 6603 | { |
| 6604 | input_line_pointer++; |
| 6605 | return ia64_unrecognized_line ('{'); |
| 6606 | } |
| 6607 | |
| 6608 | demand_empty_rest_of_line (); |
| 6609 | return 1; |
| 6610 | |
| 6611 | case '[': |
| 6612 | { |
| 6613 | char *s; |
| 6614 | char c; |
| 6615 | symbolS *tag; |
| 6616 | |
| 6617 | if (md.qp.X_op == O_register) |
| 6618 | { |
| 6619 | as_bad ("Tag must come before qualifying predicate."); |
| 6620 | return 0; |
| 6621 | } |
| 6622 | s = input_line_pointer; |
| 6623 | c = get_symbol_end (); |
| 6624 | if (c != ':') |
| 6625 | { |
| 6626 | /* Put ':' back for error messages' sake. */ |
| 6627 | *input_line_pointer++ = ':'; |
| 6628 | as_bad ("Expected ':'"); |
| 6629 | return 0; |
| 6630 | } |
| 6631 | defining_tag = 1; |
| 6632 | tag = colon (s); |
| 6633 | defining_tag = 0; |
| 6634 | /* Put ':' back for error messages' sake. */ |
| 6635 | *input_line_pointer++ = ':'; |
| 6636 | if (*input_line_pointer++ != ']') |
| 6637 | { |
| 6638 | as_bad ("Expected ']'"); |
| 6639 | return 0; |
| 6640 | } |
| 6641 | if (! tag) |
| 6642 | { |
| 6643 | as_bad ("Tag name expected"); |
| 6644 | return 0; |
| 6645 | } |
| 6646 | return 1; |
| 6647 | } |
| 6648 | |
| 6649 | default: |
| 6650 | break; |
| 6651 | } |
| 6652 | |
| 6653 | /* Not a valid line. */ |
| 6654 | return 0; |
| 6655 | } |
| 6656 | |
| 6657 | void |
| 6658 | ia64_frob_label (sym) |
| 6659 | struct symbol *sym; |
| 6660 | { |
| 6661 | struct label_fix *fix; |
| 6662 | |
| 6663 | /* Tags need special handling since they are not bundle breaks like |
| 6664 | labels. */ |
| 6665 | if (defining_tag) |
| 6666 | { |
| 6667 | fix = obstack_alloc (¬es, sizeof (*fix)); |
| 6668 | fix->sym = sym; |
| 6669 | fix->next = CURR_SLOT.tag_fixups; |
| 6670 | CURR_SLOT.tag_fixups = fix; |
| 6671 | |
| 6672 | return; |
| 6673 | } |
| 6674 | |
| 6675 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
| 6676 | { |
| 6677 | md.last_text_seg = now_seg; |
| 6678 | fix = obstack_alloc (¬es, sizeof (*fix)); |
| 6679 | fix->sym = sym; |
| 6680 | fix->next = CURR_SLOT.label_fixups; |
| 6681 | CURR_SLOT.label_fixups = fix; |
| 6682 | |
| 6683 | /* Keep track of how many code entry points we've seen. */ |
| 6684 | if (md.path == md.maxpaths) |
| 6685 | { |
| 6686 | md.maxpaths += 20; |
| 6687 | md.entry_labels = (const char **) |
| 6688 | xrealloc ((void *) md.entry_labels, |
| 6689 | md.maxpaths * sizeof (char *)); |
| 6690 | } |
| 6691 | md.entry_labels[md.path++] = S_GET_NAME (sym); |
| 6692 | } |
| 6693 | } |
| 6694 | |
| 6695 | void |
| 6696 | ia64_flush_pending_output () |
| 6697 | { |
| 6698 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
| 6699 | { |
| 6700 | /* ??? This causes many unnecessary stop bits to be emitted. |
| 6701 | Unfortunately, it isn't clear if it is safe to remove this. */ |
| 6702 | insn_group_break (1, 0, 0); |
| 6703 | ia64_flush_insns (); |
| 6704 | } |
| 6705 | } |
| 6706 | |
| 6707 | /* Do ia64-specific expression optimization. All that's done here is |
| 6708 | to transform index expressions that are either due to the indexing |
| 6709 | of rotating registers or due to the indexing of indirect register |
| 6710 | sets. */ |
| 6711 | int |
| 6712 | ia64_optimize_expr (l, op, r) |
| 6713 | expressionS *l; |
| 6714 | operatorT op; |
| 6715 | expressionS *r; |
| 6716 | { |
| 6717 | unsigned num_regs; |
| 6718 | |
| 6719 | if (op == O_index) |
| 6720 | { |
| 6721 | if (l->X_op == O_register && r->X_op == O_constant) |
| 6722 | { |
| 6723 | num_regs = (l->X_add_number >> 16); |
| 6724 | if ((unsigned) r->X_add_number >= num_regs) |
| 6725 | { |
| 6726 | if (!num_regs) |
| 6727 | as_bad ("No current frame"); |
| 6728 | else |
| 6729 | as_bad ("Index out of range 0..%u", num_regs - 1); |
| 6730 | r->X_add_number = 0; |
| 6731 | } |
| 6732 | l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; |
| 6733 | return 1; |
| 6734 | } |
| 6735 | else if (l->X_op == O_register && r->X_op == O_register) |
| 6736 | { |
| 6737 | if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR |
| 6738 | || l->X_add_number == IND_MEM) |
| 6739 | { |
| 6740 | as_bad ("Indirect register set name expected"); |
| 6741 | l->X_add_number = IND_CPUID; |
| 6742 | } |
| 6743 | l->X_op = O_index; |
| 6744 | l->X_op_symbol = md.regsym[l->X_add_number]; |
| 6745 | l->X_add_number = r->X_add_number; |
| 6746 | return 1; |
| 6747 | } |
| 6748 | } |
| 6749 | return 0; |
| 6750 | } |
| 6751 | |
| 6752 | int |
| 6753 | ia64_parse_name (name, e) |
| 6754 | char *name; |
| 6755 | expressionS *e; |
| 6756 | { |
| 6757 | struct const_desc *cdesc; |
| 6758 | struct dynreg *dr = 0; |
| 6759 | unsigned int regnum; |
| 6760 | struct symbol *sym; |
| 6761 | char *end; |
| 6762 | |
| 6763 | /* first see if NAME is a known register name: */ |
| 6764 | sym = hash_find (md.reg_hash, name); |
| 6765 | if (sym) |
| 6766 | { |
| 6767 | e->X_op = O_register; |
| 6768 | e->X_add_number = S_GET_VALUE (sym); |
| 6769 | return 1; |
| 6770 | } |
| 6771 | |
| 6772 | cdesc = hash_find (md.const_hash, name); |
| 6773 | if (cdesc) |
| 6774 | { |
| 6775 | e->X_op = O_constant; |
| 6776 | e->X_add_number = cdesc->value; |
| 6777 | return 1; |
| 6778 | } |
| 6779 | |
| 6780 | /* check for inN, locN, or outN: */ |
| 6781 | switch (name[0]) |
| 6782 | { |
| 6783 | case 'i': |
| 6784 | if (name[1] == 'n' && isdigit (name[2])) |
| 6785 | { |
| 6786 | dr = &md.in; |
| 6787 | name += 2; |
| 6788 | } |
| 6789 | break; |
| 6790 | |
| 6791 | case 'l': |
| 6792 | if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3])) |
| 6793 | { |
| 6794 | dr = &md.loc; |
| 6795 | name += 3; |
| 6796 | } |
| 6797 | break; |
| 6798 | |
| 6799 | case 'o': |
| 6800 | if (name[1] == 'u' && name[2] == 't' && isdigit (name[3])) |
| 6801 | { |
| 6802 | dr = &md.out; |
| 6803 | name += 3; |
| 6804 | } |
| 6805 | break; |
| 6806 | |
| 6807 | default: |
| 6808 | break; |
| 6809 | } |
| 6810 | |
| 6811 | if (dr) |
| 6812 | { |
| 6813 | /* The name is inN, locN, or outN; parse the register number. */ |
| 6814 | regnum = strtoul (name, &end, 10); |
| 6815 | if (end > name && *end == '\0') |
| 6816 | { |
| 6817 | if ((unsigned) regnum >= dr->num_regs) |
| 6818 | { |
| 6819 | if (!dr->num_regs) |
| 6820 | as_bad ("No current frame"); |
| 6821 | else |
| 6822 | as_bad ("Register number out of range 0..%u", |
| 6823 | dr->num_regs - 1); |
| 6824 | regnum = 0; |
| 6825 | } |
| 6826 | e->X_op = O_register; |
| 6827 | e->X_add_number = dr->base + regnum; |
| 6828 | return 1; |
| 6829 | } |
| 6830 | } |
| 6831 | |
| 6832 | if ((dr = hash_find (md.dynreg_hash, name))) |
| 6833 | { |
| 6834 | /* We've got ourselves the name of a rotating register set. |
| 6835 | Store the base register number in the low 16 bits of |
| 6836 | X_add_number and the size of the register set in the top 16 |
| 6837 | bits. */ |
| 6838 | e->X_op = O_register; |
| 6839 | e->X_add_number = dr->base | (dr->num_regs << 16); |
| 6840 | return 1; |
| 6841 | } |
| 6842 | return 0; |
| 6843 | } |
| 6844 | |
| 6845 | /* Remove the '#' suffix that indicates a symbol as opposed to a register. */ |
| 6846 | |
| 6847 | char * |
| 6848 | ia64_canonicalize_symbol_name (name) |
| 6849 | char *name; |
| 6850 | { |
| 6851 | size_t len = strlen (name); |
| 6852 | if (len > 1 && name[len - 1] == '#') |
| 6853 | name[len - 1] = '\0'; |
| 6854 | return name; |
| 6855 | } |
| 6856 | |
| 6857 | static int |
| 6858 | is_conditional_branch (idesc) |
| 6859 | struct ia64_opcode *idesc; |
| 6860 | { |
| 6861 | return (strncmp (idesc->name, "br", 2) == 0 |
| 6862 | && (strcmp (idesc->name, "br") == 0 |
| 6863 | || strncmp (idesc->name, "br.cond", 7) == 0 |
| 6864 | || strncmp (idesc->name, "br.call", 7) == 0 |
| 6865 | || strncmp (idesc->name, "br.ret", 6) == 0 |
| 6866 | || strcmp (idesc->name, "brl") == 0 |
| 6867 | || strncmp (idesc->name, "brl.cond", 7) == 0 |
| 6868 | || strncmp (idesc->name, "brl.call", 7) == 0 |
| 6869 | || strncmp (idesc->name, "brl.ret", 6) == 0)); |
| 6870 | } |
| 6871 | |
| 6872 | /* Return whether the given opcode is a taken branch. If there's any doubt, |
| 6873 | returns zero. */ |
| 6874 | |
| 6875 | static int |
| 6876 | is_taken_branch (idesc) |
| 6877 | struct ia64_opcode *idesc; |
| 6878 | { |
| 6879 | return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) |
| 6880 | || strncmp (idesc->name, "br.ia", 5) == 0); |
| 6881 | } |
| 6882 | |
| 6883 | /* Return whether the given opcode is an interruption or rfi. If there's any |
| 6884 | doubt, returns zero. */ |
| 6885 | |
| 6886 | static int |
| 6887 | is_interruption_or_rfi (idesc) |
| 6888 | struct ia64_opcode *idesc; |
| 6889 | { |
| 6890 | if (strcmp (idesc->name, "rfi") == 0) |
| 6891 | return 1; |
| 6892 | return 0; |
| 6893 | } |
| 6894 | |
| 6895 | /* Returns the index of the given dependency in the opcode's list of chks, or |
| 6896 | -1 if there is no dependency. */ |
| 6897 | |
| 6898 | static int |
| 6899 | depends_on (depind, idesc) |
| 6900 | int depind; |
| 6901 | struct ia64_opcode *idesc; |
| 6902 | { |
| 6903 | int i; |
| 6904 | const struct ia64_opcode_dependency *dep = idesc->dependencies; |
| 6905 | for (i = 0; i < dep->nchks; i++) |
| 6906 | { |
| 6907 | if (depind == DEP (dep->chks[i])) |
| 6908 | return i; |
| 6909 | } |
| 6910 | return -1; |
| 6911 | } |
| 6912 | |
| 6913 | /* Determine a set of specific resources used for a particular resource |
| 6914 | class. Returns the number of specific resources identified For those |
| 6915 | cases which are not determinable statically, the resource returned is |
| 6916 | marked nonspecific. |
| 6917 | |
| 6918 | Meanings of value in 'NOTE': |
| 6919 | 1) only read/write when the register number is explicitly encoded in the |
| 6920 | insn. |
| 6921 | 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only |
| 6922 | accesses CFM when qualifying predicate is in the rotating region. |
| 6923 | 3) general register value is used to specify an indirect register; not |
| 6924 | determinable statically. |
| 6925 | 4) only read the given resource when bits 7:0 of the indirect index |
| 6926 | register value does not match the register number of the resource; not |
| 6927 | determinable statically. |
| 6928 | 5) all rules are implementation specific. |
| 6929 | 6) only when both the index specified by the reader and the index specified |
| 6930 | by the writer have the same value in bits 63:61; not determinable |
| 6931 | statically. |
| 6932 | 7) only access the specified resource when the corresponding mask bit is |
| 6933 | set |
| 6934 | 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is |
| 6935 | only read when these insns reference FR2-31 |
| 6936 | 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only |
| 6937 | written when these insns write FR32-127 |
| 6938 | 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the |
| 6939 | instruction |
| 6940 | 11) The target predicates are written independently of PR[qp], but source |
| 6941 | registers are only read if PR[qp] is true. Since the state of PR[qp] |
| 6942 | cannot statically be determined, all source registers are marked used. |
| 6943 | 12) This insn only reads the specified predicate register when that |
| 6944 | register is the PR[qp]. |
| 6945 | 13) This reference to ld-c only applies to teh GR whose value is loaded |
| 6946 | with data returned from memory, not the post-incremented address register. |
| 6947 | 14) The RSE resource includes the implementation-specific RSE internal |
| 6948 | state resources. At least one (and possibly more) of these resources are |
| 6949 | read by each instruction listed in IC:rse-readers. At least one (and |
| 6950 | possibly more) of these resources are written by each insn listed in |
| 6951 | IC:rse-writers. |
| 6952 | 15+16) Represents reserved instructions, which the assembler does not |
| 6953 | generate. |
| 6954 | |
| 6955 | Memory resources (i.e. locations in memory) are *not* marked or tracked by |
| 6956 | this code; there are no dependency violations based on memory access. |
| 6957 | */ |
| 6958 | |
| 6959 | #define MAX_SPECS 256 |
| 6960 | #define DV_CHK 1 |
| 6961 | #define DV_REG 0 |
| 6962 | |
| 6963 | static int |
| 6964 | specify_resource (dep, idesc, type, specs, note, path) |
| 6965 | const struct ia64_dependency *dep; |
| 6966 | struct ia64_opcode *idesc; |
| 6967 | int type; /* is this a DV chk or a DV reg? */ |
| 6968 | struct rsrc specs[MAX_SPECS]; /* returned specific resources */ |
| 6969 | int note; /* resource note for this insn's usage */ |
| 6970 | int path; /* which execution path to examine */ |
| 6971 | { |
| 6972 | int count = 0; |
| 6973 | int i; |
| 6974 | int rsrc_write = 0; |
| 6975 | struct rsrc tmpl; |
| 6976 | |
| 6977 | if (dep->mode == IA64_DV_WAW |
| 6978 | || (dep->mode == IA64_DV_RAW && type == DV_REG) |
| 6979 | || (dep->mode == IA64_DV_WAR && type == DV_CHK)) |
| 6980 | rsrc_write = 1; |
| 6981 | |
| 6982 | /* template for any resources we identify */ |
| 6983 | tmpl.dependency = dep; |
| 6984 | tmpl.note = note; |
| 6985 | tmpl.insn_srlz = tmpl.data_srlz = 0; |
| 6986 | tmpl.qp_regno = CURR_SLOT.qp_regno; |
| 6987 | tmpl.link_to_qp_branch = 1; |
| 6988 | tmpl.mem_offset.hint = 0; |
| 6989 | tmpl.specific = 1; |
| 6990 | tmpl.index = 0; |
| 6991 | tmpl.cmp_type = CMP_NONE; |
| 6992 | |
| 6993 | #define UNHANDLED \ |
| 6994 | as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ |
| 6995 | dep->name, idesc->name, (rsrc_write?"write":"read"), note) |
| 6996 | #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) |
| 6997 | |
| 6998 | /* we don't need to track these */ |
| 6999 | if (dep->semantics == IA64_DVS_NONE) |
| 7000 | return 0; |
| 7001 | |
| 7002 | switch (dep->specifier) |
| 7003 | { |
| 7004 | case IA64_RS_AR_K: |
| 7005 | if (note == 1) |
| 7006 | { |
| 7007 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 7008 | { |
| 7009 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7010 | if (regno >= 0 && regno <= 7) |
| 7011 | { |
| 7012 | specs[count] = tmpl; |
| 7013 | specs[count++].index = regno; |
| 7014 | } |
| 7015 | } |
| 7016 | } |
| 7017 | else if (note == 0) |
| 7018 | { |
| 7019 | for (i = 0; i < 8; i++) |
| 7020 | { |
| 7021 | specs[count] = tmpl; |
| 7022 | specs[count++].index = i; |
| 7023 | } |
| 7024 | } |
| 7025 | else |
| 7026 | { |
| 7027 | UNHANDLED; |
| 7028 | } |
| 7029 | break; |
| 7030 | |
| 7031 | case IA64_RS_AR_UNAT: |
| 7032 | /* This is a mov =AR or mov AR= instruction. */ |
| 7033 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 7034 | { |
| 7035 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7036 | if (regno == AR_UNAT) |
| 7037 | { |
| 7038 | specs[count++] = tmpl; |
| 7039 | } |
| 7040 | } |
| 7041 | else |
| 7042 | { |
| 7043 | /* This is a spill/fill, or other instruction that modifies the |
| 7044 | unat register. */ |
| 7045 | |
| 7046 | /* Unless we can determine the specific bits used, mark the whole |
| 7047 | thing; bits 8:3 of the memory address indicate the bit used in |
| 7048 | UNAT. The .mem.offset hint may be used to eliminate a small |
| 7049 | subset of conflicts. */ |
| 7050 | specs[count] = tmpl; |
| 7051 | if (md.mem_offset.hint) |
| 7052 | { |
| 7053 | if (md.debug_dv) |
| 7054 | fprintf (stderr, " Using hint for spill/fill\n"); |
| 7055 | /* The index isn't actually used, just set it to something |
| 7056 | approximating the bit index. */ |
| 7057 | specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; |
| 7058 | specs[count].mem_offset.hint = 1; |
| 7059 | specs[count].mem_offset.offset = md.mem_offset.offset; |
| 7060 | specs[count++].mem_offset.base = md.mem_offset.base; |
| 7061 | } |
| 7062 | else |
| 7063 | { |
| 7064 | specs[count++].specific = 0; |
| 7065 | } |
| 7066 | } |
| 7067 | break; |
| 7068 | |
| 7069 | case IA64_RS_AR: |
| 7070 | if (note == 1) |
| 7071 | { |
| 7072 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 7073 | { |
| 7074 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7075 | if ((regno >= 8 && regno <= 15) |
| 7076 | || (regno >= 20 && regno <= 23) |
| 7077 | || (regno >= 31 && regno <= 39) |
| 7078 | || (regno >= 41 && regno <= 47) |
| 7079 | || (regno >= 67 && regno <= 111)) |
| 7080 | { |
| 7081 | specs[count] = tmpl; |
| 7082 | specs[count++].index = regno; |
| 7083 | } |
| 7084 | } |
| 7085 | } |
| 7086 | else |
| 7087 | { |
| 7088 | UNHANDLED; |
| 7089 | } |
| 7090 | break; |
| 7091 | |
| 7092 | case IA64_RS_ARb: |
| 7093 | if (note == 1) |
| 7094 | { |
| 7095 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 7096 | { |
| 7097 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7098 | if ((regno >= 48 && regno <= 63) |
| 7099 | || (regno >= 112 && regno <= 127)) |
| 7100 | { |
| 7101 | specs[count] = tmpl; |
| 7102 | specs[count++].index = regno; |
| 7103 | } |
| 7104 | } |
| 7105 | } |
| 7106 | else if (note == 0) |
| 7107 | { |
| 7108 | for (i = 48; i < 64; i++) |
| 7109 | { |
| 7110 | specs[count] = tmpl; |
| 7111 | specs[count++].index = i; |
| 7112 | } |
| 7113 | for (i = 112; i < 128; i++) |
| 7114 | { |
| 7115 | specs[count] = tmpl; |
| 7116 | specs[count++].index = i; |
| 7117 | } |
| 7118 | } |
| 7119 | else |
| 7120 | { |
| 7121 | UNHANDLED; |
| 7122 | } |
| 7123 | break; |
| 7124 | |
| 7125 | case IA64_RS_BR: |
| 7126 | if (note != 1) |
| 7127 | { |
| 7128 | UNHANDLED; |
| 7129 | } |
| 7130 | else |
| 7131 | { |
| 7132 | if (rsrc_write) |
| 7133 | { |
| 7134 | for (i = 0; i < idesc->num_outputs; i++) |
| 7135 | if (idesc->operands[i] == IA64_OPND_B1 |
| 7136 | || idesc->operands[i] == IA64_OPND_B2) |
| 7137 | { |
| 7138 | specs[count] = tmpl; |
| 7139 | specs[count++].index = |
| 7140 | CURR_SLOT.opnd[i].X_add_number - REG_BR; |
| 7141 | } |
| 7142 | } |
| 7143 | else |
| 7144 | { |
| 7145 | for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++) |
| 7146 | if (idesc->operands[i] == IA64_OPND_B1 |
| 7147 | || idesc->operands[i] == IA64_OPND_B2) |
| 7148 | { |
| 7149 | specs[count] = tmpl; |
| 7150 | specs[count++].index = |
| 7151 | CURR_SLOT.opnd[i].X_add_number - REG_BR; |
| 7152 | } |
| 7153 | } |
| 7154 | } |
| 7155 | break; |
| 7156 | |
| 7157 | case IA64_RS_CPUID: /* four or more registers */ |
| 7158 | if (note == 3) |
| 7159 | { |
| 7160 | if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) |
| 7161 | { |
| 7162 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7163 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7164 | && KNOWN (regno)) |
| 7165 | { |
| 7166 | specs[count] = tmpl; |
| 7167 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7168 | } |
| 7169 | else |
| 7170 | { |
| 7171 | specs[count] = tmpl; |
| 7172 | specs[count++].specific = 0; |
| 7173 | } |
| 7174 | } |
| 7175 | } |
| 7176 | else |
| 7177 | { |
| 7178 | UNHANDLED; |
| 7179 | } |
| 7180 | break; |
| 7181 | |
| 7182 | case IA64_RS_DBR: /* four or more registers */ |
| 7183 | if (note == 3) |
| 7184 | { |
| 7185 | if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) |
| 7186 | { |
| 7187 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7188 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7189 | && KNOWN (regno)) |
| 7190 | { |
| 7191 | specs[count] = tmpl; |
| 7192 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7193 | } |
| 7194 | else |
| 7195 | { |
| 7196 | specs[count] = tmpl; |
| 7197 | specs[count++].specific = 0; |
| 7198 | } |
| 7199 | } |
| 7200 | } |
| 7201 | else if (note == 0 && !rsrc_write) |
| 7202 | { |
| 7203 | specs[count] = tmpl; |
| 7204 | specs[count++].specific = 0; |
| 7205 | } |
| 7206 | else |
| 7207 | { |
| 7208 | UNHANDLED; |
| 7209 | } |
| 7210 | break; |
| 7211 | |
| 7212 | case IA64_RS_IBR: /* four or more registers */ |
| 7213 | if (note == 3) |
| 7214 | { |
| 7215 | if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) |
| 7216 | { |
| 7217 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7218 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7219 | && KNOWN (regno)) |
| 7220 | { |
| 7221 | specs[count] = tmpl; |
| 7222 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7223 | } |
| 7224 | else |
| 7225 | { |
| 7226 | specs[count] = tmpl; |
| 7227 | specs[count++].specific = 0; |
| 7228 | } |
| 7229 | } |
| 7230 | } |
| 7231 | else |
| 7232 | { |
| 7233 | UNHANDLED; |
| 7234 | } |
| 7235 | break; |
| 7236 | |
| 7237 | case IA64_RS_MSR: |
| 7238 | if (note == 5) |
| 7239 | { |
| 7240 | /* These are implementation specific. Force all references to |
| 7241 | conflict with all other references. */ |
| 7242 | specs[count] = tmpl; |
| 7243 | specs[count++].specific = 0; |
| 7244 | } |
| 7245 | else |
| 7246 | { |
| 7247 | UNHANDLED; |
| 7248 | } |
| 7249 | break; |
| 7250 | |
| 7251 | case IA64_RS_PKR: /* 16 or more registers */ |
| 7252 | if (note == 3 || note == 4) |
| 7253 | { |
| 7254 | if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) |
| 7255 | { |
| 7256 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7257 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7258 | && KNOWN (regno)) |
| 7259 | { |
| 7260 | if (note == 3) |
| 7261 | { |
| 7262 | specs[count] = tmpl; |
| 7263 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7264 | } |
| 7265 | else |
| 7266 | for (i = 0; i < NELEMS (gr_values); i++) |
| 7267 | { |
| 7268 | /* Uses all registers *except* the one in R3. */ |
| 7269 | if ((unsigned)i != (gr_values[regno].value & 0xFF)) |
| 7270 | { |
| 7271 | specs[count] = tmpl; |
| 7272 | specs[count++].index = i; |
| 7273 | } |
| 7274 | } |
| 7275 | } |
| 7276 | else |
| 7277 | { |
| 7278 | specs[count] = tmpl; |
| 7279 | specs[count++].specific = 0; |
| 7280 | } |
| 7281 | } |
| 7282 | } |
| 7283 | else if (note == 0) |
| 7284 | { |
| 7285 | /* probe et al. */ |
| 7286 | specs[count] = tmpl; |
| 7287 | specs[count++].specific = 0; |
| 7288 | } |
| 7289 | break; |
| 7290 | |
| 7291 | case IA64_RS_PMC: /* four or more registers */ |
| 7292 | if (note == 3) |
| 7293 | { |
| 7294 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 |
| 7295 | || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) |
| 7296 | |
| 7297 | { |
| 7298 | int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) |
| 7299 | ? 1 : !rsrc_write); |
| 7300 | int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; |
| 7301 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7302 | && KNOWN (regno)) |
| 7303 | { |
| 7304 | specs[count] = tmpl; |
| 7305 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7306 | } |
| 7307 | else |
| 7308 | { |
| 7309 | specs[count] = tmpl; |
| 7310 | specs[count++].specific = 0; |
| 7311 | } |
| 7312 | } |
| 7313 | } |
| 7314 | else |
| 7315 | { |
| 7316 | UNHANDLED; |
| 7317 | } |
| 7318 | break; |
| 7319 | |
| 7320 | case IA64_RS_PMD: /* four or more registers */ |
| 7321 | if (note == 3) |
| 7322 | { |
| 7323 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) |
| 7324 | { |
| 7325 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7326 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7327 | && KNOWN (regno)) |
| 7328 | { |
| 7329 | specs[count] = tmpl; |
| 7330 | specs[count++].index = gr_values[regno].value & 0xFF; |
| 7331 | } |
| 7332 | else |
| 7333 | { |
| 7334 | specs[count] = tmpl; |
| 7335 | specs[count++].specific = 0; |
| 7336 | } |
| 7337 | } |
| 7338 | } |
| 7339 | else |
| 7340 | { |
| 7341 | UNHANDLED; |
| 7342 | } |
| 7343 | break; |
| 7344 | |
| 7345 | case IA64_RS_RR: /* eight registers */ |
| 7346 | if (note == 6) |
| 7347 | { |
| 7348 | if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) |
| 7349 | { |
| 7350 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; |
| 7351 | if (regno >= 0 && regno < NELEMS (gr_values) |
| 7352 | && KNOWN (regno)) |
| 7353 | { |
| 7354 | specs[count] = tmpl; |
| 7355 | specs[count++].index = (gr_values[regno].value >> 61) & 0x7; |
| 7356 | } |
| 7357 | else |
| 7358 | { |
| 7359 | specs[count] = tmpl; |
| 7360 | specs[count++].specific = 0; |
| 7361 | } |
| 7362 | } |
| 7363 | } |
| 7364 | else if (note == 0 && !rsrc_write) |
| 7365 | { |
| 7366 | specs[count] = tmpl; |
| 7367 | specs[count++].specific = 0; |
| 7368 | } |
| 7369 | else |
| 7370 | { |
| 7371 | UNHANDLED; |
| 7372 | } |
| 7373 | break; |
| 7374 | |
| 7375 | case IA64_RS_CR_IRR: |
| 7376 | if (note == 0) |
| 7377 | { |
| 7378 | /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ |
| 7379 | int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; |
| 7380 | if (rsrc_write |
| 7381 | && idesc->operands[1] == IA64_OPND_CR3 |
| 7382 | && regno == CR_IVR) |
| 7383 | { |
| 7384 | for (i = 0; i < 4; i++) |
| 7385 | { |
| 7386 | specs[count] = tmpl; |
| 7387 | specs[count++].index = CR_IRR0 + i; |
| 7388 | } |
| 7389 | } |
| 7390 | } |
| 7391 | else if (note == 1) |
| 7392 | { |
| 7393 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; |
| 7394 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 |
| 7395 | && regno >= CR_IRR0 |
| 7396 | && regno <= CR_IRR3) |
| 7397 | { |
| 7398 | specs[count] = tmpl; |
| 7399 | specs[count++].index = regno; |
| 7400 | } |
| 7401 | } |
| 7402 | else |
| 7403 | { |
| 7404 | UNHANDLED; |
| 7405 | } |
| 7406 | break; |
| 7407 | |
| 7408 | case IA64_RS_CR_LRR: |
| 7409 | if (note != 1) |
| 7410 | { |
| 7411 | UNHANDLED; |
| 7412 | } |
| 7413 | else |
| 7414 | { |
| 7415 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; |
| 7416 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 |
| 7417 | && (regno == CR_LRR0 || regno == CR_LRR1)) |
| 7418 | { |
| 7419 | specs[count] = tmpl; |
| 7420 | specs[count++].index = regno; |
| 7421 | } |
| 7422 | } |
| 7423 | break; |
| 7424 | |
| 7425 | case IA64_RS_CR: |
| 7426 | if (note == 1) |
| 7427 | { |
| 7428 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) |
| 7429 | { |
| 7430 | specs[count] = tmpl; |
| 7431 | specs[count++].index = |
| 7432 | CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; |
| 7433 | } |
| 7434 | } |
| 7435 | else |
| 7436 | { |
| 7437 | UNHANDLED; |
| 7438 | } |
| 7439 | break; |
| 7440 | |
| 7441 | case IA64_RS_FR: |
| 7442 | case IA64_RS_FRb: |
| 7443 | if (note != 1) |
| 7444 | { |
| 7445 | UNHANDLED; |
| 7446 | } |
| 7447 | else if (rsrc_write) |
| 7448 | { |
| 7449 | if (dep->specifier == IA64_RS_FRb |
| 7450 | && idesc->operands[0] == IA64_OPND_F1) |
| 7451 | { |
| 7452 | specs[count] = tmpl; |
| 7453 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; |
| 7454 | } |
| 7455 | } |
| 7456 | else |
| 7457 | { |
| 7458 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) |
| 7459 | { |
| 7460 | if (idesc->operands[i] == IA64_OPND_F2 |
| 7461 | || idesc->operands[i] == IA64_OPND_F3 |
| 7462 | || idesc->operands[i] == IA64_OPND_F4) |
| 7463 | { |
| 7464 | specs[count] = tmpl; |
| 7465 | specs[count++].index = |
| 7466 | CURR_SLOT.opnd[i].X_add_number - REG_FR; |
| 7467 | } |
| 7468 | } |
| 7469 | } |
| 7470 | break; |
| 7471 | |
| 7472 | case IA64_RS_GR: |
| 7473 | if (note == 13) |
| 7474 | { |
| 7475 | /* This reference applies only to the GR whose value is loaded with |
| 7476 | data returned from memory. */ |
| 7477 | specs[count] = tmpl; |
| 7478 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; |
| 7479 | } |
| 7480 | else if (note == 1) |
| 7481 | { |
| 7482 | if (rsrc_write) |
| 7483 | { |
| 7484 | for (i = 0; i < idesc->num_outputs; i++) |
| 7485 | if (idesc->operands[i] == IA64_OPND_R1 |
| 7486 | || idesc->operands[i] == IA64_OPND_R2 |
| 7487 | || idesc->operands[i] == IA64_OPND_R3) |
| 7488 | { |
| 7489 | specs[count] = tmpl; |
| 7490 | specs[count++].index = |
| 7491 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 7492 | } |
| 7493 | if (idesc->flags & IA64_OPCODE_POSTINC) |
| 7494 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 7495 | if (idesc->operands[i] == IA64_OPND_MR3) |
| 7496 | { |
| 7497 | specs[count] = tmpl; |
| 7498 | specs[count++].index = |
| 7499 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 7500 | } |
| 7501 | } |
| 7502 | else |
| 7503 | { |
| 7504 | /* Look for anything that reads a GR. */ |
| 7505 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 7506 | { |
| 7507 | if (idesc->operands[i] == IA64_OPND_MR3 |
| 7508 | || idesc->operands[i] == IA64_OPND_CPUID_R3 |
| 7509 | || idesc->operands[i] == IA64_OPND_DBR_R3 |
| 7510 | || idesc->operands[i] == IA64_OPND_IBR_R3 |
| 7511 | || idesc->operands[i] == IA64_OPND_MSR_R3 |
| 7512 | || idesc->operands[i] == IA64_OPND_PKR_R3 |
| 7513 | || idesc->operands[i] == IA64_OPND_PMC_R3 |
| 7514 | || idesc->operands[i] == IA64_OPND_PMD_R3 |
| 7515 | || idesc->operands[i] == IA64_OPND_RR_R3 |
| 7516 | || ((i >= idesc->num_outputs) |
| 7517 | && (idesc->operands[i] == IA64_OPND_R1 |
| 7518 | || idesc->operands[i] == IA64_OPND_R2 |
| 7519 | || idesc->operands[i] == IA64_OPND_R3 |
| 7520 | /* addl source register. */ |
| 7521 | || idesc->operands[i] == IA64_OPND_R3_2))) |
| 7522 | { |
| 7523 | specs[count] = tmpl; |
| 7524 | specs[count++].index = |
| 7525 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 7526 | } |
| 7527 | } |
| 7528 | } |
| 7529 | } |
| 7530 | else |
| 7531 | { |
| 7532 | UNHANDLED; |
| 7533 | } |
| 7534 | break; |
| 7535 | |
| 7536 | /* This is the same as IA64_RS_PRr, except that the register range is |
| 7537 | from 1 - 15, and there are no rotating register reads/writes here. */ |
| 7538 | case IA64_RS_PR: |
| 7539 | if (note == 0) |
| 7540 | { |
| 7541 | for (i = 1; i < 16; i++) |
| 7542 | { |
| 7543 | specs[count] = tmpl; |
| 7544 | specs[count++].index = i; |
| 7545 | } |
| 7546 | } |
| 7547 | else if (note == 7) |
| 7548 | { |
| 7549 | valueT mask = 0; |
| 7550 | /* Mark only those registers indicated by the mask. */ |
| 7551 | if (rsrc_write) |
| 7552 | { |
| 7553 | mask = CURR_SLOT.opnd[2].X_add_number; |
| 7554 | for (i = 1; i < 16; i++) |
| 7555 | if (mask & ((valueT) 1 << i)) |
| 7556 | { |
| 7557 | specs[count] = tmpl; |
| 7558 | specs[count++].index = i; |
| 7559 | } |
| 7560 | } |
| 7561 | else |
| 7562 | { |
| 7563 | UNHANDLED; |
| 7564 | } |
| 7565 | } |
| 7566 | else if (note == 11) /* note 11 implies note 1 as well */ |
| 7567 | { |
| 7568 | if (rsrc_write) |
| 7569 | { |
| 7570 | for (i = 0; i < idesc->num_outputs; i++) |
| 7571 | { |
| 7572 | if (idesc->operands[i] == IA64_OPND_P1 |
| 7573 | || idesc->operands[i] == IA64_OPND_P2) |
| 7574 | { |
| 7575 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; |
| 7576 | if (regno >= 1 && regno < 16) |
| 7577 | { |
| 7578 | specs[count] = tmpl; |
| 7579 | specs[count++].index = regno; |
| 7580 | } |
| 7581 | } |
| 7582 | } |
| 7583 | } |
| 7584 | else |
| 7585 | { |
| 7586 | UNHANDLED; |
| 7587 | } |
| 7588 | } |
| 7589 | else if (note == 12) |
| 7590 | { |
| 7591 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) |
| 7592 | { |
| 7593 | specs[count] = tmpl; |
| 7594 | specs[count++].index = CURR_SLOT.qp_regno; |
| 7595 | } |
| 7596 | } |
| 7597 | else if (note == 1) |
| 7598 | { |
| 7599 | if (rsrc_write) |
| 7600 | { |
| 7601 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
| 7602 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
| 7603 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; |
| 7604 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; |
| 7605 | |
| 7606 | if ((idesc->operands[0] == IA64_OPND_P1 |
| 7607 | || idesc->operands[0] == IA64_OPND_P2) |
| 7608 | && p1 >= 1 && p1 < 16) |
| 7609 | { |
| 7610 | specs[count] = tmpl; |
| 7611 | specs[count].cmp_type = |
| 7612 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
| 7613 | specs[count++].index = p1; |
| 7614 | } |
| 7615 | if ((idesc->operands[1] == IA64_OPND_P1 |
| 7616 | || idesc->operands[1] == IA64_OPND_P2) |
| 7617 | && p2 >= 1 && p2 < 16) |
| 7618 | { |
| 7619 | specs[count] = tmpl; |
| 7620 | specs[count].cmp_type = |
| 7621 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
| 7622 | specs[count++].index = p2; |
| 7623 | } |
| 7624 | } |
| 7625 | else |
| 7626 | { |
| 7627 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) |
| 7628 | { |
| 7629 | specs[count] = tmpl; |
| 7630 | specs[count++].index = CURR_SLOT.qp_regno; |
| 7631 | } |
| 7632 | if (idesc->operands[1] == IA64_OPND_PR) |
| 7633 | { |
| 7634 | for (i = 1; i < 16; i++) |
| 7635 | { |
| 7636 | specs[count] = tmpl; |
| 7637 | specs[count++].index = i; |
| 7638 | } |
| 7639 | } |
| 7640 | } |
| 7641 | } |
| 7642 | else |
| 7643 | { |
| 7644 | UNHANDLED; |
| 7645 | } |
| 7646 | break; |
| 7647 | |
| 7648 | /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are |
| 7649 | simplified cases of this. */ |
| 7650 | case IA64_RS_PRr: |
| 7651 | if (note == 0) |
| 7652 | { |
| 7653 | for (i = 16; i < 63; i++) |
| 7654 | { |
| 7655 | specs[count] = tmpl; |
| 7656 | specs[count++].index = i; |
| 7657 | } |
| 7658 | } |
| 7659 | else if (note == 7) |
| 7660 | { |
| 7661 | valueT mask = 0; |
| 7662 | /* Mark only those registers indicated by the mask. */ |
| 7663 | if (rsrc_write |
| 7664 | && idesc->operands[0] == IA64_OPND_PR) |
| 7665 | { |
| 7666 | mask = CURR_SLOT.opnd[2].X_add_number; |
| 7667 | if (mask & ((valueT) 1<<16)) |
| 7668 | for (i = 16; i < 63; i++) |
| 7669 | { |
| 7670 | specs[count] = tmpl; |
| 7671 | specs[count++].index = i; |
| 7672 | } |
| 7673 | } |
| 7674 | else if (rsrc_write |
| 7675 | && idesc->operands[0] == IA64_OPND_PR_ROT) |
| 7676 | { |
| 7677 | for (i = 16; i < 63; i++) |
| 7678 | { |
| 7679 | specs[count] = tmpl; |
| 7680 | specs[count++].index = i; |
| 7681 | } |
| 7682 | } |
| 7683 | else |
| 7684 | { |
| 7685 | UNHANDLED; |
| 7686 | } |
| 7687 | } |
| 7688 | else if (note == 11) /* note 11 implies note 1 as well */ |
| 7689 | { |
| 7690 | if (rsrc_write) |
| 7691 | { |
| 7692 | for (i = 0; i < idesc->num_outputs; i++) |
| 7693 | { |
| 7694 | if (idesc->operands[i] == IA64_OPND_P1 |
| 7695 | || idesc->operands[i] == IA64_OPND_P2) |
| 7696 | { |
| 7697 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; |
| 7698 | if (regno >= 16 && regno < 63) |
| 7699 | { |
| 7700 | specs[count] = tmpl; |
| 7701 | specs[count++].index = regno; |
| 7702 | } |
| 7703 | } |
| 7704 | } |
| 7705 | } |
| 7706 | else |
| 7707 | { |
| 7708 | UNHANDLED; |
| 7709 | } |
| 7710 | } |
| 7711 | else if (note == 12) |
| 7712 | { |
| 7713 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
| 7714 | { |
| 7715 | specs[count] = tmpl; |
| 7716 | specs[count++].index = CURR_SLOT.qp_regno; |
| 7717 | } |
| 7718 | } |
| 7719 | else if (note == 1) |
| 7720 | { |
| 7721 | if (rsrc_write) |
| 7722 | { |
| 7723 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
| 7724 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
| 7725 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; |
| 7726 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; |
| 7727 | |
| 7728 | if ((idesc->operands[0] == IA64_OPND_P1 |
| 7729 | || idesc->operands[0] == IA64_OPND_P2) |
| 7730 | && p1 >= 16 && p1 < 63) |
| 7731 | { |
| 7732 | specs[count] = tmpl; |
| 7733 | specs[count].cmp_type = |
| 7734 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
| 7735 | specs[count++].index = p1; |
| 7736 | } |
| 7737 | if ((idesc->operands[1] == IA64_OPND_P1 |
| 7738 | || idesc->operands[1] == IA64_OPND_P2) |
| 7739 | && p2 >= 16 && p2 < 63) |
| 7740 | { |
| 7741 | specs[count] = tmpl; |
| 7742 | specs[count].cmp_type = |
| 7743 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
| 7744 | specs[count++].index = p2; |
| 7745 | } |
| 7746 | } |
| 7747 | else |
| 7748 | { |
| 7749 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
| 7750 | { |
| 7751 | specs[count] = tmpl; |
| 7752 | specs[count++].index = CURR_SLOT.qp_regno; |
| 7753 | } |
| 7754 | if (idesc->operands[1] == IA64_OPND_PR) |
| 7755 | { |
| 7756 | for (i = 16; i < 63; i++) |
| 7757 | { |
| 7758 | specs[count] = tmpl; |
| 7759 | specs[count++].index = i; |
| 7760 | } |
| 7761 | } |
| 7762 | } |
| 7763 | } |
| 7764 | else |
| 7765 | { |
| 7766 | UNHANDLED; |
| 7767 | } |
| 7768 | break; |
| 7769 | |
| 7770 | case IA64_RS_PSR: |
| 7771 | /* Verify that the instruction is using the PSR bit indicated in |
| 7772 | dep->regindex. */ |
| 7773 | if (note == 0) |
| 7774 | { |
| 7775 | if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) |
| 7776 | { |
| 7777 | if (dep->regindex < 6) |
| 7778 | { |
| 7779 | specs[count++] = tmpl; |
| 7780 | } |
| 7781 | } |
| 7782 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) |
| 7783 | { |
| 7784 | if (dep->regindex < 32 |
| 7785 | || dep->regindex == 35 |
| 7786 | || dep->regindex == 36 |
| 7787 | || (!rsrc_write && dep->regindex == PSR_CPL)) |
| 7788 | { |
| 7789 | specs[count++] = tmpl; |
| 7790 | } |
| 7791 | } |
| 7792 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) |
| 7793 | { |
| 7794 | if (dep->regindex < 32 |
| 7795 | || dep->regindex == 35 |
| 7796 | || dep->regindex == 36 |
| 7797 | || (rsrc_write && dep->regindex == PSR_CPL)) |
| 7798 | { |
| 7799 | specs[count++] = tmpl; |
| 7800 | } |
| 7801 | } |
| 7802 | else |
| 7803 | { |
| 7804 | /* Several PSR bits have very specific dependencies. */ |
| 7805 | switch (dep->regindex) |
| 7806 | { |
| 7807 | default: |
| 7808 | specs[count++] = tmpl; |
| 7809 | break; |
| 7810 | case PSR_IC: |
| 7811 | if (rsrc_write) |
| 7812 | { |
| 7813 | specs[count++] = tmpl; |
| 7814 | } |
| 7815 | else |
| 7816 | { |
| 7817 | /* Only certain CR accesses use PSR.ic */ |
| 7818 | if (idesc->operands[0] == IA64_OPND_CR3 |
| 7819 | || idesc->operands[1] == IA64_OPND_CR3) |
| 7820 | { |
| 7821 | int index = |
| 7822 | ((idesc->operands[0] == IA64_OPND_CR3) |
| 7823 | ? 0 : 1); |
| 7824 | int regno = |
| 7825 | CURR_SLOT.opnd[index].X_add_number - REG_CR; |
| 7826 | |
| 7827 | switch (regno) |
| 7828 | { |
| 7829 | default: |
| 7830 | break; |
| 7831 | case CR_ITIR: |
| 7832 | case CR_IFS: |
| 7833 | case CR_IIM: |
| 7834 | case CR_IIP: |
| 7835 | case CR_IPSR: |
| 7836 | case CR_ISR: |
| 7837 | case CR_IFA: |
| 7838 | case CR_IHA: |
| 7839 | case CR_IIPA: |
| 7840 | specs[count++] = tmpl; |
| 7841 | break; |
| 7842 | } |
| 7843 | } |
| 7844 | } |
| 7845 | break; |
| 7846 | case PSR_CPL: |
| 7847 | if (rsrc_write) |
| 7848 | { |
| 7849 | specs[count++] = tmpl; |
| 7850 | } |
| 7851 | else |
| 7852 | { |
| 7853 | /* Only some AR accesses use cpl */ |
| 7854 | if (idesc->operands[0] == IA64_OPND_AR3 |
| 7855 | || idesc->operands[1] == IA64_OPND_AR3) |
| 7856 | { |
| 7857 | int index = |
| 7858 | ((idesc->operands[0] == IA64_OPND_AR3) |
| 7859 | ? 0 : 1); |
| 7860 | int regno = |
| 7861 | CURR_SLOT.opnd[index].X_add_number - REG_AR; |
| 7862 | |
| 7863 | if (regno == AR_ITC |
| 7864 | || (index == 0 |
| 7865 | && (regno == AR_ITC |
| 7866 | || regno == AR_RSC |
| 7867 | || (regno >= AR_K0 |
| 7868 | && regno <= AR_K7)))) |
| 7869 | { |
| 7870 | specs[count++] = tmpl; |
| 7871 | } |
| 7872 | } |
| 7873 | else |
| 7874 | { |
| 7875 | specs[count++] = tmpl; |
| 7876 | } |
| 7877 | break; |
| 7878 | } |
| 7879 | } |
| 7880 | } |
| 7881 | } |
| 7882 | else if (note == 7) |
| 7883 | { |
| 7884 | valueT mask = 0; |
| 7885 | if (idesc->operands[0] == IA64_OPND_IMMU24) |
| 7886 | { |
| 7887 | mask = CURR_SLOT.opnd[0].X_add_number; |
| 7888 | } |
| 7889 | else |
| 7890 | { |
| 7891 | UNHANDLED; |
| 7892 | } |
| 7893 | if (mask & ((valueT) 1 << dep->regindex)) |
| 7894 | { |
| 7895 | specs[count++] = tmpl; |
| 7896 | } |
| 7897 | } |
| 7898 | else if (note == 8) |
| 7899 | { |
| 7900 | int min = dep->regindex == PSR_DFL ? 2 : 32; |
| 7901 | int max = dep->regindex == PSR_DFL ? 31 : 127; |
| 7902 | /* dfh is read on FR32-127; dfl is read on FR2-31 */ |
| 7903 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 7904 | { |
| 7905 | if (idesc->operands[i] == IA64_OPND_F1 |
| 7906 | || idesc->operands[i] == IA64_OPND_F2 |
| 7907 | || idesc->operands[i] == IA64_OPND_F3 |
| 7908 | || idesc->operands[i] == IA64_OPND_F4) |
| 7909 | { |
| 7910 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; |
| 7911 | if (reg >= min && reg <= max) |
| 7912 | { |
| 7913 | specs[count++] = tmpl; |
| 7914 | } |
| 7915 | } |
| 7916 | } |
| 7917 | } |
| 7918 | else if (note == 9) |
| 7919 | { |
| 7920 | int min = dep->regindex == PSR_MFL ? 2 : 32; |
| 7921 | int max = dep->regindex == PSR_MFL ? 31 : 127; |
| 7922 | /* mfh is read on writes to FR32-127; mfl is read on writes to |
| 7923 | FR2-31 */ |
| 7924 | for (i = 0; i < idesc->num_outputs; i++) |
| 7925 | { |
| 7926 | if (idesc->operands[i] == IA64_OPND_F1) |
| 7927 | { |
| 7928 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; |
| 7929 | if (reg >= min && reg <= max) |
| 7930 | { |
| 7931 | specs[count++] = tmpl; |
| 7932 | } |
| 7933 | } |
| 7934 | } |
| 7935 | } |
| 7936 | else if (note == 10) |
| 7937 | { |
| 7938 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 7939 | { |
| 7940 | if (idesc->operands[i] == IA64_OPND_R1 |
| 7941 | || idesc->operands[i] == IA64_OPND_R2 |
| 7942 | || idesc->operands[i] == IA64_OPND_R3) |
| 7943 | { |
| 7944 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 7945 | if (regno >= 16 && regno <= 31) |
| 7946 | { |
| 7947 | specs[count++] = tmpl; |
| 7948 | } |
| 7949 | } |
| 7950 | } |
| 7951 | } |
| 7952 | else |
| 7953 | { |
| 7954 | UNHANDLED; |
| 7955 | } |
| 7956 | break; |
| 7957 | |
| 7958 | case IA64_RS_AR_FPSR: |
| 7959 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) |
| 7960 | { |
| 7961 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7962 | if (regno == AR_FPSR) |
| 7963 | { |
| 7964 | specs[count++] = tmpl; |
| 7965 | } |
| 7966 | } |
| 7967 | else |
| 7968 | { |
| 7969 | specs[count++] = tmpl; |
| 7970 | } |
| 7971 | break; |
| 7972 | |
| 7973 | case IA64_RS_ARX: |
| 7974 | /* Handle all AR[REG] resources */ |
| 7975 | if (note == 0 || note == 1) |
| 7976 | { |
| 7977 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; |
| 7978 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 |
| 7979 | && regno == dep->regindex) |
| 7980 | { |
| 7981 | specs[count++] = tmpl; |
| 7982 | } |
| 7983 | /* other AR[REG] resources may be affected by AR accesses */ |
| 7984 | else if (idesc->operands[0] == IA64_OPND_AR3) |
| 7985 | { |
| 7986 | /* AR[] writes */ |
| 7987 | regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; |
| 7988 | switch (dep->regindex) |
| 7989 | { |
| 7990 | default: |
| 7991 | break; |
| 7992 | case AR_BSP: |
| 7993 | case AR_RNAT: |
| 7994 | if (regno == AR_BSPSTORE) |
| 7995 | { |
| 7996 | specs[count++] = tmpl; |
| 7997 | } |
| 7998 | case AR_RSC: |
| 7999 | if (!rsrc_write && |
| 8000 | (regno == AR_BSPSTORE |
| 8001 | || regno == AR_RNAT)) |
| 8002 | { |
| 8003 | specs[count++] = tmpl; |
| 8004 | } |
| 8005 | break; |
| 8006 | } |
| 8007 | } |
| 8008 | else if (idesc->operands[1] == IA64_OPND_AR3) |
| 8009 | { |
| 8010 | /* AR[] reads */ |
| 8011 | regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; |
| 8012 | switch (dep->regindex) |
| 8013 | { |
| 8014 | default: |
| 8015 | break; |
| 8016 | case AR_RSC: |
| 8017 | if (regno == AR_BSPSTORE || regno == AR_RNAT) |
| 8018 | { |
| 8019 | specs[count++] = tmpl; |
| 8020 | } |
| 8021 | break; |
| 8022 | } |
| 8023 | } |
| 8024 | else |
| 8025 | { |
| 8026 | specs[count++] = tmpl; |
| 8027 | } |
| 8028 | } |
| 8029 | else |
| 8030 | { |
| 8031 | UNHANDLED; |
| 8032 | } |
| 8033 | break; |
| 8034 | |
| 8035 | case IA64_RS_CRX: |
| 8036 | /* Handle all CR[REG] resources */ |
| 8037 | if (note == 0 || note == 1) |
| 8038 | { |
| 8039 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) |
| 8040 | { |
| 8041 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; |
| 8042 | if (regno == dep->regindex) |
| 8043 | { |
| 8044 | specs[count++] = tmpl; |
| 8045 | } |
| 8046 | else if (!rsrc_write) |
| 8047 | { |
| 8048 | /* Reads from CR[IVR] affect other resources. */ |
| 8049 | if (regno == CR_IVR) |
| 8050 | { |
| 8051 | if ((dep->regindex >= CR_IRR0 |
| 8052 | && dep->regindex <= CR_IRR3) |
| 8053 | || dep->regindex == CR_TPR) |
| 8054 | { |
| 8055 | specs[count++] = tmpl; |
| 8056 | } |
| 8057 | } |
| 8058 | } |
| 8059 | } |
| 8060 | else |
| 8061 | { |
| 8062 | specs[count++] = tmpl; |
| 8063 | } |
| 8064 | } |
| 8065 | else |
| 8066 | { |
| 8067 | UNHANDLED; |
| 8068 | } |
| 8069 | break; |
| 8070 | |
| 8071 | case IA64_RS_INSERVICE: |
| 8072 | /* look for write of EOI (67) or read of IVR (65) */ |
| 8073 | if ((idesc->operands[0] == IA64_OPND_CR3 |
| 8074 | && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) |
| 8075 | || (idesc->operands[1] == IA64_OPND_CR3 |
| 8076 | && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) |
| 8077 | { |
| 8078 | specs[count++] = tmpl; |
| 8079 | } |
| 8080 | break; |
| 8081 | |
| 8082 | case IA64_RS_GR0: |
| 8083 | if (note == 1) |
| 8084 | { |
| 8085 | specs[count++] = tmpl; |
| 8086 | } |
| 8087 | else |
| 8088 | { |
| 8089 | UNHANDLED; |
| 8090 | } |
| 8091 | break; |
| 8092 | |
| 8093 | case IA64_RS_CFM: |
| 8094 | if (note != 2) |
| 8095 | { |
| 8096 | specs[count++] = tmpl; |
| 8097 | } |
| 8098 | else |
| 8099 | { |
| 8100 | /* Check if any of the registers accessed are in the rotating region. |
| 8101 | mov to/from pr accesses CFM only when qp_regno is in the rotating |
| 8102 | region */ |
| 8103 | for (i = 0; i < NELEMS (idesc->operands); i++) |
| 8104 | { |
| 8105 | if (idesc->operands[i] == IA64_OPND_R1 |
| 8106 | || idesc->operands[i] == IA64_OPND_R2 |
| 8107 | || idesc->operands[i] == IA64_OPND_R3) |
| 8108 | { |
| 8109 | int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 8110 | /* Assumes that md.rot.num_regs is always valid */ |
| 8111 | if (md.rot.num_regs > 0 |
| 8112 | && num > 31 |
| 8113 | && num < 31 + md.rot.num_regs) |
| 8114 | { |
| 8115 | specs[count] = tmpl; |
| 8116 | specs[count++].specific = 0; |
| 8117 | } |
| 8118 | } |
| 8119 | else if (idesc->operands[i] == IA64_OPND_F1 |
| 8120 | || idesc->operands[i] == IA64_OPND_F2 |
| 8121 | || idesc->operands[i] == IA64_OPND_F3 |
| 8122 | || idesc->operands[i] == IA64_OPND_F4) |
| 8123 | { |
| 8124 | int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; |
| 8125 | if (num > 31) |
| 8126 | { |
| 8127 | specs[count] = tmpl; |
| 8128 | specs[count++].specific = 0; |
| 8129 | } |
| 8130 | } |
| 8131 | else if (idesc->operands[i] == IA64_OPND_P1 |
| 8132 | || idesc->operands[i] == IA64_OPND_P2) |
| 8133 | { |
| 8134 | int num = CURR_SLOT.opnd[i].X_add_number - REG_P; |
| 8135 | if (num > 15) |
| 8136 | { |
| 8137 | specs[count] = tmpl; |
| 8138 | specs[count++].specific = 0; |
| 8139 | } |
| 8140 | } |
| 8141 | } |
| 8142 | if (CURR_SLOT.qp_regno > 15) |
| 8143 | { |
| 8144 | specs[count] = tmpl; |
| 8145 | specs[count++].specific = 0; |
| 8146 | } |
| 8147 | } |
| 8148 | break; |
| 8149 | |
| 8150 | /* This is the same as IA64_RS_PRr, except simplified to account for |
| 8151 | the fact that there is only one register. */ |
| 8152 | case IA64_RS_PR63: |
| 8153 | if (note == 0) |
| 8154 | { |
| 8155 | specs[count++] = tmpl; |
| 8156 | } |
| 8157 | else if (note == 7) |
| 8158 | { |
| 8159 | valueT mask = 0; |
| 8160 | if (idesc->operands[2] == IA64_OPND_IMM17) |
| 8161 | mask = CURR_SLOT.opnd[2].X_add_number; |
| 8162 | if (mask & ((valueT) 1 << 63)) |
| 8163 | specs[count++] = tmpl; |
| 8164 | } |
| 8165 | else if (note == 11) |
| 8166 | { |
| 8167 | if ((idesc->operands[0] == IA64_OPND_P1 |
| 8168 | && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) |
| 8169 | || (idesc->operands[1] == IA64_OPND_P2 |
| 8170 | && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) |
| 8171 | { |
| 8172 | specs[count++] = tmpl; |
| 8173 | } |
| 8174 | } |
| 8175 | else if (note == 12) |
| 8176 | { |
| 8177 | if (CURR_SLOT.qp_regno == 63) |
| 8178 | { |
| 8179 | specs[count++] = tmpl; |
| 8180 | } |
| 8181 | } |
| 8182 | else if (note == 1) |
| 8183 | { |
| 8184 | if (rsrc_write) |
| 8185 | { |
| 8186 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
| 8187 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
| 8188 | int or_andcm = strstr(idesc->name, "or.andcm") != NULL; |
| 8189 | int and_orcm = strstr(idesc->name, "and.orcm") != NULL; |
| 8190 | |
| 8191 | if (p1 == 63 |
| 8192 | && (idesc->operands[0] == IA64_OPND_P1 |
| 8193 | || idesc->operands[0] == IA64_OPND_P2)) |
| 8194 | { |
| 8195 | specs[count] = tmpl; |
| 8196 | specs[count++].cmp_type = |
| 8197 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
| 8198 | } |
| 8199 | if (p2 == 63 |
| 8200 | && (idesc->operands[1] == IA64_OPND_P1 |
| 8201 | || idesc->operands[1] == IA64_OPND_P2)) |
| 8202 | { |
| 8203 | specs[count] = tmpl; |
| 8204 | specs[count++].cmp_type = |
| 8205 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
| 8206 | } |
| 8207 | } |
| 8208 | else |
| 8209 | { |
| 8210 | if (CURR_SLOT.qp_regno == 63) |
| 8211 | { |
| 8212 | specs[count++] = tmpl; |
| 8213 | } |
| 8214 | } |
| 8215 | } |
| 8216 | else |
| 8217 | { |
| 8218 | UNHANDLED; |
| 8219 | } |
| 8220 | break; |
| 8221 | |
| 8222 | case IA64_RS_RSE: |
| 8223 | /* FIXME we can identify some individual RSE written resources, but RSE |
| 8224 | read resources have not yet been completely identified, so for now |
| 8225 | treat RSE as a single resource */ |
| 8226 | if (strncmp (idesc->name, "mov", 3) == 0) |
| 8227 | { |
| 8228 | if (rsrc_write) |
| 8229 | { |
| 8230 | if (idesc->operands[0] == IA64_OPND_AR3 |
| 8231 | && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) |
| 8232 | { |
| 8233 | specs[count] = tmpl; |
| 8234 | specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ |
| 8235 | } |
| 8236 | } |
| 8237 | else |
| 8238 | { |
| 8239 | if (idesc->operands[0] == IA64_OPND_AR3) |
| 8240 | { |
| 8241 | if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE |
| 8242 | || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) |
| 8243 | { |
| 8244 | specs[count++] = tmpl; |
| 8245 | } |
| 8246 | } |
| 8247 | else if (idesc->operands[1] == IA64_OPND_AR3) |
| 8248 | { |
| 8249 | if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP |
| 8250 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE |
| 8251 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) |
| 8252 | { |
| 8253 | specs[count++] = tmpl; |
| 8254 | } |
| 8255 | } |
| 8256 | } |
| 8257 | } |
| 8258 | else |
| 8259 | { |
| 8260 | specs[count++] = tmpl; |
| 8261 | } |
| 8262 | break; |
| 8263 | |
| 8264 | case IA64_RS_ANY: |
| 8265 | /* FIXME -- do any of these need to be non-specific? */ |
| 8266 | specs[count++] = tmpl; |
| 8267 | break; |
| 8268 | |
| 8269 | default: |
| 8270 | as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); |
| 8271 | break; |
| 8272 | } |
| 8273 | |
| 8274 | return count; |
| 8275 | } |
| 8276 | |
| 8277 | /* Clear branch flags on marked resources. This breaks the link between the |
| 8278 | QP of the marking instruction and a subsequent branch on the same QP. */ |
| 8279 | |
| 8280 | static void |
| 8281 | clear_qp_branch_flag (mask) |
| 8282 | valueT mask; |
| 8283 | { |
| 8284 | int i; |
| 8285 | for (i = 0; i < regdepslen; i++) |
| 8286 | { |
| 8287 | valueT bit = ((valueT) 1 << regdeps[i].qp_regno); |
| 8288 | if ((bit & mask) != 0) |
| 8289 | { |
| 8290 | regdeps[i].link_to_qp_branch = 0; |
| 8291 | } |
| 8292 | } |
| 8293 | } |
| 8294 | |
| 8295 | /* Remove any mutexes which contain any of the PRs indicated in the mask. |
| 8296 | |
| 8297 | Any changes to a PR clears the mutex relations which include that PR. */ |
| 8298 | |
| 8299 | static void |
| 8300 | clear_qp_mutex (mask) |
| 8301 | valueT mask; |
| 8302 | { |
| 8303 | int i; |
| 8304 | |
| 8305 | i = 0; |
| 8306 | while (i < qp_mutexeslen) |
| 8307 | { |
| 8308 | if ((qp_mutexes[i].prmask & mask) != 0) |
| 8309 | { |
| 8310 | if (md.debug_dv) |
| 8311 | { |
| 8312 | fprintf (stderr, " Clearing mutex relation"); |
| 8313 | print_prmask (qp_mutexes[i].prmask); |
| 8314 | fprintf (stderr, "\n"); |
| 8315 | } |
| 8316 | qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; |
| 8317 | } |
| 8318 | else |
| 8319 | ++i; |
| 8320 | } |
| 8321 | } |
| 8322 | |
| 8323 | /* Clear implies relations which contain PRs in the given masks. |
| 8324 | P1_MASK indicates the source of the implies relation, while P2_MASK |
| 8325 | indicates the implied PR. */ |
| 8326 | |
| 8327 | static void |
| 8328 | clear_qp_implies (p1_mask, p2_mask) |
| 8329 | valueT p1_mask; |
| 8330 | valueT p2_mask; |
| 8331 | { |
| 8332 | int i; |
| 8333 | |
| 8334 | i = 0; |
| 8335 | while (i < qp_implieslen) |
| 8336 | { |
| 8337 | if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 |
| 8338 | || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) |
| 8339 | { |
| 8340 | if (md.debug_dv) |
| 8341 | fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", |
| 8342 | qp_implies[i].p1, qp_implies[i].p2); |
| 8343 | qp_implies[i] = qp_implies[--qp_implieslen]; |
| 8344 | } |
| 8345 | else |
| 8346 | ++i; |
| 8347 | } |
| 8348 | } |
| 8349 | |
| 8350 | /* Add the PRs specified to the list of implied relations. */ |
| 8351 | |
| 8352 | static void |
| 8353 | add_qp_imply (p1, p2) |
| 8354 | int p1, p2; |
| 8355 | { |
| 8356 | valueT mask; |
| 8357 | valueT bit; |
| 8358 | int i; |
| 8359 | |
| 8360 | /* p0 is not meaningful here. */ |
| 8361 | if (p1 == 0 || p2 == 0) |
| 8362 | abort (); |
| 8363 | |
| 8364 | if (p1 == p2) |
| 8365 | return; |
| 8366 | |
| 8367 | /* If it exists already, ignore it. */ |
| 8368 | for (i = 0; i < qp_implieslen; i++) |
| 8369 | { |
| 8370 | if (qp_implies[i].p1 == p1 |
| 8371 | && qp_implies[i].p2 == p2 |
| 8372 | && qp_implies[i].path == md.path |
| 8373 | && !qp_implies[i].p2_branched) |
| 8374 | return; |
| 8375 | } |
| 8376 | |
| 8377 | if (qp_implieslen == qp_impliestotlen) |
| 8378 | { |
| 8379 | qp_impliestotlen += 20; |
| 8380 | qp_implies = (struct qp_imply *) |
| 8381 | xrealloc ((void *) qp_implies, |
| 8382 | qp_impliestotlen * sizeof (struct qp_imply)); |
| 8383 | } |
| 8384 | if (md.debug_dv) |
| 8385 | fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); |
| 8386 | qp_implies[qp_implieslen].p1 = p1; |
| 8387 | qp_implies[qp_implieslen].p2 = p2; |
| 8388 | qp_implies[qp_implieslen].path = md.path; |
| 8389 | qp_implies[qp_implieslen++].p2_branched = 0; |
| 8390 | |
| 8391 | /* Add in the implied transitive relations; for everything that p2 implies, |
| 8392 | make p1 imply that, too; for everything that implies p1, make it imply p2 |
| 8393 | as well. */ |
| 8394 | for (i = 0; i < qp_implieslen; i++) |
| 8395 | { |
| 8396 | if (qp_implies[i].p1 == p2) |
| 8397 | add_qp_imply (p1, qp_implies[i].p2); |
| 8398 | if (qp_implies[i].p2 == p1) |
| 8399 | add_qp_imply (qp_implies[i].p1, p2); |
| 8400 | } |
| 8401 | /* Add in mutex relations implied by this implies relation; for each mutex |
| 8402 | relation containing p2, duplicate it and replace p2 with p1. */ |
| 8403 | bit = (valueT) 1 << p1; |
| 8404 | mask = (valueT) 1 << p2; |
| 8405 | for (i = 0; i < qp_mutexeslen; i++) |
| 8406 | { |
| 8407 | if (qp_mutexes[i].prmask & mask) |
| 8408 | add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); |
| 8409 | } |
| 8410 | } |
| 8411 | |
| 8412 | /* Add the PRs specified in the mask to the mutex list; this means that only |
| 8413 | one of the PRs can be true at any time. PR0 should never be included in |
| 8414 | the mask. */ |
| 8415 | |
| 8416 | static void |
| 8417 | add_qp_mutex (mask) |
| 8418 | valueT mask; |
| 8419 | { |
| 8420 | if (mask & 0x1) |
| 8421 | abort (); |
| 8422 | |
| 8423 | if (qp_mutexeslen == qp_mutexestotlen) |
| 8424 | { |
| 8425 | qp_mutexestotlen += 20; |
| 8426 | qp_mutexes = (struct qpmutex *) |
| 8427 | xrealloc ((void *) qp_mutexes, |
| 8428 | qp_mutexestotlen * sizeof (struct qpmutex)); |
| 8429 | } |
| 8430 | if (md.debug_dv) |
| 8431 | { |
| 8432 | fprintf (stderr, " Registering mutex on"); |
| 8433 | print_prmask (mask); |
| 8434 | fprintf (stderr, "\n"); |
| 8435 | } |
| 8436 | qp_mutexes[qp_mutexeslen].path = md.path; |
| 8437 | qp_mutexes[qp_mutexeslen++].prmask = mask; |
| 8438 | } |
| 8439 | |
| 8440 | static void |
| 8441 | clear_register_values () |
| 8442 | { |
| 8443 | int i; |
| 8444 | if (md.debug_dv) |
| 8445 | fprintf (stderr, " Clearing register values\n"); |
| 8446 | for (i = 1; i < NELEMS (gr_values); i++) |
| 8447 | gr_values[i].known = 0; |
| 8448 | } |
| 8449 | |
| 8450 | /* Keep track of register values/changes which affect DV tracking. |
| 8451 | |
| 8452 | optimization note: should add a flag to classes of insns where otherwise we |
| 8453 | have to examine a group of strings to identify them. */ |
| 8454 | |
| 8455 | static void |
| 8456 | note_register_values (idesc) |
| 8457 | struct ia64_opcode *idesc; |
| 8458 | { |
| 8459 | valueT qp_changemask = 0; |
| 8460 | int i; |
| 8461 | |
| 8462 | /* Invalidate values for registers being written to. */ |
| 8463 | for (i = 0; i < idesc->num_outputs; i++) |
| 8464 | { |
| 8465 | if (idesc->operands[i] == IA64_OPND_R1 |
| 8466 | || idesc->operands[i] == IA64_OPND_R2 |
| 8467 | || idesc->operands[i] == IA64_OPND_R3) |
| 8468 | { |
| 8469 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 8470 | if (regno > 0 && regno < NELEMS (gr_values)) |
| 8471 | gr_values[regno].known = 0; |
| 8472 | } |
| 8473 | else if (idesc->operands[i] == IA64_OPND_R3_2) |
| 8474 | { |
| 8475 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; |
| 8476 | if (regno > 0 && regno < 4) |
| 8477 | gr_values[regno].known = 0; |
| 8478 | } |
| 8479 | else if (idesc->operands[i] == IA64_OPND_P1 |
| 8480 | || idesc->operands[i] == IA64_OPND_P2) |
| 8481 | { |
| 8482 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; |
| 8483 | qp_changemask |= (valueT) 1 << regno; |
| 8484 | } |
| 8485 | else if (idesc->operands[i] == IA64_OPND_PR) |
| 8486 | { |
| 8487 | if (idesc->operands[2] & (valueT) 0x10000) |
| 8488 | qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; |
| 8489 | else |
| 8490 | qp_changemask = idesc->operands[2]; |
| 8491 | break; |
| 8492 | } |
| 8493 | else if (idesc->operands[i] == IA64_OPND_PR_ROT) |
| 8494 | { |
| 8495 | if (idesc->operands[1] & ((valueT) 1 << 43)) |
| 8496 | qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; |
| 8497 | else |
| 8498 | qp_changemask = idesc->operands[1]; |
| 8499 | qp_changemask &= ~(valueT) 0xFFFF; |
| 8500 | break; |
| 8501 | } |
| 8502 | } |
| 8503 | |
| 8504 | /* Always clear qp branch flags on any PR change. */ |
| 8505 | /* FIXME there may be exceptions for certain compares. */ |
| 8506 | clear_qp_branch_flag (qp_changemask); |
| 8507 | |
| 8508 | /* Invalidate rotating registers on insns which affect RRBs in CFM. */ |
| 8509 | if (idesc->flags & IA64_OPCODE_MOD_RRBS) |
| 8510 | { |
| 8511 | qp_changemask |= ~(valueT) 0xFFFF; |
| 8512 | if (strcmp (idesc->name, "clrrrb.pr") != 0) |
| 8513 | { |
| 8514 | for (i = 32; i < 32 + md.rot.num_regs; i++) |
| 8515 | gr_values[i].known = 0; |
| 8516 | } |
| 8517 | clear_qp_mutex (qp_changemask); |
| 8518 | clear_qp_implies (qp_changemask, qp_changemask); |
| 8519 | } |
| 8520 | /* After a call, all register values are undefined, except those marked |
| 8521 | as "safe". */ |
| 8522 | else if (strncmp (idesc->name, "br.call", 6) == 0 |
| 8523 | || strncmp (idesc->name, "brl.call", 7) == 0) |
| 8524 | { |
| 8525 | /* FIXME keep GR values which are marked as "safe_across_calls" */ |
| 8526 | clear_register_values (); |
| 8527 | clear_qp_mutex (~qp_safe_across_calls); |
| 8528 | clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); |
| 8529 | clear_qp_branch_flag (~qp_safe_across_calls); |
| 8530 | } |
| 8531 | else if (is_interruption_or_rfi (idesc) |
| 8532 | || is_taken_branch (idesc)) |
| 8533 | { |
| 8534 | clear_register_values (); |
| 8535 | clear_qp_mutex (~(valueT) 0); |
| 8536 | clear_qp_implies (~(valueT) 0, ~(valueT) 0); |
| 8537 | } |
| 8538 | /* Look for mutex and implies relations. */ |
| 8539 | else if ((idesc->operands[0] == IA64_OPND_P1 |
| 8540 | || idesc->operands[0] == IA64_OPND_P2) |
| 8541 | && (idesc->operands[1] == IA64_OPND_P1 |
| 8542 | || idesc->operands[1] == IA64_OPND_P2)) |
| 8543 | { |
| 8544 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
| 8545 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
| 8546 | valueT p1mask = (valueT) 1 << p1; |
| 8547 | valueT p2mask = (valueT) 1 << p2; |
| 8548 | |
| 8549 | /* If one of the PRs is PR0, we can't really do anything. */ |
| 8550 | if (p1 == 0 || p2 == 0) |
| 8551 | { |
| 8552 | if (md.debug_dv) |
| 8553 | fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); |
| 8554 | } |
| 8555 | /* In general, clear mutexes and implies which include P1 or P2, |
| 8556 | with the following exceptions. */ |
| 8557 | else if (strstr (idesc->name, ".or.andcm") != NULL) |
| 8558 | { |
| 8559 | add_qp_mutex (p1mask | p2mask); |
| 8560 | clear_qp_implies (p2mask, p1mask); |
| 8561 | } |
| 8562 | else if (strstr (idesc->name, ".and.orcm") != NULL) |
| 8563 | { |
| 8564 | add_qp_mutex (p1mask | p2mask); |
| 8565 | clear_qp_implies (p1mask, p2mask); |
| 8566 | } |
| 8567 | else if (strstr (idesc->name, ".and") != NULL) |
| 8568 | { |
| 8569 | clear_qp_implies (0, p1mask | p2mask); |
| 8570 | } |
| 8571 | else if (strstr (idesc->name, ".or") != NULL) |
| 8572 | { |
| 8573 | clear_qp_mutex (p1mask | p2mask); |
| 8574 | clear_qp_implies (p1mask | p2mask, 0); |
| 8575 | } |
| 8576 | else |
| 8577 | { |
| 8578 | clear_qp_implies (p1mask | p2mask, p1mask | p2mask); |
| 8579 | if (strstr (idesc->name, ".unc") != NULL) |
| 8580 | { |
| 8581 | add_qp_mutex (p1mask | p2mask); |
| 8582 | if (CURR_SLOT.qp_regno != 0) |
| 8583 | { |
| 8584 | add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, |
| 8585 | CURR_SLOT.qp_regno); |
| 8586 | add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, |
| 8587 | CURR_SLOT.qp_regno); |
| 8588 | } |
| 8589 | } |
| 8590 | else if (CURR_SLOT.qp_regno == 0) |
| 8591 | { |
| 8592 | add_qp_mutex (p1mask | p2mask); |
| 8593 | } |
| 8594 | else |
| 8595 | { |
| 8596 | clear_qp_mutex (p1mask | p2mask); |
| 8597 | } |
| 8598 | } |
| 8599 | } |
| 8600 | /* Look for mov imm insns into GRs. */ |
| 8601 | else if (idesc->operands[0] == IA64_OPND_R1 |
| 8602 | && (idesc->operands[1] == IA64_OPND_IMM22 |
| 8603 | || idesc->operands[1] == IA64_OPND_IMMU64) |
| 8604 | && (strcmp (idesc->name, "mov") == 0 |
| 8605 | || strcmp (idesc->name, "movl") == 0)) |
| 8606 | { |
| 8607 | int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; |
| 8608 | if (regno > 0 && regno < NELEMS (gr_values)) |
| 8609 | { |
| 8610 | gr_values[regno].known = 1; |
| 8611 | gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; |
| 8612 | gr_values[regno].path = md.path; |
| 8613 | if (md.debug_dv) |
| 8614 | { |
| 8615 | fprintf (stderr, " Know gr%d = ", regno); |
| 8616 | fprintf_vma (stderr, gr_values[regno].value); |
| 8617 | fputs ("\n", stderr); |
| 8618 | } |
| 8619 | } |
| 8620 | } |
| 8621 | else |
| 8622 | { |
| 8623 | clear_qp_mutex (qp_changemask); |
| 8624 | clear_qp_implies (qp_changemask, qp_changemask); |
| 8625 | } |
| 8626 | } |
| 8627 | |
| 8628 | /* Return whether the given predicate registers are currently mutex. */ |
| 8629 | |
| 8630 | static int |
| 8631 | qp_mutex (p1, p2, path) |
| 8632 | int p1; |
| 8633 | int p2; |
| 8634 | int path; |
| 8635 | { |
| 8636 | int i; |
| 8637 | valueT mask; |
| 8638 | |
| 8639 | if (p1 != p2) |
| 8640 | { |
| 8641 | mask = ((valueT) 1 << p1) | (valueT) 1 << p2; |
| 8642 | for (i = 0; i < qp_mutexeslen; i++) |
| 8643 | { |
| 8644 | if (qp_mutexes[i].path >= path |
| 8645 | && (qp_mutexes[i].prmask & mask) == mask) |
| 8646 | return 1; |
| 8647 | } |
| 8648 | } |
| 8649 | return 0; |
| 8650 | } |
| 8651 | |
| 8652 | /* Return whether the given resource is in the given insn's list of chks |
| 8653 | Return 1 if the conflict is absolutely determined, 2 if it's a potential |
| 8654 | conflict. */ |
| 8655 | |
| 8656 | static int |
| 8657 | resources_match (rs, idesc, note, qp_regno, path) |
| 8658 | struct rsrc *rs; |
| 8659 | struct ia64_opcode *idesc; |
| 8660 | int note; |
| 8661 | int qp_regno; |
| 8662 | int path; |
| 8663 | { |
| 8664 | struct rsrc specs[MAX_SPECS]; |
| 8665 | int count; |
| 8666 | |
| 8667 | /* If the marked resource's qp_regno and the given qp_regno are mutex, |
| 8668 | we don't need to check. One exception is note 11, which indicates that |
| 8669 | target predicates are written regardless of PR[qp]. */ |
| 8670 | if (qp_mutex (rs->qp_regno, qp_regno, path) |
| 8671 | && note != 11) |
| 8672 | return 0; |
| 8673 | |
| 8674 | count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); |
| 8675 | while (count-- > 0) |
| 8676 | { |
| 8677 | /* UNAT checking is a bit more specific than other resources */ |
| 8678 | if (rs->dependency->specifier == IA64_RS_AR_UNAT |
| 8679 | && specs[count].mem_offset.hint |
| 8680 | && rs->mem_offset.hint) |
| 8681 | { |
| 8682 | if (rs->mem_offset.base == specs[count].mem_offset.base) |
| 8683 | { |
| 8684 | if (((rs->mem_offset.offset >> 3) & 0x3F) == |
| 8685 | ((specs[count].mem_offset.offset >> 3) & 0x3F)) |
| 8686 | return 1; |
| 8687 | else |
| 8688 | continue; |
| 8689 | } |
| 8690 | } |
| 8691 | |
| 8692 | /* Skip apparent PR write conflicts where both writes are an AND or both |
| 8693 | writes are an OR. */ |
| 8694 | if (rs->dependency->specifier == IA64_RS_PR |
| 8695 | || rs->dependency->specifier == IA64_RS_PRr |
| 8696 | || rs->dependency->specifier == IA64_RS_PR63) |
| 8697 | { |
| 8698 | if (specs[count].cmp_type != CMP_NONE |
| 8699 | && specs[count].cmp_type == rs->cmp_type) |
| 8700 | { |
| 8701 | if (md.debug_dv) |
| 8702 | fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", |
| 8703 | dv_mode[rs->dependency->mode], |
| 8704 | rs->dependency->specifier != IA64_RS_PR63 ? |
| 8705 | specs[count].index : 63); |
| 8706 | continue; |
| 8707 | } |
| 8708 | if (md.debug_dv) |
| 8709 | fprintf (stderr, |
| 8710 | " %s on parallel compare conflict %s vs %s on PR%d\n", |
| 8711 | dv_mode[rs->dependency->mode], |
| 8712 | dv_cmp_type[rs->cmp_type], |
| 8713 | dv_cmp_type[specs[count].cmp_type], |
| 8714 | rs->dependency->specifier != IA64_RS_PR63 ? |
| 8715 | specs[count].index : 63); |
| 8716 | |
| 8717 | } |
| 8718 | |
| 8719 | /* If either resource is not specific, conservatively assume a conflict |
| 8720 | */ |
| 8721 | if (!specs[count].specific || !rs->specific) |
| 8722 | return 2; |
| 8723 | else if (specs[count].index == rs->index) |
| 8724 | return 1; |
| 8725 | } |
| 8726 | #if 0 |
| 8727 | if (md.debug_dv) |
| 8728 | fprintf (stderr, " No %s conflicts\n", rs->dependency->name); |
| 8729 | #endif |
| 8730 | |
| 8731 | return 0; |
| 8732 | } |
| 8733 | |
| 8734 | /* Indicate an instruction group break; if INSERT_STOP is non-zero, then |
| 8735 | insert a stop to create the break. Update all resource dependencies |
| 8736 | appropriately. If QP_REGNO is non-zero, only apply the break to resources |
| 8737 | which use the same QP_REGNO and have the link_to_qp_branch flag set. |
| 8738 | If SAVE_CURRENT is non-zero, don't affect resources marked by the current |
| 8739 | instruction. */ |
| 8740 | |
| 8741 | static void |
| 8742 | insn_group_break (insert_stop, qp_regno, save_current) |
| 8743 | int insert_stop; |
| 8744 | int qp_regno; |
| 8745 | int save_current; |
| 8746 | { |
| 8747 | int i; |
| 8748 | |
| 8749 | if (insert_stop && md.num_slots_in_use > 0) |
| 8750 | PREV_SLOT.end_of_insn_group = 1; |
| 8751 | |
| 8752 | if (md.debug_dv) |
| 8753 | { |
| 8754 | fprintf (stderr, " Insn group break%s", |
| 8755 | (insert_stop ? " (w/stop)" : "")); |
| 8756 | if (qp_regno != 0) |
| 8757 | fprintf (stderr, " effective for QP=%d", qp_regno); |
| 8758 | fprintf (stderr, "\n"); |
| 8759 | } |
| 8760 | |
| 8761 | i = 0; |
| 8762 | while (i < regdepslen) |
| 8763 | { |
| 8764 | const struct ia64_dependency *dep = regdeps[i].dependency; |
| 8765 | |
| 8766 | if (qp_regno != 0 |
| 8767 | && regdeps[i].qp_regno != qp_regno) |
| 8768 | { |
| 8769 | ++i; |
| 8770 | continue; |
| 8771 | } |
| 8772 | |
| 8773 | if (save_current |
| 8774 | && CURR_SLOT.src_file == regdeps[i].file |
| 8775 | && CURR_SLOT.src_line == regdeps[i].line) |
| 8776 | { |
| 8777 | ++i; |
| 8778 | continue; |
| 8779 | } |
| 8780 | |
| 8781 | /* clear dependencies which are automatically cleared by a stop, or |
| 8782 | those that have reached the appropriate state of insn serialization */ |
| 8783 | if (dep->semantics == IA64_DVS_IMPLIED |
| 8784 | || dep->semantics == IA64_DVS_IMPLIEDF |
| 8785 | || regdeps[i].insn_srlz == STATE_SRLZ) |
| 8786 | { |
| 8787 | print_dependency ("Removing", i); |
| 8788 | regdeps[i] = regdeps[--regdepslen]; |
| 8789 | } |
| 8790 | else |
| 8791 | { |
| 8792 | if (dep->semantics == IA64_DVS_DATA |
| 8793 | || dep->semantics == IA64_DVS_INSTR |
| 8794 | || dep->semantics == IA64_DVS_SPECIFIC) |
| 8795 | { |
| 8796 | if (regdeps[i].insn_srlz == STATE_NONE) |
| 8797 | regdeps[i].insn_srlz = STATE_STOP; |
| 8798 | if (regdeps[i].data_srlz == STATE_NONE) |
| 8799 | regdeps[i].data_srlz = STATE_STOP; |
| 8800 | } |
| 8801 | ++i; |
| 8802 | } |
| 8803 | } |
| 8804 | } |
| 8805 | |
| 8806 | /* Add the given resource usage spec to the list of active dependencies. */ |
| 8807 | |
| 8808 | static void |
| 8809 | mark_resource (idesc, dep, spec, depind, path) |
| 8810 | struct ia64_opcode *idesc ATTRIBUTE_UNUSED; |
| 8811 | const struct ia64_dependency *dep ATTRIBUTE_UNUSED; |
| 8812 | struct rsrc *spec; |
| 8813 | int depind; |
| 8814 | int path; |
| 8815 | { |
| 8816 | if (regdepslen == regdepstotlen) |
| 8817 | { |
| 8818 | regdepstotlen += 20; |
| 8819 | regdeps = (struct rsrc *) |
| 8820 | xrealloc ((void *) regdeps, |
| 8821 | regdepstotlen * sizeof (struct rsrc)); |
| 8822 | } |
| 8823 | |
| 8824 | regdeps[regdepslen] = *spec; |
| 8825 | regdeps[regdepslen].depind = depind; |
| 8826 | regdeps[regdepslen].path = path; |
| 8827 | regdeps[regdepslen].file = CURR_SLOT.src_file; |
| 8828 | regdeps[regdepslen].line = CURR_SLOT.src_line; |
| 8829 | |
| 8830 | print_dependency ("Adding", regdepslen); |
| 8831 | |
| 8832 | ++regdepslen; |
| 8833 | } |
| 8834 | |
| 8835 | static void |
| 8836 | print_dependency (action, depind) |
| 8837 | const char *action; |
| 8838 | int depind; |
| 8839 | { |
| 8840 | if (md.debug_dv) |
| 8841 | { |
| 8842 | fprintf (stderr, " %s %s '%s'", |
| 8843 | action, dv_mode[(regdeps[depind].dependency)->mode], |
| 8844 | (regdeps[depind].dependency)->name); |
| 8845 | if (regdeps[depind].specific && regdeps[depind].index != 0) |
| 8846 | fprintf (stderr, " (%d)", regdeps[depind].index); |
| 8847 | if (regdeps[depind].mem_offset.hint) |
| 8848 | { |
| 8849 | fputs (" ", stderr); |
| 8850 | fprintf_vma (stderr, regdeps[depind].mem_offset.base); |
| 8851 | fputs ("+", stderr); |
| 8852 | fprintf_vma (stderr, regdeps[depind].mem_offset.offset); |
| 8853 | } |
| 8854 | fprintf (stderr, "\n"); |
| 8855 | } |
| 8856 | } |
| 8857 | |
| 8858 | static void |
| 8859 | instruction_serialization () |
| 8860 | { |
| 8861 | int i; |
| 8862 | if (md.debug_dv) |
| 8863 | fprintf (stderr, " Instruction serialization\n"); |
| 8864 | for (i = 0; i < regdepslen; i++) |
| 8865 | if (regdeps[i].insn_srlz == STATE_STOP) |
| 8866 | regdeps[i].insn_srlz = STATE_SRLZ; |
| 8867 | } |
| 8868 | |
| 8869 | static void |
| 8870 | data_serialization () |
| 8871 | { |
| 8872 | int i = 0; |
| 8873 | if (md.debug_dv) |
| 8874 | fprintf (stderr, " Data serialization\n"); |
| 8875 | while (i < regdepslen) |
| 8876 | { |
| 8877 | if (regdeps[i].data_srlz == STATE_STOP |
| 8878 | /* Note: as of 991210, all "other" dependencies are cleared by a |
| 8879 | data serialization. This might change with new tables */ |
| 8880 | || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) |
| 8881 | { |
| 8882 | print_dependency ("Removing", i); |
| 8883 | regdeps[i] = regdeps[--regdepslen]; |
| 8884 | } |
| 8885 | else |
| 8886 | ++i; |
| 8887 | } |
| 8888 | } |
| 8889 | |
| 8890 | /* Insert stops and serializations as needed to avoid DVs. */ |
| 8891 | |
| 8892 | static void |
| 8893 | remove_marked_resource (rs) |
| 8894 | struct rsrc *rs; |
| 8895 | { |
| 8896 | switch (rs->dependency->semantics) |
| 8897 | { |
| 8898 | case IA64_DVS_SPECIFIC: |
| 8899 | if (md.debug_dv) |
| 8900 | fprintf (stderr, "Implementation-specific, assume worst case...\n"); |
| 8901 | /* ...fall through... */ |
| 8902 | case IA64_DVS_INSTR: |
| 8903 | if (md.debug_dv) |
| 8904 | fprintf (stderr, "Inserting instr serialization\n"); |
| 8905 | if (rs->insn_srlz < STATE_STOP) |
| 8906 | insn_group_break (1, 0, 0); |
| 8907 | if (rs->insn_srlz < STATE_SRLZ) |
| 8908 | { |
| 8909 | int oldqp = CURR_SLOT.qp_regno; |
| 8910 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; |
| 8911 | /* Manually jam a srlz.i insn into the stream */ |
| 8912 | CURR_SLOT.qp_regno = 0; |
| 8913 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); |
| 8914 | instruction_serialization (); |
| 8915 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; |
| 8916 | if (++md.num_slots_in_use >= NUM_SLOTS) |
| 8917 | emit_one_bundle (); |
| 8918 | CURR_SLOT.qp_regno = oldqp; |
| 8919 | CURR_SLOT.idesc = oldidesc; |
| 8920 | } |
| 8921 | insn_group_break (1, 0, 0); |
| 8922 | break; |
| 8923 | case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all |
| 8924 | "other" types of DV are eliminated |
| 8925 | by a data serialization */ |
| 8926 | case IA64_DVS_DATA: |
| 8927 | if (md.debug_dv) |
| 8928 | fprintf (stderr, "Inserting data serialization\n"); |
| 8929 | if (rs->data_srlz < STATE_STOP) |
| 8930 | insn_group_break (1, 0, 0); |
| 8931 | { |
| 8932 | int oldqp = CURR_SLOT.qp_regno; |
| 8933 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; |
| 8934 | /* Manually jam a srlz.d insn into the stream */ |
| 8935 | CURR_SLOT.qp_regno = 0; |
| 8936 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); |
| 8937 | data_serialization (); |
| 8938 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; |
| 8939 | if (++md.num_slots_in_use >= NUM_SLOTS) |
| 8940 | emit_one_bundle (); |
| 8941 | CURR_SLOT.qp_regno = oldqp; |
| 8942 | CURR_SLOT.idesc = oldidesc; |
| 8943 | } |
| 8944 | break; |
| 8945 | case IA64_DVS_IMPLIED: |
| 8946 | case IA64_DVS_IMPLIEDF: |
| 8947 | if (md.debug_dv) |
| 8948 | fprintf (stderr, "Inserting stop\n"); |
| 8949 | insn_group_break (1, 0, 0); |
| 8950 | break; |
| 8951 | default: |
| 8952 | break; |
| 8953 | } |
| 8954 | } |
| 8955 | |
| 8956 | /* Check the resources used by the given opcode against the current dependency |
| 8957 | list. |
| 8958 | |
| 8959 | The check is run once for each execution path encountered. In this case, |
| 8960 | a unique execution path is the sequence of instructions following a code |
| 8961 | entry point, e.g. the following has three execution paths, one starting |
| 8962 | at L0, one at L1, and one at L2. |
| 8963 | |
| 8964 | L0: nop |
| 8965 | L1: add |
| 8966 | L2: add |
| 8967 | br.ret |
| 8968 | */ |
| 8969 | |
| 8970 | static void |
| 8971 | check_dependencies (idesc) |
| 8972 | struct ia64_opcode *idesc; |
| 8973 | { |
| 8974 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; |
| 8975 | int path; |
| 8976 | int i; |
| 8977 | |
| 8978 | /* Note that the number of marked resources may change within the |
| 8979 | loop if in auto mode. */ |
| 8980 | i = 0; |
| 8981 | while (i < regdepslen) |
| 8982 | { |
| 8983 | struct rsrc *rs = ®deps[i]; |
| 8984 | const struct ia64_dependency *dep = rs->dependency; |
| 8985 | int chkind; |
| 8986 | int note; |
| 8987 | int start_over = 0; |
| 8988 | |
| 8989 | if (dep->semantics == IA64_DVS_NONE |
| 8990 | || (chkind = depends_on (rs->depind, idesc)) == -1) |
| 8991 | { |
| 8992 | ++i; |
| 8993 | continue; |
| 8994 | } |
| 8995 | |
| 8996 | note = NOTE (opdeps->chks[chkind]); |
| 8997 | |
| 8998 | /* Check this resource against each execution path seen thus far. */ |
| 8999 | for (path = 0; path <= md.path; path++) |
| 9000 | { |
| 9001 | int matchtype; |
| 9002 | |
| 9003 | /* If the dependency wasn't on the path being checked, ignore it. */ |
| 9004 | if (rs->path < path) |
| 9005 | continue; |
| 9006 | |
| 9007 | /* If the QP for this insn implies a QP which has branched, don't |
| 9008 | bother checking. Ed. NOTE: I don't think this check is terribly |
| 9009 | useful; what's the point of generating code which will only be |
| 9010 | reached if its QP is zero? |
| 9011 | This code was specifically inserted to handle the following code, |
| 9012 | based on notes from Intel's DV checking code, where p1 implies p2. |
| 9013 | |
| 9014 | mov r4 = 2 |
| 9015 | (p2) br.cond L |
| 9016 | (p1) mov r4 = 7 |
| 9017 | */ |
| 9018 | if (CURR_SLOT.qp_regno != 0) |
| 9019 | { |
| 9020 | int skip = 0; |
| 9021 | int implies; |
| 9022 | for (implies = 0; implies < qp_implieslen; implies++) |
| 9023 | { |
| 9024 | if (qp_implies[implies].path >= path |
| 9025 | && qp_implies[implies].p1 == CURR_SLOT.qp_regno |
| 9026 | && qp_implies[implies].p2_branched) |
| 9027 | { |
| 9028 | skip = 1; |
| 9029 | break; |
| 9030 | } |
| 9031 | } |
| 9032 | if (skip) |
| 9033 | continue; |
| 9034 | } |
| 9035 | |
| 9036 | if ((matchtype = resources_match (rs, idesc, note, |
| 9037 | CURR_SLOT.qp_regno, path)) != 0) |
| 9038 | { |
| 9039 | char msg[1024]; |
| 9040 | char pathmsg[256] = ""; |
| 9041 | char indexmsg[256] = ""; |
| 9042 | int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); |
| 9043 | |
| 9044 | if (path != 0) |
| 9045 | sprintf (pathmsg, " when entry is at label '%s'", |
| 9046 | md.entry_labels[path - 1]); |
| 9047 | if (rs->specific && rs->index != 0) |
| 9048 | sprintf (indexmsg, ", specific resource number is %d", |
| 9049 | rs->index); |
| 9050 | sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", |
| 9051 | idesc->name, |
| 9052 | (certain ? "violates" : "may violate"), |
| 9053 | dv_mode[dep->mode], dep->name, |
| 9054 | dv_sem[dep->semantics], |
| 9055 | pathmsg, indexmsg); |
| 9056 | |
| 9057 | if (md.explicit_mode) |
| 9058 | { |
| 9059 | as_warn ("%s", msg); |
| 9060 | if (path < md.path) |
| 9061 | as_warn (_("Only the first path encountering the conflict " |
| 9062 | "is reported")); |
| 9063 | as_warn_where (rs->file, rs->line, |
| 9064 | _("This is the location of the " |
| 9065 | "conflicting usage")); |
| 9066 | /* Don't bother checking other paths, to avoid duplicating |
| 9067 | the same warning */ |
| 9068 | break; |
| 9069 | } |
| 9070 | else |
| 9071 | { |
| 9072 | if (md.debug_dv) |
| 9073 | fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); |
| 9074 | |
| 9075 | remove_marked_resource (rs); |
| 9076 | |
| 9077 | /* since the set of dependencies has changed, start over */ |
| 9078 | /* FIXME -- since we're removing dvs as we go, we |
| 9079 | probably don't really need to start over... */ |
| 9080 | start_over = 1; |
| 9081 | break; |
| 9082 | } |
| 9083 | } |
| 9084 | } |
| 9085 | if (start_over) |
| 9086 | i = 0; |
| 9087 | else |
| 9088 | ++i; |
| 9089 | } |
| 9090 | } |
| 9091 | |
| 9092 | /* Register new dependencies based on the given opcode. */ |
| 9093 | |
| 9094 | static void |
| 9095 | mark_resources (idesc) |
| 9096 | struct ia64_opcode *idesc; |
| 9097 | { |
| 9098 | int i; |
| 9099 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; |
| 9100 | int add_only_qp_reads = 0; |
| 9101 | |
| 9102 | /* A conditional branch only uses its resources if it is taken; if it is |
| 9103 | taken, we stop following that path. The other branch types effectively |
| 9104 | *always* write their resources. If it's not taken, register only QP |
| 9105 | reads. */ |
| 9106 | if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) |
| 9107 | { |
| 9108 | add_only_qp_reads = 1; |
| 9109 | } |
| 9110 | |
| 9111 | if (md.debug_dv) |
| 9112 | fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); |
| 9113 | |
| 9114 | for (i = 0; i < opdeps->nregs; i++) |
| 9115 | { |
| 9116 | const struct ia64_dependency *dep; |
| 9117 | struct rsrc specs[MAX_SPECS]; |
| 9118 | int note; |
| 9119 | int path; |
| 9120 | int count; |
| 9121 | |
| 9122 | dep = ia64_find_dependency (opdeps->regs[i]); |
| 9123 | note = NOTE (opdeps->regs[i]); |
| 9124 | |
| 9125 | if (add_only_qp_reads |
| 9126 | && !(dep->mode == IA64_DV_WAR |
| 9127 | && (dep->specifier == IA64_RS_PR |
| 9128 | || dep->specifier == IA64_RS_PRr |
| 9129 | || dep->specifier == IA64_RS_PR63))) |
| 9130 | continue; |
| 9131 | |
| 9132 | count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); |
| 9133 | |
| 9134 | #if 0 |
| 9135 | if (md.debug_dv && !count) |
| 9136 | fprintf (stderr, " No %s %s usage found (path %d)\n", |
| 9137 | dv_mode[dep->mode], dep->name, md.path); |
| 9138 | #endif |
| 9139 | |
| 9140 | while (count-- > 0) |
| 9141 | { |
| 9142 | mark_resource (idesc, dep, &specs[count], |
| 9143 | DEP (opdeps->regs[i]), md.path); |
| 9144 | } |
| 9145 | |
| 9146 | /* The execution path may affect register values, which may in turn |
| 9147 | affect which indirect-access resources are accessed. */ |
| 9148 | switch (dep->specifier) |
| 9149 | { |
| 9150 | default: |
| 9151 | break; |
| 9152 | case IA64_RS_CPUID: |
| 9153 | case IA64_RS_DBR: |
| 9154 | case IA64_RS_IBR: |
| 9155 | case IA64_RS_MSR: |
| 9156 | case IA64_RS_PKR: |
| 9157 | case IA64_RS_PMC: |
| 9158 | case IA64_RS_PMD: |
| 9159 | case IA64_RS_RR: |
| 9160 | for (path = 0; path < md.path; path++) |
| 9161 | { |
| 9162 | count = specify_resource (dep, idesc, DV_REG, specs, note, path); |
| 9163 | while (count-- > 0) |
| 9164 | mark_resource (idesc, dep, &specs[count], |
| 9165 | DEP (opdeps->regs[i]), path); |
| 9166 | } |
| 9167 | break; |
| 9168 | } |
| 9169 | } |
| 9170 | } |
| 9171 | |
| 9172 | /* Remove dependencies when they no longer apply. */ |
| 9173 | |
| 9174 | static void |
| 9175 | update_dependencies (idesc) |
| 9176 | struct ia64_opcode *idesc; |
| 9177 | { |
| 9178 | int i; |
| 9179 | |
| 9180 | if (strcmp (idesc->name, "srlz.i") == 0) |
| 9181 | { |
| 9182 | instruction_serialization (); |
| 9183 | } |
| 9184 | else if (strcmp (idesc->name, "srlz.d") == 0) |
| 9185 | { |
| 9186 | data_serialization (); |
| 9187 | } |
| 9188 | else if (is_interruption_or_rfi (idesc) |
| 9189 | || is_taken_branch (idesc)) |
| 9190 | { |
| 9191 | /* Although technically the taken branch doesn't clear dependencies |
| 9192 | which require a srlz.[id], we don't follow the branch; the next |
| 9193 | instruction is assumed to start with a clean slate. */ |
| 9194 | regdepslen = 0; |
| 9195 | md.path = 0; |
| 9196 | } |
| 9197 | else if (is_conditional_branch (idesc) |
| 9198 | && CURR_SLOT.qp_regno != 0) |
| 9199 | { |
| 9200 | int is_call = strstr (idesc->name, ".call") != NULL; |
| 9201 | |
| 9202 | for (i = 0; i < qp_implieslen; i++) |
| 9203 | { |
| 9204 | /* If the conditional branch's predicate is implied by the predicate |
| 9205 | in an existing dependency, remove that dependency. */ |
| 9206 | if (qp_implies[i].p2 == CURR_SLOT.qp_regno) |
| 9207 | { |
| 9208 | int depind = 0; |
| 9209 | /* Note that this implied predicate takes a branch so that if |
| 9210 | a later insn generates a DV but its predicate implies this |
| 9211 | one, we can avoid the false DV warning. */ |
| 9212 | qp_implies[i].p2_branched = 1; |
| 9213 | while (depind < regdepslen) |
| 9214 | { |
| 9215 | if (regdeps[depind].qp_regno == qp_implies[i].p1) |
| 9216 | { |
| 9217 | print_dependency ("Removing", depind); |
| 9218 | regdeps[depind] = regdeps[--regdepslen]; |
| 9219 | } |
| 9220 | else |
| 9221 | ++depind; |
| 9222 | } |
| 9223 | } |
| 9224 | } |
| 9225 | /* Any marked resources which have this same predicate should be |
| 9226 | cleared, provided that the QP hasn't been modified between the |
| 9227 | marking instruction and the branch. */ |
| 9228 | if (is_call) |
| 9229 | { |
| 9230 | insn_group_break (0, CURR_SLOT.qp_regno, 1); |
| 9231 | } |
| 9232 | else |
| 9233 | { |
| 9234 | i = 0; |
| 9235 | while (i < regdepslen) |
| 9236 | { |
| 9237 | if (regdeps[i].qp_regno == CURR_SLOT.qp_regno |
| 9238 | && regdeps[i].link_to_qp_branch |
| 9239 | && (regdeps[i].file != CURR_SLOT.src_file |
| 9240 | || regdeps[i].line != CURR_SLOT.src_line)) |
| 9241 | { |
| 9242 | /* Treat like a taken branch */ |
| 9243 | print_dependency ("Removing", i); |
| 9244 | regdeps[i] = regdeps[--regdepslen]; |
| 9245 | } |
| 9246 | else |
| 9247 | ++i; |
| 9248 | } |
| 9249 | } |
| 9250 | } |
| 9251 | } |
| 9252 | |
| 9253 | /* Examine the current instruction for dependency violations. */ |
| 9254 | |
| 9255 | static int |
| 9256 | check_dv (idesc) |
| 9257 | struct ia64_opcode *idesc; |
| 9258 | { |
| 9259 | if (md.debug_dv) |
| 9260 | { |
| 9261 | fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", |
| 9262 | idesc->name, CURR_SLOT.src_line, |
| 9263 | idesc->dependencies->nchks, |
| 9264 | idesc->dependencies->nregs); |
| 9265 | } |
| 9266 | |
| 9267 | /* Look through the list of currently marked resources; if the current |
| 9268 | instruction has the dependency in its chks list which uses that resource, |
| 9269 | check against the specific resources used. */ |
| 9270 | check_dependencies (idesc); |
| 9271 | |
| 9272 | /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), |
| 9273 | then add them to the list of marked resources. */ |
| 9274 | mark_resources (idesc); |
| 9275 | |
| 9276 | /* There are several types of dependency semantics, and each has its own |
| 9277 | requirements for being cleared |
| 9278 | |
| 9279 | Instruction serialization (insns separated by interruption, rfi, or |
| 9280 | writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. |
| 9281 | |
| 9282 | Data serialization (instruction serialization, or writer + srlz.d + |
| 9283 | reader, where writer and srlz.d are in separate groups) clears |
| 9284 | DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to |
| 9285 | always be the case). |
| 9286 | |
| 9287 | Instruction group break (groups separated by stop, taken branch, |
| 9288 | interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. |
| 9289 | */ |
| 9290 | update_dependencies (idesc); |
| 9291 | |
| 9292 | /* Sometimes, knowing a register value allows us to avoid giving a false DV |
| 9293 | warning. Keep track of as many as possible that are useful. */ |
| 9294 | note_register_values (idesc); |
| 9295 | |
| 9296 | /* We don't need or want this anymore. */ |
| 9297 | md.mem_offset.hint = 0; |
| 9298 | |
| 9299 | return 0; |
| 9300 | } |
| 9301 | |
| 9302 | /* Translate one line of assembly. Pseudo ops and labels do not show |
| 9303 | here. */ |
| 9304 | void |
| 9305 | md_assemble (str) |
| 9306 | char *str; |
| 9307 | { |
| 9308 | char *saved_input_line_pointer, *mnemonic; |
| 9309 | const struct pseudo_opcode *pdesc; |
| 9310 | struct ia64_opcode *idesc; |
| 9311 | unsigned char qp_regno; |
| 9312 | unsigned int flags; |
| 9313 | int ch; |
| 9314 | |
| 9315 | saved_input_line_pointer = input_line_pointer; |
| 9316 | input_line_pointer = str; |
| 9317 | |
| 9318 | /* extract the opcode (mnemonic): */ |
| 9319 | |
| 9320 | mnemonic = input_line_pointer; |
| 9321 | ch = get_symbol_end (); |
| 9322 | pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); |
| 9323 | if (pdesc) |
| 9324 | { |
| 9325 | *input_line_pointer = ch; |
| 9326 | (*pdesc->handler) (pdesc->arg); |
| 9327 | goto done; |
| 9328 | } |
| 9329 | |
| 9330 | /* Find the instruction descriptor matching the arguments. */ |
| 9331 | |
| 9332 | idesc = ia64_find_opcode (mnemonic); |
| 9333 | *input_line_pointer = ch; |
| 9334 | if (!idesc) |
| 9335 | { |
| 9336 | as_bad ("Unknown opcode `%s'", mnemonic); |
| 9337 | goto done; |
| 9338 | } |
| 9339 | |
| 9340 | idesc = parse_operands (idesc); |
| 9341 | if (!idesc) |
| 9342 | goto done; |
| 9343 | |
| 9344 | /* Handle the dynamic ops we can handle now: */ |
| 9345 | if (idesc->type == IA64_TYPE_DYN) |
| 9346 | { |
| 9347 | if (strcmp (idesc->name, "add") == 0) |
| 9348 | { |
| 9349 | if (CURR_SLOT.opnd[2].X_op == O_register |
| 9350 | && CURR_SLOT.opnd[2].X_add_number < 4) |
| 9351 | mnemonic = "addl"; |
| 9352 | else |
| 9353 | mnemonic = "adds"; |
| 9354 | ia64_free_opcode (idesc); |
| 9355 | idesc = ia64_find_opcode (mnemonic); |
| 9356 | #if 0 |
| 9357 | know (!idesc->next); |
| 9358 | #endif |
| 9359 | } |
| 9360 | else if (strcmp (idesc->name, "mov") == 0) |
| 9361 | { |
| 9362 | enum ia64_opnd opnd1, opnd2; |
| 9363 | int rop; |
| 9364 | |
| 9365 | opnd1 = idesc->operands[0]; |
| 9366 | opnd2 = idesc->operands[1]; |
| 9367 | if (opnd1 == IA64_OPND_AR3) |
| 9368 | rop = 0; |
| 9369 | else if (opnd2 == IA64_OPND_AR3) |
| 9370 | rop = 1; |
| 9371 | else |
| 9372 | abort (); |
| 9373 | if (CURR_SLOT.opnd[rop].X_op == O_register |
| 9374 | && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) |
| 9375 | mnemonic = "mov.i"; |
| 9376 | else |
| 9377 | mnemonic = "mov.m"; |
| 9378 | ia64_free_opcode (idesc); |
| 9379 | idesc = ia64_find_opcode (mnemonic); |
| 9380 | while (idesc != NULL |
| 9381 | && (idesc->operands[0] != opnd1 |
| 9382 | || idesc->operands[1] != opnd2)) |
| 9383 | idesc = get_next_opcode (idesc); |
| 9384 | } |
| 9385 | } |
| 9386 | |
| 9387 | qp_regno = 0; |
| 9388 | if (md.qp.X_op == O_register) |
| 9389 | { |
| 9390 | qp_regno = md.qp.X_add_number - REG_P; |
| 9391 | md.qp.X_op = O_absent; |
| 9392 | } |
| 9393 | |
| 9394 | flags = idesc->flags; |
| 9395 | |
| 9396 | if ((flags & IA64_OPCODE_FIRST) != 0) |
| 9397 | insn_group_break (1, 0, 0); |
| 9398 | |
| 9399 | if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) |
| 9400 | { |
| 9401 | as_bad ("`%s' cannot be predicated", idesc->name); |
| 9402 | goto done; |
| 9403 | } |
| 9404 | |
| 9405 | /* Build the instruction. */ |
| 9406 | CURR_SLOT.qp_regno = qp_regno; |
| 9407 | CURR_SLOT.idesc = idesc; |
| 9408 | as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); |
| 9409 | dwarf2_where (&CURR_SLOT.debug_line); |
| 9410 | |
| 9411 | /* Add unwind entry, if there is one. */ |
| 9412 | if (unwind.current_entry) |
| 9413 | { |
| 9414 | CURR_SLOT.unwind_record = unwind.current_entry; |
| 9415 | unwind.current_entry = NULL; |
| 9416 | } |
| 9417 | |
| 9418 | /* Check for dependency violations. */ |
| 9419 | if (md.detect_dv) |
| 9420 | check_dv (idesc); |
| 9421 | |
| 9422 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; |
| 9423 | if (++md.num_slots_in_use >= NUM_SLOTS) |
| 9424 | emit_one_bundle (); |
| 9425 | |
| 9426 | if ((flags & IA64_OPCODE_LAST) != 0) |
| 9427 | insn_group_break (1, 0, 0); |
| 9428 | |
| 9429 | md.last_text_seg = now_seg; |
| 9430 | |
| 9431 | done: |
| 9432 | input_line_pointer = saved_input_line_pointer; |
| 9433 | } |
| 9434 | |
| 9435 | /* Called when symbol NAME cannot be found in the symbol table. |
| 9436 | Should be used for dynamic valued symbols only. */ |
| 9437 | |
| 9438 | symbolS * |
| 9439 | md_undefined_symbol (name) |
| 9440 | char *name ATTRIBUTE_UNUSED; |
| 9441 | { |
| 9442 | return 0; |
| 9443 | } |
| 9444 | |
| 9445 | /* Called for any expression that can not be recognized. When the |
| 9446 | function is called, `input_line_pointer' will point to the start of |
| 9447 | the expression. */ |
| 9448 | |
| 9449 | void |
| 9450 | md_operand (e) |
| 9451 | expressionS *e; |
| 9452 | { |
| 9453 | enum pseudo_type pseudo_type; |
| 9454 | const char *name; |
| 9455 | size_t len; |
| 9456 | int ch, i; |
| 9457 | |
| 9458 | switch (*input_line_pointer) |
| 9459 | { |
| 9460 | case '@': |
| 9461 | /* Find what relocation pseudo-function we're dealing with. */ |
| 9462 | pseudo_type = 0; |
| 9463 | ch = *++input_line_pointer; |
| 9464 | for (i = 0; i < NELEMS (pseudo_func); ++i) |
| 9465 | if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) |
| 9466 | { |
| 9467 | len = strlen (pseudo_func[i].name); |
| 9468 | if (strncmp (pseudo_func[i].name + 1, |
| 9469 | input_line_pointer + 1, len - 1) == 0 |
| 9470 | && !is_part_of_name (input_line_pointer[len])) |
| 9471 | { |
| 9472 | input_line_pointer += len; |
| 9473 | pseudo_type = pseudo_func[i].type; |
| 9474 | break; |
| 9475 | } |
| 9476 | } |
| 9477 | switch (pseudo_type) |
| 9478 | { |
| 9479 | case PSEUDO_FUNC_RELOC: |
| 9480 | SKIP_WHITESPACE (); |
| 9481 | if (*input_line_pointer != '(') |
| 9482 | { |
| 9483 | as_bad ("Expected '('"); |
| 9484 | goto err; |
| 9485 | } |
| 9486 | /* Skip '('. */ |
| 9487 | ++input_line_pointer; |
| 9488 | expression (e); |
| 9489 | if (*input_line_pointer++ != ')') |
| 9490 | { |
| 9491 | as_bad ("Missing ')'"); |
| 9492 | goto err; |
| 9493 | } |
| 9494 | if (e->X_op != O_symbol) |
| 9495 | { |
| 9496 | if (e->X_op != O_pseudo_fixup) |
| 9497 | { |
| 9498 | as_bad ("Not a symbolic expression"); |
| 9499 | goto err; |
| 9500 | } |
| 9501 | if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE |
| 9502 | && i == FUNC_LT_RELATIVE) |
| 9503 | i = FUNC_LT_FPTR_RELATIVE; |
| 9504 | else |
| 9505 | { |
| 9506 | as_bad ("Illegal combination of relocation functions"); |
| 9507 | goto err; |
| 9508 | } |
| 9509 | } |
| 9510 | /* Make sure gas doesn't get rid of local symbols that are used |
| 9511 | in relocs. */ |
| 9512 | e->X_op = O_pseudo_fixup; |
| 9513 | e->X_op_symbol = pseudo_func[i].u.sym; |
| 9514 | break; |
| 9515 | |
| 9516 | case PSEUDO_FUNC_CONST: |
| 9517 | e->X_op = O_constant; |
| 9518 | e->X_add_number = pseudo_func[i].u.ival; |
| 9519 | break; |
| 9520 | |
| 9521 | case PSEUDO_FUNC_REG: |
| 9522 | e->X_op = O_register; |
| 9523 | e->X_add_number = pseudo_func[i].u.ival; |
| 9524 | break; |
| 9525 | |
| 9526 | default: |
| 9527 | name = input_line_pointer - 1; |
| 9528 | get_symbol_end (); |
| 9529 | as_bad ("Unknown pseudo function `%s'", name); |
| 9530 | goto err; |
| 9531 | } |
| 9532 | break; |
| 9533 | |
| 9534 | case '[': |
| 9535 | ++input_line_pointer; |
| 9536 | expression (e); |
| 9537 | if (*input_line_pointer != ']') |
| 9538 | { |
| 9539 | as_bad ("Closing bracket misssing"); |
| 9540 | goto err; |
| 9541 | } |
| 9542 | else |
| 9543 | { |
| 9544 | if (e->X_op != O_register) |
| 9545 | as_bad ("Register expected as index"); |
| 9546 | |
| 9547 | ++input_line_pointer; |
| 9548 | e->X_op = O_index; |
| 9549 | } |
| 9550 | break; |
| 9551 | |
| 9552 | default: |
| 9553 | break; |
| 9554 | } |
| 9555 | return; |
| 9556 | |
| 9557 | err: |
| 9558 | ignore_rest_of_line (); |
| 9559 | } |
| 9560 | |
| 9561 | /* Return 1 if it's OK to adjust a reloc by replacing the symbol with |
| 9562 | a section symbol plus some offset. For relocs involving @fptr(), |
| 9563 | directives we don't want such adjustments since we need to have the |
| 9564 | original symbol's name in the reloc. */ |
| 9565 | int |
| 9566 | ia64_fix_adjustable (fix) |
| 9567 | fixS *fix; |
| 9568 | { |
| 9569 | /* Prevent all adjustments to global symbols */ |
| 9570 | if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) |
| 9571 | return 0; |
| 9572 | |
| 9573 | switch (fix->fx_r_type) |
| 9574 | { |
| 9575 | case BFD_RELOC_IA64_FPTR64I: |
| 9576 | case BFD_RELOC_IA64_FPTR32MSB: |
| 9577 | case BFD_RELOC_IA64_FPTR32LSB: |
| 9578 | case BFD_RELOC_IA64_FPTR64MSB: |
| 9579 | case BFD_RELOC_IA64_FPTR64LSB: |
| 9580 | case BFD_RELOC_IA64_LTOFF_FPTR22: |
| 9581 | case BFD_RELOC_IA64_LTOFF_FPTR64I: |
| 9582 | return 0; |
| 9583 | default: |
| 9584 | break; |
| 9585 | } |
| 9586 | |
| 9587 | return 1; |
| 9588 | } |
| 9589 | |
| 9590 | int |
| 9591 | ia64_force_relocation (fix) |
| 9592 | fixS *fix; |
| 9593 | { |
| 9594 | switch (fix->fx_r_type) |
| 9595 | { |
| 9596 | case BFD_RELOC_IA64_FPTR64I: |
| 9597 | case BFD_RELOC_IA64_FPTR32MSB: |
| 9598 | case BFD_RELOC_IA64_FPTR32LSB: |
| 9599 | case BFD_RELOC_IA64_FPTR64MSB: |
| 9600 | case BFD_RELOC_IA64_FPTR64LSB: |
| 9601 | |
| 9602 | case BFD_RELOC_IA64_LTOFF22: |
| 9603 | case BFD_RELOC_IA64_LTOFF64I: |
| 9604 | case BFD_RELOC_IA64_LTOFF_FPTR22: |
| 9605 | case BFD_RELOC_IA64_LTOFF_FPTR64I: |
| 9606 | case BFD_RELOC_IA64_PLTOFF22: |
| 9607 | case BFD_RELOC_IA64_PLTOFF64I: |
| 9608 | case BFD_RELOC_IA64_PLTOFF64MSB: |
| 9609 | case BFD_RELOC_IA64_PLTOFF64LSB: |
| 9610 | return 1; |
| 9611 | |
| 9612 | default: |
| 9613 | return 0; |
| 9614 | } |
| 9615 | return 0; |
| 9616 | } |
| 9617 | |
| 9618 | /* Decide from what point a pc-relative relocation is relative to, |
| 9619 | relative to the pc-relative fixup. Er, relatively speaking. */ |
| 9620 | long |
| 9621 | ia64_pcrel_from_section (fix, sec) |
| 9622 | fixS *fix; |
| 9623 | segT sec; |
| 9624 | { |
| 9625 | unsigned long off = fix->fx_frag->fr_address + fix->fx_where; |
| 9626 | |
| 9627 | if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) |
| 9628 | off &= ~0xfUL; |
| 9629 | |
| 9630 | return off; |
| 9631 | } |
| 9632 | |
| 9633 | /* This is called whenever some data item (not an instruction) needs a |
| 9634 | fixup. We pick the right reloc code depending on the byteorder |
| 9635 | currently in effect. */ |
| 9636 | void |
| 9637 | ia64_cons_fix_new (f, where, nbytes, exp) |
| 9638 | fragS *f; |
| 9639 | int where; |
| 9640 | int nbytes; |
| 9641 | expressionS *exp; |
| 9642 | { |
| 9643 | bfd_reloc_code_real_type code; |
| 9644 | fixS *fix; |
| 9645 | |
| 9646 | switch (nbytes) |
| 9647 | { |
| 9648 | /* There are no reloc for 8 and 16 bit quantities, but we allow |
| 9649 | them here since they will work fine as long as the expression |
| 9650 | is fully defined at the end of the pass over the source file. */ |
| 9651 | case 1: code = BFD_RELOC_8; break; |
| 9652 | case 2: code = BFD_RELOC_16; break; |
| 9653 | case 4: |
| 9654 | if (target_big_endian) |
| 9655 | code = BFD_RELOC_IA64_DIR32MSB; |
| 9656 | else |
| 9657 | code = BFD_RELOC_IA64_DIR32LSB; |
| 9658 | break; |
| 9659 | |
| 9660 | case 8: |
| 9661 | if (target_big_endian) |
| 9662 | code = BFD_RELOC_IA64_DIR64MSB; |
| 9663 | else |
| 9664 | code = BFD_RELOC_IA64_DIR64LSB; |
| 9665 | break; |
| 9666 | |
| 9667 | default: |
| 9668 | as_bad ("Unsupported fixup size %d", nbytes); |
| 9669 | ignore_rest_of_line (); |
| 9670 | return; |
| 9671 | } |
| 9672 | if (exp->X_op == O_pseudo_fixup) |
| 9673 | { |
| 9674 | /* ??? */ |
| 9675 | exp->X_op = O_symbol; |
| 9676 | code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); |
| 9677 | } |
| 9678 | fix = fix_new_exp (f, where, nbytes, exp, 0, code); |
| 9679 | /* We need to store the byte order in effect in case we're going |
| 9680 | to fix an 8 or 16 bit relocation (for which there no real |
| 9681 | relocs available). See md_apply_fix(). */ |
| 9682 | fix->tc_fix_data.bigendian = target_big_endian; |
| 9683 | } |
| 9684 | |
| 9685 | /* Return the actual relocation we wish to associate with the pseudo |
| 9686 | reloc described by SYM and R_TYPE. SYM should be one of the |
| 9687 | symbols in the pseudo_func array, or NULL. */ |
| 9688 | |
| 9689 | static bfd_reloc_code_real_type |
| 9690 | ia64_gen_real_reloc_type (sym, r_type) |
| 9691 | struct symbol *sym; |
| 9692 | bfd_reloc_code_real_type r_type; |
| 9693 | { |
| 9694 | bfd_reloc_code_real_type new = 0; |
| 9695 | |
| 9696 | if (sym == NULL) |
| 9697 | { |
| 9698 | return r_type; |
| 9699 | } |
| 9700 | |
| 9701 | switch (S_GET_VALUE (sym)) |
| 9702 | { |
| 9703 | case FUNC_FPTR_RELATIVE: |
| 9704 | switch (r_type) |
| 9705 | { |
| 9706 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; |
| 9707 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; |
| 9708 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; |
| 9709 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; |
| 9710 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; |
| 9711 | default: break; |
| 9712 | } |
| 9713 | break; |
| 9714 | |
| 9715 | case FUNC_GP_RELATIVE: |
| 9716 | switch (r_type) |
| 9717 | { |
| 9718 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; |
| 9719 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; |
| 9720 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; |
| 9721 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; |
| 9722 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; |
| 9723 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; |
| 9724 | default: break; |
| 9725 | } |
| 9726 | break; |
| 9727 | |
| 9728 | case FUNC_LT_RELATIVE: |
| 9729 | switch (r_type) |
| 9730 | { |
| 9731 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; |
| 9732 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; |
| 9733 | default: break; |
| 9734 | } |
| 9735 | break; |
| 9736 | |
| 9737 | case FUNC_PC_RELATIVE: |
| 9738 | switch (r_type) |
| 9739 | { |
| 9740 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; |
| 9741 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; |
| 9742 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; |
| 9743 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; |
| 9744 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; |
| 9745 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; |
| 9746 | default: break; |
| 9747 | } |
| 9748 | break; |
| 9749 | |
| 9750 | case FUNC_PLT_RELATIVE: |
| 9751 | switch (r_type) |
| 9752 | { |
| 9753 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; |
| 9754 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; |
| 9755 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; |
| 9756 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; |
| 9757 | default: break; |
| 9758 | } |
| 9759 | break; |
| 9760 | |
| 9761 | case FUNC_SEC_RELATIVE: |
| 9762 | switch (r_type) |
| 9763 | { |
| 9764 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; |
| 9765 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; |
| 9766 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; |
| 9767 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; |
| 9768 | default: break; |
| 9769 | } |
| 9770 | break; |
| 9771 | |
| 9772 | case FUNC_SEG_RELATIVE: |
| 9773 | switch (r_type) |
| 9774 | { |
| 9775 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; |
| 9776 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; |
| 9777 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; |
| 9778 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; |
| 9779 | default: break; |
| 9780 | } |
| 9781 | break; |
| 9782 | |
| 9783 | case FUNC_LTV_RELATIVE: |
| 9784 | switch (r_type) |
| 9785 | { |
| 9786 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; |
| 9787 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; |
| 9788 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; |
| 9789 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; |
| 9790 | default: break; |
| 9791 | } |
| 9792 | break; |
| 9793 | |
| 9794 | case FUNC_LT_FPTR_RELATIVE: |
| 9795 | switch (r_type) |
| 9796 | { |
| 9797 | case BFD_RELOC_IA64_IMM22: |
| 9798 | new = BFD_RELOC_IA64_LTOFF_FPTR22; break; |
| 9799 | case BFD_RELOC_IA64_IMM64: |
| 9800 | new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; |
| 9801 | default: |
| 9802 | break; |
| 9803 | } |
| 9804 | break; |
| 9805 | default: |
| 9806 | abort (); |
| 9807 | } |
| 9808 | /* Hmmmm. Should this ever occur? */ |
| 9809 | if (new) |
| 9810 | return new; |
| 9811 | else |
| 9812 | return r_type; |
| 9813 | } |
| 9814 | |
| 9815 | /* Here is where generate the appropriate reloc for pseudo relocation |
| 9816 | functions. */ |
| 9817 | void |
| 9818 | ia64_validate_fix (fix) |
| 9819 | fixS *fix; |
| 9820 | { |
| 9821 | switch (fix->fx_r_type) |
| 9822 | { |
| 9823 | case BFD_RELOC_IA64_FPTR64I: |
| 9824 | case BFD_RELOC_IA64_FPTR32MSB: |
| 9825 | case BFD_RELOC_IA64_FPTR64LSB: |
| 9826 | case BFD_RELOC_IA64_LTOFF_FPTR22: |
| 9827 | case BFD_RELOC_IA64_LTOFF_FPTR64I: |
| 9828 | if (fix->fx_offset != 0) |
| 9829 | as_bad_where (fix->fx_file, fix->fx_line, |
| 9830 | "No addend allowed in @fptr() relocation"); |
| 9831 | break; |
| 9832 | default: |
| 9833 | break; |
| 9834 | } |
| 9835 | |
| 9836 | return; |
| 9837 | } |
| 9838 | |
| 9839 | static void |
| 9840 | fix_insn (fix, odesc, value) |
| 9841 | fixS *fix; |
| 9842 | const struct ia64_operand *odesc; |
| 9843 | valueT value; |
| 9844 | { |
| 9845 | bfd_vma insn[3], t0, t1, control_bits; |
| 9846 | const char *err; |
| 9847 | char *fixpos; |
| 9848 | long slot; |
| 9849 | |
| 9850 | slot = fix->fx_where & 0x3; |
| 9851 | fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); |
| 9852 | |
| 9853 | /* Bundles are always in little-endian byte order */ |
| 9854 | t0 = bfd_getl64 (fixpos); |
| 9855 | t1 = bfd_getl64 (fixpos + 8); |
| 9856 | control_bits = t0 & 0x1f; |
| 9857 | insn[0] = (t0 >> 5) & 0x1ffffffffffLL; |
| 9858 | insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); |
| 9859 | insn[2] = (t1 >> 23) & 0x1ffffffffffLL; |
| 9860 | |
| 9861 | err = NULL; |
| 9862 | if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) |
| 9863 | { |
| 9864 | insn[1] = (value >> 22) & 0x1ffffffffffLL; |
| 9865 | insn[2] |= (((value & 0x7f) << 13) |
| 9866 | | (((value >> 7) & 0x1ff) << 27) |
| 9867 | | (((value >> 16) & 0x1f) << 22) |
| 9868 | | (((value >> 21) & 0x1) << 21) |
| 9869 | | (((value >> 63) & 0x1) << 36)); |
| 9870 | } |
| 9871 | else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) |
| 9872 | { |
| 9873 | if (value & ~0x3fffffffffffffffULL) |
| 9874 | err = "integer operand out of range"; |
| 9875 | insn[1] = (value >> 21) & 0x1ffffffffffLL; |
| 9876 | insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); |
| 9877 | } |
| 9878 | else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) |
| 9879 | { |
| 9880 | value >>= 4; |
| 9881 | insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; |
| 9882 | insn[2] |= ((((value >> 59) & 0x1) << 36) |
| 9883 | | (((value >> 0) & 0xfffff) << 13)); |
| 9884 | } |
| 9885 | else |
| 9886 | err = (*odesc->insert) (odesc, value, insn + slot); |
| 9887 | |
| 9888 | if (err) |
| 9889 | as_bad_where (fix->fx_file, fix->fx_line, err); |
| 9890 | |
| 9891 | t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); |
| 9892 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); |
| 9893 | number_to_chars_littleendian (fixpos + 0, t0, 8); |
| 9894 | number_to_chars_littleendian (fixpos + 8, t1, 8); |
| 9895 | } |
| 9896 | |
| 9897 | /* Attempt to simplify or even eliminate a fixup. The return value is |
| 9898 | ignored; perhaps it was once meaningful, but now it is historical. |
| 9899 | To indicate that a fixup has been eliminated, set FIXP->FX_DONE. |
| 9900 | |
| 9901 | If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry |
| 9902 | (if possible). */ |
| 9903 | int |
| 9904 | md_apply_fix3 (fix, valuep, seg) |
| 9905 | fixS *fix; |
| 9906 | valueT *valuep; |
| 9907 | segT seg ATTRIBUTE_UNUSED; |
| 9908 | { |
| 9909 | char *fixpos; |
| 9910 | valueT value = *valuep; |
| 9911 | int adjust = 0; |
| 9912 | |
| 9913 | fixpos = fix->fx_frag->fr_literal + fix->fx_where; |
| 9914 | |
| 9915 | if (fix->fx_pcrel) |
| 9916 | { |
| 9917 | switch (fix->fx_r_type) |
| 9918 | { |
| 9919 | case BFD_RELOC_IA64_DIR32MSB: |
| 9920 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; |
| 9921 | adjust = 1; |
| 9922 | break; |
| 9923 | |
| 9924 | case BFD_RELOC_IA64_DIR32LSB: |
| 9925 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; |
| 9926 | adjust = 1; |
| 9927 | break; |
| 9928 | |
| 9929 | case BFD_RELOC_IA64_DIR64MSB: |
| 9930 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; |
| 9931 | adjust = 1; |
| 9932 | break; |
| 9933 | |
| 9934 | case BFD_RELOC_IA64_DIR64LSB: |
| 9935 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; |
| 9936 | adjust = 1; |
| 9937 | break; |
| 9938 | |
| 9939 | default: |
| 9940 | break; |
| 9941 | } |
| 9942 | } |
| 9943 | if (fix->fx_addsy) |
| 9944 | { |
| 9945 | if (fix->fx_r_type == (int) BFD_RELOC_UNUSED) |
| 9946 | { |
| 9947 | /* This must be a TAG13 or TAG13b operand. There are no external |
| 9948 | relocs defined for them, so we must give an error. */ |
| 9949 | as_bad_where (fix->fx_file, fix->fx_line, |
| 9950 | "%s must have a constant value", |
| 9951 | elf64_ia64_operands[fix->tc_fix_data.opnd].desc); |
| 9952 | fix->fx_done = 1; |
| 9953 | return 1; |
| 9954 | } |
| 9955 | |
| 9956 | /* ??? This is a hack copied from tc-i386.c to make PCREL relocs |
| 9957 | work. There should be a better way to handle this. */ |
| 9958 | if (adjust) |
| 9959 | fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address; |
| 9960 | } |
| 9961 | else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) |
| 9962 | { |
| 9963 | if (fix->tc_fix_data.bigendian) |
| 9964 | number_to_chars_bigendian (fixpos, value, fix->fx_size); |
| 9965 | else |
| 9966 | number_to_chars_littleendian (fixpos, value, fix->fx_size); |
| 9967 | fix->fx_done = 1; |
| 9968 | return 1; |
| 9969 | } |
| 9970 | else |
| 9971 | { |
| 9972 | fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); |
| 9973 | fix->fx_done = 1; |
| 9974 | return 1; |
| 9975 | } |
| 9976 | return 1; |
| 9977 | } |
| 9978 | |
| 9979 | /* Generate the BFD reloc to be stuck in the object file from the |
| 9980 | fixup used internally in the assembler. */ |
| 9981 | |
| 9982 | arelent * |
| 9983 | tc_gen_reloc (sec, fixp) |
| 9984 | asection *sec ATTRIBUTE_UNUSED; |
| 9985 | fixS *fixp; |
| 9986 | { |
| 9987 | arelent *reloc; |
| 9988 | |
| 9989 | reloc = xmalloc (sizeof (*reloc)); |
| 9990 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 9991 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 9992 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 9993 | reloc->addend = fixp->fx_offset; |
| 9994 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
| 9995 | |
| 9996 | if (!reloc->howto) |
| 9997 | { |
| 9998 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 9999 | "Cannot represent %s relocation in object file", |
| 10000 | bfd_get_reloc_code_name (fixp->fx_r_type)); |
| 10001 | } |
| 10002 | return reloc; |
| 10003 | } |
| 10004 | |
| 10005 | /* Turn a string in input_line_pointer into a floating point constant |
| 10006 | of type TYPE, and store the appropriate bytes in *LIT. The number |
| 10007 | of LITTLENUMS emitted is stored in *SIZE. An error message is |
| 10008 | returned, or NULL on OK. */ |
| 10009 | |
| 10010 | #define MAX_LITTLENUMS 5 |
| 10011 | |
| 10012 | char * |
| 10013 | md_atof (type, lit, size) |
| 10014 | int type; |
| 10015 | char *lit; |
| 10016 | int *size; |
| 10017 | { |
| 10018 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 10019 | LITTLENUM_TYPE *word; |
| 10020 | char *t; |
| 10021 | int prec; |
| 10022 | |
| 10023 | switch (type) |
| 10024 | { |
| 10025 | /* IEEE floats */ |
| 10026 | case 'f': |
| 10027 | case 'F': |
| 10028 | case 's': |
| 10029 | case 'S': |
| 10030 | prec = 2; |
| 10031 | break; |
| 10032 | |
| 10033 | case 'd': |
| 10034 | case 'D': |
| 10035 | case 'r': |
| 10036 | case 'R': |
| 10037 | prec = 4; |
| 10038 | break; |
| 10039 | |
| 10040 | case 'x': |
| 10041 | case 'X': |
| 10042 | case 'p': |
| 10043 | case 'P': |
| 10044 | prec = 5; |
| 10045 | break; |
| 10046 | |
| 10047 | default: |
| 10048 | *size = 0; |
| 10049 | return "Bad call to MD_ATOF()"; |
| 10050 | } |
| 10051 | t = atof_ieee (input_line_pointer, type, words); |
| 10052 | if (t) |
| 10053 | input_line_pointer = t; |
| 10054 | *size = prec * sizeof (LITTLENUM_TYPE); |
| 10055 | |
| 10056 | for (word = words + prec - 1; prec--;) |
| 10057 | { |
| 10058 | md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE)); |
| 10059 | lit += sizeof (LITTLENUM_TYPE); |
| 10060 | } |
| 10061 | return 0; |
| 10062 | } |
| 10063 | |
| 10064 | /* Round up a section's size to the appropriate boundary. */ |
| 10065 | valueT |
| 10066 | md_section_align (seg, size) |
| 10067 | segT seg; |
| 10068 | valueT size; |
| 10069 | { |
| 10070 | int align = bfd_get_section_alignment (stdoutput, seg); |
| 10071 | valueT mask = ((valueT) 1 << align) - 1; |
| 10072 | |
| 10073 | return (size + mask) & ~mask; |
| 10074 | } |
| 10075 | |
| 10076 | /* Handle ia64 specific semantics of the align directive. */ |
| 10077 | |
| 10078 | void |
| 10079 | ia64_md_do_align (n, fill, len, max) |
| 10080 | int n ATTRIBUTE_UNUSED; |
| 10081 | const char *fill ATTRIBUTE_UNUSED; |
| 10082 | int len ATTRIBUTE_UNUSED; |
| 10083 | int max ATTRIBUTE_UNUSED; |
| 10084 | { |
| 10085 | if (subseg_text_p (now_seg)) |
| 10086 | ia64_flush_insns (); |
| 10087 | } |
| 10088 | |
| 10089 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
| 10090 | of an rs_align_code fragment. */ |
| 10091 | |
| 10092 | void |
| 10093 | ia64_handle_align (fragp) |
| 10094 | fragS *fragp; |
| 10095 | { |
| 10096 | /* Use mfi bundle of nops with no stop bits. */ |
| 10097 | static const unsigned char be_nop[] |
| 10098 | = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, |
| 10099 | 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; |
| 10100 | static const unsigned char le_nop[] |
| 10101 | = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, |
| 10102 | 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; |
| 10103 | |
| 10104 | int bytes; |
| 10105 | char *p; |
| 10106 | |
| 10107 | if (fragp->fr_type != rs_align_code) |
| 10108 | return; |
| 10109 | |
| 10110 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
| 10111 | p = fragp->fr_literal + fragp->fr_fix; |
| 10112 | |
| 10113 | /* Make sure we are on a 16-byte boundary, in case someone has been |
| 10114 | putting data into a text section. */ |
| 10115 | if (bytes & 15) |
| 10116 | { |
| 10117 | int fix = bytes & 15; |
| 10118 | memset (p, 0, fix); |
| 10119 | p += fix; |
| 10120 | bytes -= fix; |
| 10121 | fragp->fr_fix += fix; |
| 10122 | } |
| 10123 | |
| 10124 | memcpy (p, (target_big_endian ? be_nop : le_nop), 16); |
| 10125 | fragp->fr_var = 16; |
| 10126 | } |