| 1 | /* tc-m32r.c -- Assembler for the Renesas M32R. |
| 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GAS, the GNU Assembler. |
| 6 | |
| 7 | GAS is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | GAS is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to |
| 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | #include <stdio.h> |
| 23 | #include "as.h" |
| 24 | #include "safe-ctype.h" |
| 25 | #include "subsegs.h" |
| 26 | #include "symcat.h" |
| 27 | #include "opcodes/m32r-desc.h" |
| 28 | #include "opcodes/m32r-opc.h" |
| 29 | #include "cgen.h" |
| 30 | |
| 31 | /* Linked list of symbols that are debugging symbols to be defined as the |
| 32 | beginning of the current instruction. */ |
| 33 | typedef struct sym_link |
| 34 | { |
| 35 | struct sym_link *next; |
| 36 | symbolS *symbol; |
| 37 | } sym_linkS; |
| 38 | |
| 39 | static sym_linkS *debug_sym_link = (sym_linkS *) 0; |
| 40 | |
| 41 | /* Structure to hold all of the different components describing |
| 42 | an individual instruction. */ |
| 43 | typedef struct |
| 44 | { |
| 45 | const CGEN_INSN *insn; |
| 46 | const CGEN_INSN *orig_insn; |
| 47 | CGEN_FIELDS fields; |
| 48 | #if CGEN_INT_INSN_P |
| 49 | CGEN_INSN_INT buffer[1]; |
| 50 | #define INSN_VALUE(buf) (*(buf)) |
| 51 | #else |
| 52 | unsigned char buffer[CGEN_MAX_INSN_SIZE]; |
| 53 | #define INSN_VALUE(buf) (buf) |
| 54 | #endif |
| 55 | char *addr; |
| 56 | fragS *frag; |
| 57 | int num_fixups; |
| 58 | fixS *fixups[GAS_CGEN_MAX_FIXUPS]; |
| 59 | int indices[MAX_OPERAND_INSTANCES]; |
| 60 | sym_linkS *debug_sym_link; |
| 61 | } |
| 62 | m32r_insn; |
| 63 | |
| 64 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit |
| 65 | boundary (i.e. was the first of two 16 bit insns). */ |
| 66 | static m32r_insn prev_insn; |
| 67 | |
| 68 | /* Non-zero if we've seen a relaxable insn since the last 32 bit |
| 69 | alignment request. */ |
| 70 | static int seen_relaxable_p = 0; |
| 71 | |
| 72 | /* Non-zero if -relax specified, in which case sufficient relocs are output |
| 73 | for the linker to do relaxing. |
| 74 | We do simple forms of relaxing internally, but they are always done. |
| 75 | This flag does not apply to them. */ |
| 76 | static int m32r_relax; |
| 77 | |
| 78 | #if 0 |
| 79 | /* Not supported yet. */ |
| 80 | /* If non-NULL, pointer to cpu description file to read. |
| 81 | This allows runtime additions to the assembler. */ |
| 82 | static const char *m32r_cpu_desc; |
| 83 | #endif |
| 84 | |
| 85 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. |
| 86 | Each high/shigh reloc must be paired with it's low cousin in order to |
| 87 | properly calculate the addend in a relocatable link (since there is a |
| 88 | potential carry from the low to the high/shigh). |
| 89 | This option is off by default though for user-written assembler code it |
| 90 | might make sense to make the default be on (i.e. have gcc pass a flag |
| 91 | to turn it off). This warning must not be on for GCC created code as |
| 92 | optimization may delete the low but not the high/shigh (at least we |
| 93 | shouldn't assume or require it to). */ |
| 94 | static int warn_unmatched_high = 0; |
| 95 | |
| 96 | /* Non-zero if -m32rx has been specified, in which case support for the |
| 97 | extended M32RX instruction set should be enabled. */ |
| 98 | static int enable_m32rx = 0; |
| 99 | |
| 100 | /* Non-zero if -m32rx -hidden has been specified, in which case support for |
| 101 | the special M32RX instruction set should be enabled. */ |
| 102 | static int enable_special = 0; |
| 103 | |
| 104 | /* Non-zero if the programmer should be warned when an explicit parallel |
| 105 | instruction might have constraint violations. */ |
| 106 | static int warn_explicit_parallel_conflicts = 1; |
| 107 | |
| 108 | /* Non-zero if insns can be made parallel. */ |
| 109 | static int optimize; |
| 110 | |
| 111 | /* Stuff for .scomm symbols. */ |
| 112 | static segT sbss_section; |
| 113 | static asection scom_section; |
| 114 | static asymbol scom_symbol; |
| 115 | |
| 116 | const char comment_chars[] = ";"; |
| 117 | const char line_comment_chars[] = "#"; |
| 118 | const char line_separator_chars[] = ""; |
| 119 | const char EXP_CHARS[] = "eE"; |
| 120 | const char FLT_CHARS[] = "dD"; |
| 121 | |
| 122 | /* Relocations against symbols are done in two |
| 123 | parts, with a HI relocation and a LO relocation. Each relocation |
| 124 | has only 16 bits of space to store an addend. This means that in |
| 125 | order for the linker to handle carries correctly, it must be able |
| 126 | to locate both the HI and the LO relocation. This means that the |
| 127 | relocations must appear in order in the relocation table. |
| 128 | |
| 129 | In order to implement this, we keep track of each unmatched HI |
| 130 | relocation. We then sort them so that they immediately precede the |
| 131 | corresponding LO relocation. */ |
| 132 | |
| 133 | struct m32r_hi_fixup |
| 134 | { |
| 135 | /* Next HI fixup. */ |
| 136 | struct m32r_hi_fixup *next; |
| 137 | |
| 138 | /* This fixup. */ |
| 139 | fixS *fixp; |
| 140 | |
| 141 | /* The section this fixup is in. */ |
| 142 | segT seg; |
| 143 | }; |
| 144 | |
| 145 | /* The list of unmatched HI relocs. */ |
| 146 | |
| 147 | static struct m32r_hi_fixup *m32r_hi_fixup_list; |
| 148 | \f |
| 149 | static void allow_m32rx PARAMS ((int)); |
| 150 | |
| 151 | static void |
| 152 | allow_m32rx (on) |
| 153 | int on; |
| 154 | { |
| 155 | enable_m32rx = on; |
| 156 | |
| 157 | if (stdoutput != NULL) |
| 158 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, |
| 159 | enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r); |
| 160 | } |
| 161 | \f |
| 162 | #define M32R_SHORTOPTS "O" |
| 163 | |
| 164 | const char *md_shortopts = M32R_SHORTOPTS; |
| 165 | |
| 166 | struct option md_longopts[] = |
| 167 | { |
| 168 | #define OPTION_M32R (OPTION_MD_BASE) |
| 169 | #define OPTION_M32RX (OPTION_M32R + 1) |
| 170 | #define OPTION_WARN_PARALLEL (OPTION_M32RX + 1) |
| 171 | #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1) |
| 172 | #define OPTION_SPECIAL (OPTION_NO_WARN_PARALLEL + 1) |
| 173 | #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL + 1) |
| 174 | #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1) |
| 175 | {"m32r", no_argument, NULL, OPTION_M32R}, |
| 176 | {"m32rx", no_argument, NULL, OPTION_M32RX}, |
| 177 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, |
| 178 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, |
| 179 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
| 180 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
| 181 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
| 182 | /* Sigh. I guess all warnings must now have both variants. */ |
| 183 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
| 184 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
| 185 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
| 186 | {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
| 187 | |
| 188 | #if 0 |
| 189 | /* Not supported yet. */ |
| 190 | #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1) |
| 191 | #define OPTION_CPU_DESC (OPTION_RELAX + 1) |
| 192 | {"relax", no_argument, NULL, OPTION_RELAX}, |
| 193 | {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, |
| 194 | #endif |
| 195 | {NULL, no_argument, NULL, 0} |
| 196 | }; |
| 197 | |
| 198 | size_t md_longopts_size = sizeof (md_longopts); |
| 199 | |
| 200 | int |
| 201 | md_parse_option (c, arg) |
| 202 | int c; |
| 203 | char *arg ATTRIBUTE_UNUSED; |
| 204 | { |
| 205 | switch (c) |
| 206 | { |
| 207 | case 'O': |
| 208 | optimize = 1; |
| 209 | break; |
| 210 | |
| 211 | case OPTION_M32R: |
| 212 | allow_m32rx (0); |
| 213 | break; |
| 214 | |
| 215 | case OPTION_M32RX: |
| 216 | allow_m32rx (1); |
| 217 | break; |
| 218 | |
| 219 | case OPTION_WARN_PARALLEL: |
| 220 | warn_explicit_parallel_conflicts = 1; |
| 221 | break; |
| 222 | |
| 223 | case OPTION_NO_WARN_PARALLEL: |
| 224 | warn_explicit_parallel_conflicts = 0; |
| 225 | break; |
| 226 | |
| 227 | case OPTION_SPECIAL: |
| 228 | if (enable_m32rx) |
| 229 | enable_special = 1; |
| 230 | else |
| 231 | { |
| 232 | /* Pretend that we do not recognise this option. */ |
| 233 | as_bad (_("Unrecognised option: -hidden")); |
| 234 | return 0; |
| 235 | } |
| 236 | break; |
| 237 | |
| 238 | case OPTION_WARN_UNMATCHED: |
| 239 | warn_unmatched_high = 1; |
| 240 | break; |
| 241 | |
| 242 | case OPTION_NO_WARN_UNMATCHED: |
| 243 | warn_unmatched_high = 0; |
| 244 | break; |
| 245 | |
| 246 | #if 0 |
| 247 | /* Not supported yet. */ |
| 248 | case OPTION_RELAX: |
| 249 | m32r_relax = 1; |
| 250 | break; |
| 251 | case OPTION_CPU_DESC: |
| 252 | m32r_cpu_desc = arg; |
| 253 | break; |
| 254 | #endif |
| 255 | |
| 256 | default: |
| 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | return 1; |
| 261 | } |
| 262 | |
| 263 | void |
| 264 | md_show_usage (stream) |
| 265 | FILE *stream; |
| 266 | { |
| 267 | fprintf (stream, _(" M32R specific command line options:\n")); |
| 268 | |
| 269 | fprintf (stream, _("\ |
| 270 | -m32r disable support for the m32rx instruction set\n")); |
| 271 | fprintf (stream, _("\ |
| 272 | -m32rx support the extended m32rx instruction set\n")); |
| 273 | fprintf (stream, _("\ |
| 274 | -O try to combine instructions in parallel\n")); |
| 275 | |
| 276 | fprintf (stream, _("\ |
| 277 | -warn-explicit-parallel-conflicts warn when parallel instructions\n")); |
| 278 | fprintf (stream, _("\ |
| 279 | violate contraints\n")); |
| 280 | fprintf (stream, _("\ |
| 281 | -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); |
| 282 | fprintf (stream, _("\ |
| 283 | instructions violate contraints\n")); |
| 284 | fprintf (stream, _("\ |
| 285 | -Wp synonym for -warn-explicit-parallel-conflicts\n")); |
| 286 | fprintf (stream, _("\ |
| 287 | -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); |
| 288 | |
| 289 | fprintf (stream, _("\ |
| 290 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); |
| 291 | fprintf (stream, _("\ |
| 292 | -no-warn-unmatched-high do not warn about missing low relocs\n")); |
| 293 | fprintf (stream, _("\ |
| 294 | -Wuh synonym for -warn-unmatched-high\n")); |
| 295 | fprintf (stream, _("\ |
| 296 | -Wnuh synonym for -no-warn-unmatched-high\n")); |
| 297 | |
| 298 | #if 0 |
| 299 | fprintf (stream, _("\ |
| 300 | -relax create linker relaxable code\n")); |
| 301 | fprintf (stream, _("\ |
| 302 | -cpu-desc provide runtime cpu description file\n")); |
| 303 | #endif |
| 304 | } |
| 305 | |
| 306 | static void fill_insn PARAMS ((int)); |
| 307 | static void m32r_scomm PARAMS ((int)); |
| 308 | static void debug_sym PARAMS ((int)); |
| 309 | static void expand_debug_syms PARAMS ((sym_linkS *, int)); |
| 310 | |
| 311 | /* Set by md_assemble for use by m32r_fill_insn. */ |
| 312 | static subsegT prev_subseg; |
| 313 | static segT prev_seg; |
| 314 | |
| 315 | /* The target specific pseudo-ops which we support. */ |
| 316 | const pseudo_typeS md_pseudo_table[] = |
| 317 | { |
| 318 | { "word", cons, 4 }, |
| 319 | { "fillinsn", fill_insn, 0 }, |
| 320 | { "scomm", m32r_scomm, 0 }, |
| 321 | { "debugsym", debug_sym, 0 }, |
| 322 | /* Not documented as so far there is no need for them.... */ |
| 323 | { "m32r", allow_m32rx, 0 }, |
| 324 | { "m32rx", allow_m32rx, 1 }, |
| 325 | { NULL, NULL, 0 } |
| 326 | }; |
| 327 | |
| 328 | /* FIXME: Should be machine generated. */ |
| 329 | #define NOP_INSN 0x7000 |
| 330 | #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ |
| 331 | |
| 332 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
| 333 | of an rs_align_code fragment. */ |
| 334 | |
| 335 | void |
| 336 | m32r_handle_align (fragp) |
| 337 | fragS *fragp; |
| 338 | { |
| 339 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; |
| 340 | static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; |
| 341 | |
| 342 | int bytes, fix; |
| 343 | char *p; |
| 344 | |
| 345 | if (fragp->fr_type != rs_align_code) |
| 346 | return; |
| 347 | |
| 348 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
| 349 | p = fragp->fr_literal + fragp->fr_fix; |
| 350 | fix = 0; |
| 351 | |
| 352 | if (bytes & 1) |
| 353 | { |
| 354 | fix = 1; |
| 355 | *p++ = 0; |
| 356 | bytes--; |
| 357 | } |
| 358 | |
| 359 | if (bytes & 2) |
| 360 | { |
| 361 | memcpy (p, nop_pattern, 2); |
| 362 | p += 2; |
| 363 | bytes -= 2; |
| 364 | fix += 2; |
| 365 | } |
| 366 | |
| 367 | memcpy (p, multi_nop_pattern, 4); |
| 368 | |
| 369 | fragp->fr_fix += fix; |
| 370 | fragp->fr_var = 4; |
| 371 | } |
| 372 | |
| 373 | /* If the last instruction was the first of 2 16 bit insns, |
| 374 | output a nop to move the PC to a 32 bit boundary. |
| 375 | |
| 376 | This is done via an alignment specification since branch relaxing |
| 377 | may make it unnecessary. |
| 378 | |
| 379 | Internally, we need to output one of these each time a 32 bit insn is |
| 380 | seen after an insn that is relaxable. */ |
| 381 | |
| 382 | static void |
| 383 | fill_insn (ignore) |
| 384 | int ignore ATTRIBUTE_UNUSED; |
| 385 | { |
| 386 | frag_align_code (2, 0); |
| 387 | prev_insn.insn = NULL; |
| 388 | seen_relaxable_p = 0; |
| 389 | } |
| 390 | |
| 391 | /* Record the symbol so that when we output the insn, we can create |
| 392 | a symbol that is at the start of the instruction. This is used |
| 393 | to emit the label for the start of a breakpoint without causing |
| 394 | the assembler to emit a NOP if the previous instruction was a |
| 395 | 16 bit instruction. */ |
| 396 | |
| 397 | static void |
| 398 | debug_sym (ignore) |
| 399 | int ignore ATTRIBUTE_UNUSED; |
| 400 | { |
| 401 | register char *name; |
| 402 | register char delim; |
| 403 | register char *end_name; |
| 404 | register symbolS *symbolP; |
| 405 | register sym_linkS *link; |
| 406 | |
| 407 | name = input_line_pointer; |
| 408 | delim = get_symbol_end (); |
| 409 | end_name = input_line_pointer; |
| 410 | |
| 411 | if ((symbolP = symbol_find (name)) == NULL |
| 412 | && (symbolP = md_undefined_symbol (name)) == NULL) |
| 413 | { |
| 414 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); |
| 415 | } |
| 416 | |
| 417 | symbol_table_insert (symbolP); |
| 418 | if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section) |
| 419 | /* xgettext:c-format */ |
| 420 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); |
| 421 | |
| 422 | else |
| 423 | { |
| 424 | link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); |
| 425 | link->symbol = symbolP; |
| 426 | link->next = debug_sym_link; |
| 427 | debug_sym_link = link; |
| 428 | symbol_get_obj (symbolP)->local = 1; |
| 429 | } |
| 430 | |
| 431 | *end_name = delim; |
| 432 | demand_empty_rest_of_line (); |
| 433 | } |
| 434 | |
| 435 | /* Second pass to expanding the debug symbols, go through linked |
| 436 | list of symbols and reassign the address. */ |
| 437 | |
| 438 | static void |
| 439 | expand_debug_syms (syms, align) |
| 440 | sym_linkS *syms; |
| 441 | int align; |
| 442 | { |
| 443 | char *save_input_line = input_line_pointer; |
| 444 | sym_linkS *next_syms; |
| 445 | |
| 446 | if (!syms) |
| 447 | return; |
| 448 | |
| 449 | (void) frag_align_code (align, 0); |
| 450 | for (; syms != (sym_linkS *) 0; syms = next_syms) |
| 451 | { |
| 452 | symbolS *symbolP = syms->symbol; |
| 453 | next_syms = syms->next; |
| 454 | input_line_pointer = ".\n"; |
| 455 | pseudo_set (symbolP); |
| 456 | free ((char *) syms); |
| 457 | } |
| 458 | |
| 459 | input_line_pointer = save_input_line; |
| 460 | } |
| 461 | |
| 462 | /* Cover function to fill_insn called after a label and at end of assembly. |
| 463 | The result is always 1: we're called in a conditional to see if the |
| 464 | current line is a label. */ |
| 465 | |
| 466 | int |
| 467 | m32r_fill_insn (done) |
| 468 | int done; |
| 469 | { |
| 470 | if (prev_seg != NULL) |
| 471 | { |
| 472 | segT seg = now_seg; |
| 473 | subsegT subseg = now_subseg; |
| 474 | |
| 475 | subseg_set (prev_seg, prev_subseg); |
| 476 | |
| 477 | fill_insn (0); |
| 478 | |
| 479 | subseg_set (seg, subseg); |
| 480 | } |
| 481 | |
| 482 | if (done && debug_sym_link) |
| 483 | { |
| 484 | expand_debug_syms (debug_sym_link, 1); |
| 485 | debug_sym_link = (sym_linkS *) 0; |
| 486 | } |
| 487 | |
| 488 | return 1; |
| 489 | } |
| 490 | \f |
| 491 | void |
| 492 | md_begin () |
| 493 | { |
| 494 | flagword applicable; |
| 495 | segT seg; |
| 496 | subsegT subseg; |
| 497 | |
| 498 | /* Initialize the `cgen' interface. */ |
| 499 | |
| 500 | /* Set the machine number and endian. */ |
| 501 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, |
| 502 | CGEN_CPU_OPEN_ENDIAN, |
| 503 | CGEN_ENDIAN_BIG, |
| 504 | CGEN_CPU_OPEN_END); |
| 505 | m32r_cgen_init_asm (gas_cgen_cpu_desc); |
| 506 | |
| 507 | /* The operand instance table is used during optimization to determine |
| 508 | which insns can be executed in parallel. It is also used to give |
| 509 | warnings regarding operand interference in parallel insns. */ |
| 510 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); |
| 511 | |
| 512 | /* This is a callback from cgen to gas to parse operands. */ |
| 513 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); |
| 514 | |
| 515 | #if 0 |
| 516 | /* Not supported yet. */ |
| 517 | /* If a runtime cpu description file was provided, parse it. */ |
| 518 | if (m32r_cpu_desc != NULL) |
| 519 | { |
| 520 | const char *errmsg; |
| 521 | |
| 522 | errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc); |
| 523 | if (errmsg != NULL) |
| 524 | as_bad ("%s: %s", m32r_cpu_desc, errmsg); |
| 525 | } |
| 526 | #endif |
| 527 | |
| 528 | /* Save the current subseg so we can restore it [it's the default one and |
| 529 | we don't want the initial section to be .sbss]. */ |
| 530 | seg = now_seg; |
| 531 | subseg = now_subseg; |
| 532 | |
| 533 | /* The sbss section is for local .scomm symbols. */ |
| 534 | sbss_section = subseg_new (".sbss", 0); |
| 535 | |
| 536 | /* This is copied from perform_an_assembly_pass. */ |
| 537 | applicable = bfd_applicable_section_flags (stdoutput); |
| 538 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); |
| 539 | |
| 540 | #if 0 |
| 541 | /* What does this do? [see perform_an_assembly_pass] */ |
| 542 | seg_info (bss_section)->bss = 1; |
| 543 | #endif |
| 544 | |
| 545 | subseg_set (seg, subseg); |
| 546 | |
| 547 | /* We must construct a fake section similar to bfd_com_section |
| 548 | but with the name .scommon. */ |
| 549 | scom_section = bfd_com_section; |
| 550 | scom_section.name = ".scommon"; |
| 551 | scom_section.output_section = &scom_section; |
| 552 | scom_section.symbol = &scom_symbol; |
| 553 | scom_section.symbol_ptr_ptr = &scom_section.symbol; |
| 554 | scom_symbol = *bfd_com_section.symbol; |
| 555 | scom_symbol.name = ".scommon"; |
| 556 | scom_symbol.section = &scom_section; |
| 557 | |
| 558 | allow_m32rx (enable_m32rx); |
| 559 | |
| 560 | gas_cgen_initialize_saved_fixups_array (); |
| 561 | } |
| 562 | |
| 563 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ |
| 564 | ((operand)->hw_type == HW_H_COND \ |
| 565 | || ((operand)->hw_type == HW_H_PSW) \ |
| 566 | || ((operand)->hw_type == HW_H_CR \ |
| 567 | && (indices [index] == 0 || indices [index] == 1))) |
| 568 | |
| 569 | /* Returns true if an output of instruction 'a' is referenced by an operand |
| 570 | of instruction 'b'. If 'check_outputs' is true then b's outputs are |
| 571 | checked, otherwise its inputs are examined. */ |
| 572 | |
| 573 | static int first_writes_to_seconds_operands |
| 574 | PARAMS ((m32r_insn *, m32r_insn *, const int)); |
| 575 | |
| 576 | static int |
| 577 | first_writes_to_seconds_operands (a, b, check_outputs) |
| 578 | m32r_insn *a; |
| 579 | m32r_insn *b; |
| 580 | const int check_outputs; |
| 581 | { |
| 582 | const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); |
| 583 | const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); |
| 584 | int a_index; |
| 585 | |
| 586 | /* If at least one of the instructions takes no operands, then there is |
| 587 | nothing to check. There really are instructions without operands, |
| 588 | eg 'nop'. */ |
| 589 | if (a_operands == NULL || b_ops == NULL) |
| 590 | return 0; |
| 591 | |
| 592 | /* Scan the operand list of 'a' looking for an output operand. */ |
| 593 | for (a_index = 0; |
| 594 | a_operands->type != CGEN_OPINST_END; |
| 595 | a_index ++, a_operands ++) |
| 596 | { |
| 597 | if (a_operands->type == CGEN_OPINST_OUTPUT) |
| 598 | { |
| 599 | int b_index; |
| 600 | const CGEN_OPINST *b_operands = b_ops; |
| 601 | |
| 602 | /* Special Case: |
| 603 | The Condition bit 'C' is a shadow of the CBR register (control |
| 604 | register 1) and also a shadow of bit 31 of the program status |
| 605 | word (control register 0). For now this is handled here, rather |
| 606 | than by cgen.... */ |
| 607 | |
| 608 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) |
| 609 | { |
| 610 | /* Scan operand list of 'b' looking for another reference to the |
| 611 | condition bit, which goes in the right direction. */ |
| 612 | for (b_index = 0; |
| 613 | b_operands->type != CGEN_OPINST_END; |
| 614 | b_index++, b_operands++) |
| 615 | { |
| 616 | if ((b_operands->type |
| 617 | == (check_outputs |
| 618 | ? CGEN_OPINST_OUTPUT |
| 619 | : CGEN_OPINST_INPUT)) |
| 620 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) |
| 621 | return 1; |
| 622 | } |
| 623 | } |
| 624 | else |
| 625 | { |
| 626 | /* Scan operand list of 'b' looking for an operand that |
| 627 | references the same hardware element, and which goes in the |
| 628 | right direction. */ |
| 629 | for (b_index = 0; |
| 630 | b_operands->type != CGEN_OPINST_END; |
| 631 | b_index++, b_operands++) |
| 632 | { |
| 633 | if ((b_operands->type |
| 634 | == (check_outputs |
| 635 | ? CGEN_OPINST_OUTPUT |
| 636 | : CGEN_OPINST_INPUT)) |
| 637 | && (b_operands->hw_type == a_operands->hw_type) |
| 638 | && (a->indices[a_index] == b->indices[b_index])) |
| 639 | return 1; |
| 640 | } |
| 641 | } |
| 642 | } |
| 643 | } |
| 644 | |
| 645 | return 0; |
| 646 | } |
| 647 | |
| 648 | /* Returns true if the insn can (potentially) alter the program counter. */ |
| 649 | |
| 650 | static int writes_to_pc PARAMS ((m32r_insn *)); |
| 651 | |
| 652 | static int |
| 653 | writes_to_pc (a) |
| 654 | m32r_insn *a; |
| 655 | { |
| 656 | #if 0 |
| 657 | /* Once PC operands are working.... */ |
| 658 | const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc, |
| 659 | a->insn); |
| 660 | |
| 661 | if (a_operands == NULL) |
| 662 | return 0; |
| 663 | |
| 664 | while (a_operands->type != CGEN_OPINST_END) |
| 665 | { |
| 666 | if (a_operands->operand != NULL |
| 667 | && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, |
| 668 | a_operands->operand) == M32R_OPERAND_PC) |
| 669 | return 1; |
| 670 | |
| 671 | a_operands++; |
| 672 | } |
| 673 | #else |
| 674 | if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) |
| 675 | || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) |
| 676 | return 1; |
| 677 | #endif |
| 678 | return 0; |
| 679 | } |
| 680 | |
| 681 | /* Return NULL if the two 16 bit insns can be executed in parallel. |
| 682 | Otherwise return a pointer to an error message explaining why not. */ |
| 683 | |
| 684 | static const char *can_make_parallel PARAMS ((m32r_insn *, m32r_insn *)); |
| 685 | |
| 686 | static const char * |
| 687 | can_make_parallel (a, b) |
| 688 | m32r_insn *a; |
| 689 | m32r_insn *b; |
| 690 | { |
| 691 | PIPE_ATTR a_pipe; |
| 692 | PIPE_ATTR b_pipe; |
| 693 | |
| 694 | /* Make sure the instructions are the right length. */ |
| 695 | if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 |
| 696 | || CGEN_FIELDS_BITSIZE (&b->fields) != 16) |
| 697 | abort (); |
| 698 | |
| 699 | if (first_writes_to_seconds_operands (a, b, TRUE)) |
| 700 | return _("Instructions write to the same destination register."); |
| 701 | |
| 702 | a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); |
| 703 | b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); |
| 704 | |
| 705 | /* Make sure that the instructions use the correct execution pipelines. */ |
| 706 | if (a_pipe == PIPE_NONE |
| 707 | || b_pipe == PIPE_NONE) |
| 708 | return _("Instructions do not use parallel execution pipelines."); |
| 709 | |
| 710 | /* Leave this test for last, since it is the only test that can |
| 711 | go away if the instructions are swapped, and we want to make |
| 712 | sure that any other errors are detected before this happens. */ |
| 713 | if (a_pipe == PIPE_S |
| 714 | || b_pipe == PIPE_O) |
| 715 | return _("Instructions share the same execution pipeline"); |
| 716 | |
| 717 | return NULL; |
| 718 | } |
| 719 | |
| 720 | /* Force the top bit of the second 16-bit insn to be set. */ |
| 721 | |
| 722 | static void make_parallel PARAMS ((CGEN_INSN_BYTES_PTR)); |
| 723 | |
| 724 | static void |
| 725 | make_parallel (buffer) |
| 726 | CGEN_INSN_BYTES_PTR buffer; |
| 727 | { |
| 728 | #if CGEN_INT_INSN_P |
| 729 | *buffer |= 0x8000; |
| 730 | #else |
| 731 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
| 732 | |= 0x80; |
| 733 | #endif |
| 734 | } |
| 735 | |
| 736 | /* Same as make_parallel except buffer contains the bytes in target order. */ |
| 737 | |
| 738 | static void target_make_parallel PARAMS ((char *)); |
| 739 | |
| 740 | static void |
| 741 | target_make_parallel (buffer) |
| 742 | char *buffer; |
| 743 | { |
| 744 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
| 745 | |= 0x80; |
| 746 | } |
| 747 | |
| 748 | /* Assemble two instructions with an explicit parallel operation (||) or |
| 749 | sequential operation (->). */ |
| 750 | |
| 751 | static void assemble_two_insns PARAMS ((char *, char *, int)); |
| 752 | |
| 753 | static void |
| 754 | assemble_two_insns (str, str2, parallel_p) |
| 755 | char *str; |
| 756 | char *str2; |
| 757 | int parallel_p; |
| 758 | { |
| 759 | char *str3; |
| 760 | m32r_insn first; |
| 761 | m32r_insn second; |
| 762 | char *errmsg; |
| 763 | char save_str2 = *str2; |
| 764 | |
| 765 | /* Seperate the two instructions. */ |
| 766 | *str2 = 0; |
| 767 | |
| 768 | /* Make sure the two insns begin on a 32 bit boundary. |
| 769 | This is also done for the serial case (foo -> bar), relaxing doesn't |
| 770 | affect insns written like this. |
| 771 | Note that we must always do this as we can't assume anything about |
| 772 | whether we're currently on a 32 bit boundary or not. Relaxing may |
| 773 | change this. */ |
| 774 | fill_insn (0); |
| 775 | |
| 776 | first.debug_sym_link = debug_sym_link; |
| 777 | debug_sym_link = (sym_linkS *) 0; |
| 778 | |
| 779 | /* Parse the first instruction. */ |
| 780 | if (! (first.insn = m32r_cgen_assemble_insn |
| 781 | (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg))) |
| 782 | { |
| 783 | as_bad (errmsg); |
| 784 | return; |
| 785 | } |
| 786 | |
| 787 | /* Check it. */ |
| 788 | if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) |
| 789 | { |
| 790 | /* xgettext:c-format */ |
| 791 | as_bad (_("not a 16 bit instruction '%s'"), str); |
| 792 | return; |
| 793 | } |
| 794 | else if (! enable_special |
| 795 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) |
| 796 | { |
| 797 | /* xgettext:c-format */ |
| 798 | as_bad (_("unknown instruction '%s'"), str); |
| 799 | return; |
| 800 | } |
| 801 | else if (! enable_m32rx |
| 802 | /* FIXME: Need standard macro to perform this test. */ |
| 803 | && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 804 | == (1 << MACH_M32RX))) |
| 805 | { |
| 806 | /* xgettext:c-format */ |
| 807 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
| 808 | return; |
| 809 | } |
| 810 | |
| 811 | /* Check to see if this is an allowable parallel insn. */ |
| 812 | if (parallel_p |
| 813 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) |
| 814 | { |
| 815 | /* xgettext:c-format */ |
| 816 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
| 817 | return; |
| 818 | } |
| 819 | |
| 820 | /* Restore the original assembly text, just in case it is needed. */ |
| 821 | *str2 = save_str2; |
| 822 | |
| 823 | /* Save the original string pointer. */ |
| 824 | str3 = str; |
| 825 | |
| 826 | /* Advanced past the parsed string. */ |
| 827 | str = str2 + 2; |
| 828 | |
| 829 | /* Remember the entire string in case it is needed for error |
| 830 | messages. */ |
| 831 | str2 = str3; |
| 832 | |
| 833 | /* Convert the opcode to lower case. */ |
| 834 | { |
| 835 | char *s2 = str; |
| 836 | |
| 837 | while (ISSPACE (*s2++)) |
| 838 | continue; |
| 839 | |
| 840 | --s2; |
| 841 | |
| 842 | while (ISALNUM (*s2)) |
| 843 | { |
| 844 | *s2 = TOLOWER (*s2); |
| 845 | s2++; |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | /* Preserve any fixups that have been generated and reset the list |
| 850 | to empty. */ |
| 851 | gas_cgen_save_fixups (0); |
| 852 | |
| 853 | /* Get the indices of the operands of the instruction. */ |
| 854 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact |
| 855 | doesn't seem right. Perhaps allow passing fields like we do insn. */ |
| 856 | /* FIXME: ALIAS insns do not have operands, so we use this function |
| 857 | to find the equivalent insn and overwrite the value stored in our |
| 858 | structure. We still need the original insn, however, since this |
| 859 | may have certain attributes that are not present in the unaliased |
| 860 | version (eg relaxability). When aliases behave differently this |
| 861 | may have to change. */ |
| 862 | first.orig_insn = first.insn; |
| 863 | { |
| 864 | CGEN_FIELDS tmp_fields; |
| 865 | first.insn = cgen_lookup_get_insn_operands |
| 866 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, |
| 867 | first.indices, &tmp_fields); |
| 868 | } |
| 869 | |
| 870 | if (first.insn == NULL) |
| 871 | as_fatal (_("internal error: lookup/get operands failed")); |
| 872 | |
| 873 | second.debug_sym_link = NULL; |
| 874 | |
| 875 | /* Parse the second instruction. */ |
| 876 | if (! (second.insn = m32r_cgen_assemble_insn |
| 877 | (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg))) |
| 878 | { |
| 879 | as_bad (errmsg); |
| 880 | return; |
| 881 | } |
| 882 | |
| 883 | /* Check it. */ |
| 884 | if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) |
| 885 | { |
| 886 | /* xgettext:c-format */ |
| 887 | as_bad (_("not a 16 bit instruction '%s'"), str); |
| 888 | return; |
| 889 | } |
| 890 | else if (! enable_special |
| 891 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) |
| 892 | { |
| 893 | /* xgettext:c-format */ |
| 894 | as_bad (_("unknown instruction '%s'"), str); |
| 895 | return; |
| 896 | } |
| 897 | else if (! enable_m32rx |
| 898 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
| 899 | { |
| 900 | /* xgettext:c-format */ |
| 901 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
| 902 | return; |
| 903 | } |
| 904 | |
| 905 | /* Check to see if this is an allowable parallel insn. */ |
| 906 | if (parallel_p |
| 907 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) |
| 908 | { |
| 909 | /* xgettext:c-format */ |
| 910 | as_bad (_("instruction '%s' cannot be executed in parallel."), str); |
| 911 | return; |
| 912 | } |
| 913 | |
| 914 | if (parallel_p && ! enable_m32rx) |
| 915 | { |
| 916 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP |
| 917 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) |
| 918 | { |
| 919 | /* xgettext:c-format */ |
| 920 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
| 921 | return; |
| 922 | } |
| 923 | } |
| 924 | |
| 925 | /* Get the indices of the operands of the instruction. */ |
| 926 | second.orig_insn = second.insn; |
| 927 | { |
| 928 | CGEN_FIELDS tmp_fields; |
| 929 | second.insn = cgen_lookup_get_insn_operands |
| 930 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, |
| 931 | second.indices, &tmp_fields); |
| 932 | } |
| 933 | |
| 934 | if (second.insn == NULL) |
| 935 | as_fatal (_("internal error: lookup/get operands failed")); |
| 936 | |
| 937 | /* We assume that if the first instruction writes to a register that is |
| 938 | read by the second instruction it is because the programmer intended |
| 939 | this to happen, (after all they have explicitly requested that these |
| 940 | two instructions be executed in parallel). Although if the global |
| 941 | variable warn_explicit_parallel_conflicts is true then we do generate |
| 942 | a warning message. Similarly we assume that parallel branch and jump |
| 943 | instructions are deliberate and should not produce errors. */ |
| 944 | |
| 945 | if (parallel_p && warn_explicit_parallel_conflicts) |
| 946 | { |
| 947 | if (first_writes_to_seconds_operands (&first, &second, FALSE)) |
| 948 | /* xgettext:c-format */ |
| 949 | as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
| 950 | |
| 951 | if (first_writes_to_seconds_operands (&second, &first, FALSE)) |
| 952 | /* xgettext:c-format */ |
| 953 | as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
| 954 | } |
| 955 | |
| 956 | if (!parallel_p |
| 957 | || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) |
| 958 | { |
| 959 | /* Get the fixups for the first instruction. */ |
| 960 | gas_cgen_swap_fixups (0); |
| 961 | |
| 962 | /* Write it out. */ |
| 963 | expand_debug_syms (first.debug_sym_link, 1); |
| 964 | gas_cgen_finish_insn (first.orig_insn, first.buffer, |
| 965 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
| 966 | |
| 967 | /* Force the top bit of the second insn to be set. */ |
| 968 | if (parallel_p) |
| 969 | make_parallel (second.buffer); |
| 970 | |
| 971 | /* Get its fixups. */ |
| 972 | gas_cgen_restore_fixups (0); |
| 973 | |
| 974 | /* Write it out. */ |
| 975 | expand_debug_syms (second.debug_sym_link, 1); |
| 976 | gas_cgen_finish_insn (second.orig_insn, second.buffer, |
| 977 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
| 978 | } |
| 979 | /* Try swapping the instructions to see if they work that way. */ |
| 980 | else if (can_make_parallel (&second, &first) == NULL) |
| 981 | { |
| 982 | /* Write out the second instruction first. */ |
| 983 | expand_debug_syms (second.debug_sym_link, 1); |
| 984 | gas_cgen_finish_insn (second.orig_insn, second.buffer, |
| 985 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
| 986 | |
| 987 | /* Force the top bit of the first instruction to be set. */ |
| 988 | make_parallel (first.buffer); |
| 989 | |
| 990 | /* Get the fixups for the first instruction. */ |
| 991 | gas_cgen_restore_fixups (0); |
| 992 | |
| 993 | /* Write out the first instruction. */ |
| 994 | expand_debug_syms (first.debug_sym_link, 1); |
| 995 | gas_cgen_finish_insn (first.orig_insn, first.buffer, |
| 996 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
| 997 | } |
| 998 | else |
| 999 | { |
| 1000 | as_bad ("'%s': %s", str2, errmsg); |
| 1001 | return; |
| 1002 | } |
| 1003 | |
| 1004 | /* Set these so m32r_fill_insn can use them. */ |
| 1005 | prev_seg = now_seg; |
| 1006 | prev_subseg = now_subseg; |
| 1007 | } |
| 1008 | |
| 1009 | void |
| 1010 | md_assemble (str) |
| 1011 | char *str; |
| 1012 | { |
| 1013 | m32r_insn insn; |
| 1014 | char *errmsg; |
| 1015 | char *str2 = NULL; |
| 1016 | |
| 1017 | /* Initialize GAS's cgen interface for a new instruction. */ |
| 1018 | gas_cgen_init_parse (); |
| 1019 | |
| 1020 | /* Look for a parallel instruction seperator. */ |
| 1021 | if ((str2 = strstr (str, "||")) != NULL) |
| 1022 | { |
| 1023 | assemble_two_insns (str, str2, 1); |
| 1024 | return; |
| 1025 | } |
| 1026 | |
| 1027 | /* Also look for a sequential instruction seperator. */ |
| 1028 | if ((str2 = strstr (str, "->")) != NULL) |
| 1029 | { |
| 1030 | assemble_two_insns (str, str2, 0); |
| 1031 | return; |
| 1032 | } |
| 1033 | |
| 1034 | insn.debug_sym_link = debug_sym_link; |
| 1035 | debug_sym_link = (sym_linkS *) 0; |
| 1036 | |
| 1037 | insn.insn = m32r_cgen_assemble_insn |
| 1038 | (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); |
| 1039 | |
| 1040 | if (!insn.insn) |
| 1041 | { |
| 1042 | as_bad (errmsg); |
| 1043 | return; |
| 1044 | } |
| 1045 | |
| 1046 | if (! enable_special |
| 1047 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
| 1048 | { |
| 1049 | /* xgettext:c-format */ |
| 1050 | as_bad (_("unknown instruction '%s'"), str); |
| 1051 | return; |
| 1052 | } |
| 1053 | else if (! enable_m32rx |
| 1054 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
| 1055 | { |
| 1056 | /* xgettext:c-format */ |
| 1057 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
| 1058 | return; |
| 1059 | } |
| 1060 | |
| 1061 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) |
| 1062 | { |
| 1063 | /* 32 bit insns must live on 32 bit boundaries. */ |
| 1064 | if (prev_insn.insn || seen_relaxable_p) |
| 1065 | { |
| 1066 | /* ??? If calling fill_insn too many times turns us into a memory |
| 1067 | pig, can we call a fn to assemble a nop instead of |
| 1068 | !seen_relaxable_p? */ |
| 1069 | fill_insn (0); |
| 1070 | } |
| 1071 | |
| 1072 | expand_debug_syms (insn.debug_sym_link, 2); |
| 1073 | |
| 1074 | /* Doesn't really matter what we pass for RELAX_P here. */ |
| 1075 | gas_cgen_finish_insn (insn.insn, insn.buffer, |
| 1076 | CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); |
| 1077 | } |
| 1078 | else |
| 1079 | { |
| 1080 | int on_32bit_boundary_p; |
| 1081 | int swap = FALSE; |
| 1082 | |
| 1083 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) |
| 1084 | abort (); |
| 1085 | |
| 1086 | insn.orig_insn = insn.insn; |
| 1087 | |
| 1088 | /* If the previous insn was relaxable, then it may be expanded |
| 1089 | to fill the current 16 bit slot. Emit a NOP here to occupy |
| 1090 | this slot, so that we can start at optimizing at a 32 bit |
| 1091 | boundary. */ |
| 1092 | if (prev_insn.insn && seen_relaxable_p && optimize) |
| 1093 | fill_insn (0); |
| 1094 | |
| 1095 | if (enable_m32rx) |
| 1096 | { |
| 1097 | /* Get the indices of the operands of the instruction. |
| 1098 | FIXME: See assemble_parallel for notes on orig_insn. */ |
| 1099 | { |
| 1100 | CGEN_FIELDS tmp_fields; |
| 1101 | insn.insn = cgen_lookup_get_insn_operands |
| 1102 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, |
| 1103 | 16, insn.indices, &tmp_fields); |
| 1104 | } |
| 1105 | |
| 1106 | if (insn.insn == NULL) |
| 1107 | as_fatal (_("internal error: lookup/get operands failed")); |
| 1108 | } |
| 1109 | |
| 1110 | /* Compute whether we're on a 32 bit boundary or not. |
| 1111 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
| 1112 | on_32bit_boundary_p = prev_insn.insn == NULL; |
| 1113 | |
| 1114 | /* Look to see if this instruction can be combined with the |
| 1115 | previous instruction to make one, parallel, 32 bit instruction. |
| 1116 | If the previous instruction (potentially) changed the flow of |
| 1117 | program control, then it cannot be combined with the current |
| 1118 | instruction. If the current instruction is relaxable, then it |
| 1119 | might be replaced with a longer version, so we cannot combine it. |
| 1120 | Also if the output of the previous instruction is used as an |
| 1121 | input to the current instruction then it cannot be combined. |
| 1122 | Otherwise call can_make_parallel() with both orderings of the |
| 1123 | instructions to see if they can be combined. */ |
| 1124 | if (! on_32bit_boundary_p |
| 1125 | && enable_m32rx |
| 1126 | && optimize |
| 1127 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 |
| 1128 | && ! writes_to_pc (&prev_insn) |
| 1129 | && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE)) |
| 1130 | { |
| 1131 | if (can_make_parallel (&prev_insn, &insn) == NULL) |
| 1132 | make_parallel (insn.buffer); |
| 1133 | else if (can_make_parallel (&insn, &prev_insn) == NULL) |
| 1134 | swap = TRUE; |
| 1135 | } |
| 1136 | |
| 1137 | expand_debug_syms (insn.debug_sym_link, 1); |
| 1138 | |
| 1139 | { |
| 1140 | int i; |
| 1141 | finished_insnS fi; |
| 1142 | |
| 1143 | /* Ensure each pair of 16 bit insns is in the same frag. */ |
| 1144 | frag_grow (4); |
| 1145 | |
| 1146 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, |
| 1147 | CGEN_FIELDS_BITSIZE (&insn.fields), |
| 1148 | 1 /* relax_p */, &fi); |
| 1149 | insn.addr = fi.addr; |
| 1150 | insn.frag = fi.frag; |
| 1151 | insn.num_fixups = fi.num_fixups; |
| 1152 | for (i = 0; i < fi.num_fixups; ++i) |
| 1153 | insn.fixups[i] = fi.fixups[i]; |
| 1154 | } |
| 1155 | |
| 1156 | if (swap) |
| 1157 | { |
| 1158 | int i, tmp; |
| 1159 | |
| 1160 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp |
| 1161 | |
| 1162 | /* Swap the two insns */ |
| 1163 | SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); |
| 1164 | SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); |
| 1165 | |
| 1166 | target_make_parallel (insn.addr); |
| 1167 | |
| 1168 | /* Swap any relaxable frags recorded for the two insns. */ |
| 1169 | /* FIXME: Clarify. relaxation precludes parallel insns */ |
| 1170 | if (prev_insn.frag->fr_opcode == prev_insn.addr) |
| 1171 | prev_insn.frag->fr_opcode = insn.addr; |
| 1172 | else if (insn.frag->fr_opcode == insn.addr) |
| 1173 | insn.frag->fr_opcode = prev_insn.addr; |
| 1174 | |
| 1175 | /* Update the addresses in any fixups. |
| 1176 | Note that we don't have to handle the case where each insn is in |
| 1177 | a different frag as we ensure they're in the same frag above. */ |
| 1178 | for (i = 0; i < prev_insn.num_fixups; ++i) |
| 1179 | prev_insn.fixups[i]->fx_where += 2; |
| 1180 | for (i = 0; i < insn.num_fixups; ++i) |
| 1181 | insn.fixups[i]->fx_where -= 2; |
| 1182 | } |
| 1183 | |
| 1184 | /* Keep track of whether we've seen a pair of 16 bit insns. |
| 1185 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
| 1186 | if (on_32bit_boundary_p) |
| 1187 | prev_insn = insn; |
| 1188 | else |
| 1189 | prev_insn.insn = NULL; |
| 1190 | |
| 1191 | /* If the insn needs the following one to be on a 32 bit boundary |
| 1192 | (e.g. subroutine calls), fill this insn's slot. */ |
| 1193 | if (on_32bit_boundary_p |
| 1194 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) |
| 1195 | fill_insn (0); |
| 1196 | |
| 1197 | /* If this is a relaxable insn (can be replaced with a larger version) |
| 1198 | mark the fact so that we can emit an alignment directive for a |
| 1199 | following 32 bit insn if we see one. */ |
| 1200 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) |
| 1201 | seen_relaxable_p = 1; |
| 1202 | } |
| 1203 | |
| 1204 | /* Set these so m32r_fill_insn can use them. */ |
| 1205 | prev_seg = now_seg; |
| 1206 | prev_subseg = now_subseg; |
| 1207 | } |
| 1208 | |
| 1209 | /* The syntax in the manual says constants begin with '#'. |
| 1210 | We just ignore it. */ |
| 1211 | |
| 1212 | void |
| 1213 | md_operand (expressionP) |
| 1214 | expressionS *expressionP; |
| 1215 | { |
| 1216 | if (*input_line_pointer == '#') |
| 1217 | { |
| 1218 | input_line_pointer++; |
| 1219 | expression (expressionP); |
| 1220 | } |
| 1221 | } |
| 1222 | |
| 1223 | valueT |
| 1224 | md_section_align (segment, size) |
| 1225 | segT segment; |
| 1226 | valueT size; |
| 1227 | { |
| 1228 | int align = bfd_get_section_alignment (stdoutput, segment); |
| 1229 | return ((size + (1 << align) - 1) & (-1 << align)); |
| 1230 | } |
| 1231 | |
| 1232 | symbolS * |
| 1233 | md_undefined_symbol (name) |
| 1234 | char *name ATTRIBUTE_UNUSED; |
| 1235 | { |
| 1236 | return 0; |
| 1237 | } |
| 1238 | \f |
| 1239 | /* .scomm pseudo-op handler. |
| 1240 | |
| 1241 | This is a new pseudo-op to handle putting objects in .scommon. |
| 1242 | By doing this the linker won't need to do any work, |
| 1243 | and more importantly it removes the implicit -G arg necessary to |
| 1244 | correctly link the object file. */ |
| 1245 | |
| 1246 | static void |
| 1247 | m32r_scomm (ignore) |
| 1248 | int ignore ATTRIBUTE_UNUSED; |
| 1249 | { |
| 1250 | register char *name; |
| 1251 | register char c; |
| 1252 | register char *p; |
| 1253 | offsetT size; |
| 1254 | register symbolS *symbolP; |
| 1255 | offsetT align; |
| 1256 | int align2; |
| 1257 | |
| 1258 | name = input_line_pointer; |
| 1259 | c = get_symbol_end (); |
| 1260 | |
| 1261 | /* Just after name is now '\0'. */ |
| 1262 | p = input_line_pointer; |
| 1263 | *p = c; |
| 1264 | SKIP_WHITESPACE (); |
| 1265 | if (*input_line_pointer != ',') |
| 1266 | { |
| 1267 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); |
| 1268 | ignore_rest_of_line (); |
| 1269 | return; |
| 1270 | } |
| 1271 | |
| 1272 | /* Skip ','. */ |
| 1273 | input_line_pointer++; |
| 1274 | if ((size = get_absolute_expression ()) < 0) |
| 1275 | { |
| 1276 | /* xgettext:c-format */ |
| 1277 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
| 1278 | ignore_rest_of_line (); |
| 1279 | return; |
| 1280 | } |
| 1281 | |
| 1282 | /* The third argument to .scomm is the alignment. */ |
| 1283 | if (*input_line_pointer != ',') |
| 1284 | align = 8; |
| 1285 | else |
| 1286 | { |
| 1287 | ++input_line_pointer; |
| 1288 | align = get_absolute_expression (); |
| 1289 | if (align <= 0) |
| 1290 | { |
| 1291 | as_warn (_("ignoring bad alignment")); |
| 1292 | align = 8; |
| 1293 | } |
| 1294 | } |
| 1295 | |
| 1296 | /* Convert to a power of 2 alignment. */ |
| 1297 | if (align) |
| 1298 | { |
| 1299 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) |
| 1300 | continue; |
| 1301 | if (align != 1) |
| 1302 | { |
| 1303 | as_bad (_("Common alignment not a power of 2")); |
| 1304 | ignore_rest_of_line (); |
| 1305 | return; |
| 1306 | } |
| 1307 | } |
| 1308 | else |
| 1309 | align2 = 0; |
| 1310 | |
| 1311 | *p = 0; |
| 1312 | symbolP = symbol_find_or_make (name); |
| 1313 | *p = c; |
| 1314 | |
| 1315 | if (S_IS_DEFINED (symbolP)) |
| 1316 | { |
| 1317 | /* xgettext:c-format */ |
| 1318 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
| 1319 | S_GET_NAME (symbolP)); |
| 1320 | ignore_rest_of_line (); |
| 1321 | return; |
| 1322 | } |
| 1323 | |
| 1324 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) |
| 1325 | { |
| 1326 | /* xgettext:c-format */ |
| 1327 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
| 1328 | S_GET_NAME (symbolP), |
| 1329 | (long) S_GET_VALUE (symbolP), |
| 1330 | (long) size); |
| 1331 | |
| 1332 | ignore_rest_of_line (); |
| 1333 | return; |
| 1334 | } |
| 1335 | |
| 1336 | if (symbol_get_obj (symbolP)->local) |
| 1337 | { |
| 1338 | segT old_sec = now_seg; |
| 1339 | int old_subsec = now_subseg; |
| 1340 | char *pfrag; |
| 1341 | |
| 1342 | record_alignment (sbss_section, align2); |
| 1343 | subseg_set (sbss_section, 0); |
| 1344 | |
| 1345 | if (align2) |
| 1346 | frag_align (align2, 0, 0); |
| 1347 | |
| 1348 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
| 1349 | symbol_get_frag (symbolP)->fr_symbol = 0; |
| 1350 | |
| 1351 | symbol_set_frag (symbolP, frag_now); |
| 1352 | |
| 1353 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
| 1354 | (char *) 0); |
| 1355 | *pfrag = 0; |
| 1356 | S_SET_SIZE (symbolP, size); |
| 1357 | S_SET_SEGMENT (symbolP, sbss_section); |
| 1358 | S_CLEAR_EXTERNAL (symbolP); |
| 1359 | subseg_set (old_sec, old_subsec); |
| 1360 | } |
| 1361 | else |
| 1362 | { |
| 1363 | S_SET_VALUE (symbolP, (valueT) size); |
| 1364 | S_SET_ALIGN (symbolP, align2); |
| 1365 | S_SET_EXTERNAL (symbolP); |
| 1366 | S_SET_SEGMENT (symbolP, &scom_section); |
| 1367 | } |
| 1368 | |
| 1369 | demand_empty_rest_of_line (); |
| 1370 | } |
| 1371 | \f |
| 1372 | /* Interface to relax_segment. */ |
| 1373 | |
| 1374 | /* FIXME: Build table by hand, get it working, then machine generate. */ |
| 1375 | |
| 1376 | const relax_typeS md_relax_table[] = |
| 1377 | { |
| 1378 | /* The fields are: |
| 1379 | 1) most positive reach of this state, |
| 1380 | 2) most negative reach of this state, |
| 1381 | 3) how many bytes this mode will add to the size of the current frag |
| 1382 | 4) which index into the table to try if we can't fit into this one. */ |
| 1383 | |
| 1384 | /* The first entry must be unused because an `rlx_more' value of zero ends |
| 1385 | each list. */ |
| 1386 | {1, 1, 0, 0}, |
| 1387 | |
| 1388 | /* The displacement used by GAS is from the end of the 2 byte insn, |
| 1389 | so we subtract 2 from the following. */ |
| 1390 | /* 16 bit insn, 8 bit disp -> 10 bit range. |
| 1391 | This doesn't handle a branch in the right slot at the border: |
| 1392 | the "& -4" isn't taken into account. It's not important enough to |
| 1393 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve |
| 1394 | case). */ |
| 1395 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, |
| 1396 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ |
| 1397 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, |
| 1398 | /* Same thing, but with leading nop for alignment. */ |
| 1399 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } |
| 1400 | }; |
| 1401 | |
| 1402 | long |
| 1403 | m32r_relax_frag (segment, fragP, stretch) |
| 1404 | segT segment; |
| 1405 | fragS *fragP; |
| 1406 | long stretch; |
| 1407 | { |
| 1408 | /* Address of branch insn. */ |
| 1409 | long address = fragP->fr_address + fragP->fr_fix - 2; |
| 1410 | long growth = 0; |
| 1411 | |
| 1412 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ |
| 1413 | if (fragP->fr_subtype == 2) |
| 1414 | { |
| 1415 | if ((address & 3) != 0) |
| 1416 | { |
| 1417 | fragP->fr_subtype = 3; |
| 1418 | growth = 2; |
| 1419 | } |
| 1420 | } |
| 1421 | else if (fragP->fr_subtype == 3) |
| 1422 | { |
| 1423 | if ((address & 3) == 0) |
| 1424 | { |
| 1425 | fragP->fr_subtype = 2; |
| 1426 | growth = -2; |
| 1427 | } |
| 1428 | } |
| 1429 | else |
| 1430 | { |
| 1431 | growth = relax_frag (segment, fragP, stretch); |
| 1432 | |
| 1433 | /* Long jump on odd halfword boundary? */ |
| 1434 | if (fragP->fr_subtype == 2 && (address & 3) != 0) |
| 1435 | { |
| 1436 | fragP->fr_subtype = 3; |
| 1437 | growth += 2; |
| 1438 | } |
| 1439 | } |
| 1440 | |
| 1441 | return growth; |
| 1442 | } |
| 1443 | |
| 1444 | /* Return an initial guess of the length by which a fragment must grow to |
| 1445 | hold a branch to reach its destination. |
| 1446 | Also updates fr_type/fr_subtype as necessary. |
| 1447 | |
| 1448 | Called just before doing relaxation. |
| 1449 | Any symbol that is now undefined will not become defined. |
| 1450 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. |
| 1451 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. |
| 1452 | Although it may not be explicit in the frag, pretend fr_var starts |
| 1453 | with a 0 value. */ |
| 1454 | |
| 1455 | int |
| 1456 | md_estimate_size_before_relax (fragP, segment) |
| 1457 | fragS *fragP; |
| 1458 | segT segment; |
| 1459 | { |
| 1460 | /* The only thing we have to handle here are symbols outside of the |
| 1461 | current segment. They may be undefined or in a different segment in |
| 1462 | which case linker scripts may place them anywhere. |
| 1463 | However, we can't finish the fragment here and emit the reloc as insn |
| 1464 | alignment requirements may move the insn about. */ |
| 1465 | |
| 1466 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) |
| 1467 | { |
| 1468 | #if 0 |
| 1469 | int old_fr_fix = fragP->fr_fix; |
| 1470 | #endif |
| 1471 | |
| 1472 | /* The symbol is undefined in this segment. |
| 1473 | Change the relaxation subtype to the max allowable and leave |
| 1474 | all further handling to md_convert_frag. */ |
| 1475 | fragP->fr_subtype = 2; |
| 1476 | |
| 1477 | #if 0 |
| 1478 | /* Can't use this, but leave in for illustration. */ |
| 1479 | /* Change 16 bit insn to 32 bit insn. */ |
| 1480 | fragP->fr_opcode[0] |= 0x80; |
| 1481 | |
| 1482 | /* Increase known (fixed) size of fragment. */ |
| 1483 | fragP->fr_fix += 2; |
| 1484 | |
| 1485 | /* Create a relocation for it. */ |
| 1486 | fix_new (fragP, old_fr_fix, 4, |
| 1487 | fragP->fr_symbol, |
| 1488 | fragP->fr_offset, 1 /* pcrel */, |
| 1489 | /* FIXME: Can't use a real BFD reloc here. |
| 1490 | gas_cgen_md_apply_fix3 can't handle it. */ |
| 1491 | BFD_RELOC_M32R_26_PCREL); |
| 1492 | |
| 1493 | /* Mark this fragment as finished. */ |
| 1494 | frag_wane (fragP); |
| 1495 | return fragP->fr_fix - old_fr_fix; |
| 1496 | #else |
| 1497 | { |
| 1498 | const CGEN_INSN *insn; |
| 1499 | int i; |
| 1500 | |
| 1501 | /* Update the recorded insn. |
| 1502 | Fortunately we don't have to look very far. |
| 1503 | FIXME: Change this to record in the instruction the next higher |
| 1504 | relaxable insn to use. */ |
| 1505 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) |
| 1506 | { |
| 1507 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
| 1508 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) |
| 1509 | == 0) |
| 1510 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) |
| 1511 | break; |
| 1512 | } |
| 1513 | if (i == 4) |
| 1514 | abort (); |
| 1515 | |
| 1516 | fragP->fr_cgen.insn = insn; |
| 1517 | return 2; |
| 1518 | } |
| 1519 | #endif |
| 1520 | } |
| 1521 | |
| 1522 | return md_relax_table[fragP->fr_subtype].rlx_length; |
| 1523 | } |
| 1524 | |
| 1525 | /* *FRAGP has been relaxed to its final size, and now needs to have |
| 1526 | the bytes inside it modified to conform to the new size. |
| 1527 | |
| 1528 | Called after relaxation is finished. |
| 1529 | fragP->fr_type == rs_machine_dependent. |
| 1530 | fragP->fr_subtype is the subtype of what the address relaxed to. */ |
| 1531 | |
| 1532 | void |
| 1533 | md_convert_frag (abfd, sec, fragP) |
| 1534 | bfd *abfd ATTRIBUTE_UNUSED; |
| 1535 | segT sec; |
| 1536 | fragS *fragP; |
| 1537 | { |
| 1538 | char *opcode; |
| 1539 | char *displacement; |
| 1540 | int target_address; |
| 1541 | int opcode_address; |
| 1542 | int extension; |
| 1543 | int addend; |
| 1544 | |
| 1545 | opcode = fragP->fr_opcode; |
| 1546 | |
| 1547 | /* Address opcode resides at in file space. */ |
| 1548 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; |
| 1549 | |
| 1550 | switch (fragP->fr_subtype) |
| 1551 | { |
| 1552 | case 1: |
| 1553 | extension = 0; |
| 1554 | displacement = &opcode[1]; |
| 1555 | break; |
| 1556 | case 2: |
| 1557 | opcode[0] |= 0x80; |
| 1558 | extension = 2; |
| 1559 | displacement = &opcode[1]; |
| 1560 | break; |
| 1561 | case 3: |
| 1562 | opcode[2] = opcode[0] | 0x80; |
| 1563 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); |
| 1564 | opcode_address += 2; |
| 1565 | extension = 4; |
| 1566 | displacement = &opcode[3]; |
| 1567 | break; |
| 1568 | default: |
| 1569 | abort (); |
| 1570 | } |
| 1571 | |
| 1572 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) |
| 1573 | { |
| 1574 | /* Symbol must be resolved by linker. */ |
| 1575 | if (fragP->fr_offset & 3) |
| 1576 | as_warn (_("Addend to unresolved symbol not on word boundary.")); |
| 1577 | addend = fragP->fr_offset >> 2; |
| 1578 | } |
| 1579 | else |
| 1580 | { |
| 1581 | /* Address we want to reach in file space. */ |
| 1582 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
| 1583 | addend = (target_address - (opcode_address & -4)) >> 2; |
| 1584 | } |
| 1585 | |
| 1586 | /* Create a relocation for symbols that must be resolved by the linker. |
| 1587 | Otherwise output the completed insn. */ |
| 1588 | |
| 1589 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec) |
| 1590 | { |
| 1591 | assert (fragP->fr_subtype != 1); |
| 1592 | assert (fragP->fr_cgen.insn != 0); |
| 1593 | gas_cgen_record_fixup (fragP, |
| 1594 | /* Offset of branch insn in frag. */ |
| 1595 | fragP->fr_fix + extension - 4, |
| 1596 | fragP->fr_cgen.insn, |
| 1597 | 4 /* Length. */, |
| 1598 | /* FIXME: quick hack. */ |
| 1599 | #if 0 |
| 1600 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, |
| 1601 | fragP->fr_cgen.opindex), |
| 1602 | #else |
| 1603 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, |
| 1604 | M32R_OPERAND_DISP24), |
| 1605 | #endif |
| 1606 | fragP->fr_cgen.opinfo, |
| 1607 | fragP->fr_symbol, fragP->fr_offset); |
| 1608 | } |
| 1609 | |
| 1610 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) |
| 1611 | |
| 1612 | md_number_to_chars (displacement, (valueT) addend, |
| 1613 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
| 1614 | |
| 1615 | fragP->fr_fix += extension; |
| 1616 | } |
| 1617 | \f |
| 1618 | /* Functions concerning relocs. */ |
| 1619 | |
| 1620 | /* The location from which a PC relative jump should be calculated, |
| 1621 | given a PC relative reloc. */ |
| 1622 | |
| 1623 | long |
| 1624 | md_pcrel_from_section (fixP, sec) |
| 1625 | fixS *fixP; |
| 1626 | segT sec; |
| 1627 | { |
| 1628 | if (fixP->fx_addsy != (symbolS *) NULL |
| 1629 | && (! S_IS_DEFINED (fixP->fx_addsy) |
| 1630 | || S_GET_SEGMENT (fixP->fx_addsy) != sec)) |
| 1631 | { |
| 1632 | /* The symbol is undefined (or is defined but not in this section). |
| 1633 | Let the linker figure it out. */ |
| 1634 | return 0; |
| 1635 | } |
| 1636 | |
| 1637 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; |
| 1638 | } |
| 1639 | |
| 1640 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. |
| 1641 | Returns BFD_RELOC_NONE if no reloc type can be found. |
| 1642 | *FIXP may be modified if desired. */ |
| 1643 | |
| 1644 | bfd_reloc_code_real_type |
| 1645 | md_cgen_lookup_reloc (insn, operand, fixP) |
| 1646 | const CGEN_INSN *insn ATTRIBUTE_UNUSED; |
| 1647 | const CGEN_OPERAND *operand; |
| 1648 | fixS *fixP; |
| 1649 | { |
| 1650 | switch (operand->type) |
| 1651 | { |
| 1652 | case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; |
| 1653 | case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; |
| 1654 | case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; |
| 1655 | case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; |
| 1656 | case M32R_OPERAND_HI16: |
| 1657 | case M32R_OPERAND_SLO16: |
| 1658 | case M32R_OPERAND_ULO16: |
| 1659 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
| 1660 | if (fixP->fx_cgen.opinfo != 0) |
| 1661 | return fixP->fx_cgen.opinfo; |
| 1662 | break; |
| 1663 | default: |
| 1664 | /* Avoid -Wall warning. */ |
| 1665 | break; |
| 1666 | } |
| 1667 | return BFD_RELOC_NONE; |
| 1668 | } |
| 1669 | |
| 1670 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
| 1671 | |
| 1672 | static void m32r_record_hi16 PARAMS ((int, fixS *, segT)); |
| 1673 | |
| 1674 | static void |
| 1675 | m32r_record_hi16 (reloc_type, fixP, seg) |
| 1676 | int reloc_type; |
| 1677 | fixS *fixP; |
| 1678 | segT seg ATTRIBUTE_UNUSED; |
| 1679 | { |
| 1680 | struct m32r_hi_fixup *hi_fixup; |
| 1681 | |
| 1682 | assert (reloc_type == BFD_RELOC_M32R_HI16_SLO |
| 1683 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); |
| 1684 | |
| 1685 | hi_fixup = ((struct m32r_hi_fixup *) |
| 1686 | xmalloc (sizeof (struct m32r_hi_fixup))); |
| 1687 | hi_fixup->fixp = fixP; |
| 1688 | hi_fixup->seg = now_seg; |
| 1689 | hi_fixup->next = m32r_hi_fixup_list; |
| 1690 | |
| 1691 | m32r_hi_fixup_list = hi_fixup; |
| 1692 | } |
| 1693 | |
| 1694 | /* Called while parsing an instruction to create a fixup. |
| 1695 | We need to check for HI16 relocs and queue them up for later sorting. */ |
| 1696 | |
| 1697 | fixS * |
| 1698 | m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) |
| 1699 | fragS *frag; |
| 1700 | int where; |
| 1701 | const CGEN_INSN *insn; |
| 1702 | int length; |
| 1703 | const CGEN_OPERAND *operand; |
| 1704 | int opinfo; |
| 1705 | expressionS *exp; |
| 1706 | { |
| 1707 | fixS *fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, |
| 1708 | operand, opinfo, exp); |
| 1709 | |
| 1710 | switch (operand->type) |
| 1711 | { |
| 1712 | case M32R_OPERAND_HI16: |
| 1713 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
| 1714 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO |
| 1715 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) |
| 1716 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); |
| 1717 | break; |
| 1718 | default: |
| 1719 | /* Avoid -Wall warning */ |
| 1720 | break; |
| 1721 | } |
| 1722 | |
| 1723 | return fixP; |
| 1724 | } |
| 1725 | |
| 1726 | /* Return BFD reloc type from opinfo field in a fixS. |
| 1727 | It's tricky using fx_r_type in m32r_frob_file because the values |
| 1728 | are BFD_RELOC_UNUSED + operand number. */ |
| 1729 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) |
| 1730 | |
| 1731 | /* Sort any unmatched HI16 relocs so that they immediately precede |
| 1732 | the corresponding LO16 reloc. This is called before md_apply_fix3 and |
| 1733 | tc_gen_reloc. */ |
| 1734 | |
| 1735 | void |
| 1736 | m32r_frob_file () |
| 1737 | { |
| 1738 | struct m32r_hi_fixup *l; |
| 1739 | |
| 1740 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) |
| 1741 | { |
| 1742 | segment_info_type *seginfo; |
| 1743 | int pass; |
| 1744 | |
| 1745 | assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO |
| 1746 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); |
| 1747 | |
| 1748 | /* Check quickly whether the next fixup happens to be a matching low. */ |
| 1749 | if (l->fixp->fx_next != NULL |
| 1750 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 |
| 1751 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy |
| 1752 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) |
| 1753 | continue; |
| 1754 | |
| 1755 | /* Look through the fixups for this segment for a matching `low'. |
| 1756 | When we find one, move the high/shigh just in front of it. We do |
| 1757 | this in two passes. In the first pass, we try to find a |
| 1758 | unique `low'. In the second pass, we permit multiple high's |
| 1759 | relocs for a single `low'. */ |
| 1760 | seginfo = seg_info (l->seg); |
| 1761 | for (pass = 0; pass < 2; pass++) |
| 1762 | { |
| 1763 | fixS *f; |
| 1764 | fixS *prev; |
| 1765 | |
| 1766 | prev = NULL; |
| 1767 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) |
| 1768 | { |
| 1769 | /* Check whether this is a `low' fixup which matches l->fixp. */ |
| 1770 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 |
| 1771 | && f->fx_addsy == l->fixp->fx_addsy |
| 1772 | && f->fx_offset == l->fixp->fx_offset |
| 1773 | && (pass == 1 |
| 1774 | || prev == NULL |
| 1775 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO |
| 1776 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) |
| 1777 | || prev->fx_addsy != f->fx_addsy |
| 1778 | || prev->fx_offset != f->fx_offset)) |
| 1779 | { |
| 1780 | fixS **pf; |
| 1781 | |
| 1782 | /* Move l->fixp before f. */ |
| 1783 | for (pf = &seginfo->fix_root; |
| 1784 | *pf != l->fixp; |
| 1785 | pf = & (*pf)->fx_next) |
| 1786 | assert (*pf != NULL); |
| 1787 | |
| 1788 | *pf = l->fixp->fx_next; |
| 1789 | |
| 1790 | l->fixp->fx_next = f; |
| 1791 | if (prev == NULL) |
| 1792 | seginfo->fix_root = l->fixp; |
| 1793 | else |
| 1794 | prev->fx_next = l->fixp; |
| 1795 | |
| 1796 | break; |
| 1797 | } |
| 1798 | |
| 1799 | prev = f; |
| 1800 | } |
| 1801 | |
| 1802 | if (f != NULL) |
| 1803 | break; |
| 1804 | |
| 1805 | if (pass == 1 |
| 1806 | && warn_unmatched_high) |
| 1807 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, |
| 1808 | _("Unmatched high/shigh reloc")); |
| 1809 | } |
| 1810 | } |
| 1811 | } |
| 1812 | |
| 1813 | /* See whether we need to force a relocation into the output file. |
| 1814 | This is used to force out switch and PC relative relocations when |
| 1815 | relaxing. */ |
| 1816 | |
| 1817 | int |
| 1818 | m32r_force_relocation (fix) |
| 1819 | fixS *fix; |
| 1820 | { |
| 1821 | if (generic_force_reloc (fix)) |
| 1822 | return 1; |
| 1823 | |
| 1824 | if (! m32r_relax) |
| 1825 | return 0; |
| 1826 | |
| 1827 | return fix->fx_pcrel; |
| 1828 | } |
| 1829 | \f |
| 1830 | /* Write a value out to the object file, using the appropriate endianness. */ |
| 1831 | |
| 1832 | void |
| 1833 | md_number_to_chars (buf, val, n) |
| 1834 | char *buf; |
| 1835 | valueT val; |
| 1836 | int n; |
| 1837 | { |
| 1838 | if (target_big_endian) |
| 1839 | number_to_chars_bigendian (buf, val, n); |
| 1840 | else |
| 1841 | number_to_chars_littleendian (buf, val, n); |
| 1842 | } |
| 1843 | |
| 1844 | /* Turn a string in input_line_pointer into a floating point constant |
| 1845 | of type TYPE, and store the appropriate bytes in *LITP. The number |
| 1846 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
| 1847 | returned, or NULL on OK. */ |
| 1848 | |
| 1849 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
| 1850 | #define MAX_LITTLENUMS 6 |
| 1851 | |
| 1852 | char * |
| 1853 | md_atof (type, litP, sizeP) |
| 1854 | char type; |
| 1855 | char *litP; |
| 1856 | int *sizeP; |
| 1857 | { |
| 1858 | int i; |
| 1859 | int prec; |
| 1860 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 1861 | char *t; |
| 1862 | |
| 1863 | switch (type) |
| 1864 | { |
| 1865 | case 'f': |
| 1866 | case 'F': |
| 1867 | case 's': |
| 1868 | case 'S': |
| 1869 | prec = 2; |
| 1870 | break; |
| 1871 | |
| 1872 | case 'd': |
| 1873 | case 'D': |
| 1874 | case 'r': |
| 1875 | case 'R': |
| 1876 | prec = 4; |
| 1877 | break; |
| 1878 | |
| 1879 | /* FIXME: Some targets allow other format chars for bigger sizes |
| 1880 | here. */ |
| 1881 | |
| 1882 | default: |
| 1883 | *sizeP = 0; |
| 1884 | return _("Bad call to md_atof()"); |
| 1885 | } |
| 1886 | |
| 1887 | t = atof_ieee (input_line_pointer, type, words); |
| 1888 | if (t) |
| 1889 | input_line_pointer = t; |
| 1890 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
| 1891 | |
| 1892 | if (target_big_endian) |
| 1893 | { |
| 1894 | for (i = 0; i < prec; i++) |
| 1895 | { |
| 1896 | md_number_to_chars (litP, (valueT) words[i], |
| 1897 | sizeof (LITTLENUM_TYPE)); |
| 1898 | litP += sizeof (LITTLENUM_TYPE); |
| 1899 | } |
| 1900 | } |
| 1901 | else |
| 1902 | { |
| 1903 | for (i = prec - 1; i >= 0; i--) |
| 1904 | { |
| 1905 | md_number_to_chars (litP, (valueT) words[i], |
| 1906 | sizeof (LITTLENUM_TYPE)); |
| 1907 | litP += sizeof (LITTLENUM_TYPE); |
| 1908 | } |
| 1909 | } |
| 1910 | |
| 1911 | return 0; |
| 1912 | } |
| 1913 | |
| 1914 | void |
| 1915 | m32r_elf_section_change_hook () |
| 1916 | { |
| 1917 | /* If we have reached the end of a section and we have just emitted a |
| 1918 | 16 bit insn, then emit a nop to make sure that the section ends on |
| 1919 | a 32 bit boundary. */ |
| 1920 | |
| 1921 | if (prev_insn.insn || seen_relaxable_p) |
| 1922 | (void) m32r_fill_insn (0); |
| 1923 | } |
| 1924 | |
| 1925 | /* Return true if can adjust the reloc to be relative to its section |
| 1926 | (such as .data) instead of relative to some symbol. */ |
| 1927 | |
| 1928 | bfd_boolean |
| 1929 | m32r_fix_adjustable (fixP) |
| 1930 | fixS *fixP; |
| 1931 | { |
| 1932 | bfd_reloc_code_real_type reloc_type; |
| 1933 | |
| 1934 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
| 1935 | { |
| 1936 | const CGEN_INSN *insn = NULL; |
| 1937 | int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; |
| 1938 | const CGEN_OPERAND *operand = |
| 1939 | cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); |
| 1940 | reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); |
| 1941 | } |
| 1942 | else |
| 1943 | reloc_type = fixP->fx_r_type; |
| 1944 | |
| 1945 | /* We need the symbol name for the VTABLE entries. */ |
| 1946 | if (reloc_type == BFD_RELOC_VTABLE_INHERIT |
| 1947 | || reloc_type == BFD_RELOC_VTABLE_ENTRY) |
| 1948 | return 0; |
| 1949 | |
| 1950 | return 1; |
| 1951 | } |