| 1 | /* tc-m32r.c -- Assembler for the Renesas M32R. |
| 2 | Copyright (C) 1996-2015 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GAS, the GNU Assembler. |
| 5 | |
| 6 | GAS is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 3, or (at your option) |
| 9 | any later version. |
| 10 | |
| 11 | GAS is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with GAS; see the file COPYING. If not, write to |
| 18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
| 19 | Boston, MA 02110-1301, USA. */ |
| 20 | |
| 21 | #include "as.h" |
| 22 | #include "safe-ctype.h" |
| 23 | #include "subsegs.h" |
| 24 | #include "symcat.h" |
| 25 | #include "opcodes/m32r-desc.h" |
| 26 | #include "opcodes/m32r-opc.h" |
| 27 | #include "cgen.h" |
| 28 | #include "elf/m32r.h" |
| 29 | |
| 30 | /* Linked list of symbols that are debugging symbols to be defined as the |
| 31 | beginning of the current instruction. */ |
| 32 | typedef struct sym_link |
| 33 | { |
| 34 | struct sym_link *next; |
| 35 | symbolS *symbol; |
| 36 | } sym_linkS; |
| 37 | |
| 38 | static sym_linkS *debug_sym_link = (sym_linkS *) 0; |
| 39 | |
| 40 | /* Structure to hold all of the different components describing |
| 41 | an individual instruction. */ |
| 42 | typedef struct |
| 43 | { |
| 44 | const CGEN_INSN *insn; |
| 45 | const CGEN_INSN *orig_insn; |
| 46 | CGEN_FIELDS fields; |
| 47 | #if CGEN_INT_INSN_P |
| 48 | CGEN_INSN_INT buffer[1]; |
| 49 | #define INSN_VALUE(buf) (*(buf)) |
| 50 | #else |
| 51 | unsigned char buffer[CGEN_MAX_INSN_SIZE]; |
| 52 | #define INSN_VALUE(buf) (buf) |
| 53 | #endif |
| 54 | char *addr; |
| 55 | fragS *frag; |
| 56 | int num_fixups; |
| 57 | fixS *fixups[GAS_CGEN_MAX_FIXUPS]; |
| 58 | int indices[MAX_OPERAND_INSTANCES]; |
| 59 | sym_linkS *debug_sym_link; |
| 60 | } |
| 61 | m32r_insn; |
| 62 | |
| 63 | /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit |
| 64 | boundary (i.e. was the first of two 16 bit insns). */ |
| 65 | static m32r_insn prev_insn; |
| 66 | |
| 67 | /* Non-zero if we've seen a relaxable insn since the last 32 bit |
| 68 | alignment request. */ |
| 69 | static int seen_relaxable_p = 0; |
| 70 | |
| 71 | /* Non-zero if we are generating PIC code. */ |
| 72 | int pic_code; |
| 73 | |
| 74 | /* Non-zero if -relax specified, in which case sufficient relocs are output |
| 75 | for the linker to do relaxing. |
| 76 | We do simple forms of relaxing internally, but they are always done. |
| 77 | This flag does not apply to them. */ |
| 78 | static int m32r_relax; |
| 79 | |
| 80 | /* Non-zero if warn when a high/shigh reloc has no matching low reloc. |
| 81 | Each high/shigh reloc must be paired with it's low cousin in order to |
| 82 | properly calculate the addend in a relocatable link (since there is a |
| 83 | potential carry from the low to the high/shigh). |
| 84 | This option is off by default though for user-written assembler code it |
| 85 | might make sense to make the default be on (i.e. have gcc pass a flag |
| 86 | to turn it off). This warning must not be on for GCC created code as |
| 87 | optimization may delete the low but not the high/shigh (at least we |
| 88 | shouldn't assume or require it to). */ |
| 89 | static int warn_unmatched_high = 0; |
| 90 | |
| 91 | /* 1 if -m32rx has been specified, in which case support for |
| 92 | the extended M32RX instruction set should be enabled. |
| 93 | 2 if -m32r2 has been specified, in which case support for |
| 94 | the extended M32R2 instruction set should be enabled. */ |
| 95 | static int enable_m32rx = 0; /* Default to M32R. */ |
| 96 | |
| 97 | /* Non-zero if -m32rx -hidden has been specified, in which case support for |
| 98 | the special M32RX instruction set should be enabled. */ |
| 99 | static int enable_special = 0; |
| 100 | |
| 101 | /* Non-zero if -bitinst has been specified, in which case support |
| 102 | for extended M32R bit-field instruction set should be enabled. */ |
| 103 | static int enable_special_m32r = 1; |
| 104 | |
| 105 | /* Non-zero if -float has been specified, in which case support for |
| 106 | extended M32R floating point instruction set should be enabled. */ |
| 107 | static int enable_special_float = 0; |
| 108 | |
| 109 | /* Non-zero if the programmer should be warned when an explicit parallel |
| 110 | instruction might have constraint violations. */ |
| 111 | static int warn_explicit_parallel_conflicts = 1; |
| 112 | |
| 113 | /* Non-zero if the programmer should not receive any messages about |
| 114 | parallel instruction with potential or real constraint violations. |
| 115 | The ability to suppress these messages is intended only for hardware |
| 116 | vendors testing the chip. It superceedes |
| 117 | warn_explicit_parallel_conflicts. */ |
| 118 | static int ignore_parallel_conflicts = 0; |
| 119 | |
| 120 | /* Non-zero if insns can be made parallel. */ |
| 121 | static int use_parallel = 0; |
| 122 | |
| 123 | /* Non-zero if optimizations should be performed. */ |
| 124 | static int optimize; |
| 125 | |
| 126 | /* m32r er_flags. */ |
| 127 | static int m32r_flags = 0; |
| 128 | |
| 129 | /* Stuff for .scomm symbols. */ |
| 130 | static segT sbss_section; |
| 131 | static asection scom_section; |
| 132 | static asymbol scom_symbol; |
| 133 | |
| 134 | const char comment_chars[] = ";"; |
| 135 | const char line_comment_chars[] = "#"; |
| 136 | const char line_separator_chars[] = "!"; |
| 137 | const char EXP_CHARS[] = "eE"; |
| 138 | const char FLT_CHARS[] = "dD"; |
| 139 | |
| 140 | /* Relocations against symbols are done in two |
| 141 | parts, with a HI relocation and a LO relocation. Each relocation |
| 142 | has only 16 bits of space to store an addend. This means that in |
| 143 | order for the linker to handle carries correctly, it must be able |
| 144 | to locate both the HI and the LO relocation. This means that the |
| 145 | relocations must appear in order in the relocation table. |
| 146 | |
| 147 | In order to implement this, we keep track of each unmatched HI |
| 148 | relocation. We then sort them so that they immediately precede the |
| 149 | corresponding LO relocation. */ |
| 150 | |
| 151 | struct m32r_hi_fixup |
| 152 | { |
| 153 | /* Next HI fixup. */ |
| 154 | struct m32r_hi_fixup *next; |
| 155 | |
| 156 | /* This fixup. */ |
| 157 | fixS *fixp; |
| 158 | |
| 159 | /* The section this fixup is in. */ |
| 160 | segT seg; |
| 161 | }; |
| 162 | |
| 163 | /* The list of unmatched HI relocs. */ |
| 164 | |
| 165 | static struct m32r_hi_fixup *m32r_hi_fixup_list; |
| 166 | \f |
| 167 | struct |
| 168 | { |
| 169 | enum bfd_architecture bfd_mach; |
| 170 | int mach_flags; |
| 171 | } mach_table[] = |
| 172 | { |
| 173 | { bfd_mach_m32r, (1<<MACH_M32R) }, |
| 174 | { bfd_mach_m32rx, (1<<MACH_M32RX) }, |
| 175 | { bfd_mach_m32r2, (1<<MACH_M32R2) } |
| 176 | }; |
| 177 | |
| 178 | static void |
| 179 | allow_m32rx (int on) |
| 180 | { |
| 181 | enable_m32rx = on; |
| 182 | |
| 183 | if (stdoutput != NULL) |
| 184 | bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach); |
| 185 | |
| 186 | if (gas_cgen_cpu_desc != NULL) |
| 187 | gas_cgen_cpu_desc->machs = mach_table[on].mach_flags; |
| 188 | } |
| 189 | \f |
| 190 | #define M32R_SHORTOPTS "O::K:" |
| 191 | |
| 192 | const char *md_shortopts = M32R_SHORTOPTS; |
| 193 | |
| 194 | enum md_option_enums |
| 195 | { |
| 196 | OPTION_M32R = OPTION_MD_BASE, |
| 197 | OPTION_M32RX, |
| 198 | OPTION_M32R2, |
| 199 | OPTION_BIG, |
| 200 | OPTION_LITTLE, |
| 201 | OPTION_PARALLEL, |
| 202 | OPTION_NO_PARALLEL, |
| 203 | OPTION_WARN_PARALLEL, |
| 204 | OPTION_NO_WARN_PARALLEL, |
| 205 | OPTION_IGNORE_PARALLEL, |
| 206 | OPTION_NO_IGNORE_PARALLEL, |
| 207 | OPTION_SPECIAL, |
| 208 | OPTION_SPECIAL_M32R, |
| 209 | OPTION_NO_SPECIAL_M32R, |
| 210 | OPTION_SPECIAL_FLOAT, |
| 211 | OPTION_WARN_UNMATCHED, |
| 212 | OPTION_NO_WARN_UNMATCHED |
| 213 | }; |
| 214 | |
| 215 | struct option md_longopts[] = |
| 216 | { |
| 217 | {"m32r", no_argument, NULL, OPTION_M32R}, |
| 218 | {"m32rx", no_argument, NULL, OPTION_M32RX}, |
| 219 | {"m32r2", no_argument, NULL, OPTION_M32R2}, |
| 220 | {"big", no_argument, NULL, OPTION_BIG}, |
| 221 | {"little", no_argument, NULL, OPTION_LITTLE}, |
| 222 | {"EB", no_argument, NULL, OPTION_BIG}, |
| 223 | {"EL", no_argument, NULL, OPTION_LITTLE}, |
| 224 | {"parallel", no_argument, NULL, OPTION_PARALLEL}, |
| 225 | {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL}, |
| 226 | {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, |
| 227 | {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, |
| 228 | {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
| 229 | {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, |
| 230 | {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL}, |
| 231 | {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL}, |
| 232 | {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, |
| 233 | {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, |
| 234 | {"hidden", no_argument, NULL, OPTION_SPECIAL}, |
| 235 | {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R}, |
| 236 | {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R}, |
| 237 | {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT}, |
| 238 | /* Sigh. I guess all warnings must now have both variants. */ |
| 239 | {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
| 240 | {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, |
| 241 | {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
| 242 | {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, |
| 243 | {NULL, no_argument, NULL, 0} |
| 244 | }; |
| 245 | |
| 246 | size_t md_longopts_size = sizeof (md_longopts); |
| 247 | |
| 248 | static void |
| 249 | little (int on) |
| 250 | { |
| 251 | target_big_endian = ! on; |
| 252 | } |
| 253 | |
| 254 | /* Use parallel execution. */ |
| 255 | |
| 256 | static int |
| 257 | parallel (void) |
| 258 | { |
| 259 | if (! enable_m32rx) |
| 260 | return 0; |
| 261 | |
| 262 | if (use_parallel == 1) |
| 263 | return 1; |
| 264 | |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | int |
| 269 | md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) |
| 270 | { |
| 271 | switch (c) |
| 272 | { |
| 273 | case 'O': |
| 274 | optimize = 1; |
| 275 | use_parallel = 1; |
| 276 | break; |
| 277 | |
| 278 | case OPTION_M32R: |
| 279 | allow_m32rx (0); |
| 280 | break; |
| 281 | |
| 282 | case OPTION_M32RX: |
| 283 | allow_m32rx (1); |
| 284 | break; |
| 285 | |
| 286 | case OPTION_M32R2: |
| 287 | allow_m32rx (2); |
| 288 | enable_special = 1; |
| 289 | enable_special_m32r = 1; |
| 290 | break; |
| 291 | |
| 292 | case OPTION_BIG: |
| 293 | target_big_endian = 1; |
| 294 | break; |
| 295 | |
| 296 | case OPTION_LITTLE: |
| 297 | target_big_endian = 0; |
| 298 | break; |
| 299 | |
| 300 | case OPTION_PARALLEL: |
| 301 | use_parallel = 1; |
| 302 | break; |
| 303 | |
| 304 | case OPTION_NO_PARALLEL: |
| 305 | use_parallel = 0; |
| 306 | break; |
| 307 | |
| 308 | case OPTION_WARN_PARALLEL: |
| 309 | warn_explicit_parallel_conflicts = 1; |
| 310 | break; |
| 311 | |
| 312 | case OPTION_NO_WARN_PARALLEL: |
| 313 | warn_explicit_parallel_conflicts = 0; |
| 314 | break; |
| 315 | |
| 316 | case OPTION_IGNORE_PARALLEL: |
| 317 | ignore_parallel_conflicts = 1; |
| 318 | break; |
| 319 | |
| 320 | case OPTION_NO_IGNORE_PARALLEL: |
| 321 | ignore_parallel_conflicts = 0; |
| 322 | break; |
| 323 | |
| 324 | case OPTION_SPECIAL: |
| 325 | if (enable_m32rx) |
| 326 | enable_special = 1; |
| 327 | else |
| 328 | { |
| 329 | /* Pretend that we do not recognise this option. */ |
| 330 | as_bad (_("Unrecognised option: -hidden")); |
| 331 | return 0; |
| 332 | } |
| 333 | break; |
| 334 | |
| 335 | case OPTION_SPECIAL_M32R: |
| 336 | enable_special_m32r = 1; |
| 337 | break; |
| 338 | |
| 339 | case OPTION_NO_SPECIAL_M32R: |
| 340 | enable_special_m32r = 0; |
| 341 | break; |
| 342 | |
| 343 | case OPTION_SPECIAL_FLOAT: |
| 344 | enable_special_float = 1; |
| 345 | break; |
| 346 | |
| 347 | case OPTION_WARN_UNMATCHED: |
| 348 | warn_unmatched_high = 1; |
| 349 | break; |
| 350 | |
| 351 | case OPTION_NO_WARN_UNMATCHED: |
| 352 | warn_unmatched_high = 0; |
| 353 | break; |
| 354 | |
| 355 | case 'K': |
| 356 | if (strcmp (arg, "PIC") != 0) |
| 357 | as_warn (_("Unrecognized option following -K")); |
| 358 | else |
| 359 | pic_code = 1; |
| 360 | break; |
| 361 | |
| 362 | default: |
| 363 | return 0; |
| 364 | } |
| 365 | |
| 366 | return 1; |
| 367 | } |
| 368 | |
| 369 | void |
| 370 | md_show_usage (FILE *stream) |
| 371 | { |
| 372 | fprintf (stream, _(" M32R specific command line options:\n")); |
| 373 | |
| 374 | fprintf (stream, _("\ |
| 375 | -m32r disable support for the m32rx instruction set\n")); |
| 376 | fprintf (stream, _("\ |
| 377 | -m32rx support the extended m32rx instruction set\n")); |
| 378 | fprintf (stream, _("\ |
| 379 | -m32r2 support the extended m32r2 instruction set\n")); |
| 380 | fprintf (stream, _("\ |
| 381 | -EL,-little produce little endian code and data\n")); |
| 382 | fprintf (stream, _("\ |
| 383 | -EB,-big produce big endian code and data\n")); |
| 384 | fprintf (stream, _("\ |
| 385 | -parallel try to combine instructions in parallel\n")); |
| 386 | fprintf (stream, _("\ |
| 387 | -no-parallel disable -parallel\n")); |
| 388 | fprintf (stream, _("\ |
| 389 | -no-bitinst disallow the M32R2's extended bit-field instructions\n")); |
| 390 | fprintf (stream, _("\ |
| 391 | -O try to optimize code. Implies -parallel\n")); |
| 392 | |
| 393 | fprintf (stream, _("\ |
| 394 | -warn-explicit-parallel-conflicts warn when parallel instructions\n")); |
| 395 | fprintf (stream, _("\ |
| 396 | might violate contraints\n")); |
| 397 | fprintf (stream, _("\ |
| 398 | -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); |
| 399 | fprintf (stream, _("\ |
| 400 | instructions might violate contraints\n")); |
| 401 | fprintf (stream, _("\ |
| 402 | -Wp synonym for -warn-explicit-parallel-conflicts\n")); |
| 403 | fprintf (stream, _("\ |
| 404 | -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); |
| 405 | fprintf (stream, _("\ |
| 406 | -ignore-parallel-conflicts do not check parallel instructions\n")); |
| 407 | fprintf (stream, _("\ |
| 408 | for constraint violations\n")); |
| 409 | fprintf (stream, _("\ |
| 410 | -no-ignore-parallel-conflicts check parallel instructions for\n")); |
| 411 | fprintf (stream, _("\ |
| 412 | constraint violations\n")); |
| 413 | fprintf (stream, _("\ |
| 414 | -Ip synonym for -ignore-parallel-conflicts\n")); |
| 415 | fprintf (stream, _("\ |
| 416 | -nIp synonym for -no-ignore-parallel-conflicts\n")); |
| 417 | |
| 418 | fprintf (stream, _("\ |
| 419 | -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); |
| 420 | fprintf (stream, _("\ |
| 421 | -no-warn-unmatched-high do not warn about missing low relocs\n")); |
| 422 | fprintf (stream, _("\ |
| 423 | -Wuh synonym for -warn-unmatched-high\n")); |
| 424 | fprintf (stream, _("\ |
| 425 | -Wnuh synonym for -no-warn-unmatched-high\n")); |
| 426 | |
| 427 | fprintf (stream, _("\ |
| 428 | -KPIC generate PIC\n")); |
| 429 | } |
| 430 | |
| 431 | /* Set by md_assemble for use by m32r_fill_insn. */ |
| 432 | static subsegT prev_subseg; |
| 433 | static segT prev_seg; |
| 434 | |
| 435 | #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" |
| 436 | symbolS * GOT_symbol; |
| 437 | |
| 438 | static inline int |
| 439 | m32r_PIC_related_p (symbolS *sym) |
| 440 | { |
| 441 | expressionS *exp; |
| 442 | |
| 443 | if (! sym) |
| 444 | return 0; |
| 445 | |
| 446 | if (sym == GOT_symbol) |
| 447 | return 1; |
| 448 | |
| 449 | exp = symbol_get_value_expression (sym); |
| 450 | |
| 451 | return (exp->X_op == O_PIC_reloc |
| 452 | || exp->X_md == BFD_RELOC_M32R_26_PLTREL |
| 453 | || m32r_PIC_related_p (exp->X_add_symbol) |
| 454 | || m32r_PIC_related_p (exp->X_op_symbol)); |
| 455 | } |
| 456 | |
| 457 | static inline int |
| 458 | m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p) |
| 459 | { |
| 460 | expressionS *exp = main_exp; |
| 461 | |
| 462 | if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol)) |
| 463 | return 1; |
| 464 | |
| 465 | if (exp->X_op == O_symbol && exp->X_add_symbol) |
| 466 | { |
| 467 | if (exp->X_add_symbol == GOT_symbol) |
| 468 | { |
| 469 | *r_type_p = BFD_RELOC_M32R_GOTPC24; |
| 470 | return 0; |
| 471 | } |
| 472 | } |
| 473 | else if (exp->X_op == O_add) |
| 474 | { |
| 475 | exp = symbol_get_value_expression (exp->X_add_symbol); |
| 476 | if (! exp) |
| 477 | return 0; |
| 478 | } |
| 479 | |
| 480 | if (exp->X_op == O_PIC_reloc) |
| 481 | { |
| 482 | *r_type_p = exp->X_md; |
| 483 | if (exp == main_exp) |
| 484 | exp->X_op = O_symbol; |
| 485 | else |
| 486 | { |
| 487 | main_exp->X_add_symbol = exp->X_add_symbol; |
| 488 | main_exp->X_add_number += exp->X_add_number; |
| 489 | } |
| 490 | } |
| 491 | else |
| 492 | return (m32r_PIC_related_p (exp->X_add_symbol) |
| 493 | || m32r_PIC_related_p (exp->X_op_symbol)); |
| 494 | |
| 495 | return 0; |
| 496 | } |
| 497 | |
| 498 | /* FIXME: Should be machine generated. */ |
| 499 | #define NOP_INSN 0x7000 |
| 500 | #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ |
| 501 | |
| 502 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
| 503 | of an rs_align_code fragment. */ |
| 504 | |
| 505 | void |
| 506 | m32r_handle_align (fragS *fragp) |
| 507 | { |
| 508 | static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; |
| 509 | static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; |
| 510 | |
| 511 | int bytes, fix; |
| 512 | char *p; |
| 513 | |
| 514 | if (fragp->fr_type != rs_align_code) |
| 515 | return; |
| 516 | |
| 517 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
| 518 | p = fragp->fr_literal + fragp->fr_fix; |
| 519 | fix = 0; |
| 520 | |
| 521 | if (bytes & 1) |
| 522 | { |
| 523 | fix = 1; |
| 524 | *p++ = 0; |
| 525 | bytes--; |
| 526 | } |
| 527 | |
| 528 | if (bytes & 2) |
| 529 | { |
| 530 | memcpy (p, nop_pattern, 2); |
| 531 | p += 2; |
| 532 | bytes -= 2; |
| 533 | fix += 2; |
| 534 | } |
| 535 | |
| 536 | memcpy (p, multi_nop_pattern, 4); |
| 537 | |
| 538 | fragp->fr_fix += fix; |
| 539 | fragp->fr_var = 4; |
| 540 | } |
| 541 | |
| 542 | /* If the last instruction was the first of 2 16 bit insns, |
| 543 | output a nop to move the PC to a 32 bit boundary. |
| 544 | |
| 545 | This is done via an alignment specification since branch relaxing |
| 546 | may make it unnecessary. |
| 547 | |
| 548 | Internally, we need to output one of these each time a 32 bit insn is |
| 549 | seen after an insn that is relaxable. */ |
| 550 | |
| 551 | static void |
| 552 | fill_insn (int ignore ATTRIBUTE_UNUSED) |
| 553 | { |
| 554 | frag_align_code (2, 0); |
| 555 | prev_insn.insn = NULL; |
| 556 | seen_relaxable_p = 0; |
| 557 | } |
| 558 | |
| 559 | /* Record the symbol so that when we output the insn, we can create |
| 560 | a symbol that is at the start of the instruction. This is used |
| 561 | to emit the label for the start of a breakpoint without causing |
| 562 | the assembler to emit a NOP if the previous instruction was a |
| 563 | 16 bit instruction. */ |
| 564 | |
| 565 | static void |
| 566 | debug_sym (int ignore ATTRIBUTE_UNUSED) |
| 567 | { |
| 568 | char *name; |
| 569 | char delim; |
| 570 | symbolS *symbolP; |
| 571 | sym_linkS *lnk; |
| 572 | |
| 573 | delim = get_symbol_name (&name); |
| 574 | |
| 575 | if ((symbolP = symbol_find (name)) == NULL |
| 576 | && (symbolP = md_undefined_symbol (name)) == NULL) |
| 577 | symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); |
| 578 | |
| 579 | symbol_table_insert (symbolP); |
| 580 | if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section |
| 581 | || S_IS_EXTERNAL (symbolP) |
| 582 | || S_IS_WEAK (symbolP))) |
| 583 | /* xgettext:c-format */ |
| 584 | as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); |
| 585 | |
| 586 | else |
| 587 | { |
| 588 | lnk = (sym_linkS *) xmalloc (sizeof (sym_linkS)); |
| 589 | lnk->symbol = symbolP; |
| 590 | lnk->next = debug_sym_link; |
| 591 | debug_sym_link = lnk; |
| 592 | symbol_get_obj (symbolP)->local = 1; |
| 593 | } |
| 594 | |
| 595 | (void) restore_line_pointer (delim); |
| 596 | demand_empty_rest_of_line (); |
| 597 | } |
| 598 | |
| 599 | /* Second pass to expanding the debug symbols, go through linked |
| 600 | list of symbols and reassign the address. */ |
| 601 | |
| 602 | static void |
| 603 | expand_debug_syms (sym_linkS *syms, int align) |
| 604 | { |
| 605 | char *save_input_line = input_line_pointer; |
| 606 | sym_linkS *next_syms; |
| 607 | |
| 608 | if (!syms) |
| 609 | return; |
| 610 | |
| 611 | (void) frag_align_code (align, 0); |
| 612 | for (; syms != (sym_linkS *) 0; syms = next_syms) |
| 613 | { |
| 614 | symbolS *symbolP = syms->symbol; |
| 615 | next_syms = syms->next; |
| 616 | input_line_pointer = ".\n"; |
| 617 | pseudo_set (symbolP); |
| 618 | free ((char *) syms); |
| 619 | } |
| 620 | |
| 621 | input_line_pointer = save_input_line; |
| 622 | } |
| 623 | |
| 624 | void |
| 625 | m32r_flush_pending_output (void) |
| 626 | { |
| 627 | if (debug_sym_link) |
| 628 | { |
| 629 | expand_debug_syms (debug_sym_link, 1); |
| 630 | debug_sym_link = (sym_linkS *) 0; |
| 631 | } |
| 632 | } |
| 633 | |
| 634 | /* Cover function to fill_insn called after a label and at end of assembly. |
| 635 | The result is always 1: we're called in a conditional to see if the |
| 636 | current line is a label. */ |
| 637 | |
| 638 | int |
| 639 | m32r_fill_insn (int done) |
| 640 | { |
| 641 | if (prev_seg != NULL) |
| 642 | { |
| 643 | segT seg = now_seg; |
| 644 | subsegT subseg = now_subseg; |
| 645 | |
| 646 | subseg_set (prev_seg, prev_subseg); |
| 647 | |
| 648 | fill_insn (0); |
| 649 | |
| 650 | subseg_set (seg, subseg); |
| 651 | } |
| 652 | |
| 653 | if (done && debug_sym_link) |
| 654 | { |
| 655 | expand_debug_syms (debug_sym_link, 1); |
| 656 | debug_sym_link = (sym_linkS *) 0; |
| 657 | } |
| 658 | |
| 659 | return 1; |
| 660 | } |
| 661 | \f |
| 662 | /* The default target format to use. */ |
| 663 | |
| 664 | const char * |
| 665 | m32r_target_format (void) |
| 666 | { |
| 667 | #ifdef TE_LINUX |
| 668 | if (target_big_endian) |
| 669 | return "elf32-m32r-linux"; |
| 670 | else |
| 671 | return "elf32-m32rle-linux"; |
| 672 | #else |
| 673 | if (target_big_endian) |
| 674 | return "elf32-m32r"; |
| 675 | else |
| 676 | return "elf32-m32rle"; |
| 677 | #endif |
| 678 | } |
| 679 | |
| 680 | void |
| 681 | md_begin (void) |
| 682 | { |
| 683 | flagword applicable; |
| 684 | segT seg; |
| 685 | subsegT subseg; |
| 686 | |
| 687 | /* Initialize the `cgen' interface. */ |
| 688 | |
| 689 | /* Set the machine number and endian. */ |
| 690 | gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, |
| 691 | CGEN_CPU_OPEN_ENDIAN, |
| 692 | (target_big_endian ? |
| 693 | CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE), |
| 694 | CGEN_CPU_OPEN_END); |
| 695 | m32r_cgen_init_asm (gas_cgen_cpu_desc); |
| 696 | |
| 697 | /* The operand instance table is used during optimization to determine |
| 698 | which insns can be executed in parallel. It is also used to give |
| 699 | warnings regarding operand interference in parallel insns. */ |
| 700 | m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); |
| 701 | |
| 702 | /* This is a callback from cgen to gas to parse operands. */ |
| 703 | cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); |
| 704 | |
| 705 | /* Save the current subseg so we can restore it [it's the default one and |
| 706 | we don't want the initial section to be .sbss]. */ |
| 707 | seg = now_seg; |
| 708 | subseg = now_subseg; |
| 709 | |
| 710 | /* The sbss section is for local .scomm symbols. */ |
| 711 | sbss_section = subseg_new (".sbss", 0); |
| 712 | seg_info (sbss_section)->bss = 1; |
| 713 | |
| 714 | /* This is copied from perform_an_assembly_pass. */ |
| 715 | applicable = bfd_applicable_section_flags (stdoutput); |
| 716 | bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); |
| 717 | |
| 718 | subseg_set (seg, subseg); |
| 719 | |
| 720 | /* We must construct a fake section similar to bfd_com_section |
| 721 | but with the name .scommon. */ |
| 722 | scom_section = *bfd_com_section_ptr; |
| 723 | scom_section.name = ".scommon"; |
| 724 | scom_section.output_section = & scom_section; |
| 725 | scom_section.symbol = & scom_symbol; |
| 726 | scom_section.symbol_ptr_ptr = & scom_section.symbol; |
| 727 | scom_symbol = * bfd_com_section_ptr->symbol; |
| 728 | scom_symbol.name = ".scommon"; |
| 729 | scom_symbol.section = & scom_section; |
| 730 | |
| 731 | allow_m32rx (enable_m32rx); |
| 732 | |
| 733 | gas_cgen_initialize_saved_fixups_array (); |
| 734 | } |
| 735 | |
| 736 | #define OPERAND_IS_COND_BIT(operand, indices, index) \ |
| 737 | ((operand)->hw_type == HW_H_COND \ |
| 738 | || ((operand)->hw_type == HW_H_PSW) \ |
| 739 | || ((operand)->hw_type == HW_H_CR \ |
| 740 | && (indices [index] == 0 || indices [index] == 1))) |
| 741 | |
| 742 | /* Returns true if an output of instruction 'a' is referenced by an operand |
| 743 | of instruction 'b'. If 'check_outputs' is true then b's outputs are |
| 744 | checked, otherwise its inputs are examined. */ |
| 745 | |
| 746 | static int |
| 747 | first_writes_to_seconds_operands (m32r_insn *a, |
| 748 | m32r_insn *b, |
| 749 | const int check_outputs) |
| 750 | { |
| 751 | const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); |
| 752 | const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); |
| 753 | int a_index; |
| 754 | |
| 755 | if (ignore_parallel_conflicts) |
| 756 | return 0; |
| 757 | |
| 758 | /* If at least one of the instructions takes no operands, then there is |
| 759 | nothing to check. There really are instructions without operands, |
| 760 | eg 'nop'. */ |
| 761 | if (a_operands == NULL || b_ops == NULL) |
| 762 | return 0; |
| 763 | |
| 764 | /* Scan the operand list of 'a' looking for an output operand. */ |
| 765 | for (a_index = 0; |
| 766 | a_operands->type != CGEN_OPINST_END; |
| 767 | a_index ++, a_operands ++) |
| 768 | { |
| 769 | if (a_operands->type == CGEN_OPINST_OUTPUT) |
| 770 | { |
| 771 | int b_index; |
| 772 | const CGEN_OPINST *b_operands = b_ops; |
| 773 | |
| 774 | /* Special Case: |
| 775 | The Condition bit 'C' is a shadow of the CBR register (control |
| 776 | register 1) and also a shadow of bit 31 of the program status |
| 777 | word (control register 0). For now this is handled here, rather |
| 778 | than by cgen.... */ |
| 779 | |
| 780 | if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) |
| 781 | { |
| 782 | /* Scan operand list of 'b' looking for another reference to the |
| 783 | condition bit, which goes in the right direction. */ |
| 784 | for (b_index = 0; |
| 785 | b_operands->type != CGEN_OPINST_END; |
| 786 | b_index++, b_operands++) |
| 787 | { |
| 788 | if ((b_operands->type |
| 789 | == (check_outputs |
| 790 | ? CGEN_OPINST_OUTPUT |
| 791 | : CGEN_OPINST_INPUT)) |
| 792 | && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) |
| 793 | return 1; |
| 794 | } |
| 795 | } |
| 796 | else |
| 797 | { |
| 798 | /* Scan operand list of 'b' looking for an operand that |
| 799 | references the same hardware element, and which goes in the |
| 800 | right direction. */ |
| 801 | for (b_index = 0; |
| 802 | b_operands->type != CGEN_OPINST_END; |
| 803 | b_index++, b_operands++) |
| 804 | { |
| 805 | if ((b_operands->type |
| 806 | == (check_outputs |
| 807 | ? CGEN_OPINST_OUTPUT |
| 808 | : CGEN_OPINST_INPUT)) |
| 809 | && (b_operands->hw_type == a_operands->hw_type) |
| 810 | && (a->indices[a_index] == b->indices[b_index])) |
| 811 | return 1; |
| 812 | } |
| 813 | } |
| 814 | } |
| 815 | } |
| 816 | |
| 817 | return 0; |
| 818 | } |
| 819 | |
| 820 | /* Returns true if the insn can (potentially) alter the program counter. */ |
| 821 | |
| 822 | static int |
| 823 | writes_to_pc (m32r_insn *a) |
| 824 | { |
| 825 | if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) |
| 826 | || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) |
| 827 | return 1; |
| 828 | return 0; |
| 829 | } |
| 830 | |
| 831 | /* Return NULL if the two 16 bit insns can be executed in parallel. |
| 832 | Otherwise return a pointer to an error message explaining why not. */ |
| 833 | |
| 834 | static const char * |
| 835 | can_make_parallel (m32r_insn *a, m32r_insn *b) |
| 836 | { |
| 837 | PIPE_ATTR a_pipe; |
| 838 | PIPE_ATTR b_pipe; |
| 839 | |
| 840 | /* Make sure the instructions are the right length. */ |
| 841 | if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 |
| 842 | || CGEN_FIELDS_BITSIZE (&b->fields) != 16) |
| 843 | abort (); |
| 844 | |
| 845 | if (first_writes_to_seconds_operands (a, b, TRUE)) |
| 846 | return _("instructions write to the same destination register."); |
| 847 | |
| 848 | a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); |
| 849 | b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); |
| 850 | |
| 851 | /* Make sure that the instructions use the correct execution pipelines. */ |
| 852 | if (a_pipe == PIPE_NONE |
| 853 | || b_pipe == PIPE_NONE) |
| 854 | return _("Instructions do not use parallel execution pipelines."); |
| 855 | |
| 856 | /* Leave this test for last, since it is the only test that can |
| 857 | go away if the instructions are swapped, and we want to make |
| 858 | sure that any other errors are detected before this happens. */ |
| 859 | if (a_pipe == PIPE_S |
| 860 | || b_pipe == PIPE_O |
| 861 | || (b_pipe == PIPE_O_OS && (enable_m32rx != 2))) |
| 862 | return _("Instructions share the same execution pipeline"); |
| 863 | |
| 864 | return NULL; |
| 865 | } |
| 866 | |
| 867 | /* Force the top bit of the second 16-bit insn to be set. */ |
| 868 | |
| 869 | static void |
| 870 | make_parallel (CGEN_INSN_BYTES_PTR buffer) |
| 871 | { |
| 872 | #if CGEN_INT_INSN_P |
| 873 | *buffer |= 0x8000; |
| 874 | #else |
| 875 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
| 876 | |= 0x80; |
| 877 | #endif |
| 878 | } |
| 879 | |
| 880 | /* Same as make_parallel except buffer contains the bytes in target order. */ |
| 881 | |
| 882 | static void |
| 883 | target_make_parallel (char *buffer) |
| 884 | { |
| 885 | buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] |
| 886 | |= 0x80; |
| 887 | } |
| 888 | |
| 889 | /* Assemble two instructions with an explicit parallel operation (||) or |
| 890 | sequential operation (->). */ |
| 891 | |
| 892 | static void |
| 893 | assemble_two_insns (char *str1, char *str2, int parallel_p) |
| 894 | { |
| 895 | char *str3; |
| 896 | m32r_insn first; |
| 897 | m32r_insn second; |
| 898 | char *errmsg; |
| 899 | char save_str2 = *str2; |
| 900 | |
| 901 | /* Separate the two instructions. */ |
| 902 | *str2 = 0; |
| 903 | |
| 904 | /* Make sure the two insns begin on a 32 bit boundary. |
| 905 | This is also done for the serial case (foo -> bar), relaxing doesn't |
| 906 | affect insns written like this. |
| 907 | Note that we must always do this as we can't assume anything about |
| 908 | whether we're currently on a 32 bit boundary or not. Relaxing may |
| 909 | change this. */ |
| 910 | fill_insn (0); |
| 911 | |
| 912 | first.debug_sym_link = debug_sym_link; |
| 913 | debug_sym_link = (sym_linkS *) 0; |
| 914 | |
| 915 | /* Parse the first instruction. */ |
| 916 | if (! (first.insn = m32r_cgen_assemble_insn |
| 917 | (gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg))) |
| 918 | { |
| 919 | as_bad ("%s", errmsg); |
| 920 | return; |
| 921 | } |
| 922 | |
| 923 | /* Check it. */ |
| 924 | if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) |
| 925 | { |
| 926 | /* xgettext:c-format */ |
| 927 | as_bad (_("not a 16 bit instruction '%s'"), str1); |
| 928 | return; |
| 929 | } |
| 930 | #ifdef E_M32R2_ARCH |
| 931 | else if ((enable_m32rx == 1) |
| 932 | /* FIXME: Need standard macro to perform this test. */ |
| 933 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 934 | & (1 << MACH_M32R2)) |
| 935 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 936 | & (1 << MACH_M32RX))))) |
| 937 | { |
| 938 | /* xgettext:c-format */ |
| 939 | as_bad (_("instruction '%s' is for the M32R2 only"), str1); |
| 940 | return; |
| 941 | } |
| 942 | else if ((! enable_special |
| 943 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) |
| 944 | || (! enable_special_m32r |
| 945 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R))) |
| 946 | #else |
| 947 | else if (! enable_special |
| 948 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) |
| 949 | #endif |
| 950 | { |
| 951 | /* xgettext:c-format */ |
| 952 | as_bad (_("unknown instruction '%s'"), str1); |
| 953 | return; |
| 954 | } |
| 955 | else if (! enable_m32rx |
| 956 | /* FIXME: Need standard macro to perform this test. */ |
| 957 | && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 958 | == (1 << MACH_M32RX))) |
| 959 | { |
| 960 | /* xgettext:c-format */ |
| 961 | as_bad (_("instruction '%s' is for the M32RX only"), str1); |
| 962 | return; |
| 963 | } |
| 964 | |
| 965 | /* Check to see if this is an allowable parallel insn. */ |
| 966 | if (parallel_p |
| 967 | && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) |
| 968 | { |
| 969 | /* xgettext:c-format */ |
| 970 | as_bad (_("instruction '%s' cannot be executed in parallel."), str1); |
| 971 | return; |
| 972 | } |
| 973 | |
| 974 | /* Restore the original assembly text, just in case it is needed. */ |
| 975 | *str2 = save_str2; |
| 976 | |
| 977 | /* Save the original string pointer. */ |
| 978 | str3 = str1; |
| 979 | |
| 980 | /* Advanced past the parsed string. */ |
| 981 | str1 = str2 + 2; |
| 982 | |
| 983 | /* Remember the entire string in case it is needed for error |
| 984 | messages. */ |
| 985 | str2 = str3; |
| 986 | |
| 987 | /* Convert the opcode to lower case. */ |
| 988 | { |
| 989 | char *s2 = str1; |
| 990 | |
| 991 | while (ISSPACE (*s2++)) |
| 992 | continue; |
| 993 | |
| 994 | --s2; |
| 995 | |
| 996 | while (ISALNUM (*s2)) |
| 997 | { |
| 998 | *s2 = TOLOWER (*s2); |
| 999 | s2++; |
| 1000 | } |
| 1001 | } |
| 1002 | |
| 1003 | /* Preserve any fixups that have been generated and reset the list |
| 1004 | to empty. */ |
| 1005 | gas_cgen_save_fixups (0); |
| 1006 | |
| 1007 | /* Get the indices of the operands of the instruction. */ |
| 1008 | /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact |
| 1009 | doesn't seem right. Perhaps allow passing fields like we do insn. */ |
| 1010 | /* FIXME: ALIAS insns do not have operands, so we use this function |
| 1011 | to find the equivalent insn and overwrite the value stored in our |
| 1012 | structure. We still need the original insn, however, since this |
| 1013 | may have certain attributes that are not present in the unaliased |
| 1014 | version (eg relaxability). When aliases behave differently this |
| 1015 | may have to change. */ |
| 1016 | first.orig_insn = first.insn; |
| 1017 | { |
| 1018 | CGEN_FIELDS tmp_fields; |
| 1019 | first.insn = cgen_lookup_get_insn_operands |
| 1020 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, |
| 1021 | first.indices, &tmp_fields); |
| 1022 | } |
| 1023 | |
| 1024 | if (first.insn == NULL) |
| 1025 | as_fatal (_("internal error: lookup/get operands failed")); |
| 1026 | |
| 1027 | second.debug_sym_link = NULL; |
| 1028 | |
| 1029 | /* Parse the second instruction. */ |
| 1030 | if (! (second.insn = m32r_cgen_assemble_insn |
| 1031 | (gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg))) |
| 1032 | { |
| 1033 | as_bad ("%s", errmsg); |
| 1034 | return; |
| 1035 | } |
| 1036 | |
| 1037 | /* Check it. */ |
| 1038 | if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) |
| 1039 | { |
| 1040 | /* xgettext:c-format */ |
| 1041 | as_bad (_("not a 16 bit instruction '%s'"), str1); |
| 1042 | return; |
| 1043 | } |
| 1044 | #ifdef E_M32R2_ARCH |
| 1045 | else if ((enable_m32rx == 1) |
| 1046 | /* FIXME: Need standard macro to perform this test. */ |
| 1047 | && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 1048 | & (1 << MACH_M32R2)) |
| 1049 | && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) |
| 1050 | & (1 << MACH_M32RX))))) |
| 1051 | { |
| 1052 | /* xgettext:c-format */ |
| 1053 | as_bad (_("instruction '%s' is for the M32R2 only"), str1); |
| 1054 | return; |
| 1055 | } |
| 1056 | else if ((! enable_special |
| 1057 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) |
| 1058 | || (! enable_special_m32r |
| 1059 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))) |
| 1060 | #else |
| 1061 | else if (! enable_special |
| 1062 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) |
| 1063 | #endif |
| 1064 | { |
| 1065 | /* xgettext:c-format */ |
| 1066 | as_bad (_("unknown instruction '%s'"), str1); |
| 1067 | return; |
| 1068 | } |
| 1069 | else if (! enable_m32rx |
| 1070 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
| 1071 | { |
| 1072 | /* xgettext:c-format */ |
| 1073 | as_bad (_("instruction '%s' is for the M32RX only"), str1); |
| 1074 | return; |
| 1075 | } |
| 1076 | |
| 1077 | /* Check to see if this is an allowable parallel insn. */ |
| 1078 | if (parallel_p |
| 1079 | && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) |
| 1080 | { |
| 1081 | /* xgettext:c-format */ |
| 1082 | as_bad (_("instruction '%s' cannot be executed in parallel."), str1); |
| 1083 | return; |
| 1084 | } |
| 1085 | |
| 1086 | if (parallel_p && ! enable_m32rx) |
| 1087 | { |
| 1088 | if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP |
| 1089 | && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) |
| 1090 | { |
| 1091 | /* xgettext:c-format */ |
| 1092 | as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); |
| 1093 | return; |
| 1094 | } |
| 1095 | } |
| 1096 | |
| 1097 | /* Get the indices of the operands of the instruction. */ |
| 1098 | second.orig_insn = second.insn; |
| 1099 | { |
| 1100 | CGEN_FIELDS tmp_fields; |
| 1101 | second.insn = cgen_lookup_get_insn_operands |
| 1102 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, |
| 1103 | second.indices, &tmp_fields); |
| 1104 | } |
| 1105 | |
| 1106 | if (second.insn == NULL) |
| 1107 | as_fatal (_("internal error: lookup/get operands failed")); |
| 1108 | |
| 1109 | /* We assume that if the first instruction writes to a register that is |
| 1110 | read by the second instruction it is because the programmer intended |
| 1111 | this to happen, (after all they have explicitly requested that these |
| 1112 | two instructions be executed in parallel). Although if the global |
| 1113 | variable warn_explicit_parallel_conflicts is true then we do generate |
| 1114 | a warning message. Similarly we assume that parallel branch and jump |
| 1115 | instructions are deliberate and should not produce errors. */ |
| 1116 | |
| 1117 | if (parallel_p && warn_explicit_parallel_conflicts) |
| 1118 | { |
| 1119 | if (first_writes_to_seconds_operands (&first, &second, FALSE)) |
| 1120 | /* xgettext:c-format */ |
| 1121 | as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); |
| 1122 | |
| 1123 | if (first_writes_to_seconds_operands (&second, &first, FALSE)) |
| 1124 | /* xgettext:c-format */ |
| 1125 | as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); |
| 1126 | } |
| 1127 | |
| 1128 | if (!parallel_p |
| 1129 | || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) |
| 1130 | { |
| 1131 | /* Get the fixups for the first instruction. */ |
| 1132 | gas_cgen_swap_fixups (0); |
| 1133 | |
| 1134 | /* Write it out. */ |
| 1135 | expand_debug_syms (first.debug_sym_link, 1); |
| 1136 | gas_cgen_finish_insn (first.orig_insn, first.buffer, |
| 1137 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
| 1138 | |
| 1139 | /* Force the top bit of the second insn to be set. */ |
| 1140 | if (parallel_p) |
| 1141 | make_parallel (second.buffer); |
| 1142 | |
| 1143 | /* Get its fixups. */ |
| 1144 | gas_cgen_restore_fixups (0); |
| 1145 | |
| 1146 | /* Write it out. */ |
| 1147 | expand_debug_syms (second.debug_sym_link, 1); |
| 1148 | gas_cgen_finish_insn (second.orig_insn, second.buffer, |
| 1149 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
| 1150 | } |
| 1151 | /* Try swapping the instructions to see if they work that way. */ |
| 1152 | else if (can_make_parallel (&second, &first) == NULL) |
| 1153 | { |
| 1154 | /* Write out the second instruction first. */ |
| 1155 | expand_debug_syms (second.debug_sym_link, 1); |
| 1156 | gas_cgen_finish_insn (second.orig_insn, second.buffer, |
| 1157 | CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); |
| 1158 | |
| 1159 | /* Force the top bit of the first instruction to be set. */ |
| 1160 | make_parallel (first.buffer); |
| 1161 | |
| 1162 | /* Get the fixups for the first instruction. */ |
| 1163 | gas_cgen_restore_fixups (0); |
| 1164 | |
| 1165 | /* Write out the first instruction. */ |
| 1166 | expand_debug_syms (first.debug_sym_link, 1); |
| 1167 | gas_cgen_finish_insn (first.orig_insn, first.buffer, |
| 1168 | CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); |
| 1169 | } |
| 1170 | else |
| 1171 | { |
| 1172 | as_bad ("'%s': %s", str2, errmsg); |
| 1173 | return; |
| 1174 | } |
| 1175 | |
| 1176 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL) |
| 1177 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) |
| 1178 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; |
| 1179 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R) |
| 1180 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)) |
| 1181 | m32r_flags |= E_M32R_HAS_BIT_INST; |
| 1182 | if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT) |
| 1183 | || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT)) |
| 1184 | m32r_flags |= E_M32R_HAS_FLOAT_INST; |
| 1185 | |
| 1186 | /* Set these so m32r_fill_insn can use them. */ |
| 1187 | prev_seg = now_seg; |
| 1188 | prev_subseg = now_subseg; |
| 1189 | } |
| 1190 | |
| 1191 | void |
| 1192 | md_assemble (char *str) |
| 1193 | { |
| 1194 | m32r_insn insn; |
| 1195 | char *errmsg; |
| 1196 | char *str2 = NULL; |
| 1197 | |
| 1198 | /* Initialize GAS's cgen interface for a new instruction. */ |
| 1199 | gas_cgen_init_parse (); |
| 1200 | |
| 1201 | /* Look for a parallel instruction separator. */ |
| 1202 | if ((str2 = strstr (str, "||")) != NULL) |
| 1203 | { |
| 1204 | assemble_two_insns (str, str2, 1); |
| 1205 | m32r_flags |= E_M32R_HAS_PARALLEL; |
| 1206 | return; |
| 1207 | } |
| 1208 | |
| 1209 | /* Also look for a sequential instruction separator. */ |
| 1210 | if ((str2 = strstr (str, "->")) != NULL) |
| 1211 | { |
| 1212 | assemble_two_insns (str, str2, 0); |
| 1213 | return; |
| 1214 | } |
| 1215 | |
| 1216 | insn.debug_sym_link = debug_sym_link; |
| 1217 | debug_sym_link = (sym_linkS *) 0; |
| 1218 | |
| 1219 | insn.insn = m32r_cgen_assemble_insn |
| 1220 | (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); |
| 1221 | |
| 1222 | if (!insn.insn) |
| 1223 | { |
| 1224 | as_bad ("%s", errmsg); |
| 1225 | return; |
| 1226 | } |
| 1227 | |
| 1228 | #ifdef E_M32R2_ARCH |
| 1229 | if ((enable_m32rx == 1) |
| 1230 | /* FIXME: Need standard macro to perform this test. */ |
| 1231 | && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) |
| 1232 | & (1 << MACH_M32R2)) |
| 1233 | && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) |
| 1234 | & (1 << MACH_M32RX))))) |
| 1235 | { |
| 1236 | /* xgettext:c-format */ |
| 1237 | as_bad (_("instruction '%s' is for the M32R2 only"), str); |
| 1238 | return; |
| 1239 | } |
| 1240 | else if ((! enable_special |
| 1241 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
| 1242 | || (! enable_special_m32r |
| 1243 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))) |
| 1244 | #else |
| 1245 | if (! enable_special |
| 1246 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
| 1247 | #endif |
| 1248 | { |
| 1249 | /* xgettext:c-format */ |
| 1250 | as_bad (_("unknown instruction '%s'"), str); |
| 1251 | return; |
| 1252 | } |
| 1253 | else if (! enable_m32rx |
| 1254 | && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) |
| 1255 | { |
| 1256 | /* xgettext:c-format */ |
| 1257 | as_bad (_("instruction '%s' is for the M32RX only"), str); |
| 1258 | return; |
| 1259 | } |
| 1260 | |
| 1261 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) |
| 1262 | m32r_flags |= E_M32R_HAS_HIDDEN_INST; |
| 1263 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)) |
| 1264 | m32r_flags |= E_M32R_HAS_BIT_INST; |
| 1265 | if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT)) |
| 1266 | m32r_flags |= E_M32R_HAS_FLOAT_INST; |
| 1267 | |
| 1268 | if (CGEN_INSN_BITSIZE (insn.insn) == 32) |
| 1269 | { |
| 1270 | /* 32 bit insns must live on 32 bit boundaries. */ |
| 1271 | if (prev_insn.insn || seen_relaxable_p) |
| 1272 | { |
| 1273 | /* ??? If calling fill_insn too many times turns us into a memory |
| 1274 | pig, can we call a fn to assemble a nop instead of |
| 1275 | !seen_relaxable_p? */ |
| 1276 | fill_insn (0); |
| 1277 | } |
| 1278 | |
| 1279 | expand_debug_syms (insn.debug_sym_link, 2); |
| 1280 | |
| 1281 | /* Doesn't really matter what we pass for RELAX_P here. */ |
| 1282 | gas_cgen_finish_insn (insn.insn, insn.buffer, |
| 1283 | CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); |
| 1284 | } |
| 1285 | else |
| 1286 | { |
| 1287 | int on_32bit_boundary_p; |
| 1288 | int swap = FALSE; |
| 1289 | |
| 1290 | if (CGEN_INSN_BITSIZE (insn.insn) != 16) |
| 1291 | abort (); |
| 1292 | |
| 1293 | insn.orig_insn = insn.insn; |
| 1294 | |
| 1295 | /* If the previous insn was relaxable, then it may be expanded |
| 1296 | to fill the current 16 bit slot. Emit a NOP here to occupy |
| 1297 | this slot, so that we can start at optimizing at a 32 bit |
| 1298 | boundary. */ |
| 1299 | if (prev_insn.insn && seen_relaxable_p && optimize) |
| 1300 | fill_insn (0); |
| 1301 | |
| 1302 | if (enable_m32rx) |
| 1303 | { |
| 1304 | /* Get the indices of the operands of the instruction. |
| 1305 | FIXME: See assemble_parallel for notes on orig_insn. */ |
| 1306 | { |
| 1307 | CGEN_FIELDS tmp_fields; |
| 1308 | insn.insn = cgen_lookup_get_insn_operands |
| 1309 | (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, |
| 1310 | 16, insn.indices, &tmp_fields); |
| 1311 | } |
| 1312 | |
| 1313 | if (insn.insn == NULL) |
| 1314 | as_fatal (_("internal error: lookup/get operands failed")); |
| 1315 | } |
| 1316 | |
| 1317 | /* Compute whether we're on a 32 bit boundary or not. |
| 1318 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
| 1319 | on_32bit_boundary_p = prev_insn.insn == NULL; |
| 1320 | |
| 1321 | /* Change a frag to, if each insn to swap is in a different frag. |
| 1322 | It must keep only one instruction in a frag. */ |
| 1323 | if (parallel() && on_32bit_boundary_p) |
| 1324 | { |
| 1325 | frag_wane (frag_now); |
| 1326 | frag_new (0); |
| 1327 | } |
| 1328 | |
| 1329 | /* Look to see if this instruction can be combined with the |
| 1330 | previous instruction to make one, parallel, 32 bit instruction. |
| 1331 | If the previous instruction (potentially) changed the flow of |
| 1332 | program control, then it cannot be combined with the current |
| 1333 | instruction. If the current instruction is relaxable, then it |
| 1334 | might be replaced with a longer version, so we cannot combine it. |
| 1335 | Also if the output of the previous instruction is used as an |
| 1336 | input to the current instruction then it cannot be combined. |
| 1337 | Otherwise call can_make_parallel() with both orderings of the |
| 1338 | instructions to see if they can be combined. */ |
| 1339 | if (! on_32bit_boundary_p |
| 1340 | && parallel () |
| 1341 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 |
| 1342 | && ! writes_to_pc (&prev_insn) |
| 1343 | && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE)) |
| 1344 | { |
| 1345 | if (can_make_parallel (&prev_insn, &insn) == NULL) |
| 1346 | make_parallel (insn.buffer); |
| 1347 | else if (can_make_parallel (&insn, &prev_insn) == NULL) |
| 1348 | swap = TRUE; |
| 1349 | } |
| 1350 | |
| 1351 | expand_debug_syms (insn.debug_sym_link, 1); |
| 1352 | |
| 1353 | { |
| 1354 | int i; |
| 1355 | finished_insnS fi; |
| 1356 | |
| 1357 | /* Ensure each pair of 16 bit insns is in the same frag. */ |
| 1358 | frag_grow (4); |
| 1359 | |
| 1360 | gas_cgen_finish_insn (insn.orig_insn, insn.buffer, |
| 1361 | CGEN_FIELDS_BITSIZE (&insn.fields), |
| 1362 | 1 /* relax_p */, &fi); |
| 1363 | insn.addr = fi.addr; |
| 1364 | insn.frag = fi.frag; |
| 1365 | insn.num_fixups = fi.num_fixups; |
| 1366 | for (i = 0; i < fi.num_fixups; ++i) |
| 1367 | insn.fixups[i] = fi.fixups[i]; |
| 1368 | } |
| 1369 | |
| 1370 | if (swap) |
| 1371 | { |
| 1372 | int i, tmp; |
| 1373 | |
| 1374 | #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp |
| 1375 | |
| 1376 | /* Swap the two insns */ |
| 1377 | SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); |
| 1378 | SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); |
| 1379 | |
| 1380 | target_make_parallel (insn.addr); |
| 1381 | |
| 1382 | /* Swap any relaxable frags recorded for the two insns. */ |
| 1383 | /* FIXME: Clarify. relaxation precludes parallel insns */ |
| 1384 | if (prev_insn.frag->fr_opcode == prev_insn.addr) |
| 1385 | prev_insn.frag->fr_opcode = insn.addr; |
| 1386 | else if (insn.frag->fr_opcode == insn.addr) |
| 1387 | insn.frag->fr_opcode = prev_insn.addr; |
| 1388 | |
| 1389 | /* Change a frag to, if each insn is in a different frag. |
| 1390 | It must keep only one instruction in a frag. */ |
| 1391 | if (prev_insn.frag != insn.frag) |
| 1392 | { |
| 1393 | for (i = 0; i < prev_insn.num_fixups; ++i) |
| 1394 | prev_insn.fixups[i]->fx_frag = insn.frag; |
| 1395 | for (i = 0; i < insn.num_fixups; ++i) |
| 1396 | insn.fixups[i]->fx_frag = prev_insn.frag; |
| 1397 | } |
| 1398 | else |
| 1399 | { |
| 1400 | /* Update the addresses in any fixups. |
| 1401 | Note that we don't have to handle the case where each insn is in |
| 1402 | a different frag as we ensure they're in the same frag above. */ |
| 1403 | for (i = 0; i < prev_insn.num_fixups; ++i) |
| 1404 | prev_insn.fixups[i]->fx_where += 2; |
| 1405 | for (i = 0; i < insn.num_fixups; ++i) |
| 1406 | insn.fixups[i]->fx_where -= 2; |
| 1407 | } |
| 1408 | } |
| 1409 | |
| 1410 | /* Keep track of whether we've seen a pair of 16 bit insns. |
| 1411 | prev_insn.insn is NULL when we're on a 32 bit boundary. */ |
| 1412 | if (on_32bit_boundary_p) |
| 1413 | prev_insn = insn; |
| 1414 | else |
| 1415 | prev_insn.insn = NULL; |
| 1416 | |
| 1417 | /* If the insn needs the following one to be on a 32 bit boundary |
| 1418 | (e.g. subroutine calls), fill this insn's slot. */ |
| 1419 | if (on_32bit_boundary_p |
| 1420 | && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) |
| 1421 | fill_insn (0); |
| 1422 | |
| 1423 | /* If this is a relaxable insn (can be replaced with a larger version) |
| 1424 | mark the fact so that we can emit an alignment directive for a |
| 1425 | following 32 bit insn if we see one. */ |
| 1426 | if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) |
| 1427 | seen_relaxable_p = 1; |
| 1428 | } |
| 1429 | |
| 1430 | /* Set these so m32r_fill_insn can use them. */ |
| 1431 | prev_seg = now_seg; |
| 1432 | prev_subseg = now_subseg; |
| 1433 | } |
| 1434 | |
| 1435 | /* The syntax in the manual says constants begin with '#'. |
| 1436 | We just ignore it. */ |
| 1437 | |
| 1438 | void |
| 1439 | md_operand (expressionS *expressionP) |
| 1440 | { |
| 1441 | if (*input_line_pointer == '#') |
| 1442 | { |
| 1443 | input_line_pointer++; |
| 1444 | expression (expressionP); |
| 1445 | } |
| 1446 | } |
| 1447 | |
| 1448 | valueT |
| 1449 | md_section_align (segT segment, valueT size) |
| 1450 | { |
| 1451 | int align = bfd_get_section_alignment (stdoutput, segment); |
| 1452 | |
| 1453 | return ((size + (1 << align) - 1) & -(1 << align)); |
| 1454 | } |
| 1455 | |
| 1456 | symbolS * |
| 1457 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
| 1458 | { |
| 1459 | return 0; |
| 1460 | } |
| 1461 | \f |
| 1462 | /* .scomm pseudo-op handler. |
| 1463 | |
| 1464 | This is a new pseudo-op to handle putting objects in .scommon. |
| 1465 | By doing this the linker won't need to do any work, |
| 1466 | and more importantly it removes the implicit -G arg necessary to |
| 1467 | correctly link the object file. */ |
| 1468 | |
| 1469 | static void |
| 1470 | m32r_scomm (int ignore ATTRIBUTE_UNUSED) |
| 1471 | { |
| 1472 | char *name; |
| 1473 | char c; |
| 1474 | char *p; |
| 1475 | offsetT size; |
| 1476 | symbolS *symbolP; |
| 1477 | offsetT align; |
| 1478 | int align2; |
| 1479 | |
| 1480 | c = get_symbol_name (&name); |
| 1481 | |
| 1482 | /* Just after name is now '\0'. */ |
| 1483 | p = input_line_pointer; |
| 1484 | *p = c; |
| 1485 | SKIP_WHITESPACE_AFTER_NAME (); |
| 1486 | if (*input_line_pointer != ',') |
| 1487 | { |
| 1488 | as_bad (_("Expected comma after symbol-name: rest of line ignored.")); |
| 1489 | ignore_rest_of_line (); |
| 1490 | return; |
| 1491 | } |
| 1492 | |
| 1493 | /* Skip ','. */ |
| 1494 | input_line_pointer++; |
| 1495 | if ((size = get_absolute_expression ()) < 0) |
| 1496 | { |
| 1497 | /* xgettext:c-format */ |
| 1498 | as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); |
| 1499 | ignore_rest_of_line (); |
| 1500 | return; |
| 1501 | } |
| 1502 | |
| 1503 | /* The third argument to .scomm is the alignment. */ |
| 1504 | if (*input_line_pointer != ',') |
| 1505 | align = 8; |
| 1506 | else |
| 1507 | { |
| 1508 | ++input_line_pointer; |
| 1509 | align = get_absolute_expression (); |
| 1510 | if (align <= 0) |
| 1511 | { |
| 1512 | as_warn (_("ignoring bad alignment")); |
| 1513 | align = 8; |
| 1514 | } |
| 1515 | } |
| 1516 | |
| 1517 | /* Convert to a power of 2 alignment. */ |
| 1518 | if (align) |
| 1519 | { |
| 1520 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) |
| 1521 | continue; |
| 1522 | if (align != 1) |
| 1523 | { |
| 1524 | as_bad (_("Common alignment not a power of 2")); |
| 1525 | ignore_rest_of_line (); |
| 1526 | return; |
| 1527 | } |
| 1528 | } |
| 1529 | else |
| 1530 | align2 = 0; |
| 1531 | |
| 1532 | *p = 0; |
| 1533 | symbolP = symbol_find_or_make (name); |
| 1534 | *p = c; |
| 1535 | |
| 1536 | if (S_IS_DEFINED (symbolP)) |
| 1537 | { |
| 1538 | /* xgettext:c-format */ |
| 1539 | as_bad (_("Ignoring attempt to re-define symbol `%s'."), |
| 1540 | S_GET_NAME (symbolP)); |
| 1541 | ignore_rest_of_line (); |
| 1542 | return; |
| 1543 | } |
| 1544 | |
| 1545 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) |
| 1546 | { |
| 1547 | /* xgettext:c-format */ |
| 1548 | as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), |
| 1549 | S_GET_NAME (symbolP), |
| 1550 | (long) S_GET_VALUE (symbolP), |
| 1551 | (long) size); |
| 1552 | |
| 1553 | ignore_rest_of_line (); |
| 1554 | return; |
| 1555 | } |
| 1556 | |
| 1557 | if (symbol_get_obj (symbolP)->local) |
| 1558 | { |
| 1559 | segT old_sec = now_seg; |
| 1560 | int old_subsec = now_subseg; |
| 1561 | char *pfrag; |
| 1562 | |
| 1563 | record_alignment (sbss_section, align2); |
| 1564 | subseg_set (sbss_section, 0); |
| 1565 | |
| 1566 | if (align2) |
| 1567 | frag_align (align2, 0, 0); |
| 1568 | |
| 1569 | if (S_GET_SEGMENT (symbolP) == sbss_section) |
| 1570 | symbol_get_frag (symbolP)->fr_symbol = 0; |
| 1571 | |
| 1572 | symbol_set_frag (symbolP, frag_now); |
| 1573 | |
| 1574 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
| 1575 | (char *) 0); |
| 1576 | *pfrag = 0; |
| 1577 | S_SET_SIZE (symbolP, size); |
| 1578 | S_SET_SEGMENT (symbolP, sbss_section); |
| 1579 | S_CLEAR_EXTERNAL (symbolP); |
| 1580 | subseg_set (old_sec, old_subsec); |
| 1581 | } |
| 1582 | else |
| 1583 | { |
| 1584 | S_SET_VALUE (symbolP, (valueT) size); |
| 1585 | S_SET_ALIGN (symbolP, align2); |
| 1586 | S_SET_EXTERNAL (symbolP); |
| 1587 | S_SET_SEGMENT (symbolP, &scom_section); |
| 1588 | } |
| 1589 | |
| 1590 | demand_empty_rest_of_line (); |
| 1591 | } |
| 1592 | |
| 1593 | /* The target specific pseudo-ops which we support. */ |
| 1594 | const pseudo_typeS md_pseudo_table[] = |
| 1595 | { |
| 1596 | { "word", cons, 4 }, |
| 1597 | { "fillinsn", fill_insn, 0 }, |
| 1598 | { "scomm", m32r_scomm, 0 }, |
| 1599 | { "debugsym", debug_sym, 0 }, |
| 1600 | { "m32r", allow_m32rx, 0 }, |
| 1601 | { "m32rx", allow_m32rx, 1 }, |
| 1602 | { "m32r2", allow_m32rx, 2 }, |
| 1603 | { "little", little, 1 }, |
| 1604 | { "big", little, 0 }, |
| 1605 | { NULL, NULL, 0 } |
| 1606 | }; |
| 1607 | \f |
| 1608 | /* Interface to relax_segment. */ |
| 1609 | |
| 1610 | /* FIXME: Build table by hand, get it working, then machine generate. */ |
| 1611 | |
| 1612 | const relax_typeS md_relax_table[] = |
| 1613 | { |
| 1614 | /* The fields are: |
| 1615 | 1) most positive reach of this state, |
| 1616 | 2) most negative reach of this state, |
| 1617 | 3) how many bytes this mode will add to the size of the current frag |
| 1618 | 4) which index into the table to try if we can't fit into this one. */ |
| 1619 | |
| 1620 | /* The first entry must be unused because an `rlx_more' value of zero ends |
| 1621 | each list. */ |
| 1622 | {1, 1, 0, 0}, |
| 1623 | |
| 1624 | /* The displacement used by GAS is from the end of the 2 byte insn, |
| 1625 | so we subtract 2 from the following. */ |
| 1626 | /* 16 bit insn, 8 bit disp -> 10 bit range. |
| 1627 | This doesn't handle a branch in the right slot at the border: |
| 1628 | the "& -4" isn't taken into account. It's not important enough to |
| 1629 | complicate things over it, so we subtract an extra 2 (or + 2 in -ve |
| 1630 | case). */ |
| 1631 | {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, |
| 1632 | /* 32 bit insn, 24 bit disp -> 26 bit range. */ |
| 1633 | {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, |
| 1634 | /* Same thing, but with leading nop for alignment. */ |
| 1635 | {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } |
| 1636 | }; |
| 1637 | |
| 1638 | long |
| 1639 | m32r_relax_frag (segT segment, fragS *fragP, long stretch) |
| 1640 | { |
| 1641 | /* Address of branch insn. */ |
| 1642 | long address = fragP->fr_address + fragP->fr_fix - 2; |
| 1643 | long growth = 0; |
| 1644 | |
| 1645 | /* Keep 32 bit insns aligned on 32 bit boundaries. */ |
| 1646 | if (fragP->fr_subtype == 2) |
| 1647 | { |
| 1648 | if ((address & 3) != 0) |
| 1649 | { |
| 1650 | fragP->fr_subtype = 3; |
| 1651 | growth = 2; |
| 1652 | } |
| 1653 | } |
| 1654 | else if (fragP->fr_subtype == 3) |
| 1655 | { |
| 1656 | if ((address & 3) == 0) |
| 1657 | { |
| 1658 | fragP->fr_subtype = 2; |
| 1659 | growth = -2; |
| 1660 | } |
| 1661 | } |
| 1662 | else |
| 1663 | { |
| 1664 | growth = relax_frag (segment, fragP, stretch); |
| 1665 | |
| 1666 | /* Long jump on odd halfword boundary? */ |
| 1667 | if (fragP->fr_subtype == 2 && (address & 3) != 0) |
| 1668 | { |
| 1669 | fragP->fr_subtype = 3; |
| 1670 | growth += 2; |
| 1671 | } |
| 1672 | } |
| 1673 | |
| 1674 | return growth; |
| 1675 | } |
| 1676 | |
| 1677 | /* Return an initial guess of the length by which a fragment must grow to |
| 1678 | hold a branch to reach its destination. |
| 1679 | Also updates fr_type/fr_subtype as necessary. |
| 1680 | |
| 1681 | Called just before doing relaxation. |
| 1682 | Any symbol that is now undefined will not become defined. |
| 1683 | The guess for fr_var is ACTUALLY the growth beyond fr_fix. |
| 1684 | Whatever we do to grow fr_fix or fr_var contributes to our returned value. |
| 1685 | Although it may not be explicit in the frag, pretend fr_var starts |
| 1686 | with a 0 value. */ |
| 1687 | |
| 1688 | int |
| 1689 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
| 1690 | { |
| 1691 | /* The only thing we have to handle here are symbols outside of the |
| 1692 | current segment. They may be undefined or in a different segment in |
| 1693 | which case linker scripts may place them anywhere. |
| 1694 | However, we can't finish the fragment here and emit the reloc as insn |
| 1695 | alignment requirements may move the insn about. */ |
| 1696 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
| 1697 | || S_IS_EXTERNAL (fragP->fr_symbol) |
| 1698 | || S_IS_WEAK (fragP->fr_symbol)) |
| 1699 | { |
| 1700 | /* The symbol is undefined in this segment. |
| 1701 | Change the relaxation subtype to the max allowable and leave |
| 1702 | all further handling to md_convert_frag. */ |
| 1703 | fragP->fr_subtype = 2; |
| 1704 | |
| 1705 | { |
| 1706 | const CGEN_INSN *insn; |
| 1707 | int i; |
| 1708 | |
| 1709 | /* Update the recorded insn. |
| 1710 | Fortunately we don't have to look very far. |
| 1711 | FIXME: Change this to record in the instruction the next higher |
| 1712 | relaxable insn to use. */ |
| 1713 | for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) |
| 1714 | { |
| 1715 | if ((strcmp (CGEN_INSN_MNEMONIC (insn), |
| 1716 | CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) |
| 1717 | == 0) |
| 1718 | && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) |
| 1719 | break; |
| 1720 | } |
| 1721 | if (i == 4) |
| 1722 | abort (); |
| 1723 | |
| 1724 | fragP->fr_cgen.insn = insn; |
| 1725 | return 2; |
| 1726 | } |
| 1727 | } |
| 1728 | |
| 1729 | return md_relax_table[fragP->fr_subtype].rlx_length; |
| 1730 | } |
| 1731 | |
| 1732 | /* *FRAGP has been relaxed to its final size, and now needs to have |
| 1733 | the bytes inside it modified to conform to the new size. |
| 1734 | |
| 1735 | Called after relaxation is finished. |
| 1736 | fragP->fr_type == rs_machine_dependent. |
| 1737 | fragP->fr_subtype is the subtype of what the address relaxed to. */ |
| 1738 | |
| 1739 | void |
| 1740 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
| 1741 | segT sec, |
| 1742 | fragS *fragP) |
| 1743 | { |
| 1744 | char *opcode; |
| 1745 | char *displacement; |
| 1746 | int target_address; |
| 1747 | int opcode_address; |
| 1748 | int extension; |
| 1749 | int addend; |
| 1750 | |
| 1751 | opcode = fragP->fr_opcode; |
| 1752 | |
| 1753 | /* Address opcode resides at in file space. */ |
| 1754 | opcode_address = fragP->fr_address + fragP->fr_fix - 2; |
| 1755 | |
| 1756 | switch (fragP->fr_subtype) |
| 1757 | { |
| 1758 | case 1: |
| 1759 | extension = 0; |
| 1760 | displacement = &opcode[1]; |
| 1761 | break; |
| 1762 | case 2: |
| 1763 | opcode[0] |= 0x80; |
| 1764 | extension = 2; |
| 1765 | displacement = &opcode[1]; |
| 1766 | break; |
| 1767 | case 3: |
| 1768 | opcode[2] = opcode[0] | 0x80; |
| 1769 | md_number_to_chars (opcode, PAR_NOP_INSN, 2); |
| 1770 | opcode_address += 2; |
| 1771 | extension = 4; |
| 1772 | displacement = &opcode[3]; |
| 1773 | break; |
| 1774 | default: |
| 1775 | abort (); |
| 1776 | } |
| 1777 | |
| 1778 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
| 1779 | || S_IS_EXTERNAL (fragP->fr_symbol) |
| 1780 | || S_IS_WEAK (fragP->fr_symbol)) |
| 1781 | { |
| 1782 | /* Symbol must be resolved by linker. */ |
| 1783 | if (fragP->fr_offset & 3) |
| 1784 | as_warn (_("Addend to unresolved symbol not on word boundary.")); |
| 1785 | #ifdef USE_M32R_OLD_RELOC |
| 1786 | addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */ |
| 1787 | #else |
| 1788 | addend = 0; |
| 1789 | #endif |
| 1790 | } |
| 1791 | else |
| 1792 | { |
| 1793 | /* Address we want to reach in file space. */ |
| 1794 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
| 1795 | addend = (target_address - (opcode_address & -4)) >> 2; |
| 1796 | } |
| 1797 | |
| 1798 | /* Create a relocation for symbols that must be resolved by the linker. |
| 1799 | Otherwise output the completed insn. */ |
| 1800 | |
| 1801 | if (S_GET_SEGMENT (fragP->fr_symbol) != sec |
| 1802 | || S_IS_EXTERNAL (fragP->fr_symbol) |
| 1803 | || S_IS_WEAK (fragP->fr_symbol)) |
| 1804 | { |
| 1805 | fixS *fixP; |
| 1806 | |
| 1807 | gas_assert (fragP->fr_subtype != 1); |
| 1808 | gas_assert (fragP->fr_cgen.insn != 0); |
| 1809 | |
| 1810 | fixP = gas_cgen_record_fixup (fragP, |
| 1811 | /* Offset of branch insn in frag. */ |
| 1812 | fragP->fr_fix + extension - 4, |
| 1813 | fragP->fr_cgen.insn, |
| 1814 | 4 /* Length. */, |
| 1815 | /* FIXME: quick hack. */ |
| 1816 | cgen_operand_lookup_by_num (gas_cgen_cpu_desc, |
| 1817 | M32R_OPERAND_DISP24), |
| 1818 | fragP->fr_cgen.opinfo, |
| 1819 | fragP->fr_symbol, fragP->fr_offset); |
| 1820 | if (fragP->fr_cgen.opinfo) |
| 1821 | fixP->fx_r_type = fragP->fr_cgen.opinfo; |
| 1822 | } |
| 1823 | |
| 1824 | #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) |
| 1825 | |
| 1826 | md_number_to_chars (displacement, (valueT) addend, |
| 1827 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
| 1828 | |
| 1829 | fragP->fr_fix += extension; |
| 1830 | } |
| 1831 | \f |
| 1832 | /* Functions concerning relocs. */ |
| 1833 | |
| 1834 | /* The location from which a PC relative jump should be calculated, |
| 1835 | given a PC relative reloc. */ |
| 1836 | |
| 1837 | long |
| 1838 | md_pcrel_from_section (fixS *fixP, segT sec) |
| 1839 | { |
| 1840 | if (fixP->fx_addsy != (symbolS *) NULL |
| 1841 | && (! S_IS_DEFINED (fixP->fx_addsy) |
| 1842 | || S_GET_SEGMENT (fixP->fx_addsy) != sec |
| 1843 | || S_IS_EXTERNAL (fixP->fx_addsy) |
| 1844 | || S_IS_WEAK (fixP->fx_addsy))) |
| 1845 | { |
| 1846 | if (S_GET_SEGMENT (fixP->fx_addsy) != sec |
| 1847 | && S_IS_DEFINED (fixP->fx_addsy) |
| 1848 | && ! S_IS_EXTERNAL (fixP->fx_addsy) |
| 1849 | && ! S_IS_WEAK (fixP->fx_addsy)) |
| 1850 | return fixP->fx_offset; |
| 1851 | |
| 1852 | /* The symbol is undefined (or is defined but not in this section). |
| 1853 | Let the linker figure it out. */ |
| 1854 | return 0; |
| 1855 | } |
| 1856 | |
| 1857 | return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; |
| 1858 | } |
| 1859 | |
| 1860 | /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. |
| 1861 | Returns BFD_RELOC_NONE if no reloc type can be found. |
| 1862 | *FIXP may be modified if desired. */ |
| 1863 | |
| 1864 | bfd_reloc_code_real_type |
| 1865 | md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, |
| 1866 | const CGEN_OPERAND *operand, |
| 1867 | fixS *fixP) |
| 1868 | { |
| 1869 | switch (operand->type) |
| 1870 | { |
| 1871 | case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; |
| 1872 | case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; |
| 1873 | case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; |
| 1874 | case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; |
| 1875 | case M32R_OPERAND_HI16: |
| 1876 | case M32R_OPERAND_SLO16: |
| 1877 | case M32R_OPERAND_ULO16: |
| 1878 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
| 1879 | if (fixP->fx_cgen.opinfo != 0) |
| 1880 | return fixP->fx_cgen.opinfo; |
| 1881 | break; |
| 1882 | default: |
| 1883 | /* Avoid -Wall warning. */ |
| 1884 | break; |
| 1885 | } |
| 1886 | return BFD_RELOC_NONE; |
| 1887 | } |
| 1888 | |
| 1889 | /* Record a HI16 reloc for later matching with its LO16 cousin. */ |
| 1890 | |
| 1891 | static void |
| 1892 | m32r_record_hi16 (int reloc_type, |
| 1893 | fixS *fixP, |
| 1894 | segT seg ATTRIBUTE_UNUSED) |
| 1895 | { |
| 1896 | struct m32r_hi_fixup *hi_fixup; |
| 1897 | |
| 1898 | gas_assert (reloc_type == BFD_RELOC_M32R_HI16_SLO |
| 1899 | || reloc_type == BFD_RELOC_M32R_HI16_ULO); |
| 1900 | |
| 1901 | hi_fixup = xmalloc (sizeof (* hi_fixup)); |
| 1902 | hi_fixup->fixp = fixP; |
| 1903 | hi_fixup->seg = now_seg; |
| 1904 | hi_fixup->next = m32r_hi_fixup_list; |
| 1905 | |
| 1906 | m32r_hi_fixup_list = hi_fixup; |
| 1907 | } |
| 1908 | |
| 1909 | /* Called while parsing an instruction to create a fixup. |
| 1910 | We need to check for HI16 relocs and queue them up for later sorting. */ |
| 1911 | |
| 1912 | fixS * |
| 1913 | m32r_cgen_record_fixup_exp (fragS *frag, |
| 1914 | int where, |
| 1915 | const CGEN_INSN *insn, |
| 1916 | int length, |
| 1917 | const CGEN_OPERAND *operand, |
| 1918 | int opinfo, |
| 1919 | expressionS *exp) |
| 1920 | { |
| 1921 | fixS *fixP; |
| 1922 | bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED; |
| 1923 | |
| 1924 | if (m32r_check_fixup (exp, &r_type)) |
| 1925 | as_bad (_("Invalid PIC expression.")); |
| 1926 | |
| 1927 | fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, |
| 1928 | operand, opinfo, exp); |
| 1929 | |
| 1930 | switch (operand->type) |
| 1931 | { |
| 1932 | case M32R_OPERAND_HI16: |
| 1933 | /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ |
| 1934 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO |
| 1935 | || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) |
| 1936 | m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); |
| 1937 | break; |
| 1938 | |
| 1939 | default: |
| 1940 | /* Avoid -Wall warning. */ |
| 1941 | break; |
| 1942 | } |
| 1943 | |
| 1944 | switch (r_type) |
| 1945 | { |
| 1946 | case BFD_RELOC_UNUSED: |
| 1947 | default: |
| 1948 | return fixP; |
| 1949 | |
| 1950 | case BFD_RELOC_M32R_GOTPC24: |
| 1951 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) |
| 1952 | r_type = BFD_RELOC_M32R_GOTPC_HI_SLO; |
| 1953 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) |
| 1954 | r_type = BFD_RELOC_M32R_GOTPC_HI_ULO; |
| 1955 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) |
| 1956 | r_type = BFD_RELOC_M32R_GOTPC_LO; |
| 1957 | break; |
| 1958 | |
| 1959 | case BFD_RELOC_M32R_GOT24: |
| 1960 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) |
| 1961 | r_type = BFD_RELOC_M32R_GOT16_HI_SLO; |
| 1962 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) |
| 1963 | r_type = BFD_RELOC_M32R_GOT16_HI_ULO; |
| 1964 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) |
| 1965 | r_type = BFD_RELOC_M32R_GOT16_LO; |
| 1966 | break; |
| 1967 | |
| 1968 | case BFD_RELOC_M32R_GOTOFF: |
| 1969 | if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO) |
| 1970 | r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO; |
| 1971 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) |
| 1972 | r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO; |
| 1973 | else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16) |
| 1974 | r_type = BFD_RELOC_M32R_GOTOFF_LO; |
| 1975 | break; |
| 1976 | |
| 1977 | case BFD_RELOC_M32R_26_PLTREL: |
| 1978 | as_bad (_("Invalid PIC expression.")); |
| 1979 | break; |
| 1980 | } |
| 1981 | |
| 1982 | fixP->fx_r_type = r_type; |
| 1983 | |
| 1984 | return fixP; |
| 1985 | } |
| 1986 | |
| 1987 | /* Return BFD reloc type from opinfo field in a fixS. |
| 1988 | It's tricky using fx_r_type in m32r_frob_file because the values |
| 1989 | are BFD_RELOC_UNUSED + operand number. */ |
| 1990 | #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) |
| 1991 | |
| 1992 | /* Sort any unmatched HI16 relocs so that they immediately precede |
| 1993 | the corresponding LO16 reloc. This is called before md_apply_fix and |
| 1994 | tc_gen_reloc. */ |
| 1995 | |
| 1996 | void |
| 1997 | m32r_frob_file (void) |
| 1998 | { |
| 1999 | struct m32r_hi_fixup *l; |
| 2000 | |
| 2001 | for (l = m32r_hi_fixup_list; l != NULL; l = l->next) |
| 2002 | { |
| 2003 | segment_info_type *seginfo; |
| 2004 | int pass; |
| 2005 | |
| 2006 | gas_assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO |
| 2007 | || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); |
| 2008 | |
| 2009 | /* Check quickly whether the next fixup happens to be a matching low. */ |
| 2010 | if (l->fixp->fx_next != NULL |
| 2011 | && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 |
| 2012 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy |
| 2013 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) |
| 2014 | continue; |
| 2015 | |
| 2016 | /* Look through the fixups for this segment for a matching `low'. |
| 2017 | When we find one, move the high/shigh just in front of it. We do |
| 2018 | this in two passes. In the first pass, we try to find a |
| 2019 | unique `low'. In the second pass, we permit multiple high's |
| 2020 | relocs for a single `low'. */ |
| 2021 | seginfo = seg_info (l->seg); |
| 2022 | for (pass = 0; pass < 2; pass++) |
| 2023 | { |
| 2024 | fixS *f; |
| 2025 | fixS *prev; |
| 2026 | |
| 2027 | prev = NULL; |
| 2028 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) |
| 2029 | { |
| 2030 | /* Check whether this is a `low' fixup which matches l->fixp. */ |
| 2031 | if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 |
| 2032 | && f->fx_addsy == l->fixp->fx_addsy |
| 2033 | && f->fx_offset == l->fixp->fx_offset |
| 2034 | && (pass == 1 |
| 2035 | || prev == NULL |
| 2036 | || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO |
| 2037 | && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) |
| 2038 | || prev->fx_addsy != f->fx_addsy |
| 2039 | || prev->fx_offset != f->fx_offset)) |
| 2040 | { |
| 2041 | fixS **pf; |
| 2042 | |
| 2043 | /* Move l->fixp before f. */ |
| 2044 | for (pf = &seginfo->fix_root; |
| 2045 | *pf != l->fixp; |
| 2046 | pf = & (*pf)->fx_next) |
| 2047 | gas_assert (*pf != NULL); |
| 2048 | |
| 2049 | *pf = l->fixp->fx_next; |
| 2050 | |
| 2051 | l->fixp->fx_next = f; |
| 2052 | if (prev == NULL) |
| 2053 | seginfo->fix_root = l->fixp; |
| 2054 | else |
| 2055 | prev->fx_next = l->fixp; |
| 2056 | |
| 2057 | break; |
| 2058 | } |
| 2059 | |
| 2060 | prev = f; |
| 2061 | } |
| 2062 | |
| 2063 | if (f != NULL) |
| 2064 | break; |
| 2065 | |
| 2066 | if (pass == 1 |
| 2067 | && warn_unmatched_high) |
| 2068 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, |
| 2069 | _("Unmatched high/shigh reloc")); |
| 2070 | } |
| 2071 | } |
| 2072 | } |
| 2073 | |
| 2074 | /* See whether we need to force a relocation into the output file. |
| 2075 | This is used to force out switch and PC relative relocations when |
| 2076 | relaxing. */ |
| 2077 | |
| 2078 | int |
| 2079 | m32r_force_relocation (fixS *fix) |
| 2080 | { |
| 2081 | if (generic_force_reloc (fix)) |
| 2082 | return 1; |
| 2083 | |
| 2084 | if (! m32r_relax) |
| 2085 | return 0; |
| 2086 | |
| 2087 | return fix->fx_pcrel; |
| 2088 | } |
| 2089 | \f |
| 2090 | /* Write a value out to the object file, using the appropriate endianness. */ |
| 2091 | |
| 2092 | void |
| 2093 | md_number_to_chars (char *buf, valueT val, int n) |
| 2094 | { |
| 2095 | if (target_big_endian) |
| 2096 | number_to_chars_bigendian (buf, val, n); |
| 2097 | else |
| 2098 | number_to_chars_littleendian (buf, val, n); |
| 2099 | } |
| 2100 | |
| 2101 | /* Turn a string in input_line_pointer into a floating point constant |
| 2102 | of type TYPE, and store the appropriate bytes in *LITP. The number |
| 2103 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
| 2104 | returned, or NULL on OK. */ |
| 2105 | |
| 2106 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
| 2107 | #define MAX_LITTLENUMS 6 |
| 2108 | |
| 2109 | char * |
| 2110 | md_atof (int type, char *litP, int *sizeP) |
| 2111 | { |
| 2112 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
| 2113 | } |
| 2114 | |
| 2115 | void |
| 2116 | m32r_elf_section_change_hook (void) |
| 2117 | { |
| 2118 | /* If we have reached the end of a section and we have just emitted a |
| 2119 | 16 bit insn, then emit a nop to make sure that the section ends on |
| 2120 | a 32 bit boundary. */ |
| 2121 | |
| 2122 | if (prev_insn.insn || seen_relaxable_p) |
| 2123 | (void) m32r_fill_insn (0); |
| 2124 | } |
| 2125 | |
| 2126 | /* Return true if can adjust the reloc to be relative to its section |
| 2127 | (such as .data) instead of relative to some symbol. */ |
| 2128 | |
| 2129 | bfd_boolean |
| 2130 | m32r_fix_adjustable (fixS *fixP) |
| 2131 | { |
| 2132 | bfd_reloc_code_real_type reloc_type; |
| 2133 | |
| 2134 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
| 2135 | { |
| 2136 | const CGEN_INSN *insn = NULL; |
| 2137 | int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; |
| 2138 | const CGEN_OPERAND *operand = |
| 2139 | cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); |
| 2140 | |
| 2141 | reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); |
| 2142 | } |
| 2143 | else |
| 2144 | reloc_type = fixP->fx_r_type; |
| 2145 | |
| 2146 | if (fixP->fx_addsy == NULL) |
| 2147 | return 1; |
| 2148 | |
| 2149 | /* Prevent all adjustments to global symbols. */ |
| 2150 | if (S_IS_EXTERNAL (fixP->fx_addsy)) |
| 2151 | return 0; |
| 2152 | if (S_IS_WEAK (fixP->fx_addsy)) |
| 2153 | return 0; |
| 2154 | |
| 2155 | if (pic_code |
| 2156 | && (reloc_type == BFD_RELOC_M32R_24 |
| 2157 | || reloc_type == BFD_RELOC_M32R_26_PCREL |
| 2158 | || reloc_type == BFD_RELOC_M32R_HI16_SLO |
| 2159 | || reloc_type == BFD_RELOC_M32R_HI16_ULO |
| 2160 | || reloc_type == BFD_RELOC_M32R_LO16)) |
| 2161 | return 0; |
| 2162 | |
| 2163 | if (reloc_type == BFD_RELOC_M32R_GOT24 |
| 2164 | || reloc_type == BFD_RELOC_M32R_26_PLTREL |
| 2165 | || reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO |
| 2166 | || reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO |
| 2167 | || reloc_type == BFD_RELOC_M32R_GOTPC_LO |
| 2168 | || reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO |
| 2169 | || reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO |
| 2170 | || reloc_type == BFD_RELOC_M32R_GOT16_LO) |
| 2171 | return 0; |
| 2172 | |
| 2173 | /* We need the symbol name for the VTABLE entries. */ |
| 2174 | if (reloc_type == BFD_RELOC_VTABLE_INHERIT |
| 2175 | || reloc_type == BFD_RELOC_VTABLE_ENTRY) |
| 2176 | return 0; |
| 2177 | |
| 2178 | return 1; |
| 2179 | } |
| 2180 | |
| 2181 | void |
| 2182 | m32r_elf_final_processing (void) |
| 2183 | { |
| 2184 | if (use_parallel) |
| 2185 | m32r_flags |= E_M32R_HAS_PARALLEL; |
| 2186 | elf_elfheader (stdoutput)->e_flags |= m32r_flags; |
| 2187 | } |
| 2188 | |
| 2189 | /* Translate internal representation of relocation info to BFD target |
| 2190 | format. */ |
| 2191 | |
| 2192 | arelent * |
| 2193 | tc_gen_reloc (asection * section, fixS * fixP) |
| 2194 | { |
| 2195 | arelent * reloc; |
| 2196 | bfd_reloc_code_real_type code; |
| 2197 | |
| 2198 | reloc = xmalloc (sizeof (* reloc)); |
| 2199 | |
| 2200 | reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); |
| 2201 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); |
| 2202 | reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; |
| 2203 | |
| 2204 | if (fixP->fx_pcrel) |
| 2205 | { |
| 2206 | if (fixP->fx_r_type == BFD_RELOC_32) |
| 2207 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
| 2208 | else if (fixP->fx_r_type == BFD_RELOC_16) |
| 2209 | { |
| 2210 | fixP->fx_r_type = BFD_RELOC_16_PCREL; |
| 2211 | bfd_set_error (bfd_error_bad_value); |
| 2212 | } |
| 2213 | } |
| 2214 | |
| 2215 | code = fixP->fx_r_type; |
| 2216 | if (pic_code) |
| 2217 | { |
| 2218 | #ifdef DEBUG_PIC |
| 2219 | printf("%s",bfd_get_reloc_code_name(code)); |
| 2220 | #endif |
| 2221 | switch (code) |
| 2222 | { |
| 2223 | case BFD_RELOC_M32R_26_PCREL: |
| 2224 | code = BFD_RELOC_M32R_26_PLTREL; |
| 2225 | break; |
| 2226 | |
| 2227 | case BFD_RELOC_M32R_24: |
| 2228 | if (fixP->fx_addsy != NULL |
| 2229 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) |
| 2230 | code = BFD_RELOC_M32R_GOTPC24; |
| 2231 | else |
| 2232 | code = BFD_RELOC_M32R_GOT24; |
| 2233 | break; |
| 2234 | |
| 2235 | case BFD_RELOC_M32R_HI16_ULO: |
| 2236 | if (fixP->fx_addsy != NULL |
| 2237 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) |
| 2238 | code = BFD_RELOC_M32R_GOTPC_HI_ULO; |
| 2239 | else |
| 2240 | code = BFD_RELOC_M32R_GOT16_HI_ULO; |
| 2241 | break; |
| 2242 | |
| 2243 | case BFD_RELOC_M32R_HI16_SLO: |
| 2244 | if (fixP->fx_addsy != NULL |
| 2245 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) |
| 2246 | code = BFD_RELOC_M32R_GOTPC_HI_SLO; |
| 2247 | else |
| 2248 | code = BFD_RELOC_M32R_GOT16_HI_SLO; |
| 2249 | break; |
| 2250 | |
| 2251 | case BFD_RELOC_M32R_LO16: |
| 2252 | if (fixP->fx_addsy != NULL |
| 2253 | && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) |
| 2254 | code = BFD_RELOC_M32R_GOTPC_LO; |
| 2255 | else |
| 2256 | code = BFD_RELOC_M32R_GOT16_LO; |
| 2257 | break; |
| 2258 | |
| 2259 | default: |
| 2260 | break; |
| 2261 | } |
| 2262 | #ifdef DEBUG_PIC |
| 2263 | printf(" => %s",bfd_get_reloc_code_name(code)); |
| 2264 | #endif |
| 2265 | } |
| 2266 | |
| 2267 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 2268 | |
| 2269 | #ifdef DEBUG_PIC |
| 2270 | printf(" => %s\n",reloc->howto->name); |
| 2271 | #endif |
| 2272 | |
| 2273 | if (reloc->howto == (reloc_howto_type *) NULL) |
| 2274 | { |
| 2275 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 2276 | _("internal error: can't export reloc type %d (`%s')"), |
| 2277 | fixP->fx_r_type, bfd_get_reloc_code_name (code)); |
| 2278 | return NULL; |
| 2279 | } |
| 2280 | |
| 2281 | /* Use fx_offset for these cases. */ |
| 2282 | if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
| 2283 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 2284 | || fixP->fx_r_type == BFD_RELOC_32_PCREL) |
| 2285 | reloc->addend = fixP->fx_offset; |
| 2286 | else if ((!pic_code |
| 2287 | && code != BFD_RELOC_M32R_26_PLTREL) |
| 2288 | && fixP->fx_pcrel |
| 2289 | && fixP->fx_addsy != NULL |
| 2290 | && (S_GET_SEGMENT(fixP->fx_addsy) != section) |
| 2291 | && S_IS_DEFINED (fixP->fx_addsy) |
| 2292 | && ! S_IS_EXTERNAL(fixP->fx_addsy) |
| 2293 | && ! S_IS_WEAK(fixP->fx_addsy)) |
| 2294 | /* Already used fx_offset in the opcode field itseld. */ |
| 2295 | reloc->addend = fixP->fx_offset; |
| 2296 | else |
| 2297 | reloc->addend = fixP->fx_addnumber; |
| 2298 | |
| 2299 | return reloc; |
| 2300 | } |
| 2301 | |
| 2302 | inline static char * |
| 2303 | m32r_end_of_match (char *cont, char *what) |
| 2304 | { |
| 2305 | int len = strlen (what); |
| 2306 | |
| 2307 | if (strncasecmp (cont, what, strlen (what)) == 0 |
| 2308 | && ! is_part_of_name (cont[len])) |
| 2309 | return cont + len; |
| 2310 | |
| 2311 | return NULL; |
| 2312 | } |
| 2313 | |
| 2314 | int |
| 2315 | m32r_parse_name (char const *name, |
| 2316 | expressionS *exprP, |
| 2317 | enum expr_mode mode, |
| 2318 | char *nextcharP) |
| 2319 | { |
| 2320 | char *next = input_line_pointer; |
| 2321 | char *next_end; |
| 2322 | int reloc_type; |
| 2323 | operatorT op_type; |
| 2324 | segT segment; |
| 2325 | |
| 2326 | exprP->X_op_symbol = NULL; |
| 2327 | exprP->X_md = BFD_RELOC_UNUSED; |
| 2328 | |
| 2329 | if (strcmp (name, GOT_NAME) == 0) |
| 2330 | { |
| 2331 | if (! GOT_symbol) |
| 2332 | GOT_symbol = symbol_find_or_make (name); |
| 2333 | |
| 2334 | exprP->X_add_symbol = GOT_symbol; |
| 2335 | no_suffix: |
| 2336 | /* If we have an absolute symbol or a |
| 2337 | reg, then we know its value now. */ |
| 2338 | segment = S_GET_SEGMENT (exprP->X_add_symbol); |
| 2339 | if (mode != expr_defer && segment == absolute_section) |
| 2340 | { |
| 2341 | exprP->X_op = O_constant; |
| 2342 | exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); |
| 2343 | exprP->X_add_symbol = NULL; |
| 2344 | } |
| 2345 | else if (mode != expr_defer && segment == reg_section) |
| 2346 | { |
| 2347 | exprP->X_op = O_register; |
| 2348 | exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol); |
| 2349 | exprP->X_add_symbol = NULL; |
| 2350 | } |
| 2351 | else |
| 2352 | { |
| 2353 | exprP->X_op = O_symbol; |
| 2354 | exprP->X_add_number = 0; |
| 2355 | } |
| 2356 | |
| 2357 | return 1; |
| 2358 | } |
| 2359 | |
| 2360 | exprP->X_add_symbol = symbol_find_or_make (name); |
| 2361 | |
| 2362 | if (*nextcharP != '@') |
| 2363 | goto no_suffix; |
| 2364 | else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF"))) |
| 2365 | { |
| 2366 | reloc_type = BFD_RELOC_M32R_GOTOFF; |
| 2367 | op_type = O_PIC_reloc; |
| 2368 | } |
| 2369 | else if ((next_end = m32r_end_of_match (next + 1, "GOT"))) |
| 2370 | { |
| 2371 | reloc_type = BFD_RELOC_M32R_GOT24; |
| 2372 | op_type = O_PIC_reloc; |
| 2373 | } |
| 2374 | else if ((next_end = m32r_end_of_match (next + 1, "PLT"))) |
| 2375 | { |
| 2376 | reloc_type = BFD_RELOC_M32R_26_PLTREL; |
| 2377 | op_type = O_PIC_reloc; |
| 2378 | } |
| 2379 | else |
| 2380 | goto no_suffix; |
| 2381 | |
| 2382 | *input_line_pointer = *nextcharP; |
| 2383 | input_line_pointer = next_end; |
| 2384 | *nextcharP = *input_line_pointer; |
| 2385 | *input_line_pointer = '\0'; |
| 2386 | |
| 2387 | exprP->X_op = op_type; |
| 2388 | exprP->X_add_number = 0; |
| 2389 | exprP->X_md = reloc_type; |
| 2390 | |
| 2391 | return 1; |
| 2392 | } |
| 2393 | |
| 2394 | int |
| 2395 | m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp) |
| 2396 | { |
| 2397 | if (exp->X_op == O_PIC_reloc |
| 2398 | && exp->X_md == BFD_RELOC_M32R_26_PLTREL) |
| 2399 | { |
| 2400 | exp->X_op = O_symbol; |
| 2401 | opinfo = exp->X_md; |
| 2402 | } |
| 2403 | |
| 2404 | return opinfo; |
| 2405 | } |