| 1 | /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12. |
| 2 | Copyright 1999, 2000, 2001 Free Software Foundation, Inc. |
| 3 | Written by Stephane Carrez (stcarrez@worldnet.fr) |
| 4 | |
| 5 | This file is part of GAS, the GNU Assembler. |
| 6 | |
| 7 | GAS is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | GAS is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to |
| 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | #include <stdio.h> |
| 23 | #include "as.h" |
| 24 | #include "safe-ctype.h" |
| 25 | #include "subsegs.h" |
| 26 | #include "opcode/m68hc11.h" |
| 27 | #include "dwarf2dbg.h" |
| 28 | |
| 29 | const char comment_chars[] = ";!"; |
| 30 | const char line_comment_chars[] = "#*"; |
| 31 | const char line_separator_chars[] = ""; |
| 32 | |
| 33 | const char EXP_CHARS[] = "eE"; |
| 34 | const char FLT_CHARS[] = "dD"; |
| 35 | |
| 36 | #define STATE_CONDITIONAL_BRANCH (1) |
| 37 | #define STATE_PC_RELATIVE (2) |
| 38 | #define STATE_INDEXED_OFFSET (3) |
| 39 | #define STATE_XBCC_BRANCH (4) |
| 40 | #define STATE_CONDITIONAL_BRANCH_6812 (5) |
| 41 | |
| 42 | #define STATE_BYTE (0) |
| 43 | #define STATE_BITS5 (0) |
| 44 | #define STATE_WORD (1) |
| 45 | #define STATE_BITS9 (1) |
| 46 | #define STATE_LONG (2) |
| 47 | #define STATE_BITS16 (2) |
| 48 | #define STATE_UNDF (3) /* Symbol undefined in pass1 */ |
| 49 | |
| 50 | /* This macro has no side-effects. */ |
| 51 | #define ENCODE_RELAX(what,length) (((what) << 2) + (length)) |
| 52 | #define RELAX_STATE(s) ((s) >> 2) |
| 53 | #define RELAX_LENGTH(s) ((s) & 3) |
| 54 | |
| 55 | #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF)) |
| 56 | |
| 57 | /* This table describes how you change sizes for the various types of variable |
| 58 | size expressions. This version only supports two kinds. */ |
| 59 | |
| 60 | /* The fields are: |
| 61 | How far Forward this mode will reach. |
| 62 | How far Backward this mode will reach. |
| 63 | How many bytes this mode will add to the size of the frag. |
| 64 | Which mode to go to if the offset won't fit in this one. */ |
| 65 | |
| 66 | relax_typeS md_relax_table[] = { |
| 67 | {1, 1, 0, 0}, /* First entries aren't used. */ |
| 68 | {1, 1, 0, 0}, /* For no good reason except. */ |
| 69 | {1, 1, 0, 0}, /* that the VAX doesn't either. */ |
| 70 | {1, 1, 0, 0}, |
| 71 | |
| 72 | /* Relax for bcc <L>. |
| 73 | These insns are translated into b!cc +3 jmp L. */ |
| 74 | {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD)}, |
| 75 | {0, 0, 3, 0}, |
| 76 | {1, 1, 0, 0}, |
| 77 | {1, 1, 0, 0}, |
| 78 | |
| 79 | /* Relax for bsr <L> and bra <L>. |
| 80 | These insns are translated into jsr and jmp. */ |
| 81 | {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD)}, |
| 82 | {0, 0, 1, 0}, |
| 83 | {1, 1, 0, 0}, |
| 84 | {1, 1, 0, 0}, |
| 85 | |
| 86 | /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */ |
| 87 | {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9)}, |
| 88 | {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16)}, |
| 89 | {0, 0, 2, 0}, |
| 90 | {1, 1, 0, 0}, |
| 91 | |
| 92 | /* Relax for dbeq/ibeq/tbeq r,<L>: |
| 93 | These insns are translated into db!cc +3 jmp L. */ |
| 94 | {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD)}, |
| 95 | {0, 0, 3, 0}, |
| 96 | {1, 1, 0, 0}, |
| 97 | {1, 1, 0, 0}, |
| 98 | |
| 99 | /* Relax for bcc <L> on 68HC12. |
| 100 | These insns are translated into lbcc <L>. */ |
| 101 | {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD)}, |
| 102 | {0, 0, 2, 0}, |
| 103 | {1, 1, 0, 0}, |
| 104 | {1, 1, 0, 0}, |
| 105 | |
| 106 | }; |
| 107 | |
| 108 | /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */ |
| 109 | typedef enum register_id { |
| 110 | REG_NONE = -1, |
| 111 | REG_A = 0, |
| 112 | REG_B = 1, |
| 113 | REG_CCR = 2, |
| 114 | REG_D = 4, |
| 115 | REG_X = 5, |
| 116 | REG_Y = 6, |
| 117 | REG_SP = 7, |
| 118 | REG_PC = 8 |
| 119 | } register_id; |
| 120 | |
| 121 | typedef struct operand { |
| 122 | expressionS exp; |
| 123 | register_id reg1; |
| 124 | register_id reg2; |
| 125 | int mode; |
| 126 | } operand; |
| 127 | |
| 128 | struct m68hc11_opcode_def { |
| 129 | long format; |
| 130 | int min_operands; |
| 131 | int max_operands; |
| 132 | int nb_modes; |
| 133 | int used; |
| 134 | struct m68hc11_opcode *opcode; |
| 135 | }; |
| 136 | |
| 137 | static struct m68hc11_opcode_def *m68hc11_opcode_defs = 0; |
| 138 | static int m68hc11_nb_opcode_defs = 0; |
| 139 | |
| 140 | typedef struct alias { |
| 141 | const char *name; |
| 142 | const char *alias; |
| 143 | } alias; |
| 144 | |
| 145 | static alias alias_opcodes[] = { |
| 146 | {"cpd", "cmpd"}, |
| 147 | {"cpx", "cmpx"}, |
| 148 | {"cpy", "cmpy"}, |
| 149 | {0, 0} |
| 150 | }; |
| 151 | |
| 152 | /* Local functions. */ |
| 153 | static register_id reg_name_search PARAMS ((char *)); |
| 154 | static register_id register_name PARAMS ((void)); |
| 155 | static int cmp_opcode PARAMS ((struct m68hc11_opcode *, |
| 156 | struct m68hc11_opcode *)); |
| 157 | static char *print_opcode_format PARAMS ((struct m68hc11_opcode *, int)); |
| 158 | static char *skip_whites PARAMS ((char *)); |
| 159 | static int check_range PARAMS ((long, int)); |
| 160 | static void print_opcode_list PARAMS ((void)); |
| 161 | static void get_default_target PARAMS ((void)); |
| 162 | static void print_insn_format PARAMS ((char *)); |
| 163 | static int get_operand PARAMS ((operand *, int, long)); |
| 164 | static void fixup8 PARAMS ((expressionS *, int, int)); |
| 165 | static void fixup16 PARAMS ((expressionS *, int, int)); |
| 166 | static unsigned char convert_branch PARAMS ((unsigned char)); |
| 167 | static char *m68hc11_new_insn PARAMS ((int)); |
| 168 | static void build_dbranch_insn PARAMS ((struct m68hc11_opcode *, |
| 169 | operand *, int, int)); |
| 170 | static int build_indexed_byte PARAMS ((operand *, int, int)); |
| 171 | static int build_reg_mode PARAMS ((operand *, int)); |
| 172 | |
| 173 | static struct m68hc11_opcode *find |
| 174 | PARAMS ((struct m68hc11_opcode_def *, operand *, int)); |
| 175 | static struct m68hc11_opcode *find_opcode |
| 176 | PARAMS ((struct m68hc11_opcode_def *, operand *, int *)); |
| 177 | static void build_jump_insn |
| 178 | PARAMS ((struct m68hc11_opcode *, operand *, int, int)); |
| 179 | static void build_insn |
| 180 | PARAMS ((struct m68hc11_opcode *, operand *, int)); |
| 181 | static int relaxable_symbol PARAMS ((symbolS *)); |
| 182 | |
| 183 | /* Controls whether relative branches can be turned into long branches. |
| 184 | When the relative offset is too large, the insn are changed: |
| 185 | bra -> jmp |
| 186 | bsr -> jsr |
| 187 | bcc -> b!cc +3 |
| 188 | jmp L |
| 189 | dbcc -> db!cc +3 |
| 190 | jmp L |
| 191 | |
| 192 | Setting the flag forbidds this. */ |
| 193 | static short flag_fixed_branchs = 0; |
| 194 | |
| 195 | /* Force to use long jumps (absolute) instead of relative branches. */ |
| 196 | static short flag_force_long_jumps = 0; |
| 197 | |
| 198 | /* Change the direct addressing mode into an absolute addressing mode |
| 199 | when the insn does not support direct addressing. |
| 200 | For example, "clr *ZD0" is normally not possible and is changed |
| 201 | into "clr ZDO". */ |
| 202 | static short flag_strict_direct_addressing = 1; |
| 203 | |
| 204 | /* When an opcode has invalid operand, print out the syntax of the opcode |
| 205 | to stderr. */ |
| 206 | static short flag_print_insn_syntax = 0; |
| 207 | |
| 208 | /* Dumps the list of instructions with syntax and then exit: |
| 209 | 1 -> Only dumps the list (sorted by name) |
| 210 | 2 -> Generate an example (or test) that can be compiled. */ |
| 211 | static short flag_print_opcodes = 0; |
| 212 | |
| 213 | /* Opcode hash table. */ |
| 214 | static struct hash_control *m68hc11_hash; |
| 215 | |
| 216 | /* Current cpu (either cpu6811 or cpu6812). This is determined automagically |
| 217 | by 'get_default_target' by looking at default BFD vector. This is overriden |
| 218 | with the -m<cpu> option. */ |
| 219 | static int current_architecture = 0; |
| 220 | |
| 221 | /* Default cpu determined by 'get_default_target'. */ |
| 222 | static const char *default_cpu; |
| 223 | |
| 224 | /* Number of opcodes in the sorted table (filtered by current cpu). */ |
| 225 | static int num_opcodes; |
| 226 | |
| 227 | /* The opcodes sorted by name and filtered by current cpu. */ |
| 228 | static struct m68hc11_opcode *m68hc11_sorted_opcodes; |
| 229 | |
| 230 | /* These are the machine dependent pseudo-ops. These are included so |
| 231 | the assembler can work on the output from the SUN C compiler, which |
| 232 | generates these. */ |
| 233 | |
| 234 | /* This table describes all the machine specific pseudo-ops the assembler |
| 235 | has to support. The fields are: |
| 236 | pseudo-op name without dot |
| 237 | function to call to execute this pseudo-op |
| 238 | Integer arg to pass to the function. */ |
| 239 | const pseudo_typeS md_pseudo_table[] = { |
| 240 | /* The following pseudo-ops are supported for MRI compatibility. */ |
| 241 | {"fcb", cons, 1}, |
| 242 | {"fdb", cons, 2}, |
| 243 | {"fcc", stringer, 1}, |
| 244 | {"rmb", s_space, 0}, |
| 245 | |
| 246 | /* Dwarf2 support for Gcc. */ |
| 247 | {"file", dwarf2_directive_file, 0}, |
| 248 | {"loc", dwarf2_directive_loc, 0}, |
| 249 | |
| 250 | /* Motorola ALIS. */ |
| 251 | {"xrefb", s_ignore, 0}, /* Same as xref */ |
| 252 | |
| 253 | {0, 0, 0} |
| 254 | }; |
| 255 | \f |
| 256 | /* Options and initialization. */ |
| 257 | |
| 258 | CONST char *md_shortopts = "Sm:"; |
| 259 | |
| 260 | struct option md_longopts[] = { |
| 261 | #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE) |
| 262 | {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, |
| 263 | |
| 264 | #define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1) |
| 265 | {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHS}, |
| 266 | |
| 267 | #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2) |
| 268 | {"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE}, |
| 269 | |
| 270 | #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3) |
| 271 | {"print-insn-syntax", no_argument, NULL, OPTION_PRINT_INSN_SYNTAX}, |
| 272 | |
| 273 | #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4) |
| 274 | {"print-opcodes", no_argument, NULL, OPTION_PRINT_OPCODES}, |
| 275 | |
| 276 | #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5) |
| 277 | {"generate-example", no_argument, NULL, OPTION_GENERATE_EXAMPLE}, |
| 278 | |
| 279 | {NULL, no_argument, NULL, 0} |
| 280 | }; |
| 281 | size_t md_longopts_size = sizeof (md_longopts); |
| 282 | |
| 283 | /* Get the target cpu for the assembler. This is based on the configure |
| 284 | options and on the -m68hc11/-m68hc12 option. If no option is specified, |
| 285 | we must get the default. */ |
| 286 | const char * |
| 287 | m68hc11_arch_format () |
| 288 | { |
| 289 | get_default_target (); |
| 290 | if (current_architecture & cpu6811) |
| 291 | return "elf32-m68hc11"; |
| 292 | else |
| 293 | return "elf32-m68hc12"; |
| 294 | } |
| 295 | |
| 296 | enum bfd_architecture |
| 297 | m68hc11_arch () |
| 298 | { |
| 299 | get_default_target (); |
| 300 | if (current_architecture & cpu6811) |
| 301 | return bfd_arch_m68hc11; |
| 302 | else |
| 303 | return bfd_arch_m68hc12; |
| 304 | } |
| 305 | |
| 306 | int |
| 307 | m68hc11_mach () |
| 308 | { |
| 309 | return 0; |
| 310 | } |
| 311 | |
| 312 | /* Listing header selected according to cpu. */ |
| 313 | const char * |
| 314 | m68hc11_listing_header () |
| 315 | { |
| 316 | if (current_architecture & cpu6811) |
| 317 | return "M68HC11 GAS "; |
| 318 | else |
| 319 | return "M68HC12 GAS "; |
| 320 | } |
| 321 | |
| 322 | void |
| 323 | md_show_usage (stream) |
| 324 | FILE *stream; |
| 325 | { |
| 326 | get_default_target (); |
| 327 | fprintf (stream, _("\ |
| 328 | Motorola 68HC11/68HC12 options:\n\ |
| 329 | -m68hc11 | -m68hc12 specify the processor [default %s]\n\ |
| 330 | --force-long-branchs always turn relative branchs into absolute ones\n\ |
| 331 | -S,--short-branchs do not turn relative branchs into absolute ones\n\ |
| 332 | when the offset is out of range\n\ |
| 333 | --strict-direct-mode do not turn the direct mode into extended mode\n\ |
| 334 | when the instruction does not support direct mode\n\ |
| 335 | --print-insn-syntax print the syntax of instruction in case of error\n\ |
| 336 | --print-opcodes print the list of instructions with syntax\n\ |
| 337 | --generate-example generate an example of each instruction\n\ |
| 338 | (used for testing)\n"), default_cpu); |
| 339 | |
| 340 | } |
| 341 | |
| 342 | /* Try to identify the default target based on the BFD library. */ |
| 343 | static void |
| 344 | get_default_target () |
| 345 | { |
| 346 | const bfd_target *target; |
| 347 | bfd abfd; |
| 348 | |
| 349 | if (current_architecture != 0) |
| 350 | return; |
| 351 | |
| 352 | default_cpu = "unknown"; |
| 353 | target = bfd_find_target (0, &abfd); |
| 354 | if (target && target->name) |
| 355 | { |
| 356 | if (strcmp (target->name, "elf32-m68hc12") == 0) |
| 357 | { |
| 358 | current_architecture = cpu6812; |
| 359 | default_cpu = "m68hc12"; |
| 360 | } |
| 361 | else if (strcmp (target->name, "elf32-m68hc11") == 0) |
| 362 | { |
| 363 | current_architecture = cpu6811; |
| 364 | default_cpu = "m68hc11"; |
| 365 | } |
| 366 | else |
| 367 | { |
| 368 | as_bad (_("Default target `%s' is not supported."), target->name); |
| 369 | } |
| 370 | } |
| 371 | } |
| 372 | |
| 373 | void |
| 374 | m68hc11_print_statistics (file) |
| 375 | FILE *file; |
| 376 | { |
| 377 | int i; |
| 378 | struct m68hc11_opcode_def *opc; |
| 379 | |
| 380 | hash_print_statistics (file, "opcode table", m68hc11_hash); |
| 381 | |
| 382 | opc = m68hc11_opcode_defs; |
| 383 | if (opc == 0 || m68hc11_nb_opcode_defs == 0) |
| 384 | return; |
| 385 | |
| 386 | /* Dump the opcode statistics table. */ |
| 387 | fprintf (file, _("Name # Modes Min ops Max ops Modes mask # Used\n")); |
| 388 | for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++) |
| 389 | { |
| 390 | fprintf (file, "%-7.7s %5d %7d %7d 0x%08lx %7d\n", |
| 391 | opc->opcode->name, |
| 392 | opc->nb_modes, |
| 393 | opc->min_operands, opc->max_operands, opc->format, opc->used); |
| 394 | } |
| 395 | } |
| 396 | |
| 397 | int |
| 398 | md_parse_option (c, arg) |
| 399 | int c; |
| 400 | char *arg; |
| 401 | { |
| 402 | get_default_target (); |
| 403 | switch (c) |
| 404 | { |
| 405 | /* -S means keep external to 2 bit offset rather than 16 bit one. */ |
| 406 | case OPTION_SHORT_BRANCHS: |
| 407 | case 'S': |
| 408 | flag_fixed_branchs = 1; |
| 409 | break; |
| 410 | |
| 411 | case OPTION_FORCE_LONG_BRANCH: |
| 412 | flag_force_long_jumps = 1; |
| 413 | break; |
| 414 | |
| 415 | case OPTION_PRINT_INSN_SYNTAX: |
| 416 | flag_print_insn_syntax = 1; |
| 417 | break; |
| 418 | |
| 419 | case OPTION_PRINT_OPCODES: |
| 420 | flag_print_opcodes = 1; |
| 421 | break; |
| 422 | |
| 423 | case OPTION_STRICT_DIRECT_MODE: |
| 424 | flag_strict_direct_addressing = 0; |
| 425 | break; |
| 426 | |
| 427 | case OPTION_GENERATE_EXAMPLE: |
| 428 | flag_print_opcodes = 2; |
| 429 | break; |
| 430 | |
| 431 | case 'm': |
| 432 | if (strcasecmp (arg, "68hc11") == 0) |
| 433 | current_architecture = cpu6811; |
| 434 | else if (strcasecmp (arg, "68hc12") == 0) |
| 435 | current_architecture = cpu6812; |
| 436 | else |
| 437 | as_bad (_("Option `%s' is not recognized."), arg); |
| 438 | break; |
| 439 | |
| 440 | default: |
| 441 | return 0; |
| 442 | } |
| 443 | |
| 444 | return 1; |
| 445 | } |
| 446 | \f |
| 447 | symbolS * |
| 448 | md_undefined_symbol (name) |
| 449 | char *name ATTRIBUTE_UNUSED; |
| 450 | { |
| 451 | return 0; |
| 452 | } |
| 453 | |
| 454 | /* Equal to MAX_PRECISION in atof-ieee.c. */ |
| 455 | #define MAX_LITTLENUMS 6 |
| 456 | |
| 457 | /* Turn a string in input_line_pointer into a floating point constant |
| 458 | of type TYPE, and store the appropriate bytes in *LITP. The number |
| 459 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
| 460 | returned, or NULL on OK. */ |
| 461 | char * |
| 462 | md_atof (type, litP, sizeP) |
| 463 | char type; |
| 464 | char *litP; |
| 465 | int *sizeP; |
| 466 | { |
| 467 | int prec; |
| 468 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; |
| 469 | LITTLENUM_TYPE *wordP; |
| 470 | char *t; |
| 471 | |
| 472 | switch (type) |
| 473 | { |
| 474 | case 'f': |
| 475 | case 'F': |
| 476 | case 's': |
| 477 | case 'S': |
| 478 | prec = 2; |
| 479 | break; |
| 480 | |
| 481 | case 'd': |
| 482 | case 'D': |
| 483 | case 'r': |
| 484 | case 'R': |
| 485 | prec = 4; |
| 486 | break; |
| 487 | |
| 488 | case 'x': |
| 489 | case 'X': |
| 490 | prec = 6; |
| 491 | break; |
| 492 | |
| 493 | case 'p': |
| 494 | case 'P': |
| 495 | prec = 6; |
| 496 | break; |
| 497 | |
| 498 | default: |
| 499 | *sizeP = 0; |
| 500 | return _("Bad call to MD_ATOF()"); |
| 501 | } |
| 502 | t = atof_ieee (input_line_pointer, type, words); |
| 503 | if (t) |
| 504 | input_line_pointer = t; |
| 505 | |
| 506 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
| 507 | for (wordP = words; prec--;) |
| 508 | { |
| 509 | md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE)); |
| 510 | litP += sizeof (LITTLENUM_TYPE); |
| 511 | } |
| 512 | return 0; |
| 513 | } |
| 514 | |
| 515 | valueT |
| 516 | md_section_align (seg, addr) |
| 517 | asection *seg; |
| 518 | valueT addr; |
| 519 | { |
| 520 | int align = bfd_get_section_alignment (stdoutput, seg); |
| 521 | return ((addr + (1 << align) - 1) & (-1 << align)); |
| 522 | } |
| 523 | |
| 524 | static int |
| 525 | cmp_opcode (op1, op2) |
| 526 | struct m68hc11_opcode *op1; |
| 527 | struct m68hc11_opcode *op2; |
| 528 | { |
| 529 | return strcmp (op1->name, op2->name); |
| 530 | } |
| 531 | |
| 532 | /* Initialize the assembler. Create the opcode hash table |
| 533 | (sorted on the names) with the M6811 opcode table |
| 534 | (from opcode library). */ |
| 535 | void |
| 536 | md_begin () |
| 537 | { |
| 538 | char *prev_name = ""; |
| 539 | struct m68hc11_opcode *opcodes; |
| 540 | struct m68hc11_opcode_def *opc = 0; |
| 541 | int i, j; |
| 542 | |
| 543 | get_default_target (); |
| 544 | |
| 545 | m68hc11_hash = hash_new (); |
| 546 | |
| 547 | /* Get a writable copy of the opcode table and sort it on the names. */ |
| 548 | opcodes = (struct m68hc11_opcode *) xmalloc (m68hc11_num_opcodes * |
| 549 | sizeof (struct |
| 550 | m68hc11_opcode)); |
| 551 | m68hc11_sorted_opcodes = opcodes; |
| 552 | num_opcodes = 0; |
| 553 | for (i = 0; i < m68hc11_num_opcodes; i++) |
| 554 | { |
| 555 | if (m68hc11_opcodes[i].arch & current_architecture) |
| 556 | { |
| 557 | opcodes[num_opcodes] = m68hc11_opcodes[i]; |
| 558 | if (opcodes[num_opcodes].name[0] == 'b' |
| 559 | && opcodes[num_opcodes].format & M6811_OP_JUMP_REL |
| 560 | && !(opcodes[num_opcodes].format & M6811_OP_BITMASK)) |
| 561 | { |
| 562 | num_opcodes++; |
| 563 | opcodes[num_opcodes] = m68hc11_opcodes[i]; |
| 564 | } |
| 565 | num_opcodes++; |
| 566 | for (j = 0; alias_opcodes[j].name != 0; j++) |
| 567 | if (strcmp (m68hc11_opcodes[i].name, alias_opcodes[j].name) == 0) |
| 568 | { |
| 569 | opcodes[num_opcodes] = m68hc11_opcodes[i]; |
| 570 | opcodes[num_opcodes].name = alias_opcodes[j].alias; |
| 571 | num_opcodes++; |
| 572 | break; |
| 573 | } |
| 574 | } |
| 575 | } |
| 576 | qsort (opcodes, num_opcodes, sizeof (struct m68hc11_opcode), cmp_opcode); |
| 577 | |
| 578 | opc = (struct m68hc11_opcode_def *) |
| 579 | xmalloc (num_opcodes * sizeof (struct m68hc11_opcode_def)); |
| 580 | m68hc11_opcode_defs = opc--; |
| 581 | |
| 582 | /* Insert unique names into hash table. The M6811 instruction set |
| 583 | has several identical opcode names that have different opcodes based |
| 584 | on the operands. This hash table then provides a quick index to |
| 585 | the first opcode with a particular name in the opcode table. */ |
| 586 | for (i = 0; i < num_opcodes; i++, opcodes++) |
| 587 | { |
| 588 | int expect; |
| 589 | |
| 590 | if (strcmp (prev_name, opcodes->name)) |
| 591 | { |
| 592 | prev_name = (char *) opcodes->name; |
| 593 | |
| 594 | opc++; |
| 595 | opc->format = 0; |
| 596 | opc->min_operands = 100; |
| 597 | opc->max_operands = 0; |
| 598 | opc->nb_modes = 0; |
| 599 | opc->opcode = opcodes; |
| 600 | opc->used = 0; |
| 601 | hash_insert (m68hc11_hash, opcodes->name, (char *) opc); |
| 602 | } |
| 603 | opc->nb_modes++; |
| 604 | opc->format |= opcodes->format; |
| 605 | |
| 606 | /* See how many operands this opcode needs. */ |
| 607 | expect = 0; |
| 608 | if (opcodes->format & M6811_OP_MASK) |
| 609 | expect++; |
| 610 | if (opcodes->format & M6811_OP_BITMASK) |
| 611 | expect++; |
| 612 | if (opcodes->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) |
| 613 | expect++; |
| 614 | if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) |
| 615 | expect++; |
| 616 | |
| 617 | if (expect < opc->min_operands) |
| 618 | opc->min_operands = expect; |
| 619 | if (expect > opc->max_operands) |
| 620 | opc->max_operands = expect; |
| 621 | } |
| 622 | opc++; |
| 623 | m68hc11_nb_opcode_defs = opc - m68hc11_opcode_defs; |
| 624 | |
| 625 | if (flag_print_opcodes) |
| 626 | { |
| 627 | print_opcode_list (); |
| 628 | exit (EXIT_SUCCESS); |
| 629 | } |
| 630 | } |
| 631 | |
| 632 | void |
| 633 | m68hc11_init_after_args () |
| 634 | { |
| 635 | } |
| 636 | \f |
| 637 | /* Builtin help. */ |
| 638 | |
| 639 | /* Return a string that represents the operand format for the instruction. |
| 640 | When example is true, this generates an example of operand. This is used |
| 641 | to give an example and also to generate a test. */ |
| 642 | static char * |
| 643 | print_opcode_format (opcode, example) |
| 644 | struct m68hc11_opcode *opcode; |
| 645 | int example; |
| 646 | { |
| 647 | static char buf[128]; |
| 648 | int format = opcode->format; |
| 649 | char *p; |
| 650 | |
| 651 | p = buf; |
| 652 | buf[0] = 0; |
| 653 | if (format & M6811_OP_IMM8) |
| 654 | { |
| 655 | if (example) |
| 656 | sprintf (p, "#%d", rand () & 0x0FF); |
| 657 | else |
| 658 | strcpy (p, _("#<imm8>")); |
| 659 | p = &p[strlen (p)]; |
| 660 | } |
| 661 | |
| 662 | if (format & M6811_OP_IMM16) |
| 663 | { |
| 664 | if (example) |
| 665 | sprintf (p, "#%d", rand () & 0x0FFFF); |
| 666 | else |
| 667 | strcpy (p, _("#<imm16>")); |
| 668 | p = &p[strlen (p)]; |
| 669 | } |
| 670 | |
| 671 | if (format & M6811_OP_IX) |
| 672 | { |
| 673 | if (example) |
| 674 | sprintf (p, "%d,X", rand () & 0x0FF); |
| 675 | else |
| 676 | strcpy (p, _("<imm8>,X")); |
| 677 | p = &p[strlen (p)]; |
| 678 | } |
| 679 | |
| 680 | if (format & M6811_OP_IY) |
| 681 | { |
| 682 | if (example) |
| 683 | sprintf (p, "%d,X", rand () & 0x0FF); |
| 684 | else |
| 685 | strcpy (p, _("<imm8>,X")); |
| 686 | p = &p[strlen (p)]; |
| 687 | } |
| 688 | |
| 689 | if (format & M6812_OP_IDX) |
| 690 | { |
| 691 | if (example) |
| 692 | sprintf (p, "%d,X", rand () & 0x0FF); |
| 693 | else |
| 694 | strcpy (p, "n,r"); |
| 695 | p = &p[strlen (p)]; |
| 696 | } |
| 697 | |
| 698 | if (format & M6811_OP_DIRECT) |
| 699 | { |
| 700 | if (example) |
| 701 | sprintf (p, "*Z%d", rand () & 0x0FF); |
| 702 | else |
| 703 | strcpy (p, _("*<abs8>")); |
| 704 | p = &p[strlen (p)]; |
| 705 | } |
| 706 | |
| 707 | if (format & M6811_OP_BITMASK) |
| 708 | { |
| 709 | if (buf[0]) |
| 710 | *p++ = ' '; |
| 711 | |
| 712 | if (example) |
| 713 | sprintf (p, "#$%02x", rand () & 0x0FF); |
| 714 | else |
| 715 | strcpy (p, _("#<mask>")); |
| 716 | |
| 717 | p = &p[strlen (p)]; |
| 718 | if (format & M6811_OP_JUMP_REL) |
| 719 | *p++ = ' '; |
| 720 | } |
| 721 | |
| 722 | if (format & M6811_OP_IND16) |
| 723 | { |
| 724 | if (example) |
| 725 | sprintf (p, _("symbol%d"), rand () & 0x0FF); |
| 726 | else |
| 727 | strcpy (p, _("<abs>")); |
| 728 | |
| 729 | p = &p[strlen (p)]; |
| 730 | } |
| 731 | |
| 732 | if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) |
| 733 | { |
| 734 | if (example) |
| 735 | { |
| 736 | if (format & M6811_OP_BITMASK) |
| 737 | { |
| 738 | sprintf (p, ".+%d", rand () & 0x7F); |
| 739 | } |
| 740 | else |
| 741 | { |
| 742 | sprintf (p, "L%d", rand () & 0x0FF); |
| 743 | } |
| 744 | } |
| 745 | else |
| 746 | strcpy (p, _("<label>")); |
| 747 | } |
| 748 | |
| 749 | return buf; |
| 750 | } |
| 751 | |
| 752 | /* Prints the list of instructions with the possible operands. */ |
| 753 | static void |
| 754 | print_opcode_list () |
| 755 | { |
| 756 | int i; |
| 757 | char *prev_name = ""; |
| 758 | struct m68hc11_opcode *opcodes; |
| 759 | int example = flag_print_opcodes == 2; |
| 760 | |
| 761 | if (example) |
| 762 | printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"), |
| 763 | default_cpu); |
| 764 | |
| 765 | opcodes = m68hc11_sorted_opcodes; |
| 766 | |
| 767 | /* Walk the list sorted on names (by md_begin). We only report |
| 768 | one instruction per line, and we collect the different operand |
| 769 | formats. */ |
| 770 | for (i = 0; i < num_opcodes; i++, opcodes++) |
| 771 | { |
| 772 | char *fmt = print_opcode_format (opcodes, example); |
| 773 | |
| 774 | if (example) |
| 775 | { |
| 776 | printf ("L%d:\t", i); |
| 777 | printf ("%s %s\n", opcodes->name, fmt); |
| 778 | } |
| 779 | else |
| 780 | { |
| 781 | if (strcmp (prev_name, opcodes->name)) |
| 782 | { |
| 783 | if (i > 0) |
| 784 | printf ("\n"); |
| 785 | |
| 786 | printf ("%-5.5s ", opcodes->name); |
| 787 | prev_name = (char *) opcodes->name; |
| 788 | } |
| 789 | if (fmt[0]) |
| 790 | printf (" [%s]", fmt); |
| 791 | } |
| 792 | } |
| 793 | printf ("\n"); |
| 794 | } |
| 795 | |
| 796 | /* Print the instruction format. This operation is called when some |
| 797 | instruction is not correct. Instruction format is printed as an |
| 798 | error message. */ |
| 799 | static void |
| 800 | print_insn_format (name) |
| 801 | char *name; |
| 802 | { |
| 803 | struct m68hc11_opcode_def *opc; |
| 804 | struct m68hc11_opcode *opcode; |
| 805 | char buf[128]; |
| 806 | |
| 807 | opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); |
| 808 | if (opc == NULL) |
| 809 | { |
| 810 | as_bad (_("Instruction `%s' is not recognized."), name); |
| 811 | return; |
| 812 | } |
| 813 | opcode = opc->opcode; |
| 814 | |
| 815 | as_bad (_("Instruction formats for `%s':"), name); |
| 816 | do |
| 817 | { |
| 818 | char *fmt; |
| 819 | |
| 820 | fmt = print_opcode_format (opcode, 0); |
| 821 | sprintf (buf, "\t%-5.5s %s", opcode->name, fmt); |
| 822 | |
| 823 | as_bad ("%s", buf); |
| 824 | opcode++; |
| 825 | } |
| 826 | while (strcmp (opcode->name, name) == 0); |
| 827 | } |
| 828 | \f |
| 829 | /* Analysis of 68HC11 and 68HC12 operands. */ |
| 830 | |
| 831 | /* reg_name_search() finds the register number given its name. |
| 832 | Returns the register number or REG_NONE on failure. */ |
| 833 | static register_id |
| 834 | reg_name_search (name) |
| 835 | char *name; |
| 836 | { |
| 837 | if (strcasecmp (name, "x") == 0 || strcasecmp (name, "ix") == 0) |
| 838 | return REG_X; |
| 839 | if (strcasecmp (name, "y") == 0 || strcasecmp (name, "iy") == 0) |
| 840 | return REG_Y; |
| 841 | if (strcasecmp (name, "a") == 0) |
| 842 | return REG_A; |
| 843 | if (strcasecmp (name, "b") == 0) |
| 844 | return REG_B; |
| 845 | if (strcasecmp (name, "d") == 0) |
| 846 | return REG_D; |
| 847 | if (strcasecmp (name, "sp") == 0) |
| 848 | return REG_SP; |
| 849 | if (strcasecmp (name, "pc") == 0) |
| 850 | return REG_PC; |
| 851 | if (strcasecmp (name, "ccr") == 0) |
| 852 | return REG_CCR; |
| 853 | |
| 854 | return REG_NONE; |
| 855 | } |
| 856 | |
| 857 | static char * |
| 858 | skip_whites (p) |
| 859 | char *p; |
| 860 | { |
| 861 | while (*p == ' ' || *p == '\t') |
| 862 | p++; |
| 863 | |
| 864 | return p; |
| 865 | } |
| 866 | |
| 867 | /* Check the string at input_line_pointer |
| 868 | to see if it is a valid register name. */ |
| 869 | static register_id |
| 870 | register_name () |
| 871 | { |
| 872 | register_id reg_number; |
| 873 | char c, *p = input_line_pointer; |
| 874 | |
| 875 | if (!is_name_beginner (*p++)) |
| 876 | return REG_NONE; |
| 877 | |
| 878 | while (is_part_of_name (*p++)) |
| 879 | continue; |
| 880 | |
| 881 | c = *--p; |
| 882 | if (c) |
| 883 | *p++ = 0; |
| 884 | |
| 885 | /* Look to see if it's in the register table. */ |
| 886 | reg_number = reg_name_search (input_line_pointer); |
| 887 | if (reg_number != REG_NONE) |
| 888 | { |
| 889 | if (c) |
| 890 | *--p = c; |
| 891 | |
| 892 | input_line_pointer = p; |
| 893 | return reg_number; |
| 894 | } |
| 895 | if (c) |
| 896 | *--p = c; |
| 897 | |
| 898 | return reg_number; |
| 899 | } |
| 900 | |
| 901 | /* Parse a string of operands and return an array of expressions. |
| 902 | |
| 903 | Operand mode[0] mode[1] exp[0] exp[1] |
| 904 | #n M6811_OP_IMM16 - O_* |
| 905 | *<exp> M6811_OP_DIRECT - O_* |
| 906 | .{+-}<exp> M6811_OP_JUMP_REL - O_* |
| 907 | <exp> M6811_OP_IND16 - O_* |
| 908 | ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register |
| 909 | n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register |
| 910 | n,+r M6812_PRE_INC " " |
| 911 | n,r- M6812_POST_DEC " " |
| 912 | n,r+ M6812_POST_INC " " |
| 913 | A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register |
| 914 | [D,r] M6811_OP_IDX_2 M6812_OP_REG O_register O_register |
| 915 | [n,r] M6811_OP_IDX_1 M6812_OP_REG O_constant O_register */ |
| 916 | static int |
| 917 | get_operand (oper, which, opmode) |
| 918 | operand *oper; |
| 919 | int which; |
| 920 | long opmode; |
| 921 | { |
| 922 | char *p = input_line_pointer; |
| 923 | int mode; |
| 924 | register_id reg; |
| 925 | |
| 926 | oper->exp.X_op = O_absent; |
| 927 | oper->reg1 = REG_NONE; |
| 928 | oper->reg2 = REG_NONE; |
| 929 | mode = M6811_OP_NONE; |
| 930 | |
| 931 | p = skip_whites (p); |
| 932 | |
| 933 | if (*p == 0 || *p == '\n' || *p == '\r') |
| 934 | { |
| 935 | input_line_pointer = p; |
| 936 | return 0; |
| 937 | } |
| 938 | |
| 939 | if (*p == '*' && (opmode & (M6811_OP_DIRECT | M6811_OP_IND16))) |
| 940 | { |
| 941 | mode = M6811_OP_DIRECT; |
| 942 | p++; |
| 943 | } |
| 944 | else if (*p == '#') |
| 945 | { |
| 946 | if (!(opmode & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK))) |
| 947 | { |
| 948 | as_bad (_("Immediate operand is not allowed for operand %d."), |
| 949 | which); |
| 950 | return -1; |
| 951 | } |
| 952 | |
| 953 | mode = M6811_OP_IMM16; |
| 954 | p++; |
| 955 | if (strncmp (p, "%hi", 3) == 0) |
| 956 | { |
| 957 | p += 3; |
| 958 | mode |= M6811_OP_HIGH_ADDR; |
| 959 | } |
| 960 | else if (strncmp (p, "%lo", 3) == 0) |
| 961 | { |
| 962 | p += 3; |
| 963 | mode |= M6811_OP_LOW_ADDR; |
| 964 | } |
| 965 | } |
| 966 | else if (*p == '.' && (p[1] == '+' || p[1] == '-')) |
| 967 | { |
| 968 | p++; |
| 969 | mode = M6811_OP_JUMP_REL; |
| 970 | } |
| 971 | else if (*p == '[') |
| 972 | { |
| 973 | if (current_architecture & cpu6811) |
| 974 | as_bad (_("Indirect indexed addressing is not valid for 68HC11.")); |
| 975 | |
| 976 | p++; |
| 977 | mode = M6812_OP_IDX_2; |
| 978 | p = skip_whites (p); |
| 979 | } |
| 980 | else if (*p == ',') /* Special handling of ,x and ,y. */ |
| 981 | { |
| 982 | p++; |
| 983 | input_line_pointer = p; |
| 984 | |
| 985 | reg = register_name (); |
| 986 | if (reg != REG_NONE) |
| 987 | { |
| 988 | oper->reg1 = reg; |
| 989 | oper->exp.X_op = O_constant; |
| 990 | oper->exp.X_add_number = 0; |
| 991 | oper->mode = M6812_OP_IDX; |
| 992 | return 1; |
| 993 | } |
| 994 | as_bad (_("Spurious `,' or bad indirect register addressing mode.")); |
| 995 | return -1; |
| 996 | } |
| 997 | input_line_pointer = p; |
| 998 | |
| 999 | if (mode == M6811_OP_NONE || mode == M6812_OP_IDX_2) |
| 1000 | reg = register_name (); |
| 1001 | else |
| 1002 | reg = REG_NONE; |
| 1003 | |
| 1004 | if (reg != REG_NONE) |
| 1005 | { |
| 1006 | p = skip_whites (input_line_pointer); |
| 1007 | if (*p == ']' && mode == M6812_OP_IDX_2) |
| 1008 | { |
| 1009 | as_bad |
| 1010 | (_("Missing second register or offset for indexed-indirect mode.")); |
| 1011 | return -1; |
| 1012 | } |
| 1013 | |
| 1014 | oper->reg1 = reg; |
| 1015 | oper->mode = mode | M6812_OP_REG; |
| 1016 | if (*p != ',') |
| 1017 | { |
| 1018 | if (mode == M6812_OP_IDX_2) |
| 1019 | { |
| 1020 | as_bad (_("Missing second register for indexed-indirect mode.")); |
| 1021 | return -1; |
| 1022 | } |
| 1023 | return 1; |
| 1024 | } |
| 1025 | |
| 1026 | p++; |
| 1027 | input_line_pointer = p; |
| 1028 | reg = register_name (); |
| 1029 | if (reg != REG_NONE) |
| 1030 | { |
| 1031 | p = skip_whites (input_line_pointer); |
| 1032 | if (mode == M6812_OP_IDX_2) |
| 1033 | { |
| 1034 | if (*p != ']') |
| 1035 | { |
| 1036 | as_bad (_("Missing `]' to close indexed-indirect mode.")); |
| 1037 | return -1; |
| 1038 | } |
| 1039 | p++; |
| 1040 | } |
| 1041 | input_line_pointer = p; |
| 1042 | |
| 1043 | oper->reg2 = reg; |
| 1044 | return 1; |
| 1045 | } |
| 1046 | return 1; |
| 1047 | } |
| 1048 | |
| 1049 | /* In MRI mode, isolate the operand because we can't distinguish |
| 1050 | operands from comments. */ |
| 1051 | if (flag_mri) |
| 1052 | { |
| 1053 | char c = 0; |
| 1054 | |
| 1055 | p = skip_whites (p); |
| 1056 | while (*p && *p != ' ' && *p != '\t') |
| 1057 | p++; |
| 1058 | |
| 1059 | if (*p) |
| 1060 | { |
| 1061 | c = *p; |
| 1062 | *p = 0; |
| 1063 | } |
| 1064 | |
| 1065 | /* Parse as an expression. */ |
| 1066 | expression (&oper->exp); |
| 1067 | |
| 1068 | if (c) |
| 1069 | { |
| 1070 | *p = c; |
| 1071 | } |
| 1072 | } |
| 1073 | else |
| 1074 | { |
| 1075 | expression (&oper->exp); |
| 1076 | } |
| 1077 | |
| 1078 | if (oper->exp.X_op == O_illegal) |
| 1079 | { |
| 1080 | as_bad (_("Illegal operand.")); |
| 1081 | return -1; |
| 1082 | } |
| 1083 | else if (oper->exp.X_op == O_absent) |
| 1084 | { |
| 1085 | as_bad (_("Missing operand.")); |
| 1086 | return -1; |
| 1087 | } |
| 1088 | |
| 1089 | p = input_line_pointer; |
| 1090 | |
| 1091 | if (mode == M6811_OP_NONE || mode == M6811_OP_DIRECT |
| 1092 | || mode == M6812_OP_IDX_2) |
| 1093 | { |
| 1094 | p = skip_whites (input_line_pointer); |
| 1095 | |
| 1096 | if (*p == ',') |
| 1097 | { |
| 1098 | int possible_mode = M6811_OP_NONE; |
| 1099 | char *old_input_line; |
| 1100 | p++; |
| 1101 | |
| 1102 | /* 68HC12 pre increment or decrement. */ |
| 1103 | if (mode == M6811_OP_NONE) |
| 1104 | { |
| 1105 | if (*p == '-') |
| 1106 | { |
| 1107 | possible_mode = M6812_PRE_DEC; |
| 1108 | p++; |
| 1109 | } |
| 1110 | else if (*p == '+') |
| 1111 | { |
| 1112 | possible_mode = M6812_PRE_INC; |
| 1113 | p++; |
| 1114 | } |
| 1115 | p = skip_whites (p); |
| 1116 | } |
| 1117 | old_input_line = input_line_pointer; |
| 1118 | input_line_pointer = p; |
| 1119 | reg = register_name (); |
| 1120 | |
| 1121 | /* Backtrack if we have a valid constant expression and |
| 1122 | it does not correspond to the offset of the 68HC12 indexed |
| 1123 | addressing mode (as in N,x). */ |
| 1124 | if (reg == REG_NONE && mode == M6811_OP_NONE |
| 1125 | && possible_mode != M6811_OP_NONE) |
| 1126 | { |
| 1127 | oper->mode = M6811_OP_IND16 | M6811_OP_JUMP_REL; |
| 1128 | input_line_pointer = skip_whites (old_input_line); |
| 1129 | return 1; |
| 1130 | } |
| 1131 | |
| 1132 | if (possible_mode != M6811_OP_NONE) |
| 1133 | mode = possible_mode; |
| 1134 | |
| 1135 | if ((current_architecture & cpu6811) |
| 1136 | && possible_mode != M6811_OP_NONE) |
| 1137 | as_bad (_("Pre-increment mode is not valid for 68HC11")); |
| 1138 | /* Backtrack. */ |
| 1139 | if (which == 0 && opmode & M6812_OP_IDX_P2 |
| 1140 | && reg != REG_X && reg != REG_Y |
| 1141 | && reg != REG_PC && reg != REG_SP) |
| 1142 | { |
| 1143 | reg = REG_NONE; |
| 1144 | input_line_pointer = p; |
| 1145 | } |
| 1146 | |
| 1147 | if (reg == REG_NONE && mode != M6811_OP_DIRECT |
| 1148 | && !(mode == M6811_OP_NONE && opmode & M6811_OP_IND16)) |
| 1149 | { |
| 1150 | as_bad (_("Wrong register in register indirect mode.")); |
| 1151 | return -1; |
| 1152 | } |
| 1153 | if (mode == M6812_OP_IDX_2) |
| 1154 | { |
| 1155 | p = skip_whites (input_line_pointer); |
| 1156 | if (*p++ != ']') |
| 1157 | { |
| 1158 | as_bad (_("Missing `]' to close register indirect operand.")); |
| 1159 | return -1; |
| 1160 | } |
| 1161 | input_line_pointer = p; |
| 1162 | } |
| 1163 | if (reg != REG_NONE) |
| 1164 | { |
| 1165 | oper->reg1 = reg; |
| 1166 | if (mode == M6811_OP_NONE) |
| 1167 | { |
| 1168 | p = input_line_pointer; |
| 1169 | if (*p == '-') |
| 1170 | { |
| 1171 | mode = M6812_POST_DEC; |
| 1172 | p++; |
| 1173 | if (current_architecture & cpu6811) |
| 1174 | as_bad |
| 1175 | (_("Post-decrement mode is not valid for 68HC11.")); |
| 1176 | } |
| 1177 | else if (*p == '+') |
| 1178 | { |
| 1179 | mode = M6812_POST_INC; |
| 1180 | p++; |
| 1181 | if (current_architecture & cpu6811) |
| 1182 | as_bad |
| 1183 | (_("Post-increment mode is not valid for 68HC11.")); |
| 1184 | } |
| 1185 | else |
| 1186 | mode = M6812_OP_IDX; |
| 1187 | |
| 1188 | input_line_pointer = p; |
| 1189 | } |
| 1190 | else |
| 1191 | mode |= M6812_OP_IDX; |
| 1192 | |
| 1193 | oper->mode = mode; |
| 1194 | return 1; |
| 1195 | } |
| 1196 | } |
| 1197 | |
| 1198 | if (mode == M6812_OP_D_IDX_2) |
| 1199 | { |
| 1200 | as_bad (_("Invalid indexed indirect mode.")); |
| 1201 | return -1; |
| 1202 | } |
| 1203 | } |
| 1204 | |
| 1205 | /* If the mode is not known until now, this is either a label |
| 1206 | or an indirect address. */ |
| 1207 | if (mode == M6811_OP_NONE) |
| 1208 | mode = M6811_OP_IND16 | M6811_OP_JUMP_REL; |
| 1209 | |
| 1210 | p = input_line_pointer; |
| 1211 | while (*p == ' ' || *p == '\t') |
| 1212 | p++; |
| 1213 | input_line_pointer = p; |
| 1214 | oper->mode = mode; |
| 1215 | |
| 1216 | return 1; |
| 1217 | } |
| 1218 | |
| 1219 | #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \ |
| 1220 | | M6812_POST_INC | M6812_POST_DEC) |
| 1221 | |
| 1222 | /* Checks that the number 'num' fits for a given mode. */ |
| 1223 | static int |
| 1224 | check_range (num, mode) |
| 1225 | long num; |
| 1226 | int mode; |
| 1227 | { |
| 1228 | /* Auto increment and decrement are ok for [-8..8] without 0. */ |
| 1229 | if (mode & M6812_AUTO_INC_DEC) |
| 1230 | return (num != 0 && num <= 8 && num >= -8); |
| 1231 | |
| 1232 | /* The 68HC12 supports 5, 9 and 16-bit offsets. */ |
| 1233 | if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX)) |
| 1234 | mode = M6811_OP_IND16; |
| 1235 | |
| 1236 | if (mode & M6812_OP_JUMP_REL16) |
| 1237 | mode = M6811_OP_IND16; |
| 1238 | |
| 1239 | switch (mode) |
| 1240 | { |
| 1241 | case M6811_OP_IX: |
| 1242 | case M6811_OP_IY: |
| 1243 | case M6811_OP_DIRECT: |
| 1244 | return (num >= 0 && num <= 255) ? 1 : 0; |
| 1245 | |
| 1246 | case M6811_OP_BITMASK: |
| 1247 | case M6811_OP_IMM8: |
| 1248 | return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00)) |
| 1249 | ? 1 : 0; |
| 1250 | |
| 1251 | case M6811_OP_JUMP_REL: |
| 1252 | return (num >= -128 && num <= 127) ? 1 : 0; |
| 1253 | |
| 1254 | case M6811_OP_IND16: |
| 1255 | case M6811_OP_IMM16: |
| 1256 | return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000)) |
| 1257 | ? 1 : 0; |
| 1258 | |
| 1259 | case M6812_OP_IBCC_MARKER: |
| 1260 | case M6812_OP_TBCC_MARKER: |
| 1261 | case M6812_OP_DBCC_MARKER: |
| 1262 | return (num >= -256 && num <= 255) ? 1 : 0; |
| 1263 | |
| 1264 | case M6812_OP_TRAP_ID: |
| 1265 | return ((num >= 0x30 && num <= 0x39) |
| 1266 | || (num >= 0x40 && num <= 0x0ff)) ? 1 : 0; |
| 1267 | |
| 1268 | default: |
| 1269 | return 0; |
| 1270 | } |
| 1271 | } |
| 1272 | \f |
| 1273 | /* Gas fixup generation. */ |
| 1274 | |
| 1275 | /* Put a 1 byte expression described by 'oper'. If this expression contains |
| 1276 | unresolved symbols, generate an 8-bit fixup. */ |
| 1277 | static void |
| 1278 | fixup8 (oper, mode, opmode) |
| 1279 | expressionS *oper; |
| 1280 | int mode; |
| 1281 | int opmode; |
| 1282 | { |
| 1283 | char *f; |
| 1284 | |
| 1285 | f = frag_more (1); |
| 1286 | |
| 1287 | if (oper->X_op == O_constant) |
| 1288 | { |
| 1289 | if (mode & M6812_OP_TRAP_ID |
| 1290 | && !check_range (oper->X_add_number, M6812_OP_TRAP_ID)) |
| 1291 | { |
| 1292 | static char trap_id_warn_once = 0; |
| 1293 | |
| 1294 | as_bad (_("Trap id `%ld' is out of range."), oper->X_add_number); |
| 1295 | if (trap_id_warn_once == 0) |
| 1296 | { |
| 1297 | trap_id_warn_once = 1; |
| 1298 | as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff].")); |
| 1299 | } |
| 1300 | } |
| 1301 | |
| 1302 | if (!(mode & M6812_OP_TRAP_ID) |
| 1303 | && !check_range (oper->X_add_number, mode)) |
| 1304 | { |
| 1305 | as_bad (_("Operand out of 8-bit range: `%ld'."), oper->X_add_number); |
| 1306 | } |
| 1307 | number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1); |
| 1308 | } |
| 1309 | else if (oper->X_op != O_register) |
| 1310 | { |
| 1311 | if (mode & M6812_OP_TRAP_ID) |
| 1312 | as_bad (_("The trap id must be a constant.")); |
| 1313 | |
| 1314 | if (mode == M6811_OP_JUMP_REL) |
| 1315 | { |
| 1316 | fixS *fixp; |
| 1317 | |
| 1318 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, |
| 1319 | oper, true, BFD_RELOC_8_PCREL); |
| 1320 | fixp->fx_pcrel_adjust = 1; |
| 1321 | } |
| 1322 | else |
| 1323 | { |
| 1324 | /* Now create an 8-bit fixup. If there was some %hi or %lo |
| 1325 | modifier, generate the reloc accordingly. */ |
| 1326 | fix_new_exp (frag_now, f - frag_now->fr_literal, 1, |
| 1327 | oper, false, |
| 1328 | ((opmode & M6811_OP_HIGH_ADDR) |
| 1329 | ? BFD_RELOC_M68HC11_HI8 |
| 1330 | : ((opmode & M6811_OP_LOW_ADDR) |
| 1331 | ? BFD_RELOC_M68HC11_LO8 : BFD_RELOC_8))); |
| 1332 | } |
| 1333 | number_to_chars_bigendian (f, 0, 1); |
| 1334 | } |
| 1335 | else |
| 1336 | { |
| 1337 | as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op); |
| 1338 | } |
| 1339 | } |
| 1340 | |
| 1341 | /* Put a 2 byte expression described by 'oper'. If this expression contains |
| 1342 | unresolved symbols, generate a 16-bit fixup. */ |
| 1343 | static void |
| 1344 | fixup16 (oper, mode, opmode) |
| 1345 | expressionS *oper; |
| 1346 | int mode; |
| 1347 | int opmode ATTRIBUTE_UNUSED; |
| 1348 | { |
| 1349 | char *f; |
| 1350 | |
| 1351 | f = frag_more (2); |
| 1352 | |
| 1353 | if (oper->X_op == O_constant) |
| 1354 | { |
| 1355 | if (!check_range (oper->X_add_number, mode)) |
| 1356 | { |
| 1357 | as_bad (_("Operand out of 16-bit range: `%ld'."), |
| 1358 | oper->X_add_number); |
| 1359 | } |
| 1360 | number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFF, 2); |
| 1361 | } |
| 1362 | else if (oper->X_op != O_register) |
| 1363 | { |
| 1364 | fixS *fixp; |
| 1365 | |
| 1366 | /* Now create a 16-bit fixup. */ |
| 1367 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2, |
| 1368 | oper, |
| 1369 | (mode & M6812_OP_JUMP_REL16 ? true : false), |
| 1370 | (mode & M6812_OP_JUMP_REL16 |
| 1371 | ? BFD_RELOC_16_PCREL : BFD_RELOC_16)); |
| 1372 | number_to_chars_bigendian (f, 0, 2); |
| 1373 | if (mode & M6812_OP_JUMP_REL16) |
| 1374 | fixp->fx_pcrel_adjust = 2; |
| 1375 | } |
| 1376 | else |
| 1377 | { |
| 1378 | as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op); |
| 1379 | } |
| 1380 | } |
| 1381 | \f |
| 1382 | /* 68HC11 and 68HC12 code generation. */ |
| 1383 | |
| 1384 | /* Translate the short branch/bsr instruction into a long branch. */ |
| 1385 | static unsigned char |
| 1386 | convert_branch (code) |
| 1387 | unsigned char code; |
| 1388 | { |
| 1389 | if (IS_OPCODE (code, M6812_BSR)) |
| 1390 | return M6812_JSR; |
| 1391 | else if (IS_OPCODE (code, M6811_BSR)) |
| 1392 | return M6811_JSR; |
| 1393 | else if (IS_OPCODE (code, M6811_BRA)) |
| 1394 | return (current_architecture & cpu6812) ? M6812_JMP : M6811_JMP; |
| 1395 | else |
| 1396 | as_fatal (_("Unexpected branch conversion with `%x'"), code); |
| 1397 | |
| 1398 | /* Keep gcc happy. */ |
| 1399 | return M6811_JSR; |
| 1400 | } |
| 1401 | |
| 1402 | /* Start a new insn that contains at least 'size' bytes. Record the |
| 1403 | line information of that insn in the dwarf2 debug sections. */ |
| 1404 | static char * |
| 1405 | m68hc11_new_insn (size) |
| 1406 | int size; |
| 1407 | { |
| 1408 | char *f; |
| 1409 | |
| 1410 | f = frag_more (size); |
| 1411 | |
| 1412 | dwarf2_emit_insn (size); |
| 1413 | |
| 1414 | return f; |
| 1415 | } |
| 1416 | |
| 1417 | /* Builds a jump instruction (bra, bcc, bsr). */ |
| 1418 | static void |
| 1419 | build_jump_insn (opcode, operands, nb_operands, jmp_mode) |
| 1420 | struct m68hc11_opcode *opcode; |
| 1421 | operand operands[]; |
| 1422 | int nb_operands; |
| 1423 | int jmp_mode; |
| 1424 | { |
| 1425 | unsigned char code; |
| 1426 | char *f; |
| 1427 | unsigned long n; |
| 1428 | |
| 1429 | /* The relative branch convertion is not supported for |
| 1430 | brclr and brset. */ |
| 1431 | assert ((opcode->format & M6811_OP_BITMASK) == 0); |
| 1432 | assert (nb_operands == 1); |
| 1433 | assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE); |
| 1434 | |
| 1435 | code = opcode->opcode; |
| 1436 | |
| 1437 | n = operands[0].exp.X_add_number; |
| 1438 | |
| 1439 | /* Turn into a long branch: |
| 1440 | - when force long branch option (and not for jbcc pseudos), |
| 1441 | - when jbcc and the constant is out of -128..127 range, |
| 1442 | - when branch optimization is allowed and branch out of range. */ |
| 1443 | if ((jmp_mode == 0 && flag_force_long_jumps) |
| 1444 | || (operands[0].exp.X_op == O_constant |
| 1445 | && (!check_range (n, opcode->format) && |
| 1446 | (jmp_mode == 1 || flag_fixed_branchs == 0)))) |
| 1447 | { |
| 1448 | if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR) |
| 1449 | { |
| 1450 | code = convert_branch (code); |
| 1451 | |
| 1452 | f = m68hc11_new_insn (1); |
| 1453 | number_to_chars_bigendian (f, code, 1); |
| 1454 | } |
| 1455 | else if (current_architecture & cpu6812) |
| 1456 | { |
| 1457 | /* 68HC12: translate the bcc into a lbcc. */ |
| 1458 | f = m68hc11_new_insn (2); |
| 1459 | number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); |
| 1460 | number_to_chars_bigendian (f + 1, code, 1); |
| 1461 | fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, |
| 1462 | M6812_OP_JUMP_REL16); |
| 1463 | return; |
| 1464 | } |
| 1465 | else |
| 1466 | { |
| 1467 | /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */ |
| 1468 | f = m68hc11_new_insn (3); |
| 1469 | code ^= 1; |
| 1470 | number_to_chars_bigendian (f, code, 1); |
| 1471 | number_to_chars_bigendian (f + 1, 3, 1); |
| 1472 | number_to_chars_bigendian (f + 2, M6811_JMP, 1); |
| 1473 | } |
| 1474 | fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16); |
| 1475 | return; |
| 1476 | } |
| 1477 | |
| 1478 | /* Branch with a constant that must fit in 8-bits. */ |
| 1479 | if (operands[0].exp.X_op == O_constant) |
| 1480 | { |
| 1481 | if (!check_range (n, opcode->format)) |
| 1482 | { |
| 1483 | as_bad (_("Operand out of range for a relative branch: `%ld'"), |
| 1484 | n); |
| 1485 | } |
| 1486 | else if (opcode->format & M6812_OP_JUMP_REL16) |
| 1487 | { |
| 1488 | f = m68hc11_new_insn (4); |
| 1489 | number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); |
| 1490 | number_to_chars_bigendian (f + 1, code, 1); |
| 1491 | number_to_chars_bigendian (f + 2, n & 0x0ffff, 2); |
| 1492 | } |
| 1493 | else |
| 1494 | { |
| 1495 | f = m68hc11_new_insn (2); |
| 1496 | number_to_chars_bigendian (f, code, 1); |
| 1497 | number_to_chars_bigendian (f + 1, n & 0x0FF, 1); |
| 1498 | } |
| 1499 | } |
| 1500 | else if (opcode->format & M6812_OP_JUMP_REL16) |
| 1501 | { |
| 1502 | f = m68hc11_new_insn (2); |
| 1503 | number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); |
| 1504 | number_to_chars_bigendian (f + 1, code, 1); |
| 1505 | fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, M6812_OP_JUMP_REL16); |
| 1506 | } |
| 1507 | else |
| 1508 | { |
| 1509 | char *opcode; |
| 1510 | |
| 1511 | /* Branch offset must fit in 8-bits, don't do some relax. */ |
| 1512 | if (jmp_mode == 0 && flag_fixed_branchs) |
| 1513 | { |
| 1514 | opcode = m68hc11_new_insn (1); |
| 1515 | number_to_chars_bigendian (opcode, code, 1); |
| 1516 | fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL); |
| 1517 | } |
| 1518 | |
| 1519 | /* bra/bsr made be changed into jmp/jsr. */ |
| 1520 | else if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR) |
| 1521 | { |
| 1522 | /* Allocate worst case storage. */ |
| 1523 | opcode = m68hc11_new_insn (3); |
| 1524 | number_to_chars_bigendian (opcode, code, 1); |
| 1525 | number_to_chars_bigendian (opcode + 1, 0, 1); |
| 1526 | frag_variant (rs_machine_dependent, 1, 1, |
| 1527 | ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF), |
| 1528 | operands[0].exp.X_add_symbol, (offsetT) n, |
| 1529 | opcode); |
| 1530 | } |
| 1531 | else if (current_architecture & cpu6812) |
| 1532 | { |
| 1533 | opcode = m68hc11_new_insn (2); |
| 1534 | number_to_chars_bigendian (opcode, code, 1); |
| 1535 | number_to_chars_bigendian (opcode + 1, 0, 1); |
| 1536 | frag_var (rs_machine_dependent, 2, 2, |
| 1537 | ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF), |
| 1538 | operands[0].exp.X_add_symbol, (offsetT) n, opcode); |
| 1539 | } |
| 1540 | else |
| 1541 | { |
| 1542 | opcode = m68hc11_new_insn (2); |
| 1543 | number_to_chars_bigendian (opcode, code, 1); |
| 1544 | number_to_chars_bigendian (opcode + 1, 0, 1); |
| 1545 | frag_var (rs_machine_dependent, 3, 3, |
| 1546 | ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF), |
| 1547 | operands[0].exp.X_add_symbol, (offsetT) n, opcode); |
| 1548 | } |
| 1549 | } |
| 1550 | } |
| 1551 | |
| 1552 | /* Builds a dbne/dbeq/tbne/tbeq instruction. */ |
| 1553 | static void |
| 1554 | build_dbranch_insn (opcode, operands, nb_operands, jmp_mode) |
| 1555 | struct m68hc11_opcode *opcode; |
| 1556 | operand operands[]; |
| 1557 | int nb_operands; |
| 1558 | int jmp_mode; |
| 1559 | { |
| 1560 | unsigned char code; |
| 1561 | char *f; |
| 1562 | unsigned long n; |
| 1563 | |
| 1564 | /* The relative branch convertion is not supported for |
| 1565 | brclr and brset. */ |
| 1566 | assert ((opcode->format & M6811_OP_BITMASK) == 0); |
| 1567 | assert (nb_operands == 2); |
| 1568 | assert (operands[0].reg1 != REG_NONE); |
| 1569 | |
| 1570 | code = opcode->opcode & 0x0FF; |
| 1571 | |
| 1572 | f = m68hc11_new_insn (1); |
| 1573 | number_to_chars_bigendian (f, code, 1); |
| 1574 | |
| 1575 | n = operands[1].exp.X_add_number; |
| 1576 | code = operands[0].reg1; |
| 1577 | |
| 1578 | if (operands[0].reg1 == REG_NONE || operands[0].reg1 == REG_CCR |
| 1579 | || operands[0].reg1 == REG_PC) |
| 1580 | as_bad (_("Invalid register for dbcc/tbcc instruction.")); |
| 1581 | |
| 1582 | if (opcode->format & M6812_OP_IBCC_MARKER) |
| 1583 | code |= 0x80; |
| 1584 | else if (opcode->format & M6812_OP_TBCC_MARKER) |
| 1585 | code |= 0x40; |
| 1586 | |
| 1587 | if (!(opcode->format & M6812_OP_EQ_MARKER)) |
| 1588 | code |= 0x20; |
| 1589 | |
| 1590 | /* Turn into a long branch: |
| 1591 | - when force long branch option (and not for jbcc pseudos), |
| 1592 | - when jdbcc and the constant is out of -256..255 range, |
| 1593 | - when branch optimization is allowed and branch out of range. */ |
| 1594 | if ((jmp_mode == 0 && flag_force_long_jumps) |
| 1595 | || (operands[1].exp.X_op == O_constant |
| 1596 | && (!check_range (n, M6812_OP_IBCC_MARKER) && |
| 1597 | (jmp_mode == 1 || flag_fixed_branchs == 0)))) |
| 1598 | { |
| 1599 | f = frag_more (2); |
| 1600 | code ^= 0x20; |
| 1601 | number_to_chars_bigendian (f, code, 1); |
| 1602 | number_to_chars_bigendian (f + 1, M6812_JMP, 1); |
| 1603 | fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16); |
| 1604 | return; |
| 1605 | } |
| 1606 | |
| 1607 | /* Branch with a constant that must fit in 9-bits. */ |
| 1608 | if (operands[1].exp.X_op == O_constant) |
| 1609 | { |
| 1610 | if (!check_range (n, M6812_OP_IBCC_MARKER)) |
| 1611 | { |
| 1612 | as_bad (_("Operand out of range for a relative branch: `%ld'"), |
| 1613 | n); |
| 1614 | } |
| 1615 | else |
| 1616 | { |
| 1617 | if ((long) n < 0) |
| 1618 | code |= 0x10; |
| 1619 | |
| 1620 | f = frag_more (2); |
| 1621 | number_to_chars_bigendian (f, code, 1); |
| 1622 | number_to_chars_bigendian (f + 1, n & 0x0FF, 1); |
| 1623 | } |
| 1624 | } |
| 1625 | else |
| 1626 | { |
| 1627 | /* Branch offset must fit in 8-bits, don't do some relax. */ |
| 1628 | if (jmp_mode == 0 && flag_fixed_branchs) |
| 1629 | { |
| 1630 | fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL); |
| 1631 | } |
| 1632 | |
| 1633 | else |
| 1634 | { |
| 1635 | f = frag_more (2); |
| 1636 | number_to_chars_bigendian (f, code, 1); |
| 1637 | number_to_chars_bigendian (f + 1, 0, 1); |
| 1638 | frag_var (rs_machine_dependent, 3, 3, |
| 1639 | ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF), |
| 1640 | operands[1].exp.X_add_symbol, (offsetT) n, f); |
| 1641 | } |
| 1642 | } |
| 1643 | } |
| 1644 | |
| 1645 | #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4) |
| 1646 | |
| 1647 | /* Assemble the post index byte for 68HC12 extended addressing modes. */ |
| 1648 | static int |
| 1649 | build_indexed_byte (op, format, move_insn) |
| 1650 | operand *op; |
| 1651 | int format ATTRIBUTE_UNUSED; |
| 1652 | int move_insn; |
| 1653 | { |
| 1654 | unsigned char byte = 0; |
| 1655 | char *f; |
| 1656 | int mode; |
| 1657 | long val; |
| 1658 | |
| 1659 | val = op->exp.X_add_number; |
| 1660 | mode = op->mode; |
| 1661 | if (mode & M6812_AUTO_INC_DEC) |
| 1662 | { |
| 1663 | byte = 0x20; |
| 1664 | if (mode & (M6812_POST_INC | M6812_POST_DEC)) |
| 1665 | byte |= 0x10; |
| 1666 | |
| 1667 | if (op->exp.X_op == O_constant) |
| 1668 | { |
| 1669 | if (!check_range (val, mode)) |
| 1670 | { |
| 1671 | as_bad (_("Increment/decrement value is out of range: `%ld'."), |
| 1672 | val); |
| 1673 | } |
| 1674 | if (mode & (M6812_POST_INC | M6812_PRE_INC)) |
| 1675 | byte |= (val - 1) & 0x07; |
| 1676 | else |
| 1677 | byte |= (8 - ((val) & 7)) | 0x8; |
| 1678 | } |
| 1679 | switch (op->reg1) |
| 1680 | { |
| 1681 | case REG_NONE: |
| 1682 | as_fatal (_("Expecting a register.")); |
| 1683 | |
| 1684 | case REG_X: |
| 1685 | byte |= 0; |
| 1686 | break; |
| 1687 | |
| 1688 | case REG_Y: |
| 1689 | byte |= 0x40; |
| 1690 | break; |
| 1691 | |
| 1692 | case REG_SP: |
| 1693 | byte |= 0x80; |
| 1694 | break; |
| 1695 | |
| 1696 | default: |
| 1697 | as_bad (_("Invalid register for post/pre increment.")); |
| 1698 | break; |
| 1699 | } |
| 1700 | |
| 1701 | f = frag_more (1); |
| 1702 | number_to_chars_bigendian (f, byte, 1); |
| 1703 | return 1; |
| 1704 | } |
| 1705 | |
| 1706 | if (mode & M6812_OP_IDX) |
| 1707 | { |
| 1708 | switch (op->reg1) |
| 1709 | { |
| 1710 | case REG_X: |
| 1711 | byte = 0; |
| 1712 | break; |
| 1713 | |
| 1714 | case REG_Y: |
| 1715 | byte = 1; |
| 1716 | break; |
| 1717 | |
| 1718 | case REG_SP: |
| 1719 | byte = 2; |
| 1720 | break; |
| 1721 | |
| 1722 | case REG_PC: |
| 1723 | byte = 3; |
| 1724 | break; |
| 1725 | |
| 1726 | default: |
| 1727 | as_bad (_("Invalid register.")); |
| 1728 | break; |
| 1729 | } |
| 1730 | if (op->exp.X_op == O_constant) |
| 1731 | { |
| 1732 | if (!check_range (val, M6812_OP_IDX)) |
| 1733 | { |
| 1734 | as_bad (_("Offset out of 16-bit range: %ld."), val); |
| 1735 | } |
| 1736 | |
| 1737 | if (move_insn && !(val >= -16 && val <= 15)) |
| 1738 | { |
| 1739 | as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."), |
| 1740 | val); |
| 1741 | return -1; |
| 1742 | } |
| 1743 | |
| 1744 | if (val >= -16 && val <= 15 && !(mode & M6812_OP_IDX_2)) |
| 1745 | { |
| 1746 | byte = byte << 6; |
| 1747 | byte |= val & 0x1f; |
| 1748 | f = frag_more (1); |
| 1749 | number_to_chars_bigendian (f, byte, 1); |
| 1750 | return 1; |
| 1751 | } |
| 1752 | else if (val >= -256 && val <= 255 && !(mode & M6812_OP_IDX_2)) |
| 1753 | { |
| 1754 | byte = byte << 3; |
| 1755 | byte |= 0xe0; |
| 1756 | if (val < 0) |
| 1757 | byte |= 0x1; |
| 1758 | f = frag_more (2); |
| 1759 | number_to_chars_bigendian (f, byte, 1); |
| 1760 | number_to_chars_bigendian (f + 1, val & 0x0FF, 1); |
| 1761 | return 2; |
| 1762 | } |
| 1763 | else |
| 1764 | { |
| 1765 | byte = byte << 3; |
| 1766 | if (mode & M6812_OP_IDX_2) |
| 1767 | byte |= 0xe3; |
| 1768 | else |
| 1769 | byte |= 0xe2; |
| 1770 | |
| 1771 | f = frag_more (3); |
| 1772 | number_to_chars_bigendian (f, byte, 1); |
| 1773 | number_to_chars_bigendian (f + 1, val & 0x0FFFF, 2); |
| 1774 | return 3; |
| 1775 | } |
| 1776 | } |
| 1777 | if (op->reg1 != REG_PC) |
| 1778 | { |
| 1779 | byte = (byte << 3) | 0xe2; |
| 1780 | f = frag_more (1); |
| 1781 | number_to_chars_bigendian (f, byte, 1); |
| 1782 | |
| 1783 | f = frag_more (2); |
| 1784 | fix_new_exp (frag_now, f - frag_now->fr_literal, 2, |
| 1785 | &op->exp, false, BFD_RELOC_16); |
| 1786 | number_to_chars_bigendian (f, 0, 2); |
| 1787 | } |
| 1788 | else |
| 1789 | { |
| 1790 | f = frag_more (1); |
| 1791 | number_to_chars_bigendian (f, byte, 1); |
| 1792 | frag_var (rs_machine_dependent, 2, 2, |
| 1793 | ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF), |
| 1794 | op->exp.X_add_symbol, |
| 1795 | op->exp.X_add_number, f); |
| 1796 | } |
| 1797 | return 3; |
| 1798 | } |
| 1799 | |
| 1800 | if (mode & M6812_OP_REG) |
| 1801 | { |
| 1802 | if (mode & M6812_OP_IDX_2) |
| 1803 | { |
| 1804 | if (op->reg1 != REG_D) |
| 1805 | as_bad (_("Expecting register D for indexed indirect mode.")); |
| 1806 | if (move_insn) |
| 1807 | as_bad (_("Indexed indirect mode is not allowed for movb/movw.")); |
| 1808 | |
| 1809 | byte = 0xE7; |
| 1810 | } |
| 1811 | else |
| 1812 | { |
| 1813 | switch (op->reg1) |
| 1814 | { |
| 1815 | case REG_A: |
| 1816 | byte = 0xE4; |
| 1817 | break; |
| 1818 | |
| 1819 | case REG_B: |
| 1820 | byte = 0xE5; |
| 1821 | break; |
| 1822 | |
| 1823 | default: |
| 1824 | as_bad (_("Invalid accumulator register.")); |
| 1825 | |
| 1826 | case REG_D: |
| 1827 | byte = 0xE6; |
| 1828 | break; |
| 1829 | } |
| 1830 | } |
| 1831 | switch (op->reg2) |
| 1832 | { |
| 1833 | case REG_X: |
| 1834 | break; |
| 1835 | |
| 1836 | case REG_Y: |
| 1837 | byte |= (1 << 3); |
| 1838 | break; |
| 1839 | |
| 1840 | case REG_SP: |
| 1841 | byte |= (2 << 3); |
| 1842 | break; |
| 1843 | |
| 1844 | case REG_PC: |
| 1845 | byte |= (3 << 3); |
| 1846 | break; |
| 1847 | |
| 1848 | default: |
| 1849 | as_bad (_("Invalid indexed register.")); |
| 1850 | break; |
| 1851 | } |
| 1852 | f = frag_more (1); |
| 1853 | number_to_chars_bigendian (f, byte, 1); |
| 1854 | return 1; |
| 1855 | } |
| 1856 | |
| 1857 | as_fatal (_("Addressing mode not implemented yet.")); |
| 1858 | return 0; |
| 1859 | } |
| 1860 | |
| 1861 | /* Assemble the 68HC12 register mode byte. */ |
| 1862 | static int |
| 1863 | build_reg_mode (op, format) |
| 1864 | operand *op; |
| 1865 | int format; |
| 1866 | { |
| 1867 | unsigned char byte; |
| 1868 | char *f; |
| 1869 | |
| 1870 | if (format & M6812_OP_SEX_MARKER |
| 1871 | && op->reg1 != REG_A && op->reg1 != REG_B && op->reg1 != REG_CCR) |
| 1872 | as_bad (_("Invalid source register for this instruction, use 'tfr'.")); |
| 1873 | else if (op->reg1 == REG_NONE || op->reg1 == REG_PC) |
| 1874 | as_bad (_("Invalid source register.")); |
| 1875 | |
| 1876 | if (format & M6812_OP_SEX_MARKER |
| 1877 | && op->reg2 != REG_D |
| 1878 | && op->reg2 != REG_X && op->reg2 != REG_Y && op->reg2 != REG_SP) |
| 1879 | as_bad (_("Invalid destination register for this instruction, use 'tfr'.")); |
| 1880 | else if (op->reg2 == REG_NONE || op->reg2 == REG_PC) |
| 1881 | as_bad (_("Invalid destination register.")); |
| 1882 | |
| 1883 | byte = (op->reg1 << 4) | (op->reg2); |
| 1884 | if (format & M6812_OP_EXG_MARKER) |
| 1885 | byte |= 0x80; |
| 1886 | |
| 1887 | f = frag_more (1); |
| 1888 | number_to_chars_bigendian (f, byte, 1); |
| 1889 | return 1; |
| 1890 | } |
| 1891 | |
| 1892 | /* build_insn takes a pointer to the opcode entry in the opcode table, |
| 1893 | the array of operand expressions and builds the correspding instruction. |
| 1894 | This operation only deals with non relative jumps insn (need special |
| 1895 | handling). */ |
| 1896 | static void |
| 1897 | build_insn (opcode, operands, nb_operands) |
| 1898 | struct m68hc11_opcode *opcode; |
| 1899 | operand operands[]; |
| 1900 | int nb_operands ATTRIBUTE_UNUSED; |
| 1901 | { |
| 1902 | int i; |
| 1903 | char *f; |
| 1904 | long format; |
| 1905 | int move_insn = 0; |
| 1906 | |
| 1907 | /* Put the page code instruction if there is one. */ |
| 1908 | format = opcode->format; |
| 1909 | if (format & OP_EXTENDED) |
| 1910 | { |
| 1911 | int page_code; |
| 1912 | |
| 1913 | f = m68hc11_new_insn (2); |
| 1914 | if (format & M6811_OP_PAGE2) |
| 1915 | page_code = M6811_OPCODE_PAGE2; |
| 1916 | else if (format & M6811_OP_PAGE3) |
| 1917 | page_code = M6811_OPCODE_PAGE3; |
| 1918 | else |
| 1919 | page_code = M6811_OPCODE_PAGE4; |
| 1920 | |
| 1921 | number_to_chars_bigendian (f, page_code, 1); |
| 1922 | f++; |
| 1923 | } |
| 1924 | else |
| 1925 | f = m68hc11_new_insn (1); |
| 1926 | |
| 1927 | number_to_chars_bigendian (f, opcode->opcode, 1); |
| 1928 | |
| 1929 | i = 0; |
| 1930 | |
| 1931 | /* The 68HC12 movb and movw instructions are special. We have to handle |
| 1932 | them in a special way. */ |
| 1933 | if (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) |
| 1934 | { |
| 1935 | move_insn = 1; |
| 1936 | if (format & M6812_OP_IDX) |
| 1937 | { |
| 1938 | build_indexed_byte (&operands[0], format, 1); |
| 1939 | i = 1; |
| 1940 | format &= ~M6812_OP_IDX; |
| 1941 | } |
| 1942 | if (format & M6812_OP_IDX_P2) |
| 1943 | { |
| 1944 | build_indexed_byte (&operands[1], format, 1); |
| 1945 | i = 0; |
| 1946 | format &= ~M6812_OP_IDX_P2; |
| 1947 | } |
| 1948 | } |
| 1949 | |
| 1950 | if (format & (M6811_OP_DIRECT | M6811_OP_IMM8)) |
| 1951 | { |
| 1952 | fixup8 (&operands[i].exp, |
| 1953 | format & (M6811_OP_DIRECT | M6811_OP_IMM8 | M6812_OP_TRAP_ID), |
| 1954 | operands[i].mode); |
| 1955 | i++; |
| 1956 | } |
| 1957 | else if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) |
| 1958 | { |
| 1959 | fixup16 (&operands[i].exp, format & (M6811_OP_IMM16 | M6811_OP_IND16), |
| 1960 | operands[i].mode); |
| 1961 | i++; |
| 1962 | } |
| 1963 | else if (format & (M6811_OP_IX | M6811_OP_IY)) |
| 1964 | { |
| 1965 | if ((format & M6811_OP_IX) && (operands[0].reg1 != REG_X)) |
| 1966 | as_bad (_("Invalid indexed register, expecting register X.")); |
| 1967 | if ((format & M6811_OP_IY) && (operands[0].reg1 != REG_Y)) |
| 1968 | as_bad (_("Invalid indexed register, expecting register Y.")); |
| 1969 | |
| 1970 | fixup8 (&operands[0].exp, M6811_OP_IX, operands[0].mode); |
| 1971 | i = 1; |
| 1972 | } |
| 1973 | else if (format & |
| 1974 | (M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1 | M6812_OP_D_IDX)) |
| 1975 | { |
| 1976 | build_indexed_byte (&operands[i], format, move_insn); |
| 1977 | i++; |
| 1978 | } |
| 1979 | else if (format & M6812_OP_REG && current_architecture & cpu6812) |
| 1980 | { |
| 1981 | build_reg_mode (&operands[i], format); |
| 1982 | i++; |
| 1983 | } |
| 1984 | if (format & M6811_OP_BITMASK) |
| 1985 | { |
| 1986 | fixup8 (&operands[i].exp, M6811_OP_BITMASK, operands[i].mode); |
| 1987 | i++; |
| 1988 | } |
| 1989 | if (format & M6811_OP_JUMP_REL) |
| 1990 | { |
| 1991 | fixup8 (&operands[i].exp, M6811_OP_JUMP_REL, operands[i].mode); |
| 1992 | } |
| 1993 | else if (format & M6812_OP_IND16_P2) |
| 1994 | { |
| 1995 | fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode); |
| 1996 | } |
| 1997 | } |
| 1998 | \f |
| 1999 | /* Opcode identification and operand analysis. */ |
| 2000 | |
| 2001 | /* find() gets a pointer to an entry in the opcode table. It must look at all |
| 2002 | opcodes with the same name and use the operands to choose the correct |
| 2003 | opcode. Returns the opcode pointer if there was a match and 0 if none. */ |
| 2004 | static struct m68hc11_opcode * |
| 2005 | find (opc, operands, nb_operands) |
| 2006 | struct m68hc11_opcode_def *opc; |
| 2007 | operand operands[]; |
| 2008 | int nb_operands; |
| 2009 | { |
| 2010 | int i, match, pos; |
| 2011 | struct m68hc11_opcode *opcode; |
| 2012 | struct m68hc11_opcode *op_indirect; |
| 2013 | |
| 2014 | op_indirect = 0; |
| 2015 | opcode = opc->opcode; |
| 2016 | |
| 2017 | /* Now search the opcode table table for one with operands |
| 2018 | that matches what we've got. We're only done if the operands matched so |
| 2019 | far AND there are no more to check. */ |
| 2020 | for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++) |
| 2021 | { |
| 2022 | int poss_indirect = 0; |
| 2023 | long format = opcode->format; |
| 2024 | int expect; |
| 2025 | |
| 2026 | expect = 0; |
| 2027 | if (opcode->format & M6811_OP_MASK) |
| 2028 | expect++; |
| 2029 | if (opcode->format & M6811_OP_BITMASK) |
| 2030 | expect++; |
| 2031 | if (opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) |
| 2032 | expect++; |
| 2033 | if (opcode->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) |
| 2034 | expect++; |
| 2035 | |
| 2036 | for (i = 0; expect == nb_operands && i < nb_operands; i++) |
| 2037 | { |
| 2038 | int mode = operands[i].mode; |
| 2039 | |
| 2040 | if (mode & M6811_OP_IMM16) |
| 2041 | { |
| 2042 | if (format & |
| 2043 | (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK)) |
| 2044 | continue; |
| 2045 | break; |
| 2046 | } |
| 2047 | if (mode == M6811_OP_DIRECT) |
| 2048 | { |
| 2049 | if (format & M6811_OP_DIRECT) |
| 2050 | continue; |
| 2051 | |
| 2052 | /* If the operand is a page 0 operand, remember a |
| 2053 | possible <abs-16> addressing mode. We mark |
| 2054 | this and continue to check other operands. */ |
| 2055 | if (format & M6811_OP_IND16 |
| 2056 | && flag_strict_direct_addressing && op_indirect == 0) |
| 2057 | { |
| 2058 | poss_indirect = 1; |
| 2059 | continue; |
| 2060 | } |
| 2061 | break; |
| 2062 | } |
| 2063 | if (mode & M6811_OP_IND16) |
| 2064 | { |
| 2065 | if (i == 0 && (format & M6811_OP_IND16) != 0) |
| 2066 | continue; |
| 2067 | if (i != 0 && (format & M6812_OP_IND16_P2) != 0) |
| 2068 | continue; |
| 2069 | if (i == 0 && (format & M6811_OP_BITMASK)) |
| 2070 | break; |
| 2071 | } |
| 2072 | if (mode & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) |
| 2073 | { |
| 2074 | if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) |
| 2075 | continue; |
| 2076 | } |
| 2077 | if (mode & M6812_OP_REG) |
| 2078 | { |
| 2079 | if (i == 0 |
| 2080 | && (format & M6812_OP_REG) |
| 2081 | && (operands[i].reg2 == REG_NONE)) |
| 2082 | continue; |
| 2083 | if (i == 0 |
| 2084 | && (format & M6812_OP_REG) |
| 2085 | && (format & M6812_OP_REG_2) |
| 2086 | && (operands[i].reg2 != REG_NONE)) |
| 2087 | continue; |
| 2088 | if (i == 0 |
| 2089 | && (format & M6812_OP_IDX) |
| 2090 | && (operands[i].reg2 != REG_NONE)) |
| 2091 | continue; |
| 2092 | if (i == 0 |
| 2093 | && (format & M6812_OP_D_IDX)) |
| 2094 | continue; |
| 2095 | if (i == 0 |
| 2096 | && (format & M6812_OP_IDX) |
| 2097 | && (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))) |
| 2098 | continue; |
| 2099 | if (i == 1 |
| 2100 | && (format & M6812_OP_IDX_P2)) |
| 2101 | continue; |
| 2102 | break; |
| 2103 | } |
| 2104 | if (mode & M6812_OP_IDX) |
| 2105 | { |
| 2106 | if (format & M6811_OP_IX && operands[i].reg1 == REG_X) |
| 2107 | continue; |
| 2108 | if (format & M6811_OP_IY && operands[i].reg1 == REG_Y) |
| 2109 | continue; |
| 2110 | if (i == 0 |
| 2111 | && format & (M6812_OP_IDX | M6812_OP_IDX_1 | M6812_OP_IDX_2) |
| 2112 | && (operands[i].reg1 == REG_X |
| 2113 | || operands[i].reg1 == REG_Y |
| 2114 | || operands[i].reg1 == REG_SP |
| 2115 | || operands[i].reg1 == REG_PC)) |
| 2116 | continue; |
| 2117 | if (i == 1 && format & M6812_OP_IDX_P2) |
| 2118 | continue; |
| 2119 | } |
| 2120 | if (mode & M6812_AUTO_INC_DEC) |
| 2121 | { |
| 2122 | if (i == 0 |
| 2123 | && format & (M6812_OP_IDX | M6812_OP_IDX_1 | |
| 2124 | M6812_OP_IDX_2)) |
| 2125 | continue; |
| 2126 | if (i == 1 && format & M6812_OP_IDX_P2) |
| 2127 | continue; |
| 2128 | } |
| 2129 | break; |
| 2130 | } |
| 2131 | match = i == nb_operands; |
| 2132 | |
| 2133 | /* Operands are ok but an operand uses page 0 addressing mode |
| 2134 | while the insn supports abs-16 mode. Keep a reference to this |
| 2135 | insns in case there is no insn supporting page 0 addressing. */ |
| 2136 | if (match && poss_indirect) |
| 2137 | { |
| 2138 | op_indirect = opcode; |
| 2139 | match = 0; |
| 2140 | } |
| 2141 | if (match) |
| 2142 | break; |
| 2143 | } |
| 2144 | |
| 2145 | /* Page 0 addressing is used but not supported by any insn. |
| 2146 | If absolute addresses are supported, we use that insn. */ |
| 2147 | if (match == 0 && op_indirect) |
| 2148 | { |
| 2149 | opcode = op_indirect; |
| 2150 | match = 1; |
| 2151 | } |
| 2152 | |
| 2153 | if (!match) |
| 2154 | { |
| 2155 | return (0); |
| 2156 | } |
| 2157 | |
| 2158 | return opcode; |
| 2159 | } |
| 2160 | |
| 2161 | /* Find the real opcode and its associated operands. We use a progressive |
| 2162 | approach here. On entry, 'opc' points to the first opcode in the |
| 2163 | table that matches the opcode name in the source line. We try to |
| 2164 | isolate an operand, find a possible match in the opcode table. |
| 2165 | We isolate another operand if no match were found. The table 'operands' |
| 2166 | is filled while operands are recognized. |
| 2167 | |
| 2168 | Returns the opcode pointer that matches the opcode name in the |
| 2169 | source line and the associated operands. */ |
| 2170 | static struct m68hc11_opcode * |
| 2171 | find_opcode (opc, operands, nb_operands) |
| 2172 | struct m68hc11_opcode_def *opc; |
| 2173 | operand operands[]; |
| 2174 | int *nb_operands; |
| 2175 | { |
| 2176 | struct m68hc11_opcode *opcode; |
| 2177 | int i; |
| 2178 | |
| 2179 | if (opc->max_operands == 0) |
| 2180 | { |
| 2181 | *nb_operands = 0; |
| 2182 | return opc->opcode; |
| 2183 | } |
| 2184 | |
| 2185 | for (i = 0; i < opc->max_operands;) |
| 2186 | { |
| 2187 | int result; |
| 2188 | |
| 2189 | result = get_operand (&operands[i], i, opc->format); |
| 2190 | if (result <= 0) |
| 2191 | return 0; |
| 2192 | |
| 2193 | /* Special case where the bitmask of the bclr/brclr |
| 2194 | instructions is not introduced by #. |
| 2195 | Example: bclr 3,x $80. */ |
| 2196 | if (i == 1 && (opc->format & M6811_OP_BITMASK) |
| 2197 | && (operands[i].mode & M6811_OP_IND16)) |
| 2198 | { |
| 2199 | operands[i].mode = M6811_OP_IMM16; |
| 2200 | } |
| 2201 | |
| 2202 | i += result; |
| 2203 | *nb_operands = i; |
| 2204 | if (i >= opc->min_operands) |
| 2205 | { |
| 2206 | opcode = find (opc, operands, i); |
| 2207 | if (opcode) |
| 2208 | return opcode; |
| 2209 | } |
| 2210 | |
| 2211 | if (*input_line_pointer == ',') |
| 2212 | input_line_pointer++; |
| 2213 | } |
| 2214 | |
| 2215 | return 0; |
| 2216 | } |
| 2217 | |
| 2218 | #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \ |
| 2219 | | M6812_OP_DBCC_MARKER \ |
| 2220 | | M6812_OP_IBCC_MARKER) |
| 2221 | \f |
| 2222 | /* Gas line assembler entry point. */ |
| 2223 | |
| 2224 | /* This is the main entry point for the machine-dependent assembler. str |
| 2225 | points to a machine-dependent instruction. This function is supposed to |
| 2226 | emit the frags/bytes it assembles to. */ |
| 2227 | void |
| 2228 | md_assemble (str) |
| 2229 | char *str; |
| 2230 | { |
| 2231 | struct m68hc11_opcode_def *opc; |
| 2232 | struct m68hc11_opcode *opcode; |
| 2233 | |
| 2234 | unsigned char *op_start, *save; |
| 2235 | unsigned char *op_end; |
| 2236 | char name[20]; |
| 2237 | int nlen = 0; |
| 2238 | operand operands[M6811_MAX_OPERANDS]; |
| 2239 | int nb_operands; |
| 2240 | int branch_optimize = 0; |
| 2241 | int alias_id = -1; |
| 2242 | |
| 2243 | /* Drop leading whitespace. */ |
| 2244 | while (*str == ' ') |
| 2245 | str++; |
| 2246 | |
| 2247 | /* Find the opcode end and get the opcode in 'name'. The opcode is forced |
| 2248 | lower case (the opcode table only has lower case op-codes). */ |
| 2249 | for (op_start = op_end = (unsigned char *) (str); |
| 2250 | *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' '; |
| 2251 | op_end++) |
| 2252 | { |
| 2253 | name[nlen] = TOLOWER (op_start[nlen]); |
| 2254 | nlen++; |
| 2255 | } |
| 2256 | name[nlen] = 0; |
| 2257 | |
| 2258 | if (nlen == 0) |
| 2259 | { |
| 2260 | as_bad (_("No instruction or missing opcode.")); |
| 2261 | return; |
| 2262 | } |
| 2263 | |
| 2264 | /* Find the opcode definition given its name. */ |
| 2265 | opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); |
| 2266 | |
| 2267 | /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are |
| 2268 | pseudo insns for relative branch. For these branchs, we always |
| 2269 | optimize them (turned into absolute branchs) even if --short-branchs |
| 2270 | is given. */ |
| 2271 | if (opc == NULL && name[0] == 'j' && name[1] == 'b') |
| 2272 | { |
| 2273 | opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, &name[1]); |
| 2274 | if (opc |
| 2275 | && (!(opc->format & M6811_OP_JUMP_REL) |
| 2276 | || (opc->format & M6811_OP_BITMASK))) |
| 2277 | opc = 0; |
| 2278 | if (opc) |
| 2279 | branch_optimize = 1; |
| 2280 | } |
| 2281 | |
| 2282 | /* The following test should probably be removed. This is not conform |
| 2283 | to Motorola assembler specs. */ |
| 2284 | if (opc == NULL && flag_mri) |
| 2285 | { |
| 2286 | if (*op_end == ' ' || *op_end == '\t') |
| 2287 | { |
| 2288 | while (*op_end == ' ' || *op_end == '\t') |
| 2289 | op_end++; |
| 2290 | |
| 2291 | if (nlen < 19 |
| 2292 | && (*op_end && |
| 2293 | (is_end_of_line[op_end[1]] |
| 2294 | || op_end[1] == ' ' || op_end[1] == '\t' |
| 2295 | || !ISALNUM (op_end[1]))) |
| 2296 | && (*op_end == 'a' || *op_end == 'b' |
| 2297 | || *op_end == 'A' || *op_end == 'B' |
| 2298 | || *op_end == 'd' || *op_end == 'D' |
| 2299 | || *op_end == 'x' || *op_end == 'X' |
| 2300 | || *op_end == 'y' || *op_end == 'Y')) |
| 2301 | { |
| 2302 | name[nlen++] = TOLOWER (*op_end++); |
| 2303 | name[nlen] = 0; |
| 2304 | opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, |
| 2305 | name); |
| 2306 | } |
| 2307 | } |
| 2308 | } |
| 2309 | |
| 2310 | /* Identify a possible instruction alias. There are some on the |
| 2311 | 68HC12 to emulate a few 68HC11 instructions. */ |
| 2312 | if (opc == NULL && (current_architecture & cpu6812)) |
| 2313 | { |
| 2314 | int i; |
| 2315 | |
| 2316 | for (i = 0; i < m68hc12_num_alias; i++) |
| 2317 | if (strcmp (m68hc12_alias[i].name, name) == 0) |
| 2318 | { |
| 2319 | alias_id = i; |
| 2320 | break; |
| 2321 | } |
| 2322 | } |
| 2323 | if (opc == NULL && alias_id < 0) |
| 2324 | { |
| 2325 | as_bad (_("Opcode `%s' is not recognized."), name); |
| 2326 | return; |
| 2327 | } |
| 2328 | save = input_line_pointer; |
| 2329 | input_line_pointer = op_end; |
| 2330 | |
| 2331 | if (opc) |
| 2332 | { |
| 2333 | opc->used++; |
| 2334 | opcode = find_opcode (opc, operands, &nb_operands); |
| 2335 | } |
| 2336 | else |
| 2337 | opcode = 0; |
| 2338 | |
| 2339 | if ((opcode || alias_id >= 0) && !flag_mri) |
| 2340 | { |
| 2341 | char *p = input_line_pointer; |
| 2342 | |
| 2343 | while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r') |
| 2344 | p++; |
| 2345 | |
| 2346 | if (*p != '\n' && *p) |
| 2347 | as_bad (_("Garbage at end of instruction: `%s'."), p); |
| 2348 | } |
| 2349 | |
| 2350 | input_line_pointer = save; |
| 2351 | |
| 2352 | if (alias_id >= 0) |
| 2353 | { |
| 2354 | char *f = m68hc11_new_insn (m68hc12_alias[alias_id].size); |
| 2355 | |
| 2356 | number_to_chars_bigendian (f, m68hc12_alias[alias_id].code1, 1); |
| 2357 | if (m68hc12_alias[alias_id].size > 1) |
| 2358 | number_to_chars_bigendian (f + 1, m68hc12_alias[alias_id].code2, 1); |
| 2359 | |
| 2360 | return; |
| 2361 | } |
| 2362 | |
| 2363 | /* Opcode is known but does not have valid operands. Print out the |
| 2364 | syntax for this opcode. */ |
| 2365 | if (opcode == 0) |
| 2366 | { |
| 2367 | if (flag_print_insn_syntax) |
| 2368 | print_insn_format (name); |
| 2369 | |
| 2370 | as_bad (_("Invalid operand for `%s'"), name); |
| 2371 | return; |
| 2372 | } |
| 2373 | |
| 2374 | /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is |
| 2375 | relative and must be in the range -256..255 (9-bits). */ |
| 2376 | if ((opcode->format & M6812_XBCC_MARKER) |
| 2377 | && (opcode->format & M6811_OP_JUMP_REL)) |
| 2378 | build_dbranch_insn (opcode, operands, nb_operands, branch_optimize); |
| 2379 | |
| 2380 | /* Relative jumps instructions are taken care of separately. We have to make |
| 2381 | sure that the relative branch is within the range -128..127. If it's out |
| 2382 | of range, the instructions are changed into absolute instructions. |
| 2383 | This is not supported for the brset and brclr instructions. */ |
| 2384 | else if ((opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) |
| 2385 | && !(opcode->format & M6811_OP_BITMASK)) |
| 2386 | build_jump_insn (opcode, operands, nb_operands, branch_optimize); |
| 2387 | else |
| 2388 | build_insn (opcode, operands, nb_operands); |
| 2389 | } |
| 2390 | \f |
| 2391 | /* Relocation, relaxation and frag conversions. */ |
| 2392 | long |
| 2393 | md_pcrel_from_section (fixp, sec) |
| 2394 | fixS *fixp; |
| 2395 | segT sec; |
| 2396 | { |
| 2397 | int adjust; |
| 2398 | if (fixp->fx_addsy != (symbolS *) NULL |
| 2399 | && (!S_IS_DEFINED (fixp->fx_addsy) |
| 2400 | || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) |
| 2401 | return 0; |
| 2402 | |
| 2403 | adjust = fixp->fx_pcrel_adjust; |
| 2404 | return fixp->fx_frag->fr_address + fixp->fx_where + adjust; |
| 2405 | } |
| 2406 | |
| 2407 | /* If while processing a fixup, a reloc really needs to be created |
| 2408 | then it is done here. */ |
| 2409 | arelent * |
| 2410 | tc_gen_reloc (section, fixp) |
| 2411 | asection *section; |
| 2412 | fixS *fixp; |
| 2413 | { |
| 2414 | arelent *reloc; |
| 2415 | |
| 2416 | reloc = (arelent *) xmalloc (sizeof (arelent)); |
| 2417 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 2418 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 2419 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 2420 | if (fixp->fx_r_type == 0) |
| 2421 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); |
| 2422 | else |
| 2423 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
| 2424 | if (reloc->howto == (reloc_howto_type *) NULL) |
| 2425 | { |
| 2426 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 2427 | _("Relocation %d is not supported by object file format."), |
| 2428 | (int) fixp->fx_r_type); |
| 2429 | return NULL; |
| 2430 | } |
| 2431 | |
| 2432 | if (!fixp->fx_pcrel) |
| 2433 | reloc->addend = fixp->fx_addnumber; |
| 2434 | else |
| 2435 | reloc->addend = (section->vma |
| 2436 | + (fixp->fx_pcrel_adjust == 64 |
| 2437 | ? -1 : fixp->fx_pcrel_adjust) |
| 2438 | + fixp->fx_addnumber |
| 2439 | + md_pcrel_from_section (fixp, section)); |
| 2440 | return reloc; |
| 2441 | } |
| 2442 | |
| 2443 | void |
| 2444 | md_convert_frag (abfd, sec, fragP) |
| 2445 | bfd *abfd ATTRIBUTE_UNUSED; |
| 2446 | asection *sec ATTRIBUTE_UNUSED; |
| 2447 | fragS *fragP; |
| 2448 | { |
| 2449 | fixS *fixp; |
| 2450 | long value; |
| 2451 | long disp; |
| 2452 | char *buffer_address = fragP->fr_literal; |
| 2453 | |
| 2454 | /* Address in object code of the displacement. */ |
| 2455 | register int object_address = fragP->fr_fix + fragP->fr_address; |
| 2456 | |
| 2457 | buffer_address += fragP->fr_fix; |
| 2458 | |
| 2459 | /* The displacement of the address, from current location. */ |
| 2460 | value = S_GET_VALUE (fragP->fr_symbol); |
| 2461 | disp = (value + fragP->fr_offset) - object_address; |
| 2462 | |
| 2463 | switch (fragP->fr_subtype) |
| 2464 | { |
| 2465 | case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE): |
| 2466 | fragP->fr_opcode[1] = disp; |
| 2467 | break; |
| 2468 | |
| 2469 | case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD): |
| 2470 | /* This relax is only for bsr and bra. */ |
| 2471 | assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) |
| 2472 | || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) |
| 2473 | || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); |
| 2474 | |
| 2475 | fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]); |
| 2476 | |
| 2477 | fix_new (fragP, fragP->fr_fix - 1, 2, |
| 2478 | fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); |
| 2479 | fragP->fr_fix += 1; |
| 2480 | break; |
| 2481 | |
| 2482 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE): |
| 2483 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_BYTE): |
| 2484 | fragP->fr_opcode[1] = disp; |
| 2485 | break; |
| 2486 | |
| 2487 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD): |
| 2488 | /* Invert branch. */ |
| 2489 | fragP->fr_opcode[0] ^= 1; |
| 2490 | fragP->fr_opcode[1] = 3; /* Branch offset. */ |
| 2491 | buffer_address[0] = M6811_JMP; |
| 2492 | fix_new (fragP, fragP->fr_fix + 1, 2, |
| 2493 | fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); |
| 2494 | fragP->fr_fix += 3; |
| 2495 | break; |
| 2496 | |
| 2497 | case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD): |
| 2498 | /* Translate branch into a long branch. */ |
| 2499 | fragP->fr_opcode[1] = fragP->fr_opcode[0]; |
| 2500 | fragP->fr_opcode[0] = M6811_OPCODE_PAGE2; |
| 2501 | |
| 2502 | fixp = fix_new (fragP, fragP->fr_fix, 2, |
| 2503 | fragP->fr_symbol, fragP->fr_offset, 1, |
| 2504 | BFD_RELOC_16_PCREL); |
| 2505 | fixp->fx_pcrel_adjust = 2; |
| 2506 | fragP->fr_fix += 2; |
| 2507 | break; |
| 2508 | |
| 2509 | case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5): |
| 2510 | fragP->fr_opcode[0] = fragP->fr_opcode[0] << 6; |
| 2511 | if ((fragP->fr_opcode[0] & 0x0ff) == 0x0c0) |
| 2512 | fragP->fr_opcode[0] |= disp & 0x1f; |
| 2513 | else |
| 2514 | fragP->fr_opcode[0] |= value & 0x1f; |
| 2515 | break; |
| 2516 | |
| 2517 | case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9): |
| 2518 | fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3); |
| 2519 | fragP->fr_opcode[0] |= 0xE0; |
| 2520 | fix_new (fragP, fragP->fr_fix, 1, |
| 2521 | fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_8); |
| 2522 | fragP->fr_fix += 1; |
| 2523 | break; |
| 2524 | |
| 2525 | case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16): |
| 2526 | fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3); |
| 2527 | fragP->fr_opcode[0] |= 0xe2; |
| 2528 | if ((fragP->fr_opcode[0] & 0x0ff) == 0x0fa) |
| 2529 | { |
| 2530 | fixp = fix_new (fragP, fragP->fr_fix, 2, |
| 2531 | fragP->fr_symbol, fragP->fr_offset, |
| 2532 | 1, BFD_RELOC_16_PCREL); |
| 2533 | fixp->fx_pcrel_adjust = 2; |
| 2534 | } |
| 2535 | else |
| 2536 | { |
| 2537 | fix_new (fragP, fragP->fr_fix, 2, |
| 2538 | fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); |
| 2539 | } |
| 2540 | fragP->fr_fix += 2; |
| 2541 | break; |
| 2542 | |
| 2543 | case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE): |
| 2544 | if (disp < 0) |
| 2545 | fragP->fr_opcode[0] |= 0x10; |
| 2546 | |
| 2547 | fragP->fr_opcode[1] = disp & 0x0FF; |
| 2548 | break; |
| 2549 | |
| 2550 | case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD): |
| 2551 | /* Invert branch. */ |
| 2552 | fragP->fr_opcode[0] ^= 0x20; |
| 2553 | fragP->fr_opcode[1] = 3; /* Branch offset. */ |
| 2554 | buffer_address[0] = M6812_JMP; |
| 2555 | fix_new (fragP, fragP->fr_fix + 1, 2, |
| 2556 | fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); |
| 2557 | fragP->fr_fix += 3; |
| 2558 | break; |
| 2559 | |
| 2560 | default: |
| 2561 | break; |
| 2562 | } |
| 2563 | } |
| 2564 | |
| 2565 | /* On an ELF system, we can't relax a weak symbol. The weak symbol |
| 2566 | can be overridden at final link time by a non weak symbol. We can |
| 2567 | relax externally visible symbol because there is no shared library |
| 2568 | and such symbol can't be overridden (unless they are weak). */ |
| 2569 | static int |
| 2570 | relaxable_symbol (symbol) |
| 2571 | symbolS *symbol; |
| 2572 | { |
| 2573 | return ! S_IS_WEAK (symbol); |
| 2574 | } |
| 2575 | |
| 2576 | /* Force truly undefined symbols to their maximum size, and generally set up |
| 2577 | the frag list to be relaxed. */ |
| 2578 | int |
| 2579 | md_estimate_size_before_relax (fragP, segment) |
| 2580 | fragS *fragP; |
| 2581 | asection *segment; |
| 2582 | { |
| 2583 | if (RELAX_LENGTH (fragP->fr_subtype) == STATE_UNDF) |
| 2584 | { |
| 2585 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
| 2586 | || !relaxable_symbol (fragP->fr_symbol)) |
| 2587 | { |
| 2588 | /* Non-relaxable cases. */ |
| 2589 | int old_fr_fix; |
| 2590 | char *buffer_address; |
| 2591 | |
| 2592 | old_fr_fix = fragP->fr_fix; |
| 2593 | buffer_address = fragP->fr_fix + fragP->fr_literal; |
| 2594 | |
| 2595 | switch (RELAX_STATE (fragP->fr_subtype)) |
| 2596 | { |
| 2597 | case STATE_PC_RELATIVE: |
| 2598 | |
| 2599 | /* This relax is only for bsr and bra. */ |
| 2600 | assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) |
| 2601 | || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) |
| 2602 | || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); |
| 2603 | |
| 2604 | if (flag_fixed_branchs) |
| 2605 | as_bad_where (fragP->fr_file, fragP->fr_line, |
| 2606 | _("bra or bsr with undefined symbol.")); |
| 2607 | |
| 2608 | /* The symbol is undefined or in a separate section. |
| 2609 | Turn bra into a jmp and bsr into a jsr. The insn |
| 2610 | becomes 3 bytes long (instead of 2). A fixup is |
| 2611 | necessary for the unresolved symbol address. */ |
| 2612 | fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]); |
| 2613 | |
| 2614 | fix_new (fragP, fragP->fr_fix - 1, 2, fragP->fr_symbol, |
| 2615 | fragP->fr_offset, 0, BFD_RELOC_16); |
| 2616 | fragP->fr_fix++; |
| 2617 | break; |
| 2618 | |
| 2619 | case STATE_CONDITIONAL_BRANCH: |
| 2620 | assert (current_architecture & cpu6811); |
| 2621 | |
| 2622 | fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */ |
| 2623 | fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ |
| 2624 | |
| 2625 | /* Don't use fr_opcode[2] because this may be |
| 2626 | in a different frag. */ |
| 2627 | buffer_address[0] = M6811_JMP; |
| 2628 | |
| 2629 | fragP->fr_fix++; |
| 2630 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
| 2631 | fragP->fr_offset, 0, BFD_RELOC_16); |
| 2632 | fragP->fr_fix += 2; |
| 2633 | break; |
| 2634 | |
| 2635 | case STATE_INDEXED_OFFSET: |
| 2636 | assert (current_architecture & cpu6812); |
| 2637 | |
| 2638 | /* Switch the indexed operation to 16-bit mode. */ |
| 2639 | fragP->fr_opcode[0] = fragP->fr_opcode[0] << 3; |
| 2640 | fragP->fr_opcode[0] |= 0xe2; |
| 2641 | fragP->fr_fix++; |
| 2642 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
| 2643 | fragP->fr_offset, 0, BFD_RELOC_16); |
| 2644 | fragP->fr_fix++; |
| 2645 | break; |
| 2646 | |
| 2647 | case STATE_XBCC_BRANCH: |
| 2648 | assert (current_architecture & cpu6812); |
| 2649 | |
| 2650 | fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */ |
| 2651 | fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ |
| 2652 | |
| 2653 | /* Don't use fr_opcode[2] because this may be |
| 2654 | in a different frag. */ |
| 2655 | buffer_address[0] = M6812_JMP; |
| 2656 | |
| 2657 | fragP->fr_fix++; |
| 2658 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
| 2659 | fragP->fr_offset, 0, BFD_RELOC_16); |
| 2660 | fragP->fr_fix += 2; |
| 2661 | break; |
| 2662 | |
| 2663 | case STATE_CONDITIONAL_BRANCH_6812: |
| 2664 | assert (current_architecture & cpu6812); |
| 2665 | |
| 2666 | /* Translate into a lbcc branch. */ |
| 2667 | fragP->fr_opcode[1] = fragP->fr_opcode[0]; |
| 2668 | fragP->fr_opcode[0] = M6811_OPCODE_PAGE2; |
| 2669 | |
| 2670 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, |
| 2671 | fragP->fr_offset, 0, BFD_RELOC_16_PCREL); |
| 2672 | fragP->fr_fix += 2; |
| 2673 | break; |
| 2674 | |
| 2675 | default: |
| 2676 | as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype); |
| 2677 | } |
| 2678 | frag_wane (fragP); |
| 2679 | |
| 2680 | /* Return the growth in the fixed part of the frag. */ |
| 2681 | return fragP->fr_fix - old_fr_fix; |
| 2682 | } |
| 2683 | |
| 2684 | /* Relaxable cases. */ |
| 2685 | switch (RELAX_STATE (fragP->fr_subtype)) |
| 2686 | { |
| 2687 | case STATE_PC_RELATIVE: |
| 2688 | /* This relax is only for bsr and bra. */ |
| 2689 | assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) |
| 2690 | || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) |
| 2691 | || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); |
| 2692 | |
| 2693 | fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE); |
| 2694 | break; |
| 2695 | |
| 2696 | case STATE_CONDITIONAL_BRANCH: |
| 2697 | assert (current_architecture & cpu6811); |
| 2698 | |
| 2699 | fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, |
| 2700 | STATE_BYTE); |
| 2701 | break; |
| 2702 | |
| 2703 | case STATE_INDEXED_OFFSET: |
| 2704 | assert (current_architecture & cpu6812); |
| 2705 | |
| 2706 | fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET, |
| 2707 | STATE_BITS5); |
| 2708 | break; |
| 2709 | |
| 2710 | case STATE_XBCC_BRANCH: |
| 2711 | assert (current_architecture & cpu6812); |
| 2712 | |
| 2713 | fragP->fr_subtype = ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE); |
| 2714 | break; |
| 2715 | |
| 2716 | case STATE_CONDITIONAL_BRANCH_6812: |
| 2717 | assert (current_architecture & cpu6812); |
| 2718 | |
| 2719 | fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, |
| 2720 | STATE_BYTE); |
| 2721 | break; |
| 2722 | } |
| 2723 | } |
| 2724 | |
| 2725 | if (fragP->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) |
| 2726 | as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype); |
| 2727 | |
| 2728 | /* Return the size of the variable part of the frag. */ |
| 2729 | return md_relax_table[fragP->fr_subtype].rlx_length; |
| 2730 | } |
| 2731 | |
| 2732 | void |
| 2733 | md_apply_fix3 (fixP, valP, seg) |
| 2734 | fixS *fixP; |
| 2735 | valueT *valP; |
| 2736 | segT seg ATTRIBUTE_UNUSED; |
| 2737 | { |
| 2738 | char *where; |
| 2739 | long value = * valP; |
| 2740 | int op_type; |
| 2741 | |
| 2742 | if (fixP->fx_addsy == (symbolS *) NULL) |
| 2743 | fixP->fx_done = 1; |
| 2744 | |
| 2745 | else if (fixP->fx_pcrel) |
| 2746 | ; |
| 2747 | |
| 2748 | else |
| 2749 | { |
| 2750 | value = fixP->fx_offset; |
| 2751 | |
| 2752 | if (fixP->fx_subsy != (symbolS *) NULL) |
| 2753 | { |
| 2754 | if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) |
| 2755 | value -= S_GET_VALUE (fixP->fx_subsy); |
| 2756 | else |
| 2757 | /* We don't actually support subtracting a symbol. */ |
| 2758 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 2759 | _("Expression too complex.")); |
| 2760 | } |
| 2761 | } |
| 2762 | |
| 2763 | op_type = fixP->fx_r_type; |
| 2764 | |
| 2765 | /* Patch the instruction with the resolved operand. Elf relocation |
| 2766 | info will also be generated to take care of linker/loader fixups. |
| 2767 | The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit |
| 2768 | relocs. BFD_RELOC_8 is basically used for .page0 access (the linker |
| 2769 | will warn for overflows). BFD_RELOC_8_PCREL should not be generated |
| 2770 | because it's either resolved or turned out into non-relative insns (see |
| 2771 | relax table, bcc, bra, bsr transformations) |
| 2772 | |
| 2773 | The BFD_RELOC_32 is necessary for the support of --gstabs. */ |
| 2774 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
| 2775 | |
| 2776 | switch (fixP->fx_r_type) |
| 2777 | { |
| 2778 | case BFD_RELOC_32: |
| 2779 | bfd_putb32 ((bfd_vma) value, (unsigned char *) where); |
| 2780 | break; |
| 2781 | |
| 2782 | case BFD_RELOC_16: |
| 2783 | case BFD_RELOC_16_PCREL: |
| 2784 | bfd_putb16 ((bfd_vma) value, (unsigned char *) where); |
| 2785 | if (value < -65537 || value > 65535) |
| 2786 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 2787 | _("Value out of 16-bit range.")); |
| 2788 | break; |
| 2789 | |
| 2790 | case BFD_RELOC_M68HC11_HI8: |
| 2791 | value = value >> 8; |
| 2792 | /* Fall through. */ |
| 2793 | |
| 2794 | case BFD_RELOC_M68HC11_LO8: |
| 2795 | case BFD_RELOC_8: |
| 2796 | #if 0 |
| 2797 | bfd_putb8 ((bfd_vma) value, (unsigned char *) where); |
| 2798 | #endif |
| 2799 | ((bfd_byte *) where)[0] = (bfd_byte) value; |
| 2800 | break; |
| 2801 | |
| 2802 | case BFD_RELOC_8_PCREL: |
| 2803 | #if 0 |
| 2804 | bfd_putb8 ((bfd_vma) value, (unsigned char *) where); |
| 2805 | #endif |
| 2806 | ((bfd_byte *) where)[0] = (bfd_byte) value; |
| 2807 | |
| 2808 | if (value < -128 || value > 127) |
| 2809 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 2810 | _("Value %ld too large for 8-bit PC-relative branch."), |
| 2811 | value); |
| 2812 | break; |
| 2813 | |
| 2814 | case BFD_RELOC_M68HC11_3B: |
| 2815 | if (value <= 0 || value > 8) |
| 2816 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 2817 | _("Auto increment/decrement offset '%ld' is out of range."), |
| 2818 | value); |
| 2819 | if (where[0] & 0x8) |
| 2820 | value = 8 - value; |
| 2821 | else |
| 2822 | value--; |
| 2823 | |
| 2824 | where[0] = where[0] | (value & 0x07); |
| 2825 | break; |
| 2826 | |
| 2827 | default: |
| 2828 | as_fatal (_("Line %d: unknown relocation type: 0x%x."), |
| 2829 | fixP->fx_line, fixP->fx_r_type); |
| 2830 | } |
| 2831 | } |