| 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
| 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
| 3 | Free Software Foundation, Inc. |
| 4 | Contributed by the OSF and Ralph Campbell. |
| 5 | Written by Keith Knowles and Ralph Campbell, working independently. |
| 6 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
| 7 | Support. |
| 8 | |
| 9 | This file is part of GAS. |
| 10 | |
| 11 | GAS is free software; you can redistribute it and/or modify |
| 12 | it under the terms of the GNU General Public License as published by |
| 13 | the Free Software Foundation; either version 2, or (at your option) |
| 14 | any later version. |
| 15 | |
| 16 | GAS is distributed in the hope that it will be useful, |
| 17 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | GNU General Public License for more details. |
| 20 | |
| 21 | You should have received a copy of the GNU General Public License |
| 22 | along with GAS; see the file COPYING. If not, write to the Free |
| 23 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA |
| 24 | 02111-1307, USA. */ |
| 25 | |
| 26 | #include "as.h" |
| 27 | #include "config.h" |
| 28 | #include "subsegs.h" |
| 29 | |
| 30 | #include <ctype.h> |
| 31 | |
| 32 | #ifdef USE_STDARG |
| 33 | #include <stdarg.h> |
| 34 | #endif |
| 35 | #ifdef USE_VARARGS |
| 36 | #include <varargs.h> |
| 37 | #endif |
| 38 | |
| 39 | #include "opcode/mips.h" |
| 40 | #include "itbl-ops.h" |
| 41 | |
| 42 | #ifdef DEBUG |
| 43 | #define DBG(x) printf x |
| 44 | #else |
| 45 | #define DBG(x) |
| 46 | #endif |
| 47 | |
| 48 | #ifdef OBJ_MAYBE_ELF |
| 49 | /* Clean up namespace so we can include obj-elf.h too. */ |
| 50 | static int mips_output_flavor PARAMS ((void)); |
| 51 | static int mips_output_flavor () { return OUTPUT_FLAVOR; } |
| 52 | #undef OBJ_PROCESS_STAB |
| 53 | #undef OUTPUT_FLAVOR |
| 54 | #undef S_GET_ALIGN |
| 55 | #undef S_GET_SIZE |
| 56 | #undef S_SET_ALIGN |
| 57 | #undef S_SET_SIZE |
| 58 | #undef obj_frob_file |
| 59 | #undef obj_frob_file_after_relocs |
| 60 | #undef obj_frob_symbol |
| 61 | #undef obj_pop_insert |
| 62 | #undef obj_sec_sym_ok_for_reloc |
| 63 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
| 64 | |
| 65 | #include "obj-elf.h" |
| 66 | /* Fix any of them that we actually care about. */ |
| 67 | #undef OUTPUT_FLAVOR |
| 68 | #define OUTPUT_FLAVOR mips_output_flavor() |
| 69 | #endif |
| 70 | |
| 71 | #if defined (OBJ_ELF) |
| 72 | #include "elf/mips.h" |
| 73 | #endif |
| 74 | |
| 75 | #ifndef ECOFF_DEBUGGING |
| 76 | #define NO_ECOFF_DEBUGGING |
| 77 | #define ECOFF_DEBUGGING 0 |
| 78 | #endif |
| 79 | |
| 80 | #include "ecoff.h" |
| 81 | |
| 82 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 83 | static char *mips_regmask_frag; |
| 84 | #endif |
| 85 | |
| 86 | #define AT 1 |
| 87 | #define TREG 24 |
| 88 | #define PIC_CALL_REG 25 |
| 89 | #define KT0 26 |
| 90 | #define KT1 27 |
| 91 | #define GP 28 |
| 92 | #define SP 29 |
| 93 | #define FP 30 |
| 94 | #define RA 31 |
| 95 | |
| 96 | #define ILLEGAL_REG (32) |
| 97 | |
| 98 | /* Allow override of standard little-endian ECOFF format. */ |
| 99 | |
| 100 | #ifndef ECOFF_LITTLE_FORMAT |
| 101 | #define ECOFF_LITTLE_FORMAT "ecoff-littlemips" |
| 102 | #endif |
| 103 | |
| 104 | extern int target_big_endian; |
| 105 | |
| 106 | /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the |
| 107 | 32 bit ABI. This has no meaning for ECOFF. |
| 108 | Note that the default is always 32 bit, even if "configured" for |
| 109 | 64 bit [e.g. --target=mips64-elf]. */ |
| 110 | static int mips_64; |
| 111 | |
| 112 | /* The default target format to use. */ |
| 113 | |
| 114 | const char * |
| 115 | mips_target_format () |
| 116 | { |
| 117 | switch (OUTPUT_FLAVOR) |
| 118 | { |
| 119 | case bfd_target_aout_flavour: |
| 120 | return target_big_endian ? "a.out-mips-big" : "a.out-mips-little"; |
| 121 | case bfd_target_ecoff_flavour: |
| 122 | return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT; |
| 123 | case bfd_target_coff_flavour: |
| 124 | return "pe-mips"; |
| 125 | case bfd_target_elf_flavour: |
| 126 | #ifdef TE_TMIPS |
| 127 | /* This is traditional mips */ |
| 128 | return (target_big_endian |
| 129 | ? (mips_64 ? "elf64-tradbigmips" : "elf32-tradbigmips") |
| 130 | : (mips_64 ? "elf64-tradlittlemips" : "elf32-tradlittlemips")); |
| 131 | #else |
| 132 | return (target_big_endian |
| 133 | ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips") |
| 134 | : (mips_64 ? "elf64-littlemips" : "elf32-littlemips")); |
| 135 | #endif |
| 136 | default: |
| 137 | abort (); |
| 138 | return NULL; |
| 139 | } |
| 140 | } |
| 141 | |
| 142 | /* The name of the readonly data section. */ |
| 143 | #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \ |
| 144 | ? ".data" \ |
| 145 | : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \ |
| 146 | ? ".rdata" \ |
| 147 | : OUTPUT_FLAVOR == bfd_target_coff_flavour \ |
| 148 | ? ".rdata" \ |
| 149 | : OUTPUT_FLAVOR == bfd_target_elf_flavour \ |
| 150 | ? ".rodata" \ |
| 151 | : (abort (), "")) |
| 152 | |
| 153 | /* This is the set of options which may be modified by the .set |
| 154 | pseudo-op. We use a struct so that .set push and .set pop are more |
| 155 | reliable. */ |
| 156 | |
| 157 | struct mips_set_options |
| 158 | { |
| 159 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
| 160 | if it has not been initialized. Changed by `.set mipsN', and the |
| 161 | -mipsN command line option, and the default CPU. */ |
| 162 | int isa; |
| 163 | /* Whether we are assembling for the mips16 processor. 0 if we are |
| 164 | not, 1 if we are, and -1 if the value has not been initialized. |
| 165 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and |
| 166 | -nomips16 command line options, and the default CPU. */ |
| 167 | int mips16; |
| 168 | /* Non-zero if we should not reorder instructions. Changed by `.set |
| 169 | reorder' and `.set noreorder'. */ |
| 170 | int noreorder; |
| 171 | /* Non-zero if we should not permit the $at ($1) register to be used |
| 172 | in instructions. Changed by `.set at' and `.set noat'. */ |
| 173 | int noat; |
| 174 | /* Non-zero if we should warn when a macro instruction expands into |
| 175 | more than one machine instruction. Changed by `.set nomacro' and |
| 176 | `.set macro'. */ |
| 177 | int warn_about_macros; |
| 178 | /* Non-zero if we should not move instructions. Changed by `.set |
| 179 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ |
| 180 | int nomove; |
| 181 | /* Non-zero if we should not optimize branches by moving the target |
| 182 | of the branch into the delay slot. Actually, we don't perform |
| 183 | this optimization anyhow. Changed by `.set bopt' and `.set |
| 184 | nobopt'. */ |
| 185 | int nobopt; |
| 186 | /* Non-zero if we should not autoextend mips16 instructions. |
| 187 | Changed by `.set autoextend' and `.set noautoextend'. */ |
| 188 | int noautoextend; |
| 189 | }; |
| 190 | |
| 191 | /* This is the struct we use to hold the current set of options. Note |
| 192 | that we must set the isa field to ISA_UNKNOWN and the mips16 field to |
| 193 | -1 to indicate that they have not been initialized. */ |
| 194 | |
| 195 | static struct mips_set_options mips_opts = |
| 196 | { |
| 197 | ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0 |
| 198 | }; |
| 199 | |
| 200 | /* These variables are filled in with the masks of registers used. |
| 201 | The object format code reads them and puts them in the appropriate |
| 202 | place. */ |
| 203 | unsigned long mips_gprmask; |
| 204 | unsigned long mips_cprmask[4]; |
| 205 | |
| 206 | /* MIPS ISA we are using for this output file. */ |
| 207 | static int file_mips_isa = ISA_UNKNOWN; |
| 208 | |
| 209 | /* The argument of the -mcpu= flag. Historical for code generation. */ |
| 210 | static int mips_cpu = CPU_UNKNOWN; |
| 211 | |
| 212 | /* The argument of the -march= flag. The architecture we are assembling. */ |
| 213 | static int mips_arch = CPU_UNKNOWN; |
| 214 | |
| 215 | /* The argument of the -mtune= flag. The architecture for which we |
| 216 | are optimizing. */ |
| 217 | static int mips_tune = CPU_UNKNOWN; |
| 218 | |
| 219 | /* The argument of the -mabi= flag. */ |
| 220 | static char * mips_abi_string = NULL; |
| 221 | |
| 222 | /* Whether we should mark the file EABI64 or EABI32. */ |
| 223 | static int mips_eabi64 = 0; |
| 224 | |
| 225 | /* If they asked for mips1 or mips2 and a cpu that is |
| 226 | mips3 or greater, then mark the object file 32BITMODE. */ |
| 227 | static int mips_32bitmode = 0; |
| 228 | |
| 229 | /* True if -mgp32 was passed. */ |
| 230 | static int mips_gp32 = 0; |
| 231 | |
| 232 | /* True if -mfp32 was passed. */ |
| 233 | static int mips_fp32 = 0; |
| 234 | |
| 235 | /* True if the selected ABI is defined for 32-bit registers only. */ |
| 236 | static int mips_32bit_abi = 0; |
| 237 | |
| 238 | /* Some ISA's have delay slots for instructions which read or write |
| 239 | from a coprocessor (eg. mips1-mips3); some don't (eg mips4). |
| 240 | Return true if instructions marked INSN_LOAD_COPROC_DELAY, |
| 241 | INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a |
| 242 | delay slot in this ISA. The uses of this macro assume that any |
| 243 | ISA that has delay slots for one of these, has them for all. They |
| 244 | also assume that ISAs which don't have delays for these insns, don't |
| 245 | have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */ |
| 246 | #define ISA_HAS_COPROC_DELAYS(ISA) ( \ |
| 247 | (ISA) == ISA_MIPS1 \ |
| 248 | || (ISA) == ISA_MIPS2 \ |
| 249 | || (ISA) == ISA_MIPS3 \ |
| 250 | ) |
| 251 | |
| 252 | /* Return true if ISA supports 64 bit gp register instructions. */ |
| 253 | #define ISA_HAS_64BIT_REGS(ISA) ( \ |
| 254 | (ISA) == ISA_MIPS3 \ |
| 255 | || (ISA) == ISA_MIPS4 \ |
| 256 | || (ISA) == ISA_MIPS5 \ |
| 257 | || (ISA) == ISA_MIPS64 \ |
| 258 | ) |
| 259 | |
| 260 | #define HAVE_32BIT_GPRS \ |
| 261 | (mips_gp32 \ |
| 262 | || mips_32bit_abi \ |
| 263 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
| 264 | |
| 265 | #define HAVE_32BIT_FPRS \ |
| 266 | (mips_fp32 \ |
| 267 | || mips_32bit_abi \ |
| 268 | || ! ISA_HAS_64BIT_REGS (mips_opts.isa)) |
| 269 | |
| 270 | #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS) |
| 271 | #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS) |
| 272 | |
| 273 | #define HAVE_32BIT_ADDRESSES \ |
| 274 | (HAVE_32BIT_GPRS \ |
| 275 | || bfd_arch_bits_per_address (stdoutput) == 32) |
| 276 | |
| 277 | /* Whether the processor uses hardware interlocks to protect |
| 278 | reads from the HI and LO registers, and thus does not |
| 279 | require nops to be inserted. */ |
| 280 | |
| 281 | #define hilo_interlocks (mips_arch == CPU_R4010 \ |
| 282 | ) |
| 283 | |
| 284 | /* Whether the processor uses hardware interlocks to protect reads |
| 285 | from the GPRs, and thus does not require nops to be inserted. */ |
| 286 | #define gpr_interlocks \ |
| 287 | (mips_opts.isa != ISA_MIPS1 \ |
| 288 | || mips_arch == CPU_R3900) |
| 289 | |
| 290 | /* As with other "interlocks" this is used by hardware that has FP |
| 291 | (co-processor) interlocks. */ |
| 292 | /* Itbl support may require additional care here. */ |
| 293 | #define cop_interlocks (mips_arch == CPU_R4300 \ |
| 294 | ) |
| 295 | |
| 296 | /* Is this a mfhi or mflo instruction? */ |
| 297 | #define MF_HILO_INSN(PINFO) \ |
| 298 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
| 299 | |
| 300 | /* MIPS PIC level. */ |
| 301 | |
| 302 | enum mips_pic_level |
| 303 | { |
| 304 | /* Do not generate PIC code. */ |
| 305 | NO_PIC, |
| 306 | |
| 307 | /* Generate PIC code as in Irix 4. This is not implemented, and I'm |
| 308 | not sure what it is supposed to do. */ |
| 309 | IRIX4_PIC, |
| 310 | |
| 311 | /* Generate PIC code as in the SVR4 MIPS ABI. */ |
| 312 | SVR4_PIC, |
| 313 | |
| 314 | /* Generate PIC code without using a global offset table: the data |
| 315 | segment has a maximum size of 64K, all data references are off |
| 316 | the $gp register, and all text references are PC relative. This |
| 317 | is used on some embedded systems. */ |
| 318 | EMBEDDED_PIC |
| 319 | }; |
| 320 | |
| 321 | static enum mips_pic_level mips_pic; |
| 322 | |
| 323 | /* Warn about all NOPS that the assembler generates. */ |
| 324 | static int warn_nops = 0; |
| 325 | |
| 326 | /* 1 if we should generate 32 bit offsets from the GP register in |
| 327 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
| 328 | static int mips_big_got; |
| 329 | |
| 330 | /* 1 if trap instructions should used for overflow rather than break |
| 331 | instructions. */ |
| 332 | static int mips_trap; |
| 333 | |
| 334 | /* 1 if double width floating point constants should not be constructed |
| 335 | by a assembling two single width halves into two single width floating |
| 336 | point registers which just happen to alias the double width destination |
| 337 | register. On some architectures this aliasing can be disabled by a bit |
| 338 | in the status register, and the setting of this bit cannot be determined |
| 339 | automatically at assemble time. */ |
| 340 | static int mips_disable_float_construction; |
| 341 | |
| 342 | /* Non-zero if any .set noreorder directives were used. */ |
| 343 | |
| 344 | static int mips_any_noreorder; |
| 345 | |
| 346 | /* Non-zero if nops should be inserted when the register referenced in |
| 347 | an mfhi/mflo instruction is read in the next two instructions. */ |
| 348 | static int mips_7000_hilo_fix; |
| 349 | |
| 350 | /* The size of the small data section. */ |
| 351 | static unsigned int g_switch_value = 8; |
| 352 | /* Whether the -G option was used. */ |
| 353 | static int g_switch_seen = 0; |
| 354 | |
| 355 | #define N_RMASK 0xc4 |
| 356 | #define N_VFP 0xd4 |
| 357 | |
| 358 | /* If we can determine in advance that GP optimization won't be |
| 359 | possible, we can skip the relaxation stuff that tries to produce |
| 360 | GP-relative references. This makes delay slot optimization work |
| 361 | better. |
| 362 | |
| 363 | This function can only provide a guess, but it seems to work for |
| 364 | gcc output. It needs to guess right for gcc, otherwise gcc |
| 365 | will put what it thinks is a GP-relative instruction in a branch |
| 366 | delay slot. |
| 367 | |
| 368 | I don't know if a fix is needed for the SVR4_PIC mode. I've only |
| 369 | fixed it for the non-PIC mode. KR 95/04/07 */ |
| 370 | static int nopic_need_relax PARAMS ((symbolS *, int)); |
| 371 | |
| 372 | /* handle of the OPCODE hash table */ |
| 373 | static struct hash_control *op_hash = NULL; |
| 374 | |
| 375 | /* The opcode hash table we use for the mips16. */ |
| 376 | static struct hash_control *mips16_op_hash = NULL; |
| 377 | |
| 378 | /* This array holds the chars that always start a comment. If the |
| 379 | pre-processor is disabled, these aren't very useful */ |
| 380 | const char comment_chars[] = "#"; |
| 381 | |
| 382 | /* This array holds the chars that only start a comment at the beginning of |
| 383 | a line. If the line seems to have the form '# 123 filename' |
| 384 | .line and .file directives will appear in the pre-processed output */ |
| 385 | /* Note that input_file.c hand checks for '#' at the beginning of the |
| 386 | first line of the input file. This is because the compiler outputs |
| 387 | #NO_APP at the beginning of its output. */ |
| 388 | /* Also note that C style comments are always supported. */ |
| 389 | const char line_comment_chars[] = "#"; |
| 390 | |
| 391 | /* This array holds machine specific line separator characters. */ |
| 392 | const char line_separator_chars[] = ";"; |
| 393 | |
| 394 | /* Chars that can be used to separate mant from exp in floating point nums */ |
| 395 | const char EXP_CHARS[] = "eE"; |
| 396 | |
| 397 | /* Chars that mean this number is a floating point constant */ |
| 398 | /* As in 0f12.456 */ |
| 399 | /* or 0d1.2345e12 */ |
| 400 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
| 401 | |
| 402 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be |
| 403 | changed in read.c . Ideally it shouldn't have to know about it at all, |
| 404 | but nothing is ideal around here. |
| 405 | */ |
| 406 | |
| 407 | static char *insn_error; |
| 408 | |
| 409 | static int auto_align = 1; |
| 410 | |
| 411 | /* When outputting SVR4 PIC code, the assembler needs to know the |
| 412 | offset in the stack frame from which to restore the $gp register. |
| 413 | This is set by the .cprestore pseudo-op, and saved in this |
| 414 | variable. */ |
| 415 | static offsetT mips_cprestore_offset = -1; |
| 416 | |
| 417 | /* This is the register which holds the stack frame, as set by the |
| 418 | .frame pseudo-op. This is needed to implement .cprestore. */ |
| 419 | static int mips_frame_reg = SP; |
| 420 | |
| 421 | /* To output NOP instructions correctly, we need to keep information |
| 422 | about the previous two instructions. */ |
| 423 | |
| 424 | /* Whether we are optimizing. The default value of 2 means to remove |
| 425 | unneeded NOPs and swap branch instructions when possible. A value |
| 426 | of 1 means to not swap branches. A value of 0 means to always |
| 427 | insert NOPs. */ |
| 428 | static int mips_optimize = 2; |
| 429 | |
| 430 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
| 431 | equivalent to seeing no -g option at all. */ |
| 432 | static int mips_debug = 0; |
| 433 | |
| 434 | /* The previous instruction. */ |
| 435 | static struct mips_cl_insn prev_insn; |
| 436 | |
| 437 | /* The instruction before prev_insn. */ |
| 438 | static struct mips_cl_insn prev_prev_insn; |
| 439 | |
| 440 | /* If we don't want information for prev_insn or prev_prev_insn, we |
| 441 | point the insn_mo field at this dummy integer. */ |
| 442 | static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 }; |
| 443 | |
| 444 | /* Non-zero if prev_insn is valid. */ |
| 445 | static int prev_insn_valid; |
| 446 | |
| 447 | /* The frag for the previous instruction. */ |
| 448 | static struct frag *prev_insn_frag; |
| 449 | |
| 450 | /* The offset into prev_insn_frag for the previous instruction. */ |
| 451 | static long prev_insn_where; |
| 452 | |
| 453 | /* The reloc type for the previous instruction, if any. */ |
| 454 | static bfd_reloc_code_real_type prev_insn_reloc_type; |
| 455 | |
| 456 | /* The reloc for the previous instruction, if any. */ |
| 457 | static fixS *prev_insn_fixp; |
| 458 | |
| 459 | /* Non-zero if the previous instruction was in a delay slot. */ |
| 460 | static int prev_insn_is_delay_slot; |
| 461 | |
| 462 | /* Non-zero if the previous instruction was in a .set noreorder. */ |
| 463 | static int prev_insn_unreordered; |
| 464 | |
| 465 | /* Non-zero if the previous instruction uses an extend opcode (if |
| 466 | mips16). */ |
| 467 | static int prev_insn_extended; |
| 468 | |
| 469 | /* Non-zero if the previous previous instruction was in a .set |
| 470 | noreorder. */ |
| 471 | static int prev_prev_insn_unreordered; |
| 472 | |
| 473 | /* If this is set, it points to a frag holding nop instructions which |
| 474 | were inserted before the start of a noreorder section. If those |
| 475 | nops turn out to be unnecessary, the size of the frag can be |
| 476 | decreased. */ |
| 477 | static fragS *prev_nop_frag; |
| 478 | |
| 479 | /* The number of nop instructions we created in prev_nop_frag. */ |
| 480 | static int prev_nop_frag_holds; |
| 481 | |
| 482 | /* The number of nop instructions that we know we need in |
| 483 | prev_nop_frag. */ |
| 484 | static int prev_nop_frag_required; |
| 485 | |
| 486 | /* The number of instructions we've seen since prev_nop_frag. */ |
| 487 | static int prev_nop_frag_since; |
| 488 | |
| 489 | /* For ECOFF and ELF, relocations against symbols are done in two |
| 490 | parts, with a HI relocation and a LO relocation. Each relocation |
| 491 | has only 16 bits of space to store an addend. This means that in |
| 492 | order for the linker to handle carries correctly, it must be able |
| 493 | to locate both the HI and the LO relocation. This means that the |
| 494 | relocations must appear in order in the relocation table. |
| 495 | |
| 496 | In order to implement this, we keep track of each unmatched HI |
| 497 | relocation. We then sort them so that they immediately precede the |
| 498 | corresponding LO relocation. */ |
| 499 | |
| 500 | struct mips_hi_fixup |
| 501 | { |
| 502 | /* Next HI fixup. */ |
| 503 | struct mips_hi_fixup *next; |
| 504 | /* This fixup. */ |
| 505 | fixS *fixp; |
| 506 | /* The section this fixup is in. */ |
| 507 | segT seg; |
| 508 | }; |
| 509 | |
| 510 | /* The list of unmatched HI relocs. */ |
| 511 | |
| 512 | static struct mips_hi_fixup *mips_hi_fixup_list; |
| 513 | |
| 514 | /* Map normal MIPS register numbers to mips16 register numbers. */ |
| 515 | |
| 516 | #define X ILLEGAL_REG |
| 517 | static const int mips32_to_16_reg_map[] = |
| 518 | { |
| 519 | X, X, 2, 3, 4, 5, 6, 7, |
| 520 | X, X, X, X, X, X, X, X, |
| 521 | 0, 1, X, X, X, X, X, X, |
| 522 | X, X, X, X, X, X, X, X |
| 523 | }; |
| 524 | #undef X |
| 525 | |
| 526 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
| 527 | |
| 528 | static const unsigned int mips16_to_32_reg_map[] = |
| 529 | { |
| 530 | 16, 17, 2, 3, 4, 5, 6, 7 |
| 531 | }; |
| 532 | \f |
| 533 | /* Since the MIPS does not have multiple forms of PC relative |
| 534 | instructions, we do not have to do relaxing as is done on other |
| 535 | platforms. However, we do have to handle GP relative addressing |
| 536 | correctly, which turns out to be a similar problem. |
| 537 | |
| 538 | Every macro that refers to a symbol can occur in (at least) two |
| 539 | forms, one with GP relative addressing and one without. For |
| 540 | example, loading a global variable into a register generally uses |
| 541 | a macro instruction like this: |
| 542 | lw $4,i |
| 543 | If i can be addressed off the GP register (this is true if it is in |
| 544 | the .sbss or .sdata section, or if it is known to be smaller than |
| 545 | the -G argument) this will generate the following instruction: |
| 546 | lw $4,i($gp) |
| 547 | This instruction will use a GPREL reloc. If i can not be addressed |
| 548 | off the GP register, the following instruction sequence will be used: |
| 549 | lui $at,i |
| 550 | lw $4,i($at) |
| 551 | In this case the first instruction will have a HI16 reloc, and the |
| 552 | second reloc will have a LO16 reloc. Both relocs will be against |
| 553 | the symbol i. |
| 554 | |
| 555 | The issue here is that we may not know whether i is GP addressable |
| 556 | until after we see the instruction that uses it. Therefore, we |
| 557 | want to be able to choose the final instruction sequence only at |
| 558 | the end of the assembly. This is similar to the way other |
| 559 | platforms choose the size of a PC relative instruction only at the |
| 560 | end of assembly. |
| 561 | |
| 562 | When generating position independent code we do not use GP |
| 563 | addressing in quite the same way, but the issue still arises as |
| 564 | external symbols and local symbols must be handled differently. |
| 565 | |
| 566 | We handle these issues by actually generating both possible |
| 567 | instruction sequences. The longer one is put in a frag_var with |
| 568 | type rs_machine_dependent. We encode what to do with the frag in |
| 569 | the subtype field. We encode (1) the number of existing bytes to |
| 570 | replace, (2) the number of new bytes to use, (3) the offset from |
| 571 | the start of the existing bytes to the first reloc we must generate |
| 572 | (that is, the offset is applied from the start of the existing |
| 573 | bytes after they are replaced by the new bytes, if any), (4) the |
| 574 | offset from the start of the existing bytes to the second reloc, |
| 575 | (5) whether a third reloc is needed (the third reloc is always four |
| 576 | bytes after the second reloc), and (6) whether to warn if this |
| 577 | variant is used (this is sometimes needed if .set nomacro or .set |
| 578 | noat is in effect). All these numbers are reasonably small. |
| 579 | |
| 580 | Generating two instruction sequences must be handled carefully to |
| 581 | ensure that delay slots are handled correctly. Fortunately, there |
| 582 | are a limited number of cases. When the second instruction |
| 583 | sequence is generated, append_insn is directed to maintain the |
| 584 | existing delay slot information, so it continues to apply to any |
| 585 | code after the second instruction sequence. This means that the |
| 586 | second instruction sequence must not impose any requirements not |
| 587 | required by the first instruction sequence. |
| 588 | |
| 589 | These variant frags are then handled in functions called by the |
| 590 | machine independent code. md_estimate_size_before_relax returns |
| 591 | the final size of the frag. md_convert_frag sets up the final form |
| 592 | of the frag. tc_gen_reloc adjust the first reloc and adds a second |
| 593 | one if needed. */ |
| 594 | #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \ |
| 595 | ((relax_substateT) \ |
| 596 | (((old) << 23) \ |
| 597 | | ((new) << 16) \ |
| 598 | | (((reloc1) + 64) << 9) \ |
| 599 | | (((reloc2) + 64) << 2) \ |
| 600 | | ((reloc3) ? (1 << 1) : 0) \ |
| 601 | | ((warn) ? 1 : 0))) |
| 602 | #define RELAX_OLD(i) (((i) >> 23) & 0x7f) |
| 603 | #define RELAX_NEW(i) (((i) >> 16) & 0x7f) |
| 604 | #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64) |
| 605 | #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64) |
| 606 | #define RELAX_RELOC3(i) (((i) >> 1) & 1) |
| 607 | #define RELAX_WARN(i) ((i) & 1) |
| 608 | |
| 609 | /* For mips16 code, we use an entirely different form of relaxation. |
| 610 | mips16 supports two versions of most instructions which take |
| 611 | immediate values: a small one which takes some small value, and a |
| 612 | larger one which takes a 16 bit value. Since branches also follow |
| 613 | this pattern, relaxing these values is required. |
| 614 | |
| 615 | We can assemble both mips16 and normal MIPS code in a single |
| 616 | object. Therefore, we need to support this type of relaxation at |
| 617 | the same time that we support the relaxation described above. We |
| 618 | use the high bit of the subtype field to distinguish these cases. |
| 619 | |
| 620 | The information we store for this type of relaxation is the |
| 621 | argument code found in the opcode file for this relocation, whether |
| 622 | the user explicitly requested a small or extended form, and whether |
| 623 | the relocation is in a jump or jal delay slot. That tells us the |
| 624 | size of the value, and how it should be stored. We also store |
| 625 | whether the fragment is considered to be extended or not. We also |
| 626 | store whether this is known to be a branch to a different section, |
| 627 | whether we have tried to relax this frag yet, and whether we have |
| 628 | ever extended a PC relative fragment because of a shift count. */ |
| 629 | #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \ |
| 630 | (0x80000000 \ |
| 631 | | ((type) & 0xff) \ |
| 632 | | ((small) ? 0x100 : 0) \ |
| 633 | | ((ext) ? 0x200 : 0) \ |
| 634 | | ((dslot) ? 0x400 : 0) \ |
| 635 | | ((jal_dslot) ? 0x800 : 0)) |
| 636 | #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0) |
| 637 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
| 638 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0) |
| 639 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0) |
| 640 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0) |
| 641 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0) |
| 642 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0) |
| 643 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000) |
| 644 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000) |
| 645 | #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0) |
| 646 | #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000) |
| 647 | #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000) |
| 648 | \f |
| 649 | /* Prototypes for static functions. */ |
| 650 | |
| 651 | #ifdef __STDC__ |
| 652 | #define internalError() \ |
| 653 | as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__) |
| 654 | #else |
| 655 | #define internalError() as_fatal (_("MIPS internal Error")); |
| 656 | #endif |
| 657 | |
| 658 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
| 659 | |
| 660 | static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip, |
| 661 | unsigned int reg, enum mips_regclass class)); |
| 662 | static int reg_needs_delay PARAMS ((unsigned int)); |
| 663 | static void mips16_mark_labels PARAMS ((void)); |
| 664 | static void append_insn PARAMS ((char *place, |
| 665 | struct mips_cl_insn * ip, |
| 666 | expressionS * p, |
| 667 | bfd_reloc_code_real_type r, |
| 668 | boolean)); |
| 669 | static void mips_no_prev_insn PARAMS ((int)); |
| 670 | static void mips_emit_delays PARAMS ((boolean)); |
| 671 | #ifdef USE_STDARG |
| 672 | static void macro_build PARAMS ((char *place, int *counter, expressionS * ep, |
| 673 | const char *name, const char *fmt, |
| 674 | ...)); |
| 675 | #else |
| 676 | static void macro_build (); |
| 677 | #endif |
| 678 | static void mips16_macro_build PARAMS ((char *, int *, expressionS *, |
| 679 | const char *, const char *, |
| 680 | va_list)); |
| 681 | static void macro_build_lui PARAMS ((char *place, int *counter, |
| 682 | expressionS * ep, int regnum)); |
| 683 | static void set_at PARAMS ((int *counter, int reg, int unsignedp)); |
| 684 | static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip, |
| 685 | expressionS *)); |
| 686 | static void load_register PARAMS ((int *, int, expressionS *, int)); |
| 687 | static void load_address PARAMS ((int *counter, int reg, expressionS *ep)); |
| 688 | static void move_register PARAMS ((int *, int, int)); |
| 689 | static void macro PARAMS ((struct mips_cl_insn * ip)); |
| 690 | static void mips16_macro PARAMS ((struct mips_cl_insn * ip)); |
| 691 | #ifdef LOSING_COMPILER |
| 692 | static void macro2 PARAMS ((struct mips_cl_insn * ip)); |
| 693 | #endif |
| 694 | static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
| 695 | static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip)); |
| 696 | static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean, |
| 697 | boolean, boolean, unsigned long *, |
| 698 | boolean *, unsigned short *)); |
| 699 | static int my_getSmallExpression PARAMS ((expressionS * ep, char *str)); |
| 700 | static void my_getExpression PARAMS ((expressionS * ep, char *str)); |
| 701 | static symbolS *get_symbol PARAMS ((void)); |
| 702 | static void mips_align PARAMS ((int to, int fill, symbolS *label)); |
| 703 | static void s_align PARAMS ((int)); |
| 704 | static void s_change_sec PARAMS ((int)); |
| 705 | static void s_cons PARAMS ((int)); |
| 706 | static void s_float_cons PARAMS ((int)); |
| 707 | static void s_mips_globl PARAMS ((int)); |
| 708 | static void s_option PARAMS ((int)); |
| 709 | static void s_mipsset PARAMS ((int)); |
| 710 | static void s_abicalls PARAMS ((int)); |
| 711 | static void s_cpload PARAMS ((int)); |
| 712 | static void s_cprestore PARAMS ((int)); |
| 713 | static void s_gpword PARAMS ((int)); |
| 714 | static void s_cpadd PARAMS ((int)); |
| 715 | static void s_insn PARAMS ((int)); |
| 716 | static void md_obj_begin PARAMS ((void)); |
| 717 | static void md_obj_end PARAMS ((void)); |
| 718 | static long get_number PARAMS ((void)); |
| 719 | static void s_mips_ent PARAMS ((int)); |
| 720 | static void s_mips_end PARAMS ((int)); |
| 721 | static void s_mips_frame PARAMS ((int)); |
| 722 | static void s_mips_mask PARAMS ((int)); |
| 723 | static void s_mips_stab PARAMS ((int)); |
| 724 | static void s_mips_weakext PARAMS ((int)); |
| 725 | static void s_file PARAMS ((int)); |
| 726 | static int mips16_extended_frag PARAMS ((fragS *, asection *, long)); |
| 727 | static const char *mips_isa_to_str PARAMS ((int)); |
| 728 | static const char *mips_cpu_to_str PARAMS ((int)); |
| 729 | static int validate_mips_insn PARAMS ((const struct mips_opcode *)); |
| 730 | static void show PARAMS ((FILE *, char *, int *, int *)); |
| 731 | |
| 732 | /* Return values of my_getSmallExpression() */ |
| 733 | |
| 734 | enum |
| 735 | { |
| 736 | S_EX_NONE = 0, |
| 737 | S_EX_LO, |
| 738 | S_EX_HI, |
| 739 | S_EX_HIGHER, |
| 740 | S_EX_HIGHEST, |
| 741 | S_EX_GPREL, |
| 742 | S_EX_NEG |
| 743 | }; |
| 744 | |
| 745 | /* Table and functions used to map between CPU/ISA names, and |
| 746 | ISA levels, and CPU numbers. */ |
| 747 | |
| 748 | struct mips_cpu_info |
| 749 | { |
| 750 | const char *name; /* CPU or ISA name. */ |
| 751 | int is_isa; /* Is this an ISA? (If 0, a CPU.) */ |
| 752 | int isa; /* ISA level. */ |
| 753 | int cpu; /* CPU number (default CPU if ISA). */ |
| 754 | }; |
| 755 | |
| 756 | static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *)); |
| 757 | static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int)); |
| 758 | static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int)); |
| 759 | \f |
| 760 | /* Pseudo-op table. |
| 761 | |
| 762 | The following pseudo-ops from the Kane and Heinrich MIPS book |
| 763 | should be defined here, but are currently unsupported: .alias, |
| 764 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. |
| 765 | |
| 766 | The following pseudo-ops from the Kane and Heinrich MIPS book are |
| 767 | specific to the type of debugging information being generated, and |
| 768 | should be defined by the object format: .aent, .begin, .bend, |
| 769 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, |
| 770 | .vreg. |
| 771 | |
| 772 | The following pseudo-ops from the Kane and Heinrich MIPS book are |
| 773 | not MIPS CPU specific, but are also not specific to the object file |
| 774 | format. This file is probably the best place to define them, but |
| 775 | they are not currently supported: .asm0, .endr, .lab, .repeat, |
| 776 | .struct. */ |
| 777 | |
| 778 | static const pseudo_typeS mips_pseudo_table[] = |
| 779 | { |
| 780 | /* MIPS specific pseudo-ops. */ |
| 781 | {"option", s_option, 0}, |
| 782 | {"set", s_mipsset, 0}, |
| 783 | {"rdata", s_change_sec, 'r'}, |
| 784 | {"sdata", s_change_sec, 's'}, |
| 785 | {"livereg", s_ignore, 0}, |
| 786 | {"abicalls", s_abicalls, 0}, |
| 787 | {"cpload", s_cpload, 0}, |
| 788 | {"cprestore", s_cprestore, 0}, |
| 789 | {"gpword", s_gpword, 0}, |
| 790 | {"cpadd", s_cpadd, 0}, |
| 791 | {"insn", s_insn, 0}, |
| 792 | |
| 793 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
| 794 | chips. */ |
| 795 | {"asciiz", stringer, 1}, |
| 796 | {"bss", s_change_sec, 'b'}, |
| 797 | {"err", s_err, 0}, |
| 798 | {"half", s_cons, 1}, |
| 799 | {"dword", s_cons, 3}, |
| 800 | {"weakext", s_mips_weakext, 0}, |
| 801 | |
| 802 | /* These pseudo-ops are defined in read.c, but must be overridden |
| 803 | here for one reason or another. */ |
| 804 | {"align", s_align, 0}, |
| 805 | {"byte", s_cons, 0}, |
| 806 | {"data", s_change_sec, 'd'}, |
| 807 | {"double", s_float_cons, 'd'}, |
| 808 | {"float", s_float_cons, 'f'}, |
| 809 | {"globl", s_mips_globl, 0}, |
| 810 | {"global", s_mips_globl, 0}, |
| 811 | {"hword", s_cons, 1}, |
| 812 | {"int", s_cons, 2}, |
| 813 | {"long", s_cons, 2}, |
| 814 | {"octa", s_cons, 4}, |
| 815 | {"quad", s_cons, 3}, |
| 816 | {"short", s_cons, 1}, |
| 817 | {"single", s_float_cons, 'f'}, |
| 818 | {"stabn", s_mips_stab, 'n'}, |
| 819 | {"text", s_change_sec, 't'}, |
| 820 | {"word", s_cons, 2}, |
| 821 | |
| 822 | #ifdef MIPS_STABS_ELF |
| 823 | { "extern", ecoff_directive_extern, 0}, |
| 824 | #endif |
| 825 | |
| 826 | { NULL, NULL, 0 }, |
| 827 | }; |
| 828 | |
| 829 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
| 830 | { |
| 831 | /* These pseudo-ops should be defined by the object file format. |
| 832 | However, a.out doesn't support them, so we have versions here. */ |
| 833 | {"aent", s_mips_ent, 1}, |
| 834 | {"bgnb", s_ignore, 0}, |
| 835 | {"end", s_mips_end, 0}, |
| 836 | {"endb", s_ignore, 0}, |
| 837 | {"ent", s_mips_ent, 0}, |
| 838 | {"file", s_file, 0}, |
| 839 | {"fmask", s_mips_mask, 'F'}, |
| 840 | {"frame", s_mips_frame, 0}, |
| 841 | {"loc", s_ignore, 0}, |
| 842 | {"mask", s_mips_mask, 'R'}, |
| 843 | {"verstamp", s_ignore, 0}, |
| 844 | { NULL, NULL, 0 }, |
| 845 | }; |
| 846 | |
| 847 | extern void pop_insert PARAMS ((const pseudo_typeS *)); |
| 848 | |
| 849 | void |
| 850 | mips_pop_insert () |
| 851 | { |
| 852 | pop_insert (mips_pseudo_table); |
| 853 | if (! ECOFF_DEBUGGING) |
| 854 | pop_insert (mips_nonecoff_pseudo_table); |
| 855 | } |
| 856 | \f |
| 857 | /* Symbols labelling the current insn. */ |
| 858 | |
| 859 | struct insn_label_list |
| 860 | { |
| 861 | struct insn_label_list *next; |
| 862 | symbolS *label; |
| 863 | }; |
| 864 | |
| 865 | static struct insn_label_list *insn_labels; |
| 866 | static struct insn_label_list *free_insn_labels; |
| 867 | |
| 868 | static void mips_clear_insn_labels PARAMS ((void)); |
| 869 | |
| 870 | static inline void |
| 871 | mips_clear_insn_labels () |
| 872 | { |
| 873 | register struct insn_label_list **pl; |
| 874 | |
| 875 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) |
| 876 | ; |
| 877 | *pl = insn_labels; |
| 878 | insn_labels = NULL; |
| 879 | } |
| 880 | \f |
| 881 | static char *expr_end; |
| 882 | |
| 883 | /* Expressions which appear in instructions. These are set by |
| 884 | mips_ip. */ |
| 885 | |
| 886 | static expressionS imm_expr; |
| 887 | static expressionS offset_expr; |
| 888 | |
| 889 | /* Relocs associated with imm_expr and offset_expr. */ |
| 890 | |
| 891 | static bfd_reloc_code_real_type imm_reloc; |
| 892 | static bfd_reloc_code_real_type offset_reloc; |
| 893 | |
| 894 | /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */ |
| 895 | |
| 896 | static boolean imm_unmatched_hi; |
| 897 | |
| 898 | /* These are set by mips16_ip if an explicit extension is used. */ |
| 899 | |
| 900 | static boolean mips16_small, mips16_ext; |
| 901 | |
| 902 | #ifdef MIPS_STABS_ELF |
| 903 | /* The pdr segment for per procedure frame/regmask info */ |
| 904 | |
| 905 | static segT pdr_seg; |
| 906 | #endif |
| 907 | |
| 908 | static const char * |
| 909 | mips_isa_to_str (isa) |
| 910 | int isa; |
| 911 | { |
| 912 | const struct mips_cpu_info *ci; |
| 913 | static char s[20]; |
| 914 | |
| 915 | ci = mips_cpu_info_from_isa (isa); |
| 916 | if (ci != NULL) |
| 917 | return (ci->name); |
| 918 | |
| 919 | sprintf (s, "ISA#%d", isa); |
| 920 | return s; |
| 921 | } |
| 922 | |
| 923 | static const char * |
| 924 | mips_cpu_to_str (cpu) |
| 925 | int cpu; |
| 926 | { |
| 927 | const struct mips_cpu_info *ci; |
| 928 | static char s[16]; |
| 929 | |
| 930 | ci = mips_cpu_info_from_cpu (cpu); |
| 931 | if (ci != NULL) |
| 932 | return (ci->name); |
| 933 | |
| 934 | sprintf (s, "CPU#%d", cpu); |
| 935 | return s; |
| 936 | } |
| 937 | |
| 938 | /* This function is called once, at assembler startup time. It should |
| 939 | set up all the tables, etc. that the MD part of the assembler will need. */ |
| 940 | |
| 941 | void |
| 942 | md_begin () |
| 943 | { |
| 944 | register const char *retval = NULL; |
| 945 | int i = 0; |
| 946 | const char *cpu; |
| 947 | char *a = NULL; |
| 948 | int broken = 0; |
| 949 | int mips_isa_from_cpu; |
| 950 | int target_cpu_had_mips16 = 0; |
| 951 | const struct mips_cpu_info *ci; |
| 952 | |
| 953 | /* GP relative stuff not working for PE */ |
| 954 | if (strncmp (TARGET_OS, "pe", 2) == 0 |
| 955 | && g_switch_value != 0) |
| 956 | { |
| 957 | if (g_switch_seen) |
| 958 | as_bad (_("-G not supported in this configuration.")); |
| 959 | g_switch_value = 0; |
| 960 | } |
| 961 | |
| 962 | cpu = TARGET_CPU; |
| 963 | if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0) |
| 964 | { |
| 965 | a = xmalloc (sizeof TARGET_CPU); |
| 966 | strcpy (a, TARGET_CPU); |
| 967 | a[(sizeof TARGET_CPU) - 3] = '\0'; |
| 968 | cpu = a; |
| 969 | } |
| 970 | |
| 971 | if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0) |
| 972 | { |
| 973 | target_cpu_had_mips16 = 1; |
| 974 | cpu += sizeof "mips16" - 1; |
| 975 | } |
| 976 | |
| 977 | if (mips_opts.mips16 < 0) |
| 978 | mips_opts.mips16 = target_cpu_had_mips16; |
| 979 | |
| 980 | /* Backward compatibility for historic -mcpu= option. Check for |
| 981 | incompatible options, warn if -mcpu is used. */ |
| 982 | if (mips_cpu != CPU_UNKNOWN |
| 983 | && mips_arch != CPU_UNKNOWN |
| 984 | && mips_cpu != mips_arch) |
| 985 | { |
| 986 | as_fatal (_("The -mcpu option can't be used together with -march. " |
| 987 | "Use -mtune instead of -mcpu.")); |
| 988 | } |
| 989 | |
| 990 | if (mips_cpu != CPU_UNKNOWN |
| 991 | && mips_tune != CPU_UNKNOWN |
| 992 | && mips_cpu != mips_tune) |
| 993 | { |
| 994 | as_fatal (_("The -mcpu option can't be used together with -mtune. " |
| 995 | "Use -march instead of -mcpu.")); |
| 996 | } |
| 997 | |
| 998 | if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN) |
| 999 | { |
| 1000 | ci = mips_cpu_info_from_cpu (mips_cpu); |
| 1001 | assert (ci != NULL); |
| 1002 | mips_arch = ci->cpu; |
| 1003 | as_warn (_("The -mcpu option is deprecated. Please use -march and " |
| 1004 | "-mtune instead.")); |
| 1005 | } |
| 1006 | |
| 1007 | /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was |
| 1008 | specified on the command line, or some other value if one was. |
| 1009 | Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on |
| 1010 | the command line, or will be set otherwise if one was. */ |
| 1011 | if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
| 1012 | { |
| 1013 | /* We have to check if the isa is the default isa of arch. Otherwise |
| 1014 | we'll get invalid object file headers. */ |
| 1015 | ci = mips_cpu_info_from_cpu (mips_arch); |
| 1016 | assert (ci != NULL); |
| 1017 | if (mips_opts.isa != ci->isa) |
| 1018 | { |
| 1019 | /* This really should be an error instead of a warning, but old |
| 1020 | compilers only have -mcpu which sets both arch and tune. For |
| 1021 | now, we discard arch and preserve tune. */ |
| 1022 | as_warn (_("The -march option is incompatible to -mipsN and " |
| 1023 | "therefore ignored.")); |
| 1024 | if (mips_tune == CPU_UNKNOWN) |
| 1025 | mips_tune = mips_arch; |
| 1026 | ci = mips_cpu_info_from_isa (mips_opts.isa); |
| 1027 | assert (ci != NULL); |
| 1028 | mips_arch = ci->cpu; |
| 1029 | } |
| 1030 | } |
| 1031 | else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) |
| 1032 | { |
| 1033 | /* We have ARCH, we need ISA. */ |
| 1034 | ci = mips_cpu_info_from_cpu (mips_arch); |
| 1035 | assert (ci != NULL); |
| 1036 | mips_opts.isa = ci->isa; |
| 1037 | } |
| 1038 | else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) |
| 1039 | { |
| 1040 | /* We have ISA, we need default ARCH. */ |
| 1041 | ci = mips_cpu_info_from_isa (mips_opts.isa); |
| 1042 | assert (ci != NULL); |
| 1043 | mips_arch = ci->cpu; |
| 1044 | } |
| 1045 | else |
| 1046 | { |
| 1047 | /* We need to set both ISA and ARCH from target cpu. */ |
| 1048 | ci = mips_cpu_info_from_name (cpu); |
| 1049 | if (ci == NULL) |
| 1050 | ci = mips_cpu_info_from_cpu (CPU_R3000); |
| 1051 | assert (ci != NULL); |
| 1052 | mips_opts.isa = ci->isa; |
| 1053 | mips_arch = ci->cpu; |
| 1054 | } |
| 1055 | |
| 1056 | if (mips_tune == CPU_UNKNOWN) |
| 1057 | mips_tune = mips_arch; |
| 1058 | |
| 1059 | ci = mips_cpu_info_from_cpu (mips_arch); |
| 1060 | assert (ci != NULL); |
| 1061 | mips_isa_from_cpu = ci->isa; |
| 1062 | |
| 1063 | /* End of TARGET_CPU processing, get rid of malloced memory |
| 1064 | if necessary. */ |
| 1065 | cpu = NULL; |
| 1066 | if (a != NULL) |
| 1067 | { |
| 1068 | free (a); |
| 1069 | a = NULL; |
| 1070 | } |
| 1071 | |
| 1072 | if (mips_opts.isa == ISA_MIPS1 && mips_trap) |
| 1073 | as_bad (_("trap exception not supported at ISA 1")); |
| 1074 | |
| 1075 | /* Set the EABI kind based on the ISA before the user gets |
| 1076 | to change the ISA with directives. This isn't really |
| 1077 | the best, but then neither is basing the abi on the isa. */ |
| 1078 | if (ISA_HAS_64BIT_REGS (mips_opts.isa) |
| 1079 | && mips_abi_string |
| 1080 | && 0 == strcmp (mips_abi_string, "eabi")) |
| 1081 | mips_eabi64 = 1; |
| 1082 | |
| 1083 | /* If they asked for mips1 or mips2 and a cpu that is |
| 1084 | mips3 or greater, then mark the object file 32BITMODE. */ |
| 1085 | if (mips_isa_from_cpu != ISA_UNKNOWN |
| 1086 | && ! ISA_HAS_64BIT_REGS (mips_opts.isa) |
| 1087 | && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) |
| 1088 | mips_32bitmode = 1; |
| 1089 | |
| 1090 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) |
| 1091 | as_warn (_("Could not set architecture and machine")); |
| 1092 | |
| 1093 | file_mips_isa = mips_opts.isa; |
| 1094 | |
| 1095 | op_hash = hash_new (); |
| 1096 | |
| 1097 | for (i = 0; i < NUMOPCODES;) |
| 1098 | { |
| 1099 | const char *name = mips_opcodes[i].name; |
| 1100 | |
| 1101 | retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]); |
| 1102 | if (retval != NULL) |
| 1103 | { |
| 1104 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), |
| 1105 | mips_opcodes[i].name, retval); |
| 1106 | /* Probably a memory allocation problem? Give up now. */ |
| 1107 | as_fatal (_("Broken assembler. No assembly attempted.")); |
| 1108 | } |
| 1109 | do |
| 1110 | { |
| 1111 | if (mips_opcodes[i].pinfo != INSN_MACRO) |
| 1112 | { |
| 1113 | if (!validate_mips_insn (&mips_opcodes[i])) |
| 1114 | broken = 1; |
| 1115 | } |
| 1116 | ++i; |
| 1117 | } |
| 1118 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); |
| 1119 | } |
| 1120 | |
| 1121 | mips16_op_hash = hash_new (); |
| 1122 | |
| 1123 | i = 0; |
| 1124 | while (i < bfd_mips16_num_opcodes) |
| 1125 | { |
| 1126 | const char *name = mips16_opcodes[i].name; |
| 1127 | |
| 1128 | retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]); |
| 1129 | if (retval != NULL) |
| 1130 | as_fatal (_("internal: can't hash `%s': %s"), |
| 1131 | mips16_opcodes[i].name, retval); |
| 1132 | do |
| 1133 | { |
| 1134 | if (mips16_opcodes[i].pinfo != INSN_MACRO |
| 1135 | && ((mips16_opcodes[i].match & mips16_opcodes[i].mask) |
| 1136 | != mips16_opcodes[i].match)) |
| 1137 | { |
| 1138 | fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"), |
| 1139 | mips16_opcodes[i].name, mips16_opcodes[i].args); |
| 1140 | broken = 1; |
| 1141 | } |
| 1142 | ++i; |
| 1143 | } |
| 1144 | while (i < bfd_mips16_num_opcodes |
| 1145 | && strcmp (mips16_opcodes[i].name, name) == 0); |
| 1146 | } |
| 1147 | |
| 1148 | if (broken) |
| 1149 | as_fatal (_("Broken assembler. No assembly attempted.")); |
| 1150 | |
| 1151 | /* We add all the general register names to the symbol table. This |
| 1152 | helps us detect invalid uses of them. */ |
| 1153 | for (i = 0; i < 32; i++) |
| 1154 | { |
| 1155 | char buf[5]; |
| 1156 | |
| 1157 | sprintf (buf, "$%d", i); |
| 1158 | symbol_table_insert (symbol_new (buf, reg_section, i, |
| 1159 | &zero_address_frag)); |
| 1160 | } |
| 1161 | symbol_table_insert (symbol_new ("$fp", reg_section, FP, |
| 1162 | &zero_address_frag)); |
| 1163 | symbol_table_insert (symbol_new ("$sp", reg_section, SP, |
| 1164 | &zero_address_frag)); |
| 1165 | symbol_table_insert (symbol_new ("$gp", reg_section, GP, |
| 1166 | &zero_address_frag)); |
| 1167 | symbol_table_insert (symbol_new ("$at", reg_section, AT, |
| 1168 | &zero_address_frag)); |
| 1169 | symbol_table_insert (symbol_new ("$kt0", reg_section, KT0, |
| 1170 | &zero_address_frag)); |
| 1171 | symbol_table_insert (symbol_new ("$kt1", reg_section, KT1, |
| 1172 | &zero_address_frag)); |
| 1173 | symbol_table_insert (symbol_new ("$pc", reg_section, -1, |
| 1174 | &zero_address_frag)); |
| 1175 | |
| 1176 | mips_no_prev_insn (false); |
| 1177 | |
| 1178 | mips_gprmask = 0; |
| 1179 | mips_cprmask[0] = 0; |
| 1180 | mips_cprmask[1] = 0; |
| 1181 | mips_cprmask[2] = 0; |
| 1182 | mips_cprmask[3] = 0; |
| 1183 | |
| 1184 | /* set the default alignment for the text section (2**2) */ |
| 1185 | record_alignment (text_section, 2); |
| 1186 | |
| 1187 | if (USE_GLOBAL_POINTER_OPT) |
| 1188 | bfd_set_gp_size (stdoutput, g_switch_value); |
| 1189 | |
| 1190 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 1191 | { |
| 1192 | /* On a native system, sections must be aligned to 16 byte |
| 1193 | boundaries. When configured for an embedded ELF target, we |
| 1194 | don't bother. */ |
| 1195 | if (strcmp (TARGET_OS, "elf") != 0) |
| 1196 | { |
| 1197 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
| 1198 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); |
| 1199 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); |
| 1200 | } |
| 1201 | |
| 1202 | /* Create a .reginfo section for register masks and a .mdebug |
| 1203 | section for debugging information. */ |
| 1204 | { |
| 1205 | segT seg; |
| 1206 | subsegT subseg; |
| 1207 | flagword flags; |
| 1208 | segT sec; |
| 1209 | |
| 1210 | seg = now_seg; |
| 1211 | subseg = now_subseg; |
| 1212 | |
| 1213 | /* The ABI says this section should be loaded so that the |
| 1214 | running program can access it. However, we don't load it |
| 1215 | if we are configured for an embedded target */ |
| 1216 | flags = SEC_READONLY | SEC_DATA; |
| 1217 | if (strcmp (TARGET_OS, "elf") != 0) |
| 1218 | flags |= SEC_ALLOC | SEC_LOAD; |
| 1219 | |
| 1220 | if (! mips_64) |
| 1221 | { |
| 1222 | sec = subseg_new (".reginfo", (subsegT) 0); |
| 1223 | |
| 1224 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
| 1225 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
| 1226 | |
| 1227 | #ifdef OBJ_ELF |
| 1228 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
| 1229 | #endif |
| 1230 | } |
| 1231 | else |
| 1232 | { |
| 1233 | /* The 64-bit ABI uses a .MIPS.options section rather than |
| 1234 | .reginfo section. */ |
| 1235 | sec = subseg_new (".MIPS.options", (subsegT) 0); |
| 1236 | (void) bfd_set_section_flags (stdoutput, sec, flags); |
| 1237 | (void) bfd_set_section_alignment (stdoutput, sec, 3); |
| 1238 | |
| 1239 | #ifdef OBJ_ELF |
| 1240 | /* Set up the option header. */ |
| 1241 | { |
| 1242 | Elf_Internal_Options opthdr; |
| 1243 | char *f; |
| 1244 | |
| 1245 | opthdr.kind = ODK_REGINFO; |
| 1246 | opthdr.size = (sizeof (Elf_External_Options) |
| 1247 | + sizeof (Elf64_External_RegInfo)); |
| 1248 | opthdr.section = 0; |
| 1249 | opthdr.info = 0; |
| 1250 | f = frag_more (sizeof (Elf_External_Options)); |
| 1251 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, |
| 1252 | (Elf_External_Options *) f); |
| 1253 | |
| 1254 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); |
| 1255 | } |
| 1256 | #endif |
| 1257 | } |
| 1258 | |
| 1259 | if (ECOFF_DEBUGGING) |
| 1260 | { |
| 1261 | sec = subseg_new (".mdebug", (subsegT) 0); |
| 1262 | (void) bfd_set_section_flags (stdoutput, sec, |
| 1263 | SEC_HAS_CONTENTS | SEC_READONLY); |
| 1264 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
| 1265 | } |
| 1266 | |
| 1267 | #ifdef MIPS_STABS_ELF |
| 1268 | pdr_seg = subseg_new (".pdr", (subsegT) 0); |
| 1269 | (void) bfd_set_section_flags (stdoutput, pdr_seg, |
| 1270 | SEC_READONLY | SEC_RELOC | SEC_DEBUGGING); |
| 1271 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); |
| 1272 | #endif |
| 1273 | |
| 1274 | subseg_set (seg, subseg); |
| 1275 | } |
| 1276 | } |
| 1277 | |
| 1278 | if (! ECOFF_DEBUGGING) |
| 1279 | md_obj_begin (); |
| 1280 | } |
| 1281 | |
| 1282 | void |
| 1283 | md_mips_end () |
| 1284 | { |
| 1285 | if (! ECOFF_DEBUGGING) |
| 1286 | md_obj_end (); |
| 1287 | } |
| 1288 | |
| 1289 | void |
| 1290 | md_assemble (str) |
| 1291 | char *str; |
| 1292 | { |
| 1293 | struct mips_cl_insn insn; |
| 1294 | |
| 1295 | imm_expr.X_op = O_absent; |
| 1296 | imm_reloc = BFD_RELOC_UNUSED; |
| 1297 | imm_unmatched_hi = false; |
| 1298 | offset_expr.X_op = O_absent; |
| 1299 | offset_reloc = BFD_RELOC_UNUSED; |
| 1300 | |
| 1301 | if (mips_opts.mips16) |
| 1302 | mips16_ip (str, &insn); |
| 1303 | else |
| 1304 | { |
| 1305 | mips_ip (str, &insn); |
| 1306 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
| 1307 | str, insn.insn_opcode)); |
| 1308 | } |
| 1309 | |
| 1310 | if (insn_error) |
| 1311 | { |
| 1312 | as_bad ("%s `%s'", insn_error, str); |
| 1313 | return; |
| 1314 | } |
| 1315 | |
| 1316 | if (insn.insn_mo->pinfo == INSN_MACRO) |
| 1317 | { |
| 1318 | if (mips_opts.mips16) |
| 1319 | mips16_macro (&insn); |
| 1320 | else |
| 1321 | macro (&insn); |
| 1322 | } |
| 1323 | else |
| 1324 | { |
| 1325 | if (imm_expr.X_op != O_absent) |
| 1326 | append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc, |
| 1327 | imm_unmatched_hi); |
| 1328 | else if (offset_expr.X_op != O_absent) |
| 1329 | append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false); |
| 1330 | else |
| 1331 | append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false); |
| 1332 | } |
| 1333 | } |
| 1334 | |
| 1335 | /* See whether instruction IP reads register REG. CLASS is the type |
| 1336 | of register. */ |
| 1337 | |
| 1338 | static int |
| 1339 | insn_uses_reg (ip, reg, class) |
| 1340 | struct mips_cl_insn *ip; |
| 1341 | unsigned int reg; |
| 1342 | enum mips_regclass class; |
| 1343 | { |
| 1344 | if (class == MIPS16_REG) |
| 1345 | { |
| 1346 | assert (mips_opts.mips16); |
| 1347 | reg = mips16_to_32_reg_map[reg]; |
| 1348 | class = MIPS_GR_REG; |
| 1349 | } |
| 1350 | |
| 1351 | /* Don't report on general register 0, since it never changes. */ |
| 1352 | if (class == MIPS_GR_REG && reg == 0) |
| 1353 | return 0; |
| 1354 | |
| 1355 | if (class == MIPS_FP_REG) |
| 1356 | { |
| 1357 | assert (! mips_opts.mips16); |
| 1358 | /* If we are called with either $f0 or $f1, we must check $f0. |
| 1359 | This is not optimal, because it will introduce an unnecessary |
| 1360 | NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would |
| 1361 | need to distinguish reading both $f0 and $f1 or just one of |
| 1362 | them. Note that we don't have to check the other way, |
| 1363 | because there is no instruction that sets both $f0 and $f1 |
| 1364 | and requires a delay. */ |
| 1365 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_S) |
| 1366 | && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1) |
| 1367 | == (reg &~ (unsigned) 1))) |
| 1368 | return 1; |
| 1369 | if ((ip->insn_mo->pinfo & INSN_READ_FPR_T) |
| 1370 | && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1) |
| 1371 | == (reg &~ (unsigned) 1))) |
| 1372 | return 1; |
| 1373 | } |
| 1374 | else if (! mips_opts.mips16) |
| 1375 | { |
| 1376 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_S) |
| 1377 | && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg) |
| 1378 | return 1; |
| 1379 | if ((ip->insn_mo->pinfo & INSN_READ_GPR_T) |
| 1380 | && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg) |
| 1381 | return 1; |
| 1382 | } |
| 1383 | else |
| 1384 | { |
| 1385 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X) |
| 1386 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX) |
| 1387 | & MIPS16OP_MASK_RX)] |
| 1388 | == reg)) |
| 1389 | return 1; |
| 1390 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y) |
| 1391 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY) |
| 1392 | & MIPS16OP_MASK_RY)] |
| 1393 | == reg)) |
| 1394 | return 1; |
| 1395 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z) |
| 1396 | && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
| 1397 | & MIPS16OP_MASK_MOVE32Z)] |
| 1398 | == reg)) |
| 1399 | return 1; |
| 1400 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG) |
| 1401 | return 1; |
| 1402 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP) |
| 1403 | return 1; |
| 1404 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA) |
| 1405 | return 1; |
| 1406 | if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X) |
| 1407 | && ((ip->insn_opcode >> MIPS16OP_SH_REGR32) |
| 1408 | & MIPS16OP_MASK_REGR32) == reg) |
| 1409 | return 1; |
| 1410 | } |
| 1411 | |
| 1412 | return 0; |
| 1413 | } |
| 1414 | |
| 1415 | /* This function returns true if modifying a register requires a |
| 1416 | delay. */ |
| 1417 | |
| 1418 | static int |
| 1419 | reg_needs_delay (reg) |
| 1420 | unsigned int reg; |
| 1421 | { |
| 1422 | unsigned long prev_pinfo; |
| 1423 | |
| 1424 | prev_pinfo = prev_insn.insn_mo->pinfo; |
| 1425 | if (! mips_opts.noreorder |
| 1426 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1427 | && ((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
| 1428 | || (! gpr_interlocks |
| 1429 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
| 1430 | { |
| 1431 | /* A load from a coprocessor or from memory. All load |
| 1432 | delays delay the use of general register rt for one |
| 1433 | instruction on the r3000. The r6000 and r4000 use |
| 1434 | interlocks. */ |
| 1435 | /* Itbl support may require additional care here. */ |
| 1436 | know (prev_pinfo & INSN_WRITE_GPR_T); |
| 1437 | if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)) |
| 1438 | return 1; |
| 1439 | } |
| 1440 | |
| 1441 | return 0; |
| 1442 | } |
| 1443 | |
| 1444 | /* Mark instruction labels in mips16 mode. This permits the linker to |
| 1445 | handle them specially, such as generating jalx instructions when |
| 1446 | needed. We also make them odd for the duration of the assembly, in |
| 1447 | order to generate the right sort of code. We will make them even |
| 1448 | in the adjust_symtab routine, while leaving them marked. This is |
| 1449 | convenient for the debugger and the disassembler. The linker knows |
| 1450 | to make them odd again. */ |
| 1451 | |
| 1452 | static void |
| 1453 | mips16_mark_labels () |
| 1454 | { |
| 1455 | if (mips_opts.mips16) |
| 1456 | { |
| 1457 | struct insn_label_list *l; |
| 1458 | valueT val; |
| 1459 | |
| 1460 | for (l = insn_labels; l != NULL; l = l->next) |
| 1461 | { |
| 1462 | #ifdef OBJ_ELF |
| 1463 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 1464 | S_SET_OTHER (l->label, STO_MIPS16); |
| 1465 | #endif |
| 1466 | val = S_GET_VALUE (l->label); |
| 1467 | if ((val & 1) == 0) |
| 1468 | S_SET_VALUE (l->label, val + 1); |
| 1469 | } |
| 1470 | } |
| 1471 | } |
| 1472 | |
| 1473 | /* Output an instruction. PLACE is where to put the instruction; if |
| 1474 | it is NULL, this uses frag_more to get room. IP is the instruction |
| 1475 | information. ADDRESS_EXPR is an operand of the instruction to be |
| 1476 | used with RELOC_TYPE. */ |
| 1477 | |
| 1478 | static void |
| 1479 | append_insn (place, ip, address_expr, reloc_type, unmatched_hi) |
| 1480 | char *place; |
| 1481 | struct mips_cl_insn *ip; |
| 1482 | expressionS *address_expr; |
| 1483 | bfd_reloc_code_real_type reloc_type; |
| 1484 | boolean unmatched_hi; |
| 1485 | { |
| 1486 | register unsigned long prev_pinfo, pinfo; |
| 1487 | char *f; |
| 1488 | fixS *fixp; |
| 1489 | int nops = 0; |
| 1490 | |
| 1491 | /* Mark instruction labels in mips16 mode. */ |
| 1492 | if (mips_opts.mips16) |
| 1493 | mips16_mark_labels (); |
| 1494 | |
| 1495 | prev_pinfo = prev_insn.insn_mo->pinfo; |
| 1496 | pinfo = ip->insn_mo->pinfo; |
| 1497 | |
| 1498 | if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL)) |
| 1499 | { |
| 1500 | int prev_prev_nop; |
| 1501 | |
| 1502 | /* If the previous insn required any delay slots, see if we need |
| 1503 | to insert a NOP or two. There are eight kinds of possible |
| 1504 | hazards, of which an instruction can have at most one type. |
| 1505 | (1) a load from memory delay |
| 1506 | (2) a load from a coprocessor delay |
| 1507 | (3) an unconditional branch delay |
| 1508 | (4) a conditional branch delay |
| 1509 | (5) a move to coprocessor register delay |
| 1510 | (6) a load coprocessor register from memory delay |
| 1511 | (7) a coprocessor condition code delay |
| 1512 | (8) a HI/LO special register delay |
| 1513 | |
| 1514 | There are a lot of optimizations we could do that we don't. |
| 1515 | In particular, we do not, in general, reorder instructions. |
| 1516 | If you use gcc with optimization, it will reorder |
| 1517 | instructions and generally do much more optimization then we |
| 1518 | do here; repeating all that work in the assembler would only |
| 1519 | benefit hand written assembly code, and does not seem worth |
| 1520 | it. */ |
| 1521 | |
| 1522 | /* This is how a NOP is emitted. */ |
| 1523 | #define emit_nop() \ |
| 1524 | (mips_opts.mips16 \ |
| 1525 | ? md_number_to_chars (frag_more (2), 0x6500, 2) \ |
| 1526 | : md_number_to_chars (frag_more (4), 0, 4)) |
| 1527 | |
| 1528 | /* The previous insn might require a delay slot, depending upon |
| 1529 | the contents of the current insn. */ |
| 1530 | if (! mips_opts.mips16 |
| 1531 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1532 | && (((prev_pinfo & INSN_LOAD_COPROC_DELAY) |
| 1533 | && ! cop_interlocks) |
| 1534 | || (! gpr_interlocks |
| 1535 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)))) |
| 1536 | { |
| 1537 | /* A load from a coprocessor or from memory. All load |
| 1538 | delays delay the use of general register rt for one |
| 1539 | instruction on the r3000. The r6000 and r4000 use |
| 1540 | interlocks. */ |
| 1541 | /* Itbl support may require additional care here. */ |
| 1542 | know (prev_pinfo & INSN_WRITE_GPR_T); |
| 1543 | if (mips_optimize == 0 |
| 1544 | || insn_uses_reg (ip, |
| 1545 | ((prev_insn.insn_opcode >> OP_SH_RT) |
| 1546 | & OP_MASK_RT), |
| 1547 | MIPS_GR_REG)) |
| 1548 | ++nops; |
| 1549 | } |
| 1550 | else if (! mips_opts.mips16 |
| 1551 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1552 | && (((prev_pinfo & INSN_COPROC_MOVE_DELAY) |
| 1553 | && ! cop_interlocks) |
| 1554 | || (mips_opts.isa == ISA_MIPS1 |
| 1555 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)))) |
| 1556 | { |
| 1557 | /* A generic coprocessor delay. The previous instruction |
| 1558 | modified a coprocessor general or control register. If |
| 1559 | it modified a control register, we need to avoid any |
| 1560 | coprocessor instruction (this is probably not always |
| 1561 | required, but it sometimes is). If it modified a general |
| 1562 | register, we avoid using that register. |
| 1563 | |
| 1564 | On the r6000 and r4000 loading a coprocessor register |
| 1565 | from memory is interlocked, and does not require a delay. |
| 1566 | |
| 1567 | This case is not handled very well. There is no special |
| 1568 | knowledge of CP0 handling, and the coprocessors other |
| 1569 | than the floating point unit are not distinguished at |
| 1570 | all. */ |
| 1571 | /* Itbl support may require additional care here. FIXME! |
| 1572 | Need to modify this to include knowledge about |
| 1573 | user specified delays! */ |
| 1574 | if (prev_pinfo & INSN_WRITE_FPR_T) |
| 1575 | { |
| 1576 | if (mips_optimize == 0 |
| 1577 | || insn_uses_reg (ip, |
| 1578 | ((prev_insn.insn_opcode >> OP_SH_FT) |
| 1579 | & OP_MASK_FT), |
| 1580 | MIPS_FP_REG)) |
| 1581 | ++nops; |
| 1582 | } |
| 1583 | else if (prev_pinfo & INSN_WRITE_FPR_S) |
| 1584 | { |
| 1585 | if (mips_optimize == 0 |
| 1586 | || insn_uses_reg (ip, |
| 1587 | ((prev_insn.insn_opcode >> OP_SH_FS) |
| 1588 | & OP_MASK_FS), |
| 1589 | MIPS_FP_REG)) |
| 1590 | ++nops; |
| 1591 | } |
| 1592 | else |
| 1593 | { |
| 1594 | /* We don't know exactly what the previous instruction |
| 1595 | does. If the current instruction uses a coprocessor |
| 1596 | register, we must insert a NOP. If previous |
| 1597 | instruction may set the condition codes, and the |
| 1598 | current instruction uses them, we must insert two |
| 1599 | NOPS. */ |
| 1600 | /* Itbl support may require additional care here. */ |
| 1601 | if (mips_optimize == 0 |
| 1602 | || ((prev_pinfo & INSN_WRITE_COND_CODE) |
| 1603 | && (pinfo & INSN_READ_COND_CODE))) |
| 1604 | nops += 2; |
| 1605 | else if (pinfo & INSN_COP) |
| 1606 | ++nops; |
| 1607 | } |
| 1608 | } |
| 1609 | else if (! mips_opts.mips16 |
| 1610 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1611 | && (prev_pinfo & INSN_WRITE_COND_CODE) |
| 1612 | && ! cop_interlocks) |
| 1613 | { |
| 1614 | /* The previous instruction sets the coprocessor condition |
| 1615 | codes, but does not require a general coprocessor delay |
| 1616 | (this means it is a floating point comparison |
| 1617 | instruction). If this instruction uses the condition |
| 1618 | codes, we need to insert a single NOP. */ |
| 1619 | /* Itbl support may require additional care here. */ |
| 1620 | if (mips_optimize == 0 |
| 1621 | || (pinfo & INSN_READ_COND_CODE)) |
| 1622 | ++nops; |
| 1623 | } |
| 1624 | |
| 1625 | /* If we're fixing up mfhi/mflo for the r7000 and the |
| 1626 | previous insn was an mfhi/mflo and the current insn |
| 1627 | reads the register that the mfhi/mflo wrote to, then |
| 1628 | insert two nops. */ |
| 1629 | |
| 1630 | else if (mips_7000_hilo_fix |
| 1631 | && MF_HILO_INSN (prev_pinfo) |
| 1632 | && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD) |
| 1633 | & OP_MASK_RD), |
| 1634 | MIPS_GR_REG)) |
| 1635 | { |
| 1636 | nops += 2; |
| 1637 | } |
| 1638 | |
| 1639 | /* If we're fixing up mfhi/mflo for the r7000 and the |
| 1640 | 2nd previous insn was an mfhi/mflo and the current insn |
| 1641 | reads the register that the mfhi/mflo wrote to, then |
| 1642 | insert one nop. */ |
| 1643 | |
| 1644 | else if (mips_7000_hilo_fix |
| 1645 | && MF_HILO_INSN (prev_prev_insn.insn_opcode) |
| 1646 | && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD) |
| 1647 | & OP_MASK_RD), |
| 1648 | MIPS_GR_REG)) |
| 1649 | |
| 1650 | { |
| 1651 | nops += 1; |
| 1652 | } |
| 1653 | |
| 1654 | else if (prev_pinfo & INSN_READ_LO) |
| 1655 | { |
| 1656 | /* The previous instruction reads the LO register; if the |
| 1657 | current instruction writes to the LO register, we must |
| 1658 | insert two NOPS. Some newer processors have interlocks. |
| 1659 | Also the tx39's multiply instructions can be exectuted |
| 1660 | immediatly after a read from HI/LO (without the delay), |
| 1661 | though the tx39's divide insns still do require the |
| 1662 | delay. */ |
| 1663 | if (! (hilo_interlocks |
| 1664 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
| 1665 | && (mips_optimize == 0 |
| 1666 | || (pinfo & INSN_WRITE_LO))) |
| 1667 | nops += 2; |
| 1668 | /* Most mips16 branch insns don't have a delay slot. |
| 1669 | If a read from LO is immediately followed by a branch |
| 1670 | to a write to LO we have a read followed by a write |
| 1671 | less than 2 insns away. We assume the target of |
| 1672 | a branch might be a write to LO, and insert a nop |
| 1673 | between a read and an immediately following branch. */ |
| 1674 | else if (mips_opts.mips16 |
| 1675 | && (mips_optimize == 0 |
| 1676 | || (pinfo & MIPS16_INSN_BRANCH))) |
| 1677 | nops += 1; |
| 1678 | } |
| 1679 | else if (prev_insn.insn_mo->pinfo & INSN_READ_HI) |
| 1680 | { |
| 1681 | /* The previous instruction reads the HI register; if the |
| 1682 | current instruction writes to the HI register, we must |
| 1683 | insert a NOP. Some newer processors have interlocks. |
| 1684 | Also the note tx39's multiply above. */ |
| 1685 | if (! (hilo_interlocks |
| 1686 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
| 1687 | && (mips_optimize == 0 |
| 1688 | || (pinfo & INSN_WRITE_HI))) |
| 1689 | nops += 2; |
| 1690 | /* Most mips16 branch insns don't have a delay slot. |
| 1691 | If a read from HI is immediately followed by a branch |
| 1692 | to a write to HI we have a read followed by a write |
| 1693 | less than 2 insns away. We assume the target of |
| 1694 | a branch might be a write to HI, and insert a nop |
| 1695 | between a read and an immediately following branch. */ |
| 1696 | else if (mips_opts.mips16 |
| 1697 | && (mips_optimize == 0 |
| 1698 | || (pinfo & MIPS16_INSN_BRANCH))) |
| 1699 | nops += 1; |
| 1700 | } |
| 1701 | |
| 1702 | /* If the previous instruction was in a noreorder section, then |
| 1703 | we don't want to insert the nop after all. */ |
| 1704 | /* Itbl support may require additional care here. */ |
| 1705 | if (prev_insn_unreordered) |
| 1706 | nops = 0; |
| 1707 | |
| 1708 | /* There are two cases which require two intervening |
| 1709 | instructions: 1) setting the condition codes using a move to |
| 1710 | coprocessor instruction which requires a general coprocessor |
| 1711 | delay and then reading the condition codes 2) reading the HI |
| 1712 | or LO register and then writing to it (except on processors |
| 1713 | which have interlocks). If we are not already emitting a NOP |
| 1714 | instruction, we must check for these cases compared to the |
| 1715 | instruction previous to the previous instruction. */ |
| 1716 | if ((! mips_opts.mips16 |
| 1717 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 1718 | && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY) |
| 1719 | && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE) |
| 1720 | && (pinfo & INSN_READ_COND_CODE) |
| 1721 | && ! cop_interlocks) |
| 1722 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) |
| 1723 | && (pinfo & INSN_WRITE_LO) |
| 1724 | && ! (hilo_interlocks |
| 1725 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) |
| 1726 | || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
| 1727 | && (pinfo & INSN_WRITE_HI) |
| 1728 | && ! (hilo_interlocks |
| 1729 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) |
| 1730 | prev_prev_nop = 1; |
| 1731 | else |
| 1732 | prev_prev_nop = 0; |
| 1733 | |
| 1734 | if (prev_prev_insn_unreordered) |
| 1735 | prev_prev_nop = 0; |
| 1736 | |
| 1737 | if (prev_prev_nop && nops == 0) |
| 1738 | ++nops; |
| 1739 | |
| 1740 | /* If we are being given a nop instruction, don't bother with |
| 1741 | one of the nops we would otherwise output. This will only |
| 1742 | happen when a nop instruction is used with mips_optimize set |
| 1743 | to 0. */ |
| 1744 | if (nops > 0 |
| 1745 | && ! mips_opts.noreorder |
| 1746 | && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0)) |
| 1747 | --nops; |
| 1748 | |
| 1749 | /* Now emit the right number of NOP instructions. */ |
| 1750 | if (nops > 0 && ! mips_opts.noreorder) |
| 1751 | { |
| 1752 | fragS *old_frag; |
| 1753 | unsigned long old_frag_offset; |
| 1754 | int i; |
| 1755 | struct insn_label_list *l; |
| 1756 | |
| 1757 | old_frag = frag_now; |
| 1758 | old_frag_offset = frag_now_fix (); |
| 1759 | |
| 1760 | for (i = 0; i < nops; i++) |
| 1761 | emit_nop (); |
| 1762 | |
| 1763 | if (listing) |
| 1764 | { |
| 1765 | listing_prev_line (); |
| 1766 | /* We may be at the start of a variant frag. In case we |
| 1767 | are, make sure there is enough space for the frag |
| 1768 | after the frags created by listing_prev_line. The |
| 1769 | argument to frag_grow here must be at least as large |
| 1770 | as the argument to all other calls to frag_grow in |
| 1771 | this file. We don't have to worry about being in the |
| 1772 | middle of a variant frag, because the variants insert |
| 1773 | all needed nop instructions themselves. */ |
| 1774 | frag_grow (40); |
| 1775 | } |
| 1776 | |
| 1777 | for (l = insn_labels; l != NULL; l = l->next) |
| 1778 | { |
| 1779 | valueT val; |
| 1780 | |
| 1781 | assert (S_GET_SEGMENT (l->label) == now_seg); |
| 1782 | symbol_set_frag (l->label, frag_now); |
| 1783 | val = (valueT) frag_now_fix (); |
| 1784 | /* mips16 text labels are stored as odd. */ |
| 1785 | if (mips_opts.mips16) |
| 1786 | val += 1; |
| 1787 | S_SET_VALUE (l->label, val); |
| 1788 | } |
| 1789 | |
| 1790 | #ifndef NO_ECOFF_DEBUGGING |
| 1791 | if (ECOFF_DEBUGGING) |
| 1792 | ecoff_fix_loc (old_frag, old_frag_offset); |
| 1793 | #endif |
| 1794 | } |
| 1795 | else if (prev_nop_frag != NULL) |
| 1796 | { |
| 1797 | /* We have a frag holding nops we may be able to remove. If |
| 1798 | we don't need any nops, we can decrease the size of |
| 1799 | prev_nop_frag by the size of one instruction. If we do |
| 1800 | need some nops, we count them in prev_nops_required. */ |
| 1801 | if (prev_nop_frag_since == 0) |
| 1802 | { |
| 1803 | if (nops == 0) |
| 1804 | { |
| 1805 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
| 1806 | --prev_nop_frag_holds; |
| 1807 | } |
| 1808 | else |
| 1809 | prev_nop_frag_required += nops; |
| 1810 | } |
| 1811 | else |
| 1812 | { |
| 1813 | if (prev_prev_nop == 0) |
| 1814 | { |
| 1815 | prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4; |
| 1816 | --prev_nop_frag_holds; |
| 1817 | } |
| 1818 | else |
| 1819 | ++prev_nop_frag_required; |
| 1820 | } |
| 1821 | |
| 1822 | if (prev_nop_frag_holds <= prev_nop_frag_required) |
| 1823 | prev_nop_frag = NULL; |
| 1824 | |
| 1825 | ++prev_nop_frag_since; |
| 1826 | |
| 1827 | /* Sanity check: by the time we reach the second instruction |
| 1828 | after prev_nop_frag, we should have used up all the nops |
| 1829 | one way or another. */ |
| 1830 | assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL); |
| 1831 | } |
| 1832 | } |
| 1833 | |
| 1834 | if (reloc_type > BFD_RELOC_UNUSED) |
| 1835 | { |
| 1836 | /* We need to set up a variant frag. */ |
| 1837 | assert (mips_opts.mips16 && address_expr != NULL); |
| 1838 | f = frag_var (rs_machine_dependent, 4, 0, |
| 1839 | RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED, |
| 1840 | mips16_small, mips16_ext, |
| 1841 | (prev_pinfo |
| 1842 | & INSN_UNCOND_BRANCH_DELAY), |
| 1843 | (prev_insn_reloc_type |
| 1844 | == BFD_RELOC_MIPS16_JMP)), |
| 1845 | make_expr_symbol (address_expr), (offsetT) 0, |
| 1846 | (char *) NULL); |
| 1847 | } |
| 1848 | else if (place != NULL) |
| 1849 | f = place; |
| 1850 | else if (mips_opts.mips16 |
| 1851 | && ! ip->use_extend |
| 1852 | && reloc_type != BFD_RELOC_MIPS16_JMP) |
| 1853 | { |
| 1854 | /* Make sure there is enough room to swap this instruction with |
| 1855 | a following jump instruction. */ |
| 1856 | frag_grow (6); |
| 1857 | f = frag_more (2); |
| 1858 | } |
| 1859 | else |
| 1860 | { |
| 1861 | if (mips_opts.mips16 |
| 1862 | && mips_opts.noreorder |
| 1863 | && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) |
| 1864 | as_warn (_("extended instruction in delay slot")); |
| 1865 | |
| 1866 | f = frag_more (4); |
| 1867 | } |
| 1868 | |
| 1869 | fixp = NULL; |
| 1870 | if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED) |
| 1871 | { |
| 1872 | if (address_expr->X_op == O_constant) |
| 1873 | { |
| 1874 | switch (reloc_type) |
| 1875 | { |
| 1876 | case BFD_RELOC_32: |
| 1877 | ip->insn_opcode |= address_expr->X_add_number; |
| 1878 | break; |
| 1879 | |
| 1880 | case BFD_RELOC_LO16: |
| 1881 | ip->insn_opcode |= address_expr->X_add_number & 0xffff; |
| 1882 | break; |
| 1883 | |
| 1884 | case BFD_RELOC_MIPS_JMP: |
| 1885 | if ((address_expr->X_add_number & 3) != 0) |
| 1886 | as_bad (_("jump to misaligned address (0x%lx)"), |
| 1887 | (unsigned long) address_expr->X_add_number); |
| 1888 | ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff; |
| 1889 | break; |
| 1890 | |
| 1891 | case BFD_RELOC_MIPS16_JMP: |
| 1892 | if ((address_expr->X_add_number & 3) != 0) |
| 1893 | as_bad (_("jump to misaligned address (0x%lx)"), |
| 1894 | (unsigned long) address_expr->X_add_number); |
| 1895 | ip->insn_opcode |= |
| 1896 | (((address_expr->X_add_number & 0x7c0000) << 3) |
| 1897 | | ((address_expr->X_add_number & 0xf800000) >> 7) |
| 1898 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); |
| 1899 | break; |
| 1900 | |
| 1901 | case BFD_RELOC_16_PCREL_S2: |
| 1902 | goto need_reloc; |
| 1903 | |
| 1904 | default: |
| 1905 | internalError (); |
| 1906 | } |
| 1907 | } |
| 1908 | else |
| 1909 | { |
| 1910 | need_reloc: |
| 1911 | /* Don't generate a reloc if we are writing into a variant |
| 1912 | frag. */ |
| 1913 | if (place == NULL) |
| 1914 | { |
| 1915 | fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4, |
| 1916 | address_expr, |
| 1917 | reloc_type == BFD_RELOC_16_PCREL_S2, |
| 1918 | reloc_type); |
| 1919 | if (unmatched_hi) |
| 1920 | { |
| 1921 | struct mips_hi_fixup *hi_fixup; |
| 1922 | |
| 1923 | assert (reloc_type == BFD_RELOC_HI16_S); |
| 1924 | hi_fixup = ((struct mips_hi_fixup *) |
| 1925 | xmalloc (sizeof (struct mips_hi_fixup))); |
| 1926 | hi_fixup->fixp = fixp; |
| 1927 | hi_fixup->seg = now_seg; |
| 1928 | hi_fixup->next = mips_hi_fixup_list; |
| 1929 | mips_hi_fixup_list = hi_fixup; |
| 1930 | } |
| 1931 | } |
| 1932 | } |
| 1933 | } |
| 1934 | |
| 1935 | if (! mips_opts.mips16) |
| 1936 | md_number_to_chars (f, ip->insn_opcode, 4); |
| 1937 | else if (reloc_type == BFD_RELOC_MIPS16_JMP) |
| 1938 | { |
| 1939 | md_number_to_chars (f, ip->insn_opcode >> 16, 2); |
| 1940 | md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2); |
| 1941 | } |
| 1942 | else |
| 1943 | { |
| 1944 | if (ip->use_extend) |
| 1945 | { |
| 1946 | md_number_to_chars (f, 0xf000 | ip->extend, 2); |
| 1947 | f += 2; |
| 1948 | } |
| 1949 | md_number_to_chars (f, ip->insn_opcode, 2); |
| 1950 | } |
| 1951 | |
| 1952 | /* Update the register mask information. */ |
| 1953 | if (! mips_opts.mips16) |
| 1954 | { |
| 1955 | if (pinfo & INSN_WRITE_GPR_D) |
| 1956 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD); |
| 1957 | if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0) |
| 1958 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT); |
| 1959 | if (pinfo & INSN_READ_GPR_S) |
| 1960 | mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS); |
| 1961 | if (pinfo & INSN_WRITE_GPR_31) |
| 1962 | mips_gprmask |= 1 << 31; |
| 1963 | if (pinfo & INSN_WRITE_FPR_D) |
| 1964 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD); |
| 1965 | if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0) |
| 1966 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS); |
| 1967 | if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0) |
| 1968 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT); |
| 1969 | if ((pinfo & INSN_READ_FPR_R) != 0) |
| 1970 | mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR); |
| 1971 | if (pinfo & INSN_COP) |
| 1972 | { |
| 1973 | /* We don't keep enough information to sort these cases out. |
| 1974 | The itbl support does keep this information however, although |
| 1975 | we currently don't support itbl fprmats as part of the cop |
| 1976 | instruction. May want to add this support in the future. */ |
| 1977 | } |
| 1978 | /* Never set the bit for $0, which is always zero. */ |
| 1979 | mips_gprmask &= ~1 << 0; |
| 1980 | } |
| 1981 | else |
| 1982 | { |
| 1983 | if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X)) |
| 1984 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX) |
| 1985 | & MIPS16OP_MASK_RX); |
| 1986 | if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y)) |
| 1987 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY) |
| 1988 | & MIPS16OP_MASK_RY); |
| 1989 | if (pinfo & MIPS16_INSN_WRITE_Z) |
| 1990 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ) |
| 1991 | & MIPS16OP_MASK_RZ); |
| 1992 | if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T)) |
| 1993 | mips_gprmask |= 1 << TREG; |
| 1994 | if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP)) |
| 1995 | mips_gprmask |= 1 << SP; |
| 1996 | if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31)) |
| 1997 | mips_gprmask |= 1 << RA; |
| 1998 | if (pinfo & MIPS16_INSN_WRITE_GPR_Y) |
| 1999 | mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode); |
| 2000 | if (pinfo & MIPS16_INSN_READ_Z) |
| 2001 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z) |
| 2002 | & MIPS16OP_MASK_MOVE32Z); |
| 2003 | if (pinfo & MIPS16_INSN_READ_GPR_X) |
| 2004 | mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32) |
| 2005 | & MIPS16OP_MASK_REGR32); |
| 2006 | } |
| 2007 | |
| 2008 | if (place == NULL && ! mips_opts.noreorder) |
| 2009 | { |
| 2010 | /* Filling the branch delay slot is more complex. We try to |
| 2011 | switch the branch with the previous instruction, which we can |
| 2012 | do if the previous instruction does not set up a condition |
| 2013 | that the branch tests and if the branch is not itself the |
| 2014 | target of any branch. */ |
| 2015 | if ((pinfo & INSN_UNCOND_BRANCH_DELAY) |
| 2016 | || (pinfo & INSN_COND_BRANCH_DELAY)) |
| 2017 | { |
| 2018 | if (mips_optimize < 2 |
| 2019 | /* If we have seen .set volatile or .set nomove, don't |
| 2020 | optimize. */ |
| 2021 | || mips_opts.nomove != 0 |
| 2022 | /* If we had to emit any NOP instructions, then we |
| 2023 | already know we can not swap. */ |
| 2024 | || nops != 0 |
| 2025 | /* If we don't even know the previous insn, we can not |
| 2026 | swap. */ |
| 2027 | || ! prev_insn_valid |
| 2028 | /* If the previous insn is already in a branch delay |
| 2029 | slot, then we can not swap. */ |
| 2030 | || prev_insn_is_delay_slot |
| 2031 | /* If the previous previous insn was in a .set |
| 2032 | noreorder, we can't swap. Actually, the MIPS |
| 2033 | assembler will swap in this situation. However, gcc |
| 2034 | configured -with-gnu-as will generate code like |
| 2035 | .set noreorder |
| 2036 | lw $4,XXX |
| 2037 | .set reorder |
| 2038 | INSN |
| 2039 | bne $4,$0,foo |
| 2040 | in which we can not swap the bne and INSN. If gcc is |
| 2041 | not configured -with-gnu-as, it does not output the |
| 2042 | .set pseudo-ops. We don't have to check |
| 2043 | prev_insn_unreordered, because prev_insn_valid will |
| 2044 | be 0 in that case. We don't want to use |
| 2045 | prev_prev_insn_valid, because we do want to be able |
| 2046 | to swap at the start of a function. */ |
| 2047 | || prev_prev_insn_unreordered |
| 2048 | /* If the branch is itself the target of a branch, we |
| 2049 | can not swap. We cheat on this; all we check for is |
| 2050 | whether there is a label on this instruction. If |
| 2051 | there are any branches to anything other than a |
| 2052 | label, users must use .set noreorder. */ |
| 2053 | || insn_labels != NULL |
| 2054 | /* If the previous instruction is in a variant frag, we |
| 2055 | can not do the swap. This does not apply to the |
| 2056 | mips16, which uses variant frags for different |
| 2057 | purposes. */ |
| 2058 | || (! mips_opts.mips16 |
| 2059 | && prev_insn_frag->fr_type == rs_machine_dependent) |
| 2060 | /* If the branch reads the condition codes, we don't |
| 2061 | even try to swap, because in the sequence |
| 2062 | ctc1 $X,$31 |
| 2063 | INSN |
| 2064 | INSN |
| 2065 | bc1t LABEL |
| 2066 | we can not swap, and I don't feel like handling that |
| 2067 | case. */ |
| 2068 | || (! mips_opts.mips16 |
| 2069 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2070 | && (pinfo & INSN_READ_COND_CODE)) |
| 2071 | /* We can not swap with an instruction that requires a |
| 2072 | delay slot, becase the target of the branch might |
| 2073 | interfere with that instruction. */ |
| 2074 | || (! mips_opts.mips16 |
| 2075 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2076 | && (prev_pinfo |
| 2077 | /* Itbl support may require additional care here. */ |
| 2078 | & (INSN_LOAD_COPROC_DELAY |
| 2079 | | INSN_COPROC_MOVE_DELAY |
| 2080 | | INSN_WRITE_COND_CODE))) |
| 2081 | || (! (hilo_interlocks |
| 2082 | || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) |
| 2083 | && (prev_pinfo |
| 2084 | & (INSN_READ_LO |
| 2085 | | INSN_READ_HI))) |
| 2086 | || (! mips_opts.mips16 |
| 2087 | && ! gpr_interlocks |
| 2088 | && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)) |
| 2089 | || (! mips_opts.mips16 |
| 2090 | && mips_opts.isa == ISA_MIPS1 |
| 2091 | /* Itbl support may require additional care here. */ |
| 2092 | && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)) |
| 2093 | /* We can not swap with a branch instruction. */ |
| 2094 | || (prev_pinfo |
| 2095 | & (INSN_UNCOND_BRANCH_DELAY |
| 2096 | | INSN_COND_BRANCH_DELAY |
| 2097 | | INSN_COND_BRANCH_LIKELY)) |
| 2098 | /* We do not swap with a trap instruction, since it |
| 2099 | complicates trap handlers to have the trap |
| 2100 | instruction be in a delay slot. */ |
| 2101 | || (prev_pinfo & INSN_TRAP) |
| 2102 | /* If the branch reads a register that the previous |
| 2103 | instruction sets, we can not swap. */ |
| 2104 | || (! mips_opts.mips16 |
| 2105 | && (prev_pinfo & INSN_WRITE_GPR_T) |
| 2106 | && insn_uses_reg (ip, |
| 2107 | ((prev_insn.insn_opcode >> OP_SH_RT) |
| 2108 | & OP_MASK_RT), |
| 2109 | MIPS_GR_REG)) |
| 2110 | || (! mips_opts.mips16 |
| 2111 | && (prev_pinfo & INSN_WRITE_GPR_D) |
| 2112 | && insn_uses_reg (ip, |
| 2113 | ((prev_insn.insn_opcode >> OP_SH_RD) |
| 2114 | & OP_MASK_RD), |
| 2115 | MIPS_GR_REG)) |
| 2116 | || (mips_opts.mips16 |
| 2117 | && (((prev_pinfo & MIPS16_INSN_WRITE_X) |
| 2118 | && insn_uses_reg (ip, |
| 2119 | ((prev_insn.insn_opcode |
| 2120 | >> MIPS16OP_SH_RX) |
| 2121 | & MIPS16OP_MASK_RX), |
| 2122 | MIPS16_REG)) |
| 2123 | || ((prev_pinfo & MIPS16_INSN_WRITE_Y) |
| 2124 | && insn_uses_reg (ip, |
| 2125 | ((prev_insn.insn_opcode |
| 2126 | >> MIPS16OP_SH_RY) |
| 2127 | & MIPS16OP_MASK_RY), |
| 2128 | MIPS16_REG)) |
| 2129 | || ((prev_pinfo & MIPS16_INSN_WRITE_Z) |
| 2130 | && insn_uses_reg (ip, |
| 2131 | ((prev_insn.insn_opcode |
| 2132 | >> MIPS16OP_SH_RZ) |
| 2133 | & MIPS16OP_MASK_RZ), |
| 2134 | MIPS16_REG)) |
| 2135 | || ((prev_pinfo & MIPS16_INSN_WRITE_T) |
| 2136 | && insn_uses_reg (ip, TREG, MIPS_GR_REG)) |
| 2137 | || ((prev_pinfo & MIPS16_INSN_WRITE_31) |
| 2138 | && insn_uses_reg (ip, RA, MIPS_GR_REG)) |
| 2139 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) |
| 2140 | && insn_uses_reg (ip, |
| 2141 | MIPS16OP_EXTRACT_REG32R (prev_insn. |
| 2142 | insn_opcode), |
| 2143 | MIPS_GR_REG)))) |
| 2144 | /* If the branch writes a register that the previous |
| 2145 | instruction sets, we can not swap (we know that |
| 2146 | branches write only to RD or to $31). */ |
| 2147 | || (! mips_opts.mips16 |
| 2148 | && (prev_pinfo & INSN_WRITE_GPR_T) |
| 2149 | && (((pinfo & INSN_WRITE_GPR_D) |
| 2150 | && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT) |
| 2151 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) |
| 2152 | || ((pinfo & INSN_WRITE_GPR_31) |
| 2153 | && (((prev_insn.insn_opcode >> OP_SH_RT) |
| 2154 | & OP_MASK_RT) |
| 2155 | == 31)))) |
| 2156 | || (! mips_opts.mips16 |
| 2157 | && (prev_pinfo & INSN_WRITE_GPR_D) |
| 2158 | && (((pinfo & INSN_WRITE_GPR_D) |
| 2159 | && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD) |
| 2160 | == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD))) |
| 2161 | || ((pinfo & INSN_WRITE_GPR_31) |
| 2162 | && (((prev_insn.insn_opcode >> OP_SH_RD) |
| 2163 | & OP_MASK_RD) |
| 2164 | == 31)))) |
| 2165 | || (mips_opts.mips16 |
| 2166 | && (pinfo & MIPS16_INSN_WRITE_31) |
| 2167 | && ((prev_pinfo & MIPS16_INSN_WRITE_31) |
| 2168 | || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y) |
| 2169 | && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode) |
| 2170 | == RA)))) |
| 2171 | /* If the branch writes a register that the previous |
| 2172 | instruction reads, we can not swap (we know that |
| 2173 | branches only write to RD or to $31). */ |
| 2174 | || (! mips_opts.mips16 |
| 2175 | && (pinfo & INSN_WRITE_GPR_D) |
| 2176 | && insn_uses_reg (&prev_insn, |
| 2177 | ((ip->insn_opcode >> OP_SH_RD) |
| 2178 | & OP_MASK_RD), |
| 2179 | MIPS_GR_REG)) |
| 2180 | || (! mips_opts.mips16 |
| 2181 | && (pinfo & INSN_WRITE_GPR_31) |
| 2182 | && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG)) |
| 2183 | || (mips_opts.mips16 |
| 2184 | && (pinfo & MIPS16_INSN_WRITE_31) |
| 2185 | && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG)) |
| 2186 | /* If we are generating embedded PIC code, the branch |
| 2187 | might be expanded into a sequence which uses $at, so |
| 2188 | we can't swap with an instruction which reads it. */ |
| 2189 | || (mips_pic == EMBEDDED_PIC |
| 2190 | && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG)) |
| 2191 | /* If the previous previous instruction has a load |
| 2192 | delay, and sets a register that the branch reads, we |
| 2193 | can not swap. */ |
| 2194 | || (! mips_opts.mips16 |
| 2195 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2196 | /* Itbl support may require additional care here. */ |
| 2197 | && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY) |
| 2198 | || (! gpr_interlocks |
| 2199 | && (prev_prev_insn.insn_mo->pinfo |
| 2200 | & INSN_LOAD_MEMORY_DELAY))) |
| 2201 | && insn_uses_reg (ip, |
| 2202 | ((prev_prev_insn.insn_opcode >> OP_SH_RT) |
| 2203 | & OP_MASK_RT), |
| 2204 | MIPS_GR_REG)) |
| 2205 | /* If one instruction sets a condition code and the |
| 2206 | other one uses a condition code, we can not swap. */ |
| 2207 | || ((pinfo & INSN_READ_COND_CODE) |
| 2208 | && (prev_pinfo & INSN_WRITE_COND_CODE)) |
| 2209 | || ((pinfo & INSN_WRITE_COND_CODE) |
| 2210 | && (prev_pinfo & INSN_READ_COND_CODE)) |
| 2211 | /* If the previous instruction uses the PC, we can not |
| 2212 | swap. */ |
| 2213 | || (mips_opts.mips16 |
| 2214 | && (prev_pinfo & MIPS16_INSN_READ_PC)) |
| 2215 | /* If the previous instruction was extended, we can not |
| 2216 | swap. */ |
| 2217 | || (mips_opts.mips16 && prev_insn_extended) |
| 2218 | /* If the previous instruction had a fixup in mips16 |
| 2219 | mode, we can not swap. This normally means that the |
| 2220 | previous instruction was a 4 byte branch anyhow. */ |
| 2221 | || (mips_opts.mips16 && prev_insn_fixp) |
| 2222 | /* If the previous instruction is a sync, sync.l, or |
| 2223 | sync.p, we can not swap. */ |
| 2224 | || (prev_pinfo & INSN_SYNC)) |
| 2225 | { |
| 2226 | /* We could do even better for unconditional branches to |
| 2227 | portions of this object file; we could pick up the |
| 2228 | instruction at the destination, put it in the delay |
| 2229 | slot, and bump the destination address. */ |
| 2230 | emit_nop (); |
| 2231 | /* Update the previous insn information. */ |
| 2232 | prev_prev_insn = *ip; |
| 2233 | prev_insn.insn_mo = &dummy_opcode; |
| 2234 | } |
| 2235 | else |
| 2236 | { |
| 2237 | /* It looks like we can actually do the swap. */ |
| 2238 | if (! mips_opts.mips16) |
| 2239 | { |
| 2240 | char *prev_f; |
| 2241 | char temp[4]; |
| 2242 | |
| 2243 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
| 2244 | memcpy (temp, prev_f, 4); |
| 2245 | memcpy (prev_f, f, 4); |
| 2246 | memcpy (f, temp, 4); |
| 2247 | if (prev_insn_fixp) |
| 2248 | { |
| 2249 | prev_insn_fixp->fx_frag = frag_now; |
| 2250 | prev_insn_fixp->fx_where = f - frag_now->fr_literal; |
| 2251 | } |
| 2252 | if (fixp) |
| 2253 | { |
| 2254 | fixp->fx_frag = prev_insn_frag; |
| 2255 | fixp->fx_where = prev_insn_where; |
| 2256 | } |
| 2257 | } |
| 2258 | else |
| 2259 | { |
| 2260 | char *prev_f; |
| 2261 | char temp[2]; |
| 2262 | |
| 2263 | assert (prev_insn_fixp == NULL); |
| 2264 | prev_f = prev_insn_frag->fr_literal + prev_insn_where; |
| 2265 | memcpy (temp, prev_f, 2); |
| 2266 | memcpy (prev_f, f, 2); |
| 2267 | if (reloc_type != BFD_RELOC_MIPS16_JMP) |
| 2268 | { |
| 2269 | assert (reloc_type == BFD_RELOC_UNUSED); |
| 2270 | memcpy (f, temp, 2); |
| 2271 | } |
| 2272 | else |
| 2273 | { |
| 2274 | memcpy (f, f + 2, 2); |
| 2275 | memcpy (f + 2, temp, 2); |
| 2276 | } |
| 2277 | if (fixp) |
| 2278 | { |
| 2279 | fixp->fx_frag = prev_insn_frag; |
| 2280 | fixp->fx_where = prev_insn_where; |
| 2281 | } |
| 2282 | } |
| 2283 | |
| 2284 | /* Update the previous insn information; leave prev_insn |
| 2285 | unchanged. */ |
| 2286 | prev_prev_insn = *ip; |
| 2287 | } |
| 2288 | prev_insn_is_delay_slot = 1; |
| 2289 | |
| 2290 | /* If that was an unconditional branch, forget the previous |
| 2291 | insn information. */ |
| 2292 | if (pinfo & INSN_UNCOND_BRANCH_DELAY) |
| 2293 | { |
| 2294 | prev_prev_insn.insn_mo = &dummy_opcode; |
| 2295 | prev_insn.insn_mo = &dummy_opcode; |
| 2296 | } |
| 2297 | |
| 2298 | prev_insn_fixp = NULL; |
| 2299 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
| 2300 | prev_insn_extended = 0; |
| 2301 | } |
| 2302 | else if (pinfo & INSN_COND_BRANCH_LIKELY) |
| 2303 | { |
| 2304 | /* We don't yet optimize a branch likely. What we should do |
| 2305 | is look at the target, copy the instruction found there |
| 2306 | into the delay slot, and increment the branch to jump to |
| 2307 | the next instruction. */ |
| 2308 | emit_nop (); |
| 2309 | /* Update the previous insn information. */ |
| 2310 | prev_prev_insn = *ip; |
| 2311 | prev_insn.insn_mo = &dummy_opcode; |
| 2312 | prev_insn_fixp = NULL; |
| 2313 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
| 2314 | prev_insn_extended = 0; |
| 2315 | } |
| 2316 | else |
| 2317 | { |
| 2318 | /* Update the previous insn information. */ |
| 2319 | if (nops > 0) |
| 2320 | prev_prev_insn.insn_mo = &dummy_opcode; |
| 2321 | else |
| 2322 | prev_prev_insn = prev_insn; |
| 2323 | prev_insn = *ip; |
| 2324 | |
| 2325 | /* Any time we see a branch, we always fill the delay slot |
| 2326 | immediately; since this insn is not a branch, we know it |
| 2327 | is not in a delay slot. */ |
| 2328 | prev_insn_is_delay_slot = 0; |
| 2329 | |
| 2330 | prev_insn_fixp = fixp; |
| 2331 | prev_insn_reloc_type = reloc_type; |
| 2332 | if (mips_opts.mips16) |
| 2333 | prev_insn_extended = (ip->use_extend |
| 2334 | || reloc_type > BFD_RELOC_UNUSED); |
| 2335 | } |
| 2336 | |
| 2337 | prev_prev_insn_unreordered = prev_insn_unreordered; |
| 2338 | prev_insn_unreordered = 0; |
| 2339 | prev_insn_frag = frag_now; |
| 2340 | prev_insn_where = f - frag_now->fr_literal; |
| 2341 | prev_insn_valid = 1; |
| 2342 | } |
| 2343 | else if (place == NULL) |
| 2344 | { |
| 2345 | /* We need to record a bit of information even when we are not |
| 2346 | reordering, in order to determine the base address for mips16 |
| 2347 | PC relative relocs. */ |
| 2348 | prev_prev_insn = prev_insn; |
| 2349 | prev_insn = *ip; |
| 2350 | prev_insn_reloc_type = reloc_type; |
| 2351 | prev_prev_insn_unreordered = prev_insn_unreordered; |
| 2352 | prev_insn_unreordered = 1; |
| 2353 | } |
| 2354 | |
| 2355 | /* We just output an insn, so the next one doesn't have a label. */ |
| 2356 | mips_clear_insn_labels (); |
| 2357 | |
| 2358 | /* We must ensure that a fixup associated with an unmatched %hi |
| 2359 | reloc does not become a variant frag. Otherwise, the |
| 2360 | rearrangement of %hi relocs in frob_file may confuse |
| 2361 | tc_gen_reloc. */ |
| 2362 | if (unmatched_hi) |
| 2363 | { |
| 2364 | frag_wane (frag_now); |
| 2365 | frag_new (0); |
| 2366 | } |
| 2367 | } |
| 2368 | |
| 2369 | /* This function forgets that there was any previous instruction or |
| 2370 | label. If PRESERVE is non-zero, it remembers enough information to |
| 2371 | know whether nops are needed before a noreorder section. */ |
| 2372 | |
| 2373 | static void |
| 2374 | mips_no_prev_insn (preserve) |
| 2375 | int preserve; |
| 2376 | { |
| 2377 | if (! preserve) |
| 2378 | { |
| 2379 | prev_insn.insn_mo = &dummy_opcode; |
| 2380 | prev_prev_insn.insn_mo = &dummy_opcode; |
| 2381 | prev_nop_frag = NULL; |
| 2382 | prev_nop_frag_holds = 0; |
| 2383 | prev_nop_frag_required = 0; |
| 2384 | prev_nop_frag_since = 0; |
| 2385 | } |
| 2386 | prev_insn_valid = 0; |
| 2387 | prev_insn_is_delay_slot = 0; |
| 2388 | prev_insn_unreordered = 0; |
| 2389 | prev_insn_extended = 0; |
| 2390 | prev_insn_reloc_type = BFD_RELOC_UNUSED; |
| 2391 | prev_prev_insn_unreordered = 0; |
| 2392 | mips_clear_insn_labels (); |
| 2393 | } |
| 2394 | |
| 2395 | /* This function must be called whenever we turn on noreorder or emit |
| 2396 | something other than instructions. It inserts any NOPS which might |
| 2397 | be needed by the previous instruction, and clears the information |
| 2398 | kept for the previous instructions. The INSNS parameter is true if |
| 2399 | instructions are to follow. */ |
| 2400 | |
| 2401 | static void |
| 2402 | mips_emit_delays (insns) |
| 2403 | boolean insns; |
| 2404 | { |
| 2405 | if (! mips_opts.noreorder) |
| 2406 | { |
| 2407 | int nops; |
| 2408 | |
| 2409 | nops = 0; |
| 2410 | if ((! mips_opts.mips16 |
| 2411 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2412 | && (! cop_interlocks |
| 2413 | && (prev_insn.insn_mo->pinfo |
| 2414 | & (INSN_LOAD_COPROC_DELAY |
| 2415 | | INSN_COPROC_MOVE_DELAY |
| 2416 | | INSN_WRITE_COND_CODE)))) |
| 2417 | || (! hilo_interlocks |
| 2418 | && (prev_insn.insn_mo->pinfo |
| 2419 | & (INSN_READ_LO |
| 2420 | | INSN_READ_HI))) |
| 2421 | || (! mips_opts.mips16 |
| 2422 | && ! gpr_interlocks |
| 2423 | && (prev_insn.insn_mo->pinfo |
| 2424 | & INSN_LOAD_MEMORY_DELAY)) |
| 2425 | || (! mips_opts.mips16 |
| 2426 | && mips_opts.isa == ISA_MIPS1 |
| 2427 | && (prev_insn.insn_mo->pinfo |
| 2428 | & INSN_COPROC_MEMORY_DELAY))) |
| 2429 | { |
| 2430 | /* Itbl support may require additional care here. */ |
| 2431 | ++nops; |
| 2432 | if ((! mips_opts.mips16 |
| 2433 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2434 | && (! cop_interlocks |
| 2435 | && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) |
| 2436 | || (! hilo_interlocks |
| 2437 | && ((prev_insn.insn_mo->pinfo & INSN_READ_HI) |
| 2438 | || (prev_insn.insn_mo->pinfo & INSN_READ_LO)))) |
| 2439 | ++nops; |
| 2440 | |
| 2441 | if (prev_insn_unreordered) |
| 2442 | nops = 0; |
| 2443 | } |
| 2444 | else if ((! mips_opts.mips16 |
| 2445 | && ISA_HAS_COPROC_DELAYS (mips_opts.isa) |
| 2446 | && (! cop_interlocks |
| 2447 | && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)) |
| 2448 | || (! hilo_interlocks |
| 2449 | && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) |
| 2450 | || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)))) |
| 2451 | { |
| 2452 | /* Itbl support may require additional care here. */ |
| 2453 | if (! prev_prev_insn_unreordered) |
| 2454 | ++nops; |
| 2455 | } |
| 2456 | |
| 2457 | if (nops > 0) |
| 2458 | { |
| 2459 | struct insn_label_list *l; |
| 2460 | |
| 2461 | if (insns) |
| 2462 | { |
| 2463 | /* Record the frag which holds the nop instructions, so |
| 2464 | that we can remove them if we don't need them. */ |
| 2465 | frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4); |
| 2466 | prev_nop_frag = frag_now; |
| 2467 | prev_nop_frag_holds = nops; |
| 2468 | prev_nop_frag_required = 0; |
| 2469 | prev_nop_frag_since = 0; |
| 2470 | } |
| 2471 | |
| 2472 | for (; nops > 0; --nops) |
| 2473 | emit_nop (); |
| 2474 | |
| 2475 | if (insns) |
| 2476 | { |
| 2477 | /* Move on to a new frag, so that it is safe to simply |
| 2478 | decrease the size of prev_nop_frag. */ |
| 2479 | frag_wane (frag_now); |
| 2480 | frag_new (0); |
| 2481 | } |
| 2482 | |
| 2483 | for (l = insn_labels; l != NULL; l = l->next) |
| 2484 | { |
| 2485 | valueT val; |
| 2486 | |
| 2487 | assert (S_GET_SEGMENT (l->label) == now_seg); |
| 2488 | symbol_set_frag (l->label, frag_now); |
| 2489 | val = (valueT) frag_now_fix (); |
| 2490 | /* mips16 text labels are stored as odd. */ |
| 2491 | if (mips_opts.mips16) |
| 2492 | val += 1; |
| 2493 | S_SET_VALUE (l->label, val); |
| 2494 | } |
| 2495 | } |
| 2496 | } |
| 2497 | |
| 2498 | /* Mark instruction labels in mips16 mode. */ |
| 2499 | if (mips_opts.mips16 && insns) |
| 2500 | mips16_mark_labels (); |
| 2501 | |
| 2502 | mips_no_prev_insn (insns); |
| 2503 | } |
| 2504 | |
| 2505 | /* Build an instruction created by a macro expansion. This is passed |
| 2506 | a pointer to the count of instructions created so far, an |
| 2507 | expression, the name of the instruction to build, an operand format |
| 2508 | string, and corresponding arguments. */ |
| 2509 | |
| 2510 | #ifdef USE_STDARG |
| 2511 | static void |
| 2512 | macro_build (char *place, |
| 2513 | int *counter, |
| 2514 | expressionS * ep, |
| 2515 | const char *name, |
| 2516 | const char *fmt, |
| 2517 | ...) |
| 2518 | #else |
| 2519 | static void |
| 2520 | macro_build (place, counter, ep, name, fmt, va_alist) |
| 2521 | char *place; |
| 2522 | int *counter; |
| 2523 | expressionS *ep; |
| 2524 | const char *name; |
| 2525 | const char *fmt; |
| 2526 | va_dcl |
| 2527 | #endif |
| 2528 | { |
| 2529 | struct mips_cl_insn insn; |
| 2530 | bfd_reloc_code_real_type r; |
| 2531 | va_list args; |
| 2532 | |
| 2533 | #ifdef USE_STDARG |
| 2534 | va_start (args, fmt); |
| 2535 | #else |
| 2536 | va_start (args); |
| 2537 | #endif |
| 2538 | |
| 2539 | /* |
| 2540 | * If the macro is about to expand into a second instruction, |
| 2541 | * print a warning if needed. We need to pass ip as a parameter |
| 2542 | * to generate a better warning message here... |
| 2543 | */ |
| 2544 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
| 2545 | as_warn (_("Macro instruction expanded into multiple instructions")); |
| 2546 | |
| 2547 | if (place == NULL) |
| 2548 | *counter += 1; /* bump instruction counter */ |
| 2549 | |
| 2550 | if (mips_opts.mips16) |
| 2551 | { |
| 2552 | mips16_macro_build (place, counter, ep, name, fmt, args); |
| 2553 | va_end (args); |
| 2554 | return; |
| 2555 | } |
| 2556 | |
| 2557 | r = BFD_RELOC_UNUSED; |
| 2558 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
| 2559 | assert (insn.insn_mo); |
| 2560 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 2561 | |
| 2562 | /* Search until we get a match for NAME. */ |
| 2563 | while (1) |
| 2564 | { |
| 2565 | if (strcmp (fmt, insn.insn_mo->args) == 0 |
| 2566 | && insn.insn_mo->pinfo != INSN_MACRO |
| 2567 | && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch) |
| 2568 | && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) |
| 2569 | break; |
| 2570 | |
| 2571 | ++insn.insn_mo; |
| 2572 | assert (insn.insn_mo->name); |
| 2573 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 2574 | } |
| 2575 | |
| 2576 | insn.insn_opcode = insn.insn_mo->match; |
| 2577 | for (;;) |
| 2578 | { |
| 2579 | switch (*fmt++) |
| 2580 | { |
| 2581 | case '\0': |
| 2582 | break; |
| 2583 | |
| 2584 | case ',': |
| 2585 | case '(': |
| 2586 | case ')': |
| 2587 | continue; |
| 2588 | |
| 2589 | case 't': |
| 2590 | case 'w': |
| 2591 | case 'E': |
| 2592 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RT; |
| 2593 | continue; |
| 2594 | |
| 2595 | case 'c': |
| 2596 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE; |
| 2597 | continue; |
| 2598 | |
| 2599 | case 'T': |
| 2600 | case 'W': |
| 2601 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FT; |
| 2602 | continue; |
| 2603 | |
| 2604 | case 'd': |
| 2605 | case 'G': |
| 2606 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RD; |
| 2607 | continue; |
| 2608 | |
| 2609 | case 'U': |
| 2610 | { |
| 2611 | int tmp = va_arg (args, int); |
| 2612 | |
| 2613 | insn.insn_opcode |= tmp << OP_SH_RT; |
| 2614 | insn.insn_opcode |= tmp << OP_SH_RD; |
| 2615 | continue; |
| 2616 | } |
| 2617 | |
| 2618 | case 'V': |
| 2619 | case 'S': |
| 2620 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FS; |
| 2621 | continue; |
| 2622 | |
| 2623 | case 'z': |
| 2624 | continue; |
| 2625 | |
| 2626 | case '<': |
| 2627 | insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT; |
| 2628 | continue; |
| 2629 | |
| 2630 | case 'D': |
| 2631 | insn.insn_opcode |= va_arg (args, int) << OP_SH_FD; |
| 2632 | continue; |
| 2633 | |
| 2634 | case 'B': |
| 2635 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20; |
| 2636 | continue; |
| 2637 | |
| 2638 | case 'J': |
| 2639 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19; |
| 2640 | continue; |
| 2641 | |
| 2642 | case 'q': |
| 2643 | insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2; |
| 2644 | continue; |
| 2645 | |
| 2646 | case 'b': |
| 2647 | case 's': |
| 2648 | case 'r': |
| 2649 | case 'v': |
| 2650 | insn.insn_opcode |= va_arg (args, int) << OP_SH_RS; |
| 2651 | continue; |
| 2652 | |
| 2653 | case 'i': |
| 2654 | case 'j': |
| 2655 | case 'o': |
| 2656 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
| 2657 | assert (r == BFD_RELOC_MIPS_GPREL |
| 2658 | || r == BFD_RELOC_MIPS_LITERAL |
| 2659 | || r == BFD_RELOC_LO16 |
| 2660 | || r == BFD_RELOC_MIPS_GOT16 |
| 2661 | || r == BFD_RELOC_MIPS_CALL16 |
| 2662 | || r == BFD_RELOC_MIPS_GOT_LO16 |
| 2663 | || r == BFD_RELOC_MIPS_CALL_LO16 |
| 2664 | || (ep->X_op == O_subtract |
| 2665 | && r == BFD_RELOC_PCREL_LO16)); |
| 2666 | continue; |
| 2667 | |
| 2668 | case 'u': |
| 2669 | r = (bfd_reloc_code_real_type) va_arg (args, int); |
| 2670 | assert (ep != NULL |
| 2671 | && (ep->X_op == O_constant |
| 2672 | || (ep->X_op == O_symbol |
| 2673 | && (r == BFD_RELOC_HI16_S |
| 2674 | || r == BFD_RELOC_HI16 |
| 2675 | || r == BFD_RELOC_MIPS_GOT_HI16 |
| 2676 | || r == BFD_RELOC_MIPS_CALL_HI16)) |
| 2677 | || (ep->X_op == O_subtract |
| 2678 | && r == BFD_RELOC_PCREL_HI16_S))); |
| 2679 | if (ep->X_op == O_constant) |
| 2680 | { |
| 2681 | insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff; |
| 2682 | ep = NULL; |
| 2683 | r = BFD_RELOC_UNUSED; |
| 2684 | } |
| 2685 | continue; |
| 2686 | |
| 2687 | case 'p': |
| 2688 | assert (ep != NULL); |
| 2689 | /* |
| 2690 | * This allows macro() to pass an immediate expression for |
| 2691 | * creating short branches without creating a symbol. |
| 2692 | * Note that the expression still might come from the assembly |
| 2693 | * input, in which case the value is not checked for range nor |
| 2694 | * is a relocation entry generated (yuck). |
| 2695 | */ |
| 2696 | if (ep->X_op == O_constant) |
| 2697 | { |
| 2698 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
| 2699 | ep = NULL; |
| 2700 | } |
| 2701 | else |
| 2702 | r = BFD_RELOC_16_PCREL_S2; |
| 2703 | continue; |
| 2704 | |
| 2705 | case 'a': |
| 2706 | assert (ep != NULL); |
| 2707 | r = BFD_RELOC_MIPS_JMP; |
| 2708 | continue; |
| 2709 | |
| 2710 | case 'C': |
| 2711 | insn.insn_opcode |= va_arg (args, unsigned long); |
| 2712 | continue; |
| 2713 | |
| 2714 | default: |
| 2715 | internalError (); |
| 2716 | } |
| 2717 | break; |
| 2718 | } |
| 2719 | va_end (args); |
| 2720 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
| 2721 | |
| 2722 | append_insn (place, &insn, ep, r, false); |
| 2723 | } |
| 2724 | |
| 2725 | static void |
| 2726 | mips16_macro_build (place, counter, ep, name, fmt, args) |
| 2727 | char *place; |
| 2728 | int *counter ATTRIBUTE_UNUSED; |
| 2729 | expressionS *ep; |
| 2730 | const char *name; |
| 2731 | const char *fmt; |
| 2732 | va_list args; |
| 2733 | { |
| 2734 | struct mips_cl_insn insn; |
| 2735 | bfd_reloc_code_real_type r; |
| 2736 | |
| 2737 | r = BFD_RELOC_UNUSED; |
| 2738 | insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
| 2739 | assert (insn.insn_mo); |
| 2740 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 2741 | |
| 2742 | while (strcmp (fmt, insn.insn_mo->args) != 0 |
| 2743 | || insn.insn_mo->pinfo == INSN_MACRO) |
| 2744 | { |
| 2745 | ++insn.insn_mo; |
| 2746 | assert (insn.insn_mo->name); |
| 2747 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 2748 | } |
| 2749 | |
| 2750 | insn.insn_opcode = insn.insn_mo->match; |
| 2751 | insn.use_extend = false; |
| 2752 | |
| 2753 | for (;;) |
| 2754 | { |
| 2755 | int c; |
| 2756 | |
| 2757 | c = *fmt++; |
| 2758 | switch (c) |
| 2759 | { |
| 2760 | case '\0': |
| 2761 | break; |
| 2762 | |
| 2763 | case ',': |
| 2764 | case '(': |
| 2765 | case ')': |
| 2766 | continue; |
| 2767 | |
| 2768 | case 'y': |
| 2769 | case 'w': |
| 2770 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY; |
| 2771 | continue; |
| 2772 | |
| 2773 | case 'x': |
| 2774 | case 'v': |
| 2775 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX; |
| 2776 | continue; |
| 2777 | |
| 2778 | case 'z': |
| 2779 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ; |
| 2780 | continue; |
| 2781 | |
| 2782 | case 'Z': |
| 2783 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z; |
| 2784 | continue; |
| 2785 | |
| 2786 | case '0': |
| 2787 | case 'S': |
| 2788 | case 'P': |
| 2789 | case 'R': |
| 2790 | continue; |
| 2791 | |
| 2792 | case 'X': |
| 2793 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32; |
| 2794 | continue; |
| 2795 | |
| 2796 | case 'Y': |
| 2797 | { |
| 2798 | int regno; |
| 2799 | |
| 2800 | regno = va_arg (args, int); |
| 2801 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
| 2802 | insn.insn_opcode |= regno << MIPS16OP_SH_REG32R; |
| 2803 | } |
| 2804 | continue; |
| 2805 | |
| 2806 | case '<': |
| 2807 | case '>': |
| 2808 | case '4': |
| 2809 | case '5': |
| 2810 | case 'H': |
| 2811 | case 'W': |
| 2812 | case 'D': |
| 2813 | case 'j': |
| 2814 | case '8': |
| 2815 | case 'V': |
| 2816 | case 'C': |
| 2817 | case 'U': |
| 2818 | case 'k': |
| 2819 | case 'K': |
| 2820 | case 'p': |
| 2821 | case 'q': |
| 2822 | { |
| 2823 | assert (ep != NULL); |
| 2824 | |
| 2825 | if (ep->X_op != O_constant) |
| 2826 | r = BFD_RELOC_UNUSED + c; |
| 2827 | else |
| 2828 | { |
| 2829 | mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false, |
| 2830 | false, false, &insn.insn_opcode, |
| 2831 | &insn.use_extend, &insn.extend); |
| 2832 | ep = NULL; |
| 2833 | r = BFD_RELOC_UNUSED; |
| 2834 | } |
| 2835 | } |
| 2836 | continue; |
| 2837 | |
| 2838 | case '6': |
| 2839 | insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6; |
| 2840 | continue; |
| 2841 | } |
| 2842 | |
| 2843 | break; |
| 2844 | } |
| 2845 | |
| 2846 | assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
| 2847 | |
| 2848 | append_insn (place, &insn, ep, r, false); |
| 2849 | } |
| 2850 | |
| 2851 | /* |
| 2852 | * Generate a "lui" instruction. |
| 2853 | */ |
| 2854 | static void |
| 2855 | macro_build_lui (place, counter, ep, regnum) |
| 2856 | char *place; |
| 2857 | int *counter; |
| 2858 | expressionS *ep; |
| 2859 | int regnum; |
| 2860 | { |
| 2861 | expressionS high_expr; |
| 2862 | struct mips_cl_insn insn; |
| 2863 | bfd_reloc_code_real_type r; |
| 2864 | CONST char *name = "lui"; |
| 2865 | CONST char *fmt = "t,u"; |
| 2866 | |
| 2867 | assert (! mips_opts.mips16); |
| 2868 | |
| 2869 | if (place == NULL) |
| 2870 | high_expr = *ep; |
| 2871 | else |
| 2872 | { |
| 2873 | high_expr.X_op = O_constant; |
| 2874 | high_expr.X_add_number = ep->X_add_number; |
| 2875 | } |
| 2876 | |
| 2877 | if (high_expr.X_op == O_constant) |
| 2878 | { |
| 2879 | /* we can compute the instruction now without a relocation entry */ |
| 2880 | high_expr.X_add_number = ((high_expr.X_add_number + 0x8000) |
| 2881 | >> 16) & 0xffff; |
| 2882 | r = BFD_RELOC_UNUSED; |
| 2883 | } |
| 2884 | else |
| 2885 | { |
| 2886 | assert (ep->X_op == O_symbol); |
| 2887 | /* _gp_disp is a special case, used from s_cpload. */ |
| 2888 | assert (mips_pic == NO_PIC |
| 2889 | || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0); |
| 2890 | r = BFD_RELOC_HI16_S; |
| 2891 | } |
| 2892 | |
| 2893 | /* |
| 2894 | * If the macro is about to expand into a second instruction, |
| 2895 | * print a warning if needed. We need to pass ip as a parameter |
| 2896 | * to generate a better warning message here... |
| 2897 | */ |
| 2898 | if (mips_opts.warn_about_macros && place == NULL && *counter == 1) |
| 2899 | as_warn (_("Macro instruction expanded into multiple instructions")); |
| 2900 | |
| 2901 | if (place == NULL) |
| 2902 | *counter += 1; /* bump instruction counter */ |
| 2903 | |
| 2904 | insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name); |
| 2905 | assert (insn.insn_mo); |
| 2906 | assert (strcmp (name, insn.insn_mo->name) == 0); |
| 2907 | assert (strcmp (fmt, insn.insn_mo->args) == 0); |
| 2908 | |
| 2909 | insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT); |
| 2910 | if (r == BFD_RELOC_UNUSED) |
| 2911 | { |
| 2912 | insn.insn_opcode |= high_expr.X_add_number; |
| 2913 | append_insn (place, &insn, NULL, r, false); |
| 2914 | } |
| 2915 | else |
| 2916 | append_insn (place, &insn, &high_expr, r, false); |
| 2917 | } |
| 2918 | |
| 2919 | /* set_at() |
| 2920 | * Generates code to set the $at register to true (one) |
| 2921 | * if reg is less than the immediate expression. |
| 2922 | */ |
| 2923 | static void |
| 2924 | set_at (counter, reg, unsignedp) |
| 2925 | int *counter; |
| 2926 | int reg; |
| 2927 | int unsignedp; |
| 2928 | { |
| 2929 | if (imm_expr.X_op == O_constant |
| 2930 | && imm_expr.X_add_number >= -0x8000 |
| 2931 | && imm_expr.X_add_number < 0x8000) |
| 2932 | macro_build ((char *) NULL, counter, &imm_expr, |
| 2933 | unsignedp ? "sltiu" : "slti", |
| 2934 | "t,r,j", AT, reg, (int) BFD_RELOC_LO16); |
| 2935 | else |
| 2936 | { |
| 2937 | load_register (counter, AT, &imm_expr, 0); |
| 2938 | macro_build ((char *) NULL, counter, NULL, |
| 2939 | unsignedp ? "sltu" : "slt", |
| 2940 | "d,v,t", AT, reg, AT); |
| 2941 | } |
| 2942 | } |
| 2943 | |
| 2944 | /* Warn if an expression is not a constant. */ |
| 2945 | |
| 2946 | static void |
| 2947 | check_absolute_expr (ip, ex) |
| 2948 | struct mips_cl_insn *ip; |
| 2949 | expressionS *ex; |
| 2950 | { |
| 2951 | if (ex->X_op == O_big) |
| 2952 | as_bad (_("unsupported large constant")); |
| 2953 | else if (ex->X_op != O_constant) |
| 2954 | as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name); |
| 2955 | } |
| 2956 | |
| 2957 | /* Count the leading zeroes by performing a binary chop. This is a |
| 2958 | bulky bit of source, but performance is a LOT better for the |
| 2959 | majority of values than a simple loop to count the bits: |
| 2960 | for (lcnt = 0; (lcnt < 32); lcnt++) |
| 2961 | if ((v) & (1 << (31 - lcnt))) |
| 2962 | break; |
| 2963 | However it is not code size friendly, and the gain will drop a bit |
| 2964 | on certain cached systems. |
| 2965 | */ |
| 2966 | #define COUNT_TOP_ZEROES(v) \ |
| 2967 | (((v) & ~0xffff) == 0 \ |
| 2968 | ? ((v) & ~0xff) == 0 \ |
| 2969 | ? ((v) & ~0xf) == 0 \ |
| 2970 | ? ((v) & ~0x3) == 0 \ |
| 2971 | ? ((v) & ~0x1) == 0 \ |
| 2972 | ? !(v) \ |
| 2973 | ? 32 \ |
| 2974 | : 31 \ |
| 2975 | : 30 \ |
| 2976 | : ((v) & ~0x7) == 0 \ |
| 2977 | ? 29 \ |
| 2978 | : 28 \ |
| 2979 | : ((v) & ~0x3f) == 0 \ |
| 2980 | ? ((v) & ~0x1f) == 0 \ |
| 2981 | ? 27 \ |
| 2982 | : 26 \ |
| 2983 | : ((v) & ~0x7f) == 0 \ |
| 2984 | ? 25 \ |
| 2985 | : 24 \ |
| 2986 | : ((v) & ~0xfff) == 0 \ |
| 2987 | ? ((v) & ~0x3ff) == 0 \ |
| 2988 | ? ((v) & ~0x1ff) == 0 \ |
| 2989 | ? 23 \ |
| 2990 | : 22 \ |
| 2991 | : ((v) & ~0x7ff) == 0 \ |
| 2992 | ? 21 \ |
| 2993 | : 20 \ |
| 2994 | : ((v) & ~0x3fff) == 0 \ |
| 2995 | ? ((v) & ~0x1fff) == 0 \ |
| 2996 | ? 19 \ |
| 2997 | : 18 \ |
| 2998 | : ((v) & ~0x7fff) == 0 \ |
| 2999 | ? 17 \ |
| 3000 | : 16 \ |
| 3001 | : ((v) & ~0xffffff) == 0 \ |
| 3002 | ? ((v) & ~0xfffff) == 0 \ |
| 3003 | ? ((v) & ~0x3ffff) == 0 \ |
| 3004 | ? ((v) & ~0x1ffff) == 0 \ |
| 3005 | ? 15 \ |
| 3006 | : 14 \ |
| 3007 | : ((v) & ~0x7ffff) == 0 \ |
| 3008 | ? 13 \ |
| 3009 | : 12 \ |
| 3010 | : ((v) & ~0x3fffff) == 0 \ |
| 3011 | ? ((v) & ~0x1fffff) == 0 \ |
| 3012 | ? 11 \ |
| 3013 | : 10 \ |
| 3014 | : ((v) & ~0x7fffff) == 0 \ |
| 3015 | ? 9 \ |
| 3016 | : 8 \ |
| 3017 | : ((v) & ~0xfffffff) == 0 \ |
| 3018 | ? ((v) & ~0x3ffffff) == 0 \ |
| 3019 | ? ((v) & ~0x1ffffff) == 0 \ |
| 3020 | ? 7 \ |
| 3021 | : 6 \ |
| 3022 | : ((v) & ~0x7ffffff) == 0 \ |
| 3023 | ? 5 \ |
| 3024 | : 4 \ |
| 3025 | : ((v) & ~0x3fffffff) == 0 \ |
| 3026 | ? ((v) & ~0x1fffffff) == 0 \ |
| 3027 | ? 3 \ |
| 3028 | : 2 \ |
| 3029 | : ((v) & ~0x7fffffff) == 0 \ |
| 3030 | ? 1 \ |
| 3031 | : 0) |
| 3032 | |
| 3033 | /* load_register() |
| 3034 | * This routine generates the least number of instructions neccessary to load |
| 3035 | * an absolute expression value into a register. |
| 3036 | */ |
| 3037 | static void |
| 3038 | load_register (counter, reg, ep, dbl) |
| 3039 | int *counter; |
| 3040 | int reg; |
| 3041 | expressionS *ep; |
| 3042 | int dbl; |
| 3043 | { |
| 3044 | int freg; |
| 3045 | expressionS hi32, lo32; |
| 3046 | |
| 3047 | if (ep->X_op != O_big) |
| 3048 | { |
| 3049 | assert (ep->X_op == O_constant); |
| 3050 | if (ep->X_add_number < 0x8000 |
| 3051 | && (ep->X_add_number >= 0 |
| 3052 | || (ep->X_add_number >= -0x8000 |
| 3053 | && (! dbl |
| 3054 | || ! ep->X_unsigned |
| 3055 | || sizeof (ep->X_add_number) > 4)))) |
| 3056 | { |
| 3057 | /* We can handle 16 bit signed values with an addiu to |
| 3058 | $zero. No need to ever use daddiu here, since $zero and |
| 3059 | the result are always correct in 32 bit mode. */ |
| 3060 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
| 3061 | (int) BFD_RELOC_LO16); |
| 3062 | return; |
| 3063 | } |
| 3064 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) |
| 3065 | { |
| 3066 | /* We can handle 16 bit unsigned values with an ori to |
| 3067 | $zero. */ |
| 3068 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0, |
| 3069 | (int) BFD_RELOC_LO16); |
| 3070 | return; |
| 3071 | } |
| 3072 | else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0 |
| 3073 | || ((ep->X_add_number &~ (offsetT) 0x7fffffff) |
| 3074 | == ~ (offsetT) 0x7fffffff)) |
| 3075 | && (! dbl |
| 3076 | || ! ep->X_unsigned |
| 3077 | || sizeof (ep->X_add_number) > 4 |
| 3078 | || (ep->X_add_number & 0x80000000) == 0)) |
| 3079 | || ((HAVE_32BIT_GPRS || ! dbl) |
| 3080 | && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0) |
| 3081 | || (HAVE_32BIT_GPRS |
| 3082 | && ! dbl |
| 3083 | && ((ep->X_add_number &~ (offsetT) 0xffffffff) |
| 3084 | == ~ (offsetT) 0xffffffff))) |
| 3085 | { |
| 3086 | /* 32 bit values require an lui. */ |
| 3087 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, |
| 3088 | (int) BFD_RELOC_HI16); |
| 3089 | if ((ep->X_add_number & 0xffff) != 0) |
| 3090 | macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg, |
| 3091 | (int) BFD_RELOC_LO16); |
| 3092 | return; |
| 3093 | } |
| 3094 | } |
| 3095 | |
| 3096 | /* The value is larger than 32 bits. */ |
| 3097 | |
| 3098 | if (HAVE_32BIT_GPRS) |
| 3099 | { |
| 3100 | as_bad (_("Number larger than 32 bits")); |
| 3101 | macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0, |
| 3102 | (int) BFD_RELOC_LO16); |
| 3103 | return; |
| 3104 | } |
| 3105 | |
| 3106 | if (ep->X_op != O_big) |
| 3107 | { |
| 3108 | hi32 = *ep; |
| 3109 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
| 3110 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
| 3111 | hi32.X_add_number &= 0xffffffff; |
| 3112 | lo32 = *ep; |
| 3113 | lo32.X_add_number &= 0xffffffff; |
| 3114 | } |
| 3115 | else |
| 3116 | { |
| 3117 | assert (ep->X_add_number > 2); |
| 3118 | if (ep->X_add_number == 3) |
| 3119 | generic_bignum[3] = 0; |
| 3120 | else if (ep->X_add_number > 4) |
| 3121 | as_bad (_("Number larger than 64 bits")); |
| 3122 | lo32.X_op = O_constant; |
| 3123 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); |
| 3124 | hi32.X_op = O_constant; |
| 3125 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); |
| 3126 | } |
| 3127 | |
| 3128 | if (hi32.X_add_number == 0) |
| 3129 | freg = 0; |
| 3130 | else |
| 3131 | { |
| 3132 | int shift, bit; |
| 3133 | unsigned long hi, lo; |
| 3134 | |
| 3135 | if (hi32.X_add_number == 0xffffffff) |
| 3136 | { |
| 3137 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) |
| 3138 | { |
| 3139 | macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j", |
| 3140 | reg, 0, (int) BFD_RELOC_LO16); |
| 3141 | return; |
| 3142 | } |
| 3143 | if (lo32.X_add_number & 0x80000000) |
| 3144 | { |
| 3145 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
| 3146 | (int) BFD_RELOC_HI16); |
| 3147 | if (lo32.X_add_number & 0xffff) |
| 3148 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", |
| 3149 | reg, reg, (int) BFD_RELOC_LO16); |
| 3150 | return; |
| 3151 | } |
| 3152 | } |
| 3153 | |
| 3154 | /* Check for 16bit shifted constant. We know that hi32 is |
| 3155 | non-zero, so start the mask on the first bit of the hi32 |
| 3156 | value. */ |
| 3157 | shift = 17; |
| 3158 | do |
| 3159 | { |
| 3160 | unsigned long himask, lomask; |
| 3161 | |
| 3162 | if (shift < 32) |
| 3163 | { |
| 3164 | himask = 0xffff >> (32 - shift); |
| 3165 | lomask = (0xffff << shift) & 0xffffffff; |
| 3166 | } |
| 3167 | else |
| 3168 | { |
| 3169 | himask = 0xffff << (shift - 32); |
| 3170 | lomask = 0; |
| 3171 | } |
| 3172 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 |
| 3173 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) |
| 3174 | { |
| 3175 | expressionS tmp; |
| 3176 | |
| 3177 | tmp.X_op = O_constant; |
| 3178 | if (shift < 32) |
| 3179 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) |
| 3180 | | (lo32.X_add_number >> shift)); |
| 3181 | else |
| 3182 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); |
| 3183 | macro_build ((char *) NULL, counter, &tmp, |
| 3184 | "ori", "t,r,i", reg, 0, |
| 3185 | (int) BFD_RELOC_LO16); |
| 3186 | macro_build ((char *) NULL, counter, NULL, |
| 3187 | (shift >= 32) ? "dsll32" : "dsll", |
| 3188 | "d,w,<", reg, reg, |
| 3189 | (shift >= 32) ? shift - 32 : shift); |
| 3190 | return; |
| 3191 | } |
| 3192 | shift++; |
| 3193 | } |
| 3194 | while (shift <= (64 - 16)); |
| 3195 | |
| 3196 | /* Find the bit number of the lowest one bit, and store the |
| 3197 | shifted value in hi/lo. */ |
| 3198 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); |
| 3199 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); |
| 3200 | if (lo != 0) |
| 3201 | { |
| 3202 | bit = 0; |
| 3203 | while ((lo & 1) == 0) |
| 3204 | { |
| 3205 | lo >>= 1; |
| 3206 | ++bit; |
| 3207 | } |
| 3208 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); |
| 3209 | hi >>= bit; |
| 3210 | } |
| 3211 | else |
| 3212 | { |
| 3213 | bit = 32; |
| 3214 | while ((hi & 1) == 0) |
| 3215 | { |
| 3216 | hi >>= 1; |
| 3217 | ++bit; |
| 3218 | } |
| 3219 | lo = hi; |
| 3220 | hi = 0; |
| 3221 | } |
| 3222 | |
| 3223 | /* Optimize if the shifted value is a (power of 2) - 1. */ |
| 3224 | if ((hi == 0 && ((lo + 1) & lo) == 0) |
| 3225 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) |
| 3226 | { |
| 3227 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
| 3228 | if (shift != 0) |
| 3229 | { |
| 3230 | expressionS tmp; |
| 3231 | |
| 3232 | /* This instruction will set the register to be all |
| 3233 | ones. */ |
| 3234 | tmp.X_op = O_constant; |
| 3235 | tmp.X_add_number = (offsetT) -1; |
| 3236 | macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j", |
| 3237 | reg, 0, (int) BFD_RELOC_LO16); |
| 3238 | if (bit != 0) |
| 3239 | { |
| 3240 | bit += shift; |
| 3241 | macro_build ((char *) NULL, counter, NULL, |
| 3242 | (bit >= 32) ? "dsll32" : "dsll", |
| 3243 | "d,w,<", reg, reg, |
| 3244 | (bit >= 32) ? bit - 32 : bit); |
| 3245 | } |
| 3246 | macro_build ((char *) NULL, counter, NULL, |
| 3247 | (shift >= 32) ? "dsrl32" : "dsrl", |
| 3248 | "d,w,<", reg, reg, |
| 3249 | (shift >= 32) ? shift - 32 : shift); |
| 3250 | return; |
| 3251 | } |
| 3252 | } |
| 3253 | |
| 3254 | /* Sign extend hi32 before calling load_register, because we can |
| 3255 | generally get better code when we load a sign extended value. */ |
| 3256 | if ((hi32.X_add_number & 0x80000000) != 0) |
| 3257 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
| 3258 | load_register (counter, reg, &hi32, 0); |
| 3259 | freg = reg; |
| 3260 | } |
| 3261 | if ((lo32.X_add_number & 0xffff0000) == 0) |
| 3262 | { |
| 3263 | if (freg != 0) |
| 3264 | { |
| 3265 | macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg, |
| 3266 | freg, 0); |
| 3267 | freg = reg; |
| 3268 | } |
| 3269 | } |
| 3270 | else |
| 3271 | { |
| 3272 | expressionS mid16; |
| 3273 | |
| 3274 | if ((freg == 0) && (lo32.X_add_number == 0xffffffff)) |
| 3275 | { |
| 3276 | macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg, |
| 3277 | (int) BFD_RELOC_HI16); |
| 3278 | macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg, |
| 3279 | reg, 0); |
| 3280 | return; |
| 3281 | } |
| 3282 | |
| 3283 | if (freg != 0) |
| 3284 | { |
| 3285 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
| 3286 | freg, 16); |
| 3287 | freg = reg; |
| 3288 | } |
| 3289 | mid16 = lo32; |
| 3290 | mid16.X_add_number >>= 16; |
| 3291 | macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg, |
| 3292 | freg, (int) BFD_RELOC_LO16); |
| 3293 | macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg, |
| 3294 | reg, 16); |
| 3295 | freg = reg; |
| 3296 | } |
| 3297 | if ((lo32.X_add_number & 0xffff) != 0) |
| 3298 | macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg, |
| 3299 | (int) BFD_RELOC_LO16); |
| 3300 | } |
| 3301 | |
| 3302 | /* Load an address into a register. */ |
| 3303 | |
| 3304 | static void |
| 3305 | load_address (counter, reg, ep) |
| 3306 | int *counter; |
| 3307 | int reg; |
| 3308 | expressionS *ep; |
| 3309 | { |
| 3310 | char *p; |
| 3311 | |
| 3312 | if (ep->X_op != O_constant |
| 3313 | && ep->X_op != O_symbol) |
| 3314 | { |
| 3315 | as_bad (_("expression too complex")); |
| 3316 | ep->X_op = O_constant; |
| 3317 | } |
| 3318 | |
| 3319 | if (ep->X_op == O_constant) |
| 3320 | { |
| 3321 | load_register (counter, reg, ep, 0); |
| 3322 | return; |
| 3323 | } |
| 3324 | |
| 3325 | if (mips_pic == NO_PIC) |
| 3326 | { |
| 3327 | /* If this is a reference to a GP relative symbol, we want |
| 3328 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) |
| 3329 | Otherwise we want |
| 3330 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
| 3331 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
| 3332 | If we have an addend, we always use the latter form. */ |
| 3333 | if ((valueT) ep->X_add_number > MAX_GPREL_OFFSET |
| 3334 | || nopic_need_relax (ep->X_add_symbol, 1)) |
| 3335 | p = NULL; |
| 3336 | else |
| 3337 | { |
| 3338 | frag_grow (20); |
| 3339 | macro_build ((char *) NULL, counter, ep, |
| 3340 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3341 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
| 3342 | p = frag_var (rs_machine_dependent, 8, 0, |
| 3343 | RELAX_ENCODE (4, 8, 0, 4, 0, |
| 3344 | mips_opts.warn_about_macros), |
| 3345 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
| 3346 | } |
| 3347 | macro_build_lui (p, counter, ep, reg); |
| 3348 | if (p != NULL) |
| 3349 | p += 4; |
| 3350 | macro_build (p, counter, ep, |
| 3351 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3352 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3353 | } |
| 3354 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
| 3355 | { |
| 3356 | expressionS ex; |
| 3357 | |
| 3358 | /* If this is a reference to an external symbol, we want |
| 3359 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 3360 | Otherwise we want |
| 3361 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 3362 | nop |
| 3363 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
| 3364 | If there is a constant, it must be added in after. */ |
| 3365 | ex.X_add_number = ep->X_add_number; |
| 3366 | ep->X_add_number = 0; |
| 3367 | frag_grow (20); |
| 3368 | macro_build ((char *) NULL, counter, ep, |
| 3369 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 3370 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
| 3371 | macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", ""); |
| 3372 | p = frag_var (rs_machine_dependent, 4, 0, |
| 3373 | RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros), |
| 3374 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
| 3375 | macro_build (p, counter, ep, |
| 3376 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3377 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3378 | if (ex.X_add_number != 0) |
| 3379 | { |
| 3380 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
| 3381 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 3382 | ex.X_op = O_constant; |
| 3383 | macro_build ((char *) NULL, counter, &ex, |
| 3384 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3385 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3386 | } |
| 3387 | } |
| 3388 | else if (mips_pic == SVR4_PIC) |
| 3389 | { |
| 3390 | expressionS ex; |
| 3391 | int off; |
| 3392 | |
| 3393 | /* This is the large GOT case. If this is a reference to an |
| 3394 | external symbol, we want |
| 3395 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 3396 | addu $reg,$reg,$gp |
| 3397 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) |
| 3398 | Otherwise, for a reference to a local symbol, we want |
| 3399 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 3400 | nop |
| 3401 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
| 3402 | If there is a constant, it must be added in after. */ |
| 3403 | ex.X_add_number = ep->X_add_number; |
| 3404 | ep->X_add_number = 0; |
| 3405 | if (reg_needs_delay (GP)) |
| 3406 | off = 4; |
| 3407 | else |
| 3408 | off = 0; |
| 3409 | frag_grow (32); |
| 3410 | macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg, |
| 3411 | (int) BFD_RELOC_MIPS_GOT_HI16); |
| 3412 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3413 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 3414 | "d,v,t", reg, reg, GP); |
| 3415 | macro_build ((char *) NULL, counter, ep, |
| 3416 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 3417 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg); |
| 3418 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
| 3419 | RELAX_ENCODE (12, 12 + off, off, 8 + off, 0, |
| 3420 | mips_opts.warn_about_macros), |
| 3421 | ep->X_add_symbol, (offsetT) 0, (char *) NULL); |
| 3422 | if (off > 0) |
| 3423 | { |
| 3424 | /* We need a nop before loading from $gp. This special |
| 3425 | check is required because the lui which starts the main |
| 3426 | instruction stream does not refer to $gp, and so will not |
| 3427 | insert the nop which may be required. */ |
| 3428 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
| 3429 | p += 4; |
| 3430 | } |
| 3431 | macro_build (p, counter, ep, HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 3432 | "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP); |
| 3433 | p += 4; |
| 3434 | macro_build (p, counter, (expressionS *) NULL, "nop", ""); |
| 3435 | p += 4; |
| 3436 | macro_build (p, counter, ep, HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3437 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3438 | if (ex.X_add_number != 0) |
| 3439 | { |
| 3440 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
| 3441 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 3442 | ex.X_op = O_constant; |
| 3443 | macro_build ((char *) NULL, counter, &ex, |
| 3444 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3445 | "t,r,j", reg, reg, (int) BFD_RELOC_LO16); |
| 3446 | } |
| 3447 | } |
| 3448 | else if (mips_pic == EMBEDDED_PIC) |
| 3449 | { |
| 3450 | /* We always do |
| 3451 | addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) |
| 3452 | */ |
| 3453 | macro_build ((char *) NULL, counter, ep, |
| 3454 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 3455 | "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL); |
| 3456 | } |
| 3457 | else |
| 3458 | abort (); |
| 3459 | } |
| 3460 | |
| 3461 | /* Move the contents of register SOURCE into register DEST. */ |
| 3462 | |
| 3463 | static void |
| 3464 | move_register (counter, dest, source) |
| 3465 | int *counter; |
| 3466 | int dest; |
| 3467 | int source; |
| 3468 | { |
| 3469 | macro_build ((char *) NULL, counter, (expressionS *) NULL, |
| 3470 | HAVE_32BIT_GPRS ? "addu" : "daddu", |
| 3471 | "d,v,t", dest, source, 0); |
| 3472 | } |
| 3473 | |
| 3474 | /* |
| 3475 | * Build macros |
| 3476 | * This routine implements the seemingly endless macro or synthesized |
| 3477 | * instructions and addressing modes in the mips assembly language. Many |
| 3478 | * of these macros are simple and are similar to each other. These could |
| 3479 | * probably be handled by some kind of table or grammer aproach instead of |
| 3480 | * this verbose method. Others are not simple macros but are more like |
| 3481 | * optimizing code generation. |
| 3482 | * One interesting optimization is when several store macros appear |
| 3483 | * consecutivly that would load AT with the upper half of the same address. |
| 3484 | * The ensuing load upper instructions are ommited. This implies some kind |
| 3485 | * of global optimization. We currently only optimize within a single macro. |
| 3486 | * For many of the load and store macros if the address is specified as a |
| 3487 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we |
| 3488 | * first load register 'at' with zero and use it as the base register. The |
| 3489 | * mips assembler simply uses register $zero. Just one tiny optimization |
| 3490 | * we're missing. |
| 3491 | */ |
| 3492 | static void |
| 3493 | macro (ip) |
| 3494 | struct mips_cl_insn *ip; |
| 3495 | { |
| 3496 | register int treg, sreg, dreg, breg; |
| 3497 | int tempreg; |
| 3498 | int mask; |
| 3499 | int icnt = 0; |
| 3500 | int used_at = 0; |
| 3501 | expressionS expr1; |
| 3502 | const char *s; |
| 3503 | const char *s2; |
| 3504 | const char *fmt; |
| 3505 | int likely = 0; |
| 3506 | int dbl = 0; |
| 3507 | int coproc = 0; |
| 3508 | int lr = 0; |
| 3509 | int imm = 0; |
| 3510 | offsetT maxnum; |
| 3511 | int off; |
| 3512 | bfd_reloc_code_real_type r; |
| 3513 | char *p; |
| 3514 | int hold_mips_optimize; |
| 3515 | |
| 3516 | assert (! mips_opts.mips16); |
| 3517 | |
| 3518 | treg = (ip->insn_opcode >> 16) & 0x1f; |
| 3519 | dreg = (ip->insn_opcode >> 11) & 0x1f; |
| 3520 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; |
| 3521 | mask = ip->insn_mo->mask; |
| 3522 | |
| 3523 | expr1.X_op = O_constant; |
| 3524 | expr1.X_op_symbol = NULL; |
| 3525 | expr1.X_add_symbol = NULL; |
| 3526 | expr1.X_add_number = 1; |
| 3527 | |
| 3528 | switch (mask) |
| 3529 | { |
| 3530 | case M_DABS: |
| 3531 | dbl = 1; |
| 3532 | case M_ABS: |
| 3533 | /* bgez $a0,.+12 |
| 3534 | move v0,$a0 |
| 3535 | sub v0,$zero,$a0 |
| 3536 | */ |
| 3537 | |
| 3538 | mips_emit_delays (true); |
| 3539 | ++mips_opts.noreorder; |
| 3540 | mips_any_noreorder = 1; |
| 3541 | |
| 3542 | expr1.X_add_number = 8; |
| 3543 | macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg); |
| 3544 | if (dreg == sreg) |
| 3545 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
| 3546 | else |
| 3547 | move_register (&icnt, dreg, sreg); |
| 3548 | macro_build ((char *) NULL, &icnt, NULL, |
| 3549 | dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg); |
| 3550 | |
| 3551 | --mips_opts.noreorder; |
| 3552 | return; |
| 3553 | |
| 3554 | case M_ADD_I: |
| 3555 | s = "addi"; |
| 3556 | s2 = "add"; |
| 3557 | goto do_addi; |
| 3558 | case M_ADDU_I: |
| 3559 | s = "addiu"; |
| 3560 | s2 = "addu"; |
| 3561 | goto do_addi; |
| 3562 | case M_DADD_I: |
| 3563 | dbl = 1; |
| 3564 | s = "daddi"; |
| 3565 | s2 = "dadd"; |
| 3566 | goto do_addi; |
| 3567 | case M_DADDU_I: |
| 3568 | dbl = 1; |
| 3569 | s = "daddiu"; |
| 3570 | s2 = "daddu"; |
| 3571 | do_addi: |
| 3572 | if (imm_expr.X_op == O_constant |
| 3573 | && imm_expr.X_add_number >= -0x8000 |
| 3574 | && imm_expr.X_add_number < 0x8000) |
| 3575 | { |
| 3576 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg, |
| 3577 | (int) BFD_RELOC_LO16); |
| 3578 | return; |
| 3579 | } |
| 3580 | load_register (&icnt, AT, &imm_expr, dbl); |
| 3581 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
| 3582 | break; |
| 3583 | |
| 3584 | case M_AND_I: |
| 3585 | s = "andi"; |
| 3586 | s2 = "and"; |
| 3587 | goto do_bit; |
| 3588 | case M_OR_I: |
| 3589 | s = "ori"; |
| 3590 | s2 = "or"; |
| 3591 | goto do_bit; |
| 3592 | case M_NOR_I: |
| 3593 | s = ""; |
| 3594 | s2 = "nor"; |
| 3595 | goto do_bit; |
| 3596 | case M_XOR_I: |
| 3597 | s = "xori"; |
| 3598 | s2 = "xor"; |
| 3599 | do_bit: |
| 3600 | if (imm_expr.X_op == O_constant |
| 3601 | && imm_expr.X_add_number >= 0 |
| 3602 | && imm_expr.X_add_number < 0x10000) |
| 3603 | { |
| 3604 | if (mask != M_NOR_I) |
| 3605 | macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg, |
| 3606 | sreg, (int) BFD_RELOC_LO16); |
| 3607 | else |
| 3608 | { |
| 3609 | macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i", |
| 3610 | treg, sreg, (int) BFD_RELOC_LO16); |
| 3611 | macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t", |
| 3612 | treg, treg, 0); |
| 3613 | } |
| 3614 | return; |
| 3615 | } |
| 3616 | |
| 3617 | load_register (&icnt, AT, &imm_expr, 0); |
| 3618 | macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT); |
| 3619 | break; |
| 3620 | |
| 3621 | case M_BEQ_I: |
| 3622 | s = "beq"; |
| 3623 | goto beq_i; |
| 3624 | case M_BEQL_I: |
| 3625 | s = "beql"; |
| 3626 | likely = 1; |
| 3627 | goto beq_i; |
| 3628 | case M_BNE_I: |
| 3629 | s = "bne"; |
| 3630 | goto beq_i; |
| 3631 | case M_BNEL_I: |
| 3632 | s = "bnel"; |
| 3633 | likely = 1; |
| 3634 | beq_i: |
| 3635 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 3636 | { |
| 3637 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, |
| 3638 | 0); |
| 3639 | return; |
| 3640 | } |
| 3641 | load_register (&icnt, AT, &imm_expr, 0); |
| 3642 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT); |
| 3643 | break; |
| 3644 | |
| 3645 | case M_BGEL: |
| 3646 | likely = 1; |
| 3647 | case M_BGE: |
| 3648 | if (treg == 0) |
| 3649 | { |
| 3650 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3651 | likely ? "bgezl" : "bgez", |
| 3652 | "s,p", sreg); |
| 3653 | return; |
| 3654 | } |
| 3655 | if (sreg == 0) |
| 3656 | { |
| 3657 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3658 | likely ? "blezl" : "blez", |
| 3659 | "s,p", treg); |
| 3660 | return; |
| 3661 | } |
| 3662 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
| 3663 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3664 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 3665 | break; |
| 3666 | |
| 3667 | case M_BGTL_I: |
| 3668 | likely = 1; |
| 3669 | case M_BGT_I: |
| 3670 | /* check for > max integer */ |
| 3671 | maxnum = 0x7fffffff; |
| 3672 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
| 3673 | { |
| 3674 | maxnum <<= 16; |
| 3675 | maxnum |= 0xffff; |
| 3676 | maxnum <<= 16; |
| 3677 | maxnum |= 0xffff; |
| 3678 | } |
| 3679 | if (imm_expr.X_op == O_constant |
| 3680 | && imm_expr.X_add_number >= maxnum |
| 3681 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
| 3682 | { |
| 3683 | do_false: |
| 3684 | /* result is always false */ |
| 3685 | if (! likely) |
| 3686 | { |
| 3687 | if (warn_nops) |
| 3688 | as_warn (_("Branch %s is always false (nop)"), |
| 3689 | ip->insn_mo->name); |
| 3690 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
| 3691 | } |
| 3692 | else |
| 3693 | { |
| 3694 | if (warn_nops) |
| 3695 | as_warn (_("Branch likely %s is always false"), |
| 3696 | ip->insn_mo->name); |
| 3697 | macro_build ((char *) NULL, &icnt, &offset_expr, "bnel", |
| 3698 | "s,t,p", 0, 0); |
| 3699 | } |
| 3700 | return; |
| 3701 | } |
| 3702 | if (imm_expr.X_op != O_constant) |
| 3703 | as_bad (_("Unsupported large constant")); |
| 3704 | imm_expr.X_add_number++; |
| 3705 | /* FALLTHROUGH */ |
| 3706 | case M_BGE_I: |
| 3707 | case M_BGEL_I: |
| 3708 | if (mask == M_BGEL_I) |
| 3709 | likely = 1; |
| 3710 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 3711 | { |
| 3712 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3713 | likely ? "bgezl" : "bgez", "s,p", sreg); |
| 3714 | return; |
| 3715 | } |
| 3716 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 3717 | { |
| 3718 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3719 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
| 3720 | return; |
| 3721 | } |
| 3722 | maxnum = 0x7fffffff; |
| 3723 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
| 3724 | { |
| 3725 | maxnum <<= 16; |
| 3726 | maxnum |= 0xffff; |
| 3727 | maxnum <<= 16; |
| 3728 | maxnum |= 0xffff; |
| 3729 | } |
| 3730 | maxnum = - maxnum - 1; |
| 3731 | if (imm_expr.X_op == O_constant |
| 3732 | && imm_expr.X_add_number <= maxnum |
| 3733 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
| 3734 | { |
| 3735 | do_true: |
| 3736 | /* result is always true */ |
| 3737 | as_warn (_("Branch %s is always true"), ip->insn_mo->name); |
| 3738 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
| 3739 | return; |
| 3740 | } |
| 3741 | set_at (&icnt, sreg, 0); |
| 3742 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3743 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 3744 | break; |
| 3745 | |
| 3746 | case M_BGEUL: |
| 3747 | likely = 1; |
| 3748 | case M_BGEU: |
| 3749 | if (treg == 0) |
| 3750 | goto do_true; |
| 3751 | if (sreg == 0) |
| 3752 | { |
| 3753 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3754 | likely ? "beql" : "beq", "s,t,p", 0, treg); |
| 3755 | return; |
| 3756 | } |
| 3757 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
| 3758 | treg); |
| 3759 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3760 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 3761 | break; |
| 3762 | |
| 3763 | case M_BGTUL_I: |
| 3764 | likely = 1; |
| 3765 | case M_BGTU_I: |
| 3766 | if (sreg == 0 |
| 3767 | || (HAVE_32BIT_GPRS |
| 3768 | && imm_expr.X_op == O_constant |
| 3769 | && imm_expr.X_add_number == 0xffffffff)) |
| 3770 | goto do_false; |
| 3771 | if (imm_expr.X_op != O_constant) |
| 3772 | as_bad (_("Unsupported large constant")); |
| 3773 | imm_expr.X_add_number++; |
| 3774 | /* FALLTHROUGH */ |
| 3775 | case M_BGEU_I: |
| 3776 | case M_BGEUL_I: |
| 3777 | if (mask == M_BGEUL_I) |
| 3778 | likely = 1; |
| 3779 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 3780 | goto do_true; |
| 3781 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 3782 | { |
| 3783 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3784 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
| 3785 | return; |
| 3786 | } |
| 3787 | set_at (&icnt, sreg, 1); |
| 3788 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3789 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 3790 | break; |
| 3791 | |
| 3792 | case M_BGTL: |
| 3793 | likely = 1; |
| 3794 | case M_BGT: |
| 3795 | if (treg == 0) |
| 3796 | { |
| 3797 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3798 | likely ? "bgtzl" : "bgtz", "s,p", sreg); |
| 3799 | return; |
| 3800 | } |
| 3801 | if (sreg == 0) |
| 3802 | { |
| 3803 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3804 | likely ? "bltzl" : "bltz", "s,p", treg); |
| 3805 | return; |
| 3806 | } |
| 3807 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
| 3808 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3809 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 3810 | break; |
| 3811 | |
| 3812 | case M_BGTUL: |
| 3813 | likely = 1; |
| 3814 | case M_BGTU: |
| 3815 | if (treg == 0) |
| 3816 | { |
| 3817 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3818 | likely ? "bnel" : "bne", "s,t,p", sreg, 0); |
| 3819 | return; |
| 3820 | } |
| 3821 | if (sreg == 0) |
| 3822 | goto do_false; |
| 3823 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
| 3824 | sreg); |
| 3825 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3826 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 3827 | break; |
| 3828 | |
| 3829 | case M_BLEL: |
| 3830 | likely = 1; |
| 3831 | case M_BLE: |
| 3832 | if (treg == 0) |
| 3833 | { |
| 3834 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3835 | likely ? "blezl" : "blez", "s,p", sreg); |
| 3836 | return; |
| 3837 | } |
| 3838 | if (sreg == 0) |
| 3839 | { |
| 3840 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3841 | likely ? "bgezl" : "bgez", "s,p", treg); |
| 3842 | return; |
| 3843 | } |
| 3844 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg); |
| 3845 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3846 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 3847 | break; |
| 3848 | |
| 3849 | case M_BLEL_I: |
| 3850 | likely = 1; |
| 3851 | case M_BLE_I: |
| 3852 | maxnum = 0x7fffffff; |
| 3853 | if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4) |
| 3854 | { |
| 3855 | maxnum <<= 16; |
| 3856 | maxnum |= 0xffff; |
| 3857 | maxnum <<= 16; |
| 3858 | maxnum |= 0xffff; |
| 3859 | } |
| 3860 | if (imm_expr.X_op == O_constant |
| 3861 | && imm_expr.X_add_number >= maxnum |
| 3862 | && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4)) |
| 3863 | goto do_true; |
| 3864 | if (imm_expr.X_op != O_constant) |
| 3865 | as_bad (_("Unsupported large constant")); |
| 3866 | imm_expr.X_add_number++; |
| 3867 | /* FALLTHROUGH */ |
| 3868 | case M_BLT_I: |
| 3869 | case M_BLTL_I: |
| 3870 | if (mask == M_BLTL_I) |
| 3871 | likely = 1; |
| 3872 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 3873 | { |
| 3874 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3875 | likely ? "bltzl" : "bltz", "s,p", sreg); |
| 3876 | return; |
| 3877 | } |
| 3878 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 3879 | { |
| 3880 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3881 | likely ? "blezl" : "blez", "s,p", sreg); |
| 3882 | return; |
| 3883 | } |
| 3884 | set_at (&icnt, sreg, 0); |
| 3885 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3886 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 3887 | break; |
| 3888 | |
| 3889 | case M_BLEUL: |
| 3890 | likely = 1; |
| 3891 | case M_BLEU: |
| 3892 | if (treg == 0) |
| 3893 | { |
| 3894 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3895 | likely ? "beql" : "beq", "s,t,p", sreg, 0); |
| 3896 | return; |
| 3897 | } |
| 3898 | if (sreg == 0) |
| 3899 | goto do_true; |
| 3900 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, |
| 3901 | sreg); |
| 3902 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3903 | likely ? "beql" : "beq", "s,t,p", AT, 0); |
| 3904 | break; |
| 3905 | |
| 3906 | case M_BLEUL_I: |
| 3907 | likely = 1; |
| 3908 | case M_BLEU_I: |
| 3909 | if (sreg == 0 |
| 3910 | || (HAVE_32BIT_GPRS |
| 3911 | && imm_expr.X_op == O_constant |
| 3912 | && imm_expr.X_add_number == 0xffffffff)) |
| 3913 | goto do_true; |
| 3914 | if (imm_expr.X_op != O_constant) |
| 3915 | as_bad (_("Unsupported large constant")); |
| 3916 | imm_expr.X_add_number++; |
| 3917 | /* FALLTHROUGH */ |
| 3918 | case M_BLTU_I: |
| 3919 | case M_BLTUL_I: |
| 3920 | if (mask == M_BLTUL_I) |
| 3921 | likely = 1; |
| 3922 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 3923 | goto do_false; |
| 3924 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 3925 | { |
| 3926 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3927 | likely ? "beql" : "beq", |
| 3928 | "s,t,p", sreg, 0); |
| 3929 | return; |
| 3930 | } |
| 3931 | set_at (&icnt, sreg, 1); |
| 3932 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3933 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 3934 | break; |
| 3935 | |
| 3936 | case M_BLTL: |
| 3937 | likely = 1; |
| 3938 | case M_BLT: |
| 3939 | if (treg == 0) |
| 3940 | { |
| 3941 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3942 | likely ? "bltzl" : "bltz", "s,p", sreg); |
| 3943 | return; |
| 3944 | } |
| 3945 | if (sreg == 0) |
| 3946 | { |
| 3947 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3948 | likely ? "bgtzl" : "bgtz", "s,p", treg); |
| 3949 | return; |
| 3950 | } |
| 3951 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg); |
| 3952 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3953 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 3954 | break; |
| 3955 | |
| 3956 | case M_BLTUL: |
| 3957 | likely = 1; |
| 3958 | case M_BLTU: |
| 3959 | if (treg == 0) |
| 3960 | goto do_false; |
| 3961 | if (sreg == 0) |
| 3962 | { |
| 3963 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3964 | likely ? "bnel" : "bne", "s,t,p", 0, treg); |
| 3965 | return; |
| 3966 | } |
| 3967 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, |
| 3968 | treg); |
| 3969 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 3970 | likely ? "bnel" : "bne", "s,t,p", AT, 0); |
| 3971 | break; |
| 3972 | |
| 3973 | case M_DDIV_3: |
| 3974 | dbl = 1; |
| 3975 | case M_DIV_3: |
| 3976 | s = "mflo"; |
| 3977 | goto do_div3; |
| 3978 | case M_DREM_3: |
| 3979 | dbl = 1; |
| 3980 | case M_REM_3: |
| 3981 | s = "mfhi"; |
| 3982 | do_div3: |
| 3983 | if (treg == 0) |
| 3984 | { |
| 3985 | as_warn (_("Divide by zero.")); |
| 3986 | if (mips_trap) |
| 3987 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); |
| 3988 | else |
| 3989 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
| 3990 | return; |
| 3991 | } |
| 3992 | |
| 3993 | mips_emit_delays (true); |
| 3994 | ++mips_opts.noreorder; |
| 3995 | mips_any_noreorder = 1; |
| 3996 | if (mips_trap) |
| 3997 | { |
| 3998 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); |
| 3999 | macro_build ((char *) NULL, &icnt, NULL, |
| 4000 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
| 4001 | } |
| 4002 | else |
| 4003 | { |
| 4004 | expr1.X_add_number = 8; |
| 4005 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
| 4006 | macro_build ((char *) NULL, &icnt, NULL, |
| 4007 | dbl ? "ddiv" : "div", "z,s,t", sreg, treg); |
| 4008 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
| 4009 | } |
| 4010 | expr1.X_add_number = -1; |
| 4011 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4012 | dbl ? "daddiu" : "addiu", |
| 4013 | "t,r,j", AT, 0, (int) BFD_RELOC_LO16); |
| 4014 | expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
| 4015 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT); |
| 4016 | if (dbl) |
| 4017 | { |
| 4018 | expr1.X_add_number = 1; |
| 4019 | macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0, |
| 4020 | (int) BFD_RELOC_LO16); |
| 4021 | macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, |
| 4022 | 31); |
| 4023 | } |
| 4024 | else |
| 4025 | { |
| 4026 | expr1.X_add_number = 0x80000000; |
| 4027 | macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT, |
| 4028 | (int) BFD_RELOC_HI16); |
| 4029 | } |
| 4030 | if (mips_trap) |
| 4031 | { |
| 4032 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT); |
| 4033 | /* We want to close the noreorder block as soon as possible, so |
| 4034 | that later insns are available for delay slot filling. */ |
| 4035 | --mips_opts.noreorder; |
| 4036 | } |
| 4037 | else |
| 4038 | { |
| 4039 | expr1.X_add_number = 8; |
| 4040 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT); |
| 4041 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
| 4042 | |
| 4043 | /* We want to close the noreorder block as soon as possible, so |
| 4044 | that later insns are available for delay slot filling. */ |
| 4045 | --mips_opts.noreorder; |
| 4046 | |
| 4047 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
| 4048 | } |
| 4049 | macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg); |
| 4050 | break; |
| 4051 | |
| 4052 | case M_DIV_3I: |
| 4053 | s = "div"; |
| 4054 | s2 = "mflo"; |
| 4055 | goto do_divi; |
| 4056 | case M_DIVU_3I: |
| 4057 | s = "divu"; |
| 4058 | s2 = "mflo"; |
| 4059 | goto do_divi; |
| 4060 | case M_REM_3I: |
| 4061 | s = "div"; |
| 4062 | s2 = "mfhi"; |
| 4063 | goto do_divi; |
| 4064 | case M_REMU_3I: |
| 4065 | s = "divu"; |
| 4066 | s2 = "mfhi"; |
| 4067 | goto do_divi; |
| 4068 | case M_DDIV_3I: |
| 4069 | dbl = 1; |
| 4070 | s = "ddiv"; |
| 4071 | s2 = "mflo"; |
| 4072 | goto do_divi; |
| 4073 | case M_DDIVU_3I: |
| 4074 | dbl = 1; |
| 4075 | s = "ddivu"; |
| 4076 | s2 = "mflo"; |
| 4077 | goto do_divi; |
| 4078 | case M_DREM_3I: |
| 4079 | dbl = 1; |
| 4080 | s = "ddiv"; |
| 4081 | s2 = "mfhi"; |
| 4082 | goto do_divi; |
| 4083 | case M_DREMU_3I: |
| 4084 | dbl = 1; |
| 4085 | s = "ddivu"; |
| 4086 | s2 = "mfhi"; |
| 4087 | do_divi: |
| 4088 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 4089 | { |
| 4090 | as_warn (_("Divide by zero.")); |
| 4091 | if (mips_trap) |
| 4092 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0); |
| 4093 | else |
| 4094 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
| 4095 | return; |
| 4096 | } |
| 4097 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1) |
| 4098 | { |
| 4099 | if (strcmp (s2, "mflo") == 0) |
| 4100 | move_register (&icnt, dreg, sreg); |
| 4101 | else |
| 4102 | move_register (&icnt, dreg, 0); |
| 4103 | return; |
| 4104 | } |
| 4105 | if (imm_expr.X_op == O_constant |
| 4106 | && imm_expr.X_add_number == -1 |
| 4107 | && s[strlen (s) - 1] != 'u') |
| 4108 | { |
| 4109 | if (strcmp (s2, "mflo") == 0) |
| 4110 | { |
| 4111 | macro_build ((char *) NULL, &icnt, NULL, dbl ? "dneg" : "neg", |
| 4112 | "d,w", dreg, sreg); |
| 4113 | } |
| 4114 | else |
| 4115 | move_register (&icnt, dreg, 0); |
| 4116 | return; |
| 4117 | } |
| 4118 | |
| 4119 | load_register (&icnt, AT, &imm_expr, dbl); |
| 4120 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT); |
| 4121 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
| 4122 | break; |
| 4123 | |
| 4124 | case M_DIVU_3: |
| 4125 | s = "divu"; |
| 4126 | s2 = "mflo"; |
| 4127 | goto do_divu3; |
| 4128 | case M_REMU_3: |
| 4129 | s = "divu"; |
| 4130 | s2 = "mfhi"; |
| 4131 | goto do_divu3; |
| 4132 | case M_DDIVU_3: |
| 4133 | s = "ddivu"; |
| 4134 | s2 = "mflo"; |
| 4135 | goto do_divu3; |
| 4136 | case M_DREMU_3: |
| 4137 | s = "ddivu"; |
| 4138 | s2 = "mfhi"; |
| 4139 | do_divu3: |
| 4140 | mips_emit_delays (true); |
| 4141 | ++mips_opts.noreorder; |
| 4142 | mips_any_noreorder = 1; |
| 4143 | if (mips_trap) |
| 4144 | { |
| 4145 | macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0); |
| 4146 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); |
| 4147 | /* We want to close the noreorder block as soon as possible, so |
| 4148 | that later insns are available for delay slot filling. */ |
| 4149 | --mips_opts.noreorder; |
| 4150 | } |
| 4151 | else |
| 4152 | { |
| 4153 | expr1.X_add_number = 8; |
| 4154 | macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0); |
| 4155 | macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg); |
| 4156 | |
| 4157 | /* We want to close the noreorder block as soon as possible, so |
| 4158 | that later insns are available for delay slot filling. */ |
| 4159 | --mips_opts.noreorder; |
| 4160 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7); |
| 4161 | } |
| 4162 | macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg); |
| 4163 | return; |
| 4164 | |
| 4165 | case M_DLA_AB: |
| 4166 | dbl = 1; |
| 4167 | case M_LA_AB: |
| 4168 | /* Load the address of a symbol into a register. If breg is not |
| 4169 | zero, we then add a base register to it. */ |
| 4170 | |
| 4171 | /* When generating embedded PIC code, we permit expressions of |
| 4172 | the form |
| 4173 | la $4,foo-bar |
| 4174 | where bar is an address in the current section. These are used |
| 4175 | when getting the addresses of functions. We don't permit |
| 4176 | X_add_number to be non-zero, because if the symbol is |
| 4177 | external the relaxing code needs to know that any addend is |
| 4178 | purely the offset to X_op_symbol. */ |
| 4179 | if (mips_pic == EMBEDDED_PIC |
| 4180 | && offset_expr.X_op == O_subtract |
| 4181 | && (symbol_constant_p (offset_expr.X_op_symbol) |
| 4182 | ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg |
| 4183 | : (symbol_equated_p (offset_expr.X_op_symbol) |
| 4184 | && (S_GET_SEGMENT |
| 4185 | (symbol_get_value_expression (offset_expr.X_op_symbol) |
| 4186 | ->X_add_symbol) |
| 4187 | == now_seg))) |
| 4188 | && breg == 0 |
| 4189 | && (offset_expr.X_add_number == 0 |
| 4190 | || OUTPUT_FLAVOR == bfd_target_elf_flavour)) |
| 4191 | { |
| 4192 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 4193 | treg, (int) BFD_RELOC_PCREL_HI16_S); |
| 4194 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4195 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4196 | "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16); |
| 4197 | return; |
| 4198 | } |
| 4199 | |
| 4200 | if (offset_expr.X_op != O_symbol |
| 4201 | && offset_expr.X_op != O_constant) |
| 4202 | { |
| 4203 | as_bad (_("expression too complex")); |
| 4204 | offset_expr.X_op = O_constant; |
| 4205 | } |
| 4206 | |
| 4207 | if (treg == breg) |
| 4208 | { |
| 4209 | tempreg = AT; |
| 4210 | used_at = 1; |
| 4211 | } |
| 4212 | else |
| 4213 | { |
| 4214 | tempreg = treg; |
| 4215 | used_at = 0; |
| 4216 | } |
| 4217 | |
| 4218 | if (offset_expr.X_op == O_constant) |
| 4219 | load_register (&icnt, tempreg, &offset_expr, dbl); |
| 4220 | else if (mips_pic == NO_PIC) |
| 4221 | { |
| 4222 | /* If this is a reference to an GP relative symbol, we want |
| 4223 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) |
| 4224 | Otherwise we want |
| 4225 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 4226 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 4227 | If we have a constant, we need two instructions anyhow, |
| 4228 | so we may as well always use the latter form. */ |
| 4229 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
| 4230 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 4231 | p = NULL; |
| 4232 | else |
| 4233 | { |
| 4234 | frag_grow (20); |
| 4235 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4236 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4237 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
| 4238 | p = frag_var (rs_machine_dependent, 8, 0, |
| 4239 | RELAX_ENCODE (4, 8, 0, 4, 0, |
| 4240 | mips_opts.warn_about_macros), |
| 4241 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4242 | (char *) NULL); |
| 4243 | } |
| 4244 | macro_build_lui (p, &icnt, &offset_expr, tempreg); |
| 4245 | if (p != NULL) |
| 4246 | p += 4; |
| 4247 | macro_build (p, &icnt, &offset_expr, |
| 4248 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4249 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4250 | } |
| 4251 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
| 4252 | { |
| 4253 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
| 4254 | |
| 4255 | /* If this is a reference to an external symbol, and there |
| 4256 | is no constant, we want |
| 4257 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4258 | or if tempreg is PIC_CALL_REG |
| 4259 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
| 4260 | For a local symbol, we want |
| 4261 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4262 | nop |
| 4263 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 4264 | |
| 4265 | If we have a small constant, and this is a reference to |
| 4266 | an external symbol, we want |
| 4267 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4268 | nop |
| 4269 | addiu $tempreg,$tempreg,<constant> |
| 4270 | For a local symbol, we want the same instruction |
| 4271 | sequence, but we output a BFD_RELOC_LO16 reloc on the |
| 4272 | addiu instruction. |
| 4273 | |
| 4274 | If we have a large constant, and this is a reference to |
| 4275 | an external symbol, we want |
| 4276 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4277 | lui $at,<hiconstant> |
| 4278 | addiu $at,$at,<loconstant> |
| 4279 | addu $tempreg,$tempreg,$at |
| 4280 | For a local symbol, we want the same instruction |
| 4281 | sequence, but we output a BFD_RELOC_LO16 reloc on the |
| 4282 | addiu instruction. */ |
| 4283 | expr1.X_add_number = offset_expr.X_add_number; |
| 4284 | offset_expr.X_add_number = 0; |
| 4285 | frag_grow (32); |
| 4286 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
| 4287 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
| 4288 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4289 | dbl ? "ld" : "lw", |
| 4290 | "t,o(b)", tempreg, lw_reloc_type, GP); |
| 4291 | if (expr1.X_add_number == 0) |
| 4292 | { |
| 4293 | int off; |
| 4294 | |
| 4295 | if (breg == 0) |
| 4296 | off = 0; |
| 4297 | else |
| 4298 | { |
| 4299 | /* We're going to put in an addu instruction using |
| 4300 | tempreg, so we may as well insert the nop right |
| 4301 | now. */ |
| 4302 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4303 | "nop", ""); |
| 4304 | off = 4; |
| 4305 | } |
| 4306 | p = frag_var (rs_machine_dependent, 8 - off, 0, |
| 4307 | RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0, |
| 4308 | (breg == 0 |
| 4309 | ? mips_opts.warn_about_macros |
| 4310 | : 0)), |
| 4311 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4312 | (char *) NULL); |
| 4313 | if (breg == 0) |
| 4314 | { |
| 4315 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4316 | p += 4; |
| 4317 | } |
| 4318 | macro_build (p, &icnt, &expr1, |
| 4319 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4320 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4321 | /* FIXME: If breg == 0, and the next instruction uses |
| 4322 | $tempreg, then if this variant case is used an extra |
| 4323 | nop will be generated. */ |
| 4324 | } |
| 4325 | else if (expr1.X_add_number >= -0x8000 |
| 4326 | && expr1.X_add_number < 0x8000) |
| 4327 | { |
| 4328 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4329 | "nop", ""); |
| 4330 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4331 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4332 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4333 | (void) frag_var (rs_machine_dependent, 0, 0, |
| 4334 | RELAX_ENCODE (0, 0, -12, -4, 0, 0), |
| 4335 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4336 | (char *) NULL); |
| 4337 | } |
| 4338 | else |
| 4339 | { |
| 4340 | int off1; |
| 4341 | |
| 4342 | /* If we are going to add in a base register, and the |
| 4343 | target register and the base register are the same, |
| 4344 | then we are using AT as a temporary register. Since |
| 4345 | we want to load the constant into AT, we add our |
| 4346 | current AT (from the global offset table) and the |
| 4347 | register into the register now, and pretend we were |
| 4348 | not using a base register. */ |
| 4349 | if (breg != treg) |
| 4350 | off1 = 0; |
| 4351 | else |
| 4352 | { |
| 4353 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4354 | "nop", ""); |
| 4355 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4356 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4357 | "d,v,t", treg, AT, breg); |
| 4358 | breg = 0; |
| 4359 | tempreg = treg; |
| 4360 | off1 = -8; |
| 4361 | } |
| 4362 | |
| 4363 | /* Set mips_optimize around the lui instruction to avoid |
| 4364 | inserting an unnecessary nop after the lw. */ |
| 4365 | hold_mips_optimize = mips_optimize; |
| 4366 | mips_optimize = 2; |
| 4367 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
| 4368 | mips_optimize = hold_mips_optimize; |
| 4369 | |
| 4370 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4371 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4372 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
| 4373 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4374 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4375 | "d,v,t", tempreg, tempreg, AT); |
| 4376 | (void) frag_var (rs_machine_dependent, 0, 0, |
| 4377 | RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0), |
| 4378 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4379 | (char *) NULL); |
| 4380 | used_at = 1; |
| 4381 | } |
| 4382 | } |
| 4383 | else if (mips_pic == SVR4_PIC) |
| 4384 | { |
| 4385 | int gpdel; |
| 4386 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
| 4387 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; |
| 4388 | |
| 4389 | /* This is the large GOT case. If this is a reference to an |
| 4390 | external symbol, and there is no constant, we want |
| 4391 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 4392 | addu $tempreg,$tempreg,$gp |
| 4393 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 4394 | or if tempreg is PIC_CALL_REG |
| 4395 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
| 4396 | addu $tempreg,$tempreg,$gp |
| 4397 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) |
| 4398 | For a local symbol, we want |
| 4399 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4400 | nop |
| 4401 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 4402 | |
| 4403 | If we have a small constant, and this is a reference to |
| 4404 | an external symbol, we want |
| 4405 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 4406 | addu $tempreg,$tempreg,$gp |
| 4407 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 4408 | nop |
| 4409 | addiu $tempreg,$tempreg,<constant> |
| 4410 | For a local symbol, we want |
| 4411 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4412 | nop |
| 4413 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) |
| 4414 | |
| 4415 | If we have a large constant, and this is a reference to |
| 4416 | an external symbol, we want |
| 4417 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 4418 | addu $tempreg,$tempreg,$gp |
| 4419 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 4420 | lui $at,<hiconstant> |
| 4421 | addiu $at,$at,<loconstant> |
| 4422 | addu $tempreg,$tempreg,$at |
| 4423 | For a local symbol, we want |
| 4424 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4425 | lui $at,<hiconstant> |
| 4426 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) |
| 4427 | addu $tempreg,$tempreg,$at |
| 4428 | */ |
| 4429 | expr1.X_add_number = offset_expr.X_add_number; |
| 4430 | offset_expr.X_add_number = 0; |
| 4431 | frag_grow (52); |
| 4432 | if (reg_needs_delay (GP)) |
| 4433 | gpdel = 4; |
| 4434 | else |
| 4435 | gpdel = 0; |
| 4436 | if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG) |
| 4437 | { |
| 4438 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; |
| 4439 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; |
| 4440 | } |
| 4441 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 4442 | tempreg, lui_reloc_type); |
| 4443 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4444 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4445 | "d,v,t", tempreg, tempreg, GP); |
| 4446 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4447 | dbl ? "ld" : "lw", |
| 4448 | "t,o(b)", tempreg, lw_reloc_type, tempreg); |
| 4449 | if (expr1.X_add_number == 0) |
| 4450 | { |
| 4451 | int off; |
| 4452 | |
| 4453 | if (breg == 0) |
| 4454 | off = 0; |
| 4455 | else |
| 4456 | { |
| 4457 | /* We're going to put in an addu instruction using |
| 4458 | tempreg, so we may as well insert the nop right |
| 4459 | now. */ |
| 4460 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4461 | "nop", ""); |
| 4462 | off = 4; |
| 4463 | } |
| 4464 | |
| 4465 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
| 4466 | RELAX_ENCODE (12 + off, 12 + gpdel, gpdel, |
| 4467 | 8 + gpdel, 0, |
| 4468 | (breg == 0 |
| 4469 | ? mips_opts.warn_about_macros |
| 4470 | : 0)), |
| 4471 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4472 | (char *) NULL); |
| 4473 | } |
| 4474 | else if (expr1.X_add_number >= -0x8000 |
| 4475 | && expr1.X_add_number < 0x8000) |
| 4476 | { |
| 4477 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4478 | "nop", ""); |
| 4479 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4480 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4481 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4482 | |
| 4483 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
| 4484 | RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0, |
| 4485 | (breg == 0 |
| 4486 | ? mips_opts.warn_about_macros |
| 4487 | : 0)), |
| 4488 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4489 | (char *) NULL); |
| 4490 | } |
| 4491 | else |
| 4492 | { |
| 4493 | int adj, dreg; |
| 4494 | |
| 4495 | /* If we are going to add in a base register, and the |
| 4496 | target register and the base register are the same, |
| 4497 | then we are using AT as a temporary register. Since |
| 4498 | we want to load the constant into AT, we add our |
| 4499 | current AT (from the global offset table) and the |
| 4500 | register into the register now, and pretend we were |
| 4501 | not using a base register. */ |
| 4502 | if (breg != treg) |
| 4503 | { |
| 4504 | adj = 0; |
| 4505 | dreg = tempreg; |
| 4506 | } |
| 4507 | else |
| 4508 | { |
| 4509 | assert (tempreg == AT); |
| 4510 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4511 | "nop", ""); |
| 4512 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4513 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4514 | "d,v,t", treg, AT, breg); |
| 4515 | dreg = treg; |
| 4516 | adj = 8; |
| 4517 | } |
| 4518 | |
| 4519 | /* Set mips_optimize around the lui instruction to avoid |
| 4520 | inserting an unnecessary nop after the lw. */ |
| 4521 | hold_mips_optimize = mips_optimize; |
| 4522 | mips_optimize = 2; |
| 4523 | macro_build_lui ((char *) NULL, &icnt, &expr1, AT); |
| 4524 | mips_optimize = hold_mips_optimize; |
| 4525 | |
| 4526 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4527 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4528 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
| 4529 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4530 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4531 | "d,v,t", dreg, dreg, AT); |
| 4532 | |
| 4533 | p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0, |
| 4534 | RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel, |
| 4535 | 8 + gpdel, 0, |
| 4536 | (breg == 0 |
| 4537 | ? mips_opts.warn_about_macros |
| 4538 | : 0)), |
| 4539 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4540 | (char *) NULL); |
| 4541 | |
| 4542 | used_at = 1; |
| 4543 | } |
| 4544 | |
| 4545 | if (gpdel > 0) |
| 4546 | { |
| 4547 | /* This is needed because this instruction uses $gp, but |
| 4548 | the first instruction on the main stream does not. */ |
| 4549 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4550 | p += 4; |
| 4551 | } |
| 4552 | macro_build (p, &icnt, &offset_expr, |
| 4553 | dbl ? "ld" : "lw", |
| 4554 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
| 4555 | p += 4; |
| 4556 | if (expr1.X_add_number >= -0x8000 |
| 4557 | && expr1.X_add_number < 0x8000) |
| 4558 | { |
| 4559 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4560 | p += 4; |
| 4561 | macro_build (p, &icnt, &expr1, |
| 4562 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4563 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 4564 | /* FIXME: If add_number is 0, and there was no base |
| 4565 | register, the external symbol case ended with a load, |
| 4566 | so if the symbol turns out to not be external, and |
| 4567 | the next instruction uses tempreg, an unnecessary nop |
| 4568 | will be inserted. */ |
| 4569 | } |
| 4570 | else |
| 4571 | { |
| 4572 | if (breg == treg) |
| 4573 | { |
| 4574 | /* We must add in the base register now, as in the |
| 4575 | external symbol case. */ |
| 4576 | assert (tempreg == AT); |
| 4577 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4578 | p += 4; |
| 4579 | macro_build (p, &icnt, (expressionS *) NULL, |
| 4580 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4581 | "d,v,t", treg, AT, breg); |
| 4582 | p += 4; |
| 4583 | tempreg = treg; |
| 4584 | /* We set breg to 0 because we have arranged to add |
| 4585 | it in in both cases. */ |
| 4586 | breg = 0; |
| 4587 | } |
| 4588 | |
| 4589 | macro_build_lui (p, &icnt, &expr1, AT); |
| 4590 | p += 4; |
| 4591 | macro_build (p, &icnt, &expr1, |
| 4592 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4593 | "t,r,j", AT, AT, (int) BFD_RELOC_LO16); |
| 4594 | p += 4; |
| 4595 | macro_build (p, &icnt, (expressionS *) NULL, |
| 4596 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4597 | "d,v,t", tempreg, tempreg, AT); |
| 4598 | p += 4; |
| 4599 | } |
| 4600 | } |
| 4601 | else if (mips_pic == EMBEDDED_PIC) |
| 4602 | { |
| 4603 | /* We use |
| 4604 | addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL) |
| 4605 | */ |
| 4606 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4607 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4608 | "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL); |
| 4609 | } |
| 4610 | else |
| 4611 | abort (); |
| 4612 | |
| 4613 | if (breg != 0) |
| 4614 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4615 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4616 | "d,v,t", treg, tempreg, breg); |
| 4617 | |
| 4618 | if (! used_at) |
| 4619 | return; |
| 4620 | |
| 4621 | break; |
| 4622 | |
| 4623 | case M_J_A: |
| 4624 | /* The j instruction may not be used in PIC code, since it |
| 4625 | requires an absolute address. We convert it to a b |
| 4626 | instruction. */ |
| 4627 | if (mips_pic == NO_PIC) |
| 4628 | macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a"); |
| 4629 | else |
| 4630 | macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p"); |
| 4631 | return; |
| 4632 | |
| 4633 | /* The jal instructions must be handled as macros because when |
| 4634 | generating PIC code they expand to multi-instruction |
| 4635 | sequences. Normally they are simple instructions. */ |
| 4636 | case M_JAL_1: |
| 4637 | dreg = RA; |
| 4638 | /* Fall through. */ |
| 4639 | case M_JAL_2: |
| 4640 | if (mips_pic == NO_PIC |
| 4641 | || mips_pic == EMBEDDED_PIC) |
| 4642 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
| 4643 | "d,s", dreg, sreg); |
| 4644 | else if (mips_pic == SVR4_PIC) |
| 4645 | { |
| 4646 | if (sreg != PIC_CALL_REG) |
| 4647 | as_warn (_("MIPS PIC call to register other than $25")); |
| 4648 | |
| 4649 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr", |
| 4650 | "d,s", dreg, sreg); |
| 4651 | if (mips_cprestore_offset < 0) |
| 4652 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
| 4653 | else |
| 4654 | { |
| 4655 | expr1.X_add_number = mips_cprestore_offset; |
| 4656 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4657 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 4658 | "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg); |
| 4659 | } |
| 4660 | } |
| 4661 | else |
| 4662 | abort (); |
| 4663 | |
| 4664 | return; |
| 4665 | |
| 4666 | case M_JAL_A: |
| 4667 | if (mips_pic == NO_PIC) |
| 4668 | macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a"); |
| 4669 | else if (mips_pic == SVR4_PIC) |
| 4670 | { |
| 4671 | /* If this is a reference to an external symbol, and we are |
| 4672 | using a small GOT, we want |
| 4673 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
| 4674 | nop |
| 4675 | jalr $25 |
| 4676 | nop |
| 4677 | lw $gp,cprestore($sp) |
| 4678 | The cprestore value is set using the .cprestore |
| 4679 | pseudo-op. If we are using a big GOT, we want |
| 4680 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
| 4681 | addu $25,$25,$gp |
| 4682 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) |
| 4683 | nop |
| 4684 | jalr $25 |
| 4685 | nop |
| 4686 | lw $gp,cprestore($sp) |
| 4687 | If the symbol is not external, we want |
| 4688 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 4689 | nop |
| 4690 | addiu $25,$25,<sym> (BFD_RELOC_LO16) |
| 4691 | jalr $25 |
| 4692 | nop |
| 4693 | lw $gp,cprestore($sp) */ |
| 4694 | frag_grow (40); |
| 4695 | if (! mips_big_got) |
| 4696 | { |
| 4697 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4698 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 4699 | "t,o(b)", PIC_CALL_REG, |
| 4700 | (int) BFD_RELOC_MIPS_CALL16, GP); |
| 4701 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4702 | "nop", ""); |
| 4703 | p = frag_var (rs_machine_dependent, 4, 0, |
| 4704 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
| 4705 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4706 | (char *) NULL); |
| 4707 | } |
| 4708 | else |
| 4709 | { |
| 4710 | int gpdel; |
| 4711 | |
| 4712 | if (reg_needs_delay (GP)) |
| 4713 | gpdel = 4; |
| 4714 | else |
| 4715 | gpdel = 0; |
| 4716 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 4717 | PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16); |
| 4718 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4719 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 4720 | "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP); |
| 4721 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 4722 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 4723 | "t,o(b)", PIC_CALL_REG, |
| 4724 | (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG); |
| 4725 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4726 | "nop", ""); |
| 4727 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
| 4728 | RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel, |
| 4729 | 0, 0), |
| 4730 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4731 | (char *) NULL); |
| 4732 | if (gpdel > 0) |
| 4733 | { |
| 4734 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4735 | p += 4; |
| 4736 | } |
| 4737 | macro_build (p, &icnt, &offset_expr, |
| 4738 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 4739 | "t,o(b)", PIC_CALL_REG, |
| 4740 | (int) BFD_RELOC_MIPS_GOT16, GP); |
| 4741 | p += 4; |
| 4742 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 4743 | p += 4; |
| 4744 | } |
| 4745 | macro_build (p, &icnt, &offset_expr, |
| 4746 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 4747 | "t,r,j", PIC_CALL_REG, PIC_CALL_REG, |
| 4748 | (int) BFD_RELOC_LO16); |
| 4749 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4750 | "jalr", "s", PIC_CALL_REG); |
| 4751 | if (mips_cprestore_offset < 0) |
| 4752 | as_warn (_("No .cprestore pseudo-op used in PIC code")); |
| 4753 | else |
| 4754 | { |
| 4755 | if (mips_opts.noreorder) |
| 4756 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 4757 | "nop", ""); |
| 4758 | expr1.X_add_number = mips_cprestore_offset; |
| 4759 | macro_build ((char *) NULL, &icnt, &expr1, |
| 4760 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 4761 | "t,o(b)", GP, (int) BFD_RELOC_LO16, |
| 4762 | mips_frame_reg); |
| 4763 | } |
| 4764 | } |
| 4765 | else if (mips_pic == EMBEDDED_PIC) |
| 4766 | { |
| 4767 | macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p"); |
| 4768 | /* The linker may expand the call to a longer sequence which |
| 4769 | uses $at, so we must break rather than return. */ |
| 4770 | break; |
| 4771 | } |
| 4772 | else |
| 4773 | abort (); |
| 4774 | |
| 4775 | return; |
| 4776 | |
| 4777 | case M_LB_AB: |
| 4778 | s = "lb"; |
| 4779 | goto ld; |
| 4780 | case M_LBU_AB: |
| 4781 | s = "lbu"; |
| 4782 | goto ld; |
| 4783 | case M_LH_AB: |
| 4784 | s = "lh"; |
| 4785 | goto ld; |
| 4786 | case M_LHU_AB: |
| 4787 | s = "lhu"; |
| 4788 | goto ld; |
| 4789 | case M_LW_AB: |
| 4790 | s = "lw"; |
| 4791 | goto ld; |
| 4792 | case M_LWC0_AB: |
| 4793 | s = "lwc0"; |
| 4794 | /* Itbl support may require additional care here. */ |
| 4795 | coproc = 1; |
| 4796 | goto ld; |
| 4797 | case M_LWC1_AB: |
| 4798 | s = "lwc1"; |
| 4799 | /* Itbl support may require additional care here. */ |
| 4800 | coproc = 1; |
| 4801 | goto ld; |
| 4802 | case M_LWC2_AB: |
| 4803 | s = "lwc2"; |
| 4804 | /* Itbl support may require additional care here. */ |
| 4805 | coproc = 1; |
| 4806 | goto ld; |
| 4807 | case M_LWC3_AB: |
| 4808 | s = "lwc3"; |
| 4809 | /* Itbl support may require additional care here. */ |
| 4810 | coproc = 1; |
| 4811 | goto ld; |
| 4812 | case M_LWL_AB: |
| 4813 | s = "lwl"; |
| 4814 | lr = 1; |
| 4815 | goto ld; |
| 4816 | case M_LWR_AB: |
| 4817 | s = "lwr"; |
| 4818 | lr = 1; |
| 4819 | goto ld; |
| 4820 | case M_LDC1_AB: |
| 4821 | if (mips_arch == CPU_R4650) |
| 4822 | { |
| 4823 | as_bad (_("opcode not supported on this processor")); |
| 4824 | return; |
| 4825 | } |
| 4826 | s = "ldc1"; |
| 4827 | /* Itbl support may require additional care here. */ |
| 4828 | coproc = 1; |
| 4829 | goto ld; |
| 4830 | case M_LDC2_AB: |
| 4831 | s = "ldc2"; |
| 4832 | /* Itbl support may require additional care here. */ |
| 4833 | coproc = 1; |
| 4834 | goto ld; |
| 4835 | case M_LDC3_AB: |
| 4836 | s = "ldc3"; |
| 4837 | /* Itbl support may require additional care here. */ |
| 4838 | coproc = 1; |
| 4839 | goto ld; |
| 4840 | case M_LDL_AB: |
| 4841 | s = "ldl"; |
| 4842 | lr = 1; |
| 4843 | goto ld; |
| 4844 | case M_LDR_AB: |
| 4845 | s = "ldr"; |
| 4846 | lr = 1; |
| 4847 | goto ld; |
| 4848 | case M_LL_AB: |
| 4849 | s = "ll"; |
| 4850 | goto ld; |
| 4851 | case M_LLD_AB: |
| 4852 | s = "lld"; |
| 4853 | goto ld; |
| 4854 | case M_LWU_AB: |
| 4855 | s = "lwu"; |
| 4856 | ld: |
| 4857 | if (breg == treg || coproc || lr) |
| 4858 | { |
| 4859 | tempreg = AT; |
| 4860 | used_at = 1; |
| 4861 | } |
| 4862 | else |
| 4863 | { |
| 4864 | tempreg = treg; |
| 4865 | used_at = 0; |
| 4866 | } |
| 4867 | goto ld_st; |
| 4868 | case M_SB_AB: |
| 4869 | s = "sb"; |
| 4870 | goto st; |
| 4871 | case M_SH_AB: |
| 4872 | s = "sh"; |
| 4873 | goto st; |
| 4874 | case M_SW_AB: |
| 4875 | s = "sw"; |
| 4876 | goto st; |
| 4877 | case M_SWC0_AB: |
| 4878 | s = "swc0"; |
| 4879 | /* Itbl support may require additional care here. */ |
| 4880 | coproc = 1; |
| 4881 | goto st; |
| 4882 | case M_SWC1_AB: |
| 4883 | s = "swc1"; |
| 4884 | /* Itbl support may require additional care here. */ |
| 4885 | coproc = 1; |
| 4886 | goto st; |
| 4887 | case M_SWC2_AB: |
| 4888 | s = "swc2"; |
| 4889 | /* Itbl support may require additional care here. */ |
| 4890 | coproc = 1; |
| 4891 | goto st; |
| 4892 | case M_SWC3_AB: |
| 4893 | s = "swc3"; |
| 4894 | /* Itbl support may require additional care here. */ |
| 4895 | coproc = 1; |
| 4896 | goto st; |
| 4897 | case M_SWL_AB: |
| 4898 | s = "swl"; |
| 4899 | goto st; |
| 4900 | case M_SWR_AB: |
| 4901 | s = "swr"; |
| 4902 | goto st; |
| 4903 | case M_SC_AB: |
| 4904 | s = "sc"; |
| 4905 | goto st; |
| 4906 | case M_SCD_AB: |
| 4907 | s = "scd"; |
| 4908 | goto st; |
| 4909 | case M_SDC1_AB: |
| 4910 | if (mips_arch == CPU_R4650) |
| 4911 | { |
| 4912 | as_bad (_("opcode not supported on this processor")); |
| 4913 | return; |
| 4914 | } |
| 4915 | s = "sdc1"; |
| 4916 | coproc = 1; |
| 4917 | /* Itbl support may require additional care here. */ |
| 4918 | goto st; |
| 4919 | case M_SDC2_AB: |
| 4920 | s = "sdc2"; |
| 4921 | /* Itbl support may require additional care here. */ |
| 4922 | coproc = 1; |
| 4923 | goto st; |
| 4924 | case M_SDC3_AB: |
| 4925 | s = "sdc3"; |
| 4926 | /* Itbl support may require additional care here. */ |
| 4927 | coproc = 1; |
| 4928 | goto st; |
| 4929 | case M_SDL_AB: |
| 4930 | s = "sdl"; |
| 4931 | goto st; |
| 4932 | case M_SDR_AB: |
| 4933 | s = "sdr"; |
| 4934 | st: |
| 4935 | tempreg = AT; |
| 4936 | used_at = 1; |
| 4937 | ld_st: |
| 4938 | /* Itbl support may require additional care here. */ |
| 4939 | if (mask == M_LWC1_AB |
| 4940 | || mask == M_SWC1_AB |
| 4941 | || mask == M_LDC1_AB |
| 4942 | || mask == M_SDC1_AB |
| 4943 | || mask == M_L_DAB |
| 4944 | || mask == M_S_DAB) |
| 4945 | fmt = "T,o(b)"; |
| 4946 | else if (coproc) |
| 4947 | fmt = "E,o(b)"; |
| 4948 | else |
| 4949 | fmt = "t,o(b)"; |
| 4950 | |
| 4951 | if (offset_expr.X_op != O_constant |
| 4952 | && offset_expr.X_op != O_symbol) |
| 4953 | { |
| 4954 | as_bad (_("expression too complex")); |
| 4955 | offset_expr.X_op = O_constant; |
| 4956 | } |
| 4957 | |
| 4958 | /* A constant expression in PIC code can be handled just as it |
| 4959 | is in non PIC code. */ |
| 4960 | if (mips_pic == NO_PIC |
| 4961 | || offset_expr.X_op == O_constant) |
| 4962 | { |
| 4963 | /* If this is a reference to a GP relative symbol, and there |
| 4964 | is no base register, we want |
| 4965 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) |
| 4966 | Otherwise, if there is no base register, we want |
| 4967 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 4968 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) |
| 4969 | If we have a constant, we need two instructions anyhow, |
| 4970 | so we always use the latter form. |
| 4971 | |
| 4972 | If we have a base register, and this is a reference to a |
| 4973 | GP relative symbol, we want |
| 4974 | addu $tempreg,$breg,$gp |
| 4975 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) |
| 4976 | Otherwise we want |
| 4977 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 4978 | addu $tempreg,$tempreg,$breg |
| 4979 | <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16) |
| 4980 | With a constant we always use the latter case. */ |
| 4981 | if (breg == 0) |
| 4982 | { |
| 4983 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
| 4984 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 4985 | p = NULL; |
| 4986 | else |
| 4987 | { |
| 4988 | frag_grow (20); |
| 4989 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 4990 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); |
| 4991 | p = frag_var (rs_machine_dependent, 8, 0, |
| 4992 | RELAX_ENCODE (4, 8, 0, 4, 0, |
| 4993 | (mips_opts.warn_about_macros |
| 4994 | || (used_at |
| 4995 | && mips_opts.noat))), |
| 4996 | offset_expr.X_add_symbol, (offsetT) 0, |
| 4997 | (char *) NULL); |
| 4998 | used_at = 0; |
| 4999 | } |
| 5000 | macro_build_lui (p, &icnt, &offset_expr, tempreg); |
| 5001 | if (p != NULL) |
| 5002 | p += 4; |
| 5003 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, |
| 5004 | (int) BFD_RELOC_LO16, tempreg); |
| 5005 | } |
| 5006 | else |
| 5007 | { |
| 5008 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
| 5009 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 5010 | p = NULL; |
| 5011 | else |
| 5012 | { |
| 5013 | frag_grow (28); |
| 5014 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5015 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5016 | "d,v,t", tempreg, breg, GP); |
| 5017 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5018 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); |
| 5019 | p = frag_var (rs_machine_dependent, 12, 0, |
| 5020 | RELAX_ENCODE (8, 12, 0, 8, 0, 0), |
| 5021 | offset_expr.X_add_symbol, (offsetT) 0, |
| 5022 | (char *) NULL); |
| 5023 | } |
| 5024 | macro_build_lui (p, &icnt, &offset_expr, tempreg); |
| 5025 | if (p != NULL) |
| 5026 | p += 4; |
| 5027 | macro_build (p, &icnt, (expressionS *) NULL, |
| 5028 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5029 | "d,v,t", tempreg, tempreg, breg); |
| 5030 | if (p != NULL) |
| 5031 | p += 4; |
| 5032 | macro_build (p, &icnt, &offset_expr, s, fmt, treg, |
| 5033 | (int) BFD_RELOC_LO16, tempreg); |
| 5034 | } |
| 5035 | } |
| 5036 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
| 5037 | { |
| 5038 | /* If this is a reference to an external symbol, we want |
| 5039 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5040 | nop |
| 5041 | <op> $treg,0($tempreg) |
| 5042 | Otherwise we want |
| 5043 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5044 | nop |
| 5045 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 5046 | <op> $treg,0($tempreg) |
| 5047 | If there is a base register, we add it to $tempreg before |
| 5048 | the <op>. If there is a constant, we stick it in the |
| 5049 | <op> instruction. We don't handle constants larger than |
| 5050 | 16 bits, because we have no way to load the upper 16 bits |
| 5051 | (actually, we could handle them for the subset of cases |
| 5052 | in which we are not using $at). */ |
| 5053 | assert (offset_expr.X_op == O_symbol); |
| 5054 | expr1.X_add_number = offset_expr.X_add_number; |
| 5055 | offset_expr.X_add_number = 0; |
| 5056 | if (expr1.X_add_number < -0x8000 |
| 5057 | || expr1.X_add_number >= 0x8000) |
| 5058 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 5059 | frag_grow (20); |
| 5060 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5061 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5062 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
| 5063 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
| 5064 | p = frag_var (rs_machine_dependent, 4, 0, |
| 5065 | RELAX_ENCODE (0, 4, -8, 0, 0, 0), |
| 5066 | offset_expr.X_add_symbol, (offsetT) 0, |
| 5067 | (char *) NULL); |
| 5068 | macro_build (p, &icnt, &offset_expr, |
| 5069 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 5070 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 5071 | if (breg != 0) |
| 5072 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5073 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5074 | "d,v,t", tempreg, tempreg, breg); |
| 5075 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
| 5076 | (int) BFD_RELOC_LO16, tempreg); |
| 5077 | } |
| 5078 | else if (mips_pic == SVR4_PIC) |
| 5079 | { |
| 5080 | int gpdel; |
| 5081 | |
| 5082 | /* If this is a reference to an external symbol, we want |
| 5083 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 5084 | addu $tempreg,$tempreg,$gp |
| 5085 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 5086 | <op> $treg,0($tempreg) |
| 5087 | Otherwise we want |
| 5088 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5089 | nop |
| 5090 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 5091 | <op> $treg,0($tempreg) |
| 5092 | If there is a base register, we add it to $tempreg before |
| 5093 | the <op>. If there is a constant, we stick it in the |
| 5094 | <op> instruction. We don't handle constants larger than |
| 5095 | 16 bits, because we have no way to load the upper 16 bits |
| 5096 | (actually, we could handle them for the subset of cases |
| 5097 | in which we are not using $at). */ |
| 5098 | assert (offset_expr.X_op == O_symbol); |
| 5099 | expr1.X_add_number = offset_expr.X_add_number; |
| 5100 | offset_expr.X_add_number = 0; |
| 5101 | if (expr1.X_add_number < -0x8000 |
| 5102 | || expr1.X_add_number >= 0x8000) |
| 5103 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 5104 | if (reg_needs_delay (GP)) |
| 5105 | gpdel = 4; |
| 5106 | else |
| 5107 | gpdel = 0; |
| 5108 | frag_grow (36); |
| 5109 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 5110 | tempreg, (int) BFD_RELOC_MIPS_GOT_HI16); |
| 5111 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5112 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5113 | "d,v,t", tempreg, tempreg, GP); |
| 5114 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5115 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5116 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16, |
| 5117 | tempreg); |
| 5118 | p = frag_var (rs_machine_dependent, 12 + gpdel, 0, |
| 5119 | RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0), |
| 5120 | offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL); |
| 5121 | if (gpdel > 0) |
| 5122 | { |
| 5123 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 5124 | p += 4; |
| 5125 | } |
| 5126 | macro_build (p, &icnt, &offset_expr, |
| 5127 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5128 | "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP); |
| 5129 | p += 4; |
| 5130 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 5131 | p += 4; |
| 5132 | macro_build (p, &icnt, &offset_expr, |
| 5133 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 5134 | "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16); |
| 5135 | if (breg != 0) |
| 5136 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5137 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5138 | "d,v,t", tempreg, tempreg, breg); |
| 5139 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg, |
| 5140 | (int) BFD_RELOC_LO16, tempreg); |
| 5141 | } |
| 5142 | else if (mips_pic == EMBEDDED_PIC) |
| 5143 | { |
| 5144 | /* If there is no base register, we want |
| 5145 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) |
| 5146 | If there is a base register, we want |
| 5147 | addu $tempreg,$breg,$gp |
| 5148 | <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL) |
| 5149 | */ |
| 5150 | assert (offset_expr.X_op == O_symbol); |
| 5151 | if (breg == 0) |
| 5152 | { |
| 5153 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5154 | treg, (int) BFD_RELOC_MIPS_GPREL, GP); |
| 5155 | used_at = 0; |
| 5156 | } |
| 5157 | else |
| 5158 | { |
| 5159 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5160 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5161 | "d,v,t", tempreg, breg, GP); |
| 5162 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5163 | treg, (int) BFD_RELOC_MIPS_GPREL, tempreg); |
| 5164 | } |
| 5165 | } |
| 5166 | else |
| 5167 | abort (); |
| 5168 | |
| 5169 | if (! used_at) |
| 5170 | return; |
| 5171 | |
| 5172 | break; |
| 5173 | |
| 5174 | case M_LI: |
| 5175 | case M_LI_S: |
| 5176 | load_register (&icnt, treg, &imm_expr, 0); |
| 5177 | return; |
| 5178 | |
| 5179 | case M_DLI: |
| 5180 | load_register (&icnt, treg, &imm_expr, 1); |
| 5181 | return; |
| 5182 | |
| 5183 | case M_LI_SS: |
| 5184 | if (imm_expr.X_op == O_constant) |
| 5185 | { |
| 5186 | load_register (&icnt, AT, &imm_expr, 0); |
| 5187 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5188 | "mtc1", "t,G", AT, treg); |
| 5189 | break; |
| 5190 | } |
| 5191 | else |
| 5192 | { |
| 5193 | assert (offset_expr.X_op == O_symbol |
| 5194 | && strcmp (segment_name (S_GET_SEGMENT |
| 5195 | (offset_expr.X_add_symbol)), |
| 5196 | ".lit4") == 0 |
| 5197 | && offset_expr.X_add_number == 0); |
| 5198 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
| 5199 | treg, (int) BFD_RELOC_MIPS_LITERAL, GP); |
| 5200 | return; |
| 5201 | } |
| 5202 | |
| 5203 | case M_LI_D: |
| 5204 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
| 5205 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high |
| 5206 | order 32 bits of the value and the low order 32 bits are either |
| 5207 | zero or in OFFSET_EXPR. */ |
| 5208 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
| 5209 | { |
| 5210 | if (HAVE_64BIT_GPRS) |
| 5211 | load_register (&icnt, treg, &imm_expr, 1); |
| 5212 | else |
| 5213 | { |
| 5214 | int hreg, lreg; |
| 5215 | |
| 5216 | if (target_big_endian) |
| 5217 | { |
| 5218 | hreg = treg; |
| 5219 | lreg = treg + 1; |
| 5220 | } |
| 5221 | else |
| 5222 | { |
| 5223 | hreg = treg + 1; |
| 5224 | lreg = treg; |
| 5225 | } |
| 5226 | |
| 5227 | if (hreg <= 31) |
| 5228 | load_register (&icnt, hreg, &imm_expr, 0); |
| 5229 | if (lreg <= 31) |
| 5230 | { |
| 5231 | if (offset_expr.X_op == O_absent) |
| 5232 | move_register (&icnt, lreg, 0); |
| 5233 | else |
| 5234 | { |
| 5235 | assert (offset_expr.X_op == O_constant); |
| 5236 | load_register (&icnt, lreg, &offset_expr, 0); |
| 5237 | } |
| 5238 | } |
| 5239 | } |
| 5240 | return; |
| 5241 | } |
| 5242 | |
| 5243 | /* We know that sym is in the .rdata section. First we get the |
| 5244 | upper 16 bits of the address. */ |
| 5245 | if (mips_pic == NO_PIC) |
| 5246 | { |
| 5247 | /* FIXME: This won't work for a 64 bit address. */ |
| 5248 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); |
| 5249 | } |
| 5250 | else if (mips_pic == SVR4_PIC) |
| 5251 | { |
| 5252 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5253 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5254 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
| 5255 | } |
| 5256 | else if (mips_pic == EMBEDDED_PIC) |
| 5257 | { |
| 5258 | /* For embedded PIC we pick up the entire address off $gp in |
| 5259 | a single instruction. */ |
| 5260 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5261 | HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu", |
| 5262 | "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL); |
| 5263 | offset_expr.X_op = O_constant; |
| 5264 | offset_expr.X_add_number = 0; |
| 5265 | } |
| 5266 | else |
| 5267 | abort (); |
| 5268 | |
| 5269 | /* Now we load the register(s). */ |
| 5270 | if (HAVE_64BIT_GPRS) |
| 5271 | macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)", |
| 5272 | treg, (int) BFD_RELOC_LO16, AT); |
| 5273 | else |
| 5274 | { |
| 5275 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
| 5276 | treg, (int) BFD_RELOC_LO16, AT); |
| 5277 | if (treg != 31) |
| 5278 | { |
| 5279 | /* FIXME: How in the world do we deal with the possible |
| 5280 | overflow here? */ |
| 5281 | offset_expr.X_add_number += 4; |
| 5282 | macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)", |
| 5283 | treg + 1, (int) BFD_RELOC_LO16, AT); |
| 5284 | } |
| 5285 | } |
| 5286 | |
| 5287 | /* To avoid confusion in tc_gen_reloc, we must ensure that this |
| 5288 | does not become a variant frag. */ |
| 5289 | frag_wane (frag_now); |
| 5290 | frag_new (0); |
| 5291 | |
| 5292 | break; |
| 5293 | |
| 5294 | case M_LI_DD: |
| 5295 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
| 5296 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 |
| 5297 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of |
| 5298 | the value and the low order 32 bits are either zero or in |
| 5299 | OFFSET_EXPR. */ |
| 5300 | if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big) |
| 5301 | { |
| 5302 | load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS); |
| 5303 | if (HAVE_64BIT_FPRS) |
| 5304 | { |
| 5305 | assert (HAVE_64BIT_GPRS); |
| 5306 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5307 | "dmtc1", "t,S", AT, treg); |
| 5308 | } |
| 5309 | else |
| 5310 | { |
| 5311 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5312 | "mtc1", "t,G", AT, treg + 1); |
| 5313 | if (offset_expr.X_op == O_absent) |
| 5314 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5315 | "mtc1", "t,G", 0, treg); |
| 5316 | else |
| 5317 | { |
| 5318 | assert (offset_expr.X_op == O_constant); |
| 5319 | load_register (&icnt, AT, &offset_expr, 0); |
| 5320 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5321 | "mtc1", "t,G", AT, treg); |
| 5322 | } |
| 5323 | } |
| 5324 | break; |
| 5325 | } |
| 5326 | |
| 5327 | assert (offset_expr.X_op == O_symbol |
| 5328 | && offset_expr.X_add_number == 0); |
| 5329 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
| 5330 | if (strcmp (s, ".lit8") == 0) |
| 5331 | { |
| 5332 | if (mips_opts.isa != ISA_MIPS1) |
| 5333 | { |
| 5334 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", |
| 5335 | "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP); |
| 5336 | return; |
| 5337 | } |
| 5338 | breg = GP; |
| 5339 | r = BFD_RELOC_MIPS_LITERAL; |
| 5340 | goto dob; |
| 5341 | } |
| 5342 | else |
| 5343 | { |
| 5344 | assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
| 5345 | if (mips_pic == SVR4_PIC) |
| 5346 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5347 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5348 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
| 5349 | else |
| 5350 | { |
| 5351 | /* FIXME: This won't work for a 64 bit address. */ |
| 5352 | macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT); |
| 5353 | } |
| 5354 | |
| 5355 | if (mips_opts.isa != ISA_MIPS1) |
| 5356 | { |
| 5357 | macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1", |
| 5358 | "T,o(b)", treg, (int) BFD_RELOC_LO16, AT); |
| 5359 | |
| 5360 | /* To avoid confusion in tc_gen_reloc, we must ensure |
| 5361 | that this does not become a variant frag. */ |
| 5362 | frag_wane (frag_now); |
| 5363 | frag_new (0); |
| 5364 | |
| 5365 | break; |
| 5366 | } |
| 5367 | breg = AT; |
| 5368 | r = BFD_RELOC_LO16; |
| 5369 | goto dob; |
| 5370 | } |
| 5371 | |
| 5372 | case M_L_DOB: |
| 5373 | if (mips_arch == CPU_R4650) |
| 5374 | { |
| 5375 | as_bad (_("opcode not supported on this processor")); |
| 5376 | return; |
| 5377 | } |
| 5378 | /* Even on a big endian machine $fn comes before $fn+1. We have |
| 5379 | to adjust when loading from memory. */ |
| 5380 | r = BFD_RELOC_LO16; |
| 5381 | dob: |
| 5382 | assert (mips_opts.isa == ISA_MIPS1); |
| 5383 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
| 5384 | target_big_endian ? treg + 1 : treg, |
| 5385 | (int) r, breg); |
| 5386 | /* FIXME: A possible overflow which I don't know how to deal |
| 5387 | with. */ |
| 5388 | offset_expr.X_add_number += 4; |
| 5389 | macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", |
| 5390 | target_big_endian ? treg : treg + 1, |
| 5391 | (int) r, breg); |
| 5392 | |
| 5393 | /* To avoid confusion in tc_gen_reloc, we must ensure that this |
| 5394 | does not become a variant frag. */ |
| 5395 | frag_wane (frag_now); |
| 5396 | frag_new (0); |
| 5397 | |
| 5398 | if (breg != AT) |
| 5399 | return; |
| 5400 | break; |
| 5401 | |
| 5402 | case M_L_DAB: |
| 5403 | /* |
| 5404 | * The MIPS assembler seems to check for X_add_number not |
| 5405 | * being double aligned and generating: |
| 5406 | * lui at,%hi(foo+1) |
| 5407 | * addu at,at,v1 |
| 5408 | * addiu at,at,%lo(foo+1) |
| 5409 | * lwc1 f2,0(at) |
| 5410 | * lwc1 f3,4(at) |
| 5411 | * But, the resulting address is the same after relocation so why |
| 5412 | * generate the extra instruction? |
| 5413 | */ |
| 5414 | if (mips_arch == CPU_R4650) |
| 5415 | { |
| 5416 | as_bad (_("opcode not supported on this processor")); |
| 5417 | return; |
| 5418 | } |
| 5419 | /* Itbl support may require additional care here. */ |
| 5420 | coproc = 1; |
| 5421 | if (mips_opts.isa != ISA_MIPS1) |
| 5422 | { |
| 5423 | s = "ldc1"; |
| 5424 | goto ld; |
| 5425 | } |
| 5426 | |
| 5427 | s = "lwc1"; |
| 5428 | fmt = "T,o(b)"; |
| 5429 | goto ldd_std; |
| 5430 | |
| 5431 | case M_S_DAB: |
| 5432 | if (mips_arch == CPU_R4650) |
| 5433 | { |
| 5434 | as_bad (_("opcode not supported on this processor")); |
| 5435 | return; |
| 5436 | } |
| 5437 | |
| 5438 | if (mips_opts.isa != ISA_MIPS1) |
| 5439 | { |
| 5440 | s = "sdc1"; |
| 5441 | goto st; |
| 5442 | } |
| 5443 | |
| 5444 | s = "swc1"; |
| 5445 | fmt = "T,o(b)"; |
| 5446 | /* Itbl support may require additional care here. */ |
| 5447 | coproc = 1; |
| 5448 | goto ldd_std; |
| 5449 | |
| 5450 | case M_LD_AB: |
| 5451 | if (HAVE_64BIT_GPRS) |
| 5452 | { |
| 5453 | s = "ld"; |
| 5454 | goto ld; |
| 5455 | } |
| 5456 | |
| 5457 | s = "lw"; |
| 5458 | fmt = "t,o(b)"; |
| 5459 | goto ldd_std; |
| 5460 | |
| 5461 | case M_SD_AB: |
| 5462 | if (HAVE_64BIT_GPRS) |
| 5463 | { |
| 5464 | s = "sd"; |
| 5465 | goto st; |
| 5466 | } |
| 5467 | |
| 5468 | s = "sw"; |
| 5469 | fmt = "t,o(b)"; |
| 5470 | |
| 5471 | ldd_std: |
| 5472 | if (offset_expr.X_op != O_symbol |
| 5473 | && offset_expr.X_op != O_constant) |
| 5474 | { |
| 5475 | as_bad (_("expression too complex")); |
| 5476 | offset_expr.X_op = O_constant; |
| 5477 | } |
| 5478 | |
| 5479 | /* Even on a big endian machine $fn comes before $fn+1. We have |
| 5480 | to adjust when loading from memory. We set coproc if we must |
| 5481 | load $fn+1 first. */ |
| 5482 | /* Itbl support may require additional care here. */ |
| 5483 | if (! target_big_endian) |
| 5484 | coproc = 0; |
| 5485 | |
| 5486 | if (mips_pic == NO_PIC |
| 5487 | || offset_expr.X_op == O_constant) |
| 5488 | { |
| 5489 | /* If this is a reference to a GP relative symbol, we want |
| 5490 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) |
| 5491 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) |
| 5492 | If we have a base register, we use this |
| 5493 | addu $at,$breg,$gp |
| 5494 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) |
| 5495 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) |
| 5496 | If this is not a GP relative symbol, we want |
| 5497 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 5498 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) |
| 5499 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) |
| 5500 | If there is a base register, we add it to $at after the |
| 5501 | lui instruction. If there is a constant, we always use |
| 5502 | the last case. */ |
| 5503 | if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET |
| 5504 | || nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 5505 | { |
| 5506 | p = NULL; |
| 5507 | used_at = 1; |
| 5508 | } |
| 5509 | else |
| 5510 | { |
| 5511 | int off; |
| 5512 | |
| 5513 | if (breg == 0) |
| 5514 | { |
| 5515 | frag_grow (28); |
| 5516 | tempreg = GP; |
| 5517 | off = 0; |
| 5518 | used_at = 0; |
| 5519 | } |
| 5520 | else |
| 5521 | { |
| 5522 | frag_grow (36); |
| 5523 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5524 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5525 | "d,v,t", AT, breg, GP); |
| 5526 | tempreg = AT; |
| 5527 | off = 4; |
| 5528 | used_at = 1; |
| 5529 | } |
| 5530 | |
| 5531 | /* Itbl support may require additional care here. */ |
| 5532 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5533 | coproc ? treg + 1 : treg, |
| 5534 | (int) BFD_RELOC_MIPS_GPREL, tempreg); |
| 5535 | offset_expr.X_add_number += 4; |
| 5536 | |
| 5537 | /* Set mips_optimize to 2 to avoid inserting an |
| 5538 | undesired nop. */ |
| 5539 | hold_mips_optimize = mips_optimize; |
| 5540 | mips_optimize = 2; |
| 5541 | /* Itbl support may require additional care here. */ |
| 5542 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5543 | coproc ? treg : treg + 1, |
| 5544 | (int) BFD_RELOC_MIPS_GPREL, tempreg); |
| 5545 | mips_optimize = hold_mips_optimize; |
| 5546 | |
| 5547 | p = frag_var (rs_machine_dependent, 12 + off, 0, |
| 5548 | RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1, |
| 5549 | used_at && mips_opts.noat), |
| 5550 | offset_expr.X_add_symbol, (offsetT) 0, |
| 5551 | (char *) NULL); |
| 5552 | |
| 5553 | /* We just generated two relocs. When tc_gen_reloc |
| 5554 | handles this case, it will skip the first reloc and |
| 5555 | handle the second. The second reloc already has an |
| 5556 | extra addend of 4, which we added above. We must |
| 5557 | subtract it out, and then subtract another 4 to make |
| 5558 | the first reloc come out right. The second reloc |
| 5559 | will come out right because we are going to add 4 to |
| 5560 | offset_expr when we build its instruction below. |
| 5561 | |
| 5562 | If we have a symbol, then we don't want to include |
| 5563 | the offset, because it will wind up being included |
| 5564 | when we generate the reloc. */ |
| 5565 | |
| 5566 | if (offset_expr.X_op == O_constant) |
| 5567 | offset_expr.X_add_number -= 8; |
| 5568 | else |
| 5569 | { |
| 5570 | offset_expr.X_add_number = -4; |
| 5571 | offset_expr.X_op = O_constant; |
| 5572 | } |
| 5573 | } |
| 5574 | macro_build_lui (p, &icnt, &offset_expr, AT); |
| 5575 | if (p != NULL) |
| 5576 | p += 4; |
| 5577 | if (breg != 0) |
| 5578 | { |
| 5579 | macro_build (p, &icnt, (expressionS *) NULL, |
| 5580 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5581 | "d,v,t", AT, breg, AT); |
| 5582 | if (p != NULL) |
| 5583 | p += 4; |
| 5584 | } |
| 5585 | /* Itbl support may require additional care here. */ |
| 5586 | macro_build (p, &icnt, &offset_expr, s, fmt, |
| 5587 | coproc ? treg + 1 : treg, |
| 5588 | (int) BFD_RELOC_LO16, AT); |
| 5589 | if (p != NULL) |
| 5590 | p += 4; |
| 5591 | /* FIXME: How do we handle overflow here? */ |
| 5592 | offset_expr.X_add_number += 4; |
| 5593 | /* Itbl support may require additional care here. */ |
| 5594 | macro_build (p, &icnt, &offset_expr, s, fmt, |
| 5595 | coproc ? treg : treg + 1, |
| 5596 | (int) BFD_RELOC_LO16, AT); |
| 5597 | } |
| 5598 | else if (mips_pic == SVR4_PIC && ! mips_big_got) |
| 5599 | { |
| 5600 | int off; |
| 5601 | |
| 5602 | /* If this is a reference to an external symbol, we want |
| 5603 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5604 | nop |
| 5605 | <op> $treg,0($at) |
| 5606 | <op> $treg+1,4($at) |
| 5607 | Otherwise we want |
| 5608 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5609 | nop |
| 5610 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) |
| 5611 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) |
| 5612 | If there is a base register we add it to $at before the |
| 5613 | lwc1 instructions. If there is a constant we include it |
| 5614 | in the lwc1 instructions. */ |
| 5615 | used_at = 1; |
| 5616 | expr1.X_add_number = offset_expr.X_add_number; |
| 5617 | offset_expr.X_add_number = 0; |
| 5618 | if (expr1.X_add_number < -0x8000 |
| 5619 | || expr1.X_add_number >= 0x8000 - 4) |
| 5620 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 5621 | if (breg == 0) |
| 5622 | off = 0; |
| 5623 | else |
| 5624 | off = 4; |
| 5625 | frag_grow (24 + off); |
| 5626 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5627 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5628 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
| 5629 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
| 5630 | if (breg != 0) |
| 5631 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5632 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5633 | "d,v,t", AT, breg, AT); |
| 5634 | /* Itbl support may require additional care here. */ |
| 5635 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
| 5636 | coproc ? treg + 1 : treg, |
| 5637 | (int) BFD_RELOC_LO16, AT); |
| 5638 | expr1.X_add_number += 4; |
| 5639 | |
| 5640 | /* Set mips_optimize to 2 to avoid inserting an undesired |
| 5641 | nop. */ |
| 5642 | hold_mips_optimize = mips_optimize; |
| 5643 | mips_optimize = 2; |
| 5644 | /* Itbl support may require additional care here. */ |
| 5645 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
| 5646 | coproc ? treg : treg + 1, |
| 5647 | (int) BFD_RELOC_LO16, AT); |
| 5648 | mips_optimize = hold_mips_optimize; |
| 5649 | |
| 5650 | (void) frag_var (rs_machine_dependent, 0, 0, |
| 5651 | RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0), |
| 5652 | offset_expr.X_add_symbol, (offsetT) 0, |
| 5653 | (char *) NULL); |
| 5654 | } |
| 5655 | else if (mips_pic == SVR4_PIC) |
| 5656 | { |
| 5657 | int gpdel, off; |
| 5658 | |
| 5659 | /* If this is a reference to an external symbol, we want |
| 5660 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 5661 | addu $at,$at,$gp |
| 5662 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) |
| 5663 | nop |
| 5664 | <op> $treg,0($at) |
| 5665 | <op> $treg+1,4($at) |
| 5666 | Otherwise we want |
| 5667 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 5668 | nop |
| 5669 | <op> $treg,<sym>($at) (BFD_RELOC_LO16) |
| 5670 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16) |
| 5671 | If there is a base register we add it to $at before the |
| 5672 | lwc1 instructions. If there is a constant we include it |
| 5673 | in the lwc1 instructions. */ |
| 5674 | used_at = 1; |
| 5675 | expr1.X_add_number = offset_expr.X_add_number; |
| 5676 | offset_expr.X_add_number = 0; |
| 5677 | if (expr1.X_add_number < -0x8000 |
| 5678 | || expr1.X_add_number >= 0x8000 - 4) |
| 5679 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 5680 | if (reg_needs_delay (GP)) |
| 5681 | gpdel = 4; |
| 5682 | else |
| 5683 | gpdel = 0; |
| 5684 | if (breg == 0) |
| 5685 | off = 0; |
| 5686 | else |
| 5687 | off = 4; |
| 5688 | frag_grow (56); |
| 5689 | macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u", |
| 5690 | AT, (int) BFD_RELOC_MIPS_GOT_HI16); |
| 5691 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5692 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5693 | "d,v,t", AT, AT, GP); |
| 5694 | macro_build ((char *) NULL, &icnt, &offset_expr, |
| 5695 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5696 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT); |
| 5697 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", ""); |
| 5698 | if (breg != 0) |
| 5699 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5700 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5701 | "d,v,t", AT, breg, AT); |
| 5702 | /* Itbl support may require additional care here. */ |
| 5703 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
| 5704 | coproc ? treg + 1 : treg, |
| 5705 | (int) BFD_RELOC_LO16, AT); |
| 5706 | expr1.X_add_number += 4; |
| 5707 | |
| 5708 | /* Set mips_optimize to 2 to avoid inserting an undesired |
| 5709 | nop. */ |
| 5710 | hold_mips_optimize = mips_optimize; |
| 5711 | mips_optimize = 2; |
| 5712 | /* Itbl support may require additional care here. */ |
| 5713 | macro_build ((char *) NULL, &icnt, &expr1, s, fmt, |
| 5714 | coproc ? treg : treg + 1, |
| 5715 | (int) BFD_RELOC_LO16, AT); |
| 5716 | mips_optimize = hold_mips_optimize; |
| 5717 | expr1.X_add_number -= 4; |
| 5718 | |
| 5719 | p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0, |
| 5720 | RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel, |
| 5721 | 8 + gpdel + off, 1, 0), |
| 5722 | offset_expr.X_add_symbol, (offsetT) 0, |
| 5723 | (char *) NULL); |
| 5724 | if (gpdel > 0) |
| 5725 | { |
| 5726 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 5727 | p += 4; |
| 5728 | } |
| 5729 | macro_build (p, &icnt, &offset_expr, |
| 5730 | HAVE_32BIT_ADDRESSES ? "lw" : "ld", |
| 5731 | "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP); |
| 5732 | p += 4; |
| 5733 | macro_build (p, &icnt, (expressionS *) NULL, "nop", ""); |
| 5734 | p += 4; |
| 5735 | if (breg != 0) |
| 5736 | { |
| 5737 | macro_build (p, &icnt, (expressionS *) NULL, |
| 5738 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5739 | "d,v,t", AT, breg, AT); |
| 5740 | p += 4; |
| 5741 | } |
| 5742 | /* Itbl support may require additional care here. */ |
| 5743 | macro_build (p, &icnt, &expr1, s, fmt, |
| 5744 | coproc ? treg + 1 : treg, |
| 5745 | (int) BFD_RELOC_LO16, AT); |
| 5746 | p += 4; |
| 5747 | expr1.X_add_number += 4; |
| 5748 | |
| 5749 | /* Set mips_optimize to 2 to avoid inserting an undesired |
| 5750 | nop. */ |
| 5751 | hold_mips_optimize = mips_optimize; |
| 5752 | mips_optimize = 2; |
| 5753 | /* Itbl support may require additional care here. */ |
| 5754 | macro_build (p, &icnt, &expr1, s, fmt, |
| 5755 | coproc ? treg : treg + 1, |
| 5756 | (int) BFD_RELOC_LO16, AT); |
| 5757 | mips_optimize = hold_mips_optimize; |
| 5758 | } |
| 5759 | else if (mips_pic == EMBEDDED_PIC) |
| 5760 | { |
| 5761 | /* If there is no base register, we use |
| 5762 | <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL) |
| 5763 | <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL) |
| 5764 | If we have a base register, we use |
| 5765 | addu $at,$breg,$gp |
| 5766 | <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL) |
| 5767 | <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL) |
| 5768 | */ |
| 5769 | if (breg == 0) |
| 5770 | { |
| 5771 | tempreg = GP; |
| 5772 | used_at = 0; |
| 5773 | } |
| 5774 | else |
| 5775 | { |
| 5776 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 5777 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 5778 | "d,v,t", AT, breg, GP); |
| 5779 | tempreg = AT; |
| 5780 | used_at = 1; |
| 5781 | } |
| 5782 | |
| 5783 | /* Itbl support may require additional care here. */ |
| 5784 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5785 | coproc ? treg + 1 : treg, |
| 5786 | (int) BFD_RELOC_MIPS_GPREL, tempreg); |
| 5787 | offset_expr.X_add_number += 4; |
| 5788 | /* Itbl support may require additional care here. */ |
| 5789 | macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, |
| 5790 | coproc ? treg : treg + 1, |
| 5791 | (int) BFD_RELOC_MIPS_GPREL, tempreg); |
| 5792 | } |
| 5793 | else |
| 5794 | abort (); |
| 5795 | |
| 5796 | if (! used_at) |
| 5797 | return; |
| 5798 | |
| 5799 | break; |
| 5800 | |
| 5801 | case M_LD_OB: |
| 5802 | s = "lw"; |
| 5803 | goto sd_ob; |
| 5804 | case M_SD_OB: |
| 5805 | s = "sw"; |
| 5806 | sd_ob: |
| 5807 | assert (HAVE_32BIT_ADDRESSES); |
| 5808 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
| 5809 | (int) BFD_RELOC_LO16, breg); |
| 5810 | offset_expr.X_add_number += 4; |
| 5811 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1, |
| 5812 | (int) BFD_RELOC_LO16, breg); |
| 5813 | return; |
| 5814 | |
| 5815 | /* New code added to support COPZ instructions. |
| 5816 | This code builds table entries out of the macros in mip_opcodes. |
| 5817 | R4000 uses interlocks to handle coproc delays. |
| 5818 | Other chips (like the R3000) require nops to be inserted for delays. |
| 5819 | |
| 5820 | FIXME: Currently, we require that the user handle delays. |
| 5821 | In order to fill delay slots for non-interlocked chips, |
| 5822 | we must have a way to specify delays based on the coprocessor. |
| 5823 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. |
| 5824 | What are the side-effects of the cop instruction? |
| 5825 | What cache support might we have and what are its effects? |
| 5826 | Both coprocessor & memory require delays. how long??? |
| 5827 | What registers are read/set/modified? |
| 5828 | |
| 5829 | If an itbl is provided to interpret cop instructions, |
| 5830 | this knowledge can be encoded in the itbl spec. */ |
| 5831 | |
| 5832 | case M_COP0: |
| 5833 | s = "c0"; |
| 5834 | goto copz; |
| 5835 | case M_COP1: |
| 5836 | s = "c1"; |
| 5837 | goto copz; |
| 5838 | case M_COP2: |
| 5839 | s = "c2"; |
| 5840 | goto copz; |
| 5841 | case M_COP3: |
| 5842 | s = "c3"; |
| 5843 | copz: |
| 5844 | /* For now we just do C (same as Cz). The parameter will be |
| 5845 | stored in insn_opcode by mips_ip. */ |
| 5846 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C", |
| 5847 | ip->insn_opcode); |
| 5848 | return; |
| 5849 | |
| 5850 | case M_MOVE: |
| 5851 | move_register (&icnt, dreg, sreg); |
| 5852 | return; |
| 5853 | |
| 5854 | #ifdef LOSING_COMPILER |
| 5855 | default: |
| 5856 | /* Try and see if this is a new itbl instruction. |
| 5857 | This code builds table entries out of the macros in mip_opcodes. |
| 5858 | FIXME: For now we just assemble the expression and pass it's |
| 5859 | value along as a 32-bit immediate. |
| 5860 | We may want to have the assembler assemble this value, |
| 5861 | so that we gain the assembler's knowledge of delay slots, |
| 5862 | symbols, etc. |
| 5863 | Would it be more efficient to use mask (id) here? */ |
| 5864 | if (itbl_have_entries |
| 5865 | && (immed_expr = itbl_assemble (ip->insn_mo->name, ""))) |
| 5866 | { |
| 5867 | s = ip->insn_mo->name; |
| 5868 | s2 = "cop3"; |
| 5869 | coproc = ITBL_DECODE_PNUM (immed_expr);; |
| 5870 | macro_build ((char *) NULL, &icnt, &immed_expr, s, "C"); |
| 5871 | return; |
| 5872 | } |
| 5873 | macro2 (ip); |
| 5874 | return; |
| 5875 | } |
| 5876 | if (mips_opts.noat) |
| 5877 | as_warn (_("Macro used $at after \".set noat\"")); |
| 5878 | } |
| 5879 | |
| 5880 | static void |
| 5881 | macro2 (ip) |
| 5882 | struct mips_cl_insn *ip; |
| 5883 | { |
| 5884 | register int treg, sreg, dreg, breg; |
| 5885 | int tempreg; |
| 5886 | int mask; |
| 5887 | int icnt = 0; |
| 5888 | int used_at; |
| 5889 | expressionS expr1; |
| 5890 | const char *s; |
| 5891 | const char *s2; |
| 5892 | const char *fmt; |
| 5893 | int likely = 0; |
| 5894 | int dbl = 0; |
| 5895 | int coproc = 0; |
| 5896 | int lr = 0; |
| 5897 | int imm = 0; |
| 5898 | int off; |
| 5899 | offsetT maxnum; |
| 5900 | bfd_reloc_code_real_type r; |
| 5901 | char *p; |
| 5902 | |
| 5903 | treg = (ip->insn_opcode >> 16) & 0x1f; |
| 5904 | dreg = (ip->insn_opcode >> 11) & 0x1f; |
| 5905 | sreg = breg = (ip->insn_opcode >> 21) & 0x1f; |
| 5906 | mask = ip->insn_mo->mask; |
| 5907 | |
| 5908 | expr1.X_op = O_constant; |
| 5909 | expr1.X_op_symbol = NULL; |
| 5910 | expr1.X_add_symbol = NULL; |
| 5911 | expr1.X_add_number = 1; |
| 5912 | |
| 5913 | switch (mask) |
| 5914 | { |
| 5915 | #endif /* LOSING_COMPILER */ |
| 5916 | |
| 5917 | case M_DMUL: |
| 5918 | dbl = 1; |
| 5919 | case M_MUL: |
| 5920 | macro_build ((char *) NULL, &icnt, NULL, |
| 5921 | dbl ? "dmultu" : "multu", |
| 5922 | "s,t", sreg, treg); |
| 5923 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
| 5924 | return; |
| 5925 | |
| 5926 | case M_DMUL_I: |
| 5927 | dbl = 1; |
| 5928 | case M_MUL_I: |
| 5929 | /* The MIPS assembler some times generates shifts and adds. I'm |
| 5930 | not trying to be that fancy. GCC should do this for us |
| 5931 | anyway. */ |
| 5932 | load_register (&icnt, AT, &imm_expr, dbl); |
| 5933 | macro_build ((char *) NULL, &icnt, NULL, |
| 5934 | dbl ? "dmult" : "mult", "s,t", sreg, AT); |
| 5935 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
| 5936 | break; |
| 5937 | |
| 5938 | case M_DMULO_I: |
| 5939 | dbl = 1; |
| 5940 | case M_MULO_I: |
| 5941 | imm = 1; |
| 5942 | goto do_mulo; |
| 5943 | |
| 5944 | case M_DMULO: |
| 5945 | dbl = 1; |
| 5946 | case M_MULO: |
| 5947 | do_mulo: |
| 5948 | mips_emit_delays (true); |
| 5949 | ++mips_opts.noreorder; |
| 5950 | mips_any_noreorder = 1; |
| 5951 | if (imm) |
| 5952 | load_register (&icnt, AT, &imm_expr, dbl); |
| 5953 | macro_build ((char *) NULL, &icnt, NULL, |
| 5954 | dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg); |
| 5955 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
| 5956 | macro_build ((char *) NULL, &icnt, NULL, |
| 5957 | dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, 31); |
| 5958 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
| 5959 | if (mips_trap) |
| 5960 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT); |
| 5961 | else |
| 5962 | { |
| 5963 | expr1.X_add_number = 8; |
| 5964 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT); |
| 5965 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
| 5966 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
| 5967 | } |
| 5968 | --mips_opts.noreorder; |
| 5969 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
| 5970 | break; |
| 5971 | |
| 5972 | case M_DMULOU_I: |
| 5973 | dbl = 1; |
| 5974 | case M_MULOU_I: |
| 5975 | imm = 1; |
| 5976 | goto do_mulou; |
| 5977 | |
| 5978 | case M_DMULOU: |
| 5979 | dbl = 1; |
| 5980 | case M_MULOU: |
| 5981 | do_mulou: |
| 5982 | mips_emit_delays (true); |
| 5983 | ++mips_opts.noreorder; |
| 5984 | mips_any_noreorder = 1; |
| 5985 | if (imm) |
| 5986 | load_register (&icnt, AT, &imm_expr, dbl); |
| 5987 | macro_build ((char *) NULL, &icnt, NULL, |
| 5988 | dbl ? "dmultu" : "multu", |
| 5989 | "s,t", sreg, imm ? AT : treg); |
| 5990 | macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT); |
| 5991 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg); |
| 5992 | if (mips_trap) |
| 5993 | macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0); |
| 5994 | else |
| 5995 | { |
| 5996 | expr1.X_add_number = 8; |
| 5997 | macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0); |
| 5998 | macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0); |
| 5999 | macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6); |
| 6000 | } |
| 6001 | --mips_opts.noreorder; |
| 6002 | break; |
| 6003 | |
| 6004 | case M_ROL: |
| 6005 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
| 6006 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT); |
| 6007 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, |
| 6008 | treg); |
| 6009 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
| 6010 | break; |
| 6011 | |
| 6012 | case M_ROL_I: |
| 6013 | if (imm_expr.X_op != O_constant) |
| 6014 | as_bad (_("rotate count too large")); |
| 6015 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, |
| 6016 | (int) (imm_expr.X_add_number & 0x1f)); |
| 6017 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, |
| 6018 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
| 6019 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
| 6020 | break; |
| 6021 | |
| 6022 | case M_ROR: |
| 6023 | macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg); |
| 6024 | macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT); |
| 6025 | macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, |
| 6026 | treg); |
| 6027 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
| 6028 | break; |
| 6029 | |
| 6030 | case M_ROR_I: |
| 6031 | if (imm_expr.X_op != O_constant) |
| 6032 | as_bad (_("rotate count too large")); |
| 6033 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, |
| 6034 | (int) (imm_expr.X_add_number & 0x1f)); |
| 6035 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg, |
| 6036 | (int) ((0 - imm_expr.X_add_number) & 0x1f)); |
| 6037 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT); |
| 6038 | break; |
| 6039 | |
| 6040 | case M_S_DOB: |
| 6041 | if (mips_arch == CPU_R4650) |
| 6042 | { |
| 6043 | as_bad (_("opcode not supported on this processor")); |
| 6044 | return; |
| 6045 | } |
| 6046 | assert (mips_opts.isa == ISA_MIPS1); |
| 6047 | /* Even on a big endian machine $fn comes before $fn+1. We have |
| 6048 | to adjust when storing to memory. */ |
| 6049 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
| 6050 | target_big_endian ? treg + 1 : treg, |
| 6051 | (int) BFD_RELOC_LO16, breg); |
| 6052 | offset_expr.X_add_number += 4; |
| 6053 | macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)", |
| 6054 | target_big_endian ? treg : treg + 1, |
| 6055 | (int) BFD_RELOC_LO16, breg); |
| 6056 | return; |
| 6057 | |
| 6058 | case M_SEQ: |
| 6059 | if (sreg == 0) |
| 6060 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
| 6061 | treg, (int) BFD_RELOC_LO16); |
| 6062 | else if (treg == 0) |
| 6063 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
| 6064 | sreg, (int) BFD_RELOC_LO16); |
| 6065 | else |
| 6066 | { |
| 6067 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
| 6068 | sreg, treg); |
| 6069 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
| 6070 | dreg, (int) BFD_RELOC_LO16); |
| 6071 | } |
| 6072 | return; |
| 6073 | |
| 6074 | case M_SEQ_I: |
| 6075 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 6076 | { |
| 6077 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, |
| 6078 | sreg, (int) BFD_RELOC_LO16); |
| 6079 | return; |
| 6080 | } |
| 6081 | if (sreg == 0) |
| 6082 | { |
| 6083 | as_warn (_("Instruction %s: result is always false"), |
| 6084 | ip->insn_mo->name); |
| 6085 | move_register (&icnt, dreg, 0); |
| 6086 | return; |
| 6087 | } |
| 6088 | if (imm_expr.X_op == O_constant |
| 6089 | && imm_expr.X_add_number >= 0 |
| 6090 | && imm_expr.X_add_number < 0x10000) |
| 6091 | { |
| 6092 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, |
| 6093 | sreg, (int) BFD_RELOC_LO16); |
| 6094 | used_at = 0; |
| 6095 | } |
| 6096 | else if (imm_expr.X_op == O_constant |
| 6097 | && imm_expr.X_add_number > -0x8000 |
| 6098 | && imm_expr.X_add_number < 0) |
| 6099 | { |
| 6100 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6101 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 6102 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
| 6103 | "t,r,j", dreg, sreg, |
| 6104 | (int) BFD_RELOC_LO16); |
| 6105 | used_at = 0; |
| 6106 | } |
| 6107 | else |
| 6108 | { |
| 6109 | load_register (&icnt, AT, &imm_expr, 0); |
| 6110 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
| 6111 | sreg, AT); |
| 6112 | used_at = 1; |
| 6113 | } |
| 6114 | macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg, |
| 6115 | (int) BFD_RELOC_LO16); |
| 6116 | if (used_at) |
| 6117 | break; |
| 6118 | return; |
| 6119 | |
| 6120 | case M_SGE: /* sreg >= treg <==> not (sreg < treg) */ |
| 6121 | s = "slt"; |
| 6122 | goto sge; |
| 6123 | case M_SGEU: |
| 6124 | s = "sltu"; |
| 6125 | sge: |
| 6126 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg); |
| 6127 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
| 6128 | (int) BFD_RELOC_LO16); |
| 6129 | return; |
| 6130 | |
| 6131 | case M_SGE_I: /* sreg >= I <==> not (sreg < I) */ |
| 6132 | case M_SGEU_I: |
| 6133 | if (imm_expr.X_op == O_constant |
| 6134 | && imm_expr.X_add_number >= -0x8000 |
| 6135 | && imm_expr.X_add_number < 0x8000) |
| 6136 | { |
| 6137 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 6138 | mask == M_SGE_I ? "slti" : "sltiu", |
| 6139 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
| 6140 | used_at = 0; |
| 6141 | } |
| 6142 | else |
| 6143 | { |
| 6144 | load_register (&icnt, AT, &imm_expr, 0); |
| 6145 | macro_build ((char *) NULL, &icnt, NULL, |
| 6146 | mask == M_SGE_I ? "slt" : "sltu", |
| 6147 | "d,v,t", dreg, sreg, AT); |
| 6148 | used_at = 1; |
| 6149 | } |
| 6150 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
| 6151 | (int) BFD_RELOC_LO16); |
| 6152 | if (used_at) |
| 6153 | break; |
| 6154 | return; |
| 6155 | |
| 6156 | case M_SGT: /* sreg > treg <==> treg < sreg */ |
| 6157 | s = "slt"; |
| 6158 | goto sgt; |
| 6159 | case M_SGTU: |
| 6160 | s = "sltu"; |
| 6161 | sgt: |
| 6162 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
| 6163 | return; |
| 6164 | |
| 6165 | case M_SGT_I: /* sreg > I <==> I < sreg */ |
| 6166 | s = "slt"; |
| 6167 | goto sgti; |
| 6168 | case M_SGTU_I: |
| 6169 | s = "sltu"; |
| 6170 | sgti: |
| 6171 | load_register (&icnt, AT, &imm_expr, 0); |
| 6172 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
| 6173 | break; |
| 6174 | |
| 6175 | case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */ |
| 6176 | s = "slt"; |
| 6177 | goto sle; |
| 6178 | case M_SLEU: |
| 6179 | s = "sltu"; |
| 6180 | sle: |
| 6181 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg); |
| 6182 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
| 6183 | (int) BFD_RELOC_LO16); |
| 6184 | return; |
| 6185 | |
| 6186 | case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */ |
| 6187 | s = "slt"; |
| 6188 | goto slei; |
| 6189 | case M_SLEU_I: |
| 6190 | s = "sltu"; |
| 6191 | slei: |
| 6192 | load_register (&icnt, AT, &imm_expr, 0); |
| 6193 | macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg); |
| 6194 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg, |
| 6195 | (int) BFD_RELOC_LO16); |
| 6196 | break; |
| 6197 | |
| 6198 | case M_SLT_I: |
| 6199 | if (imm_expr.X_op == O_constant |
| 6200 | && imm_expr.X_add_number >= -0x8000 |
| 6201 | && imm_expr.X_add_number < 0x8000) |
| 6202 | { |
| 6203 | macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j", |
| 6204 | dreg, sreg, (int) BFD_RELOC_LO16); |
| 6205 | return; |
| 6206 | } |
| 6207 | load_register (&icnt, AT, &imm_expr, 0); |
| 6208 | macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT); |
| 6209 | break; |
| 6210 | |
| 6211 | case M_SLTU_I: |
| 6212 | if (imm_expr.X_op == O_constant |
| 6213 | && imm_expr.X_add_number >= -0x8000 |
| 6214 | && imm_expr.X_add_number < 0x8000) |
| 6215 | { |
| 6216 | macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j", |
| 6217 | dreg, sreg, (int) BFD_RELOC_LO16); |
| 6218 | return; |
| 6219 | } |
| 6220 | load_register (&icnt, AT, &imm_expr, 0); |
| 6221 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, |
| 6222 | AT); |
| 6223 | break; |
| 6224 | |
| 6225 | case M_SNE: |
| 6226 | if (sreg == 0) |
| 6227 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
| 6228 | treg); |
| 6229 | else if (treg == 0) |
| 6230 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
| 6231 | sreg); |
| 6232 | else |
| 6233 | { |
| 6234 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
| 6235 | sreg, treg); |
| 6236 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
| 6237 | dreg); |
| 6238 | } |
| 6239 | return; |
| 6240 | |
| 6241 | case M_SNE_I: |
| 6242 | if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0) |
| 6243 | { |
| 6244 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, |
| 6245 | sreg); |
| 6246 | return; |
| 6247 | } |
| 6248 | if (sreg == 0) |
| 6249 | { |
| 6250 | as_warn (_("Instruction %s: result is always true"), |
| 6251 | ip->insn_mo->name); |
| 6252 | macro_build ((char *) NULL, &icnt, &expr1, |
| 6253 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
| 6254 | "t,r,j", dreg, 0, (int) BFD_RELOC_LO16); |
| 6255 | return; |
| 6256 | } |
| 6257 | if (imm_expr.X_op == O_constant |
| 6258 | && imm_expr.X_add_number >= 0 |
| 6259 | && imm_expr.X_add_number < 0x10000) |
| 6260 | { |
| 6261 | macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", |
| 6262 | dreg, sreg, (int) BFD_RELOC_LO16); |
| 6263 | used_at = 0; |
| 6264 | } |
| 6265 | else if (imm_expr.X_op == O_constant |
| 6266 | && imm_expr.X_add_number > -0x8000 |
| 6267 | && imm_expr.X_add_number < 0) |
| 6268 | { |
| 6269 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6270 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 6271 | HAVE_32BIT_GPRS ? "addiu" : "daddiu", |
| 6272 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
| 6273 | used_at = 0; |
| 6274 | } |
| 6275 | else |
| 6276 | { |
| 6277 | load_register (&icnt, AT, &imm_expr, 0); |
| 6278 | macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg, |
| 6279 | sreg, AT); |
| 6280 | used_at = 1; |
| 6281 | } |
| 6282 | macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg); |
| 6283 | if (used_at) |
| 6284 | break; |
| 6285 | return; |
| 6286 | |
| 6287 | case M_DSUB_I: |
| 6288 | dbl = 1; |
| 6289 | case M_SUB_I: |
| 6290 | if (imm_expr.X_op == O_constant |
| 6291 | && imm_expr.X_add_number > -0x8000 |
| 6292 | && imm_expr.X_add_number <= 0x8000) |
| 6293 | { |
| 6294 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6295 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 6296 | dbl ? "daddi" : "addi", |
| 6297 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
| 6298 | return; |
| 6299 | } |
| 6300 | load_register (&icnt, AT, &imm_expr, dbl); |
| 6301 | macro_build ((char *) NULL, &icnt, NULL, |
| 6302 | dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT); |
| 6303 | break; |
| 6304 | |
| 6305 | case M_DSUBU_I: |
| 6306 | dbl = 1; |
| 6307 | case M_SUBU_I: |
| 6308 | if (imm_expr.X_op == O_constant |
| 6309 | && imm_expr.X_add_number > -0x8000 |
| 6310 | && imm_expr.X_add_number <= 0x8000) |
| 6311 | { |
| 6312 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6313 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 6314 | dbl ? "daddiu" : "addiu", |
| 6315 | "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16); |
| 6316 | return; |
| 6317 | } |
| 6318 | load_register (&icnt, AT, &imm_expr, dbl); |
| 6319 | macro_build ((char *) NULL, &icnt, NULL, |
| 6320 | dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT); |
| 6321 | break; |
| 6322 | |
| 6323 | case M_TEQ_I: |
| 6324 | s = "teq"; |
| 6325 | goto trap; |
| 6326 | case M_TGE_I: |
| 6327 | s = "tge"; |
| 6328 | goto trap; |
| 6329 | case M_TGEU_I: |
| 6330 | s = "tgeu"; |
| 6331 | goto trap; |
| 6332 | case M_TLT_I: |
| 6333 | s = "tlt"; |
| 6334 | goto trap; |
| 6335 | case M_TLTU_I: |
| 6336 | s = "tltu"; |
| 6337 | goto trap; |
| 6338 | case M_TNE_I: |
| 6339 | s = "tne"; |
| 6340 | trap: |
| 6341 | load_register (&icnt, AT, &imm_expr, 0); |
| 6342 | macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT); |
| 6343 | break; |
| 6344 | |
| 6345 | case M_TRUNCWS: |
| 6346 | case M_TRUNCWD: |
| 6347 | assert (mips_opts.isa == ISA_MIPS1); |
| 6348 | sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ |
| 6349 | dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ |
| 6350 | |
| 6351 | /* |
| 6352 | * Is the double cfc1 instruction a bug in the mips assembler; |
| 6353 | * or is there a reason for it? |
| 6354 | */ |
| 6355 | mips_emit_delays (true); |
| 6356 | ++mips_opts.noreorder; |
| 6357 | mips_any_noreorder = 1; |
| 6358 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); |
| 6359 | macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31); |
| 6360 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); |
| 6361 | expr1.X_add_number = 3; |
| 6362 | macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg, |
| 6363 | (int) BFD_RELOC_LO16); |
| 6364 | expr1.X_add_number = 2; |
| 6365 | macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT, |
| 6366 | (int) BFD_RELOC_LO16); |
| 6367 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31); |
| 6368 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); |
| 6369 | macro_build ((char *) NULL, &icnt, NULL, |
| 6370 | mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg); |
| 6371 | macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31); |
| 6372 | macro_build ((char *) NULL, &icnt, NULL, "nop", ""); |
| 6373 | --mips_opts.noreorder; |
| 6374 | break; |
| 6375 | |
| 6376 | case M_ULH: |
| 6377 | s = "lb"; |
| 6378 | goto ulh; |
| 6379 | case M_ULHU: |
| 6380 | s = "lbu"; |
| 6381 | ulh: |
| 6382 | if (offset_expr.X_add_number >= 0x7fff) |
| 6383 | as_bad (_("operand overflow")); |
| 6384 | /* avoid load delay */ |
| 6385 | if (! target_big_endian) |
| 6386 | offset_expr.X_add_number += 1; |
| 6387 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
| 6388 | (int) BFD_RELOC_LO16, breg); |
| 6389 | if (! target_big_endian) |
| 6390 | offset_expr.X_add_number -= 1; |
| 6391 | else |
| 6392 | offset_expr.X_add_number += 1; |
| 6393 | macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT, |
| 6394 | (int) BFD_RELOC_LO16, breg); |
| 6395 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8); |
| 6396 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT); |
| 6397 | break; |
| 6398 | |
| 6399 | case M_ULD: |
| 6400 | s = "ldl"; |
| 6401 | s2 = "ldr"; |
| 6402 | off = 7; |
| 6403 | goto ulw; |
| 6404 | case M_ULW: |
| 6405 | s = "lwl"; |
| 6406 | s2 = "lwr"; |
| 6407 | off = 3; |
| 6408 | ulw: |
| 6409 | if (offset_expr.X_add_number >= 0x8000 - off) |
| 6410 | as_bad (_("operand overflow")); |
| 6411 | if (! target_big_endian) |
| 6412 | offset_expr.X_add_number += off; |
| 6413 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
| 6414 | (int) BFD_RELOC_LO16, breg); |
| 6415 | if (! target_big_endian) |
| 6416 | offset_expr.X_add_number -= off; |
| 6417 | else |
| 6418 | offset_expr.X_add_number += off; |
| 6419 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, |
| 6420 | (int) BFD_RELOC_LO16, breg); |
| 6421 | return; |
| 6422 | |
| 6423 | case M_ULD_A: |
| 6424 | s = "ldl"; |
| 6425 | s2 = "ldr"; |
| 6426 | off = 7; |
| 6427 | goto ulwa; |
| 6428 | case M_ULW_A: |
| 6429 | s = "lwl"; |
| 6430 | s2 = "lwr"; |
| 6431 | off = 3; |
| 6432 | ulwa: |
| 6433 | load_address (&icnt, AT, &offset_expr); |
| 6434 | if (breg != 0) |
| 6435 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6436 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6437 | "d,v,t", AT, AT, breg); |
| 6438 | if (! target_big_endian) |
| 6439 | expr1.X_add_number = off; |
| 6440 | else |
| 6441 | expr1.X_add_number = 0; |
| 6442 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, |
| 6443 | (int) BFD_RELOC_LO16, AT); |
| 6444 | if (! target_big_endian) |
| 6445 | expr1.X_add_number = 0; |
| 6446 | else |
| 6447 | expr1.X_add_number = off; |
| 6448 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
| 6449 | (int) BFD_RELOC_LO16, AT); |
| 6450 | break; |
| 6451 | |
| 6452 | case M_ULH_A: |
| 6453 | case M_ULHU_A: |
| 6454 | load_address (&icnt, AT, &offset_expr); |
| 6455 | if (breg != 0) |
| 6456 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6457 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6458 | "d,v,t", AT, AT, breg); |
| 6459 | if (target_big_endian) |
| 6460 | expr1.X_add_number = 0; |
| 6461 | macro_build ((char *) NULL, &icnt, &expr1, |
| 6462 | mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg, |
| 6463 | (int) BFD_RELOC_LO16, AT); |
| 6464 | if (target_big_endian) |
| 6465 | expr1.X_add_number = 1; |
| 6466 | else |
| 6467 | expr1.X_add_number = 0; |
| 6468 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
| 6469 | (int) BFD_RELOC_LO16, AT); |
| 6470 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, |
| 6471 | treg, 8); |
| 6472 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, |
| 6473 | treg, AT); |
| 6474 | break; |
| 6475 | |
| 6476 | case M_USH: |
| 6477 | if (offset_expr.X_add_number >= 0x7fff) |
| 6478 | as_bad (_("operand overflow")); |
| 6479 | if (target_big_endian) |
| 6480 | offset_expr.X_add_number += 1; |
| 6481 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg, |
| 6482 | (int) BFD_RELOC_LO16, breg); |
| 6483 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8); |
| 6484 | if (target_big_endian) |
| 6485 | offset_expr.X_add_number -= 1; |
| 6486 | else |
| 6487 | offset_expr.X_add_number += 1; |
| 6488 | macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT, |
| 6489 | (int) BFD_RELOC_LO16, breg); |
| 6490 | break; |
| 6491 | |
| 6492 | case M_USD: |
| 6493 | s = "sdl"; |
| 6494 | s2 = "sdr"; |
| 6495 | off = 7; |
| 6496 | goto usw; |
| 6497 | case M_USW: |
| 6498 | s = "swl"; |
| 6499 | s2 = "swr"; |
| 6500 | off = 3; |
| 6501 | usw: |
| 6502 | if (offset_expr.X_add_number >= 0x8000 - off) |
| 6503 | as_bad (_("operand overflow")); |
| 6504 | if (! target_big_endian) |
| 6505 | offset_expr.X_add_number += off; |
| 6506 | macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg, |
| 6507 | (int) BFD_RELOC_LO16, breg); |
| 6508 | if (! target_big_endian) |
| 6509 | offset_expr.X_add_number -= off; |
| 6510 | else |
| 6511 | offset_expr.X_add_number += off; |
| 6512 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg, |
| 6513 | (int) BFD_RELOC_LO16, breg); |
| 6514 | return; |
| 6515 | |
| 6516 | case M_USD_A: |
| 6517 | s = "sdl"; |
| 6518 | s2 = "sdr"; |
| 6519 | off = 7; |
| 6520 | goto uswa; |
| 6521 | case M_USW_A: |
| 6522 | s = "swl"; |
| 6523 | s2 = "swr"; |
| 6524 | off = 3; |
| 6525 | uswa: |
| 6526 | load_address (&icnt, AT, &offset_expr); |
| 6527 | if (breg != 0) |
| 6528 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6529 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6530 | "d,v,t", AT, AT, breg); |
| 6531 | if (! target_big_endian) |
| 6532 | expr1.X_add_number = off; |
| 6533 | else |
| 6534 | expr1.X_add_number = 0; |
| 6535 | macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg, |
| 6536 | (int) BFD_RELOC_LO16, AT); |
| 6537 | if (! target_big_endian) |
| 6538 | expr1.X_add_number = 0; |
| 6539 | else |
| 6540 | expr1.X_add_number = off; |
| 6541 | macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg, |
| 6542 | (int) BFD_RELOC_LO16, AT); |
| 6543 | break; |
| 6544 | |
| 6545 | case M_USH_A: |
| 6546 | load_address (&icnt, AT, &offset_expr); |
| 6547 | if (breg != 0) |
| 6548 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6549 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 6550 | "d,v,t", AT, AT, breg); |
| 6551 | if (! target_big_endian) |
| 6552 | expr1.X_add_number = 0; |
| 6553 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
| 6554 | (int) BFD_RELOC_LO16, AT); |
| 6555 | macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg, |
| 6556 | treg, 8); |
| 6557 | if (! target_big_endian) |
| 6558 | expr1.X_add_number = 1; |
| 6559 | else |
| 6560 | expr1.X_add_number = 0; |
| 6561 | macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg, |
| 6562 | (int) BFD_RELOC_LO16, AT); |
| 6563 | if (! target_big_endian) |
| 6564 | expr1.X_add_number = 0; |
| 6565 | else |
| 6566 | expr1.X_add_number = 1; |
| 6567 | macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT, |
| 6568 | (int) BFD_RELOC_LO16, AT); |
| 6569 | macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, |
| 6570 | treg, 8); |
| 6571 | macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, |
| 6572 | treg, AT); |
| 6573 | break; |
| 6574 | |
| 6575 | default: |
| 6576 | /* FIXME: Check if this is one of the itbl macros, since they |
| 6577 | are added dynamically. */ |
| 6578 | as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name); |
| 6579 | break; |
| 6580 | } |
| 6581 | if (mips_opts.noat) |
| 6582 | as_warn (_("Macro used $at after \".set noat\"")); |
| 6583 | } |
| 6584 | |
| 6585 | /* Implement macros in mips16 mode. */ |
| 6586 | |
| 6587 | static void |
| 6588 | mips16_macro (ip) |
| 6589 | struct mips_cl_insn *ip; |
| 6590 | { |
| 6591 | int mask; |
| 6592 | int xreg, yreg, zreg, tmp; |
| 6593 | int icnt; |
| 6594 | expressionS expr1; |
| 6595 | int dbl; |
| 6596 | const char *s, *s2, *s3; |
| 6597 | |
| 6598 | mask = ip->insn_mo->mask; |
| 6599 | |
| 6600 | xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; |
| 6601 | yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY; |
| 6602 | zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; |
| 6603 | |
| 6604 | icnt = 0; |
| 6605 | |
| 6606 | expr1.X_op = O_constant; |
| 6607 | expr1.X_op_symbol = NULL; |
| 6608 | expr1.X_add_symbol = NULL; |
| 6609 | expr1.X_add_number = 1; |
| 6610 | |
| 6611 | dbl = 0; |
| 6612 | |
| 6613 | switch (mask) |
| 6614 | { |
| 6615 | default: |
| 6616 | internalError (); |
| 6617 | |
| 6618 | case M_DDIV_3: |
| 6619 | dbl = 1; |
| 6620 | case M_DIV_3: |
| 6621 | s = "mflo"; |
| 6622 | goto do_div3; |
| 6623 | case M_DREM_3: |
| 6624 | dbl = 1; |
| 6625 | case M_REM_3: |
| 6626 | s = "mfhi"; |
| 6627 | do_div3: |
| 6628 | mips_emit_delays (true); |
| 6629 | ++mips_opts.noreorder; |
| 6630 | mips_any_noreorder = 1; |
| 6631 | macro_build ((char *) NULL, &icnt, NULL, |
| 6632 | dbl ? "ddiv" : "div", |
| 6633 | "0,x,y", xreg, yreg); |
| 6634 | expr1.X_add_number = 2; |
| 6635 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
| 6636 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
| 6637 | |
| 6638 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
| 6639 | since that causes an overflow. We should do that as well, |
| 6640 | but I don't see how to do the comparisons without a temporary |
| 6641 | register. */ |
| 6642 | --mips_opts.noreorder; |
| 6643 | macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg); |
| 6644 | break; |
| 6645 | |
| 6646 | case M_DIVU_3: |
| 6647 | s = "divu"; |
| 6648 | s2 = "mflo"; |
| 6649 | goto do_divu3; |
| 6650 | case M_REMU_3: |
| 6651 | s = "divu"; |
| 6652 | s2 = "mfhi"; |
| 6653 | goto do_divu3; |
| 6654 | case M_DDIVU_3: |
| 6655 | s = "ddivu"; |
| 6656 | s2 = "mflo"; |
| 6657 | goto do_divu3; |
| 6658 | case M_DREMU_3: |
| 6659 | s = "ddivu"; |
| 6660 | s2 = "mfhi"; |
| 6661 | do_divu3: |
| 6662 | mips_emit_delays (true); |
| 6663 | ++mips_opts.noreorder; |
| 6664 | mips_any_noreorder = 1; |
| 6665 | macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg); |
| 6666 | expr1.X_add_number = 2; |
| 6667 | macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg); |
| 6668 | macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7); |
| 6669 | --mips_opts.noreorder; |
| 6670 | macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg); |
| 6671 | break; |
| 6672 | |
| 6673 | case M_DMUL: |
| 6674 | dbl = 1; |
| 6675 | case M_MUL: |
| 6676 | macro_build ((char *) NULL, &icnt, NULL, |
| 6677 | dbl ? "dmultu" : "multu", "x,y", xreg, yreg); |
| 6678 | macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg); |
| 6679 | return; |
| 6680 | |
| 6681 | case M_DSUBU_I: |
| 6682 | dbl = 1; |
| 6683 | goto do_subu; |
| 6684 | case M_SUBU_I: |
| 6685 | do_subu: |
| 6686 | if (imm_expr.X_op != O_constant) |
| 6687 | as_bad (_("Unsupported large constant")); |
| 6688 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6689 | macro_build ((char *) NULL, &icnt, &imm_expr, |
| 6690 | dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg); |
| 6691 | break; |
| 6692 | |
| 6693 | case M_SUBU_I_2: |
| 6694 | if (imm_expr.X_op != O_constant) |
| 6695 | as_bad (_("Unsupported large constant")); |
| 6696 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6697 | macro_build ((char *) NULL, &icnt, &imm_expr, "addiu", |
| 6698 | "x,k", xreg); |
| 6699 | break; |
| 6700 | |
| 6701 | case M_DSUBU_I_2: |
| 6702 | if (imm_expr.X_op != O_constant) |
| 6703 | as_bad (_("Unsupported large constant")); |
| 6704 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 6705 | macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu", |
| 6706 | "y,j", yreg); |
| 6707 | break; |
| 6708 | |
| 6709 | case M_BEQ: |
| 6710 | s = "cmp"; |
| 6711 | s2 = "bteqz"; |
| 6712 | goto do_branch; |
| 6713 | case M_BNE: |
| 6714 | s = "cmp"; |
| 6715 | s2 = "btnez"; |
| 6716 | goto do_branch; |
| 6717 | case M_BLT: |
| 6718 | s = "slt"; |
| 6719 | s2 = "btnez"; |
| 6720 | goto do_branch; |
| 6721 | case M_BLTU: |
| 6722 | s = "sltu"; |
| 6723 | s2 = "btnez"; |
| 6724 | goto do_branch; |
| 6725 | case M_BLE: |
| 6726 | s = "slt"; |
| 6727 | s2 = "bteqz"; |
| 6728 | goto do_reverse_branch; |
| 6729 | case M_BLEU: |
| 6730 | s = "sltu"; |
| 6731 | s2 = "bteqz"; |
| 6732 | goto do_reverse_branch; |
| 6733 | case M_BGE: |
| 6734 | s = "slt"; |
| 6735 | s2 = "bteqz"; |
| 6736 | goto do_branch; |
| 6737 | case M_BGEU: |
| 6738 | s = "sltu"; |
| 6739 | s2 = "bteqz"; |
| 6740 | goto do_branch; |
| 6741 | case M_BGT: |
| 6742 | s = "slt"; |
| 6743 | s2 = "btnez"; |
| 6744 | goto do_reverse_branch; |
| 6745 | case M_BGTU: |
| 6746 | s = "sltu"; |
| 6747 | s2 = "btnez"; |
| 6748 | |
| 6749 | do_reverse_branch: |
| 6750 | tmp = xreg; |
| 6751 | xreg = yreg; |
| 6752 | yreg = tmp; |
| 6753 | |
| 6754 | do_branch: |
| 6755 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y", |
| 6756 | xreg, yreg); |
| 6757 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); |
| 6758 | break; |
| 6759 | |
| 6760 | case M_BEQ_I: |
| 6761 | s = "cmpi"; |
| 6762 | s2 = "bteqz"; |
| 6763 | s3 = "x,U"; |
| 6764 | goto do_branch_i; |
| 6765 | case M_BNE_I: |
| 6766 | s = "cmpi"; |
| 6767 | s2 = "btnez"; |
| 6768 | s3 = "x,U"; |
| 6769 | goto do_branch_i; |
| 6770 | case M_BLT_I: |
| 6771 | s = "slti"; |
| 6772 | s2 = "btnez"; |
| 6773 | s3 = "x,8"; |
| 6774 | goto do_branch_i; |
| 6775 | case M_BLTU_I: |
| 6776 | s = "sltiu"; |
| 6777 | s2 = "btnez"; |
| 6778 | s3 = "x,8"; |
| 6779 | goto do_branch_i; |
| 6780 | case M_BLE_I: |
| 6781 | s = "slti"; |
| 6782 | s2 = "btnez"; |
| 6783 | s3 = "x,8"; |
| 6784 | goto do_addone_branch_i; |
| 6785 | case M_BLEU_I: |
| 6786 | s = "sltiu"; |
| 6787 | s2 = "btnez"; |
| 6788 | s3 = "x,8"; |
| 6789 | goto do_addone_branch_i; |
| 6790 | case M_BGE_I: |
| 6791 | s = "slti"; |
| 6792 | s2 = "bteqz"; |
| 6793 | s3 = "x,8"; |
| 6794 | goto do_branch_i; |
| 6795 | case M_BGEU_I: |
| 6796 | s = "sltiu"; |
| 6797 | s2 = "bteqz"; |
| 6798 | s3 = "x,8"; |
| 6799 | goto do_branch_i; |
| 6800 | case M_BGT_I: |
| 6801 | s = "slti"; |
| 6802 | s2 = "bteqz"; |
| 6803 | s3 = "x,8"; |
| 6804 | goto do_addone_branch_i; |
| 6805 | case M_BGTU_I: |
| 6806 | s = "sltiu"; |
| 6807 | s2 = "bteqz"; |
| 6808 | s3 = "x,8"; |
| 6809 | |
| 6810 | do_addone_branch_i: |
| 6811 | if (imm_expr.X_op != O_constant) |
| 6812 | as_bad (_("Unsupported large constant")); |
| 6813 | ++imm_expr.X_add_number; |
| 6814 | |
| 6815 | do_branch_i: |
| 6816 | macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg); |
| 6817 | macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p"); |
| 6818 | break; |
| 6819 | |
| 6820 | case M_ABS: |
| 6821 | expr1.X_add_number = 0; |
| 6822 | macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg); |
| 6823 | if (xreg != yreg) |
| 6824 | move_register (&icnt, xreg, yreg); |
| 6825 | expr1.X_add_number = 2; |
| 6826 | macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p"); |
| 6827 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 6828 | "neg", "x,w", xreg, xreg); |
| 6829 | } |
| 6830 | } |
| 6831 | |
| 6832 | /* For consistency checking, verify that all bits are specified either |
| 6833 | by the match/mask part of the instruction definition, or by the |
| 6834 | operand list. */ |
| 6835 | static int |
| 6836 | validate_mips_insn (opc) |
| 6837 | const struct mips_opcode *opc; |
| 6838 | { |
| 6839 | const char *p = opc->args; |
| 6840 | char c; |
| 6841 | unsigned long used_bits = opc->mask; |
| 6842 | |
| 6843 | if ((used_bits & opc->match) != opc->match) |
| 6844 | { |
| 6845 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), |
| 6846 | opc->name, opc->args); |
| 6847 | return 0; |
| 6848 | } |
| 6849 | #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift))) |
| 6850 | while (*p) |
| 6851 | switch (c = *p++) |
| 6852 | { |
| 6853 | case ',': break; |
| 6854 | case '(': break; |
| 6855 | case ')': break; |
| 6856 | case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
| 6857 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; |
| 6858 | case 'A': break; |
| 6859 | case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break; |
| 6860 | case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break; |
| 6861 | case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break; |
| 6862 | case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
| 6863 | case 'F': break; |
| 6864 | case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
| 6865 | case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break; |
| 6866 | case 'I': break; |
| 6867 | case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break; |
| 6868 | case 'L': break; |
| 6869 | case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break; |
| 6870 | case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break; |
| 6871 | case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break; |
| 6872 | case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break; |
| 6873 | case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break; |
| 6874 | case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break; |
| 6875 | case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break; |
| 6876 | case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break; |
| 6877 | case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
| 6878 | case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break; |
| 6879 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; |
| 6880 | case 'f': break; |
| 6881 | case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break; |
| 6882 | case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; |
| 6883 | case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; |
| 6884 | case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break; |
| 6885 | case 'l': break; |
| 6886 | case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; |
| 6887 | case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break; |
| 6888 | case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break; |
| 6889 | case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
| 6890 | case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
| 6891 | case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
| 6892 | case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break; |
| 6893 | case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break; |
| 6894 | case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
| 6895 | case 'x': break; |
| 6896 | case 'z': break; |
| 6897 | case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break; |
| 6898 | case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD); |
| 6899 | USE_BITS (OP_MASK_RT, OP_SH_RT); break; |
| 6900 | default: |
| 6901 | as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"), |
| 6902 | c, opc->name, opc->args); |
| 6903 | return 0; |
| 6904 | } |
| 6905 | #undef USE_BITS |
| 6906 | if (used_bits != 0xffffffff) |
| 6907 | { |
| 6908 | as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"), |
| 6909 | ~used_bits & 0xffffffff, opc->name, opc->args); |
| 6910 | return 0; |
| 6911 | } |
| 6912 | return 1; |
| 6913 | } |
| 6914 | |
| 6915 | /* This routine assembles an instruction into its binary format. As a |
| 6916 | side effect, it sets one of the global variables imm_reloc or |
| 6917 | offset_reloc to the type of relocation to do if one of the operands |
| 6918 | is an address expression. */ |
| 6919 | |
| 6920 | static void |
| 6921 | mips_ip (str, ip) |
| 6922 | char *str; |
| 6923 | struct mips_cl_insn *ip; |
| 6924 | { |
| 6925 | char *s; |
| 6926 | const char *args; |
| 6927 | char c = 0; |
| 6928 | struct mips_opcode *insn; |
| 6929 | char *argsStart; |
| 6930 | unsigned int regno; |
| 6931 | unsigned int lastregno = 0; |
| 6932 | char *s_reset; |
| 6933 | char save_c = 0; |
| 6934 | int full_opcode_match = 1; |
| 6935 | |
| 6936 | insn_error = NULL; |
| 6937 | |
| 6938 | /* If the instruction contains a '.', we first try to match an instruction |
| 6939 | including the '.'. Then we try again without the '.'. */ |
| 6940 | insn = NULL; |
| 6941 | for (s = str; *s != '\0' && !isspace ((unsigned char) *s); ++s) |
| 6942 | continue; |
| 6943 | |
| 6944 | /* If we stopped on whitespace, then replace the whitespace with null for |
| 6945 | the call to hash_find. Save the character we replaced just in case we |
| 6946 | have to re-parse the instruction. */ |
| 6947 | if (isspace ((unsigned char) *s)) |
| 6948 | { |
| 6949 | save_c = *s; |
| 6950 | *s++ = '\0'; |
| 6951 | } |
| 6952 | |
| 6953 | insn = (struct mips_opcode *) hash_find (op_hash, str); |
| 6954 | |
| 6955 | /* If we didn't find the instruction in the opcode table, try again, but |
| 6956 | this time with just the instruction up to, but not including the |
| 6957 | first '.'. */ |
| 6958 | if (insn == NULL) |
| 6959 | { |
| 6960 | /* Restore the character we overwrite above (if any). */ |
| 6961 | if (save_c) |
| 6962 | *(--s) = save_c; |
| 6963 | |
| 6964 | /* Scan up to the first '.' or whitespace. */ |
| 6965 | for (s = str; *s != '\0' && *s != '.' && !isspace ((unsigned char) *s); ++s) |
| 6966 | continue; |
| 6967 | |
| 6968 | /* If we did not find a '.', then we can quit now. */ |
| 6969 | if (*s != '.') |
| 6970 | { |
| 6971 | insn_error = "unrecognized opcode"; |
| 6972 | return; |
| 6973 | } |
| 6974 | |
| 6975 | /* Lookup the instruction in the hash table. */ |
| 6976 | *s++ = '\0'; |
| 6977 | if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL) |
| 6978 | { |
| 6979 | insn_error = "unrecognized opcode"; |
| 6980 | return; |
| 6981 | } |
| 6982 | |
| 6983 | full_opcode_match = 0; |
| 6984 | } |
| 6985 | |
| 6986 | argsStart = s; |
| 6987 | for (;;) |
| 6988 | { |
| 6989 | boolean ok; |
| 6990 | |
| 6991 | assert (strcmp (insn->name, str) == 0); |
| 6992 | |
| 6993 | if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch)) |
| 6994 | ok = true; |
| 6995 | else |
| 6996 | ok = false; |
| 6997 | |
| 6998 | if (insn->pinfo != INSN_MACRO) |
| 6999 | { |
| 7000 | if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) |
| 7001 | ok = false; |
| 7002 | } |
| 7003 | |
| 7004 | if (! ok) |
| 7005 | { |
| 7006 | if (insn + 1 < &mips_opcodes[NUMOPCODES] |
| 7007 | && strcmp (insn->name, insn[1].name) == 0) |
| 7008 | { |
| 7009 | ++insn; |
| 7010 | continue; |
| 7011 | } |
| 7012 | else |
| 7013 | { |
| 7014 | if (!insn_error) |
| 7015 | { |
| 7016 | static char buf[100]; |
| 7017 | sprintf (buf, |
| 7018 | _("opcode not supported on this processor: %s (%s)"), |
| 7019 | mips_cpu_to_str (mips_arch), |
| 7020 | mips_isa_to_str (mips_opts.isa)); |
| 7021 | |
| 7022 | insn_error = buf; |
| 7023 | } |
| 7024 | if (save_c) |
| 7025 | *(--s) = save_c; |
| 7026 | return; |
| 7027 | } |
| 7028 | } |
| 7029 | |
| 7030 | ip->insn_mo = insn; |
| 7031 | ip->insn_opcode = insn->match; |
| 7032 | insn_error = NULL; |
| 7033 | for (args = insn->args;; ++args) |
| 7034 | { |
| 7035 | if (*s == ' ') |
| 7036 | ++s; |
| 7037 | switch (*args) |
| 7038 | { |
| 7039 | case '\0': /* end of args */ |
| 7040 | if (*s == '\0') |
| 7041 | return; |
| 7042 | break; |
| 7043 | |
| 7044 | case ',': |
| 7045 | if (*s++ == *args) |
| 7046 | continue; |
| 7047 | s--; |
| 7048 | switch (*++args) |
| 7049 | { |
| 7050 | case 'r': |
| 7051 | case 'v': |
| 7052 | ip->insn_opcode |= lastregno << OP_SH_RS; |
| 7053 | continue; |
| 7054 | |
| 7055 | case 'w': |
| 7056 | ip->insn_opcode |= lastregno << OP_SH_RT; |
| 7057 | continue; |
| 7058 | |
| 7059 | case 'W': |
| 7060 | ip->insn_opcode |= lastregno << OP_SH_FT; |
| 7061 | continue; |
| 7062 | |
| 7063 | case 'V': |
| 7064 | ip->insn_opcode |= lastregno << OP_SH_FS; |
| 7065 | continue; |
| 7066 | } |
| 7067 | break; |
| 7068 | |
| 7069 | case '(': |
| 7070 | /* Handle optional base register. |
| 7071 | Either the base register is omitted or |
| 7072 | we must have a left paren. */ |
| 7073 | /* This is dependent on the next operand specifier |
| 7074 | is a base register specification. */ |
| 7075 | assert (args[1] == 'b' || args[1] == '5' |
| 7076 | || args[1] == '-' || args[1] == '4'); |
| 7077 | if (*s == '\0') |
| 7078 | return; |
| 7079 | |
| 7080 | case ')': /* these must match exactly */ |
| 7081 | if (*s++ == *args) |
| 7082 | continue; |
| 7083 | break; |
| 7084 | |
| 7085 | case '<': /* must be at least one digit */ |
| 7086 | /* |
| 7087 | * According to the manual, if the shift amount is greater |
| 7088 | * than 31 or less than 0 the the shift amount should be |
| 7089 | * mod 32. In reality the mips assembler issues an error. |
| 7090 | * We issue a warning and mask out all but the low 5 bits. |
| 7091 | */ |
| 7092 | my_getExpression (&imm_expr, s); |
| 7093 | check_absolute_expr (ip, &imm_expr); |
| 7094 | if ((unsigned long) imm_expr.X_add_number > 31) |
| 7095 | { |
| 7096 | as_warn (_("Improper shift amount (%ld)"), |
| 7097 | (long) imm_expr.X_add_number); |
| 7098 | imm_expr.X_add_number &= OP_MASK_SHAMT; |
| 7099 | } |
| 7100 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT; |
| 7101 | imm_expr.X_op = O_absent; |
| 7102 | s = expr_end; |
| 7103 | continue; |
| 7104 | |
| 7105 | case '>': /* shift amount minus 32 */ |
| 7106 | my_getExpression (&imm_expr, s); |
| 7107 | check_absolute_expr (ip, &imm_expr); |
| 7108 | if ((unsigned long) imm_expr.X_add_number < 32 |
| 7109 | || (unsigned long) imm_expr.X_add_number > 63) |
| 7110 | break; |
| 7111 | ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT; |
| 7112 | imm_expr.X_op = O_absent; |
| 7113 | s = expr_end; |
| 7114 | continue; |
| 7115 | |
| 7116 | case 'k': /* cache code */ |
| 7117 | case 'h': /* prefx code */ |
| 7118 | my_getExpression (&imm_expr, s); |
| 7119 | check_absolute_expr (ip, &imm_expr); |
| 7120 | if ((unsigned long) imm_expr.X_add_number > 31) |
| 7121 | { |
| 7122 | as_warn (_("Invalid value for `%s' (%lu)"), |
| 7123 | ip->insn_mo->name, |
| 7124 | (unsigned long) imm_expr.X_add_number); |
| 7125 | imm_expr.X_add_number &= 0x1f; |
| 7126 | } |
| 7127 | if (*args == 'k') |
| 7128 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE; |
| 7129 | else |
| 7130 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX; |
| 7131 | imm_expr.X_op = O_absent; |
| 7132 | s = expr_end; |
| 7133 | continue; |
| 7134 | |
| 7135 | case 'c': /* break code */ |
| 7136 | my_getExpression (&imm_expr, s); |
| 7137 | check_absolute_expr (ip, &imm_expr); |
| 7138 | if ((unsigned) imm_expr.X_add_number > 1023) |
| 7139 | { |
| 7140 | as_warn (_("Illegal break code (%ld)"), |
| 7141 | (long) imm_expr.X_add_number); |
| 7142 | imm_expr.X_add_number &= OP_MASK_CODE; |
| 7143 | } |
| 7144 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE; |
| 7145 | imm_expr.X_op = O_absent; |
| 7146 | s = expr_end; |
| 7147 | continue; |
| 7148 | |
| 7149 | case 'q': /* lower break code */ |
| 7150 | my_getExpression (&imm_expr, s); |
| 7151 | check_absolute_expr (ip, &imm_expr); |
| 7152 | if ((unsigned) imm_expr.X_add_number > 1023) |
| 7153 | { |
| 7154 | as_warn (_("Illegal lower break code (%ld)"), |
| 7155 | (long) imm_expr.X_add_number); |
| 7156 | imm_expr.X_add_number &= OP_MASK_CODE2; |
| 7157 | } |
| 7158 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2; |
| 7159 | imm_expr.X_op = O_absent; |
| 7160 | s = expr_end; |
| 7161 | continue; |
| 7162 | |
| 7163 | case 'B': /* 20-bit syscall/break code. */ |
| 7164 | my_getExpression (&imm_expr, s); |
| 7165 | check_absolute_expr (ip, &imm_expr); |
| 7166 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20) |
| 7167 | as_warn (_("Illegal 20-bit code (%ld)"), |
| 7168 | (long) imm_expr.X_add_number); |
| 7169 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20; |
| 7170 | imm_expr.X_op = O_absent; |
| 7171 | s = expr_end; |
| 7172 | continue; |
| 7173 | |
| 7174 | case 'C': /* Coprocessor code */ |
| 7175 | my_getExpression (&imm_expr, s); |
| 7176 | check_absolute_expr (ip, &imm_expr); |
| 7177 | if ((unsigned long) imm_expr.X_add_number >= (1<<25)) |
| 7178 | { |
| 7179 | as_warn (_("Coproccesor code > 25 bits (%ld)"), |
| 7180 | (long) imm_expr.X_add_number); |
| 7181 | imm_expr.X_add_number &= ((1<<25) - 1); |
| 7182 | } |
| 7183 | ip->insn_opcode |= imm_expr.X_add_number; |
| 7184 | imm_expr.X_op = O_absent; |
| 7185 | s = expr_end; |
| 7186 | continue; |
| 7187 | |
| 7188 | case 'J': /* 19-bit wait code. */ |
| 7189 | my_getExpression (&imm_expr, s); |
| 7190 | check_absolute_expr (ip, &imm_expr); |
| 7191 | if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19) |
| 7192 | as_warn (_("Illegal 19-bit code (%ld)"), |
| 7193 | (long) imm_expr.X_add_number); |
| 7194 | ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19; |
| 7195 | imm_expr.X_op = O_absent; |
| 7196 | s = expr_end; |
| 7197 | continue; |
| 7198 | |
| 7199 | case 'P': /* Performance register */ |
| 7200 | my_getExpression (&imm_expr, s); |
| 7201 | check_absolute_expr (ip, &imm_expr); |
| 7202 | if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1) |
| 7203 | { |
| 7204 | as_warn (_("Invalid performance register (%ld)"), |
| 7205 | (long) imm_expr.X_add_number); |
| 7206 | imm_expr.X_add_number &= OP_MASK_PERFREG; |
| 7207 | } |
| 7208 | ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG); |
| 7209 | imm_expr.X_op = O_absent; |
| 7210 | s = expr_end; |
| 7211 | continue; |
| 7212 | |
| 7213 | case 'b': /* base register */ |
| 7214 | case 'd': /* destination register */ |
| 7215 | case 's': /* source register */ |
| 7216 | case 't': /* target register */ |
| 7217 | case 'r': /* both target and source */ |
| 7218 | case 'v': /* both dest and source */ |
| 7219 | case 'w': /* both dest and target */ |
| 7220 | case 'E': /* coprocessor target register */ |
| 7221 | case 'G': /* coprocessor destination register */ |
| 7222 | case 'x': /* ignore register name */ |
| 7223 | case 'z': /* must be zero register */ |
| 7224 | case 'U': /* destination register (clo/clz). */ |
| 7225 | s_reset = s; |
| 7226 | if (s[0] == '$') |
| 7227 | { |
| 7228 | |
| 7229 | if (isdigit ((unsigned char) s[1])) |
| 7230 | { |
| 7231 | ++s; |
| 7232 | regno = 0; |
| 7233 | do |
| 7234 | { |
| 7235 | regno *= 10; |
| 7236 | regno += *s - '0'; |
| 7237 | ++s; |
| 7238 | } |
| 7239 | while (isdigit ((unsigned char) *s)); |
| 7240 | if (regno > 31) |
| 7241 | as_bad (_("Invalid register number (%d)"), regno); |
| 7242 | } |
| 7243 | else if (*args == 'E' || *args == 'G') |
| 7244 | goto notreg; |
| 7245 | else |
| 7246 | { |
| 7247 | if (s[1] == 'f' && s[2] == 'p') |
| 7248 | { |
| 7249 | s += 3; |
| 7250 | regno = FP; |
| 7251 | } |
| 7252 | else if (s[1] == 's' && s[2] == 'p') |
| 7253 | { |
| 7254 | s += 3; |
| 7255 | regno = SP; |
| 7256 | } |
| 7257 | else if (s[1] == 'g' && s[2] == 'p') |
| 7258 | { |
| 7259 | s += 3; |
| 7260 | regno = GP; |
| 7261 | } |
| 7262 | else if (s[1] == 'a' && s[2] == 't') |
| 7263 | { |
| 7264 | s += 3; |
| 7265 | regno = AT; |
| 7266 | } |
| 7267 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
| 7268 | { |
| 7269 | s += 4; |
| 7270 | regno = KT0; |
| 7271 | } |
| 7272 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') |
| 7273 | { |
| 7274 | s += 4; |
| 7275 | regno = KT1; |
| 7276 | } |
| 7277 | else if (itbl_have_entries) |
| 7278 | { |
| 7279 | char *p, *n; |
| 7280 | unsigned long r; |
| 7281 | |
| 7282 | p = s + 1; /* advance past '$' */ |
| 7283 | n = itbl_get_field (&p); /* n is name */ |
| 7284 | |
| 7285 | /* See if this is a register defined in an |
| 7286 | itbl entry. */ |
| 7287 | if (itbl_get_reg_val (n, &r)) |
| 7288 | { |
| 7289 | /* Get_field advances to the start of |
| 7290 | the next field, so we need to back |
| 7291 | rack to the end of the last field. */ |
| 7292 | if (p) |
| 7293 | s = p - 1; |
| 7294 | else |
| 7295 | s = strchr (s, '\0'); |
| 7296 | regno = r; |
| 7297 | } |
| 7298 | else |
| 7299 | goto notreg; |
| 7300 | } |
| 7301 | else |
| 7302 | goto notreg; |
| 7303 | } |
| 7304 | if (regno == AT |
| 7305 | && ! mips_opts.noat |
| 7306 | && *args != 'E' |
| 7307 | && *args != 'G') |
| 7308 | as_warn (_("Used $at without \".set noat\"")); |
| 7309 | c = *args; |
| 7310 | if (*s == ' ') |
| 7311 | s++; |
| 7312 | if (args[1] != *s) |
| 7313 | { |
| 7314 | if (c == 'r' || c == 'v' || c == 'w') |
| 7315 | { |
| 7316 | regno = lastregno; |
| 7317 | s = s_reset; |
| 7318 | args++; |
| 7319 | } |
| 7320 | } |
| 7321 | /* 'z' only matches $0. */ |
| 7322 | if (c == 'z' && regno != 0) |
| 7323 | break; |
| 7324 | |
| 7325 | /* Now that we have assembled one operand, we use the args string |
| 7326 | * to figure out where it goes in the instruction. */ |
| 7327 | switch (c) |
| 7328 | { |
| 7329 | case 'r': |
| 7330 | case 's': |
| 7331 | case 'v': |
| 7332 | case 'b': |
| 7333 | ip->insn_opcode |= regno << OP_SH_RS; |
| 7334 | break; |
| 7335 | case 'd': |
| 7336 | case 'G': |
| 7337 | ip->insn_opcode |= regno << OP_SH_RD; |
| 7338 | break; |
| 7339 | case 'U': |
| 7340 | ip->insn_opcode |= regno << OP_SH_RD; |
| 7341 | ip->insn_opcode |= regno << OP_SH_RT; |
| 7342 | break; |
| 7343 | case 'w': |
| 7344 | case 't': |
| 7345 | case 'E': |
| 7346 | ip->insn_opcode |= regno << OP_SH_RT; |
| 7347 | break; |
| 7348 | case 'x': |
| 7349 | /* This case exists because on the r3000 trunc |
| 7350 | expands into a macro which requires a gp |
| 7351 | register. On the r6000 or r4000 it is |
| 7352 | assembled into a single instruction which |
| 7353 | ignores the register. Thus the insn version |
| 7354 | is MIPS_ISA2 and uses 'x', and the macro |
| 7355 | version is MIPS_ISA1 and uses 't'. */ |
| 7356 | break; |
| 7357 | case 'z': |
| 7358 | /* This case is for the div instruction, which |
| 7359 | acts differently if the destination argument |
| 7360 | is $0. This only matches $0, and is checked |
| 7361 | outside the switch. */ |
| 7362 | break; |
| 7363 | case 'D': |
| 7364 | /* Itbl operand; not yet implemented. FIXME ?? */ |
| 7365 | break; |
| 7366 | /* What about all other operands like 'i', which |
| 7367 | can be specified in the opcode table? */ |
| 7368 | } |
| 7369 | lastregno = regno; |
| 7370 | continue; |
| 7371 | } |
| 7372 | notreg: |
| 7373 | switch (*args++) |
| 7374 | { |
| 7375 | case 'r': |
| 7376 | case 'v': |
| 7377 | ip->insn_opcode |= lastregno << OP_SH_RS; |
| 7378 | continue; |
| 7379 | case 'w': |
| 7380 | ip->insn_opcode |= lastregno << OP_SH_RT; |
| 7381 | continue; |
| 7382 | } |
| 7383 | break; |
| 7384 | |
| 7385 | case 'D': /* floating point destination register */ |
| 7386 | case 'S': /* floating point source register */ |
| 7387 | case 'T': /* floating point target register */ |
| 7388 | case 'R': /* floating point source register */ |
| 7389 | case 'V': |
| 7390 | case 'W': |
| 7391 | s_reset = s; |
| 7392 | if (s[0] == '$' && s[1] == 'f' && isdigit ((unsigned char) s[2])) |
| 7393 | { |
| 7394 | s += 2; |
| 7395 | regno = 0; |
| 7396 | do |
| 7397 | { |
| 7398 | regno *= 10; |
| 7399 | regno += *s - '0'; |
| 7400 | ++s; |
| 7401 | } |
| 7402 | while (isdigit ((unsigned char) *s)); |
| 7403 | |
| 7404 | if (regno > 31) |
| 7405 | as_bad (_("Invalid float register number (%d)"), regno); |
| 7406 | |
| 7407 | if ((regno & 1) != 0 |
| 7408 | && HAVE_32BIT_FPRS |
| 7409 | && ! (strcmp (str, "mtc1") == 0 |
| 7410 | || strcmp (str, "mfc1") == 0 |
| 7411 | || strcmp (str, "lwc1") == 0 |
| 7412 | || strcmp (str, "swc1") == 0 |
| 7413 | || strcmp (str, "l.s") == 0 |
| 7414 | || strcmp (str, "s.s") == 0)) |
| 7415 | as_warn (_("Float register should be even, was %d"), |
| 7416 | regno); |
| 7417 | |
| 7418 | c = *args; |
| 7419 | if (*s == ' ') |
| 7420 | s++; |
| 7421 | if (args[1] != *s) |
| 7422 | { |
| 7423 | if (c == 'V' || c == 'W') |
| 7424 | { |
| 7425 | regno = lastregno; |
| 7426 | s = s_reset; |
| 7427 | args++; |
| 7428 | } |
| 7429 | } |
| 7430 | switch (c) |
| 7431 | { |
| 7432 | case 'D': |
| 7433 | ip->insn_opcode |= regno << OP_SH_FD; |
| 7434 | break; |
| 7435 | case 'V': |
| 7436 | case 'S': |
| 7437 | ip->insn_opcode |= regno << OP_SH_FS; |
| 7438 | break; |
| 7439 | case 'W': |
| 7440 | case 'T': |
| 7441 | ip->insn_opcode |= regno << OP_SH_FT; |
| 7442 | break; |
| 7443 | case 'R': |
| 7444 | ip->insn_opcode |= regno << OP_SH_FR; |
| 7445 | break; |
| 7446 | } |
| 7447 | lastregno = regno; |
| 7448 | continue; |
| 7449 | } |
| 7450 | |
| 7451 | switch (*args++) |
| 7452 | { |
| 7453 | case 'V': |
| 7454 | ip->insn_opcode |= lastregno << OP_SH_FS; |
| 7455 | continue; |
| 7456 | case 'W': |
| 7457 | ip->insn_opcode |= lastregno << OP_SH_FT; |
| 7458 | continue; |
| 7459 | } |
| 7460 | break; |
| 7461 | |
| 7462 | case 'I': |
| 7463 | my_getExpression (&imm_expr, s); |
| 7464 | if (imm_expr.X_op != O_big |
| 7465 | && imm_expr.X_op != O_constant) |
| 7466 | insn_error = _("absolute expression required"); |
| 7467 | s = expr_end; |
| 7468 | continue; |
| 7469 | |
| 7470 | case 'A': |
| 7471 | my_getExpression (&offset_expr, s); |
| 7472 | imm_reloc = BFD_RELOC_32; |
| 7473 | s = expr_end; |
| 7474 | continue; |
| 7475 | |
| 7476 | case 'F': |
| 7477 | case 'L': |
| 7478 | case 'f': |
| 7479 | case 'l': |
| 7480 | { |
| 7481 | int f64; |
| 7482 | int using_gprs; |
| 7483 | char *save_in; |
| 7484 | char *err; |
| 7485 | unsigned char temp[8]; |
| 7486 | int len; |
| 7487 | unsigned int length; |
| 7488 | segT seg; |
| 7489 | subsegT subseg; |
| 7490 | char *p; |
| 7491 | |
| 7492 | /* These only appear as the last operand in an |
| 7493 | instruction, and every instruction that accepts |
| 7494 | them in any variant accepts them in all variants. |
| 7495 | This means we don't have to worry about backing out |
| 7496 | any changes if the instruction does not match. |
| 7497 | |
| 7498 | The difference between them is the size of the |
| 7499 | floating point constant and where it goes. For 'F' |
| 7500 | and 'L' the constant is 64 bits; for 'f' and 'l' it |
| 7501 | is 32 bits. Where the constant is placed is based |
| 7502 | on how the MIPS assembler does things: |
| 7503 | F -- .rdata |
| 7504 | L -- .lit8 |
| 7505 | f -- immediate value |
| 7506 | l -- .lit4 |
| 7507 | |
| 7508 | The .lit4 and .lit8 sections are only used if |
| 7509 | permitted by the -G argument. |
| 7510 | |
| 7511 | When generating embedded PIC code, we use the |
| 7512 | .lit8 section but not the .lit4 section (we can do |
| 7513 | .lit4 inline easily; we need to put .lit8 |
| 7514 | somewhere in the data segment, and using .lit8 |
| 7515 | permits the linker to eventually combine identical |
| 7516 | .lit8 entries). |
| 7517 | |
| 7518 | The code below needs to know whether the target register |
| 7519 | is 32 or 64 bits wide. It relies on the fact 'f' and |
| 7520 | 'F' are used with GPR-based instructions and 'l' and |
| 7521 | 'L' are used with FPR-based instructions. */ |
| 7522 | |
| 7523 | f64 = *args == 'F' || *args == 'L'; |
| 7524 | using_gprs = *args == 'F' || *args == 'f'; |
| 7525 | |
| 7526 | save_in = input_line_pointer; |
| 7527 | input_line_pointer = s; |
| 7528 | err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len); |
| 7529 | length = len; |
| 7530 | s = input_line_pointer; |
| 7531 | input_line_pointer = save_in; |
| 7532 | if (err != NULL && *err != '\0') |
| 7533 | { |
| 7534 | as_bad (_("Bad floating point constant: %s"), err); |
| 7535 | memset (temp, '\0', sizeof temp); |
| 7536 | length = f64 ? 8 : 4; |
| 7537 | } |
| 7538 | |
| 7539 | assert (length == (unsigned) (f64 ? 8 : 4)); |
| 7540 | |
| 7541 | if (*args == 'f' |
| 7542 | || (*args == 'l' |
| 7543 | && (! USE_GLOBAL_POINTER_OPT |
| 7544 | || mips_pic == EMBEDDED_PIC |
| 7545 | || g_switch_value < 4 |
| 7546 | || (temp[0] == 0 && temp[1] == 0) |
| 7547 | || (temp[2] == 0 && temp[3] == 0)))) |
| 7548 | { |
| 7549 | imm_expr.X_op = O_constant; |
| 7550 | if (! target_big_endian) |
| 7551 | imm_expr.X_add_number = bfd_getl32 (temp); |
| 7552 | else |
| 7553 | imm_expr.X_add_number = bfd_getb32 (temp); |
| 7554 | } |
| 7555 | else if (length > 4 |
| 7556 | && ! mips_disable_float_construction |
| 7557 | /* Constants can only be constructed in GPRs and |
| 7558 | copied to FPRs if the GPRs are at least as wide |
| 7559 | as the FPRs. Force the constant into memory if |
| 7560 | we are using 64-bit FPRs but the GPRs are only |
| 7561 | 32 bits wide. */ |
| 7562 | && (using_gprs |
| 7563 | || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) |
| 7564 | && ((temp[0] == 0 && temp[1] == 0) |
| 7565 | || (temp[2] == 0 && temp[3] == 0)) |
| 7566 | && ((temp[4] == 0 && temp[5] == 0) |
| 7567 | || (temp[6] == 0 && temp[7] == 0))) |
| 7568 | { |
| 7569 | /* The value is simple enough to load with a couple of |
| 7570 | instructions. If using 32-bit registers, set |
| 7571 | imm_expr to the high order 32 bits and offset_expr to |
| 7572 | the low order 32 bits. Otherwise, set imm_expr to |
| 7573 | the entire 64 bit constant. */ |
| 7574 | if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) |
| 7575 | { |
| 7576 | imm_expr.X_op = O_constant; |
| 7577 | offset_expr.X_op = O_constant; |
| 7578 | if (! target_big_endian) |
| 7579 | { |
| 7580 | imm_expr.X_add_number = bfd_getl32 (temp + 4); |
| 7581 | offset_expr.X_add_number = bfd_getl32 (temp); |
| 7582 | } |
| 7583 | else |
| 7584 | { |
| 7585 | imm_expr.X_add_number = bfd_getb32 (temp); |
| 7586 | offset_expr.X_add_number = bfd_getb32 (temp + 4); |
| 7587 | } |
| 7588 | if (offset_expr.X_add_number == 0) |
| 7589 | offset_expr.X_op = O_absent; |
| 7590 | } |
| 7591 | else if (sizeof (imm_expr.X_add_number) > 4) |
| 7592 | { |
| 7593 | imm_expr.X_op = O_constant; |
| 7594 | if (! target_big_endian) |
| 7595 | imm_expr.X_add_number = bfd_getl64 (temp); |
| 7596 | else |
| 7597 | imm_expr.X_add_number = bfd_getb64 (temp); |
| 7598 | } |
| 7599 | else |
| 7600 | { |
| 7601 | imm_expr.X_op = O_big; |
| 7602 | imm_expr.X_add_number = 4; |
| 7603 | if (! target_big_endian) |
| 7604 | { |
| 7605 | generic_bignum[0] = bfd_getl16 (temp); |
| 7606 | generic_bignum[1] = bfd_getl16 (temp + 2); |
| 7607 | generic_bignum[2] = bfd_getl16 (temp + 4); |
| 7608 | generic_bignum[3] = bfd_getl16 (temp + 6); |
| 7609 | } |
| 7610 | else |
| 7611 | { |
| 7612 | generic_bignum[0] = bfd_getb16 (temp + 6); |
| 7613 | generic_bignum[1] = bfd_getb16 (temp + 4); |
| 7614 | generic_bignum[2] = bfd_getb16 (temp + 2); |
| 7615 | generic_bignum[3] = bfd_getb16 (temp); |
| 7616 | } |
| 7617 | } |
| 7618 | } |
| 7619 | else |
| 7620 | { |
| 7621 | const char *newname; |
| 7622 | segT new_seg; |
| 7623 | |
| 7624 | /* Switch to the right section. */ |
| 7625 | seg = now_seg; |
| 7626 | subseg = now_subseg; |
| 7627 | switch (*args) |
| 7628 | { |
| 7629 | default: /* unused default case avoids warnings. */ |
| 7630 | case 'L': |
| 7631 | newname = RDATA_SECTION_NAME; |
| 7632 | if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8) |
| 7633 | || mips_pic == EMBEDDED_PIC) |
| 7634 | newname = ".lit8"; |
| 7635 | break; |
| 7636 | case 'F': |
| 7637 | if (mips_pic == EMBEDDED_PIC) |
| 7638 | newname = ".lit8"; |
| 7639 | else |
| 7640 | newname = RDATA_SECTION_NAME; |
| 7641 | break; |
| 7642 | case 'l': |
| 7643 | assert (!USE_GLOBAL_POINTER_OPT |
| 7644 | || g_switch_value >= 4); |
| 7645 | newname = ".lit4"; |
| 7646 | break; |
| 7647 | } |
| 7648 | new_seg = subseg_new (newname, (subsegT) 0); |
| 7649 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 7650 | bfd_set_section_flags (stdoutput, new_seg, |
| 7651 | (SEC_ALLOC |
| 7652 | | SEC_LOAD |
| 7653 | | SEC_READONLY |
| 7654 | | SEC_DATA)); |
| 7655 | frag_align (*args == 'l' ? 2 : 3, 0, 0); |
| 7656 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 7657 | && strcmp (TARGET_OS, "elf") != 0) |
| 7658 | record_alignment (new_seg, 4); |
| 7659 | else |
| 7660 | record_alignment (new_seg, *args == 'l' ? 2 : 3); |
| 7661 | if (seg == now_seg) |
| 7662 | as_bad (_("Can't use floating point insn in this section")); |
| 7663 | |
| 7664 | /* Set the argument to the current address in the |
| 7665 | section. */ |
| 7666 | offset_expr.X_op = O_symbol; |
| 7667 | offset_expr.X_add_symbol = |
| 7668 | symbol_new ("L0\001", now_seg, |
| 7669 | (valueT) frag_now_fix (), frag_now); |
| 7670 | offset_expr.X_add_number = 0; |
| 7671 | |
| 7672 | /* Put the floating point number into the section. */ |
| 7673 | p = frag_more ((int) length); |
| 7674 | memcpy (p, temp, length); |
| 7675 | |
| 7676 | /* Switch back to the original section. */ |
| 7677 | subseg_set (seg, subseg); |
| 7678 | } |
| 7679 | } |
| 7680 | continue; |
| 7681 | |
| 7682 | case 'i': /* 16 bit unsigned immediate */ |
| 7683 | case 'j': /* 16 bit signed immediate */ |
| 7684 | imm_reloc = BFD_RELOC_LO16; |
| 7685 | c = my_getSmallExpression (&imm_expr, s); |
| 7686 | if (c != S_EX_NONE) |
| 7687 | { |
| 7688 | if (c != S_EX_LO) |
| 7689 | { |
| 7690 | if (imm_expr.X_op == O_constant) |
| 7691 | imm_expr.X_add_number = |
| 7692 | (imm_expr.X_add_number >> 16) & 0xffff; |
| 7693 | else if (c == S_EX_HIGHEST) |
| 7694 | imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
| 7695 | else if (c == S_EX_HIGHER) |
| 7696 | imm_reloc = BFD_RELOC_MIPS_HIGHER; |
| 7697 | else if (c == S_EX_HI) |
| 7698 | { |
| 7699 | imm_reloc = BFD_RELOC_HI16_S; |
| 7700 | imm_unmatched_hi = true; |
| 7701 | } |
| 7702 | else |
| 7703 | imm_reloc = BFD_RELOC_HI16; |
| 7704 | } |
| 7705 | else if (imm_expr.X_op == O_constant) |
| 7706 | imm_expr.X_add_number &= 0xffff; |
| 7707 | } |
| 7708 | if (*args == 'i') |
| 7709 | { |
| 7710 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
| 7711 | || ((imm_expr.X_add_number < 0 |
| 7712 | || imm_expr.X_add_number >= 0x10000) |
| 7713 | && imm_expr.X_op == O_constant)) |
| 7714 | { |
| 7715 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && |
| 7716 | !strcmp (insn->name, insn[1].name)) |
| 7717 | break; |
| 7718 | if (imm_expr.X_op == O_constant |
| 7719 | || imm_expr.X_op == O_big) |
| 7720 | as_bad (_("16 bit expression not in range 0..65535")); |
| 7721 | } |
| 7722 | } |
| 7723 | else |
| 7724 | { |
| 7725 | int more; |
| 7726 | offsetT max; |
| 7727 | |
| 7728 | /* The upper bound should be 0x8000, but |
| 7729 | unfortunately the MIPS assembler accepts numbers |
| 7730 | from 0x8000 to 0xffff and sign extends them, and |
| 7731 | we want to be compatible. We only permit this |
| 7732 | extended range for an instruction which does not |
| 7733 | provide any further alternates, since those |
| 7734 | alternates may handle other cases. People should |
| 7735 | use the numbers they mean, rather than relying on |
| 7736 | a mysterious sign extension. */ |
| 7737 | more = (insn + 1 < &mips_opcodes[NUMOPCODES] && |
| 7738 | strcmp (insn->name, insn[1].name) == 0); |
| 7739 | if (more) |
| 7740 | max = 0x8000; |
| 7741 | else |
| 7742 | max = 0x10000; |
| 7743 | if ((c == S_EX_NONE && imm_expr.X_op != O_constant) |
| 7744 | || ((imm_expr.X_add_number < -0x8000 |
| 7745 | || imm_expr.X_add_number >= max) |
| 7746 | && imm_expr.X_op == O_constant) |
| 7747 | || (more |
| 7748 | && imm_expr.X_add_number < 0 |
| 7749 | && HAVE_64BIT_GPRS |
| 7750 | && imm_expr.X_unsigned |
| 7751 | && sizeof (imm_expr.X_add_number) <= 4)) |
| 7752 | { |
| 7753 | if (more) |
| 7754 | break; |
| 7755 | if (imm_expr.X_op == O_constant |
| 7756 | || imm_expr.X_op == O_big) |
| 7757 | as_bad (_("16 bit expression not in range -32768..32767")); |
| 7758 | } |
| 7759 | } |
| 7760 | s = expr_end; |
| 7761 | continue; |
| 7762 | |
| 7763 | case 'o': /* 16 bit offset */ |
| 7764 | c = my_getSmallExpression (&offset_expr, s); |
| 7765 | |
| 7766 | /* If this value won't fit into a 16 bit offset, then go |
| 7767 | find a macro that will generate the 32 bit offset |
| 7768 | code pattern. As a special hack, we accept the |
| 7769 | difference of two local symbols as a constant. This |
| 7770 | is required to suppose embedded PIC switches, which |
| 7771 | use an instruction which looks like |
| 7772 | lw $4,$L12-$LS12($4) |
| 7773 | The problem with handling this in a more general |
| 7774 | fashion is that the macro function doesn't expect to |
| 7775 | see anything which can be handled in a single |
| 7776 | constant instruction. */ |
| 7777 | if (c == S_EX_NONE |
| 7778 | && (offset_expr.X_op != O_constant |
| 7779 | || offset_expr.X_add_number >= 0x8000 |
| 7780 | || offset_expr.X_add_number < -0x8000) |
| 7781 | && (mips_pic != EMBEDDED_PIC |
| 7782 | || offset_expr.X_op != O_subtract |
| 7783 | || (S_GET_SEGMENT (offset_expr.X_add_symbol) |
| 7784 | != S_GET_SEGMENT (offset_expr.X_op_symbol)))) |
| 7785 | break; |
| 7786 | |
| 7787 | if (c == S_EX_HI) |
| 7788 | { |
| 7789 | if (offset_expr.X_op != O_constant) |
| 7790 | break; |
| 7791 | offset_expr.X_add_number = |
| 7792 | (offset_expr.X_add_number >> 16) & 0xffff; |
| 7793 | } |
| 7794 | offset_reloc = BFD_RELOC_LO16; |
| 7795 | s = expr_end; |
| 7796 | continue; |
| 7797 | |
| 7798 | case 'p': /* pc relative offset */ |
| 7799 | offset_reloc = BFD_RELOC_16_PCREL_S2; |
| 7800 | my_getExpression (&offset_expr, s); |
| 7801 | s = expr_end; |
| 7802 | continue; |
| 7803 | |
| 7804 | case 'u': /* upper 16 bits */ |
| 7805 | c = my_getSmallExpression (&imm_expr, s); |
| 7806 | imm_reloc = BFD_RELOC_LO16; |
| 7807 | if (c != S_EX_NONE) |
| 7808 | { |
| 7809 | if (c != S_EX_LO) |
| 7810 | { |
| 7811 | if (imm_expr.X_op == O_constant) |
| 7812 | imm_expr.X_add_number = |
| 7813 | (imm_expr.X_add_number >> 16) & 0xffff; |
| 7814 | else if (c == S_EX_HIGHEST) |
| 7815 | imm_reloc = BFD_RELOC_MIPS_HIGHEST; |
| 7816 | else if (c == S_EX_HI) |
| 7817 | { |
| 7818 | imm_reloc = BFD_RELOC_HI16_S; |
| 7819 | imm_unmatched_hi = true; |
| 7820 | } |
| 7821 | else |
| 7822 | imm_reloc = BFD_RELOC_HI16; |
| 7823 | } |
| 7824 | else if (imm_expr.X_op == O_constant) |
| 7825 | imm_expr.X_add_number &= 0xffff; |
| 7826 | } |
| 7827 | if (imm_expr.X_op == O_constant |
| 7828 | && (imm_expr.X_add_number < 0 |
| 7829 | || imm_expr.X_add_number >= 0x10000)) |
| 7830 | as_bad (_("lui expression not in range 0..65535")); |
| 7831 | s = expr_end; |
| 7832 | continue; |
| 7833 | |
| 7834 | case 'a': /* 26 bit address */ |
| 7835 | my_getExpression (&offset_expr, s); |
| 7836 | s = expr_end; |
| 7837 | offset_reloc = BFD_RELOC_MIPS_JMP; |
| 7838 | continue; |
| 7839 | |
| 7840 | case 'N': /* 3 bit branch condition code */ |
| 7841 | case 'M': /* 3 bit compare condition code */ |
| 7842 | if (strncmp (s, "$fcc", 4) != 0) |
| 7843 | break; |
| 7844 | s += 4; |
| 7845 | regno = 0; |
| 7846 | do |
| 7847 | { |
| 7848 | regno *= 10; |
| 7849 | regno += *s - '0'; |
| 7850 | ++s; |
| 7851 | } |
| 7852 | while (isdigit ((unsigned char) *s)); |
| 7853 | if (regno > 7) |
| 7854 | as_bad (_("invalid condition code register $fcc%d"), regno); |
| 7855 | if (*args == 'N') |
| 7856 | ip->insn_opcode |= regno << OP_SH_BCC; |
| 7857 | else |
| 7858 | ip->insn_opcode |= regno << OP_SH_CCC; |
| 7859 | continue; |
| 7860 | |
| 7861 | case 'H': |
| 7862 | if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) |
| 7863 | s += 2; |
| 7864 | if (isdigit ((unsigned char) *s)) |
| 7865 | { |
| 7866 | c = 0; |
| 7867 | do |
| 7868 | { |
| 7869 | c *= 10; |
| 7870 | c += *s - '0'; |
| 7871 | ++s; |
| 7872 | } |
| 7873 | while (isdigit ((unsigned char) *s)); |
| 7874 | } |
| 7875 | else |
| 7876 | c = 8; /* Invalid sel value. */ |
| 7877 | |
| 7878 | if (c > 7) |
| 7879 | as_bad (_("invalid coprocessor sub-selection value (0-7)")); |
| 7880 | ip->insn_opcode |= c; |
| 7881 | continue; |
| 7882 | |
| 7883 | default: |
| 7884 | as_bad (_("bad char = '%c'\n"), *args); |
| 7885 | internalError (); |
| 7886 | } |
| 7887 | break; |
| 7888 | } |
| 7889 | /* Args don't match. */ |
| 7890 | if (insn + 1 < &mips_opcodes[NUMOPCODES] && |
| 7891 | !strcmp (insn->name, insn[1].name)) |
| 7892 | { |
| 7893 | ++insn; |
| 7894 | s = argsStart; |
| 7895 | insn_error = _("illegal operands"); |
| 7896 | continue; |
| 7897 | } |
| 7898 | if (save_c) |
| 7899 | *(--s) = save_c; |
| 7900 | insn_error = _("illegal operands"); |
| 7901 | return; |
| 7902 | } |
| 7903 | } |
| 7904 | |
| 7905 | /* This routine assembles an instruction into its binary format when |
| 7906 | assembling for the mips16. As a side effect, it sets one of the |
| 7907 | global variables imm_reloc or offset_reloc to the type of |
| 7908 | relocation to do if one of the operands is an address expression. |
| 7909 | It also sets mips16_small and mips16_ext if the user explicitly |
| 7910 | requested a small or extended instruction. */ |
| 7911 | |
| 7912 | static void |
| 7913 | mips16_ip (str, ip) |
| 7914 | char *str; |
| 7915 | struct mips_cl_insn *ip; |
| 7916 | { |
| 7917 | char *s; |
| 7918 | const char *args; |
| 7919 | struct mips_opcode *insn; |
| 7920 | char *argsstart; |
| 7921 | unsigned int regno; |
| 7922 | unsigned int lastregno = 0; |
| 7923 | char *s_reset; |
| 7924 | |
| 7925 | insn_error = NULL; |
| 7926 | |
| 7927 | mips16_small = false; |
| 7928 | mips16_ext = false; |
| 7929 | |
| 7930 | for (s = str; islower ((unsigned char) *s); ++s) |
| 7931 | ; |
| 7932 | switch (*s) |
| 7933 | { |
| 7934 | case '\0': |
| 7935 | break; |
| 7936 | |
| 7937 | case ' ': |
| 7938 | *s++ = '\0'; |
| 7939 | break; |
| 7940 | |
| 7941 | case '.': |
| 7942 | if (s[1] == 't' && s[2] == ' ') |
| 7943 | { |
| 7944 | *s = '\0'; |
| 7945 | mips16_small = true; |
| 7946 | s += 3; |
| 7947 | break; |
| 7948 | } |
| 7949 | else if (s[1] == 'e' && s[2] == ' ') |
| 7950 | { |
| 7951 | *s = '\0'; |
| 7952 | mips16_ext = true; |
| 7953 | s += 3; |
| 7954 | break; |
| 7955 | } |
| 7956 | /* Fall through. */ |
| 7957 | default: |
| 7958 | insn_error = _("unknown opcode"); |
| 7959 | return; |
| 7960 | } |
| 7961 | |
| 7962 | if (mips_opts.noautoextend && ! mips16_ext) |
| 7963 | mips16_small = true; |
| 7964 | |
| 7965 | if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL) |
| 7966 | { |
| 7967 | insn_error = _("unrecognized opcode"); |
| 7968 | return; |
| 7969 | } |
| 7970 | |
| 7971 | argsstart = s; |
| 7972 | for (;;) |
| 7973 | { |
| 7974 | assert (strcmp (insn->name, str) == 0); |
| 7975 | |
| 7976 | ip->insn_mo = insn; |
| 7977 | ip->insn_opcode = insn->match; |
| 7978 | ip->use_extend = false; |
| 7979 | imm_expr.X_op = O_absent; |
| 7980 | imm_reloc = BFD_RELOC_UNUSED; |
| 7981 | offset_expr.X_op = O_absent; |
| 7982 | offset_reloc = BFD_RELOC_UNUSED; |
| 7983 | for (args = insn->args; 1; ++args) |
| 7984 | { |
| 7985 | int c; |
| 7986 | |
| 7987 | if (*s == ' ') |
| 7988 | ++s; |
| 7989 | |
| 7990 | /* In this switch statement we call break if we did not find |
| 7991 | a match, continue if we did find a match, or return if we |
| 7992 | are done. */ |
| 7993 | |
| 7994 | c = *args; |
| 7995 | switch (c) |
| 7996 | { |
| 7997 | case '\0': |
| 7998 | if (*s == '\0') |
| 7999 | { |
| 8000 | /* Stuff the immediate value in now, if we can. */ |
| 8001 | if (imm_expr.X_op == O_constant |
| 8002 | && imm_reloc > BFD_RELOC_UNUSED |
| 8003 | && insn->pinfo != INSN_MACRO) |
| 8004 | { |
| 8005 | mips16_immed ((char *) NULL, 0, |
| 8006 | imm_reloc - BFD_RELOC_UNUSED, |
| 8007 | imm_expr.X_add_number, true, mips16_small, |
| 8008 | mips16_ext, &ip->insn_opcode, |
| 8009 | &ip->use_extend, &ip->extend); |
| 8010 | imm_expr.X_op = O_absent; |
| 8011 | imm_reloc = BFD_RELOC_UNUSED; |
| 8012 | } |
| 8013 | |
| 8014 | return; |
| 8015 | } |
| 8016 | break; |
| 8017 | |
| 8018 | case ',': |
| 8019 | if (*s++ == c) |
| 8020 | continue; |
| 8021 | s--; |
| 8022 | switch (*++args) |
| 8023 | { |
| 8024 | case 'v': |
| 8025 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; |
| 8026 | continue; |
| 8027 | case 'w': |
| 8028 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; |
| 8029 | continue; |
| 8030 | } |
| 8031 | break; |
| 8032 | |
| 8033 | case '(': |
| 8034 | case ')': |
| 8035 | if (*s++ == c) |
| 8036 | continue; |
| 8037 | break; |
| 8038 | |
| 8039 | case 'v': |
| 8040 | case 'w': |
| 8041 | if (s[0] != '$') |
| 8042 | { |
| 8043 | if (c == 'v') |
| 8044 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RX; |
| 8045 | else |
| 8046 | ip->insn_opcode |= lastregno << MIPS16OP_SH_RY; |
| 8047 | ++args; |
| 8048 | continue; |
| 8049 | } |
| 8050 | /* Fall through. */ |
| 8051 | case 'x': |
| 8052 | case 'y': |
| 8053 | case 'z': |
| 8054 | case 'Z': |
| 8055 | case '0': |
| 8056 | case 'S': |
| 8057 | case 'R': |
| 8058 | case 'X': |
| 8059 | case 'Y': |
| 8060 | if (s[0] != '$') |
| 8061 | break; |
| 8062 | s_reset = s; |
| 8063 | if (isdigit ((unsigned char) s[1])) |
| 8064 | { |
| 8065 | ++s; |
| 8066 | regno = 0; |
| 8067 | do |
| 8068 | { |
| 8069 | regno *= 10; |
| 8070 | regno += *s - '0'; |
| 8071 | ++s; |
| 8072 | } |
| 8073 | while (isdigit ((unsigned char) *s)); |
| 8074 | if (regno > 31) |
| 8075 | { |
| 8076 | as_bad (_("invalid register number (%d)"), regno); |
| 8077 | regno = 2; |
| 8078 | } |
| 8079 | } |
| 8080 | else |
| 8081 | { |
| 8082 | if (s[1] == 'f' && s[2] == 'p') |
| 8083 | { |
| 8084 | s += 3; |
| 8085 | regno = FP; |
| 8086 | } |
| 8087 | else if (s[1] == 's' && s[2] == 'p') |
| 8088 | { |
| 8089 | s += 3; |
| 8090 | regno = SP; |
| 8091 | } |
| 8092 | else if (s[1] == 'g' && s[2] == 'p') |
| 8093 | { |
| 8094 | s += 3; |
| 8095 | regno = GP; |
| 8096 | } |
| 8097 | else if (s[1] == 'a' && s[2] == 't') |
| 8098 | { |
| 8099 | s += 3; |
| 8100 | regno = AT; |
| 8101 | } |
| 8102 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '0') |
| 8103 | { |
| 8104 | s += 4; |
| 8105 | regno = KT0; |
| 8106 | } |
| 8107 | else if (s[1] == 'k' && s[2] == 't' && s[3] == '1') |
| 8108 | { |
| 8109 | s += 4; |
| 8110 | regno = KT1; |
| 8111 | } |
| 8112 | else |
| 8113 | break; |
| 8114 | } |
| 8115 | |
| 8116 | if (*s == ' ') |
| 8117 | ++s; |
| 8118 | if (args[1] != *s) |
| 8119 | { |
| 8120 | if (c == 'v' || c == 'w') |
| 8121 | { |
| 8122 | regno = mips16_to_32_reg_map[lastregno]; |
| 8123 | s = s_reset; |
| 8124 | args++; |
| 8125 | } |
| 8126 | } |
| 8127 | |
| 8128 | switch (c) |
| 8129 | { |
| 8130 | case 'x': |
| 8131 | case 'y': |
| 8132 | case 'z': |
| 8133 | case 'v': |
| 8134 | case 'w': |
| 8135 | case 'Z': |
| 8136 | regno = mips32_to_16_reg_map[regno]; |
| 8137 | break; |
| 8138 | |
| 8139 | case '0': |
| 8140 | if (regno != 0) |
| 8141 | regno = ILLEGAL_REG; |
| 8142 | break; |
| 8143 | |
| 8144 | case 'S': |
| 8145 | if (regno != SP) |
| 8146 | regno = ILLEGAL_REG; |
| 8147 | break; |
| 8148 | |
| 8149 | case 'R': |
| 8150 | if (regno != RA) |
| 8151 | regno = ILLEGAL_REG; |
| 8152 | break; |
| 8153 | |
| 8154 | case 'X': |
| 8155 | case 'Y': |
| 8156 | if (regno == AT && ! mips_opts.noat) |
| 8157 | as_warn (_("used $at without \".set noat\"")); |
| 8158 | break; |
| 8159 | |
| 8160 | default: |
| 8161 | internalError (); |
| 8162 | } |
| 8163 | |
| 8164 | if (regno == ILLEGAL_REG) |
| 8165 | break; |
| 8166 | |
| 8167 | switch (c) |
| 8168 | { |
| 8169 | case 'x': |
| 8170 | case 'v': |
| 8171 | ip->insn_opcode |= regno << MIPS16OP_SH_RX; |
| 8172 | break; |
| 8173 | case 'y': |
| 8174 | case 'w': |
| 8175 | ip->insn_opcode |= regno << MIPS16OP_SH_RY; |
| 8176 | break; |
| 8177 | case 'z': |
| 8178 | ip->insn_opcode |= regno << MIPS16OP_SH_RZ; |
| 8179 | break; |
| 8180 | case 'Z': |
| 8181 | ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z; |
| 8182 | case '0': |
| 8183 | case 'S': |
| 8184 | case 'R': |
| 8185 | break; |
| 8186 | case 'X': |
| 8187 | ip->insn_opcode |= regno << MIPS16OP_SH_REGR32; |
| 8188 | break; |
| 8189 | case 'Y': |
| 8190 | regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3); |
| 8191 | ip->insn_opcode |= regno << MIPS16OP_SH_REG32R; |
| 8192 | break; |
| 8193 | default: |
| 8194 | internalError (); |
| 8195 | } |
| 8196 | |
| 8197 | lastregno = regno; |
| 8198 | continue; |
| 8199 | |
| 8200 | case 'P': |
| 8201 | if (strncmp (s, "$pc", 3) == 0) |
| 8202 | { |
| 8203 | s += 3; |
| 8204 | continue; |
| 8205 | } |
| 8206 | break; |
| 8207 | |
| 8208 | case '<': |
| 8209 | case '>': |
| 8210 | case '[': |
| 8211 | case ']': |
| 8212 | case '4': |
| 8213 | case '5': |
| 8214 | case 'H': |
| 8215 | case 'W': |
| 8216 | case 'D': |
| 8217 | case 'j': |
| 8218 | case '8': |
| 8219 | case 'V': |
| 8220 | case 'C': |
| 8221 | case 'U': |
| 8222 | case 'k': |
| 8223 | case 'K': |
| 8224 | if (s[0] == '%' |
| 8225 | && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0) |
| 8226 | { |
| 8227 | /* This is %gprel(SYMBOL). We need to read SYMBOL, |
| 8228 | and generate the appropriate reloc. If the text |
| 8229 | inside %gprel is not a symbol name with an |
| 8230 | optional offset, then we generate a normal reloc |
| 8231 | and will probably fail later. */ |
| 8232 | my_getExpression (&imm_expr, s + sizeof "%gprel" - 1); |
| 8233 | if (imm_expr.X_op == O_symbol) |
| 8234 | { |
| 8235 | mips16_ext = true; |
| 8236 | imm_reloc = BFD_RELOC_MIPS16_GPREL; |
| 8237 | s = expr_end; |
| 8238 | ip->use_extend = true; |
| 8239 | ip->extend = 0; |
| 8240 | continue; |
| 8241 | } |
| 8242 | } |
| 8243 | else |
| 8244 | { |
| 8245 | /* Just pick up a normal expression. */ |
| 8246 | my_getExpression (&imm_expr, s); |
| 8247 | } |
| 8248 | |
| 8249 | if (imm_expr.X_op == O_register) |
| 8250 | { |
| 8251 | /* What we thought was an expression turned out to |
| 8252 | be a register. */ |
| 8253 | |
| 8254 | if (s[0] == '(' && args[1] == '(') |
| 8255 | { |
| 8256 | /* It looks like the expression was omitted |
| 8257 | before a register indirection, which means |
| 8258 | that the expression is implicitly zero. We |
| 8259 | still set up imm_expr, so that we handle |
| 8260 | explicit extensions correctly. */ |
| 8261 | imm_expr.X_op = O_constant; |
| 8262 | imm_expr.X_add_number = 0; |
| 8263 | imm_reloc = (int) BFD_RELOC_UNUSED + c; |
| 8264 | continue; |
| 8265 | } |
| 8266 | |
| 8267 | break; |
| 8268 | } |
| 8269 | |
| 8270 | /* We need to relax this instruction. */ |
| 8271 | imm_reloc = (int) BFD_RELOC_UNUSED + c; |
| 8272 | s = expr_end; |
| 8273 | continue; |
| 8274 | |
| 8275 | case 'p': |
| 8276 | case 'q': |
| 8277 | case 'A': |
| 8278 | case 'B': |
| 8279 | case 'E': |
| 8280 | /* We use offset_reloc rather than imm_reloc for the PC |
| 8281 | relative operands. This lets macros with both |
| 8282 | immediate and address operands work correctly. */ |
| 8283 | my_getExpression (&offset_expr, s); |
| 8284 | |
| 8285 | if (offset_expr.X_op == O_register) |
| 8286 | break; |
| 8287 | |
| 8288 | /* We need to relax this instruction. */ |
| 8289 | offset_reloc = (int) BFD_RELOC_UNUSED + c; |
| 8290 | s = expr_end; |
| 8291 | continue; |
| 8292 | |
| 8293 | case '6': /* break code */ |
| 8294 | my_getExpression (&imm_expr, s); |
| 8295 | check_absolute_expr (ip, &imm_expr); |
| 8296 | if ((unsigned long) imm_expr.X_add_number > 63) |
| 8297 | { |
| 8298 | as_warn (_("Invalid value for `%s' (%lu)"), |
| 8299 | ip->insn_mo->name, |
| 8300 | (unsigned long) imm_expr.X_add_number); |
| 8301 | imm_expr.X_add_number &= 0x3f; |
| 8302 | } |
| 8303 | ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6; |
| 8304 | imm_expr.X_op = O_absent; |
| 8305 | s = expr_end; |
| 8306 | continue; |
| 8307 | |
| 8308 | case 'a': /* 26 bit address */ |
| 8309 | my_getExpression (&offset_expr, s); |
| 8310 | s = expr_end; |
| 8311 | offset_reloc = BFD_RELOC_MIPS16_JMP; |
| 8312 | ip->insn_opcode <<= 16; |
| 8313 | continue; |
| 8314 | |
| 8315 | case 'l': /* register list for entry macro */ |
| 8316 | case 'L': /* register list for exit macro */ |
| 8317 | { |
| 8318 | int mask; |
| 8319 | |
| 8320 | if (c == 'l') |
| 8321 | mask = 0; |
| 8322 | else |
| 8323 | mask = 7 << 3; |
| 8324 | while (*s != '\0') |
| 8325 | { |
| 8326 | int freg, reg1, reg2; |
| 8327 | |
| 8328 | while (*s == ' ' || *s == ',') |
| 8329 | ++s; |
| 8330 | if (*s != '$') |
| 8331 | { |
| 8332 | as_bad (_("can't parse register list")); |
| 8333 | break; |
| 8334 | } |
| 8335 | ++s; |
| 8336 | if (*s != 'f') |
| 8337 | freg = 0; |
| 8338 | else |
| 8339 | { |
| 8340 | freg = 1; |
| 8341 | ++s; |
| 8342 | } |
| 8343 | reg1 = 0; |
| 8344 | while (isdigit ((unsigned char) *s)) |
| 8345 | { |
| 8346 | reg1 *= 10; |
| 8347 | reg1 += *s - '0'; |
| 8348 | ++s; |
| 8349 | } |
| 8350 | if (*s == ' ') |
| 8351 | ++s; |
| 8352 | if (*s != '-') |
| 8353 | reg2 = reg1; |
| 8354 | else |
| 8355 | { |
| 8356 | ++s; |
| 8357 | if (*s != '$') |
| 8358 | break; |
| 8359 | ++s; |
| 8360 | if (freg) |
| 8361 | { |
| 8362 | if (*s == 'f') |
| 8363 | ++s; |
| 8364 | else |
| 8365 | { |
| 8366 | as_bad (_("invalid register list")); |
| 8367 | break; |
| 8368 | } |
| 8369 | } |
| 8370 | reg2 = 0; |
| 8371 | while (isdigit ((unsigned char) *s)) |
| 8372 | { |
| 8373 | reg2 *= 10; |
| 8374 | reg2 += *s - '0'; |
| 8375 | ++s; |
| 8376 | } |
| 8377 | } |
| 8378 | if (freg && reg1 == 0 && reg2 == 0 && c == 'L') |
| 8379 | { |
| 8380 | mask &= ~ (7 << 3); |
| 8381 | mask |= 5 << 3; |
| 8382 | } |
| 8383 | else if (freg && reg1 == 0 && reg2 == 1 && c == 'L') |
| 8384 | { |
| 8385 | mask &= ~ (7 << 3); |
| 8386 | mask |= 6 << 3; |
| 8387 | } |
| 8388 | else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L') |
| 8389 | mask |= (reg2 - 3) << 3; |
| 8390 | else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17) |
| 8391 | mask |= (reg2 - 15) << 1; |
| 8392 | else if (reg1 == 31 && reg2 == 31) |
| 8393 | mask |= 1; |
| 8394 | else |
| 8395 | { |
| 8396 | as_bad (_("invalid register list")); |
| 8397 | break; |
| 8398 | } |
| 8399 | } |
| 8400 | /* The mask is filled in in the opcode table for the |
| 8401 | benefit of the disassembler. We remove it before |
| 8402 | applying the actual mask. */ |
| 8403 | ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6); |
| 8404 | ip->insn_opcode |= mask << MIPS16OP_SH_IMM6; |
| 8405 | } |
| 8406 | continue; |
| 8407 | |
| 8408 | case 'e': /* extend code */ |
| 8409 | my_getExpression (&imm_expr, s); |
| 8410 | check_absolute_expr (ip, &imm_expr); |
| 8411 | if ((unsigned long) imm_expr.X_add_number > 0x7ff) |
| 8412 | { |
| 8413 | as_warn (_("Invalid value for `%s' (%lu)"), |
| 8414 | ip->insn_mo->name, |
| 8415 | (unsigned long) imm_expr.X_add_number); |
| 8416 | imm_expr.X_add_number &= 0x7ff; |
| 8417 | } |
| 8418 | ip->insn_opcode |= imm_expr.X_add_number; |
| 8419 | imm_expr.X_op = O_absent; |
| 8420 | s = expr_end; |
| 8421 | continue; |
| 8422 | |
| 8423 | default: |
| 8424 | internalError (); |
| 8425 | } |
| 8426 | break; |
| 8427 | } |
| 8428 | |
| 8429 | /* Args don't match. */ |
| 8430 | if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] && |
| 8431 | strcmp (insn->name, insn[1].name) == 0) |
| 8432 | { |
| 8433 | ++insn; |
| 8434 | s = argsstart; |
| 8435 | continue; |
| 8436 | } |
| 8437 | |
| 8438 | insn_error = _("illegal operands"); |
| 8439 | |
| 8440 | return; |
| 8441 | } |
| 8442 | } |
| 8443 | |
| 8444 | /* This structure holds information we know about a mips16 immediate |
| 8445 | argument type. */ |
| 8446 | |
| 8447 | struct mips16_immed_operand |
| 8448 | { |
| 8449 | /* The type code used in the argument string in the opcode table. */ |
| 8450 | int type; |
| 8451 | /* The number of bits in the short form of the opcode. */ |
| 8452 | int nbits; |
| 8453 | /* The number of bits in the extended form of the opcode. */ |
| 8454 | int extbits; |
| 8455 | /* The amount by which the short form is shifted when it is used; |
| 8456 | for example, the sw instruction has a shift count of 2. */ |
| 8457 | int shift; |
| 8458 | /* The amount by which the short form is shifted when it is stored |
| 8459 | into the instruction code. */ |
| 8460 | int op_shift; |
| 8461 | /* Non-zero if the short form is unsigned. */ |
| 8462 | int unsp; |
| 8463 | /* Non-zero if the extended form is unsigned. */ |
| 8464 | int extu; |
| 8465 | /* Non-zero if the value is PC relative. */ |
| 8466 | int pcrel; |
| 8467 | }; |
| 8468 | |
| 8469 | /* The mips16 immediate operand types. */ |
| 8470 | |
| 8471 | static const struct mips16_immed_operand mips16_immed_operands[] = |
| 8472 | { |
| 8473 | { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, |
| 8474 | { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 }, |
| 8475 | { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 }, |
| 8476 | { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 }, |
| 8477 | { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 }, |
| 8478 | { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 }, |
| 8479 | { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 }, |
| 8480 | { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 }, |
| 8481 | { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 }, |
| 8482 | { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 }, |
| 8483 | { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 }, |
| 8484 | { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 }, |
| 8485 | { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 }, |
| 8486 | { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 }, |
| 8487 | { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 }, |
| 8488 | { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 }, |
| 8489 | { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, |
| 8490 | { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 }, |
| 8491 | { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 }, |
| 8492 | { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 }, |
| 8493 | { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 } |
| 8494 | }; |
| 8495 | |
| 8496 | #define MIPS16_NUM_IMMED \ |
| 8497 | (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0]) |
| 8498 | |
| 8499 | /* Handle a mips16 instruction with an immediate value. This or's the |
| 8500 | small immediate value into *INSN. It sets *USE_EXTEND to indicate |
| 8501 | whether an extended value is needed; if one is needed, it sets |
| 8502 | *EXTEND to the value. The argument type is TYPE. The value is VAL. |
| 8503 | If SMALL is true, an unextended opcode was explicitly requested. |
| 8504 | If EXT is true, an extended opcode was explicitly requested. If |
| 8505 | WARN is true, warn if EXT does not match reality. */ |
| 8506 | |
| 8507 | static void |
| 8508 | mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend, |
| 8509 | extend) |
| 8510 | char *file; |
| 8511 | unsigned int line; |
| 8512 | int type; |
| 8513 | offsetT val; |
| 8514 | boolean warn; |
| 8515 | boolean small; |
| 8516 | boolean ext; |
| 8517 | unsigned long *insn; |
| 8518 | boolean *use_extend; |
| 8519 | unsigned short *extend; |
| 8520 | { |
| 8521 | register const struct mips16_immed_operand *op; |
| 8522 | int mintiny, maxtiny; |
| 8523 | boolean needext; |
| 8524 | |
| 8525 | op = mips16_immed_operands; |
| 8526 | while (op->type != type) |
| 8527 | { |
| 8528 | ++op; |
| 8529 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
| 8530 | } |
| 8531 | |
| 8532 | if (op->unsp) |
| 8533 | { |
| 8534 | if (type == '<' || type == '>' || type == '[' || type == ']') |
| 8535 | { |
| 8536 | mintiny = 1; |
| 8537 | maxtiny = 1 << op->nbits; |
| 8538 | } |
| 8539 | else |
| 8540 | { |
| 8541 | mintiny = 0; |
| 8542 | maxtiny = (1 << op->nbits) - 1; |
| 8543 | } |
| 8544 | } |
| 8545 | else |
| 8546 | { |
| 8547 | mintiny = - (1 << (op->nbits - 1)); |
| 8548 | maxtiny = (1 << (op->nbits - 1)) - 1; |
| 8549 | } |
| 8550 | |
| 8551 | /* Branch offsets have an implicit 0 in the lowest bit. */ |
| 8552 | if (type == 'p' || type == 'q') |
| 8553 | val /= 2; |
| 8554 | |
| 8555 | if ((val & ((1 << op->shift) - 1)) != 0 |
| 8556 | || val < (mintiny << op->shift) |
| 8557 | || val > (maxtiny << op->shift)) |
| 8558 | needext = true; |
| 8559 | else |
| 8560 | needext = false; |
| 8561 | |
| 8562 | if (warn && ext && ! needext) |
| 8563 | as_warn_where (file, line, |
| 8564 | _("extended operand requested but not required")); |
| 8565 | if (small && needext) |
| 8566 | as_bad_where (file, line, _("invalid unextended operand value")); |
| 8567 | |
| 8568 | if (small || (! ext && ! needext)) |
| 8569 | { |
| 8570 | int insnval; |
| 8571 | |
| 8572 | *use_extend = false; |
| 8573 | insnval = ((val >> op->shift) & ((1 << op->nbits) - 1)); |
| 8574 | insnval <<= op->op_shift; |
| 8575 | *insn |= insnval; |
| 8576 | } |
| 8577 | else |
| 8578 | { |
| 8579 | long minext, maxext; |
| 8580 | int extval; |
| 8581 | |
| 8582 | if (op->extu) |
| 8583 | { |
| 8584 | minext = 0; |
| 8585 | maxext = (1 << op->extbits) - 1; |
| 8586 | } |
| 8587 | else |
| 8588 | { |
| 8589 | minext = - (1 << (op->extbits - 1)); |
| 8590 | maxext = (1 << (op->extbits - 1)) - 1; |
| 8591 | } |
| 8592 | if (val < minext || val > maxext) |
| 8593 | as_bad_where (file, line, |
| 8594 | _("operand value out of range for instruction")); |
| 8595 | |
| 8596 | *use_extend = true; |
| 8597 | if (op->extbits == 16) |
| 8598 | { |
| 8599 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); |
| 8600 | val &= 0x1f; |
| 8601 | } |
| 8602 | else if (op->extbits == 15) |
| 8603 | { |
| 8604 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); |
| 8605 | val &= 0xf; |
| 8606 | } |
| 8607 | else |
| 8608 | { |
| 8609 | extval = ((val & 0x1f) << 6) | (val & 0x20); |
| 8610 | val = 0; |
| 8611 | } |
| 8612 | |
| 8613 | *extend = (unsigned short) extval; |
| 8614 | *insn |= val; |
| 8615 | } |
| 8616 | } |
| 8617 | \f |
| 8618 | |
| 8619 | static int |
| 8620 | my_getSmallExpression (ep, str) |
| 8621 | expressionS *ep; |
| 8622 | char *str; |
| 8623 | { |
| 8624 | char *sp; |
| 8625 | char *oldstr = str; |
| 8626 | int c = S_EX_NONE; |
| 8627 | |
| 8628 | if (*str == ' ') |
| 8629 | str++; |
| 8630 | if (*str == '(') |
| 8631 | c = S_EX_NONE; |
| 8632 | else if (str[0] == '%' |
| 8633 | && tolower(str[1]) == 'l' |
| 8634 | && tolower(str[2]) == 'o' |
| 8635 | && str[3] == '(') |
| 8636 | { |
| 8637 | c = S_EX_LO; |
| 8638 | str += sizeof ("%lo(") - 2; |
| 8639 | } |
| 8640 | else if (str[0] == '%' |
| 8641 | && tolower(str[1]) == 'h' |
| 8642 | && tolower(str[2]) == 'i' |
| 8643 | && str[3] == '(') |
| 8644 | { |
| 8645 | c = S_EX_HI; |
| 8646 | str += sizeof ("%hi(") - 2; |
| 8647 | } |
| 8648 | else if (str[0] == '%' |
| 8649 | && tolower(str[1]) == 'h' |
| 8650 | && tolower(str[2]) == 'i' |
| 8651 | && tolower(str[3]) == 'g' |
| 8652 | && tolower(str[4]) == 'h' |
| 8653 | && tolower(str[5]) == 'e' |
| 8654 | && tolower(str[6]) == 'r' |
| 8655 | && str[7] == '(') |
| 8656 | { |
| 8657 | c = S_EX_HIGHER; |
| 8658 | str += sizeof ("%higher(") - 2; |
| 8659 | } |
| 8660 | else if (str[0] == '%' |
| 8661 | && tolower(str[1]) == 'h' |
| 8662 | && tolower(str[2]) == 'i' |
| 8663 | && tolower(str[3]) == 'g' |
| 8664 | && tolower(str[4]) == 'h' |
| 8665 | && tolower(str[5]) == 'e' |
| 8666 | && tolower(str[6]) == 's' |
| 8667 | && tolower(str[7]) == 't' |
| 8668 | && str[8] == '(') |
| 8669 | { |
| 8670 | c = S_EX_HIGHEST; |
| 8671 | str += sizeof ("%highest(") - 2; |
| 8672 | } |
| 8673 | /* currently unsupported */ |
| 8674 | #if 0 |
| 8675 | else if (str[0] == '%' |
| 8676 | && tolower(str[1]) == 'g' |
| 8677 | && tolower(str[2]) == 'p' |
| 8678 | && tolower(str[3]) == '_' |
| 8679 | && tolower(str[4]) == 'r' |
| 8680 | && tolower(str[5]) == 'e' |
| 8681 | && tolower(str[6]) == 'l' |
| 8682 | && str[7] == '(') |
| 8683 | { |
| 8684 | c = S_EX_GPREL; |
| 8685 | str += sizeof ("%gp_rel(") - 2; |
| 8686 | } |
| 8687 | else if (str[0] == '%' |
| 8688 | && tolower(str[1]) == 'n' |
| 8689 | && tolower(str[2]) == 'e' |
| 8690 | && tolower(str[3]) == 'g' |
| 8691 | && str[4] == '(') |
| 8692 | { |
| 8693 | c = S_EX_NEG; |
| 8694 | str += sizeof ("%neg(") - 2; |
| 8695 | } |
| 8696 | #endif |
| 8697 | else |
| 8698 | { |
| 8699 | my_getExpression (ep, str); |
| 8700 | return c; |
| 8701 | } |
| 8702 | |
| 8703 | /* |
| 8704 | * A small expression may be followed by a base register. |
| 8705 | * Scan to the end of this operand, and then back over a possible |
| 8706 | * base register. Then scan the small expression up to that |
| 8707 | * point. (Based on code in sparc.c...) |
| 8708 | */ |
| 8709 | for (sp = str; *sp && *sp != ','; sp++) |
| 8710 | ; |
| 8711 | if (sp - 4 >= str && sp[-1] == ')') |
| 8712 | { |
| 8713 | if (isdigit ((unsigned char) sp[-2])) |
| 8714 | { |
| 8715 | for (sp -= 3; sp >= str && isdigit ((unsigned char) *sp); sp--) |
| 8716 | ; |
| 8717 | if (*sp == '$' && sp > str && sp[-1] == '(') |
| 8718 | { |
| 8719 | sp--; |
| 8720 | goto do_it; |
| 8721 | } |
| 8722 | } |
| 8723 | else if (sp - 5 >= str |
| 8724 | && sp[-5] == '(' |
| 8725 | && sp[-4] == '$' |
| 8726 | && ((sp[-3] == 'f' && sp[-2] == 'p') |
| 8727 | || (sp[-3] == 's' && sp[-2] == 'p') |
| 8728 | || (sp[-3] == 'g' && sp[-2] == 'p') |
| 8729 | || (sp[-3] == 'a' && sp[-2] == 't'))) |
| 8730 | { |
| 8731 | sp -= 5; |
| 8732 | do_it: |
| 8733 | if (sp == str) |
| 8734 | { |
| 8735 | /* no expression means zero offset */ |
| 8736 | if (c != S_EX_NONE) |
| 8737 | { |
| 8738 | /* %xx(reg) is an error */ |
| 8739 | ep->X_op = O_absent; |
| 8740 | expr_end = oldstr; |
| 8741 | } |
| 8742 | else |
| 8743 | { |
| 8744 | ep->X_op = O_constant; |
| 8745 | expr_end = sp; |
| 8746 | } |
| 8747 | ep->X_add_symbol = NULL; |
| 8748 | ep->X_op_symbol = NULL; |
| 8749 | ep->X_add_number = 0; |
| 8750 | } |
| 8751 | else |
| 8752 | { |
| 8753 | *sp = '\0'; |
| 8754 | my_getExpression (ep, str); |
| 8755 | *sp = '('; |
| 8756 | } |
| 8757 | return c; |
| 8758 | } |
| 8759 | } |
| 8760 | my_getExpression (ep, str); |
| 8761 | |
| 8762 | /* => %highest, %higher, %hi, %lo, %gprel, %neg encountered */ |
| 8763 | return c; |
| 8764 | } |
| 8765 | |
| 8766 | static void |
| 8767 | my_getExpression (ep, str) |
| 8768 | expressionS *ep; |
| 8769 | char *str; |
| 8770 | { |
| 8771 | char *save_in; |
| 8772 | valueT val; |
| 8773 | |
| 8774 | save_in = input_line_pointer; |
| 8775 | input_line_pointer = str; |
| 8776 | expression (ep); |
| 8777 | expr_end = input_line_pointer; |
| 8778 | input_line_pointer = save_in; |
| 8779 | |
| 8780 | /* If we are in mips16 mode, and this is an expression based on `.', |
| 8781 | then we bump the value of the symbol by 1 since that is how other |
| 8782 | text symbols are handled. We don't bother to handle complex |
| 8783 | expressions, just `.' plus or minus a constant. */ |
| 8784 | if (mips_opts.mips16 |
| 8785 | && ep->X_op == O_symbol |
| 8786 | && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0 |
| 8787 | && S_GET_SEGMENT (ep->X_add_symbol) == now_seg |
| 8788 | && symbol_get_frag (ep->X_add_symbol) == frag_now |
| 8789 | && symbol_constant_p (ep->X_add_symbol) |
| 8790 | && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ()) |
| 8791 | S_SET_VALUE (ep->X_add_symbol, val + 1); |
| 8792 | } |
| 8793 | |
| 8794 | /* Turn a string in input_line_pointer into a floating point constant |
| 8795 | of type TYPE, and store the appropriate bytes in *LITP. The number |
| 8796 | of LITTLENUMS emitted is stored in *SIZEP. An error message is |
| 8797 | returned, or NULL on OK. */ |
| 8798 | |
| 8799 | char * |
| 8800 | md_atof (type, litP, sizeP) |
| 8801 | int type; |
| 8802 | char *litP; |
| 8803 | int *sizeP; |
| 8804 | { |
| 8805 | int prec; |
| 8806 | LITTLENUM_TYPE words[4]; |
| 8807 | char *t; |
| 8808 | int i; |
| 8809 | |
| 8810 | switch (type) |
| 8811 | { |
| 8812 | case 'f': |
| 8813 | prec = 2; |
| 8814 | break; |
| 8815 | |
| 8816 | case 'd': |
| 8817 | prec = 4; |
| 8818 | break; |
| 8819 | |
| 8820 | default: |
| 8821 | *sizeP = 0; |
| 8822 | return _("bad call to md_atof"); |
| 8823 | } |
| 8824 | |
| 8825 | t = atof_ieee (input_line_pointer, type, words); |
| 8826 | if (t) |
| 8827 | input_line_pointer = t; |
| 8828 | |
| 8829 | *sizeP = prec * 2; |
| 8830 | |
| 8831 | if (! target_big_endian) |
| 8832 | { |
| 8833 | for (i = prec - 1; i >= 0; i--) |
| 8834 | { |
| 8835 | md_number_to_chars (litP, (valueT) words[i], 2); |
| 8836 | litP += 2; |
| 8837 | } |
| 8838 | } |
| 8839 | else |
| 8840 | { |
| 8841 | for (i = 0; i < prec; i++) |
| 8842 | { |
| 8843 | md_number_to_chars (litP, (valueT) words[i], 2); |
| 8844 | litP += 2; |
| 8845 | } |
| 8846 | } |
| 8847 | |
| 8848 | return NULL; |
| 8849 | } |
| 8850 | |
| 8851 | void |
| 8852 | md_number_to_chars (buf, val, n) |
| 8853 | char *buf; |
| 8854 | valueT val; |
| 8855 | int n; |
| 8856 | { |
| 8857 | if (target_big_endian) |
| 8858 | number_to_chars_bigendian (buf, val, n); |
| 8859 | else |
| 8860 | number_to_chars_littleendian (buf, val, n); |
| 8861 | } |
| 8862 | \f |
| 8863 | CONST char *md_shortopts = "nO::g::G:"; |
| 8864 | |
| 8865 | struct option md_longopts[] = |
| 8866 | { |
| 8867 | #define OPTION_MIPS1 (OPTION_MD_BASE + 1) |
| 8868 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
| 8869 | {"mips1", no_argument, NULL, OPTION_MIPS1}, |
| 8870 | #define OPTION_MIPS2 (OPTION_MD_BASE + 2) |
| 8871 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
| 8872 | #define OPTION_MIPS3 (OPTION_MD_BASE + 3) |
| 8873 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
| 8874 | #define OPTION_MIPS4 (OPTION_MD_BASE + 4) |
| 8875 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
| 8876 | #define OPTION_MCPU (OPTION_MD_BASE + 5) |
| 8877 | {"mcpu", required_argument, NULL, OPTION_MCPU}, |
| 8878 | #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6) |
| 8879 | {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC}, |
| 8880 | #define OPTION_TRAP (OPTION_MD_BASE + 7) |
| 8881 | {"trap", no_argument, NULL, OPTION_TRAP}, |
| 8882 | {"no-break", no_argument, NULL, OPTION_TRAP}, |
| 8883 | #define OPTION_BREAK (OPTION_MD_BASE + 8) |
| 8884 | {"break", no_argument, NULL, OPTION_BREAK}, |
| 8885 | {"no-trap", no_argument, NULL, OPTION_BREAK}, |
| 8886 | #define OPTION_EB (OPTION_MD_BASE + 9) |
| 8887 | {"EB", no_argument, NULL, OPTION_EB}, |
| 8888 | #define OPTION_EL (OPTION_MD_BASE + 10) |
| 8889 | {"EL", no_argument, NULL, OPTION_EL}, |
| 8890 | #define OPTION_M4650 (OPTION_MD_BASE + 11) |
| 8891 | {"m4650", no_argument, NULL, OPTION_M4650}, |
| 8892 | #define OPTION_NO_M4650 (OPTION_MD_BASE + 12) |
| 8893 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
| 8894 | #define OPTION_M4010 (OPTION_MD_BASE + 13) |
| 8895 | {"m4010", no_argument, NULL, OPTION_M4010}, |
| 8896 | #define OPTION_NO_M4010 (OPTION_MD_BASE + 14) |
| 8897 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
| 8898 | #define OPTION_M4100 (OPTION_MD_BASE + 15) |
| 8899 | {"m4100", no_argument, NULL, OPTION_M4100}, |
| 8900 | #define OPTION_NO_M4100 (OPTION_MD_BASE + 16) |
| 8901 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
| 8902 | #define OPTION_MIPS16 (OPTION_MD_BASE + 17) |
| 8903 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
| 8904 | #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18) |
| 8905 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
| 8906 | #define OPTION_M3900 (OPTION_MD_BASE + 19) |
| 8907 | {"m3900", no_argument, NULL, OPTION_M3900}, |
| 8908 | #define OPTION_NO_M3900 (OPTION_MD_BASE + 20) |
| 8909 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
| 8910 | #define OPTION_MABI (OPTION_MD_BASE + 21) |
| 8911 | {"mabi", required_argument, NULL, OPTION_MABI}, |
| 8912 | #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22) |
| 8913 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
| 8914 | #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23) |
| 8915 | {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX}, |
| 8916 | #define OPTION_GP32 (OPTION_MD_BASE + 24) |
| 8917 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
| 8918 | #define OPTION_GP64 (OPTION_MD_BASE + 25) |
| 8919 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
| 8920 | #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26) |
| 8921 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
| 8922 | #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27) |
| 8923 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
| 8924 | #define OPTION_MIPS32 (OPTION_MD_BASE + 28) |
| 8925 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
| 8926 | #define OPTION_MIPS5 (OPTION_MD_BASE + 29) |
| 8927 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
| 8928 | #define OPTION_MIPS64 (OPTION_MD_BASE + 30) |
| 8929 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
| 8930 | #define OPTION_MARCH (OPTION_MD_BASE + 31) |
| 8931 | {"march", required_argument, NULL, OPTION_MARCH}, |
| 8932 | #define OPTION_MTUNE (OPTION_MD_BASE + 32) |
| 8933 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
| 8934 | #define OPTION_FP32 (OPTION_MD_BASE + 33) |
| 8935 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
| 8936 | #ifdef OBJ_ELF |
| 8937 | #define OPTION_ELF_BASE (OPTION_MD_BASE + 35) |
| 8938 | #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) |
| 8939 | #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1) |
| 8940 | #define OPTION_XGOT (OPTION_ELF_BASE + 2) |
| 8941 | #define OPTION_32 (OPTION_ELF_BASE + 3) |
| 8942 | #define OPTION_64 (OPTION_ELF_BASE + 4) |
| 8943 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
| 8944 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
| 8945 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
| 8946 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
| 8947 | {"32", no_argument, NULL, OPTION_32}, |
| 8948 | {"64", no_argument, NULL, OPTION_64}, |
| 8949 | #endif |
| 8950 | |
| 8951 | {NULL, no_argument, NULL, 0} |
| 8952 | }; |
| 8953 | size_t md_longopts_size = sizeof (md_longopts); |
| 8954 | |
| 8955 | int |
| 8956 | md_parse_option (c, arg) |
| 8957 | int c; |
| 8958 | char *arg; |
| 8959 | { |
| 8960 | switch (c) |
| 8961 | { |
| 8962 | case OPTION_CONSTRUCT_FLOATS: |
| 8963 | mips_disable_float_construction = 0; |
| 8964 | break; |
| 8965 | |
| 8966 | case OPTION_NO_CONSTRUCT_FLOATS: |
| 8967 | mips_disable_float_construction = 1; |
| 8968 | break; |
| 8969 | |
| 8970 | case OPTION_TRAP: |
| 8971 | mips_trap = 1; |
| 8972 | break; |
| 8973 | |
| 8974 | case OPTION_BREAK: |
| 8975 | mips_trap = 0; |
| 8976 | break; |
| 8977 | |
| 8978 | case OPTION_EB: |
| 8979 | target_big_endian = 1; |
| 8980 | break; |
| 8981 | |
| 8982 | case OPTION_EL: |
| 8983 | target_big_endian = 0; |
| 8984 | break; |
| 8985 | |
| 8986 | case 'n': |
| 8987 | warn_nops = 1; |
| 8988 | break; |
| 8989 | |
| 8990 | case 'O': |
| 8991 | if (arg && arg[1] == '0') |
| 8992 | mips_optimize = 1; |
| 8993 | else |
| 8994 | mips_optimize = 2; |
| 8995 | break; |
| 8996 | |
| 8997 | case 'g': |
| 8998 | if (arg == NULL) |
| 8999 | mips_debug = 2; |
| 9000 | else |
| 9001 | mips_debug = atoi (arg); |
| 9002 | /* When the MIPS assembler sees -g or -g2, it does not do |
| 9003 | optimizations which limit full symbolic debugging. We take |
| 9004 | that to be equivalent to -O0. */ |
| 9005 | if (mips_debug == 2) |
| 9006 | mips_optimize = 1; |
| 9007 | break; |
| 9008 | |
| 9009 | case OPTION_MIPS1: |
| 9010 | mips_opts.isa = ISA_MIPS1; |
| 9011 | break; |
| 9012 | |
| 9013 | case OPTION_MIPS2: |
| 9014 | mips_opts.isa = ISA_MIPS2; |
| 9015 | break; |
| 9016 | |
| 9017 | case OPTION_MIPS3: |
| 9018 | mips_opts.isa = ISA_MIPS3; |
| 9019 | break; |
| 9020 | |
| 9021 | case OPTION_MIPS4: |
| 9022 | mips_opts.isa = ISA_MIPS4; |
| 9023 | break; |
| 9024 | |
| 9025 | case OPTION_MIPS5: |
| 9026 | mips_opts.isa = ISA_MIPS5; |
| 9027 | break; |
| 9028 | |
| 9029 | case OPTION_MIPS32: |
| 9030 | mips_opts.isa = ISA_MIPS32; |
| 9031 | break; |
| 9032 | |
| 9033 | case OPTION_MIPS64: |
| 9034 | mips_opts.isa = ISA_MIPS64; |
| 9035 | break; |
| 9036 | |
| 9037 | case OPTION_MTUNE: |
| 9038 | case OPTION_MARCH: |
| 9039 | case OPTION_MCPU: |
| 9040 | { |
| 9041 | int cpu = CPU_UNKNOWN; |
| 9042 | |
| 9043 | /* Identify the processor type. */ |
| 9044 | if (strcasecmp (arg, "default") != 0) |
| 9045 | { |
| 9046 | const struct mips_cpu_info *ci; |
| 9047 | |
| 9048 | ci = mips_cpu_info_from_name (arg); |
| 9049 | if (ci == NULL || ci->is_isa) |
| 9050 | { |
| 9051 | switch (c) |
| 9052 | { |
| 9053 | case OPTION_MTUNE: |
| 9054 | as_fatal (_("invalid architecture -mtune=%s"), arg); |
| 9055 | break; |
| 9056 | case OPTION_MARCH: |
| 9057 | as_fatal (_("invalid architecture -march=%s"), arg); |
| 9058 | break; |
| 9059 | case OPTION_MCPU: |
| 9060 | as_fatal (_("invalid architecture -mcpu=%s"), arg); |
| 9061 | break; |
| 9062 | } |
| 9063 | } |
| 9064 | else |
| 9065 | cpu = ci->cpu; |
| 9066 | } |
| 9067 | |
| 9068 | switch (c) |
| 9069 | { |
| 9070 | case OPTION_MTUNE: |
| 9071 | if (mips_tune != CPU_UNKNOWN && mips_tune != cpu) |
| 9072 | as_warn(_("A different -mtune= was already specified, is now " |
| 9073 | "-mtune=%s"), arg); |
| 9074 | mips_tune = cpu; |
| 9075 | break; |
| 9076 | case OPTION_MARCH: |
| 9077 | if (mips_arch != CPU_UNKNOWN && mips_arch != cpu) |
| 9078 | as_warn(_("A different -march= was already specified, is now " |
| 9079 | "-march=%s"), arg); |
| 9080 | mips_arch = cpu; |
| 9081 | break; |
| 9082 | case OPTION_MCPU: |
| 9083 | if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu) |
| 9084 | as_warn(_("A different -mcpu= was already specified, is now " |
| 9085 | "-mcpu=%s"), arg); |
| 9086 | mips_cpu = cpu; |
| 9087 | } |
| 9088 | } |
| 9089 | break; |
| 9090 | |
| 9091 | case OPTION_M4650: |
| 9092 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650) |
| 9093 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650)) |
| 9094 | as_warn(_("A different -march= or -mtune= was already specified, " |
| 9095 | "is now -m4650")); |
| 9096 | mips_arch = CPU_R4650; |
| 9097 | mips_tune = CPU_R4650; |
| 9098 | break; |
| 9099 | |
| 9100 | case OPTION_NO_M4650: |
| 9101 | break; |
| 9102 | |
| 9103 | case OPTION_M4010: |
| 9104 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010) |
| 9105 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010)) |
| 9106 | as_warn(_("A different -march= or -mtune= was already specified, " |
| 9107 | "is now -m4010")); |
| 9108 | mips_arch = CPU_R4010; |
| 9109 | mips_tune = CPU_R4010; |
| 9110 | break; |
| 9111 | |
| 9112 | case OPTION_NO_M4010: |
| 9113 | break; |
| 9114 | |
| 9115 | case OPTION_M4100: |
| 9116 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100) |
| 9117 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100)) |
| 9118 | as_warn(_("A different -march= or -mtune= was already specified, " |
| 9119 | "is now -m4100")); |
| 9120 | mips_arch = CPU_VR4100; |
| 9121 | mips_tune = CPU_VR4100; |
| 9122 | break; |
| 9123 | |
| 9124 | case OPTION_NO_M4100: |
| 9125 | break; |
| 9126 | |
| 9127 | case OPTION_M3900: |
| 9128 | if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900) |
| 9129 | || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900)) |
| 9130 | as_warn(_("A different -march= or -mtune= was already specified, " |
| 9131 | "is now -m3900")); |
| 9132 | mips_arch = CPU_R3900; |
| 9133 | mips_tune = CPU_R3900; |
| 9134 | break; |
| 9135 | |
| 9136 | case OPTION_NO_M3900: |
| 9137 | break; |
| 9138 | |
| 9139 | case OPTION_MIPS16: |
| 9140 | mips_opts.mips16 = 1; |
| 9141 | mips_no_prev_insn (false); |
| 9142 | break; |
| 9143 | |
| 9144 | case OPTION_NO_MIPS16: |
| 9145 | mips_opts.mips16 = 0; |
| 9146 | mips_no_prev_insn (false); |
| 9147 | break; |
| 9148 | |
| 9149 | case OPTION_MEMBEDDED_PIC: |
| 9150 | mips_pic = EMBEDDED_PIC; |
| 9151 | if (USE_GLOBAL_POINTER_OPT && g_switch_seen) |
| 9152 | { |
| 9153 | as_bad (_("-G may not be used with embedded PIC code")); |
| 9154 | return 0; |
| 9155 | } |
| 9156 | g_switch_value = 0x7fffffff; |
| 9157 | break; |
| 9158 | |
| 9159 | #ifdef OBJ_ELF |
| 9160 | /* When generating ELF code, we permit -KPIC and -call_shared to |
| 9161 | select SVR4_PIC, and -non_shared to select no PIC. This is |
| 9162 | intended to be compatible with Irix 5. */ |
| 9163 | case OPTION_CALL_SHARED: |
| 9164 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 9165 | { |
| 9166 | as_bad (_("-call_shared is supported only for ELF format")); |
| 9167 | return 0; |
| 9168 | } |
| 9169 | mips_pic = SVR4_PIC; |
| 9170 | if (g_switch_seen && g_switch_value != 0) |
| 9171 | { |
| 9172 | as_bad (_("-G may not be used with SVR4 PIC code")); |
| 9173 | return 0; |
| 9174 | } |
| 9175 | g_switch_value = 0; |
| 9176 | break; |
| 9177 | |
| 9178 | case OPTION_NON_SHARED: |
| 9179 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 9180 | { |
| 9181 | as_bad (_("-non_shared is supported only for ELF format")); |
| 9182 | return 0; |
| 9183 | } |
| 9184 | mips_pic = NO_PIC; |
| 9185 | break; |
| 9186 | |
| 9187 | /* The -xgot option tells the assembler to use 32 offsets when |
| 9188 | accessing the got in SVR4_PIC mode. It is for Irix |
| 9189 | compatibility. */ |
| 9190 | case OPTION_XGOT: |
| 9191 | mips_big_got = 1; |
| 9192 | break; |
| 9193 | #endif /* OBJ_ELF */ |
| 9194 | |
| 9195 | case 'G': |
| 9196 | if (! USE_GLOBAL_POINTER_OPT) |
| 9197 | { |
| 9198 | as_bad (_("-G is not supported for this configuration")); |
| 9199 | return 0; |
| 9200 | } |
| 9201 | else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC) |
| 9202 | { |
| 9203 | as_bad (_("-G may not be used with SVR4 or embedded PIC code")); |
| 9204 | return 0; |
| 9205 | } |
| 9206 | else |
| 9207 | g_switch_value = atoi (arg); |
| 9208 | g_switch_seen = 1; |
| 9209 | break; |
| 9210 | |
| 9211 | #ifdef OBJ_ELF |
| 9212 | /* The -32 and -64 options tell the assembler to output the 32 |
| 9213 | bit or the 64 bit MIPS ELF format. */ |
| 9214 | case OPTION_32: |
| 9215 | mips_64 = 0; |
| 9216 | break; |
| 9217 | |
| 9218 | case OPTION_64: |
| 9219 | { |
| 9220 | const char **list, **l; |
| 9221 | |
| 9222 | list = bfd_target_list (); |
| 9223 | for (l = list; *l != NULL; l++) |
| 9224 | #ifdef TE_TMIPS |
| 9225 | /* This is traditional mips */ |
| 9226 | if (strcmp (*l, "elf64-tradbigmips") == 0 |
| 9227 | || strcmp (*l, "elf64-tradlittlemips") == 0) |
| 9228 | #else |
| 9229 | if (strcmp (*l, "elf64-bigmips") == 0 |
| 9230 | || strcmp (*l, "elf64-littlemips") == 0) |
| 9231 | #endif |
| 9232 | break; |
| 9233 | if (*l == NULL) |
| 9234 | as_fatal (_("No compiled in support for 64 bit object file format")); |
| 9235 | free (list); |
| 9236 | mips_64 = 1; |
| 9237 | } |
| 9238 | break; |
| 9239 | #endif /* OBJ_ELF */ |
| 9240 | |
| 9241 | case OPTION_GP32: |
| 9242 | mips_gp32 = 1; |
| 9243 | mips_64 = 0; |
| 9244 | |
| 9245 | /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE |
| 9246 | flag in object files because to do so would make it |
| 9247 | impossible to link with libraries compiled without "-gp32". |
| 9248 | This is unnecessarily restrictive. |
| 9249 | |
| 9250 | We could solve this problem by adding "-gp32" multilibs to |
| 9251 | gcc, but to set this flag before gcc is built with such |
| 9252 | multilibs will break too many systems. */ |
| 9253 | |
| 9254 | #if 0 |
| 9255 | mips_32bitmode = 1; |
| 9256 | #endif |
| 9257 | break; |
| 9258 | |
| 9259 | case OPTION_GP64: |
| 9260 | mips_gp32 = 0; |
| 9261 | mips_64 = 1; |
| 9262 | #if 0 |
| 9263 | mips_32bitmode = 0; |
| 9264 | #endif |
| 9265 | break; |
| 9266 | |
| 9267 | case OPTION_FP32: |
| 9268 | mips_fp32 = 1; |
| 9269 | break; |
| 9270 | |
| 9271 | case OPTION_MABI: |
| 9272 | if (strcmp (arg, "32") == 0 |
| 9273 | || strcmp (arg, "n32") == 0 |
| 9274 | || strcmp (arg, "64") == 0 |
| 9275 | || strcmp (arg, "o64") == 0 |
| 9276 | || strcmp (arg, "eabi") == 0) |
| 9277 | { |
| 9278 | mips_abi_string = arg; |
| 9279 | mips_32bit_abi = (strcmp (arg, "32") == 0); |
| 9280 | } |
| 9281 | break; |
| 9282 | |
| 9283 | case OPTION_M7000_HILO_FIX: |
| 9284 | mips_7000_hilo_fix = true; |
| 9285 | break; |
| 9286 | |
| 9287 | case OPTION_NO_M7000_HILO_FIX: |
| 9288 | mips_7000_hilo_fix = false; |
| 9289 | break; |
| 9290 | |
| 9291 | default: |
| 9292 | return 0; |
| 9293 | } |
| 9294 | |
| 9295 | return 1; |
| 9296 | } |
| 9297 | |
| 9298 | static void |
| 9299 | show (stream, string, col_p, first_p) |
| 9300 | FILE *stream; |
| 9301 | char *string; |
| 9302 | int *col_p; |
| 9303 | int *first_p; |
| 9304 | { |
| 9305 | if (*first_p) |
| 9306 | { |
| 9307 | fprintf (stream, "%24s", ""); |
| 9308 | *col_p = 24; |
| 9309 | } |
| 9310 | else |
| 9311 | { |
| 9312 | fprintf (stream, ", "); |
| 9313 | *col_p += 2; |
| 9314 | } |
| 9315 | |
| 9316 | if (*col_p + strlen (string) > 72) |
| 9317 | { |
| 9318 | fprintf (stream, "\n%24s", ""); |
| 9319 | *col_p = 24; |
| 9320 | } |
| 9321 | |
| 9322 | fprintf (stream, "%s", string); |
| 9323 | *col_p += strlen (string); |
| 9324 | |
| 9325 | *first_p = 0; |
| 9326 | } |
| 9327 | |
| 9328 | void |
| 9329 | md_show_usage (stream) |
| 9330 | FILE *stream; |
| 9331 | { |
| 9332 | int column, first; |
| 9333 | |
| 9334 | fprintf (stream, _("\ |
| 9335 | MIPS options:\n\ |
| 9336 | -membedded-pic generate embedded position independent code\n\ |
| 9337 | -EB generate big endian output\n\ |
| 9338 | -EL generate little endian output\n\ |
| 9339 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ |
| 9340 | -G NUM allow referencing objects up to NUM bytes\n\ |
| 9341 | implicitly with the gp register [default 8]\n")); |
| 9342 | fprintf (stream, _("\ |
| 9343 | -mips1 generate MIPS ISA I instructions\n\ |
| 9344 | -mips2 generate MIPS ISA II instructions\n\ |
| 9345 | -mips3 generate MIPS ISA III instructions\n\ |
| 9346 | -mips4 generate MIPS ISA IV instructions\n\ |
| 9347 | -mips5 generate MIPS ISA V instructions\n\ |
| 9348 | -mips32 generate MIPS32 ISA instructions\n\ |
| 9349 | -mips64 generate MIPS64 ISA instructions\n\ |
| 9350 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
| 9351 | |
| 9352 | first = 1; |
| 9353 | |
| 9354 | show (stream, "2000", &column, &first); |
| 9355 | show (stream, "3000", &column, &first); |
| 9356 | show (stream, "3900", &column, &first); |
| 9357 | show (stream, "4000", &column, &first); |
| 9358 | show (stream, "4010", &column, &first); |
| 9359 | show (stream, "4100", &column, &first); |
| 9360 | show (stream, "4111", &column, &first); |
| 9361 | show (stream, "4300", &column, &first); |
| 9362 | show (stream, "4400", &column, &first); |
| 9363 | show (stream, "4600", &column, &first); |
| 9364 | show (stream, "4650", &column, &first); |
| 9365 | show (stream, "5000", &column, &first); |
| 9366 | show (stream, "5200", &column, &first); |
| 9367 | show (stream, "5230", &column, &first); |
| 9368 | show (stream, "5231", &column, &first); |
| 9369 | show (stream, "5261", &column, &first); |
| 9370 | show (stream, "5721", &column, &first); |
| 9371 | show (stream, "6000", &column, &first); |
| 9372 | show (stream, "8000", &column, &first); |
| 9373 | show (stream, "10000", &column, &first); |
| 9374 | show (stream, "12000", &column, &first); |
| 9375 | show (stream, "sb-1", &column, &first); |
| 9376 | fputc ('\n', stream); |
| 9377 | |
| 9378 | fprintf (stream, _("\ |
| 9379 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
| 9380 | -no-mCPU don't generate code specific to CPU.\n\ |
| 9381 | For -mCPU and -no-mCPU, CPU must be one of:\n")); |
| 9382 | |
| 9383 | first = 1; |
| 9384 | |
| 9385 | show (stream, "3900", &column, &first); |
| 9386 | show (stream, "4010", &column, &first); |
| 9387 | show (stream, "4100", &column, &first); |
| 9388 | show (stream, "4650", &column, &first); |
| 9389 | fputc ('\n', stream); |
| 9390 | |
| 9391 | fprintf (stream, _("\ |
| 9392 | -mips16 generate mips16 instructions\n\ |
| 9393 | -no-mips16 do not generate mips16 instructions\n")); |
| 9394 | fprintf (stream, _("\ |
| 9395 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
| 9396 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ |
| 9397 | -O0 remove unneeded NOPs, do not swap branches\n\ |
| 9398 | -O remove unneeded NOPs and swap branches\n\ |
| 9399 | -n warn about NOPs generated from macros\n\ |
| 9400 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
| 9401 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
| 9402 | --break, --no-trap break exception on div by 0 and mult overflow\n")); |
| 9403 | #ifdef OBJ_ELF |
| 9404 | fprintf (stream, _("\ |
| 9405 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
| 9406 | -non_shared do not generate position independent code\n\ |
| 9407 | -xgot assume a 32 bit GOT\n\ |
| 9408 | -32 create 32 bit object file (default)\n\ |
| 9409 | -64 create 64 bit object file\n")); |
| 9410 | #endif |
| 9411 | } |
| 9412 | \f |
| 9413 | void |
| 9414 | mips_init_after_args () |
| 9415 | { |
| 9416 | /* initialize opcodes */ |
| 9417 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; |
| 9418 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
| 9419 | } |
| 9420 | |
| 9421 | long |
| 9422 | md_pcrel_from (fixP) |
| 9423 | fixS *fixP; |
| 9424 | { |
| 9425 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour |
| 9426 | && fixP->fx_addsy != (symbolS *) NULL |
| 9427 | && ! S_IS_DEFINED (fixP->fx_addsy)) |
| 9428 | { |
| 9429 | /* This makes a branch to an undefined symbol be a branch to the |
| 9430 | current location. */ |
| 9431 | return 4; |
| 9432 | } |
| 9433 | |
| 9434 | /* return the address of the delay slot */ |
| 9435 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
| 9436 | } |
| 9437 | |
| 9438 | /* This is called before the symbol table is processed. In order to |
| 9439 | work with gcc when using mips-tfile, we must keep all local labels. |
| 9440 | However, in other cases, we want to discard them. If we were |
| 9441 | called with -g, but we didn't see any debugging information, it may |
| 9442 | mean that gcc is smuggling debugging information through to |
| 9443 | mips-tfile, in which case we must generate all local labels. */ |
| 9444 | |
| 9445 | void |
| 9446 | mips_frob_file_before_adjust () |
| 9447 | { |
| 9448 | #ifndef NO_ECOFF_DEBUGGING |
| 9449 | if (ECOFF_DEBUGGING |
| 9450 | && mips_debug != 0 |
| 9451 | && ! ecoff_debugging_seen) |
| 9452 | flag_keep_locals = 1; |
| 9453 | #endif |
| 9454 | } |
| 9455 | |
| 9456 | /* Sort any unmatched HI16_S relocs so that they immediately precede |
| 9457 | the corresponding LO reloc. This is called before md_apply_fix and |
| 9458 | tc_gen_reloc. Unmatched HI16_S relocs can only be generated by |
| 9459 | explicit use of the %hi modifier. */ |
| 9460 | |
| 9461 | void |
| 9462 | mips_frob_file () |
| 9463 | { |
| 9464 | struct mips_hi_fixup *l; |
| 9465 | |
| 9466 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) |
| 9467 | { |
| 9468 | segment_info_type *seginfo; |
| 9469 | int pass; |
| 9470 | |
| 9471 | assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S); |
| 9472 | |
| 9473 | /* Check quickly whether the next fixup happens to be a matching |
| 9474 | %lo. */ |
| 9475 | if (l->fixp->fx_next != NULL |
| 9476 | && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16 |
| 9477 | && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy |
| 9478 | && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) |
| 9479 | continue; |
| 9480 | |
| 9481 | /* Look through the fixups for this segment for a matching %lo. |
| 9482 | When we find one, move the %hi just in front of it. We do |
| 9483 | this in two passes. In the first pass, we try to find a |
| 9484 | unique %lo. In the second pass, we permit multiple %hi |
| 9485 | relocs for a single %lo (this is a GNU extension). */ |
| 9486 | seginfo = seg_info (l->seg); |
| 9487 | for (pass = 0; pass < 2; pass++) |
| 9488 | { |
| 9489 | fixS *f, *prev; |
| 9490 | |
| 9491 | prev = NULL; |
| 9492 | for (f = seginfo->fix_root; f != NULL; f = f->fx_next) |
| 9493 | { |
| 9494 | /* Check whether this is a %lo fixup which matches l->fixp. */ |
| 9495 | if (f->fx_r_type == BFD_RELOC_LO16 |
| 9496 | && f->fx_addsy == l->fixp->fx_addsy |
| 9497 | && f->fx_offset == l->fixp->fx_offset |
| 9498 | && (pass == 1 |
| 9499 | || prev == NULL |
| 9500 | || prev->fx_r_type != BFD_RELOC_HI16_S |
| 9501 | || prev->fx_addsy != f->fx_addsy |
| 9502 | || prev->fx_offset != f->fx_offset)) |
| 9503 | { |
| 9504 | fixS **pf; |
| 9505 | |
| 9506 | /* Move l->fixp before f. */ |
| 9507 | for (pf = &seginfo->fix_root; |
| 9508 | *pf != l->fixp; |
| 9509 | pf = &(*pf)->fx_next) |
| 9510 | assert (*pf != NULL); |
| 9511 | |
| 9512 | *pf = l->fixp->fx_next; |
| 9513 | |
| 9514 | l->fixp->fx_next = f; |
| 9515 | if (prev == NULL) |
| 9516 | seginfo->fix_root = l->fixp; |
| 9517 | else |
| 9518 | prev->fx_next = l->fixp; |
| 9519 | |
| 9520 | break; |
| 9521 | } |
| 9522 | |
| 9523 | prev = f; |
| 9524 | } |
| 9525 | |
| 9526 | if (f != NULL) |
| 9527 | break; |
| 9528 | |
| 9529 | #if 0 /* GCC code motion plus incomplete dead code elimination |
| 9530 | can leave a %hi without a %lo. */ |
| 9531 | if (pass == 1) |
| 9532 | as_warn_where (l->fixp->fx_file, l->fixp->fx_line, |
| 9533 | _("Unmatched %%hi reloc")); |
| 9534 | #endif |
| 9535 | } |
| 9536 | } |
| 9537 | } |
| 9538 | |
| 9539 | /* When generating embedded PIC code we need to use a special |
| 9540 | relocation to represent the difference of two symbols in the .text |
| 9541 | section (switch tables use a difference of this sort). See |
| 9542 | include/coff/mips.h for details. This macro checks whether this |
| 9543 | fixup requires the special reloc. */ |
| 9544 | #define SWITCH_TABLE(fixp) \ |
| 9545 | ((fixp)->fx_r_type == BFD_RELOC_32 \ |
| 9546 | && OUTPUT_FLAVOR != bfd_target_elf_flavour \ |
| 9547 | && (fixp)->fx_addsy != NULL \ |
| 9548 | && (fixp)->fx_subsy != NULL \ |
| 9549 | && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \ |
| 9550 | && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section) |
| 9551 | |
| 9552 | /* When generating embedded PIC code we must keep all PC relative |
| 9553 | relocations, in case the linker has to relax a call. We also need |
| 9554 | to keep relocations for switch table entries. */ |
| 9555 | |
| 9556 | int |
| 9557 | mips_force_relocation (fixp) |
| 9558 | fixS *fixp; |
| 9559 | { |
| 9560 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 9561 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 9562 | return 1; |
| 9563 | |
| 9564 | return (mips_pic == EMBEDDED_PIC |
| 9565 | && (fixp->fx_pcrel |
| 9566 | || SWITCH_TABLE (fixp) |
| 9567 | || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S |
| 9568 | || fixp->fx_r_type == BFD_RELOC_PCREL_LO16)); |
| 9569 | } |
| 9570 | |
| 9571 | /* Apply a fixup to the object file. */ |
| 9572 | |
| 9573 | int |
| 9574 | md_apply_fix (fixP, valueP) |
| 9575 | fixS *fixP; |
| 9576 | valueT *valueP; |
| 9577 | { |
| 9578 | unsigned char *buf; |
| 9579 | long insn; |
| 9580 | valueT value; |
| 9581 | |
| 9582 | assert (fixP->fx_size == 4 |
| 9583 | || fixP->fx_r_type == BFD_RELOC_16 |
| 9584 | || fixP->fx_r_type == BFD_RELOC_64 |
| 9585 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 9586 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY); |
| 9587 | |
| 9588 | value = *valueP; |
| 9589 | |
| 9590 | /* If we aren't adjusting this fixup to be against the section |
| 9591 | symbol, we need to adjust the value. */ |
| 9592 | #ifdef OBJ_ELF |
| 9593 | if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 9594 | { |
| 9595 | if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16 |
| 9596 | || ((S_IS_WEAK (fixP->fx_addsy) |
| 9597 | || S_IS_EXTERN (fixP->fx_addsy)) |
| 9598 | && !S_IS_COMMON (fixP->fx_addsy)) |
| 9599 | || (symbol_used_in_reloc_p (fixP->fx_addsy) |
| 9600 | && (((bfd_get_section_flags (stdoutput, |
| 9601 | S_GET_SEGMENT (fixP->fx_addsy)) |
| 9602 | & SEC_LINK_ONCE) != 0) |
| 9603 | || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)), |
| 9604 | ".gnu.linkonce", |
| 9605 | sizeof (".gnu.linkonce") - 1)))) |
| 9606 | |
| 9607 | { |
| 9608 | valueT symval = S_GET_VALUE (fixP->fx_addsy); |
| 9609 | value -= symval; |
| 9610 | if (value != 0 |
| 9611 | && ! fixP->fx_pcrel |
| 9612 | && fixP->fx_r_type != BFD_RELOC_MIPS_GPREL) |
| 9613 | { |
| 9614 | /* In this case, the bfd_install_relocation routine will |
| 9615 | incorrectly add the symbol value back in. We just want |
| 9616 | the addend to appear in the object file. */ |
| 9617 | value -= symval; |
| 9618 | |
| 9619 | /* Make sure the addend is still non-zero. If it became zero |
| 9620 | after the last operation, set it to a spurious value and |
| 9621 | subtract the same value from the object file's contents. */ |
| 9622 | if (value == 0) |
| 9623 | { |
| 9624 | value = 8; |
| 9625 | |
| 9626 | /* The in-place addends for LO16 relocations are signed; |
| 9627 | leave the matching HI16 in-place addends as zero. */ |
| 9628 | if (fixP->fx_r_type != BFD_RELOC_HI16_S) |
| 9629 | { |
| 9630 | reloc_howto_type *howto; |
| 9631 | bfd_vma contents, mask, field; |
| 9632 | |
| 9633 | howto = bfd_reloc_type_lookup (stdoutput, |
| 9634 | fixP->fx_r_type); |
| 9635 | |
| 9636 | contents = bfd_get_bits (fixP->fx_frag->fr_literal |
| 9637 | + fixP->fx_where, |
| 9638 | fixP->fx_size * 8, |
| 9639 | target_big_endian); |
| 9640 | |
| 9641 | /* MASK has bits set where the relocation should go. |
| 9642 | FIELD is -value, shifted into the appropriate place |
| 9643 | for this relocation. */ |
| 9644 | mask = 1 << (howto->bitsize - 1); |
| 9645 | mask = (((mask - 1) << 1) | 1) << howto->bitpos; |
| 9646 | field = (-value >> howto->rightshift) << howto->bitpos; |
| 9647 | |
| 9648 | bfd_put_bits ((field & mask) | (contents & ~mask), |
| 9649 | fixP->fx_frag->fr_literal + fixP->fx_where, |
| 9650 | fixP->fx_size * 8, |
| 9651 | target_big_endian); |
| 9652 | } |
| 9653 | } |
| 9654 | } |
| 9655 | } |
| 9656 | |
| 9657 | /* This code was generated using trial and error and so is |
| 9658 | fragile and not trustworthy. If you change it, you should |
| 9659 | rerun the elf-rel, elf-rel2, and empic testcases and ensure |
| 9660 | they still pass. */ |
| 9661 | if (fixP->fx_pcrel || fixP->fx_subsy != NULL) |
| 9662 | { |
| 9663 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
| 9664 | |
| 9665 | /* BFD's REL handling, for MIPS, is _very_ weird. |
| 9666 | This gives the right results, but it can't possibly |
| 9667 | be the way things are supposed to work. */ |
| 9668 | if (fixP->fx_r_type != BFD_RELOC_16_PCREL_S2 |
| 9669 | || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section) |
| 9670 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
| 9671 | } |
| 9672 | } |
| 9673 | #endif |
| 9674 | |
| 9675 | fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */ |
| 9676 | |
| 9677 | if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel) |
| 9678 | fixP->fx_done = 1; |
| 9679 | |
| 9680 | switch (fixP->fx_r_type) |
| 9681 | { |
| 9682 | case BFD_RELOC_MIPS_JMP: |
| 9683 | case BFD_RELOC_HI16: |
| 9684 | case BFD_RELOC_HI16_S: |
| 9685 | case BFD_RELOC_MIPS_GPREL: |
| 9686 | case BFD_RELOC_MIPS_LITERAL: |
| 9687 | case BFD_RELOC_MIPS_CALL16: |
| 9688 | case BFD_RELOC_MIPS_GOT16: |
| 9689 | case BFD_RELOC_MIPS_GPREL32: |
| 9690 | case BFD_RELOC_MIPS_GOT_HI16: |
| 9691 | case BFD_RELOC_MIPS_GOT_LO16: |
| 9692 | case BFD_RELOC_MIPS_CALL_HI16: |
| 9693 | case BFD_RELOC_MIPS_CALL_LO16: |
| 9694 | case BFD_RELOC_MIPS16_GPREL: |
| 9695 | if (fixP->fx_pcrel) |
| 9696 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 9697 | _("Invalid PC relative reloc")); |
| 9698 | /* Nothing needed to do. The value comes from the reloc entry */ |
| 9699 | break; |
| 9700 | |
| 9701 | case BFD_RELOC_MIPS16_JMP: |
| 9702 | /* We currently always generate a reloc against a symbol, which |
| 9703 | means that we don't want an addend even if the symbol is |
| 9704 | defined. */ |
| 9705 | fixP->fx_addnumber = 0; |
| 9706 | break; |
| 9707 | |
| 9708 | case BFD_RELOC_PCREL_HI16_S: |
| 9709 | /* The addend for this is tricky if it is internal, so we just |
| 9710 | do everything here rather than in bfd_install_relocation. */ |
| 9711 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 9712 | && !fixP->fx_done |
| 9713 | && value != 0) |
| 9714 | break; |
| 9715 | if (fixP->fx_addsy |
| 9716 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) |
| 9717 | { |
| 9718 | /* For an external symbol adjust by the address to make it |
| 9719 | pcrel_offset. We use the address of the RELLO reloc |
| 9720 | which follows this one. */ |
| 9721 | value += (fixP->fx_next->fx_frag->fr_address |
| 9722 | + fixP->fx_next->fx_where); |
| 9723 | } |
| 9724 | value = ((value + 0x8000) >> 16) & 0xffff; |
| 9725 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
| 9726 | if (target_big_endian) |
| 9727 | buf += 2; |
| 9728 | md_number_to_chars (buf, value, 2); |
| 9729 | break; |
| 9730 | |
| 9731 | case BFD_RELOC_PCREL_LO16: |
| 9732 | /* The addend for this is tricky if it is internal, so we just |
| 9733 | do everything here rather than in bfd_install_relocation. */ |
| 9734 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 9735 | && !fixP->fx_done |
| 9736 | && value != 0) |
| 9737 | break; |
| 9738 | if (fixP->fx_addsy |
| 9739 | && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0) |
| 9740 | value += fixP->fx_frag->fr_address + fixP->fx_where; |
| 9741 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
| 9742 | if (target_big_endian) |
| 9743 | buf += 2; |
| 9744 | md_number_to_chars (buf, value, 2); |
| 9745 | break; |
| 9746 | |
| 9747 | case BFD_RELOC_64: |
| 9748 | /* This is handled like BFD_RELOC_32, but we output a sign |
| 9749 | extended value if we are only 32 bits. */ |
| 9750 | if (fixP->fx_done |
| 9751 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) |
| 9752 | { |
| 9753 | if (8 <= sizeof (valueT)) |
| 9754 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
| 9755 | value, 8); |
| 9756 | else |
| 9757 | { |
| 9758 | long w1, w2; |
| 9759 | long hiv; |
| 9760 | |
| 9761 | w1 = w2 = fixP->fx_where; |
| 9762 | if (target_big_endian) |
| 9763 | w1 += 4; |
| 9764 | else |
| 9765 | w2 += 4; |
| 9766 | md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4); |
| 9767 | if ((value & 0x80000000) != 0) |
| 9768 | hiv = 0xffffffff; |
| 9769 | else |
| 9770 | hiv = 0; |
| 9771 | md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4); |
| 9772 | } |
| 9773 | } |
| 9774 | break; |
| 9775 | |
| 9776 | case BFD_RELOC_RVA: |
| 9777 | case BFD_RELOC_32: |
| 9778 | /* If we are deleting this reloc entry, we must fill in the |
| 9779 | value now. This can happen if we have a .word which is not |
| 9780 | resolved when it appears but is later defined. We also need |
| 9781 | to fill in the value if this is an embedded PIC switch table |
| 9782 | entry. */ |
| 9783 | if (fixP->fx_done |
| 9784 | || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP))) |
| 9785 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
| 9786 | value, 4); |
| 9787 | break; |
| 9788 | |
| 9789 | case BFD_RELOC_16: |
| 9790 | /* If we are deleting this reloc entry, we must fill in the |
| 9791 | value now. */ |
| 9792 | assert (fixP->fx_size == 2); |
| 9793 | if (fixP->fx_done) |
| 9794 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
| 9795 | value, 2); |
| 9796 | break; |
| 9797 | |
| 9798 | case BFD_RELOC_LO16: |
| 9799 | /* When handling an embedded PIC switch statement, we can wind |
| 9800 | up deleting a LO16 reloc. See the 'o' case in mips_ip. */ |
| 9801 | if (fixP->fx_done) |
| 9802 | { |
| 9803 | if (value + 0x8000 > 0xffff) |
| 9804 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 9805 | _("relocation overflow")); |
| 9806 | buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
| 9807 | if (target_big_endian) |
| 9808 | buf += 2; |
| 9809 | md_number_to_chars (buf, value, 2); |
| 9810 | } |
| 9811 | break; |
| 9812 | |
| 9813 | case BFD_RELOC_16_PCREL_S2: |
| 9814 | /* |
| 9815 | * We need to save the bits in the instruction since fixup_segment() |
| 9816 | * might be deleting the relocation entry (i.e., a branch within |
| 9817 | * the current segment). |
| 9818 | */ |
| 9819 | if ((value & 0x3) != 0) |
| 9820 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 9821 | _("Branch to odd address (%lx)"), (long) value); |
| 9822 | |
| 9823 | if (!fixP->fx_done && value != 0) |
| 9824 | break; |
| 9825 | /* If 'value' is zero, the remaining reloc code won't actually |
| 9826 | do the store, so it must be done here. This is probably |
| 9827 | a bug somewhere. */ |
| 9828 | if (!fixP->fx_done) |
| 9829 | value -= fixP->fx_frag->fr_address + fixP->fx_where; |
| 9830 | |
| 9831 | value = (offsetT) value >> 2; |
| 9832 | |
| 9833 | /* update old instruction data */ |
| 9834 | buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal); |
| 9835 | if (target_big_endian) |
| 9836 | insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; |
| 9837 | else |
| 9838 | insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0]; |
| 9839 | |
| 9840 | if (value + 0x8000 <= 0xffff) |
| 9841 | insn |= value & 0xffff; |
| 9842 | else |
| 9843 | { |
| 9844 | /* The branch offset is too large. If this is an |
| 9845 | unconditional branch, and we are not generating PIC code, |
| 9846 | we can convert it to an absolute jump instruction. */ |
| 9847 | if (mips_pic == NO_PIC |
| 9848 | && fixP->fx_done |
| 9849 | && fixP->fx_frag->fr_address >= text_section->vma |
| 9850 | && (fixP->fx_frag->fr_address |
| 9851 | < text_section->vma + text_section->_raw_size) |
| 9852 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
| 9853 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ |
| 9854 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ |
| 9855 | { |
| 9856 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
| 9857 | insn = 0x0c000000; /* jal */ |
| 9858 | else |
| 9859 | insn = 0x08000000; /* j */ |
| 9860 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; |
| 9861 | fixP->fx_done = 0; |
| 9862 | fixP->fx_addsy = section_symbol (text_section); |
| 9863 | fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP); |
| 9864 | } |
| 9865 | else |
| 9866 | { |
| 9867 | /* FIXME. It would be possible in principle to handle |
| 9868 | conditional branches which overflow. They could be |
| 9869 | transformed into a branch around a jump. This would |
| 9870 | require setting up variant frags for each different |
| 9871 | branch type. The native MIPS assembler attempts to |
| 9872 | handle these cases, but it appears to do it |
| 9873 | incorrectly. */ |
| 9874 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 9875 | _("Branch out of range")); |
| 9876 | } |
| 9877 | } |
| 9878 | |
| 9879 | md_number_to_chars ((char *) buf, (valueT) insn, 4); |
| 9880 | break; |
| 9881 | |
| 9882 | case BFD_RELOC_VTABLE_INHERIT: |
| 9883 | fixP->fx_done = 0; |
| 9884 | if (fixP->fx_addsy |
| 9885 | && !S_IS_DEFINED (fixP->fx_addsy) |
| 9886 | && !S_IS_WEAK (fixP->fx_addsy)) |
| 9887 | S_SET_WEAK (fixP->fx_addsy); |
| 9888 | break; |
| 9889 | |
| 9890 | case BFD_RELOC_VTABLE_ENTRY: |
| 9891 | fixP->fx_done = 0; |
| 9892 | break; |
| 9893 | |
| 9894 | default: |
| 9895 | internalError (); |
| 9896 | } |
| 9897 | |
| 9898 | return 1; |
| 9899 | } |
| 9900 | |
| 9901 | #if 0 |
| 9902 | void |
| 9903 | printInsn (oc) |
| 9904 | unsigned long oc; |
| 9905 | { |
| 9906 | const struct mips_opcode *p; |
| 9907 | int treg, sreg, dreg, shamt; |
| 9908 | short imm; |
| 9909 | const char *args; |
| 9910 | int i; |
| 9911 | |
| 9912 | for (i = 0; i < NUMOPCODES; ++i) |
| 9913 | { |
| 9914 | p = &mips_opcodes[i]; |
| 9915 | if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO)) |
| 9916 | { |
| 9917 | printf ("%08lx %s\t", oc, p->name); |
| 9918 | treg = (oc >> 16) & 0x1f; |
| 9919 | sreg = (oc >> 21) & 0x1f; |
| 9920 | dreg = (oc >> 11) & 0x1f; |
| 9921 | shamt = (oc >> 6) & 0x1f; |
| 9922 | imm = oc; |
| 9923 | for (args = p->args;; ++args) |
| 9924 | { |
| 9925 | switch (*args) |
| 9926 | { |
| 9927 | case '\0': |
| 9928 | printf ("\n"); |
| 9929 | break; |
| 9930 | |
| 9931 | case ',': |
| 9932 | case '(': |
| 9933 | case ')': |
| 9934 | printf ("%c", *args); |
| 9935 | continue; |
| 9936 | |
| 9937 | case 'r': |
| 9938 | assert (treg == sreg); |
| 9939 | printf ("$%d,$%d", treg, sreg); |
| 9940 | continue; |
| 9941 | |
| 9942 | case 'd': |
| 9943 | case 'G': |
| 9944 | printf ("$%d", dreg); |
| 9945 | continue; |
| 9946 | |
| 9947 | case 't': |
| 9948 | case 'E': |
| 9949 | printf ("$%d", treg); |
| 9950 | continue; |
| 9951 | |
| 9952 | case 'k': |
| 9953 | printf ("0x%x", treg); |
| 9954 | continue; |
| 9955 | |
| 9956 | case 'b': |
| 9957 | case 's': |
| 9958 | printf ("$%d", sreg); |
| 9959 | continue; |
| 9960 | |
| 9961 | case 'a': |
| 9962 | printf ("0x%08lx", oc & 0x1ffffff); |
| 9963 | continue; |
| 9964 | |
| 9965 | case 'i': |
| 9966 | case 'j': |
| 9967 | case 'o': |
| 9968 | case 'u': |
| 9969 | printf ("%d", imm); |
| 9970 | continue; |
| 9971 | |
| 9972 | case '<': |
| 9973 | case '>': |
| 9974 | printf ("$%d", shamt); |
| 9975 | continue; |
| 9976 | |
| 9977 | default: |
| 9978 | internalError (); |
| 9979 | } |
| 9980 | break; |
| 9981 | } |
| 9982 | return; |
| 9983 | } |
| 9984 | } |
| 9985 | printf (_("%08lx UNDEFINED\n"), oc); |
| 9986 | } |
| 9987 | #endif |
| 9988 | |
| 9989 | static symbolS * |
| 9990 | get_symbol () |
| 9991 | { |
| 9992 | int c; |
| 9993 | char *name; |
| 9994 | symbolS *p; |
| 9995 | |
| 9996 | name = input_line_pointer; |
| 9997 | c = get_symbol_end (); |
| 9998 | p = (symbolS *) symbol_find_or_make (name); |
| 9999 | *input_line_pointer = c; |
| 10000 | return p; |
| 10001 | } |
| 10002 | |
| 10003 | /* Align the current frag to a given power of two. The MIPS assembler |
| 10004 | also automatically adjusts any preceding label. */ |
| 10005 | |
| 10006 | static void |
| 10007 | mips_align (to, fill, label) |
| 10008 | int to; |
| 10009 | int fill; |
| 10010 | symbolS *label; |
| 10011 | { |
| 10012 | mips_emit_delays (false); |
| 10013 | frag_align (to, fill, 0); |
| 10014 | record_alignment (now_seg, to); |
| 10015 | if (label != NULL) |
| 10016 | { |
| 10017 | assert (S_GET_SEGMENT (label) == now_seg); |
| 10018 | symbol_set_frag (label, frag_now); |
| 10019 | S_SET_VALUE (label, (valueT) frag_now_fix ()); |
| 10020 | } |
| 10021 | } |
| 10022 | |
| 10023 | /* Align to a given power of two. .align 0 turns off the automatic |
| 10024 | alignment used by the data creating pseudo-ops. */ |
| 10025 | |
| 10026 | static void |
| 10027 | s_align (x) |
| 10028 | int x ATTRIBUTE_UNUSED; |
| 10029 | { |
| 10030 | register int temp; |
| 10031 | register long temp_fill; |
| 10032 | long max_alignment = 15; |
| 10033 | |
| 10034 | /* |
| 10035 | |
| 10036 | o Note that the assembler pulls down any immediately preceeding label |
| 10037 | to the aligned address. |
| 10038 | o It's not documented but auto alignment is reinstated by |
| 10039 | a .align pseudo instruction. |
| 10040 | o Note also that after auto alignment is turned off the mips assembler |
| 10041 | issues an error on attempt to assemble an improperly aligned data item. |
| 10042 | We don't. |
| 10043 | |
| 10044 | */ |
| 10045 | |
| 10046 | temp = get_absolute_expression (); |
| 10047 | if (temp > max_alignment) |
| 10048 | as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment); |
| 10049 | else if (temp < 0) |
| 10050 | { |
| 10051 | as_warn (_("Alignment negative: 0 assumed.")); |
| 10052 | temp = 0; |
| 10053 | } |
| 10054 | if (*input_line_pointer == ',') |
| 10055 | { |
| 10056 | input_line_pointer++; |
| 10057 | temp_fill = get_absolute_expression (); |
| 10058 | } |
| 10059 | else |
| 10060 | temp_fill = 0; |
| 10061 | if (temp) |
| 10062 | { |
| 10063 | auto_align = 1; |
| 10064 | mips_align (temp, (int) temp_fill, |
| 10065 | insn_labels != NULL ? insn_labels->label : NULL); |
| 10066 | } |
| 10067 | else |
| 10068 | { |
| 10069 | auto_align = 0; |
| 10070 | } |
| 10071 | |
| 10072 | demand_empty_rest_of_line (); |
| 10073 | } |
| 10074 | |
| 10075 | void |
| 10076 | mips_flush_pending_output () |
| 10077 | { |
| 10078 | mips_emit_delays (false); |
| 10079 | mips_clear_insn_labels (); |
| 10080 | } |
| 10081 | |
| 10082 | static void |
| 10083 | s_change_sec (sec) |
| 10084 | int sec; |
| 10085 | { |
| 10086 | segT seg; |
| 10087 | |
| 10088 | /* When generating embedded PIC code, we only use the .text, .lit8, |
| 10089 | .sdata and .sbss sections. We change the .data and .rdata |
| 10090 | pseudo-ops to use .sdata. */ |
| 10091 | if (mips_pic == EMBEDDED_PIC |
| 10092 | && (sec == 'd' || sec == 'r')) |
| 10093 | sec = 's'; |
| 10094 | |
| 10095 | #ifdef OBJ_ELF |
| 10096 | /* The ELF backend needs to know that we are changing sections, so |
| 10097 | that .previous works correctly. We could do something like check |
| 10098 | for a obj_section_change_hook macro, but that might be confusing |
| 10099 | as it would not be appropriate to use it in the section changing |
| 10100 | functions in read.c, since obj-elf.c intercepts those. FIXME: |
| 10101 | This should be cleaner, somehow. */ |
| 10102 | obj_elf_section_change_hook (); |
| 10103 | #endif |
| 10104 | |
| 10105 | mips_emit_delays (false); |
| 10106 | switch (sec) |
| 10107 | { |
| 10108 | case 't': |
| 10109 | s_text (0); |
| 10110 | break; |
| 10111 | case 'd': |
| 10112 | s_data (0); |
| 10113 | break; |
| 10114 | case 'b': |
| 10115 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
| 10116 | demand_empty_rest_of_line (); |
| 10117 | break; |
| 10118 | |
| 10119 | case 'r': |
| 10120 | if (USE_GLOBAL_POINTER_OPT) |
| 10121 | { |
| 10122 | seg = subseg_new (RDATA_SECTION_NAME, |
| 10123 | (subsegT) get_absolute_expression ()); |
| 10124 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 10125 | { |
| 10126 | bfd_set_section_flags (stdoutput, seg, |
| 10127 | (SEC_ALLOC |
| 10128 | | SEC_LOAD |
| 10129 | | SEC_READONLY |
| 10130 | | SEC_RELOC |
| 10131 | | SEC_DATA)); |
| 10132 | if (strcmp (TARGET_OS, "elf") != 0) |
| 10133 | record_alignment (seg, 4); |
| 10134 | } |
| 10135 | demand_empty_rest_of_line (); |
| 10136 | } |
| 10137 | else |
| 10138 | { |
| 10139 | as_bad (_("No read only data section in this object file format")); |
| 10140 | demand_empty_rest_of_line (); |
| 10141 | return; |
| 10142 | } |
| 10143 | break; |
| 10144 | |
| 10145 | case 's': |
| 10146 | if (USE_GLOBAL_POINTER_OPT) |
| 10147 | { |
| 10148 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
| 10149 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 10150 | { |
| 10151 | bfd_set_section_flags (stdoutput, seg, |
| 10152 | SEC_ALLOC | SEC_LOAD | SEC_RELOC |
| 10153 | | SEC_DATA); |
| 10154 | if (strcmp (TARGET_OS, "elf") != 0) |
| 10155 | record_alignment (seg, 4); |
| 10156 | } |
| 10157 | demand_empty_rest_of_line (); |
| 10158 | break; |
| 10159 | } |
| 10160 | else |
| 10161 | { |
| 10162 | as_bad (_("Global pointers not supported; recompile -G 0")); |
| 10163 | demand_empty_rest_of_line (); |
| 10164 | return; |
| 10165 | } |
| 10166 | } |
| 10167 | |
| 10168 | auto_align = 1; |
| 10169 | } |
| 10170 | |
| 10171 | void |
| 10172 | mips_enable_auto_align () |
| 10173 | { |
| 10174 | auto_align = 1; |
| 10175 | } |
| 10176 | |
| 10177 | static void |
| 10178 | s_cons (log_size) |
| 10179 | int log_size; |
| 10180 | { |
| 10181 | symbolS *label; |
| 10182 | |
| 10183 | label = insn_labels != NULL ? insn_labels->label : NULL; |
| 10184 | mips_emit_delays (false); |
| 10185 | if (log_size > 0 && auto_align) |
| 10186 | mips_align (log_size, 0, label); |
| 10187 | mips_clear_insn_labels (); |
| 10188 | cons (1 << log_size); |
| 10189 | } |
| 10190 | |
| 10191 | static void |
| 10192 | s_float_cons (type) |
| 10193 | int type; |
| 10194 | { |
| 10195 | symbolS *label; |
| 10196 | |
| 10197 | label = insn_labels != NULL ? insn_labels->label : NULL; |
| 10198 | |
| 10199 | mips_emit_delays (false); |
| 10200 | |
| 10201 | if (auto_align) |
| 10202 | { |
| 10203 | if (type == 'd') |
| 10204 | mips_align (3, 0, label); |
| 10205 | else |
| 10206 | mips_align (2, 0, label); |
| 10207 | } |
| 10208 | |
| 10209 | mips_clear_insn_labels (); |
| 10210 | |
| 10211 | float_cons (type); |
| 10212 | } |
| 10213 | |
| 10214 | /* Handle .globl. We need to override it because on Irix 5 you are |
| 10215 | permitted to say |
| 10216 | .globl foo .text |
| 10217 | where foo is an undefined symbol, to mean that foo should be |
| 10218 | considered to be the address of a function. */ |
| 10219 | |
| 10220 | static void |
| 10221 | s_mips_globl (x) |
| 10222 | int x ATTRIBUTE_UNUSED; |
| 10223 | { |
| 10224 | char *name; |
| 10225 | int c; |
| 10226 | symbolS *symbolP; |
| 10227 | flagword flag; |
| 10228 | |
| 10229 | name = input_line_pointer; |
| 10230 | c = get_symbol_end (); |
| 10231 | symbolP = symbol_find_or_make (name); |
| 10232 | *input_line_pointer = c; |
| 10233 | SKIP_WHITESPACE (); |
| 10234 | |
| 10235 | /* On Irix 5, every global symbol that is not explicitly labelled as |
| 10236 | being a function is apparently labelled as being an object. */ |
| 10237 | flag = BSF_OBJECT; |
| 10238 | |
| 10239 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 10240 | { |
| 10241 | char *secname; |
| 10242 | asection *sec; |
| 10243 | |
| 10244 | secname = input_line_pointer; |
| 10245 | c = get_symbol_end (); |
| 10246 | sec = bfd_get_section_by_name (stdoutput, secname); |
| 10247 | if (sec == NULL) |
| 10248 | as_bad (_("%s: no such section"), secname); |
| 10249 | *input_line_pointer = c; |
| 10250 | |
| 10251 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) |
| 10252 | flag = BSF_FUNCTION; |
| 10253 | } |
| 10254 | |
| 10255 | symbol_get_bfdsym (symbolP)->flags |= flag; |
| 10256 | |
| 10257 | S_SET_EXTERNAL (symbolP); |
| 10258 | demand_empty_rest_of_line (); |
| 10259 | } |
| 10260 | |
| 10261 | static void |
| 10262 | s_option (x) |
| 10263 | int x ATTRIBUTE_UNUSED; |
| 10264 | { |
| 10265 | char *opt; |
| 10266 | char c; |
| 10267 | |
| 10268 | opt = input_line_pointer; |
| 10269 | c = get_symbol_end (); |
| 10270 | |
| 10271 | if (*opt == 'O') |
| 10272 | { |
| 10273 | /* FIXME: What does this mean? */ |
| 10274 | } |
| 10275 | else if (strncmp (opt, "pic", 3) == 0) |
| 10276 | { |
| 10277 | int i; |
| 10278 | |
| 10279 | i = atoi (opt + 3); |
| 10280 | if (i == 0) |
| 10281 | mips_pic = NO_PIC; |
| 10282 | else if (i == 2) |
| 10283 | mips_pic = SVR4_PIC; |
| 10284 | else |
| 10285 | as_bad (_(".option pic%d not supported"), i); |
| 10286 | |
| 10287 | if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC) |
| 10288 | { |
| 10289 | if (g_switch_seen && g_switch_value != 0) |
| 10290 | as_warn (_("-G may not be used with SVR4 PIC code")); |
| 10291 | g_switch_value = 0; |
| 10292 | bfd_set_gp_size (stdoutput, 0); |
| 10293 | } |
| 10294 | } |
| 10295 | else |
| 10296 | as_warn (_("Unrecognized option \"%s\""), opt); |
| 10297 | |
| 10298 | *input_line_pointer = c; |
| 10299 | demand_empty_rest_of_line (); |
| 10300 | } |
| 10301 | |
| 10302 | /* This structure is used to hold a stack of .set values. */ |
| 10303 | |
| 10304 | struct mips_option_stack |
| 10305 | { |
| 10306 | struct mips_option_stack *next; |
| 10307 | struct mips_set_options options; |
| 10308 | }; |
| 10309 | |
| 10310 | static struct mips_option_stack *mips_opts_stack; |
| 10311 | |
| 10312 | /* Handle the .set pseudo-op. */ |
| 10313 | |
| 10314 | static void |
| 10315 | s_mipsset (x) |
| 10316 | int x ATTRIBUTE_UNUSED; |
| 10317 | { |
| 10318 | char *name = input_line_pointer, ch; |
| 10319 | |
| 10320 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 10321 | input_line_pointer++; |
| 10322 | ch = *input_line_pointer; |
| 10323 | *input_line_pointer = '\0'; |
| 10324 | |
| 10325 | if (strcmp (name, "reorder") == 0) |
| 10326 | { |
| 10327 | if (mips_opts.noreorder && prev_nop_frag != NULL) |
| 10328 | { |
| 10329 | /* If we still have pending nops, we can discard them. The |
| 10330 | usual nop handling will insert any that are still |
| 10331 | needed. */ |
| 10332 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
| 10333 | * (mips_opts.mips16 ? 2 : 4)); |
| 10334 | prev_nop_frag = NULL; |
| 10335 | } |
| 10336 | mips_opts.noreorder = 0; |
| 10337 | } |
| 10338 | else if (strcmp (name, "noreorder") == 0) |
| 10339 | { |
| 10340 | mips_emit_delays (true); |
| 10341 | mips_opts.noreorder = 1; |
| 10342 | mips_any_noreorder = 1; |
| 10343 | } |
| 10344 | else if (strcmp (name, "at") == 0) |
| 10345 | { |
| 10346 | mips_opts.noat = 0; |
| 10347 | } |
| 10348 | else if (strcmp (name, "noat") == 0) |
| 10349 | { |
| 10350 | mips_opts.noat = 1; |
| 10351 | } |
| 10352 | else if (strcmp (name, "macro") == 0) |
| 10353 | { |
| 10354 | mips_opts.warn_about_macros = 0; |
| 10355 | } |
| 10356 | else if (strcmp (name, "nomacro") == 0) |
| 10357 | { |
| 10358 | if (mips_opts.noreorder == 0) |
| 10359 | as_bad (_("`noreorder' must be set before `nomacro'")); |
| 10360 | mips_opts.warn_about_macros = 1; |
| 10361 | } |
| 10362 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
| 10363 | { |
| 10364 | mips_opts.nomove = 0; |
| 10365 | } |
| 10366 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
| 10367 | { |
| 10368 | mips_opts.nomove = 1; |
| 10369 | } |
| 10370 | else if (strcmp (name, "bopt") == 0) |
| 10371 | { |
| 10372 | mips_opts.nobopt = 0; |
| 10373 | } |
| 10374 | else if (strcmp (name, "nobopt") == 0) |
| 10375 | { |
| 10376 | mips_opts.nobopt = 1; |
| 10377 | } |
| 10378 | else if (strcmp (name, "mips16") == 0 |
| 10379 | || strcmp (name, "MIPS-16") == 0) |
| 10380 | mips_opts.mips16 = 1; |
| 10381 | else if (strcmp (name, "nomips16") == 0 |
| 10382 | || strcmp (name, "noMIPS-16") == 0) |
| 10383 | mips_opts.mips16 = 0; |
| 10384 | else if (strncmp (name, "mips", 4) == 0) |
| 10385 | { |
| 10386 | int isa; |
| 10387 | |
| 10388 | /* Permit the user to change the ISA on the fly. Needless to |
| 10389 | say, misuse can cause serious problems. */ |
| 10390 | isa = atoi (name + 4); |
| 10391 | switch (isa) |
| 10392 | { |
| 10393 | case 0: mips_opts.isa = file_mips_isa; break; |
| 10394 | case 1: mips_opts.isa = ISA_MIPS1; break; |
| 10395 | case 2: mips_opts.isa = ISA_MIPS2; break; |
| 10396 | case 3: mips_opts.isa = ISA_MIPS3; break; |
| 10397 | case 4: mips_opts.isa = ISA_MIPS4; break; |
| 10398 | case 5: mips_opts.isa = ISA_MIPS5; break; |
| 10399 | case 32: mips_opts.isa = ISA_MIPS32; break; |
| 10400 | case 64: mips_opts.isa = ISA_MIPS64; break; |
| 10401 | default: as_bad (_("unknown ISA level")); break; |
| 10402 | } |
| 10403 | } |
| 10404 | else if (strcmp (name, "autoextend") == 0) |
| 10405 | mips_opts.noautoextend = 0; |
| 10406 | else if (strcmp (name, "noautoextend") == 0) |
| 10407 | mips_opts.noautoextend = 1; |
| 10408 | else if (strcmp (name, "push") == 0) |
| 10409 | { |
| 10410 | struct mips_option_stack *s; |
| 10411 | |
| 10412 | s = (struct mips_option_stack *) xmalloc (sizeof *s); |
| 10413 | s->next = mips_opts_stack; |
| 10414 | s->options = mips_opts; |
| 10415 | mips_opts_stack = s; |
| 10416 | } |
| 10417 | else if (strcmp (name, "pop") == 0) |
| 10418 | { |
| 10419 | struct mips_option_stack *s; |
| 10420 | |
| 10421 | s = mips_opts_stack; |
| 10422 | if (s == NULL) |
| 10423 | as_bad (_(".set pop with no .set push")); |
| 10424 | else |
| 10425 | { |
| 10426 | /* If we're changing the reorder mode we need to handle |
| 10427 | delay slots correctly. */ |
| 10428 | if (s->options.noreorder && ! mips_opts.noreorder) |
| 10429 | mips_emit_delays (true); |
| 10430 | else if (! s->options.noreorder && mips_opts.noreorder) |
| 10431 | { |
| 10432 | if (prev_nop_frag != NULL) |
| 10433 | { |
| 10434 | prev_nop_frag->fr_fix -= (prev_nop_frag_holds |
| 10435 | * (mips_opts.mips16 ? 2 : 4)); |
| 10436 | prev_nop_frag = NULL; |
| 10437 | } |
| 10438 | } |
| 10439 | |
| 10440 | mips_opts = s->options; |
| 10441 | mips_opts_stack = s->next; |
| 10442 | free (s); |
| 10443 | } |
| 10444 | } |
| 10445 | else |
| 10446 | { |
| 10447 | as_warn (_("Tried to set unrecognized symbol: %s\n"), name); |
| 10448 | } |
| 10449 | *input_line_pointer = ch; |
| 10450 | demand_empty_rest_of_line (); |
| 10451 | } |
| 10452 | |
| 10453 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
| 10454 | .option pic2. It means to generate SVR4 PIC calls. */ |
| 10455 | |
| 10456 | static void |
| 10457 | s_abicalls (ignore) |
| 10458 | int ignore ATTRIBUTE_UNUSED; |
| 10459 | { |
| 10460 | mips_pic = SVR4_PIC; |
| 10461 | if (USE_GLOBAL_POINTER_OPT) |
| 10462 | { |
| 10463 | if (g_switch_seen && g_switch_value != 0) |
| 10464 | as_warn (_("-G may not be used with SVR4 PIC code")); |
| 10465 | g_switch_value = 0; |
| 10466 | } |
| 10467 | bfd_set_gp_size (stdoutput, 0); |
| 10468 | demand_empty_rest_of_line (); |
| 10469 | } |
| 10470 | |
| 10471 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 |
| 10472 | PIC code. It sets the $gp register for the function based on the |
| 10473 | function address, which is in the register named in the argument. |
| 10474 | This uses a relocation against _gp_disp, which is handled specially |
| 10475 | by the linker. The result is: |
| 10476 | lui $gp,%hi(_gp_disp) |
| 10477 | addiu $gp,$gp,%lo(_gp_disp) |
| 10478 | addu $gp,$gp,.cpload argument |
| 10479 | The .cpload argument is normally $25 == $t9. */ |
| 10480 | |
| 10481 | static void |
| 10482 | s_cpload (ignore) |
| 10483 | int ignore ATTRIBUTE_UNUSED; |
| 10484 | { |
| 10485 | expressionS ex; |
| 10486 | int icnt = 0; |
| 10487 | |
| 10488 | /* If we are not generating SVR4 PIC code, .cpload is ignored. */ |
| 10489 | if (mips_pic != SVR4_PIC) |
| 10490 | { |
| 10491 | s_ignore (0); |
| 10492 | return; |
| 10493 | } |
| 10494 | |
| 10495 | /* .cpload should be a in .set noreorder section. */ |
| 10496 | if (mips_opts.noreorder == 0) |
| 10497 | as_warn (_(".cpload not in noreorder section")); |
| 10498 | |
| 10499 | ex.X_op = O_symbol; |
| 10500 | ex.X_add_symbol = symbol_find_or_make ("_gp_disp"); |
| 10501 | ex.X_op_symbol = NULL; |
| 10502 | ex.X_add_number = 0; |
| 10503 | |
| 10504 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
| 10505 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
| 10506 | |
| 10507 | macro_build_lui ((char *) NULL, &icnt, &ex, GP); |
| 10508 | macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP, |
| 10509 | (int) BFD_RELOC_LO16); |
| 10510 | |
| 10511 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t", |
| 10512 | GP, GP, tc_get_register (0)); |
| 10513 | |
| 10514 | demand_empty_rest_of_line (); |
| 10515 | } |
| 10516 | |
| 10517 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
| 10518 | offset from $sp. The offset is remembered, and after making a PIC |
| 10519 | call $gp is restored from that location. */ |
| 10520 | |
| 10521 | static void |
| 10522 | s_cprestore (ignore) |
| 10523 | int ignore ATTRIBUTE_UNUSED; |
| 10524 | { |
| 10525 | expressionS ex; |
| 10526 | int icnt = 0; |
| 10527 | |
| 10528 | /* If we are not generating SVR4 PIC code, .cprestore is ignored. */ |
| 10529 | if (mips_pic != SVR4_PIC) |
| 10530 | { |
| 10531 | s_ignore (0); |
| 10532 | return; |
| 10533 | } |
| 10534 | |
| 10535 | mips_cprestore_offset = get_absolute_expression (); |
| 10536 | |
| 10537 | ex.X_op = O_constant; |
| 10538 | ex.X_add_symbol = NULL; |
| 10539 | ex.X_op_symbol = NULL; |
| 10540 | ex.X_add_number = mips_cprestore_offset; |
| 10541 | |
| 10542 | macro_build ((char *) NULL, &icnt, &ex, |
| 10543 | HAVE_32BIT_ADDRESSES ? "sw" : "sd", |
| 10544 | "t,o(b)", GP, (int) BFD_RELOC_LO16, SP); |
| 10545 | |
| 10546 | demand_empty_rest_of_line (); |
| 10547 | } |
| 10548 | |
| 10549 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
| 10550 | code. It generates a 32 bit GP relative reloc. */ |
| 10551 | |
| 10552 | static void |
| 10553 | s_gpword (ignore) |
| 10554 | int ignore ATTRIBUTE_UNUSED; |
| 10555 | { |
| 10556 | symbolS *label; |
| 10557 | expressionS ex; |
| 10558 | char *p; |
| 10559 | |
| 10560 | /* When not generating PIC code, this is treated as .word. */ |
| 10561 | if (mips_pic != SVR4_PIC) |
| 10562 | { |
| 10563 | s_cons (2); |
| 10564 | return; |
| 10565 | } |
| 10566 | |
| 10567 | label = insn_labels != NULL ? insn_labels->label : NULL; |
| 10568 | mips_emit_delays (true); |
| 10569 | if (auto_align) |
| 10570 | mips_align (2, 0, label); |
| 10571 | mips_clear_insn_labels (); |
| 10572 | |
| 10573 | expression (&ex); |
| 10574 | |
| 10575 | if (ex.X_op != O_symbol || ex.X_add_number != 0) |
| 10576 | { |
| 10577 | as_bad (_("Unsupported use of .gpword")); |
| 10578 | ignore_rest_of_line (); |
| 10579 | } |
| 10580 | |
| 10581 | p = frag_more (4); |
| 10582 | md_number_to_chars (p, (valueT) 0, 4); |
| 10583 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0, |
| 10584 | BFD_RELOC_MIPS_GPREL32); |
| 10585 | |
| 10586 | demand_empty_rest_of_line (); |
| 10587 | } |
| 10588 | |
| 10589 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
| 10590 | tables in SVR4 PIC code. */ |
| 10591 | |
| 10592 | static void |
| 10593 | s_cpadd (ignore) |
| 10594 | int ignore ATTRIBUTE_UNUSED; |
| 10595 | { |
| 10596 | int icnt = 0; |
| 10597 | int reg; |
| 10598 | |
| 10599 | /* This is ignored when not generating SVR4 PIC code. */ |
| 10600 | if (mips_pic != SVR4_PIC) |
| 10601 | { |
| 10602 | s_ignore (0); |
| 10603 | return; |
| 10604 | } |
| 10605 | |
| 10606 | /* Add $gp to the register named as an argument. */ |
| 10607 | reg = tc_get_register (0); |
| 10608 | macro_build ((char *) NULL, &icnt, (expressionS *) NULL, |
| 10609 | HAVE_32BIT_ADDRESSES ? "addu" : "daddu", |
| 10610 | "d,v,t", reg, reg, GP); |
| 10611 | |
| 10612 | demand_empty_rest_of_line (); |
| 10613 | } |
| 10614 | |
| 10615 | /* Handle the .insn pseudo-op. This marks instruction labels in |
| 10616 | mips16 mode. This permits the linker to handle them specially, |
| 10617 | such as generating jalx instructions when needed. We also make |
| 10618 | them odd for the duration of the assembly, in order to generate the |
| 10619 | right sort of code. We will make them even in the adjust_symtab |
| 10620 | routine, while leaving them marked. This is convenient for the |
| 10621 | debugger and the disassembler. The linker knows to make them odd |
| 10622 | again. */ |
| 10623 | |
| 10624 | static void |
| 10625 | s_insn (ignore) |
| 10626 | int ignore ATTRIBUTE_UNUSED; |
| 10627 | { |
| 10628 | if (mips_opts.mips16) |
| 10629 | mips16_mark_labels (); |
| 10630 | |
| 10631 | demand_empty_rest_of_line (); |
| 10632 | } |
| 10633 | |
| 10634 | /* Handle a .stabn directive. We need these in order to mark a label |
| 10635 | as being a mips16 text label correctly. Sometimes the compiler |
| 10636 | will emit a label, followed by a .stabn, and then switch sections. |
| 10637 | If the label and .stabn are in mips16 mode, then the label is |
| 10638 | really a mips16 text label. */ |
| 10639 | |
| 10640 | static void |
| 10641 | s_mips_stab (type) |
| 10642 | int type; |
| 10643 | { |
| 10644 | if (type == 'n' && mips_opts.mips16) |
| 10645 | mips16_mark_labels (); |
| 10646 | |
| 10647 | s_stab (type); |
| 10648 | } |
| 10649 | |
| 10650 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. |
| 10651 | */ |
| 10652 | |
| 10653 | static void |
| 10654 | s_mips_weakext (ignore) |
| 10655 | int ignore ATTRIBUTE_UNUSED; |
| 10656 | { |
| 10657 | char *name; |
| 10658 | int c; |
| 10659 | symbolS *symbolP; |
| 10660 | expressionS exp; |
| 10661 | |
| 10662 | name = input_line_pointer; |
| 10663 | c = get_symbol_end (); |
| 10664 | symbolP = symbol_find_or_make (name); |
| 10665 | S_SET_WEAK (symbolP); |
| 10666 | *input_line_pointer = c; |
| 10667 | |
| 10668 | SKIP_WHITESPACE (); |
| 10669 | |
| 10670 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 10671 | { |
| 10672 | if (S_IS_DEFINED (symbolP)) |
| 10673 | { |
| 10674 | as_bad ("Ignoring attempt to redefine symbol `%s'.", |
| 10675 | S_GET_NAME (symbolP)); |
| 10676 | ignore_rest_of_line (); |
| 10677 | return; |
| 10678 | } |
| 10679 | |
| 10680 | if (*input_line_pointer == ',') |
| 10681 | { |
| 10682 | ++input_line_pointer; |
| 10683 | SKIP_WHITESPACE (); |
| 10684 | } |
| 10685 | |
| 10686 | expression (&exp); |
| 10687 | if (exp.X_op != O_symbol) |
| 10688 | { |
| 10689 | as_bad ("bad .weakext directive"); |
| 10690 | ignore_rest_of_line(); |
| 10691 | return; |
| 10692 | } |
| 10693 | symbol_set_value_expression (symbolP, &exp); |
| 10694 | } |
| 10695 | |
| 10696 | demand_empty_rest_of_line (); |
| 10697 | } |
| 10698 | |
| 10699 | /* Parse a register string into a number. Called from the ECOFF code |
| 10700 | to parse .frame. The argument is non-zero if this is the frame |
| 10701 | register, so that we can record it in mips_frame_reg. */ |
| 10702 | |
| 10703 | int |
| 10704 | tc_get_register (frame) |
| 10705 | int frame; |
| 10706 | { |
| 10707 | int reg; |
| 10708 | |
| 10709 | SKIP_WHITESPACE (); |
| 10710 | if (*input_line_pointer++ != '$') |
| 10711 | { |
| 10712 | as_warn (_("expected `$'")); |
| 10713 | reg = 0; |
| 10714 | } |
| 10715 | else if (isdigit ((unsigned char) *input_line_pointer)) |
| 10716 | { |
| 10717 | reg = get_absolute_expression (); |
| 10718 | if (reg < 0 || reg >= 32) |
| 10719 | { |
| 10720 | as_warn (_("Bad register number")); |
| 10721 | reg = 0; |
| 10722 | } |
| 10723 | } |
| 10724 | else |
| 10725 | { |
| 10726 | if (strncmp (input_line_pointer, "fp", 2) == 0) |
| 10727 | reg = FP; |
| 10728 | else if (strncmp (input_line_pointer, "sp", 2) == 0) |
| 10729 | reg = SP; |
| 10730 | else if (strncmp (input_line_pointer, "gp", 2) == 0) |
| 10731 | reg = GP; |
| 10732 | else if (strncmp (input_line_pointer, "at", 2) == 0) |
| 10733 | reg = AT; |
| 10734 | else |
| 10735 | { |
| 10736 | as_warn (_("Unrecognized register name")); |
| 10737 | reg = 0; |
| 10738 | } |
| 10739 | input_line_pointer += 2; |
| 10740 | } |
| 10741 | if (frame) |
| 10742 | mips_frame_reg = reg != 0 ? reg : SP; |
| 10743 | return reg; |
| 10744 | } |
| 10745 | |
| 10746 | valueT |
| 10747 | md_section_align (seg, addr) |
| 10748 | asection *seg; |
| 10749 | valueT addr; |
| 10750 | { |
| 10751 | int align = bfd_get_section_alignment (stdoutput, seg); |
| 10752 | |
| 10753 | #ifdef OBJ_ELF |
| 10754 | /* We don't need to align ELF sections to the full alignment. |
| 10755 | However, Irix 5 may prefer that we align them at least to a 16 |
| 10756 | byte boundary. We don't bother to align the sections if we are |
| 10757 | targeted for an embedded system. */ |
| 10758 | if (strcmp (TARGET_OS, "elf") == 0) |
| 10759 | return addr; |
| 10760 | if (align > 4) |
| 10761 | align = 4; |
| 10762 | #endif |
| 10763 | |
| 10764 | return ((addr + (1 << align) - 1) & (-1 << align)); |
| 10765 | } |
| 10766 | |
| 10767 | /* Utility routine, called from above as well. If called while the |
| 10768 | input file is still being read, it's only an approximation. (For |
| 10769 | example, a symbol may later become defined which appeared to be |
| 10770 | undefined earlier.) */ |
| 10771 | |
| 10772 | static int |
| 10773 | nopic_need_relax (sym, before_relaxing) |
| 10774 | symbolS *sym; |
| 10775 | int before_relaxing; |
| 10776 | { |
| 10777 | if (sym == 0) |
| 10778 | return 0; |
| 10779 | |
| 10780 | if (USE_GLOBAL_POINTER_OPT) |
| 10781 | { |
| 10782 | const char *symname; |
| 10783 | int change; |
| 10784 | |
| 10785 | /* Find out whether this symbol can be referenced off the GP |
| 10786 | register. It can be if it is smaller than the -G size or if |
| 10787 | it is in the .sdata or .sbss section. Certain symbols can |
| 10788 | not be referenced off the GP, although it appears as though |
| 10789 | they can. */ |
| 10790 | symname = S_GET_NAME (sym); |
| 10791 | if (symname != (const char *) NULL |
| 10792 | && (strcmp (symname, "eprol") == 0 |
| 10793 | || strcmp (symname, "etext") == 0 |
| 10794 | || strcmp (symname, "_gp") == 0 |
| 10795 | || strcmp (symname, "edata") == 0 |
| 10796 | || strcmp (symname, "_fbss") == 0 |
| 10797 | || strcmp (symname, "_fdata") == 0 |
| 10798 | || strcmp (symname, "_ftext") == 0 |
| 10799 | || strcmp (symname, "end") == 0 |
| 10800 | || strcmp (symname, "_gp_disp") == 0)) |
| 10801 | change = 1; |
| 10802 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
| 10803 | && (0 |
| 10804 | #ifndef NO_ECOFF_DEBUGGING |
| 10805 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
| 10806 | && (symbol_get_obj (sym)->ecoff_extern_size |
| 10807 | <= g_switch_value)) |
| 10808 | #endif |
| 10809 | /* We must defer this decision until after the whole |
| 10810 | file has been read, since there might be a .extern |
| 10811 | after the first use of this symbol. */ |
| 10812 | || (before_relaxing |
| 10813 | #ifndef NO_ECOFF_DEBUGGING |
| 10814 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
| 10815 | #endif |
| 10816 | && S_GET_VALUE (sym) == 0) |
| 10817 | || (S_GET_VALUE (sym) != 0 |
| 10818 | && S_GET_VALUE (sym) <= g_switch_value))) |
| 10819 | change = 0; |
| 10820 | else |
| 10821 | { |
| 10822 | const char *segname; |
| 10823 | |
| 10824 | segname = segment_name (S_GET_SEGMENT (sym)); |
| 10825 | assert (strcmp (segname, ".lit8") != 0 |
| 10826 | && strcmp (segname, ".lit4") != 0); |
| 10827 | change = (strcmp (segname, ".sdata") != 0 |
| 10828 | && strcmp (segname, ".sbss") != 0 |
| 10829 | && strncmp (segname, ".sdata.", 7) != 0 |
| 10830 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
| 10831 | } |
| 10832 | return change; |
| 10833 | } |
| 10834 | else |
| 10835 | /* We are not optimizing for the GP register. */ |
| 10836 | return 1; |
| 10837 | } |
| 10838 | |
| 10839 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
| 10840 | extended opcode. SEC is the section the frag is in. */ |
| 10841 | |
| 10842 | static int |
| 10843 | mips16_extended_frag (fragp, sec, stretch) |
| 10844 | fragS *fragp; |
| 10845 | asection *sec; |
| 10846 | long stretch; |
| 10847 | { |
| 10848 | int type; |
| 10849 | register const struct mips16_immed_operand *op; |
| 10850 | offsetT val; |
| 10851 | int mintiny, maxtiny; |
| 10852 | segT symsec; |
| 10853 | fragS *sym_frag; |
| 10854 | |
| 10855 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
| 10856 | return 0; |
| 10857 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
| 10858 | return 1; |
| 10859 | |
| 10860 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
| 10861 | op = mips16_immed_operands; |
| 10862 | while (op->type != type) |
| 10863 | { |
| 10864 | ++op; |
| 10865 | assert (op < mips16_immed_operands + MIPS16_NUM_IMMED); |
| 10866 | } |
| 10867 | |
| 10868 | if (op->unsp) |
| 10869 | { |
| 10870 | if (type == '<' || type == '>' || type == '[' || type == ']') |
| 10871 | { |
| 10872 | mintiny = 1; |
| 10873 | maxtiny = 1 << op->nbits; |
| 10874 | } |
| 10875 | else |
| 10876 | { |
| 10877 | mintiny = 0; |
| 10878 | maxtiny = (1 << op->nbits) - 1; |
| 10879 | } |
| 10880 | } |
| 10881 | else |
| 10882 | { |
| 10883 | mintiny = - (1 << (op->nbits - 1)); |
| 10884 | maxtiny = (1 << (op->nbits - 1)) - 1; |
| 10885 | } |
| 10886 | |
| 10887 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
| 10888 | val = S_GET_VALUE (fragp->fr_symbol); |
| 10889 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
| 10890 | |
| 10891 | if (op->pcrel) |
| 10892 | { |
| 10893 | addressT addr; |
| 10894 | |
| 10895 | /* We won't have the section when we are called from |
| 10896 | mips_relax_frag. However, we will always have been called |
| 10897 | from md_estimate_size_before_relax first. If this is a |
| 10898 | branch to a different section, we mark it as such. If SEC is |
| 10899 | NULL, and the frag is not marked, then it must be a branch to |
| 10900 | the same section. */ |
| 10901 | if (sec == NULL) |
| 10902 | { |
| 10903 | if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype)) |
| 10904 | return 1; |
| 10905 | } |
| 10906 | else |
| 10907 | { |
| 10908 | /* Must have been called from md_estimate_size_before_relax. */ |
| 10909 | if (symsec != sec) |
| 10910 | { |
| 10911 | fragp->fr_subtype = |
| 10912 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); |
| 10913 | |
| 10914 | /* FIXME: We should support this, and let the linker |
| 10915 | catch branches and loads that are out of range. */ |
| 10916 | as_bad_where (fragp->fr_file, fragp->fr_line, |
| 10917 | _("unsupported PC relative reference to different section")); |
| 10918 | |
| 10919 | return 1; |
| 10920 | } |
| 10921 | if (fragp != sym_frag && sym_frag->fr_address == 0) |
| 10922 | /* Assume non-extended on the first relaxation pass. |
| 10923 | The address we have calculated will be bogus if this is |
| 10924 | a forward branch to another frag, as the forward frag |
| 10925 | will have fr_address == 0. */ |
| 10926 | return 0; |
| 10927 | } |
| 10928 | |
| 10929 | /* In this case, we know for sure that the symbol fragment is in |
| 10930 | the same section. If the relax_marker of the symbol fragment |
| 10931 | differs from the relax_marker of this fragment, we have not |
| 10932 | yet adjusted the symbol fragment fr_address. We want to add |
| 10933 | in STRETCH in order to get a better estimate of the address. |
| 10934 | This particularly matters because of the shift bits. */ |
| 10935 | if (stretch != 0 |
| 10936 | && sym_frag->relax_marker != fragp->relax_marker) |
| 10937 | { |
| 10938 | fragS *f; |
| 10939 | |
| 10940 | /* Adjust stretch for any alignment frag. Note that if have |
| 10941 | been expanding the earlier code, the symbol may be |
| 10942 | defined in what appears to be an earlier frag. FIXME: |
| 10943 | This doesn't handle the fr_subtype field, which specifies |
| 10944 | a maximum number of bytes to skip when doing an |
| 10945 | alignment. */ |
| 10946 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
| 10947 | { |
| 10948 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
| 10949 | { |
| 10950 | if (stretch < 0) |
| 10951 | stretch = - ((- stretch) |
| 10952 | & ~ ((1 << (int) f->fr_offset) - 1)); |
| 10953 | else |
| 10954 | stretch &= ~ ((1 << (int) f->fr_offset) - 1); |
| 10955 | if (stretch == 0) |
| 10956 | break; |
| 10957 | } |
| 10958 | } |
| 10959 | if (f != NULL) |
| 10960 | val += stretch; |
| 10961 | } |
| 10962 | |
| 10963 | addr = fragp->fr_address + fragp->fr_fix; |
| 10964 | |
| 10965 | /* The base address rules are complicated. The base address of |
| 10966 | a branch is the following instruction. The base address of a |
| 10967 | PC relative load or add is the instruction itself, but if it |
| 10968 | is in a delay slot (in which case it can not be extended) use |
| 10969 | the address of the instruction whose delay slot it is in. */ |
| 10970 | if (type == 'p' || type == 'q') |
| 10971 | { |
| 10972 | addr += 2; |
| 10973 | |
| 10974 | /* If we are currently assuming that this frag should be |
| 10975 | extended, then, the current address is two bytes |
| 10976 | higher. */ |
| 10977 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 10978 | addr += 2; |
| 10979 | |
| 10980 | /* Ignore the low bit in the target, since it will be set |
| 10981 | for a text label. */ |
| 10982 | if ((val & 1) != 0) |
| 10983 | --val; |
| 10984 | } |
| 10985 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
| 10986 | addr -= 4; |
| 10987 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) |
| 10988 | addr -= 2; |
| 10989 | |
| 10990 | val -= addr & ~ ((1 << op->shift) - 1); |
| 10991 | |
| 10992 | /* Branch offsets have an implicit 0 in the lowest bit. */ |
| 10993 | if (type == 'p' || type == 'q') |
| 10994 | val /= 2; |
| 10995 | |
| 10996 | /* If any of the shifted bits are set, we must use an extended |
| 10997 | opcode. If the address depends on the size of this |
| 10998 | instruction, this can lead to a loop, so we arrange to always |
| 10999 | use an extended opcode. We only check this when we are in |
| 11000 | the main relaxation loop, when SEC is NULL. */ |
| 11001 | if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL) |
| 11002 | { |
| 11003 | fragp->fr_subtype = |
| 11004 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); |
| 11005 | return 1; |
| 11006 | } |
| 11007 | |
| 11008 | /* If we are about to mark a frag as extended because the value |
| 11009 | is precisely maxtiny + 1, then there is a chance of an |
| 11010 | infinite loop as in the following code: |
| 11011 | la $4,foo |
| 11012 | .skip 1020 |
| 11013 | .align 2 |
| 11014 | foo: |
| 11015 | In this case when the la is extended, foo is 0x3fc bytes |
| 11016 | away, so the la can be shrunk, but then foo is 0x400 away, so |
| 11017 | the la must be extended. To avoid this loop, we mark the |
| 11018 | frag as extended if it was small, and is about to become |
| 11019 | extended with a value of maxtiny + 1. */ |
| 11020 | if (val == ((maxtiny + 1) << op->shift) |
| 11021 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype) |
| 11022 | && sec == NULL) |
| 11023 | { |
| 11024 | fragp->fr_subtype = |
| 11025 | RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype); |
| 11026 | return 1; |
| 11027 | } |
| 11028 | } |
| 11029 | else if (symsec != absolute_section && sec != NULL) |
| 11030 | as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation")); |
| 11031 | |
| 11032 | if ((val & ((1 << op->shift) - 1)) != 0 |
| 11033 | || val < (mintiny << op->shift) |
| 11034 | || val > (maxtiny << op->shift)) |
| 11035 | return 1; |
| 11036 | else |
| 11037 | return 0; |
| 11038 | } |
| 11039 | |
| 11040 | /* Estimate the size of a frag before relaxing. Unless this is the |
| 11041 | mips16, we are not really relaxing here, and the final size is |
| 11042 | encoded in the subtype information. For the mips16, we have to |
| 11043 | decide whether we are using an extended opcode or not. */ |
| 11044 | |
| 11045 | int |
| 11046 | md_estimate_size_before_relax (fragp, segtype) |
| 11047 | fragS *fragp; |
| 11048 | asection *segtype; |
| 11049 | { |
| 11050 | int change = 0; |
| 11051 | boolean linkonce = false; |
| 11052 | |
| 11053 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
| 11054 | { |
| 11055 | if (mips16_extended_frag (fragp, segtype, 0)) |
| 11056 | { |
| 11057 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); |
| 11058 | return 4; |
| 11059 | } |
| 11060 | else |
| 11061 | { |
| 11062 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); |
| 11063 | return 2; |
| 11064 | } |
| 11065 | } |
| 11066 | |
| 11067 | if (mips_pic == NO_PIC) |
| 11068 | { |
| 11069 | change = nopic_need_relax (fragp->fr_symbol, 0); |
| 11070 | } |
| 11071 | else if (mips_pic == SVR4_PIC) |
| 11072 | { |
| 11073 | symbolS *sym; |
| 11074 | asection *symsec; |
| 11075 | |
| 11076 | sym = fragp->fr_symbol; |
| 11077 | |
| 11078 | /* Handle the case of a symbol equated to another symbol. */ |
| 11079 | while (symbol_equated_p (sym) |
| 11080 | && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym))) |
| 11081 | { |
| 11082 | symbolS *n; |
| 11083 | |
| 11084 | /* It's possible to get a loop here in a badly written |
| 11085 | program. */ |
| 11086 | n = symbol_get_value_expression (sym)->X_add_symbol; |
| 11087 | if (n == sym) |
| 11088 | break; |
| 11089 | sym = n; |
| 11090 | } |
| 11091 | |
| 11092 | symsec = S_GET_SEGMENT (sym); |
| 11093 | |
| 11094 | /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */ |
| 11095 | if (symsec != segtype && ! S_IS_LOCAL (sym)) |
| 11096 | { |
| 11097 | if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) |
| 11098 | != 0) |
| 11099 | linkonce = true; |
| 11100 | |
| 11101 | /* The GNU toolchain uses an extension for ELF: a section |
| 11102 | beginning with the magic string .gnu.linkonce is a linkonce |
| 11103 | section. */ |
| 11104 | if (strncmp (segment_name (symsec), ".gnu.linkonce", |
| 11105 | sizeof ".gnu.linkonce" - 1) == 0) |
| 11106 | linkonce = true; |
| 11107 | } |
| 11108 | |
| 11109 | /* This must duplicate the test in adjust_reloc_syms. */ |
| 11110 | change = (symsec != &bfd_und_section |
| 11111 | && symsec != &bfd_abs_section |
| 11112 | && ! bfd_is_com_section (symsec) |
| 11113 | && !linkonce |
| 11114 | #ifdef OBJ_ELF |
| 11115 | /* A global or weak symbol is treated as external. */ |
| 11116 | && (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 11117 | && ! (S_IS_EXTERN (sym) || S_IS_WEAK (sym))) |
| 11118 | #endif |
| 11119 | ); |
| 11120 | } |
| 11121 | else |
| 11122 | abort (); |
| 11123 | |
| 11124 | if (change) |
| 11125 | { |
| 11126 | /* Record the offset to the first reloc in the fr_opcode field. |
| 11127 | This lets md_convert_frag and tc_gen_reloc know that the code |
| 11128 | must be expanded. */ |
| 11129 | fragp->fr_opcode = (fragp->fr_literal |
| 11130 | + fragp->fr_fix |
| 11131 | - RELAX_OLD (fragp->fr_subtype) |
| 11132 | + RELAX_RELOC1 (fragp->fr_subtype)); |
| 11133 | /* FIXME: This really needs as_warn_where. */ |
| 11134 | if (RELAX_WARN (fragp->fr_subtype)) |
| 11135 | as_warn (_("AT used after \".set noat\" or macro used after " |
| 11136 | "\".set nomacro\"")); |
| 11137 | |
| 11138 | return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype); |
| 11139 | } |
| 11140 | |
| 11141 | return 0; |
| 11142 | } |
| 11143 | |
| 11144 | /* This is called to see whether a reloc against a defined symbol |
| 11145 | should be converted into a reloc against a section. Don't adjust |
| 11146 | MIPS16 jump relocations, so we don't have to worry about the format |
| 11147 | of the offset in the .o file. Don't adjust relocations against |
| 11148 | mips16 symbols, so that the linker can find them if it needs to set |
| 11149 | up a stub. */ |
| 11150 | |
| 11151 | int |
| 11152 | mips_fix_adjustable (fixp) |
| 11153 | fixS *fixp; |
| 11154 | { |
| 11155 | #ifdef OBJ_ELF |
| 11156 | /* Prevent all adjustments to global symbols. */ |
| 11157 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 11158 | && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))) |
| 11159 | return 0; |
| 11160 | #endif |
| 11161 | if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP) |
| 11162 | return 0; |
| 11163 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 11164 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 11165 | return 0; |
| 11166 | if (fixp->fx_addsy == NULL) |
| 11167 | return 1; |
| 11168 | #ifdef OBJ_ELF |
| 11169 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
| 11170 | && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16 |
| 11171 | && fixp->fx_subsy == NULL) |
| 11172 | return 0; |
| 11173 | #endif |
| 11174 | return 1; |
| 11175 | } |
| 11176 | |
| 11177 | /* Translate internal representation of relocation info to BFD target |
| 11178 | format. */ |
| 11179 | |
| 11180 | arelent ** |
| 11181 | tc_gen_reloc (section, fixp) |
| 11182 | asection *section ATTRIBUTE_UNUSED; |
| 11183 | fixS *fixp; |
| 11184 | { |
| 11185 | static arelent *retval[4]; |
| 11186 | arelent *reloc; |
| 11187 | bfd_reloc_code_real_type code; |
| 11188 | |
| 11189 | reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent)); |
| 11190 | retval[1] = NULL; |
| 11191 | |
| 11192 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 11193 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 11194 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 11195 | |
| 11196 | if (mips_pic == EMBEDDED_PIC |
| 11197 | && SWITCH_TABLE (fixp)) |
| 11198 | { |
| 11199 | /* For a switch table entry we use a special reloc. The addend |
| 11200 | is actually the difference between the reloc address and the |
| 11201 | subtrahend. */ |
| 11202 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
| 11203 | if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour) |
| 11204 | as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc")); |
| 11205 | fixp->fx_r_type = BFD_RELOC_GPREL32; |
| 11206 | } |
| 11207 | else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 11208 | reloc->addend = fixp->fx_addnumber; |
| 11209 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16) |
| 11210 | { |
| 11211 | /* We use a special addend for an internal RELLO reloc. */ |
| 11212 | if (symbol_section_p (fixp->fx_addsy)) |
| 11213 | reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy); |
| 11214 | else |
| 11215 | reloc->addend = fixp->fx_addnumber + reloc->address; |
| 11216 | } |
| 11217 | else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S) |
| 11218 | { |
| 11219 | assert (fixp->fx_next != NULL |
| 11220 | && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16); |
| 11221 | /* We use a special addend for an internal RELHI reloc. The |
| 11222 | reloc is relative to the RELLO; adjust the addend |
| 11223 | accordingly. */ |
| 11224 | if (symbol_section_p (fixp->fx_addsy)) |
| 11225 | reloc->addend = (fixp->fx_next->fx_frag->fr_address |
| 11226 | + fixp->fx_next->fx_where |
| 11227 | - S_GET_VALUE (fixp->fx_subsy)); |
| 11228 | else |
| 11229 | reloc->addend = (fixp->fx_addnumber |
| 11230 | + fixp->fx_next->fx_frag->fr_address |
| 11231 | + fixp->fx_next->fx_where); |
| 11232 | } |
| 11233 | else |
| 11234 | { |
| 11235 | if (OUTPUT_FLAVOR != bfd_target_aout_flavour) |
| 11236 | /* A gruesome hack which is a result of the gruesome gas reloc |
| 11237 | handling. */ |
| 11238 | reloc->addend = reloc->address; |
| 11239 | else |
| 11240 | reloc->addend = -reloc->address; |
| 11241 | } |
| 11242 | |
| 11243 | /* If this is a variant frag, we may need to adjust the existing |
| 11244 | reloc and generate a new one. */ |
| 11245 | if (fixp->fx_frag->fr_opcode != NULL |
| 11246 | && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
| 11247 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16 |
| 11248 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16 |
| 11249 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
| 11250 | || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16 |
| 11251 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 |
| 11252 | || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16)) |
| 11253 | { |
| 11254 | arelent *reloc2; |
| 11255 | |
| 11256 | assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype)); |
| 11257 | |
| 11258 | /* If this is not the last reloc in this frag, then we have two |
| 11259 | GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a |
| 11260 | CALL_HI16/CALL_LO16, both of which are being replaced. Let |
| 11261 | the second one handle all of them. */ |
| 11262 | if (fixp->fx_next != NULL |
| 11263 | && fixp->fx_frag == fixp->fx_next->fx_frag) |
| 11264 | { |
| 11265 | assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL |
| 11266 | && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL) |
| 11267 | || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16 |
| 11268 | && (fixp->fx_next->fx_r_type |
| 11269 | == BFD_RELOC_MIPS_GOT_LO16)) |
| 11270 | || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16 |
| 11271 | && (fixp->fx_next->fx_r_type |
| 11272 | == BFD_RELOC_MIPS_CALL_LO16))); |
| 11273 | retval[0] = NULL; |
| 11274 | return retval; |
| 11275 | } |
| 11276 | |
| 11277 | fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal; |
| 11278 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 11279 | reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent)); |
| 11280 | retval[2] = NULL; |
| 11281 | reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
| 11282 | *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 11283 | reloc2->address = (reloc->address |
| 11284 | + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype) |
| 11285 | - RELAX_RELOC1 (fixp->fx_frag->fr_subtype))); |
| 11286 | reloc2->addend = fixp->fx_addnumber; |
| 11287 | reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16); |
| 11288 | assert (reloc2->howto != NULL); |
| 11289 | |
| 11290 | if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype)) |
| 11291 | { |
| 11292 | arelent *reloc3; |
| 11293 | |
| 11294 | reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent)); |
| 11295 | retval[3] = NULL; |
| 11296 | *reloc3 = *reloc2; |
| 11297 | reloc3->address += 4; |
| 11298 | } |
| 11299 | |
| 11300 | if (mips_pic == NO_PIC) |
| 11301 | { |
| 11302 | assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL); |
| 11303 | fixp->fx_r_type = BFD_RELOC_HI16_S; |
| 11304 | } |
| 11305 | else if (mips_pic == SVR4_PIC) |
| 11306 | { |
| 11307 | switch (fixp->fx_r_type) |
| 11308 | { |
| 11309 | default: |
| 11310 | abort (); |
| 11311 | case BFD_RELOC_MIPS_GOT16: |
| 11312 | break; |
| 11313 | case BFD_RELOC_MIPS_CALL16: |
| 11314 | case BFD_RELOC_MIPS_GOT_LO16: |
| 11315 | case BFD_RELOC_MIPS_CALL_LO16: |
| 11316 | fixp->fx_r_type = BFD_RELOC_MIPS_GOT16; |
| 11317 | break; |
| 11318 | } |
| 11319 | } |
| 11320 | else |
| 11321 | abort (); |
| 11322 | } |
| 11323 | |
| 11324 | /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry |
| 11325 | to be used in the relocation's section offset. */ |
| 11326 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 11327 | { |
| 11328 | reloc->address = reloc->addend; |
| 11329 | reloc->addend = 0; |
| 11330 | } |
| 11331 | |
| 11332 | /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that |
| 11333 | fixup_segment converted a non-PC relative reloc into a PC |
| 11334 | relative reloc. In such a case, we need to convert the reloc |
| 11335 | code. */ |
| 11336 | code = fixp->fx_r_type; |
| 11337 | if (fixp->fx_pcrel) |
| 11338 | { |
| 11339 | switch (code) |
| 11340 | { |
| 11341 | case BFD_RELOC_8: |
| 11342 | code = BFD_RELOC_8_PCREL; |
| 11343 | break; |
| 11344 | case BFD_RELOC_16: |
| 11345 | code = BFD_RELOC_16_PCREL; |
| 11346 | break; |
| 11347 | case BFD_RELOC_32: |
| 11348 | code = BFD_RELOC_32_PCREL; |
| 11349 | break; |
| 11350 | case BFD_RELOC_64: |
| 11351 | code = BFD_RELOC_64_PCREL; |
| 11352 | break; |
| 11353 | case BFD_RELOC_8_PCREL: |
| 11354 | case BFD_RELOC_16_PCREL: |
| 11355 | case BFD_RELOC_32_PCREL: |
| 11356 | case BFD_RELOC_64_PCREL: |
| 11357 | case BFD_RELOC_16_PCREL_S2: |
| 11358 | case BFD_RELOC_PCREL_HI16_S: |
| 11359 | case BFD_RELOC_PCREL_LO16: |
| 11360 | break; |
| 11361 | default: |
| 11362 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 11363 | _("Cannot make %s relocation PC relative"), |
| 11364 | bfd_get_reloc_code_name (code)); |
| 11365 | } |
| 11366 | } |
| 11367 | |
| 11368 | /* To support a PC relative reloc when generating embedded PIC code |
| 11369 | for ECOFF, we use a Cygnus extension. We check for that here to |
| 11370 | make sure that we don't let such a reloc escape normally. */ |
| 11371 | if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour |
| 11372 | || OUTPUT_FLAVOR == bfd_target_elf_flavour) |
| 11373 | && code == BFD_RELOC_16_PCREL_S2 |
| 11374 | && mips_pic != EMBEDDED_PIC) |
| 11375 | reloc->howto = NULL; |
| 11376 | else |
| 11377 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 11378 | |
| 11379 | if (reloc->howto == NULL) |
| 11380 | { |
| 11381 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 11382 | _("Can not represent %s relocation in this object file format"), |
| 11383 | bfd_get_reloc_code_name (code)); |
| 11384 | retval[0] = NULL; |
| 11385 | } |
| 11386 | |
| 11387 | return retval; |
| 11388 | } |
| 11389 | |
| 11390 | /* Relax a machine dependent frag. This returns the amount by which |
| 11391 | the current size of the frag should change. */ |
| 11392 | |
| 11393 | int |
| 11394 | mips_relax_frag (fragp, stretch) |
| 11395 | fragS *fragp; |
| 11396 | long stretch; |
| 11397 | { |
| 11398 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
| 11399 | return 0; |
| 11400 | |
| 11401 | if (mips16_extended_frag (fragp, (asection *) NULL, stretch)) |
| 11402 | { |
| 11403 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 11404 | return 0; |
| 11405 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); |
| 11406 | return 2; |
| 11407 | } |
| 11408 | else |
| 11409 | { |
| 11410 | if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 11411 | return 0; |
| 11412 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); |
| 11413 | return -2; |
| 11414 | } |
| 11415 | |
| 11416 | return 0; |
| 11417 | } |
| 11418 | |
| 11419 | /* Convert a machine dependent frag. */ |
| 11420 | |
| 11421 | void |
| 11422 | md_convert_frag (abfd, asec, fragp) |
| 11423 | bfd *abfd ATTRIBUTE_UNUSED; |
| 11424 | segT asec; |
| 11425 | fragS *fragp; |
| 11426 | { |
| 11427 | int old, new; |
| 11428 | char *fixptr; |
| 11429 | |
| 11430 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
| 11431 | { |
| 11432 | int type; |
| 11433 | register const struct mips16_immed_operand *op; |
| 11434 | boolean small, ext; |
| 11435 | offsetT val; |
| 11436 | bfd_byte *buf; |
| 11437 | unsigned long insn; |
| 11438 | boolean use_extend; |
| 11439 | unsigned short extend; |
| 11440 | |
| 11441 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
| 11442 | op = mips16_immed_operands; |
| 11443 | while (op->type != type) |
| 11444 | ++op; |
| 11445 | |
| 11446 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 11447 | { |
| 11448 | small = false; |
| 11449 | ext = true; |
| 11450 | } |
| 11451 | else |
| 11452 | { |
| 11453 | small = true; |
| 11454 | ext = false; |
| 11455 | } |
| 11456 | |
| 11457 | resolve_symbol_value (fragp->fr_symbol); |
| 11458 | val = S_GET_VALUE (fragp->fr_symbol); |
| 11459 | if (op->pcrel) |
| 11460 | { |
| 11461 | addressT addr; |
| 11462 | |
| 11463 | addr = fragp->fr_address + fragp->fr_fix; |
| 11464 | |
| 11465 | /* The rules for the base address of a PC relative reloc are |
| 11466 | complicated; see mips16_extended_frag. */ |
| 11467 | if (type == 'p' || type == 'q') |
| 11468 | { |
| 11469 | addr += 2; |
| 11470 | if (ext) |
| 11471 | addr += 2; |
| 11472 | /* Ignore the low bit in the target, since it will be |
| 11473 | set for a text label. */ |
| 11474 | if ((val & 1) != 0) |
| 11475 | --val; |
| 11476 | } |
| 11477 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
| 11478 | addr -= 4; |
| 11479 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) |
| 11480 | addr -= 2; |
| 11481 | |
| 11482 | addr &= ~ (addressT) ((1 << op->shift) - 1); |
| 11483 | val -= addr; |
| 11484 | |
| 11485 | /* Make sure the section winds up with the alignment we have |
| 11486 | assumed. */ |
| 11487 | if (op->shift > 0) |
| 11488 | record_alignment (asec, op->shift); |
| 11489 | } |
| 11490 | |
| 11491 | if (ext |
| 11492 | && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
| 11493 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype))) |
| 11494 | as_warn_where (fragp->fr_file, fragp->fr_line, |
| 11495 | _("extended instruction in delay slot")); |
| 11496 | |
| 11497 | buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix); |
| 11498 | |
| 11499 | if (target_big_endian) |
| 11500 | insn = bfd_getb16 (buf); |
| 11501 | else |
| 11502 | insn = bfd_getl16 (buf); |
| 11503 | |
| 11504 | mips16_immed (fragp->fr_file, fragp->fr_line, type, val, |
| 11505 | RELAX_MIPS16_USER_EXT (fragp->fr_subtype), |
| 11506 | small, ext, &insn, &use_extend, &extend); |
| 11507 | |
| 11508 | if (use_extend) |
| 11509 | { |
| 11510 | md_number_to_chars (buf, 0xf000 | extend, 2); |
| 11511 | fragp->fr_fix += 2; |
| 11512 | buf += 2; |
| 11513 | } |
| 11514 | |
| 11515 | md_number_to_chars (buf, insn, 2); |
| 11516 | fragp->fr_fix += 2; |
| 11517 | buf += 2; |
| 11518 | } |
| 11519 | else |
| 11520 | { |
| 11521 | if (fragp->fr_opcode == NULL) |
| 11522 | return; |
| 11523 | |
| 11524 | old = RELAX_OLD (fragp->fr_subtype); |
| 11525 | new = RELAX_NEW (fragp->fr_subtype); |
| 11526 | fixptr = fragp->fr_literal + fragp->fr_fix; |
| 11527 | |
| 11528 | if (new > 0) |
| 11529 | memcpy (fixptr - old, fixptr, new); |
| 11530 | |
| 11531 | fragp->fr_fix += new - old; |
| 11532 | } |
| 11533 | } |
| 11534 | |
| 11535 | #ifdef OBJ_ELF |
| 11536 | |
| 11537 | /* This function is called after the relocs have been generated. |
| 11538 | We've been storing mips16 text labels as odd. Here we convert them |
| 11539 | back to even for the convenience of the debugger. */ |
| 11540 | |
| 11541 | void |
| 11542 | mips_frob_file_after_relocs () |
| 11543 | { |
| 11544 | asymbol **syms; |
| 11545 | unsigned int count, i; |
| 11546 | |
| 11547 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
| 11548 | return; |
| 11549 | |
| 11550 | syms = bfd_get_outsymbols (stdoutput); |
| 11551 | count = bfd_get_symcount (stdoutput); |
| 11552 | for (i = 0; i < count; i++, syms++) |
| 11553 | { |
| 11554 | if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16 |
| 11555 | && ((*syms)->value & 1) != 0) |
| 11556 | { |
| 11557 | (*syms)->value &= ~1; |
| 11558 | /* If the symbol has an odd size, it was probably computed |
| 11559 | incorrectly, so adjust that as well. */ |
| 11560 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) |
| 11561 | ++elf_symbol (*syms)->internal_elf_sym.st_size; |
| 11562 | } |
| 11563 | } |
| 11564 | } |
| 11565 | |
| 11566 | #endif |
| 11567 | |
| 11568 | /* This function is called whenever a label is defined. It is used |
| 11569 | when handling branch delays; if a branch has a label, we assume we |
| 11570 | can not move it. */ |
| 11571 | |
| 11572 | void |
| 11573 | mips_define_label (sym) |
| 11574 | symbolS *sym; |
| 11575 | { |
| 11576 | struct insn_label_list *l; |
| 11577 | |
| 11578 | if (free_insn_labels == NULL) |
| 11579 | l = (struct insn_label_list *) xmalloc (sizeof *l); |
| 11580 | else |
| 11581 | { |
| 11582 | l = free_insn_labels; |
| 11583 | free_insn_labels = l->next; |
| 11584 | } |
| 11585 | |
| 11586 | l->label = sym; |
| 11587 | l->next = insn_labels; |
| 11588 | insn_labels = l; |
| 11589 | } |
| 11590 | \f |
| 11591 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
| 11592 | |
| 11593 | /* Some special processing for a MIPS ELF file. */ |
| 11594 | |
| 11595 | void |
| 11596 | mips_elf_final_processing () |
| 11597 | { |
| 11598 | /* Write out the register information. */ |
| 11599 | if (! mips_64) |
| 11600 | { |
| 11601 | Elf32_RegInfo s; |
| 11602 | |
| 11603 | s.ri_gprmask = mips_gprmask; |
| 11604 | s.ri_cprmask[0] = mips_cprmask[0]; |
| 11605 | s.ri_cprmask[1] = mips_cprmask[1]; |
| 11606 | s.ri_cprmask[2] = mips_cprmask[2]; |
| 11607 | s.ri_cprmask[3] = mips_cprmask[3]; |
| 11608 | /* The gp_value field is set by the MIPS ELF backend. */ |
| 11609 | |
| 11610 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, |
| 11611 | ((Elf32_External_RegInfo *) |
| 11612 | mips_regmask_frag)); |
| 11613 | } |
| 11614 | else |
| 11615 | { |
| 11616 | Elf64_Internal_RegInfo s; |
| 11617 | |
| 11618 | s.ri_gprmask = mips_gprmask; |
| 11619 | s.ri_pad = 0; |
| 11620 | s.ri_cprmask[0] = mips_cprmask[0]; |
| 11621 | s.ri_cprmask[1] = mips_cprmask[1]; |
| 11622 | s.ri_cprmask[2] = mips_cprmask[2]; |
| 11623 | s.ri_cprmask[3] = mips_cprmask[3]; |
| 11624 | /* The gp_value field is set by the MIPS ELF backend. */ |
| 11625 | |
| 11626 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, |
| 11627 | ((Elf64_External_RegInfo *) |
| 11628 | mips_regmask_frag)); |
| 11629 | } |
| 11630 | |
| 11631 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some |
| 11632 | sort of BFD interface for this. */ |
| 11633 | if (mips_any_noreorder) |
| 11634 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; |
| 11635 | if (mips_pic != NO_PIC) |
| 11636 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
| 11637 | |
| 11638 | /* Set the MIPS ELF ABI flags. */ |
| 11639 | if (mips_abi_string == NULL) |
| 11640 | ; |
| 11641 | else if (strcmp (mips_abi_string, "32") == 0) |
| 11642 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
| 11643 | else if (strcmp (mips_abi_string, "o64") == 0) |
| 11644 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
| 11645 | else if (strcmp (mips_abi_string, "eabi") == 0) |
| 11646 | { |
| 11647 | if (mips_eabi64) |
| 11648 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
| 11649 | else |
| 11650 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; |
| 11651 | } |
| 11652 | else if (strcmp (mips_abi_string, "n32") == 0) |
| 11653 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
| 11654 | |
| 11655 | /* Nothing to do for "64". */ |
| 11656 | |
| 11657 | if (mips_32bitmode) |
| 11658 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; |
| 11659 | } |
| 11660 | |
| 11661 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |
| 11662 | \f |
| 11663 | typedef struct proc { |
| 11664 | symbolS *isym; |
| 11665 | unsigned long reg_mask; |
| 11666 | unsigned long reg_offset; |
| 11667 | unsigned long fpreg_mask; |
| 11668 | unsigned long fpreg_offset; |
| 11669 | unsigned long frame_offset; |
| 11670 | unsigned long frame_reg; |
| 11671 | unsigned long pc_reg; |
| 11672 | } procS; |
| 11673 | |
| 11674 | static procS cur_proc; |
| 11675 | static procS *cur_proc_ptr; |
| 11676 | static int numprocs; |
| 11677 | |
| 11678 | /* Fill in an rs_align_code fragment. */ |
| 11679 | |
| 11680 | void |
| 11681 | mips_handle_align (fragp) |
| 11682 | fragS *fragp; |
| 11683 | { |
| 11684 | if (fragp->fr_type != rs_align_code) |
| 11685 | return; |
| 11686 | |
| 11687 | if (mips_opts.mips16) |
| 11688 | { |
| 11689 | static const unsigned char be_nop[] = { 0x65, 0x00 }; |
| 11690 | static const unsigned char le_nop[] = { 0x00, 0x65 }; |
| 11691 | |
| 11692 | int bytes; |
| 11693 | char *p; |
| 11694 | |
| 11695 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
| 11696 | p = fragp->fr_literal + fragp->fr_fix; |
| 11697 | |
| 11698 | if (bytes & 1) |
| 11699 | { |
| 11700 | *p++ = 0; |
| 11701 | fragp->fr_fix += 1; |
| 11702 | } |
| 11703 | |
| 11704 | memcpy (p, (target_big_endian ? be_nop : le_nop), 2); |
| 11705 | fragp->fr_var = 2; |
| 11706 | } |
| 11707 | |
| 11708 | /* For mips32, a nop is a zero, which we trivially get by doing nothing. */ |
| 11709 | } |
| 11710 | |
| 11711 | static void |
| 11712 | md_obj_begin () |
| 11713 | { |
| 11714 | } |
| 11715 | |
| 11716 | static void |
| 11717 | md_obj_end () |
| 11718 | { |
| 11719 | /* check for premature end, nesting errors, etc */ |
| 11720 | if (cur_proc_ptr) |
| 11721 | as_warn (_("missing .end at end of assembly")); |
| 11722 | } |
| 11723 | |
| 11724 | static long |
| 11725 | get_number () |
| 11726 | { |
| 11727 | int negative = 0; |
| 11728 | long val = 0; |
| 11729 | |
| 11730 | if (*input_line_pointer == '-') |
| 11731 | { |
| 11732 | ++input_line_pointer; |
| 11733 | negative = 1; |
| 11734 | } |
| 11735 | if (!isdigit ((unsigned char) *input_line_pointer)) |
| 11736 | as_bad (_("Expected simple number.")); |
| 11737 | if (input_line_pointer[0] == '0') |
| 11738 | { |
| 11739 | if (input_line_pointer[1] == 'x') |
| 11740 | { |
| 11741 | input_line_pointer += 2; |
| 11742 | while (isxdigit ((unsigned char) *input_line_pointer)) |
| 11743 | { |
| 11744 | val <<= 4; |
| 11745 | val |= hex_value (*input_line_pointer++); |
| 11746 | } |
| 11747 | return negative ? -val : val; |
| 11748 | } |
| 11749 | else |
| 11750 | { |
| 11751 | ++input_line_pointer; |
| 11752 | while (isdigit ((unsigned char) *input_line_pointer)) |
| 11753 | { |
| 11754 | val <<= 3; |
| 11755 | val |= *input_line_pointer++ - '0'; |
| 11756 | } |
| 11757 | return negative ? -val : val; |
| 11758 | } |
| 11759 | } |
| 11760 | if (!isdigit ((unsigned char) *input_line_pointer)) |
| 11761 | { |
| 11762 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), |
| 11763 | *input_line_pointer, *input_line_pointer); |
| 11764 | as_warn (_("Invalid number")); |
| 11765 | return -1; |
| 11766 | } |
| 11767 | while (isdigit ((unsigned char) *input_line_pointer)) |
| 11768 | { |
| 11769 | val *= 10; |
| 11770 | val += *input_line_pointer++ - '0'; |
| 11771 | } |
| 11772 | return negative ? -val : val; |
| 11773 | } |
| 11774 | |
| 11775 | /* The .file directive; just like the usual .file directive, but there |
| 11776 | is an initial number which is the ECOFF file index. */ |
| 11777 | |
| 11778 | static void |
| 11779 | s_file (x) |
| 11780 | int x ATTRIBUTE_UNUSED; |
| 11781 | { |
| 11782 | int line; |
| 11783 | |
| 11784 | line = get_number (); |
| 11785 | s_app_file (0); |
| 11786 | } |
| 11787 | |
| 11788 | /* The .end directive. */ |
| 11789 | |
| 11790 | static void |
| 11791 | s_mips_end (x) |
| 11792 | int x ATTRIBUTE_UNUSED; |
| 11793 | { |
| 11794 | symbolS *p; |
| 11795 | int maybe_text; |
| 11796 | |
| 11797 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 11798 | { |
| 11799 | p = get_symbol (); |
| 11800 | demand_empty_rest_of_line (); |
| 11801 | } |
| 11802 | else |
| 11803 | p = NULL; |
| 11804 | |
| 11805 | #ifdef BFD_ASSEMBLER |
| 11806 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) |
| 11807 | maybe_text = 1; |
| 11808 | else |
| 11809 | maybe_text = 0; |
| 11810 | #else |
| 11811 | if (now_seg != data_section && now_seg != bss_section) |
| 11812 | maybe_text = 1; |
| 11813 | else |
| 11814 | maybe_text = 0; |
| 11815 | #endif |
| 11816 | |
| 11817 | if (!maybe_text) |
| 11818 | as_warn (_(".end not in text section")); |
| 11819 | |
| 11820 | if (!cur_proc_ptr) |
| 11821 | { |
| 11822 | as_warn (_(".end directive without a preceding .ent directive.")); |
| 11823 | demand_empty_rest_of_line (); |
| 11824 | return; |
| 11825 | } |
| 11826 | |
| 11827 | if (p != NULL) |
| 11828 | { |
| 11829 | assert (S_GET_NAME (p)); |
| 11830 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym))) |
| 11831 | as_warn (_(".end symbol does not match .ent symbol.")); |
| 11832 | } |
| 11833 | else |
| 11834 | as_warn (_(".end directive missing or unknown symbol")); |
| 11835 | |
| 11836 | #ifdef MIPS_STABS_ELF |
| 11837 | { |
| 11838 | segT saved_seg = now_seg; |
| 11839 | subsegT saved_subseg = now_subseg; |
| 11840 | valueT dot; |
| 11841 | expressionS exp; |
| 11842 | char *fragp; |
| 11843 | |
| 11844 | dot = frag_now_fix (); |
| 11845 | |
| 11846 | #ifdef md_flush_pending_output |
| 11847 | md_flush_pending_output (); |
| 11848 | #endif |
| 11849 | |
| 11850 | assert (pdr_seg); |
| 11851 | subseg_set (pdr_seg, 0); |
| 11852 | |
| 11853 | /* Write the symbol. */ |
| 11854 | exp.X_op = O_symbol; |
| 11855 | exp.X_add_symbol = p; |
| 11856 | exp.X_add_number = 0; |
| 11857 | emit_expr (&exp, 4); |
| 11858 | |
| 11859 | fragp = frag_more (7 * 4); |
| 11860 | |
| 11861 | md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4); |
| 11862 | md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); |
| 11863 | md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4); |
| 11864 | md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4); |
| 11865 | md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4); |
| 11866 | md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4); |
| 11867 | md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4); |
| 11868 | |
| 11869 | subseg_set (saved_seg, saved_subseg); |
| 11870 | } |
| 11871 | #endif |
| 11872 | |
| 11873 | cur_proc_ptr = NULL; |
| 11874 | } |
| 11875 | |
| 11876 | /* The .aent and .ent directives. */ |
| 11877 | |
| 11878 | static void |
| 11879 | s_mips_ent (aent) |
| 11880 | int aent; |
| 11881 | { |
| 11882 | int number = 0; |
| 11883 | symbolS *symbolP; |
| 11884 | int maybe_text; |
| 11885 | |
| 11886 | symbolP = get_symbol (); |
| 11887 | if (*input_line_pointer == ',') |
| 11888 | input_line_pointer++; |
| 11889 | SKIP_WHITESPACE (); |
| 11890 | if (isdigit ((unsigned char) *input_line_pointer) |
| 11891 | || *input_line_pointer == '-') |
| 11892 | number = get_number (); |
| 11893 | |
| 11894 | #ifdef BFD_ASSEMBLER |
| 11895 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0) |
| 11896 | maybe_text = 1; |
| 11897 | else |
| 11898 | maybe_text = 0; |
| 11899 | #else |
| 11900 | if (now_seg != data_section && now_seg != bss_section) |
| 11901 | maybe_text = 1; |
| 11902 | else |
| 11903 | maybe_text = 0; |
| 11904 | #endif |
| 11905 | |
| 11906 | if (!maybe_text) |
| 11907 | as_warn (_(".ent or .aent not in text section.")); |
| 11908 | |
| 11909 | if (!aent && cur_proc_ptr) |
| 11910 | as_warn (_("missing .end")); |
| 11911 | |
| 11912 | if (!aent) |
| 11913 | { |
| 11914 | cur_proc_ptr = &cur_proc; |
| 11915 | memset (cur_proc_ptr, '\0', sizeof (procS)); |
| 11916 | |
| 11917 | cur_proc_ptr->isym = symbolP; |
| 11918 | |
| 11919 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
| 11920 | |
| 11921 | numprocs++; |
| 11922 | } |
| 11923 | |
| 11924 | demand_empty_rest_of_line (); |
| 11925 | } |
| 11926 | |
| 11927 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) |
| 11928 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
| 11929 | s_mips_frame is used so that we can set the PDR information correctly. |
| 11930 | We can't use the ecoff routines because they make reference to the ecoff |
| 11931 | symbol table (in the mdebug section). */ |
| 11932 | |
| 11933 | static void |
| 11934 | s_mips_frame (ignore) |
| 11935 | int ignore ATTRIBUTE_UNUSED; |
| 11936 | { |
| 11937 | #ifdef MIPS_STABS_ELF |
| 11938 | |
| 11939 | long val; |
| 11940 | |
| 11941 | if (cur_proc_ptr == (procS *) NULL) |
| 11942 | { |
| 11943 | as_warn (_(".frame outside of .ent")); |
| 11944 | demand_empty_rest_of_line (); |
| 11945 | return; |
| 11946 | } |
| 11947 | |
| 11948 | cur_proc_ptr->frame_reg = tc_get_register (1); |
| 11949 | |
| 11950 | SKIP_WHITESPACE (); |
| 11951 | if (*input_line_pointer++ != ',' |
| 11952 | || get_absolute_expression_and_terminator (&val) != ',') |
| 11953 | { |
| 11954 | as_warn (_("Bad .frame directive")); |
| 11955 | --input_line_pointer; |
| 11956 | demand_empty_rest_of_line (); |
| 11957 | return; |
| 11958 | } |
| 11959 | |
| 11960 | cur_proc_ptr->frame_offset = val; |
| 11961 | cur_proc_ptr->pc_reg = tc_get_register (0); |
| 11962 | |
| 11963 | demand_empty_rest_of_line (); |
| 11964 | #else |
| 11965 | s_ignore (ignore); |
| 11966 | #endif /* MIPS_STABS_ELF */ |
| 11967 | } |
| 11968 | |
| 11969 | /* The .fmask and .mask directives. If the mdebug section is present |
| 11970 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For |
| 11971 | embedded targets, s_mips_mask is used so that we can set the PDR |
| 11972 | information correctly. We can't use the ecoff routines because they |
| 11973 | make reference to the ecoff symbol table (in the mdebug section). */ |
| 11974 | |
| 11975 | static void |
| 11976 | s_mips_mask (reg_type) |
| 11977 | char reg_type; |
| 11978 | { |
| 11979 | #ifdef MIPS_STABS_ELF |
| 11980 | long mask, off; |
| 11981 | |
| 11982 | if (cur_proc_ptr == (procS *) NULL) |
| 11983 | { |
| 11984 | as_warn (_(".mask/.fmask outside of .ent")); |
| 11985 | demand_empty_rest_of_line (); |
| 11986 | return; |
| 11987 | } |
| 11988 | |
| 11989 | if (get_absolute_expression_and_terminator (&mask) != ',') |
| 11990 | { |
| 11991 | as_warn (_("Bad .mask/.fmask directive")); |
| 11992 | --input_line_pointer; |
| 11993 | demand_empty_rest_of_line (); |
| 11994 | return; |
| 11995 | } |
| 11996 | |
| 11997 | off = get_absolute_expression (); |
| 11998 | |
| 11999 | if (reg_type == 'F') |
| 12000 | { |
| 12001 | cur_proc_ptr->fpreg_mask = mask; |
| 12002 | cur_proc_ptr->fpreg_offset = off; |
| 12003 | } |
| 12004 | else |
| 12005 | { |
| 12006 | cur_proc_ptr->reg_mask = mask; |
| 12007 | cur_proc_ptr->reg_offset = off; |
| 12008 | } |
| 12009 | |
| 12010 | demand_empty_rest_of_line (); |
| 12011 | #else |
| 12012 | s_ignore (reg_type); |
| 12013 | #endif /* MIPS_STABS_ELF */ |
| 12014 | } |
| 12015 | |
| 12016 | /* The .loc directive. */ |
| 12017 | |
| 12018 | #if 0 |
| 12019 | static void |
| 12020 | s_loc (x) |
| 12021 | int x; |
| 12022 | { |
| 12023 | symbolS *symbolP; |
| 12024 | int lineno; |
| 12025 | int addroff; |
| 12026 | |
| 12027 | assert (now_seg == text_section); |
| 12028 | |
| 12029 | lineno = get_number (); |
| 12030 | addroff = frag_now_fix (); |
| 12031 | |
| 12032 | symbolP = symbol_new ("", N_SLINE, addroff, frag_now); |
| 12033 | S_SET_TYPE (symbolP, N_SLINE); |
| 12034 | S_SET_OTHER (symbolP, 0); |
| 12035 | S_SET_DESC (symbolP, lineno); |
| 12036 | symbolP->sy_segment = now_seg; |
| 12037 | } |
| 12038 | #endif |
| 12039 | |
| 12040 | /* CPU name/ISA/number mapping table. |
| 12041 | |
| 12042 | Entries are grouped by type. The first matching CPU or ISA entry |
| 12043 | gets chosen by CPU or ISA, so it should be the 'canonical' name |
| 12044 | for that type. Entries after that within the type are sorted |
| 12045 | alphabetically. |
| 12046 | |
| 12047 | Case is ignored in comparison, so put the canonical entry in the |
| 12048 | appropriate case but everything else in lower case to ease eye pain. */ |
| 12049 | static const struct mips_cpu_info mips_cpu_info_table[] = |
| 12050 | { |
| 12051 | /* MIPS1 ISA */ |
| 12052 | { "MIPS1", 1, ISA_MIPS1, CPU_R3000, }, |
| 12053 | { "mips", 1, ISA_MIPS1, CPU_R3000, }, |
| 12054 | |
| 12055 | /* MIPS2 ISA */ |
| 12056 | { "MIPS2", 1, ISA_MIPS2, CPU_R6000, }, |
| 12057 | |
| 12058 | /* MIPS3 ISA */ |
| 12059 | { "MIPS3", 1, ISA_MIPS3, CPU_R4000, }, |
| 12060 | |
| 12061 | /* MIPS4 ISA */ |
| 12062 | { "MIPS4", 1, ISA_MIPS4, CPU_R8000, }, |
| 12063 | |
| 12064 | /* MIPS5 ISA */ |
| 12065 | { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, }, |
| 12066 | { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, }, |
| 12067 | |
| 12068 | /* MIPS32 ISA */ |
| 12069 | { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, }, |
| 12070 | { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, }, |
| 12071 | { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, }, |
| 12072 | { "4kc", 0, ISA_MIPS32, CPU_MIPS32, }, |
| 12073 | { "4km", 0, ISA_MIPS32, CPU_MIPS32, }, |
| 12074 | { "4kp", 0, ISA_MIPS32, CPU_MIPS32, }, |
| 12075 | |
| 12076 | /* For historical reasons. */ |
| 12077 | { "MIPS64", 1, ISA_MIPS3, CPU_R4000, }, |
| 12078 | |
| 12079 | /* MIPS64 ISA */ |
| 12080 | { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, }, |
| 12081 | { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, }, |
| 12082 | { "5kc", 0, ISA_MIPS64, CPU_MIPS64, }, |
| 12083 | { "20kc", 0, ISA_MIPS64, CPU_MIPS64, }, |
| 12084 | |
| 12085 | /* R2000 CPU */ |
| 12086 | { "R2000", 0, ISA_MIPS1, CPU_R2000, }, |
| 12087 | { "2000", 0, ISA_MIPS1, CPU_R2000, }, |
| 12088 | { "2k", 0, ISA_MIPS1, CPU_R2000, }, |
| 12089 | { "r2k", 0, ISA_MIPS1, CPU_R2000, }, |
| 12090 | |
| 12091 | /* R3000 CPU */ |
| 12092 | { "R3000", 0, ISA_MIPS1, CPU_R3000, }, |
| 12093 | { "3000", 0, ISA_MIPS1, CPU_R3000, }, |
| 12094 | { "3k", 0, ISA_MIPS1, CPU_R3000, }, |
| 12095 | { "r3k", 0, ISA_MIPS1, CPU_R3000, }, |
| 12096 | |
| 12097 | /* TX3900 CPU */ |
| 12098 | { "R3900", 0, ISA_MIPS1, CPU_R3900, }, |
| 12099 | { "3900", 0, ISA_MIPS1, CPU_R3900, }, |
| 12100 | { "mipstx39", 0, ISA_MIPS1, CPU_R3900, }, |
| 12101 | |
| 12102 | /* R4000 CPU */ |
| 12103 | { "R4000", 0, ISA_MIPS3, CPU_R4000, }, |
| 12104 | { "4000", 0, ISA_MIPS3, CPU_R4000, }, |
| 12105 | { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */ |
| 12106 | { "r4k", 0, ISA_MIPS3, CPU_R4000, }, |
| 12107 | |
| 12108 | /* R4010 CPU */ |
| 12109 | { "R4010", 0, ISA_MIPS2, CPU_R4010, }, |
| 12110 | { "4010", 0, ISA_MIPS2, CPU_R4010, }, |
| 12111 | |
| 12112 | /* R4400 CPU */ |
| 12113 | { "R4400", 0, ISA_MIPS3, CPU_R4400, }, |
| 12114 | { "4400", 0, ISA_MIPS3, CPU_R4400, }, |
| 12115 | |
| 12116 | /* R4600 CPU */ |
| 12117 | { "R4600", 0, ISA_MIPS3, CPU_R4600, }, |
| 12118 | { "4600", 0, ISA_MIPS3, CPU_R4600, }, |
| 12119 | { "mips64orion", 0, ISA_MIPS3, CPU_R4600, }, |
| 12120 | { "orion", 0, ISA_MIPS3, CPU_R4600, }, |
| 12121 | |
| 12122 | /* R4650 CPU */ |
| 12123 | { "R4650", 0, ISA_MIPS3, CPU_R4650, }, |
| 12124 | { "4650", 0, ISA_MIPS3, CPU_R4650, }, |
| 12125 | |
| 12126 | /* R6000 CPU */ |
| 12127 | { "R6000", 0, ISA_MIPS2, CPU_R6000, }, |
| 12128 | { "6000", 0, ISA_MIPS2, CPU_R6000, }, |
| 12129 | { "6k", 0, ISA_MIPS2, CPU_R6000, }, |
| 12130 | { "r6k", 0, ISA_MIPS2, CPU_R6000, }, |
| 12131 | |
| 12132 | /* R8000 CPU */ |
| 12133 | { "R8000", 0, ISA_MIPS4, CPU_R8000, }, |
| 12134 | { "8000", 0, ISA_MIPS4, CPU_R8000, }, |
| 12135 | { "8k", 0, ISA_MIPS4, CPU_R8000, }, |
| 12136 | { "r8k", 0, ISA_MIPS4, CPU_R8000, }, |
| 12137 | |
| 12138 | /* R10000 CPU */ |
| 12139 | { "R10000", 0, ISA_MIPS4, CPU_R10000, }, |
| 12140 | { "10000", 0, ISA_MIPS4, CPU_R10000, }, |
| 12141 | { "10k", 0, ISA_MIPS4, CPU_R10000, }, |
| 12142 | { "r10k", 0, ISA_MIPS4, CPU_R10000, }, |
| 12143 | |
| 12144 | /* R12000 CPU */ |
| 12145 | { "R12000", 0, ISA_MIPS4, CPU_R12000, }, |
| 12146 | { "12000", 0, ISA_MIPS4, CPU_R12000, }, |
| 12147 | { "12k", 0, ISA_MIPS4, CPU_R12000, }, |
| 12148 | { "r12k", 0, ISA_MIPS4, CPU_R12000, }, |
| 12149 | |
| 12150 | /* VR4100 CPU */ |
| 12151 | { "VR4100", 0, ISA_MIPS3, CPU_VR4100, }, |
| 12152 | { "4100", 0, ISA_MIPS3, CPU_VR4100, }, |
| 12153 | { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, }, |
| 12154 | { "r4100", 0, ISA_MIPS3, CPU_VR4100, }, |
| 12155 | |
| 12156 | /* VR4111 CPU */ |
| 12157 | { "VR4111", 0, ISA_MIPS3, CPU_R4111, }, |
| 12158 | { "4111", 0, ISA_MIPS3, CPU_R4111, }, |
| 12159 | { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, }, |
| 12160 | { "r4111", 0, ISA_MIPS3, CPU_R4111, }, |
| 12161 | |
| 12162 | /* VR4300 CPU */ |
| 12163 | { "VR4300", 0, ISA_MIPS3, CPU_R4300, }, |
| 12164 | { "4300", 0, ISA_MIPS3, CPU_R4300, }, |
| 12165 | { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, }, |
| 12166 | { "r4300", 0, ISA_MIPS3, CPU_R4300, }, |
| 12167 | |
| 12168 | /* VR5000 CPU */ |
| 12169 | { "VR5000", 0, ISA_MIPS4, CPU_R5000, }, |
| 12170 | { "5000", 0, ISA_MIPS4, CPU_R5000, }, |
| 12171 | { "5k", 0, ISA_MIPS4, CPU_R5000, }, |
| 12172 | { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, }, |
| 12173 | { "r5000", 0, ISA_MIPS4, CPU_R5000, }, |
| 12174 | { "r5200", 0, ISA_MIPS4, CPU_R5000, }, |
| 12175 | { "rm5200", 0, ISA_MIPS4, CPU_R5000, }, |
| 12176 | { "r5230", 0, ISA_MIPS4, CPU_R5000, }, |
| 12177 | { "rm5230", 0, ISA_MIPS4, CPU_R5000, }, |
| 12178 | { "r5231", 0, ISA_MIPS4, CPU_R5000, }, |
| 12179 | { "rm5231", 0, ISA_MIPS4, CPU_R5000, }, |
| 12180 | { "r5261", 0, ISA_MIPS4, CPU_R5000, }, |
| 12181 | { "rm5261", 0, ISA_MIPS4, CPU_R5000, }, |
| 12182 | { "r5721", 0, ISA_MIPS4, CPU_R5000, }, |
| 12183 | { "rm5721", 0, ISA_MIPS4, CPU_R5000, }, |
| 12184 | { "r5k", 0, ISA_MIPS4, CPU_R5000, }, |
| 12185 | { "r7000", 0, ISA_MIPS4, CPU_R5000, }, |
| 12186 | |
| 12187 | /* SiByte SB-1 CPU */ |
| 12188 | { "SB-1", 0, ISA_MIPS64, CPU_SB1, }, |
| 12189 | { "sb-1250", 0, ISA_MIPS64, CPU_SB1, }, |
| 12190 | { "sb1", 0, ISA_MIPS64, CPU_SB1, }, |
| 12191 | { "sb1250", 0, ISA_MIPS64, CPU_SB1, }, |
| 12192 | |
| 12193 | /* End marker. */ |
| 12194 | { NULL, 0, 0, 0, }, |
| 12195 | }; |
| 12196 | |
| 12197 | static const struct mips_cpu_info * |
| 12198 | mips_cpu_info_from_name (name) |
| 12199 | const char *name; |
| 12200 | { |
| 12201 | int i; |
| 12202 | |
| 12203 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) |
| 12204 | if (strcasecmp (name, mips_cpu_info_table[i].name) == 0) |
| 12205 | return (&mips_cpu_info_table[i]); |
| 12206 | |
| 12207 | return NULL; |
| 12208 | } |
| 12209 | |
| 12210 | static const struct mips_cpu_info * |
| 12211 | mips_cpu_info_from_isa (isa) |
| 12212 | int isa; |
| 12213 | { |
| 12214 | int i; |
| 12215 | |
| 12216 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) |
| 12217 | if (mips_cpu_info_table[i].is_isa |
| 12218 | && isa == mips_cpu_info_table[i].isa) |
| 12219 | return (&mips_cpu_info_table[i]); |
| 12220 | |
| 12221 | return NULL; |
| 12222 | } |
| 12223 | |
| 12224 | static const struct mips_cpu_info * |
| 12225 | mips_cpu_info_from_cpu (cpu) |
| 12226 | int cpu; |
| 12227 | { |
| 12228 | int i; |
| 12229 | |
| 12230 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) |
| 12231 | if (!mips_cpu_info_table[i].is_isa |
| 12232 | && cpu == mips_cpu_info_table[i].cpu) |
| 12233 | return (&mips_cpu_info_table[i]); |
| 12234 | |
| 12235 | return NULL; |
| 12236 | } |