| 1 | /* tc-mips.c -- assemble code for a MIPS chip. |
| 2 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
| 3 | Contributed by the OSF and Ralph Campbell. |
| 4 | Written by Keith Knowles and Ralph Campbell, working independently. |
| 5 | Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus |
| 6 | Support. |
| 7 | |
| 8 | This file is part of GAS. |
| 9 | |
| 10 | GAS is free software; you can redistribute it and/or modify |
| 11 | it under the terms of the GNU General Public License as published by |
| 12 | the Free Software Foundation; either version 3, or (at your option) |
| 13 | any later version. |
| 14 | |
| 15 | GAS is distributed in the hope that it will be useful, |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | GNU General Public License for more details. |
| 19 | |
| 20 | You should have received a copy of the GNU General Public License |
| 21 | along with GAS; see the file COPYING. If not, write to the Free |
| 22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. */ |
| 24 | |
| 25 | #include "as.h" |
| 26 | #include "config.h" |
| 27 | #include "subsegs.h" |
| 28 | #include "safe-ctype.h" |
| 29 | |
| 30 | #include "opcode/mips.h" |
| 31 | #include "itbl-ops.h" |
| 32 | #include "dwarf2dbg.h" |
| 33 | #include "dw2gencfi.h" |
| 34 | |
| 35 | /* Check assumptions made in this file. */ |
| 36 | typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; |
| 37 | typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; |
| 38 | |
| 39 | #ifdef DEBUG |
| 40 | #define DBG(x) printf x |
| 41 | #else |
| 42 | #define DBG(x) |
| 43 | #endif |
| 44 | |
| 45 | #define streq(a, b) (strcmp (a, b) == 0) |
| 46 | |
| 47 | #define SKIP_SPACE_TABS(S) \ |
| 48 | do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) |
| 49 | |
| 50 | /* Clean up namespace so we can include obj-elf.h too. */ |
| 51 | static int mips_output_flavor (void); |
| 52 | static int mips_output_flavor (void) { return OUTPUT_FLAVOR; } |
| 53 | #undef OBJ_PROCESS_STAB |
| 54 | #undef OUTPUT_FLAVOR |
| 55 | #undef S_GET_ALIGN |
| 56 | #undef S_GET_SIZE |
| 57 | #undef S_SET_ALIGN |
| 58 | #undef S_SET_SIZE |
| 59 | #undef obj_frob_file |
| 60 | #undef obj_frob_file_after_relocs |
| 61 | #undef obj_frob_symbol |
| 62 | #undef obj_pop_insert |
| 63 | #undef obj_sec_sym_ok_for_reloc |
| 64 | #undef OBJ_COPY_SYMBOL_ATTRIBUTES |
| 65 | |
| 66 | #include "obj-elf.h" |
| 67 | /* Fix any of them that we actually care about. */ |
| 68 | #undef OUTPUT_FLAVOR |
| 69 | #define OUTPUT_FLAVOR mips_output_flavor() |
| 70 | |
| 71 | #include "elf/mips.h" |
| 72 | |
| 73 | #ifndef ECOFF_DEBUGGING |
| 74 | #define NO_ECOFF_DEBUGGING |
| 75 | #define ECOFF_DEBUGGING 0 |
| 76 | #endif |
| 77 | |
| 78 | int mips_flag_mdebug = -1; |
| 79 | |
| 80 | /* Control generation of .pdr sections. Off by default on IRIX: the native |
| 81 | linker doesn't know about and discards them, but relocations against them |
| 82 | remain, leading to rld crashes. */ |
| 83 | #ifdef TE_IRIX |
| 84 | int mips_flag_pdr = FALSE; |
| 85 | #else |
| 86 | int mips_flag_pdr = TRUE; |
| 87 | #endif |
| 88 | |
| 89 | #include "ecoff.h" |
| 90 | |
| 91 | static char *mips_regmask_frag; |
| 92 | static char *mips_flags_frag; |
| 93 | |
| 94 | #define ZERO 0 |
| 95 | #define ATREG 1 |
| 96 | #define S0 16 |
| 97 | #define S7 23 |
| 98 | #define TREG 24 |
| 99 | #define PIC_CALL_REG 25 |
| 100 | #define KT0 26 |
| 101 | #define KT1 27 |
| 102 | #define GP 28 |
| 103 | #define SP 29 |
| 104 | #define FP 30 |
| 105 | #define RA 31 |
| 106 | |
| 107 | #define ILLEGAL_REG (32) |
| 108 | |
| 109 | #define AT mips_opts.at |
| 110 | |
| 111 | extern int target_big_endian; |
| 112 | |
| 113 | /* The name of the readonly data section. */ |
| 114 | #define RDATA_SECTION_NAME ".rodata" |
| 115 | |
| 116 | /* Ways in which an instruction can be "appended" to the output. */ |
| 117 | enum append_method { |
| 118 | /* Just add it normally. */ |
| 119 | APPEND_ADD, |
| 120 | |
| 121 | /* Add it normally and then add a nop. */ |
| 122 | APPEND_ADD_WITH_NOP, |
| 123 | |
| 124 | /* Turn an instruction with a delay slot into a "compact" version. */ |
| 125 | APPEND_ADD_COMPACT, |
| 126 | |
| 127 | /* Insert the instruction before the last one. */ |
| 128 | APPEND_SWAP |
| 129 | }; |
| 130 | |
| 131 | /* Information about an instruction, including its format, operands |
| 132 | and fixups. */ |
| 133 | struct mips_cl_insn |
| 134 | { |
| 135 | /* The opcode's entry in mips_opcodes or mips16_opcodes. */ |
| 136 | const struct mips_opcode *insn_mo; |
| 137 | |
| 138 | /* The 16-bit or 32-bit bitstring of the instruction itself. This is |
| 139 | a copy of INSN_MO->match with the operands filled in. If we have |
| 140 | decided to use an extended MIPS16 instruction, this includes the |
| 141 | extension. */ |
| 142 | unsigned long insn_opcode; |
| 143 | |
| 144 | /* The frag that contains the instruction. */ |
| 145 | struct frag *frag; |
| 146 | |
| 147 | /* The offset into FRAG of the first instruction byte. */ |
| 148 | long where; |
| 149 | |
| 150 | /* The relocs associated with the instruction, if any. */ |
| 151 | fixS *fixp[3]; |
| 152 | |
| 153 | /* True if this entry cannot be moved from its current position. */ |
| 154 | unsigned int fixed_p : 1; |
| 155 | |
| 156 | /* True if this instruction occurred in a .set noreorder block. */ |
| 157 | unsigned int noreorder_p : 1; |
| 158 | |
| 159 | /* True for mips16 instructions that jump to an absolute address. */ |
| 160 | unsigned int mips16_absolute_jump_p : 1; |
| 161 | |
| 162 | /* True if this instruction is complete. */ |
| 163 | unsigned int complete_p : 1; |
| 164 | |
| 165 | /* True if this instruction is cleared from history by unconditional |
| 166 | branch. */ |
| 167 | unsigned int cleared_p : 1; |
| 168 | }; |
| 169 | |
| 170 | /* The ABI to use. */ |
| 171 | enum mips_abi_level |
| 172 | { |
| 173 | NO_ABI = 0, |
| 174 | O32_ABI, |
| 175 | O64_ABI, |
| 176 | N32_ABI, |
| 177 | N64_ABI, |
| 178 | EABI_ABI |
| 179 | }; |
| 180 | |
| 181 | /* MIPS ABI we are using for this output file. */ |
| 182 | static enum mips_abi_level mips_abi = NO_ABI; |
| 183 | |
| 184 | /* Whether or not we have code that can call pic code. */ |
| 185 | int mips_abicalls = FALSE; |
| 186 | |
| 187 | /* Whether or not we have code which can be put into a shared |
| 188 | library. */ |
| 189 | static bfd_boolean mips_in_shared = TRUE; |
| 190 | |
| 191 | /* This is the set of options which may be modified by the .set |
| 192 | pseudo-op. We use a struct so that .set push and .set pop are more |
| 193 | reliable. */ |
| 194 | |
| 195 | struct mips_set_options |
| 196 | { |
| 197 | /* MIPS ISA (Instruction Set Architecture) level. This is set to -1 |
| 198 | if it has not been initialized. Changed by `.set mipsN', and the |
| 199 | -mipsN command line option, and the default CPU. */ |
| 200 | int isa; |
| 201 | /* Enabled Application Specific Extensions (ASEs). Changed by `.set |
| 202 | <asename>', by command line options, and based on the default |
| 203 | architecture. */ |
| 204 | int ase; |
| 205 | /* Whether we are assembling for the mips16 processor. 0 if we are |
| 206 | not, 1 if we are, and -1 if the value has not been initialized. |
| 207 | Changed by `.set mips16' and `.set nomips16', and the -mips16 and |
| 208 | -nomips16 command line options, and the default CPU. */ |
| 209 | int mips16; |
| 210 | /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not, |
| 211 | 1 if we are, and -1 if the value has not been initialized. Changed |
| 212 | by `.set micromips' and `.set nomicromips', and the -mmicromips |
| 213 | and -mno-micromips command line options, and the default CPU. */ |
| 214 | int micromips; |
| 215 | /* Non-zero if we should not reorder instructions. Changed by `.set |
| 216 | reorder' and `.set noreorder'. */ |
| 217 | int noreorder; |
| 218 | /* Non-zero if we should not permit the register designated "assembler |
| 219 | temporary" to be used in instructions. The value is the register |
| 220 | number, normally $at ($1). Changed by `.set at=REG', `.set noat' |
| 221 | (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */ |
| 222 | unsigned int at; |
| 223 | /* Non-zero if we should warn when a macro instruction expands into |
| 224 | more than one machine instruction. Changed by `.set nomacro' and |
| 225 | `.set macro'. */ |
| 226 | int warn_about_macros; |
| 227 | /* Non-zero if we should not move instructions. Changed by `.set |
| 228 | move', `.set volatile', `.set nomove', and `.set novolatile'. */ |
| 229 | int nomove; |
| 230 | /* Non-zero if we should not optimize branches by moving the target |
| 231 | of the branch into the delay slot. Actually, we don't perform |
| 232 | this optimization anyhow. Changed by `.set bopt' and `.set |
| 233 | nobopt'. */ |
| 234 | int nobopt; |
| 235 | /* Non-zero if we should not autoextend mips16 instructions. |
| 236 | Changed by `.set autoextend' and `.set noautoextend'. */ |
| 237 | int noautoextend; |
| 238 | /* True if we should only emit 32-bit microMIPS instructions. |
| 239 | Changed by `.set insn32' and `.set noinsn32', and the -minsn32 |
| 240 | and -mno-insn32 command line options. */ |
| 241 | bfd_boolean insn32; |
| 242 | /* Restrict general purpose registers and floating point registers |
| 243 | to 32 bit. This is initially determined when -mgp32 or -mfp32 |
| 244 | is passed but can changed if the assembler code uses .set mipsN. */ |
| 245 | int gp; |
| 246 | int fp; |
| 247 | /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march |
| 248 | command line option, and the default CPU. */ |
| 249 | int arch; |
| 250 | /* True if ".set sym32" is in effect. */ |
| 251 | bfd_boolean sym32; |
| 252 | /* True if floating-point operations are not allowed. Changed by .set |
| 253 | softfloat or .set hardfloat, by command line options -msoft-float or |
| 254 | -mhard-float. The default is false. */ |
| 255 | bfd_boolean soft_float; |
| 256 | |
| 257 | /* True if only single-precision floating-point operations are allowed. |
| 258 | Changed by .set singlefloat or .set doublefloat, command-line options |
| 259 | -msingle-float or -mdouble-float. The default is false. */ |
| 260 | bfd_boolean single_float; |
| 261 | |
| 262 | /* 1 if single-precision operations on odd-numbered registers are |
| 263 | allowed. */ |
| 264 | int oddspreg; |
| 265 | }; |
| 266 | |
| 267 | /* Specifies whether module level options have been checked yet. */ |
| 268 | static bfd_boolean file_mips_opts_checked = FALSE; |
| 269 | |
| 270 | /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the |
| 271 | value has not been initialized. Changed by `.nan legacy' and |
| 272 | `.nan 2008', and the -mnan=legacy and -mnan=2008 command line |
| 273 | options, and the default CPU. */ |
| 274 | static int mips_nan2008 = -1; |
| 275 | |
| 276 | /* This is the struct we use to hold the module level set of options. |
| 277 | Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and |
| 278 | fp fields to -1 to indicate that they have not been initialized. */ |
| 279 | |
| 280 | static struct mips_set_options file_mips_opts = |
| 281 | { |
| 282 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
| 283 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
| 284 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
| 285 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
| 286 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
| 287 | }; |
| 288 | |
| 289 | /* This is similar to file_mips_opts, but for the current set of options. */ |
| 290 | |
| 291 | static struct mips_set_options mips_opts = |
| 292 | { |
| 293 | /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, |
| 294 | /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, |
| 295 | /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, |
| 296 | /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, |
| 297 | /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 |
| 298 | }; |
| 299 | |
| 300 | /* Which bits of file_ase were explicitly set or cleared by ASE options. */ |
| 301 | static unsigned int file_ase_explicit; |
| 302 | |
| 303 | /* These variables are filled in with the masks of registers used. |
| 304 | The object format code reads them and puts them in the appropriate |
| 305 | place. */ |
| 306 | unsigned long mips_gprmask; |
| 307 | unsigned long mips_cprmask[4]; |
| 308 | |
| 309 | /* True if any MIPS16 code was produced. */ |
| 310 | static int file_ase_mips16; |
| 311 | |
| 312 | #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ |
| 313 | || mips_opts.isa == ISA_MIPS32R2 \ |
| 314 | || mips_opts.isa == ISA_MIPS32R3 \ |
| 315 | || mips_opts.isa == ISA_MIPS32R5 \ |
| 316 | || mips_opts.isa == ISA_MIPS64 \ |
| 317 | || mips_opts.isa == ISA_MIPS64R2 \ |
| 318 | || mips_opts.isa == ISA_MIPS64R3 \ |
| 319 | || mips_opts.isa == ISA_MIPS64R5) |
| 320 | |
| 321 | /* True if any microMIPS code was produced. */ |
| 322 | static int file_ase_micromips; |
| 323 | |
| 324 | /* True if we want to create R_MIPS_JALR for jalr $25. */ |
| 325 | #ifdef TE_IRIX |
| 326 | #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI |
| 327 | #else |
| 328 | /* As a GNU extension, we use R_MIPS_JALR for o32 too. However, |
| 329 | because there's no place for any addend, the only acceptable |
| 330 | expression is a bare symbol. */ |
| 331 | #define MIPS_JALR_HINT_P(EXPR) \ |
| 332 | (!HAVE_IN_PLACE_ADDENDS \ |
| 333 | || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0)) |
| 334 | #endif |
| 335 | |
| 336 | /* The argument of the -march= flag. The architecture we are assembling. */ |
| 337 | static const char *mips_arch_string; |
| 338 | |
| 339 | /* The argument of the -mtune= flag. The architecture for which we |
| 340 | are optimizing. */ |
| 341 | static int mips_tune = CPU_UNKNOWN; |
| 342 | static const char *mips_tune_string; |
| 343 | |
| 344 | /* True when generating 32-bit code for a 64-bit processor. */ |
| 345 | static int mips_32bitmode = 0; |
| 346 | |
| 347 | /* True if the given ABI requires 32-bit registers. */ |
| 348 | #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI) |
| 349 | |
| 350 | /* Likewise 64-bit registers. */ |
| 351 | #define ABI_NEEDS_64BIT_REGS(ABI) \ |
| 352 | ((ABI) == N32_ABI \ |
| 353 | || (ABI) == N64_ABI \ |
| 354 | || (ABI) == O64_ABI) |
| 355 | |
| 356 | #define ISA_IS_R6(ISA) \ |
| 357 | ((ISA) == ISA_MIPS32R6 \ |
| 358 | || (ISA) == ISA_MIPS64R6) |
| 359 | |
| 360 | /* Return true if ISA supports 64 bit wide gp registers. */ |
| 361 | #define ISA_HAS_64BIT_REGS(ISA) \ |
| 362 | ((ISA) == ISA_MIPS3 \ |
| 363 | || (ISA) == ISA_MIPS4 \ |
| 364 | || (ISA) == ISA_MIPS5 \ |
| 365 | || (ISA) == ISA_MIPS64 \ |
| 366 | || (ISA) == ISA_MIPS64R2 \ |
| 367 | || (ISA) == ISA_MIPS64R3 \ |
| 368 | || (ISA) == ISA_MIPS64R5 \ |
| 369 | || (ISA) == ISA_MIPS64R6) |
| 370 | |
| 371 | /* Return true if ISA supports 64 bit wide float registers. */ |
| 372 | #define ISA_HAS_64BIT_FPRS(ISA) \ |
| 373 | ((ISA) == ISA_MIPS3 \ |
| 374 | || (ISA) == ISA_MIPS4 \ |
| 375 | || (ISA) == ISA_MIPS5 \ |
| 376 | || (ISA) == ISA_MIPS32R2 \ |
| 377 | || (ISA) == ISA_MIPS32R3 \ |
| 378 | || (ISA) == ISA_MIPS32R5 \ |
| 379 | || (ISA) == ISA_MIPS32R6 \ |
| 380 | || (ISA) == ISA_MIPS64 \ |
| 381 | || (ISA) == ISA_MIPS64R2 \ |
| 382 | || (ISA) == ISA_MIPS64R3 \ |
| 383 | || (ISA) == ISA_MIPS64R5 \ |
| 384 | || (ISA) == ISA_MIPS64R6) |
| 385 | |
| 386 | /* Return true if ISA supports 64-bit right rotate (dror et al.) |
| 387 | instructions. */ |
| 388 | #define ISA_HAS_DROR(ISA) \ |
| 389 | ((ISA) == ISA_MIPS64R2 \ |
| 390 | || (ISA) == ISA_MIPS64R3 \ |
| 391 | || (ISA) == ISA_MIPS64R5 \ |
| 392 | || (ISA) == ISA_MIPS64R6 \ |
| 393 | || (mips_opts.micromips \ |
| 394 | && ISA_HAS_64BIT_REGS (ISA)) \ |
| 395 | ) |
| 396 | |
| 397 | /* Return true if ISA supports 32-bit right rotate (ror et al.) |
| 398 | instructions. */ |
| 399 | #define ISA_HAS_ROR(ISA) \ |
| 400 | ((ISA) == ISA_MIPS32R2 \ |
| 401 | || (ISA) == ISA_MIPS32R3 \ |
| 402 | || (ISA) == ISA_MIPS32R5 \ |
| 403 | || (ISA) == ISA_MIPS32R6 \ |
| 404 | || (ISA) == ISA_MIPS64R2 \ |
| 405 | || (ISA) == ISA_MIPS64R3 \ |
| 406 | || (ISA) == ISA_MIPS64R5 \ |
| 407 | || (ISA) == ISA_MIPS64R6 \ |
| 408 | || (mips_opts.ase & ASE_SMARTMIPS) \ |
| 409 | || mips_opts.micromips \ |
| 410 | ) |
| 411 | |
| 412 | /* Return true if ISA supports single-precision floats in odd registers. */ |
| 413 | #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ |
| 414 | (((ISA) == ISA_MIPS32 \ |
| 415 | || (ISA) == ISA_MIPS32R2 \ |
| 416 | || (ISA) == ISA_MIPS32R3 \ |
| 417 | || (ISA) == ISA_MIPS32R5 \ |
| 418 | || (ISA) == ISA_MIPS32R6 \ |
| 419 | || (ISA) == ISA_MIPS64 \ |
| 420 | || (ISA) == ISA_MIPS64R2 \ |
| 421 | || (ISA) == ISA_MIPS64R3 \ |
| 422 | || (ISA) == ISA_MIPS64R5 \ |
| 423 | || (ISA) == ISA_MIPS64R6 \ |
| 424 | || (CPU) == CPU_R5900) \ |
| 425 | && (CPU) != CPU_LOONGSON_3A) |
| 426 | |
| 427 | /* Return true if ISA supports move to/from high part of a 64-bit |
| 428 | floating-point register. */ |
| 429 | #define ISA_HAS_MXHC1(ISA) \ |
| 430 | ((ISA) == ISA_MIPS32R2 \ |
| 431 | || (ISA) == ISA_MIPS32R3 \ |
| 432 | || (ISA) == ISA_MIPS32R5 \ |
| 433 | || (ISA) == ISA_MIPS32R6 \ |
| 434 | || (ISA) == ISA_MIPS64R2 \ |
| 435 | || (ISA) == ISA_MIPS64R3 \ |
| 436 | || (ISA) == ISA_MIPS64R5 \ |
| 437 | || (ISA) == ISA_MIPS64R6) |
| 438 | |
| 439 | /* Return true if ISA supports legacy NAN. */ |
| 440 | #define ISA_HAS_LEGACY_NAN(ISA) \ |
| 441 | ((ISA) == ISA_MIPS1 \ |
| 442 | || (ISA) == ISA_MIPS2 \ |
| 443 | || (ISA) == ISA_MIPS3 \ |
| 444 | || (ISA) == ISA_MIPS4 \ |
| 445 | || (ISA) == ISA_MIPS5 \ |
| 446 | || (ISA) == ISA_MIPS32 \ |
| 447 | || (ISA) == ISA_MIPS32R2 \ |
| 448 | || (ISA) == ISA_MIPS32R3 \ |
| 449 | || (ISA) == ISA_MIPS32R5 \ |
| 450 | || (ISA) == ISA_MIPS64 \ |
| 451 | || (ISA) == ISA_MIPS64R2 \ |
| 452 | || (ISA) == ISA_MIPS64R3 \ |
| 453 | || (ISA) == ISA_MIPS64R5) |
| 454 | |
| 455 | #define GPR_SIZE \ |
| 456 | (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ |
| 457 | ? 32 \ |
| 458 | : mips_opts.gp) |
| 459 | |
| 460 | #define FPR_SIZE \ |
| 461 | (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ |
| 462 | ? 32 \ |
| 463 | : mips_opts.fp) |
| 464 | |
| 465 | #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) |
| 466 | |
| 467 | #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI) |
| 468 | |
| 469 | /* True if relocations are stored in-place. */ |
| 470 | #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI) |
| 471 | |
| 472 | /* The ABI-derived address size. */ |
| 473 | #define HAVE_64BIT_ADDRESSES \ |
| 474 | (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) |
| 475 | #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) |
| 476 | |
| 477 | /* The size of symbolic constants (i.e., expressions of the form |
| 478 | "SYMBOL" or "SYMBOL + OFFSET"). */ |
| 479 | #define HAVE_32BIT_SYMBOLS \ |
| 480 | (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32) |
| 481 | #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) |
| 482 | |
| 483 | /* Addresses are loaded in different ways, depending on the address size |
| 484 | in use. The n32 ABI Documentation also mandates the use of additions |
| 485 | with overflow checking, but existing implementations don't follow it. */ |
| 486 | #define ADDRESS_ADD_INSN \ |
| 487 | (HAVE_32BIT_ADDRESSES ? "addu" : "daddu") |
| 488 | |
| 489 | #define ADDRESS_ADDI_INSN \ |
| 490 | (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu") |
| 491 | |
| 492 | #define ADDRESS_LOAD_INSN \ |
| 493 | (HAVE_32BIT_ADDRESSES ? "lw" : "ld") |
| 494 | |
| 495 | #define ADDRESS_STORE_INSN \ |
| 496 | (HAVE_32BIT_ADDRESSES ? "sw" : "sd") |
| 497 | |
| 498 | /* Return true if the given CPU supports the MIPS16 ASE. */ |
| 499 | #define CPU_HAS_MIPS16(cpu) \ |
| 500 | (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \ |
| 501 | || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0) |
| 502 | |
| 503 | /* Return true if the given CPU supports the microMIPS ASE. */ |
| 504 | #define CPU_HAS_MICROMIPS(cpu) 0 |
| 505 | |
| 506 | /* True if CPU has a dror instruction. */ |
| 507 | #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) |
| 508 | |
| 509 | /* True if CPU has a ror instruction. */ |
| 510 | #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) |
| 511 | |
| 512 | /* True if CPU is in the Octeon family */ |
| 513 | #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ |
| 514 | || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3) |
| 515 | |
| 516 | /* True if CPU has seq/sne and seqi/snei instructions. */ |
| 517 | #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) |
| 518 | |
| 519 | /* True, if CPU has support for ldc1 and sdc1. */ |
| 520 | #define CPU_HAS_LDC1_SDC1(CPU) \ |
| 521 | ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) |
| 522 | |
| 523 | /* True if mflo and mfhi can be immediately followed by instructions |
| 524 | which write to the HI and LO registers. |
| 525 | |
| 526 | According to MIPS specifications, MIPS ISAs I, II, and III need |
| 527 | (at least) two instructions between the reads of HI/LO and |
| 528 | instructions which write them, and later ISAs do not. Contradicting |
| 529 | the MIPS specifications, some MIPS IV processor user manuals (e.g. |
| 530 | the UM for the NEC Vr5000) document needing the instructions between |
| 531 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, |
| 532 | MIPS64 and later ISAs to have the interlocks, plus any specific |
| 533 | earlier-ISA CPUs for which CPU documentation declares that the |
| 534 | instructions are really interlocked. */ |
| 535 | #define hilo_interlocks \ |
| 536 | (mips_opts.isa == ISA_MIPS32 \ |
| 537 | || mips_opts.isa == ISA_MIPS32R2 \ |
| 538 | || mips_opts.isa == ISA_MIPS32R3 \ |
| 539 | || mips_opts.isa == ISA_MIPS32R5 \ |
| 540 | || mips_opts.isa == ISA_MIPS32R6 \ |
| 541 | || mips_opts.isa == ISA_MIPS64 \ |
| 542 | || mips_opts.isa == ISA_MIPS64R2 \ |
| 543 | || mips_opts.isa == ISA_MIPS64R3 \ |
| 544 | || mips_opts.isa == ISA_MIPS64R5 \ |
| 545 | || mips_opts.isa == ISA_MIPS64R6 \ |
| 546 | || mips_opts.arch == CPU_R4010 \ |
| 547 | || mips_opts.arch == CPU_R5900 \ |
| 548 | || mips_opts.arch == CPU_R10000 \ |
| 549 | || mips_opts.arch == CPU_R12000 \ |
| 550 | || mips_opts.arch == CPU_R14000 \ |
| 551 | || mips_opts.arch == CPU_R16000 \ |
| 552 | || mips_opts.arch == CPU_RM7000 \ |
| 553 | || mips_opts.arch == CPU_VR5500 \ |
| 554 | || mips_opts.micromips \ |
| 555 | ) |
| 556 | |
| 557 | /* Whether the processor uses hardware interlocks to protect reads |
| 558 | from the GPRs after they are loaded from memory, and thus does not |
| 559 | require nops to be inserted. This applies to instructions marked |
| 560 | INSN_LOAD_MEMORY. These nops are only required at MIPS ISA |
| 561 | level I and microMIPS mode instructions are always interlocked. */ |
| 562 | #define gpr_interlocks \ |
| 563 | (mips_opts.isa != ISA_MIPS1 \ |
| 564 | || mips_opts.arch == CPU_R3900 \ |
| 565 | || mips_opts.arch == CPU_R5900 \ |
| 566 | || mips_opts.micromips \ |
| 567 | ) |
| 568 | |
| 569 | /* Whether the processor uses hardware interlocks to avoid delays |
| 570 | required by coprocessor instructions, and thus does not require |
| 571 | nops to be inserted. This applies to instructions marked |
| 572 | INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between |
| 573 | instructions marked INSN_WRITE_COND_CODE and ones marked |
| 574 | INSN_READ_COND_CODE. These nops are only required at MIPS ISA |
| 575 | levels I, II, and III and microMIPS mode instructions are always |
| 576 | interlocked. */ |
| 577 | /* Itbl support may require additional care here. */ |
| 578 | #define cop_interlocks \ |
| 579 | ((mips_opts.isa != ISA_MIPS1 \ |
| 580 | && mips_opts.isa != ISA_MIPS2 \ |
| 581 | && mips_opts.isa != ISA_MIPS3) \ |
| 582 | || mips_opts.arch == CPU_R4300 \ |
| 583 | || mips_opts.micromips \ |
| 584 | ) |
| 585 | |
| 586 | /* Whether the processor uses hardware interlocks to protect reads |
| 587 | from coprocessor registers after they are loaded from memory, and |
| 588 | thus does not require nops to be inserted. This applies to |
| 589 | instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only |
| 590 | requires at MIPS ISA level I and microMIPS mode instructions are |
| 591 | always interlocked. */ |
| 592 | #define cop_mem_interlocks \ |
| 593 | (mips_opts.isa != ISA_MIPS1 \ |
| 594 | || mips_opts.micromips \ |
| 595 | ) |
| 596 | |
| 597 | /* Is this a mfhi or mflo instruction? */ |
| 598 | #define MF_HILO_INSN(PINFO) \ |
| 599 | ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO)) |
| 600 | |
| 601 | /* Whether code compression (either of the MIPS16 or the microMIPS ASEs) |
| 602 | has been selected. This implies, in particular, that addresses of text |
| 603 | labels have their LSB set. */ |
| 604 | #define HAVE_CODE_COMPRESSION \ |
| 605 | ((mips_opts.mips16 | mips_opts.micromips) != 0) |
| 606 | |
| 607 | /* The minimum and maximum signed values that can be stored in a GPR. */ |
| 608 | #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) |
| 609 | #define GPR_SMIN (-GPR_SMAX - 1) |
| 610 | |
| 611 | /* MIPS PIC level. */ |
| 612 | |
| 613 | enum mips_pic_level mips_pic; |
| 614 | |
| 615 | /* 1 if we should generate 32 bit offsets from the $gp register in |
| 616 | SVR4_PIC mode. Currently has no meaning in other modes. */ |
| 617 | static int mips_big_got = 0; |
| 618 | |
| 619 | /* 1 if trap instructions should used for overflow rather than break |
| 620 | instructions. */ |
| 621 | static int mips_trap = 0; |
| 622 | |
| 623 | /* 1 if double width floating point constants should not be constructed |
| 624 | by assembling two single width halves into two single width floating |
| 625 | point registers which just happen to alias the double width destination |
| 626 | register. On some architectures this aliasing can be disabled by a bit |
| 627 | in the status register, and the setting of this bit cannot be determined |
| 628 | automatically at assemble time. */ |
| 629 | static int mips_disable_float_construction; |
| 630 | |
| 631 | /* Non-zero if any .set noreorder directives were used. */ |
| 632 | |
| 633 | static int mips_any_noreorder; |
| 634 | |
| 635 | /* Non-zero if nops should be inserted when the register referenced in |
| 636 | an mfhi/mflo instruction is read in the next two instructions. */ |
| 637 | static int mips_7000_hilo_fix; |
| 638 | |
| 639 | /* The size of objects in the small data section. */ |
| 640 | static unsigned int g_switch_value = 8; |
| 641 | /* Whether the -G option was used. */ |
| 642 | static int g_switch_seen = 0; |
| 643 | |
| 644 | #define N_RMASK 0xc4 |
| 645 | #define N_VFP 0xd4 |
| 646 | |
| 647 | /* If we can determine in advance that GP optimization won't be |
| 648 | possible, we can skip the relaxation stuff that tries to produce |
| 649 | GP-relative references. This makes delay slot optimization work |
| 650 | better. |
| 651 | |
| 652 | This function can only provide a guess, but it seems to work for |
| 653 | gcc output. It needs to guess right for gcc, otherwise gcc |
| 654 | will put what it thinks is a GP-relative instruction in a branch |
| 655 | delay slot. |
| 656 | |
| 657 | I don't know if a fix is needed for the SVR4_PIC mode. I've only |
| 658 | fixed it for the non-PIC mode. KR 95/04/07 */ |
| 659 | static int nopic_need_relax (symbolS *, int); |
| 660 | |
| 661 | /* handle of the OPCODE hash table */ |
| 662 | static struct hash_control *op_hash = NULL; |
| 663 | |
| 664 | /* The opcode hash table we use for the mips16. */ |
| 665 | static struct hash_control *mips16_op_hash = NULL; |
| 666 | |
| 667 | /* The opcode hash table we use for the microMIPS ASE. */ |
| 668 | static struct hash_control *micromips_op_hash = NULL; |
| 669 | |
| 670 | /* This array holds the chars that always start a comment. If the |
| 671 | pre-processor is disabled, these aren't very useful */ |
| 672 | const char comment_chars[] = "#"; |
| 673 | |
| 674 | /* This array holds the chars that only start a comment at the beginning of |
| 675 | a line. If the line seems to have the form '# 123 filename' |
| 676 | .line and .file directives will appear in the pre-processed output */ |
| 677 | /* Note that input_file.c hand checks for '#' at the beginning of the |
| 678 | first line of the input file. This is because the compiler outputs |
| 679 | #NO_APP at the beginning of its output. */ |
| 680 | /* Also note that C style comments are always supported. */ |
| 681 | const char line_comment_chars[] = "#"; |
| 682 | |
| 683 | /* This array holds machine specific line separator characters. */ |
| 684 | const char line_separator_chars[] = ";"; |
| 685 | |
| 686 | /* Chars that can be used to separate mant from exp in floating point nums */ |
| 687 | const char EXP_CHARS[] = "eE"; |
| 688 | |
| 689 | /* Chars that mean this number is a floating point constant */ |
| 690 | /* As in 0f12.456 */ |
| 691 | /* or 0d1.2345e12 */ |
| 692 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; |
| 693 | |
| 694 | /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be |
| 695 | changed in read.c . Ideally it shouldn't have to know about it at all, |
| 696 | but nothing is ideal around here. |
| 697 | */ |
| 698 | |
| 699 | /* Types of printf format used for instruction-related error messages. |
| 700 | "I" means int ("%d") and "S" means string ("%s"). */ |
| 701 | enum mips_insn_error_format { |
| 702 | ERR_FMT_PLAIN, |
| 703 | ERR_FMT_I, |
| 704 | ERR_FMT_SS, |
| 705 | }; |
| 706 | |
| 707 | /* Information about an error that was found while assembling the current |
| 708 | instruction. */ |
| 709 | struct mips_insn_error { |
| 710 | /* We sometimes need to match an instruction against more than one |
| 711 | opcode table entry. Errors found during this matching are reported |
| 712 | against a particular syntactic argument rather than against the |
| 713 | instruction as a whole. We grade these messages so that errors |
| 714 | against argument N have a greater priority than an error against |
| 715 | any argument < N, since the former implies that arguments up to N |
| 716 | were acceptable and that the opcode entry was therefore a closer match. |
| 717 | If several matches report an error against the same argument, |
| 718 | we only use that error if it is the same in all cases. |
| 719 | |
| 720 | min_argnum is the minimum argument number for which an error message |
| 721 | should be accepted. It is 0 if MSG is against the instruction as |
| 722 | a whole. */ |
| 723 | int min_argnum; |
| 724 | |
| 725 | /* The printf()-style message, including its format and arguments. */ |
| 726 | enum mips_insn_error_format format; |
| 727 | const char *msg; |
| 728 | union { |
| 729 | int i; |
| 730 | const char *ss[2]; |
| 731 | } u; |
| 732 | }; |
| 733 | |
| 734 | /* The error that should be reported for the current instruction. */ |
| 735 | static struct mips_insn_error insn_error; |
| 736 | |
| 737 | static int auto_align = 1; |
| 738 | |
| 739 | /* When outputting SVR4 PIC code, the assembler needs to know the |
| 740 | offset in the stack frame from which to restore the $gp register. |
| 741 | This is set by the .cprestore pseudo-op, and saved in this |
| 742 | variable. */ |
| 743 | static offsetT mips_cprestore_offset = -1; |
| 744 | |
| 745 | /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some |
| 746 | more optimizations, it can use a register value instead of a memory-saved |
| 747 | offset and even an other register than $gp as global pointer. */ |
| 748 | static offsetT mips_cpreturn_offset = -1; |
| 749 | static int mips_cpreturn_register = -1; |
| 750 | static int mips_gp_register = GP; |
| 751 | static int mips_gprel_offset = 0; |
| 752 | |
| 753 | /* Whether mips_cprestore_offset has been set in the current function |
| 754 | (or whether it has already been warned about, if not). */ |
| 755 | static int mips_cprestore_valid = 0; |
| 756 | |
| 757 | /* This is the register which holds the stack frame, as set by the |
| 758 | .frame pseudo-op. This is needed to implement .cprestore. */ |
| 759 | static int mips_frame_reg = SP; |
| 760 | |
| 761 | /* Whether mips_frame_reg has been set in the current function |
| 762 | (or whether it has already been warned about, if not). */ |
| 763 | static int mips_frame_reg_valid = 0; |
| 764 | |
| 765 | /* To output NOP instructions correctly, we need to keep information |
| 766 | about the previous two instructions. */ |
| 767 | |
| 768 | /* Whether we are optimizing. The default value of 2 means to remove |
| 769 | unneeded NOPs and swap branch instructions when possible. A value |
| 770 | of 1 means to not swap branches. A value of 0 means to always |
| 771 | insert NOPs. */ |
| 772 | static int mips_optimize = 2; |
| 773 | |
| 774 | /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is |
| 775 | equivalent to seeing no -g option at all. */ |
| 776 | static int mips_debug = 0; |
| 777 | |
| 778 | /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */ |
| 779 | #define MAX_VR4130_NOPS 4 |
| 780 | |
| 781 | /* The maximum number of NOPs needed to fill delay slots. */ |
| 782 | #define MAX_DELAY_NOPS 2 |
| 783 | |
| 784 | /* The maximum number of NOPs needed for any purpose. */ |
| 785 | #define MAX_NOPS 4 |
| 786 | |
| 787 | /* A list of previous instructions, with index 0 being the most recent. |
| 788 | We need to look back MAX_NOPS instructions when filling delay slots |
| 789 | or working around processor errata. We need to look back one |
| 790 | instruction further if we're thinking about using history[0] to |
| 791 | fill a branch delay slot. */ |
| 792 | static struct mips_cl_insn history[1 + MAX_NOPS]; |
| 793 | |
| 794 | /* Arrays of operands for each instruction. */ |
| 795 | #define MAX_OPERANDS 6 |
| 796 | struct mips_operand_array { |
| 797 | const struct mips_operand *operand[MAX_OPERANDS]; |
| 798 | }; |
| 799 | static struct mips_operand_array *mips_operands; |
| 800 | static struct mips_operand_array *mips16_operands; |
| 801 | static struct mips_operand_array *micromips_operands; |
| 802 | |
| 803 | /* Nop instructions used by emit_nop. */ |
| 804 | static struct mips_cl_insn nop_insn; |
| 805 | static struct mips_cl_insn mips16_nop_insn; |
| 806 | static struct mips_cl_insn micromips_nop16_insn; |
| 807 | static struct mips_cl_insn micromips_nop32_insn; |
| 808 | |
| 809 | /* The appropriate nop for the current mode. */ |
| 810 | #define NOP_INSN (mips_opts.mips16 \ |
| 811 | ? &mips16_nop_insn \ |
| 812 | : (mips_opts.micromips \ |
| 813 | ? (mips_opts.insn32 \ |
| 814 | ? µmips_nop32_insn \ |
| 815 | : µmips_nop16_insn) \ |
| 816 | : &nop_insn)) |
| 817 | |
| 818 | /* The size of NOP_INSN in bytes. */ |
| 819 | #define NOP_INSN_SIZE ((mips_opts.mips16 \ |
| 820 | || (mips_opts.micromips && !mips_opts.insn32)) \ |
| 821 | ? 2 : 4) |
| 822 | |
| 823 | /* If this is set, it points to a frag holding nop instructions which |
| 824 | were inserted before the start of a noreorder section. If those |
| 825 | nops turn out to be unnecessary, the size of the frag can be |
| 826 | decreased. */ |
| 827 | static fragS *prev_nop_frag; |
| 828 | |
| 829 | /* The number of nop instructions we created in prev_nop_frag. */ |
| 830 | static int prev_nop_frag_holds; |
| 831 | |
| 832 | /* The number of nop instructions that we know we need in |
| 833 | prev_nop_frag. */ |
| 834 | static int prev_nop_frag_required; |
| 835 | |
| 836 | /* The number of instructions we've seen since prev_nop_frag. */ |
| 837 | static int prev_nop_frag_since; |
| 838 | |
| 839 | /* Relocations against symbols are sometimes done in two parts, with a HI |
| 840 | relocation and a LO relocation. Each relocation has only 16 bits of |
| 841 | space to store an addend. This means that in order for the linker to |
| 842 | handle carries correctly, it must be able to locate both the HI and |
| 843 | the LO relocation. This means that the relocations must appear in |
| 844 | order in the relocation table. |
| 845 | |
| 846 | In order to implement this, we keep track of each unmatched HI |
| 847 | relocation. We then sort them so that they immediately precede the |
| 848 | corresponding LO relocation. */ |
| 849 | |
| 850 | struct mips_hi_fixup |
| 851 | { |
| 852 | /* Next HI fixup. */ |
| 853 | struct mips_hi_fixup *next; |
| 854 | /* This fixup. */ |
| 855 | fixS *fixp; |
| 856 | /* The section this fixup is in. */ |
| 857 | segT seg; |
| 858 | }; |
| 859 | |
| 860 | /* The list of unmatched HI relocs. */ |
| 861 | |
| 862 | static struct mips_hi_fixup *mips_hi_fixup_list; |
| 863 | |
| 864 | /* The frag containing the last explicit relocation operator. |
| 865 | Null if explicit relocations have not been used. */ |
| 866 | |
| 867 | static fragS *prev_reloc_op_frag; |
| 868 | |
| 869 | /* Map mips16 register numbers to normal MIPS register numbers. */ |
| 870 | |
| 871 | static const unsigned int mips16_to_32_reg_map[] = |
| 872 | { |
| 873 | 16, 17, 2, 3, 4, 5, 6, 7 |
| 874 | }; |
| 875 | |
| 876 | /* Map microMIPS register numbers to normal MIPS register numbers. */ |
| 877 | |
| 878 | #define micromips_to_32_reg_d_map mips16_to_32_reg_map |
| 879 | |
| 880 | /* The microMIPS registers with type h. */ |
| 881 | static const unsigned int micromips_to_32_reg_h_map1[] = |
| 882 | { |
| 883 | 5, 5, 6, 4, 4, 4, 4, 4 |
| 884 | }; |
| 885 | static const unsigned int micromips_to_32_reg_h_map2[] = |
| 886 | { |
| 887 | 6, 7, 7, 21, 22, 5, 6, 7 |
| 888 | }; |
| 889 | |
| 890 | /* The microMIPS registers with type m. */ |
| 891 | static const unsigned int micromips_to_32_reg_m_map[] = |
| 892 | { |
| 893 | 0, 17, 2, 3, 16, 18, 19, 20 |
| 894 | }; |
| 895 | |
| 896 | #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map |
| 897 | |
| 898 | /* Classifies the kind of instructions we're interested in when |
| 899 | implementing -mfix-vr4120. */ |
| 900 | enum fix_vr4120_class |
| 901 | { |
| 902 | FIX_VR4120_MACC, |
| 903 | FIX_VR4120_DMACC, |
| 904 | FIX_VR4120_MULT, |
| 905 | FIX_VR4120_DMULT, |
| 906 | FIX_VR4120_DIV, |
| 907 | FIX_VR4120_MTHILO, |
| 908 | NUM_FIX_VR4120_CLASSES |
| 909 | }; |
| 910 | |
| 911 | /* ...likewise -mfix-loongson2f-jump. */ |
| 912 | static bfd_boolean mips_fix_loongson2f_jump; |
| 913 | |
| 914 | /* ...likewise -mfix-loongson2f-nop. */ |
| 915 | static bfd_boolean mips_fix_loongson2f_nop; |
| 916 | |
| 917 | /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */ |
| 918 | static bfd_boolean mips_fix_loongson2f; |
| 919 | |
| 920 | /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if |
| 921 | there must be at least one other instruction between an instruction |
| 922 | of type X and an instruction of type Y. */ |
| 923 | static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES]; |
| 924 | |
| 925 | /* True if -mfix-vr4120 is in force. */ |
| 926 | static int mips_fix_vr4120; |
| 927 | |
| 928 | /* ...likewise -mfix-vr4130. */ |
| 929 | static int mips_fix_vr4130; |
| 930 | |
| 931 | /* ...likewise -mfix-24k. */ |
| 932 | static int mips_fix_24k; |
| 933 | |
| 934 | /* ...likewise -mfix-rm7000 */ |
| 935 | static int mips_fix_rm7000; |
| 936 | |
| 937 | /* ...likewise -mfix-cn63xxp1 */ |
| 938 | static bfd_boolean mips_fix_cn63xxp1; |
| 939 | |
| 940 | /* We don't relax branches by default, since this causes us to expand |
| 941 | `la .l2 - .l1' if there's a branch between .l1 and .l2, because we |
| 942 | fail to compute the offset before expanding the macro to the most |
| 943 | efficient expansion. */ |
| 944 | |
| 945 | static int mips_relax_branch; |
| 946 | |
| 947 | /* TRUE if checks are suppressed for invalid branches between ISA modes. |
| 948 | Needed for broken assembly produced by some GCC versions and some |
| 949 | sloppy code out there, where branches to data labels are present. */ |
| 950 | static bfd_boolean mips_ignore_branch_isa; |
| 951 | \f |
| 952 | /* The expansion of many macros depends on the type of symbol that |
| 953 | they refer to. For example, when generating position-dependent code, |
| 954 | a macro that refers to a symbol may have two different expansions, |
| 955 | one which uses GP-relative addresses and one which uses absolute |
| 956 | addresses. When generating SVR4-style PIC, a macro may have |
| 957 | different expansions for local and global symbols. |
| 958 | |
| 959 | We handle these situations by generating both sequences and putting |
| 960 | them in variant frags. In position-dependent code, the first sequence |
| 961 | will be the GP-relative one and the second sequence will be the |
| 962 | absolute one. In SVR4 PIC, the first sequence will be for global |
| 963 | symbols and the second will be for local symbols. |
| 964 | |
| 965 | The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and |
| 966 | SECOND are the lengths of the two sequences in bytes. These fields |
| 967 | can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, |
| 968 | the subtype has the following flags: |
| 969 | |
| 970 | RELAX_PIC |
| 971 | Set if generating PIC code. |
| 972 | |
| 973 | RELAX_USE_SECOND |
| 974 | Set if it has been decided that we should use the second |
| 975 | sequence instead of the first. |
| 976 | |
| 977 | RELAX_SECOND_LONGER |
| 978 | Set in the first variant frag if the macro's second implementation |
| 979 | is longer than its first. This refers to the macro as a whole, |
| 980 | not an individual relaxation. |
| 981 | |
| 982 | RELAX_NOMACRO |
| 983 | Set in the first variant frag if the macro appeared in a .set nomacro |
| 984 | block and if one alternative requires a warning but the other does not. |
| 985 | |
| 986 | RELAX_DELAY_SLOT |
| 987 | Like RELAX_NOMACRO, but indicates that the macro appears in a branch |
| 988 | delay slot. |
| 989 | |
| 990 | RELAX_DELAY_SLOT_16BIT |
| 991 | Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a |
| 992 | 16-bit instruction. |
| 993 | |
| 994 | RELAX_DELAY_SLOT_SIZE_FIRST |
| 995 | Like RELAX_DELAY_SLOT, but indicates that the first implementation of |
| 996 | the macro is of the wrong size for the branch delay slot. |
| 997 | |
| 998 | RELAX_DELAY_SLOT_SIZE_SECOND |
| 999 | Like RELAX_DELAY_SLOT, but indicates that the second implementation of |
| 1000 | the macro is of the wrong size for the branch delay slot. |
| 1001 | |
| 1002 | The frag's "opcode" points to the first fixup for relaxable code. |
| 1003 | |
| 1004 | Relaxable macros are generated using a sequence such as: |
| 1005 | |
| 1006 | relax_start (SYMBOL); |
| 1007 | ... generate first expansion ... |
| 1008 | relax_switch (); |
| 1009 | ... generate second expansion ... |
| 1010 | relax_end (); |
| 1011 | |
| 1012 | The code and fixups for the unwanted alternative are discarded |
| 1013 | by md_convert_frag. */ |
| 1014 | #define RELAX_ENCODE(FIRST, SECOND, PIC) \ |
| 1015 | (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0)) |
| 1016 | |
| 1017 | #define RELAX_FIRST(X) (((X) >> 8) & 0xff) |
| 1018 | #define RELAX_SECOND(X) ((X) & 0xff) |
| 1019 | #define RELAX_PIC(X) (((X) & 0x10000) != 0) |
| 1020 | #define RELAX_USE_SECOND 0x20000 |
| 1021 | #define RELAX_SECOND_LONGER 0x40000 |
| 1022 | #define RELAX_NOMACRO 0x80000 |
| 1023 | #define RELAX_DELAY_SLOT 0x100000 |
| 1024 | #define RELAX_DELAY_SLOT_16BIT 0x200000 |
| 1025 | #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000 |
| 1026 | #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000 |
| 1027 | |
| 1028 | /* Branch without likely bit. If label is out of range, we turn: |
| 1029 | |
| 1030 | beq reg1, reg2, label |
| 1031 | delay slot |
| 1032 | |
| 1033 | into |
| 1034 | |
| 1035 | bne reg1, reg2, 0f |
| 1036 | nop |
| 1037 | j label |
| 1038 | 0: delay slot |
| 1039 | |
| 1040 | with the following opcode replacements: |
| 1041 | |
| 1042 | beq <-> bne |
| 1043 | blez <-> bgtz |
| 1044 | bltz <-> bgez |
| 1045 | bc1f <-> bc1t |
| 1046 | |
| 1047 | bltzal <-> bgezal (with jal label instead of j label) |
| 1048 | |
| 1049 | Even though keeping the delay slot instruction in the delay slot of |
| 1050 | the branch would be more efficient, it would be very tricky to do |
| 1051 | correctly, because we'd have to introduce a variable frag *after* |
| 1052 | the delay slot instruction, and expand that instead. Let's do it |
| 1053 | the easy way for now, even if the branch-not-taken case now costs |
| 1054 | one additional instruction. Out-of-range branches are not supposed |
| 1055 | to be common, anyway. |
| 1056 | |
| 1057 | Branch likely. If label is out of range, we turn: |
| 1058 | |
| 1059 | beql reg1, reg2, label |
| 1060 | delay slot (annulled if branch not taken) |
| 1061 | |
| 1062 | into |
| 1063 | |
| 1064 | beql reg1, reg2, 1f |
| 1065 | nop |
| 1066 | beql $0, $0, 2f |
| 1067 | nop |
| 1068 | 1: j[al] label |
| 1069 | delay slot (executed only if branch taken) |
| 1070 | 2: |
| 1071 | |
| 1072 | It would be possible to generate a shorter sequence by losing the |
| 1073 | likely bit, generating something like: |
| 1074 | |
| 1075 | bne reg1, reg2, 0f |
| 1076 | nop |
| 1077 | j[al] label |
| 1078 | delay slot (executed only if branch taken) |
| 1079 | 0: |
| 1080 | |
| 1081 | beql -> bne |
| 1082 | bnel -> beq |
| 1083 | blezl -> bgtz |
| 1084 | bgtzl -> blez |
| 1085 | bltzl -> bgez |
| 1086 | bgezl -> bltz |
| 1087 | bc1fl -> bc1t |
| 1088 | bc1tl -> bc1f |
| 1089 | |
| 1090 | bltzall -> bgezal (with jal label instead of j label) |
| 1091 | bgezall -> bltzal (ditto) |
| 1092 | |
| 1093 | |
| 1094 | but it's not clear that it would actually improve performance. */ |
| 1095 | #define RELAX_BRANCH_ENCODE(at, pic, \ |
| 1096 | uncond, likely, link, toofar) \ |
| 1097 | ((relax_substateT) \ |
| 1098 | (0xc0000000 \ |
| 1099 | | ((at) & 0x1f) \ |
| 1100 | | ((pic) ? 0x20 : 0) \ |
| 1101 | | ((toofar) ? 0x40 : 0) \ |
| 1102 | | ((link) ? 0x80 : 0) \ |
| 1103 | | ((likely) ? 0x100 : 0) \ |
| 1104 | | ((uncond) ? 0x200 : 0))) |
| 1105 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) |
| 1106 | #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0) |
| 1107 | #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0) |
| 1108 | #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0) |
| 1109 | #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0) |
| 1110 | #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0) |
| 1111 | #define RELAX_BRANCH_AT(i) ((i) & 0x1f) |
| 1112 | |
| 1113 | /* For mips16 code, we use an entirely different form of relaxation. |
| 1114 | mips16 supports two versions of most instructions which take |
| 1115 | immediate values: a small one which takes some small value, and a |
| 1116 | larger one which takes a 16 bit value. Since branches also follow |
| 1117 | this pattern, relaxing these values is required. |
| 1118 | |
| 1119 | We can assemble both mips16 and normal MIPS code in a single |
| 1120 | object. Therefore, we need to support this type of relaxation at |
| 1121 | the same time that we support the relaxation described above. We |
| 1122 | use the high bit of the subtype field to distinguish these cases. |
| 1123 | |
| 1124 | The information we store for this type of relaxation is the |
| 1125 | argument code found in the opcode file for this relocation, whether |
| 1126 | the user explicitly requested a small or extended form, and whether |
| 1127 | the relocation is in a jump or jal delay slot. That tells us the |
| 1128 | size of the value, and how it should be stored. We also store |
| 1129 | whether the fragment is considered to be extended or not. We also |
| 1130 | store whether this is known to be a branch to a different section, |
| 1131 | whether we have tried to relax this frag yet, and whether we have |
| 1132 | ever extended a PC relative fragment because of a shift count. */ |
| 1133 | #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \ |
| 1134 | small, ext, \ |
| 1135 | dslot, jal_dslot) \ |
| 1136 | (0x80000000 \ |
| 1137 | | ((type) & 0xff) \ |
| 1138 | | ((e2) ? 0x100 : 0) \ |
| 1139 | | ((pic) ? 0x200 : 0) \ |
| 1140 | | ((sym32) ? 0x400 : 0) \ |
| 1141 | | ((nomacro) ? 0x800 : 0) \ |
| 1142 | | ((small) ? 0x1000 : 0) \ |
| 1143 | | ((ext) ? 0x2000 : 0) \ |
| 1144 | | ((dslot) ? 0x4000 : 0) \ |
| 1145 | | ((jal_dslot) ? 0x8000 : 0)) |
| 1146 | |
| 1147 | #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000) |
| 1148 | #define RELAX_MIPS16_TYPE(i) ((i) & 0xff) |
| 1149 | #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0) |
| 1150 | #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0) |
| 1151 | #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0) |
| 1152 | #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0) |
| 1153 | #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0) |
| 1154 | #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0) |
| 1155 | #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0) |
| 1156 | #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0) |
| 1157 | |
| 1158 | #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0) |
| 1159 | #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000) |
| 1160 | #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000) |
| 1161 | #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0) |
| 1162 | #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000) |
| 1163 | #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000) |
| 1164 | #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0) |
| 1165 | #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000) |
| 1166 | #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000) |
| 1167 | |
| 1168 | /* For microMIPS code, we use relaxation similar to one we use for |
| 1169 | MIPS16 code. Some instructions that take immediate values support |
| 1170 | two encodings: a small one which takes some small value, and a |
| 1171 | larger one which takes a 16 bit value. As some branches also follow |
| 1172 | this pattern, relaxing these values is required. |
| 1173 | |
| 1174 | We can assemble both microMIPS and normal MIPS code in a single |
| 1175 | object. Therefore, we need to support this type of relaxation at |
| 1176 | the same time that we support the relaxation described above. We |
| 1177 | use one of the high bits of the subtype field to distinguish these |
| 1178 | cases. |
| 1179 | |
| 1180 | The information we store for this type of relaxation is the argument |
| 1181 | code found in the opcode file for this relocation, the register |
| 1182 | selected as the assembler temporary, whether in the 32-bit |
| 1183 | instruction mode, whether the branch is unconditional, whether it is |
| 1184 | compact, whether there is no delay-slot instruction available to fill |
| 1185 | in, whether it stores the link address implicitly in $ra, whether |
| 1186 | relaxation of out-of-range 32-bit branches to a sequence of |
| 1187 | instructions is enabled, and whether the displacement of a branch is |
| 1188 | too large to fit as an immediate argument of a 16-bit and a 32-bit |
| 1189 | branch, respectively. */ |
| 1190 | #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \ |
| 1191 | uncond, compact, link, nods, \ |
| 1192 | relax32, toofar16, toofar32) \ |
| 1193 | (0x40000000 \ |
| 1194 | | ((type) & 0xff) \ |
| 1195 | | (((at) & 0x1f) << 8) \ |
| 1196 | | ((insn32) ? 0x2000 : 0) \ |
| 1197 | | ((pic) ? 0x4000 : 0) \ |
| 1198 | | ((uncond) ? 0x8000 : 0) \ |
| 1199 | | ((compact) ? 0x10000 : 0) \ |
| 1200 | | ((link) ? 0x20000 : 0) \ |
| 1201 | | ((nods) ? 0x40000 : 0) \ |
| 1202 | | ((relax32) ? 0x80000 : 0) \ |
| 1203 | | ((toofar16) ? 0x100000 : 0) \ |
| 1204 | | ((toofar32) ? 0x200000 : 0)) |
| 1205 | #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000) |
| 1206 | #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff) |
| 1207 | #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f) |
| 1208 | #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0) |
| 1209 | #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0) |
| 1210 | #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0) |
| 1211 | #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0) |
| 1212 | #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0) |
| 1213 | #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0) |
| 1214 | #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0) |
| 1215 | |
| 1216 | #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0) |
| 1217 | #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000) |
| 1218 | #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000) |
| 1219 | #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0) |
| 1220 | #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000) |
| 1221 | #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000) |
| 1222 | |
| 1223 | /* Sign-extend 16-bit value X. */ |
| 1224 | #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) |
| 1225 | |
| 1226 | /* Is the given value a sign-extended 32-bit value? */ |
| 1227 | #define IS_SEXT_32BIT_NUM(x) \ |
| 1228 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ |
| 1229 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) |
| 1230 | |
| 1231 | /* Is the given value a sign-extended 16-bit value? */ |
| 1232 | #define IS_SEXT_16BIT_NUM(x) \ |
| 1233 | (((x) &~ (offsetT) 0x7fff) == 0 \ |
| 1234 | || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff)) |
| 1235 | |
| 1236 | /* Is the given value a sign-extended 12-bit value? */ |
| 1237 | #define IS_SEXT_12BIT_NUM(x) \ |
| 1238 | (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) |
| 1239 | |
| 1240 | /* Is the given value a sign-extended 9-bit value? */ |
| 1241 | #define IS_SEXT_9BIT_NUM(x) \ |
| 1242 | (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) |
| 1243 | |
| 1244 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ |
| 1245 | #define IS_ZEXT_32BIT_NUM(x) \ |
| 1246 | (((x) &~ (offsetT) 0xffffffff) == 0 \ |
| 1247 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) |
| 1248 | |
| 1249 | /* Extract bits MASK << SHIFT from STRUCT and shift them right |
| 1250 | SHIFT places. */ |
| 1251 | #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ |
| 1252 | (((STRUCT) >> (SHIFT)) & (MASK)) |
| 1253 | |
| 1254 | /* Extract the operand given by FIELD from mips_cl_insn INSN. */ |
| 1255 | #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \ |
| 1256 | (!(MICROMIPS) \ |
| 1257 | ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \ |
| 1258 | : EXTRACT_BITS ((INSN).insn_opcode, \ |
| 1259 | MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD)) |
| 1260 | #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \ |
| 1261 | EXTRACT_BITS ((INSN).insn_opcode, \ |
| 1262 | MIPS16OP_MASK_##FIELD, \ |
| 1263 | MIPS16OP_SH_##FIELD) |
| 1264 | |
| 1265 | /* The MIPS16 EXTEND opcode, shifted left 16 places. */ |
| 1266 | #define MIPS16_EXTEND (0xf000U << 16) |
| 1267 | \f |
| 1268 | /* Whether or not we are emitting a branch-likely macro. */ |
| 1269 | static bfd_boolean emit_branch_likely_macro = FALSE; |
| 1270 | |
| 1271 | /* Global variables used when generating relaxable macros. See the |
| 1272 | comment above RELAX_ENCODE for more details about how relaxation |
| 1273 | is used. */ |
| 1274 | static struct { |
| 1275 | /* 0 if we're not emitting a relaxable macro. |
| 1276 | 1 if we're emitting the first of the two relaxation alternatives. |
| 1277 | 2 if we're emitting the second alternative. */ |
| 1278 | int sequence; |
| 1279 | |
| 1280 | /* The first relaxable fixup in the current frag. (In other words, |
| 1281 | the first fixup that refers to relaxable code.) */ |
| 1282 | fixS *first_fixup; |
| 1283 | |
| 1284 | /* sizes[0] says how many bytes of the first alternative are stored in |
| 1285 | the current frag. Likewise sizes[1] for the second alternative. */ |
| 1286 | unsigned int sizes[2]; |
| 1287 | |
| 1288 | /* The symbol on which the choice of sequence depends. */ |
| 1289 | symbolS *symbol; |
| 1290 | } mips_relax; |
| 1291 | \f |
| 1292 | /* Global variables used to decide whether a macro needs a warning. */ |
| 1293 | static struct { |
| 1294 | /* True if the macro is in a branch delay slot. */ |
| 1295 | bfd_boolean delay_slot_p; |
| 1296 | |
| 1297 | /* Set to the length in bytes required if the macro is in a delay slot |
| 1298 | that requires a specific length of instruction, otherwise zero. */ |
| 1299 | unsigned int delay_slot_length; |
| 1300 | |
| 1301 | /* For relaxable macros, sizes[0] is the length of the first alternative |
| 1302 | in bytes and sizes[1] is the length of the second alternative. |
| 1303 | For non-relaxable macros, both elements give the length of the |
| 1304 | macro in bytes. */ |
| 1305 | unsigned int sizes[2]; |
| 1306 | |
| 1307 | /* For relaxable macros, first_insn_sizes[0] is the length of the first |
| 1308 | instruction of the first alternative in bytes and first_insn_sizes[1] |
| 1309 | is the length of the first instruction of the second alternative. |
| 1310 | For non-relaxable macros, both elements give the length of the first |
| 1311 | instruction in bytes. |
| 1312 | |
| 1313 | Set to zero if we haven't yet seen the first instruction. */ |
| 1314 | unsigned int first_insn_sizes[2]; |
| 1315 | |
| 1316 | /* For relaxable macros, insns[0] is the number of instructions for the |
| 1317 | first alternative and insns[1] is the number of instructions for the |
| 1318 | second alternative. |
| 1319 | |
| 1320 | For non-relaxable macros, both elements give the number of |
| 1321 | instructions for the macro. */ |
| 1322 | unsigned int insns[2]; |
| 1323 | |
| 1324 | /* The first variant frag for this macro. */ |
| 1325 | fragS *first_frag; |
| 1326 | } mips_macro_warning; |
| 1327 | \f |
| 1328 | /* Prototypes for static functions. */ |
| 1329 | |
| 1330 | enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG }; |
| 1331 | |
| 1332 | static void append_insn |
| 1333 | (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, |
| 1334 | bfd_boolean expansionp); |
| 1335 | static void mips_no_prev_insn (void); |
| 1336 | static void macro_build (expressionS *, const char *, const char *, ...); |
| 1337 | static void mips16_macro_build |
| 1338 | (expressionS *, const char *, const char *, va_list *); |
| 1339 | static void load_register (int, expressionS *, int); |
| 1340 | static void macro_start (void); |
| 1341 | static void macro_end (void); |
| 1342 | static void macro (struct mips_cl_insn *ip, char *str); |
| 1343 | static void mips16_macro (struct mips_cl_insn * ip); |
| 1344 | static void mips_ip (char *str, struct mips_cl_insn * ip); |
| 1345 | static void mips16_ip (char *str, struct mips_cl_insn * ip); |
| 1346 | static unsigned long mips16_immed_extend (offsetT, unsigned int); |
| 1347 | static void mips16_immed |
| 1348 | (const char *, unsigned int, int, bfd_reloc_code_real_type, offsetT, |
| 1349 | unsigned int, unsigned long *); |
| 1350 | static size_t my_getSmallExpression |
| 1351 | (expressionS *, bfd_reloc_code_real_type *, char *); |
| 1352 | static void my_getExpression (expressionS *, char *); |
| 1353 | static void s_align (int); |
| 1354 | static void s_change_sec (int); |
| 1355 | static void s_change_section (int); |
| 1356 | static void s_cons (int); |
| 1357 | static void s_float_cons (int); |
| 1358 | static void s_mips_globl (int); |
| 1359 | static void s_option (int); |
| 1360 | static void s_mipsset (int); |
| 1361 | static void s_abicalls (int); |
| 1362 | static void s_cpload (int); |
| 1363 | static void s_cpsetup (int); |
| 1364 | static void s_cplocal (int); |
| 1365 | static void s_cprestore (int); |
| 1366 | static void s_cpreturn (int); |
| 1367 | static void s_dtprelword (int); |
| 1368 | static void s_dtpreldword (int); |
| 1369 | static void s_tprelword (int); |
| 1370 | static void s_tpreldword (int); |
| 1371 | static void s_gpvalue (int); |
| 1372 | static void s_gpword (int); |
| 1373 | static void s_gpdword (int); |
| 1374 | static void s_ehword (int); |
| 1375 | static void s_cpadd (int); |
| 1376 | static void s_insn (int); |
| 1377 | static void s_nan (int); |
| 1378 | static void s_module (int); |
| 1379 | static void s_mips_ent (int); |
| 1380 | static void s_mips_end (int); |
| 1381 | static void s_mips_frame (int); |
| 1382 | static void s_mips_mask (int reg_type); |
| 1383 | static void s_mips_stab (int); |
| 1384 | static void s_mips_weakext (int); |
| 1385 | static void s_mips_file (int); |
| 1386 | static void s_mips_loc (int); |
| 1387 | static bfd_boolean pic_need_relax (symbolS *); |
| 1388 | static int relaxed_branch_length (fragS *, asection *, int); |
| 1389 | static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); |
| 1390 | static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); |
| 1391 | static void file_mips_check_options (void); |
| 1392 | |
| 1393 | /* Table and functions used to map between CPU/ISA names, and |
| 1394 | ISA levels, and CPU numbers. */ |
| 1395 | |
| 1396 | struct mips_cpu_info |
| 1397 | { |
| 1398 | const char *name; /* CPU or ISA name. */ |
| 1399 | int flags; /* MIPS_CPU_* flags. */ |
| 1400 | int ase; /* Set of ASEs implemented by the CPU. */ |
| 1401 | int isa; /* ISA level. */ |
| 1402 | int cpu; /* CPU number (default CPU if ISA). */ |
| 1403 | }; |
| 1404 | |
| 1405 | #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ |
| 1406 | |
| 1407 | static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *); |
| 1408 | static const struct mips_cpu_info *mips_cpu_info_from_isa (int); |
| 1409 | static const struct mips_cpu_info *mips_cpu_info_from_arch (int); |
| 1410 | \f |
| 1411 | /* Command-line options. */ |
| 1412 | const char *md_shortopts = "O::g::G:"; |
| 1413 | |
| 1414 | enum options |
| 1415 | { |
| 1416 | OPTION_MARCH = OPTION_MD_BASE, |
| 1417 | OPTION_MTUNE, |
| 1418 | OPTION_MIPS1, |
| 1419 | OPTION_MIPS2, |
| 1420 | OPTION_MIPS3, |
| 1421 | OPTION_MIPS4, |
| 1422 | OPTION_MIPS5, |
| 1423 | OPTION_MIPS32, |
| 1424 | OPTION_MIPS64, |
| 1425 | OPTION_MIPS32R2, |
| 1426 | OPTION_MIPS32R3, |
| 1427 | OPTION_MIPS32R5, |
| 1428 | OPTION_MIPS32R6, |
| 1429 | OPTION_MIPS64R2, |
| 1430 | OPTION_MIPS64R3, |
| 1431 | OPTION_MIPS64R5, |
| 1432 | OPTION_MIPS64R6, |
| 1433 | OPTION_MIPS16, |
| 1434 | OPTION_NO_MIPS16, |
| 1435 | OPTION_MIPS3D, |
| 1436 | OPTION_NO_MIPS3D, |
| 1437 | OPTION_MDMX, |
| 1438 | OPTION_NO_MDMX, |
| 1439 | OPTION_DSP, |
| 1440 | OPTION_NO_DSP, |
| 1441 | OPTION_MT, |
| 1442 | OPTION_NO_MT, |
| 1443 | OPTION_VIRT, |
| 1444 | OPTION_NO_VIRT, |
| 1445 | OPTION_MSA, |
| 1446 | OPTION_NO_MSA, |
| 1447 | OPTION_SMARTMIPS, |
| 1448 | OPTION_NO_SMARTMIPS, |
| 1449 | OPTION_DSPR2, |
| 1450 | OPTION_NO_DSPR2, |
| 1451 | OPTION_DSPR3, |
| 1452 | OPTION_NO_DSPR3, |
| 1453 | OPTION_EVA, |
| 1454 | OPTION_NO_EVA, |
| 1455 | OPTION_XPA, |
| 1456 | OPTION_NO_XPA, |
| 1457 | OPTION_MICROMIPS, |
| 1458 | OPTION_NO_MICROMIPS, |
| 1459 | OPTION_MCU, |
| 1460 | OPTION_NO_MCU, |
| 1461 | OPTION_MIPS16E2, |
| 1462 | OPTION_NO_MIPS16E2, |
| 1463 | OPTION_COMPAT_ARCH_BASE, |
| 1464 | OPTION_M4650, |
| 1465 | OPTION_NO_M4650, |
| 1466 | OPTION_M4010, |
| 1467 | OPTION_NO_M4010, |
| 1468 | OPTION_M4100, |
| 1469 | OPTION_NO_M4100, |
| 1470 | OPTION_M3900, |
| 1471 | OPTION_NO_M3900, |
| 1472 | OPTION_M7000_HILO_FIX, |
| 1473 | OPTION_MNO_7000_HILO_FIX, |
| 1474 | OPTION_FIX_24K, |
| 1475 | OPTION_NO_FIX_24K, |
| 1476 | OPTION_FIX_RM7000, |
| 1477 | OPTION_NO_FIX_RM7000, |
| 1478 | OPTION_FIX_LOONGSON2F_JUMP, |
| 1479 | OPTION_NO_FIX_LOONGSON2F_JUMP, |
| 1480 | OPTION_FIX_LOONGSON2F_NOP, |
| 1481 | OPTION_NO_FIX_LOONGSON2F_NOP, |
| 1482 | OPTION_FIX_VR4120, |
| 1483 | OPTION_NO_FIX_VR4120, |
| 1484 | OPTION_FIX_VR4130, |
| 1485 | OPTION_NO_FIX_VR4130, |
| 1486 | OPTION_FIX_CN63XXP1, |
| 1487 | OPTION_NO_FIX_CN63XXP1, |
| 1488 | OPTION_TRAP, |
| 1489 | OPTION_BREAK, |
| 1490 | OPTION_EB, |
| 1491 | OPTION_EL, |
| 1492 | OPTION_FP32, |
| 1493 | OPTION_GP32, |
| 1494 | OPTION_CONSTRUCT_FLOATS, |
| 1495 | OPTION_NO_CONSTRUCT_FLOATS, |
| 1496 | OPTION_FP64, |
| 1497 | OPTION_FPXX, |
| 1498 | OPTION_GP64, |
| 1499 | OPTION_RELAX_BRANCH, |
| 1500 | OPTION_NO_RELAX_BRANCH, |
| 1501 | OPTION_IGNORE_BRANCH_ISA, |
| 1502 | OPTION_NO_IGNORE_BRANCH_ISA, |
| 1503 | OPTION_INSN32, |
| 1504 | OPTION_NO_INSN32, |
| 1505 | OPTION_MSHARED, |
| 1506 | OPTION_MNO_SHARED, |
| 1507 | OPTION_MSYM32, |
| 1508 | OPTION_MNO_SYM32, |
| 1509 | OPTION_SOFT_FLOAT, |
| 1510 | OPTION_HARD_FLOAT, |
| 1511 | OPTION_SINGLE_FLOAT, |
| 1512 | OPTION_DOUBLE_FLOAT, |
| 1513 | OPTION_32, |
| 1514 | OPTION_CALL_SHARED, |
| 1515 | OPTION_CALL_NONPIC, |
| 1516 | OPTION_NON_SHARED, |
| 1517 | OPTION_XGOT, |
| 1518 | OPTION_MABI, |
| 1519 | OPTION_N32, |
| 1520 | OPTION_64, |
| 1521 | OPTION_MDEBUG, |
| 1522 | OPTION_NO_MDEBUG, |
| 1523 | OPTION_PDR, |
| 1524 | OPTION_NO_PDR, |
| 1525 | OPTION_MVXWORKS_PIC, |
| 1526 | OPTION_NAN, |
| 1527 | OPTION_ODD_SPREG, |
| 1528 | OPTION_NO_ODD_SPREG, |
| 1529 | OPTION_END_OF_ENUM |
| 1530 | }; |
| 1531 | |
| 1532 | struct option md_longopts[] = |
| 1533 | { |
| 1534 | /* Options which specify architecture. */ |
| 1535 | {"march", required_argument, NULL, OPTION_MARCH}, |
| 1536 | {"mtune", required_argument, NULL, OPTION_MTUNE}, |
| 1537 | {"mips0", no_argument, NULL, OPTION_MIPS1}, |
| 1538 | {"mips1", no_argument, NULL, OPTION_MIPS1}, |
| 1539 | {"mips2", no_argument, NULL, OPTION_MIPS2}, |
| 1540 | {"mips3", no_argument, NULL, OPTION_MIPS3}, |
| 1541 | {"mips4", no_argument, NULL, OPTION_MIPS4}, |
| 1542 | {"mips5", no_argument, NULL, OPTION_MIPS5}, |
| 1543 | {"mips32", no_argument, NULL, OPTION_MIPS32}, |
| 1544 | {"mips64", no_argument, NULL, OPTION_MIPS64}, |
| 1545 | {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, |
| 1546 | {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, |
| 1547 | {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, |
| 1548 | {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, |
| 1549 | {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, |
| 1550 | {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, |
| 1551 | {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, |
| 1552 | {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, |
| 1553 | |
| 1554 | /* Options which specify Application Specific Extensions (ASEs). */ |
| 1555 | {"mips16", no_argument, NULL, OPTION_MIPS16}, |
| 1556 | {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16}, |
| 1557 | {"mips3d", no_argument, NULL, OPTION_MIPS3D}, |
| 1558 | {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D}, |
| 1559 | {"mdmx", no_argument, NULL, OPTION_MDMX}, |
| 1560 | {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX}, |
| 1561 | {"mdsp", no_argument, NULL, OPTION_DSP}, |
| 1562 | {"mno-dsp", no_argument, NULL, OPTION_NO_DSP}, |
| 1563 | {"mmt", no_argument, NULL, OPTION_MT}, |
| 1564 | {"mno-mt", no_argument, NULL, OPTION_NO_MT}, |
| 1565 | {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS}, |
| 1566 | {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS}, |
| 1567 | {"mdspr2", no_argument, NULL, OPTION_DSPR2}, |
| 1568 | {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2}, |
| 1569 | {"mdspr3", no_argument, NULL, OPTION_DSPR3}, |
| 1570 | {"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3}, |
| 1571 | {"meva", no_argument, NULL, OPTION_EVA}, |
| 1572 | {"mno-eva", no_argument, NULL, OPTION_NO_EVA}, |
| 1573 | {"mmicromips", no_argument, NULL, OPTION_MICROMIPS}, |
| 1574 | {"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS}, |
| 1575 | {"mmcu", no_argument, NULL, OPTION_MCU}, |
| 1576 | {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, |
| 1577 | {"mvirt", no_argument, NULL, OPTION_VIRT}, |
| 1578 | {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, |
| 1579 | {"mmsa", no_argument, NULL, OPTION_MSA}, |
| 1580 | {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, |
| 1581 | {"mxpa", no_argument, NULL, OPTION_XPA}, |
| 1582 | {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, |
| 1583 | {"mmips16e2", no_argument, NULL, OPTION_MIPS16E2}, |
| 1584 | {"mno-mips16e2", no_argument, NULL, OPTION_NO_MIPS16E2}, |
| 1585 | |
| 1586 | /* Old-style architecture options. Don't add more of these. */ |
| 1587 | {"m4650", no_argument, NULL, OPTION_M4650}, |
| 1588 | {"no-m4650", no_argument, NULL, OPTION_NO_M4650}, |
| 1589 | {"m4010", no_argument, NULL, OPTION_M4010}, |
| 1590 | {"no-m4010", no_argument, NULL, OPTION_NO_M4010}, |
| 1591 | {"m4100", no_argument, NULL, OPTION_M4100}, |
| 1592 | {"no-m4100", no_argument, NULL, OPTION_NO_M4100}, |
| 1593 | {"m3900", no_argument, NULL, OPTION_M3900}, |
| 1594 | {"no-m3900", no_argument, NULL, OPTION_NO_M3900}, |
| 1595 | |
| 1596 | /* Options which enable bug fixes. */ |
| 1597 | {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX}, |
| 1598 | {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
| 1599 | {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX}, |
| 1600 | {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP}, |
| 1601 | {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP}, |
| 1602 | {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP}, |
| 1603 | {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP}, |
| 1604 | {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120}, |
| 1605 | {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120}, |
| 1606 | {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130}, |
| 1607 | {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, |
| 1608 | {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, |
| 1609 | {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, |
| 1610 | {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, |
| 1611 | {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, |
| 1612 | {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, |
| 1613 | {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, |
| 1614 | |
| 1615 | /* Miscellaneous options. */ |
| 1616 | {"trap", no_argument, NULL, OPTION_TRAP}, |
| 1617 | {"no-break", no_argument, NULL, OPTION_TRAP}, |
| 1618 | {"break", no_argument, NULL, OPTION_BREAK}, |
| 1619 | {"no-trap", no_argument, NULL, OPTION_BREAK}, |
| 1620 | {"EB", no_argument, NULL, OPTION_EB}, |
| 1621 | {"EL", no_argument, NULL, OPTION_EL}, |
| 1622 | {"mfp32", no_argument, NULL, OPTION_FP32}, |
| 1623 | {"mgp32", no_argument, NULL, OPTION_GP32}, |
| 1624 | {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, |
| 1625 | {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, |
| 1626 | {"mfp64", no_argument, NULL, OPTION_FP64}, |
| 1627 | {"mfpxx", no_argument, NULL, OPTION_FPXX}, |
| 1628 | {"mgp64", no_argument, NULL, OPTION_GP64}, |
| 1629 | {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, |
| 1630 | {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, |
| 1631 | {"mignore-branch-isa", no_argument, NULL, OPTION_IGNORE_BRANCH_ISA}, |
| 1632 | {"mno-ignore-branch-isa", no_argument, NULL, OPTION_NO_IGNORE_BRANCH_ISA}, |
| 1633 | {"minsn32", no_argument, NULL, OPTION_INSN32}, |
| 1634 | {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, |
| 1635 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
| 1636 | {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED}, |
| 1637 | {"msym32", no_argument, NULL, OPTION_MSYM32}, |
| 1638 | {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32}, |
| 1639 | {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, |
| 1640 | {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, |
| 1641 | {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, |
| 1642 | {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, |
| 1643 | {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, |
| 1644 | {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, |
| 1645 | |
| 1646 | /* Strictly speaking this next option is ELF specific, |
| 1647 | but we allow it for other ports as well in order to |
| 1648 | make testing easier. */ |
| 1649 | {"32", no_argument, NULL, OPTION_32}, |
| 1650 | |
| 1651 | /* ELF-specific options. */ |
| 1652 | {"KPIC", no_argument, NULL, OPTION_CALL_SHARED}, |
| 1653 | {"call_shared", no_argument, NULL, OPTION_CALL_SHARED}, |
| 1654 | {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC}, |
| 1655 | {"non_shared", no_argument, NULL, OPTION_NON_SHARED}, |
| 1656 | {"xgot", no_argument, NULL, OPTION_XGOT}, |
| 1657 | {"mabi", required_argument, NULL, OPTION_MABI}, |
| 1658 | {"n32", no_argument, NULL, OPTION_N32}, |
| 1659 | {"64", no_argument, NULL, OPTION_64}, |
| 1660 | {"mdebug", no_argument, NULL, OPTION_MDEBUG}, |
| 1661 | {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG}, |
| 1662 | {"mpdr", no_argument, NULL, OPTION_PDR}, |
| 1663 | {"mno-pdr", no_argument, NULL, OPTION_NO_PDR}, |
| 1664 | {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC}, |
| 1665 | {"mnan", required_argument, NULL, OPTION_NAN}, |
| 1666 | |
| 1667 | {NULL, no_argument, NULL, 0} |
| 1668 | }; |
| 1669 | size_t md_longopts_size = sizeof (md_longopts); |
| 1670 | \f |
| 1671 | /* Information about either an Application Specific Extension or an |
| 1672 | optional architecture feature that, for simplicity, we treat in the |
| 1673 | same way as an ASE. */ |
| 1674 | struct mips_ase |
| 1675 | { |
| 1676 | /* The name of the ASE, used in both the command-line and .set options. */ |
| 1677 | const char *name; |
| 1678 | |
| 1679 | /* The associated ASE_* flags. If the ASE is available on both 32-bit |
| 1680 | and 64-bit architectures, the flags here refer to the subset that |
| 1681 | is available on both. */ |
| 1682 | unsigned int flags; |
| 1683 | |
| 1684 | /* The ASE_* flag used for instructions that are available on 64-bit |
| 1685 | architectures but that are not included in FLAGS. */ |
| 1686 | unsigned int flags64; |
| 1687 | |
| 1688 | /* The command-line options that turn the ASE on and off. */ |
| 1689 | int option_on; |
| 1690 | int option_off; |
| 1691 | |
| 1692 | /* The minimum required architecture revisions for MIPS32, MIPS64, |
| 1693 | microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */ |
| 1694 | int mips32_rev; |
| 1695 | int mips64_rev; |
| 1696 | int micromips32_rev; |
| 1697 | int micromips64_rev; |
| 1698 | |
| 1699 | /* The architecture where the ASE was removed or -1 if the extension has not |
| 1700 | been removed. */ |
| 1701 | int rem_rev; |
| 1702 | }; |
| 1703 | |
| 1704 | /* A table of all supported ASEs. */ |
| 1705 | static const struct mips_ase mips_ases[] = { |
| 1706 | { "dsp", ASE_DSP, ASE_DSP64, |
| 1707 | OPTION_DSP, OPTION_NO_DSP, |
| 1708 | 2, 2, 2, 2, |
| 1709 | -1 }, |
| 1710 | |
| 1711 | { "dspr2", ASE_DSP | ASE_DSPR2, 0, |
| 1712 | OPTION_DSPR2, OPTION_NO_DSPR2, |
| 1713 | 2, 2, 2, 2, |
| 1714 | -1 }, |
| 1715 | |
| 1716 | { "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0, |
| 1717 | OPTION_DSPR3, OPTION_NO_DSPR3, |
| 1718 | 6, 6, -1, -1, |
| 1719 | -1 }, |
| 1720 | |
| 1721 | { "eva", ASE_EVA, 0, |
| 1722 | OPTION_EVA, OPTION_NO_EVA, |
| 1723 | 2, 2, 2, 2, |
| 1724 | -1 }, |
| 1725 | |
| 1726 | { "mcu", ASE_MCU, 0, |
| 1727 | OPTION_MCU, OPTION_NO_MCU, |
| 1728 | 2, 2, 2, 2, |
| 1729 | -1 }, |
| 1730 | |
| 1731 | /* Deprecated in MIPS64r5, but we don't implement that yet. */ |
| 1732 | { "mdmx", ASE_MDMX, 0, |
| 1733 | OPTION_MDMX, OPTION_NO_MDMX, |
| 1734 | -1, 1, -1, -1, |
| 1735 | 6 }, |
| 1736 | |
| 1737 | /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ |
| 1738 | { "mips3d", ASE_MIPS3D, 0, |
| 1739 | OPTION_MIPS3D, OPTION_NO_MIPS3D, |
| 1740 | 2, 1, -1, -1, |
| 1741 | 6 }, |
| 1742 | |
| 1743 | { "mt", ASE_MT, 0, |
| 1744 | OPTION_MT, OPTION_NO_MT, |
| 1745 | 2, 2, -1, -1, |
| 1746 | -1 }, |
| 1747 | |
| 1748 | { "smartmips", ASE_SMARTMIPS, 0, |
| 1749 | OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, |
| 1750 | 1, -1, -1, -1, |
| 1751 | 6 }, |
| 1752 | |
| 1753 | { "virt", ASE_VIRT, ASE_VIRT64, |
| 1754 | OPTION_VIRT, OPTION_NO_VIRT, |
| 1755 | 2, 2, 2, 2, |
| 1756 | -1 }, |
| 1757 | |
| 1758 | { "msa", ASE_MSA, ASE_MSA64, |
| 1759 | OPTION_MSA, OPTION_NO_MSA, |
| 1760 | 2, 2, 2, 2, |
| 1761 | -1 }, |
| 1762 | |
| 1763 | { "xpa", ASE_XPA, 0, |
| 1764 | OPTION_XPA, OPTION_NO_XPA, |
| 1765 | 2, 2, -1, -1, |
| 1766 | -1 }, |
| 1767 | |
| 1768 | { "mips16e2", ASE_MIPS16E2, 0, |
| 1769 | OPTION_MIPS16E2, OPTION_NO_MIPS16E2, |
| 1770 | 2, 2, -1, -1, |
| 1771 | 6 }, |
| 1772 | }; |
| 1773 | |
| 1774 | /* The set of ASEs that require -mfp64. */ |
| 1775 | #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) |
| 1776 | |
| 1777 | /* Groups of ASE_* flags that represent different revisions of an ASE. */ |
| 1778 | static const unsigned int mips_ase_groups[] = { |
| 1779 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
| 1780 | }; |
| 1781 | \f |
| 1782 | /* Pseudo-op table. |
| 1783 | |
| 1784 | The following pseudo-ops from the Kane and Heinrich MIPS book |
| 1785 | should be defined here, but are currently unsupported: .alias, |
| 1786 | .galive, .gjaldef, .gjrlive, .livereg, .noalias. |
| 1787 | |
| 1788 | The following pseudo-ops from the Kane and Heinrich MIPS book are |
| 1789 | specific to the type of debugging information being generated, and |
| 1790 | should be defined by the object format: .aent, .begin, .bend, |
| 1791 | .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp, |
| 1792 | .vreg. |
| 1793 | |
| 1794 | The following pseudo-ops from the Kane and Heinrich MIPS book are |
| 1795 | not MIPS CPU specific, but are also not specific to the object file |
| 1796 | format. This file is probably the best place to define them, but |
| 1797 | they are not currently supported: .asm0, .endr, .lab, .struct. */ |
| 1798 | |
| 1799 | static const pseudo_typeS mips_pseudo_table[] = |
| 1800 | { |
| 1801 | /* MIPS specific pseudo-ops. */ |
| 1802 | {"option", s_option, 0}, |
| 1803 | {"set", s_mipsset, 0}, |
| 1804 | {"rdata", s_change_sec, 'r'}, |
| 1805 | {"sdata", s_change_sec, 's'}, |
| 1806 | {"livereg", s_ignore, 0}, |
| 1807 | {"abicalls", s_abicalls, 0}, |
| 1808 | {"cpload", s_cpload, 0}, |
| 1809 | {"cpsetup", s_cpsetup, 0}, |
| 1810 | {"cplocal", s_cplocal, 0}, |
| 1811 | {"cprestore", s_cprestore, 0}, |
| 1812 | {"cpreturn", s_cpreturn, 0}, |
| 1813 | {"dtprelword", s_dtprelword, 0}, |
| 1814 | {"dtpreldword", s_dtpreldword, 0}, |
| 1815 | {"tprelword", s_tprelword, 0}, |
| 1816 | {"tpreldword", s_tpreldword, 0}, |
| 1817 | {"gpvalue", s_gpvalue, 0}, |
| 1818 | {"gpword", s_gpword, 0}, |
| 1819 | {"gpdword", s_gpdword, 0}, |
| 1820 | {"ehword", s_ehword, 0}, |
| 1821 | {"cpadd", s_cpadd, 0}, |
| 1822 | {"insn", s_insn, 0}, |
| 1823 | {"nan", s_nan, 0}, |
| 1824 | {"module", s_module, 0}, |
| 1825 | |
| 1826 | /* Relatively generic pseudo-ops that happen to be used on MIPS |
| 1827 | chips. */ |
| 1828 | {"asciiz", stringer, 8 + 1}, |
| 1829 | {"bss", s_change_sec, 'b'}, |
| 1830 | {"err", s_err, 0}, |
| 1831 | {"half", s_cons, 1}, |
| 1832 | {"dword", s_cons, 3}, |
| 1833 | {"weakext", s_mips_weakext, 0}, |
| 1834 | {"origin", s_org, 0}, |
| 1835 | {"repeat", s_rept, 0}, |
| 1836 | |
| 1837 | /* For MIPS this is non-standard, but we define it for consistency. */ |
| 1838 | {"sbss", s_change_sec, 'B'}, |
| 1839 | |
| 1840 | /* These pseudo-ops are defined in read.c, but must be overridden |
| 1841 | here for one reason or another. */ |
| 1842 | {"align", s_align, 0}, |
| 1843 | {"byte", s_cons, 0}, |
| 1844 | {"data", s_change_sec, 'd'}, |
| 1845 | {"double", s_float_cons, 'd'}, |
| 1846 | {"float", s_float_cons, 'f'}, |
| 1847 | {"globl", s_mips_globl, 0}, |
| 1848 | {"global", s_mips_globl, 0}, |
| 1849 | {"hword", s_cons, 1}, |
| 1850 | {"int", s_cons, 2}, |
| 1851 | {"long", s_cons, 2}, |
| 1852 | {"octa", s_cons, 4}, |
| 1853 | {"quad", s_cons, 3}, |
| 1854 | {"section", s_change_section, 0}, |
| 1855 | {"short", s_cons, 1}, |
| 1856 | {"single", s_float_cons, 'f'}, |
| 1857 | {"stabd", s_mips_stab, 'd'}, |
| 1858 | {"stabn", s_mips_stab, 'n'}, |
| 1859 | {"stabs", s_mips_stab, 's'}, |
| 1860 | {"text", s_change_sec, 't'}, |
| 1861 | {"word", s_cons, 2}, |
| 1862 | |
| 1863 | { "extern", ecoff_directive_extern, 0}, |
| 1864 | |
| 1865 | { NULL, NULL, 0 }, |
| 1866 | }; |
| 1867 | |
| 1868 | static const pseudo_typeS mips_nonecoff_pseudo_table[] = |
| 1869 | { |
| 1870 | /* These pseudo-ops should be defined by the object file format. |
| 1871 | However, a.out doesn't support them, so we have versions here. */ |
| 1872 | {"aent", s_mips_ent, 1}, |
| 1873 | {"bgnb", s_ignore, 0}, |
| 1874 | {"end", s_mips_end, 0}, |
| 1875 | {"endb", s_ignore, 0}, |
| 1876 | {"ent", s_mips_ent, 0}, |
| 1877 | {"file", s_mips_file, 0}, |
| 1878 | {"fmask", s_mips_mask, 'F'}, |
| 1879 | {"frame", s_mips_frame, 0}, |
| 1880 | {"loc", s_mips_loc, 0}, |
| 1881 | {"mask", s_mips_mask, 'R'}, |
| 1882 | {"verstamp", s_ignore, 0}, |
| 1883 | { NULL, NULL, 0 }, |
| 1884 | }; |
| 1885 | |
| 1886 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
| 1887 | purpose of the `.dc.a' internal pseudo-op. */ |
| 1888 | |
| 1889 | int |
| 1890 | mips_address_bytes (void) |
| 1891 | { |
| 1892 | file_mips_check_options (); |
| 1893 | return HAVE_64BIT_ADDRESSES ? 8 : 4; |
| 1894 | } |
| 1895 | |
| 1896 | extern void pop_insert (const pseudo_typeS *); |
| 1897 | |
| 1898 | void |
| 1899 | mips_pop_insert (void) |
| 1900 | { |
| 1901 | pop_insert (mips_pseudo_table); |
| 1902 | if (! ECOFF_DEBUGGING) |
| 1903 | pop_insert (mips_nonecoff_pseudo_table); |
| 1904 | } |
| 1905 | \f |
| 1906 | /* Symbols labelling the current insn. */ |
| 1907 | |
| 1908 | struct insn_label_list |
| 1909 | { |
| 1910 | struct insn_label_list *next; |
| 1911 | symbolS *label; |
| 1912 | }; |
| 1913 | |
| 1914 | static struct insn_label_list *free_insn_labels; |
| 1915 | #define label_list tc_segment_info_data.labels |
| 1916 | |
| 1917 | static void mips_clear_insn_labels (void); |
| 1918 | static void mips_mark_labels (void); |
| 1919 | static void mips_compressed_mark_labels (void); |
| 1920 | |
| 1921 | static inline void |
| 1922 | mips_clear_insn_labels (void) |
| 1923 | { |
| 1924 | struct insn_label_list **pl; |
| 1925 | segment_info_type *si; |
| 1926 | |
| 1927 | if (now_seg) |
| 1928 | { |
| 1929 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) |
| 1930 | ; |
| 1931 | |
| 1932 | si = seg_info (now_seg); |
| 1933 | *pl = si->label_list; |
| 1934 | si->label_list = NULL; |
| 1935 | } |
| 1936 | } |
| 1937 | |
| 1938 | /* Mark instruction labels in MIPS16/microMIPS mode. */ |
| 1939 | |
| 1940 | static inline void |
| 1941 | mips_mark_labels (void) |
| 1942 | { |
| 1943 | if (HAVE_CODE_COMPRESSION) |
| 1944 | mips_compressed_mark_labels (); |
| 1945 | } |
| 1946 | \f |
| 1947 | static char *expr_end; |
| 1948 | |
| 1949 | /* An expression in a macro instruction. This is set by mips_ip and |
| 1950 | mips16_ip and when populated is always an O_constant. */ |
| 1951 | |
| 1952 | static expressionS imm_expr; |
| 1953 | |
| 1954 | /* The relocatable field in an instruction and the relocs associated |
| 1955 | with it. These variables are used for instructions like LUI and |
| 1956 | JAL as well as true offsets. They are also used for address |
| 1957 | operands in macros. */ |
| 1958 | |
| 1959 | static expressionS offset_expr; |
| 1960 | static bfd_reloc_code_real_type offset_reloc[3] |
| 1961 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; |
| 1962 | |
| 1963 | /* This is set to the resulting size of the instruction to be produced |
| 1964 | by mips16_ip if an explicit extension is used or by mips_ip if an |
| 1965 | explicit size is supplied. */ |
| 1966 | |
| 1967 | static unsigned int forced_insn_length; |
| 1968 | |
| 1969 | /* True if we are assembling an instruction. All dot symbols defined during |
| 1970 | this time should be treated as code labels. */ |
| 1971 | |
| 1972 | static bfd_boolean mips_assembling_insn; |
| 1973 | |
| 1974 | /* The pdr segment for per procedure frame/regmask info. Not used for |
| 1975 | ECOFF debugging. */ |
| 1976 | |
| 1977 | static segT pdr_seg; |
| 1978 | |
| 1979 | /* The default target format to use. */ |
| 1980 | |
| 1981 | #if defined (TE_FreeBSD) |
| 1982 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd" |
| 1983 | #elif defined (TE_TMIPS) |
| 1984 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips" |
| 1985 | #else |
| 1986 | #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips" |
| 1987 | #endif |
| 1988 | |
| 1989 | const char * |
| 1990 | mips_target_format (void) |
| 1991 | { |
| 1992 | switch (OUTPUT_FLAVOR) |
| 1993 | { |
| 1994 | case bfd_target_elf_flavour: |
| 1995 | #ifdef TE_VXWORKS |
| 1996 | if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI) |
| 1997 | return (target_big_endian |
| 1998 | ? "elf32-bigmips-vxworks" |
| 1999 | : "elf32-littlemips-vxworks"); |
| 2000 | #endif |
| 2001 | return (target_big_endian |
| 2002 | ? (HAVE_64BIT_OBJECTS |
| 2003 | ? ELF_TARGET ("elf64-", "big") |
| 2004 | : (HAVE_NEWABI |
| 2005 | ? ELF_TARGET ("elf32-n", "big") |
| 2006 | : ELF_TARGET ("elf32-", "big"))) |
| 2007 | : (HAVE_64BIT_OBJECTS |
| 2008 | ? ELF_TARGET ("elf64-", "little") |
| 2009 | : (HAVE_NEWABI |
| 2010 | ? ELF_TARGET ("elf32-n", "little") |
| 2011 | : ELF_TARGET ("elf32-", "little")))); |
| 2012 | default: |
| 2013 | abort (); |
| 2014 | return NULL; |
| 2015 | } |
| 2016 | } |
| 2017 | |
| 2018 | /* Return the ISA revision that is currently in use, or 0 if we are |
| 2019 | generating code for MIPS V or below. */ |
| 2020 | |
| 2021 | static int |
| 2022 | mips_isa_rev (void) |
| 2023 | { |
| 2024 | if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) |
| 2025 | return 2; |
| 2026 | |
| 2027 | if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) |
| 2028 | return 3; |
| 2029 | |
| 2030 | if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) |
| 2031 | return 5; |
| 2032 | |
| 2033 | if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) |
| 2034 | return 6; |
| 2035 | |
| 2036 | /* microMIPS implies revision 2 or above. */ |
| 2037 | if (mips_opts.micromips) |
| 2038 | return 2; |
| 2039 | |
| 2040 | if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64) |
| 2041 | return 1; |
| 2042 | |
| 2043 | return 0; |
| 2044 | } |
| 2045 | |
| 2046 | /* Return the mask of all ASEs that are revisions of those in FLAGS. */ |
| 2047 | |
| 2048 | static unsigned int |
| 2049 | mips_ase_mask (unsigned int flags) |
| 2050 | { |
| 2051 | unsigned int i; |
| 2052 | |
| 2053 | for (i = 0; i < ARRAY_SIZE (mips_ase_groups); i++) |
| 2054 | if (flags & mips_ase_groups[i]) |
| 2055 | flags |= mips_ase_groups[i]; |
| 2056 | return flags; |
| 2057 | } |
| 2058 | |
| 2059 | /* Check whether the current ISA supports ASE. Issue a warning if |
| 2060 | appropriate. */ |
| 2061 | |
| 2062 | static void |
| 2063 | mips_check_isa_supports_ase (const struct mips_ase *ase) |
| 2064 | { |
| 2065 | const char *base; |
| 2066 | int min_rev, size; |
| 2067 | static unsigned int warned_isa; |
| 2068 | static unsigned int warned_fp32; |
| 2069 | |
| 2070 | if (ISA_HAS_64BIT_REGS (mips_opts.isa)) |
| 2071 | min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; |
| 2072 | else |
| 2073 | min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; |
| 2074 | if ((min_rev < 0 || mips_isa_rev () < min_rev) |
| 2075 | && (warned_isa & ase->flags) != ase->flags) |
| 2076 | { |
| 2077 | warned_isa |= ase->flags; |
| 2078 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; |
| 2079 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; |
| 2080 | if (min_rev < 0) |
| 2081 | as_warn (_("the %d-bit %s architecture does not support the" |
| 2082 | " `%s' extension"), size, base, ase->name); |
| 2083 | else |
| 2084 | as_warn (_("the `%s' extension requires %s%d revision %d or greater"), |
| 2085 | ase->name, base, size, min_rev); |
| 2086 | } |
| 2087 | else if ((ase->rem_rev > 0 && mips_isa_rev () >= ase->rem_rev) |
| 2088 | && (warned_isa & ase->flags) != ase->flags) |
| 2089 | { |
| 2090 | warned_isa |= ase->flags; |
| 2091 | base = mips_opts.micromips ? "microMIPS" : "MIPS"; |
| 2092 | size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; |
| 2093 | as_warn (_("the `%s' extension was removed in %s%d revision %d"), |
| 2094 | ase->name, base, size, ase->rem_rev); |
| 2095 | } |
| 2096 | |
| 2097 | if ((ase->flags & FP64_ASES) |
| 2098 | && mips_opts.fp != 64 |
| 2099 | && (warned_fp32 & ase->flags) != ase->flags) |
| 2100 | { |
| 2101 | warned_fp32 |= ase->flags; |
| 2102 | as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name); |
| 2103 | } |
| 2104 | } |
| 2105 | |
| 2106 | /* Check all enabled ASEs to see whether they are supported by the |
| 2107 | chosen architecture. */ |
| 2108 | |
| 2109 | static void |
| 2110 | mips_check_isa_supports_ases (void) |
| 2111 | { |
| 2112 | unsigned int i, mask; |
| 2113 | |
| 2114 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
| 2115 | { |
| 2116 | mask = mips_ase_mask (mips_ases[i].flags); |
| 2117 | if ((mips_opts.ase & mask) == mips_ases[i].flags) |
| 2118 | mips_check_isa_supports_ase (&mips_ases[i]); |
| 2119 | } |
| 2120 | } |
| 2121 | |
| 2122 | /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags |
| 2123 | that were affected. */ |
| 2124 | |
| 2125 | static unsigned int |
| 2126 | mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, |
| 2127 | bfd_boolean enabled_p) |
| 2128 | { |
| 2129 | unsigned int mask; |
| 2130 | |
| 2131 | mask = mips_ase_mask (ase->flags); |
| 2132 | opts->ase &= ~mask; |
| 2133 | if (enabled_p) |
| 2134 | opts->ase |= ase->flags; |
| 2135 | |
| 2136 | if ((opts->ase & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) |
| 2137 | { |
| 2138 | opts->ase |= ASE_MIPS16E2_MT; |
| 2139 | mask |= ASE_MIPS16E2_MT; |
| 2140 | } |
| 2141 | |
| 2142 | return mask; |
| 2143 | } |
| 2144 | |
| 2145 | /* Return the ASE called NAME, or null if none. */ |
| 2146 | |
| 2147 | static const struct mips_ase * |
| 2148 | mips_lookup_ase (const char *name) |
| 2149 | { |
| 2150 | unsigned int i; |
| 2151 | |
| 2152 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
| 2153 | if (strcmp (name, mips_ases[i].name) == 0) |
| 2154 | return &mips_ases[i]; |
| 2155 | return NULL; |
| 2156 | } |
| 2157 | |
| 2158 | /* Return the length of a microMIPS instruction in bytes. If bits of |
| 2159 | the mask beyond the low 16 are 0, then it is a 16-bit instruction, |
| 2160 | otherwise it is a 32-bit instruction. */ |
| 2161 | |
| 2162 | static inline unsigned int |
| 2163 | micromips_insn_length (const struct mips_opcode *mo) |
| 2164 | { |
| 2165 | return mips_opcode_32bit_p (mo) ? 4 : 2; |
| 2166 | } |
| 2167 | |
| 2168 | /* Return the length of MIPS16 instruction OPCODE. */ |
| 2169 | |
| 2170 | static inline unsigned int |
| 2171 | mips16_opcode_length (unsigned long opcode) |
| 2172 | { |
| 2173 | return (opcode >> 16) == 0 ? 2 : 4; |
| 2174 | } |
| 2175 | |
| 2176 | /* Return the length of instruction INSN. */ |
| 2177 | |
| 2178 | static inline unsigned int |
| 2179 | insn_length (const struct mips_cl_insn *insn) |
| 2180 | { |
| 2181 | if (mips_opts.micromips) |
| 2182 | return micromips_insn_length (insn->insn_mo); |
| 2183 | else if (mips_opts.mips16) |
| 2184 | return mips16_opcode_length (insn->insn_opcode); |
| 2185 | else |
| 2186 | return 4; |
| 2187 | } |
| 2188 | |
| 2189 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ |
| 2190 | |
| 2191 | static void |
| 2192 | create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo) |
| 2193 | { |
| 2194 | size_t i; |
| 2195 | |
| 2196 | insn->insn_mo = mo; |
| 2197 | insn->insn_opcode = mo->match; |
| 2198 | insn->frag = NULL; |
| 2199 | insn->where = 0; |
| 2200 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) |
| 2201 | insn->fixp[i] = NULL; |
| 2202 | insn->fixed_p = (mips_opts.noreorder > 0); |
| 2203 | insn->noreorder_p = (mips_opts.noreorder > 0); |
| 2204 | insn->mips16_absolute_jump_p = 0; |
| 2205 | insn->complete_p = 0; |
| 2206 | insn->cleared_p = 0; |
| 2207 | } |
| 2208 | |
| 2209 | /* Get a list of all the operands in INSN. */ |
| 2210 | |
| 2211 | static const struct mips_operand_array * |
| 2212 | insn_operands (const struct mips_cl_insn *insn) |
| 2213 | { |
| 2214 | if (insn->insn_mo >= &mips_opcodes[0] |
| 2215 | && insn->insn_mo < &mips_opcodes[NUMOPCODES]) |
| 2216 | return &mips_operands[insn->insn_mo - &mips_opcodes[0]]; |
| 2217 | |
| 2218 | if (insn->insn_mo >= &mips16_opcodes[0] |
| 2219 | && insn->insn_mo < &mips16_opcodes[bfd_mips16_num_opcodes]) |
| 2220 | return &mips16_operands[insn->insn_mo - &mips16_opcodes[0]]; |
| 2221 | |
| 2222 | if (insn->insn_mo >= µmips_opcodes[0] |
| 2223 | && insn->insn_mo < µmips_opcodes[bfd_micromips_num_opcodes]) |
| 2224 | return µmips_operands[insn->insn_mo - µmips_opcodes[0]]; |
| 2225 | |
| 2226 | abort (); |
| 2227 | } |
| 2228 | |
| 2229 | /* Get a description of operand OPNO of INSN. */ |
| 2230 | |
| 2231 | static const struct mips_operand * |
| 2232 | insn_opno (const struct mips_cl_insn *insn, unsigned opno) |
| 2233 | { |
| 2234 | const struct mips_operand_array *operands; |
| 2235 | |
| 2236 | operands = insn_operands (insn); |
| 2237 | if (opno >= MAX_OPERANDS || !operands->operand[opno]) |
| 2238 | abort (); |
| 2239 | return operands->operand[opno]; |
| 2240 | } |
| 2241 | |
| 2242 | /* Install UVAL as the value of OPERAND in INSN. */ |
| 2243 | |
| 2244 | static inline void |
| 2245 | insn_insert_operand (struct mips_cl_insn *insn, |
| 2246 | const struct mips_operand *operand, unsigned int uval) |
| 2247 | { |
| 2248 | if (mips_opts.mips16 |
| 2249 | && operand->type == OP_INT && operand->lsb == 0 |
| 2250 | && mips_opcode_32bit_p (insn->insn_mo)) |
| 2251 | insn->insn_opcode |= mips16_immed_extend (uval, operand->size); |
| 2252 | else |
| 2253 | insn->insn_opcode = mips_insert_operand (operand, insn->insn_opcode, uval); |
| 2254 | } |
| 2255 | |
| 2256 | /* Extract the value of OPERAND from INSN. */ |
| 2257 | |
| 2258 | static inline unsigned |
| 2259 | insn_extract_operand (const struct mips_cl_insn *insn, |
| 2260 | const struct mips_operand *operand) |
| 2261 | { |
| 2262 | return mips_extract_operand (operand, insn->insn_opcode); |
| 2263 | } |
| 2264 | |
| 2265 | /* Record the current MIPS16/microMIPS mode in now_seg. */ |
| 2266 | |
| 2267 | static void |
| 2268 | mips_record_compressed_mode (void) |
| 2269 | { |
| 2270 | segment_info_type *si; |
| 2271 | |
| 2272 | si = seg_info (now_seg); |
| 2273 | if (si->tc_segment_info_data.mips16 != mips_opts.mips16) |
| 2274 | si->tc_segment_info_data.mips16 = mips_opts.mips16; |
| 2275 | if (si->tc_segment_info_data.micromips != mips_opts.micromips) |
| 2276 | si->tc_segment_info_data.micromips = mips_opts.micromips; |
| 2277 | } |
| 2278 | |
| 2279 | /* Read a standard MIPS instruction from BUF. */ |
| 2280 | |
| 2281 | static unsigned long |
| 2282 | read_insn (char *buf) |
| 2283 | { |
| 2284 | if (target_big_endian) |
| 2285 | return bfd_getb32 ((bfd_byte *) buf); |
| 2286 | else |
| 2287 | return bfd_getl32 ((bfd_byte *) buf); |
| 2288 | } |
| 2289 | |
| 2290 | /* Write standard MIPS instruction INSN to BUF. Return a pointer to |
| 2291 | the next byte. */ |
| 2292 | |
| 2293 | static char * |
| 2294 | write_insn (char *buf, unsigned int insn) |
| 2295 | { |
| 2296 | md_number_to_chars (buf, insn, 4); |
| 2297 | return buf + 4; |
| 2298 | } |
| 2299 | |
| 2300 | /* Read a microMIPS or MIPS16 opcode from BUF, given that it |
| 2301 | has length LENGTH. */ |
| 2302 | |
| 2303 | static unsigned long |
| 2304 | read_compressed_insn (char *buf, unsigned int length) |
| 2305 | { |
| 2306 | unsigned long insn; |
| 2307 | unsigned int i; |
| 2308 | |
| 2309 | insn = 0; |
| 2310 | for (i = 0; i < length; i += 2) |
| 2311 | { |
| 2312 | insn <<= 16; |
| 2313 | if (target_big_endian) |
| 2314 | insn |= bfd_getb16 ((char *) buf); |
| 2315 | else |
| 2316 | insn |= bfd_getl16 ((char *) buf); |
| 2317 | buf += 2; |
| 2318 | } |
| 2319 | return insn; |
| 2320 | } |
| 2321 | |
| 2322 | /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the |
| 2323 | instruction is LENGTH bytes long. Return a pointer to the next byte. */ |
| 2324 | |
| 2325 | static char * |
| 2326 | write_compressed_insn (char *buf, unsigned int insn, unsigned int length) |
| 2327 | { |
| 2328 | unsigned int i; |
| 2329 | |
| 2330 | for (i = 0; i < length; i += 2) |
| 2331 | md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); |
| 2332 | return buf + length; |
| 2333 | } |
| 2334 | |
| 2335 | /* Install INSN at the location specified by its "frag" and "where" fields. */ |
| 2336 | |
| 2337 | static void |
| 2338 | install_insn (const struct mips_cl_insn *insn) |
| 2339 | { |
| 2340 | char *f = insn->frag->fr_literal + insn->where; |
| 2341 | if (HAVE_CODE_COMPRESSION) |
| 2342 | write_compressed_insn (f, insn->insn_opcode, insn_length (insn)); |
| 2343 | else |
| 2344 | write_insn (f, insn->insn_opcode); |
| 2345 | mips_record_compressed_mode (); |
| 2346 | } |
| 2347 | |
| 2348 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly |
| 2349 | and install the opcode in the new location. */ |
| 2350 | |
| 2351 | static void |
| 2352 | move_insn (struct mips_cl_insn *insn, fragS *frag, long where) |
| 2353 | { |
| 2354 | size_t i; |
| 2355 | |
| 2356 | insn->frag = frag; |
| 2357 | insn->where = where; |
| 2358 | for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) |
| 2359 | if (insn->fixp[i] != NULL) |
| 2360 | { |
| 2361 | insn->fixp[i]->fx_frag = frag; |
| 2362 | insn->fixp[i]->fx_where = where; |
| 2363 | } |
| 2364 | install_insn (insn); |
| 2365 | } |
| 2366 | |
| 2367 | /* Add INSN to the end of the output. */ |
| 2368 | |
| 2369 | static void |
| 2370 | add_fixed_insn (struct mips_cl_insn *insn) |
| 2371 | { |
| 2372 | char *f = frag_more (insn_length (insn)); |
| 2373 | move_insn (insn, frag_now, f - frag_now->fr_literal); |
| 2374 | } |
| 2375 | |
| 2376 | /* Start a variant frag and move INSN to the start of the variant part, |
| 2377 | marking it as fixed. The other arguments are as for frag_var. */ |
| 2378 | |
| 2379 | static void |
| 2380 | add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var, |
| 2381 | relax_substateT subtype, symbolS *symbol, offsetT offset) |
| 2382 | { |
| 2383 | frag_grow (max_chars); |
| 2384 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); |
| 2385 | insn->fixed_p = 1; |
| 2386 | frag_var (rs_machine_dependent, max_chars, var, |
| 2387 | subtype, symbol, offset, NULL); |
| 2388 | } |
| 2389 | |
| 2390 | /* Insert N copies of INSN into the history buffer, starting at |
| 2391 | position FIRST. Neither FIRST nor N need to be clipped. */ |
| 2392 | |
| 2393 | static void |
| 2394 | insert_into_history (unsigned int first, unsigned int n, |
| 2395 | const struct mips_cl_insn *insn) |
| 2396 | { |
| 2397 | if (mips_relax.sequence != 2) |
| 2398 | { |
| 2399 | unsigned int i; |
| 2400 | |
| 2401 | for (i = ARRAY_SIZE (history); i-- > first;) |
| 2402 | if (i >= first + n) |
| 2403 | history[i] = history[i - n]; |
| 2404 | else |
| 2405 | history[i] = *insn; |
| 2406 | } |
| 2407 | } |
| 2408 | |
| 2409 | /* Clear the error in insn_error. */ |
| 2410 | |
| 2411 | static void |
| 2412 | clear_insn_error (void) |
| 2413 | { |
| 2414 | memset (&insn_error, 0, sizeof (insn_error)); |
| 2415 | } |
| 2416 | |
| 2417 | /* Possibly record error message MSG for the current instruction. |
| 2418 | If the error is about a particular argument, ARGNUM is the 1-based |
| 2419 | number of that argument, otherwise it is 0. FORMAT is the format |
| 2420 | of MSG. Return true if MSG was used, false if the current message |
| 2421 | was kept. */ |
| 2422 | |
| 2423 | static bfd_boolean |
| 2424 | set_insn_error_format (int argnum, enum mips_insn_error_format format, |
| 2425 | const char *msg) |
| 2426 | { |
| 2427 | if (argnum == 0) |
| 2428 | { |
| 2429 | /* Give priority to errors against specific arguments, and to |
| 2430 | the first whole-instruction message. */ |
| 2431 | if (insn_error.msg) |
| 2432 | return FALSE; |
| 2433 | } |
| 2434 | else |
| 2435 | { |
| 2436 | /* Keep insn_error if it is against a later argument. */ |
| 2437 | if (argnum < insn_error.min_argnum) |
| 2438 | return FALSE; |
| 2439 | |
| 2440 | /* If both errors are against the same argument but are different, |
| 2441 | give up on reporting a specific error for this argument. |
| 2442 | See the comment about mips_insn_error for details. */ |
| 2443 | if (argnum == insn_error.min_argnum |
| 2444 | && insn_error.msg |
| 2445 | && strcmp (insn_error.msg, msg) != 0) |
| 2446 | { |
| 2447 | insn_error.msg = 0; |
| 2448 | insn_error.min_argnum += 1; |
| 2449 | return FALSE; |
| 2450 | } |
| 2451 | } |
| 2452 | insn_error.min_argnum = argnum; |
| 2453 | insn_error.format = format; |
| 2454 | insn_error.msg = msg; |
| 2455 | return TRUE; |
| 2456 | } |
| 2457 | |
| 2458 | /* Record an instruction error with no % format fields. ARGNUM and MSG are |
| 2459 | as for set_insn_error_format. */ |
| 2460 | |
| 2461 | static void |
| 2462 | set_insn_error (int argnum, const char *msg) |
| 2463 | { |
| 2464 | set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); |
| 2465 | } |
| 2466 | |
| 2467 | /* Record an instruction error with one %d field I. ARGNUM and MSG are |
| 2468 | as for set_insn_error_format. */ |
| 2469 | |
| 2470 | static void |
| 2471 | set_insn_error_i (int argnum, const char *msg, int i) |
| 2472 | { |
| 2473 | if (set_insn_error_format (argnum, ERR_FMT_I, msg)) |
| 2474 | insn_error.u.i = i; |
| 2475 | } |
| 2476 | |
| 2477 | /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG |
| 2478 | are as for set_insn_error_format. */ |
| 2479 | |
| 2480 | static void |
| 2481 | set_insn_error_ss (int argnum, const char *msg, const char *s1, const char *s2) |
| 2482 | { |
| 2483 | if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) |
| 2484 | { |
| 2485 | insn_error.u.ss[0] = s1; |
| 2486 | insn_error.u.ss[1] = s2; |
| 2487 | } |
| 2488 | } |
| 2489 | |
| 2490 | /* Report the error in insn_error, which is against assembly code STR. */ |
| 2491 | |
| 2492 | static void |
| 2493 | report_insn_error (const char *str) |
| 2494 | { |
| 2495 | const char *msg = concat (insn_error.msg, " `%s'", NULL); |
| 2496 | |
| 2497 | switch (insn_error.format) |
| 2498 | { |
| 2499 | case ERR_FMT_PLAIN: |
| 2500 | as_bad (msg, str); |
| 2501 | break; |
| 2502 | |
| 2503 | case ERR_FMT_I: |
| 2504 | as_bad (msg, insn_error.u.i, str); |
| 2505 | break; |
| 2506 | |
| 2507 | case ERR_FMT_SS: |
| 2508 | as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); |
| 2509 | break; |
| 2510 | } |
| 2511 | |
| 2512 | free ((char *) msg); |
| 2513 | } |
| 2514 | |
| 2515 | /* Initialize vr4120_conflicts. There is a bit of duplication here: |
| 2516 | the idea is to make it obvious at a glance that each errata is |
| 2517 | included. */ |
| 2518 | |
| 2519 | static void |
| 2520 | init_vr4120_conflicts (void) |
| 2521 | { |
| 2522 | #define CONFLICT(FIRST, SECOND) \ |
| 2523 | vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND |
| 2524 | |
| 2525 | /* Errata 21 - [D]DIV[U] after [D]MACC */ |
| 2526 | CONFLICT (MACC, DIV); |
| 2527 | CONFLICT (DMACC, DIV); |
| 2528 | |
| 2529 | /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */ |
| 2530 | CONFLICT (DMULT, DMULT); |
| 2531 | CONFLICT (DMULT, DMACC); |
| 2532 | CONFLICT (DMACC, DMULT); |
| 2533 | CONFLICT (DMACC, DMACC); |
| 2534 | |
| 2535 | /* Errata 24 - MT{LO,HI} after [D]MACC */ |
| 2536 | CONFLICT (MACC, MTHILO); |
| 2537 | CONFLICT (DMACC, MTHILO); |
| 2538 | |
| 2539 | /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU |
| 2540 | instruction is executed immediately after a MACC or DMACC |
| 2541 | instruction, the result of [either instruction] is incorrect." */ |
| 2542 | CONFLICT (MACC, MULT); |
| 2543 | CONFLICT (MACC, DMULT); |
| 2544 | CONFLICT (DMACC, MULT); |
| 2545 | CONFLICT (DMACC, DMULT); |
| 2546 | |
| 2547 | /* VR4181A errata MD(4): "If a MACC or DMACC instruction is |
| 2548 | executed immediately after a DMULT, DMULTU, DIV, DIVU, |
| 2549 | DDIV or DDIVU instruction, the result of the MACC or |
| 2550 | DMACC instruction is incorrect.". */ |
| 2551 | CONFLICT (DMULT, MACC); |
| 2552 | CONFLICT (DMULT, DMACC); |
| 2553 | CONFLICT (DIV, MACC); |
| 2554 | CONFLICT (DIV, DMACC); |
| 2555 | |
| 2556 | #undef CONFLICT |
| 2557 | } |
| 2558 | |
| 2559 | struct regname { |
| 2560 | const char *name; |
| 2561 | unsigned int num; |
| 2562 | }; |
| 2563 | |
| 2564 | #define RNUM_MASK 0x00000ff |
| 2565 | #define RTYPE_MASK 0x0ffff00 |
| 2566 | #define RTYPE_NUM 0x0000100 |
| 2567 | #define RTYPE_FPU 0x0000200 |
| 2568 | #define RTYPE_FCC 0x0000400 |
| 2569 | #define RTYPE_VEC 0x0000800 |
| 2570 | #define RTYPE_GP 0x0001000 |
| 2571 | #define RTYPE_CP0 0x0002000 |
| 2572 | #define RTYPE_PC 0x0004000 |
| 2573 | #define RTYPE_ACC 0x0008000 |
| 2574 | #define RTYPE_CCC 0x0010000 |
| 2575 | #define RTYPE_VI 0x0020000 |
| 2576 | #define RTYPE_VF 0x0040000 |
| 2577 | #define RTYPE_R5900_I 0x0080000 |
| 2578 | #define RTYPE_R5900_Q 0x0100000 |
| 2579 | #define RTYPE_R5900_R 0x0200000 |
| 2580 | #define RTYPE_R5900_ACC 0x0400000 |
| 2581 | #define RTYPE_MSA 0x0800000 |
| 2582 | #define RWARN 0x8000000 |
| 2583 | |
| 2584 | #define GENERIC_REGISTER_NUMBERS \ |
| 2585 | {"$0", RTYPE_NUM | 0}, \ |
| 2586 | {"$1", RTYPE_NUM | 1}, \ |
| 2587 | {"$2", RTYPE_NUM | 2}, \ |
| 2588 | {"$3", RTYPE_NUM | 3}, \ |
| 2589 | {"$4", RTYPE_NUM | 4}, \ |
| 2590 | {"$5", RTYPE_NUM | 5}, \ |
| 2591 | {"$6", RTYPE_NUM | 6}, \ |
| 2592 | {"$7", RTYPE_NUM | 7}, \ |
| 2593 | {"$8", RTYPE_NUM | 8}, \ |
| 2594 | {"$9", RTYPE_NUM | 9}, \ |
| 2595 | {"$10", RTYPE_NUM | 10}, \ |
| 2596 | {"$11", RTYPE_NUM | 11}, \ |
| 2597 | {"$12", RTYPE_NUM | 12}, \ |
| 2598 | {"$13", RTYPE_NUM | 13}, \ |
| 2599 | {"$14", RTYPE_NUM | 14}, \ |
| 2600 | {"$15", RTYPE_NUM | 15}, \ |
| 2601 | {"$16", RTYPE_NUM | 16}, \ |
| 2602 | {"$17", RTYPE_NUM | 17}, \ |
| 2603 | {"$18", RTYPE_NUM | 18}, \ |
| 2604 | {"$19", RTYPE_NUM | 19}, \ |
| 2605 | {"$20", RTYPE_NUM | 20}, \ |
| 2606 | {"$21", RTYPE_NUM | 21}, \ |
| 2607 | {"$22", RTYPE_NUM | 22}, \ |
| 2608 | {"$23", RTYPE_NUM | 23}, \ |
| 2609 | {"$24", RTYPE_NUM | 24}, \ |
| 2610 | {"$25", RTYPE_NUM | 25}, \ |
| 2611 | {"$26", RTYPE_NUM | 26}, \ |
| 2612 | {"$27", RTYPE_NUM | 27}, \ |
| 2613 | {"$28", RTYPE_NUM | 28}, \ |
| 2614 | {"$29", RTYPE_NUM | 29}, \ |
| 2615 | {"$30", RTYPE_NUM | 30}, \ |
| 2616 | {"$31", RTYPE_NUM | 31} |
| 2617 | |
| 2618 | #define FPU_REGISTER_NAMES \ |
| 2619 | {"$f0", RTYPE_FPU | 0}, \ |
| 2620 | {"$f1", RTYPE_FPU | 1}, \ |
| 2621 | {"$f2", RTYPE_FPU | 2}, \ |
| 2622 | {"$f3", RTYPE_FPU | 3}, \ |
| 2623 | {"$f4", RTYPE_FPU | 4}, \ |
| 2624 | {"$f5", RTYPE_FPU | 5}, \ |
| 2625 | {"$f6", RTYPE_FPU | 6}, \ |
| 2626 | {"$f7", RTYPE_FPU | 7}, \ |
| 2627 | {"$f8", RTYPE_FPU | 8}, \ |
| 2628 | {"$f9", RTYPE_FPU | 9}, \ |
| 2629 | {"$f10", RTYPE_FPU | 10}, \ |
| 2630 | {"$f11", RTYPE_FPU | 11}, \ |
| 2631 | {"$f12", RTYPE_FPU | 12}, \ |
| 2632 | {"$f13", RTYPE_FPU | 13}, \ |
| 2633 | {"$f14", RTYPE_FPU | 14}, \ |
| 2634 | {"$f15", RTYPE_FPU | 15}, \ |
| 2635 | {"$f16", RTYPE_FPU | 16}, \ |
| 2636 | {"$f17", RTYPE_FPU | 17}, \ |
| 2637 | {"$f18", RTYPE_FPU | 18}, \ |
| 2638 | {"$f19", RTYPE_FPU | 19}, \ |
| 2639 | {"$f20", RTYPE_FPU | 20}, \ |
| 2640 | {"$f21", RTYPE_FPU | 21}, \ |
| 2641 | {"$f22", RTYPE_FPU | 22}, \ |
| 2642 | {"$f23", RTYPE_FPU | 23}, \ |
| 2643 | {"$f24", RTYPE_FPU | 24}, \ |
| 2644 | {"$f25", RTYPE_FPU | 25}, \ |
| 2645 | {"$f26", RTYPE_FPU | 26}, \ |
| 2646 | {"$f27", RTYPE_FPU | 27}, \ |
| 2647 | {"$f28", RTYPE_FPU | 28}, \ |
| 2648 | {"$f29", RTYPE_FPU | 29}, \ |
| 2649 | {"$f30", RTYPE_FPU | 30}, \ |
| 2650 | {"$f31", RTYPE_FPU | 31} |
| 2651 | |
| 2652 | #define FPU_CONDITION_CODE_NAMES \ |
| 2653 | {"$fcc0", RTYPE_FCC | 0}, \ |
| 2654 | {"$fcc1", RTYPE_FCC | 1}, \ |
| 2655 | {"$fcc2", RTYPE_FCC | 2}, \ |
| 2656 | {"$fcc3", RTYPE_FCC | 3}, \ |
| 2657 | {"$fcc4", RTYPE_FCC | 4}, \ |
| 2658 | {"$fcc5", RTYPE_FCC | 5}, \ |
| 2659 | {"$fcc6", RTYPE_FCC | 6}, \ |
| 2660 | {"$fcc7", RTYPE_FCC | 7} |
| 2661 | |
| 2662 | #define COPROC_CONDITION_CODE_NAMES \ |
| 2663 | {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ |
| 2664 | {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ |
| 2665 | {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ |
| 2666 | {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ |
| 2667 | {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ |
| 2668 | {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ |
| 2669 | {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ |
| 2670 | {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} |
| 2671 | |
| 2672 | #define N32N64_SYMBOLIC_REGISTER_NAMES \ |
| 2673 | {"$a4", RTYPE_GP | 8}, \ |
| 2674 | {"$a5", RTYPE_GP | 9}, \ |
| 2675 | {"$a6", RTYPE_GP | 10}, \ |
| 2676 | {"$a7", RTYPE_GP | 11}, \ |
| 2677 | {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \ |
| 2678 | {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \ |
| 2679 | {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \ |
| 2680 | {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \ |
| 2681 | {"$t0", RTYPE_GP | 12}, \ |
| 2682 | {"$t1", RTYPE_GP | 13}, \ |
| 2683 | {"$t2", RTYPE_GP | 14}, \ |
| 2684 | {"$t3", RTYPE_GP | 15} |
| 2685 | |
| 2686 | #define O32_SYMBOLIC_REGISTER_NAMES \ |
| 2687 | {"$t0", RTYPE_GP | 8}, \ |
| 2688 | {"$t1", RTYPE_GP | 9}, \ |
| 2689 | {"$t2", RTYPE_GP | 10}, \ |
| 2690 | {"$t3", RTYPE_GP | 11}, \ |
| 2691 | {"$t4", RTYPE_GP | 12}, \ |
| 2692 | {"$t5", RTYPE_GP | 13}, \ |
| 2693 | {"$t6", RTYPE_GP | 14}, \ |
| 2694 | {"$t7", RTYPE_GP | 15}, \ |
| 2695 | {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \ |
| 2696 | {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \ |
| 2697 | {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \ |
| 2698 | {"$ta3", RTYPE_GP | 15} /* alias for $t7 */ |
| 2699 | |
| 2700 | /* Remaining symbolic register names */ |
| 2701 | #define SYMBOLIC_REGISTER_NAMES \ |
| 2702 | {"$zero", RTYPE_GP | 0}, \ |
| 2703 | {"$at", RTYPE_GP | 1}, \ |
| 2704 | {"$AT", RTYPE_GP | 1}, \ |
| 2705 | {"$v0", RTYPE_GP | 2}, \ |
| 2706 | {"$v1", RTYPE_GP | 3}, \ |
| 2707 | {"$a0", RTYPE_GP | 4}, \ |
| 2708 | {"$a1", RTYPE_GP | 5}, \ |
| 2709 | {"$a2", RTYPE_GP | 6}, \ |
| 2710 | {"$a3", RTYPE_GP | 7}, \ |
| 2711 | {"$s0", RTYPE_GP | 16}, \ |
| 2712 | {"$s1", RTYPE_GP | 17}, \ |
| 2713 | {"$s2", RTYPE_GP | 18}, \ |
| 2714 | {"$s3", RTYPE_GP | 19}, \ |
| 2715 | {"$s4", RTYPE_GP | 20}, \ |
| 2716 | {"$s5", RTYPE_GP | 21}, \ |
| 2717 | {"$s6", RTYPE_GP | 22}, \ |
| 2718 | {"$s7", RTYPE_GP | 23}, \ |
| 2719 | {"$t8", RTYPE_GP | 24}, \ |
| 2720 | {"$t9", RTYPE_GP | 25}, \ |
| 2721 | {"$k0", RTYPE_GP | 26}, \ |
| 2722 | {"$kt0", RTYPE_GP | 26}, \ |
| 2723 | {"$k1", RTYPE_GP | 27}, \ |
| 2724 | {"$kt1", RTYPE_GP | 27}, \ |
| 2725 | {"$gp", RTYPE_GP | 28}, \ |
| 2726 | {"$sp", RTYPE_GP | 29}, \ |
| 2727 | {"$s8", RTYPE_GP | 30}, \ |
| 2728 | {"$fp", RTYPE_GP | 30}, \ |
| 2729 | {"$ra", RTYPE_GP | 31} |
| 2730 | |
| 2731 | #define MIPS16_SPECIAL_REGISTER_NAMES \ |
| 2732 | {"$pc", RTYPE_PC | 0} |
| 2733 | |
| 2734 | #define MDMX_VECTOR_REGISTER_NAMES \ |
| 2735 | /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \ |
| 2736 | /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \ |
| 2737 | {"$v2", RTYPE_VEC | 2}, \ |
| 2738 | {"$v3", RTYPE_VEC | 3}, \ |
| 2739 | {"$v4", RTYPE_VEC | 4}, \ |
| 2740 | {"$v5", RTYPE_VEC | 5}, \ |
| 2741 | {"$v6", RTYPE_VEC | 6}, \ |
| 2742 | {"$v7", RTYPE_VEC | 7}, \ |
| 2743 | {"$v8", RTYPE_VEC | 8}, \ |
| 2744 | {"$v9", RTYPE_VEC | 9}, \ |
| 2745 | {"$v10", RTYPE_VEC | 10}, \ |
| 2746 | {"$v11", RTYPE_VEC | 11}, \ |
| 2747 | {"$v12", RTYPE_VEC | 12}, \ |
| 2748 | {"$v13", RTYPE_VEC | 13}, \ |
| 2749 | {"$v14", RTYPE_VEC | 14}, \ |
| 2750 | {"$v15", RTYPE_VEC | 15}, \ |
| 2751 | {"$v16", RTYPE_VEC | 16}, \ |
| 2752 | {"$v17", RTYPE_VEC | 17}, \ |
| 2753 | {"$v18", RTYPE_VEC | 18}, \ |
| 2754 | {"$v19", RTYPE_VEC | 19}, \ |
| 2755 | {"$v20", RTYPE_VEC | 20}, \ |
| 2756 | {"$v21", RTYPE_VEC | 21}, \ |
| 2757 | {"$v22", RTYPE_VEC | 22}, \ |
| 2758 | {"$v23", RTYPE_VEC | 23}, \ |
| 2759 | {"$v24", RTYPE_VEC | 24}, \ |
| 2760 | {"$v25", RTYPE_VEC | 25}, \ |
| 2761 | {"$v26", RTYPE_VEC | 26}, \ |
| 2762 | {"$v27", RTYPE_VEC | 27}, \ |
| 2763 | {"$v28", RTYPE_VEC | 28}, \ |
| 2764 | {"$v29", RTYPE_VEC | 29}, \ |
| 2765 | {"$v30", RTYPE_VEC | 30}, \ |
| 2766 | {"$v31", RTYPE_VEC | 31} |
| 2767 | |
| 2768 | #define R5900_I_NAMES \ |
| 2769 | {"$I", RTYPE_R5900_I | 0} |
| 2770 | |
| 2771 | #define R5900_Q_NAMES \ |
| 2772 | {"$Q", RTYPE_R5900_Q | 0} |
| 2773 | |
| 2774 | #define R5900_R_NAMES \ |
| 2775 | {"$R", RTYPE_R5900_R | 0} |
| 2776 | |
| 2777 | #define R5900_ACC_NAMES \ |
| 2778 | {"$ACC", RTYPE_R5900_ACC | 0 } |
| 2779 | |
| 2780 | #define MIPS_DSP_ACCUMULATOR_NAMES \ |
| 2781 | {"$ac0", RTYPE_ACC | 0}, \ |
| 2782 | {"$ac1", RTYPE_ACC | 1}, \ |
| 2783 | {"$ac2", RTYPE_ACC | 2}, \ |
| 2784 | {"$ac3", RTYPE_ACC | 3} |
| 2785 | |
| 2786 | static const struct regname reg_names[] = { |
| 2787 | GENERIC_REGISTER_NUMBERS, |
| 2788 | FPU_REGISTER_NAMES, |
| 2789 | FPU_CONDITION_CODE_NAMES, |
| 2790 | COPROC_CONDITION_CODE_NAMES, |
| 2791 | |
| 2792 | /* The $txx registers depends on the abi, |
| 2793 | these will be added later into the symbol table from |
| 2794 | one of the tables below once mips_abi is set after |
| 2795 | parsing of arguments from the command line. */ |
| 2796 | SYMBOLIC_REGISTER_NAMES, |
| 2797 | |
| 2798 | MIPS16_SPECIAL_REGISTER_NAMES, |
| 2799 | MDMX_VECTOR_REGISTER_NAMES, |
| 2800 | R5900_I_NAMES, |
| 2801 | R5900_Q_NAMES, |
| 2802 | R5900_R_NAMES, |
| 2803 | R5900_ACC_NAMES, |
| 2804 | MIPS_DSP_ACCUMULATOR_NAMES, |
| 2805 | {0, 0} |
| 2806 | }; |
| 2807 | |
| 2808 | static const struct regname reg_names_o32[] = { |
| 2809 | O32_SYMBOLIC_REGISTER_NAMES, |
| 2810 | {0, 0} |
| 2811 | }; |
| 2812 | |
| 2813 | static const struct regname reg_names_n32n64[] = { |
| 2814 | N32N64_SYMBOLIC_REGISTER_NAMES, |
| 2815 | {0, 0} |
| 2816 | }; |
| 2817 | |
| 2818 | /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be |
| 2819 | interpreted as vector registers 0 and 1. If SYMVAL is the value of one |
| 2820 | of these register symbols, return the associated vector register, |
| 2821 | otherwise return SYMVAL itself. */ |
| 2822 | |
| 2823 | static unsigned int |
| 2824 | mips_prefer_vec_regno (unsigned int symval) |
| 2825 | { |
| 2826 | if ((symval & -2) == (RTYPE_GP | 2)) |
| 2827 | return RTYPE_VEC | (symval & 1); |
| 2828 | return symval; |
| 2829 | } |
| 2830 | |
| 2831 | /* Return true if string [S, E) is a valid register name, storing its |
| 2832 | symbol value in *SYMVAL_PTR if so. */ |
| 2833 | |
| 2834 | static bfd_boolean |
| 2835 | mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) |
| 2836 | { |
| 2837 | char save_c; |
| 2838 | symbolS *symbol; |
| 2839 | |
| 2840 | /* Terminate name. */ |
| 2841 | save_c = *e; |
| 2842 | *e = '\0'; |
| 2843 | |
| 2844 | /* Look up the name. */ |
| 2845 | symbol = symbol_find (s); |
| 2846 | *e = save_c; |
| 2847 | |
| 2848 | if (!symbol || S_GET_SEGMENT (symbol) != reg_section) |
| 2849 | return FALSE; |
| 2850 | |
| 2851 | *symval_ptr = S_GET_VALUE (symbol); |
| 2852 | return TRUE; |
| 2853 | } |
| 2854 | |
| 2855 | /* Return true if the string at *SPTR is a valid register name. Allow it |
| 2856 | to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR |
| 2857 | is nonnull. |
| 2858 | |
| 2859 | When returning true, move *SPTR past the register, store the |
| 2860 | register's symbol value in *SYMVAL_PTR and the channel mask in |
| 2861 | *CHANNELS_PTR (if nonnull). The symbol value includes the register |
| 2862 | number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask |
| 2863 | is a 4-bit value of the form XYZW and is 0 if no suffix was given. */ |
| 2864 | |
| 2865 | static bfd_boolean |
| 2866 | mips_parse_register (char **sptr, unsigned int *symval_ptr, |
| 2867 | unsigned int *channels_ptr) |
| 2868 | { |
| 2869 | char *s, *e, *m; |
| 2870 | const char *q; |
| 2871 | unsigned int channels, symval, bit; |
| 2872 | |
| 2873 | /* Find end of name. */ |
| 2874 | s = e = *sptr; |
| 2875 | if (is_name_beginner (*e)) |
| 2876 | ++e; |
| 2877 | while (is_part_of_name (*e)) |
| 2878 | ++e; |
| 2879 | |
| 2880 | channels = 0; |
| 2881 | if (!mips_parse_register_1 (s, e, &symval)) |
| 2882 | { |
| 2883 | if (!channels_ptr) |
| 2884 | return FALSE; |
| 2885 | |
| 2886 | /* Eat characters from the end of the string that are valid |
| 2887 | channel suffixes. The preceding register must be $ACC or |
| 2888 | end with a digit, so there is no ambiguity. */ |
| 2889 | bit = 1; |
| 2890 | m = e; |
| 2891 | for (q = "wzyx"; *q; q++, bit <<= 1) |
| 2892 | if (m > s && m[-1] == *q) |
| 2893 | { |
| 2894 | --m; |
| 2895 | channels |= bit; |
| 2896 | } |
| 2897 | |
| 2898 | if (channels == 0 |
| 2899 | || !mips_parse_register_1 (s, m, &symval) |
| 2900 | || (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0) |
| 2901 | return FALSE; |
| 2902 | } |
| 2903 | |
| 2904 | *sptr = e; |
| 2905 | *symval_ptr = symval; |
| 2906 | if (channels_ptr) |
| 2907 | *channels_ptr = channels; |
| 2908 | return TRUE; |
| 2909 | } |
| 2910 | |
| 2911 | /* Check if SPTR points at a valid register specifier according to TYPES. |
| 2912 | If so, then return 1, advance S to consume the specifier and store |
| 2913 | the register's number in REGNOP, otherwise return 0. */ |
| 2914 | |
| 2915 | static int |
| 2916 | reg_lookup (char **s, unsigned int types, unsigned int *regnop) |
| 2917 | { |
| 2918 | unsigned int regno; |
| 2919 | |
| 2920 | if (mips_parse_register (s, ®no, NULL)) |
| 2921 | { |
| 2922 | if (types & RTYPE_VEC) |
| 2923 | regno = mips_prefer_vec_regno (regno); |
| 2924 | if (regno & types) |
| 2925 | regno &= RNUM_MASK; |
| 2926 | else |
| 2927 | regno = ~0; |
| 2928 | } |
| 2929 | else |
| 2930 | { |
| 2931 | if (types & RWARN) |
| 2932 | as_warn (_("unrecognized register name `%s'"), *s); |
| 2933 | regno = ~0; |
| 2934 | } |
| 2935 | if (regnop) |
| 2936 | *regnop = regno; |
| 2937 | return regno <= RNUM_MASK; |
| 2938 | } |
| 2939 | |
| 2940 | /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated |
| 2941 | mask in *CHANNELS. Return a pointer to the first unconsumed character. */ |
| 2942 | |
| 2943 | static char * |
| 2944 | mips_parse_vu0_channels (char *s, unsigned int *channels) |
| 2945 | { |
| 2946 | unsigned int i; |
| 2947 | |
| 2948 | *channels = 0; |
| 2949 | for (i = 0; i < 4; i++) |
| 2950 | if (*s == "xyzw"[i]) |
| 2951 | { |
| 2952 | *channels |= 1 << (3 - i); |
| 2953 | ++s; |
| 2954 | } |
| 2955 | return s; |
| 2956 | } |
| 2957 | |
| 2958 | /* Token types for parsed operand lists. */ |
| 2959 | enum mips_operand_token_type { |
| 2960 | /* A plain register, e.g. $f2. */ |
| 2961 | OT_REG, |
| 2962 | |
| 2963 | /* A 4-bit XYZW channel mask. */ |
| 2964 | OT_CHANNELS, |
| 2965 | |
| 2966 | /* A constant vector index, e.g. [1]. */ |
| 2967 | OT_INTEGER_INDEX, |
| 2968 | |
| 2969 | /* A register vector index, e.g. [$2]. */ |
| 2970 | OT_REG_INDEX, |
| 2971 | |
| 2972 | /* A continuous range of registers, e.g. $s0-$s4. */ |
| 2973 | OT_REG_RANGE, |
| 2974 | |
| 2975 | /* A (possibly relocated) expression. */ |
| 2976 | OT_INTEGER, |
| 2977 | |
| 2978 | /* A floating-point value. */ |
| 2979 | OT_FLOAT, |
| 2980 | |
| 2981 | /* A single character. This can be '(', ')' or ',', but '(' only appears |
| 2982 | before OT_REGs. */ |
| 2983 | OT_CHAR, |
| 2984 | |
| 2985 | /* A doubled character, either "--" or "++". */ |
| 2986 | OT_DOUBLE_CHAR, |
| 2987 | |
| 2988 | /* The end of the operand list. */ |
| 2989 | OT_END |
| 2990 | }; |
| 2991 | |
| 2992 | /* A parsed operand token. */ |
| 2993 | struct mips_operand_token |
| 2994 | { |
| 2995 | /* The type of token. */ |
| 2996 | enum mips_operand_token_type type; |
| 2997 | union |
| 2998 | { |
| 2999 | /* The register symbol value for an OT_REG or OT_REG_INDEX. */ |
| 3000 | unsigned int regno; |
| 3001 | |
| 3002 | /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ |
| 3003 | unsigned int channels; |
| 3004 | |
| 3005 | /* The integer value of an OT_INTEGER_INDEX. */ |
| 3006 | addressT index; |
| 3007 | |
| 3008 | /* The two register symbol values involved in an OT_REG_RANGE. */ |
| 3009 | struct { |
| 3010 | unsigned int regno1; |
| 3011 | unsigned int regno2; |
| 3012 | } reg_range; |
| 3013 | |
| 3014 | /* The value of an OT_INTEGER. The value is represented as an |
| 3015 | expression and the relocation operators that were applied to |
| 3016 | that expression. The reloc entries are BFD_RELOC_UNUSED if no |
| 3017 | relocation operators were used. */ |
| 3018 | struct { |
| 3019 | expressionS value; |
| 3020 | bfd_reloc_code_real_type relocs[3]; |
| 3021 | } integer; |
| 3022 | |
| 3023 | /* The binary data for an OT_FLOAT constant, and the number of bytes |
| 3024 | in the constant. */ |
| 3025 | struct { |
| 3026 | unsigned char data[8]; |
| 3027 | int length; |
| 3028 | } flt; |
| 3029 | |
| 3030 | /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ |
| 3031 | char ch; |
| 3032 | } u; |
| 3033 | }; |
| 3034 | |
| 3035 | /* An obstack used to construct lists of mips_operand_tokens. */ |
| 3036 | static struct obstack mips_operand_tokens; |
| 3037 | |
| 3038 | /* Give TOKEN type TYPE and add it to mips_operand_tokens. */ |
| 3039 | |
| 3040 | static void |
| 3041 | mips_add_token (struct mips_operand_token *token, |
| 3042 | enum mips_operand_token_type type) |
| 3043 | { |
| 3044 | token->type = type; |
| 3045 | obstack_grow (&mips_operand_tokens, token, sizeof (*token)); |
| 3046 | } |
| 3047 | |
| 3048 | /* Check whether S is '(' followed by a register name. Add OT_CHAR |
| 3049 | and OT_REG tokens for them if so, and return a pointer to the first |
| 3050 | unconsumed character. Return null otherwise. */ |
| 3051 | |
| 3052 | static char * |
| 3053 | mips_parse_base_start (char *s) |
| 3054 | { |
| 3055 | struct mips_operand_token token; |
| 3056 | unsigned int regno, channels; |
| 3057 | bfd_boolean decrement_p; |
| 3058 | |
| 3059 | if (*s != '(') |
| 3060 | return 0; |
| 3061 | |
| 3062 | ++s; |
| 3063 | SKIP_SPACE_TABS (s); |
| 3064 | |
| 3065 | /* Only match "--" as part of a base expression. In other contexts "--X" |
| 3066 | is a double negative. */ |
| 3067 | decrement_p = (s[0] == '-' && s[1] == '-'); |
| 3068 | if (decrement_p) |
| 3069 | { |
| 3070 | s += 2; |
| 3071 | SKIP_SPACE_TABS (s); |
| 3072 | } |
| 3073 | |
| 3074 | /* Allow a channel specifier because that leads to better error messages |
| 3075 | than treating something like "$vf0x++" as an expression. */ |
| 3076 | if (!mips_parse_register (&s, ®no, &channels)) |
| 3077 | return 0; |
| 3078 | |
| 3079 | token.u.ch = '('; |
| 3080 | mips_add_token (&token, OT_CHAR); |
| 3081 | |
| 3082 | if (decrement_p) |
| 3083 | { |
| 3084 | token.u.ch = '-'; |
| 3085 | mips_add_token (&token, OT_DOUBLE_CHAR); |
| 3086 | } |
| 3087 | |
| 3088 | token.u.regno = regno; |
| 3089 | mips_add_token (&token, OT_REG); |
| 3090 | |
| 3091 | if (channels) |
| 3092 | { |
| 3093 | token.u.channels = channels; |
| 3094 | mips_add_token (&token, OT_CHANNELS); |
| 3095 | } |
| 3096 | |
| 3097 | /* For consistency, only match "++" as part of base expressions too. */ |
| 3098 | SKIP_SPACE_TABS (s); |
| 3099 | if (s[0] == '+' && s[1] == '+') |
| 3100 | { |
| 3101 | s += 2; |
| 3102 | token.u.ch = '+'; |
| 3103 | mips_add_token (&token, OT_DOUBLE_CHAR); |
| 3104 | } |
| 3105 | |
| 3106 | return s; |
| 3107 | } |
| 3108 | |
| 3109 | /* Parse one or more tokens from S. Return a pointer to the first |
| 3110 | unconsumed character on success. Return null if an error was found |
| 3111 | and store the error text in insn_error. FLOAT_FORMAT is as for |
| 3112 | mips_parse_arguments. */ |
| 3113 | |
| 3114 | static char * |
| 3115 | mips_parse_argument_token (char *s, char float_format) |
| 3116 | { |
| 3117 | char *end, *save_in; |
| 3118 | const char *err; |
| 3119 | unsigned int regno1, regno2, channels; |
| 3120 | struct mips_operand_token token; |
| 3121 | |
| 3122 | /* First look for "($reg", since we want to treat that as an |
| 3123 | OT_CHAR and OT_REG rather than an expression. */ |
| 3124 | end = mips_parse_base_start (s); |
| 3125 | if (end) |
| 3126 | return end; |
| 3127 | |
| 3128 | /* Handle other characters that end up as OT_CHARs. */ |
| 3129 | if (*s == ')' || *s == ',') |
| 3130 | { |
| 3131 | token.u.ch = *s; |
| 3132 | mips_add_token (&token, OT_CHAR); |
| 3133 | ++s; |
| 3134 | return s; |
| 3135 | } |
| 3136 | |
| 3137 | /* Handle tokens that start with a register. */ |
| 3138 | if (mips_parse_register (&s, ®no1, &channels)) |
| 3139 | { |
| 3140 | if (channels) |
| 3141 | { |
| 3142 | /* A register and a VU0 channel suffix. */ |
| 3143 | token.u.regno = regno1; |
| 3144 | mips_add_token (&token, OT_REG); |
| 3145 | |
| 3146 | token.u.channels = channels; |
| 3147 | mips_add_token (&token, OT_CHANNELS); |
| 3148 | return s; |
| 3149 | } |
| 3150 | |
| 3151 | SKIP_SPACE_TABS (s); |
| 3152 | if (*s == '-') |
| 3153 | { |
| 3154 | /* A register range. */ |
| 3155 | ++s; |
| 3156 | SKIP_SPACE_TABS (s); |
| 3157 | if (!mips_parse_register (&s, ®no2, NULL)) |
| 3158 | { |
| 3159 | set_insn_error (0, _("invalid register range")); |
| 3160 | return 0; |
| 3161 | } |
| 3162 | |
| 3163 | token.u.reg_range.regno1 = regno1; |
| 3164 | token.u.reg_range.regno2 = regno2; |
| 3165 | mips_add_token (&token, OT_REG_RANGE); |
| 3166 | return s; |
| 3167 | } |
| 3168 | |
| 3169 | /* Add the register itself. */ |
| 3170 | token.u.regno = regno1; |
| 3171 | mips_add_token (&token, OT_REG); |
| 3172 | |
| 3173 | /* Check for a vector index. */ |
| 3174 | if (*s == '[') |
| 3175 | { |
| 3176 | ++s; |
| 3177 | SKIP_SPACE_TABS (s); |
| 3178 | if (mips_parse_register (&s, &token.u.regno, NULL)) |
| 3179 | mips_add_token (&token, OT_REG_INDEX); |
| 3180 | else |
| 3181 | { |
| 3182 | expressionS element; |
| 3183 | |
| 3184 | my_getExpression (&element, s); |
| 3185 | if (element.X_op != O_constant) |
| 3186 | { |
| 3187 | set_insn_error (0, _("vector element must be constant")); |
| 3188 | return 0; |
| 3189 | } |
| 3190 | s = expr_end; |
| 3191 | token.u.index = element.X_add_number; |
| 3192 | mips_add_token (&token, OT_INTEGER_INDEX); |
| 3193 | } |
| 3194 | SKIP_SPACE_TABS (s); |
| 3195 | if (*s != ']') |
| 3196 | { |
| 3197 | set_insn_error (0, _("missing `]'")); |
| 3198 | return 0; |
| 3199 | } |
| 3200 | ++s; |
| 3201 | } |
| 3202 | return s; |
| 3203 | } |
| 3204 | |
| 3205 | if (float_format) |
| 3206 | { |
| 3207 | /* First try to treat expressions as floats. */ |
| 3208 | save_in = input_line_pointer; |
| 3209 | input_line_pointer = s; |
| 3210 | err = md_atof (float_format, (char *) token.u.flt.data, |
| 3211 | &token.u.flt.length); |
| 3212 | end = input_line_pointer; |
| 3213 | input_line_pointer = save_in; |
| 3214 | if (err && *err) |
| 3215 | { |
| 3216 | set_insn_error (0, err); |
| 3217 | return 0; |
| 3218 | } |
| 3219 | if (s != end) |
| 3220 | { |
| 3221 | mips_add_token (&token, OT_FLOAT); |
| 3222 | return end; |
| 3223 | } |
| 3224 | } |
| 3225 | |
| 3226 | /* Treat everything else as an integer expression. */ |
| 3227 | token.u.integer.relocs[0] = BFD_RELOC_UNUSED; |
| 3228 | token.u.integer.relocs[1] = BFD_RELOC_UNUSED; |
| 3229 | token.u.integer.relocs[2] = BFD_RELOC_UNUSED; |
| 3230 | my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); |
| 3231 | s = expr_end; |
| 3232 | mips_add_token (&token, OT_INTEGER); |
| 3233 | return s; |
| 3234 | } |
| 3235 | |
| 3236 | /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' |
| 3237 | if expressions should be treated as 32-bit floating-point constants, |
| 3238 | 'd' if they should be treated as 64-bit floating-point constants, |
| 3239 | or 0 if they should be treated as integer expressions (the usual case). |
| 3240 | |
| 3241 | Return a list of tokens on success, otherwise return 0. The caller |
| 3242 | must obstack_free the list after use. */ |
| 3243 | |
| 3244 | static struct mips_operand_token * |
| 3245 | mips_parse_arguments (char *s, char float_format) |
| 3246 | { |
| 3247 | struct mips_operand_token token; |
| 3248 | |
| 3249 | SKIP_SPACE_TABS (s); |
| 3250 | while (*s) |
| 3251 | { |
| 3252 | s = mips_parse_argument_token (s, float_format); |
| 3253 | if (!s) |
| 3254 | { |
| 3255 | obstack_free (&mips_operand_tokens, |
| 3256 | obstack_finish (&mips_operand_tokens)); |
| 3257 | return 0; |
| 3258 | } |
| 3259 | SKIP_SPACE_TABS (s); |
| 3260 | } |
| 3261 | mips_add_token (&token, OT_END); |
| 3262 | return (struct mips_operand_token *) obstack_finish (&mips_operand_tokens); |
| 3263 | } |
| 3264 | |
| 3265 | /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE |
| 3266 | and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */ |
| 3267 | |
| 3268 | static bfd_boolean |
| 3269 | is_opcode_valid (const struct mips_opcode *mo) |
| 3270 | { |
| 3271 | int isa = mips_opts.isa; |
| 3272 | int ase = mips_opts.ase; |
| 3273 | int fp_s, fp_d; |
| 3274 | unsigned int i; |
| 3275 | |
| 3276 | if (ISA_HAS_64BIT_REGS (isa)) |
| 3277 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
| 3278 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) |
| 3279 | ase |= mips_ases[i].flags64; |
| 3280 | |
| 3281 | if (!opcode_is_member (mo, isa, ase, mips_opts.arch)) |
| 3282 | return FALSE; |
| 3283 | |
| 3284 | /* Check whether the instruction or macro requires single-precision or |
| 3285 | double-precision floating-point support. Note that this information is |
| 3286 | stored differently in the opcode table for insns and macros. */ |
| 3287 | if (mo->pinfo == INSN_MACRO) |
| 3288 | { |
| 3289 | fp_s = mo->pinfo2 & INSN2_M_FP_S; |
| 3290 | fp_d = mo->pinfo2 & INSN2_M_FP_D; |
| 3291 | } |
| 3292 | else |
| 3293 | { |
| 3294 | fp_s = mo->pinfo & FP_S; |
| 3295 | fp_d = mo->pinfo & FP_D; |
| 3296 | } |
| 3297 | |
| 3298 | if (fp_d && (mips_opts.soft_float || mips_opts.single_float)) |
| 3299 | return FALSE; |
| 3300 | |
| 3301 | if (fp_s && mips_opts.soft_float) |
| 3302 | return FALSE; |
| 3303 | |
| 3304 | return TRUE; |
| 3305 | } |
| 3306 | |
| 3307 | /* Return TRUE if the MIPS16 opcode MO is valid on the currently |
| 3308 | selected ISA and architecture. */ |
| 3309 | |
| 3310 | static bfd_boolean |
| 3311 | is_opcode_valid_16 (const struct mips_opcode *mo) |
| 3312 | { |
| 3313 | int isa = mips_opts.isa; |
| 3314 | int ase = mips_opts.ase; |
| 3315 | unsigned int i; |
| 3316 | |
| 3317 | if (ISA_HAS_64BIT_REGS (isa)) |
| 3318 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
| 3319 | if ((ase & mips_ases[i].flags) == mips_ases[i].flags) |
| 3320 | ase |= mips_ases[i].flags64; |
| 3321 | |
| 3322 | return opcode_is_member (mo, isa, ase, mips_opts.arch); |
| 3323 | } |
| 3324 | |
| 3325 | /* Return TRUE if the size of the microMIPS opcode MO matches one |
| 3326 | explicitly requested. Always TRUE in the standard MIPS mode. |
| 3327 | Use is_size_valid_16 for MIPS16 opcodes. */ |
| 3328 | |
| 3329 | static bfd_boolean |
| 3330 | is_size_valid (const struct mips_opcode *mo) |
| 3331 | { |
| 3332 | if (!mips_opts.micromips) |
| 3333 | return TRUE; |
| 3334 | |
| 3335 | if (mips_opts.insn32) |
| 3336 | { |
| 3337 | if (mo->pinfo != INSN_MACRO && micromips_insn_length (mo) != 4) |
| 3338 | return FALSE; |
| 3339 | if ((mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0) |
| 3340 | return FALSE; |
| 3341 | } |
| 3342 | if (!forced_insn_length) |
| 3343 | return TRUE; |
| 3344 | if (mo->pinfo == INSN_MACRO) |
| 3345 | return FALSE; |
| 3346 | return forced_insn_length == micromips_insn_length (mo); |
| 3347 | } |
| 3348 | |
| 3349 | /* Return TRUE if the size of the MIPS16 opcode MO matches one |
| 3350 | explicitly requested. */ |
| 3351 | |
| 3352 | static bfd_boolean |
| 3353 | is_size_valid_16 (const struct mips_opcode *mo) |
| 3354 | { |
| 3355 | if (!forced_insn_length) |
| 3356 | return TRUE; |
| 3357 | if (mo->pinfo == INSN_MACRO) |
| 3358 | return FALSE; |
| 3359 | if (forced_insn_length == 2 && mips_opcode_32bit_p (mo)) |
| 3360 | return FALSE; |
| 3361 | if (forced_insn_length == 4 && (mo->pinfo2 & INSN2_SHORT_ONLY)) |
| 3362 | return FALSE; |
| 3363 | return TRUE; |
| 3364 | } |
| 3365 | |
| 3366 | /* Return TRUE if the microMIPS opcode MO is valid for the delay slot |
| 3367 | of the preceding instruction. Always TRUE in the standard MIPS mode. |
| 3368 | |
| 3369 | We don't accept macros in 16-bit delay slots to avoid a case where |
| 3370 | a macro expansion fails because it relies on a preceding 32-bit real |
| 3371 | instruction to have matched and does not handle the operands correctly. |
| 3372 | The only macros that may expand to 16-bit instructions are JAL that |
| 3373 | cannot be placed in a delay slot anyway, and corner cases of BALIGN |
| 3374 | and BGT (that likewise cannot be placed in a delay slot) that decay to |
| 3375 | a NOP. In all these cases the macros precede any corresponding real |
| 3376 | instruction definitions in the opcode table, so they will match in the |
| 3377 | second pass where the size of the delay slot is ignored and therefore |
| 3378 | produce correct code. */ |
| 3379 | |
| 3380 | static bfd_boolean |
| 3381 | is_delay_slot_valid (const struct mips_opcode *mo) |
| 3382 | { |
| 3383 | if (!mips_opts.micromips) |
| 3384 | return TRUE; |
| 3385 | |
| 3386 | if (mo->pinfo == INSN_MACRO) |
| 3387 | return (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) == 0; |
| 3388 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
| 3389 | && micromips_insn_length (mo) != 4) |
| 3390 | return FALSE; |
| 3391 | if ((history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
| 3392 | && micromips_insn_length (mo) != 2) |
| 3393 | return FALSE; |
| 3394 | |
| 3395 | return TRUE; |
| 3396 | } |
| 3397 | |
| 3398 | /* For consistency checking, verify that all bits of OPCODE are specified |
| 3399 | either by the match/mask part of the instruction definition, or by the |
| 3400 | operand list. Also build up a list of operands in OPERANDS. |
| 3401 | |
| 3402 | INSN_BITS says which bits of the instruction are significant. |
| 3403 | If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND |
| 3404 | provides the mips_operand description of each operand. DECODE_OPERAND |
| 3405 | is null for MIPS16 instructions. */ |
| 3406 | |
| 3407 | static int |
| 3408 | validate_mips_insn (const struct mips_opcode *opcode, |
| 3409 | unsigned long insn_bits, |
| 3410 | const struct mips_operand *(*decode_operand) (const char *), |
| 3411 | struct mips_operand_array *operands) |
| 3412 | { |
| 3413 | const char *s; |
| 3414 | unsigned long used_bits, doubled, undefined, opno, mask; |
| 3415 | const struct mips_operand *operand; |
| 3416 | |
| 3417 | mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); |
| 3418 | if ((mask & opcode->match) != opcode->match) |
| 3419 | { |
| 3420 | as_bad (_("internal: bad mips opcode (mask error): %s %s"), |
| 3421 | opcode->name, opcode->args); |
| 3422 | return 0; |
| 3423 | } |
| 3424 | used_bits = 0; |
| 3425 | opno = 0; |
| 3426 | if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) |
| 3427 | used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1); |
| 3428 | for (s = opcode->args; *s; ++s) |
| 3429 | switch (*s) |
| 3430 | { |
| 3431 | case ',': |
| 3432 | case '(': |
| 3433 | case ')': |
| 3434 | break; |
| 3435 | |
| 3436 | case '#': |
| 3437 | s++; |
| 3438 | break; |
| 3439 | |
| 3440 | default: |
| 3441 | if (!decode_operand) |
| 3442 | operand = decode_mips16_operand (*s, mips_opcode_32bit_p (opcode)); |
| 3443 | else |
| 3444 | operand = decode_operand (s); |
| 3445 | if (!operand && opcode->pinfo != INSN_MACRO) |
| 3446 | { |
| 3447 | as_bad (_("internal: unknown operand type: %s %s"), |
| 3448 | opcode->name, opcode->args); |
| 3449 | return 0; |
| 3450 | } |
| 3451 | gas_assert (opno < MAX_OPERANDS); |
| 3452 | operands->operand[opno] = operand; |
| 3453 | if (!decode_operand && operand |
| 3454 | && operand->type == OP_INT && operand->lsb == 0 |
| 3455 | && mips_opcode_32bit_p (opcode)) |
| 3456 | used_bits |= mips16_immed_extend (-1, operand->size); |
| 3457 | else if (operand && operand->type != OP_VU0_MATCH_SUFFIX) |
| 3458 | { |
| 3459 | used_bits = mips_insert_operand (operand, used_bits, -1); |
| 3460 | if (operand->type == OP_MDMX_IMM_REG) |
| 3461 | /* Bit 5 is the format selector (OB vs QH). The opcode table |
| 3462 | has separate entries for each format. */ |
| 3463 | used_bits &= ~(1 << (operand->lsb + 5)); |
| 3464 | if (operand->type == OP_ENTRY_EXIT_LIST) |
| 3465 | used_bits &= ~(mask & 0x700); |
| 3466 | } |
| 3467 | /* Skip prefix characters. */ |
| 3468 | if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) |
| 3469 | ++s; |
| 3470 | opno += 1; |
| 3471 | break; |
| 3472 | } |
| 3473 | doubled = used_bits & mask & insn_bits; |
| 3474 | if (doubled) |
| 3475 | { |
| 3476 | as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):" |
| 3477 | " %s %s"), doubled, opcode->name, opcode->args); |
| 3478 | return 0; |
| 3479 | } |
| 3480 | used_bits |= mask; |
| 3481 | undefined = ~used_bits & insn_bits; |
| 3482 | if (opcode->pinfo != INSN_MACRO && undefined) |
| 3483 | { |
| 3484 | as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"), |
| 3485 | undefined, opcode->name, opcode->args); |
| 3486 | return 0; |
| 3487 | } |
| 3488 | used_bits &= ~insn_bits; |
| 3489 | if (used_bits) |
| 3490 | { |
| 3491 | as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"), |
| 3492 | used_bits, opcode->name, opcode->args); |
| 3493 | return 0; |
| 3494 | } |
| 3495 | return 1; |
| 3496 | } |
| 3497 | |
| 3498 | /* The MIPS16 version of validate_mips_insn. */ |
| 3499 | |
| 3500 | static int |
| 3501 | validate_mips16_insn (const struct mips_opcode *opcode, |
| 3502 | struct mips_operand_array *operands) |
| 3503 | { |
| 3504 | unsigned long insn_bits = mips_opcode_32bit_p (opcode) ? 0xffffffff : 0xffff; |
| 3505 | |
| 3506 | return validate_mips_insn (opcode, insn_bits, 0, operands); |
| 3507 | } |
| 3508 | |
| 3509 | /* The microMIPS version of validate_mips_insn. */ |
| 3510 | |
| 3511 | static int |
| 3512 | validate_micromips_insn (const struct mips_opcode *opc, |
| 3513 | struct mips_operand_array *operands) |
| 3514 | { |
| 3515 | unsigned long insn_bits; |
| 3516 | unsigned long major; |
| 3517 | unsigned int length; |
| 3518 | |
| 3519 | if (opc->pinfo == INSN_MACRO) |
| 3520 | return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand, |
| 3521 | operands); |
| 3522 | |
| 3523 | length = micromips_insn_length (opc); |
| 3524 | if (length != 2 && length != 4) |
| 3525 | { |
| 3526 | as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): " |
| 3527 | "%s %s"), length, opc->name, opc->args); |
| 3528 | return 0; |
| 3529 | } |
| 3530 | major = opc->match >> (10 + 8 * (length - 2)); |
| 3531 | if ((length == 2 && (major & 7) != 1 && (major & 6) != 2) |
| 3532 | || (length == 4 && (major & 7) != 0 && (major & 4) != 4)) |
| 3533 | { |
| 3534 | as_bad (_("internal error: bad microMIPS opcode " |
| 3535 | "(opcode/length mismatch): %s %s"), opc->name, opc->args); |
| 3536 | return 0; |
| 3537 | } |
| 3538 | |
| 3539 | /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ |
| 3540 | insn_bits = 1 << 4 * length; |
| 3541 | insn_bits <<= 4 * length; |
| 3542 | insn_bits -= 1; |
| 3543 | return validate_mips_insn (opc, insn_bits, decode_micromips_operand, |
| 3544 | operands); |
| 3545 | } |
| 3546 | |
| 3547 | /* This function is called once, at assembler startup time. It should set up |
| 3548 | all the tables, etc. that the MD part of the assembler will need. */ |
| 3549 | |
| 3550 | void |
| 3551 | md_begin (void) |
| 3552 | { |
| 3553 | const char *retval = NULL; |
| 3554 | int i = 0; |
| 3555 | int broken = 0; |
| 3556 | |
| 3557 | if (mips_pic != NO_PIC) |
| 3558 | { |
| 3559 | if (g_switch_seen && g_switch_value != 0) |
| 3560 | as_bad (_("-G may not be used in position-independent code")); |
| 3561 | g_switch_value = 0; |
| 3562 | } |
| 3563 | else if (mips_abicalls) |
| 3564 | { |
| 3565 | if (g_switch_seen && g_switch_value != 0) |
| 3566 | as_bad (_("-G may not be used with abicalls")); |
| 3567 | g_switch_value = 0; |
| 3568 | } |
| 3569 | |
| 3570 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
| 3571 | as_warn (_("could not set architecture and machine")); |
| 3572 | |
| 3573 | op_hash = hash_new (); |
| 3574 | |
| 3575 | mips_operands = XCNEWVEC (struct mips_operand_array, NUMOPCODES); |
| 3576 | for (i = 0; i < NUMOPCODES;) |
| 3577 | { |
| 3578 | const char *name = mips_opcodes[i].name; |
| 3579 | |
| 3580 | retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]); |
| 3581 | if (retval != NULL) |
| 3582 | { |
| 3583 | fprintf (stderr, _("internal error: can't hash `%s': %s\n"), |
| 3584 | mips_opcodes[i].name, retval); |
| 3585 | /* Probably a memory allocation problem? Give up now. */ |
| 3586 | as_fatal (_("broken assembler, no assembly attempted")); |
| 3587 | } |
| 3588 | do |
| 3589 | { |
| 3590 | if (!validate_mips_insn (&mips_opcodes[i], 0xffffffff, |
| 3591 | decode_mips_operand, &mips_operands[i])) |
| 3592 | broken = 1; |
| 3593 | if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
| 3594 | { |
| 3595 | create_insn (&nop_insn, mips_opcodes + i); |
| 3596 | if (mips_fix_loongson2f_nop) |
| 3597 | nop_insn.insn_opcode = LOONGSON2F_NOP_INSN; |
| 3598 | nop_insn.fixed_p = 1; |
| 3599 | } |
| 3600 | ++i; |
| 3601 | } |
| 3602 | while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name)); |
| 3603 | } |
| 3604 | |
| 3605 | mips16_op_hash = hash_new (); |
| 3606 | mips16_operands = XCNEWVEC (struct mips_operand_array, |
| 3607 | bfd_mips16_num_opcodes); |
| 3608 | |
| 3609 | i = 0; |
| 3610 | while (i < bfd_mips16_num_opcodes) |
| 3611 | { |
| 3612 | const char *name = mips16_opcodes[i].name; |
| 3613 | |
| 3614 | retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]); |
| 3615 | if (retval != NULL) |
| 3616 | as_fatal (_("internal: can't hash `%s': %s"), |
| 3617 | mips16_opcodes[i].name, retval); |
| 3618 | do |
| 3619 | { |
| 3620 | if (!validate_mips16_insn (&mips16_opcodes[i], &mips16_operands[i])) |
| 3621 | broken = 1; |
| 3622 | if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0) |
| 3623 | { |
| 3624 | create_insn (&mips16_nop_insn, mips16_opcodes + i); |
| 3625 | mips16_nop_insn.fixed_p = 1; |
| 3626 | } |
| 3627 | ++i; |
| 3628 | } |
| 3629 | while (i < bfd_mips16_num_opcodes |
| 3630 | && strcmp (mips16_opcodes[i].name, name) == 0); |
| 3631 | } |
| 3632 | |
| 3633 | micromips_op_hash = hash_new (); |
| 3634 | micromips_operands = XCNEWVEC (struct mips_operand_array, |
| 3635 | bfd_micromips_num_opcodes); |
| 3636 | |
| 3637 | i = 0; |
| 3638 | while (i < bfd_micromips_num_opcodes) |
| 3639 | { |
| 3640 | const char *name = micromips_opcodes[i].name; |
| 3641 | |
| 3642 | retval = hash_insert (micromips_op_hash, name, |
| 3643 | (void *) µmips_opcodes[i]); |
| 3644 | if (retval != NULL) |
| 3645 | as_fatal (_("internal: can't hash `%s': %s"), |
| 3646 | micromips_opcodes[i].name, retval); |
| 3647 | do |
| 3648 | { |
| 3649 | struct mips_cl_insn *micromips_nop_insn; |
| 3650 | |
| 3651 | if (!validate_micromips_insn (µmips_opcodes[i], |
| 3652 | µmips_operands[i])) |
| 3653 | broken = 1; |
| 3654 | |
| 3655 | if (micromips_opcodes[i].pinfo != INSN_MACRO) |
| 3656 | { |
| 3657 | if (micromips_insn_length (micromips_opcodes + i) == 2) |
| 3658 | micromips_nop_insn = µmips_nop16_insn; |
| 3659 | else if (micromips_insn_length (micromips_opcodes + i) == 4) |
| 3660 | micromips_nop_insn = µmips_nop32_insn; |
| 3661 | else |
| 3662 | continue; |
| 3663 | |
| 3664 | if (micromips_nop_insn->insn_mo == NULL |
| 3665 | && strcmp (name, "nop") == 0) |
| 3666 | { |
| 3667 | create_insn (micromips_nop_insn, micromips_opcodes + i); |
| 3668 | micromips_nop_insn->fixed_p = 1; |
| 3669 | } |
| 3670 | } |
| 3671 | } |
| 3672 | while (++i < bfd_micromips_num_opcodes |
| 3673 | && strcmp (micromips_opcodes[i].name, name) == 0); |
| 3674 | } |
| 3675 | |
| 3676 | if (broken) |
| 3677 | as_fatal (_("broken assembler, no assembly attempted")); |
| 3678 | |
| 3679 | /* We add all the general register names to the symbol table. This |
| 3680 | helps us detect invalid uses of them. */ |
| 3681 | for (i = 0; reg_names[i].name; i++) |
| 3682 | symbol_table_insert (symbol_new (reg_names[i].name, reg_section, |
| 3683 | reg_names[i].num, /* & RNUM_MASK, */ |
| 3684 | &zero_address_frag)); |
| 3685 | if (HAVE_NEWABI) |
| 3686 | for (i = 0; reg_names_n32n64[i].name; i++) |
| 3687 | symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section, |
| 3688 | reg_names_n32n64[i].num, /* & RNUM_MASK, */ |
| 3689 | &zero_address_frag)); |
| 3690 | else |
| 3691 | for (i = 0; reg_names_o32[i].name; i++) |
| 3692 | symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section, |
| 3693 | reg_names_o32[i].num, /* & RNUM_MASK, */ |
| 3694 | &zero_address_frag)); |
| 3695 | |
| 3696 | for (i = 0; i < 32; i++) |
| 3697 | { |
| 3698 | char regname[6]; |
| 3699 | |
| 3700 | /* R5900 VU0 floating-point register. */ |
| 3701 | sprintf (regname, "$vf%d", i); |
| 3702 | symbol_table_insert (symbol_new (regname, reg_section, |
| 3703 | RTYPE_VF | i, &zero_address_frag)); |
| 3704 | |
| 3705 | /* R5900 VU0 integer register. */ |
| 3706 | sprintf (regname, "$vi%d", i); |
| 3707 | symbol_table_insert (symbol_new (regname, reg_section, |
| 3708 | RTYPE_VI | i, &zero_address_frag)); |
| 3709 | |
| 3710 | /* MSA register. */ |
| 3711 | sprintf (regname, "$w%d", i); |
| 3712 | symbol_table_insert (symbol_new (regname, reg_section, |
| 3713 | RTYPE_MSA | i, &zero_address_frag)); |
| 3714 | } |
| 3715 | |
| 3716 | obstack_init (&mips_operand_tokens); |
| 3717 | |
| 3718 | mips_no_prev_insn (); |
| 3719 | |
| 3720 | mips_gprmask = 0; |
| 3721 | mips_cprmask[0] = 0; |
| 3722 | mips_cprmask[1] = 0; |
| 3723 | mips_cprmask[2] = 0; |
| 3724 | mips_cprmask[3] = 0; |
| 3725 | |
| 3726 | /* set the default alignment for the text section (2**2) */ |
| 3727 | record_alignment (text_section, 2); |
| 3728 | |
| 3729 | bfd_set_gp_size (stdoutput, g_switch_value); |
| 3730 | |
| 3731 | /* On a native system other than VxWorks, sections must be aligned |
| 3732 | to 16 byte boundaries. When configured for an embedded ELF |
| 3733 | target, we don't bother. */ |
| 3734 | if (strncmp (TARGET_OS, "elf", 3) != 0 |
| 3735 | && strncmp (TARGET_OS, "vxworks", 7) != 0) |
| 3736 | { |
| 3737 | (void) bfd_set_section_alignment (stdoutput, text_section, 4); |
| 3738 | (void) bfd_set_section_alignment (stdoutput, data_section, 4); |
| 3739 | (void) bfd_set_section_alignment (stdoutput, bss_section, 4); |
| 3740 | } |
| 3741 | |
| 3742 | /* Create a .reginfo section for register masks and a .mdebug |
| 3743 | section for debugging information. */ |
| 3744 | { |
| 3745 | segT seg; |
| 3746 | subsegT subseg; |
| 3747 | flagword flags; |
| 3748 | segT sec; |
| 3749 | |
| 3750 | seg = now_seg; |
| 3751 | subseg = now_subseg; |
| 3752 | |
| 3753 | /* The ABI says this section should be loaded so that the |
| 3754 | running program can access it. However, we don't load it |
| 3755 | if we are configured for an embedded target */ |
| 3756 | flags = SEC_READONLY | SEC_DATA; |
| 3757 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
| 3758 | flags |= SEC_ALLOC | SEC_LOAD; |
| 3759 | |
| 3760 | if (mips_abi != N64_ABI) |
| 3761 | { |
| 3762 | sec = subseg_new (".reginfo", (subsegT) 0); |
| 3763 | |
| 3764 | bfd_set_section_flags (stdoutput, sec, flags); |
| 3765 | bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2); |
| 3766 | |
| 3767 | mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo)); |
| 3768 | } |
| 3769 | else |
| 3770 | { |
| 3771 | /* The 64-bit ABI uses a .MIPS.options section rather than |
| 3772 | .reginfo section. */ |
| 3773 | sec = subseg_new (".MIPS.options", (subsegT) 0); |
| 3774 | bfd_set_section_flags (stdoutput, sec, flags); |
| 3775 | bfd_set_section_alignment (stdoutput, sec, 3); |
| 3776 | |
| 3777 | /* Set up the option header. */ |
| 3778 | { |
| 3779 | Elf_Internal_Options opthdr; |
| 3780 | char *f; |
| 3781 | |
| 3782 | opthdr.kind = ODK_REGINFO; |
| 3783 | opthdr.size = (sizeof (Elf_External_Options) |
| 3784 | + sizeof (Elf64_External_RegInfo)); |
| 3785 | opthdr.section = 0; |
| 3786 | opthdr.info = 0; |
| 3787 | f = frag_more (sizeof (Elf_External_Options)); |
| 3788 | bfd_mips_elf_swap_options_out (stdoutput, &opthdr, |
| 3789 | (Elf_External_Options *) f); |
| 3790 | |
| 3791 | mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo)); |
| 3792 | } |
| 3793 | } |
| 3794 | |
| 3795 | sec = subseg_new (".MIPS.abiflags", (subsegT) 0); |
| 3796 | bfd_set_section_flags (stdoutput, sec, |
| 3797 | SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); |
| 3798 | bfd_set_section_alignment (stdoutput, sec, 3); |
| 3799 | mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); |
| 3800 | |
| 3801 | if (ECOFF_DEBUGGING) |
| 3802 | { |
| 3803 | sec = subseg_new (".mdebug", (subsegT) 0); |
| 3804 | (void) bfd_set_section_flags (stdoutput, sec, |
| 3805 | SEC_HAS_CONTENTS | SEC_READONLY); |
| 3806 | (void) bfd_set_section_alignment (stdoutput, sec, 2); |
| 3807 | } |
| 3808 | else if (mips_flag_pdr) |
| 3809 | { |
| 3810 | pdr_seg = subseg_new (".pdr", (subsegT) 0); |
| 3811 | (void) bfd_set_section_flags (stdoutput, pdr_seg, |
| 3812 | SEC_READONLY | SEC_RELOC |
| 3813 | | SEC_DEBUGGING); |
| 3814 | (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2); |
| 3815 | } |
| 3816 | |
| 3817 | subseg_set (seg, subseg); |
| 3818 | } |
| 3819 | |
| 3820 | if (mips_fix_vr4120) |
| 3821 | init_vr4120_conflicts (); |
| 3822 | } |
| 3823 | |
| 3824 | static inline void |
| 3825 | fpabi_incompatible_with (int fpabi, const char *what) |
| 3826 | { |
| 3827 | as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), |
| 3828 | Tag_GNU_MIPS_ABI_FP, fpabi, what); |
| 3829 | } |
| 3830 | |
| 3831 | static inline void |
| 3832 | fpabi_requires (int fpabi, const char *what) |
| 3833 | { |
| 3834 | as_warn (_(".gnu_attribute %d,%d requires `%s'"), |
| 3835 | Tag_GNU_MIPS_ABI_FP, fpabi, what); |
| 3836 | } |
| 3837 | |
| 3838 | /* Check -mabi and register sizes against the specified FP ABI. */ |
| 3839 | static void |
| 3840 | check_fpabi (int fpabi) |
| 3841 | { |
| 3842 | switch (fpabi) |
| 3843 | { |
| 3844 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
| 3845 | if (file_mips_opts.soft_float) |
| 3846 | fpabi_incompatible_with (fpabi, "softfloat"); |
| 3847 | else if (file_mips_opts.single_float) |
| 3848 | fpabi_incompatible_with (fpabi, "singlefloat"); |
| 3849 | if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) |
| 3850 | fpabi_incompatible_with (fpabi, "gp=64 fp=32"); |
| 3851 | else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) |
| 3852 | fpabi_incompatible_with (fpabi, "gp=32 fp=64"); |
| 3853 | break; |
| 3854 | |
| 3855 | case Val_GNU_MIPS_ABI_FP_XX: |
| 3856 | if (mips_abi != O32_ABI) |
| 3857 | fpabi_requires (fpabi, "-mabi=32"); |
| 3858 | else if (file_mips_opts.soft_float) |
| 3859 | fpabi_incompatible_with (fpabi, "softfloat"); |
| 3860 | else if (file_mips_opts.single_float) |
| 3861 | fpabi_incompatible_with (fpabi, "singlefloat"); |
| 3862 | else if (file_mips_opts.fp != 0) |
| 3863 | fpabi_requires (fpabi, "fp=xx"); |
| 3864 | break; |
| 3865 | |
| 3866 | case Val_GNU_MIPS_ABI_FP_64A: |
| 3867 | case Val_GNU_MIPS_ABI_FP_64: |
| 3868 | if (mips_abi != O32_ABI) |
| 3869 | fpabi_requires (fpabi, "-mabi=32"); |
| 3870 | else if (file_mips_opts.soft_float) |
| 3871 | fpabi_incompatible_with (fpabi, "softfloat"); |
| 3872 | else if (file_mips_opts.single_float) |
| 3873 | fpabi_incompatible_with (fpabi, "singlefloat"); |
| 3874 | else if (file_mips_opts.fp != 64) |
| 3875 | fpabi_requires (fpabi, "fp=64"); |
| 3876 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) |
| 3877 | fpabi_incompatible_with (fpabi, "nooddspreg"); |
| 3878 | else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) |
| 3879 | fpabi_requires (fpabi, "nooddspreg"); |
| 3880 | break; |
| 3881 | |
| 3882 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
| 3883 | if (file_mips_opts.soft_float) |
| 3884 | fpabi_incompatible_with (fpabi, "softfloat"); |
| 3885 | else if (!file_mips_opts.single_float) |
| 3886 | fpabi_requires (fpabi, "singlefloat"); |
| 3887 | break; |
| 3888 | |
| 3889 | case Val_GNU_MIPS_ABI_FP_SOFT: |
| 3890 | if (!file_mips_opts.soft_float) |
| 3891 | fpabi_requires (fpabi, "softfloat"); |
| 3892 | break; |
| 3893 | |
| 3894 | case Val_GNU_MIPS_ABI_FP_OLD_64: |
| 3895 | as_warn (_(".gnu_attribute %d,%d is no longer supported"), |
| 3896 | Tag_GNU_MIPS_ABI_FP, fpabi); |
| 3897 | break; |
| 3898 | |
| 3899 | case Val_GNU_MIPS_ABI_FP_NAN2008: |
| 3900 | /* Silently ignore compatibility value. */ |
| 3901 | break; |
| 3902 | |
| 3903 | default: |
| 3904 | as_warn (_(".gnu_attribute %d,%d is not a recognized" |
| 3905 | " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); |
| 3906 | break; |
| 3907 | } |
| 3908 | } |
| 3909 | |
| 3910 | /* Perform consistency checks on the current options. */ |
| 3911 | |
| 3912 | static void |
| 3913 | mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) |
| 3914 | { |
| 3915 | /* Check the size of integer registers agrees with the ABI and ISA. */ |
| 3916 | if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) |
| 3917 | as_bad (_("`gp=64' used with a 32-bit processor")); |
| 3918 | else if (abi_checks |
| 3919 | && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) |
| 3920 | as_bad (_("`gp=32' used with a 64-bit ABI")); |
| 3921 | else if (abi_checks |
| 3922 | && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) |
| 3923 | as_bad (_("`gp=64' used with a 32-bit ABI")); |
| 3924 | |
| 3925 | /* Check the size of the float registers agrees with the ABI and ISA. */ |
| 3926 | switch (opts->fp) |
| 3927 | { |
| 3928 | case 0: |
| 3929 | if (!CPU_HAS_LDC1_SDC1 (opts->arch)) |
| 3930 | as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); |
| 3931 | else if (opts->single_float == 1) |
| 3932 | as_bad (_("`fp=xx' cannot be used with `singlefloat'")); |
| 3933 | break; |
| 3934 | case 64: |
| 3935 | if (!ISA_HAS_64BIT_FPRS (opts->isa)) |
| 3936 | as_bad (_("`fp=64' used with a 32-bit fpu")); |
| 3937 | else if (abi_checks |
| 3938 | && ABI_NEEDS_32BIT_REGS (mips_abi) |
| 3939 | && !ISA_HAS_MXHC1 (opts->isa)) |
| 3940 | as_warn (_("`fp=64' used with a 32-bit ABI")); |
| 3941 | break; |
| 3942 | case 32: |
| 3943 | if (abi_checks |
| 3944 | && ABI_NEEDS_64BIT_REGS (mips_abi)) |
| 3945 | as_warn (_("`fp=32' used with a 64-bit ABI")); |
| 3946 | if (ISA_IS_R6 (opts->isa) && opts->single_float == 0) |
| 3947 | as_bad (_("`fp=32' used with a MIPS R6 cpu")); |
| 3948 | break; |
| 3949 | default: |
| 3950 | as_bad (_("Unknown size of floating point registers")); |
| 3951 | break; |
| 3952 | } |
| 3953 | |
| 3954 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) |
| 3955 | as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); |
| 3956 | |
| 3957 | if (opts->micromips == 1 && opts->mips16 == 1) |
| 3958 | as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips"); |
| 3959 | else if (ISA_IS_R6 (opts->isa) |
| 3960 | && (opts->micromips == 1 |
| 3961 | || opts->mips16 == 1)) |
| 3962 | as_fatal (_("`%s' cannot be used with `%s'"), |
| 3963 | opts->micromips ? "micromips" : "mips16", |
| 3964 | mips_cpu_info_from_isa (opts->isa)->name); |
| 3965 | |
| 3966 | if (ISA_IS_R6 (opts->isa) && mips_relax_branch) |
| 3967 | as_fatal (_("branch relaxation is not supported in `%s'"), |
| 3968 | mips_cpu_info_from_isa (opts->isa)->name); |
| 3969 | } |
| 3970 | |
| 3971 | /* Perform consistency checks on the module level options exactly once. |
| 3972 | This is a deferred check that happens: |
| 3973 | at the first .set directive |
| 3974 | or, at the first pseudo op that generates code (inc .dc.a) |
| 3975 | or, at the first instruction |
| 3976 | or, at the end. */ |
| 3977 | |
| 3978 | static void |
| 3979 | file_mips_check_options (void) |
| 3980 | { |
| 3981 | const struct mips_cpu_info *arch_info = 0; |
| 3982 | |
| 3983 | if (file_mips_opts_checked) |
| 3984 | return; |
| 3985 | |
| 3986 | /* The following code determines the register size. |
| 3987 | Similar code was added to GCC 3.3 (see override_options() in |
| 3988 | config/mips/mips.c). The GAS and GCC code should be kept in sync |
| 3989 | as much as possible. */ |
| 3990 | |
| 3991 | if (file_mips_opts.gp < 0) |
| 3992 | { |
| 3993 | /* Infer the integer register size from the ABI and processor. |
| 3994 | Restrict ourselves to 32-bit registers if that's all the |
| 3995 | processor has, or if the ABI cannot handle 64-bit registers. */ |
| 3996 | file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) |
| 3997 | || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) |
| 3998 | ? 32 : 64; |
| 3999 | } |
| 4000 | |
| 4001 | if (file_mips_opts.fp < 0) |
| 4002 | { |
| 4003 | /* No user specified float register size. |
| 4004 | ??? GAS treats single-float processors as though they had 64-bit |
| 4005 | float registers (although it complains when double-precision |
| 4006 | instructions are used). As things stand, saying they have 32-bit |
| 4007 | registers would lead to spurious "register must be even" messages. |
| 4008 | So here we assume float registers are never smaller than the |
| 4009 | integer ones. */ |
| 4010 | if (file_mips_opts.gp == 64) |
| 4011 | /* 64-bit integer registers implies 64-bit float registers. */ |
| 4012 | file_mips_opts.fp = 64; |
| 4013 | else if ((file_mips_opts.ase & FP64_ASES) |
| 4014 | && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) |
| 4015 | /* Handle ASEs that require 64-bit float registers, if possible. */ |
| 4016 | file_mips_opts.fp = 64; |
| 4017 | else if (ISA_IS_R6 (mips_opts.isa)) |
| 4018 | /* R6 implies 64-bit float registers. */ |
| 4019 | file_mips_opts.fp = 64; |
| 4020 | else |
| 4021 | /* 32-bit float registers. */ |
| 4022 | file_mips_opts.fp = 32; |
| 4023 | } |
| 4024 | |
| 4025 | arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); |
| 4026 | |
| 4027 | /* Disable operations on odd-numbered floating-point registers by default |
| 4028 | when using the FPXX ABI. */ |
| 4029 | if (file_mips_opts.oddspreg < 0) |
| 4030 | { |
| 4031 | if (file_mips_opts.fp == 0) |
| 4032 | file_mips_opts.oddspreg = 0; |
| 4033 | else |
| 4034 | file_mips_opts.oddspreg = 1; |
| 4035 | } |
| 4036 | |
| 4037 | /* End of GCC-shared inference code. */ |
| 4038 | |
| 4039 | /* This flag is set when we have a 64-bit capable CPU but use only |
| 4040 | 32-bit wide registers. Note that EABI does not use it. */ |
| 4041 | if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) |
| 4042 | && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) |
| 4043 | || mips_abi == O32_ABI)) |
| 4044 | mips_32bitmode = 1; |
| 4045 | |
| 4046 | if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) |
| 4047 | as_bad (_("trap exception not supported at ISA 1")); |
| 4048 | |
| 4049 | /* If the selected architecture includes support for ASEs, enable |
| 4050 | generation of code for them. */ |
| 4051 | if (file_mips_opts.mips16 == -1) |
| 4052 | file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; |
| 4053 | if (file_mips_opts.micromips == -1) |
| 4054 | file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) |
| 4055 | ? 1 : 0; |
| 4056 | |
| 4057 | if (mips_nan2008 == -1) |
| 4058 | mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; |
| 4059 | else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) |
| 4060 | as_fatal (_("`%s' does not support legacy NaN"), |
| 4061 | mips_cpu_info_from_arch (file_mips_opts.arch)->name); |
| 4062 | |
| 4063 | /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from |
| 4064 | being selected implicitly. */ |
| 4065 | if (file_mips_opts.fp != 64) |
| 4066 | file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; |
| 4067 | |
| 4068 | /* If the user didn't explicitly select or deselect a particular ASE, |
| 4069 | use the default setting for the CPU. */ |
| 4070 | file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); |
| 4071 | |
| 4072 | /* Set up the current options. These may change throughout assembly. */ |
| 4073 | mips_opts = file_mips_opts; |
| 4074 | |
| 4075 | mips_check_isa_supports_ases (); |
| 4076 | mips_check_options (&file_mips_opts, TRUE); |
| 4077 | file_mips_opts_checked = TRUE; |
| 4078 | |
| 4079 | if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) |
| 4080 | as_warn (_("could not set architecture and machine")); |
| 4081 | } |
| 4082 | |
| 4083 | void |
| 4084 | md_assemble (char *str) |
| 4085 | { |
| 4086 | struct mips_cl_insn insn; |
| 4087 | bfd_reloc_code_real_type unused_reloc[3] |
| 4088 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; |
| 4089 | |
| 4090 | file_mips_check_options (); |
| 4091 | |
| 4092 | imm_expr.X_op = O_absent; |
| 4093 | offset_expr.X_op = O_absent; |
| 4094 | offset_reloc[0] = BFD_RELOC_UNUSED; |
| 4095 | offset_reloc[1] = BFD_RELOC_UNUSED; |
| 4096 | offset_reloc[2] = BFD_RELOC_UNUSED; |
| 4097 | |
| 4098 | mips_mark_labels (); |
| 4099 | mips_assembling_insn = TRUE; |
| 4100 | clear_insn_error (); |
| 4101 | |
| 4102 | if (mips_opts.mips16) |
| 4103 | mips16_ip (str, &insn); |
| 4104 | else |
| 4105 | { |
| 4106 | mips_ip (str, &insn); |
| 4107 | DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"), |
| 4108 | str, insn.insn_opcode)); |
| 4109 | } |
| 4110 | |
| 4111 | if (insn_error.msg) |
| 4112 | report_insn_error (str); |
| 4113 | else if (insn.insn_mo->pinfo == INSN_MACRO) |
| 4114 | { |
| 4115 | macro_start (); |
| 4116 | if (mips_opts.mips16) |
| 4117 | mips16_macro (&insn); |
| 4118 | else |
| 4119 | macro (&insn, str); |
| 4120 | macro_end (); |
| 4121 | } |
| 4122 | else |
| 4123 | { |
| 4124 | if (offset_expr.X_op != O_absent) |
| 4125 | append_insn (&insn, &offset_expr, offset_reloc, FALSE); |
| 4126 | else |
| 4127 | append_insn (&insn, NULL, unused_reloc, FALSE); |
| 4128 | } |
| 4129 | |
| 4130 | mips_assembling_insn = FALSE; |
| 4131 | } |
| 4132 | |
| 4133 | /* Convenience functions for abstracting away the differences between |
| 4134 | MIPS16 and non-MIPS16 relocations. */ |
| 4135 | |
| 4136 | static inline bfd_boolean |
| 4137 | mips16_reloc_p (bfd_reloc_code_real_type reloc) |
| 4138 | { |
| 4139 | switch (reloc) |
| 4140 | { |
| 4141 | case BFD_RELOC_MIPS16_JMP: |
| 4142 | case BFD_RELOC_MIPS16_GPREL: |
| 4143 | case BFD_RELOC_MIPS16_GOT16: |
| 4144 | case BFD_RELOC_MIPS16_CALL16: |
| 4145 | case BFD_RELOC_MIPS16_HI16_S: |
| 4146 | case BFD_RELOC_MIPS16_HI16: |
| 4147 | case BFD_RELOC_MIPS16_LO16: |
| 4148 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
| 4149 | return TRUE; |
| 4150 | |
| 4151 | default: |
| 4152 | return FALSE; |
| 4153 | } |
| 4154 | } |
| 4155 | |
| 4156 | static inline bfd_boolean |
| 4157 | micromips_reloc_p (bfd_reloc_code_real_type reloc) |
| 4158 | { |
| 4159 | switch (reloc) |
| 4160 | { |
| 4161 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
| 4162 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: |
| 4163 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: |
| 4164 | case BFD_RELOC_MICROMIPS_GPREL16: |
| 4165 | case BFD_RELOC_MICROMIPS_JMP: |
| 4166 | case BFD_RELOC_MICROMIPS_HI16: |
| 4167 | case BFD_RELOC_MICROMIPS_HI16_S: |
| 4168 | case BFD_RELOC_MICROMIPS_LO16: |
| 4169 | case BFD_RELOC_MICROMIPS_LITERAL: |
| 4170 | case BFD_RELOC_MICROMIPS_GOT16: |
| 4171 | case BFD_RELOC_MICROMIPS_CALL16: |
| 4172 | case BFD_RELOC_MICROMIPS_GOT_HI16: |
| 4173 | case BFD_RELOC_MICROMIPS_GOT_LO16: |
| 4174 | case BFD_RELOC_MICROMIPS_CALL_HI16: |
| 4175 | case BFD_RELOC_MICROMIPS_CALL_LO16: |
| 4176 | case BFD_RELOC_MICROMIPS_SUB: |
| 4177 | case BFD_RELOC_MICROMIPS_GOT_PAGE: |
| 4178 | case BFD_RELOC_MICROMIPS_GOT_OFST: |
| 4179 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
| 4180 | case BFD_RELOC_MICROMIPS_HIGHEST: |
| 4181 | case BFD_RELOC_MICROMIPS_HIGHER: |
| 4182 | case BFD_RELOC_MICROMIPS_SCN_DISP: |
| 4183 | case BFD_RELOC_MICROMIPS_JALR: |
| 4184 | return TRUE; |
| 4185 | |
| 4186 | default: |
| 4187 | return FALSE; |
| 4188 | } |
| 4189 | } |
| 4190 | |
| 4191 | static inline bfd_boolean |
| 4192 | jmp_reloc_p (bfd_reloc_code_real_type reloc) |
| 4193 | { |
| 4194 | return reloc == BFD_RELOC_MIPS_JMP || reloc == BFD_RELOC_MICROMIPS_JMP; |
| 4195 | } |
| 4196 | |
| 4197 | static inline bfd_boolean |
| 4198 | b_reloc_p (bfd_reloc_code_real_type reloc) |
| 4199 | { |
| 4200 | return (reloc == BFD_RELOC_MIPS_26_PCREL_S2 |
| 4201 | || reloc == BFD_RELOC_MIPS_21_PCREL_S2 |
| 4202 | || reloc == BFD_RELOC_16_PCREL_S2 |
| 4203 | || reloc == BFD_RELOC_MIPS16_16_PCREL_S1 |
| 4204 | || reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
| 4205 | || reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1 |
| 4206 | || reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1); |
| 4207 | } |
| 4208 | |
| 4209 | static inline bfd_boolean |
| 4210 | got16_reloc_p (bfd_reloc_code_real_type reloc) |
| 4211 | { |
| 4212 | return (reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16 |
| 4213 | || reloc == BFD_RELOC_MICROMIPS_GOT16); |
| 4214 | } |
| 4215 | |
| 4216 | static inline bfd_boolean |
| 4217 | hi16_reloc_p (bfd_reloc_code_real_type reloc) |
| 4218 | { |
| 4219 | return (reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S |
| 4220 | || reloc == BFD_RELOC_MICROMIPS_HI16_S); |
| 4221 | } |
| 4222 | |
| 4223 | static inline bfd_boolean |
| 4224 | lo16_reloc_p (bfd_reloc_code_real_type reloc) |
| 4225 | { |
| 4226 | return (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16 |
| 4227 | || reloc == BFD_RELOC_MICROMIPS_LO16); |
| 4228 | } |
| 4229 | |
| 4230 | static inline bfd_boolean |
| 4231 | jalr_reloc_p (bfd_reloc_code_real_type reloc) |
| 4232 | { |
| 4233 | return reloc == BFD_RELOC_MIPS_JALR || reloc == BFD_RELOC_MICROMIPS_JALR; |
| 4234 | } |
| 4235 | |
| 4236 | static inline bfd_boolean |
| 4237 | gprel16_reloc_p (bfd_reloc_code_real_type reloc) |
| 4238 | { |
| 4239 | return (reloc == BFD_RELOC_GPREL16 || reloc == BFD_RELOC_MIPS16_GPREL |
| 4240 | || reloc == BFD_RELOC_MICROMIPS_GPREL16); |
| 4241 | } |
| 4242 | |
| 4243 | /* Return true if RELOC is a PC-relative relocation that does not have |
| 4244 | full address range. */ |
| 4245 | |
| 4246 | static inline bfd_boolean |
| 4247 | limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) |
| 4248 | { |
| 4249 | switch (reloc) |
| 4250 | { |
| 4251 | case BFD_RELOC_16_PCREL_S2: |
| 4252 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
| 4253 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
| 4254 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: |
| 4255 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: |
| 4256 | case BFD_RELOC_MIPS_21_PCREL_S2: |
| 4257 | case BFD_RELOC_MIPS_26_PCREL_S2: |
| 4258 | case BFD_RELOC_MIPS_18_PCREL_S3: |
| 4259 | case BFD_RELOC_MIPS_19_PCREL_S2: |
| 4260 | return TRUE; |
| 4261 | |
| 4262 | case BFD_RELOC_32_PCREL: |
| 4263 | case BFD_RELOC_HI16_S_PCREL: |
| 4264 | case BFD_RELOC_LO16_PCREL: |
| 4265 | return HAVE_64BIT_ADDRESSES; |
| 4266 | |
| 4267 | default: |
| 4268 | return FALSE; |
| 4269 | } |
| 4270 | } |
| 4271 | |
| 4272 | /* Return true if the given relocation might need a matching %lo(). |
| 4273 | This is only "might" because SVR4 R_MIPS_GOT16 relocations only |
| 4274 | need a matching %lo() when applied to local symbols. */ |
| 4275 | |
| 4276 | static inline bfd_boolean |
| 4277 | reloc_needs_lo_p (bfd_reloc_code_real_type reloc) |
| 4278 | { |
| 4279 | return (HAVE_IN_PLACE_ADDENDS |
| 4280 | && (hi16_reloc_p (reloc) |
| 4281 | /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo(); |
| 4282 | all GOT16 relocations evaluate to "G". */ |
| 4283 | || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC))); |
| 4284 | } |
| 4285 | |
| 4286 | /* Return the type of %lo() reloc needed by RELOC, given that |
| 4287 | reloc_needs_lo_p. */ |
| 4288 | |
| 4289 | static inline bfd_reloc_code_real_type |
| 4290 | matching_lo_reloc (bfd_reloc_code_real_type reloc) |
| 4291 | { |
| 4292 | return (mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 |
| 4293 | : (micromips_reloc_p (reloc) ? BFD_RELOC_MICROMIPS_LO16 |
| 4294 | : BFD_RELOC_LO16)); |
| 4295 | } |
| 4296 | |
| 4297 | /* Return true if the given fixup is followed by a matching R_MIPS_LO16 |
| 4298 | relocation. */ |
| 4299 | |
| 4300 | static inline bfd_boolean |
| 4301 | fixup_has_matching_lo_p (fixS *fixp) |
| 4302 | { |
| 4303 | return (fixp->fx_next != NULL |
| 4304 | && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) |
| 4305 | && fixp->fx_addsy == fixp->fx_next->fx_addsy |
| 4306 | && fixp->fx_offset == fixp->fx_next->fx_offset); |
| 4307 | } |
| 4308 | |
| 4309 | /* Move all labels in LABELS to the current insertion point. TEXT_P |
| 4310 | says whether the labels refer to text or data. */ |
| 4311 | |
| 4312 | static void |
| 4313 | mips_move_labels (struct insn_label_list *labels, bfd_boolean text_p) |
| 4314 | { |
| 4315 | struct insn_label_list *l; |
| 4316 | valueT val; |
| 4317 | |
| 4318 | for (l = labels; l != NULL; l = l->next) |
| 4319 | { |
| 4320 | gas_assert (S_GET_SEGMENT (l->label) == now_seg); |
| 4321 | symbol_set_frag (l->label, frag_now); |
| 4322 | val = (valueT) frag_now_fix (); |
| 4323 | /* MIPS16/microMIPS text labels are stored as odd. */ |
| 4324 | if (text_p && HAVE_CODE_COMPRESSION) |
| 4325 | ++val; |
| 4326 | S_SET_VALUE (l->label, val); |
| 4327 | } |
| 4328 | } |
| 4329 | |
| 4330 | /* Move all labels in insn_labels to the current insertion point |
| 4331 | and treat them as text labels. */ |
| 4332 | |
| 4333 | static void |
| 4334 | mips_move_text_labels (void) |
| 4335 | { |
| 4336 | mips_move_labels (seg_info (now_seg)->label_list, TRUE); |
| 4337 | } |
| 4338 | |
| 4339 | /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */ |
| 4340 | |
| 4341 | static bfd_boolean |
| 4342 | s_is_linkonce (symbolS *sym, segT from_seg) |
| 4343 | { |
| 4344 | bfd_boolean linkonce = FALSE; |
| 4345 | segT symseg = S_GET_SEGMENT (sym); |
| 4346 | |
| 4347 | if (symseg != from_seg && !S_IS_LOCAL (sym)) |
| 4348 | { |
| 4349 | if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE)) |
| 4350 | linkonce = TRUE; |
| 4351 | /* The GNU toolchain uses an extension for ELF: a section |
| 4352 | beginning with the magic string .gnu.linkonce is a |
| 4353 | linkonce section. */ |
| 4354 | if (strncmp (segment_name (symseg), ".gnu.linkonce", |
| 4355 | sizeof ".gnu.linkonce" - 1) == 0) |
| 4356 | linkonce = TRUE; |
| 4357 | } |
| 4358 | return linkonce; |
| 4359 | } |
| 4360 | |
| 4361 | /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the |
| 4362 | linker to handle them specially, such as generating jalx instructions |
| 4363 | when needed. We also make them odd for the duration of the assembly, |
| 4364 | in order to generate the right sort of code. We will make them even |
| 4365 | in the adjust_symtab routine, while leaving them marked. This is |
| 4366 | convenient for the debugger and the disassembler. The linker knows |
| 4367 | to make them odd again. */ |
| 4368 | |
| 4369 | static void |
| 4370 | mips_compressed_mark_label (symbolS *label) |
| 4371 | { |
| 4372 | gas_assert (HAVE_CODE_COMPRESSION); |
| 4373 | |
| 4374 | if (mips_opts.mips16) |
| 4375 | S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label))); |
| 4376 | else |
| 4377 | S_SET_OTHER (label, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label))); |
| 4378 | if ((S_GET_VALUE (label) & 1) == 0 |
| 4379 | /* Don't adjust the address if the label is global or weak, or |
| 4380 | in a link-once section, since we'll be emitting symbol reloc |
| 4381 | references to it which will be patched up by the linker, and |
| 4382 | the final value of the symbol may or may not be MIPS16/microMIPS. */ |
| 4383 | && !S_IS_WEAK (label) |
| 4384 | && !S_IS_EXTERNAL (label) |
| 4385 | && !s_is_linkonce (label, now_seg)) |
| 4386 | S_SET_VALUE (label, S_GET_VALUE (label) | 1); |
| 4387 | } |
| 4388 | |
| 4389 | /* Mark preceding MIPS16 or microMIPS instruction labels. */ |
| 4390 | |
| 4391 | static void |
| 4392 | mips_compressed_mark_labels (void) |
| 4393 | { |
| 4394 | struct insn_label_list *l; |
| 4395 | |
| 4396 | for (l = seg_info (now_seg)->label_list; l != NULL; l = l->next) |
| 4397 | mips_compressed_mark_label (l->label); |
| 4398 | } |
| 4399 | |
| 4400 | /* End the current frag. Make it a variant frag and record the |
| 4401 | relaxation info. */ |
| 4402 | |
| 4403 | static void |
| 4404 | relax_close_frag (void) |
| 4405 | { |
| 4406 | mips_macro_warning.first_frag = frag_now; |
| 4407 | frag_var (rs_machine_dependent, 0, 0, |
| 4408 | RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1], |
| 4409 | mips_pic != NO_PIC), |
| 4410 | mips_relax.symbol, 0, (char *) mips_relax.first_fixup); |
| 4411 | |
| 4412 | memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes)); |
| 4413 | mips_relax.first_fixup = 0; |
| 4414 | } |
| 4415 | |
| 4416 | /* Start a new relaxation sequence whose expansion depends on SYMBOL. |
| 4417 | See the comment above RELAX_ENCODE for more details. */ |
| 4418 | |
| 4419 | static void |
| 4420 | relax_start (symbolS *symbol) |
| 4421 | { |
| 4422 | gas_assert (mips_relax.sequence == 0); |
| 4423 | mips_relax.sequence = 1; |
| 4424 | mips_relax.symbol = symbol; |
| 4425 | } |
| 4426 | |
| 4427 | /* Start generating the second version of a relaxable sequence. |
| 4428 | See the comment above RELAX_ENCODE for more details. */ |
| 4429 | |
| 4430 | static void |
| 4431 | relax_switch (void) |
| 4432 | { |
| 4433 | gas_assert (mips_relax.sequence == 1); |
| 4434 | mips_relax.sequence = 2; |
| 4435 | } |
| 4436 | |
| 4437 | /* End the current relaxable sequence. */ |
| 4438 | |
| 4439 | static void |
| 4440 | relax_end (void) |
| 4441 | { |
| 4442 | gas_assert (mips_relax.sequence == 2); |
| 4443 | relax_close_frag (); |
| 4444 | mips_relax.sequence = 0; |
| 4445 | } |
| 4446 | |
| 4447 | /* Return true if IP is a delayed branch or jump. */ |
| 4448 | |
| 4449 | static inline bfd_boolean |
| 4450 | delayed_branch_p (const struct mips_cl_insn *ip) |
| 4451 | { |
| 4452 | return (ip->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY |
| 4453 | | INSN_COND_BRANCH_DELAY |
| 4454 | | INSN_COND_BRANCH_LIKELY)) != 0; |
| 4455 | } |
| 4456 | |
| 4457 | /* Return true if IP is a compact branch or jump. */ |
| 4458 | |
| 4459 | static inline bfd_boolean |
| 4460 | compact_branch_p (const struct mips_cl_insn *ip) |
| 4461 | { |
| 4462 | return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH |
| 4463 | | INSN2_COND_BRANCH)) != 0; |
| 4464 | } |
| 4465 | |
| 4466 | /* Return true if IP is an unconditional branch or jump. */ |
| 4467 | |
| 4468 | static inline bfd_boolean |
| 4469 | uncond_branch_p (const struct mips_cl_insn *ip) |
| 4470 | { |
| 4471 | return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0 |
| 4472 | || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); |
| 4473 | } |
| 4474 | |
| 4475 | /* Return true if IP is a branch-likely instruction. */ |
| 4476 | |
| 4477 | static inline bfd_boolean |
| 4478 | branch_likely_p (const struct mips_cl_insn *ip) |
| 4479 | { |
| 4480 | return (ip->insn_mo->pinfo & INSN_COND_BRANCH_LIKELY) != 0; |
| 4481 | } |
| 4482 | |
| 4483 | /* Return the type of nop that should be used to fill the delay slot |
| 4484 | of delayed branch IP. */ |
| 4485 | |
| 4486 | static struct mips_cl_insn * |
| 4487 | get_delay_slot_nop (const struct mips_cl_insn *ip) |
| 4488 | { |
| 4489 | if (mips_opts.micromips |
| 4490 | && (ip->insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
| 4491 | return µmips_nop32_insn; |
| 4492 | return NOP_INSN; |
| 4493 | } |
| 4494 | |
| 4495 | /* Return a mask that has bit N set if OPCODE reads the register(s) |
| 4496 | in operand N. */ |
| 4497 | |
| 4498 | static unsigned int |
| 4499 | insn_read_mask (const struct mips_opcode *opcode) |
| 4500 | { |
| 4501 | return (opcode->pinfo & INSN_READ_ALL) >> INSN_READ_SHIFT; |
| 4502 | } |
| 4503 | |
| 4504 | /* Return a mask that has bit N set if OPCODE writes to the register(s) |
| 4505 | in operand N. */ |
| 4506 | |
| 4507 | static unsigned int |
| 4508 | insn_write_mask (const struct mips_opcode *opcode) |
| 4509 | { |
| 4510 | return (opcode->pinfo & INSN_WRITE_ALL) >> INSN_WRITE_SHIFT; |
| 4511 | } |
| 4512 | |
| 4513 | /* Return a mask of the registers specified by operand OPERAND of INSN. |
| 4514 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK |
| 4515 | is set. */ |
| 4516 | |
| 4517 | static unsigned int |
| 4518 | operand_reg_mask (const struct mips_cl_insn *insn, |
| 4519 | const struct mips_operand *operand, |
| 4520 | unsigned int type_mask) |
| 4521 | { |
| 4522 | unsigned int uval, vsel; |
| 4523 | |
| 4524 | switch (operand->type) |
| 4525 | { |
| 4526 | case OP_INT: |
| 4527 | case OP_MAPPED_INT: |
| 4528 | case OP_MSB: |
| 4529 | case OP_PCREL: |
| 4530 | case OP_PERF_REG: |
| 4531 | case OP_ADDIUSP_INT: |
| 4532 | case OP_ENTRY_EXIT_LIST: |
| 4533 | case OP_REPEAT_DEST_REG: |
| 4534 | case OP_REPEAT_PREV_REG: |
| 4535 | case OP_PC: |
| 4536 | case OP_VU0_SUFFIX: |
| 4537 | case OP_VU0_MATCH_SUFFIX: |
| 4538 | case OP_IMM_INDEX: |
| 4539 | abort (); |
| 4540 | |
| 4541 | case OP_REG28: |
| 4542 | return 1 << 28; |
| 4543 | |
| 4544 | case OP_REG: |
| 4545 | case OP_OPTIONAL_REG: |
| 4546 | { |
| 4547 | const struct mips_reg_operand *reg_op; |
| 4548 | |
| 4549 | reg_op = (const struct mips_reg_operand *) operand; |
| 4550 | if (!(type_mask & (1 << reg_op->reg_type))) |
| 4551 | return 0; |
| 4552 | uval = insn_extract_operand (insn, operand); |
| 4553 | return 1 << mips_decode_reg_operand (reg_op, uval); |
| 4554 | } |
| 4555 | |
| 4556 | case OP_REG_PAIR: |
| 4557 | { |
| 4558 | const struct mips_reg_pair_operand *pair_op; |
| 4559 | |
| 4560 | pair_op = (const struct mips_reg_pair_operand *) operand; |
| 4561 | if (!(type_mask & (1 << pair_op->reg_type))) |
| 4562 | return 0; |
| 4563 | uval = insn_extract_operand (insn, operand); |
| 4564 | return (1 << pair_op->reg1_map[uval]) | (1 << pair_op->reg2_map[uval]); |
| 4565 | } |
| 4566 | |
| 4567 | case OP_CLO_CLZ_DEST: |
| 4568 | if (!(type_mask & (1 << OP_REG_GP))) |
| 4569 | return 0; |
| 4570 | uval = insn_extract_operand (insn, operand); |
| 4571 | return (1 << (uval & 31)) | (1 << (uval >> 5)); |
| 4572 | |
| 4573 | case OP_SAME_RS_RT: |
| 4574 | if (!(type_mask & (1 << OP_REG_GP))) |
| 4575 | return 0; |
| 4576 | uval = insn_extract_operand (insn, operand); |
| 4577 | gas_assert ((uval & 31) == (uval >> 5)); |
| 4578 | return 1 << (uval & 31); |
| 4579 | |
| 4580 | case OP_CHECK_PREV: |
| 4581 | case OP_NON_ZERO_REG: |
| 4582 | if (!(type_mask & (1 << OP_REG_GP))) |
| 4583 | return 0; |
| 4584 | uval = insn_extract_operand (insn, operand); |
| 4585 | return 1 << (uval & 31); |
| 4586 | |
| 4587 | case OP_LWM_SWM_LIST: |
| 4588 | abort (); |
| 4589 | |
| 4590 | case OP_SAVE_RESTORE_LIST: |
| 4591 | abort (); |
| 4592 | |
| 4593 | case OP_MDMX_IMM_REG: |
| 4594 | if (!(type_mask & (1 << OP_REG_VEC))) |
| 4595 | return 0; |
| 4596 | uval = insn_extract_operand (insn, operand); |
| 4597 | vsel = uval >> 5; |
| 4598 | if ((vsel & 0x18) == 0x18) |
| 4599 | return 0; |
| 4600 | return 1 << (uval & 31); |
| 4601 | |
| 4602 | case OP_REG_INDEX: |
| 4603 | if (!(type_mask & (1 << OP_REG_GP))) |
| 4604 | return 0; |
| 4605 | return 1 << insn_extract_operand (insn, operand); |
| 4606 | } |
| 4607 | abort (); |
| 4608 | } |
| 4609 | |
| 4610 | /* Return a mask of the registers specified by operands OPNO_MASK of INSN, |
| 4611 | where bit N of OPNO_MASK is set if operand N should be included. |
| 4612 | Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK |
| 4613 | is set. */ |
| 4614 | |
| 4615 | static unsigned int |
| 4616 | insn_reg_mask (const struct mips_cl_insn *insn, |
| 4617 | unsigned int type_mask, unsigned int opno_mask) |
| 4618 | { |
| 4619 | unsigned int opno, reg_mask; |
| 4620 | |
| 4621 | opno = 0; |
| 4622 | reg_mask = 0; |
| 4623 | while (opno_mask != 0) |
| 4624 | { |
| 4625 | if (opno_mask & 1) |
| 4626 | reg_mask |= operand_reg_mask (insn, insn_opno (insn, opno), type_mask); |
| 4627 | opno_mask >>= 1; |
| 4628 | opno += 1; |
| 4629 | } |
| 4630 | return reg_mask; |
| 4631 | } |
| 4632 | |
| 4633 | /* Return the mask of core registers that IP reads. */ |
| 4634 | |
| 4635 | static unsigned int |
| 4636 | gpr_read_mask (const struct mips_cl_insn *ip) |
| 4637 | { |
| 4638 | unsigned long pinfo, pinfo2; |
| 4639 | unsigned int mask; |
| 4640 | |
| 4641 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_read_mask (ip->insn_mo)); |
| 4642 | pinfo = ip->insn_mo->pinfo; |
| 4643 | pinfo2 = ip->insn_mo->pinfo2; |
| 4644 | if (pinfo & INSN_UDI) |
| 4645 | { |
| 4646 | /* UDI instructions have traditionally been assumed to read RS |
| 4647 | and RT. */ |
| 4648 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RT, *ip); |
| 4649 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip); |
| 4650 | } |
| 4651 | if (pinfo & INSN_READ_GPR_24) |
| 4652 | mask |= 1 << 24; |
| 4653 | if (pinfo2 & INSN2_READ_GPR_16) |
| 4654 | mask |= 1 << 16; |
| 4655 | if (pinfo2 & INSN2_READ_SP) |
| 4656 | mask |= 1 << SP; |
| 4657 | if (pinfo2 & INSN2_READ_GPR_31) |
| 4658 | mask |= 1 << 31; |
| 4659 | /* Don't include register 0. */ |
| 4660 | return mask & ~1; |
| 4661 | } |
| 4662 | |
| 4663 | /* Return the mask of core registers that IP writes. */ |
| 4664 | |
| 4665 | static unsigned int |
| 4666 | gpr_write_mask (const struct mips_cl_insn *ip) |
| 4667 | { |
| 4668 | unsigned long pinfo, pinfo2; |
| 4669 | unsigned int mask; |
| 4670 | |
| 4671 | mask = insn_reg_mask (ip, 1 << OP_REG_GP, insn_write_mask (ip->insn_mo)); |
| 4672 | pinfo = ip->insn_mo->pinfo; |
| 4673 | pinfo2 = ip->insn_mo->pinfo2; |
| 4674 | if (pinfo & INSN_WRITE_GPR_24) |
| 4675 | mask |= 1 << 24; |
| 4676 | if (pinfo & INSN_WRITE_GPR_31) |
| 4677 | mask |= 1 << 31; |
| 4678 | if (pinfo & INSN_UDI) |
| 4679 | /* UDI instructions have traditionally been assumed to write to RD. */ |
| 4680 | mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RD, *ip); |
| 4681 | if (pinfo2 & INSN2_WRITE_SP) |
| 4682 | mask |= 1 << SP; |
| 4683 | /* Don't include register 0. */ |
| 4684 | return mask & ~1; |
| 4685 | } |
| 4686 | |
| 4687 | /* Return the mask of floating-point registers that IP reads. */ |
| 4688 | |
| 4689 | static unsigned int |
| 4690 | fpr_read_mask (const struct mips_cl_insn *ip) |
| 4691 | { |
| 4692 | unsigned long pinfo; |
| 4693 | unsigned int mask; |
| 4694 | |
| 4695 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
| 4696 | | (1 << OP_REG_MSA)), |
| 4697 | insn_read_mask (ip->insn_mo)); |
| 4698 | pinfo = ip->insn_mo->pinfo; |
| 4699 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
| 4700 | (This is overly pessimistic for things like cvt.d.s.) */ |
| 4701 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
| 4702 | mask |= mask << 1; |
| 4703 | return mask; |
| 4704 | } |
| 4705 | |
| 4706 | /* Return the mask of floating-point registers that IP writes. */ |
| 4707 | |
| 4708 | static unsigned int |
| 4709 | fpr_write_mask (const struct mips_cl_insn *ip) |
| 4710 | { |
| 4711 | unsigned long pinfo; |
| 4712 | unsigned int mask; |
| 4713 | |
| 4714 | mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) |
| 4715 | | (1 << OP_REG_MSA)), |
| 4716 | insn_write_mask (ip->insn_mo)); |
| 4717 | pinfo = ip->insn_mo->pinfo; |
| 4718 | /* Conservatively treat all operands to an FP_D instruction are doubles. |
| 4719 | (This is overly pessimistic for things like cvt.s.d.) */ |
| 4720 | if (FPR_SIZE != 64 && (pinfo & FP_D)) |
| 4721 | mask |= mask << 1; |
| 4722 | return mask; |
| 4723 | } |
| 4724 | |
| 4725 | /* Operand OPNUM of INSN is an odd-numbered floating-point register. |
| 4726 | Check whether that is allowed. */ |
| 4727 | |
| 4728 | static bfd_boolean |
| 4729 | mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) |
| 4730 | { |
| 4731 | const char *s = insn->name; |
| 4732 | bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) |
| 4733 | || FPR_SIZE == 64) |
| 4734 | && mips_opts.oddspreg; |
| 4735 | |
| 4736 | if (insn->pinfo == INSN_MACRO) |
| 4737 | /* Let a macro pass, we'll catch it later when it is expanded. */ |
| 4738 | return TRUE; |
| 4739 | |
| 4740 | /* Single-precision coprocessor loads and moves are OK for 32-bit registers, |
| 4741 | otherwise it depends on oddspreg. */ |
| 4742 | if ((insn->pinfo & FP_S) |
| 4743 | && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY |
| 4744 | | INSN_LOAD_COPROC | INSN_COPROC_MOVE))) |
| 4745 | return FPR_SIZE == 32 || oddspreg; |
| 4746 | |
| 4747 | /* Allow odd registers for single-precision ops and double-precision if the |
| 4748 | floating-point registers are 64-bit wide. */ |
| 4749 | switch (insn->pinfo & (FP_S | FP_D)) |
| 4750 | { |
| 4751 | case FP_S: |
| 4752 | case 0: |
| 4753 | return oddspreg; |
| 4754 | case FP_D: |
| 4755 | return FPR_SIZE == 64; |
| 4756 | default: |
| 4757 | break; |
| 4758 | } |
| 4759 | |
| 4760 | /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ |
| 4761 | s = strchr (insn->name, '.'); |
| 4762 | if (s != NULL && opnum == 2) |
| 4763 | s = strchr (s + 1, '.'); |
| 4764 | if (s != NULL && (s[1] == 'w' || s[1] == 's')) |
| 4765 | return oddspreg; |
| 4766 | |
| 4767 | return FPR_SIZE == 64; |
| 4768 | } |
| 4769 | |
| 4770 | /* Information about an instruction argument that we're trying to match. */ |
| 4771 | struct mips_arg_info |
| 4772 | { |
| 4773 | /* The instruction so far. */ |
| 4774 | struct mips_cl_insn *insn; |
| 4775 | |
| 4776 | /* The first unconsumed operand token. */ |
| 4777 | struct mips_operand_token *token; |
| 4778 | |
| 4779 | /* The 1-based operand number, in terms of insn->insn_mo->args. */ |
| 4780 | int opnum; |
| 4781 | |
| 4782 | /* The 1-based argument number, for error reporting. This does not |
| 4783 | count elided optional registers, etc.. */ |
| 4784 | int argnum; |
| 4785 | |
| 4786 | /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ |
| 4787 | unsigned int last_regno; |
| 4788 | |
| 4789 | /* If the first operand was an OP_REG, this is the register that it |
| 4790 | specified, otherwise it is ILLEGAL_REG. */ |
| 4791 | unsigned int dest_regno; |
| 4792 | |
| 4793 | /* The value of the last OP_INT operand. Only used for OP_MSB, |
| 4794 | where it gives the lsb position. */ |
| 4795 | unsigned int last_op_int; |
| 4796 | |
| 4797 | /* If true, match routines should assume that no later instruction |
| 4798 | alternative matches and should therefore be as accommodating as |
| 4799 | possible. Match routines should not report errors if something |
| 4800 | is only invalid for !LAX_MATCH. */ |
| 4801 | bfd_boolean lax_match; |
| 4802 | |
| 4803 | /* True if a reference to the current AT register was seen. */ |
| 4804 | bfd_boolean seen_at; |
| 4805 | }; |
| 4806 | |
| 4807 | /* Record that the argument is out of range. */ |
| 4808 | |
| 4809 | static void |
| 4810 | match_out_of_range (struct mips_arg_info *arg) |
| 4811 | { |
| 4812 | set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); |
| 4813 | } |
| 4814 | |
| 4815 | /* Record that the argument isn't constant but needs to be. */ |
| 4816 | |
| 4817 | static void |
| 4818 | match_not_constant (struct mips_arg_info *arg) |
| 4819 | { |
| 4820 | set_insn_error_i (arg->argnum, _("operand %d must be constant"), |
| 4821 | arg->argnum); |
| 4822 | } |
| 4823 | |
| 4824 | /* Try to match an OT_CHAR token for character CH. Consume the token |
| 4825 | and return true on success, otherwise return false. */ |
| 4826 | |
| 4827 | static bfd_boolean |
| 4828 | match_char (struct mips_arg_info *arg, char ch) |
| 4829 | { |
| 4830 | if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) |
| 4831 | { |
| 4832 | ++arg->token; |
| 4833 | if (ch == ',') |
| 4834 | arg->argnum += 1; |
| 4835 | return TRUE; |
| 4836 | } |
| 4837 | return FALSE; |
| 4838 | } |
| 4839 | |
| 4840 | /* Try to get an expression from the next tokens in ARG. Consume the |
| 4841 | tokens and return true on success, storing the expression value in |
| 4842 | VALUE and relocation types in R. */ |
| 4843 | |
| 4844 | static bfd_boolean |
| 4845 | match_expression (struct mips_arg_info *arg, expressionS *value, |
| 4846 | bfd_reloc_code_real_type *r) |
| 4847 | { |
| 4848 | /* If the next token is a '(' that was parsed as being part of a base |
| 4849 | expression, assume we have an elided offset. The later match will fail |
| 4850 | if this turns out to be wrong. */ |
| 4851 | if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') |
| 4852 | { |
| 4853 | value->X_op = O_constant; |
| 4854 | value->X_add_number = 0; |
| 4855 | r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; |
| 4856 | return TRUE; |
| 4857 | } |
| 4858 | |
| 4859 | /* Reject register-based expressions such as "0+$2" and "(($2))". |
| 4860 | For plain registers the default error seems more appropriate. */ |
| 4861 | if (arg->token->type == OT_INTEGER |
| 4862 | && arg->token->u.integer.value.X_op == O_register) |
| 4863 | { |
| 4864 | set_insn_error (arg->argnum, _("register value used as expression")); |
| 4865 | return FALSE; |
| 4866 | } |
| 4867 | |
| 4868 | if (arg->token->type == OT_INTEGER) |
| 4869 | { |
| 4870 | *value = arg->token->u.integer.value; |
| 4871 | memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); |
| 4872 | ++arg->token; |
| 4873 | return TRUE; |
| 4874 | } |
| 4875 | |
| 4876 | set_insn_error_i |
| 4877 | (arg->argnum, _("operand %d must be an immediate expression"), |
| 4878 | arg->argnum); |
| 4879 | return FALSE; |
| 4880 | } |
| 4881 | |
| 4882 | /* Try to get a constant expression from the next tokens in ARG. Consume |
| 4883 | the tokens and return return true on success, storing the constant value |
| 4884 | in *VALUE. */ |
| 4885 | |
| 4886 | static bfd_boolean |
| 4887 | match_const_int (struct mips_arg_info *arg, offsetT *value) |
| 4888 | { |
| 4889 | expressionS ex; |
| 4890 | bfd_reloc_code_real_type r[3]; |
| 4891 | |
| 4892 | if (!match_expression (arg, &ex, r)) |
| 4893 | return FALSE; |
| 4894 | |
| 4895 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) |
| 4896 | *value = ex.X_add_number; |
| 4897 | else |
| 4898 | { |
| 4899 | if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_big) |
| 4900 | match_out_of_range (arg); |
| 4901 | else |
| 4902 | match_not_constant (arg); |
| 4903 | return FALSE; |
| 4904 | } |
| 4905 | return TRUE; |
| 4906 | } |
| 4907 | |
| 4908 | /* Return the RTYPE_* flags for a register operand of type TYPE that |
| 4909 | appears in instruction OPCODE. */ |
| 4910 | |
| 4911 | static unsigned int |
| 4912 | convert_reg_type (const struct mips_opcode *opcode, |
| 4913 | enum mips_reg_operand_type type) |
| 4914 | { |
| 4915 | switch (type) |
| 4916 | { |
| 4917 | case OP_REG_GP: |
| 4918 | return RTYPE_NUM | RTYPE_GP; |
| 4919 | |
| 4920 | case OP_REG_FP: |
| 4921 | /* Allow vector register names for MDMX if the instruction is a 64-bit |
| 4922 | FPR load, store or move (including moves to and from GPRs). */ |
| 4923 | if ((mips_opts.ase & ASE_MDMX) |
| 4924 | && (opcode->pinfo & FP_D) |
| 4925 | && (opcode->pinfo & (INSN_COPROC_MOVE |
| 4926 | | INSN_COPROC_MEMORY_DELAY |
| 4927 | | INSN_LOAD_COPROC |
| 4928 | | INSN_LOAD_MEMORY |
| 4929 | | INSN_STORE_MEMORY))) |
| 4930 | return RTYPE_FPU | RTYPE_VEC; |
| 4931 | return RTYPE_FPU; |
| 4932 | |
| 4933 | case OP_REG_CCC: |
| 4934 | if (opcode->pinfo & (FP_D | FP_S)) |
| 4935 | return RTYPE_CCC | RTYPE_FCC; |
| 4936 | return RTYPE_CCC; |
| 4937 | |
| 4938 | case OP_REG_VEC: |
| 4939 | if (opcode->membership & INSN_5400) |
| 4940 | return RTYPE_FPU; |
| 4941 | return RTYPE_FPU | RTYPE_VEC; |
| 4942 | |
| 4943 | case OP_REG_ACC: |
| 4944 | return RTYPE_ACC; |
| 4945 | |
| 4946 | case OP_REG_COPRO: |
| 4947 | if (opcode->name[strlen (opcode->name) - 1] == '0') |
| 4948 | return RTYPE_NUM | RTYPE_CP0; |
| 4949 | return RTYPE_NUM; |
| 4950 | |
| 4951 | case OP_REG_HW: |
| 4952 | return RTYPE_NUM; |
| 4953 | |
| 4954 | case OP_REG_VI: |
| 4955 | return RTYPE_NUM | RTYPE_VI; |
| 4956 | |
| 4957 | case OP_REG_VF: |
| 4958 | return RTYPE_NUM | RTYPE_VF; |
| 4959 | |
| 4960 | case OP_REG_R5900_I: |
| 4961 | return RTYPE_R5900_I; |
| 4962 | |
| 4963 | case OP_REG_R5900_Q: |
| 4964 | return RTYPE_R5900_Q; |
| 4965 | |
| 4966 | case OP_REG_R5900_R: |
| 4967 | return RTYPE_R5900_R; |
| 4968 | |
| 4969 | case OP_REG_R5900_ACC: |
| 4970 | return RTYPE_R5900_ACC; |
| 4971 | |
| 4972 | case OP_REG_MSA: |
| 4973 | return RTYPE_MSA; |
| 4974 | |
| 4975 | case OP_REG_MSA_CTRL: |
| 4976 | return RTYPE_NUM; |
| 4977 | } |
| 4978 | abort (); |
| 4979 | } |
| 4980 | |
| 4981 | /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ |
| 4982 | |
| 4983 | static void |
| 4984 | check_regno (struct mips_arg_info *arg, |
| 4985 | enum mips_reg_operand_type type, unsigned int regno) |
| 4986 | { |
| 4987 | if (AT && type == OP_REG_GP && regno == AT) |
| 4988 | arg->seen_at = TRUE; |
| 4989 | |
| 4990 | if (type == OP_REG_FP |
| 4991 | && (regno & 1) != 0 |
| 4992 | && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) |
| 4993 | { |
| 4994 | /* This was a warning prior to introducing O32 FPXX and FP64 support |
| 4995 | so maintain a warning for FP32 but raise an error for the new |
| 4996 | cases. */ |
| 4997 | if (FPR_SIZE == 32) |
| 4998 | as_warn (_("float register should be even, was %d"), regno); |
| 4999 | else |
| 5000 | as_bad (_("float register should be even, was %d"), regno); |
| 5001 | } |
| 5002 | |
| 5003 | if (type == OP_REG_CCC) |
| 5004 | { |
| 5005 | const char *name; |
| 5006 | size_t length; |
| 5007 | |
| 5008 | name = arg->insn->insn_mo->name; |
| 5009 | length = strlen (name); |
| 5010 | if ((regno & 1) != 0 |
| 5011 | && ((length >= 3 && strcmp (name + length - 3, ".ps") == 0) |
| 5012 | || (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0))) |
| 5013 | as_warn (_("condition code register should be even for %s, was %d"), |
| 5014 | name, regno); |
| 5015 | |
| 5016 | if ((regno & 3) != 0 |
| 5017 | && (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0)) |
| 5018 | as_warn (_("condition code register should be 0 or 4 for %s, was %d"), |
| 5019 | name, regno); |
| 5020 | } |
| 5021 | } |
| 5022 | |
| 5023 | /* ARG is a register with symbol value SYMVAL. Try to interpret it as |
| 5024 | a register of type TYPE. Return true on success, storing the register |
| 5025 | number in *REGNO and warning about any dubious uses. */ |
| 5026 | |
| 5027 | static bfd_boolean |
| 5028 | match_regno (struct mips_arg_info *arg, enum mips_reg_operand_type type, |
| 5029 | unsigned int symval, unsigned int *regno) |
| 5030 | { |
| 5031 | if (type == OP_REG_VEC) |
| 5032 | symval = mips_prefer_vec_regno (symval); |
| 5033 | if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) |
| 5034 | return FALSE; |
| 5035 | |
| 5036 | *regno = symval & RNUM_MASK; |
| 5037 | check_regno (arg, type, *regno); |
| 5038 | return TRUE; |
| 5039 | } |
| 5040 | |
| 5041 | /* Try to interpret the next token in ARG as a register of type TYPE. |
| 5042 | Consume the token and return true on success, storing the register |
| 5043 | number in *REGNO. Return false on failure. */ |
| 5044 | |
| 5045 | static bfd_boolean |
| 5046 | match_reg (struct mips_arg_info *arg, enum mips_reg_operand_type type, |
| 5047 | unsigned int *regno) |
| 5048 | { |
| 5049 | if (arg->token->type == OT_REG |
| 5050 | && match_regno (arg, type, arg->token->u.regno, regno)) |
| 5051 | { |
| 5052 | ++arg->token; |
| 5053 | return TRUE; |
| 5054 | } |
| 5055 | return FALSE; |
| 5056 | } |
| 5057 | |
| 5058 | /* Try to interpret the next token in ARG as a range of registers of type TYPE. |
| 5059 | Consume the token and return true on success, storing the register numbers |
| 5060 | in *REGNO1 and *REGNO2. Return false on failure. */ |
| 5061 | |
| 5062 | static bfd_boolean |
| 5063 | match_reg_range (struct mips_arg_info *arg, enum mips_reg_operand_type type, |
| 5064 | unsigned int *regno1, unsigned int *regno2) |
| 5065 | { |
| 5066 | if (match_reg (arg, type, regno1)) |
| 5067 | { |
| 5068 | *regno2 = *regno1; |
| 5069 | return TRUE; |
| 5070 | } |
| 5071 | if (arg->token->type == OT_REG_RANGE |
| 5072 | && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) |
| 5073 | && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) |
| 5074 | && *regno1 <= *regno2) |
| 5075 | { |
| 5076 | ++arg->token; |
| 5077 | return TRUE; |
| 5078 | } |
| 5079 | return FALSE; |
| 5080 | } |
| 5081 | |
| 5082 | /* OP_INT matcher. */ |
| 5083 | |
| 5084 | static bfd_boolean |
| 5085 | match_int_operand (struct mips_arg_info *arg, |
| 5086 | const struct mips_operand *operand_base) |
| 5087 | { |
| 5088 | const struct mips_int_operand *operand; |
| 5089 | unsigned int uval; |
| 5090 | int min_val, max_val, factor; |
| 5091 | offsetT sval; |
| 5092 | |
| 5093 | operand = (const struct mips_int_operand *) operand_base; |
| 5094 | factor = 1 << operand->shift; |
| 5095 | min_val = mips_int_operand_min (operand); |
| 5096 | max_val = mips_int_operand_max (operand); |
| 5097 | |
| 5098 | if (operand_base->lsb == 0 |
| 5099 | && operand_base->size == 16 |
| 5100 | && operand->shift == 0 |
| 5101 | && operand->bias == 0 |
| 5102 | && (operand->max_val == 32767 || operand->max_val == 65535)) |
| 5103 | { |
| 5104 | /* The operand can be relocated. */ |
| 5105 | if (!match_expression (arg, &offset_expr, offset_reloc)) |
| 5106 | return FALSE; |
| 5107 | |
| 5108 | if (offset_expr.X_op == O_big) |
| 5109 | { |
| 5110 | match_out_of_range (arg); |
| 5111 | return FALSE; |
| 5112 | } |
| 5113 | |
| 5114 | if (offset_reloc[0] != BFD_RELOC_UNUSED) |
| 5115 | /* Relocation operators were used. Accept the argument and |
| 5116 | leave the relocation value in offset_expr and offset_relocs |
| 5117 | for the caller to process. */ |
| 5118 | return TRUE; |
| 5119 | |
| 5120 | if (offset_expr.X_op != O_constant) |
| 5121 | { |
| 5122 | /* Accept non-constant operands if no later alternative matches, |
| 5123 | leaving it for the caller to process. */ |
| 5124 | if (!arg->lax_match) |
| 5125 | { |
| 5126 | match_not_constant (arg); |
| 5127 | return FALSE; |
| 5128 | } |
| 5129 | offset_reloc[0] = BFD_RELOC_LO16; |
| 5130 | return TRUE; |
| 5131 | } |
| 5132 | |
| 5133 | /* Clear the global state; we're going to install the operand |
| 5134 | ourselves. */ |
| 5135 | sval = offset_expr.X_add_number; |
| 5136 | offset_expr.X_op = O_absent; |
| 5137 | |
| 5138 | /* For compatibility with older assemblers, we accept |
| 5139 | 0x8000-0xffff as signed 16-bit numbers when only |
| 5140 | signed numbers are allowed. */ |
| 5141 | if (sval > max_val) |
| 5142 | { |
| 5143 | max_val = ((1 << operand_base->size) - 1) << operand->shift; |
| 5144 | if (!arg->lax_match && sval <= max_val) |
| 5145 | { |
| 5146 | match_out_of_range (arg); |
| 5147 | return FALSE; |
| 5148 | } |
| 5149 | } |
| 5150 | } |
| 5151 | else |
| 5152 | { |
| 5153 | if (!match_const_int (arg, &sval)) |
| 5154 | return FALSE; |
| 5155 | } |
| 5156 | |
| 5157 | arg->last_op_int = sval; |
| 5158 | |
| 5159 | if (sval < min_val || sval > max_val || sval % factor) |
| 5160 | { |
| 5161 | match_out_of_range (arg); |
| 5162 | return FALSE; |
| 5163 | } |
| 5164 | |
| 5165 | uval = (unsigned int) sval >> operand->shift; |
| 5166 | uval -= operand->bias; |
| 5167 | |
| 5168 | /* Handle -mfix-cn63xxp1. */ |
| 5169 | if (arg->opnum == 1 |
| 5170 | && mips_fix_cn63xxp1 |
| 5171 | && !mips_opts.micromips |
| 5172 | && strcmp ("pref", arg->insn->insn_mo->name) == 0) |
| 5173 | switch (uval) |
| 5174 | { |
| 5175 | case 5: |
| 5176 | case 25: |
| 5177 | case 26: |
| 5178 | case 27: |
| 5179 | case 28: |
| 5180 | case 29: |
| 5181 | case 30: |
| 5182 | case 31: |
| 5183 | /* These are ok. */ |
| 5184 | break; |
| 5185 | |
| 5186 | default: |
| 5187 | /* The rest must be changed to 28. */ |
| 5188 | uval = 28; |
| 5189 | break; |
| 5190 | } |
| 5191 | |
| 5192 | insn_insert_operand (arg->insn, operand_base, uval); |
| 5193 | return TRUE; |
| 5194 | } |
| 5195 | |
| 5196 | /* OP_MAPPED_INT matcher. */ |
| 5197 | |
| 5198 | static bfd_boolean |
| 5199 | match_mapped_int_operand (struct mips_arg_info *arg, |
| 5200 | const struct mips_operand *operand_base) |
| 5201 | { |
| 5202 | const struct mips_mapped_int_operand *operand; |
| 5203 | unsigned int uval, num_vals; |
| 5204 | offsetT sval; |
| 5205 | |
| 5206 | operand = (const struct mips_mapped_int_operand *) operand_base; |
| 5207 | if (!match_const_int (arg, &sval)) |
| 5208 | return FALSE; |
| 5209 | |
| 5210 | num_vals = 1 << operand_base->size; |
| 5211 | for (uval = 0; uval < num_vals; uval++) |
| 5212 | if (operand->int_map[uval] == sval) |
| 5213 | break; |
| 5214 | if (uval == num_vals) |
| 5215 | { |
| 5216 | match_out_of_range (arg); |
| 5217 | return FALSE; |
| 5218 | } |
| 5219 | |
| 5220 | insn_insert_operand (arg->insn, operand_base, uval); |
| 5221 | return TRUE; |
| 5222 | } |
| 5223 | |
| 5224 | /* OP_MSB matcher. */ |
| 5225 | |
| 5226 | static bfd_boolean |
| 5227 | match_msb_operand (struct mips_arg_info *arg, |
| 5228 | const struct mips_operand *operand_base) |
| 5229 | { |
| 5230 | const struct mips_msb_operand *operand; |
| 5231 | int min_val, max_val, max_high; |
| 5232 | offsetT size, sval, high; |
| 5233 | |
| 5234 | operand = (const struct mips_msb_operand *) operand_base; |
| 5235 | min_val = operand->bias; |
| 5236 | max_val = min_val + (1 << operand_base->size) - 1; |
| 5237 | max_high = operand->opsize; |
| 5238 | |
| 5239 | if (!match_const_int (arg, &size)) |
| 5240 | return FALSE; |
| 5241 | |
| 5242 | high = size + arg->last_op_int; |
| 5243 | sval = operand->add_lsb ? high : size; |
| 5244 | |
| 5245 | if (size < 0 || high > max_high || sval < min_val || sval > max_val) |
| 5246 | { |
| 5247 | match_out_of_range (arg); |
| 5248 | return FALSE; |
| 5249 | } |
| 5250 | insn_insert_operand (arg->insn, operand_base, sval - min_val); |
| 5251 | return TRUE; |
| 5252 | } |
| 5253 | |
| 5254 | /* OP_REG matcher. */ |
| 5255 | |
| 5256 | static bfd_boolean |
| 5257 | match_reg_operand (struct mips_arg_info *arg, |
| 5258 | const struct mips_operand *operand_base) |
| 5259 | { |
| 5260 | const struct mips_reg_operand *operand; |
| 5261 | unsigned int regno, uval, num_vals; |
| 5262 | |
| 5263 | operand = (const struct mips_reg_operand *) operand_base; |
| 5264 | if (!match_reg (arg, operand->reg_type, ®no)) |
| 5265 | return FALSE; |
| 5266 | |
| 5267 | if (operand->reg_map) |
| 5268 | { |
| 5269 | num_vals = 1 << operand->root.size; |
| 5270 | for (uval = 0; uval < num_vals; uval++) |
| 5271 | if (operand->reg_map[uval] == regno) |
| 5272 | break; |
| 5273 | if (num_vals == uval) |
| 5274 | return FALSE; |
| 5275 | } |
| 5276 | else |
| 5277 | uval = regno; |
| 5278 | |
| 5279 | arg->last_regno = regno; |
| 5280 | if (arg->opnum == 1) |
| 5281 | arg->dest_regno = regno; |
| 5282 | insn_insert_operand (arg->insn, operand_base, uval); |
| 5283 | return TRUE; |
| 5284 | } |
| 5285 | |
| 5286 | /* OP_REG_PAIR matcher. */ |
| 5287 | |
| 5288 | static bfd_boolean |
| 5289 | match_reg_pair_operand (struct mips_arg_info *arg, |
| 5290 | const struct mips_operand *operand_base) |
| 5291 | { |
| 5292 | const struct mips_reg_pair_operand *operand; |
| 5293 | unsigned int regno1, regno2, uval, num_vals; |
| 5294 | |
| 5295 | operand = (const struct mips_reg_pair_operand *) operand_base; |
| 5296 | if (!match_reg (arg, operand->reg_type, ®no1) |
| 5297 | || !match_char (arg, ',') |
| 5298 | || !match_reg (arg, operand->reg_type, ®no2)) |
| 5299 | return FALSE; |
| 5300 | |
| 5301 | num_vals = 1 << operand_base->size; |
| 5302 | for (uval = 0; uval < num_vals; uval++) |
| 5303 | if (operand->reg1_map[uval] == regno1 && operand->reg2_map[uval] == regno2) |
| 5304 | break; |
| 5305 | if (uval == num_vals) |
| 5306 | return FALSE; |
| 5307 | |
| 5308 | insn_insert_operand (arg->insn, operand_base, uval); |
| 5309 | return TRUE; |
| 5310 | } |
| 5311 | |
| 5312 | /* OP_PCREL matcher. The caller chooses the relocation type. */ |
| 5313 | |
| 5314 | static bfd_boolean |
| 5315 | match_pcrel_operand (struct mips_arg_info *arg) |
| 5316 | { |
| 5317 | bfd_reloc_code_real_type r[3]; |
| 5318 | |
| 5319 | return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; |
| 5320 | } |
| 5321 | |
| 5322 | /* OP_PERF_REG matcher. */ |
| 5323 | |
| 5324 | static bfd_boolean |
| 5325 | match_perf_reg_operand (struct mips_arg_info *arg, |
| 5326 | const struct mips_operand *operand) |
| 5327 | { |
| 5328 | offsetT sval; |
| 5329 | |
| 5330 | if (!match_const_int (arg, &sval)) |
| 5331 | return FALSE; |
| 5332 | |
| 5333 | if (sval != 0 |
| 5334 | && (sval != 1 |
| 5335 | || (mips_opts.arch == CPU_R5900 |
| 5336 | && (strcmp (arg->insn->insn_mo->name, "mfps") == 0 |
| 5337 | || strcmp (arg->insn->insn_mo->name, "mtps") == 0)))) |
| 5338 | { |
| 5339 | set_insn_error (arg->argnum, _("invalid performance register")); |
| 5340 | return FALSE; |
| 5341 | } |
| 5342 | |
| 5343 | insn_insert_operand (arg->insn, operand, sval); |
| 5344 | return TRUE; |
| 5345 | } |
| 5346 | |
| 5347 | /* OP_ADDIUSP matcher. */ |
| 5348 | |
| 5349 | static bfd_boolean |
| 5350 | match_addiusp_operand (struct mips_arg_info *arg, |
| 5351 | const struct mips_operand *operand) |
| 5352 | { |
| 5353 | offsetT sval; |
| 5354 | unsigned int uval; |
| 5355 | |
| 5356 | if (!match_const_int (arg, &sval)) |
| 5357 | return FALSE; |
| 5358 | |
| 5359 | if (sval % 4) |
| 5360 | { |
| 5361 | match_out_of_range (arg); |
| 5362 | return FALSE; |
| 5363 | } |
| 5364 | |
| 5365 | sval /= 4; |
| 5366 | if (!(sval >= -258 && sval <= 257) || (sval >= -2 && sval <= 1)) |
| 5367 | { |
| 5368 | match_out_of_range (arg); |
| 5369 | return FALSE; |
| 5370 | } |
| 5371 | |
| 5372 | uval = (unsigned int) sval; |
| 5373 | uval = ((uval >> 1) & ~0xff) | (uval & 0xff); |
| 5374 | insn_insert_operand (arg->insn, operand, uval); |
| 5375 | return TRUE; |
| 5376 | } |
| 5377 | |
| 5378 | /* OP_CLO_CLZ_DEST matcher. */ |
| 5379 | |
| 5380 | static bfd_boolean |
| 5381 | match_clo_clz_dest_operand (struct mips_arg_info *arg, |
| 5382 | const struct mips_operand *operand) |
| 5383 | { |
| 5384 | unsigned int regno; |
| 5385 | |
| 5386 | if (!match_reg (arg, OP_REG_GP, ®no)) |
| 5387 | return FALSE; |
| 5388 | |
| 5389 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
| 5390 | return TRUE; |
| 5391 | } |
| 5392 | |
| 5393 | /* OP_CHECK_PREV matcher. */ |
| 5394 | |
| 5395 | static bfd_boolean |
| 5396 | match_check_prev_operand (struct mips_arg_info *arg, |
| 5397 | const struct mips_operand *operand_base) |
| 5398 | { |
| 5399 | const struct mips_check_prev_operand *operand; |
| 5400 | unsigned int regno; |
| 5401 | |
| 5402 | operand = (const struct mips_check_prev_operand *) operand_base; |
| 5403 | |
| 5404 | if (!match_reg (arg, OP_REG_GP, ®no)) |
| 5405 | return FALSE; |
| 5406 | |
| 5407 | if (!operand->zero_ok && regno == 0) |
| 5408 | return FALSE; |
| 5409 | |
| 5410 | if ((operand->less_than_ok && regno < arg->last_regno) |
| 5411 | || (operand->greater_than_ok && regno > arg->last_regno) |
| 5412 | || (operand->equal_ok && regno == arg->last_regno)) |
| 5413 | { |
| 5414 | arg->last_regno = regno; |
| 5415 | insn_insert_operand (arg->insn, operand_base, regno); |
| 5416 | return TRUE; |
| 5417 | } |
| 5418 | |
| 5419 | return FALSE; |
| 5420 | } |
| 5421 | |
| 5422 | /* OP_SAME_RS_RT matcher. */ |
| 5423 | |
| 5424 | static bfd_boolean |
| 5425 | match_same_rs_rt_operand (struct mips_arg_info *arg, |
| 5426 | const struct mips_operand *operand) |
| 5427 | { |
| 5428 | unsigned int regno; |
| 5429 | |
| 5430 | if (!match_reg (arg, OP_REG_GP, ®no)) |
| 5431 | return FALSE; |
| 5432 | |
| 5433 | if (regno == 0) |
| 5434 | { |
| 5435 | set_insn_error (arg->argnum, _("the source register must not be $0")); |
| 5436 | return FALSE; |
| 5437 | } |
| 5438 | |
| 5439 | arg->last_regno = regno; |
| 5440 | |
| 5441 | insn_insert_operand (arg->insn, operand, regno | (regno << 5)); |
| 5442 | return TRUE; |
| 5443 | } |
| 5444 | |
| 5445 | /* OP_LWM_SWM_LIST matcher. */ |
| 5446 | |
| 5447 | static bfd_boolean |
| 5448 | match_lwm_swm_list_operand (struct mips_arg_info *arg, |
| 5449 | const struct mips_operand *operand) |
| 5450 | { |
| 5451 | unsigned int reglist, sregs, ra, regno1, regno2; |
| 5452 | struct mips_arg_info reset; |
| 5453 | |
| 5454 | reglist = 0; |
| 5455 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
| 5456 | return FALSE; |
| 5457 | do |
| 5458 | { |
| 5459 | if (regno2 == FP && regno1 >= S0 && regno1 <= S7) |
| 5460 | { |
| 5461 | reglist |= 1 << FP; |
| 5462 | regno2 = S7; |
| 5463 | } |
| 5464 | reglist |= ((1U << regno2 << 1) - 1) & -(1U << regno1); |
| 5465 | reset = *arg; |
| 5466 | } |
| 5467 | while (match_char (arg, ',') |
| 5468 | && match_reg_range (arg, OP_REG_GP, ®no1, ®no2)); |
| 5469 | *arg = reset; |
| 5470 | |
| 5471 | if (operand->size == 2) |
| 5472 | { |
| 5473 | /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.: |
| 5474 | |
| 5475 | s0, ra |
| 5476 | s0, s1, ra, s2, s3 |
| 5477 | s0-s2, ra |
| 5478 | |
| 5479 | and any permutations of these. */ |
| 5480 | if ((reglist & 0xfff1ffff) != 0x80010000) |
| 5481 | return FALSE; |
| 5482 | |
| 5483 | sregs = (reglist >> 17) & 7; |
| 5484 | ra = 0; |
| 5485 | } |
| 5486 | else |
| 5487 | { |
| 5488 | /* The list must include at least one of ra and s0-sN, |
| 5489 | for 0 <= N <= 8. (Note that there is a gap between s7 and s8, |
| 5490 | which are $23 and $30 respectively.) E.g.: |
| 5491 | |
| 5492 | ra |
| 5493 | s0 |
| 5494 | ra, s0, s1, s2 |
| 5495 | s0-s8 |
| 5496 | s0-s5, ra |
| 5497 | |
| 5498 | and any permutations of these. */ |
| 5499 | if ((reglist & 0x3f00ffff) != 0) |
| 5500 | return FALSE; |
| 5501 | |
| 5502 | ra = (reglist >> 27) & 0x10; |
| 5503 | sregs = ((reglist >> 22) & 0x100) | ((reglist >> 16) & 0xff); |
| 5504 | } |
| 5505 | sregs += 1; |
| 5506 | if ((sregs & -sregs) != sregs) |
| 5507 | return FALSE; |
| 5508 | |
| 5509 | insn_insert_operand (arg->insn, operand, (ffs (sregs) - 1) | ra); |
| 5510 | return TRUE; |
| 5511 | } |
| 5512 | |
| 5513 | /* OP_ENTRY_EXIT_LIST matcher. */ |
| 5514 | |
| 5515 | static unsigned int |
| 5516 | match_entry_exit_operand (struct mips_arg_info *arg, |
| 5517 | const struct mips_operand *operand) |
| 5518 | { |
| 5519 | unsigned int mask; |
| 5520 | bfd_boolean is_exit; |
| 5521 | |
| 5522 | /* The format is the same for both ENTRY and EXIT, but the constraints |
| 5523 | are different. */ |
| 5524 | is_exit = strcmp (arg->insn->insn_mo->name, "exit") == 0; |
| 5525 | mask = (is_exit ? 7 << 3 : 0); |
| 5526 | do |
| 5527 | { |
| 5528 | unsigned int regno1, regno2; |
| 5529 | bfd_boolean is_freg; |
| 5530 | |
| 5531 | if (match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
| 5532 | is_freg = FALSE; |
| 5533 | else if (match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) |
| 5534 | is_freg = TRUE; |
| 5535 | else |
| 5536 | return FALSE; |
| 5537 | |
| 5538 | if (is_exit && is_freg && regno1 == 0 && regno2 < 2) |
| 5539 | { |
| 5540 | mask &= ~(7 << 3); |
| 5541 | mask |= (5 + regno2) << 3; |
| 5542 | } |
| 5543 | else if (!is_exit && regno1 == 4 && regno2 >= 4 && regno2 <= 7) |
| 5544 | mask |= (regno2 - 3) << 3; |
| 5545 | else if (regno1 == 16 && regno2 >= 16 && regno2 <= 17) |
| 5546 | mask |= (regno2 - 15) << 1; |
| 5547 | else if (regno1 == RA && regno2 == RA) |
| 5548 | mask |= 1; |
| 5549 | else |
| 5550 | return FALSE; |
| 5551 | } |
| 5552 | while (match_char (arg, ',')); |
| 5553 | |
| 5554 | insn_insert_operand (arg->insn, operand, mask); |
| 5555 | return TRUE; |
| 5556 | } |
| 5557 | |
| 5558 | /* OP_SAVE_RESTORE_LIST matcher. */ |
| 5559 | |
| 5560 | static bfd_boolean |
| 5561 | match_save_restore_list_operand (struct mips_arg_info *arg) |
| 5562 | { |
| 5563 | unsigned int opcode, args, statics, sregs; |
| 5564 | unsigned int num_frame_sizes, num_args, num_statics, num_sregs; |
| 5565 | offsetT frame_size; |
| 5566 | |
| 5567 | opcode = arg->insn->insn_opcode; |
| 5568 | frame_size = 0; |
| 5569 | num_frame_sizes = 0; |
| 5570 | args = 0; |
| 5571 | statics = 0; |
| 5572 | sregs = 0; |
| 5573 | do |
| 5574 | { |
| 5575 | unsigned int regno1, regno2; |
| 5576 | |
| 5577 | if (arg->token->type == OT_INTEGER) |
| 5578 | { |
| 5579 | /* Handle the frame size. */ |
| 5580 | if (!match_const_int (arg, &frame_size)) |
| 5581 | return FALSE; |
| 5582 | num_frame_sizes += 1; |
| 5583 | } |
| 5584 | else |
| 5585 | { |
| 5586 | if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) |
| 5587 | return FALSE; |
| 5588 | |
| 5589 | while (regno1 <= regno2) |
| 5590 | { |
| 5591 | if (regno1 >= 4 && regno1 <= 7) |
| 5592 | { |
| 5593 | if (num_frame_sizes == 0) |
| 5594 | /* args $a0-$a3 */ |
| 5595 | args |= 1 << (regno1 - 4); |
| 5596 | else |
| 5597 | /* statics $a0-$a3 */ |
| 5598 | statics |= 1 << (regno1 - 4); |
| 5599 | } |
| 5600 | else if (regno1 >= 16 && regno1 <= 23) |
| 5601 | /* $s0-$s7 */ |
| 5602 | sregs |= 1 << (regno1 - 16); |
| 5603 | else if (regno1 == 30) |
| 5604 | /* $s8 */ |
| 5605 | sregs |= 1 << 8; |
| 5606 | else if (regno1 == 31) |
| 5607 | /* Add $ra to insn. */ |
| 5608 | opcode |= 0x40; |
| 5609 | else |
| 5610 | return FALSE; |
| 5611 | regno1 += 1; |
| 5612 | if (regno1 == 24) |
| 5613 | regno1 = 30; |
| 5614 | } |
| 5615 | } |
| 5616 | } |
| 5617 | while (match_char (arg, ',')); |
| 5618 | |
| 5619 | /* Encode args/statics combination. */ |
| 5620 | if (args & statics) |
| 5621 | return FALSE; |
| 5622 | else if (args == 0xf) |
| 5623 | /* All $a0-$a3 are args. */ |
| 5624 | opcode |= MIPS16_ALL_ARGS << 16; |
| 5625 | else if (statics == 0xf) |
| 5626 | /* All $a0-$a3 are statics. */ |
| 5627 | opcode |= MIPS16_ALL_STATICS << 16; |
| 5628 | else |
| 5629 | { |
| 5630 | /* Count arg registers. */ |
| 5631 | num_args = 0; |
| 5632 | while (args & 0x1) |
| 5633 | { |
| 5634 | args >>= 1; |
| 5635 | num_args += 1; |
| 5636 | } |
| 5637 | if (args != 0) |
| 5638 | return FALSE; |
| 5639 | |
| 5640 | /* Count static registers. */ |
| 5641 | num_statics = 0; |
| 5642 | while (statics & 0x8) |
| 5643 | { |
| 5644 | statics = (statics << 1) & 0xf; |
| 5645 | num_statics += 1; |
| 5646 | } |
| 5647 | if (statics != 0) |
| 5648 | return FALSE; |
| 5649 | |
| 5650 | /* Encode args/statics. */ |
| 5651 | opcode |= ((num_args << 2) | num_statics) << 16; |
| 5652 | } |
| 5653 | |
| 5654 | /* Encode $s0/$s1. */ |
| 5655 | if (sregs & (1 << 0)) /* $s0 */ |
| 5656 | opcode |= 0x20; |
| 5657 | if (sregs & (1 << 1)) /* $s1 */ |
| 5658 | opcode |= 0x10; |
| 5659 | sregs >>= 2; |
| 5660 | |
| 5661 | /* Encode $s2-$s8. */ |
| 5662 | num_sregs = 0; |
| 5663 | while (sregs & 1) |
| 5664 | { |
| 5665 | sregs >>= 1; |
| 5666 | num_sregs += 1; |
| 5667 | } |
| 5668 | if (sregs != 0) |
| 5669 | return FALSE; |
| 5670 | opcode |= num_sregs << 24; |
| 5671 | |
| 5672 | /* Encode frame size. */ |
| 5673 | if (num_frame_sizes == 0) |
| 5674 | { |
| 5675 | set_insn_error (arg->argnum, _("missing frame size")); |
| 5676 | return FALSE; |
| 5677 | } |
| 5678 | if (num_frame_sizes > 1) |
| 5679 | { |
| 5680 | set_insn_error (arg->argnum, _("frame size specified twice")); |
| 5681 | return FALSE; |
| 5682 | } |
| 5683 | if ((frame_size & 7) != 0 || frame_size < 0 || frame_size > 0xff * 8) |
| 5684 | { |
| 5685 | set_insn_error (arg->argnum, _("invalid frame size")); |
| 5686 | return FALSE; |
| 5687 | } |
| 5688 | if (frame_size != 128 || (opcode >> 16) != 0) |
| 5689 | { |
| 5690 | frame_size /= 8; |
| 5691 | opcode |= (((frame_size & 0xf0) << 16) |
| 5692 | | (frame_size & 0x0f)); |
| 5693 | } |
| 5694 | |
| 5695 | /* Finally build the instruction. */ |
| 5696 | if ((opcode >> 16) != 0 || frame_size == 0) |
| 5697 | opcode |= MIPS16_EXTEND; |
| 5698 | arg->insn->insn_opcode = opcode; |
| 5699 | return TRUE; |
| 5700 | } |
| 5701 | |
| 5702 | /* OP_MDMX_IMM_REG matcher. */ |
| 5703 | |
| 5704 | static bfd_boolean |
| 5705 | match_mdmx_imm_reg_operand (struct mips_arg_info *arg, |
| 5706 | const struct mips_operand *operand) |
| 5707 | { |
| 5708 | unsigned int regno, uval; |
| 5709 | bfd_boolean is_qh; |
| 5710 | const struct mips_opcode *opcode; |
| 5711 | |
| 5712 | /* The mips_opcode records whether this is an octobyte or quadhalf |
| 5713 | instruction. Start out with that bit in place. */ |
| 5714 | opcode = arg->insn->insn_mo; |
| 5715 | uval = mips_extract_operand (operand, opcode->match); |
| 5716 | is_qh = (uval != 0); |
| 5717 | |
| 5718 | if (arg->token->type == OT_REG) |
| 5719 | { |
| 5720 | if ((opcode->membership & INSN_5400) |
| 5721 | && strcmp (opcode->name, "rzu.ob") == 0) |
| 5722 | { |
| 5723 | set_insn_error_i (arg->argnum, _("operand %d must be an immediate"), |
| 5724 | arg->argnum); |
| 5725 | return FALSE; |
| 5726 | } |
| 5727 | |
| 5728 | if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) |
| 5729 | return FALSE; |
| 5730 | ++arg->token; |
| 5731 | |
| 5732 | /* Check whether this is a vector register or a broadcast of |
| 5733 | a single element. */ |
| 5734 | if (arg->token->type == OT_INTEGER_INDEX) |
| 5735 | { |
| 5736 | if (arg->token->u.index > (is_qh ? 3 : 7)) |
| 5737 | { |
| 5738 | set_insn_error (arg->argnum, _("invalid element selector")); |
| 5739 | return FALSE; |
| 5740 | } |
| 5741 | uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; |
| 5742 | ++arg->token; |
| 5743 | } |
| 5744 | else |
| 5745 | { |
| 5746 | /* A full vector. */ |
| 5747 | if ((opcode->membership & INSN_5400) |
| 5748 | && (strcmp (opcode->name, "sll.ob") == 0 |
| 5749 | || strcmp (opcode->name, "srl.ob") == 0)) |
| 5750 | { |
| 5751 | set_insn_error_i (arg->argnum, _("operand %d must be scalar"), |
| 5752 | arg->argnum); |
| 5753 | return FALSE; |
| 5754 | } |
| 5755 | |
| 5756 | if (is_qh) |
| 5757 | uval |= MDMX_FMTSEL_VEC_QH << 5; |
| 5758 | else |
| 5759 | uval |= MDMX_FMTSEL_VEC_OB << 5; |
| 5760 | } |
| 5761 | uval |= regno; |
| 5762 | } |
| 5763 | else |
| 5764 | { |
| 5765 | offsetT sval; |
| 5766 | |
| 5767 | if (!match_const_int (arg, &sval)) |
| 5768 | return FALSE; |
| 5769 | if (sval < 0 || sval > 31) |
| 5770 | { |
| 5771 | match_out_of_range (arg); |
| 5772 | return FALSE; |
| 5773 | } |
| 5774 | uval |= (sval & 31); |
| 5775 | if (is_qh) |
| 5776 | uval |= MDMX_FMTSEL_IMM_QH << 5; |
| 5777 | else |
| 5778 | uval |= MDMX_FMTSEL_IMM_OB << 5; |
| 5779 | } |
| 5780 | insn_insert_operand (arg->insn, operand, uval); |
| 5781 | return TRUE; |
| 5782 | } |
| 5783 | |
| 5784 | /* OP_IMM_INDEX matcher. */ |
| 5785 | |
| 5786 | static bfd_boolean |
| 5787 | match_imm_index_operand (struct mips_arg_info *arg, |
| 5788 | const struct mips_operand *operand) |
| 5789 | { |
| 5790 | unsigned int max_val; |
| 5791 | |
| 5792 | if (arg->token->type != OT_INTEGER_INDEX) |
| 5793 | return FALSE; |
| 5794 | |
| 5795 | max_val = (1 << operand->size) - 1; |
| 5796 | if (arg->token->u.index > max_val) |
| 5797 | { |
| 5798 | match_out_of_range (arg); |
| 5799 | return FALSE; |
| 5800 | } |
| 5801 | insn_insert_operand (arg->insn, operand, arg->token->u.index); |
| 5802 | ++arg->token; |
| 5803 | return TRUE; |
| 5804 | } |
| 5805 | |
| 5806 | /* OP_REG_INDEX matcher. */ |
| 5807 | |
| 5808 | static bfd_boolean |
| 5809 | match_reg_index_operand (struct mips_arg_info *arg, |
| 5810 | const struct mips_operand *operand) |
| 5811 | { |
| 5812 | unsigned int regno; |
| 5813 | |
| 5814 | if (arg->token->type != OT_REG_INDEX) |
| 5815 | return FALSE; |
| 5816 | |
| 5817 | if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) |
| 5818 | return FALSE; |
| 5819 | |
| 5820 | insn_insert_operand (arg->insn, operand, regno); |
| 5821 | ++arg->token; |
| 5822 | return TRUE; |
| 5823 | } |
| 5824 | |
| 5825 | /* OP_PC matcher. */ |
| 5826 | |
| 5827 | static bfd_boolean |
| 5828 | match_pc_operand (struct mips_arg_info *arg) |
| 5829 | { |
| 5830 | if (arg->token->type == OT_REG && (arg->token->u.regno & RTYPE_PC)) |
| 5831 | { |
| 5832 | ++arg->token; |
| 5833 | return TRUE; |
| 5834 | } |
| 5835 | return FALSE; |
| 5836 | } |
| 5837 | |
| 5838 | /* OP_REG28 matcher. */ |
| 5839 | |
| 5840 | static bfd_boolean |
| 5841 | match_reg28_operand (struct mips_arg_info *arg) |
| 5842 | { |
| 5843 | unsigned int regno; |
| 5844 | |
| 5845 | if (arg->token->type == OT_REG |
| 5846 | && match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no) |
| 5847 | && regno == GP) |
| 5848 | { |
| 5849 | ++arg->token; |
| 5850 | return TRUE; |
| 5851 | } |
| 5852 | return FALSE; |
| 5853 | } |
| 5854 | |
| 5855 | /* OP_NON_ZERO_REG matcher. */ |
| 5856 | |
| 5857 | static bfd_boolean |
| 5858 | match_non_zero_reg_operand (struct mips_arg_info *arg, |
| 5859 | const struct mips_operand *operand) |
| 5860 | { |
| 5861 | unsigned int regno; |
| 5862 | |
| 5863 | if (!match_reg (arg, OP_REG_GP, ®no)) |
| 5864 | return FALSE; |
| 5865 | |
| 5866 | if (regno == 0) |
| 5867 | return FALSE; |
| 5868 | |
| 5869 | arg->last_regno = regno; |
| 5870 | insn_insert_operand (arg->insn, operand, regno); |
| 5871 | return TRUE; |
| 5872 | } |
| 5873 | |
| 5874 | /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the |
| 5875 | register that we need to match. */ |
| 5876 | |
| 5877 | static bfd_boolean |
| 5878 | match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno) |
| 5879 | { |
| 5880 | unsigned int regno; |
| 5881 | |
| 5882 | return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; |
| 5883 | } |
| 5884 | |
| 5885 | /* Read a floating-point constant from S for LI.S or LI.D. LENGTH is |
| 5886 | the length of the value in bytes (4 for float, 8 for double) and |
| 5887 | USING_GPRS says whether the destination is a GPR rather than an FPR. |
| 5888 | |
| 5889 | Return the constant in IMM and OFFSET as follows: |
| 5890 | |
| 5891 | - If the constant should be loaded via memory, set IMM to O_absent and |
| 5892 | OFFSET to the memory address. |
| 5893 | |
| 5894 | - Otherwise, if the constant should be loaded into two 32-bit registers, |
| 5895 | set IMM to the O_constant to load into the high register and OFFSET |
| 5896 | to the corresponding value for the low register. |
| 5897 | |
| 5898 | - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. |
| 5899 | |
| 5900 | These constants only appear as the last operand in an instruction, |
| 5901 | and every instruction that accepts them in any variant accepts them |
| 5902 | in all variants. This means we don't have to worry about backing out |
| 5903 | any changes if the instruction does not match. We just match |
| 5904 | unconditionally and report an error if the constant is invalid. */ |
| 5905 | |
| 5906 | static bfd_boolean |
| 5907 | match_float_constant (struct mips_arg_info *arg, expressionS *imm, |
| 5908 | expressionS *offset, int length, bfd_boolean using_gprs) |
| 5909 | { |
| 5910 | char *p; |
| 5911 | segT seg, new_seg; |
| 5912 | subsegT subseg; |
| 5913 | const char *newname; |
| 5914 | unsigned char *data; |
| 5915 | |
| 5916 | /* Where the constant is placed is based on how the MIPS assembler |
| 5917 | does things: |
| 5918 | |
| 5919 | length == 4 && using_gprs -- immediate value only |
| 5920 | length == 8 && using_gprs -- .rdata or immediate value |
| 5921 | length == 4 && !using_gprs -- .lit4 or immediate value |
| 5922 | length == 8 && !using_gprs -- .lit8 or immediate value |
| 5923 | |
| 5924 | The .lit4 and .lit8 sections are only used if permitted by the |
| 5925 | -G argument. */ |
| 5926 | if (arg->token->type != OT_FLOAT) |
| 5927 | { |
| 5928 | set_insn_error (arg->argnum, _("floating-point expression required")); |
| 5929 | return FALSE; |
| 5930 | } |
| 5931 | |
| 5932 | gas_assert (arg->token->u.flt.length == length); |
| 5933 | data = arg->token->u.flt.data; |
| 5934 | ++arg->token; |
| 5935 | |
| 5936 | /* Handle 32-bit constants for which an immediate value is best. */ |
| 5937 | if (length == 4 |
| 5938 | && (using_gprs |
| 5939 | || g_switch_value < 4 |
| 5940 | || (data[0] == 0 && data[1] == 0) |
| 5941 | || (data[2] == 0 && data[3] == 0))) |
| 5942 | { |
| 5943 | imm->X_op = O_constant; |
| 5944 | if (!target_big_endian) |
| 5945 | imm->X_add_number = bfd_getl32 (data); |
| 5946 | else |
| 5947 | imm->X_add_number = bfd_getb32 (data); |
| 5948 | offset->X_op = O_absent; |
| 5949 | return TRUE; |
| 5950 | } |
| 5951 | |
| 5952 | /* Handle 64-bit constants for which an immediate value is best. */ |
| 5953 | if (length == 8 |
| 5954 | && !mips_disable_float_construction |
| 5955 | /* Constants can only be constructed in GPRs and copied to FPRs if the |
| 5956 | GPRs are at least as wide as the FPRs or MTHC1 is available. |
| 5957 | Unlike most tests for 32-bit floating-point registers this check |
| 5958 | specifically looks for GPR_SIZE == 32 as the FPXX ABI does not |
| 5959 | permit 64-bit moves without MXHC1. |
| 5960 | Force the constant into memory otherwise. */ |
| 5961 | && (using_gprs |
| 5962 | || GPR_SIZE == 64 |
| 5963 | || ISA_HAS_MXHC1 (mips_opts.isa) |
| 5964 | || FPR_SIZE == 32) |
| 5965 | && ((data[0] == 0 && data[1] == 0) |
| 5966 | || (data[2] == 0 && data[3] == 0)) |
| 5967 | && ((data[4] == 0 && data[5] == 0) |
| 5968 | || (data[6] == 0 && data[7] == 0))) |
| 5969 | { |
| 5970 | /* The value is simple enough to load with a couple of instructions. |
| 5971 | If using 32-bit registers, set IMM to the high order 32 bits and |
| 5972 | OFFSET to the low order 32 bits. Otherwise, set IMM to the entire |
| 5973 | 64 bit constant. */ |
| 5974 | if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) |
| 5975 | { |
| 5976 | imm->X_op = O_constant; |
| 5977 | offset->X_op = O_constant; |
| 5978 | if (!target_big_endian) |
| 5979 | { |
| 5980 | imm->X_add_number = bfd_getl32 (data + 4); |
| 5981 | offset->X_add_number = bfd_getl32 (data); |
| 5982 | } |
| 5983 | else |
| 5984 | { |
| 5985 | imm->X_add_number = bfd_getb32 (data); |
| 5986 | offset->X_add_number = bfd_getb32 (data + 4); |
| 5987 | } |
| 5988 | if (offset->X_add_number == 0) |
| 5989 | offset->X_op = O_absent; |
| 5990 | } |
| 5991 | else |
| 5992 | { |
| 5993 | imm->X_op = O_constant; |
| 5994 | if (!target_big_endian) |
| 5995 | imm->X_add_number = bfd_getl64 (data); |
| 5996 | else |
| 5997 | imm->X_add_number = bfd_getb64 (data); |
| 5998 | offset->X_op = O_absent; |
| 5999 | } |
| 6000 | return TRUE; |
| 6001 | } |
| 6002 | |
| 6003 | /* Switch to the right section. */ |
| 6004 | seg = now_seg; |
| 6005 | subseg = now_subseg; |
| 6006 | if (length == 4) |
| 6007 | { |
| 6008 | gas_assert (!using_gprs && g_switch_value >= 4); |
| 6009 | newname = ".lit4"; |
| 6010 | } |
| 6011 | else |
| 6012 | { |
| 6013 | if (using_gprs || g_switch_value < 8) |
| 6014 | newname = RDATA_SECTION_NAME; |
| 6015 | else |
| 6016 | newname = ".lit8"; |
| 6017 | } |
| 6018 | |
| 6019 | new_seg = subseg_new (newname, (subsegT) 0); |
| 6020 | bfd_set_section_flags (stdoutput, new_seg, |
| 6021 | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA); |
| 6022 | frag_align (length == 4 ? 2 : 3, 0, 0); |
| 6023 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
| 6024 | record_alignment (new_seg, 4); |
| 6025 | else |
| 6026 | record_alignment (new_seg, length == 4 ? 2 : 3); |
| 6027 | if (seg == now_seg) |
| 6028 | as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); |
| 6029 | |
| 6030 | /* Set the argument to the current address in the section. */ |
| 6031 | imm->X_op = O_absent; |
| 6032 | offset->X_op = O_symbol; |
| 6033 | offset->X_add_symbol = symbol_temp_new_now (); |
| 6034 | offset->X_add_number = 0; |
| 6035 | |
| 6036 | /* Put the floating point number into the section. */ |
| 6037 | p = frag_more (length); |
| 6038 | memcpy (p, data, length); |
| 6039 | |
| 6040 | /* Switch back to the original section. */ |
| 6041 | subseg_set (seg, subseg); |
| 6042 | return TRUE; |
| 6043 | } |
| 6044 | |
| 6045 | /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between |
| 6046 | them. */ |
| 6047 | |
| 6048 | static bfd_boolean |
| 6049 | match_vu0_suffix_operand (struct mips_arg_info *arg, |
| 6050 | const struct mips_operand *operand, |
| 6051 | bfd_boolean match_p) |
| 6052 | { |
| 6053 | unsigned int uval; |
| 6054 | |
| 6055 | /* The operand can be an XYZW mask or a single 2-bit channel index |
| 6056 | (with X being 0). */ |
| 6057 | gas_assert (operand->size == 2 || operand->size == 4); |
| 6058 | |
| 6059 | /* The suffix can be omitted when it is already part of the opcode. */ |
| 6060 | if (arg->token->type != OT_CHANNELS) |
| 6061 | return match_p; |
| 6062 | |
| 6063 | uval = arg->token->u.channels; |
| 6064 | if (operand->size == 2) |
| 6065 | { |
| 6066 | /* Check that a single bit is set and convert it into a 2-bit index. */ |
| 6067 | if ((uval & -uval) != uval) |
| 6068 | return FALSE; |
| 6069 | uval = 4 - ffs (uval); |
| 6070 | } |
| 6071 | |
| 6072 | if (match_p && insn_extract_operand (arg->insn, operand) != uval) |
| 6073 | return FALSE; |
| 6074 | |
| 6075 | ++arg->token; |
| 6076 | if (!match_p) |
| 6077 | insn_insert_operand (arg->insn, operand, uval); |
| 6078 | return TRUE; |
| 6079 | } |
| 6080 | |
| 6081 | /* S is the text seen for ARG. Match it against OPERAND. Return the end |
| 6082 | of the argument text if the match is successful, otherwise return null. */ |
| 6083 | |
| 6084 | static bfd_boolean |
| 6085 | match_operand (struct mips_arg_info *arg, |
| 6086 | const struct mips_operand *operand) |
| 6087 | { |
| 6088 | switch (operand->type) |
| 6089 | { |
| 6090 | case OP_INT: |
| 6091 | return match_int_operand (arg, operand); |
| 6092 | |
| 6093 | case OP_MAPPED_INT: |
| 6094 | return match_mapped_int_operand (arg, operand); |
| 6095 | |
| 6096 | case OP_MSB: |
| 6097 | return match_msb_operand (arg, operand); |
| 6098 | |
| 6099 | case OP_REG: |
| 6100 | case OP_OPTIONAL_REG: |
| 6101 | return match_reg_operand (arg, operand); |
| 6102 | |
| 6103 | case OP_REG_PAIR: |
| 6104 | return match_reg_pair_operand (arg, operand); |
| 6105 | |
| 6106 | case OP_PCREL: |
| 6107 | return match_pcrel_operand (arg); |
| 6108 | |
| 6109 | case OP_PERF_REG: |
| 6110 | return match_perf_reg_operand (arg, operand); |
| 6111 | |
| 6112 | case OP_ADDIUSP_INT: |
| 6113 | return match_addiusp_operand (arg, operand); |
| 6114 | |
| 6115 | case OP_CLO_CLZ_DEST: |
| 6116 | return match_clo_clz_dest_operand (arg, operand); |
| 6117 | |
| 6118 | case OP_LWM_SWM_LIST: |
| 6119 | return match_lwm_swm_list_operand (arg, operand); |
| 6120 | |
| 6121 | case OP_ENTRY_EXIT_LIST: |
| 6122 | return match_entry_exit_operand (arg, operand); |
| 6123 | |
| 6124 | case OP_SAVE_RESTORE_LIST: |
| 6125 | return match_save_restore_list_operand (arg); |
| 6126 | |
| 6127 | case OP_MDMX_IMM_REG: |
| 6128 | return match_mdmx_imm_reg_operand (arg, operand); |
| 6129 | |
| 6130 | case OP_REPEAT_DEST_REG: |
| 6131 | return match_tied_reg_operand (arg, arg->dest_regno); |
| 6132 | |
| 6133 | case OP_REPEAT_PREV_REG: |
| 6134 | return match_tied_reg_operand (arg, arg->last_regno); |
| 6135 | |
| 6136 | case OP_PC: |
| 6137 | return match_pc_operand (arg); |
| 6138 | |
| 6139 | case OP_REG28: |
| 6140 | return match_reg28_operand (arg); |
| 6141 | |
| 6142 | case OP_VU0_SUFFIX: |
| 6143 | return match_vu0_suffix_operand (arg, operand, FALSE); |
| 6144 | |
| 6145 | case OP_VU0_MATCH_SUFFIX: |
| 6146 | return match_vu0_suffix_operand (arg, operand, TRUE); |
| 6147 | |
| 6148 | case OP_IMM_INDEX: |
| 6149 | return match_imm_index_operand (arg, operand); |
| 6150 | |
| 6151 | case OP_REG_INDEX: |
| 6152 | return match_reg_index_operand (arg, operand); |
| 6153 | |
| 6154 | case OP_SAME_RS_RT: |
| 6155 | return match_same_rs_rt_operand (arg, operand); |
| 6156 | |
| 6157 | case OP_CHECK_PREV: |
| 6158 | return match_check_prev_operand (arg, operand); |
| 6159 | |
| 6160 | case OP_NON_ZERO_REG: |
| 6161 | return match_non_zero_reg_operand (arg, operand); |
| 6162 | } |
| 6163 | abort (); |
| 6164 | } |
| 6165 | |
| 6166 | /* ARG is the state after successfully matching an instruction. |
| 6167 | Issue any queued-up warnings. */ |
| 6168 | |
| 6169 | static void |
| 6170 | check_completed_insn (struct mips_arg_info *arg) |
| 6171 | { |
| 6172 | if (arg->seen_at) |
| 6173 | { |
| 6174 | if (AT == ATREG) |
| 6175 | as_warn (_("used $at without \".set noat\"")); |
| 6176 | else |
| 6177 | as_warn (_("used $%u with \".set at=$%u\""), AT, AT); |
| 6178 | } |
| 6179 | } |
| 6180 | |
| 6181 | /* Return true if modifying general-purpose register REG needs a delay. */ |
| 6182 | |
| 6183 | static bfd_boolean |
| 6184 | reg_needs_delay (unsigned int reg) |
| 6185 | { |
| 6186 | unsigned long prev_pinfo; |
| 6187 | |
| 6188 | prev_pinfo = history[0].insn_mo->pinfo; |
| 6189 | if (!mips_opts.noreorder |
| 6190 | && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) |
| 6191 | || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks)) |
| 6192 | && (gpr_write_mask (&history[0]) & (1 << reg))) |
| 6193 | return TRUE; |
| 6194 | |
| 6195 | return FALSE; |
| 6196 | } |
| 6197 | |
| 6198 | /* Classify an instruction according to the FIX_VR4120_* enumeration. |
| 6199 | Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected |
| 6200 | by VR4120 errata. */ |
| 6201 | |
| 6202 | static unsigned int |
| 6203 | classify_vr4120_insn (const char *name) |
| 6204 | { |
| 6205 | if (strncmp (name, "macc", 4) == 0) |
| 6206 | return FIX_VR4120_MACC; |
| 6207 | if (strncmp (name, "dmacc", 5) == 0) |
| 6208 | return FIX_VR4120_DMACC; |
| 6209 | if (strncmp (name, "mult", 4) == 0) |
| 6210 | return FIX_VR4120_MULT; |
| 6211 | if (strncmp (name, "dmult", 5) == 0) |
| 6212 | return FIX_VR4120_DMULT; |
| 6213 | if (strstr (name, "div")) |
| 6214 | return FIX_VR4120_DIV; |
| 6215 | if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0) |
| 6216 | return FIX_VR4120_MTHILO; |
| 6217 | return NUM_FIX_VR4120_CLASSES; |
| 6218 | } |
| 6219 | |
| 6220 | #define INSN_ERET 0x42000018 |
| 6221 | #define INSN_DERET 0x4200001f |
| 6222 | #define INSN_DMULT 0x1c |
| 6223 | #define INSN_DMULTU 0x1d |
| 6224 | |
| 6225 | /* Return the number of instructions that must separate INSN1 and INSN2, |
| 6226 | where INSN1 is the earlier instruction. Return the worst-case value |
| 6227 | for any INSN2 if INSN2 is null. */ |
| 6228 | |
| 6229 | static unsigned int |
| 6230 | insns_between (const struct mips_cl_insn *insn1, |
| 6231 | const struct mips_cl_insn *insn2) |
| 6232 | { |
| 6233 | unsigned long pinfo1, pinfo2; |
| 6234 | unsigned int mask; |
| 6235 | |
| 6236 | /* If INFO2 is null, pessimistically assume that all flags are set for |
| 6237 | the second instruction. */ |
| 6238 | pinfo1 = insn1->insn_mo->pinfo; |
| 6239 | pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U; |
| 6240 | |
| 6241 | /* For most targets, write-after-read dependencies on the HI and LO |
| 6242 | registers must be separated by at least two instructions. */ |
| 6243 | if (!hilo_interlocks) |
| 6244 | { |
| 6245 | if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO)) |
| 6246 | return 2; |
| 6247 | if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI)) |
| 6248 | return 2; |
| 6249 | } |
| 6250 | |
| 6251 | /* If we're working around r7000 errata, there must be two instructions |
| 6252 | between an mfhi or mflo and any instruction that uses the result. */ |
| 6253 | if (mips_7000_hilo_fix |
| 6254 | && !mips_opts.micromips |
| 6255 | && MF_HILO_INSN (pinfo1) |
| 6256 | && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))) |
| 6257 | return 2; |
| 6258 | |
| 6259 | /* If we're working around 24K errata, one instruction is required |
| 6260 | if an ERET or DERET is followed by a branch instruction. */ |
| 6261 | if (mips_fix_24k && !mips_opts.micromips) |
| 6262 | { |
| 6263 | if (insn1->insn_opcode == INSN_ERET |
| 6264 | || insn1->insn_opcode == INSN_DERET) |
| 6265 | { |
| 6266 | if (insn2 == NULL |
| 6267 | || insn2->insn_opcode == INSN_ERET |
| 6268 | || insn2->insn_opcode == INSN_DERET |
| 6269 | || delayed_branch_p (insn2)) |
| 6270 | return 1; |
| 6271 | } |
| 6272 | } |
| 6273 | |
| 6274 | /* If we're working around PMC RM7000 errata, there must be three |
| 6275 | nops between a dmult and a load instruction. */ |
| 6276 | if (mips_fix_rm7000 && !mips_opts.micromips) |
| 6277 | { |
| 6278 | if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT |
| 6279 | || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) |
| 6280 | { |
| 6281 | if (pinfo2 & INSN_LOAD_MEMORY) |
| 6282 | return 3; |
| 6283 | } |
| 6284 | } |
| 6285 | |
| 6286 | /* If working around VR4120 errata, check for combinations that need |
| 6287 | a single intervening instruction. */ |
| 6288 | if (mips_fix_vr4120 && !mips_opts.micromips) |
| 6289 | { |
| 6290 | unsigned int class1, class2; |
| 6291 | |
| 6292 | class1 = classify_vr4120_insn (insn1->insn_mo->name); |
| 6293 | if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0) |
| 6294 | { |
| 6295 | if (insn2 == NULL) |
| 6296 | return 1; |
| 6297 | class2 = classify_vr4120_insn (insn2->insn_mo->name); |
| 6298 | if (vr4120_conflicts[class1] & (1 << class2)) |
| 6299 | return 1; |
| 6300 | } |
| 6301 | } |
| 6302 | |
| 6303 | if (!HAVE_CODE_COMPRESSION) |
| 6304 | { |
| 6305 | /* Check for GPR or coprocessor load delays. All such delays |
| 6306 | are on the RT register. */ |
| 6307 | /* Itbl support may require additional care here. */ |
| 6308 | if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) |
| 6309 | || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC))) |
| 6310 | { |
| 6311 | if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) |
| 6312 | return 1; |
| 6313 | } |
| 6314 | |
| 6315 | /* Check for generic coprocessor hazards. |
| 6316 | |
| 6317 | This case is not handled very well. There is no special |
| 6318 | knowledge of CP0 handling, and the coprocessors other than |
| 6319 | the floating point unit are not distinguished at all. */ |
| 6320 | /* Itbl support may require additional care here. FIXME! |
| 6321 | Need to modify this to include knowledge about |
| 6322 | user specified delays! */ |
| 6323 | else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE)) |
| 6324 | || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY))) |
| 6325 | { |
| 6326 | /* Handle cases where INSN1 writes to a known general coprocessor |
| 6327 | register. There must be a one instruction delay before INSN2 |
| 6328 | if INSN2 reads that register, otherwise no delay is needed. */ |
| 6329 | mask = fpr_write_mask (insn1); |
| 6330 | if (mask != 0) |
| 6331 | { |
| 6332 | if (!insn2 || (mask & fpr_read_mask (insn2)) != 0) |
| 6333 | return 1; |
| 6334 | } |
| 6335 | else |
| 6336 | { |
| 6337 | /* Read-after-write dependencies on the control registers |
| 6338 | require a two-instruction gap. */ |
| 6339 | if ((pinfo1 & INSN_WRITE_COND_CODE) |
| 6340 | && (pinfo2 & INSN_READ_COND_CODE)) |
| 6341 | return 2; |
| 6342 | |
| 6343 | /* We don't know exactly what INSN1 does. If INSN2 is |
| 6344 | also a coprocessor instruction, assume there must be |
| 6345 | a one instruction gap. */ |
| 6346 | if (pinfo2 & INSN_COP) |
| 6347 | return 1; |
| 6348 | } |
| 6349 | } |
| 6350 | |
| 6351 | /* Check for read-after-write dependencies on the coprocessor |
| 6352 | control registers in cases where INSN1 does not need a general |
| 6353 | coprocessor delay. This means that INSN1 is a floating point |
| 6354 | comparison instruction. */ |
| 6355 | /* Itbl support may require additional care here. */ |
| 6356 | else if (!cop_interlocks |
| 6357 | && (pinfo1 & INSN_WRITE_COND_CODE) |
| 6358 | && (pinfo2 & INSN_READ_COND_CODE)) |
| 6359 | return 1; |
| 6360 | } |
| 6361 | |
| 6362 | /* Forbidden slots can not contain Control Transfer Instructions (CTIs) |
| 6363 | CTIs include all branches and jumps, nal, eret, eretnc, deret, wait |
| 6364 | and pause. */ |
| 6365 | if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) |
| 6366 | && ((pinfo2 & INSN_NO_DELAY_SLOT) |
| 6367 | || (insn2 && delayed_branch_p (insn2)))) |
| 6368 | return 1; |
| 6369 | |
| 6370 | return 0; |
| 6371 | } |
| 6372 | |
| 6373 | /* Return the number of nops that would be needed to work around the |
| 6374 | VR4130 mflo/mfhi errata if instruction INSN immediately followed |
| 6375 | the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards |
| 6376 | that are contained within the first IGNORE instructions of HIST. */ |
| 6377 | |
| 6378 | static int |
| 6379 | nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, |
| 6380 | const struct mips_cl_insn *insn) |
| 6381 | { |
| 6382 | int i, j; |
| 6383 | unsigned int mask; |
| 6384 | |
| 6385 | /* Check if the instruction writes to HI or LO. MTHI and MTLO |
| 6386 | are not affected by the errata. */ |
| 6387 | if (insn != 0 |
| 6388 | && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0 |
| 6389 | || strcmp (insn->insn_mo->name, "mtlo") == 0 |
| 6390 | || strcmp (insn->insn_mo->name, "mthi") == 0)) |
| 6391 | return 0; |
| 6392 | |
| 6393 | /* Search for the first MFLO or MFHI. */ |
| 6394 | for (i = 0; i < MAX_VR4130_NOPS; i++) |
| 6395 | if (MF_HILO_INSN (hist[i].insn_mo->pinfo)) |
| 6396 | { |
| 6397 | /* Extract the destination register. */ |
| 6398 | mask = gpr_write_mask (&hist[i]); |
| 6399 | |
| 6400 | /* No nops are needed if INSN reads that register. */ |
| 6401 | if (insn != NULL && (gpr_read_mask (insn) & mask) != 0) |
| 6402 | return 0; |
| 6403 | |
| 6404 | /* ...or if any of the intervening instructions do. */ |
| 6405 | for (j = 0; j < i; j++) |
| 6406 | if (gpr_read_mask (&hist[j]) & mask) |
| 6407 | return 0; |
| 6408 | |
| 6409 | if (i >= ignore) |
| 6410 | return MAX_VR4130_NOPS - i; |
| 6411 | } |
| 6412 | return 0; |
| 6413 | } |
| 6414 | |
| 6415 | #define BASE_REG_EQ(INSN1, INSN2) \ |
| 6416 | ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ |
| 6417 | == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) |
| 6418 | |
| 6419 | /* Return the minimum alignment for this store instruction. */ |
| 6420 | |
| 6421 | static int |
| 6422 | fix_24k_align_to (const struct mips_opcode *mo) |
| 6423 | { |
| 6424 | if (strcmp (mo->name, "sh") == 0) |
| 6425 | return 2; |
| 6426 | |
| 6427 | if (strcmp (mo->name, "swc1") == 0 |
| 6428 | || strcmp (mo->name, "swc2") == 0 |
| 6429 | || strcmp (mo->name, "sw") == 0 |
| 6430 | || strcmp (mo->name, "sc") == 0 |
| 6431 | || strcmp (mo->name, "s.s") == 0) |
| 6432 | return 4; |
| 6433 | |
| 6434 | if (strcmp (mo->name, "sdc1") == 0 |
| 6435 | || strcmp (mo->name, "sdc2") == 0 |
| 6436 | || strcmp (mo->name, "s.d") == 0) |
| 6437 | return 8; |
| 6438 | |
| 6439 | /* sb, swl, swr */ |
| 6440 | return 1; |
| 6441 | } |
| 6442 | |
| 6443 | struct fix_24k_store_info |
| 6444 | { |
| 6445 | /* Immediate offset, if any, for this store instruction. */ |
| 6446 | short off; |
| 6447 | /* Alignment required by this store instruction. */ |
| 6448 | int align_to; |
| 6449 | /* True for register offsets. */ |
| 6450 | int register_offset; |
| 6451 | }; |
| 6452 | |
| 6453 | /* Comparison function used by qsort. */ |
| 6454 | |
| 6455 | static int |
| 6456 | fix_24k_sort (const void *a, const void *b) |
| 6457 | { |
| 6458 | const struct fix_24k_store_info *pos1 = a; |
| 6459 | const struct fix_24k_store_info *pos2 = b; |
| 6460 | |
| 6461 | return (pos1->off - pos2->off); |
| 6462 | } |
| 6463 | |
| 6464 | /* INSN is a store instruction. Try to record the store information |
| 6465 | in STINFO. Return false if the information isn't known. */ |
| 6466 | |
| 6467 | static bfd_boolean |
| 6468 | fix_24k_record_store_info (struct fix_24k_store_info *stinfo, |
| 6469 | const struct mips_cl_insn *insn) |
| 6470 | { |
| 6471 | /* The instruction must have a known offset. */ |
| 6472 | if (!insn->complete_p || !strstr (insn->insn_mo->args, "o(")) |
| 6473 | return FALSE; |
| 6474 | |
| 6475 | stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE; |
| 6476 | stinfo->align_to = fix_24k_align_to (insn->insn_mo); |
| 6477 | return TRUE; |
| 6478 | } |
| 6479 | |
| 6480 | /* Return the number of nops that would be needed to work around the 24k |
| 6481 | "lost data on stores during refill" errata if instruction INSN |
| 6482 | immediately followed the 2 instructions described by HIST. |
| 6483 | Ignore hazards that are contained within the first IGNORE |
| 6484 | instructions of HIST. |
| 6485 | |
| 6486 | Problem: The FSB (fetch store buffer) acts as an intermediate buffer |
| 6487 | for the data cache refills and store data. The following describes |
| 6488 | the scenario where the store data could be lost. |
| 6489 | |
| 6490 | * A data cache miss, due to either a load or a store, causing fill |
| 6491 | data to be supplied by the memory subsystem |
| 6492 | * The first three doublewords of fill data are returned and written |
| 6493 | into the cache |
| 6494 | * A sequence of four stores occurs in consecutive cycles around the |
| 6495 | final doubleword of the fill: |
| 6496 | * Store A |
| 6497 | * Store B |
| 6498 | * Store C |
| 6499 | * Zero, One or more instructions |
| 6500 | * Store D |
| 6501 | |
| 6502 | The four stores A-D must be to different doublewords of the line that |
| 6503 | is being filled. The fourth instruction in the sequence above permits |
| 6504 | the fill of the final doubleword to be transferred from the FSB into |
| 6505 | the cache. In the sequence above, the stores may be either integer |
| 6506 | (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2, |
| 6507 | swxc1, sdxc1, suxc1) stores, as long as the four stores are to |
| 6508 | different doublewords on the line. If the floating point unit is |
| 6509 | running in 1:2 mode, it is not possible to create the sequence above |
| 6510 | using only floating point store instructions. |
| 6511 | |
| 6512 | In this case, the cache line being filled is incorrectly marked |
| 6513 | invalid, thereby losing the data from any store to the line that |
| 6514 | occurs between the original miss and the completion of the five |
| 6515 | cycle sequence shown above. |
| 6516 | |
| 6517 | The workarounds are: |
| 6518 | |
| 6519 | * Run the data cache in write-through mode. |
| 6520 | * Insert a non-store instruction between |
| 6521 | Store A and Store B or Store B and Store C. */ |
| 6522 | |
| 6523 | static int |
| 6524 | nops_for_24k (int ignore, const struct mips_cl_insn *hist, |
| 6525 | const struct mips_cl_insn *insn) |
| 6526 | { |
| 6527 | struct fix_24k_store_info pos[3]; |
| 6528 | int align, i, base_offset; |
| 6529 | |
| 6530 | if (ignore >= 2) |
| 6531 | return 0; |
| 6532 | |
| 6533 | /* If the previous instruction wasn't a store, there's nothing to |
| 6534 | worry about. */ |
| 6535 | if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
| 6536 | return 0; |
| 6537 | |
| 6538 | /* If the instructions after the previous one are unknown, we have |
| 6539 | to assume the worst. */ |
| 6540 | if (!insn) |
| 6541 | return 1; |
| 6542 | |
| 6543 | /* Check whether we are dealing with three consecutive stores. */ |
| 6544 | if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0 |
| 6545 | || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0) |
| 6546 | return 0; |
| 6547 | |
| 6548 | /* If we don't know the relationship between the store addresses, |
| 6549 | assume the worst. */ |
| 6550 | if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode) |
| 6551 | || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode)) |
| 6552 | return 1; |
| 6553 | |
| 6554 | if (!fix_24k_record_store_info (&pos[0], insn) |
| 6555 | || !fix_24k_record_store_info (&pos[1], &hist[0]) |
| 6556 | || !fix_24k_record_store_info (&pos[2], &hist[1])) |
| 6557 | return 1; |
| 6558 | |
| 6559 | qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort); |
| 6560 | |
| 6561 | /* Pick a value of ALIGN and X such that all offsets are adjusted by |
| 6562 | X bytes and such that the base register + X is known to be aligned |
| 6563 | to align bytes. */ |
| 6564 | |
| 6565 | if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP) |
| 6566 | align = 8; |
| 6567 | else |
| 6568 | { |
| 6569 | align = pos[0].align_to; |
| 6570 | base_offset = pos[0].off; |
| 6571 | for (i = 1; i < 3; i++) |
| 6572 | if (align < pos[i].align_to) |
| 6573 | { |
| 6574 | align = pos[i].align_to; |
| 6575 | base_offset = pos[i].off; |
| 6576 | } |
| 6577 | for (i = 0; i < 3; i++) |
| 6578 | pos[i].off -= base_offset; |
| 6579 | } |
| 6580 | |
| 6581 | pos[0].off &= ~align + 1; |
| 6582 | pos[1].off &= ~align + 1; |
| 6583 | pos[2].off &= ~align + 1; |
| 6584 | |
| 6585 | /* If any two stores write to the same chunk, they also write to the |
| 6586 | same doubleword. The offsets are still sorted at this point. */ |
| 6587 | if (pos[0].off == pos[1].off || pos[1].off == pos[2].off) |
| 6588 | return 0; |
| 6589 | |
| 6590 | /* A range of at least 9 bytes is needed for the stores to be in |
| 6591 | non-overlapping doublewords. */ |
| 6592 | if (pos[2].off - pos[0].off <= 8) |
| 6593 | return 0; |
| 6594 | |
| 6595 | if (pos[2].off - pos[1].off >= 24 |
| 6596 | || pos[1].off - pos[0].off >= 24 |
| 6597 | || pos[2].off - pos[0].off >= 32) |
| 6598 | return 0; |
| 6599 | |
| 6600 | return 1; |
| 6601 | } |
| 6602 | |
| 6603 | /* Return the number of nops that would be needed if instruction INSN |
| 6604 | immediately followed the MAX_NOPS instructions given by HIST, |
| 6605 | where HIST[0] is the most recent instruction. Ignore hazards |
| 6606 | between INSN and the first IGNORE instructions in HIST. |
| 6607 | |
| 6608 | If INSN is null, return the worse-case number of nops for any |
| 6609 | instruction. */ |
| 6610 | |
| 6611 | static int |
| 6612 | nops_for_insn (int ignore, const struct mips_cl_insn *hist, |
| 6613 | const struct mips_cl_insn *insn) |
| 6614 | { |
| 6615 | int i, nops, tmp_nops; |
| 6616 | |
| 6617 | nops = 0; |
| 6618 | for (i = ignore; i < MAX_DELAY_NOPS; i++) |
| 6619 | { |
| 6620 | tmp_nops = insns_between (hist + i, insn) - i; |
| 6621 | if (tmp_nops > nops) |
| 6622 | nops = tmp_nops; |
| 6623 | } |
| 6624 | |
| 6625 | if (mips_fix_vr4130 && !mips_opts.micromips) |
| 6626 | { |
| 6627 | tmp_nops = nops_for_vr4130 (ignore, hist, insn); |
| 6628 | if (tmp_nops > nops) |
| 6629 | nops = tmp_nops; |
| 6630 | } |
| 6631 | |
| 6632 | if (mips_fix_24k && !mips_opts.micromips) |
| 6633 | { |
| 6634 | tmp_nops = nops_for_24k (ignore, hist, insn); |
| 6635 | if (tmp_nops > nops) |
| 6636 | nops = tmp_nops; |
| 6637 | } |
| 6638 | |
| 6639 | return nops; |
| 6640 | } |
| 6641 | |
| 6642 | /* The variable arguments provide NUM_INSNS extra instructions that |
| 6643 | might be added to HIST. Return the largest number of nops that |
| 6644 | would be needed after the extended sequence, ignoring hazards |
| 6645 | in the first IGNORE instructions. */ |
| 6646 | |
| 6647 | static int |
| 6648 | nops_for_sequence (int num_insns, int ignore, |
| 6649 | const struct mips_cl_insn *hist, ...) |
| 6650 | { |
| 6651 | va_list args; |
| 6652 | struct mips_cl_insn buffer[MAX_NOPS]; |
| 6653 | struct mips_cl_insn *cursor; |
| 6654 | int nops; |
| 6655 | |
| 6656 | va_start (args, hist); |
| 6657 | cursor = buffer + num_insns; |
| 6658 | memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor)); |
| 6659 | while (cursor > buffer) |
| 6660 | *--cursor = *va_arg (args, const struct mips_cl_insn *); |
| 6661 | |
| 6662 | nops = nops_for_insn (ignore, buffer, NULL); |
| 6663 | va_end (args); |
| 6664 | return nops; |
| 6665 | } |
| 6666 | |
| 6667 | /* Like nops_for_insn, but if INSN is a branch, take into account the |
| 6668 | worst-case delay for the branch target. */ |
| 6669 | |
| 6670 | static int |
| 6671 | nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist, |
| 6672 | const struct mips_cl_insn *insn) |
| 6673 | { |
| 6674 | int nops, tmp_nops; |
| 6675 | |
| 6676 | nops = nops_for_insn (ignore, hist, insn); |
| 6677 | if (delayed_branch_p (insn)) |
| 6678 | { |
| 6679 | tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0, |
| 6680 | hist, insn, get_delay_slot_nop (insn)); |
| 6681 | if (tmp_nops > nops) |
| 6682 | nops = tmp_nops; |
| 6683 | } |
| 6684 | else if (compact_branch_p (insn)) |
| 6685 | { |
| 6686 | tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn); |
| 6687 | if (tmp_nops > nops) |
| 6688 | nops = tmp_nops; |
| 6689 | } |
| 6690 | return nops; |
| 6691 | } |
| 6692 | |
| 6693 | /* Fix NOP issue: Replace nops by "or at,at,zero". */ |
| 6694 | |
| 6695 | static void |
| 6696 | fix_loongson2f_nop (struct mips_cl_insn * ip) |
| 6697 | { |
| 6698 | gas_assert (!HAVE_CODE_COMPRESSION); |
| 6699 | if (strcmp (ip->insn_mo->name, "nop") == 0) |
| 6700 | ip->insn_opcode = LOONGSON2F_NOP_INSN; |
| 6701 | } |
| 6702 | |
| 6703 | /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region |
| 6704 | jr target pc &= 'hffff_ffff_cfff_ffff. */ |
| 6705 | |
| 6706 | static void |
| 6707 | fix_loongson2f_jump (struct mips_cl_insn * ip) |
| 6708 | { |
| 6709 | gas_assert (!HAVE_CODE_COMPRESSION); |
| 6710 | if (strcmp (ip->insn_mo->name, "j") == 0 |
| 6711 | || strcmp (ip->insn_mo->name, "jr") == 0 |
| 6712 | || strcmp (ip->insn_mo->name, "jalr") == 0) |
| 6713 | { |
| 6714 | int sreg; |
| 6715 | expressionS ep; |
| 6716 | |
| 6717 | if (! mips_opts.at) |
| 6718 | return; |
| 6719 | |
| 6720 | sreg = EXTRACT_OPERAND (0, RS, *ip); |
| 6721 | if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG) |
| 6722 | return; |
| 6723 | |
| 6724 | ep.X_op = O_constant; |
| 6725 | ep.X_add_number = 0xcfff0000; |
| 6726 | macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16); |
| 6727 | ep.X_add_number = 0xffff; |
| 6728 | macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16); |
| 6729 | macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG); |
| 6730 | } |
| 6731 | } |
| 6732 | |
| 6733 | static void |
| 6734 | fix_loongson2f (struct mips_cl_insn * ip) |
| 6735 | { |
| 6736 | if (mips_fix_loongson2f_nop) |
| 6737 | fix_loongson2f_nop (ip); |
| 6738 | |
| 6739 | if (mips_fix_loongson2f_jump) |
| 6740 | fix_loongson2f_jump (ip); |
| 6741 | } |
| 6742 | |
| 6743 | /* IP is a branch that has a delay slot, and we need to fill it |
| 6744 | automatically. Return true if we can do that by swapping IP |
| 6745 | with the previous instruction. |
| 6746 | ADDRESS_EXPR is an operand of the instruction to be used with |
| 6747 | RELOC_TYPE. */ |
| 6748 | |
| 6749 | static bfd_boolean |
| 6750 | can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, |
| 6751 | bfd_reloc_code_real_type *reloc_type) |
| 6752 | { |
| 6753 | unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; |
| 6754 | unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; |
| 6755 | unsigned int fpr_read, prev_fpr_write; |
| 6756 | |
| 6757 | /* -O2 and above is required for this optimization. */ |
| 6758 | if (mips_optimize < 2) |
| 6759 | return FALSE; |
| 6760 | |
| 6761 | /* If we have seen .set volatile or .set nomove, don't optimize. */ |
| 6762 | if (mips_opts.nomove) |
| 6763 | return FALSE; |
| 6764 | |
| 6765 | /* We can't swap if the previous instruction's position is fixed. */ |
| 6766 | if (history[0].fixed_p) |
| 6767 | return FALSE; |
| 6768 | |
| 6769 | /* If the previous previous insn was in a .set noreorder, we can't |
| 6770 | swap. Actually, the MIPS assembler will swap in this situation. |
| 6771 | However, gcc configured -with-gnu-as will generate code like |
| 6772 | |
| 6773 | .set noreorder |
| 6774 | lw $4,XXX |
| 6775 | .set reorder |
| 6776 | INSN |
| 6777 | bne $4,$0,foo |
| 6778 | |
| 6779 | in which we can not swap the bne and INSN. If gcc is not configured |
| 6780 | -with-gnu-as, it does not output the .set pseudo-ops. */ |
| 6781 | if (history[1].noreorder_p) |
| 6782 | return FALSE; |
| 6783 | |
| 6784 | /* If the previous instruction had a fixup in mips16 mode, we can not swap. |
| 6785 | This means that the previous instruction was a 4-byte one anyhow. */ |
| 6786 | if (mips_opts.mips16 && history[0].fixp[0]) |
| 6787 | return FALSE; |
| 6788 | |
| 6789 | /* If the branch is itself the target of a branch, we can not swap. |
| 6790 | We cheat on this; all we check for is whether there is a label on |
| 6791 | this instruction. If there are any branches to anything other than |
| 6792 | a label, users must use .set noreorder. */ |
| 6793 | if (seg_info (now_seg)->label_list) |
| 6794 | return FALSE; |
| 6795 | |
| 6796 | /* If the previous instruction is in a variant frag other than this |
| 6797 | branch's one, we cannot do the swap. This does not apply to |
| 6798 | MIPS16 code, which uses variant frags for different purposes. */ |
| 6799 | if (!mips_opts.mips16 |
| 6800 | && history[0].frag |
| 6801 | && history[0].frag->fr_type == rs_machine_dependent) |
| 6802 | return FALSE; |
| 6803 | |
| 6804 | /* We do not swap with instructions that cannot architecturally |
| 6805 | be placed in a branch delay slot, such as SYNC or ERET. We |
| 6806 | also refrain from swapping with a trap instruction, since it |
| 6807 | complicates trap handlers to have the trap instruction be in |
| 6808 | a delay slot. */ |
| 6809 | prev_pinfo = history[0].insn_mo->pinfo; |
| 6810 | if (prev_pinfo & INSN_NO_DELAY_SLOT) |
| 6811 | return FALSE; |
| 6812 | |
| 6813 | /* Check for conflicts between the branch and the instructions |
| 6814 | before the candidate delay slot. */ |
| 6815 | if (nops_for_insn (0, history + 1, ip) > 0) |
| 6816 | return FALSE; |
| 6817 | |
| 6818 | /* Check for conflicts between the swapped sequence and the |
| 6819 | target of the branch. */ |
| 6820 | if (nops_for_sequence (2, 0, history + 1, ip, history) > 0) |
| 6821 | return FALSE; |
| 6822 | |
| 6823 | /* If the branch reads a register that the previous |
| 6824 | instruction sets, we can not swap. */ |
| 6825 | gpr_read = gpr_read_mask (ip); |
| 6826 | prev_gpr_write = gpr_write_mask (&history[0]); |
| 6827 | if (gpr_read & prev_gpr_write) |
| 6828 | return FALSE; |
| 6829 | |
| 6830 | fpr_read = fpr_read_mask (ip); |
| 6831 | prev_fpr_write = fpr_write_mask (&history[0]); |
| 6832 | if (fpr_read & prev_fpr_write) |
| 6833 | return FALSE; |
| 6834 | |
| 6835 | /* If the branch writes a register that the previous |
| 6836 | instruction sets, we can not swap. */ |
| 6837 | gpr_write = gpr_write_mask (ip); |
| 6838 | if (gpr_write & prev_gpr_write) |
| 6839 | return FALSE; |
| 6840 | |
| 6841 | /* If the branch writes a register that the previous |
| 6842 | instruction reads, we can not swap. */ |
| 6843 | prev_gpr_read = gpr_read_mask (&history[0]); |
| 6844 | if (gpr_write & prev_gpr_read) |
| 6845 | return FALSE; |
| 6846 | |
| 6847 | /* If one instruction sets a condition code and the |
| 6848 | other one uses a condition code, we can not swap. */ |
| 6849 | pinfo = ip->insn_mo->pinfo; |
| 6850 | if ((pinfo & INSN_READ_COND_CODE) |
| 6851 | && (prev_pinfo & INSN_WRITE_COND_CODE)) |
| 6852 | return FALSE; |
| 6853 | if ((pinfo & INSN_WRITE_COND_CODE) |
| 6854 | && (prev_pinfo & INSN_READ_COND_CODE)) |
| 6855 | return FALSE; |
| 6856 | |
| 6857 | /* If the previous instruction uses the PC, we can not swap. */ |
| 6858 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
| 6859 | if (prev_pinfo2 & INSN2_READ_PC) |
| 6860 | return FALSE; |
| 6861 | |
| 6862 | /* If the previous instruction has an incorrect size for a fixed |
| 6863 | branch delay slot in microMIPS mode, we cannot swap. */ |
| 6864 | pinfo2 = ip->insn_mo->pinfo2; |
| 6865 | if (mips_opts.micromips |
| 6866 | && (pinfo2 & INSN2_BRANCH_DELAY_16BIT) |
| 6867 | && insn_length (history) != 2) |
| 6868 | return FALSE; |
| 6869 | if (mips_opts.micromips |
| 6870 | && (pinfo2 & INSN2_BRANCH_DELAY_32BIT) |
| 6871 | && insn_length (history) != 4) |
| 6872 | return FALSE; |
| 6873 | |
| 6874 | /* On R5900 short loops need to be fixed by inserting a nop in |
| 6875 | the branch delay slots. |
| 6876 | A short loop can be terminated too early. */ |
| 6877 | if (mips_opts.arch == CPU_R5900 |
| 6878 | /* Check if instruction has a parameter, ignore "j $31". */ |
| 6879 | && (address_expr != NULL) |
| 6880 | /* Parameter must be 16 bit. */ |
| 6881 | && (*reloc_type == BFD_RELOC_16_PCREL_S2) |
| 6882 | /* Branch to same segment. */ |
| 6883 | && (S_GET_SEGMENT (address_expr->X_add_symbol) == now_seg) |
| 6884 | /* Branch to same code fragment. */ |
| 6885 | && (symbol_get_frag (address_expr->X_add_symbol) == frag_now) |
| 6886 | /* Can only calculate branch offset if value is known. */ |
| 6887 | && symbol_constant_p (address_expr->X_add_symbol) |
| 6888 | /* Check if branch is really conditional. */ |
| 6889 | && !((ip->insn_opcode & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
| 6890 | || (ip->insn_opcode & 0xffff0000) == 0x04010000 /* bgez $0 */ |
| 6891 | || (ip->insn_opcode & 0xffff0000) == 0x04110000)) /* bgezal $0 */ |
| 6892 | { |
| 6893 | int distance; |
| 6894 | /* Check if loop is shorter than 6 instructions including |
| 6895 | branch and delay slot. */ |
| 6896 | distance = frag_now_fix () - S_GET_VALUE (address_expr->X_add_symbol); |
| 6897 | if (distance <= 20) |
| 6898 | { |
| 6899 | int i; |
| 6900 | int rv; |
| 6901 | |
| 6902 | rv = FALSE; |
| 6903 | /* When the loop includes branches or jumps, |
| 6904 | it is not a short loop. */ |
| 6905 | for (i = 0; i < (distance / 4); i++) |
| 6906 | { |
| 6907 | if ((history[i].cleared_p) |
| 6908 | || delayed_branch_p (&history[i])) |
| 6909 | { |
| 6910 | rv = TRUE; |
| 6911 | break; |
| 6912 | } |
| 6913 | } |
| 6914 | if (!rv) |
| 6915 | { |
| 6916 | /* Insert nop after branch to fix short loop. */ |
| 6917 | return FALSE; |
| 6918 | } |
| 6919 | } |
| 6920 | } |
| 6921 | |
| 6922 | return TRUE; |
| 6923 | } |
| 6924 | |
| 6925 | /* Decide how we should add IP to the instruction stream. |
| 6926 | ADDRESS_EXPR is an operand of the instruction to be used with |
| 6927 | RELOC_TYPE. */ |
| 6928 | |
| 6929 | static enum append_method |
| 6930 | get_append_method (struct mips_cl_insn *ip, expressionS *address_expr, |
| 6931 | bfd_reloc_code_real_type *reloc_type) |
| 6932 | { |
| 6933 | /* The relaxed version of a macro sequence must be inherently |
| 6934 | hazard-free. */ |
| 6935 | if (mips_relax.sequence == 2) |
| 6936 | return APPEND_ADD; |
| 6937 | |
| 6938 | /* We must not dabble with instructions in a ".set noreorder" block. */ |
| 6939 | if (mips_opts.noreorder) |
| 6940 | return APPEND_ADD; |
| 6941 | |
| 6942 | /* Otherwise, it's our responsibility to fill branch delay slots. */ |
| 6943 | if (delayed_branch_p (ip)) |
| 6944 | { |
| 6945 | if (!branch_likely_p (ip) |
| 6946 | && can_swap_branch_p (ip, address_expr, reloc_type)) |
| 6947 | return APPEND_SWAP; |
| 6948 | |
| 6949 | if (mips_opts.mips16 |
| 6950 | && ISA_SUPPORTS_MIPS16E |
| 6951 | && gpr_read_mask (ip) != 0) |
| 6952 | return APPEND_ADD_COMPACT; |
| 6953 | |
| 6954 | if (mips_opts.micromips |
| 6955 | && ((ip->insn_opcode & 0xffe0) == 0x4580 |
| 6956 | || (!forced_insn_length |
| 6957 | && ((ip->insn_opcode & 0xfc00) == 0xcc00 |
| 6958 | || (ip->insn_opcode & 0xdc00) == 0x8c00)) |
| 6959 | || (ip->insn_opcode & 0xdfe00000) == 0x94000000 |
| 6960 | || (ip->insn_opcode & 0xdc1f0000) == 0x94000000)) |
| 6961 | return APPEND_ADD_COMPACT; |
| 6962 | |
| 6963 | return APPEND_ADD_WITH_NOP; |
| 6964 | } |
| 6965 | |
| 6966 | return APPEND_ADD; |
| 6967 | } |
| 6968 | |
| 6969 | /* IP is an instruction whose opcode we have just changed, END points |
| 6970 | to the end of the opcode table processed. Point IP->insn_mo to the |
| 6971 | new opcode's definition. */ |
| 6972 | |
| 6973 | static void |
| 6974 | find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end) |
| 6975 | { |
| 6976 | const struct mips_opcode *mo; |
| 6977 | |
| 6978 | for (mo = ip->insn_mo; mo < end; mo++) |
| 6979 | if (mo->pinfo != INSN_MACRO |
| 6980 | && (ip->insn_opcode & mo->mask) == mo->match) |
| 6981 | { |
| 6982 | ip->insn_mo = mo; |
| 6983 | return; |
| 6984 | } |
| 6985 | abort (); |
| 6986 | } |
| 6987 | |
| 6988 | /* IP is a MIPS16 instruction whose opcode we have just changed. |
| 6989 | Point IP->insn_mo to the new opcode's definition. */ |
| 6990 | |
| 6991 | static void |
| 6992 | find_altered_mips16_opcode (struct mips_cl_insn *ip) |
| 6993 | { |
| 6994 | find_altered_opcode (ip, &mips16_opcodes[bfd_mips16_num_opcodes]); |
| 6995 | } |
| 6996 | |
| 6997 | /* IP is a microMIPS instruction whose opcode we have just changed. |
| 6998 | Point IP->insn_mo to the new opcode's definition. */ |
| 6999 | |
| 7000 | static void |
| 7001 | find_altered_micromips_opcode (struct mips_cl_insn *ip) |
| 7002 | { |
| 7003 | find_altered_opcode (ip, µmips_opcodes[bfd_micromips_num_opcodes]); |
| 7004 | } |
| 7005 | |
| 7006 | /* For microMIPS macros, we need to generate a local number label |
| 7007 | as the target of branches. */ |
| 7008 | #define MICROMIPS_LABEL_CHAR '\037' |
| 7009 | static unsigned long micromips_target_label; |
| 7010 | static char micromips_target_name[32]; |
| 7011 | |
| 7012 | static char * |
| 7013 | micromips_label_name (void) |
| 7014 | { |
| 7015 | char *p = micromips_target_name; |
| 7016 | char symbol_name_temporary[24]; |
| 7017 | unsigned long l; |
| 7018 | int i; |
| 7019 | |
| 7020 | if (*p) |
| 7021 | return p; |
| 7022 | |
| 7023 | i = 0; |
| 7024 | l = micromips_target_label; |
| 7025 | #ifdef LOCAL_LABEL_PREFIX |
| 7026 | *p++ = LOCAL_LABEL_PREFIX; |
| 7027 | #endif |
| 7028 | *p++ = 'L'; |
| 7029 | *p++ = MICROMIPS_LABEL_CHAR; |
| 7030 | do |
| 7031 | { |
| 7032 | symbol_name_temporary[i++] = l % 10 + '0'; |
| 7033 | l /= 10; |
| 7034 | } |
| 7035 | while (l != 0); |
| 7036 | while (i > 0) |
| 7037 | *p++ = symbol_name_temporary[--i]; |
| 7038 | *p = '\0'; |
| 7039 | |
| 7040 | return micromips_target_name; |
| 7041 | } |
| 7042 | |
| 7043 | static void |
| 7044 | micromips_label_expr (expressionS *label_expr) |
| 7045 | { |
| 7046 | label_expr->X_op = O_symbol; |
| 7047 | label_expr->X_add_symbol = symbol_find_or_make (micromips_label_name ()); |
| 7048 | label_expr->X_add_number = 0; |
| 7049 | } |
| 7050 | |
| 7051 | static void |
| 7052 | micromips_label_inc (void) |
| 7053 | { |
| 7054 | micromips_target_label++; |
| 7055 | *micromips_target_name = '\0'; |
| 7056 | } |
| 7057 | |
| 7058 | static void |
| 7059 | micromips_add_label (void) |
| 7060 | { |
| 7061 | symbolS *s; |
| 7062 | |
| 7063 | s = colon (micromips_label_name ()); |
| 7064 | micromips_label_inc (); |
| 7065 | S_SET_OTHER (s, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s))); |
| 7066 | } |
| 7067 | |
| 7068 | /* If assembling microMIPS code, then return the microMIPS reloc |
| 7069 | corresponding to the requested one if any. Otherwise return |
| 7070 | the reloc unchanged. */ |
| 7071 | |
| 7072 | static bfd_reloc_code_real_type |
| 7073 | micromips_map_reloc (bfd_reloc_code_real_type reloc) |
| 7074 | { |
| 7075 | static const bfd_reloc_code_real_type relocs[][2] = |
| 7076 | { |
| 7077 | /* Keep sorted incrementally by the left-hand key. */ |
| 7078 | { BFD_RELOC_16_PCREL_S2, BFD_RELOC_MICROMIPS_16_PCREL_S1 }, |
| 7079 | { BFD_RELOC_GPREL16, BFD_RELOC_MICROMIPS_GPREL16 }, |
| 7080 | { BFD_RELOC_MIPS_JMP, BFD_RELOC_MICROMIPS_JMP }, |
| 7081 | { BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 }, |
| 7082 | { BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S }, |
| 7083 | { BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 }, |
| 7084 | { BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL }, |
| 7085 | { BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 }, |
| 7086 | { BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 }, |
| 7087 | { BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 }, |
| 7088 | { BFD_RELOC_MIPS_GOT_LO16, BFD_RELOC_MICROMIPS_GOT_LO16 }, |
| 7089 | { BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MICROMIPS_CALL_HI16 }, |
| 7090 | { BFD_RELOC_MIPS_CALL_LO16, BFD_RELOC_MICROMIPS_CALL_LO16 }, |
| 7091 | { BFD_RELOC_MIPS_SUB, BFD_RELOC_MICROMIPS_SUB }, |
| 7092 | { BFD_RELOC_MIPS_GOT_PAGE, BFD_RELOC_MICROMIPS_GOT_PAGE }, |
| 7093 | { BFD_RELOC_MIPS_GOT_OFST, BFD_RELOC_MICROMIPS_GOT_OFST }, |
| 7094 | { BFD_RELOC_MIPS_GOT_DISP, BFD_RELOC_MICROMIPS_GOT_DISP }, |
| 7095 | { BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MICROMIPS_HIGHEST }, |
| 7096 | { BFD_RELOC_MIPS_HIGHER, BFD_RELOC_MICROMIPS_HIGHER }, |
| 7097 | { BFD_RELOC_MIPS_SCN_DISP, BFD_RELOC_MICROMIPS_SCN_DISP }, |
| 7098 | { BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MICROMIPS_TLS_GD }, |
| 7099 | { BFD_RELOC_MIPS_TLS_LDM, BFD_RELOC_MICROMIPS_TLS_LDM }, |
| 7100 | { BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 }, |
| 7101 | { BFD_RELOC_MIPS_TLS_DTPREL_LO16, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 }, |
| 7102 | { BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MICROMIPS_TLS_GOTTPREL }, |
| 7103 | { BFD_RELOC_MIPS_TLS_TPREL_HI16, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 }, |
| 7104 | { BFD_RELOC_MIPS_TLS_TPREL_LO16, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 } |
| 7105 | }; |
| 7106 | bfd_reloc_code_real_type r; |
| 7107 | size_t i; |
| 7108 | |
| 7109 | if (!mips_opts.micromips) |
| 7110 | return reloc; |
| 7111 | for (i = 0; i < ARRAY_SIZE (relocs); i++) |
| 7112 | { |
| 7113 | r = relocs[i][0]; |
| 7114 | if (r > reloc) |
| 7115 | return reloc; |
| 7116 | if (r == reloc) |
| 7117 | return relocs[i][1]; |
| 7118 | } |
| 7119 | return reloc; |
| 7120 | } |
| 7121 | |
| 7122 | /* Try to resolve relocation RELOC against constant OPERAND at assembly time. |
| 7123 | Return true on success, storing the resolved value in RESULT. */ |
| 7124 | |
| 7125 | static bfd_boolean |
| 7126 | calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand, |
| 7127 | offsetT *result) |
| 7128 | { |
| 7129 | switch (reloc) |
| 7130 | { |
| 7131 | case BFD_RELOC_MIPS_HIGHEST: |
| 7132 | case BFD_RELOC_MICROMIPS_HIGHEST: |
| 7133 | *result = ((operand + 0x800080008000ull) >> 48) & 0xffff; |
| 7134 | return TRUE; |
| 7135 | |
| 7136 | case BFD_RELOC_MIPS_HIGHER: |
| 7137 | case BFD_RELOC_MICROMIPS_HIGHER: |
| 7138 | *result = ((operand + 0x80008000ull) >> 32) & 0xffff; |
| 7139 | return TRUE; |
| 7140 | |
| 7141 | case BFD_RELOC_HI16_S: |
| 7142 | case BFD_RELOC_HI16_S_PCREL: |
| 7143 | case BFD_RELOC_MICROMIPS_HI16_S: |
| 7144 | case BFD_RELOC_MIPS16_HI16_S: |
| 7145 | *result = ((operand + 0x8000) >> 16) & 0xffff; |
| 7146 | return TRUE; |
| 7147 | |
| 7148 | case BFD_RELOC_HI16: |
| 7149 | case BFD_RELOC_MICROMIPS_HI16: |
| 7150 | case BFD_RELOC_MIPS16_HI16: |
| 7151 | *result = (operand >> 16) & 0xffff; |
| 7152 | return TRUE; |
| 7153 | |
| 7154 | case BFD_RELOC_LO16: |
| 7155 | case BFD_RELOC_LO16_PCREL: |
| 7156 | case BFD_RELOC_MICROMIPS_LO16: |
| 7157 | case BFD_RELOC_MIPS16_LO16: |
| 7158 | *result = operand & 0xffff; |
| 7159 | return TRUE; |
| 7160 | |
| 7161 | case BFD_RELOC_UNUSED: |
| 7162 | *result = operand; |
| 7163 | return TRUE; |
| 7164 | |
| 7165 | default: |
| 7166 | return FALSE; |
| 7167 | } |
| 7168 | } |
| 7169 | |
| 7170 | /* Output an instruction. IP is the instruction information. |
| 7171 | ADDRESS_EXPR is an operand of the instruction to be used with |
| 7172 | RELOC_TYPE. EXPANSIONP is true if the instruction is part of |
| 7173 | a macro expansion. */ |
| 7174 | |
| 7175 | static void |
| 7176 | append_insn (struct mips_cl_insn *ip, expressionS *address_expr, |
| 7177 | bfd_reloc_code_real_type *reloc_type, bfd_boolean expansionp) |
| 7178 | { |
| 7179 | unsigned long prev_pinfo2, pinfo; |
| 7180 | bfd_boolean relaxed_branch = FALSE; |
| 7181 | enum append_method method; |
| 7182 | bfd_boolean relax32; |
| 7183 | int branch_disp; |
| 7184 | |
| 7185 | if (mips_fix_loongson2f && !HAVE_CODE_COMPRESSION) |
| 7186 | fix_loongson2f (ip); |
| 7187 | |
| 7188 | file_ase_mips16 |= mips_opts.mips16; |
| 7189 | file_ase_micromips |= mips_opts.micromips; |
| 7190 | |
| 7191 | prev_pinfo2 = history[0].insn_mo->pinfo2; |
| 7192 | pinfo = ip->insn_mo->pinfo; |
| 7193 | |
| 7194 | /* Don't raise alarm about `nods' frags as they'll fill in the right |
| 7195 | kind of nop in relaxation if required. */ |
| 7196 | if (mips_opts.micromips |
| 7197 | && !expansionp |
| 7198 | && !(history[0].frag |
| 7199 | && history[0].frag->fr_type == rs_machine_dependent |
| 7200 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) |
| 7201 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) |
| 7202 | && (((prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 |
| 7203 | && micromips_insn_length (ip->insn_mo) != 2) |
| 7204 | || ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0 |
| 7205 | && micromips_insn_length (ip->insn_mo) != 4))) |
| 7206 | as_warn (_("wrong size instruction in a %u-bit branch delay slot"), |
| 7207 | (prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32); |
| 7208 | |
| 7209 | if (address_expr == NULL) |
| 7210 | ip->complete_p = 1; |
| 7211 | else if (reloc_type[0] <= BFD_RELOC_UNUSED |
| 7212 | && reloc_type[1] == BFD_RELOC_UNUSED |
| 7213 | && reloc_type[2] == BFD_RELOC_UNUSED |
| 7214 | && address_expr->X_op == O_constant) |
| 7215 | { |
| 7216 | switch (*reloc_type) |
| 7217 | { |
| 7218 | case BFD_RELOC_MIPS_JMP: |
| 7219 | { |
| 7220 | int shift; |
| 7221 | |
| 7222 | /* Shift is 2, unusually, for microMIPS JALX. */ |
| 7223 | shift = (mips_opts.micromips |
| 7224 | && strcmp (ip->insn_mo->name, "jalx") != 0) ? 1 : 2; |
| 7225 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
| 7226 | as_bad (_("jump to misaligned address (0x%lx)"), |
| 7227 | (unsigned long) address_expr->X_add_number); |
| 7228 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) |
| 7229 | & 0x3ffffff); |
| 7230 | ip->complete_p = 1; |
| 7231 | } |
| 7232 | break; |
| 7233 | |
| 7234 | case BFD_RELOC_MIPS16_JMP: |
| 7235 | if ((address_expr->X_add_number & 3) != 0) |
| 7236 | as_bad (_("jump to misaligned address (0x%lx)"), |
| 7237 | (unsigned long) address_expr->X_add_number); |
| 7238 | ip->insn_opcode |= |
| 7239 | (((address_expr->X_add_number & 0x7c0000) << 3) |
| 7240 | | ((address_expr->X_add_number & 0xf800000) >> 7) |
| 7241 | | ((address_expr->X_add_number & 0x3fffc) >> 2)); |
| 7242 | ip->complete_p = 1; |
| 7243 | break; |
| 7244 | |
| 7245 | case BFD_RELOC_16_PCREL_S2: |
| 7246 | { |
| 7247 | int shift; |
| 7248 | |
| 7249 | shift = mips_opts.micromips ? 1 : 2; |
| 7250 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
| 7251 | as_bad (_("branch to misaligned address (0x%lx)"), |
| 7252 | (unsigned long) address_expr->X_add_number); |
| 7253 | if (!mips_relax_branch) |
| 7254 | { |
| 7255 | if ((address_expr->X_add_number + (1 << (shift + 15))) |
| 7256 | & ~((1 << (shift + 16)) - 1)) |
| 7257 | as_bad (_("branch address range overflow (0x%lx)"), |
| 7258 | (unsigned long) address_expr->X_add_number); |
| 7259 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) |
| 7260 | & 0xffff); |
| 7261 | } |
| 7262 | } |
| 7263 | break; |
| 7264 | |
| 7265 | case BFD_RELOC_MIPS_21_PCREL_S2: |
| 7266 | { |
| 7267 | int shift; |
| 7268 | |
| 7269 | shift = 2; |
| 7270 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
| 7271 | as_bad (_("branch to misaligned address (0x%lx)"), |
| 7272 | (unsigned long) address_expr->X_add_number); |
| 7273 | if ((address_expr->X_add_number + (1 << (shift + 20))) |
| 7274 | & ~((1 << (shift + 21)) - 1)) |
| 7275 | as_bad (_("branch address range overflow (0x%lx)"), |
| 7276 | (unsigned long) address_expr->X_add_number); |
| 7277 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) |
| 7278 | & 0x1fffff); |
| 7279 | } |
| 7280 | break; |
| 7281 | |
| 7282 | case BFD_RELOC_MIPS_26_PCREL_S2: |
| 7283 | { |
| 7284 | int shift; |
| 7285 | |
| 7286 | shift = 2; |
| 7287 | if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) |
| 7288 | as_bad (_("branch to misaligned address (0x%lx)"), |
| 7289 | (unsigned long) address_expr->X_add_number); |
| 7290 | if ((address_expr->X_add_number + (1 << (shift + 25))) |
| 7291 | & ~((1 << (shift + 26)) - 1)) |
| 7292 | as_bad (_("branch address range overflow (0x%lx)"), |
| 7293 | (unsigned long) address_expr->X_add_number); |
| 7294 | ip->insn_opcode |= ((address_expr->X_add_number >> shift) |
| 7295 | & 0x3ffffff); |
| 7296 | } |
| 7297 | break; |
| 7298 | |
| 7299 | default: |
| 7300 | { |
| 7301 | offsetT value; |
| 7302 | |
| 7303 | if (calculate_reloc (*reloc_type, address_expr->X_add_number, |
| 7304 | &value)) |
| 7305 | { |
| 7306 | ip->insn_opcode |= value & 0xffff; |
| 7307 | ip->complete_p = 1; |
| 7308 | } |
| 7309 | } |
| 7310 | break; |
| 7311 | } |
| 7312 | } |
| 7313 | |
| 7314 | if (mips_relax.sequence != 2 && !mips_opts.noreorder) |
| 7315 | { |
| 7316 | /* There are a lot of optimizations we could do that we don't. |
| 7317 | In particular, we do not, in general, reorder instructions. |
| 7318 | If you use gcc with optimization, it will reorder |
| 7319 | instructions and generally do much more optimization then we |
| 7320 | do here; repeating all that work in the assembler would only |
| 7321 | benefit hand written assembly code, and does not seem worth |
| 7322 | it. */ |
| 7323 | int nops = (mips_optimize == 0 |
| 7324 | ? nops_for_insn (0, history, NULL) |
| 7325 | : nops_for_insn_or_target (0, history, ip)); |
| 7326 | if (nops > 0) |
| 7327 | { |
| 7328 | fragS *old_frag; |
| 7329 | unsigned long old_frag_offset; |
| 7330 | int i; |
| 7331 | |
| 7332 | old_frag = frag_now; |
| 7333 | old_frag_offset = frag_now_fix (); |
| 7334 | |
| 7335 | for (i = 0; i < nops; i++) |
| 7336 | add_fixed_insn (NOP_INSN); |
| 7337 | insert_into_history (0, nops, NOP_INSN); |
| 7338 | |
| 7339 | if (listing) |
| 7340 | { |
| 7341 | listing_prev_line (); |
| 7342 | /* We may be at the start of a variant frag. In case we |
| 7343 | are, make sure there is enough space for the frag |
| 7344 | after the frags created by listing_prev_line. The |
| 7345 | argument to frag_grow here must be at least as large |
| 7346 | as the argument to all other calls to frag_grow in |
| 7347 | this file. We don't have to worry about being in the |
| 7348 | middle of a variant frag, because the variants insert |
| 7349 | all needed nop instructions themselves. */ |
| 7350 | frag_grow (40); |
| 7351 | } |
| 7352 | |
| 7353 | mips_move_text_labels (); |
| 7354 | |
| 7355 | #ifndef NO_ECOFF_DEBUGGING |
| 7356 | if (ECOFF_DEBUGGING) |
| 7357 | ecoff_fix_loc (old_frag, old_frag_offset); |
| 7358 | #endif |
| 7359 | } |
| 7360 | } |
| 7361 | else if (mips_relax.sequence != 2 && prev_nop_frag != NULL) |
| 7362 | { |
| 7363 | int nops; |
| 7364 | |
| 7365 | /* Work out how many nops in prev_nop_frag are needed by IP, |
| 7366 | ignoring hazards generated by the first prev_nop_frag_since |
| 7367 | instructions. */ |
| 7368 | nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip); |
| 7369 | gas_assert (nops <= prev_nop_frag_holds); |
| 7370 | |
| 7371 | /* Enforce NOPS as a minimum. */ |
| 7372 | if (nops > prev_nop_frag_required) |
| 7373 | prev_nop_frag_required = nops; |
| 7374 | |
| 7375 | if (prev_nop_frag_holds == prev_nop_frag_required) |
| 7376 | { |
| 7377 | /* Settle for the current number of nops. Update the history |
| 7378 | accordingly (for the benefit of any future .set reorder code). */ |
| 7379 | prev_nop_frag = NULL; |
| 7380 | insert_into_history (prev_nop_frag_since, |
| 7381 | prev_nop_frag_holds, NOP_INSN); |
| 7382 | } |
| 7383 | else |
| 7384 | { |
| 7385 | /* Allow this instruction to replace one of the nops that was |
| 7386 | tentatively added to prev_nop_frag. */ |
| 7387 | prev_nop_frag->fr_fix -= NOP_INSN_SIZE; |
| 7388 | prev_nop_frag_holds--; |
| 7389 | prev_nop_frag_since++; |
| 7390 | } |
| 7391 | } |
| 7392 | |
| 7393 | method = get_append_method (ip, address_expr, reloc_type); |
| 7394 | branch_disp = method == APPEND_SWAP ? insn_length (history) : 0; |
| 7395 | |
| 7396 | dwarf2_emit_insn (0); |
| 7397 | /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses, |
| 7398 | so "move" the instruction address accordingly. |
| 7399 | |
| 7400 | Also, it doesn't seem appropriate for the assembler to reorder .loc |
| 7401 | entries. If this instruction is a branch that we are going to swap |
| 7402 | with the previous instruction, the two instructions should be |
| 7403 | treated as a unit, and the debug information for both instructions |
| 7404 | should refer to the start of the branch sequence. Using the |
| 7405 | current position is certainly wrong when swapping a 32-bit branch |
| 7406 | and a 16-bit delay slot, since the current position would then be |
| 7407 | in the middle of a branch. */ |
| 7408 | dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp); |
| 7409 | |
| 7410 | relax32 = (mips_relax_branch |
| 7411 | /* Don't try branch relaxation within .set nomacro, or within |
| 7412 | .set noat if we use $at for PIC computations. If it turns |
| 7413 | out that the branch was out-of-range, we'll get an error. */ |
| 7414 | && !mips_opts.warn_about_macros |
| 7415 | && (mips_opts.at || mips_pic == NO_PIC) |
| 7416 | /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F |
| 7417 | as they have no complementing branches. */ |
| 7418 | && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP))); |
| 7419 | |
| 7420 | if (!HAVE_CODE_COMPRESSION |
| 7421 | && address_expr |
| 7422 | && relax32 |
| 7423 | && *reloc_type == BFD_RELOC_16_PCREL_S2 |
| 7424 | && delayed_branch_p (ip)) |
| 7425 | { |
| 7426 | relaxed_branch = TRUE; |
| 7427 | add_relaxed_insn (ip, (relaxed_branch_length |
| 7428 | (NULL, NULL, |
| 7429 | uncond_branch_p (ip) ? -1 |
| 7430 | : branch_likely_p (ip) ? 1 |
| 7431 | : 0)), 4, |
| 7432 | RELAX_BRANCH_ENCODE |
| 7433 | (AT, mips_pic != NO_PIC, |
| 7434 | uncond_branch_p (ip), |
| 7435 | branch_likely_p (ip), |
| 7436 | pinfo & INSN_WRITE_GPR_31, |
| 7437 | 0), |
| 7438 | address_expr->X_add_symbol, |
| 7439 | address_expr->X_add_number); |
| 7440 | *reloc_type = BFD_RELOC_UNUSED; |
| 7441 | } |
| 7442 | else if (mips_opts.micromips |
| 7443 | && address_expr |
| 7444 | && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) |
| 7445 | || *reloc_type > BFD_RELOC_UNUSED) |
| 7446 | && (delayed_branch_p (ip) || compact_branch_p (ip)) |
| 7447 | /* Don't try branch relaxation when users specify |
| 7448 | 16-bit/32-bit instructions. */ |
| 7449 | && !forced_insn_length) |
| 7450 | { |
| 7451 | bfd_boolean relax16 = (method != APPEND_ADD_COMPACT |
| 7452 | && *reloc_type > BFD_RELOC_UNUSED); |
| 7453 | int type = relax16 ? *reloc_type - BFD_RELOC_UNUSED : 0; |
| 7454 | int uncond = uncond_branch_p (ip) ? -1 : 0; |
| 7455 | int compact = compact_branch_p (ip) || method == APPEND_ADD_COMPACT; |
| 7456 | int nods = method == APPEND_ADD_WITH_NOP; |
| 7457 | int al = pinfo & INSN_WRITE_GPR_31; |
| 7458 | int length32 = nods ? 8 : 4; |
| 7459 | |
| 7460 | gas_assert (address_expr != NULL); |
| 7461 | gas_assert (!mips_relax.sequence); |
| 7462 | |
| 7463 | relaxed_branch = TRUE; |
| 7464 | if (nods) |
| 7465 | method = APPEND_ADD; |
| 7466 | if (relax32) |
| 7467 | length32 = relaxed_micromips_32bit_branch_length (NULL, NULL, uncond); |
| 7468 | add_relaxed_insn (ip, length32, relax16 ? 2 : 4, |
| 7469 | RELAX_MICROMIPS_ENCODE (type, AT, mips_opts.insn32, |
| 7470 | mips_pic != NO_PIC, |
| 7471 | uncond, compact, al, nods, |
| 7472 | relax32, 0, 0), |
| 7473 | address_expr->X_add_symbol, |
| 7474 | address_expr->X_add_number); |
| 7475 | *reloc_type = BFD_RELOC_UNUSED; |
| 7476 | } |
| 7477 | else if (mips_opts.mips16 && *reloc_type > BFD_RELOC_UNUSED) |
| 7478 | { |
| 7479 | bfd_boolean require_unextended; |
| 7480 | bfd_boolean require_extended; |
| 7481 | symbolS *symbol; |
| 7482 | offsetT offset; |
| 7483 | |
| 7484 | if (forced_insn_length != 0) |
| 7485 | { |
| 7486 | require_unextended = forced_insn_length == 2; |
| 7487 | require_extended = forced_insn_length == 4; |
| 7488 | } |
| 7489 | else |
| 7490 | { |
| 7491 | require_unextended = (mips_opts.noautoextend |
| 7492 | && !mips_opcode_32bit_p (ip->insn_mo)); |
| 7493 | require_extended = 0; |
| 7494 | } |
| 7495 | |
| 7496 | /* We need to set up a variant frag. */ |
| 7497 | gas_assert (address_expr != NULL); |
| 7498 | /* Pass any `O_symbol' expression unchanged as an `expr_section' |
| 7499 | symbol created by `make_expr_symbol' may not get a necessary |
| 7500 | external relocation produced. */ |
| 7501 | if (address_expr->X_op == O_symbol) |
| 7502 | { |
| 7503 | symbol = address_expr->X_add_symbol; |
| 7504 | offset = address_expr->X_add_number; |
| 7505 | } |
| 7506 | else |
| 7507 | { |
| 7508 | symbol = make_expr_symbol (address_expr); |
| 7509 | symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP); |
| 7510 | offset = 0; |
| 7511 | } |
| 7512 | add_relaxed_insn (ip, 12, 0, |
| 7513 | RELAX_MIPS16_ENCODE |
| 7514 | (*reloc_type - BFD_RELOC_UNUSED, |
| 7515 | mips_opts.ase & ASE_MIPS16E2, |
| 7516 | mips_pic != NO_PIC, |
| 7517 | HAVE_32BIT_SYMBOLS, |
| 7518 | mips_opts.warn_about_macros, |
| 7519 | require_unextended, require_extended, |
| 7520 | delayed_branch_p (&history[0]), |
| 7521 | history[0].mips16_absolute_jump_p), |
| 7522 | symbol, offset); |
| 7523 | } |
| 7524 | else if (mips_opts.mips16 && insn_length (ip) == 2) |
| 7525 | { |
| 7526 | if (!delayed_branch_p (ip)) |
| 7527 | /* Make sure there is enough room to swap this instruction with |
| 7528 | a following jump instruction. */ |
| 7529 | frag_grow (6); |
| 7530 | add_fixed_insn (ip); |
| 7531 | } |
| 7532 | else |
| 7533 | { |
| 7534 | if (mips_opts.mips16 |
| 7535 | && mips_opts.noreorder |
| 7536 | && delayed_branch_p (&history[0])) |
| 7537 | as_warn (_("extended instruction in delay slot")); |
| 7538 | |
| 7539 | if (mips_relax.sequence) |
| 7540 | { |
| 7541 | /* If we've reached the end of this frag, turn it into a variant |
| 7542 | frag and record the information for the instructions we've |
| 7543 | written so far. */ |
| 7544 | if (frag_room () < 4) |
| 7545 | relax_close_frag (); |
| 7546 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (ip); |
| 7547 | } |
| 7548 | |
| 7549 | if (mips_relax.sequence != 2) |
| 7550 | { |
| 7551 | if (mips_macro_warning.first_insn_sizes[0] == 0) |
| 7552 | mips_macro_warning.first_insn_sizes[0] = insn_length (ip); |
| 7553 | mips_macro_warning.sizes[0] += insn_length (ip); |
| 7554 | mips_macro_warning.insns[0]++; |
| 7555 | } |
| 7556 | if (mips_relax.sequence != 1) |
| 7557 | { |
| 7558 | if (mips_macro_warning.first_insn_sizes[1] == 0) |
| 7559 | mips_macro_warning.first_insn_sizes[1] = insn_length (ip); |
| 7560 | mips_macro_warning.sizes[1] += insn_length (ip); |
| 7561 | mips_macro_warning.insns[1]++; |
| 7562 | } |
| 7563 | |
| 7564 | if (mips_opts.mips16) |
| 7565 | { |
| 7566 | ip->fixed_p = 1; |
| 7567 | ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP); |
| 7568 | } |
| 7569 | add_fixed_insn (ip); |
| 7570 | } |
| 7571 | |
| 7572 | if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) |
| 7573 | { |
| 7574 | bfd_reloc_code_real_type final_type[3]; |
| 7575 | reloc_howto_type *howto0; |
| 7576 | reloc_howto_type *howto; |
| 7577 | int i; |
| 7578 | |
| 7579 | /* Perform any necessary conversion to microMIPS relocations |
| 7580 | and find out how many relocations there actually are. */ |
| 7581 | for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) |
| 7582 | final_type[i] = micromips_map_reloc (reloc_type[i]); |
| 7583 | |
| 7584 | /* In a compound relocation, it is the final (outermost) |
| 7585 | operator that determines the relocated field. */ |
| 7586 | howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); |
| 7587 | if (!howto) |
| 7588 | abort (); |
| 7589 | |
| 7590 | if (i > 1) |
| 7591 | howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); |
| 7592 | ip->fixp[0] = fix_new_exp (ip->frag, ip->where, |
| 7593 | bfd_get_reloc_size (howto), |
| 7594 | address_expr, |
| 7595 | howto0 && howto0->pc_relative, |
| 7596 | final_type[0]); |
| 7597 | /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */ |
| 7598 | ip->fixp[0]->fx_tcbit2 = mips_pic == NO_PIC; |
| 7599 | |
| 7600 | /* Tag symbols that have a R_MIPS16_26 relocation against them. */ |
| 7601 | if (final_type[0] == BFD_RELOC_MIPS16_JMP && ip->fixp[0]->fx_addsy) |
| 7602 | *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1; |
| 7603 | |
| 7604 | /* These relocations can have an addend that won't fit in |
| 7605 | 4 octets for 64bit assembly. */ |
| 7606 | if (GPR_SIZE == 64 |
| 7607 | && ! howto->partial_inplace |
| 7608 | && (reloc_type[0] == BFD_RELOC_16 |
| 7609 | || reloc_type[0] == BFD_RELOC_32 |
| 7610 | || reloc_type[0] == BFD_RELOC_MIPS_JMP |
| 7611 | || reloc_type[0] == BFD_RELOC_GPREL16 |
| 7612 | || reloc_type[0] == BFD_RELOC_MIPS_LITERAL |
| 7613 | || reloc_type[0] == BFD_RELOC_GPREL32 |
| 7614 | || reloc_type[0] == BFD_RELOC_64 |
| 7615 | || reloc_type[0] == BFD_RELOC_CTOR |
| 7616 | || reloc_type[0] == BFD_RELOC_MIPS_SUB |
| 7617 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST |
| 7618 | || reloc_type[0] == BFD_RELOC_MIPS_HIGHER |
| 7619 | || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP |
| 7620 | || reloc_type[0] == BFD_RELOC_MIPS_REL16 |
| 7621 | || reloc_type[0] == BFD_RELOC_MIPS_RELGOT |
| 7622 | || reloc_type[0] == BFD_RELOC_MIPS16_GPREL |
| 7623 | || hi16_reloc_p (reloc_type[0]) |
| 7624 | || lo16_reloc_p (reloc_type[0]))) |
| 7625 | ip->fixp[0]->fx_no_overflow = 1; |
| 7626 | |
| 7627 | /* These relocations can have an addend that won't fit in 2 octets. */ |
| 7628 | if (reloc_type[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
| 7629 | || reloc_type[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1) |
| 7630 | ip->fixp[0]->fx_no_overflow = 1; |
| 7631 | |
| 7632 | if (mips_relax.sequence) |
| 7633 | { |
| 7634 | if (mips_relax.first_fixup == 0) |
| 7635 | mips_relax.first_fixup = ip->fixp[0]; |
| 7636 | } |
| 7637 | else if (reloc_needs_lo_p (*reloc_type)) |
| 7638 | { |
| 7639 | struct mips_hi_fixup *hi_fixup; |
| 7640 | |
| 7641 | /* Reuse the last entry if it already has a matching %lo. */ |
| 7642 | hi_fixup = mips_hi_fixup_list; |
| 7643 | if (hi_fixup == 0 |
| 7644 | || !fixup_has_matching_lo_p (hi_fixup->fixp)) |
| 7645 | { |
| 7646 | hi_fixup = XNEW (struct mips_hi_fixup); |
| 7647 | hi_fixup->next = mips_hi_fixup_list; |
| 7648 | mips_hi_fixup_list = hi_fixup; |
| 7649 | } |
| 7650 | hi_fixup->fixp = ip->fixp[0]; |
| 7651 | hi_fixup->seg = now_seg; |
| 7652 | } |
| 7653 | |
| 7654 | /* Add fixups for the second and third relocations, if given. |
| 7655 | Note that the ABI allows the second relocation to be |
| 7656 | against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the |
| 7657 | moment we only use RSS_UNDEF, but we could add support |
| 7658 | for the others if it ever becomes necessary. */ |
| 7659 | for (i = 1; i < 3; i++) |
| 7660 | if (reloc_type[i] != BFD_RELOC_UNUSED) |
| 7661 | { |
| 7662 | ip->fixp[i] = fix_new (ip->frag, ip->where, |
| 7663 | ip->fixp[0]->fx_size, NULL, 0, |
| 7664 | FALSE, final_type[i]); |
| 7665 | |
| 7666 | /* Use fx_tcbit to mark compound relocs. */ |
| 7667 | ip->fixp[0]->fx_tcbit = 1; |
| 7668 | ip->fixp[i]->fx_tcbit = 1; |
| 7669 | } |
| 7670 | } |
| 7671 | |
| 7672 | /* Update the register mask information. */ |
| 7673 | mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip); |
| 7674 | mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip); |
| 7675 | |
| 7676 | switch (method) |
| 7677 | { |
| 7678 | case APPEND_ADD: |
| 7679 | insert_into_history (0, 1, ip); |
| 7680 | break; |
| 7681 | |
| 7682 | case APPEND_ADD_WITH_NOP: |
| 7683 | { |
| 7684 | struct mips_cl_insn *nop; |
| 7685 | |
| 7686 | insert_into_history (0, 1, ip); |
| 7687 | nop = get_delay_slot_nop (ip); |
| 7688 | add_fixed_insn (nop); |
| 7689 | insert_into_history (0, 1, nop); |
| 7690 | if (mips_relax.sequence) |
| 7691 | mips_relax.sizes[mips_relax.sequence - 1] += insn_length (nop); |
| 7692 | } |
| 7693 | break; |
| 7694 | |
| 7695 | case APPEND_ADD_COMPACT: |
| 7696 | /* Convert MIPS16 jr/jalr into a "compact" jump. */ |
| 7697 | if (mips_opts.mips16) |
| 7698 | { |
| 7699 | ip->insn_opcode |= 0x0080; |
| 7700 | find_altered_mips16_opcode (ip); |
| 7701 | } |
| 7702 | /* Convert microMIPS instructions. */ |
| 7703 | else if (mips_opts.micromips) |
| 7704 | { |
| 7705 | /* jr16->jrc */ |
| 7706 | if ((ip->insn_opcode & 0xffe0) == 0x4580) |
| 7707 | ip->insn_opcode |= 0x0020; |
| 7708 | /* b16->bc */ |
| 7709 | else if ((ip->insn_opcode & 0xfc00) == 0xcc00) |
| 7710 | ip->insn_opcode = 0x40e00000; |
| 7711 | /* beqz16->beqzc, bnez16->bnezc */ |
| 7712 | else if ((ip->insn_opcode & 0xdc00) == 0x8c00) |
| 7713 | { |
| 7714 | unsigned long regno; |
| 7715 | |
| 7716 | regno = ip->insn_opcode >> MICROMIPSOP_SH_MD; |
| 7717 | regno &= MICROMIPSOP_MASK_MD; |
| 7718 | regno = micromips_to_32_reg_d_map[regno]; |
| 7719 | ip->insn_opcode = (((ip->insn_opcode << 9) & 0x00400000) |
| 7720 | | (regno << MICROMIPSOP_SH_RS) |
| 7721 | | 0x40a00000) ^ 0x00400000; |
| 7722 | } |
| 7723 | /* beqz->beqzc, bnez->bnezc */ |
| 7724 | else if ((ip->insn_opcode & 0xdfe00000) == 0x94000000) |
| 7725 | ip->insn_opcode = ((ip->insn_opcode & 0x001f0000) |
| 7726 | | ((ip->insn_opcode >> 7) & 0x00400000) |
| 7727 | | 0x40a00000) ^ 0x00400000; |
| 7728 | /* beq $0->beqzc, bne $0->bnezc */ |
| 7729 | else if ((ip->insn_opcode & 0xdc1f0000) == 0x94000000) |
| 7730 | ip->insn_opcode = (((ip->insn_opcode >> |
| 7731 | (MICROMIPSOP_SH_RT - MICROMIPSOP_SH_RS)) |
| 7732 | & (MICROMIPSOP_MASK_RS << MICROMIPSOP_SH_RS)) |
| 7733 | | ((ip->insn_opcode >> 7) & 0x00400000) |
| 7734 | | 0x40a00000) ^ 0x00400000; |
| 7735 | else |
| 7736 | abort (); |
| 7737 | find_altered_micromips_opcode (ip); |
| 7738 | } |
| 7739 | else |
| 7740 | abort (); |
| 7741 | install_insn (ip); |
| 7742 | insert_into_history (0, 1, ip); |
| 7743 | break; |
| 7744 | |
| 7745 | case APPEND_SWAP: |
| 7746 | { |
| 7747 | struct mips_cl_insn delay = history[0]; |
| 7748 | |
| 7749 | if (relaxed_branch || delay.frag != ip->frag) |
| 7750 | { |
| 7751 | /* Add the delay slot instruction to the end of the |
| 7752 | current frag and shrink the fixed part of the |
| 7753 | original frag. If the branch occupies the tail of |
| 7754 | the latter, move it backwards to cover the gap. */ |
| 7755 | delay.frag->fr_fix -= branch_disp; |
| 7756 | if (delay.frag == ip->frag) |
| 7757 | move_insn (ip, ip->frag, ip->where - branch_disp); |
| 7758 | add_fixed_insn (&delay); |
| 7759 | } |
| 7760 | else |
| 7761 | { |
| 7762 | /* If this is not a relaxed branch and we are in the |
| 7763 | same frag, then just swap the instructions. */ |
| 7764 | move_insn (ip, delay.frag, delay.where); |
| 7765 | move_insn (&delay, ip->frag, ip->where + insn_length (ip)); |
| 7766 | } |
| 7767 | history[0] = *ip; |
| 7768 | delay.fixed_p = 1; |
| 7769 | insert_into_history (0, 1, &delay); |
| 7770 | } |
| 7771 | break; |
| 7772 | } |
| 7773 | |
| 7774 | /* If we have just completed an unconditional branch, clear the history. */ |
| 7775 | if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) |
| 7776 | || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) |
| 7777 | { |
| 7778 | unsigned int i; |
| 7779 | |
| 7780 | mips_no_prev_insn (); |
| 7781 | |
| 7782 | for (i = 0; i < ARRAY_SIZE (history); i++) |
| 7783 | history[i].cleared_p = 1; |
| 7784 | } |
| 7785 | |
| 7786 | /* We need to emit a label at the end of branch-likely macros. */ |
| 7787 | if (emit_branch_likely_macro) |
| 7788 | { |
| 7789 | emit_branch_likely_macro = FALSE; |
| 7790 | micromips_add_label (); |
| 7791 | } |
| 7792 | |
| 7793 | /* We just output an insn, so the next one doesn't have a label. */ |
| 7794 | mips_clear_insn_labels (); |
| 7795 | } |
| 7796 | |
| 7797 | /* Forget that there was any previous instruction or label. |
| 7798 | When BRANCH is true, the branch history is also flushed. */ |
| 7799 | |
| 7800 | static void |
| 7801 | mips_no_prev_insn (void) |
| 7802 | { |
| 7803 | prev_nop_frag = NULL; |
| 7804 | insert_into_history (0, ARRAY_SIZE (history), NOP_INSN); |
| 7805 | mips_clear_insn_labels (); |
| 7806 | } |
| 7807 | |
| 7808 | /* This function must be called before we emit something other than |
| 7809 | instructions. It is like mips_no_prev_insn except that it inserts |
| 7810 | any NOPS that might be needed by previous instructions. */ |
| 7811 | |
| 7812 | void |
| 7813 | mips_emit_delays (void) |
| 7814 | { |
| 7815 | if (! mips_opts.noreorder) |
| 7816 | { |
| 7817 | int nops = nops_for_insn (0, history, NULL); |
| 7818 | if (nops > 0) |
| 7819 | { |
| 7820 | while (nops-- > 0) |
| 7821 | add_fixed_insn (NOP_INSN); |
| 7822 | mips_move_text_labels (); |
| 7823 | } |
| 7824 | } |
| 7825 | mips_no_prev_insn (); |
| 7826 | } |
| 7827 | |
| 7828 | /* Start a (possibly nested) noreorder block. */ |
| 7829 | |
| 7830 | static void |
| 7831 | start_noreorder (void) |
| 7832 | { |
| 7833 | if (mips_opts.noreorder == 0) |
| 7834 | { |
| 7835 | unsigned int i; |
| 7836 | int nops; |
| 7837 | |
| 7838 | /* None of the instructions before the .set noreorder can be moved. */ |
| 7839 | for (i = 0; i < ARRAY_SIZE (history); i++) |
| 7840 | history[i].fixed_p = 1; |
| 7841 | |
| 7842 | /* Insert any nops that might be needed between the .set noreorder |
| 7843 | block and the previous instructions. We will later remove any |
| 7844 | nops that turn out not to be needed. */ |
| 7845 | nops = nops_for_insn (0, history, NULL); |
| 7846 | if (nops > 0) |
| 7847 | { |
| 7848 | if (mips_optimize != 0) |
| 7849 | { |
| 7850 | /* Record the frag which holds the nop instructions, so |
| 7851 | that we can remove them if we don't need them. */ |
| 7852 | frag_grow (nops * NOP_INSN_SIZE); |
| 7853 | prev_nop_frag = frag_now; |
| 7854 | prev_nop_frag_holds = nops; |
| 7855 | prev_nop_frag_required = 0; |
| 7856 | prev_nop_frag_since = 0; |
| 7857 | } |
| 7858 | |
| 7859 | for (; nops > 0; --nops) |
| 7860 | add_fixed_insn (NOP_INSN); |
| 7861 | |
| 7862 | /* Move on to a new frag, so that it is safe to simply |
| 7863 | decrease the size of prev_nop_frag. */ |
| 7864 | frag_wane (frag_now); |
| 7865 | frag_new (0); |
| 7866 | mips_move_text_labels (); |
| 7867 | } |
| 7868 | mips_mark_labels (); |
| 7869 | mips_clear_insn_labels (); |
| 7870 | } |
| 7871 | mips_opts.noreorder++; |
| 7872 | mips_any_noreorder = 1; |
| 7873 | } |
| 7874 | |
| 7875 | /* End a nested noreorder block. */ |
| 7876 | |
| 7877 | static void |
| 7878 | end_noreorder (void) |
| 7879 | { |
| 7880 | mips_opts.noreorder--; |
| 7881 | if (mips_opts.noreorder == 0 && prev_nop_frag != NULL) |
| 7882 | { |
| 7883 | /* Commit to inserting prev_nop_frag_required nops and go back to |
| 7884 | handling nop insertion the .set reorder way. */ |
| 7885 | prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required) |
| 7886 | * NOP_INSN_SIZE); |
| 7887 | insert_into_history (prev_nop_frag_since, |
| 7888 | prev_nop_frag_required, NOP_INSN); |
| 7889 | prev_nop_frag = NULL; |
| 7890 | } |
| 7891 | } |
| 7892 | |
| 7893 | /* Sign-extend 32-bit mode constants that have bit 31 set and all |
| 7894 | higher bits unset. */ |
| 7895 | |
| 7896 | static void |
| 7897 | normalize_constant_expr (expressionS *ex) |
| 7898 | { |
| 7899 | if (ex->X_op == O_constant |
| 7900 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
| 7901 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) |
| 7902 | - 0x80000000); |
| 7903 | } |
| 7904 | |
| 7905 | /* Sign-extend 32-bit mode address offsets that have bit 31 set and |
| 7906 | all higher bits unset. */ |
| 7907 | |
| 7908 | static void |
| 7909 | normalize_address_expr (expressionS *ex) |
| 7910 | { |
| 7911 | if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) |
| 7912 | || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) |
| 7913 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) |
| 7914 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) |
| 7915 | - 0x80000000); |
| 7916 | } |
| 7917 | |
| 7918 | /* Try to match TOKENS against OPCODE, storing the result in INSN. |
| 7919 | Return true if the match was successful. |
| 7920 | |
| 7921 | OPCODE_EXTRA is a value that should be ORed into the opcode |
| 7922 | (used for VU0 channel suffixes, etc.). MORE_ALTS is true if |
| 7923 | there are more alternatives after OPCODE and SOFT_MATCH is |
| 7924 | as for mips_arg_info. */ |
| 7925 | |
| 7926 | static bfd_boolean |
| 7927 | match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, |
| 7928 | struct mips_operand_token *tokens, unsigned int opcode_extra, |
| 7929 | bfd_boolean lax_match, bfd_boolean complete_p) |
| 7930 | { |
| 7931 | const char *args; |
| 7932 | struct mips_arg_info arg; |
| 7933 | const struct mips_operand *operand; |
| 7934 | char c; |
| 7935 | |
| 7936 | imm_expr.X_op = O_absent; |
| 7937 | offset_expr.X_op = O_absent; |
| 7938 | offset_reloc[0] = BFD_RELOC_UNUSED; |
| 7939 | offset_reloc[1] = BFD_RELOC_UNUSED; |
| 7940 | offset_reloc[2] = BFD_RELOC_UNUSED; |
| 7941 | |
| 7942 | create_insn (insn, opcode); |
| 7943 | /* When no opcode suffix is specified, assume ".xyzw". */ |
| 7944 | if ((opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0 && opcode_extra == 0) |
| 7945 | insn->insn_opcode |= 0xf << mips_vu0_channel_mask.lsb; |
| 7946 | else |
| 7947 | insn->insn_opcode |= opcode_extra; |
| 7948 | memset (&arg, 0, sizeof (arg)); |
| 7949 | arg.insn = insn; |
| 7950 | arg.token = tokens; |
| 7951 | arg.argnum = 1; |
| 7952 | arg.last_regno = ILLEGAL_REG; |
| 7953 | arg.dest_regno = ILLEGAL_REG; |
| 7954 | arg.lax_match = lax_match; |
| 7955 | for (args = opcode->args;; ++args) |
| 7956 | { |
| 7957 | if (arg.token->type == OT_END) |
| 7958 | { |
| 7959 | /* Handle unary instructions in which only one operand is given. |
| 7960 | The source is then the same as the destination. */ |
| 7961 | if (arg.opnum == 1 && *args == ',') |
| 7962 | { |
| 7963 | operand = (mips_opts.micromips |
| 7964 | ? decode_micromips_operand (args + 1) |
| 7965 | : decode_mips_operand (args + 1)); |
| 7966 | if (operand && mips_optional_operand_p (operand)) |
| 7967 | { |
| 7968 | arg.token = tokens; |
| 7969 | arg.argnum = 1; |
| 7970 | continue; |
| 7971 | } |
| 7972 | } |
| 7973 | |
| 7974 | /* Treat elided base registers as $0. */ |
| 7975 | if (strcmp (args, "(b)") == 0) |
| 7976 | args += 3; |
| 7977 | |
| 7978 | if (args[0] == '+') |
| 7979 | switch (args[1]) |
| 7980 | { |
| 7981 | case 'K': |
| 7982 | case 'N': |
| 7983 | /* The register suffix is optional. */ |
| 7984 | args += 2; |
| 7985 | break; |
| 7986 | } |
| 7987 | |
| 7988 | /* Fail the match if there were too few operands. */ |
| 7989 | if (*args) |
| 7990 | return FALSE; |
| 7991 | |
| 7992 | /* Successful match. */ |
| 7993 | if (!complete_p) |
| 7994 | return TRUE; |
| 7995 | clear_insn_error (); |
| 7996 | if (arg.dest_regno == arg.last_regno |
| 7997 | && strncmp (insn->insn_mo->name, "jalr", 4) == 0) |
| 7998 | { |
| 7999 | if (arg.opnum == 2) |
| 8000 | set_insn_error |
| 8001 | (0, _("source and destination must be different")); |
| 8002 | else if (arg.last_regno == 31) |
| 8003 | set_insn_error |
| 8004 | (0, _("a destination register must be supplied")); |
| 8005 | } |
| 8006 | else if (arg.last_regno == 31 |
| 8007 | && (strncmp (insn->insn_mo->name, "bltzal", 6) == 0 |
| 8008 | || strncmp (insn->insn_mo->name, "bgezal", 6) == 0)) |
| 8009 | set_insn_error (0, _("the source register must not be $31")); |
| 8010 | check_completed_insn (&arg); |
| 8011 | return TRUE; |
| 8012 | } |
| 8013 | |
| 8014 | /* Fail the match if the line has too many operands. */ |
| 8015 | if (*args == 0) |
| 8016 | return FALSE; |
| 8017 | |
| 8018 | /* Handle characters that need to match exactly. */ |
| 8019 | if (*args == '(' || *args == ')' || *args == ',') |
| 8020 | { |
| 8021 | if (match_char (&arg, *args)) |
| 8022 | continue; |
| 8023 | return FALSE; |
| 8024 | } |
| 8025 | if (*args == '#') |
| 8026 | { |
| 8027 | ++args; |
| 8028 | if (arg.token->type == OT_DOUBLE_CHAR |
| 8029 | && arg.token->u.ch == *args) |
| 8030 | { |
| 8031 | ++arg.token; |
| 8032 | continue; |
| 8033 | } |
| 8034 | return FALSE; |
| 8035 | } |
| 8036 | |
| 8037 | /* Handle special macro operands. Work out the properties of |
| 8038 | other operands. */ |
| 8039 | arg.opnum += 1; |
| 8040 | switch (*args) |
| 8041 | { |
| 8042 | case '-': |
| 8043 | switch (args[1]) |
| 8044 | { |
| 8045 | case 'A': |
| 8046 | *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; |
| 8047 | break; |
| 8048 | |
| 8049 | case 'B': |
| 8050 | *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; |
| 8051 | break; |
| 8052 | } |
| 8053 | break; |
| 8054 | |
| 8055 | case '+': |
| 8056 | switch (args[1]) |
| 8057 | { |
| 8058 | case 'i': |
| 8059 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
| 8060 | break; |
| 8061 | |
| 8062 | case '\'': |
| 8063 | *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; |
| 8064 | break; |
| 8065 | |
| 8066 | case '\"': |
| 8067 | *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; |
| 8068 | break; |
| 8069 | } |
| 8070 | break; |
| 8071 | |
| 8072 | case 'I': |
| 8073 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
| 8074 | return FALSE; |
| 8075 | imm_expr.X_op = O_constant; |
| 8076 | if (GPR_SIZE == 32) |
| 8077 | normalize_constant_expr (&imm_expr); |
| 8078 | continue; |
| 8079 | |
| 8080 | case 'A': |
| 8081 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') |
| 8082 | { |
| 8083 | /* Assume that the offset has been elided and that what |
| 8084 | we saw was a base register. The match will fail later |
| 8085 | if that assumption turns out to be wrong. */ |
| 8086 | offset_expr.X_op = O_constant; |
| 8087 | offset_expr.X_add_number = 0; |
| 8088 | } |
| 8089 | else |
| 8090 | { |
| 8091 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
| 8092 | return FALSE; |
| 8093 | normalize_address_expr (&offset_expr); |
| 8094 | } |
| 8095 | continue; |
| 8096 | |
| 8097 | case 'F': |
| 8098 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, |
| 8099 | 8, TRUE)) |
| 8100 | return FALSE; |
| 8101 | continue; |
| 8102 | |
| 8103 | case 'L': |
| 8104 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, |
| 8105 | 8, FALSE)) |
| 8106 | return FALSE; |
| 8107 | continue; |
| 8108 | |
| 8109 | case 'f': |
| 8110 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, |
| 8111 | 4, TRUE)) |
| 8112 | return FALSE; |
| 8113 | continue; |
| 8114 | |
| 8115 | case 'l': |
| 8116 | if (!match_float_constant (&arg, &imm_expr, &offset_expr, |
| 8117 | 4, FALSE)) |
| 8118 | return FALSE; |
| 8119 | continue; |
| 8120 | |
| 8121 | case 'p': |
| 8122 | *offset_reloc = BFD_RELOC_16_PCREL_S2; |
| 8123 | break; |
| 8124 | |
| 8125 | case 'a': |
| 8126 | *offset_reloc = BFD_RELOC_MIPS_JMP; |
| 8127 | break; |
| 8128 | |
| 8129 | case 'm': |
| 8130 | gas_assert (mips_opts.micromips); |
| 8131 | c = args[1]; |
| 8132 | switch (c) |
| 8133 | { |
| 8134 | case 'D': |
| 8135 | case 'E': |
| 8136 | if (!forced_insn_length) |
| 8137 | *offset_reloc = (int) BFD_RELOC_UNUSED + c; |
| 8138 | else if (c == 'D') |
| 8139 | *offset_reloc = BFD_RELOC_MICROMIPS_10_PCREL_S1; |
| 8140 | else |
| 8141 | *offset_reloc = BFD_RELOC_MICROMIPS_7_PCREL_S1; |
| 8142 | break; |
| 8143 | } |
| 8144 | break; |
| 8145 | } |
| 8146 | |
| 8147 | operand = (mips_opts.micromips |
| 8148 | ? decode_micromips_operand (args) |
| 8149 | : decode_mips_operand (args)); |
| 8150 | if (!operand) |
| 8151 | abort (); |
| 8152 | |
| 8153 | /* Skip prefixes. */ |
| 8154 | if (*args == '+' || *args == 'm' || *args == '-') |
| 8155 | args++; |
| 8156 | |
| 8157 | if (mips_optional_operand_p (operand) |
| 8158 | && args[1] == ',' |
| 8159 | && (arg.token[0].type != OT_REG |
| 8160 | || arg.token[1].type == OT_END)) |
| 8161 | { |
| 8162 | /* Assume that the register has been elided and is the |
| 8163 | same as the first operand. */ |
| 8164 | arg.token = tokens; |
| 8165 | arg.argnum = 1; |
| 8166 | } |
| 8167 | |
| 8168 | if (!match_operand (&arg, operand)) |
| 8169 | return FALSE; |
| 8170 | } |
| 8171 | } |
| 8172 | |
| 8173 | /* Like match_insn, but for MIPS16. */ |
| 8174 | |
| 8175 | static bfd_boolean |
| 8176 | match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, |
| 8177 | struct mips_operand_token *tokens) |
| 8178 | { |
| 8179 | const char *args; |
| 8180 | const struct mips_operand *operand; |
| 8181 | const struct mips_operand *ext_operand; |
| 8182 | bfd_boolean pcrel = FALSE; |
| 8183 | int required_insn_length; |
| 8184 | struct mips_arg_info arg; |
| 8185 | int relax_char; |
| 8186 | |
| 8187 | if (forced_insn_length) |
| 8188 | required_insn_length = forced_insn_length; |
| 8189 | else if (mips_opts.noautoextend && !mips_opcode_32bit_p (opcode)) |
| 8190 | required_insn_length = 2; |
| 8191 | else |
| 8192 | required_insn_length = 0; |
| 8193 | |
| 8194 | create_insn (insn, opcode); |
| 8195 | imm_expr.X_op = O_absent; |
| 8196 | offset_expr.X_op = O_absent; |
| 8197 | offset_reloc[0] = BFD_RELOC_UNUSED; |
| 8198 | offset_reloc[1] = BFD_RELOC_UNUSED; |
| 8199 | offset_reloc[2] = BFD_RELOC_UNUSED; |
| 8200 | relax_char = 0; |
| 8201 | |
| 8202 | memset (&arg, 0, sizeof (arg)); |
| 8203 | arg.insn = insn; |
| 8204 | arg.token = tokens; |
| 8205 | arg.argnum = 1; |
| 8206 | arg.last_regno = ILLEGAL_REG; |
| 8207 | arg.dest_regno = ILLEGAL_REG; |
| 8208 | relax_char = 0; |
| 8209 | for (args = opcode->args;; ++args) |
| 8210 | { |
| 8211 | int c; |
| 8212 | |
| 8213 | if (arg.token->type == OT_END) |
| 8214 | { |
| 8215 | offsetT value; |
| 8216 | |
| 8217 | /* Handle unary instructions in which only one operand is given. |
| 8218 | The source is then the same as the destination. */ |
| 8219 | if (arg.opnum == 1 && *args == ',') |
| 8220 | { |
| 8221 | operand = decode_mips16_operand (args[1], FALSE); |
| 8222 | if (operand && mips_optional_operand_p (operand)) |
| 8223 | { |
| 8224 | arg.token = tokens; |
| 8225 | arg.argnum = 1; |
| 8226 | continue; |
| 8227 | } |
| 8228 | } |
| 8229 | |
| 8230 | /* Fail the match if there were too few operands. */ |
| 8231 | if (*args) |
| 8232 | return FALSE; |
| 8233 | |
| 8234 | /* Successful match. Stuff the immediate value in now, if |
| 8235 | we can. */ |
| 8236 | clear_insn_error (); |
| 8237 | if (opcode->pinfo == INSN_MACRO) |
| 8238 | { |
| 8239 | gas_assert (relax_char == 0 || relax_char == 'p'); |
| 8240 | gas_assert (*offset_reloc == BFD_RELOC_UNUSED); |
| 8241 | } |
| 8242 | else if (relax_char |
| 8243 | && offset_expr.X_op == O_constant |
| 8244 | && !pcrel |
| 8245 | && calculate_reloc (*offset_reloc, |
| 8246 | offset_expr.X_add_number, |
| 8247 | &value)) |
| 8248 | { |
| 8249 | mips16_immed (NULL, 0, relax_char, *offset_reloc, value, |
| 8250 | required_insn_length, &insn->insn_opcode); |
| 8251 | offset_expr.X_op = O_absent; |
| 8252 | *offset_reloc = BFD_RELOC_UNUSED; |
| 8253 | } |
| 8254 | else if (relax_char && *offset_reloc != BFD_RELOC_UNUSED) |
| 8255 | { |
| 8256 | if (required_insn_length == 2) |
| 8257 | set_insn_error (0, _("invalid unextended operand value")); |
| 8258 | else if (!mips_opcode_32bit_p (opcode)) |
| 8259 | { |
| 8260 | forced_insn_length = 4; |
| 8261 | insn->insn_opcode |= MIPS16_EXTEND; |
| 8262 | } |
| 8263 | } |
| 8264 | else if (relax_char) |
| 8265 | *offset_reloc = (int) BFD_RELOC_UNUSED + relax_char; |
| 8266 | |
| 8267 | check_completed_insn (&arg); |
| 8268 | return TRUE; |
| 8269 | } |
| 8270 | |
| 8271 | /* Fail the match if the line has too many operands. */ |
| 8272 | if (*args == 0) |
| 8273 | return FALSE; |
| 8274 | |
| 8275 | /* Handle characters that need to match exactly. */ |
| 8276 | if (*args == '(' || *args == ')' || *args == ',') |
| 8277 | { |
| 8278 | if (match_char (&arg, *args)) |
| 8279 | continue; |
| 8280 | return FALSE; |
| 8281 | } |
| 8282 | |
| 8283 | arg.opnum += 1; |
| 8284 | c = *args; |
| 8285 | switch (c) |
| 8286 | { |
| 8287 | case 'p': |
| 8288 | case 'q': |
| 8289 | case 'A': |
| 8290 | case 'B': |
| 8291 | case 'E': |
| 8292 | case 'V': |
| 8293 | case 'u': |
| 8294 | relax_char = c; |
| 8295 | break; |
| 8296 | |
| 8297 | case 'I': |
| 8298 | if (!match_const_int (&arg, &imm_expr.X_add_number)) |
| 8299 | return FALSE; |
| 8300 | imm_expr.X_op = O_constant; |
| 8301 | if (GPR_SIZE == 32) |
| 8302 | normalize_constant_expr (&imm_expr); |
| 8303 | continue; |
| 8304 | |
| 8305 | case 'a': |
| 8306 | case 'i': |
| 8307 | *offset_reloc = BFD_RELOC_MIPS16_JMP; |
| 8308 | break; |
| 8309 | } |
| 8310 | |
| 8311 | operand = decode_mips16_operand (c, mips_opcode_32bit_p (opcode)); |
| 8312 | if (!operand) |
| 8313 | abort (); |
| 8314 | |
| 8315 | if (operand->type == OP_PCREL) |
| 8316 | pcrel = TRUE; |
| 8317 | else |
| 8318 | { |
| 8319 | ext_operand = decode_mips16_operand (c, TRUE); |
| 8320 | if (operand != ext_operand) |
| 8321 | { |
| 8322 | if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') |
| 8323 | { |
| 8324 | offset_expr.X_op = O_constant; |
| 8325 | offset_expr.X_add_number = 0; |
| 8326 | relax_char = c; |
| 8327 | continue; |
| 8328 | } |
| 8329 | |
| 8330 | if (!match_expression (&arg, &offset_expr, offset_reloc)) |
| 8331 | return FALSE; |
| 8332 | |
| 8333 | /* '8' is used for SLTI(U) and has traditionally not |
| 8334 | been allowed to take relocation operators. */ |
| 8335 | if (offset_reloc[0] != BFD_RELOC_UNUSED |
| 8336 | && (ext_operand->size != 16 || c == '8')) |
| 8337 | { |
| 8338 | match_not_constant (&arg); |
| 8339 | return FALSE; |
| 8340 | } |
| 8341 | |
| 8342 | if (offset_expr.X_op == O_big) |
| 8343 | { |
| 8344 | match_out_of_range (&arg); |
| 8345 | return FALSE; |
| 8346 | } |
| 8347 | |
| 8348 | relax_char = c; |
| 8349 | continue; |
| 8350 | } |
| 8351 | } |
| 8352 | |
| 8353 | if (mips_optional_operand_p (operand) |
| 8354 | && args[1] == ',' |
| 8355 | && (arg.token[0].type != OT_REG |
| 8356 | || arg.token[1].type == OT_END)) |
| 8357 | { |
| 8358 | /* Assume that the register has been elided and is the |
| 8359 | same as the first operand. */ |
| 8360 | arg.token = tokens; |
| 8361 | arg.argnum = 1; |
| 8362 | } |
| 8363 | |
| 8364 | if (!match_operand (&arg, operand)) |
| 8365 | return FALSE; |
| 8366 | } |
| 8367 | } |
| 8368 | |
| 8369 | /* Record that the current instruction is invalid for the current ISA. */ |
| 8370 | |
| 8371 | static void |
| 8372 | match_invalid_for_isa (void) |
| 8373 | { |
| 8374 | set_insn_error_ss |
| 8375 | (0, _("opcode not supported on this processor: %s (%s)"), |
| 8376 | mips_cpu_info_from_arch (mips_opts.arch)->name, |
| 8377 | mips_cpu_info_from_isa (mips_opts.isa)->name); |
| 8378 | } |
| 8379 | |
| 8380 | /* Try to match TOKENS against a series of opcode entries, starting at FIRST. |
| 8381 | Return true if a definite match or failure was found, storing any match |
| 8382 | in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode |
| 8383 | (to handle things like VU0 suffixes). LAX_MATCH is true if we have already |
| 8384 | tried and failed to match under normal conditions and now want to try a |
| 8385 | more relaxed match. */ |
| 8386 | |
| 8387 | static bfd_boolean |
| 8388 | match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, |
| 8389 | const struct mips_opcode *past, struct mips_operand_token *tokens, |
| 8390 | int opcode_extra, bfd_boolean lax_match) |
| 8391 | { |
| 8392 | const struct mips_opcode *opcode; |
| 8393 | const struct mips_opcode *invalid_delay_slot; |
| 8394 | bfd_boolean seen_valid_for_isa, seen_valid_for_size; |
| 8395 | |
| 8396 | /* Search for a match, ignoring alternatives that don't satisfy the |
| 8397 | current ISA or forced_length. */ |
| 8398 | invalid_delay_slot = 0; |
| 8399 | seen_valid_for_isa = FALSE; |
| 8400 | seen_valid_for_size = FALSE; |
| 8401 | opcode = first; |
| 8402 | do |
| 8403 | { |
| 8404 | gas_assert (strcmp (opcode->name, first->name) == 0); |
| 8405 | if (is_opcode_valid (opcode)) |
| 8406 | { |
| 8407 | seen_valid_for_isa = TRUE; |
| 8408 | if (is_size_valid (opcode)) |
| 8409 | { |
| 8410 | bfd_boolean delay_slot_ok; |
| 8411 | |
| 8412 | seen_valid_for_size = TRUE; |
| 8413 | delay_slot_ok = is_delay_slot_valid (opcode); |
| 8414 | if (match_insn (insn, opcode, tokens, opcode_extra, |
| 8415 | lax_match, delay_slot_ok)) |
| 8416 | { |
| 8417 | if (!delay_slot_ok) |
| 8418 | { |
| 8419 | if (!invalid_delay_slot) |
| 8420 | invalid_delay_slot = opcode; |
| 8421 | } |
| 8422 | else |
| 8423 | return TRUE; |
| 8424 | } |
| 8425 | } |
| 8426 | } |
| 8427 | ++opcode; |
| 8428 | } |
| 8429 | while (opcode < past && strcmp (opcode->name, first->name) == 0); |
| 8430 | |
| 8431 | /* If the only matches we found had the wrong length for the delay slot, |
| 8432 | pick the first such match. We'll issue an appropriate warning later. */ |
| 8433 | if (invalid_delay_slot) |
| 8434 | { |
| 8435 | if (match_insn (insn, invalid_delay_slot, tokens, opcode_extra, |
| 8436 | lax_match, TRUE)) |
| 8437 | return TRUE; |
| 8438 | abort (); |
| 8439 | } |
| 8440 | |
| 8441 | /* Handle the case where we didn't try to match an instruction because |
| 8442 | all the alternatives were incompatible with the current ISA. */ |
| 8443 | if (!seen_valid_for_isa) |
| 8444 | { |
| 8445 | match_invalid_for_isa (); |
| 8446 | return TRUE; |
| 8447 | } |
| 8448 | |
| 8449 | /* Handle the case where we didn't try to match an instruction because |
| 8450 | all the alternatives were of the wrong size. */ |
| 8451 | if (!seen_valid_for_size) |
| 8452 | { |
| 8453 | if (mips_opts.insn32) |
| 8454 | set_insn_error (0, _("opcode not supported in the `insn32' mode")); |
| 8455 | else |
| 8456 | set_insn_error_i |
| 8457 | (0, _("unrecognized %d-bit version of microMIPS opcode"), |
| 8458 | 8 * forced_insn_length); |
| 8459 | return TRUE; |
| 8460 | } |
| 8461 | |
| 8462 | return FALSE; |
| 8463 | } |
| 8464 | |
| 8465 | /* Like match_insns, but for MIPS16. */ |
| 8466 | |
| 8467 | static bfd_boolean |
| 8468 | match_mips16_insns (struct mips_cl_insn *insn, const struct mips_opcode *first, |
| 8469 | struct mips_operand_token *tokens) |
| 8470 | { |
| 8471 | const struct mips_opcode *opcode; |
| 8472 | bfd_boolean seen_valid_for_isa; |
| 8473 | bfd_boolean seen_valid_for_size; |
| 8474 | |
| 8475 | /* Search for a match, ignoring alternatives that don't satisfy the |
| 8476 | current ISA. There are no separate entries for extended forms so |
| 8477 | we deal with forced_length later. */ |
| 8478 | seen_valid_for_isa = FALSE; |
| 8479 | seen_valid_for_size = FALSE; |
| 8480 | opcode = first; |
| 8481 | do |
| 8482 | { |
| 8483 | gas_assert (strcmp (opcode->name, first->name) == 0); |
| 8484 | if (is_opcode_valid_16 (opcode)) |
| 8485 | { |
| 8486 | seen_valid_for_isa = TRUE; |
| 8487 | if (is_size_valid_16 (opcode)) |
| 8488 | { |
| 8489 | seen_valid_for_size = TRUE; |
| 8490 | if (match_mips16_insn (insn, opcode, tokens)) |
| 8491 | return TRUE; |
| 8492 | } |
| 8493 | } |
| 8494 | ++opcode; |
| 8495 | } |
| 8496 | while (opcode < &mips16_opcodes[bfd_mips16_num_opcodes] |
| 8497 | && strcmp (opcode->name, first->name) == 0); |
| 8498 | |
| 8499 | /* Handle the case where we didn't try to match an instruction because |
| 8500 | all the alternatives were incompatible with the current ISA. */ |
| 8501 | if (!seen_valid_for_isa) |
| 8502 | { |
| 8503 | match_invalid_for_isa (); |
| 8504 | return TRUE; |
| 8505 | } |
| 8506 | |
| 8507 | /* Handle the case where we didn't try to match an instruction because |
| 8508 | all the alternatives were of the wrong size. */ |
| 8509 | if (!seen_valid_for_size) |
| 8510 | { |
| 8511 | if (forced_insn_length == 2) |
| 8512 | set_insn_error |
| 8513 | (0, _("unrecognized unextended version of MIPS16 opcode")); |
| 8514 | else |
| 8515 | set_insn_error |
| 8516 | (0, _("unrecognized extended version of MIPS16 opcode")); |
| 8517 | return TRUE; |
| 8518 | } |
| 8519 | |
| 8520 | return FALSE; |
| 8521 | } |
| 8522 | |
| 8523 | /* Set up global variables for the start of a new macro. */ |
| 8524 | |
| 8525 | static void |
| 8526 | macro_start (void) |
| 8527 | { |
| 8528 | memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes)); |
| 8529 | memset (&mips_macro_warning.first_insn_sizes, 0, |
| 8530 | sizeof (mips_macro_warning.first_insn_sizes)); |
| 8531 | memset (&mips_macro_warning.insns, 0, sizeof (mips_macro_warning.insns)); |
| 8532 | mips_macro_warning.delay_slot_p = (mips_opts.noreorder |
| 8533 | && delayed_branch_p (&history[0])); |
| 8534 | if (history[0].frag |
| 8535 | && history[0].frag->fr_type == rs_machine_dependent |
| 8536 | && RELAX_MICROMIPS_P (history[0].frag->fr_subtype) |
| 8537 | && RELAX_MICROMIPS_NODS (history[0].frag->fr_subtype)) |
| 8538 | mips_macro_warning.delay_slot_length = 0; |
| 8539 | else |
| 8540 | switch (history[0].insn_mo->pinfo2 |
| 8541 | & (INSN2_BRANCH_DELAY_32BIT | INSN2_BRANCH_DELAY_16BIT)) |
| 8542 | { |
| 8543 | case INSN2_BRANCH_DELAY_32BIT: |
| 8544 | mips_macro_warning.delay_slot_length = 4; |
| 8545 | break; |
| 8546 | case INSN2_BRANCH_DELAY_16BIT: |
| 8547 | mips_macro_warning.delay_slot_length = 2; |
| 8548 | break; |
| 8549 | default: |
| 8550 | mips_macro_warning.delay_slot_length = 0; |
| 8551 | break; |
| 8552 | } |
| 8553 | mips_macro_warning.first_frag = NULL; |
| 8554 | } |
| 8555 | |
| 8556 | /* Given that a macro is longer than one instruction or of the wrong size, |
| 8557 | return the appropriate warning for it. Return null if no warning is |
| 8558 | needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT, |
| 8559 | RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND, |
| 8560 | and RELAX_NOMACRO. */ |
| 8561 | |
| 8562 | static const char * |
| 8563 | macro_warning (relax_substateT subtype) |
| 8564 | { |
| 8565 | if (subtype & RELAX_DELAY_SLOT) |
| 8566 | return _("macro instruction expanded into multiple instructions" |
| 8567 | " in a branch delay slot"); |
| 8568 | else if (subtype & RELAX_NOMACRO) |
| 8569 | return _("macro instruction expanded into multiple instructions"); |
| 8570 | else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST |
| 8571 | | RELAX_DELAY_SLOT_SIZE_SECOND)) |
| 8572 | return ((subtype & RELAX_DELAY_SLOT_16BIT) |
| 8573 | ? _("macro instruction expanded into a wrong size instruction" |
| 8574 | " in a 16-bit branch delay slot") |
| 8575 | : _("macro instruction expanded into a wrong size instruction" |
| 8576 | " in a 32-bit branch delay slot")); |
| 8577 | else |
| 8578 | return 0; |
| 8579 | } |
| 8580 | |
| 8581 | /* Finish up a macro. Emit warnings as appropriate. */ |
| 8582 | |
| 8583 | static void |
| 8584 | macro_end (void) |
| 8585 | { |
| 8586 | /* Relaxation warning flags. */ |
| 8587 | relax_substateT subtype = 0; |
| 8588 | |
| 8589 | /* Check delay slot size requirements. */ |
| 8590 | if (mips_macro_warning.delay_slot_length == 2) |
| 8591 | subtype |= RELAX_DELAY_SLOT_16BIT; |
| 8592 | if (mips_macro_warning.delay_slot_length != 0) |
| 8593 | { |
| 8594 | if (mips_macro_warning.delay_slot_length |
| 8595 | != mips_macro_warning.first_insn_sizes[0]) |
| 8596 | subtype |= RELAX_DELAY_SLOT_SIZE_FIRST; |
| 8597 | if (mips_macro_warning.delay_slot_length |
| 8598 | != mips_macro_warning.first_insn_sizes[1]) |
| 8599 | subtype |= RELAX_DELAY_SLOT_SIZE_SECOND; |
| 8600 | } |
| 8601 | |
| 8602 | /* Check instruction count requirements. */ |
| 8603 | if (mips_macro_warning.insns[0] > 1 || mips_macro_warning.insns[1] > 1) |
| 8604 | { |
| 8605 | if (mips_macro_warning.insns[1] > mips_macro_warning.insns[0]) |
| 8606 | subtype |= RELAX_SECOND_LONGER; |
| 8607 | if (mips_opts.warn_about_macros) |
| 8608 | subtype |= RELAX_NOMACRO; |
| 8609 | if (mips_macro_warning.delay_slot_p) |
| 8610 | subtype |= RELAX_DELAY_SLOT; |
| 8611 | } |
| 8612 | |
| 8613 | /* If both alternatives fail to fill a delay slot correctly, |
| 8614 | emit the warning now. */ |
| 8615 | if ((subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0 |
| 8616 | && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0) |
| 8617 | { |
| 8618 | relax_substateT s; |
| 8619 | const char *msg; |
| 8620 | |
| 8621 | s = subtype & (RELAX_DELAY_SLOT_16BIT |
| 8622 | | RELAX_DELAY_SLOT_SIZE_FIRST |
| 8623 | | RELAX_DELAY_SLOT_SIZE_SECOND); |
| 8624 | msg = macro_warning (s); |
| 8625 | if (msg != NULL) |
| 8626 | as_warn ("%s", msg); |
| 8627 | subtype &= ~s; |
| 8628 | } |
| 8629 | |
| 8630 | /* If both implementations are longer than 1 instruction, then emit the |
| 8631 | warning now. */ |
| 8632 | if (mips_macro_warning.insns[0] > 1 && mips_macro_warning.insns[1] > 1) |
| 8633 | { |
| 8634 | relax_substateT s; |
| 8635 | const char *msg; |
| 8636 | |
| 8637 | s = subtype & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT); |
| 8638 | msg = macro_warning (s); |
| 8639 | if (msg != NULL) |
| 8640 | as_warn ("%s", msg); |
| 8641 | subtype &= ~s; |
| 8642 | } |
| 8643 | |
| 8644 | /* If any flags still set, then one implementation might need a warning |
| 8645 | and the other either will need one of a different kind or none at all. |
| 8646 | Pass any remaining flags over to relaxation. */ |
| 8647 | if (mips_macro_warning.first_frag != NULL) |
| 8648 | mips_macro_warning.first_frag->fr_subtype |= subtype; |
| 8649 | } |
| 8650 | |
| 8651 | /* Instruction operand formats used in macros that vary between |
| 8652 | standard MIPS and microMIPS code. */ |
| 8653 | |
| 8654 | static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } }; |
| 8655 | static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" }; |
| 8656 | static const char * const jalr_fmt[2] = { "d,s", "t,s" }; |
| 8657 | static const char * const lui_fmt[2] = { "t,u", "s,u" }; |
| 8658 | static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" }; |
| 8659 | static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } }; |
| 8660 | static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" }; |
| 8661 | static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" }; |
| 8662 | |
| 8663 | #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32]) |
| 8664 | #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \ |
| 8665 | : cop12_fmt[mips_opts.micromips]) |
| 8666 | #define JALR_FMT (jalr_fmt[mips_opts.micromips]) |
| 8667 | #define LUI_FMT (lui_fmt[mips_opts.micromips]) |
| 8668 | #define MEM12_FMT (mem12_fmt[mips_opts.micromips]) |
| 8669 | #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \ |
| 8670 | : mem12_fmt[mips_opts.micromips]) |
| 8671 | #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32]) |
| 8672 | #define SHFT_FMT (shft_fmt[mips_opts.micromips]) |
| 8673 | #define TRAP_FMT (trap_fmt[mips_opts.micromips]) |
| 8674 | |
| 8675 | /* Read a macro's relocation codes from *ARGS and store them in *R. |
| 8676 | The first argument in *ARGS will be either the code for a single |
| 8677 | relocation or -1 followed by the three codes that make up a |
| 8678 | composite relocation. */ |
| 8679 | |
| 8680 | static void |
| 8681 | macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) |
| 8682 | { |
| 8683 | int i, next; |
| 8684 | |
| 8685 | next = va_arg (*args, int); |
| 8686 | if (next >= 0) |
| 8687 | r[0] = (bfd_reloc_code_real_type) next; |
| 8688 | else |
| 8689 | { |
| 8690 | for (i = 0; i < 3; i++) |
| 8691 | r[i] = (bfd_reloc_code_real_type) va_arg (*args, int); |
| 8692 | /* This function is only used for 16-bit relocation fields. |
| 8693 | To make the macro code simpler, treat an unrelocated value |
| 8694 | in the same way as BFD_RELOC_LO16. */ |
| 8695 | if (r[0] == BFD_RELOC_UNUSED) |
| 8696 | r[0] = BFD_RELOC_LO16; |
| 8697 | } |
| 8698 | } |
| 8699 | |
| 8700 | /* Build an instruction created by a macro expansion. This is passed |
| 8701 | a pointer to the count of instructions created so far, an |
| 8702 | expression, the name of the instruction to build, an operand format |
| 8703 | string, and corresponding arguments. */ |
| 8704 | |
| 8705 | static void |
| 8706 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) |
| 8707 | { |
| 8708 | const struct mips_opcode *mo = NULL; |
| 8709 | bfd_reloc_code_real_type r[3]; |
| 8710 | const struct mips_opcode *amo; |
| 8711 | const struct mips_operand *operand; |
| 8712 | struct hash_control *hash; |
| 8713 | struct mips_cl_insn insn; |
| 8714 | va_list args; |
| 8715 | unsigned int uval; |
| 8716 | |
| 8717 | va_start (args, fmt); |
| 8718 | |
| 8719 | if (mips_opts.mips16) |
| 8720 | { |
| 8721 | mips16_macro_build (ep, name, fmt, &args); |
| 8722 | va_end (args); |
| 8723 | return; |
| 8724 | } |
| 8725 | |
| 8726 | r[0] = BFD_RELOC_UNUSED; |
| 8727 | r[1] = BFD_RELOC_UNUSED; |
| 8728 | r[2] = BFD_RELOC_UNUSED; |
| 8729 | hash = mips_opts.micromips ? micromips_op_hash : op_hash; |
| 8730 | amo = (struct mips_opcode *) hash_find (hash, name); |
| 8731 | gas_assert (amo); |
| 8732 | gas_assert (strcmp (name, amo->name) == 0); |
| 8733 | |
| 8734 | do |
| 8735 | { |
| 8736 | /* Search until we get a match for NAME. It is assumed here that |
| 8737 | macros will never generate MDMX, MIPS-3D, or MT instructions. |
| 8738 | We try to match an instruction that fulfills the branch delay |
| 8739 | slot instruction length requirement (if any) of the previous |
| 8740 | instruction. While doing this we record the first instruction |
| 8741 | seen that matches all the other conditions and use it anyway |
| 8742 | if the requirement cannot be met; we will issue an appropriate |
| 8743 | warning later on. */ |
| 8744 | if (strcmp (fmt, amo->args) == 0 |
| 8745 | && amo->pinfo != INSN_MACRO |
| 8746 | && is_opcode_valid (amo) |
| 8747 | && is_size_valid (amo)) |
| 8748 | { |
| 8749 | if (is_delay_slot_valid (amo)) |
| 8750 | { |
| 8751 | mo = amo; |
| 8752 | break; |
| 8753 | } |
| 8754 | else if (!mo) |
| 8755 | mo = amo; |
| 8756 | } |
| 8757 | |
| 8758 | ++amo; |
| 8759 | gas_assert (amo->name); |
| 8760 | } |
| 8761 | while (strcmp (name, amo->name) == 0); |
| 8762 | |
| 8763 | gas_assert (mo); |
| 8764 | create_insn (&insn, mo); |
| 8765 | for (; *fmt; ++fmt) |
| 8766 | { |
| 8767 | switch (*fmt) |
| 8768 | { |
| 8769 | case ',': |
| 8770 | case '(': |
| 8771 | case ')': |
| 8772 | case 'z': |
| 8773 | break; |
| 8774 | |
| 8775 | case 'i': |
| 8776 | case 'j': |
| 8777 | macro_read_relocs (&args, r); |
| 8778 | gas_assert (*r == BFD_RELOC_GPREL16 |
| 8779 | || *r == BFD_RELOC_MIPS_HIGHER |
| 8780 | || *r == BFD_RELOC_HI16_S |
| 8781 | || *r == BFD_RELOC_LO16 |
| 8782 | || *r == BFD_RELOC_MIPS_GOT_OFST); |
| 8783 | break; |
| 8784 | |
| 8785 | case 'o': |
| 8786 | macro_read_relocs (&args, r); |
| 8787 | break; |
| 8788 | |
| 8789 | case 'u': |
| 8790 | macro_read_relocs (&args, r); |
| 8791 | gas_assert (ep != NULL |
| 8792 | && (ep->X_op == O_constant |
| 8793 | || (ep->X_op == O_symbol |
| 8794 | && (*r == BFD_RELOC_MIPS_HIGHEST |
| 8795 | || *r == BFD_RELOC_HI16_S |
| 8796 | || *r == BFD_RELOC_HI16 |
| 8797 | || *r == BFD_RELOC_GPREL16 |
| 8798 | || *r == BFD_RELOC_MIPS_GOT_HI16 |
| 8799 | || *r == BFD_RELOC_MIPS_CALL_HI16)))); |
| 8800 | break; |
| 8801 | |
| 8802 | case 'p': |
| 8803 | gas_assert (ep != NULL); |
| 8804 | |
| 8805 | /* |
| 8806 | * This allows macro() to pass an immediate expression for |
| 8807 | * creating short branches without creating a symbol. |
| 8808 | * |
| 8809 | * We don't allow branch relaxation for these branches, as |
| 8810 | * they should only appear in ".set nomacro" anyway. |
| 8811 | */ |
| 8812 | if (ep->X_op == O_constant) |
| 8813 | { |
| 8814 | /* For microMIPS we always use relocations for branches. |
| 8815 | So we should not resolve immediate values. */ |
| 8816 | gas_assert (!mips_opts.micromips); |
| 8817 | |
| 8818 | if ((ep->X_add_number & 3) != 0) |
| 8819 | as_bad (_("branch to misaligned address (0x%lx)"), |
| 8820 | (unsigned long) ep->X_add_number); |
| 8821 | if ((ep->X_add_number + 0x20000) & ~0x3ffff) |
| 8822 | as_bad (_("branch address range overflow (0x%lx)"), |
| 8823 | (unsigned long) ep->X_add_number); |
| 8824 | insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff; |
| 8825 | ep = NULL; |
| 8826 | } |
| 8827 | else |
| 8828 | *r = BFD_RELOC_16_PCREL_S2; |
| 8829 | break; |
| 8830 | |
| 8831 | case 'a': |
| 8832 | gas_assert (ep != NULL); |
| 8833 | *r = BFD_RELOC_MIPS_JMP; |
| 8834 | break; |
| 8835 | |
| 8836 | default: |
| 8837 | operand = (mips_opts.micromips |
| 8838 | ? decode_micromips_operand (fmt) |
| 8839 | : decode_mips_operand (fmt)); |
| 8840 | if (!operand) |
| 8841 | abort (); |
| 8842 | |
| 8843 | uval = va_arg (args, int); |
| 8844 | if (operand->type == OP_CLO_CLZ_DEST) |
| 8845 | uval |= (uval << 5); |
| 8846 | insn_insert_operand (&insn, operand, uval); |
| 8847 | |
| 8848 | if (*fmt == '+' || *fmt == 'm' || *fmt == '-') |
| 8849 | ++fmt; |
| 8850 | break; |
| 8851 | } |
| 8852 | } |
| 8853 | va_end (args); |
| 8854 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
| 8855 | |
| 8856 | append_insn (&insn, ep, r, TRUE); |
| 8857 | } |
| 8858 | |
| 8859 | static void |
| 8860 | mips16_macro_build (expressionS *ep, const char *name, const char *fmt, |
| 8861 | va_list *args) |
| 8862 | { |
| 8863 | struct mips_opcode *mo; |
| 8864 | struct mips_cl_insn insn; |
| 8865 | const struct mips_operand *operand; |
| 8866 | bfd_reloc_code_real_type r[3] |
| 8867 | = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; |
| 8868 | |
| 8869 | mo = (struct mips_opcode *) hash_find (mips16_op_hash, name); |
| 8870 | gas_assert (mo); |
| 8871 | gas_assert (strcmp (name, mo->name) == 0); |
| 8872 | |
| 8873 | while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO) |
| 8874 | { |
| 8875 | ++mo; |
| 8876 | gas_assert (mo->name); |
| 8877 | gas_assert (strcmp (name, mo->name) == 0); |
| 8878 | } |
| 8879 | |
| 8880 | create_insn (&insn, mo); |
| 8881 | for (; *fmt; ++fmt) |
| 8882 | { |
| 8883 | int c; |
| 8884 | |
| 8885 | c = *fmt; |
| 8886 | switch (c) |
| 8887 | { |
| 8888 | case ',': |
| 8889 | case '(': |
| 8890 | case ')': |
| 8891 | break; |
| 8892 | |
| 8893 | case '.': |
| 8894 | case 'S': |
| 8895 | case 'P': |
| 8896 | case 'R': |
| 8897 | break; |
| 8898 | |
| 8899 | case '<': |
| 8900 | case '5': |
| 8901 | case 'F': |
| 8902 | case 'H': |
| 8903 | case 'W': |
| 8904 | case 'D': |
| 8905 | case 'j': |
| 8906 | case '8': |
| 8907 | case 'V': |
| 8908 | case 'C': |
| 8909 | case 'U': |
| 8910 | case 'k': |
| 8911 | case 'K': |
| 8912 | case 'p': |
| 8913 | case 'q': |
| 8914 | { |
| 8915 | offsetT value; |
| 8916 | |
| 8917 | gas_assert (ep != NULL); |
| 8918 | |
| 8919 | if (ep->X_op != O_constant) |
| 8920 | *r = (int) BFD_RELOC_UNUSED + c; |
| 8921 | else if (calculate_reloc (*r, ep->X_add_number, &value)) |
| 8922 | { |
| 8923 | mips16_immed (NULL, 0, c, *r, value, 0, &insn.insn_opcode); |
| 8924 | ep = NULL; |
| 8925 | *r = BFD_RELOC_UNUSED; |
| 8926 | } |
| 8927 | } |
| 8928 | break; |
| 8929 | |
| 8930 | default: |
| 8931 | operand = decode_mips16_operand (c, FALSE); |
| 8932 | if (!operand) |
| 8933 | abort (); |
| 8934 | |
| 8935 | insn_insert_operand (&insn, operand, va_arg (*args, int)); |
| 8936 | break; |
| 8937 | } |
| 8938 | } |
| 8939 | |
| 8940 | gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); |
| 8941 | |
| 8942 | append_insn (&insn, ep, r, TRUE); |
| 8943 | } |
| 8944 | |
| 8945 | /* |
| 8946 | * Generate a "jalr" instruction with a relocation hint to the called |
| 8947 | * function. This occurs in NewABI PIC code. |
| 8948 | */ |
| 8949 | static void |
| 8950 | macro_build_jalr (expressionS *ep, int cprestore) |
| 8951 | { |
| 8952 | static const bfd_reloc_code_real_type jalr_relocs[2] |
| 8953 | = { BFD_RELOC_MIPS_JALR, BFD_RELOC_MICROMIPS_JALR }; |
| 8954 | bfd_reloc_code_real_type jalr_reloc = jalr_relocs[mips_opts.micromips]; |
| 8955 | const char *jalr; |
| 8956 | char *f = NULL; |
| 8957 | |
| 8958 | if (MIPS_JALR_HINT_P (ep)) |
| 8959 | { |
| 8960 | frag_grow (8); |
| 8961 | f = frag_more (0); |
| 8962 | } |
| 8963 | if (mips_opts.micromips) |
| 8964 | { |
| 8965 | jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32 |
| 8966 | ? "jalr" : "jalrs"); |
| 8967 | if (MIPS_JALR_HINT_P (ep) |
| 8968 | || mips_opts.insn32 |
| 8969 | || (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
| 8970 | macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG); |
| 8971 | else |
| 8972 | macro_build (NULL, jalr, "mj", PIC_CALL_REG); |
| 8973 | } |
| 8974 | else |
| 8975 | macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG); |
| 8976 | if (MIPS_JALR_HINT_P (ep)) |
| 8977 | fix_new_exp (frag_now, f - frag_now->fr_literal, 4, ep, FALSE, jalr_reloc); |
| 8978 | } |
| 8979 | |
| 8980 | /* |
| 8981 | * Generate a "lui" instruction. |
| 8982 | */ |
| 8983 | static void |
| 8984 | macro_build_lui (expressionS *ep, int regnum) |
| 8985 | { |
| 8986 | gas_assert (! mips_opts.mips16); |
| 8987 | |
| 8988 | if (ep->X_op != O_constant) |
| 8989 | { |
| 8990 | gas_assert (ep->X_op == O_symbol); |
| 8991 | /* _gp_disp is a special case, used from s_cpload. |
| 8992 | __gnu_local_gp is used if mips_no_shared. */ |
| 8993 | gas_assert (mips_pic == NO_PIC |
| 8994 | || (! HAVE_NEWABI |
| 8995 | && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0) |
| 8996 | || (! mips_in_shared |
| 8997 | && strcmp (S_GET_NAME (ep->X_add_symbol), |
| 8998 | "__gnu_local_gp") == 0)); |
| 8999 | } |
| 9000 | |
| 9001 | macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_HI16_S); |
| 9002 | } |
| 9003 | |
| 9004 | /* Generate a sequence of instructions to do a load or store from a constant |
| 9005 | offset off of a base register (breg) into/from a target register (treg), |
| 9006 | using AT if necessary. */ |
| 9007 | static void |
| 9008 | macro_build_ldst_constoffset (expressionS *ep, const char *op, |
| 9009 | int treg, int breg, int dbl) |
| 9010 | { |
| 9011 | gas_assert (ep->X_op == O_constant); |
| 9012 | |
| 9013 | /* Sign-extending 32-bit constants makes their handling easier. */ |
| 9014 | if (!dbl) |
| 9015 | normalize_constant_expr (ep); |
| 9016 | |
| 9017 | /* Right now, this routine can only handle signed 32-bit constants. */ |
| 9018 | if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000)) |
| 9019 | as_warn (_("operand overflow")); |
| 9020 | |
| 9021 | if (IS_SEXT_16BIT_NUM(ep->X_add_number)) |
| 9022 | { |
| 9023 | /* Signed 16-bit offset will fit in the op. Easy! */ |
| 9024 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg); |
| 9025 | } |
| 9026 | else |
| 9027 | { |
| 9028 | /* 32-bit offset, need multiple instructions and AT, like: |
| 9029 | lui $tempreg,const_hi (BFD_RELOC_HI16_S) |
| 9030 | addu $tempreg,$tempreg,$breg |
| 9031 | <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16) |
| 9032 | to handle the complete offset. */ |
| 9033 | macro_build_lui (ep, AT); |
| 9034 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg); |
| 9035 | macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT); |
| 9036 | |
| 9037 | if (!mips_opts.at) |
| 9038 | as_bad (_("macro used $at after \".set noat\"")); |
| 9039 | } |
| 9040 | } |
| 9041 | |
| 9042 | /* set_at() |
| 9043 | * Generates code to set the $at register to true (one) |
| 9044 | * if reg is less than the immediate expression. |
| 9045 | */ |
| 9046 | static void |
| 9047 | set_at (int reg, int unsignedp) |
| 9048 | { |
| 9049 | if (imm_expr.X_add_number >= -0x8000 |
| 9050 | && imm_expr.X_add_number < 0x8000) |
| 9051 | macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j", |
| 9052 | AT, reg, BFD_RELOC_LO16); |
| 9053 | else |
| 9054 | { |
| 9055 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 9056 | macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); |
| 9057 | } |
| 9058 | } |
| 9059 | |
| 9060 | /* Count the leading zeroes by performing a binary chop. This is a |
| 9061 | bulky bit of source, but performance is a LOT better for the |
| 9062 | majority of values than a simple loop to count the bits: |
| 9063 | for (lcnt = 0; (lcnt < 32); lcnt++) |
| 9064 | if ((v) & (1 << (31 - lcnt))) |
| 9065 | break; |
| 9066 | However it is not code size friendly, and the gain will drop a bit |
| 9067 | on certain cached systems. |
| 9068 | */ |
| 9069 | #define COUNT_TOP_ZEROES(v) \ |
| 9070 | (((v) & ~0xffff) == 0 \ |
| 9071 | ? ((v) & ~0xff) == 0 \ |
| 9072 | ? ((v) & ~0xf) == 0 \ |
| 9073 | ? ((v) & ~0x3) == 0 \ |
| 9074 | ? ((v) & ~0x1) == 0 \ |
| 9075 | ? !(v) \ |
| 9076 | ? 32 \ |
| 9077 | : 31 \ |
| 9078 | : 30 \ |
| 9079 | : ((v) & ~0x7) == 0 \ |
| 9080 | ? 29 \ |
| 9081 | : 28 \ |
| 9082 | : ((v) & ~0x3f) == 0 \ |
| 9083 | ? ((v) & ~0x1f) == 0 \ |
| 9084 | ? 27 \ |
| 9085 | : 26 \ |
| 9086 | : ((v) & ~0x7f) == 0 \ |
| 9087 | ? 25 \ |
| 9088 | : 24 \ |
| 9089 | : ((v) & ~0xfff) == 0 \ |
| 9090 | ? ((v) & ~0x3ff) == 0 \ |
| 9091 | ? ((v) & ~0x1ff) == 0 \ |
| 9092 | ? 23 \ |
| 9093 | : 22 \ |
| 9094 | : ((v) & ~0x7ff) == 0 \ |
| 9095 | ? 21 \ |
| 9096 | : 20 \ |
| 9097 | : ((v) & ~0x3fff) == 0 \ |
| 9098 | ? ((v) & ~0x1fff) == 0 \ |
| 9099 | ? 19 \ |
| 9100 | : 18 \ |
| 9101 | : ((v) & ~0x7fff) == 0 \ |
| 9102 | ? 17 \ |
| 9103 | : 16 \ |
| 9104 | : ((v) & ~0xffffff) == 0 \ |
| 9105 | ? ((v) & ~0xfffff) == 0 \ |
| 9106 | ? ((v) & ~0x3ffff) == 0 \ |
| 9107 | ? ((v) & ~0x1ffff) == 0 \ |
| 9108 | ? 15 \ |
| 9109 | : 14 \ |
| 9110 | : ((v) & ~0x7ffff) == 0 \ |
| 9111 | ? 13 \ |
| 9112 | : 12 \ |
| 9113 | : ((v) & ~0x3fffff) == 0 \ |
| 9114 | ? ((v) & ~0x1fffff) == 0 \ |
| 9115 | ? 11 \ |
| 9116 | : 10 \ |
| 9117 | : ((v) & ~0x7fffff) == 0 \ |
| 9118 | ? 9 \ |
| 9119 | : 8 \ |
| 9120 | : ((v) & ~0xfffffff) == 0 \ |
| 9121 | ? ((v) & ~0x3ffffff) == 0 \ |
| 9122 | ? ((v) & ~0x1ffffff) == 0 \ |
| 9123 | ? 7 \ |
| 9124 | : 6 \ |
| 9125 | : ((v) & ~0x7ffffff) == 0 \ |
| 9126 | ? 5 \ |
| 9127 | : 4 \ |
| 9128 | : ((v) & ~0x3fffffff) == 0 \ |
| 9129 | ? ((v) & ~0x1fffffff) == 0 \ |
| 9130 | ? 3 \ |
| 9131 | : 2 \ |
| 9132 | : ((v) & ~0x7fffffff) == 0 \ |
| 9133 | ? 1 \ |
| 9134 | : 0) |
| 9135 | |
| 9136 | /* load_register() |
| 9137 | * This routine generates the least number of instructions necessary to load |
| 9138 | * an absolute expression value into a register. |
| 9139 | */ |
| 9140 | static void |
| 9141 | load_register (int reg, expressionS *ep, int dbl) |
| 9142 | { |
| 9143 | int freg; |
| 9144 | expressionS hi32, lo32; |
| 9145 | |
| 9146 | if (ep->X_op != O_big) |
| 9147 | { |
| 9148 | gas_assert (ep->X_op == O_constant); |
| 9149 | |
| 9150 | /* Sign-extending 32-bit constants makes their handling easier. */ |
| 9151 | if (!dbl) |
| 9152 | normalize_constant_expr (ep); |
| 9153 | |
| 9154 | if (IS_SEXT_16BIT_NUM (ep->X_add_number)) |
| 9155 | { |
| 9156 | /* We can handle 16 bit signed values with an addiu to |
| 9157 | $zero. No need to ever use daddiu here, since $zero and |
| 9158 | the result are always correct in 32 bit mode. */ |
| 9159 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
| 9160 | return; |
| 9161 | } |
| 9162 | else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000) |
| 9163 | { |
| 9164 | /* We can handle 16 bit unsigned values with an ori to |
| 9165 | $zero. */ |
| 9166 | macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
| 9167 | return; |
| 9168 | } |
| 9169 | else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) |
| 9170 | { |
| 9171 | /* 32 bit values require an lui. */ |
| 9172 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
| 9173 | if ((ep->X_add_number & 0xffff) != 0) |
| 9174 | macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
| 9175 | return; |
| 9176 | } |
| 9177 | } |
| 9178 | |
| 9179 | /* The value is larger than 32 bits. */ |
| 9180 | |
| 9181 | if (!dbl || GPR_SIZE == 32) |
| 9182 | { |
| 9183 | char value[32]; |
| 9184 | |
| 9185 | sprintf_vma (value, ep->X_add_number); |
| 9186 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
| 9187 | macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
| 9188 | return; |
| 9189 | } |
| 9190 | |
| 9191 | if (ep->X_op != O_big) |
| 9192 | { |
| 9193 | hi32 = *ep; |
| 9194 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
| 9195 | hi32.X_add_number = (valueT) hi32.X_add_number >> 16; |
| 9196 | hi32.X_add_number &= 0xffffffff; |
| 9197 | lo32 = *ep; |
| 9198 | lo32.X_add_number &= 0xffffffff; |
| 9199 | } |
| 9200 | else |
| 9201 | { |
| 9202 | gas_assert (ep->X_add_number > 2); |
| 9203 | if (ep->X_add_number == 3) |
| 9204 | generic_bignum[3] = 0; |
| 9205 | else if (ep->X_add_number > 4) |
| 9206 | as_bad (_("number larger than 64 bits")); |
| 9207 | lo32.X_op = O_constant; |
| 9208 | lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16); |
| 9209 | hi32.X_op = O_constant; |
| 9210 | hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16); |
| 9211 | } |
| 9212 | |
| 9213 | if (hi32.X_add_number == 0) |
| 9214 | freg = 0; |
| 9215 | else |
| 9216 | { |
| 9217 | int shift, bit; |
| 9218 | unsigned long hi, lo; |
| 9219 | |
| 9220 | if (hi32.X_add_number == (offsetT) 0xffffffff) |
| 9221 | { |
| 9222 | if ((lo32.X_add_number & 0xffff8000) == 0xffff8000) |
| 9223 | { |
| 9224 | macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
| 9225 | return; |
| 9226 | } |
| 9227 | if (lo32.X_add_number & 0x80000000) |
| 9228 | { |
| 9229 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
| 9230 | if (lo32.X_add_number & 0xffff) |
| 9231 | macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16); |
| 9232 | return; |
| 9233 | } |
| 9234 | } |
| 9235 | |
| 9236 | /* Check for 16bit shifted constant. We know that hi32 is |
| 9237 | non-zero, so start the mask on the first bit of the hi32 |
| 9238 | value. */ |
| 9239 | shift = 17; |
| 9240 | do |
| 9241 | { |
| 9242 | unsigned long himask, lomask; |
| 9243 | |
| 9244 | if (shift < 32) |
| 9245 | { |
| 9246 | himask = 0xffff >> (32 - shift); |
| 9247 | lomask = (0xffff << shift) & 0xffffffff; |
| 9248 | } |
| 9249 | else |
| 9250 | { |
| 9251 | himask = 0xffff << (shift - 32); |
| 9252 | lomask = 0; |
| 9253 | } |
| 9254 | if ((hi32.X_add_number & ~(offsetT) himask) == 0 |
| 9255 | && (lo32.X_add_number & ~(offsetT) lomask) == 0) |
| 9256 | { |
| 9257 | expressionS tmp; |
| 9258 | |
| 9259 | tmp.X_op = O_constant; |
| 9260 | if (shift < 32) |
| 9261 | tmp.X_add_number = ((hi32.X_add_number << (32 - shift)) |
| 9262 | | (lo32.X_add_number >> shift)); |
| 9263 | else |
| 9264 | tmp.X_add_number = hi32.X_add_number >> (shift - 32); |
| 9265 | macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16); |
| 9266 | macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
| 9267 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
| 9268 | return; |
| 9269 | } |
| 9270 | ++shift; |
| 9271 | } |
| 9272 | while (shift <= (64 - 16)); |
| 9273 | |
| 9274 | /* Find the bit number of the lowest one bit, and store the |
| 9275 | shifted value in hi/lo. */ |
| 9276 | hi = (unsigned long) (hi32.X_add_number & 0xffffffff); |
| 9277 | lo = (unsigned long) (lo32.X_add_number & 0xffffffff); |
| 9278 | if (lo != 0) |
| 9279 | { |
| 9280 | bit = 0; |
| 9281 | while ((lo & 1) == 0) |
| 9282 | { |
| 9283 | lo >>= 1; |
| 9284 | ++bit; |
| 9285 | } |
| 9286 | lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit); |
| 9287 | hi >>= bit; |
| 9288 | } |
| 9289 | else |
| 9290 | { |
| 9291 | bit = 32; |
| 9292 | while ((hi & 1) == 0) |
| 9293 | { |
| 9294 | hi >>= 1; |
| 9295 | ++bit; |
| 9296 | } |
| 9297 | lo = hi; |
| 9298 | hi = 0; |
| 9299 | } |
| 9300 | |
| 9301 | /* Optimize if the shifted value is a (power of 2) - 1. */ |
| 9302 | if ((hi == 0 && ((lo + 1) & lo) == 0) |
| 9303 | || (lo == 0xffffffff && ((hi + 1) & hi) == 0)) |
| 9304 | { |
| 9305 | shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number); |
| 9306 | if (shift != 0) |
| 9307 | { |
| 9308 | expressionS tmp; |
| 9309 | |
| 9310 | /* This instruction will set the register to be all |
| 9311 | ones. */ |
| 9312 | tmp.X_op = O_constant; |
| 9313 | tmp.X_add_number = (offsetT) -1; |
| 9314 | macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16); |
| 9315 | if (bit != 0) |
| 9316 | { |
| 9317 | bit += shift; |
| 9318 | macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", SHFT_FMT, |
| 9319 | reg, reg, (bit >= 32) ? bit - 32 : bit); |
| 9320 | } |
| 9321 | macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", SHFT_FMT, |
| 9322 | reg, reg, (shift >= 32) ? shift - 32 : shift); |
| 9323 | return; |
| 9324 | } |
| 9325 | } |
| 9326 | |
| 9327 | /* Sign extend hi32 before calling load_register, because we can |
| 9328 | generally get better code when we load a sign extended value. */ |
| 9329 | if ((hi32.X_add_number & 0x80000000) != 0) |
| 9330 | hi32.X_add_number |= ~(offsetT) 0xffffffff; |
| 9331 | load_register (reg, &hi32, 0); |
| 9332 | freg = reg; |
| 9333 | } |
| 9334 | if ((lo32.X_add_number & 0xffff0000) == 0) |
| 9335 | { |
| 9336 | if (freg != 0) |
| 9337 | { |
| 9338 | macro_build (NULL, "dsll32", SHFT_FMT, reg, freg, 0); |
| 9339 | freg = reg; |
| 9340 | } |
| 9341 | } |
| 9342 | else |
| 9343 | { |
| 9344 | expressionS mid16; |
| 9345 | |
| 9346 | if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff)) |
| 9347 | { |
| 9348 | macro_build (&lo32, "lui", LUI_FMT, reg, BFD_RELOC_HI16); |
| 9349 | macro_build (NULL, "dsrl32", SHFT_FMT, reg, reg, 0); |
| 9350 | return; |
| 9351 | } |
| 9352 | |
| 9353 | if (freg != 0) |
| 9354 | { |
| 9355 | macro_build (NULL, "dsll", SHFT_FMT, reg, freg, 16); |
| 9356 | freg = reg; |
| 9357 | } |
| 9358 | mid16 = lo32; |
| 9359 | mid16.X_add_number >>= 16; |
| 9360 | macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
| 9361 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
| 9362 | freg = reg; |
| 9363 | } |
| 9364 | if ((lo32.X_add_number & 0xffff) != 0) |
| 9365 | macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16); |
| 9366 | } |
| 9367 | |
| 9368 | static inline void |
| 9369 | load_delay_nop (void) |
| 9370 | { |
| 9371 | if (!gpr_interlocks) |
| 9372 | macro_build (NULL, "nop", ""); |
| 9373 | } |
| 9374 | |
| 9375 | /* Load an address into a register. */ |
| 9376 | |
| 9377 | static void |
| 9378 | load_address (int reg, expressionS *ep, int *used_at) |
| 9379 | { |
| 9380 | if (ep->X_op != O_constant |
| 9381 | && ep->X_op != O_symbol) |
| 9382 | { |
| 9383 | as_bad (_("expression too complex")); |
| 9384 | ep->X_op = O_constant; |
| 9385 | } |
| 9386 | |
| 9387 | if (ep->X_op == O_constant) |
| 9388 | { |
| 9389 | load_register (reg, ep, HAVE_64BIT_ADDRESSES); |
| 9390 | return; |
| 9391 | } |
| 9392 | |
| 9393 | if (mips_pic == NO_PIC) |
| 9394 | { |
| 9395 | /* If this is a reference to a GP relative symbol, we want |
| 9396 | addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16) |
| 9397 | Otherwise we want |
| 9398 | lui $reg,<sym> (BFD_RELOC_HI16_S) |
| 9399 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
| 9400 | If we have an addend, we always use the latter form. |
| 9401 | |
| 9402 | With 64bit address space and a usable $at we want |
| 9403 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 9404 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 9405 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 9406 | daddiu $at,<sym> (BFD_RELOC_LO16) |
| 9407 | dsll32 $reg,0 |
| 9408 | daddu $reg,$reg,$at |
| 9409 | |
| 9410 | If $at is already in use, we use a path which is suboptimal |
| 9411 | on superscalar processors. |
| 9412 | lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 9413 | daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 9414 | dsll $reg,16 |
| 9415 | daddiu $reg,<sym> (BFD_RELOC_HI16_S) |
| 9416 | dsll $reg,16 |
| 9417 | daddiu $reg,<sym> (BFD_RELOC_LO16) |
| 9418 | |
| 9419 | For GP relative symbols in 64bit address space we can use |
| 9420 | the same sequence as in 32bit address space. */ |
| 9421 | if (HAVE_64BIT_SYMBOLS) |
| 9422 | { |
| 9423 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
| 9424 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
| 9425 | { |
| 9426 | relax_start (ep->X_add_symbol); |
| 9427 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
| 9428 | mips_gp_register, BFD_RELOC_GPREL16); |
| 9429 | relax_switch (); |
| 9430 | } |
| 9431 | |
| 9432 | if (*used_at == 0 && mips_opts.at) |
| 9433 | { |
| 9434 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
| 9435 | macro_build (ep, "lui", LUI_FMT, AT, BFD_RELOC_HI16_S); |
| 9436 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
| 9437 | BFD_RELOC_MIPS_HIGHER); |
| 9438 | macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16); |
| 9439 | macro_build (NULL, "dsll32", SHFT_FMT, reg, reg, 0); |
| 9440 | macro_build (NULL, "daddu", "d,v,t", reg, reg, AT); |
| 9441 | *used_at = 1; |
| 9442 | } |
| 9443 | else |
| 9444 | { |
| 9445 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_HIGHEST); |
| 9446 | macro_build (ep, "daddiu", "t,r,j", reg, reg, |
| 9447 | BFD_RELOC_MIPS_HIGHER); |
| 9448 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
| 9449 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S); |
| 9450 | macro_build (NULL, "dsll", SHFT_FMT, reg, reg, 16); |
| 9451 | macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16); |
| 9452 | } |
| 9453 | |
| 9454 | if (mips_relax.sequence) |
| 9455 | relax_end (); |
| 9456 | } |
| 9457 | else |
| 9458 | { |
| 9459 | if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET |
| 9460 | && !nopic_need_relax (ep->X_add_symbol, 1)) |
| 9461 | { |
| 9462 | relax_start (ep->X_add_symbol); |
| 9463 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, |
| 9464 | mips_gp_register, BFD_RELOC_GPREL16); |
| 9465 | relax_switch (); |
| 9466 | } |
| 9467 | macro_build_lui (ep, reg); |
| 9468 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", |
| 9469 | reg, reg, BFD_RELOC_LO16); |
| 9470 | if (mips_relax.sequence) |
| 9471 | relax_end (); |
| 9472 | } |
| 9473 | } |
| 9474 | else if (!mips_big_got) |
| 9475 | { |
| 9476 | expressionS ex; |
| 9477 | |
| 9478 | /* If this is a reference to an external symbol, we want |
| 9479 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 9480 | Otherwise we want |
| 9481 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 9482 | nop |
| 9483 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
| 9484 | If there is a constant, it must be added in after. |
| 9485 | |
| 9486 | If we have NewABI, we want |
| 9487 | lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
| 9488 | unless we're referencing a global symbol with a non-zero |
| 9489 | offset, in which case cst must be added separately. */ |
| 9490 | if (HAVE_NEWABI) |
| 9491 | { |
| 9492 | if (ep->X_add_number) |
| 9493 | { |
| 9494 | ex.X_add_number = ep->X_add_number; |
| 9495 | ep->X_add_number = 0; |
| 9496 | relax_start (ep->X_add_symbol); |
| 9497 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
| 9498 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
| 9499 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
| 9500 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 9501 | ex.X_op = O_constant; |
| 9502 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
| 9503 | reg, reg, BFD_RELOC_LO16); |
| 9504 | ep->X_add_number = ex.X_add_number; |
| 9505 | relax_switch (); |
| 9506 | } |
| 9507 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
| 9508 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
| 9509 | if (mips_relax.sequence) |
| 9510 | relax_end (); |
| 9511 | } |
| 9512 | else |
| 9513 | { |
| 9514 | ex.X_add_number = ep->X_add_number; |
| 9515 | ep->X_add_number = 0; |
| 9516 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
| 9517 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 9518 | load_delay_nop (); |
| 9519 | relax_start (ep->X_add_symbol); |
| 9520 | relax_switch (); |
| 9521 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
| 9522 | BFD_RELOC_LO16); |
| 9523 | relax_end (); |
| 9524 | |
| 9525 | if (ex.X_add_number != 0) |
| 9526 | { |
| 9527 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
| 9528 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 9529 | ex.X_op = O_constant; |
| 9530 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", |
| 9531 | reg, reg, BFD_RELOC_LO16); |
| 9532 | } |
| 9533 | } |
| 9534 | } |
| 9535 | else if (mips_big_got) |
| 9536 | { |
| 9537 | expressionS ex; |
| 9538 | |
| 9539 | /* This is the large GOT case. If this is a reference to an |
| 9540 | external symbol, we want |
| 9541 | lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 9542 | addu $reg,$reg,$gp |
| 9543 | lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16) |
| 9544 | |
| 9545 | Otherwise, for a reference to a local symbol in old ABI, we want |
| 9546 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 9547 | nop |
| 9548 | addiu $reg,$reg,<sym> (BFD_RELOC_LO16) |
| 9549 | If there is a constant, it must be added in after. |
| 9550 | |
| 9551 | In the NewABI, for local symbols, with or without offsets, we want: |
| 9552 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
| 9553 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) |
| 9554 | */ |
| 9555 | if (HAVE_NEWABI) |
| 9556 | { |
| 9557 | ex.X_add_number = ep->X_add_number; |
| 9558 | ep->X_add_number = 0; |
| 9559 | relax_start (ep->X_add_symbol); |
| 9560 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
| 9561 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 9562 | reg, reg, mips_gp_register); |
| 9563 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", |
| 9564 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); |
| 9565 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
| 9566 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 9567 | else if (ex.X_add_number) |
| 9568 | { |
| 9569 | ex.X_op = O_constant; |
| 9570 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
| 9571 | BFD_RELOC_LO16); |
| 9572 | } |
| 9573 | |
| 9574 | ep->X_add_number = ex.X_add_number; |
| 9575 | relax_switch (); |
| 9576 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
| 9577 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
| 9578 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
| 9579 | BFD_RELOC_MIPS_GOT_OFST); |
| 9580 | relax_end (); |
| 9581 | } |
| 9582 | else |
| 9583 | { |
| 9584 | ex.X_add_number = ep->X_add_number; |
| 9585 | ep->X_add_number = 0; |
| 9586 | relax_start (ep->X_add_symbol); |
| 9587 | macro_build (ep, "lui", LUI_FMT, reg, BFD_RELOC_MIPS_GOT_HI16); |
| 9588 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 9589 | reg, reg, mips_gp_register); |
| 9590 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", |
| 9591 | reg, BFD_RELOC_MIPS_GOT_LO16, reg); |
| 9592 | relax_switch (); |
| 9593 | if (reg_needs_delay (mips_gp_register)) |
| 9594 | { |
| 9595 | /* We need a nop before loading from $gp. This special |
| 9596 | check is required because the lui which starts the main |
| 9597 | instruction stream does not refer to $gp, and so will not |
| 9598 | insert the nop which may be required. */ |
| 9599 | macro_build (NULL, "nop", ""); |
| 9600 | } |
| 9601 | macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg, |
| 9602 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 9603 | load_delay_nop (); |
| 9604 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
| 9605 | BFD_RELOC_LO16); |
| 9606 | relax_end (); |
| 9607 | |
| 9608 | if (ex.X_add_number != 0) |
| 9609 | { |
| 9610 | if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000) |
| 9611 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 9612 | ex.X_op = O_constant; |
| 9613 | macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg, |
| 9614 | BFD_RELOC_LO16); |
| 9615 | } |
| 9616 | } |
| 9617 | } |
| 9618 | else |
| 9619 | abort (); |
| 9620 | |
| 9621 | if (!mips_opts.at && *used_at == 1) |
| 9622 | as_bad (_("macro used $at after \".set noat\"")); |
| 9623 | } |
| 9624 | |
| 9625 | /* Move the contents of register SOURCE into register DEST. */ |
| 9626 | |
| 9627 | static void |
| 9628 | move_register (int dest, int source) |
| 9629 | { |
| 9630 | /* Prefer to use a 16-bit microMIPS instruction unless the previous |
| 9631 | instruction specifically requires a 32-bit one. */ |
| 9632 | if (mips_opts.micromips |
| 9633 | && !mips_opts.insn32 |
| 9634 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
| 9635 | macro_build (NULL, "move", "mp,mj", dest, source); |
| 9636 | else |
| 9637 | macro_build (NULL, "or", "d,v,t", dest, source, 0); |
| 9638 | } |
| 9639 | |
| 9640 | /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where |
| 9641 | LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement. |
| 9642 | The two alternatives are: |
| 9643 | |
| 9644 | Global symbol Local symbol |
| 9645 | ------------- ------------ |
| 9646 | lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET) |
| 9647 | ... ... |
| 9648 | addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET) |
| 9649 | |
| 9650 | load_got_offset emits the first instruction and add_got_offset |
| 9651 | emits the second for a 16-bit offset or add_got_offset_hilo emits |
| 9652 | a sequence to add a 32-bit offset using a scratch register. */ |
| 9653 | |
| 9654 | static void |
| 9655 | load_got_offset (int dest, expressionS *local) |
| 9656 | { |
| 9657 | expressionS global; |
| 9658 | |
| 9659 | global = *local; |
| 9660 | global.X_add_number = 0; |
| 9661 | |
| 9662 | relax_start (local->X_add_symbol); |
| 9663 | macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
| 9664 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 9665 | relax_switch (); |
| 9666 | macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest, |
| 9667 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 9668 | relax_end (); |
| 9669 | } |
| 9670 | |
| 9671 | static void |
| 9672 | add_got_offset (int dest, expressionS *local) |
| 9673 | { |
| 9674 | expressionS global; |
| 9675 | |
| 9676 | global.X_op = O_constant; |
| 9677 | global.X_op_symbol = NULL; |
| 9678 | global.X_add_symbol = NULL; |
| 9679 | global.X_add_number = local->X_add_number; |
| 9680 | |
| 9681 | relax_start (local->X_add_symbol); |
| 9682 | macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j", |
| 9683 | dest, dest, BFD_RELOC_LO16); |
| 9684 | relax_switch (); |
| 9685 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16); |
| 9686 | relax_end (); |
| 9687 | } |
| 9688 | |
| 9689 | static void |
| 9690 | add_got_offset_hilo (int dest, expressionS *local, int tmp) |
| 9691 | { |
| 9692 | expressionS global; |
| 9693 | int hold_mips_optimize; |
| 9694 | |
| 9695 | global.X_op = O_constant; |
| 9696 | global.X_op_symbol = NULL; |
| 9697 | global.X_add_symbol = NULL; |
| 9698 | global.X_add_number = local->X_add_number; |
| 9699 | |
| 9700 | relax_start (local->X_add_symbol); |
| 9701 | load_register (tmp, &global, HAVE_64BIT_ADDRESSES); |
| 9702 | relax_switch (); |
| 9703 | /* Set mips_optimize around the lui instruction to avoid |
| 9704 | inserting an unnecessary nop after the lw. */ |
| 9705 | hold_mips_optimize = mips_optimize; |
| 9706 | mips_optimize = 2; |
| 9707 | macro_build_lui (&global, tmp); |
| 9708 | mips_optimize = hold_mips_optimize; |
| 9709 | macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16); |
| 9710 | relax_end (); |
| 9711 | |
| 9712 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp); |
| 9713 | } |
| 9714 | |
| 9715 | /* Emit a sequence of instructions to emulate a branch likely operation. |
| 9716 | BR is an ordinary branch corresponding to one to be emulated. BRNEG |
| 9717 | is its complementing branch with the original condition negated. |
| 9718 | CALL is set if the original branch specified the link operation. |
| 9719 | EP, FMT, SREG and TREG specify the usual macro_build() parameters. |
| 9720 | |
| 9721 | Code like this is produced in the noreorder mode: |
| 9722 | |
| 9723 | BRNEG <args>, 1f |
| 9724 | nop |
| 9725 | b <sym> |
| 9726 | delay slot (executed only if branch taken) |
| 9727 | 1: |
| 9728 | |
| 9729 | or, if CALL is set: |
| 9730 | |
| 9731 | BRNEG <args>, 1f |
| 9732 | nop |
| 9733 | bal <sym> |
| 9734 | delay slot (executed only if branch taken) |
| 9735 | 1: |
| 9736 | |
| 9737 | In the reorder mode the delay slot would be filled with a nop anyway, |
| 9738 | so code produced is simply: |
| 9739 | |
| 9740 | BR <args>, <sym> |
| 9741 | nop |
| 9742 | |
| 9743 | This function is used when producing code for the microMIPS ASE that |
| 9744 | does not implement branch likely instructions in hardware. */ |
| 9745 | |
| 9746 | static void |
| 9747 | macro_build_branch_likely (const char *br, const char *brneg, |
| 9748 | int call, expressionS *ep, const char *fmt, |
| 9749 | unsigned int sreg, unsigned int treg) |
| 9750 | { |
| 9751 | int noreorder = mips_opts.noreorder; |
| 9752 | expressionS expr1; |
| 9753 | |
| 9754 | gas_assert (mips_opts.micromips); |
| 9755 | start_noreorder (); |
| 9756 | if (noreorder) |
| 9757 | { |
| 9758 | micromips_label_expr (&expr1); |
| 9759 | macro_build (&expr1, brneg, fmt, sreg, treg); |
| 9760 | macro_build (NULL, "nop", ""); |
| 9761 | macro_build (ep, call ? "bal" : "b", "p"); |
| 9762 | |
| 9763 | /* Set to true so that append_insn adds a label. */ |
| 9764 | emit_branch_likely_macro = TRUE; |
| 9765 | } |
| 9766 | else |
| 9767 | { |
| 9768 | macro_build (ep, br, fmt, sreg, treg); |
| 9769 | macro_build (NULL, "nop", ""); |
| 9770 | } |
| 9771 | end_noreorder (); |
| 9772 | } |
| 9773 | |
| 9774 | /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as |
| 9775 | the condition code tested. EP specifies the branch target. */ |
| 9776 | |
| 9777 | static void |
| 9778 | macro_build_branch_ccl (int type, expressionS *ep, unsigned int cc) |
| 9779 | { |
| 9780 | const int call = 0; |
| 9781 | const char *brneg; |
| 9782 | const char *br; |
| 9783 | |
| 9784 | switch (type) |
| 9785 | { |
| 9786 | case M_BC1FL: |
| 9787 | br = "bc1f"; |
| 9788 | brneg = "bc1t"; |
| 9789 | break; |
| 9790 | case M_BC1TL: |
| 9791 | br = "bc1t"; |
| 9792 | brneg = "bc1f"; |
| 9793 | break; |
| 9794 | case M_BC2FL: |
| 9795 | br = "bc2f"; |
| 9796 | brneg = "bc2t"; |
| 9797 | break; |
| 9798 | case M_BC2TL: |
| 9799 | br = "bc2t"; |
| 9800 | brneg = "bc2f"; |
| 9801 | break; |
| 9802 | default: |
| 9803 | abort (); |
| 9804 | } |
| 9805 | macro_build_branch_likely (br, brneg, call, ep, "N,p", cc, ZERO); |
| 9806 | } |
| 9807 | |
| 9808 | /* Emit a two-argument branch macro specified by TYPE, using SREG as |
| 9809 | the register tested. EP specifies the branch target. */ |
| 9810 | |
| 9811 | static void |
| 9812 | macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) |
| 9813 | { |
| 9814 | const char *brneg = NULL; |
| 9815 | const char *br; |
| 9816 | int call = 0; |
| 9817 | |
| 9818 | switch (type) |
| 9819 | { |
| 9820 | case M_BGEZ: |
| 9821 | br = "bgez"; |
| 9822 | break; |
| 9823 | case M_BGEZL: |
| 9824 | br = mips_opts.micromips ? "bgez" : "bgezl"; |
| 9825 | brneg = "bltz"; |
| 9826 | break; |
| 9827 | case M_BGEZALL: |
| 9828 | gas_assert (mips_opts.micromips); |
| 9829 | br = mips_opts.insn32 ? "bgezal" : "bgezals"; |
| 9830 | brneg = "bltz"; |
| 9831 | call = 1; |
| 9832 | break; |
| 9833 | case M_BGTZ: |
| 9834 | br = "bgtz"; |
| 9835 | break; |
| 9836 | case M_BGTZL: |
| 9837 | br = mips_opts.micromips ? "bgtz" : "bgtzl"; |
| 9838 | brneg = "blez"; |
| 9839 | break; |
| 9840 | case M_BLEZ: |
| 9841 | br = "blez"; |
| 9842 | break; |
| 9843 | case M_BLEZL: |
| 9844 | br = mips_opts.micromips ? "blez" : "blezl"; |
| 9845 | brneg = "bgtz"; |
| 9846 | break; |
| 9847 | case M_BLTZ: |
| 9848 | br = "bltz"; |
| 9849 | break; |
| 9850 | case M_BLTZL: |
| 9851 | br = mips_opts.micromips ? "bltz" : "bltzl"; |
| 9852 | brneg = "bgez"; |
| 9853 | break; |
| 9854 | case M_BLTZALL: |
| 9855 | gas_assert (mips_opts.micromips); |
| 9856 | br = mips_opts.insn32 ? "bltzal" : "bltzals"; |
| 9857 | brneg = "bgez"; |
| 9858 | call = 1; |
| 9859 | break; |
| 9860 | default: |
| 9861 | abort (); |
| 9862 | } |
| 9863 | if (mips_opts.micromips && brneg) |
| 9864 | macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO); |
| 9865 | else |
| 9866 | macro_build (ep, br, "s,p", sreg); |
| 9867 | } |
| 9868 | |
| 9869 | /* Emit a three-argument branch macro specified by TYPE, using SREG and |
| 9870 | TREG as the registers tested. EP specifies the branch target. */ |
| 9871 | |
| 9872 | static void |
| 9873 | macro_build_branch_rsrt (int type, expressionS *ep, |
| 9874 | unsigned int sreg, unsigned int treg) |
| 9875 | { |
| 9876 | const char *brneg = NULL; |
| 9877 | const int call = 0; |
| 9878 | const char *br; |
| 9879 | |
| 9880 | switch (type) |
| 9881 | { |
| 9882 | case M_BEQ: |
| 9883 | case M_BEQ_I: |
| 9884 | br = "beq"; |
| 9885 | break; |
| 9886 | case M_BEQL: |
| 9887 | case M_BEQL_I: |
| 9888 | br = mips_opts.micromips ? "beq" : "beql"; |
| 9889 | brneg = "bne"; |
| 9890 | break; |
| 9891 | case M_BNE: |
| 9892 | case M_BNE_I: |
| 9893 | br = "bne"; |
| 9894 | break; |
| 9895 | case M_BNEL: |
| 9896 | case M_BNEL_I: |
| 9897 | br = mips_opts.micromips ? "bne" : "bnel"; |
| 9898 | brneg = "beq"; |
| 9899 | break; |
| 9900 | default: |
| 9901 | abort (); |
| 9902 | } |
| 9903 | if (mips_opts.micromips && brneg) |
| 9904 | macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg); |
| 9905 | else |
| 9906 | macro_build (ep, br, "s,t,p", sreg, treg); |
| 9907 | } |
| 9908 | |
| 9909 | /* Return the high part that should be loaded in order to make the low |
| 9910 | part of VALUE accessible using an offset of OFFBITS bits. */ |
| 9911 | |
| 9912 | static offsetT |
| 9913 | offset_high_part (offsetT value, unsigned int offbits) |
| 9914 | { |
| 9915 | offsetT bias; |
| 9916 | addressT low_mask; |
| 9917 | |
| 9918 | if (offbits == 0) |
| 9919 | return value; |
| 9920 | bias = 1 << (offbits - 1); |
| 9921 | low_mask = bias * 2 - 1; |
| 9922 | return (value + bias) & ~low_mask; |
| 9923 | } |
| 9924 | |
| 9925 | /* Return true if the value stored in offset_expr and offset_reloc |
| 9926 | fits into a signed offset of OFFBITS bits. RANGE is the maximum |
| 9927 | amount that the caller wants to add without inducing overflow |
| 9928 | and ALIGN is the known alignment of the value in bytes. */ |
| 9929 | |
| 9930 | static bfd_boolean |
| 9931 | small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) |
| 9932 | { |
| 9933 | if (offbits == 16) |
| 9934 | { |
| 9935 | /* Accept any relocation operator if overflow isn't a concern. */ |
| 9936 | if (range < align && *offset_reloc != BFD_RELOC_UNUSED) |
| 9937 | return TRUE; |
| 9938 | |
| 9939 | /* These relocations are guaranteed not to overflow in correct links. */ |
| 9940 | if (*offset_reloc == BFD_RELOC_MIPS_LITERAL |
| 9941 | || gprel16_reloc_p (*offset_reloc)) |
| 9942 | return TRUE; |
| 9943 | } |
| 9944 | if (offset_expr.X_op == O_constant |
| 9945 | && offset_high_part (offset_expr.X_add_number, offbits) == 0 |
| 9946 | && offset_high_part (offset_expr.X_add_number + range, offbits) == 0) |
| 9947 | return TRUE; |
| 9948 | return FALSE; |
| 9949 | } |
| 9950 | |
| 9951 | /* |
| 9952 | * Build macros |
| 9953 | * This routine implements the seemingly endless macro or synthesized |
| 9954 | * instructions and addressing modes in the mips assembly language. Many |
| 9955 | * of these macros are simple and are similar to each other. These could |
| 9956 | * probably be handled by some kind of table or grammar approach instead of |
| 9957 | * this verbose method. Others are not simple macros but are more like |
| 9958 | * optimizing code generation. |
| 9959 | * One interesting optimization is when several store macros appear |
| 9960 | * consecutively that would load AT with the upper half of the same address. |
| 9961 | * The ensuing load upper instructions are omitted. This implies some kind |
| 9962 | * of global optimization. We currently only optimize within a single macro. |
| 9963 | * For many of the load and store macros if the address is specified as a |
| 9964 | * constant expression in the first 64k of memory (ie ld $2,0x4000c) we |
| 9965 | * first load register 'at' with zero and use it as the base register. The |
| 9966 | * mips assembler simply uses register $zero. Just one tiny optimization |
| 9967 | * we're missing. |
| 9968 | */ |
| 9969 | static void |
| 9970 | macro (struct mips_cl_insn *ip, char *str) |
| 9971 | { |
| 9972 | const struct mips_operand_array *operands; |
| 9973 | unsigned int breg, i; |
| 9974 | unsigned int tempreg; |
| 9975 | int mask; |
| 9976 | int used_at = 0; |
| 9977 | expressionS label_expr; |
| 9978 | expressionS expr1; |
| 9979 | expressionS *ep; |
| 9980 | const char *s; |
| 9981 | const char *s2; |
| 9982 | const char *fmt; |
| 9983 | int likely = 0; |
| 9984 | int coproc = 0; |
| 9985 | int offbits = 16; |
| 9986 | int call = 0; |
| 9987 | int jals = 0; |
| 9988 | int dbl = 0; |
| 9989 | int imm = 0; |
| 9990 | int ust = 0; |
| 9991 | int lp = 0; |
| 9992 | bfd_boolean large_offset; |
| 9993 | int off; |
| 9994 | int hold_mips_optimize; |
| 9995 | unsigned int align; |
| 9996 | unsigned int op[MAX_OPERANDS]; |
| 9997 | |
| 9998 | gas_assert (! mips_opts.mips16); |
| 9999 | |
| 10000 | operands = insn_operands (ip); |
| 10001 | for (i = 0; i < MAX_OPERANDS; i++) |
| 10002 | if (operands->operand[i]) |
| 10003 | op[i] = insn_extract_operand (ip, operands->operand[i]); |
| 10004 | else |
| 10005 | op[i] = -1; |
| 10006 | |
| 10007 | mask = ip->insn_mo->mask; |
| 10008 | |
| 10009 | label_expr.X_op = O_constant; |
| 10010 | label_expr.X_op_symbol = NULL; |
| 10011 | label_expr.X_add_symbol = NULL; |
| 10012 | label_expr.X_add_number = 0; |
| 10013 | |
| 10014 | expr1.X_op = O_constant; |
| 10015 | expr1.X_op_symbol = NULL; |
| 10016 | expr1.X_add_symbol = NULL; |
| 10017 | expr1.X_add_number = 1; |
| 10018 | align = 1; |
| 10019 | |
| 10020 | switch (mask) |
| 10021 | { |
| 10022 | case M_DABS: |
| 10023 | dbl = 1; |
| 10024 | /* Fall through. */ |
| 10025 | case M_ABS: |
| 10026 | /* bgez $a0,1f |
| 10027 | move v0,$a0 |
| 10028 | sub v0,$zero,$a0 |
| 10029 | 1: |
| 10030 | */ |
| 10031 | |
| 10032 | start_noreorder (); |
| 10033 | |
| 10034 | if (mips_opts.micromips) |
| 10035 | micromips_label_expr (&label_expr); |
| 10036 | else |
| 10037 | label_expr.X_add_number = 8; |
| 10038 | macro_build (&label_expr, "bgez", "s,p", op[1]); |
| 10039 | if (op[0] == op[1]) |
| 10040 | macro_build (NULL, "nop", ""); |
| 10041 | else |
| 10042 | move_register (op[0], op[1]); |
| 10043 | macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]); |
| 10044 | if (mips_opts.micromips) |
| 10045 | micromips_add_label (); |
| 10046 | |
| 10047 | end_noreorder (); |
| 10048 | break; |
| 10049 | |
| 10050 | case M_ADD_I: |
| 10051 | s = "addi"; |
| 10052 | s2 = "add"; |
| 10053 | goto do_addi; |
| 10054 | case M_ADDU_I: |
| 10055 | s = "addiu"; |
| 10056 | s2 = "addu"; |
| 10057 | goto do_addi; |
| 10058 | case M_DADD_I: |
| 10059 | dbl = 1; |
| 10060 | s = "daddi"; |
| 10061 | s2 = "dadd"; |
| 10062 | if (!mips_opts.micromips) |
| 10063 | goto do_addi; |
| 10064 | if (imm_expr.X_add_number >= -0x200 |
| 10065 | && imm_expr.X_add_number < 0x200) |
| 10066 | { |
| 10067 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
| 10068 | (int) imm_expr.X_add_number); |
| 10069 | break; |
| 10070 | } |
| 10071 | goto do_addi_i; |
| 10072 | case M_DADDU_I: |
| 10073 | dbl = 1; |
| 10074 | s = "daddiu"; |
| 10075 | s2 = "daddu"; |
| 10076 | do_addi: |
| 10077 | if (imm_expr.X_add_number >= -0x8000 |
| 10078 | && imm_expr.X_add_number < 0x8000) |
| 10079 | { |
| 10080 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
| 10081 | break; |
| 10082 | } |
| 10083 | do_addi_i: |
| 10084 | used_at = 1; |
| 10085 | load_register (AT, &imm_expr, dbl); |
| 10086 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
| 10087 | break; |
| 10088 | |
| 10089 | case M_AND_I: |
| 10090 | s = "andi"; |
| 10091 | s2 = "and"; |
| 10092 | goto do_bit; |
| 10093 | case M_OR_I: |
| 10094 | s = "ori"; |
| 10095 | s2 = "or"; |
| 10096 | goto do_bit; |
| 10097 | case M_NOR_I: |
| 10098 | s = ""; |
| 10099 | s2 = "nor"; |
| 10100 | goto do_bit; |
| 10101 | case M_XOR_I: |
| 10102 | s = "xori"; |
| 10103 | s2 = "xor"; |
| 10104 | do_bit: |
| 10105 | if (imm_expr.X_add_number >= 0 |
| 10106 | && imm_expr.X_add_number < 0x10000) |
| 10107 | { |
| 10108 | if (mask != M_NOR_I) |
| 10109 | macro_build (&imm_expr, s, "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
| 10110 | else |
| 10111 | { |
| 10112 | macro_build (&imm_expr, "ori", "t,r,i", |
| 10113 | op[0], op[1], BFD_RELOC_LO16); |
| 10114 | macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); |
| 10115 | } |
| 10116 | break; |
| 10117 | } |
| 10118 | |
| 10119 | used_at = 1; |
| 10120 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 10121 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
| 10122 | break; |
| 10123 | |
| 10124 | case M_BALIGN: |
| 10125 | switch (imm_expr.X_add_number) |
| 10126 | { |
| 10127 | case 0: |
| 10128 | macro_build (NULL, "nop", ""); |
| 10129 | break; |
| 10130 | case 2: |
| 10131 | macro_build (NULL, "packrl.ph", "d,s,t", op[0], op[0], op[1]); |
| 10132 | break; |
| 10133 | case 1: |
| 10134 | case 3: |
| 10135 | macro_build (NULL, "balign", "t,s,2", op[0], op[1], |
| 10136 | (int) imm_expr.X_add_number); |
| 10137 | break; |
| 10138 | default: |
| 10139 | as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"), |
| 10140 | (unsigned long) imm_expr.X_add_number); |
| 10141 | break; |
| 10142 | } |
| 10143 | break; |
| 10144 | |
| 10145 | case M_BC1FL: |
| 10146 | case M_BC1TL: |
| 10147 | case M_BC2FL: |
| 10148 | case M_BC2TL: |
| 10149 | gas_assert (mips_opts.micromips); |
| 10150 | macro_build_branch_ccl (mask, &offset_expr, |
| 10151 | EXTRACT_OPERAND (1, BCC, *ip)); |
| 10152 | break; |
| 10153 | |
| 10154 | case M_BEQ_I: |
| 10155 | case M_BEQL_I: |
| 10156 | case M_BNE_I: |
| 10157 | case M_BNEL_I: |
| 10158 | if (imm_expr.X_add_number == 0) |
| 10159 | op[1] = 0; |
| 10160 | else |
| 10161 | { |
| 10162 | op[1] = AT; |
| 10163 | used_at = 1; |
| 10164 | load_register (op[1], &imm_expr, GPR_SIZE == 64); |
| 10165 | } |
| 10166 | /* Fall through. */ |
| 10167 | case M_BEQL: |
| 10168 | case M_BNEL: |
| 10169 | macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); |
| 10170 | break; |
| 10171 | |
| 10172 | case M_BGEL: |
| 10173 | likely = 1; |
| 10174 | /* Fall through. */ |
| 10175 | case M_BGE: |
| 10176 | if (op[1] == 0) |
| 10177 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[0]); |
| 10178 | else if (op[0] == 0) |
| 10179 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[1]); |
| 10180 | else |
| 10181 | { |
| 10182 | used_at = 1; |
| 10183 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
| 10184 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
| 10185 | &offset_expr, AT, ZERO); |
| 10186 | } |
| 10187 | break; |
| 10188 | |
| 10189 | case M_BGEZL: |
| 10190 | case M_BGEZALL: |
| 10191 | case M_BGTZL: |
| 10192 | case M_BLEZL: |
| 10193 | case M_BLTZL: |
| 10194 | case M_BLTZALL: |
| 10195 | macro_build_branch_rs (mask, &offset_expr, op[0]); |
| 10196 | break; |
| 10197 | |
| 10198 | case M_BGTL_I: |
| 10199 | likely = 1; |
| 10200 | /* Fall through. */ |
| 10201 | case M_BGT_I: |
| 10202 | /* Check for > max integer. */ |
| 10203 | if (imm_expr.X_add_number >= GPR_SMAX) |
| 10204 | { |
| 10205 | do_false: |
| 10206 | /* Result is always false. */ |
| 10207 | if (! likely) |
| 10208 | macro_build (NULL, "nop", ""); |
| 10209 | else |
| 10210 | macro_build_branch_rsrt (M_BNEL, &offset_expr, ZERO, ZERO); |
| 10211 | break; |
| 10212 | } |
| 10213 | ++imm_expr.X_add_number; |
| 10214 | /* FALLTHROUGH */ |
| 10215 | case M_BGE_I: |
| 10216 | case M_BGEL_I: |
| 10217 | if (mask == M_BGEL_I) |
| 10218 | likely = 1; |
| 10219 | if (imm_expr.X_add_number == 0) |
| 10220 | { |
| 10221 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, |
| 10222 | &offset_expr, op[0]); |
| 10223 | break; |
| 10224 | } |
| 10225 | if (imm_expr.X_add_number == 1) |
| 10226 | { |
| 10227 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, |
| 10228 | &offset_expr, op[0]); |
| 10229 | break; |
| 10230 | } |
| 10231 | if (imm_expr.X_add_number <= GPR_SMIN) |
| 10232 | { |
| 10233 | do_true: |
| 10234 | /* result is always true */ |
| 10235 | as_warn (_("branch %s is always true"), ip->insn_mo->name); |
| 10236 | macro_build (&offset_expr, "b", "p"); |
| 10237 | break; |
| 10238 | } |
| 10239 | used_at = 1; |
| 10240 | set_at (op[0], 0); |
| 10241 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
| 10242 | &offset_expr, AT, ZERO); |
| 10243 | break; |
| 10244 | |
| 10245 | case M_BGEUL: |
| 10246 | likely = 1; |
| 10247 | /* Fall through. */ |
| 10248 | case M_BGEU: |
| 10249 | if (op[1] == 0) |
| 10250 | goto do_true; |
| 10251 | else if (op[0] == 0) |
| 10252 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
| 10253 | &offset_expr, ZERO, op[1]); |
| 10254 | else |
| 10255 | { |
| 10256 | used_at = 1; |
| 10257 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
| 10258 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
| 10259 | &offset_expr, AT, ZERO); |
| 10260 | } |
| 10261 | break; |
| 10262 | |
| 10263 | case M_BGTUL_I: |
| 10264 | likely = 1; |
| 10265 | /* Fall through. */ |
| 10266 | case M_BGTU_I: |
| 10267 | if (op[0] == 0 |
| 10268 | || (GPR_SIZE == 32 |
| 10269 | && imm_expr.X_add_number == -1)) |
| 10270 | goto do_false; |
| 10271 | ++imm_expr.X_add_number; |
| 10272 | /* FALLTHROUGH */ |
| 10273 | case M_BGEU_I: |
| 10274 | case M_BGEUL_I: |
| 10275 | if (mask == M_BGEUL_I) |
| 10276 | likely = 1; |
| 10277 | if (imm_expr.X_add_number == 0) |
| 10278 | goto do_true; |
| 10279 | else if (imm_expr.X_add_number == 1) |
| 10280 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
| 10281 | &offset_expr, op[0], ZERO); |
| 10282 | else |
| 10283 | { |
| 10284 | used_at = 1; |
| 10285 | set_at (op[0], 1); |
| 10286 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
| 10287 | &offset_expr, AT, ZERO); |
| 10288 | } |
| 10289 | break; |
| 10290 | |
| 10291 | case M_BGTL: |
| 10292 | likely = 1; |
| 10293 | /* Fall through. */ |
| 10294 | case M_BGT: |
| 10295 | if (op[1] == 0) |
| 10296 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[0]); |
| 10297 | else if (op[0] == 0) |
| 10298 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[1]); |
| 10299 | else |
| 10300 | { |
| 10301 | used_at = 1; |
| 10302 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
| 10303 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
| 10304 | &offset_expr, AT, ZERO); |
| 10305 | } |
| 10306 | break; |
| 10307 | |
| 10308 | case M_BGTUL: |
| 10309 | likely = 1; |
| 10310 | /* Fall through. */ |
| 10311 | case M_BGTU: |
| 10312 | if (op[1] == 0) |
| 10313 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
| 10314 | &offset_expr, op[0], ZERO); |
| 10315 | else if (op[0] == 0) |
| 10316 | goto do_false; |
| 10317 | else |
| 10318 | { |
| 10319 | used_at = 1; |
| 10320 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
| 10321 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
| 10322 | &offset_expr, AT, ZERO); |
| 10323 | } |
| 10324 | break; |
| 10325 | |
| 10326 | case M_BLEL: |
| 10327 | likely = 1; |
| 10328 | /* Fall through. */ |
| 10329 | case M_BLE: |
| 10330 | if (op[1] == 0) |
| 10331 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
| 10332 | else if (op[0] == 0) |
| 10333 | macro_build_branch_rs (likely ? M_BGEZL : M_BGEZ, &offset_expr, op[1]); |
| 10334 | else |
| 10335 | { |
| 10336 | used_at = 1; |
| 10337 | macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); |
| 10338 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
| 10339 | &offset_expr, AT, ZERO); |
| 10340 | } |
| 10341 | break; |
| 10342 | |
| 10343 | case M_BLEL_I: |
| 10344 | likely = 1; |
| 10345 | /* Fall through. */ |
| 10346 | case M_BLE_I: |
| 10347 | if (imm_expr.X_add_number >= GPR_SMAX) |
| 10348 | goto do_true; |
| 10349 | ++imm_expr.X_add_number; |
| 10350 | /* FALLTHROUGH */ |
| 10351 | case M_BLT_I: |
| 10352 | case M_BLTL_I: |
| 10353 | if (mask == M_BLTL_I) |
| 10354 | likely = 1; |
| 10355 | if (imm_expr.X_add_number == 0) |
| 10356 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
| 10357 | else if (imm_expr.X_add_number == 1) |
| 10358 | macro_build_branch_rs (likely ? M_BLEZL : M_BLEZ, &offset_expr, op[0]); |
| 10359 | else |
| 10360 | { |
| 10361 | used_at = 1; |
| 10362 | set_at (op[0], 0); |
| 10363 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
| 10364 | &offset_expr, AT, ZERO); |
| 10365 | } |
| 10366 | break; |
| 10367 | |
| 10368 | case M_BLEUL: |
| 10369 | likely = 1; |
| 10370 | /* Fall through. */ |
| 10371 | case M_BLEU: |
| 10372 | if (op[1] == 0) |
| 10373 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
| 10374 | &offset_expr, op[0], ZERO); |
| 10375 | else if (op[0] == 0) |
| 10376 | goto do_true; |
| 10377 | else |
| 10378 | { |
| 10379 | used_at = 1; |
| 10380 | macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); |
| 10381 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
| 10382 | &offset_expr, AT, ZERO); |
| 10383 | } |
| 10384 | break; |
| 10385 | |
| 10386 | case M_BLEUL_I: |
| 10387 | likely = 1; |
| 10388 | /* Fall through. */ |
| 10389 | case M_BLEU_I: |
| 10390 | if (op[0] == 0 |
| 10391 | || (GPR_SIZE == 32 |
| 10392 | && imm_expr.X_add_number == -1)) |
| 10393 | goto do_true; |
| 10394 | ++imm_expr.X_add_number; |
| 10395 | /* FALLTHROUGH */ |
| 10396 | case M_BLTU_I: |
| 10397 | case M_BLTUL_I: |
| 10398 | if (mask == M_BLTUL_I) |
| 10399 | likely = 1; |
| 10400 | if (imm_expr.X_add_number == 0) |
| 10401 | goto do_false; |
| 10402 | else if (imm_expr.X_add_number == 1) |
| 10403 | macro_build_branch_rsrt (likely ? M_BEQL : M_BEQ, |
| 10404 | &offset_expr, op[0], ZERO); |
| 10405 | else |
| 10406 | { |
| 10407 | used_at = 1; |
| 10408 | set_at (op[0], 1); |
| 10409 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
| 10410 | &offset_expr, AT, ZERO); |
| 10411 | } |
| 10412 | break; |
| 10413 | |
| 10414 | case M_BLTL: |
| 10415 | likely = 1; |
| 10416 | /* Fall through. */ |
| 10417 | case M_BLT: |
| 10418 | if (op[1] == 0) |
| 10419 | macro_build_branch_rs (likely ? M_BLTZL : M_BLTZ, &offset_expr, op[0]); |
| 10420 | else if (op[0] == 0) |
| 10421 | macro_build_branch_rs (likely ? M_BGTZL : M_BGTZ, &offset_expr, op[1]); |
| 10422 | else |
| 10423 | { |
| 10424 | used_at = 1; |
| 10425 | macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); |
| 10426 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
| 10427 | &offset_expr, AT, ZERO); |
| 10428 | } |
| 10429 | break; |
| 10430 | |
| 10431 | case M_BLTUL: |
| 10432 | likely = 1; |
| 10433 | /* Fall through. */ |
| 10434 | case M_BLTU: |
| 10435 | if (op[1] == 0) |
| 10436 | goto do_false; |
| 10437 | else if (op[0] == 0) |
| 10438 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
| 10439 | &offset_expr, ZERO, op[1]); |
| 10440 | else |
| 10441 | { |
| 10442 | used_at = 1; |
| 10443 | macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); |
| 10444 | macro_build_branch_rsrt (likely ? M_BNEL : M_BNE, |
| 10445 | &offset_expr, AT, ZERO); |
| 10446 | } |
| 10447 | break; |
| 10448 | |
| 10449 | case M_DDIV_3: |
| 10450 | dbl = 1; |
| 10451 | /* Fall through. */ |
| 10452 | case M_DIV_3: |
| 10453 | s = "mflo"; |
| 10454 | goto do_div3; |
| 10455 | case M_DREM_3: |
| 10456 | dbl = 1; |
| 10457 | /* Fall through. */ |
| 10458 | case M_REM_3: |
| 10459 | s = "mfhi"; |
| 10460 | do_div3: |
| 10461 | if (op[2] == 0) |
| 10462 | { |
| 10463 | as_warn (_("divide by zero")); |
| 10464 | if (mips_trap) |
| 10465 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
| 10466 | else |
| 10467 | macro_build (NULL, "break", BRK_FMT, 7); |
| 10468 | break; |
| 10469 | } |
| 10470 | |
| 10471 | start_noreorder (); |
| 10472 | if (mips_trap) |
| 10473 | { |
| 10474 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
| 10475 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); |
| 10476 | } |
| 10477 | else |
| 10478 | { |
| 10479 | if (mips_opts.micromips) |
| 10480 | micromips_label_expr (&label_expr); |
| 10481 | else |
| 10482 | label_expr.X_add_number = 8; |
| 10483 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
| 10484 | macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", op[1], op[2]); |
| 10485 | macro_build (NULL, "break", BRK_FMT, 7); |
| 10486 | if (mips_opts.micromips) |
| 10487 | micromips_add_label (); |
| 10488 | } |
| 10489 | expr1.X_add_number = -1; |
| 10490 | used_at = 1; |
| 10491 | load_register (AT, &expr1, dbl); |
| 10492 | if (mips_opts.micromips) |
| 10493 | micromips_label_expr (&label_expr); |
| 10494 | else |
| 10495 | label_expr.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16); |
| 10496 | macro_build (&label_expr, "bne", "s,t,p", op[2], AT); |
| 10497 | if (dbl) |
| 10498 | { |
| 10499 | expr1.X_add_number = 1; |
| 10500 | load_register (AT, &expr1, dbl); |
| 10501 | macro_build (NULL, "dsll32", SHFT_FMT, AT, AT, 31); |
| 10502 | } |
| 10503 | else |
| 10504 | { |
| 10505 | expr1.X_add_number = 0x80000000; |
| 10506 | macro_build (&expr1, "lui", LUI_FMT, AT, BFD_RELOC_HI16); |
| 10507 | } |
| 10508 | if (mips_trap) |
| 10509 | { |
| 10510 | macro_build (NULL, "teq", TRAP_FMT, op[1], AT, 6); |
| 10511 | /* We want to close the noreorder block as soon as possible, so |
| 10512 | that later insns are available for delay slot filling. */ |
| 10513 | end_noreorder (); |
| 10514 | } |
| 10515 | else |
| 10516 | { |
| 10517 | if (mips_opts.micromips) |
| 10518 | micromips_label_expr (&label_expr); |
| 10519 | else |
| 10520 | label_expr.X_add_number = 8; |
| 10521 | macro_build (&label_expr, "bne", "s,t,p", op[1], AT); |
| 10522 | macro_build (NULL, "nop", ""); |
| 10523 | |
| 10524 | /* We want to close the noreorder block as soon as possible, so |
| 10525 | that later insns are available for delay slot filling. */ |
| 10526 | end_noreorder (); |
| 10527 | |
| 10528 | macro_build (NULL, "break", BRK_FMT, 6); |
| 10529 | } |
| 10530 | if (mips_opts.micromips) |
| 10531 | micromips_add_label (); |
| 10532 | macro_build (NULL, s, MFHL_FMT, op[0]); |
| 10533 | break; |
| 10534 | |
| 10535 | case M_DIV_3I: |
| 10536 | s = "div"; |
| 10537 | s2 = "mflo"; |
| 10538 | goto do_divi; |
| 10539 | case M_DIVU_3I: |
| 10540 | s = "divu"; |
| 10541 | s2 = "mflo"; |
| 10542 | goto do_divi; |
| 10543 | case M_REM_3I: |
| 10544 | s = "div"; |
| 10545 | s2 = "mfhi"; |
| 10546 | goto do_divi; |
| 10547 | case M_REMU_3I: |
| 10548 | s = "divu"; |
| 10549 | s2 = "mfhi"; |
| 10550 | goto do_divi; |
| 10551 | case M_DDIV_3I: |
| 10552 | dbl = 1; |
| 10553 | s = "ddiv"; |
| 10554 | s2 = "mflo"; |
| 10555 | goto do_divi; |
| 10556 | case M_DDIVU_3I: |
| 10557 | dbl = 1; |
| 10558 | s = "ddivu"; |
| 10559 | s2 = "mflo"; |
| 10560 | goto do_divi; |
| 10561 | case M_DREM_3I: |
| 10562 | dbl = 1; |
| 10563 | s = "ddiv"; |
| 10564 | s2 = "mfhi"; |
| 10565 | goto do_divi; |
| 10566 | case M_DREMU_3I: |
| 10567 | dbl = 1; |
| 10568 | s = "ddivu"; |
| 10569 | s2 = "mfhi"; |
| 10570 | do_divi: |
| 10571 | if (imm_expr.X_add_number == 0) |
| 10572 | { |
| 10573 | as_warn (_("divide by zero")); |
| 10574 | if (mips_trap) |
| 10575 | macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); |
| 10576 | else |
| 10577 | macro_build (NULL, "break", BRK_FMT, 7); |
| 10578 | break; |
| 10579 | } |
| 10580 | if (imm_expr.X_add_number == 1) |
| 10581 | { |
| 10582 | if (strcmp (s2, "mflo") == 0) |
| 10583 | move_register (op[0], op[1]); |
| 10584 | else |
| 10585 | move_register (op[0], ZERO); |
| 10586 | break; |
| 10587 | } |
| 10588 | if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') |
| 10589 | { |
| 10590 | if (strcmp (s2, "mflo") == 0) |
| 10591 | macro_build (NULL, dbl ? "dneg" : "neg", "d,w", op[0], op[1]); |
| 10592 | else |
| 10593 | move_register (op[0], ZERO); |
| 10594 | break; |
| 10595 | } |
| 10596 | |
| 10597 | used_at = 1; |
| 10598 | load_register (AT, &imm_expr, dbl); |
| 10599 | macro_build (NULL, s, "z,s,t", op[1], AT); |
| 10600 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
| 10601 | break; |
| 10602 | |
| 10603 | case M_DIVU_3: |
| 10604 | s = "divu"; |
| 10605 | s2 = "mflo"; |
| 10606 | goto do_divu3; |
| 10607 | case M_REMU_3: |
| 10608 | s = "divu"; |
| 10609 | s2 = "mfhi"; |
| 10610 | goto do_divu3; |
| 10611 | case M_DDIVU_3: |
| 10612 | s = "ddivu"; |
| 10613 | s2 = "mflo"; |
| 10614 | goto do_divu3; |
| 10615 | case M_DREMU_3: |
| 10616 | s = "ddivu"; |
| 10617 | s2 = "mfhi"; |
| 10618 | do_divu3: |
| 10619 | start_noreorder (); |
| 10620 | if (mips_trap) |
| 10621 | { |
| 10622 | macro_build (NULL, "teq", TRAP_FMT, op[2], ZERO, 7); |
| 10623 | macro_build (NULL, s, "z,s,t", op[1], op[2]); |
| 10624 | /* We want to close the noreorder block as soon as possible, so |
| 10625 | that later insns are available for delay slot filling. */ |
| 10626 | end_noreorder (); |
| 10627 | } |
| 10628 | else |
| 10629 | { |
| 10630 | if (mips_opts.micromips) |
| 10631 | micromips_label_expr (&label_expr); |
| 10632 | else |
| 10633 | label_expr.X_add_number = 8; |
| 10634 | macro_build (&label_expr, "bne", "s,t,p", op[2], ZERO); |
| 10635 | macro_build (NULL, s, "z,s,t", op[1], op[2]); |
| 10636 | |
| 10637 | /* We want to close the noreorder block as soon as possible, so |
| 10638 | that later insns are available for delay slot filling. */ |
| 10639 | end_noreorder (); |
| 10640 | macro_build (NULL, "break", BRK_FMT, 7); |
| 10641 | if (mips_opts.micromips) |
| 10642 | micromips_add_label (); |
| 10643 | } |
| 10644 | macro_build (NULL, s2, MFHL_FMT, op[0]); |
| 10645 | break; |
| 10646 | |
| 10647 | case M_DLCA_AB: |
| 10648 | dbl = 1; |
| 10649 | /* Fall through. */ |
| 10650 | case M_LCA_AB: |
| 10651 | call = 1; |
| 10652 | goto do_la; |
| 10653 | case M_DLA_AB: |
| 10654 | dbl = 1; |
| 10655 | /* Fall through. */ |
| 10656 | case M_LA_AB: |
| 10657 | do_la: |
| 10658 | /* Load the address of a symbol into a register. If breg is not |
| 10659 | zero, we then add a base register to it. */ |
| 10660 | |
| 10661 | breg = op[2]; |
| 10662 | if (dbl && GPR_SIZE == 32) |
| 10663 | as_warn (_("dla used to load 32-bit register; recommend using la " |
| 10664 | "instead")); |
| 10665 | |
| 10666 | if (!dbl && HAVE_64BIT_OBJECTS) |
| 10667 | as_warn (_("la used to load 64-bit address; recommend using dla " |
| 10668 | "instead")); |
| 10669 | |
| 10670 | if (small_offset_p (0, align, 16)) |
| 10671 | { |
| 10672 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", op[0], breg, |
| 10673 | -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
| 10674 | break; |
| 10675 | } |
| 10676 | |
| 10677 | if (mips_opts.at && (op[0] == breg)) |
| 10678 | { |
| 10679 | tempreg = AT; |
| 10680 | used_at = 1; |
| 10681 | } |
| 10682 | else |
| 10683 | tempreg = op[0]; |
| 10684 | |
| 10685 | if (offset_expr.X_op != O_symbol |
| 10686 | && offset_expr.X_op != O_constant) |
| 10687 | { |
| 10688 | as_bad (_("expression too complex")); |
| 10689 | offset_expr.X_op = O_constant; |
| 10690 | } |
| 10691 | |
| 10692 | if (offset_expr.X_op == O_constant) |
| 10693 | load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); |
| 10694 | else if (mips_pic == NO_PIC) |
| 10695 | { |
| 10696 | /* If this is a reference to a GP relative symbol, we want |
| 10697 | addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16) |
| 10698 | Otherwise we want |
| 10699 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 10700 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 10701 | If we have a constant, we need two instructions anyhow, |
| 10702 | so we may as well always use the latter form. |
| 10703 | |
| 10704 | With 64bit address space and a usable $at we want |
| 10705 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 10706 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 10707 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 10708 | daddiu $at,<sym> (BFD_RELOC_LO16) |
| 10709 | dsll32 $tempreg,0 |
| 10710 | daddu $tempreg,$tempreg,$at |
| 10711 | |
| 10712 | If $at is already in use, we use a path which is suboptimal |
| 10713 | on superscalar processors. |
| 10714 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 10715 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 10716 | dsll $tempreg,16 |
| 10717 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 10718 | dsll $tempreg,16 |
| 10719 | daddiu $tempreg,<sym> (BFD_RELOC_LO16) |
| 10720 | |
| 10721 | For GP relative symbols in 64bit address space we can use |
| 10722 | the same sequence as in 32bit address space. */ |
| 10723 | if (HAVE_64BIT_SYMBOLS) |
| 10724 | { |
| 10725 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
| 10726 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 10727 | { |
| 10728 | relax_start (offset_expr.X_add_symbol); |
| 10729 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
| 10730 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); |
| 10731 | relax_switch (); |
| 10732 | } |
| 10733 | |
| 10734 | if (used_at == 0 && mips_opts.at) |
| 10735 | { |
| 10736 | macro_build (&offset_expr, "lui", LUI_FMT, |
| 10737 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
| 10738 | macro_build (&offset_expr, "lui", LUI_FMT, |
| 10739 | AT, BFD_RELOC_HI16_S); |
| 10740 | macro_build (&offset_expr, "daddiu", "t,r,j", |
| 10741 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
| 10742 | macro_build (&offset_expr, "daddiu", "t,r,j", |
| 10743 | AT, AT, BFD_RELOC_LO16); |
| 10744 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
| 10745 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
| 10746 | used_at = 1; |
| 10747 | } |
| 10748 | else |
| 10749 | { |
| 10750 | macro_build (&offset_expr, "lui", LUI_FMT, |
| 10751 | tempreg, BFD_RELOC_MIPS_HIGHEST); |
| 10752 | macro_build (&offset_expr, "daddiu", "t,r,j", |
| 10753 | tempreg, tempreg, BFD_RELOC_MIPS_HIGHER); |
| 10754 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
| 10755 | macro_build (&offset_expr, "daddiu", "t,r,j", |
| 10756 | tempreg, tempreg, BFD_RELOC_HI16_S); |
| 10757 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
| 10758 | macro_build (&offset_expr, "daddiu", "t,r,j", |
| 10759 | tempreg, tempreg, BFD_RELOC_LO16); |
| 10760 | } |
| 10761 | |
| 10762 | if (mips_relax.sequence) |
| 10763 | relax_end (); |
| 10764 | } |
| 10765 | else |
| 10766 | { |
| 10767 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
| 10768 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 10769 | { |
| 10770 | relax_start (offset_expr.X_add_symbol); |
| 10771 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
| 10772 | tempreg, mips_gp_register, BFD_RELOC_GPREL16); |
| 10773 | relax_switch (); |
| 10774 | } |
| 10775 | if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
| 10776 | as_bad (_("offset too large")); |
| 10777 | macro_build_lui (&offset_expr, tempreg); |
| 10778 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
| 10779 | tempreg, tempreg, BFD_RELOC_LO16); |
| 10780 | if (mips_relax.sequence) |
| 10781 | relax_end (); |
| 10782 | } |
| 10783 | } |
| 10784 | else if (!mips_big_got && !HAVE_NEWABI) |
| 10785 | { |
| 10786 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
| 10787 | |
| 10788 | /* If this is a reference to an external symbol, and there |
| 10789 | is no constant, we want |
| 10790 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 10791 | or for lca or if tempreg is PIC_CALL_REG |
| 10792 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
| 10793 | For a local symbol, we want |
| 10794 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 10795 | nop |
| 10796 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 10797 | |
| 10798 | If we have a small constant, and this is a reference to |
| 10799 | an external symbol, we want |
| 10800 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 10801 | nop |
| 10802 | addiu $tempreg,$tempreg,<constant> |
| 10803 | For a local symbol, we want the same instruction |
| 10804 | sequence, but we output a BFD_RELOC_LO16 reloc on the |
| 10805 | addiu instruction. |
| 10806 | |
| 10807 | If we have a large constant, and this is a reference to |
| 10808 | an external symbol, we want |
| 10809 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 10810 | lui $at,<hiconstant> |
| 10811 | addiu $at,$at,<loconstant> |
| 10812 | addu $tempreg,$tempreg,$at |
| 10813 | For a local symbol, we want the same instruction |
| 10814 | sequence, but we output a BFD_RELOC_LO16 reloc on the |
| 10815 | addiu instruction. |
| 10816 | */ |
| 10817 | |
| 10818 | if (offset_expr.X_add_number == 0) |
| 10819 | { |
| 10820 | if (mips_pic == SVR4_PIC |
| 10821 | && breg == 0 |
| 10822 | && (call || tempreg == PIC_CALL_REG)) |
| 10823 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16; |
| 10824 | |
| 10825 | relax_start (offset_expr.X_add_symbol); |
| 10826 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 10827 | lw_reloc_type, mips_gp_register); |
| 10828 | if (breg != 0) |
| 10829 | { |
| 10830 | /* We're going to put in an addu instruction using |
| 10831 | tempreg, so we may as well insert the nop right |
| 10832 | now. */ |
| 10833 | load_delay_nop (); |
| 10834 | } |
| 10835 | relax_switch (); |
| 10836 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 10837 | tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 10838 | load_delay_nop (); |
| 10839 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
| 10840 | tempreg, tempreg, BFD_RELOC_LO16); |
| 10841 | relax_end (); |
| 10842 | /* FIXME: If breg == 0, and the next instruction uses |
| 10843 | $tempreg, then if this variant case is used an extra |
| 10844 | nop will be generated. */ |
| 10845 | } |
| 10846 | else if (offset_expr.X_add_number >= -0x8000 |
| 10847 | && offset_expr.X_add_number < 0x8000) |
| 10848 | { |
| 10849 | load_got_offset (tempreg, &offset_expr); |
| 10850 | load_delay_nop (); |
| 10851 | add_got_offset (tempreg, &offset_expr); |
| 10852 | } |
| 10853 | else |
| 10854 | { |
| 10855 | expr1.X_add_number = offset_expr.X_add_number; |
| 10856 | offset_expr.X_add_number = |
| 10857 | SEXT_16BIT (offset_expr.X_add_number); |
| 10858 | load_got_offset (tempreg, &offset_expr); |
| 10859 | offset_expr.X_add_number = expr1.X_add_number; |
| 10860 | /* If we are going to add in a base register, and the |
| 10861 | target register and the base register are the same, |
| 10862 | then we are using AT as a temporary register. Since |
| 10863 | we want to load the constant into AT, we add our |
| 10864 | current AT (from the global offset table) and the |
| 10865 | register into the register now, and pretend we were |
| 10866 | not using a base register. */ |
| 10867 | if (breg == op[0]) |
| 10868 | { |
| 10869 | load_delay_nop (); |
| 10870 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 10871 | op[0], AT, breg); |
| 10872 | breg = 0; |
| 10873 | tempreg = op[0]; |
| 10874 | } |
| 10875 | add_got_offset_hilo (tempreg, &offset_expr, AT); |
| 10876 | used_at = 1; |
| 10877 | } |
| 10878 | } |
| 10879 | else if (!mips_big_got && HAVE_NEWABI) |
| 10880 | { |
| 10881 | int add_breg_early = 0; |
| 10882 | |
| 10883 | /* If this is a reference to an external, and there is no |
| 10884 | constant, or local symbol (*), with or without a |
| 10885 | constant, we want |
| 10886 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
| 10887 | or for lca or if tempreg is PIC_CALL_REG |
| 10888 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
| 10889 | |
| 10890 | If we have a small constant, and this is a reference to |
| 10891 | an external symbol, we want |
| 10892 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
| 10893 | addiu $tempreg,$tempreg,<constant> |
| 10894 | |
| 10895 | If we have a large constant, and this is a reference to |
| 10896 | an external symbol, we want |
| 10897 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP) |
| 10898 | lui $at,<hiconstant> |
| 10899 | addiu $at,$at,<loconstant> |
| 10900 | addu $tempreg,$tempreg,$at |
| 10901 | |
| 10902 | (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for |
| 10903 | local symbols, even though it introduces an additional |
| 10904 | instruction. */ |
| 10905 | |
| 10906 | if (offset_expr.X_add_number) |
| 10907 | { |
| 10908 | expr1.X_add_number = offset_expr.X_add_number; |
| 10909 | offset_expr.X_add_number = 0; |
| 10910 | |
| 10911 | relax_start (offset_expr.X_add_symbol); |
| 10912 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 10913 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
| 10914 | |
| 10915 | if (expr1.X_add_number >= -0x8000 |
| 10916 | && expr1.X_add_number < 0x8000) |
| 10917 | { |
| 10918 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
| 10919 | tempreg, tempreg, BFD_RELOC_LO16); |
| 10920 | } |
| 10921 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
| 10922 | { |
| 10923 | unsigned int dreg; |
| 10924 | |
| 10925 | /* If we are going to add in a base register, and the |
| 10926 | target register and the base register are the same, |
| 10927 | then we are using AT as a temporary register. Since |
| 10928 | we want to load the constant into AT, we add our |
| 10929 | current AT (from the global offset table) and the |
| 10930 | register into the register now, and pretend we were |
| 10931 | not using a base register. */ |
| 10932 | if (breg != op[0]) |
| 10933 | dreg = tempreg; |
| 10934 | else |
| 10935 | { |
| 10936 | gas_assert (tempreg == AT); |
| 10937 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 10938 | op[0], AT, breg); |
| 10939 | dreg = op[0]; |
| 10940 | add_breg_early = 1; |
| 10941 | } |
| 10942 | |
| 10943 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
| 10944 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 10945 | dreg, dreg, AT); |
| 10946 | |
| 10947 | used_at = 1; |
| 10948 | } |
| 10949 | else |
| 10950 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); |
| 10951 | |
| 10952 | relax_switch (); |
| 10953 | offset_expr.X_add_number = expr1.X_add_number; |
| 10954 | |
| 10955 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 10956 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
| 10957 | if (add_breg_early) |
| 10958 | { |
| 10959 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 10960 | op[0], tempreg, breg); |
| 10961 | breg = 0; |
| 10962 | tempreg = op[0]; |
| 10963 | } |
| 10964 | relax_end (); |
| 10965 | } |
| 10966 | else if (breg == 0 && (call || tempreg == PIC_CALL_REG)) |
| 10967 | { |
| 10968 | relax_start (offset_expr.X_add_symbol); |
| 10969 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 10970 | BFD_RELOC_MIPS_CALL16, mips_gp_register); |
| 10971 | relax_switch (); |
| 10972 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 10973 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
| 10974 | relax_end (); |
| 10975 | } |
| 10976 | else |
| 10977 | { |
| 10978 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 10979 | BFD_RELOC_MIPS_GOT_DISP, mips_gp_register); |
| 10980 | } |
| 10981 | } |
| 10982 | else if (mips_big_got && !HAVE_NEWABI) |
| 10983 | { |
| 10984 | int gpdelay; |
| 10985 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
| 10986 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; |
| 10987 | int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
| 10988 | |
| 10989 | /* This is the large GOT case. If this is a reference to an |
| 10990 | external symbol, and there is no constant, we want |
| 10991 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 10992 | addu $tempreg,$tempreg,$gp |
| 10993 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 10994 | or for lca or if tempreg is PIC_CALL_REG |
| 10995 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
| 10996 | addu $tempreg,$tempreg,$gp |
| 10997 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) |
| 10998 | For a local symbol, we want |
| 10999 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 11000 | nop |
| 11001 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 11002 | |
| 11003 | If we have a small constant, and this is a reference to |
| 11004 | an external symbol, we want |
| 11005 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 11006 | addu $tempreg,$tempreg,$gp |
| 11007 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 11008 | nop |
| 11009 | addiu $tempreg,$tempreg,<constant> |
| 11010 | For a local symbol, we want |
| 11011 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 11012 | nop |
| 11013 | addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16) |
| 11014 | |
| 11015 | If we have a large constant, and this is a reference to |
| 11016 | an external symbol, we want |
| 11017 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 11018 | addu $tempreg,$tempreg,$gp |
| 11019 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 11020 | lui $at,<hiconstant> |
| 11021 | addiu $at,$at,<loconstant> |
| 11022 | addu $tempreg,$tempreg,$at |
| 11023 | For a local symbol, we want |
| 11024 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 11025 | lui $at,<hiconstant> |
| 11026 | addiu $at,$at,<loconstant> (BFD_RELOC_LO16) |
| 11027 | addu $tempreg,$tempreg,$at |
| 11028 | */ |
| 11029 | |
| 11030 | expr1.X_add_number = offset_expr.X_add_number; |
| 11031 | offset_expr.X_add_number = 0; |
| 11032 | relax_start (offset_expr.X_add_symbol); |
| 11033 | gpdelay = reg_needs_delay (mips_gp_register); |
| 11034 | if (expr1.X_add_number == 0 && breg == 0 |
| 11035 | && (call || tempreg == PIC_CALL_REG)) |
| 11036 | { |
| 11037 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; |
| 11038 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; |
| 11039 | } |
| 11040 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
| 11041 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 11042 | tempreg, tempreg, mips_gp_register); |
| 11043 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 11044 | tempreg, lw_reloc_type, tempreg); |
| 11045 | if (expr1.X_add_number == 0) |
| 11046 | { |
| 11047 | if (breg != 0) |
| 11048 | { |
| 11049 | /* We're going to put in an addu instruction using |
| 11050 | tempreg, so we may as well insert the nop right |
| 11051 | now. */ |
| 11052 | load_delay_nop (); |
| 11053 | } |
| 11054 | } |
| 11055 | else if (expr1.X_add_number >= -0x8000 |
| 11056 | && expr1.X_add_number < 0x8000) |
| 11057 | { |
| 11058 | load_delay_nop (); |
| 11059 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
| 11060 | tempreg, tempreg, BFD_RELOC_LO16); |
| 11061 | } |
| 11062 | else |
| 11063 | { |
| 11064 | unsigned int dreg; |
| 11065 | |
| 11066 | /* If we are going to add in a base register, and the |
| 11067 | target register and the base register are the same, |
| 11068 | then we are using AT as a temporary register. Since |
| 11069 | we want to load the constant into AT, we add our |
| 11070 | current AT (from the global offset table) and the |
| 11071 | register into the register now, and pretend we were |
| 11072 | not using a base register. */ |
| 11073 | if (breg != op[0]) |
| 11074 | dreg = tempreg; |
| 11075 | else |
| 11076 | { |
| 11077 | gas_assert (tempreg == AT); |
| 11078 | load_delay_nop (); |
| 11079 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 11080 | op[0], AT, breg); |
| 11081 | dreg = op[0]; |
| 11082 | } |
| 11083 | |
| 11084 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
| 11085 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
| 11086 | |
| 11087 | used_at = 1; |
| 11088 | } |
| 11089 | offset_expr.X_add_number = SEXT_16BIT (expr1.X_add_number); |
| 11090 | relax_switch (); |
| 11091 | |
| 11092 | if (gpdelay) |
| 11093 | { |
| 11094 | /* This is needed because this instruction uses $gp, but |
| 11095 | the first instruction on the main stream does not. */ |
| 11096 | macro_build (NULL, "nop", ""); |
| 11097 | } |
| 11098 | |
| 11099 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 11100 | local_reloc_type, mips_gp_register); |
| 11101 | if (expr1.X_add_number >= -0x8000 |
| 11102 | && expr1.X_add_number < 0x8000) |
| 11103 | { |
| 11104 | load_delay_nop (); |
| 11105 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
| 11106 | tempreg, tempreg, BFD_RELOC_LO16); |
| 11107 | /* FIXME: If add_number is 0, and there was no base |
| 11108 | register, the external symbol case ended with a load, |
| 11109 | so if the symbol turns out to not be external, and |
| 11110 | the next instruction uses tempreg, an unnecessary nop |
| 11111 | will be inserted. */ |
| 11112 | } |
| 11113 | else |
| 11114 | { |
| 11115 | if (breg == op[0]) |
| 11116 | { |
| 11117 | /* We must add in the base register now, as in the |
| 11118 | external symbol case. */ |
| 11119 | gas_assert (tempreg == AT); |
| 11120 | load_delay_nop (); |
| 11121 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 11122 | op[0], AT, breg); |
| 11123 | tempreg = op[0]; |
| 11124 | /* We set breg to 0 because we have arranged to add |
| 11125 | it in in both cases. */ |
| 11126 | breg = 0; |
| 11127 | } |
| 11128 | |
| 11129 | macro_build_lui (&expr1, AT); |
| 11130 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
| 11131 | AT, AT, BFD_RELOC_LO16); |
| 11132 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 11133 | tempreg, tempreg, AT); |
| 11134 | used_at = 1; |
| 11135 | } |
| 11136 | relax_end (); |
| 11137 | } |
| 11138 | else if (mips_big_got && HAVE_NEWABI) |
| 11139 | { |
| 11140 | int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16; |
| 11141 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16; |
| 11142 | int add_breg_early = 0; |
| 11143 | |
| 11144 | /* This is the large GOT case. If this is a reference to an |
| 11145 | external symbol, and there is no constant, we want |
| 11146 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 11147 | add $tempreg,$tempreg,$gp |
| 11148 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 11149 | or for lca or if tempreg is PIC_CALL_REG |
| 11150 | lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
| 11151 | add $tempreg,$tempreg,$gp |
| 11152 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16) |
| 11153 | |
| 11154 | If we have a small constant, and this is a reference to |
| 11155 | an external symbol, we want |
| 11156 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 11157 | add $tempreg,$tempreg,$gp |
| 11158 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 11159 | addi $tempreg,$tempreg,<constant> |
| 11160 | |
| 11161 | If we have a large constant, and this is a reference to |
| 11162 | an external symbol, we want |
| 11163 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 11164 | addu $tempreg,$tempreg,$gp |
| 11165 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 11166 | lui $at,<hiconstant> |
| 11167 | addi $at,$at,<loconstant> |
| 11168 | add $tempreg,$tempreg,$at |
| 11169 | |
| 11170 | If we have NewABI, and we know it's a local symbol, we want |
| 11171 | lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
| 11172 | addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST) |
| 11173 | otherwise we have to resort to GOT_HI16/GOT_LO16. */ |
| 11174 | |
| 11175 | relax_start (offset_expr.X_add_symbol); |
| 11176 | |
| 11177 | expr1.X_add_number = offset_expr.X_add_number; |
| 11178 | offset_expr.X_add_number = 0; |
| 11179 | |
| 11180 | if (expr1.X_add_number == 0 && breg == 0 |
| 11181 | && (call || tempreg == PIC_CALL_REG)) |
| 11182 | { |
| 11183 | lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16; |
| 11184 | lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16; |
| 11185 | } |
| 11186 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, lui_reloc_type); |
| 11187 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 11188 | tempreg, tempreg, mips_gp_register); |
| 11189 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 11190 | tempreg, lw_reloc_type, tempreg); |
| 11191 | |
| 11192 | if (expr1.X_add_number == 0) |
| 11193 | ; |
| 11194 | else if (expr1.X_add_number >= -0x8000 |
| 11195 | && expr1.X_add_number < 0x8000) |
| 11196 | { |
| 11197 | macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j", |
| 11198 | tempreg, tempreg, BFD_RELOC_LO16); |
| 11199 | } |
| 11200 | else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000)) |
| 11201 | { |
| 11202 | unsigned int dreg; |
| 11203 | |
| 11204 | /* If we are going to add in a base register, and the |
| 11205 | target register and the base register are the same, |
| 11206 | then we are using AT as a temporary register. Since |
| 11207 | we want to load the constant into AT, we add our |
| 11208 | current AT (from the global offset table) and the |
| 11209 | register into the register now, and pretend we were |
| 11210 | not using a base register. */ |
| 11211 | if (breg != op[0]) |
| 11212 | dreg = tempreg; |
| 11213 | else |
| 11214 | { |
| 11215 | gas_assert (tempreg == AT); |
| 11216 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 11217 | op[0], AT, breg); |
| 11218 | dreg = op[0]; |
| 11219 | add_breg_early = 1; |
| 11220 | } |
| 11221 | |
| 11222 | load_register (AT, &expr1, HAVE_64BIT_ADDRESSES); |
| 11223 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT); |
| 11224 | |
| 11225 | used_at = 1; |
| 11226 | } |
| 11227 | else |
| 11228 | as_bad (_("PIC code offset overflow (max 32 signed bits)")); |
| 11229 | |
| 11230 | relax_switch (); |
| 11231 | offset_expr.X_add_number = expr1.X_add_number; |
| 11232 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 11233 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
| 11234 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
| 11235 | tempreg, BFD_RELOC_MIPS_GOT_OFST); |
| 11236 | if (add_breg_early) |
| 11237 | { |
| 11238 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 11239 | op[0], tempreg, breg); |
| 11240 | breg = 0; |
| 11241 | tempreg = op[0]; |
| 11242 | } |
| 11243 | relax_end (); |
| 11244 | } |
| 11245 | else |
| 11246 | abort (); |
| 11247 | |
| 11248 | if (breg != 0) |
| 11249 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); |
| 11250 | break; |
| 11251 | |
| 11252 | case M_MSGSND: |
| 11253 | gas_assert (!mips_opts.micromips); |
| 11254 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x01); |
| 11255 | break; |
| 11256 | |
| 11257 | case M_MSGLD: |
| 11258 | gas_assert (!mips_opts.micromips); |
| 11259 | macro_build (NULL, "c2", "C", 0x02); |
| 11260 | break; |
| 11261 | |
| 11262 | case M_MSGLD_T: |
| 11263 | gas_assert (!mips_opts.micromips); |
| 11264 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x02); |
| 11265 | break; |
| 11266 | |
| 11267 | case M_MSGWAIT: |
| 11268 | gas_assert (!mips_opts.micromips); |
| 11269 | macro_build (NULL, "c2", "C", 3); |
| 11270 | break; |
| 11271 | |
| 11272 | case M_MSGWAIT_T: |
| 11273 | gas_assert (!mips_opts.micromips); |
| 11274 | macro_build (NULL, "c2", "C", (op[0] << 16) | 0x03); |
| 11275 | break; |
| 11276 | |
| 11277 | case M_J_A: |
| 11278 | /* The j instruction may not be used in PIC code, since it |
| 11279 | requires an absolute address. We convert it to a b |
| 11280 | instruction. */ |
| 11281 | if (mips_pic == NO_PIC) |
| 11282 | macro_build (&offset_expr, "j", "a"); |
| 11283 | else |
| 11284 | macro_build (&offset_expr, "b", "p"); |
| 11285 | break; |
| 11286 | |
| 11287 | /* The jal instructions must be handled as macros because when |
| 11288 | generating PIC code they expand to multi-instruction |
| 11289 | sequences. Normally they are simple instructions. */ |
| 11290 | case M_JALS_1: |
| 11291 | op[1] = op[0]; |
| 11292 | op[0] = RA; |
| 11293 | /* Fall through. */ |
| 11294 | case M_JALS_2: |
| 11295 | gas_assert (mips_opts.micromips); |
| 11296 | if (mips_opts.insn32) |
| 11297 | { |
| 11298 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
| 11299 | break; |
| 11300 | } |
| 11301 | jals = 1; |
| 11302 | goto jal; |
| 11303 | case M_JAL_1: |
| 11304 | op[1] = op[0]; |
| 11305 | op[0] = RA; |
| 11306 | /* Fall through. */ |
| 11307 | case M_JAL_2: |
| 11308 | jal: |
| 11309 | if (mips_pic == NO_PIC) |
| 11310 | { |
| 11311 | s = jals ? "jalrs" : "jalr"; |
| 11312 | if (mips_opts.micromips |
| 11313 | && !mips_opts.insn32 |
| 11314 | && op[0] == RA |
| 11315 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
| 11316 | macro_build (NULL, s, "mj", op[1]); |
| 11317 | else |
| 11318 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
| 11319 | } |
| 11320 | else |
| 11321 | { |
| 11322 | int cprestore = (mips_pic == SVR4_PIC && !HAVE_NEWABI |
| 11323 | && mips_cprestore_offset >= 0); |
| 11324 | |
| 11325 | if (op[1] != PIC_CALL_REG) |
| 11326 | as_warn (_("MIPS PIC call to register other than $25")); |
| 11327 | |
| 11328 | s = ((mips_opts.micromips |
| 11329 | && !mips_opts.insn32 |
| 11330 | && (!mips_opts.noreorder || cprestore)) |
| 11331 | ? "jalrs" : "jalr"); |
| 11332 | if (mips_opts.micromips |
| 11333 | && !mips_opts.insn32 |
| 11334 | && op[0] == RA |
| 11335 | && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) |
| 11336 | macro_build (NULL, s, "mj", op[1]); |
| 11337 | else |
| 11338 | macro_build (NULL, s, JALR_FMT, op[0], op[1]); |
| 11339 | if (mips_pic == SVR4_PIC && !HAVE_NEWABI) |
| 11340 | { |
| 11341 | if (mips_cprestore_offset < 0) |
| 11342 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
| 11343 | else |
| 11344 | { |
| 11345 | if (!mips_frame_reg_valid) |
| 11346 | { |
| 11347 | as_warn (_("no .frame pseudo-op used in PIC code")); |
| 11348 | /* Quiet this warning. */ |
| 11349 | mips_frame_reg_valid = 1; |
| 11350 | } |
| 11351 | if (!mips_cprestore_valid) |
| 11352 | { |
| 11353 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
| 11354 | /* Quiet this warning. */ |
| 11355 | mips_cprestore_valid = 1; |
| 11356 | } |
| 11357 | if (mips_opts.noreorder) |
| 11358 | macro_build (NULL, "nop", ""); |
| 11359 | expr1.X_add_number = mips_cprestore_offset; |
| 11360 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
| 11361 | mips_gp_register, |
| 11362 | mips_frame_reg, |
| 11363 | HAVE_64BIT_ADDRESSES); |
| 11364 | } |
| 11365 | } |
| 11366 | } |
| 11367 | |
| 11368 | break; |
| 11369 | |
| 11370 | case M_JALS_A: |
| 11371 | gas_assert (mips_opts.micromips); |
| 11372 | if (mips_opts.insn32) |
| 11373 | { |
| 11374 | as_bad (_("opcode not supported in the `insn32' mode `%s'"), str); |
| 11375 | break; |
| 11376 | } |
| 11377 | jals = 1; |
| 11378 | /* Fall through. */ |
| 11379 | case M_JAL_A: |
| 11380 | if (mips_pic == NO_PIC) |
| 11381 | macro_build (&offset_expr, jals ? "jals" : "jal", "a"); |
| 11382 | else if (mips_pic == SVR4_PIC) |
| 11383 | { |
| 11384 | /* If this is a reference to an external symbol, and we are |
| 11385 | using a small GOT, we want |
| 11386 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16) |
| 11387 | nop |
| 11388 | jalr $ra,$25 |
| 11389 | nop |
| 11390 | lw $gp,cprestore($sp) |
| 11391 | The cprestore value is set using the .cprestore |
| 11392 | pseudo-op. If we are using a big GOT, we want |
| 11393 | lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16) |
| 11394 | addu $25,$25,$gp |
| 11395 | lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16) |
| 11396 | nop |
| 11397 | jalr $ra,$25 |
| 11398 | nop |
| 11399 | lw $gp,cprestore($sp) |
| 11400 | If the symbol is not external, we want |
| 11401 | lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 11402 | nop |
| 11403 | addiu $25,$25,<sym> (BFD_RELOC_LO16) |
| 11404 | jalr $ra,$25 |
| 11405 | nop |
| 11406 | lw $gp,cprestore($sp) |
| 11407 | |
| 11408 | For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16 |
| 11409 | sequences above, minus nops, unless the symbol is local, |
| 11410 | which enables us to use GOT_PAGE/GOT_OFST (big got) or |
| 11411 | GOT_DISP. */ |
| 11412 | if (HAVE_NEWABI) |
| 11413 | { |
| 11414 | if (!mips_big_got) |
| 11415 | { |
| 11416 | relax_start (offset_expr.X_add_symbol); |
| 11417 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 11418 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, |
| 11419 | mips_gp_register); |
| 11420 | relax_switch (); |
| 11421 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 11422 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP, |
| 11423 | mips_gp_register); |
| 11424 | relax_end (); |
| 11425 | } |
| 11426 | else |
| 11427 | { |
| 11428 | relax_start (offset_expr.X_add_symbol); |
| 11429 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
| 11430 | BFD_RELOC_MIPS_CALL_HI16); |
| 11431 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, |
| 11432 | PIC_CALL_REG, mips_gp_register); |
| 11433 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 11434 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, |
| 11435 | PIC_CALL_REG); |
| 11436 | relax_switch (); |
| 11437 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 11438 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE, |
| 11439 | mips_gp_register); |
| 11440 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
| 11441 | PIC_CALL_REG, PIC_CALL_REG, |
| 11442 | BFD_RELOC_MIPS_GOT_OFST); |
| 11443 | relax_end (); |
| 11444 | } |
| 11445 | |
| 11446 | macro_build_jalr (&offset_expr, 0); |
| 11447 | } |
| 11448 | else |
| 11449 | { |
| 11450 | relax_start (offset_expr.X_add_symbol); |
| 11451 | if (!mips_big_got) |
| 11452 | { |
| 11453 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 11454 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL16, |
| 11455 | mips_gp_register); |
| 11456 | load_delay_nop (); |
| 11457 | relax_switch (); |
| 11458 | } |
| 11459 | else |
| 11460 | { |
| 11461 | int gpdelay; |
| 11462 | |
| 11463 | gpdelay = reg_needs_delay (mips_gp_register); |
| 11464 | macro_build (&offset_expr, "lui", LUI_FMT, PIC_CALL_REG, |
| 11465 | BFD_RELOC_MIPS_CALL_HI16); |
| 11466 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG, |
| 11467 | PIC_CALL_REG, mips_gp_register); |
| 11468 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 11469 | PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16, |
| 11470 | PIC_CALL_REG); |
| 11471 | load_delay_nop (); |
| 11472 | relax_switch (); |
| 11473 | if (gpdelay) |
| 11474 | macro_build (NULL, "nop", ""); |
| 11475 | } |
| 11476 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 11477 | PIC_CALL_REG, BFD_RELOC_MIPS_GOT16, |
| 11478 | mips_gp_register); |
| 11479 | load_delay_nop (); |
| 11480 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
| 11481 | PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16); |
| 11482 | relax_end (); |
| 11483 | macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0); |
| 11484 | |
| 11485 | if (mips_cprestore_offset < 0) |
| 11486 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
| 11487 | else |
| 11488 | { |
| 11489 | if (!mips_frame_reg_valid) |
| 11490 | { |
| 11491 | as_warn (_("no .frame pseudo-op used in PIC code")); |
| 11492 | /* Quiet this warning. */ |
| 11493 | mips_frame_reg_valid = 1; |
| 11494 | } |
| 11495 | if (!mips_cprestore_valid) |
| 11496 | { |
| 11497 | as_warn (_("no .cprestore pseudo-op used in PIC code")); |
| 11498 | /* Quiet this warning. */ |
| 11499 | mips_cprestore_valid = 1; |
| 11500 | } |
| 11501 | if (mips_opts.noreorder) |
| 11502 | macro_build (NULL, "nop", ""); |
| 11503 | expr1.X_add_number = mips_cprestore_offset; |
| 11504 | macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, |
| 11505 | mips_gp_register, |
| 11506 | mips_frame_reg, |
| 11507 | HAVE_64BIT_ADDRESSES); |
| 11508 | } |
| 11509 | } |
| 11510 | } |
| 11511 | else if (mips_pic == VXWORKS_PIC) |
| 11512 | as_bad (_("non-PIC jump used in PIC library")); |
| 11513 | else |
| 11514 | abort (); |
| 11515 | |
| 11516 | break; |
| 11517 | |
| 11518 | case M_LBUE_AB: |
| 11519 | s = "lbue"; |
| 11520 | fmt = "t,+j(b)"; |
| 11521 | offbits = 9; |
| 11522 | goto ld_st; |
| 11523 | case M_LHUE_AB: |
| 11524 | s = "lhue"; |
| 11525 | fmt = "t,+j(b)"; |
| 11526 | offbits = 9; |
| 11527 | goto ld_st; |
| 11528 | case M_LBE_AB: |
| 11529 | s = "lbe"; |
| 11530 | fmt = "t,+j(b)"; |
| 11531 | offbits = 9; |
| 11532 | goto ld_st; |
| 11533 | case M_LHE_AB: |
| 11534 | s = "lhe"; |
| 11535 | fmt = "t,+j(b)"; |
| 11536 | offbits = 9; |
| 11537 | goto ld_st; |
| 11538 | case M_LLE_AB: |
| 11539 | s = "lle"; |
| 11540 | fmt = "t,+j(b)"; |
| 11541 | offbits = 9; |
| 11542 | goto ld_st; |
| 11543 | case M_LWE_AB: |
| 11544 | s = "lwe"; |
| 11545 | fmt = "t,+j(b)"; |
| 11546 | offbits = 9; |
| 11547 | goto ld_st; |
| 11548 | case M_LWLE_AB: |
| 11549 | s = "lwle"; |
| 11550 | fmt = "t,+j(b)"; |
| 11551 | offbits = 9; |
| 11552 | goto ld_st; |
| 11553 | case M_LWRE_AB: |
| 11554 | s = "lwre"; |
| 11555 | fmt = "t,+j(b)"; |
| 11556 | offbits = 9; |
| 11557 | goto ld_st; |
| 11558 | case M_SBE_AB: |
| 11559 | s = "sbe"; |
| 11560 | fmt = "t,+j(b)"; |
| 11561 | offbits = 9; |
| 11562 | goto ld_st; |
| 11563 | case M_SCE_AB: |
| 11564 | s = "sce"; |
| 11565 | fmt = "t,+j(b)"; |
| 11566 | offbits = 9; |
| 11567 | goto ld_st; |
| 11568 | case M_SHE_AB: |
| 11569 | s = "she"; |
| 11570 | fmt = "t,+j(b)"; |
| 11571 | offbits = 9; |
| 11572 | goto ld_st; |
| 11573 | case M_SWE_AB: |
| 11574 | s = "swe"; |
| 11575 | fmt = "t,+j(b)"; |
| 11576 | offbits = 9; |
| 11577 | goto ld_st; |
| 11578 | case M_SWLE_AB: |
| 11579 | s = "swle"; |
| 11580 | fmt = "t,+j(b)"; |
| 11581 | offbits = 9; |
| 11582 | goto ld_st; |
| 11583 | case M_SWRE_AB: |
| 11584 | s = "swre"; |
| 11585 | fmt = "t,+j(b)"; |
| 11586 | offbits = 9; |
| 11587 | goto ld_st; |
| 11588 | case M_ACLR_AB: |
| 11589 | s = "aclr"; |
| 11590 | fmt = "\\,~(b)"; |
| 11591 | offbits = 12; |
| 11592 | goto ld_st; |
| 11593 | case M_ASET_AB: |
| 11594 | s = "aset"; |
| 11595 | fmt = "\\,~(b)"; |
| 11596 | offbits = 12; |
| 11597 | goto ld_st; |
| 11598 | case M_LB_AB: |
| 11599 | s = "lb"; |
| 11600 | fmt = "t,o(b)"; |
| 11601 | goto ld; |
| 11602 | case M_LBU_AB: |
| 11603 | s = "lbu"; |
| 11604 | fmt = "t,o(b)"; |
| 11605 | goto ld; |
| 11606 | case M_LH_AB: |
| 11607 | s = "lh"; |
| 11608 | fmt = "t,o(b)"; |
| 11609 | goto ld; |
| 11610 | case M_LHU_AB: |
| 11611 | s = "lhu"; |
| 11612 | fmt = "t,o(b)"; |
| 11613 | goto ld; |
| 11614 | case M_LW_AB: |
| 11615 | s = "lw"; |
| 11616 | fmt = "t,o(b)"; |
| 11617 | goto ld; |
| 11618 | case M_LWC0_AB: |
| 11619 | gas_assert (!mips_opts.micromips); |
| 11620 | s = "lwc0"; |
| 11621 | fmt = "E,o(b)"; |
| 11622 | /* Itbl support may require additional care here. */ |
| 11623 | coproc = 1; |
| 11624 | goto ld_st; |
| 11625 | case M_LWC1_AB: |
| 11626 | s = "lwc1"; |
| 11627 | fmt = "T,o(b)"; |
| 11628 | /* Itbl support may require additional care here. */ |
| 11629 | coproc = 1; |
| 11630 | goto ld_st; |
| 11631 | case M_LWC2_AB: |
| 11632 | s = "lwc2"; |
| 11633 | fmt = COP12_FMT; |
| 11634 | offbits = (mips_opts.micromips ? 12 |
| 11635 | : ISA_IS_R6 (mips_opts.isa) ? 11 |
| 11636 | : 16); |
| 11637 | /* Itbl support may require additional care here. */ |
| 11638 | coproc = 1; |
| 11639 | goto ld_st; |
| 11640 | case M_LWC3_AB: |
| 11641 | gas_assert (!mips_opts.micromips); |
| 11642 | s = "lwc3"; |
| 11643 | fmt = "E,o(b)"; |
| 11644 | /* Itbl support may require additional care here. */ |
| 11645 | coproc = 1; |
| 11646 | goto ld_st; |
| 11647 | case M_LWL_AB: |
| 11648 | s = "lwl"; |
| 11649 | fmt = MEM12_FMT; |
| 11650 | offbits = (mips_opts.micromips ? 12 : 16); |
| 11651 | goto ld_st; |
| 11652 | case M_LWR_AB: |
| 11653 | s = "lwr"; |
| 11654 | fmt = MEM12_FMT; |
| 11655 | offbits = (mips_opts.micromips ? 12 : 16); |
| 11656 | goto ld_st; |
| 11657 | case M_LDC1_AB: |
| 11658 | s = "ldc1"; |
| 11659 | fmt = "T,o(b)"; |
| 11660 | /* Itbl support may require additional care here. */ |
| 11661 | coproc = 1; |
| 11662 | goto ld_st; |
| 11663 | case M_LDC2_AB: |
| 11664 | s = "ldc2"; |
| 11665 | fmt = COP12_FMT; |
| 11666 | offbits = (mips_opts.micromips ? 12 |
| 11667 | : ISA_IS_R6 (mips_opts.isa) ? 11 |
| 11668 | : 16); |
| 11669 | /* Itbl support may require additional care here. */ |
| 11670 | coproc = 1; |
| 11671 | goto ld_st; |
| 11672 | case M_LQC2_AB: |
| 11673 | s = "lqc2"; |
| 11674 | fmt = "+7,o(b)"; |
| 11675 | /* Itbl support may require additional care here. */ |
| 11676 | coproc = 1; |
| 11677 | goto ld_st; |
| 11678 | case M_LDC3_AB: |
| 11679 | s = "ldc3"; |
| 11680 | fmt = "E,o(b)"; |
| 11681 | /* Itbl support may require additional care here. */ |
| 11682 | coproc = 1; |
| 11683 | goto ld_st; |
| 11684 | case M_LDL_AB: |
| 11685 | s = "ldl"; |
| 11686 | fmt = MEM12_FMT; |
| 11687 | offbits = (mips_opts.micromips ? 12 : 16); |
| 11688 | goto ld_st; |
| 11689 | case M_LDR_AB: |
| 11690 | s = "ldr"; |
| 11691 | fmt = MEM12_FMT; |
| 11692 | offbits = (mips_opts.micromips ? 12 : 16); |
| 11693 | goto ld_st; |
| 11694 | case M_LL_AB: |
| 11695 | s = "ll"; |
| 11696 | fmt = LL_SC_FMT; |
| 11697 | offbits = (mips_opts.micromips ? 12 |
| 11698 | : ISA_IS_R6 (mips_opts.isa) ? 9 |
| 11699 | : 16); |
| 11700 | goto ld; |
| 11701 | case M_LLD_AB: |
| 11702 | s = "lld"; |
| 11703 | fmt = LL_SC_FMT; |
| 11704 | offbits = (mips_opts.micromips ? 12 |
| 11705 | : ISA_IS_R6 (mips_opts.isa) ? 9 |
| 11706 | : 16); |
| 11707 | goto ld; |
| 11708 | case M_LWU_AB: |
| 11709 | s = "lwu"; |
| 11710 | fmt = MEM12_FMT; |
| 11711 | offbits = (mips_opts.micromips ? 12 : 16); |
| 11712 | goto ld; |
| 11713 | case M_LWP_AB: |
| 11714 | gas_assert (mips_opts.micromips); |
| 11715 | s = "lwp"; |
| 11716 | fmt = "t,~(b)"; |
| 11717 | offbits = 12; |
| 11718 | lp = 1; |
| 11719 | goto ld; |
| 11720 | case M_LDP_AB: |
| 11721 | gas_assert (mips_opts.micromips); |
| 11722 | s = "ldp"; |
| 11723 | fmt = "t,~(b)"; |
| 11724 | offbits = 12; |
| 11725 | lp = 1; |
| 11726 | goto ld; |
| 11727 | case M_LWM_AB: |
| 11728 | gas_assert (mips_opts.micromips); |
| 11729 | s = "lwm"; |
| 11730 | fmt = "n,~(b)"; |
| 11731 | offbits = 12; |
| 11732 | goto ld_st; |
| 11733 | case M_LDM_AB: |
| 11734 | gas_assert (mips_opts.micromips); |
| 11735 | s = "ldm"; |
| 11736 | fmt = "n,~(b)"; |
| 11737 | offbits = 12; |
| 11738 | goto ld_st; |
| 11739 | |
| 11740 | ld: |
| 11741 | /* We don't want to use $0 as tempreg. */ |
| 11742 | if (op[2] == op[0] + lp || op[0] + lp == ZERO) |
| 11743 | goto ld_st; |
| 11744 | else |
| 11745 | tempreg = op[0] + lp; |
| 11746 | goto ld_noat; |
| 11747 | |
| 11748 | case M_SB_AB: |
| 11749 | s = "sb"; |
| 11750 | fmt = "t,o(b)"; |
| 11751 | goto ld_st; |
| 11752 | case M_SH_AB: |
| 11753 | s = "sh"; |
| 11754 | fmt = "t,o(b)"; |
| 11755 | goto ld_st; |
| 11756 | case M_SW_AB: |
| 11757 | s = "sw"; |
| 11758 | fmt = "t,o(b)"; |
| 11759 | goto ld_st; |
| 11760 | case M_SWC0_AB: |
| 11761 | gas_assert (!mips_opts.micromips); |
| 11762 | s = "swc0"; |
| 11763 | fmt = "E,o(b)"; |
| 11764 | /* Itbl support may require additional care here. */ |
| 11765 | coproc = 1; |
| 11766 | goto ld_st; |
| 11767 | case M_SWC1_AB: |
| 11768 | s = "swc1"; |
| 11769 | fmt = "T,o(b)"; |
| 11770 | /* Itbl support may require additional care here. */ |
| 11771 | coproc = 1; |
| 11772 | goto ld_st; |
| 11773 | case M_SWC2_AB: |
| 11774 | s = "swc2"; |
| 11775 | fmt = COP12_FMT; |
| 11776 | offbits = (mips_opts.micromips ? 12 |
| 11777 | : ISA_IS_R6 (mips_opts.isa) ? 11 |
| 11778 | : 16); |
| 11779 | /* Itbl support may require additional care here. */ |
| 11780 | coproc = 1; |
| 11781 | goto ld_st; |
| 11782 | case M_SWC3_AB: |
| 11783 | gas_assert (!mips_opts.micromips); |
| 11784 | s = "swc3"; |
| 11785 | fmt = "E,o(b)"; |
| 11786 | /* Itbl support may require additional care here. */ |
| 11787 | coproc = 1; |
| 11788 | goto ld_st; |
| 11789 | case M_SWL_AB: |
| 11790 | s = "swl"; |
| 11791 | fmt = MEM12_FMT; |
| 11792 | offbits = (mips_opts.micromips ? 12 : 16); |
| 11793 | goto ld_st; |
| 11794 | case M_SWR_AB: |
| 11795 | s = "swr"; |
| 11796 | fmt = MEM12_FMT; |
| 11797 | offbits = (mips_opts.micromips ? 12 : 16); |
| 11798 | goto ld_st; |
| 11799 | case M_SC_AB: |
| 11800 | s = "sc"; |
| 11801 | fmt = LL_SC_FMT; |
| 11802 | offbits = (mips_opts.micromips ? 12 |
| 11803 | : ISA_IS_R6 (mips_opts.isa) ? 9 |
| 11804 | : 16); |
| 11805 | goto ld_st; |
| 11806 | case M_SCD_AB: |
| 11807 | s = "scd"; |
| 11808 | fmt = LL_SC_FMT; |
| 11809 | offbits = (mips_opts.micromips ? 12 |
| 11810 | : ISA_IS_R6 (mips_opts.isa) ? 9 |
| 11811 | : 16); |
| 11812 | goto ld_st; |
| 11813 | case M_CACHE_AB: |
| 11814 | s = "cache"; |
| 11815 | fmt = (mips_opts.micromips ? "k,~(b)" |
| 11816 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" |
| 11817 | : "k,o(b)"); |
| 11818 | offbits = (mips_opts.micromips ? 12 |
| 11819 | : ISA_IS_R6 (mips_opts.isa) ? 9 |
| 11820 | : 16); |
| 11821 | goto ld_st; |
| 11822 | case M_CACHEE_AB: |
| 11823 | s = "cachee"; |
| 11824 | fmt = "k,+j(b)"; |
| 11825 | offbits = 9; |
| 11826 | goto ld_st; |
| 11827 | case M_PREF_AB: |
| 11828 | s = "pref"; |
| 11829 | fmt = (mips_opts.micromips ? "k,~(b)" |
| 11830 | : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)" |
| 11831 | : "k,o(b)"); |
| 11832 | offbits = (mips_opts.micromips ? 12 |
| 11833 | : ISA_IS_R6 (mips_opts.isa) ? 9 |
| 11834 | : 16); |
| 11835 | goto ld_st; |
| 11836 | case M_PREFE_AB: |
| 11837 | s = "prefe"; |
| 11838 | fmt = "k,+j(b)"; |
| 11839 | offbits = 9; |
| 11840 | goto ld_st; |
| 11841 | case M_SDC1_AB: |
| 11842 | s = "sdc1"; |
| 11843 | fmt = "T,o(b)"; |
| 11844 | coproc = 1; |
| 11845 | /* Itbl support may require additional care here. */ |
| 11846 | goto ld_st; |
| 11847 | case M_SDC2_AB: |
| 11848 | s = "sdc2"; |
| 11849 | fmt = COP12_FMT; |
| 11850 | offbits = (mips_opts.micromips ? 12 |
| 11851 | : ISA_IS_R6 (mips_opts.isa) ? 11 |
| 11852 | : 16); |
| 11853 | /* Itbl support may require additional care here. */ |
| 11854 | coproc = 1; |
| 11855 | goto ld_st; |
| 11856 | case M_SQC2_AB: |
| 11857 | s = "sqc2"; |
| 11858 | fmt = "+7,o(b)"; |
| 11859 | /* Itbl support may require additional care here. */ |
| 11860 | coproc = 1; |
| 11861 | goto ld_st; |
| 11862 | case M_SDC3_AB: |
| 11863 | gas_assert (!mips_opts.micromips); |
| 11864 | s = "sdc3"; |
| 11865 | fmt = "E,o(b)"; |
| 11866 | /* Itbl support may require additional care here. */ |
| 11867 | coproc = 1; |
| 11868 | goto ld_st; |
| 11869 | case M_SDL_AB: |
| 11870 | s = "sdl"; |
| 11871 | fmt = MEM12_FMT; |
| 11872 | offbits = (mips_opts.micromips ? 12 : 16); |
| 11873 | goto ld_st; |
| 11874 | case M_SDR_AB: |
| 11875 | s = "sdr"; |
| 11876 | fmt = MEM12_FMT; |
| 11877 | offbits = (mips_opts.micromips ? 12 : 16); |
| 11878 | goto ld_st; |
| 11879 | case M_SWP_AB: |
| 11880 | gas_assert (mips_opts.micromips); |
| 11881 | s = "swp"; |
| 11882 | fmt = "t,~(b)"; |
| 11883 | offbits = 12; |
| 11884 | goto ld_st; |
| 11885 | case M_SDP_AB: |
| 11886 | gas_assert (mips_opts.micromips); |
| 11887 | s = "sdp"; |
| 11888 | fmt = "t,~(b)"; |
| 11889 | offbits = 12; |
| 11890 | goto ld_st; |
| 11891 | case M_SWM_AB: |
| 11892 | gas_assert (mips_opts.micromips); |
| 11893 | s = "swm"; |
| 11894 | fmt = "n,~(b)"; |
| 11895 | offbits = 12; |
| 11896 | goto ld_st; |
| 11897 | case M_SDM_AB: |
| 11898 | gas_assert (mips_opts.micromips); |
| 11899 | s = "sdm"; |
| 11900 | fmt = "n,~(b)"; |
| 11901 | offbits = 12; |
| 11902 | |
| 11903 | ld_st: |
| 11904 | tempreg = AT; |
| 11905 | ld_noat: |
| 11906 | breg = op[2]; |
| 11907 | if (small_offset_p (0, align, 16)) |
| 11908 | { |
| 11909 | /* The first case exists for M_LD_AB and M_SD_AB, which are |
| 11910 | macros for o32 but which should act like normal instructions |
| 11911 | otherwise. */ |
| 11912 | if (offbits == 16) |
| 11913 | macro_build (&offset_expr, s, fmt, op[0], -1, offset_reloc[0], |
| 11914 | offset_reloc[1], offset_reloc[2], breg); |
| 11915 | else if (small_offset_p (0, align, offbits)) |
| 11916 | { |
| 11917 | if (offbits == 0) |
| 11918 | macro_build (NULL, s, fmt, op[0], breg); |
| 11919 | else |
| 11920 | macro_build (NULL, s, fmt, op[0], |
| 11921 | (int) offset_expr.X_add_number, breg); |
| 11922 | } |
| 11923 | else |
| 11924 | { |
| 11925 | if (tempreg == AT) |
| 11926 | used_at = 1; |
| 11927 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", |
| 11928 | tempreg, breg, -1, offset_reloc[0], |
| 11929 | offset_reloc[1], offset_reloc[2]); |
| 11930 | if (offbits == 0) |
| 11931 | macro_build (NULL, s, fmt, op[0], tempreg); |
| 11932 | else |
| 11933 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
| 11934 | } |
| 11935 | break; |
| 11936 | } |
| 11937 | |
| 11938 | if (tempreg == AT) |
| 11939 | used_at = 1; |
| 11940 | |
| 11941 | if (offset_expr.X_op != O_constant |
| 11942 | && offset_expr.X_op != O_symbol) |
| 11943 | { |
| 11944 | as_bad (_("expression too complex")); |
| 11945 | offset_expr.X_op = O_constant; |
| 11946 | } |
| 11947 | |
| 11948 | if (HAVE_32BIT_ADDRESSES |
| 11949 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
| 11950 | { |
| 11951 | char value [32]; |
| 11952 | |
| 11953 | sprintf_vma (value, offset_expr.X_add_number); |
| 11954 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
| 11955 | } |
| 11956 | |
| 11957 | /* A constant expression in PIC code can be handled just as it |
| 11958 | is in non PIC code. */ |
| 11959 | if (offset_expr.X_op == O_constant) |
| 11960 | { |
| 11961 | expr1.X_add_number = offset_high_part (offset_expr.X_add_number, |
| 11962 | offbits == 0 ? 16 : offbits); |
| 11963 | offset_expr.X_add_number -= expr1.X_add_number; |
| 11964 | |
| 11965 | load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); |
| 11966 | if (breg != 0) |
| 11967 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 11968 | tempreg, tempreg, breg); |
| 11969 | if (offbits == 0) |
| 11970 | { |
| 11971 | if (offset_expr.X_add_number != 0) |
| 11972 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, |
| 11973 | "t,r,j", tempreg, tempreg, BFD_RELOC_LO16); |
| 11974 | macro_build (NULL, s, fmt, op[0], tempreg); |
| 11975 | } |
| 11976 | else if (offbits == 16) |
| 11977 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
| 11978 | else |
| 11979 | macro_build (NULL, s, fmt, op[0], |
| 11980 | (int) offset_expr.X_add_number, tempreg); |
| 11981 | } |
| 11982 | else if (offbits != 16) |
| 11983 | { |
| 11984 | /* The offset field is too narrow to be used for a low-part |
| 11985 | relocation, so load the whole address into the auxiliary |
| 11986 | register. */ |
| 11987 | load_address (tempreg, &offset_expr, &used_at); |
| 11988 | if (breg != 0) |
| 11989 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 11990 | tempreg, tempreg, breg); |
| 11991 | if (offbits == 0) |
| 11992 | macro_build (NULL, s, fmt, op[0], tempreg); |
| 11993 | else |
| 11994 | macro_build (NULL, s, fmt, op[0], 0, tempreg); |
| 11995 | } |
| 11996 | else if (mips_pic == NO_PIC) |
| 11997 | { |
| 11998 | /* If this is a reference to a GP relative symbol, and there |
| 11999 | is no base register, we want |
| 12000 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
| 12001 | Otherwise, if there is no base register, we want |
| 12002 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 12003 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
| 12004 | If we have a constant, we need two instructions anyhow, |
| 12005 | so we always use the latter form. |
| 12006 | |
| 12007 | If we have a base register, and this is a reference to a |
| 12008 | GP relative symbol, we want |
| 12009 | addu $tempreg,$breg,$gp |
| 12010 | <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16) |
| 12011 | Otherwise we want |
| 12012 | lui $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 12013 | addu $tempreg,$tempreg,$breg |
| 12014 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
| 12015 | With a constant we always use the latter case. |
| 12016 | |
| 12017 | With 64bit address space and no base register and $at usable, |
| 12018 | we want |
| 12019 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 12020 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 12021 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 12022 | dsll32 $tempreg,0 |
| 12023 | daddu $tempreg,$at |
| 12024 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
| 12025 | If we have a base register, we want |
| 12026 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 12027 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 12028 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 12029 | daddu $at,$breg |
| 12030 | dsll32 $tempreg,0 |
| 12031 | daddu $tempreg,$at |
| 12032 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
| 12033 | |
| 12034 | Without $at we can't generate the optimal path for superscalar |
| 12035 | processors here since this would require two temporary registers. |
| 12036 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 12037 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 12038 | dsll $tempreg,16 |
| 12039 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 12040 | dsll $tempreg,16 |
| 12041 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
| 12042 | If we have a base register, we want |
| 12043 | lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST) |
| 12044 | daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER) |
| 12045 | dsll $tempreg,16 |
| 12046 | daddiu $tempreg,<sym> (BFD_RELOC_HI16_S) |
| 12047 | dsll $tempreg,16 |
| 12048 | daddu $tempreg,$tempreg,$breg |
| 12049 | <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16) |
| 12050 | |
| 12051 | For GP relative symbols in 64bit address space we can use |
| 12052 | the same sequence as in 32bit address space. */ |
| 12053 | if (HAVE_64BIT_SYMBOLS) |
| 12054 | { |
| 12055 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
| 12056 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 12057 | { |
| 12058 | relax_start (offset_expr.X_add_symbol); |
| 12059 | if (breg == 0) |
| 12060 | { |
| 12061 | macro_build (&offset_expr, s, fmt, op[0], |
| 12062 | BFD_RELOC_GPREL16, mips_gp_register); |
| 12063 | } |
| 12064 | else |
| 12065 | { |
| 12066 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12067 | tempreg, breg, mips_gp_register); |
| 12068 | macro_build (&offset_expr, s, fmt, op[0], |
| 12069 | BFD_RELOC_GPREL16, tempreg); |
| 12070 | } |
| 12071 | relax_switch (); |
| 12072 | } |
| 12073 | |
| 12074 | if (used_at == 0 && mips_opts.at) |
| 12075 | { |
| 12076 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
| 12077 | BFD_RELOC_MIPS_HIGHEST); |
| 12078 | macro_build (&offset_expr, "lui", LUI_FMT, AT, |
| 12079 | BFD_RELOC_HI16_S); |
| 12080 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
| 12081 | tempreg, BFD_RELOC_MIPS_HIGHER); |
| 12082 | if (breg != 0) |
| 12083 | macro_build (NULL, "daddu", "d,v,t", AT, AT, breg); |
| 12084 | macro_build (NULL, "dsll32", SHFT_FMT, tempreg, tempreg, 0); |
| 12085 | macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT); |
| 12086 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, |
| 12087 | tempreg); |
| 12088 | used_at = 1; |
| 12089 | } |
| 12090 | else |
| 12091 | { |
| 12092 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
| 12093 | BFD_RELOC_MIPS_HIGHEST); |
| 12094 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
| 12095 | tempreg, BFD_RELOC_MIPS_HIGHER); |
| 12096 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
| 12097 | macro_build (&offset_expr, "daddiu", "t,r,j", tempreg, |
| 12098 | tempreg, BFD_RELOC_HI16_S); |
| 12099 | macro_build (NULL, "dsll", SHFT_FMT, tempreg, tempreg, 16); |
| 12100 | if (breg != 0) |
| 12101 | macro_build (NULL, "daddu", "d,v,t", |
| 12102 | tempreg, tempreg, breg); |
| 12103 | macro_build (&offset_expr, s, fmt, op[0], |
| 12104 | BFD_RELOC_LO16, tempreg); |
| 12105 | } |
| 12106 | |
| 12107 | if (mips_relax.sequence) |
| 12108 | relax_end (); |
| 12109 | break; |
| 12110 | } |
| 12111 | |
| 12112 | if (breg == 0) |
| 12113 | { |
| 12114 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
| 12115 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 12116 | { |
| 12117 | relax_start (offset_expr.X_add_symbol); |
| 12118 | macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_GPREL16, |
| 12119 | mips_gp_register); |
| 12120 | relax_switch (); |
| 12121 | } |
| 12122 | macro_build_lui (&offset_expr, tempreg); |
| 12123 | macro_build (&offset_expr, s, fmt, op[0], |
| 12124 | BFD_RELOC_LO16, tempreg); |
| 12125 | if (mips_relax.sequence) |
| 12126 | relax_end (); |
| 12127 | } |
| 12128 | else |
| 12129 | { |
| 12130 | if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
| 12131 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 12132 | { |
| 12133 | relax_start (offset_expr.X_add_symbol); |
| 12134 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12135 | tempreg, breg, mips_gp_register); |
| 12136 | macro_build (&offset_expr, s, fmt, op[0], |
| 12137 | BFD_RELOC_GPREL16, tempreg); |
| 12138 | relax_switch (); |
| 12139 | } |
| 12140 | macro_build_lui (&offset_expr, tempreg); |
| 12141 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12142 | tempreg, tempreg, breg); |
| 12143 | macro_build (&offset_expr, s, fmt, op[0], |
| 12144 | BFD_RELOC_LO16, tempreg); |
| 12145 | if (mips_relax.sequence) |
| 12146 | relax_end (); |
| 12147 | } |
| 12148 | } |
| 12149 | else if (!mips_big_got) |
| 12150 | { |
| 12151 | int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16; |
| 12152 | |
| 12153 | /* If this is a reference to an external symbol, we want |
| 12154 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 12155 | nop |
| 12156 | <op> op[0],0($tempreg) |
| 12157 | Otherwise we want |
| 12158 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 12159 | nop |
| 12160 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 12161 | <op> op[0],0($tempreg) |
| 12162 | |
| 12163 | For NewABI, we want |
| 12164 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
| 12165 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) |
| 12166 | |
| 12167 | If there is a base register, we add it to $tempreg before |
| 12168 | the <op>. If there is a constant, we stick it in the |
| 12169 | <op> instruction. We don't handle constants larger than |
| 12170 | 16 bits, because we have no way to load the upper 16 bits |
| 12171 | (actually, we could handle them for the subset of cases |
| 12172 | in which we are not using $at). */ |
| 12173 | gas_assert (offset_expr.X_op == O_symbol); |
| 12174 | if (HAVE_NEWABI) |
| 12175 | { |
| 12176 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 12177 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
| 12178 | if (breg != 0) |
| 12179 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12180 | tempreg, tempreg, breg); |
| 12181 | macro_build (&offset_expr, s, fmt, op[0], |
| 12182 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
| 12183 | break; |
| 12184 | } |
| 12185 | expr1.X_add_number = offset_expr.X_add_number; |
| 12186 | offset_expr.X_add_number = 0; |
| 12187 | if (expr1.X_add_number < -0x8000 |
| 12188 | || expr1.X_add_number >= 0x8000) |
| 12189 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 12190 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 12191 | lw_reloc_type, mips_gp_register); |
| 12192 | load_delay_nop (); |
| 12193 | relax_start (offset_expr.X_add_symbol); |
| 12194 | relax_switch (); |
| 12195 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
| 12196 | tempreg, BFD_RELOC_LO16); |
| 12197 | relax_end (); |
| 12198 | if (breg != 0) |
| 12199 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12200 | tempreg, tempreg, breg); |
| 12201 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
| 12202 | } |
| 12203 | else if (mips_big_got && !HAVE_NEWABI) |
| 12204 | { |
| 12205 | int gpdelay; |
| 12206 | |
| 12207 | /* If this is a reference to an external symbol, we want |
| 12208 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 12209 | addu $tempreg,$tempreg,$gp |
| 12210 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 12211 | <op> op[0],0($tempreg) |
| 12212 | Otherwise we want |
| 12213 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 12214 | nop |
| 12215 | addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16) |
| 12216 | <op> op[0],0($tempreg) |
| 12217 | If there is a base register, we add it to $tempreg before |
| 12218 | the <op>. If there is a constant, we stick it in the |
| 12219 | <op> instruction. We don't handle constants larger than |
| 12220 | 16 bits, because we have no way to load the upper 16 bits |
| 12221 | (actually, we could handle them for the subset of cases |
| 12222 | in which we are not using $at). */ |
| 12223 | gas_assert (offset_expr.X_op == O_symbol); |
| 12224 | expr1.X_add_number = offset_expr.X_add_number; |
| 12225 | offset_expr.X_add_number = 0; |
| 12226 | if (expr1.X_add_number < -0x8000 |
| 12227 | || expr1.X_add_number >= 0x8000) |
| 12228 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 12229 | gpdelay = reg_needs_delay (mips_gp_register); |
| 12230 | relax_start (offset_expr.X_add_symbol); |
| 12231 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
| 12232 | BFD_RELOC_MIPS_GOT_HI16); |
| 12233 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
| 12234 | mips_gp_register); |
| 12235 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 12236 | BFD_RELOC_MIPS_GOT_LO16, tempreg); |
| 12237 | relax_switch (); |
| 12238 | if (gpdelay) |
| 12239 | macro_build (NULL, "nop", ""); |
| 12240 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 12241 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 12242 | load_delay_nop (); |
| 12243 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg, |
| 12244 | tempreg, BFD_RELOC_LO16); |
| 12245 | relax_end (); |
| 12246 | |
| 12247 | if (breg != 0) |
| 12248 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12249 | tempreg, tempreg, breg); |
| 12250 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
| 12251 | } |
| 12252 | else if (mips_big_got && HAVE_NEWABI) |
| 12253 | { |
| 12254 | /* If this is a reference to an external symbol, we want |
| 12255 | lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 12256 | add $tempreg,$tempreg,$gp |
| 12257 | lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16) |
| 12258 | <op> op[0],<ofst>($tempreg) |
| 12259 | Otherwise, for local symbols, we want: |
| 12260 | lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE) |
| 12261 | <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */ |
| 12262 | gas_assert (offset_expr.X_op == O_symbol); |
| 12263 | expr1.X_add_number = offset_expr.X_add_number; |
| 12264 | offset_expr.X_add_number = 0; |
| 12265 | if (expr1.X_add_number < -0x8000 |
| 12266 | || expr1.X_add_number >= 0x8000) |
| 12267 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 12268 | relax_start (offset_expr.X_add_symbol); |
| 12269 | macro_build (&offset_expr, "lui", LUI_FMT, tempreg, |
| 12270 | BFD_RELOC_MIPS_GOT_HI16); |
| 12271 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, |
| 12272 | mips_gp_register); |
| 12273 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 12274 | BFD_RELOC_MIPS_GOT_LO16, tempreg); |
| 12275 | if (breg != 0) |
| 12276 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12277 | tempreg, tempreg, breg); |
| 12278 | macro_build (&expr1, s, fmt, op[0], BFD_RELOC_LO16, tempreg); |
| 12279 | |
| 12280 | relax_switch (); |
| 12281 | offset_expr.X_add_number = expr1.X_add_number; |
| 12282 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg, |
| 12283 | BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register); |
| 12284 | if (breg != 0) |
| 12285 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12286 | tempreg, tempreg, breg); |
| 12287 | macro_build (&offset_expr, s, fmt, op[0], |
| 12288 | BFD_RELOC_MIPS_GOT_OFST, tempreg); |
| 12289 | relax_end (); |
| 12290 | } |
| 12291 | else |
| 12292 | abort (); |
| 12293 | |
| 12294 | break; |
| 12295 | |
| 12296 | case M_JRADDIUSP: |
| 12297 | gas_assert (mips_opts.micromips); |
| 12298 | gas_assert (mips_opts.insn32); |
| 12299 | start_noreorder (); |
| 12300 | macro_build (NULL, "jr", "s", RA); |
| 12301 | expr1.X_add_number = op[0] << 2; |
| 12302 | macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16); |
| 12303 | end_noreorder (); |
| 12304 | break; |
| 12305 | |
| 12306 | case M_JRC: |
| 12307 | gas_assert (mips_opts.micromips); |
| 12308 | gas_assert (mips_opts.insn32); |
| 12309 | macro_build (NULL, "jr", "s", op[0]); |
| 12310 | if (mips_opts.noreorder) |
| 12311 | macro_build (NULL, "nop", ""); |
| 12312 | break; |
| 12313 | |
| 12314 | case M_LI: |
| 12315 | case M_LI_S: |
| 12316 | load_register (op[0], &imm_expr, 0); |
| 12317 | break; |
| 12318 | |
| 12319 | case M_DLI: |
| 12320 | load_register (op[0], &imm_expr, 1); |
| 12321 | break; |
| 12322 | |
| 12323 | case M_LI_SS: |
| 12324 | if (imm_expr.X_op == O_constant) |
| 12325 | { |
| 12326 | used_at = 1; |
| 12327 | load_register (AT, &imm_expr, 0); |
| 12328 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
| 12329 | break; |
| 12330 | } |
| 12331 | else |
| 12332 | { |
| 12333 | gas_assert (imm_expr.X_op == O_absent |
| 12334 | && offset_expr.X_op == O_symbol |
| 12335 | && strcmp (segment_name (S_GET_SEGMENT |
| 12336 | (offset_expr.X_add_symbol)), |
| 12337 | ".lit4") == 0 |
| 12338 | && offset_expr.X_add_number == 0); |
| 12339 | macro_build (&offset_expr, "lwc1", "T,o(b)", op[0], |
| 12340 | BFD_RELOC_MIPS_LITERAL, mips_gp_register); |
| 12341 | break; |
| 12342 | } |
| 12343 | |
| 12344 | case M_LI_D: |
| 12345 | /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits |
| 12346 | wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high |
| 12347 | order 32 bits of the value and the low order 32 bits are either |
| 12348 | zero or in OFFSET_EXPR. */ |
| 12349 | if (imm_expr.X_op == O_constant) |
| 12350 | { |
| 12351 | if (GPR_SIZE == 64) |
| 12352 | load_register (op[0], &imm_expr, 1); |
| 12353 | else |
| 12354 | { |
| 12355 | int hreg, lreg; |
| 12356 | |
| 12357 | if (target_big_endian) |
| 12358 | { |
| 12359 | hreg = op[0]; |
| 12360 | lreg = op[0] + 1; |
| 12361 | } |
| 12362 | else |
| 12363 | { |
| 12364 | hreg = op[0] + 1; |
| 12365 | lreg = op[0]; |
| 12366 | } |
| 12367 | |
| 12368 | if (hreg <= 31) |
| 12369 | load_register (hreg, &imm_expr, 0); |
| 12370 | if (lreg <= 31) |
| 12371 | { |
| 12372 | if (offset_expr.X_op == O_absent) |
| 12373 | move_register (lreg, 0); |
| 12374 | else |
| 12375 | { |
| 12376 | gas_assert (offset_expr.X_op == O_constant); |
| 12377 | load_register (lreg, &offset_expr, 0); |
| 12378 | } |
| 12379 | } |
| 12380 | } |
| 12381 | break; |
| 12382 | } |
| 12383 | gas_assert (imm_expr.X_op == O_absent); |
| 12384 | |
| 12385 | /* We know that sym is in the .rdata section. First we get the |
| 12386 | upper 16 bits of the address. */ |
| 12387 | if (mips_pic == NO_PIC) |
| 12388 | { |
| 12389 | macro_build_lui (&offset_expr, AT); |
| 12390 | used_at = 1; |
| 12391 | } |
| 12392 | else |
| 12393 | { |
| 12394 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
| 12395 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 12396 | used_at = 1; |
| 12397 | } |
| 12398 | |
| 12399 | /* Now we load the register(s). */ |
| 12400 | if (GPR_SIZE == 64) |
| 12401 | { |
| 12402 | used_at = 1; |
| 12403 | macro_build (&offset_expr, "ld", "t,o(b)", op[0], |
| 12404 | BFD_RELOC_LO16, AT); |
| 12405 | } |
| 12406 | else |
| 12407 | { |
| 12408 | used_at = 1; |
| 12409 | macro_build (&offset_expr, "lw", "t,o(b)", op[0], |
| 12410 | BFD_RELOC_LO16, AT); |
| 12411 | if (op[0] != RA) |
| 12412 | { |
| 12413 | /* FIXME: How in the world do we deal with the possible |
| 12414 | overflow here? */ |
| 12415 | offset_expr.X_add_number += 4; |
| 12416 | macro_build (&offset_expr, "lw", "t,o(b)", |
| 12417 | op[0] + 1, BFD_RELOC_LO16, AT); |
| 12418 | } |
| 12419 | } |
| 12420 | break; |
| 12421 | |
| 12422 | case M_LI_DD: |
| 12423 | /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits |
| 12424 | wide, IMM_EXPR is the entire value and the GPRs are known to be 64 |
| 12425 | bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of |
| 12426 | the value and the low order 32 bits are either zero or in |
| 12427 | OFFSET_EXPR. */ |
| 12428 | if (imm_expr.X_op == O_constant) |
| 12429 | { |
| 12430 | used_at = 1; |
| 12431 | load_register (AT, &imm_expr, FPR_SIZE == 64); |
| 12432 | if (FPR_SIZE == 64 && GPR_SIZE == 64) |
| 12433 | macro_build (NULL, "dmtc1", "t,S", AT, op[0]); |
| 12434 | else |
| 12435 | { |
| 12436 | if (ISA_HAS_MXHC1 (mips_opts.isa)) |
| 12437 | macro_build (NULL, "mthc1", "t,G", AT, op[0]); |
| 12438 | else if (FPR_SIZE != 32) |
| 12439 | as_bad (_("Unable to generate `%s' compliant code " |
| 12440 | "without mthc1"), |
| 12441 | (FPR_SIZE == 64) ? "fp64" : "fpxx"); |
| 12442 | else |
| 12443 | macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); |
| 12444 | if (offset_expr.X_op == O_absent) |
| 12445 | macro_build (NULL, "mtc1", "t,G", 0, op[0]); |
| 12446 | else |
| 12447 | { |
| 12448 | gas_assert (offset_expr.X_op == O_constant); |
| 12449 | load_register (AT, &offset_expr, 0); |
| 12450 | macro_build (NULL, "mtc1", "t,G", AT, op[0]); |
| 12451 | } |
| 12452 | } |
| 12453 | break; |
| 12454 | } |
| 12455 | |
| 12456 | gas_assert (imm_expr.X_op == O_absent |
| 12457 | && offset_expr.X_op == O_symbol |
| 12458 | && offset_expr.X_add_number == 0); |
| 12459 | s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); |
| 12460 | if (strcmp (s, ".lit8") == 0) |
| 12461 | { |
| 12462 | op[2] = mips_gp_register; |
| 12463 | offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; |
| 12464 | offset_reloc[1] = BFD_RELOC_UNUSED; |
| 12465 | offset_reloc[2] = BFD_RELOC_UNUSED; |
| 12466 | } |
| 12467 | else |
| 12468 | { |
| 12469 | gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0); |
| 12470 | used_at = 1; |
| 12471 | if (mips_pic != NO_PIC) |
| 12472 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
| 12473 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 12474 | else |
| 12475 | { |
| 12476 | /* FIXME: This won't work for a 64 bit address. */ |
| 12477 | macro_build_lui (&offset_expr, AT); |
| 12478 | } |
| 12479 | |
| 12480 | op[2] = AT; |
| 12481 | offset_reloc[0] = BFD_RELOC_LO16; |
| 12482 | offset_reloc[1] = BFD_RELOC_UNUSED; |
| 12483 | offset_reloc[2] = BFD_RELOC_UNUSED; |
| 12484 | } |
| 12485 | align = 8; |
| 12486 | /* Fall through */ |
| 12487 | |
| 12488 | case M_L_DAB: |
| 12489 | /* |
| 12490 | * The MIPS assembler seems to check for X_add_number not |
| 12491 | * being double aligned and generating: |
| 12492 | * lui at,%hi(foo+1) |
| 12493 | * addu at,at,v1 |
| 12494 | * addiu at,at,%lo(foo+1) |
| 12495 | * lwc1 f2,0(at) |
| 12496 | * lwc1 f3,4(at) |
| 12497 | * But, the resulting address is the same after relocation so why |
| 12498 | * generate the extra instruction? |
| 12499 | */ |
| 12500 | /* Itbl support may require additional care here. */ |
| 12501 | coproc = 1; |
| 12502 | fmt = "T,o(b)"; |
| 12503 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
| 12504 | { |
| 12505 | s = "ldc1"; |
| 12506 | goto ld_st; |
| 12507 | } |
| 12508 | s = "lwc1"; |
| 12509 | goto ldd_std; |
| 12510 | |
| 12511 | case M_S_DAB: |
| 12512 | gas_assert (!mips_opts.micromips); |
| 12513 | /* Itbl support may require additional care here. */ |
| 12514 | coproc = 1; |
| 12515 | fmt = "T,o(b)"; |
| 12516 | if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) |
| 12517 | { |
| 12518 | s = "sdc1"; |
| 12519 | goto ld_st; |
| 12520 | } |
| 12521 | s = "swc1"; |
| 12522 | goto ldd_std; |
| 12523 | |
| 12524 | case M_LQ_AB: |
| 12525 | fmt = "t,o(b)"; |
| 12526 | s = "lq"; |
| 12527 | goto ld; |
| 12528 | |
| 12529 | case M_SQ_AB: |
| 12530 | fmt = "t,o(b)"; |
| 12531 | s = "sq"; |
| 12532 | goto ld_st; |
| 12533 | |
| 12534 | case M_LD_AB: |
| 12535 | fmt = "t,o(b)"; |
| 12536 | if (GPR_SIZE == 64) |
| 12537 | { |
| 12538 | s = "ld"; |
| 12539 | goto ld; |
| 12540 | } |
| 12541 | s = "lw"; |
| 12542 | goto ldd_std; |
| 12543 | |
| 12544 | case M_SD_AB: |
| 12545 | fmt = "t,o(b)"; |
| 12546 | if (GPR_SIZE == 64) |
| 12547 | { |
| 12548 | s = "sd"; |
| 12549 | goto ld_st; |
| 12550 | } |
| 12551 | s = "sw"; |
| 12552 | |
| 12553 | ldd_std: |
| 12554 | /* Even on a big endian machine $fn comes before $fn+1. We have |
| 12555 | to adjust when loading from memory. We set coproc if we must |
| 12556 | load $fn+1 first. */ |
| 12557 | /* Itbl support may require additional care here. */ |
| 12558 | if (!target_big_endian) |
| 12559 | coproc = 0; |
| 12560 | |
| 12561 | breg = op[2]; |
| 12562 | if (small_offset_p (0, align, 16)) |
| 12563 | { |
| 12564 | ep = &offset_expr; |
| 12565 | if (!small_offset_p (4, align, 16)) |
| 12566 | { |
| 12567 | macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT, breg, |
| 12568 | -1, offset_reloc[0], offset_reloc[1], |
| 12569 | offset_reloc[2]); |
| 12570 | expr1.X_add_number = 0; |
| 12571 | ep = &expr1; |
| 12572 | breg = AT; |
| 12573 | used_at = 1; |
| 12574 | offset_reloc[0] = BFD_RELOC_LO16; |
| 12575 | offset_reloc[1] = BFD_RELOC_UNUSED; |
| 12576 | offset_reloc[2] = BFD_RELOC_UNUSED; |
| 12577 | } |
| 12578 | if (strcmp (s, "lw") == 0 && op[0] == breg) |
| 12579 | { |
| 12580 | ep->X_add_number += 4; |
| 12581 | macro_build (ep, s, fmt, op[0] + 1, -1, offset_reloc[0], |
| 12582 | offset_reloc[1], offset_reloc[2], breg); |
| 12583 | ep->X_add_number -= 4; |
| 12584 | macro_build (ep, s, fmt, op[0], -1, offset_reloc[0], |
| 12585 | offset_reloc[1], offset_reloc[2], breg); |
| 12586 | } |
| 12587 | else |
| 12588 | { |
| 12589 | macro_build (ep, s, fmt, coproc ? op[0] + 1 : op[0], -1, |
| 12590 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
| 12591 | breg); |
| 12592 | ep->X_add_number += 4; |
| 12593 | macro_build (ep, s, fmt, coproc ? op[0] : op[0] + 1, -1, |
| 12594 | offset_reloc[0], offset_reloc[1], offset_reloc[2], |
| 12595 | breg); |
| 12596 | } |
| 12597 | break; |
| 12598 | } |
| 12599 | |
| 12600 | if (offset_expr.X_op != O_symbol |
| 12601 | && offset_expr.X_op != O_constant) |
| 12602 | { |
| 12603 | as_bad (_("expression too complex")); |
| 12604 | offset_expr.X_op = O_constant; |
| 12605 | } |
| 12606 | |
| 12607 | if (HAVE_32BIT_ADDRESSES |
| 12608 | && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number)) |
| 12609 | { |
| 12610 | char value [32]; |
| 12611 | |
| 12612 | sprintf_vma (value, offset_expr.X_add_number); |
| 12613 | as_bad (_("number (0x%s) larger than 32 bits"), value); |
| 12614 | } |
| 12615 | |
| 12616 | if (mips_pic == NO_PIC || offset_expr.X_op == O_constant) |
| 12617 | { |
| 12618 | /* If this is a reference to a GP relative symbol, we want |
| 12619 | <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16) |
| 12620 | <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16) |
| 12621 | If we have a base register, we use this |
| 12622 | addu $at,$breg,$gp |
| 12623 | <op> op[0],<sym>($at) (BFD_RELOC_GPREL16) |
| 12624 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16) |
| 12625 | If this is not a GP relative symbol, we want |
| 12626 | lui $at,<sym> (BFD_RELOC_HI16_S) |
| 12627 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
| 12628 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) |
| 12629 | If there is a base register, we add it to $at after the |
| 12630 | lui instruction. If there is a constant, we always use |
| 12631 | the last case. */ |
| 12632 | if (offset_expr.X_op == O_symbol |
| 12633 | && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET |
| 12634 | && !nopic_need_relax (offset_expr.X_add_symbol, 1)) |
| 12635 | { |
| 12636 | relax_start (offset_expr.X_add_symbol); |
| 12637 | if (breg == 0) |
| 12638 | { |
| 12639 | tempreg = mips_gp_register; |
| 12640 | } |
| 12641 | else |
| 12642 | { |
| 12643 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12644 | AT, breg, mips_gp_register); |
| 12645 | tempreg = AT; |
| 12646 | used_at = 1; |
| 12647 | } |
| 12648 | |
| 12649 | /* Itbl support may require additional care here. */ |
| 12650 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
| 12651 | BFD_RELOC_GPREL16, tempreg); |
| 12652 | offset_expr.X_add_number += 4; |
| 12653 | |
| 12654 | /* Set mips_optimize to 2 to avoid inserting an |
| 12655 | undesired nop. */ |
| 12656 | hold_mips_optimize = mips_optimize; |
| 12657 | mips_optimize = 2; |
| 12658 | /* Itbl support may require additional care here. */ |
| 12659 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
| 12660 | BFD_RELOC_GPREL16, tempreg); |
| 12661 | mips_optimize = hold_mips_optimize; |
| 12662 | |
| 12663 | relax_switch (); |
| 12664 | |
| 12665 | offset_expr.X_add_number -= 4; |
| 12666 | } |
| 12667 | used_at = 1; |
| 12668 | if (offset_high_part (offset_expr.X_add_number, 16) |
| 12669 | != offset_high_part (offset_expr.X_add_number + 4, 16)) |
| 12670 | { |
| 12671 | load_address (AT, &offset_expr, &used_at); |
| 12672 | offset_expr.X_op = O_constant; |
| 12673 | offset_expr.X_add_number = 0; |
| 12674 | } |
| 12675 | else |
| 12676 | macro_build_lui (&offset_expr, AT); |
| 12677 | if (breg != 0) |
| 12678 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
| 12679 | /* Itbl support may require additional care here. */ |
| 12680 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
| 12681 | BFD_RELOC_LO16, AT); |
| 12682 | /* FIXME: How do we handle overflow here? */ |
| 12683 | offset_expr.X_add_number += 4; |
| 12684 | /* Itbl support may require additional care here. */ |
| 12685 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
| 12686 | BFD_RELOC_LO16, AT); |
| 12687 | if (mips_relax.sequence) |
| 12688 | relax_end (); |
| 12689 | } |
| 12690 | else if (!mips_big_got) |
| 12691 | { |
| 12692 | /* If this is a reference to an external symbol, we want |
| 12693 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 12694 | nop |
| 12695 | <op> op[0],0($at) |
| 12696 | <op> op[0]+1,4($at) |
| 12697 | Otherwise we want |
| 12698 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 12699 | nop |
| 12700 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
| 12701 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) |
| 12702 | If there is a base register we add it to $at before the |
| 12703 | lwc1 instructions. If there is a constant we include it |
| 12704 | in the lwc1 instructions. */ |
| 12705 | used_at = 1; |
| 12706 | expr1.X_add_number = offset_expr.X_add_number; |
| 12707 | if (expr1.X_add_number < -0x8000 |
| 12708 | || expr1.X_add_number >= 0x8000 - 4) |
| 12709 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 12710 | load_got_offset (AT, &offset_expr); |
| 12711 | load_delay_nop (); |
| 12712 | if (breg != 0) |
| 12713 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
| 12714 | |
| 12715 | /* Set mips_optimize to 2 to avoid inserting an undesired |
| 12716 | nop. */ |
| 12717 | hold_mips_optimize = mips_optimize; |
| 12718 | mips_optimize = 2; |
| 12719 | |
| 12720 | /* Itbl support may require additional care here. */ |
| 12721 | relax_start (offset_expr.X_add_symbol); |
| 12722 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
| 12723 | BFD_RELOC_LO16, AT); |
| 12724 | expr1.X_add_number += 4; |
| 12725 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
| 12726 | BFD_RELOC_LO16, AT); |
| 12727 | relax_switch (); |
| 12728 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
| 12729 | BFD_RELOC_LO16, AT); |
| 12730 | offset_expr.X_add_number += 4; |
| 12731 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
| 12732 | BFD_RELOC_LO16, AT); |
| 12733 | relax_end (); |
| 12734 | |
| 12735 | mips_optimize = hold_mips_optimize; |
| 12736 | } |
| 12737 | else if (mips_big_got) |
| 12738 | { |
| 12739 | int gpdelay; |
| 12740 | |
| 12741 | /* If this is a reference to an external symbol, we want |
| 12742 | lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16) |
| 12743 | addu $at,$at,$gp |
| 12744 | lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16) |
| 12745 | nop |
| 12746 | <op> op[0],0($at) |
| 12747 | <op> op[0]+1,4($at) |
| 12748 | Otherwise we want |
| 12749 | lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16) |
| 12750 | nop |
| 12751 | <op> op[0],<sym>($at) (BFD_RELOC_LO16) |
| 12752 | <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16) |
| 12753 | If there is a base register we add it to $at before the |
| 12754 | lwc1 instructions. If there is a constant we include it |
| 12755 | in the lwc1 instructions. */ |
| 12756 | used_at = 1; |
| 12757 | expr1.X_add_number = offset_expr.X_add_number; |
| 12758 | offset_expr.X_add_number = 0; |
| 12759 | if (expr1.X_add_number < -0x8000 |
| 12760 | || expr1.X_add_number >= 0x8000 - 4) |
| 12761 | as_bad (_("PIC code offset overflow (max 16 signed bits)")); |
| 12762 | gpdelay = reg_needs_delay (mips_gp_register); |
| 12763 | relax_start (offset_expr.X_add_symbol); |
| 12764 | macro_build (&offset_expr, "lui", LUI_FMT, |
| 12765 | AT, BFD_RELOC_MIPS_GOT_HI16); |
| 12766 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 12767 | AT, AT, mips_gp_register); |
| 12768 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", |
| 12769 | AT, BFD_RELOC_MIPS_GOT_LO16, AT); |
| 12770 | load_delay_nop (); |
| 12771 | if (breg != 0) |
| 12772 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
| 12773 | /* Itbl support may require additional care here. */ |
| 12774 | macro_build (&expr1, s, fmt, coproc ? op[0] + 1 : op[0], |
| 12775 | BFD_RELOC_LO16, AT); |
| 12776 | expr1.X_add_number += 4; |
| 12777 | |
| 12778 | /* Set mips_optimize to 2 to avoid inserting an undesired |
| 12779 | nop. */ |
| 12780 | hold_mips_optimize = mips_optimize; |
| 12781 | mips_optimize = 2; |
| 12782 | /* Itbl support may require additional care here. */ |
| 12783 | macro_build (&expr1, s, fmt, coproc ? op[0] : op[0] + 1, |
| 12784 | BFD_RELOC_LO16, AT); |
| 12785 | mips_optimize = hold_mips_optimize; |
| 12786 | expr1.X_add_number -= 4; |
| 12787 | |
| 12788 | relax_switch (); |
| 12789 | offset_expr.X_add_number = expr1.X_add_number; |
| 12790 | if (gpdelay) |
| 12791 | macro_build (NULL, "nop", ""); |
| 12792 | macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT, |
| 12793 | BFD_RELOC_MIPS_GOT16, mips_gp_register); |
| 12794 | load_delay_nop (); |
| 12795 | if (breg != 0) |
| 12796 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); |
| 12797 | /* Itbl support may require additional care here. */ |
| 12798 | macro_build (&offset_expr, s, fmt, coproc ? op[0] + 1 : op[0], |
| 12799 | BFD_RELOC_LO16, AT); |
| 12800 | offset_expr.X_add_number += 4; |
| 12801 | |
| 12802 | /* Set mips_optimize to 2 to avoid inserting an undesired |
| 12803 | nop. */ |
| 12804 | hold_mips_optimize = mips_optimize; |
| 12805 | mips_optimize = 2; |
| 12806 | /* Itbl support may require additional care here. */ |
| 12807 | macro_build (&offset_expr, s, fmt, coproc ? op[0] : op[0] + 1, |
| 12808 | BFD_RELOC_LO16, AT); |
| 12809 | mips_optimize = hold_mips_optimize; |
| 12810 | relax_end (); |
| 12811 | } |
| 12812 | else |
| 12813 | abort (); |
| 12814 | |
| 12815 | break; |
| 12816 | |
| 12817 | case M_SAA_AB: |
| 12818 | s = "saa"; |
| 12819 | goto saa_saad; |
| 12820 | case M_SAAD_AB: |
| 12821 | s = "saad"; |
| 12822 | saa_saad: |
| 12823 | gas_assert (!mips_opts.micromips); |
| 12824 | offbits = 0; |
| 12825 | fmt = "t,(b)"; |
| 12826 | goto ld_st; |
| 12827 | |
| 12828 | /* New code added to support COPZ instructions. |
| 12829 | This code builds table entries out of the macros in mip_opcodes. |
| 12830 | R4000 uses interlocks to handle coproc delays. |
| 12831 | Other chips (like the R3000) require nops to be inserted for delays. |
| 12832 | |
| 12833 | FIXME: Currently, we require that the user handle delays. |
| 12834 | In order to fill delay slots for non-interlocked chips, |
| 12835 | we must have a way to specify delays based on the coprocessor. |
| 12836 | Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc. |
| 12837 | What are the side-effects of the cop instruction? |
| 12838 | What cache support might we have and what are its effects? |
| 12839 | Both coprocessor & memory require delays. how long??? |
| 12840 | What registers are read/set/modified? |
| 12841 | |
| 12842 | If an itbl is provided to interpret cop instructions, |
| 12843 | this knowledge can be encoded in the itbl spec. */ |
| 12844 | |
| 12845 | case M_COP0: |
| 12846 | s = "c0"; |
| 12847 | goto copz; |
| 12848 | case M_COP1: |
| 12849 | s = "c1"; |
| 12850 | goto copz; |
| 12851 | case M_COP2: |
| 12852 | s = "c2"; |
| 12853 | goto copz; |
| 12854 | case M_COP3: |
| 12855 | s = "c3"; |
| 12856 | copz: |
| 12857 | gas_assert (!mips_opts.micromips); |
| 12858 | /* For now we just do C (same as Cz). The parameter will be |
| 12859 | stored in insn_opcode by mips_ip. */ |
| 12860 | macro_build (NULL, s, "C", (int) ip->insn_opcode); |
| 12861 | break; |
| 12862 | |
| 12863 | case M_MOVE: |
| 12864 | move_register (op[0], op[1]); |
| 12865 | break; |
| 12866 | |
| 12867 | case M_MOVEP: |
| 12868 | gas_assert (mips_opts.micromips); |
| 12869 | gas_assert (mips_opts.insn32); |
| 12870 | move_register (micromips_to_32_reg_h_map1[op[0]], |
| 12871 | micromips_to_32_reg_m_map[op[1]]); |
| 12872 | move_register (micromips_to_32_reg_h_map2[op[0]], |
| 12873 | micromips_to_32_reg_n_map[op[2]]); |
| 12874 | break; |
| 12875 | |
| 12876 | case M_DMUL: |
| 12877 | dbl = 1; |
| 12878 | /* Fall through. */ |
| 12879 | case M_MUL: |
| 12880 | if (mips_opts.arch == CPU_R5900) |
| 12881 | macro_build (NULL, dbl ? "dmultu" : "multu", "d,s,t", op[0], op[1], |
| 12882 | op[2]); |
| 12883 | else |
| 12884 | { |
| 12885 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", op[1], op[2]); |
| 12886 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
| 12887 | } |
| 12888 | break; |
| 12889 | |
| 12890 | case M_DMUL_I: |
| 12891 | dbl = 1; |
| 12892 | /* Fall through. */ |
| 12893 | case M_MUL_I: |
| 12894 | /* The MIPS assembler some times generates shifts and adds. I'm |
| 12895 | not trying to be that fancy. GCC should do this for us |
| 12896 | anyway. */ |
| 12897 | used_at = 1; |
| 12898 | load_register (AT, &imm_expr, dbl); |
| 12899 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", op[1], AT); |
| 12900 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
| 12901 | break; |
| 12902 | |
| 12903 | case M_DMULO_I: |
| 12904 | dbl = 1; |
| 12905 | /* Fall through. */ |
| 12906 | case M_MULO_I: |
| 12907 | imm = 1; |
| 12908 | goto do_mulo; |
| 12909 | |
| 12910 | case M_DMULO: |
| 12911 | dbl = 1; |
| 12912 | /* Fall through. */ |
| 12913 | case M_MULO: |
| 12914 | do_mulo: |
| 12915 | start_noreorder (); |
| 12916 | used_at = 1; |
| 12917 | if (imm) |
| 12918 | load_register (AT, &imm_expr, dbl); |
| 12919 | macro_build (NULL, dbl ? "dmult" : "mult", "s,t", |
| 12920 | op[1], imm ? AT : op[2]); |
| 12921 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
| 12922 | macro_build (NULL, dbl ? "dsra32" : "sra", SHFT_FMT, op[0], op[0], 31); |
| 12923 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
| 12924 | if (mips_trap) |
| 12925 | macro_build (NULL, "tne", TRAP_FMT, op[0], AT, 6); |
| 12926 | else |
| 12927 | { |
| 12928 | if (mips_opts.micromips) |
| 12929 | micromips_label_expr (&label_expr); |
| 12930 | else |
| 12931 | label_expr.X_add_number = 8; |
| 12932 | macro_build (&label_expr, "beq", "s,t,p", op[0], AT); |
| 12933 | macro_build (NULL, "nop", ""); |
| 12934 | macro_build (NULL, "break", BRK_FMT, 6); |
| 12935 | if (mips_opts.micromips) |
| 12936 | micromips_add_label (); |
| 12937 | } |
| 12938 | end_noreorder (); |
| 12939 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
| 12940 | break; |
| 12941 | |
| 12942 | case M_DMULOU_I: |
| 12943 | dbl = 1; |
| 12944 | /* Fall through. */ |
| 12945 | case M_MULOU_I: |
| 12946 | imm = 1; |
| 12947 | goto do_mulou; |
| 12948 | |
| 12949 | case M_DMULOU: |
| 12950 | dbl = 1; |
| 12951 | /* Fall through. */ |
| 12952 | case M_MULOU: |
| 12953 | do_mulou: |
| 12954 | start_noreorder (); |
| 12955 | used_at = 1; |
| 12956 | if (imm) |
| 12957 | load_register (AT, &imm_expr, dbl); |
| 12958 | macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", |
| 12959 | op[1], imm ? AT : op[2]); |
| 12960 | macro_build (NULL, "mfhi", MFHL_FMT, AT); |
| 12961 | macro_build (NULL, "mflo", MFHL_FMT, op[0]); |
| 12962 | if (mips_trap) |
| 12963 | macro_build (NULL, "tne", TRAP_FMT, AT, ZERO, 6); |
| 12964 | else |
| 12965 | { |
| 12966 | if (mips_opts.micromips) |
| 12967 | micromips_label_expr (&label_expr); |
| 12968 | else |
| 12969 | label_expr.X_add_number = 8; |
| 12970 | macro_build (&label_expr, "beq", "s,t,p", AT, ZERO); |
| 12971 | macro_build (NULL, "nop", ""); |
| 12972 | macro_build (NULL, "break", BRK_FMT, 6); |
| 12973 | if (mips_opts.micromips) |
| 12974 | micromips_add_label (); |
| 12975 | } |
| 12976 | end_noreorder (); |
| 12977 | break; |
| 12978 | |
| 12979 | case M_DROL: |
| 12980 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
| 12981 | { |
| 12982 | if (op[0] == op[1]) |
| 12983 | { |
| 12984 | tempreg = AT; |
| 12985 | used_at = 1; |
| 12986 | } |
| 12987 | else |
| 12988 | tempreg = op[0]; |
| 12989 | macro_build (NULL, "dnegu", "d,w", tempreg, op[2]); |
| 12990 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], tempreg); |
| 12991 | break; |
| 12992 | } |
| 12993 | used_at = 1; |
| 12994 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
| 12995 | macro_build (NULL, "dsrlv", "d,t,s", AT, op[1], AT); |
| 12996 | macro_build (NULL, "dsllv", "d,t,s", op[0], op[1], op[2]); |
| 12997 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
| 12998 | break; |
| 12999 | |
| 13000 | case M_ROL: |
| 13001 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
| 13002 | { |
| 13003 | if (op[0] == op[1]) |
| 13004 | { |
| 13005 | tempreg = AT; |
| 13006 | used_at = 1; |
| 13007 | } |
| 13008 | else |
| 13009 | tempreg = op[0]; |
| 13010 | macro_build (NULL, "negu", "d,w", tempreg, op[2]); |
| 13011 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], tempreg); |
| 13012 | break; |
| 13013 | } |
| 13014 | used_at = 1; |
| 13015 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
| 13016 | macro_build (NULL, "srlv", "d,t,s", AT, op[1], AT); |
| 13017 | macro_build (NULL, "sllv", "d,t,s", op[0], op[1], op[2]); |
| 13018 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
| 13019 | break; |
| 13020 | |
| 13021 | case M_DROL_I: |
| 13022 | { |
| 13023 | unsigned int rot; |
| 13024 | const char *l; |
| 13025 | const char *rr; |
| 13026 | |
| 13027 | rot = imm_expr.X_add_number & 0x3f; |
| 13028 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
| 13029 | { |
| 13030 | rot = (64 - rot) & 0x3f; |
| 13031 | if (rot >= 32) |
| 13032 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
| 13033 | else |
| 13034 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
| 13035 | break; |
| 13036 | } |
| 13037 | if (rot == 0) |
| 13038 | { |
| 13039 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
| 13040 | break; |
| 13041 | } |
| 13042 | l = (rot < 0x20) ? "dsll" : "dsll32"; |
| 13043 | rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; |
| 13044 | rot &= 0x1f; |
| 13045 | used_at = 1; |
| 13046 | macro_build (NULL, l, SHFT_FMT, AT, op[1], rot); |
| 13047 | macro_build (NULL, rr, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); |
| 13048 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
| 13049 | } |
| 13050 | break; |
| 13051 | |
| 13052 | case M_ROL_I: |
| 13053 | { |
| 13054 | unsigned int rot; |
| 13055 | |
| 13056 | rot = imm_expr.X_add_number & 0x1f; |
| 13057 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
| 13058 | { |
| 13059 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], |
| 13060 | (32 - rot) & 0x1f); |
| 13061 | break; |
| 13062 | } |
| 13063 | if (rot == 0) |
| 13064 | { |
| 13065 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
| 13066 | break; |
| 13067 | } |
| 13068 | used_at = 1; |
| 13069 | macro_build (NULL, "sll", SHFT_FMT, AT, op[1], rot); |
| 13070 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); |
| 13071 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
| 13072 | } |
| 13073 | break; |
| 13074 | |
| 13075 | case M_DROR: |
| 13076 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
| 13077 | { |
| 13078 | macro_build (NULL, "drorv", "d,t,s", op[0], op[1], op[2]); |
| 13079 | break; |
| 13080 | } |
| 13081 | used_at = 1; |
| 13082 | macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, op[2]); |
| 13083 | macro_build (NULL, "dsllv", "d,t,s", AT, op[1], AT); |
| 13084 | macro_build (NULL, "dsrlv", "d,t,s", op[0], op[1], op[2]); |
| 13085 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
| 13086 | break; |
| 13087 | |
| 13088 | case M_ROR: |
| 13089 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
| 13090 | { |
| 13091 | macro_build (NULL, "rorv", "d,t,s", op[0], op[1], op[2]); |
| 13092 | break; |
| 13093 | } |
| 13094 | used_at = 1; |
| 13095 | macro_build (NULL, "subu", "d,v,t", AT, ZERO, op[2]); |
| 13096 | macro_build (NULL, "sllv", "d,t,s", AT, op[1], AT); |
| 13097 | macro_build (NULL, "srlv", "d,t,s", op[0], op[1], op[2]); |
| 13098 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
| 13099 | break; |
| 13100 | |
| 13101 | case M_DROR_I: |
| 13102 | { |
| 13103 | unsigned int rot; |
| 13104 | const char *l; |
| 13105 | const char *rr; |
| 13106 | |
| 13107 | rot = imm_expr.X_add_number & 0x3f; |
| 13108 | if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch)) |
| 13109 | { |
| 13110 | if (rot >= 32) |
| 13111 | macro_build (NULL, "dror32", SHFT_FMT, op[0], op[1], rot - 32); |
| 13112 | else |
| 13113 | macro_build (NULL, "dror", SHFT_FMT, op[0], op[1], rot); |
| 13114 | break; |
| 13115 | } |
| 13116 | if (rot == 0) |
| 13117 | { |
| 13118 | macro_build (NULL, "dsrl", SHFT_FMT, op[0], op[1], 0); |
| 13119 | break; |
| 13120 | } |
| 13121 | rr = (rot < 0x20) ? "dsrl" : "dsrl32"; |
| 13122 | l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; |
| 13123 | rot &= 0x1f; |
| 13124 | used_at = 1; |
| 13125 | macro_build (NULL, rr, SHFT_FMT, AT, op[1], rot); |
| 13126 | macro_build (NULL, l, SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); |
| 13127 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
| 13128 | } |
| 13129 | break; |
| 13130 | |
| 13131 | case M_ROR_I: |
| 13132 | { |
| 13133 | unsigned int rot; |
| 13134 | |
| 13135 | rot = imm_expr.X_add_number & 0x1f; |
| 13136 | if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch)) |
| 13137 | { |
| 13138 | macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); |
| 13139 | break; |
| 13140 | } |
| 13141 | if (rot == 0) |
| 13142 | { |
| 13143 | macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], 0); |
| 13144 | break; |
| 13145 | } |
| 13146 | used_at = 1; |
| 13147 | macro_build (NULL, "srl", SHFT_FMT, AT, op[1], rot); |
| 13148 | macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], (0x20 - rot) & 0x1f); |
| 13149 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
| 13150 | } |
| 13151 | break; |
| 13152 | |
| 13153 | case M_SEQ: |
| 13154 | if (op[1] == 0) |
| 13155 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[2], BFD_RELOC_LO16); |
| 13156 | else if (op[2] == 0) |
| 13157 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
| 13158 | else |
| 13159 | { |
| 13160 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
| 13161 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
| 13162 | } |
| 13163 | break; |
| 13164 | |
| 13165 | case M_SEQ_I: |
| 13166 | if (imm_expr.X_add_number == 0) |
| 13167 | { |
| 13168 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
| 13169 | break; |
| 13170 | } |
| 13171 | if (op[1] == 0) |
| 13172 | { |
| 13173 | as_warn (_("instruction %s: result is always false"), |
| 13174 | ip->insn_mo->name); |
| 13175 | move_register (op[0], 0); |
| 13176 | break; |
| 13177 | } |
| 13178 | if (CPU_HAS_SEQ (mips_opts.arch) |
| 13179 | && -512 <= imm_expr.X_add_number |
| 13180 | && imm_expr.X_add_number < 512) |
| 13181 | { |
| 13182 | macro_build (NULL, "seqi", "t,r,+Q", op[0], op[1], |
| 13183 | (int) imm_expr.X_add_number); |
| 13184 | break; |
| 13185 | } |
| 13186 | if (imm_expr.X_add_number >= 0 |
| 13187 | && imm_expr.X_add_number < 0x10000) |
| 13188 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], BFD_RELOC_LO16); |
| 13189 | else if (imm_expr.X_add_number > -0x8000 |
| 13190 | && imm_expr.X_add_number < 0) |
| 13191 | { |
| 13192 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 13193 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
| 13194 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
| 13195 | } |
| 13196 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
| 13197 | { |
| 13198 | used_at = 1; |
| 13199 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13200 | macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); |
| 13201 | break; |
| 13202 | } |
| 13203 | else |
| 13204 | { |
| 13205 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13206 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
| 13207 | used_at = 1; |
| 13208 | } |
| 13209 | macro_build (&expr1, "sltiu", "t,r,j", op[0], op[0], BFD_RELOC_LO16); |
| 13210 | break; |
| 13211 | |
| 13212 | case M_SGE: /* X >= Y <==> not (X < Y) */ |
| 13213 | s = "slt"; |
| 13214 | goto sge; |
| 13215 | case M_SGEU: |
| 13216 | s = "sltu"; |
| 13217 | sge: |
| 13218 | macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); |
| 13219 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
| 13220 | break; |
| 13221 | |
| 13222 | case M_SGE_I: /* X >= I <==> not (X < I) */ |
| 13223 | case M_SGEU_I: |
| 13224 | if (imm_expr.X_add_number >= -0x8000 |
| 13225 | && imm_expr.X_add_number < 0x8000) |
| 13226 | macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j", |
| 13227 | op[0], op[1], BFD_RELOC_LO16); |
| 13228 | else |
| 13229 | { |
| 13230 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13231 | macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", |
| 13232 | op[0], op[1], AT); |
| 13233 | used_at = 1; |
| 13234 | } |
| 13235 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
| 13236 | break; |
| 13237 | |
| 13238 | case M_SGT: /* X > Y <==> Y < X */ |
| 13239 | s = "slt"; |
| 13240 | goto sgt; |
| 13241 | case M_SGTU: |
| 13242 | s = "sltu"; |
| 13243 | sgt: |
| 13244 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
| 13245 | break; |
| 13246 | |
| 13247 | case M_SGT_I: /* X > I <==> I < X */ |
| 13248 | s = "slt"; |
| 13249 | goto sgti; |
| 13250 | case M_SGTU_I: |
| 13251 | s = "sltu"; |
| 13252 | sgti: |
| 13253 | used_at = 1; |
| 13254 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13255 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
| 13256 | break; |
| 13257 | |
| 13258 | case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ |
| 13259 | s = "slt"; |
| 13260 | goto sle; |
| 13261 | case M_SLEU: |
| 13262 | s = "sltu"; |
| 13263 | sle: |
| 13264 | macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); |
| 13265 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
| 13266 | break; |
| 13267 | |
| 13268 | case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ |
| 13269 | s = "slt"; |
| 13270 | goto slei; |
| 13271 | case M_SLEU_I: |
| 13272 | s = "sltu"; |
| 13273 | slei: |
| 13274 | used_at = 1; |
| 13275 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13276 | macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); |
| 13277 | macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); |
| 13278 | break; |
| 13279 | |
| 13280 | case M_SLT_I: |
| 13281 | if (imm_expr.X_add_number >= -0x8000 |
| 13282 | && imm_expr.X_add_number < 0x8000) |
| 13283 | { |
| 13284 | macro_build (&imm_expr, "slti", "t,r,j", op[0], op[1], |
| 13285 | BFD_RELOC_LO16); |
| 13286 | break; |
| 13287 | } |
| 13288 | used_at = 1; |
| 13289 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13290 | macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); |
| 13291 | break; |
| 13292 | |
| 13293 | case M_SLTU_I: |
| 13294 | if (imm_expr.X_add_number >= -0x8000 |
| 13295 | && imm_expr.X_add_number < 0x8000) |
| 13296 | { |
| 13297 | macro_build (&imm_expr, "sltiu", "t,r,j", op[0], op[1], |
| 13298 | BFD_RELOC_LO16); |
| 13299 | break; |
| 13300 | } |
| 13301 | used_at = 1; |
| 13302 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13303 | macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); |
| 13304 | break; |
| 13305 | |
| 13306 | case M_SNE: |
| 13307 | if (op[1] == 0) |
| 13308 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); |
| 13309 | else if (op[2] == 0) |
| 13310 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
| 13311 | else |
| 13312 | { |
| 13313 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); |
| 13314 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
| 13315 | } |
| 13316 | break; |
| 13317 | |
| 13318 | case M_SNE_I: |
| 13319 | if (imm_expr.X_add_number == 0) |
| 13320 | { |
| 13321 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); |
| 13322 | break; |
| 13323 | } |
| 13324 | if (op[1] == 0) |
| 13325 | { |
| 13326 | as_warn (_("instruction %s: result is always true"), |
| 13327 | ip->insn_mo->name); |
| 13328 | macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", |
| 13329 | op[0], 0, BFD_RELOC_LO16); |
| 13330 | break; |
| 13331 | } |
| 13332 | if (CPU_HAS_SEQ (mips_opts.arch) |
| 13333 | && -512 <= imm_expr.X_add_number |
| 13334 | && imm_expr.X_add_number < 512) |
| 13335 | { |
| 13336 | macro_build (NULL, "snei", "t,r,+Q", op[0], op[1], |
| 13337 | (int) imm_expr.X_add_number); |
| 13338 | break; |
| 13339 | } |
| 13340 | if (imm_expr.X_add_number >= 0 |
| 13341 | && imm_expr.X_add_number < 0x10000) |
| 13342 | { |
| 13343 | macro_build (&imm_expr, "xori", "t,r,i", op[0], op[1], |
| 13344 | BFD_RELOC_LO16); |
| 13345 | } |
| 13346 | else if (imm_expr.X_add_number > -0x8000 |
| 13347 | && imm_expr.X_add_number < 0) |
| 13348 | { |
| 13349 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 13350 | macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", |
| 13351 | "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
| 13352 | } |
| 13353 | else if (CPU_HAS_SEQ (mips_opts.arch)) |
| 13354 | { |
| 13355 | used_at = 1; |
| 13356 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13357 | macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); |
| 13358 | break; |
| 13359 | } |
| 13360 | else |
| 13361 | { |
| 13362 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13363 | macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); |
| 13364 | used_at = 1; |
| 13365 | } |
| 13366 | macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); |
| 13367 | break; |
| 13368 | |
| 13369 | case M_SUB_I: |
| 13370 | s = "addi"; |
| 13371 | s2 = "sub"; |
| 13372 | goto do_subi; |
| 13373 | case M_SUBU_I: |
| 13374 | s = "addiu"; |
| 13375 | s2 = "subu"; |
| 13376 | goto do_subi; |
| 13377 | case M_DSUB_I: |
| 13378 | dbl = 1; |
| 13379 | s = "daddi"; |
| 13380 | s2 = "dsub"; |
| 13381 | if (!mips_opts.micromips) |
| 13382 | goto do_subi; |
| 13383 | if (imm_expr.X_add_number > -0x200 |
| 13384 | && imm_expr.X_add_number <= 0x200) |
| 13385 | { |
| 13386 | macro_build (NULL, s, "t,r,.", op[0], op[1], |
| 13387 | (int) -imm_expr.X_add_number); |
| 13388 | break; |
| 13389 | } |
| 13390 | goto do_subi_i; |
| 13391 | case M_DSUBU_I: |
| 13392 | dbl = 1; |
| 13393 | s = "daddiu"; |
| 13394 | s2 = "dsubu"; |
| 13395 | do_subi: |
| 13396 | if (imm_expr.X_add_number > -0x8000 |
| 13397 | && imm_expr.X_add_number <= 0x8000) |
| 13398 | { |
| 13399 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 13400 | macro_build (&imm_expr, s, "t,r,j", op[0], op[1], BFD_RELOC_LO16); |
| 13401 | break; |
| 13402 | } |
| 13403 | do_subi_i: |
| 13404 | used_at = 1; |
| 13405 | load_register (AT, &imm_expr, dbl); |
| 13406 | macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); |
| 13407 | break; |
| 13408 | |
| 13409 | case M_TEQ_I: |
| 13410 | s = "teq"; |
| 13411 | goto trap; |
| 13412 | case M_TGE_I: |
| 13413 | s = "tge"; |
| 13414 | goto trap; |
| 13415 | case M_TGEU_I: |
| 13416 | s = "tgeu"; |
| 13417 | goto trap; |
| 13418 | case M_TLT_I: |
| 13419 | s = "tlt"; |
| 13420 | goto trap; |
| 13421 | case M_TLTU_I: |
| 13422 | s = "tltu"; |
| 13423 | goto trap; |
| 13424 | case M_TNE_I: |
| 13425 | s = "tne"; |
| 13426 | trap: |
| 13427 | used_at = 1; |
| 13428 | load_register (AT, &imm_expr, GPR_SIZE == 64); |
| 13429 | macro_build (NULL, s, "s,t", op[0], AT); |
| 13430 | break; |
| 13431 | |
| 13432 | case M_TRUNCWS: |
| 13433 | case M_TRUNCWD: |
| 13434 | gas_assert (!mips_opts.micromips); |
| 13435 | gas_assert (mips_opts.isa == ISA_MIPS1); |
| 13436 | used_at = 1; |
| 13437 | |
| 13438 | /* |
| 13439 | * Is the double cfc1 instruction a bug in the mips assembler; |
| 13440 | * or is there a reason for it? |
| 13441 | */ |
| 13442 | start_noreorder (); |
| 13443 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
| 13444 | macro_build (NULL, "cfc1", "t,G", op[2], RA); |
| 13445 | macro_build (NULL, "nop", ""); |
| 13446 | expr1.X_add_number = 3; |
| 13447 | macro_build (&expr1, "ori", "t,r,i", AT, op[2], BFD_RELOC_LO16); |
| 13448 | expr1.X_add_number = 2; |
| 13449 | macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16); |
| 13450 | macro_build (NULL, "ctc1", "t,G", AT, RA); |
| 13451 | macro_build (NULL, "nop", ""); |
| 13452 | macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", |
| 13453 | op[0], op[1]); |
| 13454 | macro_build (NULL, "ctc1", "t,G", op[2], RA); |
| 13455 | macro_build (NULL, "nop", ""); |
| 13456 | end_noreorder (); |
| 13457 | break; |
| 13458 | |
| 13459 | case M_ULH_AB: |
| 13460 | s = "lb"; |
| 13461 | s2 = "lbu"; |
| 13462 | off = 1; |
| 13463 | goto uld_st; |
| 13464 | case M_ULHU_AB: |
| 13465 | s = "lbu"; |
| 13466 | s2 = "lbu"; |
| 13467 | off = 1; |
| 13468 | goto uld_st; |
| 13469 | case M_ULW_AB: |
| 13470 | s = "lwl"; |
| 13471 | s2 = "lwr"; |
| 13472 | offbits = (mips_opts.micromips ? 12 : 16); |
| 13473 | off = 3; |
| 13474 | goto uld_st; |
| 13475 | case M_ULD_AB: |
| 13476 | s = "ldl"; |
| 13477 | s2 = "ldr"; |
| 13478 | offbits = (mips_opts.micromips ? 12 : 16); |
| 13479 | off = 7; |
| 13480 | goto uld_st; |
| 13481 | case M_USH_AB: |
| 13482 | s = "sb"; |
| 13483 | s2 = "sb"; |
| 13484 | off = 1; |
| 13485 | ust = 1; |
| 13486 | goto uld_st; |
| 13487 | case M_USW_AB: |
| 13488 | s = "swl"; |
| 13489 | s2 = "swr"; |
| 13490 | offbits = (mips_opts.micromips ? 12 : 16); |
| 13491 | off = 3; |
| 13492 | ust = 1; |
| 13493 | goto uld_st; |
| 13494 | case M_USD_AB: |
| 13495 | s = "sdl"; |
| 13496 | s2 = "sdr"; |
| 13497 | offbits = (mips_opts.micromips ? 12 : 16); |
| 13498 | off = 7; |
| 13499 | ust = 1; |
| 13500 | |
| 13501 | uld_st: |
| 13502 | breg = op[2]; |
| 13503 | large_offset = !small_offset_p (off, align, offbits); |
| 13504 | ep = &offset_expr; |
| 13505 | expr1.X_add_number = 0; |
| 13506 | if (large_offset) |
| 13507 | { |
| 13508 | used_at = 1; |
| 13509 | tempreg = AT; |
| 13510 | if (small_offset_p (0, align, 16)) |
| 13511 | macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", tempreg, breg, -1, |
| 13512 | offset_reloc[0], offset_reloc[1], offset_reloc[2]); |
| 13513 | else |
| 13514 | { |
| 13515 | load_address (tempreg, ep, &used_at); |
| 13516 | if (breg != 0) |
| 13517 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", |
| 13518 | tempreg, tempreg, breg); |
| 13519 | } |
| 13520 | offset_reloc[0] = BFD_RELOC_LO16; |
| 13521 | offset_reloc[1] = BFD_RELOC_UNUSED; |
| 13522 | offset_reloc[2] = BFD_RELOC_UNUSED; |
| 13523 | breg = tempreg; |
| 13524 | tempreg = op[0]; |
| 13525 | ep = &expr1; |
| 13526 | } |
| 13527 | else if (!ust && op[0] == breg) |
| 13528 | { |
| 13529 | used_at = 1; |
| 13530 | tempreg = AT; |
| 13531 | } |
| 13532 | else |
| 13533 | tempreg = op[0]; |
| 13534 | |
| 13535 | if (off == 1) |
| 13536 | goto ulh_sh; |
| 13537 | |
| 13538 | if (!target_big_endian) |
| 13539 | ep->X_add_number += off; |
| 13540 | if (offbits == 12) |
| 13541 | macro_build (NULL, s, "t,~(b)", tempreg, (int) ep->X_add_number, breg); |
| 13542 | else |
| 13543 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
| 13544 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); |
| 13545 | |
| 13546 | if (!target_big_endian) |
| 13547 | ep->X_add_number -= off; |
| 13548 | else |
| 13549 | ep->X_add_number += off; |
| 13550 | if (offbits == 12) |
| 13551 | macro_build (NULL, s2, "t,~(b)", |
| 13552 | tempreg, (int) ep->X_add_number, breg); |
| 13553 | else |
| 13554 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
| 13555 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); |
| 13556 | |
| 13557 | /* If necessary, move the result in tempreg to the final destination. */ |
| 13558 | if (!ust && op[0] != tempreg) |
| 13559 | { |
| 13560 | /* Protect second load's delay slot. */ |
| 13561 | load_delay_nop (); |
| 13562 | move_register (op[0], tempreg); |
| 13563 | } |
| 13564 | break; |
| 13565 | |
| 13566 | ulh_sh: |
| 13567 | used_at = 1; |
| 13568 | if (target_big_endian == ust) |
| 13569 | ep->X_add_number += off; |
| 13570 | tempreg = ust || large_offset ? op[0] : AT; |
| 13571 | macro_build (ep, s, "t,o(b)", tempreg, -1, |
| 13572 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); |
| 13573 | |
| 13574 | /* For halfword transfers we need a temporary register to shuffle |
| 13575 | bytes. Unfortunately for M_USH_A we have none available before |
| 13576 | the next store as AT holds the base address. We deal with this |
| 13577 | case by clobbering TREG and then restoring it as with ULH. */ |
| 13578 | tempreg = ust == large_offset ? op[0] : AT; |
| 13579 | if (ust) |
| 13580 | macro_build (NULL, "srl", SHFT_FMT, tempreg, op[0], 8); |
| 13581 | |
| 13582 | if (target_big_endian == ust) |
| 13583 | ep->X_add_number -= off; |
| 13584 | else |
| 13585 | ep->X_add_number += off; |
| 13586 | macro_build (ep, s2, "t,o(b)", tempreg, -1, |
| 13587 | offset_reloc[0], offset_reloc[1], offset_reloc[2], breg); |
| 13588 | |
| 13589 | /* For M_USH_A re-retrieve the LSB. */ |
| 13590 | if (ust && large_offset) |
| 13591 | { |
| 13592 | if (target_big_endian) |
| 13593 | ep->X_add_number += off; |
| 13594 | else |
| 13595 | ep->X_add_number -= off; |
| 13596 | macro_build (&expr1, "lbu", "t,o(b)", AT, -1, |
| 13597 | offset_reloc[0], offset_reloc[1], offset_reloc[2], AT); |
| 13598 | } |
| 13599 | /* For ULH and M_USH_A OR the LSB in. */ |
| 13600 | if (!ust || large_offset) |
| 13601 | { |
| 13602 | tempreg = !large_offset ? AT : op[0]; |
| 13603 | macro_build (NULL, "sll", SHFT_FMT, tempreg, tempreg, 8); |
| 13604 | macro_build (NULL, "or", "d,v,t", op[0], op[0], AT); |
| 13605 | } |
| 13606 | break; |
| 13607 | |
| 13608 | default: |
| 13609 | /* FIXME: Check if this is one of the itbl macros, since they |
| 13610 | are added dynamically. */ |
| 13611 | as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); |
| 13612 | break; |
| 13613 | } |
| 13614 | if (!mips_opts.at && used_at) |
| 13615 | as_bad (_("macro used $at after \".set noat\"")); |
| 13616 | } |
| 13617 | |
| 13618 | /* Implement macros in mips16 mode. */ |
| 13619 | |
| 13620 | static void |
| 13621 | mips16_macro (struct mips_cl_insn *ip) |
| 13622 | { |
| 13623 | const struct mips_operand_array *operands; |
| 13624 | int mask; |
| 13625 | int tmp; |
| 13626 | expressionS expr1; |
| 13627 | int dbl; |
| 13628 | const char *s, *s2, *s3; |
| 13629 | unsigned int op[MAX_OPERANDS]; |
| 13630 | unsigned int i; |
| 13631 | |
| 13632 | mask = ip->insn_mo->mask; |
| 13633 | |
| 13634 | operands = insn_operands (ip); |
| 13635 | for (i = 0; i < MAX_OPERANDS; i++) |
| 13636 | if (operands->operand[i]) |
| 13637 | op[i] = insn_extract_operand (ip, operands->operand[i]); |
| 13638 | else |
| 13639 | op[i] = -1; |
| 13640 | |
| 13641 | expr1.X_op = O_constant; |
| 13642 | expr1.X_op_symbol = NULL; |
| 13643 | expr1.X_add_symbol = NULL; |
| 13644 | expr1.X_add_number = 1; |
| 13645 | |
| 13646 | dbl = 0; |
| 13647 | |
| 13648 | switch (mask) |
| 13649 | { |
| 13650 | default: |
| 13651 | abort (); |
| 13652 | |
| 13653 | case M_DDIV_3: |
| 13654 | dbl = 1; |
| 13655 | /* Fall through. */ |
| 13656 | case M_DIV_3: |
| 13657 | s = "mflo"; |
| 13658 | goto do_div3; |
| 13659 | case M_DREM_3: |
| 13660 | dbl = 1; |
| 13661 | /* Fall through. */ |
| 13662 | case M_REM_3: |
| 13663 | s = "mfhi"; |
| 13664 | do_div3: |
| 13665 | start_noreorder (); |
| 13666 | macro_build (NULL, dbl ? "ddiv" : "div", ".,x,y", op[1], op[2]); |
| 13667 | expr1.X_add_number = 2; |
| 13668 | macro_build (&expr1, "bnez", "x,p", op[2]); |
| 13669 | macro_build (NULL, "break", "6", 7); |
| 13670 | |
| 13671 | /* FIXME: The normal code checks for of -1 / -0x80000000 here, |
| 13672 | since that causes an overflow. We should do that as well, |
| 13673 | but I don't see how to do the comparisons without a temporary |
| 13674 | register. */ |
| 13675 | end_noreorder (); |
| 13676 | macro_build (NULL, s, "x", op[0]); |
| 13677 | break; |
| 13678 | |
| 13679 | case M_DIVU_3: |
| 13680 | s = "divu"; |
| 13681 | s2 = "mflo"; |
| 13682 | goto do_divu3; |
| 13683 | case M_REMU_3: |
| 13684 | s = "divu"; |
| 13685 | s2 = "mfhi"; |
| 13686 | goto do_divu3; |
| 13687 | case M_DDIVU_3: |
| 13688 | s = "ddivu"; |
| 13689 | s2 = "mflo"; |
| 13690 | goto do_divu3; |
| 13691 | case M_DREMU_3: |
| 13692 | s = "ddivu"; |
| 13693 | s2 = "mfhi"; |
| 13694 | do_divu3: |
| 13695 | start_noreorder (); |
| 13696 | macro_build (NULL, s, ".,x,y", op[1], op[2]); |
| 13697 | expr1.X_add_number = 2; |
| 13698 | macro_build (&expr1, "bnez", "x,p", op[2]); |
| 13699 | macro_build (NULL, "break", "6", 7); |
| 13700 | end_noreorder (); |
| 13701 | macro_build (NULL, s2, "x", op[0]); |
| 13702 | break; |
| 13703 | |
| 13704 | case M_DMUL: |
| 13705 | dbl = 1; |
| 13706 | /* Fall through. */ |
| 13707 | case M_MUL: |
| 13708 | macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", op[1], op[2]); |
| 13709 | macro_build (NULL, "mflo", "x", op[0]); |
| 13710 | break; |
| 13711 | |
| 13712 | case M_DSUBU_I: |
| 13713 | dbl = 1; |
| 13714 | goto do_subu; |
| 13715 | case M_SUBU_I: |
| 13716 | do_subu: |
| 13717 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 13718 | macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,F", op[0], op[1]); |
| 13719 | break; |
| 13720 | |
| 13721 | case M_SUBU_I_2: |
| 13722 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 13723 | macro_build (&imm_expr, "addiu", "x,k", op[0]); |
| 13724 | break; |
| 13725 | |
| 13726 | case M_DSUBU_I_2: |
| 13727 | imm_expr.X_add_number = -imm_expr.X_add_number; |
| 13728 | macro_build (&imm_expr, "daddiu", "y,j", op[0]); |
| 13729 | break; |
| 13730 | |
| 13731 | case M_BEQ: |
| 13732 | s = "cmp"; |
| 13733 | s2 = "bteqz"; |
| 13734 | goto do_branch; |
| 13735 | case M_BNE: |
| 13736 | s = "cmp"; |
| 13737 | s2 = "btnez"; |
| 13738 | goto do_branch; |
| 13739 | case M_BLT: |
| 13740 | s = "slt"; |
| 13741 | s2 = "btnez"; |
| 13742 | goto do_branch; |
| 13743 | case M_BLTU: |
| 13744 | s = "sltu"; |
| 13745 | s2 = "btnez"; |
| 13746 | goto do_branch; |
| 13747 | case M_BLE: |
| 13748 | s = "slt"; |
| 13749 | s2 = "bteqz"; |
| 13750 | goto do_reverse_branch; |
| 13751 | case M_BLEU: |
| 13752 | s = "sltu"; |
| 13753 | s2 = "bteqz"; |
| 13754 | goto do_reverse_branch; |
| 13755 | case M_BGE: |
| 13756 | s = "slt"; |
| 13757 | s2 = "bteqz"; |
| 13758 | goto do_branch; |
| 13759 | case M_BGEU: |
| 13760 | s = "sltu"; |
| 13761 | s2 = "bteqz"; |
| 13762 | goto do_branch; |
| 13763 | case M_BGT: |
| 13764 | s = "slt"; |
| 13765 | s2 = "btnez"; |
| 13766 | goto do_reverse_branch; |
| 13767 | case M_BGTU: |
| 13768 | s = "sltu"; |
| 13769 | s2 = "btnez"; |
| 13770 | |
| 13771 | do_reverse_branch: |
| 13772 | tmp = op[1]; |
| 13773 | op[1] = op[0]; |
| 13774 | op[0] = tmp; |
| 13775 | |
| 13776 | do_branch: |
| 13777 | macro_build (NULL, s, "x,y", op[0], op[1]); |
| 13778 | macro_build (&offset_expr, s2, "p"); |
| 13779 | break; |
| 13780 | |
| 13781 | case M_BEQ_I: |
| 13782 | s = "cmpi"; |
| 13783 | s2 = "bteqz"; |
| 13784 | s3 = "x,U"; |
| 13785 | goto do_branch_i; |
| 13786 | case M_BNE_I: |
| 13787 | s = "cmpi"; |
| 13788 | s2 = "btnez"; |
| 13789 | s3 = "x,U"; |
| 13790 | goto do_branch_i; |
| 13791 | case M_BLT_I: |
| 13792 | s = "slti"; |
| 13793 | s2 = "btnez"; |
| 13794 | s3 = "x,8"; |
| 13795 | goto do_branch_i; |
| 13796 | case M_BLTU_I: |
| 13797 | s = "sltiu"; |
| 13798 | s2 = "btnez"; |
| 13799 | s3 = "x,8"; |
| 13800 | goto do_branch_i; |
| 13801 | case M_BLE_I: |
| 13802 | s = "slti"; |
| 13803 | s2 = "btnez"; |
| 13804 | s3 = "x,8"; |
| 13805 | goto do_addone_branch_i; |
| 13806 | case M_BLEU_I: |
| 13807 | s = "sltiu"; |
| 13808 | s2 = "btnez"; |
| 13809 | s3 = "x,8"; |
| 13810 | goto do_addone_branch_i; |
| 13811 | case M_BGE_I: |
| 13812 | s = "slti"; |
| 13813 | s2 = "bteqz"; |
| 13814 | s3 = "x,8"; |
| 13815 | goto do_branch_i; |
| 13816 | case M_BGEU_I: |
| 13817 | s = "sltiu"; |
| 13818 | s2 = "bteqz"; |
| 13819 | s3 = "x,8"; |
| 13820 | goto do_branch_i; |
| 13821 | case M_BGT_I: |
| 13822 | s = "slti"; |
| 13823 | s2 = "bteqz"; |
| 13824 | s3 = "x,8"; |
| 13825 | goto do_addone_branch_i; |
| 13826 | case M_BGTU_I: |
| 13827 | s = "sltiu"; |
| 13828 | s2 = "bteqz"; |
| 13829 | s3 = "x,8"; |
| 13830 | |
| 13831 | do_addone_branch_i: |
| 13832 | ++imm_expr.X_add_number; |
| 13833 | |
| 13834 | do_branch_i: |
| 13835 | macro_build (&imm_expr, s, s3, op[0]); |
| 13836 | macro_build (&offset_expr, s2, "p"); |
| 13837 | break; |
| 13838 | |
| 13839 | case M_ABS: |
| 13840 | expr1.X_add_number = 0; |
| 13841 | macro_build (&expr1, "slti", "x,8", op[1]); |
| 13842 | if (op[0] != op[1]) |
| 13843 | macro_build (NULL, "move", "y,X", op[0], mips16_to_32_reg_map[op[1]]); |
| 13844 | expr1.X_add_number = 2; |
| 13845 | macro_build (&expr1, "bteqz", "p"); |
| 13846 | macro_build (NULL, "neg", "x,w", op[0], op[0]); |
| 13847 | break; |
| 13848 | } |
| 13849 | } |
| 13850 | |
| 13851 | /* Look up instruction [START, START + LENGTH) in HASH. Record any extra |
| 13852 | opcode bits in *OPCODE_EXTRA. */ |
| 13853 | |
| 13854 | static struct mips_opcode * |
| 13855 | mips_lookup_insn (struct hash_control *hash, const char *start, |
| 13856 | ssize_t length, unsigned int *opcode_extra) |
| 13857 | { |
| 13858 | char *name, *dot, *p; |
| 13859 | unsigned int mask, suffix; |
| 13860 | ssize_t opend; |
| 13861 | struct mips_opcode *insn; |
| 13862 | |
| 13863 | /* Make a copy of the instruction so that we can fiddle with it. */ |
| 13864 | name = xstrndup (start, length); |
| 13865 | |
| 13866 | /* Look up the instruction as-is. */ |
| 13867 | insn = (struct mips_opcode *) hash_find (hash, name); |
| 13868 | if (insn) |
| 13869 | goto end; |
| 13870 | |
| 13871 | dot = strchr (name, '.'); |
| 13872 | if (dot && dot[1]) |
| 13873 | { |
| 13874 | /* Try to interpret the text after the dot as a VU0 channel suffix. */ |
| 13875 | p = mips_parse_vu0_channels (dot + 1, &mask); |
| 13876 | if (*p == 0 && mask != 0) |
| 13877 | { |
| 13878 | *dot = 0; |
| 13879 | insn = (struct mips_opcode *) hash_find (hash, name); |
| 13880 | *dot = '.'; |
| 13881 | if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0) |
| 13882 | { |
| 13883 | *opcode_extra |= mask << mips_vu0_channel_mask.lsb; |
| 13884 | goto end; |
| 13885 | } |
| 13886 | } |
| 13887 | } |
| 13888 | |
| 13889 | if (mips_opts.micromips) |
| 13890 | { |
| 13891 | /* See if there's an instruction size override suffix, |
| 13892 | either `16' or `32', at the end of the mnemonic proper, |
| 13893 | that defines the operation, i.e. before the first `.' |
| 13894 | character if any. Strip it and retry. */ |
| 13895 | opend = dot != NULL ? dot - name : length; |
| 13896 | if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') |
| 13897 | suffix = 2; |
| 13898 | else if (name[opend - 2] == '3' && name[opend - 1] == '2') |
| 13899 | suffix = 4; |
| 13900 | else |
| 13901 | suffix = 0; |
| 13902 | if (suffix) |
| 13903 | { |
| 13904 | memcpy (name + opend - 2, name + opend, length - opend + 1); |
| 13905 | insn = (struct mips_opcode *) hash_find (hash, name); |
| 13906 | if (insn) |
| 13907 | { |
| 13908 | forced_insn_length = suffix; |
| 13909 | goto end; |
| 13910 | } |
| 13911 | } |
| 13912 | } |
| 13913 | |
| 13914 | insn = NULL; |
| 13915 | end: |
| 13916 | free (name); |
| 13917 | return insn; |
| 13918 | } |
| 13919 | |
| 13920 | /* Assemble an instruction into its binary format. If the instruction |
| 13921 | is a macro, set imm_expr and offset_expr to the values associated |
| 13922 | with "I" and "A" operands respectively. Otherwise store the value |
| 13923 | of the relocatable field (if any) in offset_expr. In both cases |
| 13924 | set offset_reloc to the relocation operators applied to offset_expr. */ |
| 13925 | |
| 13926 | static void |
| 13927 | mips_ip (char *str, struct mips_cl_insn *insn) |
| 13928 | { |
| 13929 | const struct mips_opcode *first, *past; |
| 13930 | struct hash_control *hash; |
| 13931 | char format; |
| 13932 | size_t end; |
| 13933 | struct mips_operand_token *tokens; |
| 13934 | unsigned int opcode_extra; |
| 13935 | |
| 13936 | if (mips_opts.micromips) |
| 13937 | { |
| 13938 | hash = micromips_op_hash; |
| 13939 | past = µmips_opcodes[bfd_micromips_num_opcodes]; |
| 13940 | } |
| 13941 | else |
| 13942 | { |
| 13943 | hash = op_hash; |
| 13944 | past = &mips_opcodes[NUMOPCODES]; |
| 13945 | } |
| 13946 | forced_insn_length = 0; |
| 13947 | opcode_extra = 0; |
| 13948 | |
| 13949 | /* We first try to match an instruction up to a space or to the end. */ |
| 13950 | for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++) |
| 13951 | continue; |
| 13952 | |
| 13953 | first = mips_lookup_insn (hash, str, end, &opcode_extra); |
| 13954 | if (first == NULL) |
| 13955 | { |
| 13956 | set_insn_error (0, _("unrecognized opcode")); |
| 13957 | return; |
| 13958 | } |
| 13959 | |
| 13960 | if (strcmp (first->name, "li.s") == 0) |
| 13961 | format = 'f'; |
| 13962 | else if (strcmp (first->name, "li.d") == 0) |
| 13963 | format = 'd'; |
| 13964 | else |
| 13965 | format = 0; |
| 13966 | tokens = mips_parse_arguments (str + end, format); |
| 13967 | if (!tokens) |
| 13968 | return; |
| 13969 | |
| 13970 | if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE) |
| 13971 | && !match_insns (insn, first, past, tokens, opcode_extra, TRUE)) |
| 13972 | set_insn_error (0, _("invalid operands")); |
| 13973 | |
| 13974 | obstack_free (&mips_operand_tokens, tokens); |
| 13975 | } |
| 13976 | |
| 13977 | /* As for mips_ip, but used when assembling MIPS16 code. |
| 13978 | Also set forced_insn_length to the resulting instruction size in |
| 13979 | bytes if the user explicitly requested a small or extended instruction. */ |
| 13980 | |
| 13981 | static void |
| 13982 | mips16_ip (char *str, struct mips_cl_insn *insn) |
| 13983 | { |
| 13984 | char *end, *s, c; |
| 13985 | struct mips_opcode *first; |
| 13986 | struct mips_operand_token *tokens; |
| 13987 | unsigned int l; |
| 13988 | |
| 13989 | for (s = str; *s != '\0' && *s != '.' && *s != ' '; ++s) |
| 13990 | ; |
| 13991 | end = s; |
| 13992 | c = *end; |
| 13993 | |
| 13994 | l = 0; |
| 13995 | switch (c) |
| 13996 | { |
| 13997 | case '\0': |
| 13998 | break; |
| 13999 | |
| 14000 | case ' ': |
| 14001 | s++; |
| 14002 | break; |
| 14003 | |
| 14004 | case '.': |
| 14005 | s++; |
| 14006 | if (*s == 't') |
| 14007 | { |
| 14008 | l = 2; |
| 14009 | s++; |
| 14010 | } |
| 14011 | else if (*s == 'e') |
| 14012 | { |
| 14013 | l = 4; |
| 14014 | s++; |
| 14015 | } |
| 14016 | if (*s == '\0') |
| 14017 | break; |
| 14018 | else if (*s++ == ' ') |
| 14019 | break; |
| 14020 | set_insn_error (0, _("unrecognized opcode")); |
| 14021 | return; |
| 14022 | } |
| 14023 | forced_insn_length = l; |
| 14024 | |
| 14025 | *end = 0; |
| 14026 | first = (struct mips_opcode *) hash_find (mips16_op_hash, str); |
| 14027 | *end = c; |
| 14028 | |
| 14029 | if (!first) |
| 14030 | { |
| 14031 | set_insn_error (0, _("unrecognized opcode")); |
| 14032 | return; |
| 14033 | } |
| 14034 | |
| 14035 | tokens = mips_parse_arguments (s, 0); |
| 14036 | if (!tokens) |
| 14037 | return; |
| 14038 | |
| 14039 | if (!match_mips16_insns (insn, first, tokens)) |
| 14040 | set_insn_error (0, _("invalid operands")); |
| 14041 | |
| 14042 | obstack_free (&mips_operand_tokens, tokens); |
| 14043 | } |
| 14044 | |
| 14045 | /* Marshal immediate value VAL for an extended MIPS16 instruction. |
| 14046 | NBITS is the number of significant bits in VAL. */ |
| 14047 | |
| 14048 | static unsigned long |
| 14049 | mips16_immed_extend (offsetT val, unsigned int nbits) |
| 14050 | { |
| 14051 | int extval; |
| 14052 | |
| 14053 | extval = 0; |
| 14054 | val &= (1U << nbits) - 1; |
| 14055 | if (nbits == 16 || nbits == 9) |
| 14056 | { |
| 14057 | extval = ((val >> 11) & 0x1f) | (val & 0x7e0); |
| 14058 | val &= 0x1f; |
| 14059 | } |
| 14060 | else if (nbits == 15) |
| 14061 | { |
| 14062 | extval = ((val >> 11) & 0xf) | (val & 0x7f0); |
| 14063 | val &= 0xf; |
| 14064 | } |
| 14065 | else if (nbits == 6) |
| 14066 | { |
| 14067 | extval = ((val & 0x1f) << 6) | (val & 0x20); |
| 14068 | val = 0; |
| 14069 | } |
| 14070 | return (extval << 16) | val; |
| 14071 | } |
| 14072 | |
| 14073 | /* Like decode_mips16_operand, but require the operand to be defined and |
| 14074 | require it to be an integer. */ |
| 14075 | |
| 14076 | static const struct mips_int_operand * |
| 14077 | mips16_immed_operand (int type, bfd_boolean extended_p) |
| 14078 | { |
| 14079 | const struct mips_operand *operand; |
| 14080 | |
| 14081 | operand = decode_mips16_operand (type, extended_p); |
| 14082 | if (!operand || (operand->type != OP_INT && operand->type != OP_PCREL)) |
| 14083 | abort (); |
| 14084 | return (const struct mips_int_operand *) operand; |
| 14085 | } |
| 14086 | |
| 14087 | /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */ |
| 14088 | |
| 14089 | static bfd_boolean |
| 14090 | mips16_immed_in_range_p (const struct mips_int_operand *operand, |
| 14091 | bfd_reloc_code_real_type reloc, offsetT sval) |
| 14092 | { |
| 14093 | int min_val, max_val; |
| 14094 | |
| 14095 | min_val = mips_int_operand_min (operand); |
| 14096 | max_val = mips_int_operand_max (operand); |
| 14097 | if (reloc != BFD_RELOC_UNUSED) |
| 14098 | { |
| 14099 | if (min_val < 0) |
| 14100 | sval = SEXT_16BIT (sval); |
| 14101 | else |
| 14102 | sval &= 0xffff; |
| 14103 | } |
| 14104 | |
| 14105 | return (sval >= min_val |
| 14106 | && sval <= max_val |
| 14107 | && (sval & ((1 << operand->shift) - 1)) == 0); |
| 14108 | } |
| 14109 | |
| 14110 | /* Install immediate value VAL into MIPS16 instruction *INSN, |
| 14111 | extending it if necessary. The instruction in *INSN may |
| 14112 | already be extended. |
| 14113 | |
| 14114 | RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED |
| 14115 | if none. In the former case, VAL is a 16-bit number with no |
| 14116 | defined signedness. |
| 14117 | |
| 14118 | TYPE is the type of the immediate field. USER_INSN_LENGTH |
| 14119 | is the length that the user requested, or 0 if none. */ |
| 14120 | |
| 14121 | static void |
| 14122 | mips16_immed (const char *file, unsigned int line, int type, |
| 14123 | bfd_reloc_code_real_type reloc, offsetT val, |
| 14124 | unsigned int user_insn_length, unsigned long *insn) |
| 14125 | { |
| 14126 | const struct mips_int_operand *operand; |
| 14127 | unsigned int uval, length; |
| 14128 | |
| 14129 | operand = mips16_immed_operand (type, FALSE); |
| 14130 | if (!mips16_immed_in_range_p (operand, reloc, val)) |
| 14131 | { |
| 14132 | /* We need an extended instruction. */ |
| 14133 | if (user_insn_length == 2) |
| 14134 | as_bad_where (file, line, _("invalid unextended operand value")); |
| 14135 | else |
| 14136 | *insn |= MIPS16_EXTEND; |
| 14137 | } |
| 14138 | else if (user_insn_length == 4) |
| 14139 | { |
| 14140 | /* The operand doesn't force an unextended instruction to be extended. |
| 14141 | Warn if the user wanted an extended instruction anyway. */ |
| 14142 | *insn |= MIPS16_EXTEND; |
| 14143 | as_warn_where (file, line, |
| 14144 | _("extended operand requested but not required")); |
| 14145 | } |
| 14146 | |
| 14147 | length = mips16_opcode_length (*insn); |
| 14148 | if (length == 4) |
| 14149 | { |
| 14150 | operand = mips16_immed_operand (type, TRUE); |
| 14151 | if (!mips16_immed_in_range_p (operand, reloc, val)) |
| 14152 | as_bad_where (file, line, |
| 14153 | _("operand value out of range for instruction")); |
| 14154 | } |
| 14155 | uval = ((unsigned int) val >> operand->shift) - operand->bias; |
| 14156 | if (length == 2 || operand->root.lsb != 0) |
| 14157 | *insn = mips_insert_operand (&operand->root, *insn, uval); |
| 14158 | else |
| 14159 | *insn |= mips16_immed_extend (uval, operand->root.size); |
| 14160 | } |
| 14161 | \f |
| 14162 | struct percent_op_match |
| 14163 | { |
| 14164 | const char *str; |
| 14165 | bfd_reloc_code_real_type reloc; |
| 14166 | }; |
| 14167 | |
| 14168 | static const struct percent_op_match mips_percent_op[] = |
| 14169 | { |
| 14170 | {"%lo", BFD_RELOC_LO16}, |
| 14171 | {"%call_hi", BFD_RELOC_MIPS_CALL_HI16}, |
| 14172 | {"%call_lo", BFD_RELOC_MIPS_CALL_LO16}, |
| 14173 | {"%call16", BFD_RELOC_MIPS_CALL16}, |
| 14174 | {"%got_disp", BFD_RELOC_MIPS_GOT_DISP}, |
| 14175 | {"%got_page", BFD_RELOC_MIPS_GOT_PAGE}, |
| 14176 | {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST}, |
| 14177 | {"%got_hi", BFD_RELOC_MIPS_GOT_HI16}, |
| 14178 | {"%got_lo", BFD_RELOC_MIPS_GOT_LO16}, |
| 14179 | {"%got", BFD_RELOC_MIPS_GOT16}, |
| 14180 | {"%gp_rel", BFD_RELOC_GPREL16}, |
| 14181 | {"%gprel", BFD_RELOC_GPREL16}, |
| 14182 | {"%half", BFD_RELOC_16}, |
| 14183 | {"%highest", BFD_RELOC_MIPS_HIGHEST}, |
| 14184 | {"%higher", BFD_RELOC_MIPS_HIGHER}, |
| 14185 | {"%neg", BFD_RELOC_MIPS_SUB}, |
| 14186 | {"%tlsgd", BFD_RELOC_MIPS_TLS_GD}, |
| 14187 | {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM}, |
| 14188 | {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16}, |
| 14189 | {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16}, |
| 14190 | {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, |
| 14191 | {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, |
| 14192 | {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, |
| 14193 | {"%hi", BFD_RELOC_HI16_S}, |
| 14194 | {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, |
| 14195 | {"%pcrel_lo", BFD_RELOC_LO16_PCREL} |
| 14196 | }; |
| 14197 | |
| 14198 | static const struct percent_op_match mips16_percent_op[] = |
| 14199 | { |
| 14200 | {"%lo", BFD_RELOC_MIPS16_LO16}, |
| 14201 | {"%gp_rel", BFD_RELOC_MIPS16_GPREL}, |
| 14202 | {"%gprel", BFD_RELOC_MIPS16_GPREL}, |
| 14203 | {"%got", BFD_RELOC_MIPS16_GOT16}, |
| 14204 | {"%call16", BFD_RELOC_MIPS16_CALL16}, |
| 14205 | {"%hi", BFD_RELOC_MIPS16_HI16_S}, |
| 14206 | {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD}, |
| 14207 | {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM}, |
| 14208 | {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16}, |
| 14209 | {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16}, |
| 14210 | {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16}, |
| 14211 | {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16}, |
| 14212 | {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL} |
| 14213 | }; |
| 14214 | |
| 14215 | |
| 14216 | /* Return true if *STR points to a relocation operator. When returning true, |
| 14217 | move *STR over the operator and store its relocation code in *RELOC. |
| 14218 | Leave both *STR and *RELOC alone when returning false. */ |
| 14219 | |
| 14220 | static bfd_boolean |
| 14221 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc) |
| 14222 | { |
| 14223 | const struct percent_op_match *percent_op; |
| 14224 | size_t limit, i; |
| 14225 | |
| 14226 | if (mips_opts.mips16) |
| 14227 | { |
| 14228 | percent_op = mips16_percent_op; |
| 14229 | limit = ARRAY_SIZE (mips16_percent_op); |
| 14230 | } |
| 14231 | else |
| 14232 | { |
| 14233 | percent_op = mips_percent_op; |
| 14234 | limit = ARRAY_SIZE (mips_percent_op); |
| 14235 | } |
| 14236 | |
| 14237 | for (i = 0; i < limit; i++) |
| 14238 | if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0) |
| 14239 | { |
| 14240 | int len = strlen (percent_op[i].str); |
| 14241 | |
| 14242 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') |
| 14243 | continue; |
| 14244 | |
| 14245 | *str += strlen (percent_op[i].str); |
| 14246 | *reloc = percent_op[i].reloc; |
| 14247 | |
| 14248 | /* Check whether the output BFD supports this relocation. |
| 14249 | If not, issue an error and fall back on something safe. */ |
| 14250 | if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) |
| 14251 | { |
| 14252 | as_bad (_("relocation %s isn't supported by the current ABI"), |
| 14253 | percent_op[i].str); |
| 14254 | *reloc = BFD_RELOC_UNUSED; |
| 14255 | } |
| 14256 | return TRUE; |
| 14257 | } |
| 14258 | return FALSE; |
| 14259 | } |
| 14260 | |
| 14261 | |
| 14262 | /* Parse string STR as a 16-bit relocatable operand. Store the |
| 14263 | expression in *EP and the relocations in the array starting |
| 14264 | at RELOC. Return the number of relocation operators used. |
| 14265 | |
| 14266 | On exit, EXPR_END points to the first character after the expression. */ |
| 14267 | |
| 14268 | static size_t |
| 14269 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, |
| 14270 | char *str) |
| 14271 | { |
| 14272 | bfd_reloc_code_real_type reversed_reloc[3]; |
| 14273 | size_t reloc_index, i; |
| 14274 | int crux_depth, str_depth; |
| 14275 | char *crux; |
| 14276 | |
| 14277 | /* Search for the start of the main expression, recoding relocations |
| 14278 | in REVERSED_RELOC. End the loop with CRUX pointing to the start |
| 14279 | of the main expression and with CRUX_DEPTH containing the number |
| 14280 | of open brackets at that point. */ |
| 14281 | reloc_index = -1; |
| 14282 | str_depth = 0; |
| 14283 | do |
| 14284 | { |
| 14285 | reloc_index++; |
| 14286 | crux = str; |
| 14287 | crux_depth = str_depth; |
| 14288 | |
| 14289 | /* Skip over whitespace and brackets, keeping count of the number |
| 14290 | of brackets. */ |
| 14291 | while (*str == ' ' || *str == '\t' || *str == '(') |
| 14292 | if (*str++ == '(') |
| 14293 | str_depth++; |
| 14294 | } |
| 14295 | while (*str == '%' |
| 14296 | && reloc_index < (HAVE_NEWABI ? 3 : 1) |
| 14297 | && parse_relocation (&str, &reversed_reloc[reloc_index])); |
| 14298 | |
| 14299 | my_getExpression (ep, crux); |
| 14300 | str = expr_end; |
| 14301 | |
| 14302 | /* Match every open bracket. */ |
| 14303 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) |
| 14304 | if (*str++ == ')') |
| 14305 | crux_depth--; |
| 14306 | |
| 14307 | if (crux_depth > 0) |
| 14308 | as_bad (_("unclosed '('")); |
| 14309 | |
| 14310 | expr_end = str; |
| 14311 | |
| 14312 | if (reloc_index != 0) |
| 14313 | { |
| 14314 | prev_reloc_op_frag = frag_now; |
| 14315 | for (i = 0; i < reloc_index; i++) |
| 14316 | reloc[i] = reversed_reloc[reloc_index - 1 - i]; |
| 14317 | } |
| 14318 | |
| 14319 | return reloc_index; |
| 14320 | } |
| 14321 | |
| 14322 | static void |
| 14323 | my_getExpression (expressionS *ep, char *str) |
| 14324 | { |
| 14325 | char *save_in; |
| 14326 | |
| 14327 | save_in = input_line_pointer; |
| 14328 | input_line_pointer = str; |
| 14329 | expression (ep); |
| 14330 | expr_end = input_line_pointer; |
| 14331 | input_line_pointer = save_in; |
| 14332 | } |
| 14333 | |
| 14334 | const char * |
| 14335 | md_atof (int type, char *litP, int *sizeP) |
| 14336 | { |
| 14337 | return ieee_md_atof (type, litP, sizeP, target_big_endian); |
| 14338 | } |
| 14339 | |
| 14340 | void |
| 14341 | md_number_to_chars (char *buf, valueT val, int n) |
| 14342 | { |
| 14343 | if (target_big_endian) |
| 14344 | number_to_chars_bigendian (buf, val, n); |
| 14345 | else |
| 14346 | number_to_chars_littleendian (buf, val, n); |
| 14347 | } |
| 14348 | \f |
| 14349 | static int support_64bit_objects(void) |
| 14350 | { |
| 14351 | const char **list, **l; |
| 14352 | int yes; |
| 14353 | |
| 14354 | list = bfd_target_list (); |
| 14355 | for (l = list; *l != NULL; l++) |
| 14356 | if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0 |
| 14357 | || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0) |
| 14358 | break; |
| 14359 | yes = (*l != NULL); |
| 14360 | free (list); |
| 14361 | return yes; |
| 14362 | } |
| 14363 | |
| 14364 | /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to |
| 14365 | NEW_VALUE. Warn if another value was already specified. Note: |
| 14366 | we have to defer parsing the -march and -mtune arguments in order |
| 14367 | to handle 'from-abi' correctly, since the ABI might be specified |
| 14368 | in a later argument. */ |
| 14369 | |
| 14370 | static void |
| 14371 | mips_set_option_string (const char **string_ptr, const char *new_value) |
| 14372 | { |
| 14373 | if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) |
| 14374 | as_warn (_("a different %s was already specified, is now %s"), |
| 14375 | string_ptr == &mips_arch_string ? "-march" : "-mtune", |
| 14376 | new_value); |
| 14377 | |
| 14378 | *string_ptr = new_value; |
| 14379 | } |
| 14380 | |
| 14381 | int |
| 14382 | md_parse_option (int c, const char *arg) |
| 14383 | { |
| 14384 | unsigned int i; |
| 14385 | |
| 14386 | for (i = 0; i < ARRAY_SIZE (mips_ases); i++) |
| 14387 | if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) |
| 14388 | { |
| 14389 | file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, |
| 14390 | c == mips_ases[i].option_on); |
| 14391 | return 1; |
| 14392 | } |
| 14393 | |
| 14394 | switch (c) |
| 14395 | { |
| 14396 | case OPTION_CONSTRUCT_FLOATS: |
| 14397 | mips_disable_float_construction = 0; |
| 14398 | break; |
| 14399 | |
| 14400 | case OPTION_NO_CONSTRUCT_FLOATS: |
| 14401 | mips_disable_float_construction = 1; |
| 14402 | break; |
| 14403 | |
| 14404 | case OPTION_TRAP: |
| 14405 | mips_trap = 1; |
| 14406 | break; |
| 14407 | |
| 14408 | case OPTION_BREAK: |
| 14409 | mips_trap = 0; |
| 14410 | break; |
| 14411 | |
| 14412 | case OPTION_EB: |
| 14413 | target_big_endian = 1; |
| 14414 | break; |
| 14415 | |
| 14416 | case OPTION_EL: |
| 14417 | target_big_endian = 0; |
| 14418 | break; |
| 14419 | |
| 14420 | case 'O': |
| 14421 | if (arg == NULL) |
| 14422 | mips_optimize = 1; |
| 14423 | else if (arg[0] == '0') |
| 14424 | mips_optimize = 0; |
| 14425 | else if (arg[0] == '1') |
| 14426 | mips_optimize = 1; |
| 14427 | else |
| 14428 | mips_optimize = 2; |
| 14429 | break; |
| 14430 | |
| 14431 | case 'g': |
| 14432 | if (arg == NULL) |
| 14433 | mips_debug = 2; |
| 14434 | else |
| 14435 | mips_debug = atoi (arg); |
| 14436 | break; |
| 14437 | |
| 14438 | case OPTION_MIPS1: |
| 14439 | file_mips_opts.isa = ISA_MIPS1; |
| 14440 | break; |
| 14441 | |
| 14442 | case OPTION_MIPS2: |
| 14443 | file_mips_opts.isa = ISA_MIPS2; |
| 14444 | break; |
| 14445 | |
| 14446 | case OPTION_MIPS3: |
| 14447 | file_mips_opts.isa = ISA_MIPS3; |
| 14448 | break; |
| 14449 | |
| 14450 | case OPTION_MIPS4: |
| 14451 | file_mips_opts.isa = ISA_MIPS4; |
| 14452 | break; |
| 14453 | |
| 14454 | case OPTION_MIPS5: |
| 14455 | file_mips_opts.isa = ISA_MIPS5; |
| 14456 | break; |
| 14457 | |
| 14458 | case OPTION_MIPS32: |
| 14459 | file_mips_opts.isa = ISA_MIPS32; |
| 14460 | break; |
| 14461 | |
| 14462 | case OPTION_MIPS32R2: |
| 14463 | file_mips_opts.isa = ISA_MIPS32R2; |
| 14464 | break; |
| 14465 | |
| 14466 | case OPTION_MIPS32R3: |
| 14467 | file_mips_opts.isa = ISA_MIPS32R3; |
| 14468 | break; |
| 14469 | |
| 14470 | case OPTION_MIPS32R5: |
| 14471 | file_mips_opts.isa = ISA_MIPS32R5; |
| 14472 | break; |
| 14473 | |
| 14474 | case OPTION_MIPS32R6: |
| 14475 | file_mips_opts.isa = ISA_MIPS32R6; |
| 14476 | break; |
| 14477 | |
| 14478 | case OPTION_MIPS64R2: |
| 14479 | file_mips_opts.isa = ISA_MIPS64R2; |
| 14480 | break; |
| 14481 | |
| 14482 | case OPTION_MIPS64R3: |
| 14483 | file_mips_opts.isa = ISA_MIPS64R3; |
| 14484 | break; |
| 14485 | |
| 14486 | case OPTION_MIPS64R5: |
| 14487 | file_mips_opts.isa = ISA_MIPS64R5; |
| 14488 | break; |
| 14489 | |
| 14490 | case OPTION_MIPS64R6: |
| 14491 | file_mips_opts.isa = ISA_MIPS64R6; |
| 14492 | break; |
| 14493 | |
| 14494 | case OPTION_MIPS64: |
| 14495 | file_mips_opts.isa = ISA_MIPS64; |
| 14496 | break; |
| 14497 | |
| 14498 | case OPTION_MTUNE: |
| 14499 | mips_set_option_string (&mips_tune_string, arg); |
| 14500 | break; |
| 14501 | |
| 14502 | case OPTION_MARCH: |
| 14503 | mips_set_option_string (&mips_arch_string, arg); |
| 14504 | break; |
| 14505 | |
| 14506 | case OPTION_M4650: |
| 14507 | mips_set_option_string (&mips_arch_string, "4650"); |
| 14508 | mips_set_option_string (&mips_tune_string, "4650"); |
| 14509 | break; |
| 14510 | |
| 14511 | case OPTION_NO_M4650: |
| 14512 | break; |
| 14513 | |
| 14514 | case OPTION_M4010: |
| 14515 | mips_set_option_string (&mips_arch_string, "4010"); |
| 14516 | mips_set_option_string (&mips_tune_string, "4010"); |
| 14517 | break; |
| 14518 | |
| 14519 | case OPTION_NO_M4010: |
| 14520 | break; |
| 14521 | |
| 14522 | case OPTION_M4100: |
| 14523 | mips_set_option_string (&mips_arch_string, "4100"); |
| 14524 | mips_set_option_string (&mips_tune_string, "4100"); |
| 14525 | break; |
| 14526 | |
| 14527 | case OPTION_NO_M4100: |
| 14528 | break; |
| 14529 | |
| 14530 | case OPTION_M3900: |
| 14531 | mips_set_option_string (&mips_arch_string, "3900"); |
| 14532 | mips_set_option_string (&mips_tune_string, "3900"); |
| 14533 | break; |
| 14534 | |
| 14535 | case OPTION_NO_M3900: |
| 14536 | break; |
| 14537 | |
| 14538 | case OPTION_MICROMIPS: |
| 14539 | if (file_mips_opts.mips16 == 1) |
| 14540 | { |
| 14541 | as_bad (_("-mmicromips cannot be used with -mips16")); |
| 14542 | return 0; |
| 14543 | } |
| 14544 | file_mips_opts.micromips = 1; |
| 14545 | mips_no_prev_insn (); |
| 14546 | break; |
| 14547 | |
| 14548 | case OPTION_NO_MICROMIPS: |
| 14549 | file_mips_opts.micromips = 0; |
| 14550 | mips_no_prev_insn (); |
| 14551 | break; |
| 14552 | |
| 14553 | case OPTION_MIPS16: |
| 14554 | if (file_mips_opts.micromips == 1) |
| 14555 | { |
| 14556 | as_bad (_("-mips16 cannot be used with -micromips")); |
| 14557 | return 0; |
| 14558 | } |
| 14559 | file_mips_opts.mips16 = 1; |
| 14560 | mips_no_prev_insn (); |
| 14561 | break; |
| 14562 | |
| 14563 | case OPTION_NO_MIPS16: |
| 14564 | file_mips_opts.mips16 = 0; |
| 14565 | mips_no_prev_insn (); |
| 14566 | break; |
| 14567 | |
| 14568 | case OPTION_FIX_24K: |
| 14569 | mips_fix_24k = 1; |
| 14570 | break; |
| 14571 | |
| 14572 | case OPTION_NO_FIX_24K: |
| 14573 | mips_fix_24k = 0; |
| 14574 | break; |
| 14575 | |
| 14576 | case OPTION_FIX_RM7000: |
| 14577 | mips_fix_rm7000 = 1; |
| 14578 | break; |
| 14579 | |
| 14580 | case OPTION_NO_FIX_RM7000: |
| 14581 | mips_fix_rm7000 = 0; |
| 14582 | break; |
| 14583 | |
| 14584 | case OPTION_FIX_LOONGSON2F_JUMP: |
| 14585 | mips_fix_loongson2f_jump = TRUE; |
| 14586 | break; |
| 14587 | |
| 14588 | case OPTION_NO_FIX_LOONGSON2F_JUMP: |
| 14589 | mips_fix_loongson2f_jump = FALSE; |
| 14590 | break; |
| 14591 | |
| 14592 | case OPTION_FIX_LOONGSON2F_NOP: |
| 14593 | mips_fix_loongson2f_nop = TRUE; |
| 14594 | break; |
| 14595 | |
| 14596 | case OPTION_NO_FIX_LOONGSON2F_NOP: |
| 14597 | mips_fix_loongson2f_nop = FALSE; |
| 14598 | break; |
| 14599 | |
| 14600 | case OPTION_FIX_VR4120: |
| 14601 | mips_fix_vr4120 = 1; |
| 14602 | break; |
| 14603 | |
| 14604 | case OPTION_NO_FIX_VR4120: |
| 14605 | mips_fix_vr4120 = 0; |
| 14606 | break; |
| 14607 | |
| 14608 | case OPTION_FIX_VR4130: |
| 14609 | mips_fix_vr4130 = 1; |
| 14610 | break; |
| 14611 | |
| 14612 | case OPTION_NO_FIX_VR4130: |
| 14613 | mips_fix_vr4130 = 0; |
| 14614 | break; |
| 14615 | |
| 14616 | case OPTION_FIX_CN63XXP1: |
| 14617 | mips_fix_cn63xxp1 = TRUE; |
| 14618 | break; |
| 14619 | |
| 14620 | case OPTION_NO_FIX_CN63XXP1: |
| 14621 | mips_fix_cn63xxp1 = FALSE; |
| 14622 | break; |
| 14623 | |
| 14624 | case OPTION_RELAX_BRANCH: |
| 14625 | mips_relax_branch = 1; |
| 14626 | break; |
| 14627 | |
| 14628 | case OPTION_NO_RELAX_BRANCH: |
| 14629 | mips_relax_branch = 0; |
| 14630 | break; |
| 14631 | |
| 14632 | case OPTION_IGNORE_BRANCH_ISA: |
| 14633 | mips_ignore_branch_isa = TRUE; |
| 14634 | break; |
| 14635 | |
| 14636 | case OPTION_NO_IGNORE_BRANCH_ISA: |
| 14637 | mips_ignore_branch_isa = FALSE; |
| 14638 | break; |
| 14639 | |
| 14640 | case OPTION_INSN32: |
| 14641 | file_mips_opts.insn32 = TRUE; |
| 14642 | break; |
| 14643 | |
| 14644 | case OPTION_NO_INSN32: |
| 14645 | file_mips_opts.insn32 = FALSE; |
| 14646 | break; |
| 14647 | |
| 14648 | case OPTION_MSHARED: |
| 14649 | mips_in_shared = TRUE; |
| 14650 | break; |
| 14651 | |
| 14652 | case OPTION_MNO_SHARED: |
| 14653 | mips_in_shared = FALSE; |
| 14654 | break; |
| 14655 | |
| 14656 | case OPTION_MSYM32: |
| 14657 | file_mips_opts.sym32 = TRUE; |
| 14658 | break; |
| 14659 | |
| 14660 | case OPTION_MNO_SYM32: |
| 14661 | file_mips_opts.sym32 = FALSE; |
| 14662 | break; |
| 14663 | |
| 14664 | /* When generating ELF code, we permit -KPIC and -call_shared to |
| 14665 | select SVR4_PIC, and -non_shared to select no PIC. This is |
| 14666 | intended to be compatible with Irix 5. */ |
| 14667 | case OPTION_CALL_SHARED: |
| 14668 | mips_pic = SVR4_PIC; |
| 14669 | mips_abicalls = TRUE; |
| 14670 | break; |
| 14671 | |
| 14672 | case OPTION_CALL_NONPIC: |
| 14673 | mips_pic = NO_PIC; |
| 14674 | mips_abicalls = TRUE; |
| 14675 | break; |
| 14676 | |
| 14677 | case OPTION_NON_SHARED: |
| 14678 | mips_pic = NO_PIC; |
| 14679 | mips_abicalls = FALSE; |
| 14680 | break; |
| 14681 | |
| 14682 | /* The -xgot option tells the assembler to use 32 bit offsets |
| 14683 | when accessing the got in SVR4_PIC mode. It is for Irix |
| 14684 | compatibility. */ |
| 14685 | case OPTION_XGOT: |
| 14686 | mips_big_got = 1; |
| 14687 | break; |
| 14688 | |
| 14689 | case 'G': |
| 14690 | g_switch_value = atoi (arg); |
| 14691 | g_switch_seen = 1; |
| 14692 | break; |
| 14693 | |
| 14694 | /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 |
| 14695 | and -mabi=64. */ |
| 14696 | case OPTION_32: |
| 14697 | mips_abi = O32_ABI; |
| 14698 | break; |
| 14699 | |
| 14700 | case OPTION_N32: |
| 14701 | mips_abi = N32_ABI; |
| 14702 | break; |
| 14703 | |
| 14704 | case OPTION_64: |
| 14705 | mips_abi = N64_ABI; |
| 14706 | if (!support_64bit_objects()) |
| 14707 | as_fatal (_("no compiled in support for 64 bit object file format")); |
| 14708 | break; |
| 14709 | |
| 14710 | case OPTION_GP32: |
| 14711 | file_mips_opts.gp = 32; |
| 14712 | break; |
| 14713 | |
| 14714 | case OPTION_GP64: |
| 14715 | file_mips_opts.gp = 64; |
| 14716 | break; |
| 14717 | |
| 14718 | case OPTION_FP32: |
| 14719 | file_mips_opts.fp = 32; |
| 14720 | break; |
| 14721 | |
| 14722 | case OPTION_FPXX: |
| 14723 | file_mips_opts.fp = 0; |
| 14724 | break; |
| 14725 | |
| 14726 | case OPTION_FP64: |
| 14727 | file_mips_opts.fp = 64; |
| 14728 | break; |
| 14729 | |
| 14730 | case OPTION_ODD_SPREG: |
| 14731 | file_mips_opts.oddspreg = 1; |
| 14732 | break; |
| 14733 | |
| 14734 | case OPTION_NO_ODD_SPREG: |
| 14735 | file_mips_opts.oddspreg = 0; |
| 14736 | break; |
| 14737 | |
| 14738 | case OPTION_SINGLE_FLOAT: |
| 14739 | file_mips_opts.single_float = 1; |
| 14740 | break; |
| 14741 | |
| 14742 | case OPTION_DOUBLE_FLOAT: |
| 14743 | file_mips_opts.single_float = 0; |
| 14744 | break; |
| 14745 | |
| 14746 | case OPTION_SOFT_FLOAT: |
| 14747 | file_mips_opts.soft_float = 1; |
| 14748 | break; |
| 14749 | |
| 14750 | case OPTION_HARD_FLOAT: |
| 14751 | file_mips_opts.soft_float = 0; |
| 14752 | break; |
| 14753 | |
| 14754 | case OPTION_MABI: |
| 14755 | if (strcmp (arg, "32") == 0) |
| 14756 | mips_abi = O32_ABI; |
| 14757 | else if (strcmp (arg, "o64") == 0) |
| 14758 | mips_abi = O64_ABI; |
| 14759 | else if (strcmp (arg, "n32") == 0) |
| 14760 | mips_abi = N32_ABI; |
| 14761 | else if (strcmp (arg, "64") == 0) |
| 14762 | { |
| 14763 | mips_abi = N64_ABI; |
| 14764 | if (! support_64bit_objects()) |
| 14765 | as_fatal (_("no compiled in support for 64 bit object file " |
| 14766 | "format")); |
| 14767 | } |
| 14768 | else if (strcmp (arg, "eabi") == 0) |
| 14769 | mips_abi = EABI_ABI; |
| 14770 | else |
| 14771 | { |
| 14772 | as_fatal (_("invalid abi -mabi=%s"), arg); |
| 14773 | return 0; |
| 14774 | } |
| 14775 | break; |
| 14776 | |
| 14777 | case OPTION_M7000_HILO_FIX: |
| 14778 | mips_7000_hilo_fix = TRUE; |
| 14779 | break; |
| 14780 | |
| 14781 | case OPTION_MNO_7000_HILO_FIX: |
| 14782 | mips_7000_hilo_fix = FALSE; |
| 14783 | break; |
| 14784 | |
| 14785 | case OPTION_MDEBUG: |
| 14786 | mips_flag_mdebug = TRUE; |
| 14787 | break; |
| 14788 | |
| 14789 | case OPTION_NO_MDEBUG: |
| 14790 | mips_flag_mdebug = FALSE; |
| 14791 | break; |
| 14792 | |
| 14793 | case OPTION_PDR: |
| 14794 | mips_flag_pdr = TRUE; |
| 14795 | break; |
| 14796 | |
| 14797 | case OPTION_NO_PDR: |
| 14798 | mips_flag_pdr = FALSE; |
| 14799 | break; |
| 14800 | |
| 14801 | case OPTION_MVXWORKS_PIC: |
| 14802 | mips_pic = VXWORKS_PIC; |
| 14803 | break; |
| 14804 | |
| 14805 | case OPTION_NAN: |
| 14806 | if (strcmp (arg, "2008") == 0) |
| 14807 | mips_nan2008 = 1; |
| 14808 | else if (strcmp (arg, "legacy") == 0) |
| 14809 | mips_nan2008 = 0; |
| 14810 | else |
| 14811 | { |
| 14812 | as_fatal (_("invalid NaN setting -mnan=%s"), arg); |
| 14813 | return 0; |
| 14814 | } |
| 14815 | break; |
| 14816 | |
| 14817 | default: |
| 14818 | return 0; |
| 14819 | } |
| 14820 | |
| 14821 | mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump; |
| 14822 | |
| 14823 | return 1; |
| 14824 | } |
| 14825 | \f |
| 14826 | /* Set up globals to tune for the ISA or processor described by INFO. */ |
| 14827 | |
| 14828 | static void |
| 14829 | mips_set_tune (const struct mips_cpu_info *info) |
| 14830 | { |
| 14831 | if (info != 0) |
| 14832 | mips_tune = info->cpu; |
| 14833 | } |
| 14834 | |
| 14835 | |
| 14836 | void |
| 14837 | mips_after_parse_args (void) |
| 14838 | { |
| 14839 | const struct mips_cpu_info *arch_info = 0; |
| 14840 | const struct mips_cpu_info *tune_info = 0; |
| 14841 | |
| 14842 | /* GP relative stuff not working for PE */ |
| 14843 | if (strncmp (TARGET_OS, "pe", 2) == 0) |
| 14844 | { |
| 14845 | if (g_switch_seen && g_switch_value != 0) |
| 14846 | as_bad (_("-G not supported in this configuration")); |
| 14847 | g_switch_value = 0; |
| 14848 | } |
| 14849 | |
| 14850 | if (mips_abi == NO_ABI) |
| 14851 | mips_abi = MIPS_DEFAULT_ABI; |
| 14852 | |
| 14853 | /* The following code determines the architecture. |
| 14854 | Similar code was added to GCC 3.3 (see override_options() in |
| 14855 | config/mips/mips.c). The GAS and GCC code should be kept in sync |
| 14856 | as much as possible. */ |
| 14857 | |
| 14858 | if (mips_arch_string != 0) |
| 14859 | arch_info = mips_parse_cpu ("-march", mips_arch_string); |
| 14860 | |
| 14861 | if (file_mips_opts.isa != ISA_UNKNOWN) |
| 14862 | { |
| 14863 | /* Handle -mipsN. At this point, file_mips_opts.isa contains the |
| 14864 | ISA level specified by -mipsN, while arch_info->isa contains |
| 14865 | the -march selection (if any). */ |
| 14866 | if (arch_info != 0) |
| 14867 | { |
| 14868 | /* -march takes precedence over -mipsN, since it is more descriptive. |
| 14869 | There's no harm in specifying both as long as the ISA levels |
| 14870 | are the same. */ |
| 14871 | if (file_mips_opts.isa != arch_info->isa) |
| 14872 | as_bad (_("-%s conflicts with the other architecture options," |
| 14873 | " which imply -%s"), |
| 14874 | mips_cpu_info_from_isa (file_mips_opts.isa)->name, |
| 14875 | mips_cpu_info_from_isa (arch_info->isa)->name); |
| 14876 | } |
| 14877 | else |
| 14878 | arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); |
| 14879 | } |
| 14880 | |
| 14881 | if (arch_info == 0) |
| 14882 | { |
| 14883 | arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT); |
| 14884 | gas_assert (arch_info); |
| 14885 | } |
| 14886 | |
| 14887 | if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa)) |
| 14888 | as_bad (_("-march=%s is not compatible with the selected ABI"), |
| 14889 | arch_info->name); |
| 14890 | |
| 14891 | file_mips_opts.arch = arch_info->cpu; |
| 14892 | file_mips_opts.isa = arch_info->isa; |
| 14893 | |
| 14894 | /* Set up initial mips_opts state. */ |
| 14895 | mips_opts = file_mips_opts; |
| 14896 | |
| 14897 | /* The register size inference code is now placed in |
| 14898 | file_mips_check_options. */ |
| 14899 | |
| 14900 | /* Optimize for file_mips_opts.arch, unless -mtune selects a different |
| 14901 | processor. */ |
| 14902 | if (mips_tune_string != 0) |
| 14903 | tune_info = mips_parse_cpu ("-mtune", mips_tune_string); |
| 14904 | |
| 14905 | if (tune_info == 0) |
| 14906 | mips_set_tune (arch_info); |
| 14907 | else |
| 14908 | mips_set_tune (tune_info); |
| 14909 | |
| 14910 | if (mips_flag_mdebug < 0) |
| 14911 | mips_flag_mdebug = 0; |
| 14912 | } |
| 14913 | \f |
| 14914 | void |
| 14915 | mips_init_after_args (void) |
| 14916 | { |
| 14917 | /* initialize opcodes */ |
| 14918 | bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes; |
| 14919 | mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; |
| 14920 | } |
| 14921 | |
| 14922 | long |
| 14923 | md_pcrel_from (fixS *fixP) |
| 14924 | { |
| 14925 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; |
| 14926 | switch (fixP->fx_r_type) |
| 14927 | { |
| 14928 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
| 14929 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: |
| 14930 | /* Return the address of the delay slot. */ |
| 14931 | return addr + 2; |
| 14932 | |
| 14933 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: |
| 14934 | case BFD_RELOC_MICROMIPS_JMP: |
| 14935 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
| 14936 | case BFD_RELOC_16_PCREL_S2: |
| 14937 | case BFD_RELOC_MIPS_21_PCREL_S2: |
| 14938 | case BFD_RELOC_MIPS_26_PCREL_S2: |
| 14939 | case BFD_RELOC_MIPS_JMP: |
| 14940 | /* Return the address of the delay slot. */ |
| 14941 | return addr + 4; |
| 14942 | |
| 14943 | case BFD_RELOC_MIPS_18_PCREL_S3: |
| 14944 | /* Return the aligned address of the doubleword containing |
| 14945 | the instruction. */ |
| 14946 | return addr & ~7; |
| 14947 | |
| 14948 | default: |
| 14949 | return addr; |
| 14950 | } |
| 14951 | } |
| 14952 | |
| 14953 | /* This is called before the symbol table is processed. In order to |
| 14954 | work with gcc when using mips-tfile, we must keep all local labels. |
| 14955 | However, in other cases, we want to discard them. If we were |
| 14956 | called with -g, but we didn't see any debugging information, it may |
| 14957 | mean that gcc is smuggling debugging information through to |
| 14958 | mips-tfile, in which case we must generate all local labels. */ |
| 14959 | |
| 14960 | void |
| 14961 | mips_frob_file_before_adjust (void) |
| 14962 | { |
| 14963 | #ifndef NO_ECOFF_DEBUGGING |
| 14964 | if (ECOFF_DEBUGGING |
| 14965 | && mips_debug != 0 |
| 14966 | && ! ecoff_debugging_seen) |
| 14967 | flag_keep_locals = 1; |
| 14968 | #endif |
| 14969 | } |
| 14970 | |
| 14971 | /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede |
| 14972 | the corresponding LO16 reloc. This is called before md_apply_fix and |
| 14973 | tc_gen_reloc. Unmatched relocs can only be generated by use of explicit |
| 14974 | relocation operators. |
| 14975 | |
| 14976 | For our purposes, a %lo() expression matches a %got() or %hi() |
| 14977 | expression if: |
| 14978 | |
| 14979 | (a) it refers to the same symbol; and |
| 14980 | (b) the offset applied in the %lo() expression is no lower than |
| 14981 | the offset applied in the %got() or %hi(). |
| 14982 | |
| 14983 | (b) allows us to cope with code like: |
| 14984 | |
| 14985 | lui $4,%hi(foo) |
| 14986 | lh $4,%lo(foo+2)($4) |
| 14987 | |
| 14988 | ...which is legal on RELA targets, and has a well-defined behaviour |
| 14989 | if the user knows that adding 2 to "foo" will not induce a carry to |
| 14990 | the high 16 bits. |
| 14991 | |
| 14992 | When several %lo()s match a particular %got() or %hi(), we use the |
| 14993 | following rules to distinguish them: |
| 14994 | |
| 14995 | (1) %lo()s with smaller offsets are a better match than %lo()s with |
| 14996 | higher offsets. |
| 14997 | |
| 14998 | (2) %lo()s with no matching %got() or %hi() are better than those |
| 14999 | that already have a matching %got() or %hi(). |
| 15000 | |
| 15001 | (3) later %lo()s are better than earlier %lo()s. |
| 15002 | |
| 15003 | These rules are applied in order. |
| 15004 | |
| 15005 | (1) means, among other things, that %lo()s with identical offsets are |
| 15006 | chosen if they exist. |
| 15007 | |
| 15008 | (2) means that we won't associate several high-part relocations with |
| 15009 | the same low-part relocation unless there's no alternative. Having |
| 15010 | several high parts for the same low part is a GNU extension; this rule |
| 15011 | allows careful users to avoid it. |
| 15012 | |
| 15013 | (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order, |
| 15014 | with the last high-part relocation being at the front of the list. |
| 15015 | It therefore makes sense to choose the last matching low-part |
| 15016 | relocation, all other things being equal. It's also easier |
| 15017 | to code that way. */ |
| 15018 | |
| 15019 | void |
| 15020 | mips_frob_file (void) |
| 15021 | { |
| 15022 | struct mips_hi_fixup *l; |
| 15023 | bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED; |
| 15024 | |
| 15025 | for (l = mips_hi_fixup_list; l != NULL; l = l->next) |
| 15026 | { |
| 15027 | segment_info_type *seginfo; |
| 15028 | bfd_boolean matched_lo_p; |
| 15029 | fixS **hi_pos, **lo_pos, **pos; |
| 15030 | |
| 15031 | gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type)); |
| 15032 | |
| 15033 | /* If a GOT16 relocation turns out to be against a global symbol, |
| 15034 | there isn't supposed to be a matching LO. Ignore %gots against |
| 15035 | constants; we'll report an error for those later. */ |
| 15036 | if (got16_reloc_p (l->fixp->fx_r_type) |
| 15037 | && !(l->fixp->fx_addsy |
| 15038 | && pic_need_relax (l->fixp->fx_addsy))) |
| 15039 | continue; |
| 15040 | |
| 15041 | /* Check quickly whether the next fixup happens to be a matching %lo. */ |
| 15042 | if (fixup_has_matching_lo_p (l->fixp)) |
| 15043 | continue; |
| 15044 | |
| 15045 | seginfo = seg_info (l->seg); |
| 15046 | |
| 15047 | /* Set HI_POS to the position of this relocation in the chain. |
| 15048 | Set LO_POS to the position of the chosen low-part relocation. |
| 15049 | MATCHED_LO_P is true on entry to the loop if *POS is a low-part |
| 15050 | relocation that matches an immediately-preceding high-part |
| 15051 | relocation. */ |
| 15052 | hi_pos = NULL; |
| 15053 | lo_pos = NULL; |
| 15054 | matched_lo_p = FALSE; |
| 15055 | looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type); |
| 15056 | |
| 15057 | for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next) |
| 15058 | { |
| 15059 | if (*pos == l->fixp) |
| 15060 | hi_pos = pos; |
| 15061 | |
| 15062 | if ((*pos)->fx_r_type == looking_for_rtype |
| 15063 | && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy) |
| 15064 | && (*pos)->fx_offset >= l->fixp->fx_offset |
| 15065 | && (lo_pos == NULL |
| 15066 | || (*pos)->fx_offset < (*lo_pos)->fx_offset |
| 15067 | || (!matched_lo_p |
| 15068 | && (*pos)->fx_offset == (*lo_pos)->fx_offset))) |
| 15069 | lo_pos = pos; |
| 15070 | |
| 15071 | matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type) |
| 15072 | && fixup_has_matching_lo_p (*pos)); |
| 15073 | } |
| 15074 | |
| 15075 | /* If we found a match, remove the high-part relocation from its |
| 15076 | current position and insert it before the low-part relocation. |
| 15077 | Make the offsets match so that fixup_has_matching_lo_p() |
| 15078 | will return true. |
| 15079 | |
| 15080 | We don't warn about unmatched high-part relocations since some |
| 15081 | versions of gcc have been known to emit dead "lui ...%hi(...)" |
| 15082 | instructions. */ |
| 15083 | if (lo_pos != NULL) |
| 15084 | { |
| 15085 | l->fixp->fx_offset = (*lo_pos)->fx_offset; |
| 15086 | if (l->fixp->fx_next != *lo_pos) |
| 15087 | { |
| 15088 | *hi_pos = l->fixp->fx_next; |
| 15089 | l->fixp->fx_next = *lo_pos; |
| 15090 | *lo_pos = l->fixp; |
| 15091 | } |
| 15092 | } |
| 15093 | } |
| 15094 | } |
| 15095 | |
| 15096 | int |
| 15097 | mips_force_relocation (fixS *fixp) |
| 15098 | { |
| 15099 | if (generic_force_reloc (fixp)) |
| 15100 | return 1; |
| 15101 | |
| 15102 | /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation, |
| 15103 | so that the linker relaxation can update targets. */ |
| 15104 | if (fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
| 15105 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 |
| 15106 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) |
| 15107 | return 1; |
| 15108 | |
| 15109 | /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2 |
| 15110 | and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and |
| 15111 | microMIPS symbols so that we can do cross-mode branch diagnostics |
| 15112 | and BAL to JALX conversion by the linker. */ |
| 15113 | if ((fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
| 15114 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
| 15115 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2) |
| 15116 | && fixp->fx_addsy |
| 15117 | && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp->fx_addsy))) |
| 15118 | return 1; |
| 15119 | |
| 15120 | /* We want all PC-relative relocations to be kept for R6 relaxation. */ |
| 15121 | if (ISA_IS_R6 (file_mips_opts.isa) |
| 15122 | && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
| 15123 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
| 15124 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 |
| 15125 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 |
| 15126 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 |
| 15127 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL |
| 15128 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) |
| 15129 | return 1; |
| 15130 | |
| 15131 | return 0; |
| 15132 | } |
| 15133 | |
| 15134 | /* Implement TC_FORCE_RELOCATION_ABS. */ |
| 15135 | |
| 15136 | bfd_boolean |
| 15137 | mips_force_relocation_abs (fixS *fixp) |
| 15138 | { |
| 15139 | if (generic_force_reloc (fixp)) |
| 15140 | return TRUE; |
| 15141 | |
| 15142 | /* These relocations do not have enough bits in the in-place addend |
| 15143 | to hold an arbitrary absolute section's offset. */ |
| 15144 | if (HAVE_IN_PLACE_ADDENDS && limited_pcrel_reloc_p (fixp->fx_r_type)) |
| 15145 | return TRUE; |
| 15146 | |
| 15147 | return FALSE; |
| 15148 | } |
| 15149 | |
| 15150 | /* Read the instruction associated with RELOC from BUF. */ |
| 15151 | |
| 15152 | static unsigned int |
| 15153 | read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) |
| 15154 | { |
| 15155 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) |
| 15156 | return read_compressed_insn (buf, 4); |
| 15157 | else |
| 15158 | return read_insn (buf); |
| 15159 | } |
| 15160 | |
| 15161 | /* Write instruction INSN to BUF, given that it has been relocated |
| 15162 | by RELOC. */ |
| 15163 | |
| 15164 | static void |
| 15165 | write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, |
| 15166 | unsigned long insn) |
| 15167 | { |
| 15168 | if (mips16_reloc_p (reloc) || micromips_reloc_p (reloc)) |
| 15169 | write_compressed_insn (buf, insn, 4); |
| 15170 | else |
| 15171 | write_insn (buf, insn); |
| 15172 | } |
| 15173 | |
| 15174 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
| 15175 | to a symbol in another ISA mode, which cannot be converted to JALX. */ |
| 15176 | |
| 15177 | static bfd_boolean |
| 15178 | fix_bad_cross_mode_jump_p (fixS *fixP) |
| 15179 | { |
| 15180 | unsigned long opcode; |
| 15181 | int other; |
| 15182 | char *buf; |
| 15183 | |
| 15184 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
| 15185 | return FALSE; |
| 15186 | |
| 15187 | other = S_GET_OTHER (fixP->fx_addsy); |
| 15188 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
| 15189 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; |
| 15190 | switch (fixP->fx_r_type) |
| 15191 | { |
| 15192 | case BFD_RELOC_MIPS_JMP: |
| 15193 | return opcode != 0x1d && opcode != 0x03 && ELF_ST_IS_COMPRESSED (other); |
| 15194 | case BFD_RELOC_MICROMIPS_JMP: |
| 15195 | return opcode != 0x3c && opcode != 0x3d && !ELF_ST_IS_MICROMIPS (other); |
| 15196 | default: |
| 15197 | return FALSE; |
| 15198 | } |
| 15199 | } |
| 15200 | |
| 15201 | /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX |
| 15202 | jump to a symbol in the same ISA mode. */ |
| 15203 | |
| 15204 | static bfd_boolean |
| 15205 | fix_bad_same_mode_jalx_p (fixS *fixP) |
| 15206 | { |
| 15207 | unsigned long opcode; |
| 15208 | int other; |
| 15209 | char *buf; |
| 15210 | |
| 15211 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
| 15212 | return FALSE; |
| 15213 | |
| 15214 | other = S_GET_OTHER (fixP->fx_addsy); |
| 15215 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
| 15216 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 26; |
| 15217 | switch (fixP->fx_r_type) |
| 15218 | { |
| 15219 | case BFD_RELOC_MIPS_JMP: |
| 15220 | return opcode == 0x1d && !ELF_ST_IS_COMPRESSED (other); |
| 15221 | case BFD_RELOC_MIPS16_JMP: |
| 15222 | return opcode == 0x07 && ELF_ST_IS_COMPRESSED (other); |
| 15223 | case BFD_RELOC_MICROMIPS_JMP: |
| 15224 | return opcode == 0x3c && ELF_ST_IS_COMPRESSED (other); |
| 15225 | default: |
| 15226 | return FALSE; |
| 15227 | } |
| 15228 | } |
| 15229 | |
| 15230 | /* Return TRUE if the instruction pointed to by FIXP is an invalid jump |
| 15231 | to a symbol whose value plus addend is not aligned according to the |
| 15232 | ultimate (after linker relaxation) jump instruction's immediate field |
| 15233 | requirement, either to (1 << SHIFT), or, for jumps from microMIPS to |
| 15234 | regular MIPS code, to (1 << 2). */ |
| 15235 | |
| 15236 | static bfd_boolean |
| 15237 | fix_bad_misaligned_jump_p (fixS *fixP, int shift) |
| 15238 | { |
| 15239 | bfd_boolean micro_to_mips_p; |
| 15240 | valueT val; |
| 15241 | int other; |
| 15242 | |
| 15243 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
| 15244 | return FALSE; |
| 15245 | |
| 15246 | other = S_GET_OTHER (fixP->fx_addsy); |
| 15247 | val = S_GET_VALUE (fixP->fx_addsy) | ELF_ST_IS_COMPRESSED (other); |
| 15248 | val += fixP->fx_offset; |
| 15249 | micro_to_mips_p = (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP |
| 15250 | && !ELF_ST_IS_MICROMIPS (other)); |
| 15251 | return ((val & ((1 << (micro_to_mips_p ? 2 : shift)) - 1)) |
| 15252 | != ELF_ST_IS_COMPRESSED (other)); |
| 15253 | } |
| 15254 | |
| 15255 | /* Return TRUE if the instruction pointed to by FIXP is an invalid branch |
| 15256 | to a symbol whose annotation indicates another ISA mode. For absolute |
| 15257 | symbols check the ISA bit instead. |
| 15258 | |
| 15259 | We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS |
| 15260 | symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular |
| 15261 | MIPS symbols and associated with BAL instructions as these instructions |
| 15262 | may be be converted to JALX by the linker. */ |
| 15263 | |
| 15264 | static bfd_boolean |
| 15265 | fix_bad_cross_mode_branch_p (fixS *fixP) |
| 15266 | { |
| 15267 | bfd_boolean absolute_p; |
| 15268 | unsigned long opcode; |
| 15269 | asection *symsec; |
| 15270 | valueT val; |
| 15271 | int other; |
| 15272 | char *buf; |
| 15273 | |
| 15274 | if (mips_ignore_branch_isa) |
| 15275 | return FALSE; |
| 15276 | |
| 15277 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
| 15278 | return FALSE; |
| 15279 | |
| 15280 | symsec = S_GET_SEGMENT (fixP->fx_addsy); |
| 15281 | absolute_p = bfd_is_abs_section (symsec); |
| 15282 | |
| 15283 | val = S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset; |
| 15284 | other = S_GET_OTHER (fixP->fx_addsy); |
| 15285 | |
| 15286 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
| 15287 | opcode = read_reloc_insn (buf, fixP->fx_r_type) >> 16; |
| 15288 | switch (fixP->fx_r_type) |
| 15289 | { |
| 15290 | case BFD_RELOC_16_PCREL_S2: |
| 15291 | return ((absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other)) |
| 15292 | && opcode != 0x0411); |
| 15293 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: |
| 15294 | return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other)) |
| 15295 | && opcode != 0x4060); |
| 15296 | case BFD_RELOC_MIPS_21_PCREL_S2: |
| 15297 | case BFD_RELOC_MIPS_26_PCREL_S2: |
| 15298 | return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other); |
| 15299 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
| 15300 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MIPS16 (other); |
| 15301 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
| 15302 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: |
| 15303 | return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other); |
| 15304 | default: |
| 15305 | abort (); |
| 15306 | } |
| 15307 | } |
| 15308 | |
| 15309 | /* Return TRUE if the symbol plus addend associated with a regular MIPS |
| 15310 | branch instruction pointed to by FIXP is not aligned according to the |
| 15311 | branch instruction's immediate field requirement. We need the addend |
| 15312 | to preserve the ISA bit and also the sum must not have bit 2 set. We |
| 15313 | must explicitly OR in the ISA bit from symbol annotation as the bit |
| 15314 | won't be set in the symbol's value then. */ |
| 15315 | |
| 15316 | static bfd_boolean |
| 15317 | fix_bad_misaligned_branch_p (fixS *fixP) |
| 15318 | { |
| 15319 | bfd_boolean absolute_p; |
| 15320 | asection *symsec; |
| 15321 | valueT isa_bit; |
| 15322 | valueT val; |
| 15323 | valueT off; |
| 15324 | int other; |
| 15325 | |
| 15326 | if (!fixP->fx_addsy || S_FORCE_RELOC (fixP->fx_addsy, TRUE)) |
| 15327 | return FALSE; |
| 15328 | |
| 15329 | symsec = S_GET_SEGMENT (fixP->fx_addsy); |
| 15330 | absolute_p = bfd_is_abs_section (symsec); |
| 15331 | |
| 15332 | val = S_GET_VALUE (fixP->fx_addsy); |
| 15333 | other = S_GET_OTHER (fixP->fx_addsy); |
| 15334 | off = fixP->fx_offset; |
| 15335 | |
| 15336 | isa_bit = absolute_p ? (val + off) & 1 : ELF_ST_IS_COMPRESSED (other); |
| 15337 | val |= ELF_ST_IS_COMPRESSED (other); |
| 15338 | val += off; |
| 15339 | return (val & 0x3) != isa_bit; |
| 15340 | } |
| 15341 | |
| 15342 | /* Make the necessary checks on a regular MIPS branch pointed to by FIXP |
| 15343 | and its calculated value VAL. */ |
| 15344 | |
| 15345 | static void |
| 15346 | fix_validate_branch (fixS *fixP, valueT val) |
| 15347 | { |
| 15348 | if (fixP->fx_done && (val & 0x3) != 0) |
| 15349 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15350 | _("branch to misaligned address (0x%lx)"), |
| 15351 | (long) (val + md_pcrel_from (fixP))); |
| 15352 | else if (fix_bad_cross_mode_branch_p (fixP)) |
| 15353 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15354 | _("branch to a symbol in another ISA mode")); |
| 15355 | else if (fix_bad_misaligned_branch_p (fixP)) |
| 15356 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15357 | _("branch to misaligned address (0x%lx)"), |
| 15358 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); |
| 15359 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x3) != 0) |
| 15360 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15361 | _("cannot encode misaligned addend " |
| 15362 | "in the relocatable field (0x%lx)"), |
| 15363 | (long) fixP->fx_offset); |
| 15364 | } |
| 15365 | |
| 15366 | /* Apply a fixup to the object file. */ |
| 15367 | |
| 15368 | void |
| 15369 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
| 15370 | { |
| 15371 | char *buf; |
| 15372 | unsigned long insn; |
| 15373 | reloc_howto_type *howto; |
| 15374 | |
| 15375 | if (fixP->fx_pcrel) |
| 15376 | switch (fixP->fx_r_type) |
| 15377 | { |
| 15378 | case BFD_RELOC_16_PCREL_S2: |
| 15379 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
| 15380 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
| 15381 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: |
| 15382 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: |
| 15383 | case BFD_RELOC_32_PCREL: |
| 15384 | case BFD_RELOC_MIPS_21_PCREL_S2: |
| 15385 | case BFD_RELOC_MIPS_26_PCREL_S2: |
| 15386 | case BFD_RELOC_MIPS_18_PCREL_S3: |
| 15387 | case BFD_RELOC_MIPS_19_PCREL_S2: |
| 15388 | case BFD_RELOC_HI16_S_PCREL: |
| 15389 | case BFD_RELOC_LO16_PCREL: |
| 15390 | break; |
| 15391 | |
| 15392 | case BFD_RELOC_32: |
| 15393 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
| 15394 | break; |
| 15395 | |
| 15396 | default: |
| 15397 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15398 | _("PC-relative reference to a different section")); |
| 15399 | break; |
| 15400 | } |
| 15401 | |
| 15402 | /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations |
| 15403 | that have no MIPS ELF equivalent. */ |
| 15404 | if (fixP->fx_r_type != BFD_RELOC_8) |
| 15405 | { |
| 15406 | howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); |
| 15407 | if (!howto) |
| 15408 | return; |
| 15409 | } |
| 15410 | |
| 15411 | gas_assert (fixP->fx_size == 2 |
| 15412 | || fixP->fx_size == 4 |
| 15413 | || fixP->fx_r_type == BFD_RELOC_8 |
| 15414 | || fixP->fx_r_type == BFD_RELOC_16 |
| 15415 | || fixP->fx_r_type == BFD_RELOC_64 |
| 15416 | || fixP->fx_r_type == BFD_RELOC_CTOR |
| 15417 | || fixP->fx_r_type == BFD_RELOC_MIPS_SUB |
| 15418 | || fixP->fx_r_type == BFD_RELOC_MICROMIPS_SUB |
| 15419 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 15420 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY |
| 15421 | || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64 |
| 15422 | || fixP->fx_r_type == BFD_RELOC_NONE); |
| 15423 | |
| 15424 | buf = fixP->fx_frag->fr_literal + fixP->fx_where; |
| 15425 | |
| 15426 | /* Don't treat parts of a composite relocation as done. There are two |
| 15427 | reasons for this: |
| 15428 | |
| 15429 | (1) The second and third parts will be against 0 (RSS_UNDEF) but |
| 15430 | should nevertheless be emitted if the first part is. |
| 15431 | |
| 15432 | (2) In normal usage, composite relocations are never assembly-time |
| 15433 | constants. The easiest way of dealing with the pathological |
| 15434 | exceptions is to generate a relocation against STN_UNDEF and |
| 15435 | leave everything up to the linker. */ |
| 15436 | if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) |
| 15437 | fixP->fx_done = 1; |
| 15438 | |
| 15439 | switch (fixP->fx_r_type) |
| 15440 | { |
| 15441 | case BFD_RELOC_MIPS_TLS_GD: |
| 15442 | case BFD_RELOC_MIPS_TLS_LDM: |
| 15443 | case BFD_RELOC_MIPS_TLS_DTPREL32: |
| 15444 | case BFD_RELOC_MIPS_TLS_DTPREL64: |
| 15445 | case BFD_RELOC_MIPS_TLS_DTPREL_HI16: |
| 15446 | case BFD_RELOC_MIPS_TLS_DTPREL_LO16: |
| 15447 | case BFD_RELOC_MIPS_TLS_GOTTPREL: |
| 15448 | case BFD_RELOC_MIPS_TLS_TPREL32: |
| 15449 | case BFD_RELOC_MIPS_TLS_TPREL64: |
| 15450 | case BFD_RELOC_MIPS_TLS_TPREL_HI16: |
| 15451 | case BFD_RELOC_MIPS_TLS_TPREL_LO16: |
| 15452 | case BFD_RELOC_MICROMIPS_TLS_GD: |
| 15453 | case BFD_RELOC_MICROMIPS_TLS_LDM: |
| 15454 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16: |
| 15455 | case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16: |
| 15456 | case BFD_RELOC_MICROMIPS_TLS_GOTTPREL: |
| 15457 | case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16: |
| 15458 | case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16: |
| 15459 | case BFD_RELOC_MIPS16_TLS_GD: |
| 15460 | case BFD_RELOC_MIPS16_TLS_LDM: |
| 15461 | case BFD_RELOC_MIPS16_TLS_DTPREL_HI16: |
| 15462 | case BFD_RELOC_MIPS16_TLS_DTPREL_LO16: |
| 15463 | case BFD_RELOC_MIPS16_TLS_GOTTPREL: |
| 15464 | case BFD_RELOC_MIPS16_TLS_TPREL_HI16: |
| 15465 | case BFD_RELOC_MIPS16_TLS_TPREL_LO16: |
| 15466 | if (fixP->fx_addsy) |
| 15467 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
| 15468 | else |
| 15469 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15470 | _("TLS relocation against a constant")); |
| 15471 | break; |
| 15472 | |
| 15473 | case BFD_RELOC_MIPS_JMP: |
| 15474 | case BFD_RELOC_MIPS16_JMP: |
| 15475 | case BFD_RELOC_MICROMIPS_JMP: |
| 15476 | { |
| 15477 | int shift; |
| 15478 | |
| 15479 | gas_assert (!fixP->fx_done); |
| 15480 | |
| 15481 | /* Shift is 2, unusually, for microMIPS JALX. */ |
| 15482 | if (fixP->fx_r_type == BFD_RELOC_MICROMIPS_JMP |
| 15483 | && (read_compressed_insn (buf, 4) >> 26) != 0x3c) |
| 15484 | shift = 1; |
| 15485 | else |
| 15486 | shift = 2; |
| 15487 | |
| 15488 | if (fix_bad_cross_mode_jump_p (fixP)) |
| 15489 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15490 | _("jump to a symbol in another ISA mode")); |
| 15491 | else if (fix_bad_same_mode_jalx_p (fixP)) |
| 15492 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15493 | _("JALX to a symbol in the same ISA mode")); |
| 15494 | else if (fix_bad_misaligned_jump_p (fixP, shift)) |
| 15495 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15496 | _("jump to misaligned address (0x%lx)"), |
| 15497 | (long) (S_GET_VALUE (fixP->fx_addsy) |
| 15498 | + fixP->fx_offset)); |
| 15499 | else if (HAVE_IN_PLACE_ADDENDS |
| 15500 | && (fixP->fx_offset & ((1 << shift) - 1)) != 0) |
| 15501 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15502 | _("cannot encode misaligned addend " |
| 15503 | "in the relocatable field (0x%lx)"), |
| 15504 | (long) fixP->fx_offset); |
| 15505 | } |
| 15506 | /* Fall through. */ |
| 15507 | |
| 15508 | case BFD_RELOC_MIPS_SHIFT5: |
| 15509 | case BFD_RELOC_MIPS_SHIFT6: |
| 15510 | case BFD_RELOC_MIPS_GOT_DISP: |
| 15511 | case BFD_RELOC_MIPS_GOT_PAGE: |
| 15512 | case BFD_RELOC_MIPS_GOT_OFST: |
| 15513 | case BFD_RELOC_MIPS_SUB: |
| 15514 | case BFD_RELOC_MIPS_INSERT_A: |
| 15515 | case BFD_RELOC_MIPS_INSERT_B: |
| 15516 | case BFD_RELOC_MIPS_DELETE: |
| 15517 | case BFD_RELOC_MIPS_HIGHEST: |
| 15518 | case BFD_RELOC_MIPS_HIGHER: |
| 15519 | case BFD_RELOC_MIPS_SCN_DISP: |
| 15520 | case BFD_RELOC_MIPS_REL16: |
| 15521 | case BFD_RELOC_MIPS_RELGOT: |
| 15522 | case BFD_RELOC_MIPS_JALR: |
| 15523 | case BFD_RELOC_HI16: |
| 15524 | case BFD_RELOC_HI16_S: |
| 15525 | case BFD_RELOC_LO16: |
| 15526 | case BFD_RELOC_GPREL16: |
| 15527 | case BFD_RELOC_MIPS_LITERAL: |
| 15528 | case BFD_RELOC_MIPS_CALL16: |
| 15529 | case BFD_RELOC_MIPS_GOT16: |
| 15530 | case BFD_RELOC_GPREL32: |
| 15531 | case BFD_RELOC_MIPS_GOT_HI16: |
| 15532 | case BFD_RELOC_MIPS_GOT_LO16: |
| 15533 | case BFD_RELOC_MIPS_CALL_HI16: |
| 15534 | case BFD_RELOC_MIPS_CALL_LO16: |
| 15535 | case BFD_RELOC_HI16_S_PCREL: |
| 15536 | case BFD_RELOC_LO16_PCREL: |
| 15537 | case BFD_RELOC_MIPS16_GPREL: |
| 15538 | case BFD_RELOC_MIPS16_GOT16: |
| 15539 | case BFD_RELOC_MIPS16_CALL16: |
| 15540 | case BFD_RELOC_MIPS16_HI16: |
| 15541 | case BFD_RELOC_MIPS16_HI16_S: |
| 15542 | case BFD_RELOC_MIPS16_LO16: |
| 15543 | case BFD_RELOC_MICROMIPS_GOT_DISP: |
| 15544 | case BFD_RELOC_MICROMIPS_GOT_PAGE: |
| 15545 | case BFD_RELOC_MICROMIPS_GOT_OFST: |
| 15546 | case BFD_RELOC_MICROMIPS_SUB: |
| 15547 | case BFD_RELOC_MICROMIPS_HIGHEST: |
| 15548 | case BFD_RELOC_MICROMIPS_HIGHER: |
| 15549 | case BFD_RELOC_MICROMIPS_SCN_DISP: |
| 15550 | case BFD_RELOC_MICROMIPS_JALR: |
| 15551 | case BFD_RELOC_MICROMIPS_HI16: |
| 15552 | case BFD_RELOC_MICROMIPS_HI16_S: |
| 15553 | case BFD_RELOC_MICROMIPS_LO16: |
| 15554 | case BFD_RELOC_MICROMIPS_GPREL16: |
| 15555 | case BFD_RELOC_MICROMIPS_LITERAL: |
| 15556 | case BFD_RELOC_MICROMIPS_CALL16: |
| 15557 | case BFD_RELOC_MICROMIPS_GOT16: |
| 15558 | case BFD_RELOC_MICROMIPS_GOT_HI16: |
| 15559 | case BFD_RELOC_MICROMIPS_GOT_LO16: |
| 15560 | case BFD_RELOC_MICROMIPS_CALL_HI16: |
| 15561 | case BFD_RELOC_MICROMIPS_CALL_LO16: |
| 15562 | case BFD_RELOC_MIPS_EH: |
| 15563 | if (fixP->fx_done) |
| 15564 | { |
| 15565 | offsetT value; |
| 15566 | |
| 15567 | if (calculate_reloc (fixP->fx_r_type, *valP, &value)) |
| 15568 | { |
| 15569 | insn = read_reloc_insn (buf, fixP->fx_r_type); |
| 15570 | if (mips16_reloc_p (fixP->fx_r_type)) |
| 15571 | insn |= mips16_immed_extend (value, 16); |
| 15572 | else |
| 15573 | insn |= (value & 0xffff); |
| 15574 | write_reloc_insn (buf, fixP->fx_r_type, insn); |
| 15575 | } |
| 15576 | else |
| 15577 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15578 | _("unsupported constant in relocation")); |
| 15579 | } |
| 15580 | break; |
| 15581 | |
| 15582 | case BFD_RELOC_64: |
| 15583 | /* This is handled like BFD_RELOC_32, but we output a sign |
| 15584 | extended value if we are only 32 bits. */ |
| 15585 | if (fixP->fx_done) |
| 15586 | { |
| 15587 | if (8 <= sizeof (valueT)) |
| 15588 | md_number_to_chars (buf, *valP, 8); |
| 15589 | else |
| 15590 | { |
| 15591 | valueT hiv; |
| 15592 | |
| 15593 | if ((*valP & 0x80000000) != 0) |
| 15594 | hiv = 0xffffffff; |
| 15595 | else |
| 15596 | hiv = 0; |
| 15597 | md_number_to_chars (buf + (target_big_endian ? 4 : 0), *valP, 4); |
| 15598 | md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); |
| 15599 | } |
| 15600 | } |
| 15601 | break; |
| 15602 | |
| 15603 | case BFD_RELOC_RVA: |
| 15604 | case BFD_RELOC_32: |
| 15605 | case BFD_RELOC_32_PCREL: |
| 15606 | case BFD_RELOC_16: |
| 15607 | case BFD_RELOC_8: |
| 15608 | /* If we are deleting this reloc entry, we must fill in the |
| 15609 | value now. This can happen if we have a .word which is not |
| 15610 | resolved when it appears but is later defined. */ |
| 15611 | if (fixP->fx_done) |
| 15612 | md_number_to_chars (buf, *valP, fixP->fx_size); |
| 15613 | break; |
| 15614 | |
| 15615 | case BFD_RELOC_MIPS_21_PCREL_S2: |
| 15616 | fix_validate_branch (fixP, *valP); |
| 15617 | if (!fixP->fx_done) |
| 15618 | break; |
| 15619 | |
| 15620 | if (*valP + 0x400000 <= 0x7fffff) |
| 15621 | { |
| 15622 | insn = read_insn (buf); |
| 15623 | insn |= (*valP >> 2) & 0x1fffff; |
| 15624 | write_insn (buf, insn); |
| 15625 | } |
| 15626 | else |
| 15627 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15628 | _("branch out of range")); |
| 15629 | break; |
| 15630 | |
| 15631 | case BFD_RELOC_MIPS_26_PCREL_S2: |
| 15632 | fix_validate_branch (fixP, *valP); |
| 15633 | if (!fixP->fx_done) |
| 15634 | break; |
| 15635 | |
| 15636 | if (*valP + 0x8000000 <= 0xfffffff) |
| 15637 | { |
| 15638 | insn = read_insn (buf); |
| 15639 | insn |= (*valP >> 2) & 0x3ffffff; |
| 15640 | write_insn (buf, insn); |
| 15641 | } |
| 15642 | else |
| 15643 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15644 | _("branch out of range")); |
| 15645 | break; |
| 15646 | |
| 15647 | case BFD_RELOC_MIPS_18_PCREL_S3: |
| 15648 | if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0) |
| 15649 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15650 | _("PC-relative access using misaligned symbol (%lx)"), |
| 15651 | (long) S_GET_VALUE (fixP->fx_addsy)); |
| 15652 | if ((fixP->fx_offset & 0x7) != 0) |
| 15653 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15654 | _("PC-relative access using misaligned offset (%lx)"), |
| 15655 | (long) fixP->fx_offset); |
| 15656 | if (!fixP->fx_done) |
| 15657 | break; |
| 15658 | |
| 15659 | if (*valP + 0x100000 <= 0x1fffff) |
| 15660 | { |
| 15661 | insn = read_insn (buf); |
| 15662 | insn |= (*valP >> 3) & 0x3ffff; |
| 15663 | write_insn (buf, insn); |
| 15664 | } |
| 15665 | else |
| 15666 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15667 | _("PC-relative access out of range")); |
| 15668 | break; |
| 15669 | |
| 15670 | case BFD_RELOC_MIPS_19_PCREL_S2: |
| 15671 | if ((*valP & 0x3) != 0) |
| 15672 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15673 | _("PC-relative access to misaligned address (%lx)"), |
| 15674 | (long) *valP); |
| 15675 | if (!fixP->fx_done) |
| 15676 | break; |
| 15677 | |
| 15678 | if (*valP + 0x100000 <= 0x1fffff) |
| 15679 | { |
| 15680 | insn = read_insn (buf); |
| 15681 | insn |= (*valP >> 2) & 0x7ffff; |
| 15682 | write_insn (buf, insn); |
| 15683 | } |
| 15684 | else |
| 15685 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15686 | _("PC-relative access out of range")); |
| 15687 | break; |
| 15688 | |
| 15689 | case BFD_RELOC_16_PCREL_S2: |
| 15690 | fix_validate_branch (fixP, *valP); |
| 15691 | |
| 15692 | /* We need to save the bits in the instruction since fixup_segment() |
| 15693 | might be deleting the relocation entry (i.e., a branch within |
| 15694 | the current segment). */ |
| 15695 | if (! fixP->fx_done) |
| 15696 | break; |
| 15697 | |
| 15698 | /* Update old instruction data. */ |
| 15699 | insn = read_insn (buf); |
| 15700 | |
| 15701 | if (*valP + 0x20000 <= 0x3ffff) |
| 15702 | { |
| 15703 | insn |= (*valP >> 2) & 0xffff; |
| 15704 | write_insn (buf, insn); |
| 15705 | } |
| 15706 | else if (fixP->fx_tcbit2 |
| 15707 | && fixP->fx_done |
| 15708 | && fixP->fx_frag->fr_address >= text_section->vma |
| 15709 | && (fixP->fx_frag->fr_address |
| 15710 | < text_section->vma + bfd_get_section_size (text_section)) |
| 15711 | && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */ |
| 15712 | || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */ |
| 15713 | || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */ |
| 15714 | { |
| 15715 | /* The branch offset is too large. If this is an |
| 15716 | unconditional branch, and we are not generating PIC code, |
| 15717 | we can convert it to an absolute jump instruction. */ |
| 15718 | if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */ |
| 15719 | insn = 0x0c000000; /* jal */ |
| 15720 | else |
| 15721 | insn = 0x08000000; /* j */ |
| 15722 | fixP->fx_r_type = BFD_RELOC_MIPS_JMP; |
| 15723 | fixP->fx_done = 0; |
| 15724 | fixP->fx_addsy = section_symbol (text_section); |
| 15725 | *valP += md_pcrel_from (fixP); |
| 15726 | write_insn (buf, insn); |
| 15727 | } |
| 15728 | else |
| 15729 | { |
| 15730 | /* If we got here, we have branch-relaxation disabled, |
| 15731 | and there's nothing we can do to fix this instruction |
| 15732 | without turning it into a longer sequence. */ |
| 15733 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15734 | _("branch out of range")); |
| 15735 | } |
| 15736 | break; |
| 15737 | |
| 15738 | case BFD_RELOC_MIPS16_16_PCREL_S1: |
| 15739 | case BFD_RELOC_MICROMIPS_7_PCREL_S1: |
| 15740 | case BFD_RELOC_MICROMIPS_10_PCREL_S1: |
| 15741 | case BFD_RELOC_MICROMIPS_16_PCREL_S1: |
| 15742 | gas_assert (!fixP->fx_done); |
| 15743 | if (fix_bad_cross_mode_branch_p (fixP)) |
| 15744 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15745 | _("branch to a symbol in another ISA mode")); |
| 15746 | else if (fixP->fx_addsy |
| 15747 | && !S_FORCE_RELOC (fixP->fx_addsy, TRUE) |
| 15748 | && !bfd_is_abs_section (S_GET_SEGMENT (fixP->fx_addsy)) |
| 15749 | && (fixP->fx_offset & 0x1) != 0) |
| 15750 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15751 | _("branch to misaligned address (0x%lx)"), |
| 15752 | (long) (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset)); |
| 15753 | else if (HAVE_IN_PLACE_ADDENDS && (fixP->fx_offset & 0x1) != 0) |
| 15754 | as_bad_where (fixP->fx_file, fixP->fx_line, |
| 15755 | _("cannot encode misaligned addend " |
| 15756 | "in the relocatable field (0x%lx)"), |
| 15757 | (long) fixP->fx_offset); |
| 15758 | break; |
| 15759 | |
| 15760 | case BFD_RELOC_VTABLE_INHERIT: |
| 15761 | fixP->fx_done = 0; |
| 15762 | if (fixP->fx_addsy |
| 15763 | && !S_IS_DEFINED (fixP->fx_addsy) |
| 15764 | && !S_IS_WEAK (fixP->fx_addsy)) |
| 15765 | S_SET_WEAK (fixP->fx_addsy); |
| 15766 | break; |
| 15767 | |
| 15768 | case BFD_RELOC_NONE: |
| 15769 | case BFD_RELOC_VTABLE_ENTRY: |
| 15770 | fixP->fx_done = 0; |
| 15771 | break; |
| 15772 | |
| 15773 | default: |
| 15774 | abort (); |
| 15775 | } |
| 15776 | |
| 15777 | /* Remember value for tc_gen_reloc. */ |
| 15778 | fixP->fx_addnumber = *valP; |
| 15779 | } |
| 15780 | |
| 15781 | static symbolS * |
| 15782 | get_symbol (void) |
| 15783 | { |
| 15784 | int c; |
| 15785 | char *name; |
| 15786 | symbolS *p; |
| 15787 | |
| 15788 | c = get_symbol_name (&name); |
| 15789 | p = (symbolS *) symbol_find_or_make (name); |
| 15790 | (void) restore_line_pointer (c); |
| 15791 | return p; |
| 15792 | } |
| 15793 | |
| 15794 | /* Align the current frag to a given power of two. If a particular |
| 15795 | fill byte should be used, FILL points to an integer that contains |
| 15796 | that byte, otherwise FILL is null. |
| 15797 | |
| 15798 | This function used to have the comment: |
| 15799 | |
| 15800 | The MIPS assembler also automatically adjusts any preceding label. |
| 15801 | |
| 15802 | The implementation therefore applied the adjustment to a maximum of |
| 15803 | one label. However, other label adjustments are applied to batches |
| 15804 | of labels, and adjusting just one caused problems when new labels |
| 15805 | were added for the sake of debugging or unwind information. |
| 15806 | We therefore adjust all preceding labels (given as LABELS) instead. */ |
| 15807 | |
| 15808 | static void |
| 15809 | mips_align (int to, int *fill, struct insn_label_list *labels) |
| 15810 | { |
| 15811 | mips_emit_delays (); |
| 15812 | mips_record_compressed_mode (); |
| 15813 | if (fill == NULL && subseg_text_p (now_seg)) |
| 15814 | frag_align_code (to, 0); |
| 15815 | else |
| 15816 | frag_align (to, fill ? *fill : 0, 0); |
| 15817 | record_alignment (now_seg, to); |
| 15818 | mips_move_labels (labels, FALSE); |
| 15819 | } |
| 15820 | |
| 15821 | /* Align to a given power of two. .align 0 turns off the automatic |
| 15822 | alignment used by the data creating pseudo-ops. */ |
| 15823 | |
| 15824 | static void |
| 15825 | s_align (int x ATTRIBUTE_UNUSED) |
| 15826 | { |
| 15827 | int temp, fill_value, *fill_ptr; |
| 15828 | long max_alignment = 28; |
| 15829 | |
| 15830 | /* o Note that the assembler pulls down any immediately preceding label |
| 15831 | to the aligned address. |
| 15832 | o It's not documented but auto alignment is reinstated by |
| 15833 | a .align pseudo instruction. |
| 15834 | o Note also that after auto alignment is turned off the mips assembler |
| 15835 | issues an error on attempt to assemble an improperly aligned data item. |
| 15836 | We don't. */ |
| 15837 | |
| 15838 | temp = get_absolute_expression (); |
| 15839 | if (temp > max_alignment) |
| 15840 | as_bad (_("alignment too large, %d assumed"), temp = max_alignment); |
| 15841 | else if (temp < 0) |
| 15842 | { |
| 15843 | as_warn (_("alignment negative, 0 assumed")); |
| 15844 | temp = 0; |
| 15845 | } |
| 15846 | if (*input_line_pointer == ',') |
| 15847 | { |
| 15848 | ++input_line_pointer; |
| 15849 | fill_value = get_absolute_expression (); |
| 15850 | fill_ptr = &fill_value; |
| 15851 | } |
| 15852 | else |
| 15853 | fill_ptr = 0; |
| 15854 | if (temp) |
| 15855 | { |
| 15856 | segment_info_type *si = seg_info (now_seg); |
| 15857 | struct insn_label_list *l = si->label_list; |
| 15858 | /* Auto alignment should be switched on by next section change. */ |
| 15859 | auto_align = 1; |
| 15860 | mips_align (temp, fill_ptr, l); |
| 15861 | } |
| 15862 | else |
| 15863 | { |
| 15864 | auto_align = 0; |
| 15865 | } |
| 15866 | |
| 15867 | demand_empty_rest_of_line (); |
| 15868 | } |
| 15869 | |
| 15870 | static void |
| 15871 | s_change_sec (int sec) |
| 15872 | { |
| 15873 | segT seg; |
| 15874 | |
| 15875 | /* The ELF backend needs to know that we are changing sections, so |
| 15876 | that .previous works correctly. We could do something like check |
| 15877 | for an obj_section_change_hook macro, but that might be confusing |
| 15878 | as it would not be appropriate to use it in the section changing |
| 15879 | functions in read.c, since obj-elf.c intercepts those. FIXME: |
| 15880 | This should be cleaner, somehow. */ |
| 15881 | obj_elf_section_change_hook (); |
| 15882 | |
| 15883 | mips_emit_delays (); |
| 15884 | |
| 15885 | switch (sec) |
| 15886 | { |
| 15887 | case 't': |
| 15888 | s_text (0); |
| 15889 | break; |
| 15890 | case 'd': |
| 15891 | s_data (0); |
| 15892 | break; |
| 15893 | case 'b': |
| 15894 | subseg_set (bss_section, (subsegT) get_absolute_expression ()); |
| 15895 | demand_empty_rest_of_line (); |
| 15896 | break; |
| 15897 | |
| 15898 | case 'r': |
| 15899 | seg = subseg_new (RDATA_SECTION_NAME, |
| 15900 | (subsegT) get_absolute_expression ()); |
| 15901 | bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD |
| 15902 | | SEC_READONLY | SEC_RELOC |
| 15903 | | SEC_DATA)); |
| 15904 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
| 15905 | record_alignment (seg, 4); |
| 15906 | demand_empty_rest_of_line (); |
| 15907 | break; |
| 15908 | |
| 15909 | case 's': |
| 15910 | seg = subseg_new (".sdata", (subsegT) get_absolute_expression ()); |
| 15911 | bfd_set_section_flags (stdoutput, seg, |
| 15912 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); |
| 15913 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
| 15914 | record_alignment (seg, 4); |
| 15915 | demand_empty_rest_of_line (); |
| 15916 | break; |
| 15917 | |
| 15918 | case 'B': |
| 15919 | seg = subseg_new (".sbss", (subsegT) get_absolute_expression ()); |
| 15920 | bfd_set_section_flags (stdoutput, seg, SEC_ALLOC); |
| 15921 | if (strncmp (TARGET_OS, "elf", 3) != 0) |
| 15922 | record_alignment (seg, 4); |
| 15923 | demand_empty_rest_of_line (); |
| 15924 | break; |
| 15925 | } |
| 15926 | |
| 15927 | auto_align = 1; |
| 15928 | } |
| 15929 | |
| 15930 | void |
| 15931 | s_change_section (int ignore ATTRIBUTE_UNUSED) |
| 15932 | { |
| 15933 | char *saved_ilp; |
| 15934 | char *section_name; |
| 15935 | char c, endc; |
| 15936 | char next_c = 0; |
| 15937 | int section_type; |
| 15938 | int section_flag; |
| 15939 | int section_entry_size; |
| 15940 | int section_alignment; |
| 15941 | |
| 15942 | saved_ilp = input_line_pointer; |
| 15943 | endc = get_symbol_name (§ion_name); |
| 15944 | c = (endc == '"' ? input_line_pointer[1] : endc); |
| 15945 | if (c) |
| 15946 | next_c = input_line_pointer [(endc == '"' ? 2 : 1)]; |
| 15947 | |
| 15948 | /* Do we have .section Name<,"flags">? */ |
| 15949 | if (c != ',' || (c == ',' && next_c == '"')) |
| 15950 | { |
| 15951 | /* Just after name is now '\0'. */ |
| 15952 | (void) restore_line_pointer (endc); |
| 15953 | input_line_pointer = saved_ilp; |
| 15954 | obj_elf_section (ignore); |
| 15955 | return; |
| 15956 | } |
| 15957 | |
| 15958 | section_name = xstrdup (section_name); |
| 15959 | c = restore_line_pointer (endc); |
| 15960 | |
| 15961 | input_line_pointer++; |
| 15962 | |
| 15963 | /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ |
| 15964 | if (c == ',') |
| 15965 | section_type = get_absolute_expression (); |
| 15966 | else |
| 15967 | section_type = 0; |
| 15968 | |
| 15969 | if (*input_line_pointer++ == ',') |
| 15970 | section_flag = get_absolute_expression (); |
| 15971 | else |
| 15972 | section_flag = 0; |
| 15973 | |
| 15974 | if (*input_line_pointer++ == ',') |
| 15975 | section_entry_size = get_absolute_expression (); |
| 15976 | else |
| 15977 | section_entry_size = 0; |
| 15978 | |
| 15979 | if (*input_line_pointer++ == ',') |
| 15980 | section_alignment = get_absolute_expression (); |
| 15981 | else |
| 15982 | section_alignment = 0; |
| 15983 | |
| 15984 | /* FIXME: really ignore? */ |
| 15985 | (void) section_alignment; |
| 15986 | |
| 15987 | /* When using the generic form of .section (as implemented by obj-elf.c), |
| 15988 | there's no way to set the section type to SHT_MIPS_DWARF. Users have |
| 15989 | traditionally had to fall back on the more common @progbits instead. |
| 15990 | |
| 15991 | There's nothing really harmful in this, since bfd will correct |
| 15992 | SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it |
| 15993 | means that, for backwards compatibility, the special_section entries |
| 15994 | for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF. |
| 15995 | |
| 15996 | Even so, we shouldn't force users of the MIPS .section syntax to |
| 15997 | incorrectly label the sections as SHT_PROGBITS. The best compromise |
| 15998 | seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the |
| 15999 | generic type-checking code. */ |
| 16000 | if (section_type == SHT_MIPS_DWARF) |
| 16001 | section_type = SHT_PROGBITS; |
| 16002 | |
| 16003 | obj_elf_change_section (section_name, section_type, 0, section_flag, |
| 16004 | section_entry_size, 0, 0, 0); |
| 16005 | |
| 16006 | if (now_seg->name != section_name) |
| 16007 | free (section_name); |
| 16008 | } |
| 16009 | |
| 16010 | void |
| 16011 | mips_enable_auto_align (void) |
| 16012 | { |
| 16013 | auto_align = 1; |
| 16014 | } |
| 16015 | |
| 16016 | static void |
| 16017 | s_cons (int log_size) |
| 16018 | { |
| 16019 | segment_info_type *si = seg_info (now_seg); |
| 16020 | struct insn_label_list *l = si->label_list; |
| 16021 | |
| 16022 | mips_emit_delays (); |
| 16023 | if (log_size > 0 && auto_align) |
| 16024 | mips_align (log_size, 0, l); |
| 16025 | cons (1 << log_size); |
| 16026 | mips_clear_insn_labels (); |
| 16027 | } |
| 16028 | |
| 16029 | static void |
| 16030 | s_float_cons (int type) |
| 16031 | { |
| 16032 | segment_info_type *si = seg_info (now_seg); |
| 16033 | struct insn_label_list *l = si->label_list; |
| 16034 | |
| 16035 | mips_emit_delays (); |
| 16036 | |
| 16037 | if (auto_align) |
| 16038 | { |
| 16039 | if (type == 'd') |
| 16040 | mips_align (3, 0, l); |
| 16041 | else |
| 16042 | mips_align (2, 0, l); |
| 16043 | } |
| 16044 | |
| 16045 | float_cons (type); |
| 16046 | mips_clear_insn_labels (); |
| 16047 | } |
| 16048 | |
| 16049 | /* Handle .globl. We need to override it because on Irix 5 you are |
| 16050 | permitted to say |
| 16051 | .globl foo .text |
| 16052 | where foo is an undefined symbol, to mean that foo should be |
| 16053 | considered to be the address of a function. */ |
| 16054 | |
| 16055 | static void |
| 16056 | s_mips_globl (int x ATTRIBUTE_UNUSED) |
| 16057 | { |
| 16058 | char *name; |
| 16059 | int c; |
| 16060 | symbolS *symbolP; |
| 16061 | flagword flag; |
| 16062 | |
| 16063 | do |
| 16064 | { |
| 16065 | c = get_symbol_name (&name); |
| 16066 | symbolP = symbol_find_or_make (name); |
| 16067 | S_SET_EXTERNAL (symbolP); |
| 16068 | |
| 16069 | *input_line_pointer = c; |
| 16070 | SKIP_WHITESPACE_AFTER_NAME (); |
| 16071 | |
| 16072 | /* On Irix 5, every global symbol that is not explicitly labelled as |
| 16073 | being a function is apparently labelled as being an object. */ |
| 16074 | flag = BSF_OBJECT; |
| 16075 | |
| 16076 | if (!is_end_of_line[(unsigned char) *input_line_pointer] |
| 16077 | && (*input_line_pointer != ',')) |
| 16078 | { |
| 16079 | char *secname; |
| 16080 | asection *sec; |
| 16081 | |
| 16082 | c = get_symbol_name (&secname); |
| 16083 | sec = bfd_get_section_by_name (stdoutput, secname); |
| 16084 | if (sec == NULL) |
| 16085 | as_bad (_("%s: no such section"), secname); |
| 16086 | (void) restore_line_pointer (c); |
| 16087 | |
| 16088 | if (sec != NULL && (sec->flags & SEC_CODE) != 0) |
| 16089 | flag = BSF_FUNCTION; |
| 16090 | } |
| 16091 | |
| 16092 | symbol_get_bfdsym (symbolP)->flags |= flag; |
| 16093 | |
| 16094 | c = *input_line_pointer; |
| 16095 | if (c == ',') |
| 16096 | { |
| 16097 | input_line_pointer++; |
| 16098 | SKIP_WHITESPACE (); |
| 16099 | if (is_end_of_line[(unsigned char) *input_line_pointer]) |
| 16100 | c = '\n'; |
| 16101 | } |
| 16102 | } |
| 16103 | while (c == ','); |
| 16104 | |
| 16105 | demand_empty_rest_of_line (); |
| 16106 | } |
| 16107 | |
| 16108 | static void |
| 16109 | s_option (int x ATTRIBUTE_UNUSED) |
| 16110 | { |
| 16111 | char *opt; |
| 16112 | char c; |
| 16113 | |
| 16114 | c = get_symbol_name (&opt); |
| 16115 | |
| 16116 | if (*opt == 'O') |
| 16117 | { |
| 16118 | /* FIXME: What does this mean? */ |
| 16119 | } |
| 16120 | else if (strncmp (opt, "pic", 3) == 0 && ISDIGIT (opt[3]) && opt[4] == '\0') |
| 16121 | { |
| 16122 | int i; |
| 16123 | |
| 16124 | i = atoi (opt + 3); |
| 16125 | if (i != 0 && i != 2) |
| 16126 | as_bad (_(".option pic%d not supported"), i); |
| 16127 | else if (mips_pic == VXWORKS_PIC) |
| 16128 | as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i); |
| 16129 | else if (i == 0) |
| 16130 | mips_pic = NO_PIC; |
| 16131 | else if (i == 2) |
| 16132 | { |
| 16133 | mips_pic = SVR4_PIC; |
| 16134 | mips_abicalls = TRUE; |
| 16135 | } |
| 16136 | |
| 16137 | if (mips_pic == SVR4_PIC) |
| 16138 | { |
| 16139 | if (g_switch_seen && g_switch_value != 0) |
| 16140 | as_warn (_("-G may not be used with SVR4 PIC code")); |
| 16141 | g_switch_value = 0; |
| 16142 | bfd_set_gp_size (stdoutput, 0); |
| 16143 | } |
| 16144 | } |
| 16145 | else |
| 16146 | as_warn (_("unrecognized option \"%s\""), opt); |
| 16147 | |
| 16148 | (void) restore_line_pointer (c); |
| 16149 | demand_empty_rest_of_line (); |
| 16150 | } |
| 16151 | |
| 16152 | /* This structure is used to hold a stack of .set values. */ |
| 16153 | |
| 16154 | struct mips_option_stack |
| 16155 | { |
| 16156 | struct mips_option_stack *next; |
| 16157 | struct mips_set_options options; |
| 16158 | }; |
| 16159 | |
| 16160 | static struct mips_option_stack *mips_opts_stack; |
| 16161 | |
| 16162 | /* Return status for .set/.module option handling. */ |
| 16163 | |
| 16164 | enum code_option_type |
| 16165 | { |
| 16166 | /* Unrecognized option. */ |
| 16167 | OPTION_TYPE_BAD = -1, |
| 16168 | |
| 16169 | /* Ordinary option. */ |
| 16170 | OPTION_TYPE_NORMAL, |
| 16171 | |
| 16172 | /* ISA changing option. */ |
| 16173 | OPTION_TYPE_ISA |
| 16174 | }; |
| 16175 | |
| 16176 | /* Handle common .set/.module options. Return status indicating option |
| 16177 | type. */ |
| 16178 | |
| 16179 | static enum code_option_type |
| 16180 | parse_code_option (char * name) |
| 16181 | { |
| 16182 | bfd_boolean isa_set = FALSE; |
| 16183 | const struct mips_ase *ase; |
| 16184 | |
| 16185 | if (strncmp (name, "at=", 3) == 0) |
| 16186 | { |
| 16187 | char *s = name + 3; |
| 16188 | |
| 16189 | if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at)) |
| 16190 | as_bad (_("unrecognized register name `%s'"), s); |
| 16191 | } |
| 16192 | else if (strcmp (name, "at") == 0) |
| 16193 | mips_opts.at = ATREG; |
| 16194 | else if (strcmp (name, "noat") == 0) |
| 16195 | mips_opts.at = ZERO; |
| 16196 | else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) |
| 16197 | mips_opts.nomove = 0; |
| 16198 | else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) |
| 16199 | mips_opts.nomove = 1; |
| 16200 | else if (strcmp (name, "bopt") == 0) |
| 16201 | mips_opts.nobopt = 0; |
| 16202 | else if (strcmp (name, "nobopt") == 0) |
| 16203 | mips_opts.nobopt = 1; |
| 16204 | else if (strcmp (name, "gp=32") == 0) |
| 16205 | mips_opts.gp = 32; |
| 16206 | else if (strcmp (name, "gp=64") == 0) |
| 16207 | mips_opts.gp = 64; |
| 16208 | else if (strcmp (name, "fp=32") == 0) |
| 16209 | mips_opts.fp = 32; |
| 16210 | else if (strcmp (name, "fp=xx") == 0) |
| 16211 | mips_opts.fp = 0; |
| 16212 | else if (strcmp (name, "fp=64") == 0) |
| 16213 | mips_opts.fp = 64; |
| 16214 | else if (strcmp (name, "softfloat") == 0) |
| 16215 | mips_opts.soft_float = 1; |
| 16216 | else if (strcmp (name, "hardfloat") == 0) |
| 16217 | mips_opts.soft_float = 0; |
| 16218 | else if (strcmp (name, "singlefloat") == 0) |
| 16219 | mips_opts.single_float = 1; |
| 16220 | else if (strcmp (name, "doublefloat") == 0) |
| 16221 | mips_opts.single_float = 0; |
| 16222 | else if (strcmp (name, "nooddspreg") == 0) |
| 16223 | mips_opts.oddspreg = 0; |
| 16224 | else if (strcmp (name, "oddspreg") == 0) |
| 16225 | mips_opts.oddspreg = 1; |
| 16226 | else if (strcmp (name, "mips16") == 0 |
| 16227 | || strcmp (name, "MIPS-16") == 0) |
| 16228 | mips_opts.mips16 = 1; |
| 16229 | else if (strcmp (name, "nomips16") == 0 |
| 16230 | || strcmp (name, "noMIPS-16") == 0) |
| 16231 | mips_opts.mips16 = 0; |
| 16232 | else if (strcmp (name, "micromips") == 0) |
| 16233 | mips_opts.micromips = 1; |
| 16234 | else if (strcmp (name, "nomicromips") == 0) |
| 16235 | mips_opts.micromips = 0; |
| 16236 | else if (name[0] == 'n' |
| 16237 | && name[1] == 'o' |
| 16238 | && (ase = mips_lookup_ase (name + 2))) |
| 16239 | mips_set_ase (ase, &mips_opts, FALSE); |
| 16240 | else if ((ase = mips_lookup_ase (name))) |
| 16241 | mips_set_ase (ase, &mips_opts, TRUE); |
| 16242 | else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) |
| 16243 | { |
| 16244 | /* Permit the user to change the ISA and architecture on the fly. |
| 16245 | Needless to say, misuse can cause serious problems. */ |
| 16246 | if (strncmp (name, "arch=", 5) == 0) |
| 16247 | { |
| 16248 | const struct mips_cpu_info *p; |
| 16249 | |
| 16250 | p = mips_parse_cpu ("internal use", name + 5); |
| 16251 | if (!p) |
| 16252 | as_bad (_("unknown architecture %s"), name + 5); |
| 16253 | else |
| 16254 | { |
| 16255 | mips_opts.arch = p->cpu; |
| 16256 | mips_opts.isa = p->isa; |
| 16257 | isa_set = TRUE; |
| 16258 | } |
| 16259 | } |
| 16260 | else if (strncmp (name, "mips", 4) == 0) |
| 16261 | { |
| 16262 | const struct mips_cpu_info *p; |
| 16263 | |
| 16264 | p = mips_parse_cpu ("internal use", name); |
| 16265 | if (!p) |
| 16266 | as_bad (_("unknown ISA level %s"), name + 4); |
| 16267 | else |
| 16268 | { |
| 16269 | mips_opts.arch = p->cpu; |
| 16270 | mips_opts.isa = p->isa; |
| 16271 | isa_set = TRUE; |
| 16272 | } |
| 16273 | } |
| 16274 | else |
| 16275 | as_bad (_("unknown ISA or architecture %s"), name); |
| 16276 | } |
| 16277 | else if (strcmp (name, "autoextend") == 0) |
| 16278 | mips_opts.noautoextend = 0; |
| 16279 | else if (strcmp (name, "noautoextend") == 0) |
| 16280 | mips_opts.noautoextend = 1; |
| 16281 | else if (strcmp (name, "insn32") == 0) |
| 16282 | mips_opts.insn32 = TRUE; |
| 16283 | else if (strcmp (name, "noinsn32") == 0) |
| 16284 | mips_opts.insn32 = FALSE; |
| 16285 | else if (strcmp (name, "sym32") == 0) |
| 16286 | mips_opts.sym32 = TRUE; |
| 16287 | else if (strcmp (name, "nosym32") == 0) |
| 16288 | mips_opts.sym32 = FALSE; |
| 16289 | else |
| 16290 | return OPTION_TYPE_BAD; |
| 16291 | |
| 16292 | return isa_set ? OPTION_TYPE_ISA : OPTION_TYPE_NORMAL; |
| 16293 | } |
| 16294 | |
| 16295 | /* Handle the .set pseudo-op. */ |
| 16296 | |
| 16297 | static void |
| 16298 | s_mipsset (int x ATTRIBUTE_UNUSED) |
| 16299 | { |
| 16300 | enum code_option_type type = OPTION_TYPE_NORMAL; |
| 16301 | char *name = input_line_pointer, ch; |
| 16302 | |
| 16303 | file_mips_check_options (); |
| 16304 | |
| 16305 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 16306 | ++input_line_pointer; |
| 16307 | ch = *input_line_pointer; |
| 16308 | *input_line_pointer = '\0'; |
| 16309 | |
| 16310 | if (strchr (name, ',')) |
| 16311 | { |
| 16312 | /* Generic ".set" directive; use the generic handler. */ |
| 16313 | *input_line_pointer = ch; |
| 16314 | input_line_pointer = name; |
| 16315 | s_set (0); |
| 16316 | return; |
| 16317 | } |
| 16318 | |
| 16319 | if (strcmp (name, "reorder") == 0) |
| 16320 | { |
| 16321 | if (mips_opts.noreorder) |
| 16322 | end_noreorder (); |
| 16323 | } |
| 16324 | else if (strcmp (name, "noreorder") == 0) |
| 16325 | { |
| 16326 | if (!mips_opts.noreorder) |
| 16327 | start_noreorder (); |
| 16328 | } |
| 16329 | else if (strcmp (name, "macro") == 0) |
| 16330 | mips_opts.warn_about_macros = 0; |
| 16331 | else if (strcmp (name, "nomacro") == 0) |
| 16332 | { |
| 16333 | if (mips_opts.noreorder == 0) |
| 16334 | as_bad (_("`noreorder' must be set before `nomacro'")); |
| 16335 | mips_opts.warn_about_macros = 1; |
| 16336 | } |
| 16337 | else if (strcmp (name, "gp=default") == 0) |
| 16338 | mips_opts.gp = file_mips_opts.gp; |
| 16339 | else if (strcmp (name, "fp=default") == 0) |
| 16340 | mips_opts.fp = file_mips_opts.fp; |
| 16341 | else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) |
| 16342 | { |
| 16343 | mips_opts.isa = file_mips_opts.isa; |
| 16344 | mips_opts.arch = file_mips_opts.arch; |
| 16345 | mips_opts.gp = file_mips_opts.gp; |
| 16346 | mips_opts.fp = file_mips_opts.fp; |
| 16347 | } |
| 16348 | else if (strcmp (name, "push") == 0) |
| 16349 | { |
| 16350 | struct mips_option_stack *s; |
| 16351 | |
| 16352 | s = XNEW (struct mips_option_stack); |
| 16353 | s->next = mips_opts_stack; |
| 16354 | s->options = mips_opts; |
| 16355 | mips_opts_stack = s; |
| 16356 | } |
| 16357 | else if (strcmp (name, "pop") == 0) |
| 16358 | { |
| 16359 | struct mips_option_stack *s; |
| 16360 | |
| 16361 | s = mips_opts_stack; |
| 16362 | if (s == NULL) |
| 16363 | as_bad (_(".set pop with no .set push")); |
| 16364 | else |
| 16365 | { |
| 16366 | /* If we're changing the reorder mode we need to handle |
| 16367 | delay slots correctly. */ |
| 16368 | if (s->options.noreorder && ! mips_opts.noreorder) |
| 16369 | start_noreorder (); |
| 16370 | else if (! s->options.noreorder && mips_opts.noreorder) |
| 16371 | end_noreorder (); |
| 16372 | |
| 16373 | mips_opts = s->options; |
| 16374 | mips_opts_stack = s->next; |
| 16375 | free (s); |
| 16376 | } |
| 16377 | } |
| 16378 | else |
| 16379 | { |
| 16380 | type = parse_code_option (name); |
| 16381 | if (type == OPTION_TYPE_BAD) |
| 16382 | as_warn (_("tried to set unrecognized symbol: %s\n"), name); |
| 16383 | } |
| 16384 | |
| 16385 | /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp |
| 16386 | registers based on what is supported by the arch/cpu. */ |
| 16387 | if (type == OPTION_TYPE_ISA) |
| 16388 | { |
| 16389 | switch (mips_opts.isa) |
| 16390 | { |
| 16391 | case 0: |
| 16392 | break; |
| 16393 | case ISA_MIPS1: |
| 16394 | /* MIPS I cannot support FPXX. */ |
| 16395 | mips_opts.fp = 32; |
| 16396 | /* fall-through. */ |
| 16397 | case ISA_MIPS2: |
| 16398 | case ISA_MIPS32: |
| 16399 | case ISA_MIPS32R2: |
| 16400 | case ISA_MIPS32R3: |
| 16401 | case ISA_MIPS32R5: |
| 16402 | mips_opts.gp = 32; |
| 16403 | if (mips_opts.fp != 0) |
| 16404 | mips_opts.fp = 32; |
| 16405 | break; |
| 16406 | case ISA_MIPS32R6: |
| 16407 | mips_opts.gp = 32; |
| 16408 | mips_opts.fp = 64; |
| 16409 | break; |
| 16410 | case ISA_MIPS3: |
| 16411 | case ISA_MIPS4: |
| 16412 | case ISA_MIPS5: |
| 16413 | case ISA_MIPS64: |
| 16414 | case ISA_MIPS64R2: |
| 16415 | case ISA_MIPS64R3: |
| 16416 | case ISA_MIPS64R5: |
| 16417 | case ISA_MIPS64R6: |
| 16418 | mips_opts.gp = 64; |
| 16419 | if (mips_opts.fp != 0) |
| 16420 | { |
| 16421 | if (mips_opts.arch == CPU_R5900) |
| 16422 | mips_opts.fp = 32; |
| 16423 | else |
| 16424 | mips_opts.fp = 64; |
| 16425 | } |
| 16426 | break; |
| 16427 | default: |
| 16428 | as_bad (_("unknown ISA level %s"), name + 4); |
| 16429 | break; |
| 16430 | } |
| 16431 | } |
| 16432 | |
| 16433 | mips_check_options (&mips_opts, FALSE); |
| 16434 | |
| 16435 | mips_check_isa_supports_ases (); |
| 16436 | *input_line_pointer = ch; |
| 16437 | demand_empty_rest_of_line (); |
| 16438 | } |
| 16439 | |
| 16440 | /* Handle the .module pseudo-op. */ |
| 16441 | |
| 16442 | static void |
| 16443 | s_module (int ignore ATTRIBUTE_UNUSED) |
| 16444 | { |
| 16445 | char *name = input_line_pointer, ch; |
| 16446 | |
| 16447 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 16448 | ++input_line_pointer; |
| 16449 | ch = *input_line_pointer; |
| 16450 | *input_line_pointer = '\0'; |
| 16451 | |
| 16452 | if (!file_mips_opts_checked) |
| 16453 | { |
| 16454 | if (parse_code_option (name) == OPTION_TYPE_BAD) |
| 16455 | as_bad (_(".module used with unrecognized symbol: %s\n"), name); |
| 16456 | |
| 16457 | /* Update module level settings from mips_opts. */ |
| 16458 | file_mips_opts = mips_opts; |
| 16459 | } |
| 16460 | else |
| 16461 | as_bad (_(".module is not permitted after generating code")); |
| 16462 | |
| 16463 | *input_line_pointer = ch; |
| 16464 | demand_empty_rest_of_line (); |
| 16465 | } |
| 16466 | |
| 16467 | /* Handle the .abicalls pseudo-op. I believe this is equivalent to |
| 16468 | .option pic2. It means to generate SVR4 PIC calls. */ |
| 16469 | |
| 16470 | static void |
| 16471 | s_abicalls (int ignore ATTRIBUTE_UNUSED) |
| 16472 | { |
| 16473 | mips_pic = SVR4_PIC; |
| 16474 | mips_abicalls = TRUE; |
| 16475 | |
| 16476 | if (g_switch_seen && g_switch_value != 0) |
| 16477 | as_warn (_("-G may not be used with SVR4 PIC code")); |
| 16478 | g_switch_value = 0; |
| 16479 | |
| 16480 | bfd_set_gp_size (stdoutput, 0); |
| 16481 | demand_empty_rest_of_line (); |
| 16482 | } |
| 16483 | |
| 16484 | /* Handle the .cpload pseudo-op. This is used when generating SVR4 |
| 16485 | PIC code. It sets the $gp register for the function based on the |
| 16486 | function address, which is in the register named in the argument. |
| 16487 | This uses a relocation against _gp_disp, which is handled specially |
| 16488 | by the linker. The result is: |
| 16489 | lui $gp,%hi(_gp_disp) |
| 16490 | addiu $gp,$gp,%lo(_gp_disp) |
| 16491 | addu $gp,$gp,.cpload argument |
| 16492 | The .cpload argument is normally $25 == $t9. |
| 16493 | |
| 16494 | The -mno-shared option changes this to: |
| 16495 | lui $gp,%hi(__gnu_local_gp) |
| 16496 | addiu $gp,$gp,%lo(__gnu_local_gp) |
| 16497 | and the argument is ignored. This saves an instruction, but the |
| 16498 | resulting code is not position independent; it uses an absolute |
| 16499 | address for __gnu_local_gp. Thus code assembled with -mno-shared |
| 16500 | can go into an ordinary executable, but not into a shared library. */ |
| 16501 | |
| 16502 | static void |
| 16503 | s_cpload (int ignore ATTRIBUTE_UNUSED) |
| 16504 | { |
| 16505 | expressionS ex; |
| 16506 | int reg; |
| 16507 | int in_shared; |
| 16508 | |
| 16509 | file_mips_check_options (); |
| 16510 | |
| 16511 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
| 16512 | .cpload is ignored. */ |
| 16513 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
| 16514 | { |
| 16515 | s_ignore (0); |
| 16516 | return; |
| 16517 | } |
| 16518 | |
| 16519 | if (mips_opts.mips16) |
| 16520 | { |
| 16521 | as_bad (_("%s not supported in MIPS16 mode"), ".cpload"); |
| 16522 | ignore_rest_of_line (); |
| 16523 | return; |
| 16524 | } |
| 16525 | |
| 16526 | /* .cpload should be in a .set noreorder section. */ |
| 16527 | if (mips_opts.noreorder == 0) |
| 16528 | as_warn (_(".cpload not in noreorder section")); |
| 16529 | |
| 16530 | reg = tc_get_register (0); |
| 16531 | |
| 16532 | /* If we need to produce a 64-bit address, we are better off using |
| 16533 | the default instruction sequence. */ |
| 16534 | in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS; |
| 16535 | |
| 16536 | ex.X_op = O_symbol; |
| 16537 | ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" : |
| 16538 | "__gnu_local_gp"); |
| 16539 | ex.X_op_symbol = NULL; |
| 16540 | ex.X_add_number = 0; |
| 16541 | |
| 16542 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
| 16543 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
| 16544 | |
| 16545 | mips_mark_labels (); |
| 16546 | mips_assembling_insn = TRUE; |
| 16547 | |
| 16548 | macro_start (); |
| 16549 | macro_build_lui (&ex, mips_gp_register); |
| 16550 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, |
| 16551 | mips_gp_register, BFD_RELOC_LO16); |
| 16552 | if (in_shared) |
| 16553 | macro_build (NULL, "addu", "d,v,t", mips_gp_register, |
| 16554 | mips_gp_register, reg); |
| 16555 | macro_end (); |
| 16556 | |
| 16557 | mips_assembling_insn = FALSE; |
| 16558 | demand_empty_rest_of_line (); |
| 16559 | } |
| 16560 | |
| 16561 | /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: |
| 16562 | .cpsetup $reg1, offset|$reg2, label |
| 16563 | |
| 16564 | If offset is given, this results in: |
| 16565 | sd $gp, offset($sp) |
| 16566 | lui $gp, %hi(%neg(%gp_rel(label))) |
| 16567 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
| 16568 | daddu $gp, $gp, $reg1 |
| 16569 | |
| 16570 | If $reg2 is given, this results in: |
| 16571 | or $reg2, $gp, $0 |
| 16572 | lui $gp, %hi(%neg(%gp_rel(label))) |
| 16573 | addiu $gp, $gp, %lo(%neg(%gp_rel(label))) |
| 16574 | daddu $gp, $gp, $reg1 |
| 16575 | $reg1 is normally $25 == $t9. |
| 16576 | |
| 16577 | The -mno-shared option replaces the last three instructions with |
| 16578 | lui $gp,%hi(_gp) |
| 16579 | addiu $gp,$gp,%lo(_gp) */ |
| 16580 | |
| 16581 | static void |
| 16582 | s_cpsetup (int ignore ATTRIBUTE_UNUSED) |
| 16583 | { |
| 16584 | expressionS ex_off; |
| 16585 | expressionS ex_sym; |
| 16586 | int reg1; |
| 16587 | |
| 16588 | file_mips_check_options (); |
| 16589 | |
| 16590 | /* If we are not generating SVR4 PIC code, .cpsetup is ignored. |
| 16591 | We also need NewABI support. */ |
| 16592 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
| 16593 | { |
| 16594 | s_ignore (0); |
| 16595 | return; |
| 16596 | } |
| 16597 | |
| 16598 | if (mips_opts.mips16) |
| 16599 | { |
| 16600 | as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup"); |
| 16601 | ignore_rest_of_line (); |
| 16602 | return; |
| 16603 | } |
| 16604 | |
| 16605 | reg1 = tc_get_register (0); |
| 16606 | SKIP_WHITESPACE (); |
| 16607 | if (*input_line_pointer != ',') |
| 16608 | { |
| 16609 | as_bad (_("missing argument separator ',' for .cpsetup")); |
| 16610 | return; |
| 16611 | } |
| 16612 | else |
| 16613 | ++input_line_pointer; |
| 16614 | SKIP_WHITESPACE (); |
| 16615 | if (*input_line_pointer == '$') |
| 16616 | { |
| 16617 | mips_cpreturn_register = tc_get_register (0); |
| 16618 | mips_cpreturn_offset = -1; |
| 16619 | } |
| 16620 | else |
| 16621 | { |
| 16622 | mips_cpreturn_offset = get_absolute_expression (); |
| 16623 | mips_cpreturn_register = -1; |
| 16624 | } |
| 16625 | SKIP_WHITESPACE (); |
| 16626 | if (*input_line_pointer != ',') |
| 16627 | { |
| 16628 | as_bad (_("missing argument separator ',' for .cpsetup")); |
| 16629 | return; |
| 16630 | } |
| 16631 | else |
| 16632 | ++input_line_pointer; |
| 16633 | SKIP_WHITESPACE (); |
| 16634 | expression (&ex_sym); |
| 16635 | |
| 16636 | mips_mark_labels (); |
| 16637 | mips_assembling_insn = TRUE; |
| 16638 | |
| 16639 | macro_start (); |
| 16640 | if (mips_cpreturn_register == -1) |
| 16641 | { |
| 16642 | ex_off.X_op = O_constant; |
| 16643 | ex_off.X_add_symbol = NULL; |
| 16644 | ex_off.X_op_symbol = NULL; |
| 16645 | ex_off.X_add_number = mips_cpreturn_offset; |
| 16646 | |
| 16647 | macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register, |
| 16648 | BFD_RELOC_LO16, SP); |
| 16649 | } |
| 16650 | else |
| 16651 | move_register (mips_cpreturn_register, mips_gp_register); |
| 16652 | |
| 16653 | if (mips_in_shared || HAVE_64BIT_SYMBOLS) |
| 16654 | { |
| 16655 | macro_build (&ex_sym, "lui", LUI_FMT, mips_gp_register, |
| 16656 | -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB, |
| 16657 | BFD_RELOC_HI16_S); |
| 16658 | |
| 16659 | macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register, |
| 16660 | mips_gp_register, -1, BFD_RELOC_GPREL16, |
| 16661 | BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16); |
| 16662 | |
| 16663 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register, |
| 16664 | mips_gp_register, reg1); |
| 16665 | } |
| 16666 | else |
| 16667 | { |
| 16668 | expressionS ex; |
| 16669 | |
| 16670 | ex.X_op = O_symbol; |
| 16671 | ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp"); |
| 16672 | ex.X_op_symbol = NULL; |
| 16673 | ex.X_add_number = 0; |
| 16674 | |
| 16675 | /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */ |
| 16676 | symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; |
| 16677 | |
| 16678 | macro_build_lui (&ex, mips_gp_register); |
| 16679 | macro_build (&ex, "addiu", "t,r,j", mips_gp_register, |
| 16680 | mips_gp_register, BFD_RELOC_LO16); |
| 16681 | } |
| 16682 | |
| 16683 | macro_end (); |
| 16684 | |
| 16685 | mips_assembling_insn = FALSE; |
| 16686 | demand_empty_rest_of_line (); |
| 16687 | } |
| 16688 | |
| 16689 | static void |
| 16690 | s_cplocal (int ignore ATTRIBUTE_UNUSED) |
| 16691 | { |
| 16692 | file_mips_check_options (); |
| 16693 | |
| 16694 | /* If we are not generating SVR4 PIC code, or if this is not NewABI code, |
| 16695 | .cplocal is ignored. */ |
| 16696 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
| 16697 | { |
| 16698 | s_ignore (0); |
| 16699 | return; |
| 16700 | } |
| 16701 | |
| 16702 | if (mips_opts.mips16) |
| 16703 | { |
| 16704 | as_bad (_("%s not supported in MIPS16 mode"), ".cplocal"); |
| 16705 | ignore_rest_of_line (); |
| 16706 | return; |
| 16707 | } |
| 16708 | |
| 16709 | mips_gp_register = tc_get_register (0); |
| 16710 | demand_empty_rest_of_line (); |
| 16711 | } |
| 16712 | |
| 16713 | /* Handle the .cprestore pseudo-op. This stores $gp into a given |
| 16714 | offset from $sp. The offset is remembered, and after making a PIC |
| 16715 | call $gp is restored from that location. */ |
| 16716 | |
| 16717 | static void |
| 16718 | s_cprestore (int ignore ATTRIBUTE_UNUSED) |
| 16719 | { |
| 16720 | expressionS ex; |
| 16721 | |
| 16722 | file_mips_check_options (); |
| 16723 | |
| 16724 | /* If we are not generating SVR4 PIC code, or if this is NewABI code, |
| 16725 | .cprestore is ignored. */ |
| 16726 | if (mips_pic != SVR4_PIC || HAVE_NEWABI) |
| 16727 | { |
| 16728 | s_ignore (0); |
| 16729 | return; |
| 16730 | } |
| 16731 | |
| 16732 | if (mips_opts.mips16) |
| 16733 | { |
| 16734 | as_bad (_("%s not supported in MIPS16 mode"), ".cprestore"); |
| 16735 | ignore_rest_of_line (); |
| 16736 | return; |
| 16737 | } |
| 16738 | |
| 16739 | mips_cprestore_offset = get_absolute_expression (); |
| 16740 | mips_cprestore_valid = 1; |
| 16741 | |
| 16742 | ex.X_op = O_constant; |
| 16743 | ex.X_add_symbol = NULL; |
| 16744 | ex.X_op_symbol = NULL; |
| 16745 | ex.X_add_number = mips_cprestore_offset; |
| 16746 | |
| 16747 | mips_mark_labels (); |
| 16748 | mips_assembling_insn = TRUE; |
| 16749 | |
| 16750 | macro_start (); |
| 16751 | macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register, |
| 16752 | SP, HAVE_64BIT_ADDRESSES); |
| 16753 | macro_end (); |
| 16754 | |
| 16755 | mips_assembling_insn = FALSE; |
| 16756 | demand_empty_rest_of_line (); |
| 16757 | } |
| 16758 | |
| 16759 | /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset |
| 16760 | was given in the preceding .cpsetup, it results in: |
| 16761 | ld $gp, offset($sp) |
| 16762 | |
| 16763 | If a register $reg2 was given there, it results in: |
| 16764 | or $gp, $reg2, $0 */ |
| 16765 | |
| 16766 | static void |
| 16767 | s_cpreturn (int ignore ATTRIBUTE_UNUSED) |
| 16768 | { |
| 16769 | expressionS ex; |
| 16770 | |
| 16771 | file_mips_check_options (); |
| 16772 | |
| 16773 | /* If we are not generating SVR4 PIC code, .cpreturn is ignored. |
| 16774 | We also need NewABI support. */ |
| 16775 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
| 16776 | { |
| 16777 | s_ignore (0); |
| 16778 | return; |
| 16779 | } |
| 16780 | |
| 16781 | if (mips_opts.mips16) |
| 16782 | { |
| 16783 | as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn"); |
| 16784 | ignore_rest_of_line (); |
| 16785 | return; |
| 16786 | } |
| 16787 | |
| 16788 | mips_mark_labels (); |
| 16789 | mips_assembling_insn = TRUE; |
| 16790 | |
| 16791 | macro_start (); |
| 16792 | if (mips_cpreturn_register == -1) |
| 16793 | { |
| 16794 | ex.X_op = O_constant; |
| 16795 | ex.X_add_symbol = NULL; |
| 16796 | ex.X_op_symbol = NULL; |
| 16797 | ex.X_add_number = mips_cpreturn_offset; |
| 16798 | |
| 16799 | macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP); |
| 16800 | } |
| 16801 | else |
| 16802 | move_register (mips_gp_register, mips_cpreturn_register); |
| 16803 | |
| 16804 | macro_end (); |
| 16805 | |
| 16806 | mips_assembling_insn = FALSE; |
| 16807 | demand_empty_rest_of_line (); |
| 16808 | } |
| 16809 | |
| 16810 | /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword |
| 16811 | pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size |
| 16812 | DTP- or TP-relative relocation of type RTYPE, for use in either DWARF |
| 16813 | debug information or MIPS16 TLS. */ |
| 16814 | |
| 16815 | static void |
| 16816 | s_tls_rel_directive (const size_t bytes, const char *dirstr, |
| 16817 | bfd_reloc_code_real_type rtype) |
| 16818 | { |
| 16819 | expressionS ex; |
| 16820 | char *p; |
| 16821 | |
| 16822 | expression (&ex); |
| 16823 | |
| 16824 | if (ex.X_op != O_symbol) |
| 16825 | { |
| 16826 | as_bad (_("unsupported use of %s"), dirstr); |
| 16827 | ignore_rest_of_line (); |
| 16828 | } |
| 16829 | |
| 16830 | p = frag_more (bytes); |
| 16831 | md_number_to_chars (p, 0, bytes); |
| 16832 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, rtype); |
| 16833 | demand_empty_rest_of_line (); |
| 16834 | mips_clear_insn_labels (); |
| 16835 | } |
| 16836 | |
| 16837 | /* Handle .dtprelword. */ |
| 16838 | |
| 16839 | static void |
| 16840 | s_dtprelword (int ignore ATTRIBUTE_UNUSED) |
| 16841 | { |
| 16842 | s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32); |
| 16843 | } |
| 16844 | |
| 16845 | /* Handle .dtpreldword. */ |
| 16846 | |
| 16847 | static void |
| 16848 | s_dtpreldword (int ignore ATTRIBUTE_UNUSED) |
| 16849 | { |
| 16850 | s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64); |
| 16851 | } |
| 16852 | |
| 16853 | /* Handle .tprelword. */ |
| 16854 | |
| 16855 | static void |
| 16856 | s_tprelword (int ignore ATTRIBUTE_UNUSED) |
| 16857 | { |
| 16858 | s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32); |
| 16859 | } |
| 16860 | |
| 16861 | /* Handle .tpreldword. */ |
| 16862 | |
| 16863 | static void |
| 16864 | s_tpreldword (int ignore ATTRIBUTE_UNUSED) |
| 16865 | { |
| 16866 | s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64); |
| 16867 | } |
| 16868 | |
| 16869 | /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC |
| 16870 | code. It sets the offset to use in gp_rel relocations. */ |
| 16871 | |
| 16872 | static void |
| 16873 | s_gpvalue (int ignore ATTRIBUTE_UNUSED) |
| 16874 | { |
| 16875 | /* If we are not generating SVR4 PIC code, .gpvalue is ignored. |
| 16876 | We also need NewABI support. */ |
| 16877 | if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) |
| 16878 | { |
| 16879 | s_ignore (0); |
| 16880 | return; |
| 16881 | } |
| 16882 | |
| 16883 | mips_gprel_offset = get_absolute_expression (); |
| 16884 | |
| 16885 | demand_empty_rest_of_line (); |
| 16886 | } |
| 16887 | |
| 16888 | /* Handle the .gpword pseudo-op. This is used when generating PIC |
| 16889 | code. It generates a 32 bit GP relative reloc. */ |
| 16890 | |
| 16891 | static void |
| 16892 | s_gpword (int ignore ATTRIBUTE_UNUSED) |
| 16893 | { |
| 16894 | segment_info_type *si; |
| 16895 | struct insn_label_list *l; |
| 16896 | expressionS ex; |
| 16897 | char *p; |
| 16898 | |
| 16899 | /* When not generating PIC code, this is treated as .word. */ |
| 16900 | if (mips_pic != SVR4_PIC) |
| 16901 | { |
| 16902 | s_cons (2); |
| 16903 | return; |
| 16904 | } |
| 16905 | |
| 16906 | si = seg_info (now_seg); |
| 16907 | l = si->label_list; |
| 16908 | mips_emit_delays (); |
| 16909 | if (auto_align) |
| 16910 | mips_align (2, 0, l); |
| 16911 | |
| 16912 | expression (&ex); |
| 16913 | mips_clear_insn_labels (); |
| 16914 | |
| 16915 | if (ex.X_op != O_symbol || ex.X_add_number != 0) |
| 16916 | { |
| 16917 | as_bad (_("unsupported use of .gpword")); |
| 16918 | ignore_rest_of_line (); |
| 16919 | } |
| 16920 | |
| 16921 | p = frag_more (4); |
| 16922 | md_number_to_chars (p, 0, 4); |
| 16923 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
| 16924 | BFD_RELOC_GPREL32); |
| 16925 | |
| 16926 | demand_empty_rest_of_line (); |
| 16927 | } |
| 16928 | |
| 16929 | static void |
| 16930 | s_gpdword (int ignore ATTRIBUTE_UNUSED) |
| 16931 | { |
| 16932 | segment_info_type *si; |
| 16933 | struct insn_label_list *l; |
| 16934 | expressionS ex; |
| 16935 | char *p; |
| 16936 | |
| 16937 | /* When not generating PIC code, this is treated as .dword. */ |
| 16938 | if (mips_pic != SVR4_PIC) |
| 16939 | { |
| 16940 | s_cons (3); |
| 16941 | return; |
| 16942 | } |
| 16943 | |
| 16944 | si = seg_info (now_seg); |
| 16945 | l = si->label_list; |
| 16946 | mips_emit_delays (); |
| 16947 | if (auto_align) |
| 16948 | mips_align (3, 0, l); |
| 16949 | |
| 16950 | expression (&ex); |
| 16951 | mips_clear_insn_labels (); |
| 16952 | |
| 16953 | if (ex.X_op != O_symbol || ex.X_add_number != 0) |
| 16954 | { |
| 16955 | as_bad (_("unsupported use of .gpdword")); |
| 16956 | ignore_rest_of_line (); |
| 16957 | } |
| 16958 | |
| 16959 | p = frag_more (8); |
| 16960 | md_number_to_chars (p, 0, 8); |
| 16961 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
| 16962 | BFD_RELOC_GPREL32)->fx_tcbit = 1; |
| 16963 | |
| 16964 | /* GPREL32 composed with 64 gives a 64-bit GP offset. */ |
| 16965 | fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0, |
| 16966 | FALSE, BFD_RELOC_64)->fx_tcbit = 1; |
| 16967 | |
| 16968 | demand_empty_rest_of_line (); |
| 16969 | } |
| 16970 | |
| 16971 | /* Handle the .ehword pseudo-op. This is used when generating unwinding |
| 16972 | tables. It generates a R_MIPS_EH reloc. */ |
| 16973 | |
| 16974 | static void |
| 16975 | s_ehword (int ignore ATTRIBUTE_UNUSED) |
| 16976 | { |
| 16977 | expressionS ex; |
| 16978 | char *p; |
| 16979 | |
| 16980 | mips_emit_delays (); |
| 16981 | |
| 16982 | expression (&ex); |
| 16983 | mips_clear_insn_labels (); |
| 16984 | |
| 16985 | if (ex.X_op != O_symbol || ex.X_add_number != 0) |
| 16986 | { |
| 16987 | as_bad (_("unsupported use of .ehword")); |
| 16988 | ignore_rest_of_line (); |
| 16989 | } |
| 16990 | |
| 16991 | p = frag_more (4); |
| 16992 | md_number_to_chars (p, 0, 4); |
| 16993 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, |
| 16994 | BFD_RELOC_32_PCREL); |
| 16995 | |
| 16996 | demand_empty_rest_of_line (); |
| 16997 | } |
| 16998 | |
| 16999 | /* Handle the .cpadd pseudo-op. This is used when dealing with switch |
| 17000 | tables in SVR4 PIC code. */ |
| 17001 | |
| 17002 | static void |
| 17003 | s_cpadd (int ignore ATTRIBUTE_UNUSED) |
| 17004 | { |
| 17005 | int reg; |
| 17006 | |
| 17007 | file_mips_check_options (); |
| 17008 | |
| 17009 | /* This is ignored when not generating SVR4 PIC code. */ |
| 17010 | if (mips_pic != SVR4_PIC) |
| 17011 | { |
| 17012 | s_ignore (0); |
| 17013 | return; |
| 17014 | } |
| 17015 | |
| 17016 | mips_mark_labels (); |
| 17017 | mips_assembling_insn = TRUE; |
| 17018 | |
| 17019 | /* Add $gp to the register named as an argument. */ |
| 17020 | macro_start (); |
| 17021 | reg = tc_get_register (0); |
| 17022 | macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register); |
| 17023 | macro_end (); |
| 17024 | |
| 17025 | mips_assembling_insn = FALSE; |
| 17026 | demand_empty_rest_of_line (); |
| 17027 | } |
| 17028 | |
| 17029 | /* Handle the .insn pseudo-op. This marks instruction labels in |
| 17030 | mips16/micromips mode. This permits the linker to handle them specially, |
| 17031 | such as generating jalx instructions when needed. We also make |
| 17032 | them odd for the duration of the assembly, in order to generate the |
| 17033 | right sort of code. We will make them even in the adjust_symtab |
| 17034 | routine, while leaving them marked. This is convenient for the |
| 17035 | debugger and the disassembler. The linker knows to make them odd |
| 17036 | again. */ |
| 17037 | |
| 17038 | static void |
| 17039 | s_insn (int ignore ATTRIBUTE_UNUSED) |
| 17040 | { |
| 17041 | file_mips_check_options (); |
| 17042 | file_ase_mips16 |= mips_opts.mips16; |
| 17043 | file_ase_micromips |= mips_opts.micromips; |
| 17044 | |
| 17045 | mips_mark_labels (); |
| 17046 | |
| 17047 | demand_empty_rest_of_line (); |
| 17048 | } |
| 17049 | |
| 17050 | /* Handle the .nan pseudo-op. */ |
| 17051 | |
| 17052 | static void |
| 17053 | s_nan (int ignore ATTRIBUTE_UNUSED) |
| 17054 | { |
| 17055 | static const char str_legacy[] = "legacy"; |
| 17056 | static const char str_2008[] = "2008"; |
| 17057 | size_t i; |
| 17058 | |
| 17059 | for (i = 0; !is_end_of_line[(unsigned char) input_line_pointer[i]]; i++); |
| 17060 | |
| 17061 | if (i == sizeof (str_2008) - 1 |
| 17062 | && memcmp (input_line_pointer, str_2008, i) == 0) |
| 17063 | mips_nan2008 = 1; |
| 17064 | else if (i == sizeof (str_legacy) - 1 |
| 17065 | && memcmp (input_line_pointer, str_legacy, i) == 0) |
| 17066 | { |
| 17067 | if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) |
| 17068 | mips_nan2008 = 0; |
| 17069 | else |
| 17070 | as_bad (_("`%s' does not support legacy NaN"), |
| 17071 | mips_cpu_info_from_isa (file_mips_opts.isa)->name); |
| 17072 | } |
| 17073 | else |
| 17074 | as_bad (_("bad .nan directive")); |
| 17075 | |
| 17076 | input_line_pointer += i; |
| 17077 | demand_empty_rest_of_line (); |
| 17078 | } |
| 17079 | |
| 17080 | /* Handle a .stab[snd] directive. Ideally these directives would be |
| 17081 | implemented in a transparent way, so that removing them would not |
| 17082 | have any effect on the generated instructions. However, s_stab |
| 17083 | internally changes the section, so in practice we need to decide |
| 17084 | now whether the preceding label marks compressed code. We do not |
| 17085 | support changing the compression mode of a label after a .stab* |
| 17086 | directive, such as in: |
| 17087 | |
| 17088 | foo: |
| 17089 | .stabs ... |
| 17090 | .set mips16 |
| 17091 | |
| 17092 | so the current mode wins. */ |
| 17093 | |
| 17094 | static void |
| 17095 | s_mips_stab (int type) |
| 17096 | { |
| 17097 | mips_mark_labels (); |
| 17098 | s_stab (type); |
| 17099 | } |
| 17100 | |
| 17101 | /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */ |
| 17102 | |
| 17103 | static void |
| 17104 | s_mips_weakext (int ignore ATTRIBUTE_UNUSED) |
| 17105 | { |
| 17106 | char *name; |
| 17107 | int c; |
| 17108 | symbolS *symbolP; |
| 17109 | expressionS exp; |
| 17110 | |
| 17111 | c = get_symbol_name (&name); |
| 17112 | symbolP = symbol_find_or_make (name); |
| 17113 | S_SET_WEAK (symbolP); |
| 17114 | *input_line_pointer = c; |
| 17115 | |
| 17116 | SKIP_WHITESPACE_AFTER_NAME (); |
| 17117 | |
| 17118 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) |
| 17119 | { |
| 17120 | if (S_IS_DEFINED (symbolP)) |
| 17121 | { |
| 17122 | as_bad (_("ignoring attempt to redefine symbol %s"), |
| 17123 | S_GET_NAME (symbolP)); |
| 17124 | ignore_rest_of_line (); |
| 17125 | return; |
| 17126 | } |
| 17127 | |
| 17128 | if (*input_line_pointer == ',') |
| 17129 | { |
| 17130 | ++input_line_pointer; |
| 17131 | SKIP_WHITESPACE (); |
| 17132 | } |
| 17133 | |
| 17134 | expression (&exp); |
| 17135 | if (exp.X_op != O_symbol) |
| 17136 | { |
| 17137 | as_bad (_("bad .weakext directive")); |
| 17138 | ignore_rest_of_line (); |
| 17139 | return; |
| 17140 | } |
| 17141 | symbol_set_value_expression (symbolP, &exp); |
| 17142 | } |
| 17143 | |
| 17144 | demand_empty_rest_of_line (); |
| 17145 | } |
| 17146 | |
| 17147 | /* Parse a register string into a number. Called from the ECOFF code |
| 17148 | to parse .frame. The argument is non-zero if this is the frame |
| 17149 | register, so that we can record it in mips_frame_reg. */ |
| 17150 | |
| 17151 | int |
| 17152 | tc_get_register (int frame) |
| 17153 | { |
| 17154 | unsigned int reg; |
| 17155 | |
| 17156 | SKIP_WHITESPACE (); |
| 17157 | if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) |
| 17158 | reg = 0; |
| 17159 | if (frame) |
| 17160 | { |
| 17161 | mips_frame_reg = reg != 0 ? reg : SP; |
| 17162 | mips_frame_reg_valid = 1; |
| 17163 | mips_cprestore_valid = 0; |
| 17164 | } |
| 17165 | return reg; |
| 17166 | } |
| 17167 | |
| 17168 | valueT |
| 17169 | md_section_align (asection *seg, valueT addr) |
| 17170 | { |
| 17171 | int align = bfd_get_section_alignment (stdoutput, seg); |
| 17172 | |
| 17173 | /* We don't need to align ELF sections to the full alignment. |
| 17174 | However, Irix 5 may prefer that we align them at least to a 16 |
| 17175 | byte boundary. We don't bother to align the sections if we |
| 17176 | are targeted for an embedded system. */ |
| 17177 | if (strncmp (TARGET_OS, "elf", 3) == 0) |
| 17178 | return addr; |
| 17179 | if (align > 4) |
| 17180 | align = 4; |
| 17181 | |
| 17182 | return ((addr + (1 << align) - 1) & -(1 << align)); |
| 17183 | } |
| 17184 | |
| 17185 | /* Utility routine, called from above as well. If called while the |
| 17186 | input file is still being read, it's only an approximation. (For |
| 17187 | example, a symbol may later become defined which appeared to be |
| 17188 | undefined earlier.) */ |
| 17189 | |
| 17190 | static int |
| 17191 | nopic_need_relax (symbolS *sym, int before_relaxing) |
| 17192 | { |
| 17193 | if (sym == 0) |
| 17194 | return 0; |
| 17195 | |
| 17196 | if (g_switch_value > 0) |
| 17197 | { |
| 17198 | const char *symname; |
| 17199 | int change; |
| 17200 | |
| 17201 | /* Find out whether this symbol can be referenced off the $gp |
| 17202 | register. It can be if it is smaller than the -G size or if |
| 17203 | it is in the .sdata or .sbss section. Certain symbols can |
| 17204 | not be referenced off the $gp, although it appears as though |
| 17205 | they can. */ |
| 17206 | symname = S_GET_NAME (sym); |
| 17207 | if (symname != (const char *) NULL |
| 17208 | && (strcmp (symname, "eprol") == 0 |
| 17209 | || strcmp (symname, "etext") == 0 |
| 17210 | || strcmp (symname, "_gp") == 0 |
| 17211 | || strcmp (symname, "edata") == 0 |
| 17212 | || strcmp (symname, "_fbss") == 0 |
| 17213 | || strcmp (symname, "_fdata") == 0 |
| 17214 | || strcmp (symname, "_ftext") == 0 |
| 17215 | || strcmp (symname, "end") == 0 |
| 17216 | || strcmp (symname, "_gp_disp") == 0)) |
| 17217 | change = 1; |
| 17218 | else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) |
| 17219 | && (0 |
| 17220 | #ifndef NO_ECOFF_DEBUGGING |
| 17221 | || (symbol_get_obj (sym)->ecoff_extern_size != 0 |
| 17222 | && (symbol_get_obj (sym)->ecoff_extern_size |
| 17223 | <= g_switch_value)) |
| 17224 | #endif |
| 17225 | /* We must defer this decision until after the whole |
| 17226 | file has been read, since there might be a .extern |
| 17227 | after the first use of this symbol. */ |
| 17228 | || (before_relaxing |
| 17229 | #ifndef NO_ECOFF_DEBUGGING |
| 17230 | && symbol_get_obj (sym)->ecoff_extern_size == 0 |
| 17231 | #endif |
| 17232 | && S_GET_VALUE (sym) == 0) |
| 17233 | || (S_GET_VALUE (sym) != 0 |
| 17234 | && S_GET_VALUE (sym) <= g_switch_value))) |
| 17235 | change = 0; |
| 17236 | else |
| 17237 | { |
| 17238 | const char *segname; |
| 17239 | |
| 17240 | segname = segment_name (S_GET_SEGMENT (sym)); |
| 17241 | gas_assert (strcmp (segname, ".lit8") != 0 |
| 17242 | && strcmp (segname, ".lit4") != 0); |
| 17243 | change = (strcmp (segname, ".sdata") != 0 |
| 17244 | && strcmp (segname, ".sbss") != 0 |
| 17245 | && strncmp (segname, ".sdata.", 7) != 0 |
| 17246 | && strncmp (segname, ".sbss.", 6) != 0 |
| 17247 | && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 |
| 17248 | && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); |
| 17249 | } |
| 17250 | return change; |
| 17251 | } |
| 17252 | else |
| 17253 | /* We are not optimizing for the $gp register. */ |
| 17254 | return 1; |
| 17255 | } |
| 17256 | |
| 17257 | |
| 17258 | /* Return true if the given symbol should be considered local for SVR4 PIC. */ |
| 17259 | |
| 17260 | static bfd_boolean |
| 17261 | pic_need_relax (symbolS *sym) |
| 17262 | { |
| 17263 | asection *symsec; |
| 17264 | |
| 17265 | /* Handle the case of a symbol equated to another symbol. */ |
| 17266 | while (symbol_equated_reloc_p (sym)) |
| 17267 | { |
| 17268 | symbolS *n; |
| 17269 | |
| 17270 | /* It's possible to get a loop here in a badly written program. */ |
| 17271 | n = symbol_get_value_expression (sym)->X_add_symbol; |
| 17272 | if (n == sym) |
| 17273 | break; |
| 17274 | sym = n; |
| 17275 | } |
| 17276 | |
| 17277 | if (symbol_section_p (sym)) |
| 17278 | return TRUE; |
| 17279 | |
| 17280 | symsec = S_GET_SEGMENT (sym); |
| 17281 | |
| 17282 | /* This must duplicate the test in adjust_reloc_syms. */ |
| 17283 | return (!bfd_is_und_section (symsec) |
| 17284 | && !bfd_is_abs_section (symsec) |
| 17285 | && !bfd_is_com_section (symsec) |
| 17286 | /* A global or weak symbol is treated as external. */ |
| 17287 | && (!S_IS_WEAK (sym) && !S_IS_EXTERNAL (sym))); |
| 17288 | } |
| 17289 | \f |
| 17290 | /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP |
| 17291 | convert a section-relative value VAL to the equivalent PC-relative |
| 17292 | value. */ |
| 17293 | |
| 17294 | static offsetT |
| 17295 | mips16_pcrel_val (fragS *fragp, const struct mips_pcrel_operand *pcrel_op, |
| 17296 | offsetT val, long stretch) |
| 17297 | { |
| 17298 | fragS *sym_frag; |
| 17299 | addressT addr; |
| 17300 | |
| 17301 | gas_assert (pcrel_op->root.root.type == OP_PCREL); |
| 17302 | |
| 17303 | sym_frag = symbol_get_frag (fragp->fr_symbol); |
| 17304 | |
| 17305 | /* If the relax_marker of the symbol fragment differs from the |
| 17306 | relax_marker of this fragment, we have not yet adjusted the |
| 17307 | symbol fragment fr_address. We want to add in STRETCH in |
| 17308 | order to get a better estimate of the address. This |
| 17309 | particularly matters because of the shift bits. */ |
| 17310 | if (stretch != 0 && sym_frag->relax_marker != fragp->relax_marker) |
| 17311 | { |
| 17312 | fragS *f; |
| 17313 | |
| 17314 | /* Adjust stretch for any alignment frag. Note that if have |
| 17315 | been expanding the earlier code, the symbol may be |
| 17316 | defined in what appears to be an earlier frag. FIXME: |
| 17317 | This doesn't handle the fr_subtype field, which specifies |
| 17318 | a maximum number of bytes to skip when doing an |
| 17319 | alignment. */ |
| 17320 | for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next) |
| 17321 | { |
| 17322 | if (f->fr_type == rs_align || f->fr_type == rs_align_code) |
| 17323 | { |
| 17324 | if (stretch < 0) |
| 17325 | stretch = -(-stretch & ~((1 << (int) f->fr_offset) - 1)); |
| 17326 | else |
| 17327 | stretch &= ~((1 << (int) f->fr_offset) - 1); |
| 17328 | if (stretch == 0) |
| 17329 | break; |
| 17330 | } |
| 17331 | } |
| 17332 | if (f != NULL) |
| 17333 | val += stretch; |
| 17334 | } |
| 17335 | |
| 17336 | addr = fragp->fr_address + fragp->fr_fix; |
| 17337 | |
| 17338 | /* The base address rules are complicated. The base address of |
| 17339 | a branch is the following instruction. The base address of a |
| 17340 | PC relative load or add is the instruction itself, but if it |
| 17341 | is in a delay slot (in which case it can not be extended) use |
| 17342 | the address of the instruction whose delay slot it is in. */ |
| 17343 | if (pcrel_op->include_isa_bit) |
| 17344 | { |
| 17345 | addr += 2; |
| 17346 | |
| 17347 | /* If we are currently assuming that this frag should be |
| 17348 | extended, then the current address is two bytes higher. */ |
| 17349 | if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 17350 | addr += 2; |
| 17351 | |
| 17352 | /* Ignore the low bit in the target, since it will be set |
| 17353 | for a text label. */ |
| 17354 | val &= -2; |
| 17355 | } |
| 17356 | else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)) |
| 17357 | addr -= 4; |
| 17358 | else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype)) |
| 17359 | addr -= 2; |
| 17360 | |
| 17361 | val -= addr & -(1 << pcrel_op->align_log2); |
| 17362 | |
| 17363 | return val; |
| 17364 | } |
| 17365 | |
| 17366 | /* Given a mips16 variant frag FRAGP, return non-zero if it needs an |
| 17367 | extended opcode. SEC is the section the frag is in. */ |
| 17368 | |
| 17369 | static int |
| 17370 | mips16_extended_frag (fragS *fragp, asection *sec, long stretch) |
| 17371 | { |
| 17372 | const struct mips_int_operand *operand; |
| 17373 | offsetT val; |
| 17374 | segT symsec; |
| 17375 | int type; |
| 17376 | |
| 17377 | if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
| 17378 | return 0; |
| 17379 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
| 17380 | return 1; |
| 17381 | |
| 17382 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
| 17383 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
| 17384 | operand = mips16_immed_operand (type, FALSE); |
| 17385 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
| 17386 | || (operand->root.type == OP_PCREL |
| 17387 | ? sec != symsec |
| 17388 | : !bfd_is_abs_section (symsec))) |
| 17389 | return 1; |
| 17390 | |
| 17391 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
| 17392 | |
| 17393 | if (operand->root.type == OP_PCREL) |
| 17394 | { |
| 17395 | const struct mips_pcrel_operand *pcrel_op; |
| 17396 | offsetT maxtiny; |
| 17397 | |
| 17398 | if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp->fr_subtype)) |
| 17399 | return 1; |
| 17400 | |
| 17401 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
| 17402 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
| 17403 | |
| 17404 | /* If any of the shifted bits are set, we must use an extended |
| 17405 | opcode. If the address depends on the size of this |
| 17406 | instruction, this can lead to a loop, so we arrange to always |
| 17407 | use an extended opcode. */ |
| 17408 | if ((val & ((1 << operand->shift) - 1)) != 0) |
| 17409 | { |
| 17410 | fragp->fr_subtype = |
| 17411 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
| 17412 | return 1; |
| 17413 | } |
| 17414 | |
| 17415 | /* If we are about to mark a frag as extended because the value |
| 17416 | is precisely the next value above maxtiny, then there is a |
| 17417 | chance of an infinite loop as in the following code: |
| 17418 | la $4,foo |
| 17419 | .skip 1020 |
| 17420 | .align 2 |
| 17421 | foo: |
| 17422 | In this case when the la is extended, foo is 0x3fc bytes |
| 17423 | away, so the la can be shrunk, but then foo is 0x400 away, so |
| 17424 | the la must be extended. To avoid this loop, we mark the |
| 17425 | frag as extended if it was small, and is about to become |
| 17426 | extended with the next value above maxtiny. */ |
| 17427 | maxtiny = mips_int_operand_max (operand); |
| 17428 | if (val == maxtiny + (1 << operand->shift) |
| 17429 | && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 17430 | { |
| 17431 | fragp->fr_subtype = |
| 17432 | RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp->fr_subtype); |
| 17433 | return 1; |
| 17434 | } |
| 17435 | } |
| 17436 | |
| 17437 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
| 17438 | } |
| 17439 | |
| 17440 | /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs |
| 17441 | macro expansion. SEC is the section the frag is in. We only |
| 17442 | support PC-relative instructions (LA, DLA, LW, LD) here, in |
| 17443 | non-PIC code using 32-bit addressing. */ |
| 17444 | |
| 17445 | static int |
| 17446 | mips16_macro_frag (fragS *fragp, asection *sec, long stretch) |
| 17447 | { |
| 17448 | const struct mips_pcrel_operand *pcrel_op; |
| 17449 | const struct mips_int_operand *operand; |
| 17450 | offsetT val; |
| 17451 | segT symsec; |
| 17452 | int type; |
| 17453 | |
| 17454 | gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)); |
| 17455 | |
| 17456 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
| 17457 | return 0; |
| 17458 | if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype)) |
| 17459 | return 0; |
| 17460 | |
| 17461 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
| 17462 | switch (type) |
| 17463 | { |
| 17464 | case 'A': |
| 17465 | case 'B': |
| 17466 | case 'E': |
| 17467 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
| 17468 | if (bfd_is_abs_section (symsec)) |
| 17469 | return 1; |
| 17470 | if (RELAX_MIPS16_PIC (fragp->fr_subtype)) |
| 17471 | return 0; |
| 17472 | if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec) |
| 17473 | return 1; |
| 17474 | |
| 17475 | operand = mips16_immed_operand (type, TRUE); |
| 17476 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
| 17477 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
| 17478 | val = mips16_pcrel_val (fragp, pcrel_op, val, stretch); |
| 17479 | |
| 17480 | return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val); |
| 17481 | |
| 17482 | default: |
| 17483 | return 0; |
| 17484 | } |
| 17485 | } |
| 17486 | |
| 17487 | /* Compute the length of a branch sequence, and adjust the |
| 17488 | RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the |
| 17489 | worst-case length is computed, with UPDATE being used to indicate |
| 17490 | whether an unconditional (-1), branch-likely (+1) or regular (0) |
| 17491 | branch is to be computed. */ |
| 17492 | static int |
| 17493 | relaxed_branch_length (fragS *fragp, asection *sec, int update) |
| 17494 | { |
| 17495 | bfd_boolean toofar; |
| 17496 | int length; |
| 17497 | |
| 17498 | if (fragp |
| 17499 | && S_IS_DEFINED (fragp->fr_symbol) |
| 17500 | && !S_IS_WEAK (fragp->fr_symbol) |
| 17501 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
| 17502 | { |
| 17503 | addressT addr; |
| 17504 | offsetT val; |
| 17505 | |
| 17506 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
| 17507 | |
| 17508 | addr = fragp->fr_address + fragp->fr_fix + 4; |
| 17509 | |
| 17510 | val -= addr; |
| 17511 | |
| 17512 | toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2); |
| 17513 | } |
| 17514 | else |
| 17515 | /* If the symbol is not defined or it's in a different segment, |
| 17516 | we emit the long sequence. */ |
| 17517 | toofar = TRUE; |
| 17518 | |
| 17519 | if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
| 17520 | fragp->fr_subtype |
| 17521 | = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype), |
| 17522 | RELAX_BRANCH_PIC (fragp->fr_subtype), |
| 17523 | RELAX_BRANCH_UNCOND (fragp->fr_subtype), |
| 17524 | RELAX_BRANCH_LIKELY (fragp->fr_subtype), |
| 17525 | RELAX_BRANCH_LINK (fragp->fr_subtype), |
| 17526 | toofar); |
| 17527 | |
| 17528 | length = 4; |
| 17529 | if (toofar) |
| 17530 | { |
| 17531 | if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0)) |
| 17532 | length += 8; |
| 17533 | |
| 17534 | if (!fragp || RELAX_BRANCH_PIC (fragp->fr_subtype)) |
| 17535 | { |
| 17536 | /* Additional space for PIC loading of target address. */ |
| 17537 | length += 8; |
| 17538 | if (mips_opts.isa == ISA_MIPS1) |
| 17539 | /* Additional space for $at-stabilizing nop. */ |
| 17540 | length += 4; |
| 17541 | } |
| 17542 | |
| 17543 | /* If branch is conditional. */ |
| 17544 | if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0)) |
| 17545 | length += 8; |
| 17546 | } |
| 17547 | |
| 17548 | return length; |
| 17549 | } |
| 17550 | |
| 17551 | /* Get a FRAG's branch instruction delay slot size, either from the |
| 17552 | short-delay-slot bit of a branch-and-link instruction if AL is TRUE, |
| 17553 | or SHORT_INSN_SIZE otherwise. */ |
| 17554 | |
| 17555 | static int |
| 17556 | frag_branch_delay_slot_size (fragS *fragp, bfd_boolean al, int short_insn_size) |
| 17557 | { |
| 17558 | char *buf = fragp->fr_literal + fragp->fr_fix; |
| 17559 | |
| 17560 | if (al) |
| 17561 | return (read_compressed_insn (buf, 4) & 0x02000000) ? 2 : 4; |
| 17562 | else |
| 17563 | return short_insn_size; |
| 17564 | } |
| 17565 | |
| 17566 | /* Compute the length of a branch sequence, and adjust the |
| 17567 | RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the |
| 17568 | worst-case length is computed, with UPDATE being used to indicate |
| 17569 | whether an unconditional (-1), or regular (0) branch is to be |
| 17570 | computed. */ |
| 17571 | |
| 17572 | static int |
| 17573 | relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update) |
| 17574 | { |
| 17575 | bfd_boolean insn32 = TRUE; |
| 17576 | bfd_boolean nods = TRUE; |
| 17577 | bfd_boolean pic = TRUE; |
| 17578 | bfd_boolean al = TRUE; |
| 17579 | int short_insn_size; |
| 17580 | bfd_boolean toofar; |
| 17581 | int length; |
| 17582 | |
| 17583 | if (fragp) |
| 17584 | { |
| 17585 | insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
| 17586 | nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
| 17587 | pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
| 17588 | al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
| 17589 | } |
| 17590 | short_insn_size = insn32 ? 4 : 2; |
| 17591 | |
| 17592 | if (fragp |
| 17593 | && S_IS_DEFINED (fragp->fr_symbol) |
| 17594 | && !S_IS_WEAK (fragp->fr_symbol) |
| 17595 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
| 17596 | { |
| 17597 | addressT addr; |
| 17598 | offsetT val; |
| 17599 | |
| 17600 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
| 17601 | /* Ignore the low bit in the target, since it will be set |
| 17602 | for a text label. */ |
| 17603 | if ((val & 1) != 0) |
| 17604 | --val; |
| 17605 | |
| 17606 | addr = fragp->fr_address + fragp->fr_fix + 4; |
| 17607 | |
| 17608 | val -= addr; |
| 17609 | |
| 17610 | toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1); |
| 17611 | } |
| 17612 | else |
| 17613 | /* If the symbol is not defined or it's in a different segment, |
| 17614 | we emit the long sequence. */ |
| 17615 | toofar = TRUE; |
| 17616 | |
| 17617 | if (fragp && update |
| 17618 | && toofar != RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) |
| 17619 | fragp->fr_subtype = (toofar |
| 17620 | ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp->fr_subtype) |
| 17621 | : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp->fr_subtype)); |
| 17622 | |
| 17623 | length = 4; |
| 17624 | if (toofar) |
| 17625 | { |
| 17626 | bfd_boolean compact_known = fragp != NULL; |
| 17627 | bfd_boolean compact = FALSE; |
| 17628 | bfd_boolean uncond; |
| 17629 | |
| 17630 | if (fragp) |
| 17631 | { |
| 17632 | compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
| 17633 | uncond = RELAX_MICROMIPS_UNCOND (fragp->fr_subtype); |
| 17634 | } |
| 17635 | else |
| 17636 | uncond = update < 0; |
| 17637 | |
| 17638 | /* If label is out of range, we turn branch <br>: |
| 17639 | |
| 17640 | <br> label # 4 bytes |
| 17641 | 0: |
| 17642 | |
| 17643 | into: |
| 17644 | |
| 17645 | j label # 4 bytes |
| 17646 | nop # 2/4 bytes if |
| 17647 | # compact && (!PIC || insn32) |
| 17648 | 0: |
| 17649 | */ |
| 17650 | if ((!pic || insn32) && (!compact_known || compact)) |
| 17651 | length += short_insn_size; |
| 17652 | |
| 17653 | /* If assembling PIC code, we further turn: |
| 17654 | |
| 17655 | j label # 4 bytes |
| 17656 | |
| 17657 | into: |
| 17658 | |
| 17659 | lw/ld at, %got(label)(gp) # 4 bytes |
| 17660 | d/addiu at, %lo(label) # 4 bytes |
| 17661 | jr/c at # 2/4 bytes |
| 17662 | */ |
| 17663 | if (pic) |
| 17664 | length += 4 + short_insn_size; |
| 17665 | |
| 17666 | /* Add an extra nop if the jump has no compact form and we need |
| 17667 | to fill the delay slot. */ |
| 17668 | if ((!pic || al) && nods) |
| 17669 | length += (fragp |
| 17670 | ? frag_branch_delay_slot_size (fragp, al, short_insn_size) |
| 17671 | : short_insn_size); |
| 17672 | |
| 17673 | /* If branch <br> is conditional, we prepend negated branch <brneg>: |
| 17674 | |
| 17675 | <brneg> 0f # 4 bytes |
| 17676 | nop # 2/4 bytes if !compact |
| 17677 | */ |
| 17678 | if (!uncond) |
| 17679 | length += (compact_known && compact) ? 4 : 4 + short_insn_size; |
| 17680 | } |
| 17681 | else if (nods) |
| 17682 | { |
| 17683 | /* Add an extra nop to fill the delay slot. */ |
| 17684 | gas_assert (fragp); |
| 17685 | length += frag_branch_delay_slot_size (fragp, al, short_insn_size); |
| 17686 | } |
| 17687 | |
| 17688 | return length; |
| 17689 | } |
| 17690 | |
| 17691 | /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16 |
| 17692 | bit accordingly. */ |
| 17693 | |
| 17694 | static int |
| 17695 | relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update) |
| 17696 | { |
| 17697 | bfd_boolean toofar; |
| 17698 | |
| 17699 | if (fragp |
| 17700 | && S_IS_DEFINED (fragp->fr_symbol) |
| 17701 | && !S_IS_WEAK (fragp->fr_symbol) |
| 17702 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
| 17703 | { |
| 17704 | addressT addr; |
| 17705 | offsetT val; |
| 17706 | int type; |
| 17707 | |
| 17708 | val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; |
| 17709 | /* Ignore the low bit in the target, since it will be set |
| 17710 | for a text label. */ |
| 17711 | if ((val & 1) != 0) |
| 17712 | --val; |
| 17713 | |
| 17714 | /* Assume this is a 2-byte branch. */ |
| 17715 | addr = fragp->fr_address + fragp->fr_fix + 2; |
| 17716 | |
| 17717 | /* We try to avoid the infinite loop by not adding 2 more bytes for |
| 17718 | long branches. */ |
| 17719 | |
| 17720 | val -= addr; |
| 17721 | |
| 17722 | type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); |
| 17723 | if (type == 'D') |
| 17724 | toofar = val < - (0x200 << 1) || val >= (0x200 << 1); |
| 17725 | else if (type == 'E') |
| 17726 | toofar = val < - (0x40 << 1) || val >= (0x40 << 1); |
| 17727 | else |
| 17728 | abort (); |
| 17729 | } |
| 17730 | else |
| 17731 | /* If the symbol is not defined or it's in a different segment, |
| 17732 | we emit a normal 32-bit branch. */ |
| 17733 | toofar = TRUE; |
| 17734 | |
| 17735 | if (fragp && update |
| 17736 | && toofar != RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) |
| 17737 | fragp->fr_subtype |
| 17738 | = toofar ? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp->fr_subtype) |
| 17739 | : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp->fr_subtype); |
| 17740 | |
| 17741 | if (toofar) |
| 17742 | return 4; |
| 17743 | |
| 17744 | return 2; |
| 17745 | } |
| 17746 | |
| 17747 | /* Estimate the size of a frag before relaxing. Unless this is the |
| 17748 | mips16, we are not really relaxing here, and the final size is |
| 17749 | encoded in the subtype information. For the mips16, we have to |
| 17750 | decide whether we are using an extended opcode or not. */ |
| 17751 | |
| 17752 | int |
| 17753 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) |
| 17754 | { |
| 17755 | int change; |
| 17756 | |
| 17757 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
| 17758 | { |
| 17759 | |
| 17760 | fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE); |
| 17761 | |
| 17762 | return fragp->fr_var; |
| 17763 | } |
| 17764 | |
| 17765 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
| 17766 | { |
| 17767 | /* We don't want to modify the EXTENDED bit here; it might get us |
| 17768 | into infinite loops. We change it only in mips_relax_frag(). */ |
| 17769 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
| 17770 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 8 : 12; |
| 17771 | else |
| 17772 | return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2; |
| 17773 | } |
| 17774 | |
| 17775 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
| 17776 | { |
| 17777 | int length = 4; |
| 17778 | |
| 17779 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) |
| 17780 | length = relaxed_micromips_16bit_branch_length (fragp, segtype, FALSE); |
| 17781 | if (length == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) |
| 17782 | length = relaxed_micromips_32bit_branch_length (fragp, segtype, FALSE); |
| 17783 | fragp->fr_var = length; |
| 17784 | |
| 17785 | return length; |
| 17786 | } |
| 17787 | |
| 17788 | if (mips_pic == VXWORKS_PIC) |
| 17789 | /* For vxworks, GOT16 relocations never have a corresponding LO16. */ |
| 17790 | change = 0; |
| 17791 | else if (RELAX_PIC (fragp->fr_subtype)) |
| 17792 | change = pic_need_relax (fragp->fr_symbol); |
| 17793 | else |
| 17794 | change = nopic_need_relax (fragp->fr_symbol, 0); |
| 17795 | |
| 17796 | if (change) |
| 17797 | { |
| 17798 | fragp->fr_subtype |= RELAX_USE_SECOND; |
| 17799 | return -RELAX_FIRST (fragp->fr_subtype); |
| 17800 | } |
| 17801 | else |
| 17802 | return -RELAX_SECOND (fragp->fr_subtype); |
| 17803 | } |
| 17804 | |
| 17805 | /* This is called to see whether a reloc against a defined symbol |
| 17806 | should be converted into a reloc against a section. */ |
| 17807 | |
| 17808 | int |
| 17809 | mips_fix_adjustable (fixS *fixp) |
| 17810 | { |
| 17811 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
| 17812 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 17813 | return 0; |
| 17814 | |
| 17815 | if (fixp->fx_addsy == NULL) |
| 17816 | return 1; |
| 17817 | |
| 17818 | /* Allow relocs used for EH tables. */ |
| 17819 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
| 17820 | return 1; |
| 17821 | |
| 17822 | /* If symbol SYM is in a mergeable section, relocations of the form |
| 17823 | SYM + 0 can usually be made section-relative. The mergeable data |
| 17824 | is then identified by the section offset rather than by the symbol. |
| 17825 | |
| 17826 | However, if we're generating REL LO16 relocations, the offset is split |
| 17827 | between the LO16 and partnering high part relocation. The linker will |
| 17828 | need to recalculate the complete offset in order to correctly identify |
| 17829 | the merge data. |
| 17830 | |
| 17831 | The linker has traditionally not looked for the partnering high part |
| 17832 | relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be |
| 17833 | placed anywhere. Rather than break backwards compatibility by changing |
| 17834 | this, it seems better not to force the issue, and instead keep the |
| 17835 | original symbol. This will work with either linker behavior. */ |
| 17836 | if ((lo16_reloc_p (fixp->fx_r_type) |
| 17837 | || reloc_needs_lo_p (fixp->fx_r_type)) |
| 17838 | && HAVE_IN_PLACE_ADDENDS |
| 17839 | && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0) |
| 17840 | return 0; |
| 17841 | |
| 17842 | /* There is no place to store an in-place offset for JALR relocations. */ |
| 17843 | if (jalr_reloc_p (fixp->fx_r_type) && HAVE_IN_PLACE_ADDENDS) |
| 17844 | return 0; |
| 17845 | |
| 17846 | /* Likewise an in-range offset of limited PC-relative relocations may |
| 17847 | overflow the in-place relocatable field if recalculated against the |
| 17848 | start address of the symbol's containing section. |
| 17849 | |
| 17850 | Also, PC relative relocations for MIPS R6 need to be symbol rather than |
| 17851 | section relative to allow linker relaxations to be performed later on. */ |
| 17852 | if (limited_pcrel_reloc_p (fixp->fx_r_type) |
| 17853 | && (HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (file_mips_opts.isa))) |
| 17854 | return 0; |
| 17855 | |
| 17856 | /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve |
| 17857 | to a floating-point stub. The same is true for non-R_MIPS16_26 |
| 17858 | relocations against MIPS16 functions; in this case, the stub becomes |
| 17859 | the function's canonical address. |
| 17860 | |
| 17861 | Floating-point stubs are stored in unique .mips16.call.* or |
| 17862 | .mips16.fn.* sections. If a stub T for function F is in section S, |
| 17863 | the first relocation in section S must be against F; this is how the |
| 17864 | linker determines the target function. All relocations that might |
| 17865 | resolve to T must also be against F. We therefore have the following |
| 17866 | restrictions, which are given in an intentionally-redundant way: |
| 17867 | |
| 17868 | 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16 |
| 17869 | symbols. |
| 17870 | |
| 17871 | 2. We cannot reduce a stub's relocations against non-MIPS16 symbols |
| 17872 | if that stub might be used. |
| 17873 | |
| 17874 | 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16 |
| 17875 | symbols. |
| 17876 | |
| 17877 | 4. We cannot reduce a stub's relocations against MIPS16 symbols if |
| 17878 | that stub might be used. |
| 17879 | |
| 17880 | There is a further restriction: |
| 17881 | |
| 17882 | 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or |
| 17883 | R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2, |
| 17884 | R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1, |
| 17885 | R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1) |
| 17886 | against MIPS16 or microMIPS symbols because we need to keep the |
| 17887 | MIPS16 or microMIPS symbol for the purpose of mode mismatch |
| 17888 | detection and JAL or BAL to JALX instruction conversion in the |
| 17889 | linker. |
| 17890 | |
| 17891 | For simplicity, we deal with (3)-(4) by not reducing _any_ relocation |
| 17892 | against a MIPS16 symbol. We deal with (5) by additionally leaving |
| 17893 | alone any jump and branch relocations against a microMIPS symbol. |
| 17894 | |
| 17895 | We deal with (1)-(2) by saying that, if there's a R_MIPS16_26 |
| 17896 | relocation against some symbol R, no relocation against R may be |
| 17897 | reduced. (Note that this deals with (2) as well as (1) because |
| 17898 | relocations against global symbols will never be reduced on ELF |
| 17899 | targets.) This approach is a little simpler than trying to detect |
| 17900 | stub sections, and gives the "all or nothing" per-symbol consistency |
| 17901 | that we have for MIPS16 symbols. */ |
| 17902 | if (fixp->fx_subsy == NULL |
| 17903 | && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy)) |
| 17904 | || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp->fx_addsy)) |
| 17905 | && (jmp_reloc_p (fixp->fx_r_type) |
| 17906 | || b_reloc_p (fixp->fx_r_type))) |
| 17907 | || *symbol_get_tc (fixp->fx_addsy))) |
| 17908 | return 0; |
| 17909 | |
| 17910 | return 1; |
| 17911 | } |
| 17912 | |
| 17913 | /* Translate internal representation of relocation info to BFD target |
| 17914 | format. */ |
| 17915 | |
| 17916 | arelent ** |
| 17917 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
| 17918 | { |
| 17919 | static arelent *retval[4]; |
| 17920 | arelent *reloc; |
| 17921 | bfd_reloc_code_real_type code; |
| 17922 | |
| 17923 | memset (retval, 0, sizeof(retval)); |
| 17924 | reloc = retval[0] = XCNEW (arelent); |
| 17925 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
| 17926 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
| 17927 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
| 17928 | |
| 17929 | if (fixp->fx_pcrel) |
| 17930 | { |
| 17931 | gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 |
| 17932 | || fixp->fx_r_type == BFD_RELOC_MIPS16_16_PCREL_S1 |
| 17933 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 |
| 17934 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 |
| 17935 | || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 |
| 17936 | || fixp->fx_r_type == BFD_RELOC_32_PCREL |
| 17937 | || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 |
| 17938 | || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 |
| 17939 | || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 |
| 17940 | || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 |
| 17941 | || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL |
| 17942 | || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); |
| 17943 | |
| 17944 | /* At this point, fx_addnumber is "symbol offset - pcrel address". |
| 17945 | Relocations want only the symbol offset. */ |
| 17946 | switch (fixp->fx_r_type) |
| 17947 | { |
| 17948 | case BFD_RELOC_MIPS_18_PCREL_S3: |
| 17949 | reloc->addend = fixp->fx_addnumber + (reloc->address & ~7); |
| 17950 | break; |
| 17951 | default: |
| 17952 | reloc->addend = fixp->fx_addnumber + reloc->address; |
| 17953 | break; |
| 17954 | } |
| 17955 | } |
| 17956 | else if (HAVE_IN_PLACE_ADDENDS |
| 17957 | && fixp->fx_r_type == BFD_RELOC_MICROMIPS_JMP |
| 17958 | && (read_compressed_insn (fixp->fx_frag->fr_literal |
| 17959 | + fixp->fx_where, 4) >> 26) == 0x3c) |
| 17960 | { |
| 17961 | /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place |
| 17962 | addend accordingly. */ |
| 17963 | reloc->addend = fixp->fx_addnumber >> 1; |
| 17964 | } |
| 17965 | else |
| 17966 | reloc->addend = fixp->fx_addnumber; |
| 17967 | |
| 17968 | /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable |
| 17969 | entry to be used in the relocation's section offset. */ |
| 17970 | if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
| 17971 | { |
| 17972 | reloc->address = reloc->addend; |
| 17973 | reloc->addend = 0; |
| 17974 | } |
| 17975 | |
| 17976 | code = fixp->fx_r_type; |
| 17977 | |
| 17978 | reloc->howto = bfd_reloc_type_lookup (stdoutput, code); |
| 17979 | if (reloc->howto == NULL) |
| 17980 | { |
| 17981 | as_bad_where (fixp->fx_file, fixp->fx_line, |
| 17982 | _("cannot represent %s relocation in this object file" |
| 17983 | " format"), |
| 17984 | bfd_get_reloc_code_name (code)); |
| 17985 | retval[0] = NULL; |
| 17986 | } |
| 17987 | |
| 17988 | return retval; |
| 17989 | } |
| 17990 | |
| 17991 | /* Relax a machine dependent frag. This returns the amount by which |
| 17992 | the current size of the frag should change. */ |
| 17993 | |
| 17994 | int |
| 17995 | mips_relax_frag (asection *sec, fragS *fragp, long stretch) |
| 17996 | { |
| 17997 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
| 17998 | { |
| 17999 | offsetT old_var = fragp->fr_var; |
| 18000 | |
| 18001 | fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); |
| 18002 | |
| 18003 | return fragp->fr_var - old_var; |
| 18004 | } |
| 18005 | |
| 18006 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
| 18007 | { |
| 18008 | offsetT old_var = fragp->fr_var; |
| 18009 | offsetT new_var = 4; |
| 18010 | |
| 18011 | if (RELAX_MICROMIPS_TYPE (fragp->fr_subtype) != 0) |
| 18012 | new_var = relaxed_micromips_16bit_branch_length (fragp, sec, TRUE); |
| 18013 | if (new_var == 4 && RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype)) |
| 18014 | new_var = relaxed_micromips_32bit_branch_length (fragp, sec, TRUE); |
| 18015 | fragp->fr_var = new_var; |
| 18016 | |
| 18017 | return new_var - old_var; |
| 18018 | } |
| 18019 | |
| 18020 | if (! RELAX_MIPS16_P (fragp->fr_subtype)) |
| 18021 | return 0; |
| 18022 | |
| 18023 | if (!mips16_extended_frag (fragp, sec, stretch)) |
| 18024 | { |
| 18025 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
| 18026 | { |
| 18027 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); |
| 18028 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -6 : -10; |
| 18029 | } |
| 18030 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 18031 | { |
| 18032 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); |
| 18033 | return -2; |
| 18034 | } |
| 18035 | else |
| 18036 | return 0; |
| 18037 | } |
| 18038 | else if (!mips16_macro_frag (fragp, sec, stretch)) |
| 18039 | { |
| 18040 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
| 18041 | { |
| 18042 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype); |
| 18043 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); |
| 18044 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? -4 : -8; |
| 18045 | } |
| 18046 | else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 18047 | { |
| 18048 | fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype); |
| 18049 | return 2; |
| 18050 | } |
| 18051 | else |
| 18052 | return 0; |
| 18053 | } |
| 18054 | else |
| 18055 | { |
| 18056 | if (RELAX_MIPS16_MACRO (fragp->fr_subtype)) |
| 18057 | return 0; |
| 18058 | else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype)) |
| 18059 | { |
| 18060 | fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype); |
| 18061 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); |
| 18062 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 4 : 8; |
| 18063 | } |
| 18064 | else |
| 18065 | { |
| 18066 | fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype); |
| 18067 | return RELAX_MIPS16_E2 (fragp->fr_subtype) ? 6 : 10; |
| 18068 | } |
| 18069 | } |
| 18070 | |
| 18071 | return 0; |
| 18072 | } |
| 18073 | |
| 18074 | /* Convert a machine dependent frag. */ |
| 18075 | |
| 18076 | void |
| 18077 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) |
| 18078 | { |
| 18079 | if (RELAX_BRANCH_P (fragp->fr_subtype)) |
| 18080 | { |
| 18081 | char *buf; |
| 18082 | unsigned long insn; |
| 18083 | expressionS exp; |
| 18084 | fixS *fixp; |
| 18085 | |
| 18086 | buf = fragp->fr_literal + fragp->fr_fix; |
| 18087 | insn = read_insn (buf); |
| 18088 | |
| 18089 | if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype)) |
| 18090 | { |
| 18091 | /* We generate a fixup instead of applying it right now |
| 18092 | because, if there are linker relaxations, we're going to |
| 18093 | need the relocations. */ |
| 18094 | exp.X_op = O_symbol; |
| 18095 | exp.X_add_symbol = fragp->fr_symbol; |
| 18096 | exp.X_add_number = fragp->fr_offset; |
| 18097 | |
| 18098 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
| 18099 | BFD_RELOC_16_PCREL_S2); |
| 18100 | fixp->fx_file = fragp->fr_file; |
| 18101 | fixp->fx_line = fragp->fr_line; |
| 18102 | |
| 18103 | buf = write_insn (buf, insn); |
| 18104 | } |
| 18105 | else |
| 18106 | { |
| 18107 | int i; |
| 18108 | |
| 18109 | as_warn_where (fragp->fr_file, fragp->fr_line, |
| 18110 | _("relaxed out-of-range branch into a jump")); |
| 18111 | |
| 18112 | if (RELAX_BRANCH_UNCOND (fragp->fr_subtype)) |
| 18113 | goto uncond; |
| 18114 | |
| 18115 | if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype)) |
| 18116 | { |
| 18117 | /* Reverse the branch. */ |
| 18118 | switch ((insn >> 28) & 0xf) |
| 18119 | { |
| 18120 | case 4: |
| 18121 | if ((insn & 0xff000000) == 0x47000000 |
| 18122 | || (insn & 0xff600000) == 0x45600000) |
| 18123 | { |
| 18124 | /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition |
| 18125 | reversed by tweaking bit 23. */ |
| 18126 | insn ^= 0x00800000; |
| 18127 | } |
| 18128 | else |
| 18129 | { |
| 18130 | /* bc[0-3][tf]l? instructions can have the condition |
| 18131 | reversed by tweaking a single TF bit, and their |
| 18132 | opcodes all have 0x4???????. */ |
| 18133 | gas_assert ((insn & 0xf3e00000) == 0x41000000); |
| 18134 | insn ^= 0x00010000; |
| 18135 | } |
| 18136 | break; |
| 18137 | |
| 18138 | case 0: |
| 18139 | /* bltz 0x04000000 bgez 0x04010000 |
| 18140 | bltzal 0x04100000 bgezal 0x04110000 */ |
| 18141 | gas_assert ((insn & 0xfc0e0000) == 0x04000000); |
| 18142 | insn ^= 0x00010000; |
| 18143 | break; |
| 18144 | |
| 18145 | case 1: |
| 18146 | /* beq 0x10000000 bne 0x14000000 |
| 18147 | blez 0x18000000 bgtz 0x1c000000 */ |
| 18148 | insn ^= 0x04000000; |
| 18149 | break; |
| 18150 | |
| 18151 | default: |
| 18152 | abort (); |
| 18153 | } |
| 18154 | } |
| 18155 | |
| 18156 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) |
| 18157 | { |
| 18158 | /* Clear the and-link bit. */ |
| 18159 | gas_assert ((insn & 0xfc1c0000) == 0x04100000); |
| 18160 | |
| 18161 | /* bltzal 0x04100000 bgezal 0x04110000 |
| 18162 | bltzall 0x04120000 bgezall 0x04130000 */ |
| 18163 | insn &= ~0x00100000; |
| 18164 | } |
| 18165 | |
| 18166 | /* Branch over the branch (if the branch was likely) or the |
| 18167 | full jump (not likely case). Compute the offset from the |
| 18168 | current instruction to branch to. */ |
| 18169 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) |
| 18170 | i = 16; |
| 18171 | else |
| 18172 | { |
| 18173 | /* How many bytes in instructions we've already emitted? */ |
| 18174 | i = buf - fragp->fr_literal - fragp->fr_fix; |
| 18175 | /* How many bytes in instructions from here to the end? */ |
| 18176 | i = fragp->fr_var - i; |
| 18177 | } |
| 18178 | /* Convert to instruction count. */ |
| 18179 | i >>= 2; |
| 18180 | /* Branch counts from the next instruction. */ |
| 18181 | i--; |
| 18182 | insn |= i; |
| 18183 | /* Branch over the jump. */ |
| 18184 | buf = write_insn (buf, insn); |
| 18185 | |
| 18186 | /* nop */ |
| 18187 | buf = write_insn (buf, 0); |
| 18188 | |
| 18189 | if (RELAX_BRANCH_LIKELY (fragp->fr_subtype)) |
| 18190 | { |
| 18191 | /* beql $0, $0, 2f */ |
| 18192 | insn = 0x50000000; |
| 18193 | /* Compute the PC offset from the current instruction to |
| 18194 | the end of the variable frag. */ |
| 18195 | /* How many bytes in instructions we've already emitted? */ |
| 18196 | i = buf - fragp->fr_literal - fragp->fr_fix; |
| 18197 | /* How many bytes in instructions from here to the end? */ |
| 18198 | i = fragp->fr_var - i; |
| 18199 | /* Convert to instruction count. */ |
| 18200 | i >>= 2; |
| 18201 | /* Don't decrement i, because we want to branch over the |
| 18202 | delay slot. */ |
| 18203 | insn |= i; |
| 18204 | |
| 18205 | buf = write_insn (buf, insn); |
| 18206 | buf = write_insn (buf, 0); |
| 18207 | } |
| 18208 | |
| 18209 | uncond: |
| 18210 | if (!RELAX_BRANCH_PIC (fragp->fr_subtype)) |
| 18211 | { |
| 18212 | /* j or jal. */ |
| 18213 | insn = (RELAX_BRANCH_LINK (fragp->fr_subtype) |
| 18214 | ? 0x0c000000 : 0x08000000); |
| 18215 | exp.X_op = O_symbol; |
| 18216 | exp.X_add_symbol = fragp->fr_symbol; |
| 18217 | exp.X_add_number = fragp->fr_offset; |
| 18218 | |
| 18219 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
| 18220 | FALSE, BFD_RELOC_MIPS_JMP); |
| 18221 | fixp->fx_file = fragp->fr_file; |
| 18222 | fixp->fx_line = fragp->fr_line; |
| 18223 | |
| 18224 | buf = write_insn (buf, insn); |
| 18225 | } |
| 18226 | else |
| 18227 | { |
| 18228 | unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype); |
| 18229 | |
| 18230 | /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */ |
| 18231 | insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000; |
| 18232 | insn |= at << OP_SH_RT; |
| 18233 | exp.X_op = O_symbol; |
| 18234 | exp.X_add_symbol = fragp->fr_symbol; |
| 18235 | exp.X_add_number = fragp->fr_offset; |
| 18236 | |
| 18237 | if (fragp->fr_offset) |
| 18238 | { |
| 18239 | exp.X_add_symbol = make_expr_symbol (&exp); |
| 18240 | exp.X_add_number = 0; |
| 18241 | } |
| 18242 | |
| 18243 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
| 18244 | FALSE, BFD_RELOC_MIPS_GOT16); |
| 18245 | fixp->fx_file = fragp->fr_file; |
| 18246 | fixp->fx_line = fragp->fr_line; |
| 18247 | |
| 18248 | buf = write_insn (buf, insn); |
| 18249 | |
| 18250 | if (mips_opts.isa == ISA_MIPS1) |
| 18251 | /* nop */ |
| 18252 | buf = write_insn (buf, 0); |
| 18253 | |
| 18254 | /* d/addiu $at, $at, <sym> R_MIPS_LO16 */ |
| 18255 | insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000; |
| 18256 | insn |= at << OP_SH_RS | at << OP_SH_RT; |
| 18257 | |
| 18258 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
| 18259 | FALSE, BFD_RELOC_LO16); |
| 18260 | fixp->fx_file = fragp->fr_file; |
| 18261 | fixp->fx_line = fragp->fr_line; |
| 18262 | |
| 18263 | buf = write_insn (buf, insn); |
| 18264 | |
| 18265 | /* j(al)r $at. */ |
| 18266 | if (RELAX_BRANCH_LINK (fragp->fr_subtype)) |
| 18267 | insn = 0x0000f809; |
| 18268 | else |
| 18269 | insn = 0x00000008; |
| 18270 | insn |= at << OP_SH_RS; |
| 18271 | |
| 18272 | buf = write_insn (buf, insn); |
| 18273 | } |
| 18274 | } |
| 18275 | |
| 18276 | fragp->fr_fix += fragp->fr_var; |
| 18277 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
| 18278 | return; |
| 18279 | } |
| 18280 | |
| 18281 | /* Relax microMIPS branches. */ |
| 18282 | if (RELAX_MICROMIPS_P (fragp->fr_subtype)) |
| 18283 | { |
| 18284 | char *buf = fragp->fr_literal + fragp->fr_fix; |
| 18285 | bfd_boolean compact = RELAX_MICROMIPS_COMPACT (fragp->fr_subtype); |
| 18286 | bfd_boolean insn32 = RELAX_MICROMIPS_INSN32 (fragp->fr_subtype); |
| 18287 | bfd_boolean nods = RELAX_MICROMIPS_NODS (fragp->fr_subtype); |
| 18288 | bfd_boolean pic = RELAX_MICROMIPS_PIC (fragp->fr_subtype); |
| 18289 | bfd_boolean al = RELAX_MICROMIPS_LINK (fragp->fr_subtype); |
| 18290 | int type = RELAX_MICROMIPS_TYPE (fragp->fr_subtype); |
| 18291 | bfd_boolean short_ds; |
| 18292 | unsigned long insn; |
| 18293 | expressionS exp; |
| 18294 | fixS *fixp; |
| 18295 | |
| 18296 | exp.X_op = O_symbol; |
| 18297 | exp.X_add_symbol = fragp->fr_symbol; |
| 18298 | exp.X_add_number = fragp->fr_offset; |
| 18299 | |
| 18300 | fragp->fr_fix += fragp->fr_var; |
| 18301 | |
| 18302 | /* Handle 16-bit branches that fit or are forced to fit. */ |
| 18303 | if (type != 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp->fr_subtype)) |
| 18304 | { |
| 18305 | /* We generate a fixup instead of applying it right now, |
| 18306 | because if there is linker relaxation, we're going to |
| 18307 | need the relocations. */ |
| 18308 | if (type == 'D') |
| 18309 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
| 18310 | BFD_RELOC_MICROMIPS_10_PCREL_S1); |
| 18311 | else if (type == 'E') |
| 18312 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, TRUE, |
| 18313 | BFD_RELOC_MICROMIPS_7_PCREL_S1); |
| 18314 | else |
| 18315 | abort (); |
| 18316 | |
| 18317 | fixp->fx_file = fragp->fr_file; |
| 18318 | fixp->fx_line = fragp->fr_line; |
| 18319 | |
| 18320 | /* These relocations can have an addend that won't fit in |
| 18321 | 2 octets. */ |
| 18322 | fixp->fx_no_overflow = 1; |
| 18323 | |
| 18324 | return; |
| 18325 | } |
| 18326 | |
| 18327 | /* Handle 32-bit branches that fit or are forced to fit. */ |
| 18328 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
| 18329 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) |
| 18330 | { |
| 18331 | /* We generate a fixup instead of applying it right now, |
| 18332 | because if there is linker relaxation, we're going to |
| 18333 | need the relocations. */ |
| 18334 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, TRUE, |
| 18335 | BFD_RELOC_MICROMIPS_16_PCREL_S1); |
| 18336 | fixp->fx_file = fragp->fr_file; |
| 18337 | fixp->fx_line = fragp->fr_line; |
| 18338 | |
| 18339 | if (type == 0) |
| 18340 | { |
| 18341 | insn = read_compressed_insn (buf, 4); |
| 18342 | buf += 4; |
| 18343 | |
| 18344 | if (nods) |
| 18345 | { |
| 18346 | /* Check the short-delay-slot bit. */ |
| 18347 | if (!al || (insn & 0x02000000) != 0) |
| 18348 | buf = write_compressed_insn (buf, 0x0c00, 2); |
| 18349 | else |
| 18350 | buf = write_compressed_insn (buf, 0x00000000, 4); |
| 18351 | } |
| 18352 | |
| 18353 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
| 18354 | return; |
| 18355 | } |
| 18356 | } |
| 18357 | |
| 18358 | /* Relax 16-bit branches to 32-bit branches. */ |
| 18359 | if (type != 0) |
| 18360 | { |
| 18361 | insn = read_compressed_insn (buf, 2); |
| 18362 | |
| 18363 | if ((insn & 0xfc00) == 0xcc00) /* b16 */ |
| 18364 | insn = 0x94000000; /* beq */ |
| 18365 | else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */ |
| 18366 | { |
| 18367 | unsigned long regno; |
| 18368 | |
| 18369 | regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD; |
| 18370 | regno = micromips_to_32_reg_d_map [regno]; |
| 18371 | insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */ |
| 18372 | insn |= regno << MICROMIPSOP_SH_RS; |
| 18373 | } |
| 18374 | else |
| 18375 | abort (); |
| 18376 | |
| 18377 | /* Nothing else to do, just write it out. */ |
| 18378 | if (!RELAX_MICROMIPS_RELAX32 (fragp->fr_subtype) |
| 18379 | || !RELAX_MICROMIPS_TOOFAR32 (fragp->fr_subtype)) |
| 18380 | { |
| 18381 | buf = write_compressed_insn (buf, insn, 4); |
| 18382 | if (nods) |
| 18383 | buf = write_compressed_insn (buf, 0x0c00, 2); |
| 18384 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
| 18385 | return; |
| 18386 | } |
| 18387 | } |
| 18388 | else |
| 18389 | insn = read_compressed_insn (buf, 4); |
| 18390 | |
| 18391 | /* Relax 32-bit branches to a sequence of instructions. */ |
| 18392 | as_warn_where (fragp->fr_file, fragp->fr_line, |
| 18393 | _("relaxed out-of-range branch into a jump")); |
| 18394 | |
| 18395 | /* Set the short-delay-slot bit. */ |
| 18396 | short_ds = !al || (insn & 0x02000000) != 0; |
| 18397 | |
| 18398 | if (!RELAX_MICROMIPS_UNCOND (fragp->fr_subtype)) |
| 18399 | { |
| 18400 | symbolS *l; |
| 18401 | |
| 18402 | /* Reverse the branch. */ |
| 18403 | if ((insn & 0xfc000000) == 0x94000000 /* beq */ |
| 18404 | || (insn & 0xfc000000) == 0xb4000000) /* bne */ |
| 18405 | insn ^= 0x20000000; |
| 18406 | else if ((insn & 0xffe00000) == 0x40000000 /* bltz */ |
| 18407 | || (insn & 0xffe00000) == 0x40400000 /* bgez */ |
| 18408 | || (insn & 0xffe00000) == 0x40800000 /* blez */ |
| 18409 | || (insn & 0xffe00000) == 0x40c00000 /* bgtz */ |
| 18410 | || (insn & 0xffe00000) == 0x40a00000 /* bnezc */ |
| 18411 | || (insn & 0xffe00000) == 0x40e00000 /* beqzc */ |
| 18412 | || (insn & 0xffe00000) == 0x40200000 /* bltzal */ |
| 18413 | || (insn & 0xffe00000) == 0x40600000 /* bgezal */ |
| 18414 | || (insn & 0xffe00000) == 0x42200000 /* bltzals */ |
| 18415 | || (insn & 0xffe00000) == 0x42600000) /* bgezals */ |
| 18416 | insn ^= 0x00400000; |
| 18417 | else if ((insn & 0xffe30000) == 0x43800000 /* bc1f */ |
| 18418 | || (insn & 0xffe30000) == 0x43a00000 /* bc1t */ |
| 18419 | || (insn & 0xffe30000) == 0x42800000 /* bc2f */ |
| 18420 | || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ |
| 18421 | insn ^= 0x00200000; |
| 18422 | else if ((insn & 0xff000000) == 0x83000000 /* BZ.df |
| 18423 | BNZ.df */ |
| 18424 | || (insn & 0xff600000) == 0x81600000) /* BZ.V |
| 18425 | BNZ.V */ |
| 18426 | insn ^= 0x00800000; |
| 18427 | else |
| 18428 | abort (); |
| 18429 | |
| 18430 | if (al) |
| 18431 | { |
| 18432 | /* Clear the and-link and short-delay-slot bits. */ |
| 18433 | gas_assert ((insn & 0xfda00000) == 0x40200000); |
| 18434 | |
| 18435 | /* bltzal 0x40200000 bgezal 0x40600000 */ |
| 18436 | /* bltzals 0x42200000 bgezals 0x42600000 */ |
| 18437 | insn &= ~0x02200000; |
| 18438 | } |
| 18439 | |
| 18440 | /* Make a label at the end for use with the branch. */ |
| 18441 | l = symbol_new (micromips_label_name (), asec, fragp->fr_fix, fragp); |
| 18442 | micromips_label_inc (); |
| 18443 | S_SET_OTHER (l, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l))); |
| 18444 | |
| 18445 | /* Refer to it. */ |
| 18446 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, l, 0, TRUE, |
| 18447 | BFD_RELOC_MICROMIPS_16_PCREL_S1); |
| 18448 | fixp->fx_file = fragp->fr_file; |
| 18449 | fixp->fx_line = fragp->fr_line; |
| 18450 | |
| 18451 | /* Branch over the jump. */ |
| 18452 | buf = write_compressed_insn (buf, insn, 4); |
| 18453 | |
| 18454 | if (!compact) |
| 18455 | { |
| 18456 | /* nop */ |
| 18457 | if (insn32) |
| 18458 | buf = write_compressed_insn (buf, 0x00000000, 4); |
| 18459 | else |
| 18460 | buf = write_compressed_insn (buf, 0x0c00, 2); |
| 18461 | } |
| 18462 | } |
| 18463 | |
| 18464 | if (!pic) |
| 18465 | { |
| 18466 | unsigned long jal = (short_ds || nods |
| 18467 | ? 0x74000000 : 0xf4000000); /* jal/s */ |
| 18468 | |
| 18469 | /* j/jal/jals <sym> R_MICROMIPS_26_S1 */ |
| 18470 | insn = al ? jal : 0xd4000000; |
| 18471 | |
| 18472 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
| 18473 | BFD_RELOC_MICROMIPS_JMP); |
| 18474 | fixp->fx_file = fragp->fr_file; |
| 18475 | fixp->fx_line = fragp->fr_line; |
| 18476 | |
| 18477 | buf = write_compressed_insn (buf, insn, 4); |
| 18478 | |
| 18479 | if (compact || nods) |
| 18480 | { |
| 18481 | /* nop */ |
| 18482 | if (insn32) |
| 18483 | buf = write_compressed_insn (buf, 0x00000000, 4); |
| 18484 | else |
| 18485 | buf = write_compressed_insn (buf, 0x0c00, 2); |
| 18486 | } |
| 18487 | } |
| 18488 | else |
| 18489 | { |
| 18490 | unsigned long at = RELAX_MICROMIPS_AT (fragp->fr_subtype); |
| 18491 | |
| 18492 | /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */ |
| 18493 | insn = HAVE_64BIT_ADDRESSES ? 0xdc1c0000 : 0xfc1c0000; |
| 18494 | insn |= at << MICROMIPSOP_SH_RT; |
| 18495 | |
| 18496 | if (exp.X_add_number) |
| 18497 | { |
| 18498 | exp.X_add_symbol = make_expr_symbol (&exp); |
| 18499 | exp.X_add_number = 0; |
| 18500 | } |
| 18501 | |
| 18502 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
| 18503 | BFD_RELOC_MICROMIPS_GOT16); |
| 18504 | fixp->fx_file = fragp->fr_file; |
| 18505 | fixp->fx_line = fragp->fr_line; |
| 18506 | |
| 18507 | buf = write_compressed_insn (buf, insn, 4); |
| 18508 | |
| 18509 | /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */ |
| 18510 | insn = HAVE_64BIT_ADDRESSES ? 0x5c000000 : 0x30000000; |
| 18511 | insn |= at << MICROMIPSOP_SH_RT | at << MICROMIPSOP_SH_RS; |
| 18512 | |
| 18513 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, FALSE, |
| 18514 | BFD_RELOC_MICROMIPS_LO16); |
| 18515 | fixp->fx_file = fragp->fr_file; |
| 18516 | fixp->fx_line = fragp->fr_line; |
| 18517 | |
| 18518 | buf = write_compressed_insn (buf, insn, 4); |
| 18519 | |
| 18520 | if (insn32) |
| 18521 | { |
| 18522 | /* jr/jalr $at */ |
| 18523 | insn = 0x00000f3c | (al ? RA : ZERO) << MICROMIPSOP_SH_RT; |
| 18524 | insn |= at << MICROMIPSOP_SH_RS; |
| 18525 | |
| 18526 | buf = write_compressed_insn (buf, insn, 4); |
| 18527 | |
| 18528 | if (compact || nods) |
| 18529 | /* nop */ |
| 18530 | buf = write_compressed_insn (buf, 0x00000000, 4); |
| 18531 | } |
| 18532 | else |
| 18533 | { |
| 18534 | /* jr/jrc/jalr/jalrs $at */ |
| 18535 | unsigned long jalr = short_ds ? 0x45e0 : 0x45c0; /* jalr/s */ |
| 18536 | unsigned long jr = compact || nods ? 0x45a0 : 0x4580; /* jr/c */ |
| 18537 | |
| 18538 | insn = al ? jalr : jr; |
| 18539 | insn |= at << MICROMIPSOP_SH_MJ; |
| 18540 | |
| 18541 | buf = write_compressed_insn (buf, insn, 2); |
| 18542 | if (al && nods) |
| 18543 | { |
| 18544 | /* nop */ |
| 18545 | if (short_ds) |
| 18546 | buf = write_compressed_insn (buf, 0x0c00, 2); |
| 18547 | else |
| 18548 | buf = write_compressed_insn (buf, 0x00000000, 4); |
| 18549 | } |
| 18550 | } |
| 18551 | } |
| 18552 | |
| 18553 | gas_assert (buf == fragp->fr_literal + fragp->fr_fix); |
| 18554 | return; |
| 18555 | } |
| 18556 | |
| 18557 | if (RELAX_MIPS16_P (fragp->fr_subtype)) |
| 18558 | { |
| 18559 | int type; |
| 18560 | const struct mips_int_operand *operand; |
| 18561 | offsetT val; |
| 18562 | char *buf; |
| 18563 | unsigned int user_length; |
| 18564 | bfd_boolean need_reloc; |
| 18565 | unsigned long insn; |
| 18566 | bfd_boolean mac; |
| 18567 | bfd_boolean ext; |
| 18568 | segT symsec; |
| 18569 | |
| 18570 | type = RELAX_MIPS16_TYPE (fragp->fr_subtype); |
| 18571 | operand = mips16_immed_operand (type, FALSE); |
| 18572 | |
| 18573 | mac = RELAX_MIPS16_MACRO (fragp->fr_subtype); |
| 18574 | ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype); |
| 18575 | val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset; |
| 18576 | |
| 18577 | symsec = S_GET_SEGMENT (fragp->fr_symbol); |
| 18578 | need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE) |
| 18579 | || (operand->root.type == OP_PCREL && !mac |
| 18580 | ? asec != symsec |
| 18581 | : !bfd_is_abs_section (symsec))); |
| 18582 | |
| 18583 | if (operand->root.type == OP_PCREL && !mac) |
| 18584 | { |
| 18585 | const struct mips_pcrel_operand *pcrel_op; |
| 18586 | |
| 18587 | pcrel_op = (const struct mips_pcrel_operand *) operand; |
| 18588 | |
| 18589 | if (pcrel_op->include_isa_bit && !need_reloc) |
| 18590 | { |
| 18591 | if (!ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp->fr_symbol))) |
| 18592 | as_bad_where (fragp->fr_file, fragp->fr_line, |
| 18593 | _("branch to a symbol in another ISA mode")); |
| 18594 | else if ((fragp->fr_offset & 0x1) != 0) |
| 18595 | as_bad_where (fragp->fr_file, fragp->fr_line, |
| 18596 | _("branch to misaligned address (0x%lx)"), |
| 18597 | (long) val); |
| 18598 | } |
| 18599 | |
| 18600 | val = mips16_pcrel_val (fragp, pcrel_op, val, 0); |
| 18601 | |
| 18602 | /* Make sure the section winds up with the alignment we have |
| 18603 | assumed. */ |
| 18604 | if (operand->shift > 0) |
| 18605 | record_alignment (asec, operand->shift); |
| 18606 | } |
| 18607 | |
| 18608 | if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype) |
| 18609 | || RELAX_MIPS16_DSLOT (fragp->fr_subtype)) |
| 18610 | { |
| 18611 | if (mac) |
| 18612 | as_warn_where (fragp->fr_file, fragp->fr_line, |
| 18613 | _("macro instruction expanded into multiple " |
| 18614 | "instructions in a branch delay slot")); |
| 18615 | else if (ext) |
| 18616 | as_warn_where (fragp->fr_file, fragp->fr_line, |
| 18617 | _("extended instruction in a branch delay slot")); |
| 18618 | } |
| 18619 | else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac) |
| 18620 | as_warn_where (fragp->fr_file, fragp->fr_line, |
| 18621 | _("macro instruction expanded into multiple " |
| 18622 | "instructions")); |
| 18623 | |
| 18624 | buf = fragp->fr_literal + fragp->fr_fix; |
| 18625 | |
| 18626 | insn = read_compressed_insn (buf, 2); |
| 18627 | if (ext) |
| 18628 | insn |= MIPS16_EXTEND; |
| 18629 | |
| 18630 | if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype)) |
| 18631 | user_length = 4; |
| 18632 | else if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype)) |
| 18633 | user_length = 2; |
| 18634 | else |
| 18635 | user_length = 0; |
| 18636 | |
| 18637 | if (mac) |
| 18638 | { |
| 18639 | unsigned long reg; |
| 18640 | unsigned long new; |
| 18641 | unsigned long op; |
| 18642 | bfd_boolean e2; |
| 18643 | |
| 18644 | gas_assert (type == 'A' || type == 'B' || type == 'E'); |
| 18645 | gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype)); |
| 18646 | |
| 18647 | e2 = RELAX_MIPS16_E2 (fragp->fr_subtype); |
| 18648 | |
| 18649 | if (need_reloc) |
| 18650 | { |
| 18651 | fixS *fixp; |
| 18652 | |
| 18653 | gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype)); |
| 18654 | |
| 18655 | fixp = fix_new (fragp, buf - fragp->fr_literal, 4, |
| 18656 | fragp->fr_symbol, fragp->fr_offset, |
| 18657 | FALSE, BFD_RELOC_MIPS16_HI16_S); |
| 18658 | fixp->fx_file = fragp->fr_file; |
| 18659 | fixp->fx_line = fragp->fr_line; |
| 18660 | |
| 18661 | fixp = fix_new (fragp, buf - fragp->fr_literal + (e2 ? 4 : 8), 4, |
| 18662 | fragp->fr_symbol, fragp->fr_offset, |
| 18663 | FALSE, BFD_RELOC_MIPS16_LO16); |
| 18664 | fixp->fx_file = fragp->fr_file; |
| 18665 | fixp->fx_line = fragp->fr_line; |
| 18666 | |
| 18667 | val = 0; |
| 18668 | } |
| 18669 | |
| 18670 | switch (insn & 0xf800) |
| 18671 | { |
| 18672 | case 0x0800: /* ADDIU */ |
| 18673 | reg = (insn >> 8) & 0x7; |
| 18674 | op = 0xf0004800 | (reg << 8); |
| 18675 | break; |
| 18676 | case 0xb000: /* LW */ |
| 18677 | reg = (insn >> 8) & 0x7; |
| 18678 | op = 0xf0009800 | (reg << 8) | (reg << 5); |
| 18679 | break; |
| 18680 | case 0xf800: /* I64 */ |
| 18681 | reg = (insn >> 5) & 0x7; |
| 18682 | switch (insn & 0x0700) |
| 18683 | { |
| 18684 | case 0x0400: /* LD */ |
| 18685 | op = 0xf0003800 | (reg << 8) | (reg << 5); |
| 18686 | break; |
| 18687 | case 0x0600: /* DADDIU */ |
| 18688 | op = 0xf000fd00 | (reg << 5); |
| 18689 | break; |
| 18690 | default: |
| 18691 | abort (); |
| 18692 | } |
| 18693 | break; |
| 18694 | default: |
| 18695 | abort (); |
| 18696 | } |
| 18697 | |
| 18698 | new = (e2 ? 0xf0006820 : 0xf0006800) | (reg << 8); /* LUI/LI */ |
| 18699 | new |= mips16_immed_extend ((val + 0x8000) >> 16, 16); |
| 18700 | buf = write_compressed_insn (buf, new, 4); |
| 18701 | if (!e2) |
| 18702 | { |
| 18703 | new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */ |
| 18704 | buf = write_compressed_insn (buf, new, 4); |
| 18705 | } |
| 18706 | op |= mips16_immed_extend (val, 16); |
| 18707 | buf = write_compressed_insn (buf, op, 4); |
| 18708 | |
| 18709 | fragp->fr_fix += e2 ? 8 : 12; |
| 18710 | } |
| 18711 | else |
| 18712 | { |
| 18713 | unsigned int length = ext ? 4 : 2; |
| 18714 | |
| 18715 | if (need_reloc) |
| 18716 | { |
| 18717 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
| 18718 | expressionS exp; |
| 18719 | fixS *fixp; |
| 18720 | |
| 18721 | switch (type) |
| 18722 | { |
| 18723 | case 'p': |
| 18724 | case 'q': |
| 18725 | reloc = BFD_RELOC_MIPS16_16_PCREL_S1; |
| 18726 | break; |
| 18727 | default: |
| 18728 | break; |
| 18729 | } |
| 18730 | if (mac || reloc == BFD_RELOC_NONE) |
| 18731 | as_bad_where (fragp->fr_file, fragp->fr_line, |
| 18732 | _("unsupported relocation")); |
| 18733 | else if (ext) |
| 18734 | { |
| 18735 | exp.X_op = O_symbol; |
| 18736 | exp.X_add_symbol = fragp->fr_symbol; |
| 18737 | exp.X_add_number = fragp->fr_offset; |
| 18738 | |
| 18739 | fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, |
| 18740 | TRUE, reloc); |
| 18741 | |
| 18742 | fixp->fx_file = fragp->fr_file; |
| 18743 | fixp->fx_line = fragp->fr_line; |
| 18744 | } |
| 18745 | else |
| 18746 | as_bad_where (fragp->fr_file, fragp->fr_line, |
| 18747 | _("invalid unextended operand value")); |
| 18748 | } |
| 18749 | else |
| 18750 | mips16_immed (fragp->fr_file, fragp->fr_line, type, |
| 18751 | BFD_RELOC_UNUSED, val, user_length, &insn); |
| 18752 | |
| 18753 | gas_assert (mips16_opcode_length (insn) == length); |
| 18754 | write_compressed_insn (buf, insn, length); |
| 18755 | fragp->fr_fix += length; |
| 18756 | } |
| 18757 | } |
| 18758 | else |
| 18759 | { |
| 18760 | relax_substateT subtype = fragp->fr_subtype; |
| 18761 | bfd_boolean second_longer = (subtype & RELAX_SECOND_LONGER) != 0; |
| 18762 | bfd_boolean use_second = (subtype & RELAX_USE_SECOND) != 0; |
| 18763 | int first, second; |
| 18764 | fixS *fixp; |
| 18765 | |
| 18766 | first = RELAX_FIRST (subtype); |
| 18767 | second = RELAX_SECOND (subtype); |
| 18768 | fixp = (fixS *) fragp->fr_opcode; |
| 18769 | |
| 18770 | /* If the delay slot chosen does not match the size of the instruction, |
| 18771 | then emit a warning. */ |
| 18772 | if ((!use_second && (subtype & RELAX_DELAY_SLOT_SIZE_FIRST) != 0) |
| 18773 | || (use_second && (subtype & RELAX_DELAY_SLOT_SIZE_SECOND) != 0)) |
| 18774 | { |
| 18775 | relax_substateT s; |
| 18776 | const char *msg; |
| 18777 | |
| 18778 | s = subtype & (RELAX_DELAY_SLOT_16BIT |
| 18779 | | RELAX_DELAY_SLOT_SIZE_FIRST |
| 18780 | | RELAX_DELAY_SLOT_SIZE_SECOND); |
| 18781 | msg = macro_warning (s); |
| 18782 | if (msg != NULL) |
| 18783 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
| 18784 | subtype &= ~s; |
| 18785 | } |
| 18786 | |
| 18787 | /* Possibly emit a warning if we've chosen the longer option. */ |
| 18788 | if (use_second == second_longer) |
| 18789 | { |
| 18790 | relax_substateT s; |
| 18791 | const char *msg; |
| 18792 | |
| 18793 | s = (subtype |
| 18794 | & (RELAX_SECOND_LONGER | RELAX_NOMACRO | RELAX_DELAY_SLOT)); |
| 18795 | msg = macro_warning (s); |
| 18796 | if (msg != NULL) |
| 18797 | as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg); |
| 18798 | subtype &= ~s; |
| 18799 | } |
| 18800 | |
| 18801 | /* Go through all the fixups for the first sequence. Disable them |
| 18802 | (by marking them as done) if we're going to use the second |
| 18803 | sequence instead. */ |
| 18804 | while (fixp |
| 18805 | && fixp->fx_frag == fragp |
| 18806 | && fixp->fx_where < fragp->fr_fix - second) |
| 18807 | { |
| 18808 | if (subtype & RELAX_USE_SECOND) |
| 18809 | fixp->fx_done = 1; |
| 18810 | fixp = fixp->fx_next; |
| 18811 | } |
| 18812 | |
| 18813 | /* Go through the fixups for the second sequence. Disable them if |
| 18814 | we're going to use the first sequence, otherwise adjust their |
| 18815 | addresses to account for the relaxation. */ |
| 18816 | while (fixp && fixp->fx_frag == fragp) |
| 18817 | { |
| 18818 | if (subtype & RELAX_USE_SECOND) |
| 18819 | fixp->fx_where -= first; |
| 18820 | else |
| 18821 | fixp->fx_done = 1; |
| 18822 | fixp = fixp->fx_next; |
| 18823 | } |
| 18824 | |
| 18825 | /* Now modify the frag contents. */ |
| 18826 | if (subtype & RELAX_USE_SECOND) |
| 18827 | { |
| 18828 | char *start; |
| 18829 | |
| 18830 | start = fragp->fr_literal + fragp->fr_fix - first - second; |
| 18831 | memmove (start, start + first, second); |
| 18832 | fragp->fr_fix -= first; |
| 18833 | } |
| 18834 | else |
| 18835 | fragp->fr_fix -= second; |
| 18836 | } |
| 18837 | } |
| 18838 | |
| 18839 | /* This function is called after the relocs have been generated. |
| 18840 | We've been storing mips16 text labels as odd. Here we convert them |
| 18841 | back to even for the convenience of the debugger. */ |
| 18842 | |
| 18843 | void |
| 18844 | mips_frob_file_after_relocs (void) |
| 18845 | { |
| 18846 | asymbol **syms; |
| 18847 | unsigned int count, i; |
| 18848 | |
| 18849 | syms = bfd_get_outsymbols (stdoutput); |
| 18850 | count = bfd_get_symcount (stdoutput); |
| 18851 | for (i = 0; i < count; i++, syms++) |
| 18852 | if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms)->internal_elf_sym.st_other) |
| 18853 | && ((*syms)->value & 1) != 0) |
| 18854 | { |
| 18855 | (*syms)->value &= ~1; |
| 18856 | /* If the symbol has an odd size, it was probably computed |
| 18857 | incorrectly, so adjust that as well. */ |
| 18858 | if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0) |
| 18859 | ++elf_symbol (*syms)->internal_elf_sym.st_size; |
| 18860 | } |
| 18861 | } |
| 18862 | |
| 18863 | /* This function is called whenever a label is defined, including fake |
| 18864 | labels instantiated off the dot special symbol. It is used when |
| 18865 | handling branch delays; if a branch has a label, we assume we cannot |
| 18866 | move it. This also bumps the value of the symbol by 1 in compressed |
| 18867 | code. */ |
| 18868 | |
| 18869 | static void |
| 18870 | mips_record_label (symbolS *sym) |
| 18871 | { |
| 18872 | segment_info_type *si = seg_info (now_seg); |
| 18873 | struct insn_label_list *l; |
| 18874 | |
| 18875 | if (free_insn_labels == NULL) |
| 18876 | l = XNEW (struct insn_label_list); |
| 18877 | else |
| 18878 | { |
| 18879 | l = free_insn_labels; |
| 18880 | free_insn_labels = l->next; |
| 18881 | } |
| 18882 | |
| 18883 | l->label = sym; |
| 18884 | l->next = si->label_list; |
| 18885 | si->label_list = l; |
| 18886 | } |
| 18887 | |
| 18888 | /* This function is called as tc_frob_label() whenever a label is defined |
| 18889 | and adds a DWARF-2 record we only want for true labels. */ |
| 18890 | |
| 18891 | void |
| 18892 | mips_define_label (symbolS *sym) |
| 18893 | { |
| 18894 | mips_record_label (sym); |
| 18895 | dwarf2_emit_label (sym); |
| 18896 | } |
| 18897 | |
| 18898 | /* This function is called by tc_new_dot_label whenever a new dot symbol |
| 18899 | is defined. */ |
| 18900 | |
| 18901 | void |
| 18902 | mips_add_dot_label (symbolS *sym) |
| 18903 | { |
| 18904 | mips_record_label (sym); |
| 18905 | if (mips_assembling_insn && HAVE_CODE_COMPRESSION) |
| 18906 | mips_compressed_mark_label (sym); |
| 18907 | } |
| 18908 | \f |
| 18909 | /* Converting ASE flags from internal to .MIPS.abiflags values. */ |
| 18910 | static unsigned int |
| 18911 | mips_convert_ase_flags (int ase) |
| 18912 | { |
| 18913 | unsigned int ext_ases = 0; |
| 18914 | |
| 18915 | if (ase & ASE_DSP) |
| 18916 | ext_ases |= AFL_ASE_DSP; |
| 18917 | if (ase & ASE_DSPR2) |
| 18918 | ext_ases |= AFL_ASE_DSPR2; |
| 18919 | if (ase & ASE_DSPR3) |
| 18920 | ext_ases |= AFL_ASE_DSPR3; |
| 18921 | if (ase & ASE_EVA) |
| 18922 | ext_ases |= AFL_ASE_EVA; |
| 18923 | if (ase & ASE_MCU) |
| 18924 | ext_ases |= AFL_ASE_MCU; |
| 18925 | if (ase & ASE_MDMX) |
| 18926 | ext_ases |= AFL_ASE_MDMX; |
| 18927 | if (ase & ASE_MIPS3D) |
| 18928 | ext_ases |= AFL_ASE_MIPS3D; |
| 18929 | if (ase & ASE_MT) |
| 18930 | ext_ases |= AFL_ASE_MT; |
| 18931 | if (ase & ASE_SMARTMIPS) |
| 18932 | ext_ases |= AFL_ASE_SMARTMIPS; |
| 18933 | if (ase & ASE_VIRT) |
| 18934 | ext_ases |= AFL_ASE_VIRT; |
| 18935 | if (ase & ASE_MSA) |
| 18936 | ext_ases |= AFL_ASE_MSA; |
| 18937 | if (ase & ASE_XPA) |
| 18938 | ext_ases |= AFL_ASE_XPA; |
| 18939 | if (ase & ASE_MIPS16E2) |
| 18940 | ext_ases |= file_ase_mips16 ? AFL_ASE_MIPS16E2 : 0; |
| 18941 | |
| 18942 | return ext_ases; |
| 18943 | } |
| 18944 | /* Some special processing for a MIPS ELF file. */ |
| 18945 | |
| 18946 | void |
| 18947 | mips_elf_final_processing (void) |
| 18948 | { |
| 18949 | int fpabi; |
| 18950 | Elf_Internal_ABIFlags_v0 flags; |
| 18951 | |
| 18952 | flags.version = 0; |
| 18953 | flags.isa_rev = 0; |
| 18954 | switch (file_mips_opts.isa) |
| 18955 | { |
| 18956 | case INSN_ISA1: |
| 18957 | flags.isa_level = 1; |
| 18958 | break; |
| 18959 | case INSN_ISA2: |
| 18960 | flags.isa_level = 2; |
| 18961 | break; |
| 18962 | case INSN_ISA3: |
| 18963 | flags.isa_level = 3; |
| 18964 | break; |
| 18965 | case INSN_ISA4: |
| 18966 | flags.isa_level = 4; |
| 18967 | break; |
| 18968 | case INSN_ISA5: |
| 18969 | flags.isa_level = 5; |
| 18970 | break; |
| 18971 | case INSN_ISA32: |
| 18972 | flags.isa_level = 32; |
| 18973 | flags.isa_rev = 1; |
| 18974 | break; |
| 18975 | case INSN_ISA32R2: |
| 18976 | flags.isa_level = 32; |
| 18977 | flags.isa_rev = 2; |
| 18978 | break; |
| 18979 | case INSN_ISA32R3: |
| 18980 | flags.isa_level = 32; |
| 18981 | flags.isa_rev = 3; |
| 18982 | break; |
| 18983 | case INSN_ISA32R5: |
| 18984 | flags.isa_level = 32; |
| 18985 | flags.isa_rev = 5; |
| 18986 | break; |
| 18987 | case INSN_ISA32R6: |
| 18988 | flags.isa_level = 32; |
| 18989 | flags.isa_rev = 6; |
| 18990 | break; |
| 18991 | case INSN_ISA64: |
| 18992 | flags.isa_level = 64; |
| 18993 | flags.isa_rev = 1; |
| 18994 | break; |
| 18995 | case INSN_ISA64R2: |
| 18996 | flags.isa_level = 64; |
| 18997 | flags.isa_rev = 2; |
| 18998 | break; |
| 18999 | case INSN_ISA64R3: |
| 19000 | flags.isa_level = 64; |
| 19001 | flags.isa_rev = 3; |
| 19002 | break; |
| 19003 | case INSN_ISA64R5: |
| 19004 | flags.isa_level = 64; |
| 19005 | flags.isa_rev = 5; |
| 19006 | break; |
| 19007 | case INSN_ISA64R6: |
| 19008 | flags.isa_level = 64; |
| 19009 | flags.isa_rev = 6; |
| 19010 | break; |
| 19011 | } |
| 19012 | |
| 19013 | flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; |
| 19014 | flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE |
| 19015 | : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 |
| 19016 | : (file_mips_opts.fp == 64) ? AFL_REG_64 |
| 19017 | : AFL_REG_32; |
| 19018 | flags.cpr2_size = AFL_REG_NONE; |
| 19019 | flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
| 19020 | Tag_GNU_MIPS_ABI_FP); |
| 19021 | flags.isa_ext = bfd_mips_isa_ext (stdoutput); |
| 19022 | flags.ases = mips_convert_ase_flags (file_mips_opts.ase); |
| 19023 | if (file_ase_mips16) |
| 19024 | flags.ases |= AFL_ASE_MIPS16; |
| 19025 | if (file_ase_micromips) |
| 19026 | flags.ases |= AFL_ASE_MICROMIPS; |
| 19027 | flags.flags1 = 0; |
| 19028 | if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) |
| 19029 | || file_mips_opts.fp == 64) |
| 19030 | && file_mips_opts.oddspreg) |
| 19031 | flags.flags1 |= AFL_FLAGS1_ODDSPREG; |
| 19032 | flags.flags2 = 0; |
| 19033 | |
| 19034 | bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, |
| 19035 | ((Elf_External_ABIFlags_v0 *) |
| 19036 | mips_flags_frag)); |
| 19037 | |
| 19038 | /* Write out the register information. */ |
| 19039 | if (mips_abi != N64_ABI) |
| 19040 | { |
| 19041 | Elf32_RegInfo s; |
| 19042 | |
| 19043 | s.ri_gprmask = mips_gprmask; |
| 19044 | s.ri_cprmask[0] = mips_cprmask[0]; |
| 19045 | s.ri_cprmask[1] = mips_cprmask[1]; |
| 19046 | s.ri_cprmask[2] = mips_cprmask[2]; |
| 19047 | s.ri_cprmask[3] = mips_cprmask[3]; |
| 19048 | /* The gp_value field is set by the MIPS ELF backend. */ |
| 19049 | |
| 19050 | bfd_mips_elf32_swap_reginfo_out (stdoutput, &s, |
| 19051 | ((Elf32_External_RegInfo *) |
| 19052 | mips_regmask_frag)); |
| 19053 | } |
| 19054 | else |
| 19055 | { |
| 19056 | Elf64_Internal_RegInfo s; |
| 19057 | |
| 19058 | s.ri_gprmask = mips_gprmask; |
| 19059 | s.ri_pad = 0; |
| 19060 | s.ri_cprmask[0] = mips_cprmask[0]; |
| 19061 | s.ri_cprmask[1] = mips_cprmask[1]; |
| 19062 | s.ri_cprmask[2] = mips_cprmask[2]; |
| 19063 | s.ri_cprmask[3] = mips_cprmask[3]; |
| 19064 | /* The gp_value field is set by the MIPS ELF backend. */ |
| 19065 | |
| 19066 | bfd_mips_elf64_swap_reginfo_out (stdoutput, &s, |
| 19067 | ((Elf64_External_RegInfo *) |
| 19068 | mips_regmask_frag)); |
| 19069 | } |
| 19070 | |
| 19071 | /* Set the MIPS ELF flag bits. FIXME: There should probably be some |
| 19072 | sort of BFD interface for this. */ |
| 19073 | if (mips_any_noreorder) |
| 19074 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER; |
| 19075 | if (mips_pic != NO_PIC) |
| 19076 | { |
| 19077 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC; |
| 19078 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
| 19079 | } |
| 19080 | if (mips_abicalls) |
| 19081 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC; |
| 19082 | |
| 19083 | /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags |
| 19084 | defined at present; this might need to change in future. */ |
| 19085 | if (file_ase_mips16) |
| 19086 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; |
| 19087 | if (file_ase_micromips) |
| 19088 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; |
| 19089 | if (file_mips_opts.ase & ASE_MDMX) |
| 19090 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; |
| 19091 | |
| 19092 | /* Set the MIPS ELF ABI flags. */ |
| 19093 | if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32) |
| 19094 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32; |
| 19095 | else if (mips_abi == O64_ABI) |
| 19096 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; |
| 19097 | else if (mips_abi == EABI_ABI) |
| 19098 | { |
| 19099 | if (file_mips_opts.gp == 64) |
| 19100 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; |
| 19101 | else |
| 19102 | elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; |
| 19103 | } |
| 19104 | else if (mips_abi == N32_ABI) |
| 19105 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2; |
| 19106 | |
| 19107 | /* Nothing to do for N64_ABI. */ |
| 19108 | |
| 19109 | if (mips_32bitmode) |
| 19110 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; |
| 19111 | |
| 19112 | if (mips_nan2008 == 1) |
| 19113 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; |
| 19114 | |
| 19115 | /* 32 bit code with 64 bit FP registers. */ |
| 19116 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
| 19117 | Tag_GNU_MIPS_ABI_FP); |
| 19118 | if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) |
| 19119 | elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; |
| 19120 | } |
| 19121 | \f |
| 19122 | typedef struct proc { |
| 19123 | symbolS *func_sym; |
| 19124 | symbolS *func_end_sym; |
| 19125 | unsigned long reg_mask; |
| 19126 | unsigned long reg_offset; |
| 19127 | unsigned long fpreg_mask; |
| 19128 | unsigned long fpreg_offset; |
| 19129 | unsigned long frame_offset; |
| 19130 | unsigned long frame_reg; |
| 19131 | unsigned long pc_reg; |
| 19132 | } procS; |
| 19133 | |
| 19134 | static procS cur_proc; |
| 19135 | static procS *cur_proc_ptr; |
| 19136 | static int numprocs; |
| 19137 | |
| 19138 | /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop |
| 19139 | as "2", and a normal nop as "0". */ |
| 19140 | |
| 19141 | #define NOP_OPCODE_MIPS 0 |
| 19142 | #define NOP_OPCODE_MIPS16 1 |
| 19143 | #define NOP_OPCODE_MICROMIPS 2 |
| 19144 | |
| 19145 | char |
| 19146 | mips_nop_opcode (void) |
| 19147 | { |
| 19148 | if (seg_info (now_seg)->tc_segment_info_data.micromips) |
| 19149 | return NOP_OPCODE_MICROMIPS; |
| 19150 | else if (seg_info (now_seg)->tc_segment_info_data.mips16) |
| 19151 | return NOP_OPCODE_MIPS16; |
| 19152 | else |
| 19153 | return NOP_OPCODE_MIPS; |
| 19154 | } |
| 19155 | |
| 19156 | /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use |
| 19157 | 32-bit microMIPS NOPs here (if applicable). */ |
| 19158 | |
| 19159 | void |
| 19160 | mips_handle_align (fragS *fragp) |
| 19161 | { |
| 19162 | char nop_opcode; |
| 19163 | char *p; |
| 19164 | int bytes, size, excess; |
| 19165 | valueT opcode; |
| 19166 | |
| 19167 | if (fragp->fr_type != rs_align_code) |
| 19168 | return; |
| 19169 | |
| 19170 | p = fragp->fr_literal + fragp->fr_fix; |
| 19171 | nop_opcode = *p; |
| 19172 | switch (nop_opcode) |
| 19173 | { |
| 19174 | case NOP_OPCODE_MICROMIPS: |
| 19175 | opcode = micromips_nop32_insn.insn_opcode; |
| 19176 | size = 4; |
| 19177 | break; |
| 19178 | case NOP_OPCODE_MIPS16: |
| 19179 | opcode = mips16_nop_insn.insn_opcode; |
| 19180 | size = 2; |
| 19181 | break; |
| 19182 | case NOP_OPCODE_MIPS: |
| 19183 | default: |
| 19184 | opcode = nop_insn.insn_opcode; |
| 19185 | size = 4; |
| 19186 | break; |
| 19187 | } |
| 19188 | |
| 19189 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; |
| 19190 | excess = bytes % size; |
| 19191 | |
| 19192 | /* Handle the leading part if we're not inserting a whole number of |
| 19193 | instructions, and make it the end of the fixed part of the frag. |
| 19194 | Try to fit in a short microMIPS NOP if applicable and possible, |
| 19195 | and use zeroes otherwise. */ |
| 19196 | gas_assert (excess < 4); |
| 19197 | fragp->fr_fix += excess; |
| 19198 | switch (excess) |
| 19199 | { |
| 19200 | case 3: |
| 19201 | *p++ = '\0'; |
| 19202 | /* Fall through. */ |
| 19203 | case 2: |
| 19204 | if (nop_opcode == NOP_OPCODE_MICROMIPS && !mips_opts.insn32) |
| 19205 | { |
| 19206 | p = write_compressed_insn (p, micromips_nop16_insn.insn_opcode, 2); |
| 19207 | break; |
| 19208 | } |
| 19209 | *p++ = '\0'; |
| 19210 | /* Fall through. */ |
| 19211 | case 1: |
| 19212 | *p++ = '\0'; |
| 19213 | /* Fall through. */ |
| 19214 | case 0: |
| 19215 | break; |
| 19216 | } |
| 19217 | |
| 19218 | md_number_to_chars (p, opcode, size); |
| 19219 | fragp->fr_var = size; |
| 19220 | } |
| 19221 | |
| 19222 | static long |
| 19223 | get_number (void) |
| 19224 | { |
| 19225 | int negative = 0; |
| 19226 | long val = 0; |
| 19227 | |
| 19228 | if (*input_line_pointer == '-') |
| 19229 | { |
| 19230 | ++input_line_pointer; |
| 19231 | negative = 1; |
| 19232 | } |
| 19233 | if (!ISDIGIT (*input_line_pointer)) |
| 19234 | as_bad (_("expected simple number")); |
| 19235 | if (input_line_pointer[0] == '0') |
| 19236 | { |
| 19237 | if (input_line_pointer[1] == 'x') |
| 19238 | { |
| 19239 | input_line_pointer += 2; |
| 19240 | while (ISXDIGIT (*input_line_pointer)) |
| 19241 | { |
| 19242 | val <<= 4; |
| 19243 | val |= hex_value (*input_line_pointer++); |
| 19244 | } |
| 19245 | return negative ? -val : val; |
| 19246 | } |
| 19247 | else |
| 19248 | { |
| 19249 | ++input_line_pointer; |
| 19250 | while (ISDIGIT (*input_line_pointer)) |
| 19251 | { |
| 19252 | val <<= 3; |
| 19253 | val |= *input_line_pointer++ - '0'; |
| 19254 | } |
| 19255 | return negative ? -val : val; |
| 19256 | } |
| 19257 | } |
| 19258 | if (!ISDIGIT (*input_line_pointer)) |
| 19259 | { |
| 19260 | printf (_(" *input_line_pointer == '%c' 0x%02x\n"), |
| 19261 | *input_line_pointer, *input_line_pointer); |
| 19262 | as_warn (_("invalid number")); |
| 19263 | return -1; |
| 19264 | } |
| 19265 | while (ISDIGIT (*input_line_pointer)) |
| 19266 | { |
| 19267 | val *= 10; |
| 19268 | val += *input_line_pointer++ - '0'; |
| 19269 | } |
| 19270 | return negative ? -val : val; |
| 19271 | } |
| 19272 | |
| 19273 | /* The .file directive; just like the usual .file directive, but there |
| 19274 | is an initial number which is the ECOFF file index. In the non-ECOFF |
| 19275 | case .file implies DWARF-2. */ |
| 19276 | |
| 19277 | static void |
| 19278 | s_mips_file (int x ATTRIBUTE_UNUSED) |
| 19279 | { |
| 19280 | static int first_file_directive = 0; |
| 19281 | |
| 19282 | if (ECOFF_DEBUGGING) |
| 19283 | { |
| 19284 | get_number (); |
| 19285 | s_app_file (0); |
| 19286 | } |
| 19287 | else |
| 19288 | { |
| 19289 | char *filename; |
| 19290 | |
| 19291 | filename = dwarf2_directive_file (0); |
| 19292 | |
| 19293 | /* Versions of GCC up to 3.1 start files with a ".file" |
| 19294 | directive even for stabs output. Make sure that this |
| 19295 | ".file" is handled. Note that you need a version of GCC |
| 19296 | after 3.1 in order to support DWARF-2 on MIPS. */ |
| 19297 | if (filename != NULL && ! first_file_directive) |
| 19298 | { |
| 19299 | (void) new_logical_line (filename, -1); |
| 19300 | s_app_file_string (filename, 0); |
| 19301 | } |
| 19302 | first_file_directive = 1; |
| 19303 | } |
| 19304 | } |
| 19305 | |
| 19306 | /* The .loc directive, implying DWARF-2. */ |
| 19307 | |
| 19308 | static void |
| 19309 | s_mips_loc (int x ATTRIBUTE_UNUSED) |
| 19310 | { |
| 19311 | if (!ECOFF_DEBUGGING) |
| 19312 | dwarf2_directive_loc (0); |
| 19313 | } |
| 19314 | |
| 19315 | /* The .end directive. */ |
| 19316 | |
| 19317 | static void |
| 19318 | s_mips_end (int x ATTRIBUTE_UNUSED) |
| 19319 | { |
| 19320 | symbolS *p; |
| 19321 | |
| 19322 | /* Following functions need their own .frame and .cprestore directives. */ |
| 19323 | mips_frame_reg_valid = 0; |
| 19324 | mips_cprestore_valid = 0; |
| 19325 | |
| 19326 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
| 19327 | { |
| 19328 | p = get_symbol (); |
| 19329 | demand_empty_rest_of_line (); |
| 19330 | } |
| 19331 | else |
| 19332 | p = NULL; |
| 19333 | |
| 19334 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
| 19335 | as_warn (_(".end not in text section")); |
| 19336 | |
| 19337 | if (!cur_proc_ptr) |
| 19338 | { |
| 19339 | as_warn (_(".end directive without a preceding .ent directive")); |
| 19340 | demand_empty_rest_of_line (); |
| 19341 | return; |
| 19342 | } |
| 19343 | |
| 19344 | if (p != NULL) |
| 19345 | { |
| 19346 | gas_assert (S_GET_NAME (p)); |
| 19347 | if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) |
| 19348 | as_warn (_(".end symbol does not match .ent symbol")); |
| 19349 | |
| 19350 | if (debug_type == DEBUG_STABS) |
| 19351 | stabs_generate_asm_endfunc (S_GET_NAME (p), |
| 19352 | S_GET_NAME (p)); |
| 19353 | } |
| 19354 | else |
| 19355 | as_warn (_(".end directive missing or unknown symbol")); |
| 19356 | |
| 19357 | /* Create an expression to calculate the size of the function. */ |
| 19358 | if (p && cur_proc_ptr) |
| 19359 | { |
| 19360 | OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); |
| 19361 | expressionS *exp = XNEW (expressionS); |
| 19362 | |
| 19363 | obj->size = exp; |
| 19364 | exp->X_op = O_subtract; |
| 19365 | exp->X_add_symbol = symbol_temp_new_now (); |
| 19366 | exp->X_op_symbol = p; |
| 19367 | exp->X_add_number = 0; |
| 19368 | |
| 19369 | cur_proc_ptr->func_end_sym = exp->X_add_symbol; |
| 19370 | } |
| 19371 | |
| 19372 | #ifdef md_flush_pending_output |
| 19373 | md_flush_pending_output (); |
| 19374 | #endif |
| 19375 | |
| 19376 | /* Generate a .pdr section. */ |
| 19377 | if (!ECOFF_DEBUGGING && mips_flag_pdr) |
| 19378 | { |
| 19379 | segT saved_seg = now_seg; |
| 19380 | subsegT saved_subseg = now_subseg; |
| 19381 | expressionS exp; |
| 19382 | char *fragp; |
| 19383 | |
| 19384 | gas_assert (pdr_seg); |
| 19385 | subseg_set (pdr_seg, 0); |
| 19386 | |
| 19387 | /* Write the symbol. */ |
| 19388 | exp.X_op = O_symbol; |
| 19389 | exp.X_add_symbol = p; |
| 19390 | exp.X_add_number = 0; |
| 19391 | emit_expr (&exp, 4); |
| 19392 | |
| 19393 | fragp = frag_more (7 * 4); |
| 19394 | |
| 19395 | md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4); |
| 19396 | md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); |
| 19397 | md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4); |
| 19398 | md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4); |
| 19399 | md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4); |
| 19400 | md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4); |
| 19401 | md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4); |
| 19402 | |
| 19403 | subseg_set (saved_seg, saved_subseg); |
| 19404 | } |
| 19405 | |
| 19406 | cur_proc_ptr = NULL; |
| 19407 | } |
| 19408 | |
| 19409 | /* The .aent and .ent directives. */ |
| 19410 | |
| 19411 | static void |
| 19412 | s_mips_ent (int aent) |
| 19413 | { |
| 19414 | symbolS *symbolP; |
| 19415 | |
| 19416 | symbolP = get_symbol (); |
| 19417 | if (*input_line_pointer == ',') |
| 19418 | ++input_line_pointer; |
| 19419 | SKIP_WHITESPACE (); |
| 19420 | if (ISDIGIT (*input_line_pointer) |
| 19421 | || *input_line_pointer == '-') |
| 19422 | get_number (); |
| 19423 | |
| 19424 | if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0) |
| 19425 | as_warn (_(".ent or .aent not in text section")); |
| 19426 | |
| 19427 | if (!aent && cur_proc_ptr) |
| 19428 | as_warn (_("missing .end")); |
| 19429 | |
| 19430 | if (!aent) |
| 19431 | { |
| 19432 | /* This function needs its own .frame and .cprestore directives. */ |
| 19433 | mips_frame_reg_valid = 0; |
| 19434 | mips_cprestore_valid = 0; |
| 19435 | |
| 19436 | cur_proc_ptr = &cur_proc; |
| 19437 | memset (cur_proc_ptr, '\0', sizeof (procS)); |
| 19438 | |
| 19439 | cur_proc_ptr->func_sym = symbolP; |
| 19440 | |
| 19441 | ++numprocs; |
| 19442 | |
| 19443 | if (debug_type == DEBUG_STABS) |
| 19444 | stabs_generate_asm_func (S_GET_NAME (symbolP), |
| 19445 | S_GET_NAME (symbolP)); |
| 19446 | } |
| 19447 | |
| 19448 | symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; |
| 19449 | |
| 19450 | demand_empty_rest_of_line (); |
| 19451 | } |
| 19452 | |
| 19453 | /* The .frame directive. If the mdebug section is present (IRIX 5 native) |
| 19454 | then ecoff.c (ecoff_directive_frame) is used. For embedded targets, |
| 19455 | s_mips_frame is used so that we can set the PDR information correctly. |
| 19456 | We can't use the ecoff routines because they make reference to the ecoff |
| 19457 | symbol table (in the mdebug section). */ |
| 19458 | |
| 19459 | static void |
| 19460 | s_mips_frame (int ignore ATTRIBUTE_UNUSED) |
| 19461 | { |
| 19462 | if (ECOFF_DEBUGGING) |
| 19463 | s_ignore (ignore); |
| 19464 | else |
| 19465 | { |
| 19466 | long val; |
| 19467 | |
| 19468 | if (cur_proc_ptr == (procS *) NULL) |
| 19469 | { |
| 19470 | as_warn (_(".frame outside of .ent")); |
| 19471 | demand_empty_rest_of_line (); |
| 19472 | return; |
| 19473 | } |
| 19474 | |
| 19475 | cur_proc_ptr->frame_reg = tc_get_register (1); |
| 19476 | |
| 19477 | SKIP_WHITESPACE (); |
| 19478 | if (*input_line_pointer++ != ',' |
| 19479 | || get_absolute_expression_and_terminator (&val) != ',') |
| 19480 | { |
| 19481 | as_warn (_("bad .frame directive")); |
| 19482 | --input_line_pointer; |
| 19483 | demand_empty_rest_of_line (); |
| 19484 | return; |
| 19485 | } |
| 19486 | |
| 19487 | cur_proc_ptr->frame_offset = val; |
| 19488 | cur_proc_ptr->pc_reg = tc_get_register (0); |
| 19489 | |
| 19490 | demand_empty_rest_of_line (); |
| 19491 | } |
| 19492 | } |
| 19493 | |
| 19494 | /* The .fmask and .mask directives. If the mdebug section is present |
| 19495 | (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For |
| 19496 | embedded targets, s_mips_mask is used so that we can set the PDR |
| 19497 | information correctly. We can't use the ecoff routines because they |
| 19498 | make reference to the ecoff symbol table (in the mdebug section). */ |
| 19499 | |
| 19500 | static void |
| 19501 | s_mips_mask (int reg_type) |
| 19502 | { |
| 19503 | if (ECOFF_DEBUGGING) |
| 19504 | s_ignore (reg_type); |
| 19505 | else |
| 19506 | { |
| 19507 | long mask, off; |
| 19508 | |
| 19509 | if (cur_proc_ptr == (procS *) NULL) |
| 19510 | { |
| 19511 | as_warn (_(".mask/.fmask outside of .ent")); |
| 19512 | demand_empty_rest_of_line (); |
| 19513 | return; |
| 19514 | } |
| 19515 | |
| 19516 | if (get_absolute_expression_and_terminator (&mask) != ',') |
| 19517 | { |
| 19518 | as_warn (_("bad .mask/.fmask directive")); |
| 19519 | --input_line_pointer; |
| 19520 | demand_empty_rest_of_line (); |
| 19521 | return; |
| 19522 | } |
| 19523 | |
| 19524 | off = get_absolute_expression (); |
| 19525 | |
| 19526 | if (reg_type == 'F') |
| 19527 | { |
| 19528 | cur_proc_ptr->fpreg_mask = mask; |
| 19529 | cur_proc_ptr->fpreg_offset = off; |
| 19530 | } |
| 19531 | else |
| 19532 | { |
| 19533 | cur_proc_ptr->reg_mask = mask; |
| 19534 | cur_proc_ptr->reg_offset = off; |
| 19535 | } |
| 19536 | |
| 19537 | demand_empty_rest_of_line (); |
| 19538 | } |
| 19539 | } |
| 19540 | |
| 19541 | /* A table describing all the processors gas knows about. Names are |
| 19542 | matched in the order listed. |
| 19543 | |
| 19544 | To ease comparison, please keep this table in the same order as |
| 19545 | gcc's mips_cpu_info_table[]. */ |
| 19546 | static const struct mips_cpu_info mips_cpu_info_table[] = |
| 19547 | { |
| 19548 | /* Entries for generic ISAs */ |
| 19549 | { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 }, |
| 19550 | { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 }, |
| 19551 | { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 }, |
| 19552 | { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 }, |
| 19553 | { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, |
| 19554 | { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, |
| 19555 | { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19556 | { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, |
| 19557 | { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, |
| 19558 | { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, |
| 19559 | { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, |
| 19560 | { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, |
| 19561 | { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, |
| 19562 | { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, |
| 19563 | { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, |
| 19564 | |
| 19565 | /* MIPS I */ |
| 19566 | { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
| 19567 | { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 }, |
| 19568 | { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 }, |
| 19569 | |
| 19570 | /* MIPS II */ |
| 19571 | { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, |
| 19572 | |
| 19573 | /* MIPS III */ |
| 19574 | { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, |
| 19575 | { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 }, |
| 19576 | { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 }, |
| 19577 | { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 }, |
| 19578 | { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 }, |
| 19579 | { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 }, |
| 19580 | { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 }, |
| 19581 | { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 }, |
| 19582 | { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 }, |
| 19583 | { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 }, |
| 19584 | { "orion", 0, 0, ISA_MIPS3, CPU_R4600 }, |
| 19585 | { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 }, |
| 19586 | { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 }, |
| 19587 | /* ST Microelectronics Loongson 2E and 2F cores */ |
| 19588 | { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E }, |
| 19589 | { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F }, |
| 19590 | |
| 19591 | /* MIPS IV */ |
| 19592 | { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 }, |
| 19593 | { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 }, |
| 19594 | { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 }, |
| 19595 | { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 }, |
| 19596 | { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 }, |
| 19597 | { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 }, |
| 19598 | { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 }, |
| 19599 | { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 }, |
| 19600 | { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 }, |
| 19601 | { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 }, |
| 19602 | { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 }, |
| 19603 | { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 }, |
| 19604 | { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 }, |
| 19605 | { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 }, |
| 19606 | { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 }, |
| 19607 | |
| 19608 | /* MIPS 32 */ |
| 19609 | { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
| 19610 | { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
| 19611 | { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 }, |
| 19612 | { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 }, |
| 19613 | |
| 19614 | /* MIPS 32 Release 2 */ |
| 19615 | { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19616 | { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19617 | { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19618 | { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19619 | { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19620 | { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19621 | { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19622 | { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19623 | { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, |
| 19624 | ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19625 | { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU, |
| 19626 | ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19627 | { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19628 | { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19629 | { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19630 | { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19631 | /* Deprecated forms of the above. */ |
| 19632 | { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19633 | { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19634 | /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ |
| 19635 | { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19636 | { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19637 | { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19638 | { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19639 | /* Deprecated forms of the above. */ |
| 19640 | { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19641 | { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19642 | /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ |
| 19643 | { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19644 | { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19645 | { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19646 | { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19647 | /* Deprecated forms of the above. */ |
| 19648 | { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19649 | { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19650 | /* 34Kn is a 34kc without DSP. */ |
| 19651 | { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19652 | /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ |
| 19653 | { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19654 | { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19655 | { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19656 | { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19657 | { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19658 | /* Deprecated forms of the above. */ |
| 19659 | { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19660 | { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19661 | /* 1004K cores are multiprocessor versions of the 34K. */ |
| 19662 | { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19663 | { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19664 | { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19665 | { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19666 | /* interaptiv is the new name for 1004kf */ |
| 19667 | { "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, |
| 19668 | /* M5100 family */ |
| 19669 | { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, |
| 19670 | { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, |
| 19671 | /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ |
| 19672 | { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, |
| 19673 | |
| 19674 | /* MIPS 64 */ |
| 19675 | { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
| 19676 | { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |
| 19677 | { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
| 19678 | { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 }, |
| 19679 | |
| 19680 | /* Broadcom SB-1 CPU core */ |
| 19681 | { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
| 19682 | /* Broadcom SB-1A CPU core */ |
| 19683 | { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, |
| 19684 | |
| 19685 | { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, |
| 19686 | |
| 19687 | /* MIPS 64 Release 2 */ |
| 19688 | |
| 19689 | /* Cavium Networks Octeon CPU core */ |
| 19690 | { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, |
| 19691 | { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP }, |
| 19692 | { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 }, |
| 19693 | { "octeon3", 0, ASE_VIRT | ASE_VIRT64, ISA_MIPS64R5, CPU_OCTEON3 }, |
| 19694 | |
| 19695 | /* RMI Xlr */ |
| 19696 | { "xlr", 0, 0, ISA_MIPS64, CPU_XLR }, |
| 19697 | |
| 19698 | /* Broadcom XLP. |
| 19699 | XLP is mostly like XLR, with the prominent exception that it is |
| 19700 | MIPS64R2 rather than MIPS64. */ |
| 19701 | { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR }, |
| 19702 | |
| 19703 | /* MIPS 64 Release 6 */ |
| 19704 | { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
| 19705 | { "p6600", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, |
| 19706 | |
| 19707 | /* End marker */ |
| 19708 | { NULL, 0, 0, 0, 0 } |
| 19709 | }; |
| 19710 | |
| 19711 | |
| 19712 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
| 19713 | with a final "000" replaced by "k". Ignore case. |
| 19714 | |
| 19715 | Note: this function is shared between GCC and GAS. */ |
| 19716 | |
| 19717 | static bfd_boolean |
| 19718 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) |
| 19719 | { |
| 19720 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) |
| 19721 | given++, canonical++; |
| 19722 | |
| 19723 | return ((*given == 0 && *canonical == 0) |
| 19724 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); |
| 19725 | } |
| 19726 | |
| 19727 | |
| 19728 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied |
| 19729 | CPU name. We've traditionally allowed a lot of variation here. |
| 19730 | |
| 19731 | Note: this function is shared between GCC and GAS. */ |
| 19732 | |
| 19733 | static bfd_boolean |
| 19734 | mips_matching_cpu_name_p (const char *canonical, const char *given) |
| 19735 | { |
| 19736 | /* First see if the name matches exactly, or with a final "000" |
| 19737 | turned into "k". */ |
| 19738 | if (mips_strict_matching_cpu_name_p (canonical, given)) |
| 19739 | return TRUE; |
| 19740 | |
| 19741 | /* If not, try comparing based on numerical designation alone. |
| 19742 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ |
| 19743 | if (TOLOWER (*given) == 'r') |
| 19744 | given++; |
| 19745 | if (!ISDIGIT (*given)) |
| 19746 | return FALSE; |
| 19747 | |
| 19748 | /* Skip over some well-known prefixes in the canonical name, |
| 19749 | hoping to find a number there too. */ |
| 19750 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') |
| 19751 | canonical += 2; |
| 19752 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') |
| 19753 | canonical += 2; |
| 19754 | else if (TOLOWER (canonical[0]) == 'r') |
| 19755 | canonical += 1; |
| 19756 | |
| 19757 | return mips_strict_matching_cpu_name_p (canonical, given); |
| 19758 | } |
| 19759 | |
| 19760 | |
| 19761 | /* Parse an option that takes the name of a processor as its argument. |
| 19762 | OPTION is the name of the option and CPU_STRING is the argument. |
| 19763 | Return the corresponding processor enumeration if the CPU_STRING is |
| 19764 | recognized, otherwise report an error and return null. |
| 19765 | |
| 19766 | A similar function exists in GCC. */ |
| 19767 | |
| 19768 | static const struct mips_cpu_info * |
| 19769 | mips_parse_cpu (const char *option, const char *cpu_string) |
| 19770 | { |
| 19771 | const struct mips_cpu_info *p; |
| 19772 | |
| 19773 | /* 'from-abi' selects the most compatible architecture for the given |
| 19774 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the |
| 19775 | EABIs, we have to decide whether we're using the 32-bit or 64-bit |
| 19776 | version. Look first at the -mgp options, if given, otherwise base |
| 19777 | the choice on MIPS_DEFAULT_64BIT. |
| 19778 | |
| 19779 | Treat NO_ABI like the EABIs. One reason to do this is that the |
| 19780 | plain 'mips' and 'mips64' configs have 'from-abi' as their default |
| 19781 | architecture. This code picks MIPS I for 'mips' and MIPS III for |
| 19782 | 'mips64', just as we did in the days before 'from-abi'. */ |
| 19783 | if (strcasecmp (cpu_string, "from-abi") == 0) |
| 19784 | { |
| 19785 | if (ABI_NEEDS_32BIT_REGS (mips_abi)) |
| 19786 | return mips_cpu_info_from_isa (ISA_MIPS1); |
| 19787 | |
| 19788 | if (ABI_NEEDS_64BIT_REGS (mips_abi)) |
| 19789 | return mips_cpu_info_from_isa (ISA_MIPS3); |
| 19790 | |
| 19791 | if (file_mips_opts.gp >= 0) |
| 19792 | return mips_cpu_info_from_isa (file_mips_opts.gp == 32 |
| 19793 | ? ISA_MIPS1 : ISA_MIPS3); |
| 19794 | |
| 19795 | return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT |
| 19796 | ? ISA_MIPS3 |
| 19797 | : ISA_MIPS1); |
| 19798 | } |
| 19799 | |
| 19800 | /* 'default' has traditionally been a no-op. Probably not very useful. */ |
| 19801 | if (strcasecmp (cpu_string, "default") == 0) |
| 19802 | return 0; |
| 19803 | |
| 19804 | for (p = mips_cpu_info_table; p->name != 0; p++) |
| 19805 | if (mips_matching_cpu_name_p (p->name, cpu_string)) |
| 19806 | return p; |
| 19807 | |
| 19808 | as_bad (_("bad value (%s) for %s"), cpu_string, option); |
| 19809 | return 0; |
| 19810 | } |
| 19811 | |
| 19812 | /* Return the canonical processor information for ISA (a member of the |
| 19813 | ISA_MIPS* enumeration). */ |
| 19814 | |
| 19815 | static const struct mips_cpu_info * |
| 19816 | mips_cpu_info_from_isa (int isa) |
| 19817 | { |
| 19818 | int i; |
| 19819 | |
| 19820 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) |
| 19821 | if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA) |
| 19822 | && isa == mips_cpu_info_table[i].isa) |
| 19823 | return (&mips_cpu_info_table[i]); |
| 19824 | |
| 19825 | return NULL; |
| 19826 | } |
| 19827 | |
| 19828 | static const struct mips_cpu_info * |
| 19829 | mips_cpu_info_from_arch (int arch) |
| 19830 | { |
| 19831 | int i; |
| 19832 | |
| 19833 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) |
| 19834 | if (arch == mips_cpu_info_table[i].cpu) |
| 19835 | return (&mips_cpu_info_table[i]); |
| 19836 | |
| 19837 | return NULL; |
| 19838 | } |
| 19839 | \f |
| 19840 | static void |
| 19841 | show (FILE *stream, const char *string, int *col_p, int *first_p) |
| 19842 | { |
| 19843 | if (*first_p) |
| 19844 | { |
| 19845 | fprintf (stream, "%24s", ""); |
| 19846 | *col_p = 24; |
| 19847 | } |
| 19848 | else |
| 19849 | { |
| 19850 | fprintf (stream, ", "); |
| 19851 | *col_p += 2; |
| 19852 | } |
| 19853 | |
| 19854 | if (*col_p + strlen (string) > 72) |
| 19855 | { |
| 19856 | fprintf (stream, "\n%24s", ""); |
| 19857 | *col_p = 24; |
| 19858 | } |
| 19859 | |
| 19860 | fprintf (stream, "%s", string); |
| 19861 | *col_p += strlen (string); |
| 19862 | |
| 19863 | *first_p = 0; |
| 19864 | } |
| 19865 | |
| 19866 | void |
| 19867 | md_show_usage (FILE *stream) |
| 19868 | { |
| 19869 | int column, first; |
| 19870 | size_t i; |
| 19871 | |
| 19872 | fprintf (stream, _("\ |
| 19873 | MIPS options:\n\ |
| 19874 | -EB generate big endian output\n\ |
| 19875 | -EL generate little endian output\n\ |
| 19876 | -g, -g2 do not remove unneeded NOPs or swap branches\n\ |
| 19877 | -G NUM allow referencing objects up to NUM bytes\n\ |
| 19878 | implicitly with the gp register [default 8]\n")); |
| 19879 | fprintf (stream, _("\ |
| 19880 | -mips1 generate MIPS ISA I instructions\n\ |
| 19881 | -mips2 generate MIPS ISA II instructions\n\ |
| 19882 | -mips3 generate MIPS ISA III instructions\n\ |
| 19883 | -mips4 generate MIPS ISA IV instructions\n\ |
| 19884 | -mips5 generate MIPS ISA V instructions\n\ |
| 19885 | -mips32 generate MIPS32 ISA instructions\n\ |
| 19886 | -mips32r2 generate MIPS32 release 2 ISA instructions\n\ |
| 19887 | -mips32r3 generate MIPS32 release 3 ISA instructions\n\ |
| 19888 | -mips32r5 generate MIPS32 release 5 ISA instructions\n\ |
| 19889 | -mips32r6 generate MIPS32 release 6 ISA instructions\n\ |
| 19890 | -mips64 generate MIPS64 ISA instructions\n\ |
| 19891 | -mips64r2 generate MIPS64 release 2 ISA instructions\n\ |
| 19892 | -mips64r3 generate MIPS64 release 3 ISA instructions\n\ |
| 19893 | -mips64r5 generate MIPS64 release 5 ISA instructions\n\ |
| 19894 | -mips64r6 generate MIPS64 release 6 ISA instructions\n\ |
| 19895 | -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); |
| 19896 | |
| 19897 | first = 1; |
| 19898 | |
| 19899 | for (i = 0; mips_cpu_info_table[i].name != NULL; i++) |
| 19900 | show (stream, mips_cpu_info_table[i].name, &column, &first); |
| 19901 | show (stream, "from-abi", &column, &first); |
| 19902 | fputc ('\n', stream); |
| 19903 | |
| 19904 | fprintf (stream, _("\ |
| 19905 | -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ |
| 19906 | -no-mCPU don't generate code specific to CPU.\n\ |
| 19907 | For -mCPU and -no-mCPU, CPU must be one of:\n")); |
| 19908 | |
| 19909 | first = 1; |
| 19910 | |
| 19911 | show (stream, "3900", &column, &first); |
| 19912 | show (stream, "4010", &column, &first); |
| 19913 | show (stream, "4100", &column, &first); |
| 19914 | show (stream, "4650", &column, &first); |
| 19915 | fputc ('\n', stream); |
| 19916 | |
| 19917 | fprintf (stream, _("\ |
| 19918 | -mips16 generate mips16 instructions\n\ |
| 19919 | -no-mips16 do not generate mips16 instructions\n")); |
| 19920 | fprintf (stream, _("\ |
| 19921 | -mmicromips generate microMIPS instructions\n\ |
| 19922 | -mno-micromips do not generate microMIPS instructions\n")); |
| 19923 | fprintf (stream, _("\ |
| 19924 | -msmartmips generate smartmips instructions\n\ |
| 19925 | -mno-smartmips do not generate smartmips instructions\n")); |
| 19926 | fprintf (stream, _("\ |
| 19927 | -mdsp generate DSP instructions\n\ |
| 19928 | -mno-dsp do not generate DSP instructions\n")); |
| 19929 | fprintf (stream, _("\ |
| 19930 | -mdspr2 generate DSP R2 instructions\n\ |
| 19931 | -mno-dspr2 do not generate DSP R2 instructions\n")); |
| 19932 | fprintf (stream, _("\ |
| 19933 | -mdspr3 generate DSP R3 instructions\n\ |
| 19934 | -mno-dspr3 do not generate DSP R3 instructions\n")); |
| 19935 | fprintf (stream, _("\ |
| 19936 | -mmt generate MT instructions\n\ |
| 19937 | -mno-mt do not generate MT instructions\n")); |
| 19938 | fprintf (stream, _("\ |
| 19939 | -mmcu generate MCU instructions\n\ |
| 19940 | -mno-mcu do not generate MCU instructions\n")); |
| 19941 | fprintf (stream, _("\ |
| 19942 | -mmsa generate MSA instructions\n\ |
| 19943 | -mno-msa do not generate MSA instructions\n")); |
| 19944 | fprintf (stream, _("\ |
| 19945 | -mxpa generate eXtended Physical Address (XPA) instructions\n\ |
| 19946 | -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); |
| 19947 | fprintf (stream, _("\ |
| 19948 | -mvirt generate Virtualization instructions\n\ |
| 19949 | -mno-virt do not generate Virtualization instructions\n")); |
| 19950 | fprintf (stream, _("\ |
| 19951 | -minsn32 only generate 32-bit microMIPS instructions\n\ |
| 19952 | -mno-insn32 generate all microMIPS instructions\n")); |
| 19953 | fprintf (stream, _("\ |
| 19954 | -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\ |
| 19955 | -mfix-loongson2f-nop work around Loongson2F NOP errata\n\ |
| 19956 | -mfix-vr4120 work around certain VR4120 errata\n\ |
| 19957 | -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\ |
| 19958 | -mfix-24k insert a nop after ERET and DERET instructions\n\ |
| 19959 | -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\ |
| 19960 | -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\ |
| 19961 | -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\ |
| 19962 | -msym32 assume all symbols have 32-bit values\n\ |
| 19963 | -O0 remove unneeded NOPs, do not swap branches\n\ |
| 19964 | -O remove unneeded NOPs and swap branches\n\ |
| 19965 | --trap, --no-break trap exception on div by 0 and mult overflow\n\ |
| 19966 | --break, --no-trap break exception on div by 0 and mult overflow\n")); |
| 19967 | fprintf (stream, _("\ |
| 19968 | -mhard-float allow floating-point instructions\n\ |
| 19969 | -msoft-float do not allow floating-point instructions\n\ |
| 19970 | -msingle-float only allow 32-bit floating-point operations\n\ |
| 19971 | -mdouble-float allow 32-bit and 64-bit floating-point operations\n\ |
| 19972 | --[no-]construct-floats [dis]allow floating point values to be constructed\n\ |
| 19973 | --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\ |
| 19974 | -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\ |
| 19975 | -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\ |
| 19976 | -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n")); |
| 19977 | |
| 19978 | first = 1; |
| 19979 | |
| 19980 | show (stream, "legacy", &column, &first); |
| 19981 | show (stream, "2008", &column, &first); |
| 19982 | |
| 19983 | fputc ('\n', stream); |
| 19984 | |
| 19985 | fprintf (stream, _("\ |
| 19986 | -KPIC, -call_shared generate SVR4 position independent code\n\ |
| 19987 | -call_nonpic generate non-PIC code that can operate with DSOs\n\ |
| 19988 | -mvxworks-pic generate VxWorks position independent code\n\ |
| 19989 | -non_shared do not generate code that can operate with DSOs\n\ |
| 19990 | -xgot assume a 32 bit GOT\n\ |
| 19991 | -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\ |
| 19992 | -mshared, -mno-shared disable/enable .cpload optimization for\n\ |
| 19993 | position dependent (non shared) code\n\ |
| 19994 | -mabi=ABI create ABI conformant object file for:\n")); |
| 19995 | |
| 19996 | first = 1; |
| 19997 | |
| 19998 | show (stream, "32", &column, &first); |
| 19999 | show (stream, "o64", &column, &first); |
| 20000 | show (stream, "n32", &column, &first); |
| 20001 | show (stream, "64", &column, &first); |
| 20002 | show (stream, "eabi", &column, &first); |
| 20003 | |
| 20004 | fputc ('\n', stream); |
| 20005 | |
| 20006 | fprintf (stream, _("\ |
| 20007 | -32 create o32 ABI object file (default)\n\ |
| 20008 | -n32 create n32 ABI object file\n\ |
| 20009 | -64 create 64 ABI object file\n")); |
| 20010 | } |
| 20011 | |
| 20012 | #ifdef TE_IRIX |
| 20013 | enum dwarf2_format |
| 20014 | mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED) |
| 20015 | { |
| 20016 | if (HAVE_64BIT_SYMBOLS) |
| 20017 | return dwarf2_format_64bit_irix; |
| 20018 | else |
| 20019 | return dwarf2_format_32bit; |
| 20020 | } |
| 20021 | #endif |
| 20022 | |
| 20023 | int |
| 20024 | mips_dwarf2_addr_size (void) |
| 20025 | { |
| 20026 | if (HAVE_64BIT_OBJECTS) |
| 20027 | return 8; |
| 20028 | else |
| 20029 | return 4; |
| 20030 | } |
| 20031 | |
| 20032 | /* Standard calling conventions leave the CFA at SP on entry. */ |
| 20033 | void |
| 20034 | mips_cfi_frame_initial_instructions (void) |
| 20035 | { |
| 20036 | cfi_add_CFA_def_cfa_register (SP); |
| 20037 | } |
| 20038 | |
| 20039 | int |
| 20040 | tc_mips_regname_to_dw2regnum (char *regname) |
| 20041 | { |
| 20042 | unsigned int regnum = -1; |
| 20043 | unsigned int reg; |
| 20044 | |
| 20045 | if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) |
| 20046 | regnum = reg; |
| 20047 | |
| 20048 | return regnum; |
| 20049 | } |
| 20050 | |
| 20051 | /* Implement CONVERT_SYMBOLIC_ATTRIBUTE. |
| 20052 | Given a symbolic attribute NAME, return the proper integer value. |
| 20053 | Returns -1 if the attribute is not known. */ |
| 20054 | |
| 20055 | int |
| 20056 | mips_convert_symbolic_attribute (const char *name) |
| 20057 | { |
| 20058 | static const struct |
| 20059 | { |
| 20060 | const char * name; |
| 20061 | const int tag; |
| 20062 | } |
| 20063 | attribute_table[] = |
| 20064 | { |
| 20065 | #define T(tag) {#tag, tag} |
| 20066 | T (Tag_GNU_MIPS_ABI_FP), |
| 20067 | T (Tag_GNU_MIPS_ABI_MSA), |
| 20068 | #undef T |
| 20069 | }; |
| 20070 | unsigned int i; |
| 20071 | |
| 20072 | if (name == NULL) |
| 20073 | return -1; |
| 20074 | |
| 20075 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
| 20076 | if (streq (name, attribute_table[i].name)) |
| 20077 | return attribute_table[i].tag; |
| 20078 | |
| 20079 | return -1; |
| 20080 | } |
| 20081 | |
| 20082 | void |
| 20083 | md_mips_end (void) |
| 20084 | { |
| 20085 | int fpabi = Val_GNU_MIPS_ABI_FP_ANY; |
| 20086 | |
| 20087 | mips_emit_delays (); |
| 20088 | if (cur_proc_ptr) |
| 20089 | as_warn (_("missing .end at end of assembly")); |
| 20090 | |
| 20091 | /* Just in case no code was emitted, do the consistency check. */ |
| 20092 | file_mips_check_options (); |
| 20093 | |
| 20094 | /* Set a floating-point ABI if the user did not. */ |
| 20095 | if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) |
| 20096 | { |
| 20097 | /* Perform consistency checks on the floating-point ABI. */ |
| 20098 | fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
| 20099 | Tag_GNU_MIPS_ABI_FP); |
| 20100 | if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) |
| 20101 | check_fpabi (fpabi); |
| 20102 | } |
| 20103 | else |
| 20104 | { |
| 20105 | /* Soft-float gets precedence over single-float, the two options should |
| 20106 | not be used together so this should not matter. */ |
| 20107 | if (file_mips_opts.soft_float == 1) |
| 20108 | fpabi = Val_GNU_MIPS_ABI_FP_SOFT; |
| 20109 | /* Single-float gets precedence over all double_float cases. */ |
| 20110 | else if (file_mips_opts.single_float == 1) |
| 20111 | fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; |
| 20112 | else |
| 20113 | { |
| 20114 | switch (file_mips_opts.fp) |
| 20115 | { |
| 20116 | case 32: |
| 20117 | if (file_mips_opts.gp == 32) |
| 20118 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; |
| 20119 | break; |
| 20120 | case 0: |
| 20121 | fpabi = Val_GNU_MIPS_ABI_FP_XX; |
| 20122 | break; |
| 20123 | case 64: |
| 20124 | if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) |
| 20125 | fpabi = Val_GNU_MIPS_ABI_FP_64A; |
| 20126 | else if (file_mips_opts.gp == 32) |
| 20127 | fpabi = Val_GNU_MIPS_ABI_FP_64; |
| 20128 | else |
| 20129 | fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; |
| 20130 | break; |
| 20131 | } |
| 20132 | } |
| 20133 | |
| 20134 | bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, |
| 20135 | Tag_GNU_MIPS_ABI_FP, fpabi); |
| 20136 | } |
| 20137 | } |
| 20138 | |
| 20139 | /* Returns the relocation type required for a particular CFI encoding. */ |
| 20140 | |
| 20141 | bfd_reloc_code_real_type |
| 20142 | mips_cfi_reloc_for_encoding (int encoding) |
| 20143 | { |
| 20144 | if (encoding == (DW_EH_PE_sdata4 | DW_EH_PE_pcrel)) |
| 20145 | return BFD_RELOC_32_PCREL; |
| 20146 | else return BFD_RELOC_NONE; |
| 20147 | } |