gas/
[deliverable/binutils-gdb.git] / gas / config / tc-mips.c
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1/* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by the OSF and Ralph Campbell.
6 Written by Keith Knowles and Ralph Campbell, working independently.
7 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 Support.
9
10 This file is part of GAS.
11
12 GAS is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GAS is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GAS; see the file COPYING. If not, write to the Free
24 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 02110-1301, USA. */
26
27#include "as.h"
28#include "config.h"
29#include "subsegs.h"
30#include "safe-ctype.h"
31
32#include "opcode/mips.h"
33#include "itbl-ops.h"
34#include "dwarf2dbg.h"
35#include "dw2gencfi.h"
36
37#ifdef DEBUG
38#define DBG(x) printf x
39#else
40#define DBG(x)
41#endif
42
43#ifdef OBJ_MAYBE_ELF
44/* Clean up namespace so we can include obj-elf.h too. */
45static int mips_output_flavor (void);
46static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
47#undef OBJ_PROCESS_STAB
48#undef OUTPUT_FLAVOR
49#undef S_GET_ALIGN
50#undef S_GET_SIZE
51#undef S_SET_ALIGN
52#undef S_SET_SIZE
53#undef obj_frob_file
54#undef obj_frob_file_after_relocs
55#undef obj_frob_symbol
56#undef obj_pop_insert
57#undef obj_sec_sym_ok_for_reloc
58#undef OBJ_COPY_SYMBOL_ATTRIBUTES
59
60#include "obj-elf.h"
61/* Fix any of them that we actually care about. */
62#undef OUTPUT_FLAVOR
63#define OUTPUT_FLAVOR mips_output_flavor()
64#endif
65
66#if defined (OBJ_ELF)
67#include "elf/mips.h"
68#endif
69
70#ifndef ECOFF_DEBUGGING
71#define NO_ECOFF_DEBUGGING
72#define ECOFF_DEBUGGING 0
73#endif
74
75int mips_flag_mdebug = -1;
76
77/* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
80#ifdef TE_IRIX
81int mips_flag_pdr = FALSE;
82#else
83int mips_flag_pdr = TRUE;
84#endif
85
86#include "ecoff.h"
87
88#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89static char *mips_regmask_frag;
90#endif
91
92#define ZERO 0
93#define ATREG 1
94#define TREG 24
95#define PIC_CALL_REG 25
96#define KT0 26
97#define KT1 27
98#define GP 28
99#define SP 29
100#define FP 30
101#define RA 31
102
103#define ILLEGAL_REG (32)
104
105#define AT mips_opts.at
106
107/* Allow override of standard little-endian ECOFF format. */
108
109#ifndef ECOFF_LITTLE_FORMAT
110#define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111#endif
112
113extern int target_big_endian;
114
115/* The name of the readonly data section. */
116#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 ? ".rdata" \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 ? ".rdata" \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
121 ? ".rodata" \
122 : (abort (), ""))
123
124/* Ways in which an instruction can be "appended" to the output. */
125enum append_method {
126 /* Just add it normally. */
127 APPEND_ADD,
128
129 /* Add it normally and then add a nop. */
130 APPEND_ADD_WITH_NOP,
131
132 /* Turn an instruction with a delay slot into a "compact" version. */
133 APPEND_ADD_COMPACT,
134
135 /* Insert the instruction before the last one. */
136 APPEND_SWAP
137};
138
139/* Information about an instruction, including its format, operands
140 and fixups. */
141struct mips_cl_insn
142{
143 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
144 const struct mips_opcode *insn_mo;
145
146 /* True if this is a mips16 instruction and if we want the extended
147 form of INSN_MO. */
148 bfd_boolean use_extend;
149
150 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
151 unsigned short extend;
152
153 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
154 a copy of INSN_MO->match with the operands filled in. */
155 unsigned long insn_opcode;
156
157 /* The frag that contains the instruction. */
158 struct frag *frag;
159
160 /* The offset into FRAG of the first instruction byte. */
161 long where;
162
163 /* The relocs associated with the instruction, if any. */
164 fixS *fixp[3];
165
166 /* True if this entry cannot be moved from its current position. */
167 unsigned int fixed_p : 1;
168
169 /* True if this instruction occurred in a .set noreorder block. */
170 unsigned int noreorder_p : 1;
171
172 /* True for mips16 instructions that jump to an absolute address. */
173 unsigned int mips16_absolute_jump_p : 1;
174
175 /* True if this instruction is complete. */
176 unsigned int complete_p : 1;
177};
178
179/* The ABI to use. */
180enum mips_abi_level
181{
182 NO_ABI = 0,
183 O32_ABI,
184 O64_ABI,
185 N32_ABI,
186 N64_ABI,
187 EABI_ABI
188};
189
190/* MIPS ABI we are using for this output file. */
191static enum mips_abi_level mips_abi = NO_ABI;
192
193/* Whether or not we have code that can call pic code. */
194int mips_abicalls = FALSE;
195
196/* Whether or not we have code which can be put into a shared
197 library. */
198static bfd_boolean mips_in_shared = TRUE;
199
200/* This is the set of options which may be modified by the .set
201 pseudo-op. We use a struct so that .set push and .set pop are more
202 reliable. */
203
204struct mips_set_options
205{
206 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
207 if it has not been initialized. Changed by `.set mipsN', and the
208 -mipsN command line option, and the default CPU. */
209 int isa;
210 /* Enabled Application Specific Extensions (ASEs). These are set to -1
211 if they have not been initialized. Changed by `.set <asename>', by
212 command line options, and based on the default architecture. */
213 int ase_mips3d;
214 int ase_mdmx;
215 int ase_smartmips;
216 int ase_dsp;
217 int ase_dspr2;
218 int ase_mt;
219 /* Whether we are assembling for the mips16 processor. 0 if we are
220 not, 1 if we are, and -1 if the value has not been initialized.
221 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
222 -nomips16 command line options, and the default CPU. */
223 int mips16;
224 /* Non-zero if we should not reorder instructions. Changed by `.set
225 reorder' and `.set noreorder'. */
226 int noreorder;
227 /* Non-zero if we should not permit the register designated "assembler
228 temporary" to be used in instructions. The value is the register
229 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
230 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
231 unsigned int at;
232 /* Non-zero if we should warn when a macro instruction expands into
233 more than one machine instruction. Changed by `.set nomacro' and
234 `.set macro'. */
235 int warn_about_macros;
236 /* Non-zero if we should not move instructions. Changed by `.set
237 move', `.set volatile', `.set nomove', and `.set novolatile'. */
238 int nomove;
239 /* Non-zero if we should not optimize branches by moving the target
240 of the branch into the delay slot. Actually, we don't perform
241 this optimization anyhow. Changed by `.set bopt' and `.set
242 nobopt'. */
243 int nobopt;
244 /* Non-zero if we should not autoextend mips16 instructions.
245 Changed by `.set autoextend' and `.set noautoextend'. */
246 int noautoextend;
247 /* Restrict general purpose registers and floating point registers
248 to 32 bit. This is initially determined when -mgp32 or -mfp32
249 is passed but can changed if the assembler code uses .set mipsN. */
250 int gp32;
251 int fp32;
252 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
253 command line option, and the default CPU. */
254 int arch;
255 /* True if ".set sym32" is in effect. */
256 bfd_boolean sym32;
257 /* True if floating-point operations are not allowed. Changed by .set
258 softfloat or .set hardfloat, by command line options -msoft-float or
259 -mhard-float. The default is false. */
260 bfd_boolean soft_float;
261
262 /* True if only single-precision floating-point operations are allowed.
263 Changed by .set singlefloat or .set doublefloat, command-line options
264 -msingle-float or -mdouble-float. The default is false. */
265 bfd_boolean single_float;
266};
267
268/* This is the struct we use to hold the current set of options. Note
269 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
270 -1 to indicate that they have not been initialized. */
271
272/* True if -mgp32 was passed. */
273static int file_mips_gp32 = -1;
274
275/* True if -mfp32 was passed. */
276static int file_mips_fp32 = -1;
277
278/* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
279static int file_mips_soft_float = 0;
280
281/* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
282static int file_mips_single_float = 0;
283
284static struct mips_set_options mips_opts =
285{
286 /* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
287 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
288 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG,
289 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
290 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN,
291 /* sym32 */ FALSE, /* soft_float */ FALSE, /* single_float */ FALSE
292};
293
294/* These variables are filled in with the masks of registers used.
295 The object format code reads them and puts them in the appropriate
296 place. */
297unsigned long mips_gprmask;
298unsigned long mips_cprmask[4];
299
300/* MIPS ISA we are using for this output file. */
301static int file_mips_isa = ISA_UNKNOWN;
302
303/* True if any MIPS16 code was produced. */
304static int file_ase_mips16;
305
306#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
307 || mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64 \
309 || mips_opts.isa == ISA_MIPS64R2)
310
311/* True if we want to create R_MIPS_JALR for jalr $25. */
312#ifdef TE_IRIX
313#define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
314#else
315/* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
316 because there's no place for any addend, the only acceptable
317 expression is a bare symbol. */
318#define MIPS_JALR_HINT_P(EXPR) \
319 (!HAVE_IN_PLACE_ADDENDS \
320 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
321#endif
322
323/* True if -mips3d was passed or implied by arguments passed on the
324 command line (e.g., by -march). */
325static int file_ase_mips3d;
326
327/* True if -mdmx was passed or implied by arguments passed on the
328 command line (e.g., by -march). */
329static int file_ase_mdmx;
330
331/* True if -msmartmips was passed or implied by arguments passed on the
332 command line (e.g., by -march). */
333static int file_ase_smartmips;
334
335#define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
336 || mips_opts.isa == ISA_MIPS32R2)
337
338/* True if -mdsp was passed or implied by arguments passed on the
339 command line (e.g., by -march). */
340static int file_ase_dsp;
341
342#define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
343 || mips_opts.isa == ISA_MIPS64R2)
344
345#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
346
347/* True if -mdspr2 was passed or implied by arguments passed on the
348 command line (e.g., by -march). */
349static int file_ase_dspr2;
350
351#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
352 || mips_opts.isa == ISA_MIPS64R2)
353
354/* True if -mmt was passed or implied by arguments passed on the
355 command line (e.g., by -march). */
356static int file_ase_mt;
357
358#define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
359 || mips_opts.isa == ISA_MIPS64R2)
360
361/* The argument of the -march= flag. The architecture we are assembling. */
362static int file_mips_arch = CPU_UNKNOWN;
363static const char *mips_arch_string;
364
365/* The argument of the -mtune= flag. The architecture for which we
366 are optimizing. */
367static int mips_tune = CPU_UNKNOWN;
368static const char *mips_tune_string;
369
370/* True when generating 32-bit code for a 64-bit processor. */
371static int mips_32bitmode = 0;
372
373/* True if the given ABI requires 32-bit registers. */
374#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
375
376/* Likewise 64-bit registers. */
377#define ABI_NEEDS_64BIT_REGS(ABI) \
378 ((ABI) == N32_ABI \
379 || (ABI) == N64_ABI \
380 || (ABI) == O64_ABI)
381
382/* Return true if ISA supports 64 bit wide gp registers. */
383#define ISA_HAS_64BIT_REGS(ISA) \
384 ((ISA) == ISA_MIPS3 \
385 || (ISA) == ISA_MIPS4 \
386 || (ISA) == ISA_MIPS5 \
387 || (ISA) == ISA_MIPS64 \
388 || (ISA) == ISA_MIPS64R2)
389
390/* Return true if ISA supports 64 bit wide float registers. */
391#define ISA_HAS_64BIT_FPRS(ISA) \
392 ((ISA) == ISA_MIPS3 \
393 || (ISA) == ISA_MIPS4 \
394 || (ISA) == ISA_MIPS5 \
395 || (ISA) == ISA_MIPS32R2 \
396 || (ISA) == ISA_MIPS64 \
397 || (ISA) == ISA_MIPS64R2)
398
399/* Return true if ISA supports 64-bit right rotate (dror et al.)
400 instructions. */
401#define ISA_HAS_DROR(ISA) \
402 ((ISA) == ISA_MIPS64R2)
403
404/* Return true if ISA supports 32-bit right rotate (ror et al.)
405 instructions. */
406#define ISA_HAS_ROR(ISA) \
407 ((ISA) == ISA_MIPS32R2 \
408 || (ISA) == ISA_MIPS64R2 \
409 || mips_opts.ase_smartmips)
410
411/* Return true if ISA supports single-precision floats in odd registers. */
412#define ISA_HAS_ODD_SINGLE_FPR(ISA) \
413 ((ISA) == ISA_MIPS32 \
414 || (ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS64 \
416 || (ISA) == ISA_MIPS64R2)
417
418/* Return true if ISA supports move to/from high part of a 64-bit
419 floating-point register. */
420#define ISA_HAS_MXHC1(ISA) \
421 ((ISA) == ISA_MIPS32R2 \
422 || (ISA) == ISA_MIPS64R2)
423
424#define HAVE_32BIT_GPRS \
425 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
426
427#define HAVE_32BIT_FPRS \
428 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
429
430#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
431#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
432
433#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
434
435#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
436
437/* True if relocations are stored in-place. */
438#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
439
440/* The ABI-derived address size. */
441#define HAVE_64BIT_ADDRESSES \
442 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
443#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
444
445/* The size of symbolic constants (i.e., expressions of the form
446 "SYMBOL" or "SYMBOL + OFFSET"). */
447#define HAVE_32BIT_SYMBOLS \
448 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
449#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
450
451/* Addresses are loaded in different ways, depending on the address size
452 in use. The n32 ABI Documentation also mandates the use of additions
453 with overflow checking, but existing implementations don't follow it. */
454#define ADDRESS_ADD_INSN \
455 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
456
457#define ADDRESS_ADDI_INSN \
458 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
459
460#define ADDRESS_LOAD_INSN \
461 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
462
463#define ADDRESS_STORE_INSN \
464 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
465
466/* Return true if the given CPU supports the MIPS16 ASE. */
467#define CPU_HAS_MIPS16(cpu) \
468 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
469 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
470
471/* True if CPU has a dror instruction. */
472#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
473
474/* True if CPU has a ror instruction. */
475#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
476
477/* True if CPU has seq/sne and seqi/snei instructions. */
478#define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
479
480/* True if CPU does not implement the all the coprocessor insns. For these
481 CPUs only those COP insns are accepted that are explicitly marked to be
482 available on the CPU. ISA membership for COP insns is ignored. */
483#define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
484
485/* True if mflo and mfhi can be immediately followed by instructions
486 which write to the HI and LO registers.
487
488 According to MIPS specifications, MIPS ISAs I, II, and III need
489 (at least) two instructions between the reads of HI/LO and
490 instructions which write them, and later ISAs do not. Contradicting
491 the MIPS specifications, some MIPS IV processor user manuals (e.g.
492 the UM for the NEC Vr5000) document needing the instructions between
493 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
494 MIPS64 and later ISAs to have the interlocks, plus any specific
495 earlier-ISA CPUs for which CPU documentation declares that the
496 instructions are really interlocked. */
497#define hilo_interlocks \
498 (mips_opts.isa == ISA_MIPS32 \
499 || mips_opts.isa == ISA_MIPS32R2 \
500 || mips_opts.isa == ISA_MIPS64 \
501 || mips_opts.isa == ISA_MIPS64R2 \
502 || mips_opts.arch == CPU_R4010 \
503 || mips_opts.arch == CPU_R10000 \
504 || mips_opts.arch == CPU_R12000 \
505 || mips_opts.arch == CPU_R14000 \
506 || mips_opts.arch == CPU_R16000 \
507 || mips_opts.arch == CPU_RM7000 \
508 || mips_opts.arch == CPU_VR5500 \
509 )
510
511/* Whether the processor uses hardware interlocks to protect reads
512 from the GPRs after they are loaded from memory, and thus does not
513 require nops to be inserted. This applies to instructions marked
514 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
515 level I. */
516#define gpr_interlocks \
517 (mips_opts.isa != ISA_MIPS1 \
518 || mips_opts.arch == CPU_R3900)
519
520/* Whether the processor uses hardware interlocks to avoid delays
521 required by coprocessor instructions, and thus does not require
522 nops to be inserted. This applies to instructions marked
523 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
524 between instructions marked INSN_WRITE_COND_CODE and ones marked
525 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
526 levels I, II, and III. */
527/* Itbl support may require additional care here. */
528#define cop_interlocks \
529 ((mips_opts.isa != ISA_MIPS1 \
530 && mips_opts.isa != ISA_MIPS2 \
531 && mips_opts.isa != ISA_MIPS3) \
532 || mips_opts.arch == CPU_R4300 \
533 )
534
535/* Whether the processor uses hardware interlocks to protect reads
536 from coprocessor registers after they are loaded from memory, and
537 thus does not require nops to be inserted. This applies to
538 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
539 requires at MIPS ISA level I. */
540#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
541
542/* Is this a mfhi or mflo instruction? */
543#define MF_HILO_INSN(PINFO) \
544 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
545
546/* Returns true for a (non floating-point) coprocessor instruction. Reading
547 or writing the condition code is only possible on the coprocessors and
548 these insns are not marked with INSN_COP. Thus for these insns use the
549 condition-code flags. */
550#define COP_INSN(PINFO) \
551 (PINFO != INSN_MACRO \
552 && ((PINFO) & (FP_S | FP_D)) == 0 \
553 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
554
555/* MIPS PIC level. */
556
557enum mips_pic_level mips_pic;
558
559/* 1 if we should generate 32 bit offsets from the $gp register in
560 SVR4_PIC mode. Currently has no meaning in other modes. */
561static int mips_big_got = 0;
562
563/* 1 if trap instructions should used for overflow rather than break
564 instructions. */
565static int mips_trap = 0;
566
567/* 1 if double width floating point constants should not be constructed
568 by assembling two single width halves into two single width floating
569 point registers which just happen to alias the double width destination
570 register. On some architectures this aliasing can be disabled by a bit
571 in the status register, and the setting of this bit cannot be determined
572 automatically at assemble time. */
573static int mips_disable_float_construction;
574
575/* Non-zero if any .set noreorder directives were used. */
576
577static int mips_any_noreorder;
578
579/* Non-zero if nops should be inserted when the register referenced in
580 an mfhi/mflo instruction is read in the next two instructions. */
581static int mips_7000_hilo_fix;
582
583/* The size of objects in the small data section. */
584static unsigned int g_switch_value = 8;
585/* Whether the -G option was used. */
586static int g_switch_seen = 0;
587
588#define N_RMASK 0xc4
589#define N_VFP 0xd4
590
591/* If we can determine in advance that GP optimization won't be
592 possible, we can skip the relaxation stuff that tries to produce
593 GP-relative references. This makes delay slot optimization work
594 better.
595
596 This function can only provide a guess, but it seems to work for
597 gcc output. It needs to guess right for gcc, otherwise gcc
598 will put what it thinks is a GP-relative instruction in a branch
599 delay slot.
600
601 I don't know if a fix is needed for the SVR4_PIC mode. I've only
602 fixed it for the non-PIC mode. KR 95/04/07 */
603static int nopic_need_relax (symbolS *, int);
604
605/* handle of the OPCODE hash table */
606static struct hash_control *op_hash = NULL;
607
608/* The opcode hash table we use for the mips16. */
609static struct hash_control *mips16_op_hash = NULL;
610
611/* This array holds the chars that always start a comment. If the
612 pre-processor is disabled, these aren't very useful */
613const char comment_chars[] = "#";
614
615/* This array holds the chars that only start a comment at the beginning of
616 a line. If the line seems to have the form '# 123 filename'
617 .line and .file directives will appear in the pre-processed output */
618/* Note that input_file.c hand checks for '#' at the beginning of the
619 first line of the input file. This is because the compiler outputs
620 #NO_APP at the beginning of its output. */
621/* Also note that C style comments are always supported. */
622const char line_comment_chars[] = "#";
623
624/* This array holds machine specific line separator characters. */
625const char line_separator_chars[] = ";";
626
627/* Chars that can be used to separate mant from exp in floating point nums */
628const char EXP_CHARS[] = "eE";
629
630/* Chars that mean this number is a floating point constant */
631/* As in 0f12.456 */
632/* or 0d1.2345e12 */
633const char FLT_CHARS[] = "rRsSfFdDxXpP";
634
635/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
636 changed in read.c . Ideally it shouldn't have to know about it at all,
637 but nothing is ideal around here.
638 */
639
640static char *insn_error;
641
642static int auto_align = 1;
643
644/* When outputting SVR4 PIC code, the assembler needs to know the
645 offset in the stack frame from which to restore the $gp register.
646 This is set by the .cprestore pseudo-op, and saved in this
647 variable. */
648static offsetT mips_cprestore_offset = -1;
649
650/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
651 more optimizations, it can use a register value instead of a memory-saved
652 offset and even an other register than $gp as global pointer. */
653static offsetT mips_cpreturn_offset = -1;
654static int mips_cpreturn_register = -1;
655static int mips_gp_register = GP;
656static int mips_gprel_offset = 0;
657
658/* Whether mips_cprestore_offset has been set in the current function
659 (or whether it has already been warned about, if not). */
660static int mips_cprestore_valid = 0;
661
662/* This is the register which holds the stack frame, as set by the
663 .frame pseudo-op. This is needed to implement .cprestore. */
664static int mips_frame_reg = SP;
665
666/* Whether mips_frame_reg has been set in the current function
667 (or whether it has already been warned about, if not). */
668static int mips_frame_reg_valid = 0;
669
670/* To output NOP instructions correctly, we need to keep information
671 about the previous two instructions. */
672
673/* Whether we are optimizing. The default value of 2 means to remove
674 unneeded NOPs and swap branch instructions when possible. A value
675 of 1 means to not swap branches. A value of 0 means to always
676 insert NOPs. */
677static int mips_optimize = 2;
678
679/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
680 equivalent to seeing no -g option at all. */
681static int mips_debug = 0;
682
683/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
684#define MAX_VR4130_NOPS 4
685
686/* The maximum number of NOPs needed to fill delay slots. */
687#define MAX_DELAY_NOPS 2
688
689/* The maximum number of NOPs needed for any purpose. */
690#define MAX_NOPS 4
691
692/* A list of previous instructions, with index 0 being the most recent.
693 We need to look back MAX_NOPS instructions when filling delay slots
694 or working around processor errata. We need to look back one
695 instruction further if we're thinking about using history[0] to
696 fill a branch delay slot. */
697static struct mips_cl_insn history[1 + MAX_NOPS];
698
699/* Nop instructions used by emit_nop. */
700static struct mips_cl_insn nop_insn, mips16_nop_insn;
701
702/* The appropriate nop for the current mode. */
703#define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
704
705/* If this is set, it points to a frag holding nop instructions which
706 were inserted before the start of a noreorder section. If those
707 nops turn out to be unnecessary, the size of the frag can be
708 decreased. */
709static fragS *prev_nop_frag;
710
711/* The number of nop instructions we created in prev_nop_frag. */
712static int prev_nop_frag_holds;
713
714/* The number of nop instructions that we know we need in
715 prev_nop_frag. */
716static int prev_nop_frag_required;
717
718/* The number of instructions we've seen since prev_nop_frag. */
719static int prev_nop_frag_since;
720
721/* For ECOFF and ELF, relocations against symbols are done in two
722 parts, with a HI relocation and a LO relocation. Each relocation
723 has only 16 bits of space to store an addend. This means that in
724 order for the linker to handle carries correctly, it must be able
725 to locate both the HI and the LO relocation. This means that the
726 relocations must appear in order in the relocation table.
727
728 In order to implement this, we keep track of each unmatched HI
729 relocation. We then sort them so that they immediately precede the
730 corresponding LO relocation. */
731
732struct mips_hi_fixup
733{
734 /* Next HI fixup. */
735 struct mips_hi_fixup *next;
736 /* This fixup. */
737 fixS *fixp;
738 /* The section this fixup is in. */
739 segT seg;
740};
741
742/* The list of unmatched HI relocs. */
743
744static struct mips_hi_fixup *mips_hi_fixup_list;
745
746/* The frag containing the last explicit relocation operator.
747 Null if explicit relocations have not been used. */
748
749static fragS *prev_reloc_op_frag;
750
751/* Map normal MIPS register numbers to mips16 register numbers. */
752
753#define X ILLEGAL_REG
754static const int mips32_to_16_reg_map[] =
755{
756 X, X, 2, 3, 4, 5, 6, 7,
757 X, X, X, X, X, X, X, X,
758 0, 1, X, X, X, X, X, X,
759 X, X, X, X, X, X, X, X
760};
761#undef X
762
763/* Map mips16 register numbers to normal MIPS register numbers. */
764
765static const unsigned int mips16_to_32_reg_map[] =
766{
767 16, 17, 2, 3, 4, 5, 6, 7
768};
769
770/* Classifies the kind of instructions we're interested in when
771 implementing -mfix-vr4120. */
772enum fix_vr4120_class
773{
774 FIX_VR4120_MACC,
775 FIX_VR4120_DMACC,
776 FIX_VR4120_MULT,
777 FIX_VR4120_DMULT,
778 FIX_VR4120_DIV,
779 FIX_VR4120_MTHILO,
780 NUM_FIX_VR4120_CLASSES
781};
782
783/* ...likewise -mfix-loongson2f-jump. */
784static bfd_boolean mips_fix_loongson2f_jump;
785
786/* ...likewise -mfix-loongson2f-nop. */
787static bfd_boolean mips_fix_loongson2f_nop;
788
789/* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
790static bfd_boolean mips_fix_loongson2f;
791
792/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
793 there must be at least one other instruction between an instruction
794 of type X and an instruction of type Y. */
795static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
796
797/* True if -mfix-vr4120 is in force. */
798static int mips_fix_vr4120;
799
800/* ...likewise -mfix-vr4130. */
801static int mips_fix_vr4130;
802
803/* ...likewise -mfix-24k. */
804static int mips_fix_24k;
805
806/* ...likewise -mfix-cn63xxp1 */
807static bfd_boolean mips_fix_cn63xxp1;
808
809/* We don't relax branches by default, since this causes us to expand
810 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
811 fail to compute the offset before expanding the macro to the most
812 efficient expansion. */
813
814static int mips_relax_branch;
815\f
816/* The expansion of many macros depends on the type of symbol that
817 they refer to. For example, when generating position-dependent code,
818 a macro that refers to a symbol may have two different expansions,
819 one which uses GP-relative addresses and one which uses absolute
820 addresses. When generating SVR4-style PIC, a macro may have
821 different expansions for local and global symbols.
822
823 We handle these situations by generating both sequences and putting
824 them in variant frags. In position-dependent code, the first sequence
825 will be the GP-relative one and the second sequence will be the
826 absolute one. In SVR4 PIC, the first sequence will be for global
827 symbols and the second will be for local symbols.
828
829 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
830 SECOND are the lengths of the two sequences in bytes. These fields
831 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
832 the subtype has the following flags:
833
834 RELAX_USE_SECOND
835 Set if it has been decided that we should use the second
836 sequence instead of the first.
837
838 RELAX_SECOND_LONGER
839 Set in the first variant frag if the macro's second implementation
840 is longer than its first. This refers to the macro as a whole,
841 not an individual relaxation.
842
843 RELAX_NOMACRO
844 Set in the first variant frag if the macro appeared in a .set nomacro
845 block and if one alternative requires a warning but the other does not.
846
847 RELAX_DELAY_SLOT
848 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
849 delay slot.
850
851 The frag's "opcode" points to the first fixup for relaxable code.
852
853 Relaxable macros are generated using a sequence such as:
854
855 relax_start (SYMBOL);
856 ... generate first expansion ...
857 relax_switch ();
858 ... generate second expansion ...
859 relax_end ();
860
861 The code and fixups for the unwanted alternative are discarded
862 by md_convert_frag. */
863#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
864
865#define RELAX_FIRST(X) (((X) >> 8) & 0xff)
866#define RELAX_SECOND(X) ((X) & 0xff)
867#define RELAX_USE_SECOND 0x10000
868#define RELAX_SECOND_LONGER 0x20000
869#define RELAX_NOMACRO 0x40000
870#define RELAX_DELAY_SLOT 0x80000
871
872/* Branch without likely bit. If label is out of range, we turn:
873
874 beq reg1, reg2, label
875 delay slot
876
877 into
878
879 bne reg1, reg2, 0f
880 nop
881 j label
882 0: delay slot
883
884 with the following opcode replacements:
885
886 beq <-> bne
887 blez <-> bgtz
888 bltz <-> bgez
889 bc1f <-> bc1t
890
891 bltzal <-> bgezal (with jal label instead of j label)
892
893 Even though keeping the delay slot instruction in the delay slot of
894 the branch would be more efficient, it would be very tricky to do
895 correctly, because we'd have to introduce a variable frag *after*
896 the delay slot instruction, and expand that instead. Let's do it
897 the easy way for now, even if the branch-not-taken case now costs
898 one additional instruction. Out-of-range branches are not supposed
899 to be common, anyway.
900
901 Branch likely. If label is out of range, we turn:
902
903 beql reg1, reg2, label
904 delay slot (annulled if branch not taken)
905
906 into
907
908 beql reg1, reg2, 1f
909 nop
910 beql $0, $0, 2f
911 nop
912 1: j[al] label
913 delay slot (executed only if branch taken)
914 2:
915
916 It would be possible to generate a shorter sequence by losing the
917 likely bit, generating something like:
918
919 bne reg1, reg2, 0f
920 nop
921 j[al] label
922 delay slot (executed only if branch taken)
923 0:
924
925 beql -> bne
926 bnel -> beq
927 blezl -> bgtz
928 bgtzl -> blez
929 bltzl -> bgez
930 bgezl -> bltz
931 bc1fl -> bc1t
932 bc1tl -> bc1f
933
934 bltzall -> bgezal (with jal label instead of j label)
935 bgezall -> bltzal (ditto)
936
937
938 but it's not clear that it would actually improve performance. */
939#define RELAX_BRANCH_ENCODE(at, uncond, likely, link, toofar) \
940 ((relax_substateT) \
941 (0xc0000000 \
942 | ((at) & 0x1f) \
943 | ((toofar) ? 0x20 : 0) \
944 | ((link) ? 0x40 : 0) \
945 | ((likely) ? 0x80 : 0) \
946 | ((uncond) ? 0x100 : 0)))
947#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
948#define RELAX_BRANCH_UNCOND(i) (((i) & 0x100) != 0)
949#define RELAX_BRANCH_LIKELY(i) (((i) & 0x80) != 0)
950#define RELAX_BRANCH_LINK(i) (((i) & 0x40) != 0)
951#define RELAX_BRANCH_TOOFAR(i) (((i) & 0x20) != 0)
952#define RELAX_BRANCH_AT(i) ((i) & 0x1f)
953
954/* For mips16 code, we use an entirely different form of relaxation.
955 mips16 supports two versions of most instructions which take
956 immediate values: a small one which takes some small value, and a
957 larger one which takes a 16 bit value. Since branches also follow
958 this pattern, relaxing these values is required.
959
960 We can assemble both mips16 and normal MIPS code in a single
961 object. Therefore, we need to support this type of relaxation at
962 the same time that we support the relaxation described above. We
963 use the high bit of the subtype field to distinguish these cases.
964
965 The information we store for this type of relaxation is the
966 argument code found in the opcode file for this relocation, whether
967 the user explicitly requested a small or extended form, and whether
968 the relocation is in a jump or jal delay slot. That tells us the
969 size of the value, and how it should be stored. We also store
970 whether the fragment is considered to be extended or not. We also
971 store whether this is known to be a branch to a different section,
972 whether we have tried to relax this frag yet, and whether we have
973 ever extended a PC relative fragment because of a shift count. */
974#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
975 (0x80000000 \
976 | ((type) & 0xff) \
977 | ((small) ? 0x100 : 0) \
978 | ((ext) ? 0x200 : 0) \
979 | ((dslot) ? 0x400 : 0) \
980 | ((jal_dslot) ? 0x800 : 0))
981#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
982#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
983#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
984#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
985#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
986#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
987#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
988#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
989#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
990#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
991#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
992#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
993
994/* Is the given value a sign-extended 32-bit value? */
995#define IS_SEXT_32BIT_NUM(x) \
996 (((x) &~ (offsetT) 0x7fffffff) == 0 \
997 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
998
999/* Is the given value a sign-extended 16-bit value? */
1000#define IS_SEXT_16BIT_NUM(x) \
1001 (((x) &~ (offsetT) 0x7fff) == 0 \
1002 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1003
1004/* Is the given value a zero-extended 32-bit value? Or a negated one? */
1005#define IS_ZEXT_32BIT_NUM(x) \
1006 (((x) &~ (offsetT) 0xffffffff) == 0 \
1007 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1008
1009/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
1010 VALUE << SHIFT. VALUE is evaluated exactly once. */
1011#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
1012 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
1013 | (((VALUE) & (MASK)) << (SHIFT)))
1014
1015/* Extract bits MASK << SHIFT from STRUCT and shift them right
1016 SHIFT places. */
1017#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1018 (((STRUCT) >> (SHIFT)) & (MASK))
1019
1020/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
1021 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
1022
1023 include/opcode/mips.h specifies operand fields using the macros
1024 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
1025 with "MIPS16OP" instead of "OP". */
1026#define INSERT_OPERAND(FIELD, INSN, VALUE) \
1027 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
1028#define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
1029 INSERT_BITS ((INSN).insn_opcode, VALUE, \
1030 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
1031
1032/* Extract the operand given by FIELD from mips_cl_insn INSN. */
1033#define EXTRACT_OPERAND(FIELD, INSN) \
1034 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
1035#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1036 EXTRACT_BITS ((INSN).insn_opcode, \
1037 MIPS16OP_MASK_##FIELD, \
1038 MIPS16OP_SH_##FIELD)
1039\f
1040/* Global variables used when generating relaxable macros. See the
1041 comment above RELAX_ENCODE for more details about how relaxation
1042 is used. */
1043static struct {
1044 /* 0 if we're not emitting a relaxable macro.
1045 1 if we're emitting the first of the two relaxation alternatives.
1046 2 if we're emitting the second alternative. */
1047 int sequence;
1048
1049 /* The first relaxable fixup in the current frag. (In other words,
1050 the first fixup that refers to relaxable code.) */
1051 fixS *first_fixup;
1052
1053 /* sizes[0] says how many bytes of the first alternative are stored in
1054 the current frag. Likewise sizes[1] for the second alternative. */
1055 unsigned int sizes[2];
1056
1057 /* The symbol on which the choice of sequence depends. */
1058 symbolS *symbol;
1059} mips_relax;
1060\f
1061/* Global variables used to decide whether a macro needs a warning. */
1062static struct {
1063 /* True if the macro is in a branch delay slot. */
1064 bfd_boolean delay_slot_p;
1065
1066 /* For relaxable macros, sizes[0] is the length of the first alternative
1067 in bytes and sizes[1] is the length of the second alternative.
1068 For non-relaxable macros, both elements give the length of the
1069 macro in bytes. */
1070 unsigned int sizes[2];
1071
1072 /* The first variant frag for this macro. */
1073 fragS *first_frag;
1074} mips_macro_warning;
1075\f
1076/* Prototypes for static functions. */
1077
1078#define internalError() \
1079 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1080
1081enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
1082
1083static void append_insn
1084 (struct mips_cl_insn *, expressionS *, bfd_reloc_code_real_type *);
1085static void mips_no_prev_insn (void);
1086static void macro_build (expressionS *, const char *, const char *, ...);
1087static void mips16_macro_build
1088 (expressionS *, const char *, const char *, va_list *);
1089static void load_register (int, expressionS *, int);
1090static void macro_start (void);
1091static void macro_end (void);
1092static void macro (struct mips_cl_insn * ip);
1093static void mips16_macro (struct mips_cl_insn * ip);
1094static void mips_ip (char *str, struct mips_cl_insn * ip);
1095static void mips16_ip (char *str, struct mips_cl_insn * ip);
1096static void mips16_immed
1097 (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
1098 unsigned long *, bfd_boolean *, unsigned short *);
1099static size_t my_getSmallExpression
1100 (expressionS *, bfd_reloc_code_real_type *, char *);
1101static void my_getExpression (expressionS *, char *);
1102static void s_align (int);
1103static void s_change_sec (int);
1104static void s_change_section (int);
1105static void s_cons (int);
1106static void s_float_cons (int);
1107static void s_mips_globl (int);
1108static void s_option (int);
1109static void s_mipsset (int);
1110static void s_abicalls (int);
1111static void s_cpload (int);
1112static void s_cpsetup (int);
1113static void s_cplocal (int);
1114static void s_cprestore (int);
1115static void s_cpreturn (int);
1116static void s_dtprelword (int);
1117static void s_dtpreldword (int);
1118static void s_gpvalue (int);
1119static void s_gpword (int);
1120static void s_gpdword (int);
1121static void s_cpadd (int);
1122static void s_insn (int);
1123static void md_obj_begin (void);
1124static void md_obj_end (void);
1125static void s_mips_ent (int);
1126static void s_mips_end (int);
1127static void s_mips_frame (int);
1128static void s_mips_mask (int reg_type);
1129static void s_mips_stab (int);
1130static void s_mips_weakext (int);
1131static void s_mips_file (int);
1132static void s_mips_loc (int);
1133static bfd_boolean pic_need_relax (symbolS *, asection *);
1134static int relaxed_branch_length (fragS *, asection *, int);
1135static int validate_mips_insn (const struct mips_opcode *);
1136
1137/* Table and functions used to map between CPU/ISA names, and
1138 ISA levels, and CPU numbers. */
1139
1140struct mips_cpu_info
1141{
1142 const char *name; /* CPU or ISA name. */
1143 int flags; /* ASEs available, or ISA flag. */
1144 int isa; /* ISA level. */
1145 int cpu; /* CPU number (default CPU if ISA). */
1146};
1147
1148#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1149#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1150#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1151#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1152#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1153#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1154#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1155
1156static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1157static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1158static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1159\f
1160/* Pseudo-op table.
1161
1162 The following pseudo-ops from the Kane and Heinrich MIPS book
1163 should be defined here, but are currently unsupported: .alias,
1164 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1165
1166 The following pseudo-ops from the Kane and Heinrich MIPS book are
1167 specific to the type of debugging information being generated, and
1168 should be defined by the object format: .aent, .begin, .bend,
1169 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1170 .vreg.
1171
1172 The following pseudo-ops from the Kane and Heinrich MIPS book are
1173 not MIPS CPU specific, but are also not specific to the object file
1174 format. This file is probably the best place to define them, but
1175 they are not currently supported: .asm0, .endr, .lab, .struct. */
1176
1177static const pseudo_typeS mips_pseudo_table[] =
1178{
1179 /* MIPS specific pseudo-ops. */
1180 {"option", s_option, 0},
1181 {"set", s_mipsset, 0},
1182 {"rdata", s_change_sec, 'r'},
1183 {"sdata", s_change_sec, 's'},
1184 {"livereg", s_ignore, 0},
1185 {"abicalls", s_abicalls, 0},
1186 {"cpload", s_cpload, 0},
1187 {"cpsetup", s_cpsetup, 0},
1188 {"cplocal", s_cplocal, 0},
1189 {"cprestore", s_cprestore, 0},
1190 {"cpreturn", s_cpreturn, 0},
1191 {"dtprelword", s_dtprelword, 0},
1192 {"dtpreldword", s_dtpreldword, 0},
1193 {"gpvalue", s_gpvalue, 0},
1194 {"gpword", s_gpword, 0},
1195 {"gpdword", s_gpdword, 0},
1196 {"cpadd", s_cpadd, 0},
1197 {"insn", s_insn, 0},
1198
1199 /* Relatively generic pseudo-ops that happen to be used on MIPS
1200 chips. */
1201 {"asciiz", stringer, 8 + 1},
1202 {"bss", s_change_sec, 'b'},
1203 {"err", s_err, 0},
1204 {"half", s_cons, 1},
1205 {"dword", s_cons, 3},
1206 {"weakext", s_mips_weakext, 0},
1207 {"origin", s_org, 0},
1208 {"repeat", s_rept, 0},
1209
1210 /* For MIPS this is non-standard, but we define it for consistency. */
1211 {"sbss", s_change_sec, 'B'},
1212
1213 /* These pseudo-ops are defined in read.c, but must be overridden
1214 here for one reason or another. */
1215 {"align", s_align, 0},
1216 {"byte", s_cons, 0},
1217 {"data", s_change_sec, 'd'},
1218 {"double", s_float_cons, 'd'},
1219 {"float", s_float_cons, 'f'},
1220 {"globl", s_mips_globl, 0},
1221 {"global", s_mips_globl, 0},
1222 {"hword", s_cons, 1},
1223 {"int", s_cons, 2},
1224 {"long", s_cons, 2},
1225 {"octa", s_cons, 4},
1226 {"quad", s_cons, 3},
1227 {"section", s_change_section, 0},
1228 {"short", s_cons, 1},
1229 {"single", s_float_cons, 'f'},
1230 {"stabn", s_mips_stab, 'n'},
1231 {"text", s_change_sec, 't'},
1232 {"word", s_cons, 2},
1233
1234 { "extern", ecoff_directive_extern, 0},
1235
1236 { NULL, NULL, 0 },
1237};
1238
1239static const pseudo_typeS mips_nonecoff_pseudo_table[] =
1240{
1241 /* These pseudo-ops should be defined by the object file format.
1242 However, a.out doesn't support them, so we have versions here. */
1243 {"aent", s_mips_ent, 1},
1244 {"bgnb", s_ignore, 0},
1245 {"end", s_mips_end, 0},
1246 {"endb", s_ignore, 0},
1247 {"ent", s_mips_ent, 0},
1248 {"file", s_mips_file, 0},
1249 {"fmask", s_mips_mask, 'F'},
1250 {"frame", s_mips_frame, 0},
1251 {"loc", s_mips_loc, 0},
1252 {"mask", s_mips_mask, 'R'},
1253 {"verstamp", s_ignore, 0},
1254 { NULL, NULL, 0 },
1255};
1256
1257/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1258 purpose of the `.dc.a' internal pseudo-op. */
1259
1260int
1261mips_address_bytes (void)
1262{
1263 return HAVE_64BIT_ADDRESSES ? 8 : 4;
1264}
1265
1266extern void pop_insert (const pseudo_typeS *);
1267
1268void
1269mips_pop_insert (void)
1270{
1271 pop_insert (mips_pseudo_table);
1272 if (! ECOFF_DEBUGGING)
1273 pop_insert (mips_nonecoff_pseudo_table);
1274}
1275\f
1276/* Symbols labelling the current insn. */
1277
1278struct insn_label_list
1279{
1280 struct insn_label_list *next;
1281 symbolS *label;
1282};
1283
1284static struct insn_label_list *free_insn_labels;
1285#define label_list tc_segment_info_data.labels
1286
1287static void mips_clear_insn_labels (void);
1288
1289static inline void
1290mips_clear_insn_labels (void)
1291{
1292 register struct insn_label_list **pl;
1293 segment_info_type *si;
1294
1295 if (now_seg)
1296 {
1297 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1298 ;
1299
1300 si = seg_info (now_seg);
1301 *pl = si->label_list;
1302 si->label_list = NULL;
1303 }
1304}
1305
1306\f
1307static char *expr_end;
1308
1309/* Expressions which appear in instructions. These are set by
1310 mips_ip. */
1311
1312static expressionS imm_expr;
1313static expressionS imm2_expr;
1314static expressionS offset_expr;
1315
1316/* Relocs associated with imm_expr and offset_expr. */
1317
1318static bfd_reloc_code_real_type imm_reloc[3]
1319 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1320static bfd_reloc_code_real_type offset_reloc[3]
1321 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
1322
1323/* These are set by mips16_ip if an explicit extension is used. */
1324
1325static bfd_boolean mips16_small, mips16_ext;
1326
1327#ifdef OBJ_ELF
1328/* The pdr segment for per procedure frame/regmask info. Not used for
1329 ECOFF debugging. */
1330
1331static segT pdr_seg;
1332#endif
1333
1334/* The default target format to use. */
1335
1336#if defined (TE_FreeBSD)
1337#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
1338#elif defined (TE_TMIPS)
1339#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
1340#else
1341#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
1342#endif
1343
1344const char *
1345mips_target_format (void)
1346{
1347 switch (OUTPUT_FLAVOR)
1348 {
1349 case bfd_target_ecoff_flavour:
1350 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1351 case bfd_target_coff_flavour:
1352 return "pe-mips";
1353 case bfd_target_elf_flavour:
1354#ifdef TE_VXWORKS
1355 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1356 return (target_big_endian
1357 ? "elf32-bigmips-vxworks"
1358 : "elf32-littlemips-vxworks");
1359#endif
1360 return (target_big_endian
1361 ? (HAVE_64BIT_OBJECTS
1362 ? ELF_TARGET ("elf64-", "big")
1363 : (HAVE_NEWABI
1364 ? ELF_TARGET ("elf32-n", "big")
1365 : ELF_TARGET ("elf32-", "big")))
1366 : (HAVE_64BIT_OBJECTS
1367 ? ELF_TARGET ("elf64-", "little")
1368 : (HAVE_NEWABI
1369 ? ELF_TARGET ("elf32-n", "little")
1370 : ELF_TARGET ("elf32-", "little"))));
1371 default:
1372 abort ();
1373 return NULL;
1374 }
1375}
1376
1377/* Return the length of instruction INSN. */
1378
1379static inline unsigned int
1380insn_length (const struct mips_cl_insn *insn)
1381{
1382 if (!mips_opts.mips16)
1383 return 4;
1384 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1385}
1386
1387/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1388
1389static void
1390create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1391{
1392 size_t i;
1393
1394 insn->insn_mo = mo;
1395 insn->use_extend = FALSE;
1396 insn->extend = 0;
1397 insn->insn_opcode = mo->match;
1398 insn->frag = NULL;
1399 insn->where = 0;
1400 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1401 insn->fixp[i] = NULL;
1402 insn->fixed_p = (mips_opts.noreorder > 0);
1403 insn->noreorder_p = (mips_opts.noreorder > 0);
1404 insn->mips16_absolute_jump_p = 0;
1405 insn->complete_p = 0;
1406}
1407
1408/* Record the current MIPS16 mode in now_seg. */
1409
1410static void
1411mips_record_mips16_mode (void)
1412{
1413 segment_info_type *si;
1414
1415 si = seg_info (now_seg);
1416 if (si->tc_segment_info_data.mips16 != mips_opts.mips16)
1417 si->tc_segment_info_data.mips16 = mips_opts.mips16;
1418}
1419
1420/* Install INSN at the location specified by its "frag" and "where" fields. */
1421
1422static void
1423install_insn (const struct mips_cl_insn *insn)
1424{
1425 char *f = insn->frag->fr_literal + insn->where;
1426 if (!mips_opts.mips16)
1427 md_number_to_chars (f, insn->insn_opcode, 4);
1428 else if (insn->mips16_absolute_jump_p)
1429 {
1430 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1431 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1432 }
1433 else
1434 {
1435 if (insn->use_extend)
1436 {
1437 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1438 f += 2;
1439 }
1440 md_number_to_chars (f, insn->insn_opcode, 2);
1441 }
1442 mips_record_mips16_mode ();
1443}
1444
1445/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1446 and install the opcode in the new location. */
1447
1448static void
1449move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1450{
1451 size_t i;
1452
1453 insn->frag = frag;
1454 insn->where = where;
1455 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1456 if (insn->fixp[i] != NULL)
1457 {
1458 insn->fixp[i]->fx_frag = frag;
1459 insn->fixp[i]->fx_where = where;
1460 }
1461 install_insn (insn);
1462}
1463
1464/* Add INSN to the end of the output. */
1465
1466static void
1467add_fixed_insn (struct mips_cl_insn *insn)
1468{
1469 char *f = frag_more (insn_length (insn));
1470 move_insn (insn, frag_now, f - frag_now->fr_literal);
1471}
1472
1473/* Start a variant frag and move INSN to the start of the variant part,
1474 marking it as fixed. The other arguments are as for frag_var. */
1475
1476static void
1477add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1478 relax_substateT subtype, symbolS *symbol, offsetT offset)
1479{
1480 frag_grow (max_chars);
1481 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1482 insn->fixed_p = 1;
1483 frag_var (rs_machine_dependent, max_chars, var,
1484 subtype, symbol, offset, NULL);
1485}
1486
1487/* Insert N copies of INSN into the history buffer, starting at
1488 position FIRST. Neither FIRST nor N need to be clipped. */
1489
1490static void
1491insert_into_history (unsigned int first, unsigned int n,
1492 const struct mips_cl_insn *insn)
1493{
1494 if (mips_relax.sequence != 2)
1495 {
1496 unsigned int i;
1497
1498 for (i = ARRAY_SIZE (history); i-- > first;)
1499 if (i >= first + n)
1500 history[i] = history[i - n];
1501 else
1502 history[i] = *insn;
1503 }
1504}
1505
1506/* Emit a nop instruction, recording it in the history buffer. */
1507
1508static void
1509emit_nop (void)
1510{
1511 add_fixed_insn (NOP_INSN);
1512 insert_into_history (0, 1, NOP_INSN);
1513}
1514
1515/* Initialize vr4120_conflicts. There is a bit of duplication here:
1516 the idea is to make it obvious at a glance that each errata is
1517 included. */
1518
1519static void
1520init_vr4120_conflicts (void)
1521{
1522#define CONFLICT(FIRST, SECOND) \
1523 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1524
1525 /* Errata 21 - [D]DIV[U] after [D]MACC */
1526 CONFLICT (MACC, DIV);
1527 CONFLICT (DMACC, DIV);
1528
1529 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1530 CONFLICT (DMULT, DMULT);
1531 CONFLICT (DMULT, DMACC);
1532 CONFLICT (DMACC, DMULT);
1533 CONFLICT (DMACC, DMACC);
1534
1535 /* Errata 24 - MT{LO,HI} after [D]MACC */
1536 CONFLICT (MACC, MTHILO);
1537 CONFLICT (DMACC, MTHILO);
1538
1539 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1540 instruction is executed immediately after a MACC or DMACC
1541 instruction, the result of [either instruction] is incorrect." */
1542 CONFLICT (MACC, MULT);
1543 CONFLICT (MACC, DMULT);
1544 CONFLICT (DMACC, MULT);
1545 CONFLICT (DMACC, DMULT);
1546
1547 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1548 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1549 DDIV or DDIVU instruction, the result of the MACC or
1550 DMACC instruction is incorrect.". */
1551 CONFLICT (DMULT, MACC);
1552 CONFLICT (DMULT, DMACC);
1553 CONFLICT (DIV, MACC);
1554 CONFLICT (DIV, DMACC);
1555
1556#undef CONFLICT
1557}
1558
1559struct regname {
1560 const char *name;
1561 unsigned int num;
1562};
1563
1564#define RTYPE_MASK 0x1ff00
1565#define RTYPE_NUM 0x00100
1566#define RTYPE_FPU 0x00200
1567#define RTYPE_FCC 0x00400
1568#define RTYPE_VEC 0x00800
1569#define RTYPE_GP 0x01000
1570#define RTYPE_CP0 0x02000
1571#define RTYPE_PC 0x04000
1572#define RTYPE_ACC 0x08000
1573#define RTYPE_CCC 0x10000
1574#define RNUM_MASK 0x000ff
1575#define RWARN 0x80000
1576
1577#define GENERIC_REGISTER_NUMBERS \
1578 {"$0", RTYPE_NUM | 0}, \
1579 {"$1", RTYPE_NUM | 1}, \
1580 {"$2", RTYPE_NUM | 2}, \
1581 {"$3", RTYPE_NUM | 3}, \
1582 {"$4", RTYPE_NUM | 4}, \
1583 {"$5", RTYPE_NUM | 5}, \
1584 {"$6", RTYPE_NUM | 6}, \
1585 {"$7", RTYPE_NUM | 7}, \
1586 {"$8", RTYPE_NUM | 8}, \
1587 {"$9", RTYPE_NUM | 9}, \
1588 {"$10", RTYPE_NUM | 10}, \
1589 {"$11", RTYPE_NUM | 11}, \
1590 {"$12", RTYPE_NUM | 12}, \
1591 {"$13", RTYPE_NUM | 13}, \
1592 {"$14", RTYPE_NUM | 14}, \
1593 {"$15", RTYPE_NUM | 15}, \
1594 {"$16", RTYPE_NUM | 16}, \
1595 {"$17", RTYPE_NUM | 17}, \
1596 {"$18", RTYPE_NUM | 18}, \
1597 {"$19", RTYPE_NUM | 19}, \
1598 {"$20", RTYPE_NUM | 20}, \
1599 {"$21", RTYPE_NUM | 21}, \
1600 {"$22", RTYPE_NUM | 22}, \
1601 {"$23", RTYPE_NUM | 23}, \
1602 {"$24", RTYPE_NUM | 24}, \
1603 {"$25", RTYPE_NUM | 25}, \
1604 {"$26", RTYPE_NUM | 26}, \
1605 {"$27", RTYPE_NUM | 27}, \
1606 {"$28", RTYPE_NUM | 28}, \
1607 {"$29", RTYPE_NUM | 29}, \
1608 {"$30", RTYPE_NUM | 30}, \
1609 {"$31", RTYPE_NUM | 31}
1610
1611#define FPU_REGISTER_NAMES \
1612 {"$f0", RTYPE_FPU | 0}, \
1613 {"$f1", RTYPE_FPU | 1}, \
1614 {"$f2", RTYPE_FPU | 2}, \
1615 {"$f3", RTYPE_FPU | 3}, \
1616 {"$f4", RTYPE_FPU | 4}, \
1617 {"$f5", RTYPE_FPU | 5}, \
1618 {"$f6", RTYPE_FPU | 6}, \
1619 {"$f7", RTYPE_FPU | 7}, \
1620 {"$f8", RTYPE_FPU | 8}, \
1621 {"$f9", RTYPE_FPU | 9}, \
1622 {"$f10", RTYPE_FPU | 10}, \
1623 {"$f11", RTYPE_FPU | 11}, \
1624 {"$f12", RTYPE_FPU | 12}, \
1625 {"$f13", RTYPE_FPU | 13}, \
1626 {"$f14", RTYPE_FPU | 14}, \
1627 {"$f15", RTYPE_FPU | 15}, \
1628 {"$f16", RTYPE_FPU | 16}, \
1629 {"$f17", RTYPE_FPU | 17}, \
1630 {"$f18", RTYPE_FPU | 18}, \
1631 {"$f19", RTYPE_FPU | 19}, \
1632 {"$f20", RTYPE_FPU | 20}, \
1633 {"$f21", RTYPE_FPU | 21}, \
1634 {"$f22", RTYPE_FPU | 22}, \
1635 {"$f23", RTYPE_FPU | 23}, \
1636 {"$f24", RTYPE_FPU | 24}, \
1637 {"$f25", RTYPE_FPU | 25}, \
1638 {"$f26", RTYPE_FPU | 26}, \
1639 {"$f27", RTYPE_FPU | 27}, \
1640 {"$f28", RTYPE_FPU | 28}, \
1641 {"$f29", RTYPE_FPU | 29}, \
1642 {"$f30", RTYPE_FPU | 30}, \
1643 {"$f31", RTYPE_FPU | 31}
1644
1645#define FPU_CONDITION_CODE_NAMES \
1646 {"$fcc0", RTYPE_FCC | 0}, \
1647 {"$fcc1", RTYPE_FCC | 1}, \
1648 {"$fcc2", RTYPE_FCC | 2}, \
1649 {"$fcc3", RTYPE_FCC | 3}, \
1650 {"$fcc4", RTYPE_FCC | 4}, \
1651 {"$fcc5", RTYPE_FCC | 5}, \
1652 {"$fcc6", RTYPE_FCC | 6}, \
1653 {"$fcc7", RTYPE_FCC | 7}
1654
1655#define COPROC_CONDITION_CODE_NAMES \
1656 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1657 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1658 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1659 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1660 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1661 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1662 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1663 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1664
1665#define N32N64_SYMBOLIC_REGISTER_NAMES \
1666 {"$a4", RTYPE_GP | 8}, \
1667 {"$a5", RTYPE_GP | 9}, \
1668 {"$a6", RTYPE_GP | 10}, \
1669 {"$a7", RTYPE_GP | 11}, \
1670 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1671 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1672 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1673 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1674 {"$t0", RTYPE_GP | 12}, \
1675 {"$t1", RTYPE_GP | 13}, \
1676 {"$t2", RTYPE_GP | 14}, \
1677 {"$t3", RTYPE_GP | 15}
1678
1679#define O32_SYMBOLIC_REGISTER_NAMES \
1680 {"$t0", RTYPE_GP | 8}, \
1681 {"$t1", RTYPE_GP | 9}, \
1682 {"$t2", RTYPE_GP | 10}, \
1683 {"$t3", RTYPE_GP | 11}, \
1684 {"$t4", RTYPE_GP | 12}, \
1685 {"$t5", RTYPE_GP | 13}, \
1686 {"$t6", RTYPE_GP | 14}, \
1687 {"$t7", RTYPE_GP | 15}, \
1688 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1689 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1690 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1691 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1692
1693/* Remaining symbolic register names */
1694#define SYMBOLIC_REGISTER_NAMES \
1695 {"$zero", RTYPE_GP | 0}, \
1696 {"$at", RTYPE_GP | 1}, \
1697 {"$AT", RTYPE_GP | 1}, \
1698 {"$v0", RTYPE_GP | 2}, \
1699 {"$v1", RTYPE_GP | 3}, \
1700 {"$a0", RTYPE_GP | 4}, \
1701 {"$a1", RTYPE_GP | 5}, \
1702 {"$a2", RTYPE_GP | 6}, \
1703 {"$a3", RTYPE_GP | 7}, \
1704 {"$s0", RTYPE_GP | 16}, \
1705 {"$s1", RTYPE_GP | 17}, \
1706 {"$s2", RTYPE_GP | 18}, \
1707 {"$s3", RTYPE_GP | 19}, \
1708 {"$s4", RTYPE_GP | 20}, \
1709 {"$s5", RTYPE_GP | 21}, \
1710 {"$s6", RTYPE_GP | 22}, \
1711 {"$s7", RTYPE_GP | 23}, \
1712 {"$t8", RTYPE_GP | 24}, \
1713 {"$t9", RTYPE_GP | 25}, \
1714 {"$k0", RTYPE_GP | 26}, \
1715 {"$kt0", RTYPE_GP | 26}, \
1716 {"$k1", RTYPE_GP | 27}, \
1717 {"$kt1", RTYPE_GP | 27}, \
1718 {"$gp", RTYPE_GP | 28}, \
1719 {"$sp", RTYPE_GP | 29}, \
1720 {"$s8", RTYPE_GP | 30}, \
1721 {"$fp", RTYPE_GP | 30}, \
1722 {"$ra", RTYPE_GP | 31}
1723
1724#define MIPS16_SPECIAL_REGISTER_NAMES \
1725 {"$pc", RTYPE_PC | 0}
1726
1727#define MDMX_VECTOR_REGISTER_NAMES \
1728 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1729 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1730 {"$v2", RTYPE_VEC | 2}, \
1731 {"$v3", RTYPE_VEC | 3}, \
1732 {"$v4", RTYPE_VEC | 4}, \
1733 {"$v5", RTYPE_VEC | 5}, \
1734 {"$v6", RTYPE_VEC | 6}, \
1735 {"$v7", RTYPE_VEC | 7}, \
1736 {"$v8", RTYPE_VEC | 8}, \
1737 {"$v9", RTYPE_VEC | 9}, \
1738 {"$v10", RTYPE_VEC | 10}, \
1739 {"$v11", RTYPE_VEC | 11}, \
1740 {"$v12", RTYPE_VEC | 12}, \
1741 {"$v13", RTYPE_VEC | 13}, \
1742 {"$v14", RTYPE_VEC | 14}, \
1743 {"$v15", RTYPE_VEC | 15}, \
1744 {"$v16", RTYPE_VEC | 16}, \
1745 {"$v17", RTYPE_VEC | 17}, \
1746 {"$v18", RTYPE_VEC | 18}, \
1747 {"$v19", RTYPE_VEC | 19}, \
1748 {"$v20", RTYPE_VEC | 20}, \
1749 {"$v21", RTYPE_VEC | 21}, \
1750 {"$v22", RTYPE_VEC | 22}, \
1751 {"$v23", RTYPE_VEC | 23}, \
1752 {"$v24", RTYPE_VEC | 24}, \
1753 {"$v25", RTYPE_VEC | 25}, \
1754 {"$v26", RTYPE_VEC | 26}, \
1755 {"$v27", RTYPE_VEC | 27}, \
1756 {"$v28", RTYPE_VEC | 28}, \
1757 {"$v29", RTYPE_VEC | 29}, \
1758 {"$v30", RTYPE_VEC | 30}, \
1759 {"$v31", RTYPE_VEC | 31}
1760
1761#define MIPS_DSP_ACCUMULATOR_NAMES \
1762 {"$ac0", RTYPE_ACC | 0}, \
1763 {"$ac1", RTYPE_ACC | 1}, \
1764 {"$ac2", RTYPE_ACC | 2}, \
1765 {"$ac3", RTYPE_ACC | 3}
1766
1767static const struct regname reg_names[] = {
1768 GENERIC_REGISTER_NUMBERS,
1769 FPU_REGISTER_NAMES,
1770 FPU_CONDITION_CODE_NAMES,
1771 COPROC_CONDITION_CODE_NAMES,
1772
1773 /* The $txx registers depends on the abi,
1774 these will be added later into the symbol table from
1775 one of the tables below once mips_abi is set after
1776 parsing of arguments from the command line. */
1777 SYMBOLIC_REGISTER_NAMES,
1778
1779 MIPS16_SPECIAL_REGISTER_NAMES,
1780 MDMX_VECTOR_REGISTER_NAMES,
1781 MIPS_DSP_ACCUMULATOR_NAMES,
1782 {0, 0}
1783};
1784
1785static const struct regname reg_names_o32[] = {
1786 O32_SYMBOLIC_REGISTER_NAMES,
1787 {0, 0}
1788};
1789
1790static const struct regname reg_names_n32n64[] = {
1791 N32N64_SYMBOLIC_REGISTER_NAMES,
1792 {0, 0}
1793};
1794
1795static int
1796reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1797{
1798 symbolS *symbolP;
1799 char *e;
1800 char save_c;
1801 int reg = -1;
1802
1803 /* Find end of name. */
1804 e = *s;
1805 if (is_name_beginner (*e))
1806 ++e;
1807 while (is_part_of_name (*e))
1808 ++e;
1809
1810 /* Terminate name. */
1811 save_c = *e;
1812 *e = '\0';
1813
1814 /* Look for a register symbol. */
1815 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1816 {
1817 int r = S_GET_VALUE (symbolP);
1818 if (r & types)
1819 reg = r & RNUM_MASK;
1820 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1821 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1822 reg = (r & RNUM_MASK) - 2;
1823 }
1824 /* Else see if this is a register defined in an itbl entry. */
1825 else if ((types & RTYPE_GP) && itbl_have_entries)
1826 {
1827 char *n = *s;
1828 unsigned long r;
1829
1830 if (*n == '$')
1831 ++n;
1832 if (itbl_get_reg_val (n, &r))
1833 reg = r & RNUM_MASK;
1834 }
1835
1836 /* Advance to next token if a register was recognised. */
1837 if (reg >= 0)
1838 *s = e;
1839 else if (types & RWARN)
1840 as_warn (_("Unrecognized register name `%s'"), *s);
1841
1842 *e = save_c;
1843 if (regnop)
1844 *regnop = reg;
1845 return reg >= 0;
1846}
1847
1848/* Return TRUE if opcode MO is valid on the currently selected ISA and
1849 architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
1850
1851static bfd_boolean
1852is_opcode_valid (const struct mips_opcode *mo)
1853{
1854 int isa = mips_opts.isa;
1855 int fp_s, fp_d;
1856
1857 if (mips_opts.ase_mdmx)
1858 isa |= INSN_MDMX;
1859 if (mips_opts.ase_dsp)
1860 isa |= INSN_DSP;
1861 if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
1862 isa |= INSN_DSP64;
1863 if (mips_opts.ase_dspr2)
1864 isa |= INSN_DSPR2;
1865 if (mips_opts.ase_mt)
1866 isa |= INSN_MT;
1867 if (mips_opts.ase_mips3d)
1868 isa |= INSN_MIPS3D;
1869 if (mips_opts.ase_smartmips)
1870 isa |= INSN_SMARTMIPS;
1871
1872 /* Don't accept instructions based on the ISA if the CPU does not implement
1873 all the coprocessor insns. */
1874 if (NO_ISA_COP (mips_opts.arch)
1875 && COP_INSN (mo->pinfo))
1876 isa = 0;
1877
1878 if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
1879 return FALSE;
1880
1881 /* Check whether the instruction or macro requires single-precision or
1882 double-precision floating-point support. Note that this information is
1883 stored differently in the opcode table for insns and macros. */
1884 if (mo->pinfo == INSN_MACRO)
1885 {
1886 fp_s = mo->pinfo2 & INSN2_M_FP_S;
1887 fp_d = mo->pinfo2 & INSN2_M_FP_D;
1888 }
1889 else
1890 {
1891 fp_s = mo->pinfo & FP_S;
1892 fp_d = mo->pinfo & FP_D;
1893 }
1894
1895 if (fp_d && (mips_opts.soft_float || mips_opts.single_float))
1896 return FALSE;
1897
1898 if (fp_s && mips_opts.soft_float)
1899 return FALSE;
1900
1901 return TRUE;
1902}
1903
1904/* Return TRUE if the MIPS16 opcode MO is valid on the currently
1905 selected ISA and architecture. */
1906
1907static bfd_boolean
1908is_opcode_valid_16 (const struct mips_opcode *mo)
1909{
1910 return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
1911}
1912
1913/* This function is called once, at assembler startup time. It should set up
1914 all the tables, etc. that the MD part of the assembler will need. */
1915
1916void
1917md_begin (void)
1918{
1919 const char *retval = NULL;
1920 int i = 0;
1921 int broken = 0;
1922
1923 if (mips_pic != NO_PIC)
1924 {
1925 if (g_switch_seen && g_switch_value != 0)
1926 as_bad (_("-G may not be used in position-independent code"));
1927 g_switch_value = 0;
1928 }
1929
1930 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1931 as_warn (_("Could not set architecture and machine"));
1932
1933 op_hash = hash_new ();
1934
1935 for (i = 0; i < NUMOPCODES;)
1936 {
1937 const char *name = mips_opcodes[i].name;
1938
1939 retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
1940 if (retval != NULL)
1941 {
1942 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1943 mips_opcodes[i].name, retval);
1944 /* Probably a memory allocation problem? Give up now. */
1945 as_fatal (_("Broken assembler. No assembly attempted."));
1946 }
1947 do
1948 {
1949 if (mips_opcodes[i].pinfo != INSN_MACRO)
1950 {
1951 if (!validate_mips_insn (&mips_opcodes[i]))
1952 broken = 1;
1953 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1954 {
1955 create_insn (&nop_insn, mips_opcodes + i);
1956 if (mips_fix_loongson2f_nop)
1957 nop_insn.insn_opcode = LOONGSON2F_NOP_INSN;
1958 nop_insn.fixed_p = 1;
1959 }
1960 }
1961 ++i;
1962 }
1963 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1964 }
1965
1966 mips16_op_hash = hash_new ();
1967
1968 i = 0;
1969 while (i < bfd_mips16_num_opcodes)
1970 {
1971 const char *name = mips16_opcodes[i].name;
1972
1973 retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
1974 if (retval != NULL)
1975 as_fatal (_("internal: can't hash `%s': %s"),
1976 mips16_opcodes[i].name, retval);
1977 do
1978 {
1979 if (mips16_opcodes[i].pinfo != INSN_MACRO
1980 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1981 != mips16_opcodes[i].match))
1982 {
1983 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1984 mips16_opcodes[i].name, mips16_opcodes[i].args);
1985 broken = 1;
1986 }
1987 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1988 {
1989 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1990 mips16_nop_insn.fixed_p = 1;
1991 }
1992 ++i;
1993 }
1994 while (i < bfd_mips16_num_opcodes
1995 && strcmp (mips16_opcodes[i].name, name) == 0);
1996 }
1997
1998 if (broken)
1999 as_fatal (_("Broken assembler. No assembly attempted."));
2000
2001 /* We add all the general register names to the symbol table. This
2002 helps us detect invalid uses of them. */
2003 for (i = 0; reg_names[i].name; i++)
2004 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
2005 reg_names[i].num, /* & RNUM_MASK, */
2006 &zero_address_frag));
2007 if (HAVE_NEWABI)
2008 for (i = 0; reg_names_n32n64[i].name; i++)
2009 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
2010 reg_names_n32n64[i].num, /* & RNUM_MASK, */
2011 &zero_address_frag));
2012 else
2013 for (i = 0; reg_names_o32[i].name; i++)
2014 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
2015 reg_names_o32[i].num, /* & RNUM_MASK, */
2016 &zero_address_frag));
2017
2018 mips_no_prev_insn ();
2019
2020 mips_gprmask = 0;
2021 mips_cprmask[0] = 0;
2022 mips_cprmask[1] = 0;
2023 mips_cprmask[2] = 0;
2024 mips_cprmask[3] = 0;
2025
2026 /* set the default alignment for the text section (2**2) */
2027 record_alignment (text_section, 2);
2028
2029 bfd_set_gp_size (stdoutput, g_switch_value);
2030
2031#ifdef OBJ_ELF
2032 if (IS_ELF)
2033 {
2034 /* On a native system other than VxWorks, sections must be aligned
2035 to 16 byte boundaries. When configured for an embedded ELF
2036 target, we don't bother. */
2037 if (strncmp (TARGET_OS, "elf", 3) != 0
2038 && strncmp (TARGET_OS, "vxworks", 7) != 0)
2039 {
2040 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
2041 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
2042 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
2043 }
2044
2045 /* Create a .reginfo section for register masks and a .mdebug
2046 section for debugging information. */
2047 {
2048 segT seg;
2049 subsegT subseg;
2050 flagword flags;
2051 segT sec;
2052
2053 seg = now_seg;
2054 subseg = now_subseg;
2055
2056 /* The ABI says this section should be loaded so that the
2057 running program can access it. However, we don't load it
2058 if we are configured for an embedded target */
2059 flags = SEC_READONLY | SEC_DATA;
2060 if (strncmp (TARGET_OS, "elf", 3) != 0)
2061 flags |= SEC_ALLOC | SEC_LOAD;
2062
2063 if (mips_abi != N64_ABI)
2064 {
2065 sec = subseg_new (".reginfo", (subsegT) 0);
2066
2067 bfd_set_section_flags (stdoutput, sec, flags);
2068 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
2069
2070 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
2071 }
2072 else
2073 {
2074 /* The 64-bit ABI uses a .MIPS.options section rather than
2075 .reginfo section. */
2076 sec = subseg_new (".MIPS.options", (subsegT) 0);
2077 bfd_set_section_flags (stdoutput, sec, flags);
2078 bfd_set_section_alignment (stdoutput, sec, 3);
2079
2080 /* Set up the option header. */
2081 {
2082 Elf_Internal_Options opthdr;
2083 char *f;
2084
2085 opthdr.kind = ODK_REGINFO;
2086 opthdr.size = (sizeof (Elf_External_Options)
2087 + sizeof (Elf64_External_RegInfo));
2088 opthdr.section = 0;
2089 opthdr.info = 0;
2090 f = frag_more (sizeof (Elf_External_Options));
2091 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
2092 (Elf_External_Options *) f);
2093
2094 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
2095 }
2096 }
2097
2098 if (ECOFF_DEBUGGING)
2099 {
2100 sec = subseg_new (".mdebug", (subsegT) 0);
2101 (void) bfd_set_section_flags (stdoutput, sec,
2102 SEC_HAS_CONTENTS | SEC_READONLY);
2103 (void) bfd_set_section_alignment (stdoutput, sec, 2);
2104 }
2105 else if (mips_flag_pdr)
2106 {
2107 pdr_seg = subseg_new (".pdr", (subsegT) 0);
2108 (void) bfd_set_section_flags (stdoutput, pdr_seg,
2109 SEC_READONLY | SEC_RELOC
2110 | SEC_DEBUGGING);
2111 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
2112 }
2113
2114 subseg_set (seg, subseg);
2115 }
2116 }
2117#endif /* OBJ_ELF */
2118
2119 if (! ECOFF_DEBUGGING)
2120 md_obj_begin ();
2121
2122 if (mips_fix_vr4120)
2123 init_vr4120_conflicts ();
2124}
2125
2126void
2127md_mips_end (void)
2128{
2129 mips_emit_delays ();
2130 if (! ECOFF_DEBUGGING)
2131 md_obj_end ();
2132}
2133
2134void
2135md_assemble (char *str)
2136{
2137 struct mips_cl_insn insn;
2138 bfd_reloc_code_real_type unused_reloc[3]
2139 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
2140
2141 imm_expr.X_op = O_absent;
2142 imm2_expr.X_op = O_absent;
2143 offset_expr.X_op = O_absent;
2144 imm_reloc[0] = BFD_RELOC_UNUSED;
2145 imm_reloc[1] = BFD_RELOC_UNUSED;
2146 imm_reloc[2] = BFD_RELOC_UNUSED;
2147 offset_reloc[0] = BFD_RELOC_UNUSED;
2148 offset_reloc[1] = BFD_RELOC_UNUSED;
2149 offset_reloc[2] = BFD_RELOC_UNUSED;
2150
2151 if (mips_opts.mips16)
2152 mips16_ip (str, &insn);
2153 else
2154 {
2155 mips_ip (str, &insn);
2156 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2157 str, insn.insn_opcode));
2158 }
2159
2160 if (insn_error)
2161 {
2162 as_bad ("%s `%s'", insn_error, str);
2163 return;
2164 }
2165
2166 if (insn.insn_mo->pinfo == INSN_MACRO)
2167 {
2168 macro_start ();
2169 if (mips_opts.mips16)
2170 mips16_macro (&insn);
2171 else
2172 macro (&insn);
2173 macro_end ();
2174 }
2175 else
2176 {
2177 if (imm_expr.X_op != O_absent)
2178 append_insn (&insn, &imm_expr, imm_reloc);
2179 else if (offset_expr.X_op != O_absent)
2180 append_insn (&insn, &offset_expr, offset_reloc);
2181 else
2182 append_insn (&insn, NULL, unused_reloc);
2183 }
2184}
2185
2186/* Convenience functions for abstracting away the differences between
2187 MIPS16 and non-MIPS16 relocations. */
2188
2189static inline bfd_boolean
2190mips16_reloc_p (bfd_reloc_code_real_type reloc)
2191{
2192 switch (reloc)
2193 {
2194 case BFD_RELOC_MIPS16_JMP:
2195 case BFD_RELOC_MIPS16_GPREL:
2196 case BFD_RELOC_MIPS16_GOT16:
2197 case BFD_RELOC_MIPS16_CALL16:
2198 case BFD_RELOC_MIPS16_HI16_S:
2199 case BFD_RELOC_MIPS16_HI16:
2200 case BFD_RELOC_MIPS16_LO16:
2201 return TRUE;
2202
2203 default:
2204 return FALSE;
2205 }
2206}
2207
2208static inline bfd_boolean
2209got16_reloc_p (bfd_reloc_code_real_type reloc)
2210{
2211 return reloc == BFD_RELOC_MIPS_GOT16 || reloc == BFD_RELOC_MIPS16_GOT16;
2212}
2213
2214static inline bfd_boolean
2215hi16_reloc_p (bfd_reloc_code_real_type reloc)
2216{
2217 return reloc == BFD_RELOC_HI16_S || reloc == BFD_RELOC_MIPS16_HI16_S;
2218}
2219
2220static inline bfd_boolean
2221lo16_reloc_p (bfd_reloc_code_real_type reloc)
2222{
2223 return reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_MIPS16_LO16;
2224}
2225
2226/* Return true if the given relocation might need a matching %lo().
2227 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2228 need a matching %lo() when applied to local symbols. */
2229
2230static inline bfd_boolean
2231reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2232{
2233 return (HAVE_IN_PLACE_ADDENDS
2234 && (hi16_reloc_p (reloc)
2235 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2236 all GOT16 relocations evaluate to "G". */
2237 || (got16_reloc_p (reloc) && mips_pic != VXWORKS_PIC)));
2238}
2239
2240/* Return the type of %lo() reloc needed by RELOC, given that
2241 reloc_needs_lo_p. */
2242
2243static inline bfd_reloc_code_real_type
2244matching_lo_reloc (bfd_reloc_code_real_type reloc)
2245{
2246 return mips16_reloc_p (reloc) ? BFD_RELOC_MIPS16_LO16 : BFD_RELOC_LO16;
2247}
2248
2249/* Return true if the given fixup is followed by a matching R_MIPS_LO16
2250 relocation. */
2251
2252static inline bfd_boolean
2253fixup_has_matching_lo_p (fixS *fixp)
2254{
2255 return (fixp->fx_next != NULL
2256 && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type)
2257 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2258 && fixp->fx_offset == fixp->fx_next->fx_offset);
2259}
2260
2261/* This function returns true if modifying a register requires a
2262 delay. */
2263
2264static int
2265reg_needs_delay (unsigned int reg)
2266{
2267 unsigned long prev_pinfo;
2268
2269 prev_pinfo = history[0].insn_mo->pinfo;
2270 if (! mips_opts.noreorder
2271 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2272 && ! gpr_interlocks)
2273 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
2274 && ! cop_interlocks)))
2275 {
2276 /* A load from a coprocessor or from memory. All load delays
2277 delay the use of general register rt for one instruction. */
2278 /* Itbl support may require additional care here. */
2279 know (prev_pinfo & INSN_WRITE_GPR_T);
2280 if (reg == EXTRACT_OPERAND (RT, history[0]))
2281 return 1;
2282 }
2283
2284 return 0;
2285}
2286
2287/* Move all labels in insn_labels to the current insertion point. */
2288
2289static void
2290mips_move_labels (void)
2291{
2292 segment_info_type *si = seg_info (now_seg);
2293 struct insn_label_list *l;
2294 valueT val;
2295
2296 for (l = si->label_list; l != NULL; l = l->next)
2297 {
2298 gas_assert (S_GET_SEGMENT (l->label) == now_seg);
2299 symbol_set_frag (l->label, frag_now);
2300 val = (valueT) frag_now_fix ();
2301 /* mips16 text labels are stored as odd. */
2302 if (mips_opts.mips16)
2303 ++val;
2304 S_SET_VALUE (l->label, val);
2305 }
2306}
2307
2308static bfd_boolean
2309s_is_linkonce (symbolS *sym, segT from_seg)
2310{
2311 bfd_boolean linkonce = FALSE;
2312 segT symseg = S_GET_SEGMENT (sym);
2313
2314 if (symseg != from_seg && !S_IS_LOCAL (sym))
2315 {
2316 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2317 linkonce = TRUE;
2318#ifdef OBJ_ELF
2319 /* The GNU toolchain uses an extension for ELF: a section
2320 beginning with the magic string .gnu.linkonce is a
2321 linkonce section. */
2322 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2323 sizeof ".gnu.linkonce" - 1) == 0)
2324 linkonce = TRUE;
2325#endif
2326 }
2327 return linkonce;
2328}
2329
2330/* Mark instruction labels in mips16 mode. This permits the linker to
2331 handle them specially, such as generating jalx instructions when
2332 needed. We also make them odd for the duration of the assembly, in
2333 order to generate the right sort of code. We will make them even
2334 in the adjust_symtab routine, while leaving them marked. This is
2335 convenient for the debugger and the disassembler. The linker knows
2336 to make them odd again. */
2337
2338static void
2339mips16_mark_labels (void)
2340{
2341 segment_info_type *si = seg_info (now_seg);
2342 struct insn_label_list *l;
2343
2344 if (!mips_opts.mips16)
2345 return;
2346
2347 for (l = si->label_list; l != NULL; l = l->next)
2348 {
2349 symbolS *label = l->label;
2350
2351#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2352 if (IS_ELF)
2353 S_SET_OTHER (label, ELF_ST_SET_MIPS16 (S_GET_OTHER (label)));
2354#endif
2355 if ((S_GET_VALUE (label) & 1) == 0
2356 /* Don't adjust the address if the label is global or weak, or
2357 in a link-once section, since we'll be emitting symbol reloc
2358 references to it which will be patched up by the linker, and
2359 the final value of the symbol may or may not be MIPS16. */
2360 && ! S_IS_WEAK (label)
2361 && ! S_IS_EXTERNAL (label)
2362 && ! s_is_linkonce (label, now_seg))
2363 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
2364 }
2365}
2366
2367/* End the current frag. Make it a variant frag and record the
2368 relaxation info. */
2369
2370static void
2371relax_close_frag (void)
2372{
2373 mips_macro_warning.first_frag = frag_now;
2374 frag_var (rs_machine_dependent, 0, 0,
2375 RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
2376 mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
2377
2378 memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
2379 mips_relax.first_fixup = 0;
2380}
2381
2382/* Start a new relaxation sequence whose expansion depends on SYMBOL.
2383 See the comment above RELAX_ENCODE for more details. */
2384
2385static void
2386relax_start (symbolS *symbol)
2387{
2388 gas_assert (mips_relax.sequence == 0);
2389 mips_relax.sequence = 1;
2390 mips_relax.symbol = symbol;
2391}
2392
2393/* Start generating the second version of a relaxable sequence.
2394 See the comment above RELAX_ENCODE for more details. */
2395
2396static void
2397relax_switch (void)
2398{
2399 gas_assert (mips_relax.sequence == 1);
2400 mips_relax.sequence = 2;
2401}
2402
2403/* End the current relaxable sequence. */
2404
2405static void
2406relax_end (void)
2407{
2408 gas_assert (mips_relax.sequence == 2);
2409 relax_close_frag ();
2410 mips_relax.sequence = 0;
2411}
2412
2413/* Return the mask of core registers that IP reads. */
2414
2415static unsigned int
2416gpr_read_mask (const struct mips_cl_insn *ip)
2417{
2418 unsigned long pinfo, pinfo2;
2419 unsigned int mask;
2420
2421 mask = 0;
2422 pinfo = ip->insn_mo->pinfo;
2423 pinfo2 = ip->insn_mo->pinfo2;
2424 if (mips_opts.mips16)
2425 {
2426 if (pinfo & MIPS16_INSN_READ_X)
2427 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2428 if (pinfo & MIPS16_INSN_READ_Y)
2429 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2430 if (pinfo & MIPS16_INSN_READ_T)
2431 mask |= 1 << TREG;
2432 if (pinfo & MIPS16_INSN_READ_SP)
2433 mask |= 1 << SP;
2434 if (pinfo & MIPS16_INSN_READ_31)
2435 mask |= 1 << RA;
2436 if (pinfo & MIPS16_INSN_READ_Z)
2437 mask |= 1 << (mips16_to_32_reg_map
2438 [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
2439 if (pinfo & MIPS16_INSN_READ_GPR_X)
2440 mask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2441 }
2442 else
2443 {
2444 if (pinfo2 & INSN2_READ_GPR_D)
2445 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2446 if (pinfo & INSN_READ_GPR_T)
2447 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2448 if (pinfo & INSN_READ_GPR_S)
2449 mask |= 1 << EXTRACT_OPERAND (RS, *ip);
2450 if (pinfo2 & INSN2_READ_GPR_Z)
2451 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2452 }
2453 /* Don't include register 0. */
2454 return mask & ~1;
2455}
2456
2457/* Return the mask of core registers that IP writes. */
2458
2459static unsigned int
2460gpr_write_mask (const struct mips_cl_insn *ip)
2461{
2462 unsigned long pinfo, pinfo2;
2463 unsigned int mask;
2464
2465 mask = 0;
2466 pinfo = ip->insn_mo->pinfo;
2467 pinfo2 = ip->insn_mo->pinfo2;
2468 if (mips_opts.mips16)
2469 {
2470 if (pinfo & MIPS16_INSN_WRITE_X)
2471 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)];
2472 if (pinfo & MIPS16_INSN_WRITE_Y)
2473 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)];
2474 if (pinfo & MIPS16_INSN_WRITE_Z)
2475 mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
2476 if (pinfo & MIPS16_INSN_WRITE_T)
2477 mask |= 1 << TREG;
2478 if (pinfo & MIPS16_INSN_WRITE_SP)
2479 mask |= 1 << SP;
2480 if (pinfo & MIPS16_INSN_WRITE_31)
2481 mask |= 1 << RA;
2482 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2483 mask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2484 }
2485 else
2486 {
2487 if (pinfo & INSN_WRITE_GPR_D)
2488 mask |= 1 << EXTRACT_OPERAND (RD, *ip);
2489 if (pinfo & INSN_WRITE_GPR_T)
2490 mask |= 1 << EXTRACT_OPERAND (RT, *ip);
2491 if (pinfo & INSN_WRITE_GPR_31)
2492 mask |= 1 << RA;
2493 if (pinfo2 & INSN2_WRITE_GPR_Z)
2494 mask |= 1 << EXTRACT_OPERAND (RZ, *ip);
2495 }
2496 /* Don't include register 0. */
2497 return mask & ~1;
2498}
2499
2500/* Return the mask of floating-point registers that IP reads. */
2501
2502static unsigned int
2503fpr_read_mask (const struct mips_cl_insn *ip)
2504{
2505 unsigned long pinfo, pinfo2;
2506 unsigned int mask;
2507
2508 mask = 0;
2509 pinfo = ip->insn_mo->pinfo;
2510 pinfo2 = ip->insn_mo->pinfo2;
2511 if (!mips_opts.mips16)
2512 {
2513 if (pinfo & INSN_READ_FPR_S)
2514 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2515 if (pinfo & INSN_READ_FPR_T)
2516 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2517 if (pinfo & INSN_READ_FPR_R)
2518 mask |= 1 << EXTRACT_OPERAND (FR, *ip);
2519 if (pinfo2 & INSN2_READ_FPR_Z)
2520 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2521 }
2522 /* Conservatively treat all operands to an FP_D instruction are doubles.
2523 (This is overly pessimistic for things like cvt.d.s.) */
2524 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2525 mask |= mask << 1;
2526 return mask;
2527}
2528
2529/* Return the mask of floating-point registers that IP writes. */
2530
2531static unsigned int
2532fpr_write_mask (const struct mips_cl_insn *ip)
2533{
2534 unsigned long pinfo, pinfo2;
2535 unsigned int mask;
2536
2537 mask = 0;
2538 pinfo = ip->insn_mo->pinfo;
2539 pinfo2 = ip->insn_mo->pinfo2;
2540 if (!mips_opts.mips16)
2541 {
2542 if (pinfo & INSN_WRITE_FPR_D)
2543 mask |= 1 << EXTRACT_OPERAND (FD, *ip);
2544 if (pinfo & INSN_WRITE_FPR_S)
2545 mask |= 1 << EXTRACT_OPERAND (FS, *ip);
2546 if (pinfo & INSN_WRITE_FPR_T)
2547 mask |= 1 << EXTRACT_OPERAND (FT, *ip);
2548 if (pinfo2 & INSN2_WRITE_FPR_Z)
2549 mask |= 1 << EXTRACT_OPERAND (FZ, *ip);
2550 }
2551 /* Conservatively treat all operands to an FP_D instruction are doubles.
2552 (This is overly pessimistic for things like cvt.s.d.) */
2553 if (HAVE_32BIT_FPRS && (pinfo & FP_D))
2554 mask |= mask << 1;
2555 return mask;
2556}
2557
2558/* Classify an instruction according to the FIX_VR4120_* enumeration.
2559 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2560 by VR4120 errata. */
2561
2562static unsigned int
2563classify_vr4120_insn (const char *name)
2564{
2565 if (strncmp (name, "macc", 4) == 0)
2566 return FIX_VR4120_MACC;
2567 if (strncmp (name, "dmacc", 5) == 0)
2568 return FIX_VR4120_DMACC;
2569 if (strncmp (name, "mult", 4) == 0)
2570 return FIX_VR4120_MULT;
2571 if (strncmp (name, "dmult", 5) == 0)
2572 return FIX_VR4120_DMULT;
2573 if (strstr (name, "div"))
2574 return FIX_VR4120_DIV;
2575 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
2576 return FIX_VR4120_MTHILO;
2577 return NUM_FIX_VR4120_CLASSES;
2578}
2579
2580#define INSN_ERET 0x42000018
2581#define INSN_DERET 0x4200001f
2582
2583/* Return the number of instructions that must separate INSN1 and INSN2,
2584 where INSN1 is the earlier instruction. Return the worst-case value
2585 for any INSN2 if INSN2 is null. */
2586
2587static unsigned int
2588insns_between (const struct mips_cl_insn *insn1,
2589 const struct mips_cl_insn *insn2)
2590{
2591 unsigned long pinfo1, pinfo2;
2592 unsigned int mask;
2593
2594 /* This function needs to know which pinfo flags are set for INSN2
2595 and which registers INSN2 uses. The former is stored in PINFO2 and
2596 the latter is tested via INSN2_USES_GPR. If INSN2 is null, PINFO2
2597 will have every flag set and INSN2_USES_GPR will always return true. */
2598 pinfo1 = insn1->insn_mo->pinfo;
2599 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
2600
2601#define INSN2_USES_GPR(REG) \
2602 (insn2 == NULL || (gpr_read_mask (insn2) & (1U << (REG))) != 0)
2603
2604 /* For most targets, write-after-read dependencies on the HI and LO
2605 registers must be separated by at least two instructions. */
2606 if (!hilo_interlocks)
2607 {
2608 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
2609 return 2;
2610 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
2611 return 2;
2612 }
2613
2614 /* If we're working around r7000 errata, there must be two instructions
2615 between an mfhi or mflo and any instruction that uses the result. */
2616 if (mips_7000_hilo_fix
2617 && MF_HILO_INSN (pinfo1)
2618 && INSN2_USES_GPR (EXTRACT_OPERAND (RD, *insn1)))
2619 return 2;
2620
2621 /* If we're working around 24K errata, one instruction is required
2622 if an ERET or DERET is followed by a branch instruction. */
2623 if (mips_fix_24k)
2624 {
2625 if (insn1->insn_opcode == INSN_ERET
2626 || insn1->insn_opcode == INSN_DERET)
2627 {
2628 if (insn2 == NULL
2629 || insn2->insn_opcode == INSN_ERET
2630 || insn2->insn_opcode == INSN_DERET
2631 || (insn2->insn_mo->pinfo
2632 & (INSN_UNCOND_BRANCH_DELAY
2633 | INSN_COND_BRANCH_DELAY
2634 | INSN_COND_BRANCH_LIKELY)) != 0)
2635 return 1;
2636 }
2637 }
2638
2639 /* If working around VR4120 errata, check for combinations that need
2640 a single intervening instruction. */
2641 if (mips_fix_vr4120)
2642 {
2643 unsigned int class1, class2;
2644
2645 class1 = classify_vr4120_insn (insn1->insn_mo->name);
2646 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
2647 {
2648 if (insn2 == NULL)
2649 return 1;
2650 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2651 if (vr4120_conflicts[class1] & (1 << class2))
2652 return 1;
2653 }
2654 }
2655
2656 if (!mips_opts.mips16)
2657 {
2658 /* Check for GPR or coprocessor load delays. All such delays
2659 are on the RT register. */
2660 /* Itbl support may require additional care here. */
2661 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2662 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
2663 {
2664 know (pinfo1 & INSN_WRITE_GPR_T);
2665 if (INSN2_USES_GPR (EXTRACT_OPERAND (RT, *insn1)))
2666 return 1;
2667 }
2668
2669 /* Check for generic coprocessor hazards.
2670
2671 This case is not handled very well. There is no special
2672 knowledge of CP0 handling, and the coprocessors other than
2673 the floating point unit are not distinguished at all. */
2674 /* Itbl support may require additional care here. FIXME!
2675 Need to modify this to include knowledge about
2676 user specified delays! */
2677 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2678 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2679 {
2680 /* Handle cases where INSN1 writes to a known general coprocessor
2681 register. There must be a one instruction delay before INSN2
2682 if INSN2 reads that register, otherwise no delay is needed. */
2683 mask = fpr_write_mask (insn1);
2684 if (mask != 0)
2685 {
2686 if (!insn2 || (mask & fpr_read_mask (insn2)) != 0)
2687 return 1;
2688 }
2689 else
2690 {
2691 /* Read-after-write dependencies on the control registers
2692 require a two-instruction gap. */
2693 if ((pinfo1 & INSN_WRITE_COND_CODE)
2694 && (pinfo2 & INSN_READ_COND_CODE))
2695 return 2;
2696
2697 /* We don't know exactly what INSN1 does. If INSN2 is
2698 also a coprocessor instruction, assume there must be
2699 a one instruction gap. */
2700 if (pinfo2 & INSN_COP)
2701 return 1;
2702 }
2703 }
2704
2705 /* Check for read-after-write dependencies on the coprocessor
2706 control registers in cases where INSN1 does not need a general
2707 coprocessor delay. This means that INSN1 is a floating point
2708 comparison instruction. */
2709 /* Itbl support may require additional care here. */
2710 else if (!cop_interlocks
2711 && (pinfo1 & INSN_WRITE_COND_CODE)
2712 && (pinfo2 & INSN_READ_COND_CODE))
2713 return 1;
2714 }
2715
2716#undef INSN2_USES_GPR
2717
2718 return 0;
2719}
2720
2721/* Return the number of nops that would be needed to work around the
2722 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2723 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
2724 that are contained within the first IGNORE instructions of HIST. */
2725
2726static int
2727nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist,
2728 const struct mips_cl_insn *insn)
2729{
2730 int i, j;
2731 unsigned int mask;
2732
2733 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2734 are not affected by the errata. */
2735 if (insn != 0
2736 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2737 || strcmp (insn->insn_mo->name, "mtlo") == 0
2738 || strcmp (insn->insn_mo->name, "mthi") == 0))
2739 return 0;
2740
2741 /* Search for the first MFLO or MFHI. */
2742 for (i = 0; i < MAX_VR4130_NOPS; i++)
2743 if (MF_HILO_INSN (hist[i].insn_mo->pinfo))
2744 {
2745 /* Extract the destination register. */
2746 mask = gpr_write_mask (&hist[i]);
2747
2748 /* No nops are needed if INSN reads that register. */
2749 if (insn != NULL && (gpr_read_mask (insn) & mask) != 0)
2750 return 0;
2751
2752 /* ...or if any of the intervening instructions do. */
2753 for (j = 0; j < i; j++)
2754 if (gpr_read_mask (&hist[j]) & mask)
2755 return 0;
2756
2757 if (i >= ignore)
2758 return MAX_VR4130_NOPS - i;
2759 }
2760 return 0;
2761}
2762
2763#define BASE_REG_EQ(INSN1, INSN2) \
2764 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
2765 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
2766
2767/* Return the minimum alignment for this store instruction. */
2768
2769static int
2770fix_24k_align_to (const struct mips_opcode *mo)
2771{
2772 if (strcmp (mo->name, "sh") == 0)
2773 return 2;
2774
2775 if (strcmp (mo->name, "swc1") == 0
2776 || strcmp (mo->name, "swc2") == 0
2777 || strcmp (mo->name, "sw") == 0
2778 || strcmp (mo->name, "sc") == 0
2779 || strcmp (mo->name, "s.s") == 0)
2780 return 4;
2781
2782 if (strcmp (mo->name, "sdc1") == 0
2783 || strcmp (mo->name, "sdc2") == 0
2784 || strcmp (mo->name, "s.d") == 0)
2785 return 8;
2786
2787 /* sb, swl, swr */
2788 return 1;
2789}
2790
2791struct fix_24k_store_info
2792 {
2793 /* Immediate offset, if any, for this store instruction. */
2794 short off;
2795 /* Alignment required by this store instruction. */
2796 int align_to;
2797 /* True for register offsets. */
2798 int register_offset;
2799 };
2800
2801/* Comparison function used by qsort. */
2802
2803static int
2804fix_24k_sort (const void *a, const void *b)
2805{
2806 const struct fix_24k_store_info *pos1 = a;
2807 const struct fix_24k_store_info *pos2 = b;
2808
2809 return (pos1->off - pos2->off);
2810}
2811
2812/* INSN is a store instruction. Try to record the store information
2813 in STINFO. Return false if the information isn't known. */
2814
2815static bfd_boolean
2816fix_24k_record_store_info (struct fix_24k_store_info *stinfo,
2817 const struct mips_cl_insn *insn)
2818{
2819 /* The instruction must have a known offset. */
2820 if (!insn->complete_p || !strstr (insn->insn_mo->args, "o("))
2821 return FALSE;
2822
2823 stinfo->off = (insn->insn_opcode >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE;
2824 stinfo->align_to = fix_24k_align_to (insn->insn_mo);
2825 return TRUE;
2826}
2827
2828/* Return the number of nops that would be needed to work around the 24k
2829 "lost data on stores during refill" errata if instruction INSN
2830 immediately followed the 2 instructions described by HIST.
2831 Ignore hazards that are contained within the first IGNORE
2832 instructions of HIST.
2833
2834 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
2835 for the data cache refills and store data. The following describes
2836 the scenario where the store data could be lost.
2837
2838 * A data cache miss, due to either a load or a store, causing fill
2839 data to be supplied by the memory subsystem
2840 * The first three doublewords of fill data are returned and written
2841 into the cache
2842 * A sequence of four stores occurs in consecutive cycles around the
2843 final doubleword of the fill:
2844 * Store A
2845 * Store B
2846 * Store C
2847 * Zero, One or more instructions
2848 * Store D
2849
2850 The four stores A-D must be to different doublewords of the line that
2851 is being filled. The fourth instruction in the sequence above permits
2852 the fill of the final doubleword to be transferred from the FSB into
2853 the cache. In the sequence above, the stores may be either integer
2854 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
2855 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
2856 different doublewords on the line. If the floating point unit is
2857 running in 1:2 mode, it is not possible to create the sequence above
2858 using only floating point store instructions.
2859
2860 In this case, the cache line being filled is incorrectly marked
2861 invalid, thereby losing the data from any store to the line that
2862 occurs between the original miss and the completion of the five
2863 cycle sequence shown above.
2864
2865 The workarounds are:
2866
2867 * Run the data cache in write-through mode.
2868 * Insert a non-store instruction between
2869 Store A and Store B or Store B and Store C. */
2870
2871static int
2872nops_for_24k (int ignore, const struct mips_cl_insn *hist,
2873 const struct mips_cl_insn *insn)
2874{
2875 struct fix_24k_store_info pos[3];
2876 int align, i, base_offset;
2877
2878 if (ignore >= 2)
2879 return 0;
2880
2881 /* If the previous instruction wasn't a store, there's nothing to
2882 worry about. */
2883 if ((hist[0].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2884 return 0;
2885
2886 /* If the instructions after the previous one are unknown, we have
2887 to assume the worst. */
2888 if (!insn)
2889 return 1;
2890
2891 /* Check whether we are dealing with three consecutive stores. */
2892 if ((insn->insn_mo->pinfo & INSN_STORE_MEMORY) == 0
2893 || (hist[1].insn_mo->pinfo & INSN_STORE_MEMORY) == 0)
2894 return 0;
2895
2896 /* If we don't know the relationship between the store addresses,
2897 assume the worst. */
2898 if (!BASE_REG_EQ (insn->insn_opcode, hist[0].insn_opcode)
2899 || !BASE_REG_EQ (insn->insn_opcode, hist[1].insn_opcode))
2900 return 1;
2901
2902 if (!fix_24k_record_store_info (&pos[0], insn)
2903 || !fix_24k_record_store_info (&pos[1], &hist[0])
2904 || !fix_24k_record_store_info (&pos[2], &hist[1]))
2905 return 1;
2906
2907 qsort (&pos, 3, sizeof (struct fix_24k_store_info), fix_24k_sort);
2908
2909 /* Pick a value of ALIGN and X such that all offsets are adjusted by
2910 X bytes and such that the base register + X is known to be aligned
2911 to align bytes. */
2912
2913 if (((insn->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == SP)
2914 align = 8;
2915 else
2916 {
2917 align = pos[0].align_to;
2918 base_offset = pos[0].off;
2919 for (i = 1; i < 3; i++)
2920 if (align < pos[i].align_to)
2921 {
2922 align = pos[i].align_to;
2923 base_offset = pos[i].off;
2924 }
2925 for (i = 0; i < 3; i++)
2926 pos[i].off -= base_offset;
2927 }
2928
2929 pos[0].off &= ~align + 1;
2930 pos[1].off &= ~align + 1;
2931 pos[2].off &= ~align + 1;
2932
2933 /* If any two stores write to the same chunk, they also write to the
2934 same doubleword. The offsets are still sorted at this point. */
2935 if (pos[0].off == pos[1].off || pos[1].off == pos[2].off)
2936 return 0;
2937
2938 /* A range of at least 9 bytes is needed for the stores to be in
2939 non-overlapping doublewords. */
2940 if (pos[2].off - pos[0].off <= 8)
2941 return 0;
2942
2943 if (pos[2].off - pos[1].off >= 24
2944 || pos[1].off - pos[0].off >= 24
2945 || pos[2].off - pos[0].off >= 32)
2946 return 0;
2947
2948 return 1;
2949}
2950
2951/* Return the number of nops that would be needed if instruction INSN
2952 immediately followed the MAX_NOPS instructions given by HIST,
2953 where HIST[0] is the most recent instruction. Ignore hazards
2954 between INSN and the first IGNORE instructions in HIST.
2955
2956 If INSN is null, return the worse-case number of nops for any
2957 instruction. */
2958
2959static int
2960nops_for_insn (int ignore, const struct mips_cl_insn *hist,
2961 const struct mips_cl_insn *insn)
2962{
2963 int i, nops, tmp_nops;
2964
2965 nops = 0;
2966 for (i = ignore; i < MAX_DELAY_NOPS; i++)
2967 {
2968 tmp_nops = insns_between (hist + i, insn) - i;
2969 if (tmp_nops > nops)
2970 nops = tmp_nops;
2971 }
2972
2973 if (mips_fix_vr4130)
2974 {
2975 tmp_nops = nops_for_vr4130 (ignore, hist, insn);
2976 if (tmp_nops > nops)
2977 nops = tmp_nops;
2978 }
2979
2980 if (mips_fix_24k)
2981 {
2982 tmp_nops = nops_for_24k (ignore, hist, insn);
2983 if (tmp_nops > nops)
2984 nops = tmp_nops;
2985 }
2986
2987 return nops;
2988}
2989
2990/* The variable arguments provide NUM_INSNS extra instructions that
2991 might be added to HIST. Return the largest number of nops that
2992 would be needed after the extended sequence, ignoring hazards
2993 in the first IGNORE instructions. */
2994
2995static int
2996nops_for_sequence (int num_insns, int ignore,
2997 const struct mips_cl_insn *hist, ...)
2998{
2999 va_list args;
3000 struct mips_cl_insn buffer[MAX_NOPS];
3001 struct mips_cl_insn *cursor;
3002 int nops;
3003
3004 va_start (args, hist);
3005 cursor = buffer + num_insns;
3006 memcpy (cursor, hist, (MAX_NOPS - num_insns) * sizeof (*cursor));
3007 while (cursor > buffer)
3008 *--cursor = *va_arg (args, const struct mips_cl_insn *);
3009
3010 nops = nops_for_insn (ignore, buffer, NULL);
3011 va_end (args);
3012 return nops;
3013}
3014
3015/* Like nops_for_insn, but if INSN is a branch, take into account the
3016 worst-case delay for the branch target. */
3017
3018static int
3019nops_for_insn_or_target (int ignore, const struct mips_cl_insn *hist,
3020 const struct mips_cl_insn *insn)
3021{
3022 int nops, tmp_nops;
3023
3024 nops = nops_for_insn (ignore, hist, insn);
3025 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
3026 | INSN_COND_BRANCH_DELAY
3027 | INSN_COND_BRANCH_LIKELY))
3028 {
3029 tmp_nops = nops_for_sequence (2, ignore ? ignore + 2 : 0,
3030 hist, insn, NOP_INSN);
3031 if (tmp_nops > nops)
3032 nops = tmp_nops;
3033 }
3034 else if (mips_opts.mips16
3035 && (insn->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
3036 | MIPS16_INSN_COND_BRANCH)))
3037 {
3038 tmp_nops = nops_for_sequence (1, ignore ? ignore + 1 : 0, hist, insn);
3039 if (tmp_nops > nops)
3040 nops = tmp_nops;
3041 }
3042 return nops;
3043}
3044
3045/* Fix NOP issue: Replace nops by "or at,at,zero". */
3046
3047static void
3048fix_loongson2f_nop (struct mips_cl_insn * ip)
3049{
3050 if (strcmp (ip->insn_mo->name, "nop") == 0)
3051 ip->insn_opcode = LOONGSON2F_NOP_INSN;
3052}
3053
3054/* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
3055 jr target pc &= 'hffff_ffff_cfff_ffff. */
3056
3057static void
3058fix_loongson2f_jump (struct mips_cl_insn * ip)
3059{
3060 if (strcmp (ip->insn_mo->name, "j") == 0
3061 || strcmp (ip->insn_mo->name, "jr") == 0
3062 || strcmp (ip->insn_mo->name, "jalr") == 0)
3063 {
3064 int sreg;
3065 expressionS ep;
3066
3067 if (! mips_opts.at)
3068 return;
3069
3070 sreg = EXTRACT_OPERAND (RS, *ip);
3071 if (sreg == ZERO || sreg == KT0 || sreg == KT1 || sreg == ATREG)
3072 return;
3073
3074 ep.X_op = O_constant;
3075 ep.X_add_number = 0xcfff0000;
3076 macro_build (&ep, "lui", "t,u", ATREG, BFD_RELOC_HI16);
3077 ep.X_add_number = 0xffff;
3078 macro_build (&ep, "ori", "t,r,i", ATREG, ATREG, BFD_RELOC_LO16);
3079 macro_build (NULL, "and", "d,v,t", sreg, sreg, ATREG);
3080 }
3081}
3082
3083static void
3084fix_loongson2f (struct mips_cl_insn * ip)
3085{
3086 if (mips_fix_loongson2f_nop)
3087 fix_loongson2f_nop (ip);
3088
3089 if (mips_fix_loongson2f_jump)
3090 fix_loongson2f_jump (ip);
3091}
3092
3093/* IP is a branch that has a delay slot, and we need to fill it
3094 automatically. Return true if we can do that by swapping IP
3095 with the previous instruction. */
3096
3097static bfd_boolean
3098can_swap_branch_p (struct mips_cl_insn *ip)
3099{
3100 unsigned long pinfo, prev_pinfo;
3101 unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
3102
3103 /* -O2 and above is required for this optimization. */
3104 if (mips_optimize < 2)
3105 return FALSE;
3106
3107 /* If we have seen .set volatile or .set nomove, don't optimize. */
3108 if (mips_opts.nomove)
3109 return FALSE;
3110
3111 /* We can't swap if the previous instruction's position is fixed. */
3112 if (history[0].fixed_p)
3113 return FALSE;
3114
3115 /* If the previous previous insn was in a .set noreorder, we can't
3116 swap. Actually, the MIPS assembler will swap in this situation.
3117 However, gcc configured -with-gnu-as will generate code like
3118
3119 .set noreorder
3120 lw $4,XXX
3121 .set reorder
3122 INSN
3123 bne $4,$0,foo
3124
3125 in which we can not swap the bne and INSN. If gcc is not configured
3126 -with-gnu-as, it does not output the .set pseudo-ops. */
3127 if (history[1].noreorder_p)
3128 return FALSE;
3129
3130 /* If the previous instruction had a fixup in mips16 mode, we can not
3131 swap. This normally means that the previous instruction was a 4
3132 byte branch anyhow. */
3133 if (mips_opts.mips16 && history[0].fixp[0])
3134 return FALSE;
3135
3136 /* If the branch is itself the target of a branch, we can not swap.
3137 We cheat on this; all we check for is whether there is a label on
3138 this instruction. If there are any branches to anything other than
3139 a label, users must use .set noreorder. */
3140 if (seg_info (now_seg)->label_list)
3141 return FALSE;
3142
3143 /* If the previous instruction is in a variant frag other than this
3144 branch's one, we cannot do the swap. This does not apply to the
3145 mips16, which uses variant frags for different purposes. */
3146 if (!mips_opts.mips16
3147 && history[0].frag
3148 && history[0].frag->fr_type == rs_machine_dependent)
3149 return FALSE;
3150
3151 /* We do not swap with a trap instruction, since it complicates trap
3152 handlers to have the trap instruction be in a delay slot. */
3153 prev_pinfo = history[0].insn_mo->pinfo;
3154 if (prev_pinfo & INSN_TRAP)
3155 return FALSE;
3156
3157 /* If the previous instruction is a sync, sync.l, or sync.p, we can
3158 not swap. */
3159 if (prev_pinfo & INSN_SYNC)
3160 return FALSE;
3161
3162 /* If the previous instruction is an ERET or DERET, avoid the swap. */
3163 if (history[0].insn_opcode == INSN_ERET)
3164 return FALSE;
3165 if (history[0].insn_opcode == INSN_DERET)
3166 return FALSE;
3167
3168 /* Check for conflicts between the branch and the instructions
3169 before the candidate delay slot. */
3170 if (nops_for_insn (0, history + 1, ip) > 0)
3171 return FALSE;
3172
3173 /* Check for conflicts between the swapped sequence and the
3174 target of the branch. */
3175 if (nops_for_sequence (2, 0, history + 1, ip, history) > 0)
3176 return FALSE;
3177
3178 /* If the branch reads a register that the previous
3179 instruction sets, we can not swap. */
3180 gpr_read = gpr_read_mask (ip);
3181 prev_gpr_write = gpr_write_mask (&history[0]);
3182 if (gpr_read & prev_gpr_write)
3183 return FALSE;
3184
3185 /* If the branch writes a register that the previous
3186 instruction sets, we can not swap. */
3187 gpr_write = gpr_write_mask (ip);
3188 if (gpr_write & prev_gpr_write)
3189 return FALSE;
3190
3191 /* If the branch writes a register that the previous
3192 instruction reads, we can not swap. */
3193 prev_gpr_read = gpr_read_mask (&history[0]);
3194 if (gpr_write & prev_gpr_read)
3195 return FALSE;
3196
3197 /* If one instruction sets a condition code and the
3198 other one uses a condition code, we can not swap. */
3199 pinfo = ip->insn_mo->pinfo;
3200 if ((pinfo & INSN_READ_COND_CODE)
3201 && (prev_pinfo & INSN_WRITE_COND_CODE))
3202 return FALSE;
3203 if ((pinfo & INSN_WRITE_COND_CODE)
3204 && (prev_pinfo & INSN_READ_COND_CODE))
3205 return FALSE;
3206
3207 /* If the previous instruction uses the PC, we can not swap. */
3208 if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
3209 return FALSE;
3210
3211 return TRUE;
3212}
3213
3214/* Decide how we should add IP to the instruction stream. */
3215
3216static enum append_method
3217get_append_method (struct mips_cl_insn *ip)
3218{
3219 unsigned long pinfo;
3220
3221 /* The relaxed version of a macro sequence must be inherently
3222 hazard-free. */
3223 if (mips_relax.sequence == 2)
3224 return APPEND_ADD;
3225
3226 /* We must not dabble with instructions in a ".set norerorder" block. */
3227 if (mips_opts.noreorder)
3228 return APPEND_ADD;
3229
3230 /* Otherwise, it's our responsibility to fill branch delay slots. */
3231 pinfo = ip->insn_mo->pinfo;
3232 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
3233 || (pinfo & INSN_COND_BRANCH_DELAY))
3234 {
3235 if (can_swap_branch_p (ip))
3236 return APPEND_SWAP;
3237
3238 if (mips_opts.mips16
3239 && ISA_SUPPORTS_MIPS16E
3240 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3241 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
3242 return APPEND_ADD_COMPACT;
3243
3244 return APPEND_ADD_WITH_NOP;
3245 }
3246
3247 /* We don't bother trying to track the target of branches, so there's
3248 nothing we can use to fill a branch-likely slot. */
3249 if (pinfo & INSN_COND_BRANCH_LIKELY)
3250 return APPEND_ADD_WITH_NOP;
3251
3252 return APPEND_ADD;
3253}
3254
3255/* IP is a MIPS16 instruction whose opcode we have just changed.
3256 Point IP->insn_mo to the new opcode's definition. */
3257
3258static void
3259find_altered_mips16_opcode (struct mips_cl_insn *ip)
3260{
3261 const struct mips_opcode *mo, *end;
3262
3263 end = &mips16_opcodes[bfd_mips16_num_opcodes];
3264 for (mo = ip->insn_mo; mo < end; mo++)
3265 if ((ip->insn_opcode & mo->mask) == mo->match)
3266 {
3267 ip->insn_mo = mo;
3268 return;
3269 }
3270 abort ();
3271}
3272
3273/* Output an instruction. IP is the instruction information.
3274 ADDRESS_EXPR is an operand of the instruction to be used with
3275 RELOC_TYPE. */
3276
3277static void
3278append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
3279 bfd_reloc_code_real_type *reloc_type)
3280{
3281 unsigned long prev_pinfo, pinfo;
3282 unsigned long prev_pinfo2, pinfo2;
3283 bfd_boolean relaxed_branch = FALSE;
3284 enum append_method method;
3285
3286 if (mips_fix_loongson2f)
3287 fix_loongson2f (ip);
3288
3289 /* Mark instruction labels in mips16 mode. */
3290 mips16_mark_labels ();
3291
3292 file_ase_mips16 |= mips_opts.mips16;
3293
3294 prev_pinfo = history[0].insn_mo->pinfo;
3295 prev_pinfo2 = history[0].insn_mo->pinfo2;
3296 pinfo = ip->insn_mo->pinfo;
3297 pinfo2 = ip->insn_mo->pinfo2;
3298
3299 if (address_expr == NULL)
3300 ip->complete_p = 1;
3301 else if (*reloc_type <= BFD_RELOC_UNUSED
3302 && address_expr->X_op == O_constant)
3303 {
3304 unsigned int tmp;
3305
3306 ip->complete_p = 1;
3307 switch (*reloc_type)
3308 {
3309 case BFD_RELOC_32:
3310 ip->insn_opcode |= address_expr->X_add_number;
3311 break;
3312
3313 case BFD_RELOC_MIPS_HIGHEST:
3314 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
3315 ip->insn_opcode |= tmp & 0xffff;
3316 break;
3317
3318 case BFD_RELOC_MIPS_HIGHER:
3319 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
3320 ip->insn_opcode |= tmp & 0xffff;
3321 break;
3322
3323 case BFD_RELOC_HI16_S:
3324 tmp = (address_expr->X_add_number + 0x8000) >> 16;
3325 ip->insn_opcode |= tmp & 0xffff;
3326 break;
3327
3328 case BFD_RELOC_HI16:
3329 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
3330 break;
3331
3332 case BFD_RELOC_UNUSED:
3333 case BFD_RELOC_LO16:
3334 case BFD_RELOC_MIPS_GOT_DISP:
3335 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
3336 break;
3337
3338 case BFD_RELOC_MIPS_JMP:
3339 if ((address_expr->X_add_number & 3) != 0)
3340 as_bad (_("jump to misaligned address (0x%lx)"),
3341 (unsigned long) address_expr->X_add_number);
3342 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
3343 ip->complete_p = 0;
3344 break;
3345
3346 case BFD_RELOC_MIPS16_JMP:
3347 if ((address_expr->X_add_number & 3) != 0)
3348 as_bad (_("jump to misaligned address (0x%lx)"),
3349 (unsigned long) address_expr->X_add_number);
3350 ip->insn_opcode |=
3351 (((address_expr->X_add_number & 0x7c0000) << 3)
3352 | ((address_expr->X_add_number & 0xf800000) >> 7)
3353 | ((address_expr->X_add_number & 0x3fffc) >> 2));
3354 ip->complete_p = 0;
3355 break;
3356
3357 case BFD_RELOC_16_PCREL_S2:
3358 if ((address_expr->X_add_number & 3) != 0)
3359 as_bad (_("branch to misaligned address (0x%lx)"),
3360 (unsigned long) address_expr->X_add_number);
3361 if (!mips_relax_branch)
3362 {
3363 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
3364 as_bad (_("branch address range overflow (0x%lx)"),
3365 (unsigned long) address_expr->X_add_number);
3366 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
3367 }
3368 ip->complete_p = 0;
3369 break;
3370
3371 default:
3372 internalError ();
3373 }
3374 }
3375
3376 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
3377 {
3378 /* There are a lot of optimizations we could do that we don't.
3379 In particular, we do not, in general, reorder instructions.
3380 If you use gcc with optimization, it will reorder
3381 instructions and generally do much more optimization then we
3382 do here; repeating all that work in the assembler would only
3383 benefit hand written assembly code, and does not seem worth
3384 it. */
3385 int nops = (mips_optimize == 0
3386 ? nops_for_insn (0, history, NULL)
3387 : nops_for_insn_or_target (0, history, ip));
3388 if (nops > 0)
3389 {
3390 fragS *old_frag;
3391 unsigned long old_frag_offset;
3392 int i;
3393
3394 old_frag = frag_now;
3395 old_frag_offset = frag_now_fix ();
3396
3397 for (i = 0; i < nops; i++)
3398 emit_nop ();
3399
3400 if (listing)
3401 {
3402 listing_prev_line ();
3403 /* We may be at the start of a variant frag. In case we
3404 are, make sure there is enough space for the frag
3405 after the frags created by listing_prev_line. The
3406 argument to frag_grow here must be at least as large
3407 as the argument to all other calls to frag_grow in
3408 this file. We don't have to worry about being in the
3409 middle of a variant frag, because the variants insert
3410 all needed nop instructions themselves. */
3411 frag_grow (40);
3412 }
3413
3414 mips_move_labels ();
3415
3416#ifndef NO_ECOFF_DEBUGGING
3417 if (ECOFF_DEBUGGING)
3418 ecoff_fix_loc (old_frag, old_frag_offset);
3419#endif
3420 }
3421 }
3422 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
3423 {
3424 int nops;
3425
3426 /* Work out how many nops in prev_nop_frag are needed by IP,
3427 ignoring hazards generated by the first prev_nop_frag_since
3428 instructions. */
3429 nops = nops_for_insn_or_target (prev_nop_frag_since, history, ip);
3430 gas_assert (nops <= prev_nop_frag_holds);
3431
3432 /* Enforce NOPS as a minimum. */
3433 if (nops > prev_nop_frag_required)
3434 prev_nop_frag_required = nops;
3435
3436 if (prev_nop_frag_holds == prev_nop_frag_required)
3437 {
3438 /* Settle for the current number of nops. Update the history
3439 accordingly (for the benefit of any future .set reorder code). */
3440 prev_nop_frag = NULL;
3441 insert_into_history (prev_nop_frag_since,
3442 prev_nop_frag_holds, NOP_INSN);
3443 }
3444 else
3445 {
3446 /* Allow this instruction to replace one of the nops that was
3447 tentatively added to prev_nop_frag. */
3448 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
3449 prev_nop_frag_holds--;
3450 prev_nop_frag_since++;
3451 }
3452 }
3453
3454 method = get_append_method (ip);
3455
3456#ifdef OBJ_ELF
3457 /* The value passed to dwarf2_emit_insn is the distance between
3458 the beginning of the current instruction and the address that
3459 should be recorded in the debug tables. This is normally the
3460 current address.
3461
3462 For MIPS16 debug info we want to use ISA-encoded addresses,
3463 so we use -1 for an address higher by one than the current one.
3464
3465 If the instruction produced is a branch that we will swap with
3466 the preceding instruction, then we add the displacement by which
3467 the branch will be moved backwards. This is more appropriate
3468 and for MIPS16 code also prevents a debugger from placing a
3469 breakpoint in the middle of the branch (and corrupting code if
3470 software breakpoints are used). */
3471 dwarf2_emit_insn ((mips_opts.mips16 ? -1 : 0)
3472 + (method == APPEND_SWAP ? insn_length (history) : 0));
3473#endif
3474
3475 if (address_expr
3476 && *reloc_type == BFD_RELOC_16_PCREL_S2
3477 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
3478 || pinfo & INSN_COND_BRANCH_LIKELY)
3479 && mips_relax_branch
3480 /* Don't try branch relaxation within .set nomacro, or within
3481 .set noat if we use $at for PIC computations. If it turns
3482 out that the branch was out-of-range, we'll get an error. */
3483 && !mips_opts.warn_about_macros
3484 && (mips_opts.at || mips_pic == NO_PIC)
3485 /* Don't relax BPOSGE32/64 as they have no complementing branches. */
3486 && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP))
3487 && !mips_opts.mips16)
3488 {
3489 relaxed_branch = TRUE;
3490 add_relaxed_insn (ip, (relaxed_branch_length
3491 (NULL, NULL,
3492 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
3493 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
3494 : 0)), 4,
3495 RELAX_BRANCH_ENCODE
3496 (AT,
3497 pinfo & INSN_UNCOND_BRANCH_DELAY,
3498 pinfo & INSN_COND_BRANCH_LIKELY,
3499 pinfo & INSN_WRITE_GPR_31,
3500 0),
3501 address_expr->X_add_symbol,
3502 address_expr->X_add_number);
3503 *reloc_type = BFD_RELOC_UNUSED;
3504 }
3505 else if (*reloc_type > BFD_RELOC_UNUSED)
3506 {
3507 /* We need to set up a variant frag. */
3508 gas_assert (mips_opts.mips16 && address_expr != NULL);
3509 add_relaxed_insn (ip, 4, 0,
3510 RELAX_MIPS16_ENCODE
3511 (*reloc_type - BFD_RELOC_UNUSED,
3512 mips16_small, mips16_ext,
3513 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
3514 history[0].mips16_absolute_jump_p),
3515 make_expr_symbol (address_expr), 0);
3516 }
3517 else if (mips_opts.mips16
3518 && ! ip->use_extend
3519 && *reloc_type != BFD_RELOC_MIPS16_JMP)
3520 {
3521 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
3522 /* Make sure there is enough room to swap this instruction with
3523 a following jump instruction. */
3524 frag_grow (6);
3525 add_fixed_insn (ip);
3526 }
3527 else
3528 {
3529 if (mips_opts.mips16
3530 && mips_opts.noreorder
3531 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
3532 as_warn (_("extended instruction in delay slot"));
3533
3534 if (mips_relax.sequence)
3535 {
3536 /* If we've reached the end of this frag, turn it into a variant
3537 frag and record the information for the instructions we've
3538 written so far. */
3539 if (frag_room () < 4)
3540 relax_close_frag ();
3541 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3542 }
3543
3544 if (mips_relax.sequence != 2)
3545 mips_macro_warning.sizes[0] += 4;
3546 if (mips_relax.sequence != 1)
3547 mips_macro_warning.sizes[1] += 4;
3548
3549 if (mips_opts.mips16)
3550 {
3551 ip->fixed_p = 1;
3552 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
3553 }
3554 add_fixed_insn (ip);
3555 }
3556
3557 if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED)
3558 {
3559 reloc_howto_type *howto;
3560 int i;
3561
3562 /* In a compound relocation, it is the final (outermost)
3563 operator that determines the relocated field. */
3564 for (i = 1; i < 3; i++)
3565 if (reloc_type[i] == BFD_RELOC_UNUSED)
3566 break;
3567
3568 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
3569 if (howto == NULL)
3570 {
3571 /* To reproduce this failure try assembling gas/testsuites/
3572 gas/mips/mips16-intermix.s with a mips-ecoff targeted
3573 assembler. */
3574 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type[i - 1]);
3575 howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
3576 }
3577
3578 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
3579 bfd_get_reloc_size (howto),
3580 address_expr,
3581 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
3582 reloc_type[0]);
3583
3584 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
3585 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
3586 && ip->fixp[0]->fx_addsy)
3587 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
3588
3589 /* These relocations can have an addend that won't fit in
3590 4 octets for 64bit assembly. */
3591 if (HAVE_64BIT_GPRS
3592 && ! howto->partial_inplace
3593 && (reloc_type[0] == BFD_RELOC_16
3594 || reloc_type[0] == BFD_RELOC_32
3595 || reloc_type[0] == BFD_RELOC_MIPS_JMP
3596 || reloc_type[0] == BFD_RELOC_GPREL16
3597 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
3598 || reloc_type[0] == BFD_RELOC_GPREL32
3599 || reloc_type[0] == BFD_RELOC_64
3600 || reloc_type[0] == BFD_RELOC_CTOR
3601 || reloc_type[0] == BFD_RELOC_MIPS_SUB
3602 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
3603 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
3604 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
3605 || reloc_type[0] == BFD_RELOC_MIPS_REL16
3606 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
3607 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
3608 || hi16_reloc_p (reloc_type[0])
3609 || lo16_reloc_p (reloc_type[0])))
3610 ip->fixp[0]->fx_no_overflow = 1;
3611
3612 if (mips_relax.sequence)
3613 {
3614 if (mips_relax.first_fixup == 0)
3615 mips_relax.first_fixup = ip->fixp[0];
3616 }
3617 else if (reloc_needs_lo_p (*reloc_type))
3618 {
3619 struct mips_hi_fixup *hi_fixup;
3620
3621 /* Reuse the last entry if it already has a matching %lo. */
3622 hi_fixup = mips_hi_fixup_list;
3623 if (hi_fixup == 0
3624 || !fixup_has_matching_lo_p (hi_fixup->fixp))
3625 {
3626 hi_fixup = ((struct mips_hi_fixup *)
3627 xmalloc (sizeof (struct mips_hi_fixup)));
3628 hi_fixup->next = mips_hi_fixup_list;
3629 mips_hi_fixup_list = hi_fixup;
3630 }
3631 hi_fixup->fixp = ip->fixp[0];
3632 hi_fixup->seg = now_seg;
3633 }
3634
3635 /* Add fixups for the second and third relocations, if given.
3636 Note that the ABI allows the second relocation to be
3637 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3638 moment we only use RSS_UNDEF, but we could add support
3639 for the others if it ever becomes necessary. */
3640 for (i = 1; i < 3; i++)
3641 if (reloc_type[i] != BFD_RELOC_UNUSED)
3642 {
3643 ip->fixp[i] = fix_new (ip->frag, ip->where,
3644 ip->fixp[0]->fx_size, NULL, 0,
3645 FALSE, reloc_type[i]);
3646
3647 /* Use fx_tcbit to mark compound relocs. */
3648 ip->fixp[0]->fx_tcbit = 1;
3649 ip->fixp[i]->fx_tcbit = 1;
3650 }
3651 }
3652 install_insn (ip);
3653
3654 /* Update the register mask information. */
3655 mips_gprmask |= gpr_read_mask (ip) | gpr_write_mask (ip);
3656 mips_cprmask[1] |= fpr_read_mask (ip) | fpr_write_mask (ip);
3657
3658 switch (method)
3659 {
3660 case APPEND_ADD:
3661 insert_into_history (0, 1, ip);
3662 break;
3663
3664 case APPEND_ADD_WITH_NOP:
3665 insert_into_history (0, 1, ip);
3666 emit_nop ();
3667 if (mips_relax.sequence)
3668 mips_relax.sizes[mips_relax.sequence - 1] += 4;
3669 break;
3670
3671 case APPEND_ADD_COMPACT:
3672 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3673 gas_assert (mips_opts.mips16);
3674 ip->insn_opcode |= 0x0080;
3675 find_altered_mips16_opcode (ip);
3676 install_insn (ip);
3677 insert_into_history (0, 1, ip);
3678 break;
3679
3680 case APPEND_SWAP:
3681 {
3682 struct mips_cl_insn delay = history[0];
3683 if (mips_opts.mips16)
3684 {
3685 know (delay.frag == ip->frag);
3686 move_insn (ip, delay.frag, delay.where);
3687 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
3688 }
3689 else if (relaxed_branch)
3690 {
3691 /* Add the delay slot instruction to the end of the
3692 current frag and shrink the fixed part of the
3693 original frag. If the branch occupies the tail of
3694 the latter, move it backwards to cover the gap. */
3695 delay.frag->fr_fix -= 4;
3696 if (delay.frag == ip->frag)
3697 move_insn (ip, ip->frag, ip->where - 4);
3698 add_fixed_insn (&delay);
3699 }
3700 else
3701 {
3702 move_insn (&delay, ip->frag, ip->where);
3703 move_insn (ip, history[0].frag, history[0].where);
3704 }
3705 history[0] = *ip;
3706 delay.fixed_p = 1;
3707 insert_into_history (0, 1, &delay);
3708 }
3709 break;
3710 }
3711
3712 /* If we have just completed an unconditional branch, clear the history. */
3713 if ((history[1].insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY)
3714 || (mips_opts.mips16
3715 && (history[0].insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH)))
3716 mips_no_prev_insn ();
3717
3718 /* We just output an insn, so the next one doesn't have a label. */
3719 mips_clear_insn_labels ();
3720}
3721
3722/* Forget that there was any previous instruction or label. */
3723
3724static void
3725mips_no_prev_insn (void)
3726{
3727 prev_nop_frag = NULL;
3728 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
3729 mips_clear_insn_labels ();
3730}
3731
3732/* This function must be called before we emit something other than
3733 instructions. It is like mips_no_prev_insn except that it inserts
3734 any NOPS that might be needed by previous instructions. */
3735
3736void
3737mips_emit_delays (void)
3738{
3739 if (! mips_opts.noreorder)
3740 {
3741 int nops = nops_for_insn (0, history, NULL);
3742 if (nops > 0)
3743 {
3744 while (nops-- > 0)
3745 add_fixed_insn (NOP_INSN);
3746 mips_move_labels ();
3747 }
3748 }
3749 mips_no_prev_insn ();
3750}
3751
3752/* Start a (possibly nested) noreorder block. */
3753
3754static void
3755start_noreorder (void)
3756{
3757 if (mips_opts.noreorder == 0)
3758 {
3759 unsigned int i;
3760 int nops;
3761
3762 /* None of the instructions before the .set noreorder can be moved. */
3763 for (i = 0; i < ARRAY_SIZE (history); i++)
3764 history[i].fixed_p = 1;
3765
3766 /* Insert any nops that might be needed between the .set noreorder
3767 block and the previous instructions. We will later remove any
3768 nops that turn out not to be needed. */
3769 nops = nops_for_insn (0, history, NULL);
3770 if (nops > 0)
3771 {
3772 if (mips_optimize != 0)
3773 {
3774 /* Record the frag which holds the nop instructions, so
3775 that we can remove them if we don't need them. */
3776 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
3777 prev_nop_frag = frag_now;
3778 prev_nop_frag_holds = nops;
3779 prev_nop_frag_required = 0;
3780 prev_nop_frag_since = 0;
3781 }
3782
3783 for (; nops > 0; --nops)
3784 add_fixed_insn (NOP_INSN);
3785
3786 /* Move on to a new frag, so that it is safe to simply
3787 decrease the size of prev_nop_frag. */
3788 frag_wane (frag_now);
3789 frag_new (0);
3790 mips_move_labels ();
3791 }
3792 mips16_mark_labels ();
3793 mips_clear_insn_labels ();
3794 }
3795 mips_opts.noreorder++;
3796 mips_any_noreorder = 1;
3797}
3798
3799/* End a nested noreorder block. */
3800
3801static void
3802end_noreorder (void)
3803{
3804
3805 mips_opts.noreorder--;
3806 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
3807 {
3808 /* Commit to inserting prev_nop_frag_required nops and go back to
3809 handling nop insertion the .set reorder way. */
3810 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
3811 * (mips_opts.mips16 ? 2 : 4));
3812 insert_into_history (prev_nop_frag_since,
3813 prev_nop_frag_required, NOP_INSN);
3814 prev_nop_frag = NULL;
3815 }
3816}
3817
3818/* Set up global variables for the start of a new macro. */
3819
3820static void
3821macro_start (void)
3822{
3823 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
3824 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
3825 && (history[0].insn_mo->pinfo
3826 & (INSN_UNCOND_BRANCH_DELAY
3827 | INSN_COND_BRANCH_DELAY
3828 | INSN_COND_BRANCH_LIKELY)) != 0);
3829}
3830
3831/* Given that a macro is longer than 4 bytes, return the appropriate warning
3832 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3833 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3834
3835static const char *
3836macro_warning (relax_substateT subtype)
3837{
3838 if (subtype & RELAX_DELAY_SLOT)
3839 return _("Macro instruction expanded into multiple instructions"
3840 " in a branch delay slot");
3841 else if (subtype & RELAX_NOMACRO)
3842 return _("Macro instruction expanded into multiple instructions");
3843 else
3844 return 0;
3845}
3846
3847/* Finish up a macro. Emit warnings as appropriate. */
3848
3849static void
3850macro_end (void)
3851{
3852 if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
3853 {
3854 relax_substateT subtype;
3855
3856 /* Set up the relaxation warning flags. */
3857 subtype = 0;
3858 if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
3859 subtype |= RELAX_SECOND_LONGER;
3860 if (mips_opts.warn_about_macros)
3861 subtype |= RELAX_NOMACRO;
3862 if (mips_macro_warning.delay_slot_p)
3863 subtype |= RELAX_DELAY_SLOT;
3864
3865 if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
3866 {
3867 /* Either the macro has a single implementation or both
3868 implementations are longer than 4 bytes. Emit the
3869 warning now. */
3870 const char *msg = macro_warning (subtype);
3871 if (msg != 0)
3872 as_warn ("%s", msg);
3873 }
3874 else
3875 {
3876 /* One implementation might need a warning but the other
3877 definitely doesn't. */
3878 mips_macro_warning.first_frag->fr_subtype |= subtype;
3879 }
3880 }
3881}
3882
3883/* Read a macro's relocation codes from *ARGS and store them in *R.
3884 The first argument in *ARGS will be either the code for a single
3885 relocation or -1 followed by the three codes that make up a
3886 composite relocation. */
3887
3888static void
3889macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
3890{
3891 int i, next;
3892
3893 next = va_arg (*args, int);
3894 if (next >= 0)
3895 r[0] = (bfd_reloc_code_real_type) next;
3896 else
3897 for (i = 0; i < 3; i++)
3898 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
3899}
3900
3901/* Build an instruction created by a macro expansion. This is passed
3902 a pointer to the count of instructions created so far, an
3903 expression, the name of the instruction to build, an operand format
3904 string, and corresponding arguments. */
3905
3906static void
3907macro_build (expressionS *ep, const char *name, const char *fmt, ...)
3908{
3909 const struct mips_opcode *mo;
3910 struct mips_cl_insn insn;
3911 bfd_reloc_code_real_type r[3];
3912 va_list args;
3913
3914 va_start (args, fmt);
3915
3916 if (mips_opts.mips16)
3917 {
3918 mips16_macro_build (ep, name, fmt, &args);
3919 va_end (args);
3920 return;
3921 }
3922
3923 r[0] = BFD_RELOC_UNUSED;
3924 r[1] = BFD_RELOC_UNUSED;
3925 r[2] = BFD_RELOC_UNUSED;
3926 mo = (struct mips_opcode *) hash_find (op_hash, name);
3927 gas_assert (mo);
3928 gas_assert (strcmp (name, mo->name) == 0);
3929
3930 while (1)
3931 {
3932 /* Search until we get a match for NAME. It is assumed here that
3933 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3934 if (strcmp (fmt, mo->args) == 0
3935 && mo->pinfo != INSN_MACRO
3936 && is_opcode_valid (mo))
3937 break;
3938
3939 ++mo;
3940 gas_assert (mo->name);
3941 gas_assert (strcmp (name, mo->name) == 0);
3942 }
3943
3944 create_insn (&insn, mo);
3945 for (;;)
3946 {
3947 switch (*fmt++)
3948 {
3949 case '\0':
3950 break;
3951
3952 case ',':
3953 case '(':
3954 case ')':
3955 continue;
3956
3957 case '+':
3958 switch (*fmt++)
3959 {
3960 case 'A':
3961 case 'E':
3962 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3963 continue;
3964
3965 case 'B':
3966 case 'F':
3967 /* Note that in the macro case, these arguments are already
3968 in MSB form. (When handling the instruction in the
3969 non-macro case, these arguments are sizes from which
3970 MSB values must be calculated.) */
3971 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3972 continue;
3973
3974 case 'C':
3975 case 'G':
3976 case 'H':
3977 /* Note that in the macro case, these arguments are already
3978 in MSBD form. (When handling the instruction in the
3979 non-macro case, these arguments are sizes from which
3980 MSBD values must be calculated.) */
3981 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3982 continue;
3983
3984 case 'Q':
3985 INSERT_OPERAND (SEQI, insn, va_arg (args, int));
3986 continue;
3987
3988 default:
3989 internalError ();
3990 }
3991 continue;
3992
3993 case '2':
3994 INSERT_OPERAND (BP, insn, va_arg (args, int));
3995 continue;
3996
3997 case 't':
3998 case 'w':
3999 case 'E':
4000 INSERT_OPERAND (RT, insn, va_arg (args, int));
4001 continue;
4002
4003 case 'c':
4004 INSERT_OPERAND (CODE, insn, va_arg (args, int));
4005 continue;
4006
4007 case 'T':
4008 case 'W':
4009 INSERT_OPERAND (FT, insn, va_arg (args, int));
4010 continue;
4011
4012 case 'd':
4013 case 'G':
4014 case 'K':
4015 INSERT_OPERAND (RD, insn, va_arg (args, int));
4016 continue;
4017
4018 case 'U':
4019 {
4020 int tmp = va_arg (args, int);
4021
4022 INSERT_OPERAND (RT, insn, tmp);
4023 INSERT_OPERAND (RD, insn, tmp);
4024 continue;
4025 }
4026
4027 case 'V':
4028 case 'S':
4029 INSERT_OPERAND (FS, insn, va_arg (args, int));
4030 continue;
4031
4032 case 'z':
4033 continue;
4034
4035 case '<':
4036 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
4037 continue;
4038
4039 case 'D':
4040 INSERT_OPERAND (FD, insn, va_arg (args, int));
4041 continue;
4042
4043 case 'B':
4044 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
4045 continue;
4046
4047 case 'J':
4048 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
4049 continue;
4050
4051 case 'q':
4052 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
4053 continue;
4054
4055 case 'b':
4056 case 's':
4057 case 'r':
4058 case 'v':
4059 INSERT_OPERAND (RS, insn, va_arg (args, int));
4060 continue;
4061
4062 case 'i':
4063 case 'j':
4064 macro_read_relocs (&args, r);
4065 gas_assert (*r == BFD_RELOC_GPREL16
4066 || *r == BFD_RELOC_MIPS_HIGHER
4067 || *r == BFD_RELOC_HI16_S
4068 || *r == BFD_RELOC_LO16
4069 || *r == BFD_RELOC_MIPS_GOT_OFST);
4070 continue;
4071
4072 case 'o':
4073 macro_read_relocs (&args, r);
4074 continue;
4075
4076 case 'u':
4077 macro_read_relocs (&args, r);
4078 gas_assert (ep != NULL
4079 && (ep->X_op == O_constant
4080 || (ep->X_op == O_symbol
4081 && (*r == BFD_RELOC_MIPS_HIGHEST
4082 || *r == BFD_RELOC_HI16_S
4083 || *r == BFD_RELOC_HI16
4084 || *r == BFD_RELOC_GPREL16
4085 || *r == BFD_RELOC_MIPS_GOT_HI16
4086 || *r == BFD_RELOC_MIPS_CALL_HI16))));
4087 continue;
4088
4089 case 'p':
4090 gas_assert (ep != NULL);
4091
4092 /*
4093 * This allows macro() to pass an immediate expression for
4094 * creating short branches without creating a symbol.
4095 *
4096 * We don't allow branch relaxation for these branches, as
4097 * they should only appear in ".set nomacro" anyway.
4098 */
4099 if (ep->X_op == O_constant)
4100 {
4101 if ((ep->X_add_number & 3) != 0)
4102 as_bad (_("branch to misaligned address (0x%lx)"),
4103 (unsigned long) ep->X_add_number);
4104 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
4105 as_bad (_("branch address range overflow (0x%lx)"),
4106 (unsigned long) ep->X_add_number);
4107 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
4108 ep = NULL;
4109 }
4110 else
4111 *r = BFD_RELOC_16_PCREL_S2;
4112 continue;
4113
4114 case 'a':
4115 gas_assert (ep != NULL);
4116 *r = BFD_RELOC_MIPS_JMP;
4117 continue;
4118
4119 case 'C':
4120 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
4121 continue;
4122
4123 case 'k':
4124 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
4125 continue;
4126
4127 default:
4128 internalError ();
4129 }
4130 break;
4131 }
4132 va_end (args);
4133 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4134
4135 append_insn (&insn, ep, r);
4136}
4137
4138static void
4139mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
4140 va_list *args)
4141{
4142 struct mips_opcode *mo;
4143 struct mips_cl_insn insn;
4144 bfd_reloc_code_real_type r[3]
4145 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4146
4147 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
4148 gas_assert (mo);
4149 gas_assert (strcmp (name, mo->name) == 0);
4150
4151 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
4152 {
4153 ++mo;
4154 gas_assert (mo->name);
4155 gas_assert (strcmp (name, mo->name) == 0);
4156 }
4157
4158 create_insn (&insn, mo);
4159 for (;;)
4160 {
4161 int c;
4162
4163 c = *fmt++;
4164 switch (c)
4165 {
4166 case '\0':
4167 break;
4168
4169 case ',':
4170 case '(':
4171 case ')':
4172 continue;
4173
4174 case 'y':
4175 case 'w':
4176 MIPS16_INSERT_OPERAND (RY, insn, va_arg (*args, int));
4177 continue;
4178
4179 case 'x':
4180 case 'v':
4181 MIPS16_INSERT_OPERAND (RX, insn, va_arg (*args, int));
4182 continue;
4183
4184 case 'z':
4185 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (*args, int));
4186 continue;
4187
4188 case 'Z':
4189 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (*args, int));
4190 continue;
4191
4192 case '0':
4193 case 'S':
4194 case 'P':
4195 case 'R':
4196 continue;
4197
4198 case 'X':
4199 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (*args, int));
4200 continue;
4201
4202 case 'Y':
4203 {
4204 int regno;
4205
4206 regno = va_arg (*args, int);
4207 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
4208 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
4209 }
4210 continue;
4211
4212 case '<':
4213 case '>':
4214 case '4':
4215 case '5':
4216 case 'H':
4217 case 'W':
4218 case 'D':
4219 case 'j':
4220 case '8':
4221 case 'V':
4222 case 'C':
4223 case 'U':
4224 case 'k':
4225 case 'K':
4226 case 'p':
4227 case 'q':
4228 {
4229 gas_assert (ep != NULL);
4230
4231 if (ep->X_op != O_constant)
4232 *r = (int) BFD_RELOC_UNUSED + c;
4233 else
4234 {
4235 mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
4236 FALSE, &insn.insn_opcode, &insn.use_extend,
4237 &insn.extend);
4238 ep = NULL;
4239 *r = BFD_RELOC_UNUSED;
4240 }
4241 }
4242 continue;
4243
4244 case '6':
4245 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (*args, int));
4246 continue;
4247 }
4248
4249 break;
4250 }
4251
4252 gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
4253
4254 append_insn (&insn, ep, r);
4255}
4256
4257/*
4258 * Sign-extend 32-bit mode constants that have bit 31 set and all
4259 * higher bits unset.
4260 */
4261static void
4262normalize_constant_expr (expressionS *ex)
4263{
4264 if (ex->X_op == O_constant
4265 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4266 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4267 - 0x80000000);
4268}
4269
4270/*
4271 * Sign-extend 32-bit mode address offsets that have bit 31 set and
4272 * all higher bits unset.
4273 */
4274static void
4275normalize_address_expr (expressionS *ex)
4276{
4277 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
4278 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
4279 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
4280 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
4281 - 0x80000000);
4282}
4283
4284/*
4285 * Generate a "jalr" instruction with a relocation hint to the called
4286 * function. This occurs in NewABI PIC code.
4287 */
4288static void
4289macro_build_jalr (expressionS *ep)
4290{
4291 char *f = NULL;
4292
4293 if (MIPS_JALR_HINT_P (ep))
4294 {
4295 frag_grow (8);
4296 f = frag_more (0);
4297 }
4298 macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
4299 if (MIPS_JALR_HINT_P (ep))
4300 fix_new_exp (frag_now, f - frag_now->fr_literal,
4301 4, ep, FALSE, BFD_RELOC_MIPS_JALR);
4302}
4303
4304/*
4305 * Generate a "lui" instruction.
4306 */
4307static void
4308macro_build_lui (expressionS *ep, int regnum)
4309{
4310 expressionS high_expr;
4311 const struct mips_opcode *mo;
4312 struct mips_cl_insn insn;
4313 bfd_reloc_code_real_type r[3]
4314 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
4315 const char *name = "lui";
4316 const char *fmt = "t,u";
4317
4318 gas_assert (! mips_opts.mips16);
4319
4320 high_expr = *ep;
4321
4322 if (high_expr.X_op == O_constant)
4323 {
4324 /* We can compute the instruction now without a relocation entry. */
4325 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
4326 >> 16) & 0xffff;
4327 *r = BFD_RELOC_UNUSED;
4328 }
4329 else
4330 {
4331 gas_assert (ep->X_op == O_symbol);
4332 /* _gp_disp is a special case, used from s_cpload.
4333 __gnu_local_gp is used if mips_no_shared. */
4334 gas_assert (mips_pic == NO_PIC
4335 || (! HAVE_NEWABI
4336 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
4337 || (! mips_in_shared
4338 && strcmp (S_GET_NAME (ep->X_add_symbol),
4339 "__gnu_local_gp") == 0));
4340 *r = BFD_RELOC_HI16_S;
4341 }
4342
4343 mo = hash_find (op_hash, name);
4344 gas_assert (strcmp (name, mo->name) == 0);
4345 gas_assert (strcmp (fmt, mo->args) == 0);
4346 create_insn (&insn, mo);
4347
4348 insn.insn_opcode = insn.insn_mo->match;
4349 INSERT_OPERAND (RT, insn, regnum);
4350 if (*r == BFD_RELOC_UNUSED)
4351 {
4352 insn.insn_opcode |= high_expr.X_add_number;
4353 append_insn (&insn, NULL, r);
4354 }
4355 else
4356 append_insn (&insn, &high_expr, r);
4357}
4358
4359/* Generate a sequence of instructions to do a load or store from a constant
4360 offset off of a base register (breg) into/from a target register (treg),
4361 using AT if necessary. */
4362static void
4363macro_build_ldst_constoffset (expressionS *ep, const char *op,
4364 int treg, int breg, int dbl)
4365{
4366 gas_assert (ep->X_op == O_constant);
4367
4368 /* Sign-extending 32-bit constants makes their handling easier. */
4369 if (!dbl)
4370 normalize_constant_expr (ep);
4371
4372 /* Right now, this routine can only handle signed 32-bit constants. */
4373 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
4374 as_warn (_("operand overflow"));
4375
4376 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
4377 {
4378 /* Signed 16-bit offset will fit in the op. Easy! */
4379 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
4380 }
4381 else
4382 {
4383 /* 32-bit offset, need multiple instructions and AT, like:
4384 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
4385 addu $tempreg,$tempreg,$breg
4386 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
4387 to handle the complete offset. */
4388 macro_build_lui (ep, AT);
4389 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
4390 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
4391
4392 if (!mips_opts.at)
4393 as_bad (_("Macro used $at after \".set noat\""));
4394 }
4395}
4396
4397/* set_at()
4398 * Generates code to set the $at register to true (one)
4399 * if reg is less than the immediate expression.
4400 */
4401static void
4402set_at (int reg, int unsignedp)
4403{
4404 if (imm_expr.X_op == O_constant
4405 && imm_expr.X_add_number >= -0x8000
4406 && imm_expr.X_add_number < 0x8000)
4407 macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
4408 AT, reg, BFD_RELOC_LO16);
4409 else
4410 {
4411 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4412 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
4413 }
4414}
4415
4416/* Warn if an expression is not a constant. */
4417
4418static void
4419check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
4420{
4421 if (ex->X_op == O_big)
4422 as_bad (_("unsupported large constant"));
4423 else if (ex->X_op != O_constant)
4424 as_bad (_("Instruction %s requires absolute expression"),
4425 ip->insn_mo->name);
4426
4427 if (HAVE_32BIT_GPRS)
4428 normalize_constant_expr (ex);
4429}
4430
4431/* Count the leading zeroes by performing a binary chop. This is a
4432 bulky bit of source, but performance is a LOT better for the
4433 majority of values than a simple loop to count the bits:
4434 for (lcnt = 0; (lcnt < 32); lcnt++)
4435 if ((v) & (1 << (31 - lcnt)))
4436 break;
4437 However it is not code size friendly, and the gain will drop a bit
4438 on certain cached systems.
4439*/
4440#define COUNT_TOP_ZEROES(v) \
4441 (((v) & ~0xffff) == 0 \
4442 ? ((v) & ~0xff) == 0 \
4443 ? ((v) & ~0xf) == 0 \
4444 ? ((v) & ~0x3) == 0 \
4445 ? ((v) & ~0x1) == 0 \
4446 ? !(v) \
4447 ? 32 \
4448 : 31 \
4449 : 30 \
4450 : ((v) & ~0x7) == 0 \
4451 ? 29 \
4452 : 28 \
4453 : ((v) & ~0x3f) == 0 \
4454 ? ((v) & ~0x1f) == 0 \
4455 ? 27 \
4456 : 26 \
4457 : ((v) & ~0x7f) == 0 \
4458 ? 25 \
4459 : 24 \
4460 : ((v) & ~0xfff) == 0 \
4461 ? ((v) & ~0x3ff) == 0 \
4462 ? ((v) & ~0x1ff) == 0 \
4463 ? 23 \
4464 : 22 \
4465 : ((v) & ~0x7ff) == 0 \
4466 ? 21 \
4467 : 20 \
4468 : ((v) & ~0x3fff) == 0 \
4469 ? ((v) & ~0x1fff) == 0 \
4470 ? 19 \
4471 : 18 \
4472 : ((v) & ~0x7fff) == 0 \
4473 ? 17 \
4474 : 16 \
4475 : ((v) & ~0xffffff) == 0 \
4476 ? ((v) & ~0xfffff) == 0 \
4477 ? ((v) & ~0x3ffff) == 0 \
4478 ? ((v) & ~0x1ffff) == 0 \
4479 ? 15 \
4480 : 14 \
4481 : ((v) & ~0x7ffff) == 0 \
4482 ? 13 \
4483 : 12 \
4484 : ((v) & ~0x3fffff) == 0 \
4485 ? ((v) & ~0x1fffff) == 0 \
4486 ? 11 \
4487 : 10 \
4488 : ((v) & ~0x7fffff) == 0 \
4489 ? 9 \
4490 : 8 \
4491 : ((v) & ~0xfffffff) == 0 \
4492 ? ((v) & ~0x3ffffff) == 0 \
4493 ? ((v) & ~0x1ffffff) == 0 \
4494 ? 7 \
4495 : 6 \
4496 : ((v) & ~0x7ffffff) == 0 \
4497 ? 5 \
4498 : 4 \
4499 : ((v) & ~0x3fffffff) == 0 \
4500 ? ((v) & ~0x1fffffff) == 0 \
4501 ? 3 \
4502 : 2 \
4503 : ((v) & ~0x7fffffff) == 0 \
4504 ? 1 \
4505 : 0)
4506
4507/* load_register()
4508 * This routine generates the least number of instructions necessary to load
4509 * an absolute expression value into a register.
4510 */
4511static void
4512load_register (int reg, expressionS *ep, int dbl)
4513{
4514 int freg;
4515 expressionS hi32, lo32;
4516
4517 if (ep->X_op != O_big)
4518 {
4519 gas_assert (ep->X_op == O_constant);
4520
4521 /* Sign-extending 32-bit constants makes their handling easier. */
4522 if (!dbl)
4523 normalize_constant_expr (ep);
4524
4525 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
4526 {
4527 /* We can handle 16 bit signed values with an addiu to
4528 $zero. No need to ever use daddiu here, since $zero and
4529 the result are always correct in 32 bit mode. */
4530 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4531 return;
4532 }
4533 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
4534 {
4535 /* We can handle 16 bit unsigned values with an ori to
4536 $zero. */
4537 macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4538 return;
4539 }
4540 else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
4541 {
4542 /* 32 bit values require an lui. */
4543 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
4544 if ((ep->X_add_number & 0xffff) != 0)
4545 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4546 return;
4547 }
4548 }
4549
4550 /* The value is larger than 32 bits. */
4551
4552 if (!dbl || HAVE_32BIT_GPRS)
4553 {
4554 char value[32];
4555
4556 sprintf_vma (value, ep->X_add_number);
4557 as_bad (_("Number (0x%s) larger than 32 bits"), value);
4558 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4559 return;
4560 }
4561
4562 if (ep->X_op != O_big)
4563 {
4564 hi32 = *ep;
4565 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4566 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
4567 hi32.X_add_number &= 0xffffffff;
4568 lo32 = *ep;
4569 lo32.X_add_number &= 0xffffffff;
4570 }
4571 else
4572 {
4573 gas_assert (ep->X_add_number > 2);
4574 if (ep->X_add_number == 3)
4575 generic_bignum[3] = 0;
4576 else if (ep->X_add_number > 4)
4577 as_bad (_("Number larger than 64 bits"));
4578 lo32.X_op = O_constant;
4579 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
4580 hi32.X_op = O_constant;
4581 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
4582 }
4583
4584 if (hi32.X_add_number == 0)
4585 freg = 0;
4586 else
4587 {
4588 int shift, bit;
4589 unsigned long hi, lo;
4590
4591 if (hi32.X_add_number == (offsetT) 0xffffffff)
4592 {
4593 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
4594 {
4595 macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4596 return;
4597 }
4598 if (lo32.X_add_number & 0x80000000)
4599 {
4600 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4601 if (lo32.X_add_number & 0xffff)
4602 macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
4603 return;
4604 }
4605 }
4606
4607 /* Check for 16bit shifted constant. We know that hi32 is
4608 non-zero, so start the mask on the first bit of the hi32
4609 value. */
4610 shift = 17;
4611 do
4612 {
4613 unsigned long himask, lomask;
4614
4615 if (shift < 32)
4616 {
4617 himask = 0xffff >> (32 - shift);
4618 lomask = (0xffff << shift) & 0xffffffff;
4619 }
4620 else
4621 {
4622 himask = 0xffff << (shift - 32);
4623 lomask = 0;
4624 }
4625 if ((hi32.X_add_number & ~(offsetT) himask) == 0
4626 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
4627 {
4628 expressionS tmp;
4629
4630 tmp.X_op = O_constant;
4631 if (shift < 32)
4632 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
4633 | (lo32.X_add_number >> shift));
4634 else
4635 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
4636 macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
4637 macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
4638 reg, reg, (shift >= 32) ? shift - 32 : shift);
4639 return;
4640 }
4641 ++shift;
4642 }
4643 while (shift <= (64 - 16));
4644
4645 /* Find the bit number of the lowest one bit, and store the
4646 shifted value in hi/lo. */
4647 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
4648 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
4649 if (lo != 0)
4650 {
4651 bit = 0;
4652 while ((lo & 1) == 0)
4653 {
4654 lo >>= 1;
4655 ++bit;
4656 }
4657 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
4658 hi >>= bit;
4659 }
4660 else
4661 {
4662 bit = 32;
4663 while ((hi & 1) == 0)
4664 {
4665 hi >>= 1;
4666 ++bit;
4667 }
4668 lo = hi;
4669 hi = 0;
4670 }
4671
4672 /* Optimize if the shifted value is a (power of 2) - 1. */
4673 if ((hi == 0 && ((lo + 1) & lo) == 0)
4674 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
4675 {
4676 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
4677 if (shift != 0)
4678 {
4679 expressionS tmp;
4680
4681 /* This instruction will set the register to be all
4682 ones. */
4683 tmp.X_op = O_constant;
4684 tmp.X_add_number = (offsetT) -1;
4685 macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
4686 if (bit != 0)
4687 {
4688 bit += shift;
4689 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
4690 reg, reg, (bit >= 32) ? bit - 32 : bit);
4691 }
4692 macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
4693 reg, reg, (shift >= 32) ? shift - 32 : shift);
4694 return;
4695 }
4696 }
4697
4698 /* Sign extend hi32 before calling load_register, because we can
4699 generally get better code when we load a sign extended value. */
4700 if ((hi32.X_add_number & 0x80000000) != 0)
4701 hi32.X_add_number |= ~(offsetT) 0xffffffff;
4702 load_register (reg, &hi32, 0);
4703 freg = reg;
4704 }
4705 if ((lo32.X_add_number & 0xffff0000) == 0)
4706 {
4707 if (freg != 0)
4708 {
4709 macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
4710 freg = reg;
4711 }
4712 }
4713 else
4714 {
4715 expressionS mid16;
4716
4717 if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
4718 {
4719 macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
4720 macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
4721 return;
4722 }
4723
4724 if (freg != 0)
4725 {
4726 macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
4727 freg = reg;
4728 }
4729 mid16 = lo32;
4730 mid16.X_add_number >>= 16;
4731 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4732 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4733 freg = reg;
4734 }
4735 if ((lo32.X_add_number & 0xffff) != 0)
4736 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
4737}
4738
4739static inline void
4740load_delay_nop (void)
4741{
4742 if (!gpr_interlocks)
4743 macro_build (NULL, "nop", "");
4744}
4745
4746/* Load an address into a register. */
4747
4748static void
4749load_address (int reg, expressionS *ep, int *used_at)
4750{
4751 if (ep->X_op != O_constant
4752 && ep->X_op != O_symbol)
4753 {
4754 as_bad (_("expression too complex"));
4755 ep->X_op = O_constant;
4756 }
4757
4758 if (ep->X_op == O_constant)
4759 {
4760 load_register (reg, ep, HAVE_64BIT_ADDRESSES);
4761 return;
4762 }
4763
4764 if (mips_pic == NO_PIC)
4765 {
4766 /* If this is a reference to a GP relative symbol, we want
4767 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4768 Otherwise we want
4769 lui $reg,<sym> (BFD_RELOC_HI16_S)
4770 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4771 If we have an addend, we always use the latter form.
4772
4773 With 64bit address space and a usable $at we want
4774 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4775 lui $at,<sym> (BFD_RELOC_HI16_S)
4776 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4777 daddiu $at,<sym> (BFD_RELOC_LO16)
4778 dsll32 $reg,0
4779 daddu $reg,$reg,$at
4780
4781 If $at is already in use, we use a path which is suboptimal
4782 on superscalar processors.
4783 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4784 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4785 dsll $reg,16
4786 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4787 dsll $reg,16
4788 daddiu $reg,<sym> (BFD_RELOC_LO16)
4789
4790 For GP relative symbols in 64bit address space we can use
4791 the same sequence as in 32bit address space. */
4792 if (HAVE_64BIT_SYMBOLS)
4793 {
4794 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4795 && !nopic_need_relax (ep->X_add_symbol, 1))
4796 {
4797 relax_start (ep->X_add_symbol);
4798 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4799 mips_gp_register, BFD_RELOC_GPREL16);
4800 relax_switch ();
4801 }
4802
4803 if (*used_at == 0 && mips_opts.at)
4804 {
4805 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4806 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
4807 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4808 BFD_RELOC_MIPS_HIGHER);
4809 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
4810 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
4811 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
4812 *used_at = 1;
4813 }
4814 else
4815 {
4816 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
4817 macro_build (ep, "daddiu", "t,r,j", reg, reg,
4818 BFD_RELOC_MIPS_HIGHER);
4819 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4820 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
4821 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
4822 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
4823 }
4824
4825 if (mips_relax.sequence)
4826 relax_end ();
4827 }
4828 else
4829 {
4830 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
4831 && !nopic_need_relax (ep->X_add_symbol, 1))
4832 {
4833 relax_start (ep->X_add_symbol);
4834 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
4835 mips_gp_register, BFD_RELOC_GPREL16);
4836 relax_switch ();
4837 }
4838 macro_build_lui (ep, reg);
4839 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4840 reg, reg, BFD_RELOC_LO16);
4841 if (mips_relax.sequence)
4842 relax_end ();
4843 }
4844 }
4845 else if (!mips_big_got)
4846 {
4847 expressionS ex;
4848
4849 /* If this is a reference to an external symbol, we want
4850 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4851 Otherwise we want
4852 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4853 nop
4854 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4855 If there is a constant, it must be added in after.
4856
4857 If we have NewABI, we want
4858 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4859 unless we're referencing a global symbol with a non-zero
4860 offset, in which case cst must be added separately. */
4861 if (HAVE_NEWABI)
4862 {
4863 if (ep->X_add_number)
4864 {
4865 ex.X_add_number = ep->X_add_number;
4866 ep->X_add_number = 0;
4867 relax_start (ep->X_add_symbol);
4868 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4869 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4870 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4871 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4872 ex.X_op = O_constant;
4873 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4874 reg, reg, BFD_RELOC_LO16);
4875 ep->X_add_number = ex.X_add_number;
4876 relax_switch ();
4877 }
4878 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4879 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
4880 if (mips_relax.sequence)
4881 relax_end ();
4882 }
4883 else
4884 {
4885 ex.X_add_number = ep->X_add_number;
4886 ep->X_add_number = 0;
4887 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4888 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4889 load_delay_nop ();
4890 relax_start (ep->X_add_symbol);
4891 relax_switch ();
4892 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4893 BFD_RELOC_LO16);
4894 relax_end ();
4895
4896 if (ex.X_add_number != 0)
4897 {
4898 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4899 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4900 ex.X_op = O_constant;
4901 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
4902 reg, reg, BFD_RELOC_LO16);
4903 }
4904 }
4905 }
4906 else if (mips_big_got)
4907 {
4908 expressionS ex;
4909
4910 /* This is the large GOT case. If this is a reference to an
4911 external symbol, we want
4912 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4913 addu $reg,$reg,$gp
4914 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4915
4916 Otherwise, for a reference to a local symbol in old ABI, we want
4917 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4918 nop
4919 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4920 If there is a constant, it must be added in after.
4921
4922 In the NewABI, for local symbols, with or without offsets, we want:
4923 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4924 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4925 */
4926 if (HAVE_NEWABI)
4927 {
4928 ex.X_add_number = ep->X_add_number;
4929 ep->X_add_number = 0;
4930 relax_start (ep->X_add_symbol);
4931 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4932 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4933 reg, reg, mips_gp_register);
4934 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4935 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4936 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4937 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4938 else if (ex.X_add_number)
4939 {
4940 ex.X_op = O_constant;
4941 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4942 BFD_RELOC_LO16);
4943 }
4944
4945 ep->X_add_number = ex.X_add_number;
4946 relax_switch ();
4947 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4948 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
4949 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4950 BFD_RELOC_MIPS_GOT_OFST);
4951 relax_end ();
4952 }
4953 else
4954 {
4955 ex.X_add_number = ep->X_add_number;
4956 ep->X_add_number = 0;
4957 relax_start (ep->X_add_symbol);
4958 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
4959 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
4960 reg, reg, mips_gp_register);
4961 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
4962 reg, BFD_RELOC_MIPS_GOT_LO16, reg);
4963 relax_switch ();
4964 if (reg_needs_delay (mips_gp_register))
4965 {
4966 /* We need a nop before loading from $gp. This special
4967 check is required because the lui which starts the main
4968 instruction stream does not refer to $gp, and so will not
4969 insert the nop which may be required. */
4970 macro_build (NULL, "nop", "");
4971 }
4972 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4973 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4974 load_delay_nop ();
4975 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4976 BFD_RELOC_LO16);
4977 relax_end ();
4978
4979 if (ex.X_add_number != 0)
4980 {
4981 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4982 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4983 ex.X_op = O_constant;
4984 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4985 BFD_RELOC_LO16);
4986 }
4987 }
4988 }
4989 else
4990 abort ();
4991
4992 if (!mips_opts.at && *used_at == 1)
4993 as_bad (_("Macro used $at after \".set noat\""));
4994}
4995
4996/* Move the contents of register SOURCE into register DEST. */
4997
4998static void
4999move_register (int dest, int source)
5000{
5001 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
5002 dest, source, 0);
5003}
5004
5005/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
5006 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
5007 The two alternatives are:
5008
5009 Global symbol Local sybmol
5010 ------------- ------------
5011 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
5012 ... ...
5013 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
5014
5015 load_got_offset emits the first instruction and add_got_offset
5016 emits the second for a 16-bit offset or add_got_offset_hilo emits
5017 a sequence to add a 32-bit offset using a scratch register. */
5018
5019static void
5020load_got_offset (int dest, expressionS *local)
5021{
5022 expressionS global;
5023
5024 global = *local;
5025 global.X_add_number = 0;
5026
5027 relax_start (local->X_add_symbol);
5028 macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5029 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5030 relax_switch ();
5031 macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
5032 BFD_RELOC_MIPS_GOT16, mips_gp_register);
5033 relax_end ();
5034}
5035
5036static void
5037add_got_offset (int dest, expressionS *local)
5038{
5039 expressionS global;
5040
5041 global.X_op = O_constant;
5042 global.X_op_symbol = NULL;
5043 global.X_add_symbol = NULL;
5044 global.X_add_number = local->X_add_number;
5045
5046 relax_start (local->X_add_symbol);
5047 macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
5048 dest, dest, BFD_RELOC_LO16);
5049 relax_switch ();
5050 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
5051 relax_end ();
5052}
5053
5054static void
5055add_got_offset_hilo (int dest, expressionS *local, int tmp)
5056{
5057 expressionS global;
5058 int hold_mips_optimize;
5059
5060 global.X_op = O_constant;
5061 global.X_op_symbol = NULL;
5062 global.X_add_symbol = NULL;
5063 global.X_add_number = local->X_add_number;
5064
5065 relax_start (local->X_add_symbol);
5066 load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
5067 relax_switch ();
5068 /* Set mips_optimize around the lui instruction to avoid
5069 inserting an unnecessary nop after the lw. */
5070 hold_mips_optimize = mips_optimize;
5071 mips_optimize = 2;
5072 macro_build_lui (&global, tmp);
5073 mips_optimize = hold_mips_optimize;
5074 macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
5075 relax_end ();
5076
5077 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
5078}
5079
5080/*
5081 * Build macros
5082 * This routine implements the seemingly endless macro or synthesized
5083 * instructions and addressing modes in the mips assembly language. Many
5084 * of these macros are simple and are similar to each other. These could
5085 * probably be handled by some kind of table or grammar approach instead of
5086 * this verbose method. Others are not simple macros but are more like
5087 * optimizing code generation.
5088 * One interesting optimization is when several store macros appear
5089 * consecutively that would load AT with the upper half of the same address.
5090 * The ensuing load upper instructions are ommited. This implies some kind
5091 * of global optimization. We currently only optimize within a single macro.
5092 * For many of the load and store macros if the address is specified as a
5093 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
5094 * first load register 'at' with zero and use it as the base register. The
5095 * mips assembler simply uses register $zero. Just one tiny optimization
5096 * we're missing.
5097 */
5098static void
5099macro (struct mips_cl_insn *ip)
5100{
5101 unsigned int treg, sreg, dreg, breg;
5102 unsigned int tempreg;
5103 int mask;
5104 int used_at = 0;
5105 expressionS expr1;
5106 const char *s;
5107 const char *s2;
5108 const char *fmt;
5109 int likely = 0;
5110 int dbl = 0;
5111 int coproc = 0;
5112 int lr = 0;
5113 int imm = 0;
5114 int call = 0;
5115 int off;
5116 offsetT maxnum;
5117 bfd_reloc_code_real_type r;
5118 int hold_mips_optimize;
5119
5120 gas_assert (! mips_opts.mips16);
5121
5122 treg = EXTRACT_OPERAND (RT, *ip);
5123 dreg = EXTRACT_OPERAND (RD, *ip);
5124 sreg = breg = EXTRACT_OPERAND (RS, *ip);
5125 mask = ip->insn_mo->mask;
5126
5127 expr1.X_op = O_constant;
5128 expr1.X_op_symbol = NULL;
5129 expr1.X_add_symbol = NULL;
5130 expr1.X_add_number = 1;
5131
5132 switch (mask)
5133 {
5134 case M_DABS:
5135 dbl = 1;
5136 case M_ABS:
5137 /* bgez $a0,.+12
5138 move v0,$a0
5139 sub v0,$zero,$a0
5140 */
5141
5142 start_noreorder ();
5143
5144 expr1.X_add_number = 8;
5145 macro_build (&expr1, "bgez", "s,p", sreg);
5146 if (dreg == sreg)
5147 macro_build (NULL, "nop", "");
5148 else
5149 move_register (dreg, sreg);
5150 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
5151
5152 end_noreorder ();
5153 break;
5154
5155 case M_ADD_I:
5156 s = "addi";
5157 s2 = "add";
5158 goto do_addi;
5159 case M_ADDU_I:
5160 s = "addiu";
5161 s2 = "addu";
5162 goto do_addi;
5163 case M_DADD_I:
5164 dbl = 1;
5165 s = "daddi";
5166 s2 = "dadd";
5167 goto do_addi;
5168 case M_DADDU_I:
5169 dbl = 1;
5170 s = "daddiu";
5171 s2 = "daddu";
5172 do_addi:
5173 if (imm_expr.X_op == O_constant
5174 && imm_expr.X_add_number >= -0x8000
5175 && imm_expr.X_add_number < 0x8000)
5176 {
5177 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
5178 break;
5179 }
5180 used_at = 1;
5181 load_register (AT, &imm_expr, dbl);
5182 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5183 break;
5184
5185 case M_AND_I:
5186 s = "andi";
5187 s2 = "and";
5188 goto do_bit;
5189 case M_OR_I:
5190 s = "ori";
5191 s2 = "or";
5192 goto do_bit;
5193 case M_NOR_I:
5194 s = "";
5195 s2 = "nor";
5196 goto do_bit;
5197 case M_XOR_I:
5198 s = "xori";
5199 s2 = "xor";
5200 do_bit:
5201 if (imm_expr.X_op == O_constant
5202 && imm_expr.X_add_number >= 0
5203 && imm_expr.X_add_number < 0x10000)
5204 {
5205 if (mask != M_NOR_I)
5206 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
5207 else
5208 {
5209 macro_build (&imm_expr, "ori", "t,r,i",
5210 treg, sreg, BFD_RELOC_LO16);
5211 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
5212 }
5213 break;
5214 }
5215
5216 used_at = 1;
5217 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5218 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
5219 break;
5220
5221 case M_BALIGN:
5222 switch (imm_expr.X_add_number)
5223 {
5224 case 0:
5225 macro_build (NULL, "nop", "");
5226 break;
5227 case 2:
5228 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
5229 break;
5230 default:
5231 macro_build (NULL, "balign", "t,s,2", treg, sreg,
5232 (int) imm_expr.X_add_number);
5233 break;
5234 }
5235 break;
5236
5237 case M_BEQ_I:
5238 s = "beq";
5239 goto beq_i;
5240 case M_BEQL_I:
5241 s = "beql";
5242 likely = 1;
5243 goto beq_i;
5244 case M_BNE_I:
5245 s = "bne";
5246 goto beq_i;
5247 case M_BNEL_I:
5248 s = "bnel";
5249 likely = 1;
5250 beq_i:
5251 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5252 {
5253 macro_build (&offset_expr, s, "s,t,p", sreg, ZERO);
5254 break;
5255 }
5256 used_at = 1;
5257 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
5258 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
5259 break;
5260
5261 case M_BGEL:
5262 likely = 1;
5263 case M_BGE:
5264 if (treg == 0)
5265 {
5266 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5267 break;
5268 }
5269 if (sreg == 0)
5270 {
5271 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
5272 break;
5273 }
5274 used_at = 1;
5275 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5276 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5277 break;
5278
5279 case M_BGTL_I:
5280 likely = 1;
5281 case M_BGT_I:
5282 /* Check for > max integer. */
5283 maxnum = 0x7fffffff;
5284 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5285 {
5286 maxnum <<= 16;
5287 maxnum |= 0xffff;
5288 maxnum <<= 16;
5289 maxnum |= 0xffff;
5290 }
5291 if (imm_expr.X_op == O_constant
5292 && imm_expr.X_add_number >= maxnum
5293 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5294 {
5295 do_false:
5296 /* Result is always false. */
5297 if (! likely)
5298 macro_build (NULL, "nop", "");
5299 else
5300 macro_build (&offset_expr, "bnel", "s,t,p", ZERO, ZERO);
5301 break;
5302 }
5303 if (imm_expr.X_op != O_constant)
5304 as_bad (_("Unsupported large constant"));
5305 ++imm_expr.X_add_number;
5306 /* FALLTHROUGH */
5307 case M_BGE_I:
5308 case M_BGEL_I:
5309 if (mask == M_BGEL_I)
5310 likely = 1;
5311 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5312 {
5313 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
5314 break;
5315 }
5316 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5317 {
5318 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5319 break;
5320 }
5321 maxnum = 0x7fffffff;
5322 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5323 {
5324 maxnum <<= 16;
5325 maxnum |= 0xffff;
5326 maxnum <<= 16;
5327 maxnum |= 0xffff;
5328 }
5329 maxnum = - maxnum - 1;
5330 if (imm_expr.X_op == O_constant
5331 && imm_expr.X_add_number <= maxnum
5332 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5333 {
5334 do_true:
5335 /* result is always true */
5336 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
5337 macro_build (&offset_expr, "b", "p");
5338 break;
5339 }
5340 used_at = 1;
5341 set_at (sreg, 0);
5342 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5343 break;
5344
5345 case M_BGEUL:
5346 likely = 1;
5347 case M_BGEU:
5348 if (treg == 0)
5349 goto do_true;
5350 if (sreg == 0)
5351 {
5352 macro_build (&offset_expr, likely ? "beql" : "beq",
5353 "s,t,p", ZERO, treg);
5354 break;
5355 }
5356 used_at = 1;
5357 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5358 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5359 break;
5360
5361 case M_BGTUL_I:
5362 likely = 1;
5363 case M_BGTU_I:
5364 if (sreg == 0
5365 || (HAVE_32BIT_GPRS
5366 && imm_expr.X_op == O_constant
5367 && imm_expr.X_add_number == -1))
5368 goto do_false;
5369 if (imm_expr.X_op != O_constant)
5370 as_bad (_("Unsupported large constant"));
5371 ++imm_expr.X_add_number;
5372 /* FALLTHROUGH */
5373 case M_BGEU_I:
5374 case M_BGEUL_I:
5375 if (mask == M_BGEUL_I)
5376 likely = 1;
5377 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5378 goto do_true;
5379 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5380 {
5381 macro_build (&offset_expr, likely ? "bnel" : "bne",
5382 "s,t,p", sreg, ZERO);
5383 break;
5384 }
5385 used_at = 1;
5386 set_at (sreg, 1);
5387 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5388 break;
5389
5390 case M_BGTL:
5391 likely = 1;
5392 case M_BGT:
5393 if (treg == 0)
5394 {
5395 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
5396 break;
5397 }
5398 if (sreg == 0)
5399 {
5400 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
5401 break;
5402 }
5403 used_at = 1;
5404 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5405 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5406 break;
5407
5408 case M_BGTUL:
5409 likely = 1;
5410 case M_BGTU:
5411 if (treg == 0)
5412 {
5413 macro_build (&offset_expr, likely ? "bnel" : "bne",
5414 "s,t,p", sreg, ZERO);
5415 break;
5416 }
5417 if (sreg == 0)
5418 goto do_false;
5419 used_at = 1;
5420 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5421 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5422 break;
5423
5424 case M_BLEL:
5425 likely = 1;
5426 case M_BLE:
5427 if (treg == 0)
5428 {
5429 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5430 break;
5431 }
5432 if (sreg == 0)
5433 {
5434 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
5435 break;
5436 }
5437 used_at = 1;
5438 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
5439 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5440 break;
5441
5442 case M_BLEL_I:
5443 likely = 1;
5444 case M_BLE_I:
5445 maxnum = 0x7fffffff;
5446 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
5447 {
5448 maxnum <<= 16;
5449 maxnum |= 0xffff;
5450 maxnum <<= 16;
5451 maxnum |= 0xffff;
5452 }
5453 if (imm_expr.X_op == O_constant
5454 && imm_expr.X_add_number >= maxnum
5455 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
5456 goto do_true;
5457 if (imm_expr.X_op != O_constant)
5458 as_bad (_("Unsupported large constant"));
5459 ++imm_expr.X_add_number;
5460 /* FALLTHROUGH */
5461 case M_BLT_I:
5462 case M_BLTL_I:
5463 if (mask == M_BLTL_I)
5464 likely = 1;
5465 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5466 {
5467 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5468 break;
5469 }
5470 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5471 {
5472 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
5473 break;
5474 }
5475 used_at = 1;
5476 set_at (sreg, 0);
5477 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5478 break;
5479
5480 case M_BLEUL:
5481 likely = 1;
5482 case M_BLEU:
5483 if (treg == 0)
5484 {
5485 macro_build (&offset_expr, likely ? "beql" : "beq",
5486 "s,t,p", sreg, ZERO);
5487 break;
5488 }
5489 if (sreg == 0)
5490 goto do_true;
5491 used_at = 1;
5492 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
5493 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, ZERO);
5494 break;
5495
5496 case M_BLEUL_I:
5497 likely = 1;
5498 case M_BLEU_I:
5499 if (sreg == 0
5500 || (HAVE_32BIT_GPRS
5501 && imm_expr.X_op == O_constant
5502 && imm_expr.X_add_number == -1))
5503 goto do_true;
5504 if (imm_expr.X_op != O_constant)
5505 as_bad (_("Unsupported large constant"));
5506 ++imm_expr.X_add_number;
5507 /* FALLTHROUGH */
5508 case M_BLTU_I:
5509 case M_BLTUL_I:
5510 if (mask == M_BLTUL_I)
5511 likely = 1;
5512 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5513 goto do_false;
5514 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5515 {
5516 macro_build (&offset_expr, likely ? "beql" : "beq",
5517 "s,t,p", sreg, ZERO);
5518 break;
5519 }
5520 used_at = 1;
5521 set_at (sreg, 1);
5522 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5523 break;
5524
5525 case M_BLTL:
5526 likely = 1;
5527 case M_BLT:
5528 if (treg == 0)
5529 {
5530 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
5531 break;
5532 }
5533 if (sreg == 0)
5534 {
5535 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
5536 break;
5537 }
5538 used_at = 1;
5539 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
5540 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5541 break;
5542
5543 case M_BLTUL:
5544 likely = 1;
5545 case M_BLTU:
5546 if (treg == 0)
5547 goto do_false;
5548 if (sreg == 0)
5549 {
5550 macro_build (&offset_expr, likely ? "bnel" : "bne",
5551 "s,t,p", ZERO, treg);
5552 break;
5553 }
5554 used_at = 1;
5555 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
5556 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, ZERO);
5557 break;
5558
5559 case M_DEXT:
5560 {
5561 /* Use unsigned arithmetic. */
5562 addressT pos;
5563 addressT size;
5564
5565 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5566 {
5567 as_bad (_("Unsupported large constant"));
5568 pos = size = 1;
5569 }
5570 else
5571 {
5572 pos = imm_expr.X_add_number;
5573 size = imm2_expr.X_add_number;
5574 }
5575
5576 if (pos > 63)
5577 {
5578 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5579 pos = 1;
5580 }
5581 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5582 {
5583 as_bad (_("Improper extract size (%lu, position %lu)"),
5584 (unsigned long) size, (unsigned long) pos);
5585 size = 1;
5586 }
5587
5588 if (size <= 32 && pos < 32)
5589 {
5590 s = "dext";
5591 fmt = "t,r,+A,+C";
5592 }
5593 else if (size <= 32)
5594 {
5595 s = "dextu";
5596 fmt = "t,r,+E,+H";
5597 }
5598 else
5599 {
5600 s = "dextm";
5601 fmt = "t,r,+A,+G";
5602 }
5603 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5604 (int) (size - 1));
5605 }
5606 break;
5607
5608 case M_DINS:
5609 {
5610 /* Use unsigned arithmetic. */
5611 addressT pos;
5612 addressT size;
5613
5614 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
5615 {
5616 as_bad (_("Unsupported large constant"));
5617 pos = size = 1;
5618 }
5619 else
5620 {
5621 pos = imm_expr.X_add_number;
5622 size = imm2_expr.X_add_number;
5623 }
5624
5625 if (pos > 63)
5626 {
5627 as_bad (_("Improper position (%lu)"), (unsigned long) pos);
5628 pos = 1;
5629 }
5630 if (size == 0 || size > 64 || (pos + size - 1) > 63)
5631 {
5632 as_bad (_("Improper insert size (%lu, position %lu)"),
5633 (unsigned long) size, (unsigned long) pos);
5634 size = 1;
5635 }
5636
5637 if (pos < 32 && (pos + size - 1) < 32)
5638 {
5639 s = "dins";
5640 fmt = "t,r,+A,+B";
5641 }
5642 else if (pos >= 32)
5643 {
5644 s = "dinsu";
5645 fmt = "t,r,+E,+F";
5646 }
5647 else
5648 {
5649 s = "dinsm";
5650 fmt = "t,r,+A,+F";
5651 }
5652 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, (int) pos,
5653 (int) (pos + size - 1));
5654 }
5655 break;
5656
5657 case M_DDIV_3:
5658 dbl = 1;
5659 case M_DIV_3:
5660 s = "mflo";
5661 goto do_div3;
5662 case M_DREM_3:
5663 dbl = 1;
5664 case M_REM_3:
5665 s = "mfhi";
5666 do_div3:
5667 if (treg == 0)
5668 {
5669 as_warn (_("Divide by zero."));
5670 if (mips_trap)
5671 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5672 else
5673 macro_build (NULL, "break", "c", 7);
5674 break;
5675 }
5676
5677 start_noreorder ();
5678 if (mips_trap)
5679 {
5680 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5681 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5682 }
5683 else
5684 {
5685 expr1.X_add_number = 8;
5686 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5687 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
5688 macro_build (NULL, "break", "c", 7);
5689 }
5690 expr1.X_add_number = -1;
5691 used_at = 1;
5692 load_register (AT, &expr1, dbl);
5693 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
5694 macro_build (&expr1, "bne", "s,t,p", treg, AT);
5695 if (dbl)
5696 {
5697 expr1.X_add_number = 1;
5698 load_register (AT, &expr1, dbl);
5699 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
5700 }
5701 else
5702 {
5703 expr1.X_add_number = 0x80000000;
5704 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
5705 }
5706 if (mips_trap)
5707 {
5708 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
5709 /* We want to close the noreorder block as soon as possible, so
5710 that later insns are available for delay slot filling. */
5711 end_noreorder ();
5712 }
5713 else
5714 {
5715 expr1.X_add_number = 8;
5716 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
5717 macro_build (NULL, "nop", "");
5718
5719 /* We want to close the noreorder block as soon as possible, so
5720 that later insns are available for delay slot filling. */
5721 end_noreorder ();
5722
5723 macro_build (NULL, "break", "c", 6);
5724 }
5725 macro_build (NULL, s, "d", dreg);
5726 break;
5727
5728 case M_DIV_3I:
5729 s = "div";
5730 s2 = "mflo";
5731 goto do_divi;
5732 case M_DIVU_3I:
5733 s = "divu";
5734 s2 = "mflo";
5735 goto do_divi;
5736 case M_REM_3I:
5737 s = "div";
5738 s2 = "mfhi";
5739 goto do_divi;
5740 case M_REMU_3I:
5741 s = "divu";
5742 s2 = "mfhi";
5743 goto do_divi;
5744 case M_DDIV_3I:
5745 dbl = 1;
5746 s = "ddiv";
5747 s2 = "mflo";
5748 goto do_divi;
5749 case M_DDIVU_3I:
5750 dbl = 1;
5751 s = "ddivu";
5752 s2 = "mflo";
5753 goto do_divi;
5754 case M_DREM_3I:
5755 dbl = 1;
5756 s = "ddiv";
5757 s2 = "mfhi";
5758 goto do_divi;
5759 case M_DREMU_3I:
5760 dbl = 1;
5761 s = "ddivu";
5762 s2 = "mfhi";
5763 do_divi:
5764 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
5765 {
5766 as_warn (_("Divide by zero."));
5767 if (mips_trap)
5768 macro_build (NULL, "teq", "s,t,q", ZERO, ZERO, 7);
5769 else
5770 macro_build (NULL, "break", "c", 7);
5771 break;
5772 }
5773 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
5774 {
5775 if (strcmp (s2, "mflo") == 0)
5776 move_register (dreg, sreg);
5777 else
5778 move_register (dreg, ZERO);
5779 break;
5780 }
5781 if (imm_expr.X_op == O_constant
5782 && imm_expr.X_add_number == -1
5783 && s[strlen (s) - 1] != 'u')
5784 {
5785 if (strcmp (s2, "mflo") == 0)
5786 {
5787 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
5788 }
5789 else
5790 move_register (dreg, ZERO);
5791 break;
5792 }
5793
5794 used_at = 1;
5795 load_register (AT, &imm_expr, dbl);
5796 macro_build (NULL, s, "z,s,t", sreg, AT);
5797 macro_build (NULL, s2, "d", dreg);
5798 break;
5799
5800 case M_DIVU_3:
5801 s = "divu";
5802 s2 = "mflo";
5803 goto do_divu3;
5804 case M_REMU_3:
5805 s = "divu";
5806 s2 = "mfhi";
5807 goto do_divu3;
5808 case M_DDIVU_3:
5809 s = "ddivu";
5810 s2 = "mflo";
5811 goto do_divu3;
5812 case M_DREMU_3:
5813 s = "ddivu";
5814 s2 = "mfhi";
5815 do_divu3:
5816 start_noreorder ();
5817 if (mips_trap)
5818 {
5819 macro_build (NULL, "teq", "s,t,q", treg, ZERO, 7);
5820 macro_build (NULL, s, "z,s,t", sreg, treg);
5821 /* We want to close the noreorder block as soon as possible, so
5822 that later insns are available for delay slot filling. */
5823 end_noreorder ();
5824 }
5825 else
5826 {
5827 expr1.X_add_number = 8;
5828 macro_build (&expr1, "bne", "s,t,p", treg, ZERO);
5829 macro_build (NULL, s, "z,s,t", sreg, treg);
5830
5831 /* We want to close the noreorder block as soon as possible, so
5832 that later insns are available for delay slot filling. */
5833 end_noreorder ();
5834 macro_build (NULL, "break", "c", 7);
5835 }
5836 macro_build (NULL, s2, "d", dreg);
5837 break;
5838
5839 case M_DLCA_AB:
5840 dbl = 1;
5841 case M_LCA_AB:
5842 call = 1;
5843 goto do_la;
5844 case M_DLA_AB:
5845 dbl = 1;
5846 case M_LA_AB:
5847 do_la:
5848 /* Load the address of a symbol into a register. If breg is not
5849 zero, we then add a base register to it. */
5850
5851 if (dbl && HAVE_32BIT_GPRS)
5852 as_warn (_("dla used to load 32-bit register"));
5853
5854 if (!dbl && HAVE_64BIT_OBJECTS)
5855 as_warn (_("la used to load 64-bit address"));
5856
5857 if (offset_expr.X_op == O_constant
5858 && offset_expr.X_add_number >= -0x8000
5859 && offset_expr.X_add_number < 0x8000)
5860 {
5861 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
5862 "t,r,j", treg, sreg, BFD_RELOC_LO16);
5863 break;
5864 }
5865
5866 if (mips_opts.at && (treg == breg))
5867 {
5868 tempreg = AT;
5869 used_at = 1;
5870 }
5871 else
5872 {
5873 tempreg = treg;
5874 }
5875
5876 if (offset_expr.X_op != O_symbol
5877 && offset_expr.X_op != O_constant)
5878 {
5879 as_bad (_("Expression too complex"));
5880 offset_expr.X_op = O_constant;
5881 }
5882
5883 if (offset_expr.X_op == O_constant)
5884 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
5885 else if (mips_pic == NO_PIC)
5886 {
5887 /* If this is a reference to a GP relative symbol, we want
5888 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5889 Otherwise we want
5890 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5891 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5892 If we have a constant, we need two instructions anyhow,
5893 so we may as well always use the latter form.
5894
5895 With 64bit address space and a usable $at we want
5896 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5897 lui $at,<sym> (BFD_RELOC_HI16_S)
5898 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5899 daddiu $at,<sym> (BFD_RELOC_LO16)
5900 dsll32 $tempreg,0
5901 daddu $tempreg,$tempreg,$at
5902
5903 If $at is already in use, we use a path which is suboptimal
5904 on superscalar processors.
5905 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5906 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5907 dsll $tempreg,16
5908 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5909 dsll $tempreg,16
5910 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5911
5912 For GP relative symbols in 64bit address space we can use
5913 the same sequence as in 32bit address space. */
5914 if (HAVE_64BIT_SYMBOLS)
5915 {
5916 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5917 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5918 {
5919 relax_start (offset_expr.X_add_symbol);
5920 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5921 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5922 relax_switch ();
5923 }
5924
5925 if (used_at == 0 && mips_opts.at)
5926 {
5927 macro_build (&offset_expr, "lui", "t,u",
5928 tempreg, BFD_RELOC_MIPS_HIGHEST);
5929 macro_build (&offset_expr, "lui", "t,u",
5930 AT, BFD_RELOC_HI16_S);
5931 macro_build (&offset_expr, "daddiu", "t,r,j",
5932 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5933 macro_build (&offset_expr, "daddiu", "t,r,j",
5934 AT, AT, BFD_RELOC_LO16);
5935 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
5936 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
5937 used_at = 1;
5938 }
5939 else
5940 {
5941 macro_build (&offset_expr, "lui", "t,u",
5942 tempreg, BFD_RELOC_MIPS_HIGHEST);
5943 macro_build (&offset_expr, "daddiu", "t,r,j",
5944 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5945 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5946 macro_build (&offset_expr, "daddiu", "t,r,j",
5947 tempreg, tempreg, BFD_RELOC_HI16_S);
5948 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5949 macro_build (&offset_expr, "daddiu", "t,r,j",
5950 tempreg, tempreg, BFD_RELOC_LO16);
5951 }
5952
5953 if (mips_relax.sequence)
5954 relax_end ();
5955 }
5956 else
5957 {
5958 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5959 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5960 {
5961 relax_start (offset_expr.X_add_symbol);
5962 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5963 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5964 relax_switch ();
5965 }
5966 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5967 as_bad (_("Offset too large"));
5968 macro_build_lui (&offset_expr, tempreg);
5969 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5970 tempreg, tempreg, BFD_RELOC_LO16);
5971 if (mips_relax.sequence)
5972 relax_end ();
5973 }
5974 }
5975 else if (!mips_big_got && !HAVE_NEWABI)
5976 {
5977 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5978
5979 /* If this is a reference to an external symbol, and there
5980 is no constant, we want
5981 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5982 or for lca or if tempreg is PIC_CALL_REG
5983 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5984 For a local symbol, we want
5985 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5986 nop
5987 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5988
5989 If we have a small constant, and this is a reference to
5990 an external symbol, we want
5991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5992 nop
5993 addiu $tempreg,$tempreg,<constant>
5994 For a local symbol, we want the same instruction
5995 sequence, but we output a BFD_RELOC_LO16 reloc on the
5996 addiu instruction.
5997
5998 If we have a large constant, and this is a reference to
5999 an external symbol, we want
6000 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6001 lui $at,<hiconstant>
6002 addiu $at,$at,<loconstant>
6003 addu $tempreg,$tempreg,$at
6004 For a local symbol, we want the same instruction
6005 sequence, but we output a BFD_RELOC_LO16 reloc on the
6006 addiu instruction.
6007 */
6008
6009 if (offset_expr.X_add_number == 0)
6010 {
6011 if (mips_pic == SVR4_PIC
6012 && breg == 0
6013 && (call || tempreg == PIC_CALL_REG))
6014 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
6015
6016 relax_start (offset_expr.X_add_symbol);
6017 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6018 lw_reloc_type, mips_gp_register);
6019 if (breg != 0)
6020 {
6021 /* We're going to put in an addu instruction using
6022 tempreg, so we may as well insert the nop right
6023 now. */
6024 load_delay_nop ();
6025 }
6026 relax_switch ();
6027 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6028 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
6029 load_delay_nop ();
6030 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6031 tempreg, tempreg, BFD_RELOC_LO16);
6032 relax_end ();
6033 /* FIXME: If breg == 0, and the next instruction uses
6034 $tempreg, then if this variant case is used an extra
6035 nop will be generated. */
6036 }
6037 else if (offset_expr.X_add_number >= -0x8000
6038 && offset_expr.X_add_number < 0x8000)
6039 {
6040 load_got_offset (tempreg, &offset_expr);
6041 load_delay_nop ();
6042 add_got_offset (tempreg, &offset_expr);
6043 }
6044 else
6045 {
6046 expr1.X_add_number = offset_expr.X_add_number;
6047 offset_expr.X_add_number =
6048 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
6049 load_got_offset (tempreg, &offset_expr);
6050 offset_expr.X_add_number = expr1.X_add_number;
6051 /* If we are going to add in a base register, and the
6052 target register and the base register are the same,
6053 then we are using AT as a temporary register. Since
6054 we want to load the constant into AT, we add our
6055 current AT (from the global offset table) and the
6056 register into the register now, and pretend we were
6057 not using a base register. */
6058 if (breg == treg)
6059 {
6060 load_delay_nop ();
6061 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6062 treg, AT, breg);
6063 breg = 0;
6064 tempreg = treg;
6065 }
6066 add_got_offset_hilo (tempreg, &offset_expr, AT);
6067 used_at = 1;
6068 }
6069 }
6070 else if (!mips_big_got && HAVE_NEWABI)
6071 {
6072 int add_breg_early = 0;
6073
6074 /* If this is a reference to an external, and there is no
6075 constant, or local symbol (*), with or without a
6076 constant, we want
6077 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6078 or for lca or if tempreg is PIC_CALL_REG
6079 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6080
6081 If we have a small constant, and this is a reference to
6082 an external symbol, we want
6083 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6084 addiu $tempreg,$tempreg,<constant>
6085
6086 If we have a large constant, and this is a reference to
6087 an external symbol, we want
6088 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
6089 lui $at,<hiconstant>
6090 addiu $at,$at,<loconstant>
6091 addu $tempreg,$tempreg,$at
6092
6093 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
6094 local symbols, even though it introduces an additional
6095 instruction. */
6096
6097 if (offset_expr.X_add_number)
6098 {
6099 expr1.X_add_number = offset_expr.X_add_number;
6100 offset_expr.X_add_number = 0;
6101
6102 relax_start (offset_expr.X_add_symbol);
6103 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6104 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6105
6106 if (expr1.X_add_number >= -0x8000
6107 && expr1.X_add_number < 0x8000)
6108 {
6109 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6110 tempreg, tempreg, BFD_RELOC_LO16);
6111 }
6112 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6113 {
6114 /* If we are going to add in a base register, and the
6115 target register and the base register are the same,
6116 then we are using AT as a temporary register. Since
6117 we want to load the constant into AT, we add our
6118 current AT (from the global offset table) and the
6119 register into the register now, and pretend we were
6120 not using a base register. */
6121 if (breg != treg)
6122 dreg = tempreg;
6123 else
6124 {
6125 gas_assert (tempreg == AT);
6126 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6127 treg, AT, breg);
6128 dreg = treg;
6129 add_breg_early = 1;
6130 }
6131
6132 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6133 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6134 dreg, dreg, AT);
6135
6136 used_at = 1;
6137 }
6138 else
6139 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6140
6141 relax_switch ();
6142 offset_expr.X_add_number = expr1.X_add_number;
6143
6144 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6145 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6146 if (add_breg_early)
6147 {
6148 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6149 treg, tempreg, breg);
6150 breg = 0;
6151 tempreg = treg;
6152 }
6153 relax_end ();
6154 }
6155 else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
6156 {
6157 relax_start (offset_expr.X_add_symbol);
6158 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6159 BFD_RELOC_MIPS_CALL16, mips_gp_register);
6160 relax_switch ();
6161 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6162 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6163 relax_end ();
6164 }
6165 else
6166 {
6167 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6168 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
6169 }
6170 }
6171 else if (mips_big_got && !HAVE_NEWABI)
6172 {
6173 int gpdelay;
6174 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6175 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6176 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6177
6178 /* This is the large GOT case. If this is a reference to an
6179 external symbol, and there is no constant, we want
6180 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6181 addu $tempreg,$tempreg,$gp
6182 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6183 or for lca or if tempreg is PIC_CALL_REG
6184 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6185 addu $tempreg,$tempreg,$gp
6186 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6187 For a local symbol, we want
6188 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6189 nop
6190 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6191
6192 If we have a small constant, and this is a reference to
6193 an external symbol, we want
6194 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6195 addu $tempreg,$tempreg,$gp
6196 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6197 nop
6198 addiu $tempreg,$tempreg,<constant>
6199 For a local symbol, we want
6200 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6201 nop
6202 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
6203
6204 If we have a large constant, and this is a reference to
6205 an external symbol, we want
6206 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6207 addu $tempreg,$tempreg,$gp
6208 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6209 lui $at,<hiconstant>
6210 addiu $at,$at,<loconstant>
6211 addu $tempreg,$tempreg,$at
6212 For a local symbol, we want
6213 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6214 lui $at,<hiconstant>
6215 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
6216 addu $tempreg,$tempreg,$at
6217 */
6218
6219 expr1.X_add_number = offset_expr.X_add_number;
6220 offset_expr.X_add_number = 0;
6221 relax_start (offset_expr.X_add_symbol);
6222 gpdelay = reg_needs_delay (mips_gp_register);
6223 if (expr1.X_add_number == 0 && breg == 0
6224 && (call || tempreg == PIC_CALL_REG))
6225 {
6226 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6227 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6228 }
6229 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6230 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6231 tempreg, tempreg, mips_gp_register);
6232 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6233 tempreg, lw_reloc_type, tempreg);
6234 if (expr1.X_add_number == 0)
6235 {
6236 if (breg != 0)
6237 {
6238 /* We're going to put in an addu instruction using
6239 tempreg, so we may as well insert the nop right
6240 now. */
6241 load_delay_nop ();
6242 }
6243 }
6244 else if (expr1.X_add_number >= -0x8000
6245 && expr1.X_add_number < 0x8000)
6246 {
6247 load_delay_nop ();
6248 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6249 tempreg, tempreg, BFD_RELOC_LO16);
6250 }
6251 else
6252 {
6253 /* If we are going to add in a base register, and the
6254 target register and the base register are the same,
6255 then we are using AT as a temporary register. Since
6256 we want to load the constant into AT, we add our
6257 current AT (from the global offset table) and the
6258 register into the register now, and pretend we were
6259 not using a base register. */
6260 if (breg != treg)
6261 dreg = tempreg;
6262 else
6263 {
6264 gas_assert (tempreg == AT);
6265 load_delay_nop ();
6266 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6267 treg, AT, breg);
6268 dreg = treg;
6269 }
6270
6271 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6272 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6273
6274 used_at = 1;
6275 }
6276 offset_expr.X_add_number =
6277 ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
6278 relax_switch ();
6279
6280 if (gpdelay)
6281 {
6282 /* This is needed because this instruction uses $gp, but
6283 the first instruction on the main stream does not. */
6284 macro_build (NULL, "nop", "");
6285 }
6286
6287 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6288 local_reloc_type, mips_gp_register);
6289 if (expr1.X_add_number >= -0x8000
6290 && expr1.X_add_number < 0x8000)
6291 {
6292 load_delay_nop ();
6293 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6294 tempreg, tempreg, BFD_RELOC_LO16);
6295 /* FIXME: If add_number is 0, and there was no base
6296 register, the external symbol case ended with a load,
6297 so if the symbol turns out to not be external, and
6298 the next instruction uses tempreg, an unnecessary nop
6299 will be inserted. */
6300 }
6301 else
6302 {
6303 if (breg == treg)
6304 {
6305 /* We must add in the base register now, as in the
6306 external symbol case. */
6307 gas_assert (tempreg == AT);
6308 load_delay_nop ();
6309 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6310 treg, AT, breg);
6311 tempreg = treg;
6312 /* We set breg to 0 because we have arranged to add
6313 it in in both cases. */
6314 breg = 0;
6315 }
6316
6317 macro_build_lui (&expr1, AT);
6318 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6319 AT, AT, BFD_RELOC_LO16);
6320 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6321 tempreg, tempreg, AT);
6322 used_at = 1;
6323 }
6324 relax_end ();
6325 }
6326 else if (mips_big_got && HAVE_NEWABI)
6327 {
6328 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
6329 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
6330 int add_breg_early = 0;
6331
6332 /* This is the large GOT case. If this is a reference to an
6333 external symbol, and there is no constant, we want
6334 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6335 add $tempreg,$tempreg,$gp
6336 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6337 or for lca or if tempreg is PIC_CALL_REG
6338 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6339 add $tempreg,$tempreg,$gp
6340 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
6341
6342 If we have a small constant, and this is a reference to
6343 an external symbol, we want
6344 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6345 add $tempreg,$tempreg,$gp
6346 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6347 addi $tempreg,$tempreg,<constant>
6348
6349 If we have a large constant, and this is a reference to
6350 an external symbol, we want
6351 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6352 addu $tempreg,$tempreg,$gp
6353 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6354 lui $at,<hiconstant>
6355 addi $at,$at,<loconstant>
6356 add $tempreg,$tempreg,$at
6357
6358 If we have NewABI, and we know it's a local symbol, we want
6359 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6360 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
6361 otherwise we have to resort to GOT_HI16/GOT_LO16. */
6362
6363 relax_start (offset_expr.X_add_symbol);
6364
6365 expr1.X_add_number = offset_expr.X_add_number;
6366 offset_expr.X_add_number = 0;
6367
6368 if (expr1.X_add_number == 0 && breg == 0
6369 && (call || tempreg == PIC_CALL_REG))
6370 {
6371 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
6372 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
6373 }
6374 macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
6375 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6376 tempreg, tempreg, mips_gp_register);
6377 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6378 tempreg, lw_reloc_type, tempreg);
6379
6380 if (expr1.X_add_number == 0)
6381 ;
6382 else if (expr1.X_add_number >= -0x8000
6383 && expr1.X_add_number < 0x8000)
6384 {
6385 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
6386 tempreg, tempreg, BFD_RELOC_LO16);
6387 }
6388 else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
6389 {
6390 /* If we are going to add in a base register, and the
6391 target register and the base register are the same,
6392 then we are using AT as a temporary register. Since
6393 we want to load the constant into AT, we add our
6394 current AT (from the global offset table) and the
6395 register into the register now, and pretend we were
6396 not using a base register. */
6397 if (breg != treg)
6398 dreg = tempreg;
6399 else
6400 {
6401 gas_assert (tempreg == AT);
6402 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6403 treg, AT, breg);
6404 dreg = treg;
6405 add_breg_early = 1;
6406 }
6407
6408 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
6409 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
6410
6411 used_at = 1;
6412 }
6413 else
6414 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6415
6416 relax_switch ();
6417 offset_expr.X_add_number = expr1.X_add_number;
6418 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6419 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6420 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6421 tempreg, BFD_RELOC_MIPS_GOT_OFST);
6422 if (add_breg_early)
6423 {
6424 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6425 treg, tempreg, breg);
6426 breg = 0;
6427 tempreg = treg;
6428 }
6429 relax_end ();
6430 }
6431 else
6432 abort ();
6433
6434 if (breg != 0)
6435 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
6436 break;
6437
6438 case M_MSGSND:
6439 {
6440 unsigned long temp = (treg << 16) | (0x01);
6441 macro_build (NULL, "c2", "C", temp);
6442 }
6443 break;
6444
6445 case M_MSGLD:
6446 {
6447 unsigned long temp = (0x02);
6448 macro_build (NULL, "c2", "C", temp);
6449 }
6450 break;
6451
6452 case M_MSGLD_T:
6453 {
6454 unsigned long temp = (treg << 16) | (0x02);
6455 macro_build (NULL, "c2", "C", temp);
6456 }
6457 break;
6458
6459 case M_MSGWAIT:
6460 macro_build (NULL, "c2", "C", 3);
6461 break;
6462
6463 case M_MSGWAIT_T:
6464 {
6465 unsigned long temp = (treg << 16) | 0x03;
6466 macro_build (NULL, "c2", "C", temp);
6467 }
6468 break;
6469
6470 case M_J_A:
6471 /* The j instruction may not be used in PIC code, since it
6472 requires an absolute address. We convert it to a b
6473 instruction. */
6474 if (mips_pic == NO_PIC)
6475 macro_build (&offset_expr, "j", "a");
6476 else
6477 macro_build (&offset_expr, "b", "p");
6478 break;
6479
6480 /* The jal instructions must be handled as macros because when
6481 generating PIC code they expand to multi-instruction
6482 sequences. Normally they are simple instructions. */
6483 case M_JAL_1:
6484 dreg = RA;
6485 /* Fall through. */
6486 case M_JAL_2:
6487 if (mips_pic == NO_PIC)
6488 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6489 else
6490 {
6491 if (sreg != PIC_CALL_REG)
6492 as_warn (_("MIPS PIC call to register other than $25"));
6493
6494 macro_build (NULL, "jalr", "d,s", dreg, sreg);
6495 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
6496 {
6497 if (mips_cprestore_offset < 0)
6498 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6499 else
6500 {
6501 if (!mips_frame_reg_valid)
6502 {
6503 as_warn (_("No .frame pseudo-op used in PIC code"));
6504 /* Quiet this warning. */
6505 mips_frame_reg_valid = 1;
6506 }
6507 if (!mips_cprestore_valid)
6508 {
6509 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6510 /* Quiet this warning. */
6511 mips_cprestore_valid = 1;
6512 }
6513 if (mips_opts.noreorder)
6514 macro_build (NULL, "nop", "");
6515 expr1.X_add_number = mips_cprestore_offset;
6516 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6517 mips_gp_register,
6518 mips_frame_reg,
6519 HAVE_64BIT_ADDRESSES);
6520 }
6521 }
6522 }
6523
6524 break;
6525
6526 case M_JAL_A:
6527 if (mips_pic == NO_PIC)
6528 macro_build (&offset_expr, "jal", "a");
6529 else if (mips_pic == SVR4_PIC)
6530 {
6531 /* If this is a reference to an external symbol, and we are
6532 using a small GOT, we want
6533 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6534 nop
6535 jalr $ra,$25
6536 nop
6537 lw $gp,cprestore($sp)
6538 The cprestore value is set using the .cprestore
6539 pseudo-op. If we are using a big GOT, we want
6540 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6541 addu $25,$25,$gp
6542 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6543 nop
6544 jalr $ra,$25
6545 nop
6546 lw $gp,cprestore($sp)
6547 If the symbol is not external, we want
6548 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6549 nop
6550 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6551 jalr $ra,$25
6552 nop
6553 lw $gp,cprestore($sp)
6554
6555 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6556 sequences above, minus nops, unless the symbol is local,
6557 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6558 GOT_DISP. */
6559 if (HAVE_NEWABI)
6560 {
6561 if (!mips_big_got)
6562 {
6563 relax_start (offset_expr.X_add_symbol);
6564 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6565 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6566 mips_gp_register);
6567 relax_switch ();
6568 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6569 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
6570 mips_gp_register);
6571 relax_end ();
6572 }
6573 else
6574 {
6575 relax_start (offset_expr.X_add_symbol);
6576 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6577 BFD_RELOC_MIPS_CALL_HI16);
6578 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6579 PIC_CALL_REG, mips_gp_register);
6580 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6581 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6582 PIC_CALL_REG);
6583 relax_switch ();
6584 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6585 PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
6586 mips_gp_register);
6587 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6588 PIC_CALL_REG, PIC_CALL_REG,
6589 BFD_RELOC_MIPS_GOT_OFST);
6590 relax_end ();
6591 }
6592
6593 macro_build_jalr (&offset_expr);
6594 }
6595 else
6596 {
6597 relax_start (offset_expr.X_add_symbol);
6598 if (!mips_big_got)
6599 {
6600 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6601 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
6602 mips_gp_register);
6603 load_delay_nop ();
6604 relax_switch ();
6605 }
6606 else
6607 {
6608 int gpdelay;
6609
6610 gpdelay = reg_needs_delay (mips_gp_register);
6611 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
6612 BFD_RELOC_MIPS_CALL_HI16);
6613 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
6614 PIC_CALL_REG, mips_gp_register);
6615 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6616 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
6617 PIC_CALL_REG);
6618 load_delay_nop ();
6619 relax_switch ();
6620 if (gpdelay)
6621 macro_build (NULL, "nop", "");
6622 }
6623 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6624 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
6625 mips_gp_register);
6626 load_delay_nop ();
6627 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
6628 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
6629 relax_end ();
6630 macro_build_jalr (&offset_expr);
6631
6632 if (mips_cprestore_offset < 0)
6633 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6634 else
6635 {
6636 if (!mips_frame_reg_valid)
6637 {
6638 as_warn (_("No .frame pseudo-op used in PIC code"));
6639 /* Quiet this warning. */
6640 mips_frame_reg_valid = 1;
6641 }
6642 if (!mips_cprestore_valid)
6643 {
6644 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6645 /* Quiet this warning. */
6646 mips_cprestore_valid = 1;
6647 }
6648 if (mips_opts.noreorder)
6649 macro_build (NULL, "nop", "");
6650 expr1.X_add_number = mips_cprestore_offset;
6651 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6652 mips_gp_register,
6653 mips_frame_reg,
6654 HAVE_64BIT_ADDRESSES);
6655 }
6656 }
6657 }
6658 else if (mips_pic == VXWORKS_PIC)
6659 as_bad (_("Non-PIC jump used in PIC library"));
6660 else
6661 abort ();
6662
6663 break;
6664
6665 case M_LB_AB:
6666 s = "lb";
6667 goto ld;
6668 case M_LBU_AB:
6669 s = "lbu";
6670 goto ld;
6671 case M_LH_AB:
6672 s = "lh";
6673 goto ld;
6674 case M_LHU_AB:
6675 s = "lhu";
6676 goto ld;
6677 case M_LW_AB:
6678 s = "lw";
6679 goto ld;
6680 case M_LWC0_AB:
6681 s = "lwc0";
6682 /* Itbl support may require additional care here. */
6683 coproc = 1;
6684 goto ld;
6685 case M_LWC1_AB:
6686 s = "lwc1";
6687 /* Itbl support may require additional care here. */
6688 coproc = 1;
6689 goto ld;
6690 case M_LWC2_AB:
6691 s = "lwc2";
6692 /* Itbl support may require additional care here. */
6693 coproc = 1;
6694 goto ld;
6695 case M_LWC3_AB:
6696 s = "lwc3";
6697 /* Itbl support may require additional care here. */
6698 coproc = 1;
6699 goto ld;
6700 case M_LWL_AB:
6701 s = "lwl";
6702 lr = 1;
6703 goto ld;
6704 case M_LWR_AB:
6705 s = "lwr";
6706 lr = 1;
6707 goto ld;
6708 case M_LDC1_AB:
6709 s = "ldc1";
6710 /* Itbl support may require additional care here. */
6711 coproc = 1;
6712 goto ld;
6713 case M_LDC2_AB:
6714 s = "ldc2";
6715 /* Itbl support may require additional care here. */
6716 coproc = 1;
6717 goto ld;
6718 case M_LDC3_AB:
6719 s = "ldc3";
6720 /* Itbl support may require additional care here. */
6721 coproc = 1;
6722 goto ld;
6723 case M_LDL_AB:
6724 s = "ldl";
6725 lr = 1;
6726 goto ld;
6727 case M_LDR_AB:
6728 s = "ldr";
6729 lr = 1;
6730 goto ld;
6731 case M_LL_AB:
6732 s = "ll";
6733 goto ld;
6734 case M_LLD_AB:
6735 s = "lld";
6736 goto ld;
6737 case M_LWU_AB:
6738 s = "lwu";
6739 ld:
6740 if (breg == treg || coproc || lr)
6741 {
6742 tempreg = AT;
6743 used_at = 1;
6744 }
6745 else
6746 {
6747 tempreg = treg;
6748 }
6749 goto ld_st;
6750 case M_SB_AB:
6751 s = "sb";
6752 goto st;
6753 case M_SH_AB:
6754 s = "sh";
6755 goto st;
6756 case M_SW_AB:
6757 s = "sw";
6758 goto st;
6759 case M_SWC0_AB:
6760 s = "swc0";
6761 /* Itbl support may require additional care here. */
6762 coproc = 1;
6763 goto st;
6764 case M_SWC1_AB:
6765 s = "swc1";
6766 /* Itbl support may require additional care here. */
6767 coproc = 1;
6768 goto st;
6769 case M_SWC2_AB:
6770 s = "swc2";
6771 /* Itbl support may require additional care here. */
6772 coproc = 1;
6773 goto st;
6774 case M_SWC3_AB:
6775 s = "swc3";
6776 /* Itbl support may require additional care here. */
6777 coproc = 1;
6778 goto st;
6779 case M_SWL_AB:
6780 s = "swl";
6781 goto st;
6782 case M_SWR_AB:
6783 s = "swr";
6784 goto st;
6785 case M_SC_AB:
6786 s = "sc";
6787 goto st;
6788 case M_SCD_AB:
6789 s = "scd";
6790 goto st;
6791 case M_CACHE_AB:
6792 s = "cache";
6793 goto st;
6794 case M_PREF_AB:
6795 s = "pref";
6796 goto st;
6797 case M_SDC1_AB:
6798 s = "sdc1";
6799 coproc = 1;
6800 /* Itbl support may require additional care here. */
6801 goto st;
6802 case M_SDC2_AB:
6803 s = "sdc2";
6804 /* Itbl support may require additional care here. */
6805 coproc = 1;
6806 goto st;
6807 case M_SDC3_AB:
6808 s = "sdc3";
6809 /* Itbl support may require additional care here. */
6810 coproc = 1;
6811 goto st;
6812 case M_SDL_AB:
6813 s = "sdl";
6814 goto st;
6815 case M_SDR_AB:
6816 s = "sdr";
6817 st:
6818 tempreg = AT;
6819 used_at = 1;
6820 ld_st:
6821 if (coproc
6822 && NO_ISA_COP (mips_opts.arch)
6823 && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
6824 {
6825 as_bad (_("Opcode not supported on this processor: %s"),
6826 mips_cpu_info_from_arch (mips_opts.arch)->name);
6827 break;
6828 }
6829
6830 /* Itbl support may require additional care here. */
6831 if (mask == M_LWC1_AB
6832 || mask == M_SWC1_AB
6833 || mask == M_LDC1_AB
6834 || mask == M_SDC1_AB
6835 || mask == M_L_DAB
6836 || mask == M_S_DAB)
6837 fmt = "T,o(b)";
6838 else if (mask == M_CACHE_AB || mask == M_PREF_AB)
6839 fmt = "k,o(b)";
6840 else if (coproc)
6841 fmt = "E,o(b)";
6842 else
6843 fmt = "t,o(b)";
6844
6845 if (offset_expr.X_op != O_constant
6846 && offset_expr.X_op != O_symbol)
6847 {
6848 as_bad (_("Expression too complex"));
6849 offset_expr.X_op = O_constant;
6850 }
6851
6852 if (HAVE_32BIT_ADDRESSES
6853 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6854 {
6855 char value [32];
6856
6857 sprintf_vma (value, offset_expr.X_add_number);
6858 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6859 }
6860
6861 /* A constant expression in PIC code can be handled just as it
6862 is in non PIC code. */
6863 if (offset_expr.X_op == O_constant)
6864 {
6865 expr1.X_add_number = offset_expr.X_add_number;
6866 normalize_address_expr (&expr1);
6867 if (!IS_SEXT_16BIT_NUM (expr1.X_add_number))
6868 {
6869 expr1.X_add_number = ((expr1.X_add_number + 0x8000)
6870 & ~(bfd_vma) 0xffff);
6871 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
6872 if (breg != 0)
6873 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6874 tempreg, tempreg, breg);
6875 breg = tempreg;
6876 }
6877 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
6878 }
6879 else if (mips_pic == NO_PIC)
6880 {
6881 /* If this is a reference to a GP relative symbol, and there
6882 is no base register, we want
6883 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6884 Otherwise, if there is no base register, we want
6885 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6886 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6887 If we have a constant, we need two instructions anyhow,
6888 so we always use the latter form.
6889
6890 If we have a base register, and this is a reference to a
6891 GP relative symbol, we want
6892 addu $tempreg,$breg,$gp
6893 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6894 Otherwise we want
6895 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6896 addu $tempreg,$tempreg,$breg
6897 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6898 With a constant we always use the latter case.
6899
6900 With 64bit address space and no base register and $at usable,
6901 we want
6902 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6903 lui $at,<sym> (BFD_RELOC_HI16_S)
6904 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6905 dsll32 $tempreg,0
6906 daddu $tempreg,$at
6907 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6908 If we have a base register, we want
6909 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6910 lui $at,<sym> (BFD_RELOC_HI16_S)
6911 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6912 daddu $at,$breg
6913 dsll32 $tempreg,0
6914 daddu $tempreg,$at
6915 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6916
6917 Without $at we can't generate the optimal path for superscalar
6918 processors here since this would require two temporary registers.
6919 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6920 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6921 dsll $tempreg,16
6922 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6923 dsll $tempreg,16
6924 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6925 If we have a base register, we want
6926 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6927 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6928 dsll $tempreg,16
6929 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6930 dsll $tempreg,16
6931 daddu $tempreg,$tempreg,$breg
6932 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6933
6934 For GP relative symbols in 64bit address space we can use
6935 the same sequence as in 32bit address space. */
6936 if (HAVE_64BIT_SYMBOLS)
6937 {
6938 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6939 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6940 {
6941 relax_start (offset_expr.X_add_symbol);
6942 if (breg == 0)
6943 {
6944 macro_build (&offset_expr, s, fmt, treg,
6945 BFD_RELOC_GPREL16, mips_gp_register);
6946 }
6947 else
6948 {
6949 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6950 tempreg, breg, mips_gp_register);
6951 macro_build (&offset_expr, s, fmt, treg,
6952 BFD_RELOC_GPREL16, tempreg);
6953 }
6954 relax_switch ();
6955 }
6956
6957 if (used_at == 0 && mips_opts.at)
6958 {
6959 macro_build (&offset_expr, "lui", "t,u", tempreg,
6960 BFD_RELOC_MIPS_HIGHEST);
6961 macro_build (&offset_expr, "lui", "t,u", AT,
6962 BFD_RELOC_HI16_S);
6963 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6964 tempreg, BFD_RELOC_MIPS_HIGHER);
6965 if (breg != 0)
6966 macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
6967 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
6968 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
6969 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
6970 tempreg);
6971 used_at = 1;
6972 }
6973 else
6974 {
6975 macro_build (&offset_expr, "lui", "t,u", tempreg,
6976 BFD_RELOC_MIPS_HIGHEST);
6977 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6978 tempreg, BFD_RELOC_MIPS_HIGHER);
6979 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6980 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6981 tempreg, BFD_RELOC_HI16_S);
6982 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6983 if (breg != 0)
6984 macro_build (NULL, "daddu", "d,v,t",
6985 tempreg, tempreg, breg);
6986 macro_build (&offset_expr, s, fmt, treg,
6987 BFD_RELOC_LO16, tempreg);
6988 }
6989
6990 if (mips_relax.sequence)
6991 relax_end ();
6992 break;
6993 }
6994
6995 if (breg == 0)
6996 {
6997 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6998 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6999 {
7000 relax_start (offset_expr.X_add_symbol);
7001 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
7002 mips_gp_register);
7003 relax_switch ();
7004 }
7005 macro_build_lui (&offset_expr, tempreg);
7006 macro_build (&offset_expr, s, fmt, treg,
7007 BFD_RELOC_LO16, tempreg);
7008 if (mips_relax.sequence)
7009 relax_end ();
7010 }
7011 else
7012 {
7013 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7014 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7015 {
7016 relax_start (offset_expr.X_add_symbol);
7017 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7018 tempreg, breg, mips_gp_register);
7019 macro_build (&offset_expr, s, fmt, treg,
7020 BFD_RELOC_GPREL16, tempreg);
7021 relax_switch ();
7022 }
7023 macro_build_lui (&offset_expr, tempreg);
7024 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7025 tempreg, tempreg, breg);
7026 macro_build (&offset_expr, s, fmt, treg,
7027 BFD_RELOC_LO16, tempreg);
7028 if (mips_relax.sequence)
7029 relax_end ();
7030 }
7031 }
7032 else if (!mips_big_got)
7033 {
7034 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
7035
7036 /* If this is a reference to an external symbol, we want
7037 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7038 nop
7039 <op> $treg,0($tempreg)
7040 Otherwise we want
7041 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7042 nop
7043 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7044 <op> $treg,0($tempreg)
7045
7046 For NewABI, we want
7047 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7048 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
7049
7050 If there is a base register, we add it to $tempreg before
7051 the <op>. If there is a constant, we stick it in the
7052 <op> instruction. We don't handle constants larger than
7053 16 bits, because we have no way to load the upper 16 bits
7054 (actually, we could handle them for the subset of cases
7055 in which we are not using $at). */
7056 gas_assert (offset_expr.X_op == O_symbol);
7057 if (HAVE_NEWABI)
7058 {
7059 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7060 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7061 if (breg != 0)
7062 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7063 tempreg, tempreg, breg);
7064 macro_build (&offset_expr, s, fmt, treg,
7065 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7066 break;
7067 }
7068 expr1.X_add_number = offset_expr.X_add_number;
7069 offset_expr.X_add_number = 0;
7070 if (expr1.X_add_number < -0x8000
7071 || expr1.X_add_number >= 0x8000)
7072 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7073 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7074 lw_reloc_type, mips_gp_register);
7075 load_delay_nop ();
7076 relax_start (offset_expr.X_add_symbol);
7077 relax_switch ();
7078 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7079 tempreg, BFD_RELOC_LO16);
7080 relax_end ();
7081 if (breg != 0)
7082 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7083 tempreg, tempreg, breg);
7084 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7085 }
7086 else if (mips_big_got && !HAVE_NEWABI)
7087 {
7088 int gpdelay;
7089
7090 /* If this is a reference to an external symbol, we want
7091 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7092 addu $tempreg,$tempreg,$gp
7093 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7094 <op> $treg,0($tempreg)
7095 Otherwise we want
7096 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7097 nop
7098 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
7099 <op> $treg,0($tempreg)
7100 If there is a base register, we add it to $tempreg before
7101 the <op>. If there is a constant, we stick it in the
7102 <op> instruction. We don't handle constants larger than
7103 16 bits, because we have no way to load the upper 16 bits
7104 (actually, we could handle them for the subset of cases
7105 in which we are not using $at). */
7106 gas_assert (offset_expr.X_op == O_symbol);
7107 expr1.X_add_number = offset_expr.X_add_number;
7108 offset_expr.X_add_number = 0;
7109 if (expr1.X_add_number < -0x8000
7110 || expr1.X_add_number >= 0x8000)
7111 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7112 gpdelay = reg_needs_delay (mips_gp_register);
7113 relax_start (offset_expr.X_add_symbol);
7114 macro_build (&offset_expr, "lui", "t,u", tempreg,
7115 BFD_RELOC_MIPS_GOT_HI16);
7116 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7117 mips_gp_register);
7118 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7119 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7120 relax_switch ();
7121 if (gpdelay)
7122 macro_build (NULL, "nop", "");
7123 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7124 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7125 load_delay_nop ();
7126 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
7127 tempreg, BFD_RELOC_LO16);
7128 relax_end ();
7129
7130 if (breg != 0)
7131 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7132 tempreg, tempreg, breg);
7133 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7134 }
7135 else if (mips_big_got && HAVE_NEWABI)
7136 {
7137 /* If this is a reference to an external symbol, we want
7138 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7139 add $tempreg,$tempreg,$gp
7140 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
7141 <op> $treg,<ofst>($tempreg)
7142 Otherwise, for local symbols, we want:
7143 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
7144 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
7145 gas_assert (offset_expr.X_op == O_symbol);
7146 expr1.X_add_number = offset_expr.X_add_number;
7147 offset_expr.X_add_number = 0;
7148 if (expr1.X_add_number < -0x8000
7149 || expr1.X_add_number >= 0x8000)
7150 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7151 relax_start (offset_expr.X_add_symbol);
7152 macro_build (&offset_expr, "lui", "t,u", tempreg,
7153 BFD_RELOC_MIPS_GOT_HI16);
7154 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
7155 mips_gp_register);
7156 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7157 BFD_RELOC_MIPS_GOT_LO16, tempreg);
7158 if (breg != 0)
7159 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7160 tempreg, tempreg, breg);
7161 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
7162
7163 relax_switch ();
7164 offset_expr.X_add_number = expr1.X_add_number;
7165 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
7166 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
7167 if (breg != 0)
7168 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7169 tempreg, tempreg, breg);
7170 macro_build (&offset_expr, s, fmt, treg,
7171 BFD_RELOC_MIPS_GOT_OFST, tempreg);
7172 relax_end ();
7173 }
7174 else
7175 abort ();
7176
7177 break;
7178
7179 case M_LI:
7180 case M_LI_S:
7181 load_register (treg, &imm_expr, 0);
7182 break;
7183
7184 case M_DLI:
7185 load_register (treg, &imm_expr, 1);
7186 break;
7187
7188 case M_LI_SS:
7189 if (imm_expr.X_op == O_constant)
7190 {
7191 used_at = 1;
7192 load_register (AT, &imm_expr, 0);
7193 macro_build (NULL, "mtc1", "t,G", AT, treg);
7194 break;
7195 }
7196 else
7197 {
7198 gas_assert (offset_expr.X_op == O_symbol
7199 && strcmp (segment_name (S_GET_SEGMENT
7200 (offset_expr.X_add_symbol)),
7201 ".lit4") == 0
7202 && offset_expr.X_add_number == 0);
7203 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
7204 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7205 break;
7206 }
7207
7208 case M_LI_D:
7209 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
7210 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
7211 order 32 bits of the value and the low order 32 bits are either
7212 zero or in OFFSET_EXPR. */
7213 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7214 {
7215 if (HAVE_64BIT_GPRS)
7216 load_register (treg, &imm_expr, 1);
7217 else
7218 {
7219 int hreg, lreg;
7220
7221 if (target_big_endian)
7222 {
7223 hreg = treg;
7224 lreg = treg + 1;
7225 }
7226 else
7227 {
7228 hreg = treg + 1;
7229 lreg = treg;
7230 }
7231
7232 if (hreg <= 31)
7233 load_register (hreg, &imm_expr, 0);
7234 if (lreg <= 31)
7235 {
7236 if (offset_expr.X_op == O_absent)
7237 move_register (lreg, 0);
7238 else
7239 {
7240 gas_assert (offset_expr.X_op == O_constant);
7241 load_register (lreg, &offset_expr, 0);
7242 }
7243 }
7244 }
7245 break;
7246 }
7247
7248 /* We know that sym is in the .rdata section. First we get the
7249 upper 16 bits of the address. */
7250 if (mips_pic == NO_PIC)
7251 {
7252 macro_build_lui (&offset_expr, AT);
7253 used_at = 1;
7254 }
7255 else
7256 {
7257 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7258 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7259 used_at = 1;
7260 }
7261
7262 /* Now we load the register(s). */
7263 if (HAVE_64BIT_GPRS)
7264 {
7265 used_at = 1;
7266 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7267 }
7268 else
7269 {
7270 used_at = 1;
7271 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7272 if (treg != RA)
7273 {
7274 /* FIXME: How in the world do we deal with the possible
7275 overflow here? */
7276 offset_expr.X_add_number += 4;
7277 macro_build (&offset_expr, "lw", "t,o(b)",
7278 treg + 1, BFD_RELOC_LO16, AT);
7279 }
7280 }
7281 break;
7282
7283 case M_LI_DD:
7284 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
7285 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
7286 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
7287 the value and the low order 32 bits are either zero or in
7288 OFFSET_EXPR. */
7289 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
7290 {
7291 used_at = 1;
7292 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
7293 if (HAVE_64BIT_FPRS)
7294 {
7295 gas_assert (HAVE_64BIT_GPRS);
7296 macro_build (NULL, "dmtc1", "t,S", AT, treg);
7297 }
7298 else
7299 {
7300 macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
7301 if (offset_expr.X_op == O_absent)
7302 macro_build (NULL, "mtc1", "t,G", 0, treg);
7303 else
7304 {
7305 gas_assert (offset_expr.X_op == O_constant);
7306 load_register (AT, &offset_expr, 0);
7307 macro_build (NULL, "mtc1", "t,G", AT, treg);
7308 }
7309 }
7310 break;
7311 }
7312
7313 gas_assert (offset_expr.X_op == O_symbol
7314 && offset_expr.X_add_number == 0);
7315 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
7316 if (strcmp (s, ".lit8") == 0)
7317 {
7318 if (mips_opts.isa != ISA_MIPS1)
7319 {
7320 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
7321 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
7322 break;
7323 }
7324 breg = mips_gp_register;
7325 r = BFD_RELOC_MIPS_LITERAL;
7326 goto dob;
7327 }
7328 else
7329 {
7330 gas_assert (strcmp (s, RDATA_SECTION_NAME) == 0);
7331 used_at = 1;
7332 if (mips_pic != NO_PIC)
7333 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7334 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7335 else
7336 {
7337 /* FIXME: This won't work for a 64 bit address. */
7338 macro_build_lui (&offset_expr, AT);
7339 }
7340
7341 if (mips_opts.isa != ISA_MIPS1)
7342 {
7343 macro_build (&offset_expr, "ldc1", "T,o(b)",
7344 treg, BFD_RELOC_LO16, AT);
7345 break;
7346 }
7347 breg = AT;
7348 r = BFD_RELOC_LO16;
7349 goto dob;
7350 }
7351
7352 case M_L_DOB:
7353 /* Even on a big endian machine $fn comes before $fn+1. We have
7354 to adjust when loading from memory. */
7355 r = BFD_RELOC_LO16;
7356 dob:
7357 gas_assert (mips_opts.isa == ISA_MIPS1);
7358 macro_build (&offset_expr, "lwc1", "T,o(b)",
7359 target_big_endian ? treg + 1 : treg, r, breg);
7360 /* FIXME: A possible overflow which I don't know how to deal
7361 with. */
7362 offset_expr.X_add_number += 4;
7363 macro_build (&offset_expr, "lwc1", "T,o(b)",
7364 target_big_endian ? treg : treg + 1, r, breg);
7365 break;
7366
7367 case M_S_DOB:
7368 gas_assert (mips_opts.isa == ISA_MIPS1);
7369 /* Even on a big endian machine $fn comes before $fn+1. We have
7370 to adjust when storing to memory. */
7371 macro_build (&offset_expr, "swc1", "T,o(b)",
7372 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7373 offset_expr.X_add_number += 4;
7374 macro_build (&offset_expr, "swc1", "T,o(b)",
7375 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7376 break;
7377
7378 case M_L_DAB:
7379 /*
7380 * The MIPS assembler seems to check for X_add_number not
7381 * being double aligned and generating:
7382 * lui at,%hi(foo+1)
7383 * addu at,at,v1
7384 * addiu at,at,%lo(foo+1)
7385 * lwc1 f2,0(at)
7386 * lwc1 f3,4(at)
7387 * But, the resulting address is the same after relocation so why
7388 * generate the extra instruction?
7389 */
7390 /* Itbl support may require additional care here. */
7391 coproc = 1;
7392 if (mips_opts.isa != ISA_MIPS1)
7393 {
7394 s = "ldc1";
7395 goto ld;
7396 }
7397
7398 s = "lwc1";
7399 fmt = "T,o(b)";
7400 goto ldd_std;
7401
7402 case M_S_DAB:
7403 if (mips_opts.isa != ISA_MIPS1)
7404 {
7405 s = "sdc1";
7406 goto st;
7407 }
7408
7409 s = "swc1";
7410 fmt = "T,o(b)";
7411 /* Itbl support may require additional care here. */
7412 coproc = 1;
7413 goto ldd_std;
7414
7415 case M_LD_AB:
7416 if (HAVE_64BIT_GPRS)
7417 {
7418 s = "ld";
7419 goto ld;
7420 }
7421
7422 s = "lw";
7423 fmt = "t,o(b)";
7424 goto ldd_std;
7425
7426 case M_SD_AB:
7427 if (HAVE_64BIT_GPRS)
7428 {
7429 s = "sd";
7430 goto st;
7431 }
7432
7433 s = "sw";
7434 fmt = "t,o(b)";
7435
7436 ldd_std:
7437 if (offset_expr.X_op != O_symbol
7438 && offset_expr.X_op != O_constant)
7439 {
7440 as_bad (_("Expression too complex"));
7441 offset_expr.X_op = O_constant;
7442 }
7443
7444 if (HAVE_32BIT_ADDRESSES
7445 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
7446 {
7447 char value [32];
7448
7449 sprintf_vma (value, offset_expr.X_add_number);
7450 as_bad (_("Number (0x%s) larger than 32 bits"), value);
7451 }
7452
7453 /* Even on a big endian machine $fn comes before $fn+1. We have
7454 to adjust when loading from memory. We set coproc if we must
7455 load $fn+1 first. */
7456 /* Itbl support may require additional care here. */
7457 if (!target_big_endian)
7458 coproc = 0;
7459
7460 if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
7461 {
7462 /* If this is a reference to a GP relative symbol, we want
7463 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7464 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7465 If we have a base register, we use this
7466 addu $at,$breg,$gp
7467 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7468 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7469 If this is not a GP relative symbol, we want
7470 lui $at,<sym> (BFD_RELOC_HI16_S)
7471 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7472 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7473 If there is a base register, we add it to $at after the
7474 lui instruction. If there is a constant, we always use
7475 the last case. */
7476 if (offset_expr.X_op == O_symbol
7477 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
7478 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
7479 {
7480 relax_start (offset_expr.X_add_symbol);
7481 if (breg == 0)
7482 {
7483 tempreg = mips_gp_register;
7484 }
7485 else
7486 {
7487 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7488 AT, breg, mips_gp_register);
7489 tempreg = AT;
7490 used_at = 1;
7491 }
7492
7493 /* Itbl support may require additional care here. */
7494 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7495 BFD_RELOC_GPREL16, tempreg);
7496 offset_expr.X_add_number += 4;
7497
7498 /* Set mips_optimize to 2 to avoid inserting an
7499 undesired nop. */
7500 hold_mips_optimize = mips_optimize;
7501 mips_optimize = 2;
7502 /* Itbl support may require additional care here. */
7503 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7504 BFD_RELOC_GPREL16, tempreg);
7505 mips_optimize = hold_mips_optimize;
7506
7507 relax_switch ();
7508
7509 offset_expr.X_add_number -= 4;
7510 }
7511 used_at = 1;
7512 macro_build_lui (&offset_expr, AT);
7513 if (breg != 0)
7514 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7515 /* Itbl support may require additional care here. */
7516 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7517 BFD_RELOC_LO16, AT);
7518 /* FIXME: How do we handle overflow here? */
7519 offset_expr.X_add_number += 4;
7520 /* Itbl support may require additional care here. */
7521 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7522 BFD_RELOC_LO16, AT);
7523 if (mips_relax.sequence)
7524 relax_end ();
7525 }
7526 else if (!mips_big_got)
7527 {
7528 /* If this is a reference to an external symbol, we want
7529 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7530 nop
7531 <op> $treg,0($at)
7532 <op> $treg+1,4($at)
7533 Otherwise we want
7534 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7535 nop
7536 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7537 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7538 If there is a base register we add it to $at before the
7539 lwc1 instructions. If there is a constant we include it
7540 in the lwc1 instructions. */
7541 used_at = 1;
7542 expr1.X_add_number = offset_expr.X_add_number;
7543 if (expr1.X_add_number < -0x8000
7544 || expr1.X_add_number >= 0x8000 - 4)
7545 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7546 load_got_offset (AT, &offset_expr);
7547 load_delay_nop ();
7548 if (breg != 0)
7549 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7550
7551 /* Set mips_optimize to 2 to avoid inserting an undesired
7552 nop. */
7553 hold_mips_optimize = mips_optimize;
7554 mips_optimize = 2;
7555
7556 /* Itbl support may require additional care here. */
7557 relax_start (offset_expr.X_add_symbol);
7558 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7559 BFD_RELOC_LO16, AT);
7560 expr1.X_add_number += 4;
7561 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7562 BFD_RELOC_LO16, AT);
7563 relax_switch ();
7564 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7565 BFD_RELOC_LO16, AT);
7566 offset_expr.X_add_number += 4;
7567 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7568 BFD_RELOC_LO16, AT);
7569 relax_end ();
7570
7571 mips_optimize = hold_mips_optimize;
7572 }
7573 else if (mips_big_got)
7574 {
7575 int gpdelay;
7576
7577 /* If this is a reference to an external symbol, we want
7578 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7579 addu $at,$at,$gp
7580 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7581 nop
7582 <op> $treg,0($at)
7583 <op> $treg+1,4($at)
7584 Otherwise we want
7585 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7586 nop
7587 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7588 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7589 If there is a base register we add it to $at before the
7590 lwc1 instructions. If there is a constant we include it
7591 in the lwc1 instructions. */
7592 used_at = 1;
7593 expr1.X_add_number = offset_expr.X_add_number;
7594 offset_expr.X_add_number = 0;
7595 if (expr1.X_add_number < -0x8000
7596 || expr1.X_add_number >= 0x8000 - 4)
7597 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7598 gpdelay = reg_needs_delay (mips_gp_register);
7599 relax_start (offset_expr.X_add_symbol);
7600 macro_build (&offset_expr, "lui", "t,u",
7601 AT, BFD_RELOC_MIPS_GOT_HI16);
7602 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
7603 AT, AT, mips_gp_register);
7604 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
7605 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
7606 load_delay_nop ();
7607 if (breg != 0)
7608 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7609 /* Itbl support may require additional care here. */
7610 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
7611 BFD_RELOC_LO16, AT);
7612 expr1.X_add_number += 4;
7613
7614 /* Set mips_optimize to 2 to avoid inserting an undesired
7615 nop. */
7616 hold_mips_optimize = mips_optimize;
7617 mips_optimize = 2;
7618 /* Itbl support may require additional care here. */
7619 macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
7620 BFD_RELOC_LO16, AT);
7621 mips_optimize = hold_mips_optimize;
7622 expr1.X_add_number -= 4;
7623
7624 relax_switch ();
7625 offset_expr.X_add_number = expr1.X_add_number;
7626 if (gpdelay)
7627 macro_build (NULL, "nop", "");
7628 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
7629 BFD_RELOC_MIPS_GOT16, mips_gp_register);
7630 load_delay_nop ();
7631 if (breg != 0)
7632 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
7633 /* Itbl support may require additional care here. */
7634 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
7635 BFD_RELOC_LO16, AT);
7636 offset_expr.X_add_number += 4;
7637
7638 /* Set mips_optimize to 2 to avoid inserting an undesired
7639 nop. */
7640 hold_mips_optimize = mips_optimize;
7641 mips_optimize = 2;
7642 /* Itbl support may require additional care here. */
7643 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
7644 BFD_RELOC_LO16, AT);
7645 mips_optimize = hold_mips_optimize;
7646 relax_end ();
7647 }
7648 else
7649 abort ();
7650
7651 break;
7652
7653 case M_LD_OB:
7654 s = HAVE_64BIT_GPRS ? "ld" : "lw";
7655 goto sd_ob;
7656 case M_SD_OB:
7657 s = HAVE_64BIT_GPRS ? "sd" : "sw";
7658 sd_ob:
7659 macro_build (&offset_expr, s, "t,o(b)", treg,
7660 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7661 breg);
7662 if (!HAVE_64BIT_GPRS)
7663 {
7664 offset_expr.X_add_number += 4;
7665 macro_build (&offset_expr, s, "t,o(b)", treg + 1,
7666 -1, offset_reloc[0], offset_reloc[1], offset_reloc[2],
7667 breg);
7668 }
7669 break;
7670
7671 /* New code added to support COPZ instructions.
7672 This code builds table entries out of the macros in mip_opcodes.
7673 R4000 uses interlocks to handle coproc delays.
7674 Other chips (like the R3000) require nops to be inserted for delays.
7675
7676 FIXME: Currently, we require that the user handle delays.
7677 In order to fill delay slots for non-interlocked chips,
7678 we must have a way to specify delays based on the coprocessor.
7679 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7680 What are the side-effects of the cop instruction?
7681 What cache support might we have and what are its effects?
7682 Both coprocessor & memory require delays. how long???
7683 What registers are read/set/modified?
7684
7685 If an itbl is provided to interpret cop instructions,
7686 this knowledge can be encoded in the itbl spec. */
7687
7688 case M_COP0:
7689 s = "c0";
7690 goto copz;
7691 case M_COP1:
7692 s = "c1";
7693 goto copz;
7694 case M_COP2:
7695 s = "c2";
7696 goto copz;
7697 case M_COP3:
7698 s = "c3";
7699 copz:
7700 if (NO_ISA_COP (mips_opts.arch)
7701 && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
7702 {
7703 as_bad (_("opcode not supported on this processor: %s"),
7704 mips_cpu_info_from_arch (mips_opts.arch)->name);
7705 break;
7706 }
7707
7708 /* For now we just do C (same as Cz). The parameter will be
7709 stored in insn_opcode by mips_ip. */
7710 macro_build (NULL, s, "C", ip->insn_opcode);
7711 break;
7712
7713 case M_MOVE:
7714 move_register (dreg, sreg);
7715 break;
7716
7717 case M_DMUL:
7718 dbl = 1;
7719 case M_MUL:
7720 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
7721 macro_build (NULL, "mflo", "d", dreg);
7722 break;
7723
7724 case M_DMUL_I:
7725 dbl = 1;
7726 case M_MUL_I:
7727 /* The MIPS assembler some times generates shifts and adds. I'm
7728 not trying to be that fancy. GCC should do this for us
7729 anyway. */
7730 used_at = 1;
7731 load_register (AT, &imm_expr, dbl);
7732 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
7733 macro_build (NULL, "mflo", "d", dreg);
7734 break;
7735
7736 case M_DMULO_I:
7737 dbl = 1;
7738 case M_MULO_I:
7739 imm = 1;
7740 goto do_mulo;
7741
7742 case M_DMULO:
7743 dbl = 1;
7744 case M_MULO:
7745 do_mulo:
7746 start_noreorder ();
7747 used_at = 1;
7748 if (imm)
7749 load_register (AT, &imm_expr, dbl);
7750 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
7751 macro_build (NULL, "mflo", "d", dreg);
7752 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
7753 macro_build (NULL, "mfhi", "d", AT);
7754 if (mips_trap)
7755 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
7756 else
7757 {
7758 expr1.X_add_number = 8;
7759 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
7760 macro_build (NULL, "nop", "");
7761 macro_build (NULL, "break", "c", 6);
7762 }
7763 end_noreorder ();
7764 macro_build (NULL, "mflo", "d", dreg);
7765 break;
7766
7767 case M_DMULOU_I:
7768 dbl = 1;
7769 case M_MULOU_I:
7770 imm = 1;
7771 goto do_mulou;
7772
7773 case M_DMULOU:
7774 dbl = 1;
7775 case M_MULOU:
7776 do_mulou:
7777 start_noreorder ();
7778 used_at = 1;
7779 if (imm)
7780 load_register (AT, &imm_expr, dbl);
7781 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7782 sreg, imm ? AT : treg);
7783 macro_build (NULL, "mfhi", "d", AT);
7784 macro_build (NULL, "mflo", "d", dreg);
7785 if (mips_trap)
7786 macro_build (NULL, "tne", "s,t,q", AT, ZERO, 6);
7787 else
7788 {
7789 expr1.X_add_number = 8;
7790 macro_build (&expr1, "beq", "s,t,p", AT, ZERO);
7791 macro_build (NULL, "nop", "");
7792 macro_build (NULL, "break", "c", 6);
7793 }
7794 end_noreorder ();
7795 break;
7796
7797 case M_DROL:
7798 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7799 {
7800 if (dreg == sreg)
7801 {
7802 tempreg = AT;
7803 used_at = 1;
7804 }
7805 else
7806 {
7807 tempreg = dreg;
7808 }
7809 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7810 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7811 break;
7812 }
7813 used_at = 1;
7814 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7815 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7816 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7817 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7818 break;
7819
7820 case M_ROL:
7821 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7822 {
7823 if (dreg == sreg)
7824 {
7825 tempreg = AT;
7826 used_at = 1;
7827 }
7828 else
7829 {
7830 tempreg = dreg;
7831 }
7832 macro_build (NULL, "negu", "d,w", tempreg, treg);
7833 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7834 break;
7835 }
7836 used_at = 1;
7837 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7838 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7839 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7840 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7841 break;
7842
7843 case M_DROL_I:
7844 {
7845 unsigned int rot;
7846 char *l;
7847 char *rr;
7848
7849 if (imm_expr.X_op != O_constant)
7850 as_bad (_("Improper rotate count"));
7851 rot = imm_expr.X_add_number & 0x3f;
7852 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7853 {
7854 rot = (64 - rot) & 0x3f;
7855 if (rot >= 32)
7856 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7857 else
7858 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7859 break;
7860 }
7861 if (rot == 0)
7862 {
7863 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7864 break;
7865 }
7866 l = (rot < 0x20) ? "dsll" : "dsll32";
7867 rr = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7868 rot &= 0x1f;
7869 used_at = 1;
7870 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7871 macro_build (NULL, rr, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7872 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7873 }
7874 break;
7875
7876 case M_ROL_I:
7877 {
7878 unsigned int rot;
7879
7880 if (imm_expr.X_op != O_constant)
7881 as_bad (_("Improper rotate count"));
7882 rot = imm_expr.X_add_number & 0x1f;
7883 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7884 {
7885 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7886 break;
7887 }
7888 if (rot == 0)
7889 {
7890 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7891 break;
7892 }
7893 used_at = 1;
7894 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7895 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7896 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7897 }
7898 break;
7899
7900 case M_DROR:
7901 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7902 {
7903 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7904 break;
7905 }
7906 used_at = 1;
7907 macro_build (NULL, "dsubu", "d,v,t", AT, ZERO, treg);
7908 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7909 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7910 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7911 break;
7912
7913 case M_ROR:
7914 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7915 {
7916 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7917 break;
7918 }
7919 used_at = 1;
7920 macro_build (NULL, "subu", "d,v,t", AT, ZERO, treg);
7921 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7922 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7923 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7924 break;
7925
7926 case M_DROR_I:
7927 {
7928 unsigned int rot;
7929 char *l;
7930 char *rr;
7931
7932 if (imm_expr.X_op != O_constant)
7933 as_bad (_("Improper rotate count"));
7934 rot = imm_expr.X_add_number & 0x3f;
7935 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7936 {
7937 if (rot >= 32)
7938 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7939 else
7940 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7941 break;
7942 }
7943 if (rot == 0)
7944 {
7945 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7946 break;
7947 }
7948 rr = (rot < 0x20) ? "dsrl" : "dsrl32";
7949 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7950 rot &= 0x1f;
7951 used_at = 1;
7952 macro_build (NULL, rr, "d,w,<", AT, sreg, rot);
7953 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7954 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7955 }
7956 break;
7957
7958 case M_ROR_I:
7959 {
7960 unsigned int rot;
7961
7962 if (imm_expr.X_op != O_constant)
7963 as_bad (_("Improper rotate count"));
7964 rot = imm_expr.X_add_number & 0x1f;
7965 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7966 {
7967 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7968 break;
7969 }
7970 if (rot == 0)
7971 {
7972 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7973 break;
7974 }
7975 used_at = 1;
7976 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7977 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7978 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7979 }
7980 break;
7981
7982 case M_SEQ:
7983 if (sreg == 0)
7984 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7985 else if (treg == 0)
7986 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7987 else
7988 {
7989 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7990 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7991 }
7992 break;
7993
7994 case M_SEQ_I:
7995 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7996 {
7997 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7998 break;
7999 }
8000 if (sreg == 0)
8001 {
8002 as_warn (_("Instruction %s: result is always false"),
8003 ip->insn_mo->name);
8004 move_register (dreg, 0);
8005 break;
8006 }
8007 if (CPU_HAS_SEQ (mips_opts.arch)
8008 && -512 <= imm_expr.X_add_number
8009 && imm_expr.X_add_number < 512)
8010 {
8011 macro_build (NULL, "seqi", "t,r,+Q", dreg, sreg,
8012 (int) imm_expr.X_add_number);
8013 break;
8014 }
8015 if (imm_expr.X_op == O_constant
8016 && imm_expr.X_add_number >= 0
8017 && imm_expr.X_add_number < 0x10000)
8018 {
8019 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8020 }
8021 else if (imm_expr.X_op == O_constant
8022 && imm_expr.X_add_number > -0x8000
8023 && imm_expr.X_add_number < 0)
8024 {
8025 imm_expr.X_add_number = -imm_expr.X_add_number;
8026 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8027 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8028 }
8029 else if (CPU_HAS_SEQ (mips_opts.arch))
8030 {
8031 used_at = 1;
8032 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8033 macro_build (NULL, "seq", "d,v,t", dreg, sreg, AT);
8034 break;
8035 }
8036 else
8037 {
8038 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8039 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8040 used_at = 1;
8041 }
8042 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
8043 break;
8044
8045 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
8046 s = "slt";
8047 goto sge;
8048 case M_SGEU:
8049 s = "sltu";
8050 sge:
8051 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
8052 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8053 break;
8054
8055 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
8056 case M_SGEU_I:
8057 if (imm_expr.X_op == O_constant
8058 && imm_expr.X_add_number >= -0x8000
8059 && imm_expr.X_add_number < 0x8000)
8060 {
8061 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
8062 dreg, sreg, BFD_RELOC_LO16);
8063 }
8064 else
8065 {
8066 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8067 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
8068 dreg, sreg, AT);
8069 used_at = 1;
8070 }
8071 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8072 break;
8073
8074 case M_SGT: /* sreg > treg <==> treg < sreg */
8075 s = "slt";
8076 goto sgt;
8077 case M_SGTU:
8078 s = "sltu";
8079 sgt:
8080 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8081 break;
8082
8083 case M_SGT_I: /* sreg > I <==> I < sreg */
8084 s = "slt";
8085 goto sgti;
8086 case M_SGTU_I:
8087 s = "sltu";
8088 sgti:
8089 used_at = 1;
8090 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8091 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8092 break;
8093
8094 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
8095 s = "slt";
8096 goto sle;
8097 case M_SLEU:
8098 s = "sltu";
8099 sle:
8100 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
8101 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8102 break;
8103
8104 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
8105 s = "slt";
8106 goto slei;
8107 case M_SLEU_I:
8108 s = "sltu";
8109 slei:
8110 used_at = 1;
8111 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8112 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
8113 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
8114 break;
8115
8116 case M_SLT_I:
8117 if (imm_expr.X_op == O_constant
8118 && imm_expr.X_add_number >= -0x8000
8119 && imm_expr.X_add_number < 0x8000)
8120 {
8121 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8122 break;
8123 }
8124 used_at = 1;
8125 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8126 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
8127 break;
8128
8129 case M_SLTU_I:
8130 if (imm_expr.X_op == O_constant
8131 && imm_expr.X_add_number >= -0x8000
8132 && imm_expr.X_add_number < 0x8000)
8133 {
8134 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
8135 BFD_RELOC_LO16);
8136 break;
8137 }
8138 used_at = 1;
8139 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8140 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
8141 break;
8142
8143 case M_SNE:
8144 if (sreg == 0)
8145 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
8146 else if (treg == 0)
8147 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8148 else
8149 {
8150 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
8151 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8152 }
8153 break;
8154
8155 case M_SNE_I:
8156 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
8157 {
8158 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
8159 break;
8160 }
8161 if (sreg == 0)
8162 {
8163 as_warn (_("Instruction %s: result is always true"),
8164 ip->insn_mo->name);
8165 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
8166 dreg, 0, BFD_RELOC_LO16);
8167 break;
8168 }
8169 if (CPU_HAS_SEQ (mips_opts.arch)
8170 && -512 <= imm_expr.X_add_number
8171 && imm_expr.X_add_number < 512)
8172 {
8173 macro_build (NULL, "snei", "t,r,+Q", dreg, sreg,
8174 (int) imm_expr.X_add_number);
8175 break;
8176 }
8177 if (imm_expr.X_op == O_constant
8178 && imm_expr.X_add_number >= 0
8179 && imm_expr.X_add_number < 0x10000)
8180 {
8181 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
8182 }
8183 else if (imm_expr.X_op == O_constant
8184 && imm_expr.X_add_number > -0x8000
8185 && imm_expr.X_add_number < 0)
8186 {
8187 imm_expr.X_add_number = -imm_expr.X_add_number;
8188 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
8189 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
8190 }
8191 else if (CPU_HAS_SEQ (mips_opts.arch))
8192 {
8193 used_at = 1;
8194 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8195 macro_build (NULL, "sne", "d,v,t", dreg, sreg, AT);
8196 break;
8197 }
8198 else
8199 {
8200 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8201 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
8202 used_at = 1;
8203 }
8204 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
8205 break;
8206
8207 case M_DSUB_I:
8208 dbl = 1;
8209 case M_SUB_I:
8210 if (imm_expr.X_op == O_constant
8211 && imm_expr.X_add_number > -0x8000
8212 && imm_expr.X_add_number <= 0x8000)
8213 {
8214 imm_expr.X_add_number = -imm_expr.X_add_number;
8215 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
8216 dreg, sreg, BFD_RELOC_LO16);
8217 break;
8218 }
8219 used_at = 1;
8220 load_register (AT, &imm_expr, dbl);
8221 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
8222 break;
8223
8224 case M_DSUBU_I:
8225 dbl = 1;
8226 case M_SUBU_I:
8227 if (imm_expr.X_op == O_constant
8228 && imm_expr.X_add_number > -0x8000
8229 && imm_expr.X_add_number <= 0x8000)
8230 {
8231 imm_expr.X_add_number = -imm_expr.X_add_number;
8232 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
8233 dreg, sreg, BFD_RELOC_LO16);
8234 break;
8235 }
8236 used_at = 1;
8237 load_register (AT, &imm_expr, dbl);
8238 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
8239 break;
8240
8241 case M_TEQ_I:
8242 s = "teq";
8243 goto trap;
8244 case M_TGE_I:
8245 s = "tge";
8246 goto trap;
8247 case M_TGEU_I:
8248 s = "tgeu";
8249 goto trap;
8250 case M_TLT_I:
8251 s = "tlt";
8252 goto trap;
8253 case M_TLTU_I:
8254 s = "tltu";
8255 goto trap;
8256 case M_TNE_I:
8257 s = "tne";
8258 trap:
8259 used_at = 1;
8260 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
8261 macro_build (NULL, s, "s,t", sreg, AT);
8262 break;
8263
8264 case M_TRUNCWS:
8265 case M_TRUNCWD:
8266 gas_assert (mips_opts.isa == ISA_MIPS1);
8267 used_at = 1;
8268 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
8269 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
8270
8271 /*
8272 * Is the double cfc1 instruction a bug in the mips assembler;
8273 * or is there a reason for it?
8274 */
8275 start_noreorder ();
8276 macro_build (NULL, "cfc1", "t,G", treg, RA);
8277 macro_build (NULL, "cfc1", "t,G", treg, RA);
8278 macro_build (NULL, "nop", "");
8279 expr1.X_add_number = 3;
8280 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
8281 expr1.X_add_number = 2;
8282 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
8283 macro_build (NULL, "ctc1", "t,G", AT, RA);
8284 macro_build (NULL, "nop", "");
8285 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
8286 dreg, sreg);
8287 macro_build (NULL, "ctc1", "t,G", treg, RA);
8288 macro_build (NULL, "nop", "");
8289 end_noreorder ();
8290 break;
8291
8292 case M_ULH:
8293 s = "lb";
8294 goto ulh;
8295 case M_ULHU:
8296 s = "lbu";
8297 ulh:
8298 used_at = 1;
8299 if (offset_expr.X_add_number >= 0x7fff)
8300 as_bad (_("Operand overflow"));
8301 if (!target_big_endian)
8302 ++offset_expr.X_add_number;
8303 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
8304 if (!target_big_endian)
8305 --offset_expr.X_add_number;
8306 else
8307 ++offset_expr.X_add_number;
8308 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8309 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
8310 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8311 break;
8312
8313 case M_ULD:
8314 s = "ldl";
8315 s2 = "ldr";
8316 off = 7;
8317 goto ulw;
8318 case M_ULW:
8319 s = "lwl";
8320 s2 = "lwr";
8321 off = 3;
8322 ulw:
8323 if (offset_expr.X_add_number >= 0x8000 - off)
8324 as_bad (_("Operand overflow"));
8325 if (treg != breg)
8326 tempreg = treg;
8327 else
8328 {
8329 used_at = 1;
8330 tempreg = AT;
8331 }
8332 if (!target_big_endian)
8333 offset_expr.X_add_number += off;
8334 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8335 if (!target_big_endian)
8336 offset_expr.X_add_number -= off;
8337 else
8338 offset_expr.X_add_number += off;
8339 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
8340
8341 /* If necessary, move the result in tempreg to the final destination. */
8342 if (treg == tempreg)
8343 break;
8344 /* Protect second load's delay slot. */
8345 load_delay_nop ();
8346 move_register (treg, tempreg);
8347 break;
8348
8349 case M_ULD_A:
8350 s = "ldl";
8351 s2 = "ldr";
8352 off = 7;
8353 goto ulwa;
8354 case M_ULW_A:
8355 s = "lwl";
8356 s2 = "lwr";
8357 off = 3;
8358 ulwa:
8359 used_at = 1;
8360 load_address (AT, &offset_expr, &used_at);
8361 if (breg != 0)
8362 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8363 if (!target_big_endian)
8364 expr1.X_add_number = off;
8365 else
8366 expr1.X_add_number = 0;
8367 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8368 if (!target_big_endian)
8369 expr1.X_add_number = 0;
8370 else
8371 expr1.X_add_number = off;
8372 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8373 break;
8374
8375 case M_ULH_A:
8376 case M_ULHU_A:
8377 used_at = 1;
8378 load_address (AT, &offset_expr, &used_at);
8379 if (breg != 0)
8380 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8381 if (target_big_endian)
8382 expr1.X_add_number = 0;
8383 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
8384 treg, BFD_RELOC_LO16, AT);
8385 if (target_big_endian)
8386 expr1.X_add_number = 1;
8387 else
8388 expr1.X_add_number = 0;
8389 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8390 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8391 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8392 break;
8393
8394 case M_USH:
8395 used_at = 1;
8396 if (offset_expr.X_add_number >= 0x7fff)
8397 as_bad (_("Operand overflow"));
8398 if (target_big_endian)
8399 ++offset_expr.X_add_number;
8400 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
8401 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
8402 if (target_big_endian)
8403 --offset_expr.X_add_number;
8404 else
8405 ++offset_expr.X_add_number;
8406 macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
8407 break;
8408
8409 case M_USD:
8410 s = "sdl";
8411 s2 = "sdr";
8412 off = 7;
8413 goto usw;
8414 case M_USW:
8415 s = "swl";
8416 s2 = "swr";
8417 off = 3;
8418 usw:
8419 if (offset_expr.X_add_number >= 0x8000 - off)
8420 as_bad (_("Operand overflow"));
8421 if (!target_big_endian)
8422 offset_expr.X_add_number += off;
8423 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8424 if (!target_big_endian)
8425 offset_expr.X_add_number -= off;
8426 else
8427 offset_expr.X_add_number += off;
8428 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
8429 break;
8430
8431 case M_USD_A:
8432 s = "sdl";
8433 s2 = "sdr";
8434 off = 7;
8435 goto uswa;
8436 case M_USW_A:
8437 s = "swl";
8438 s2 = "swr";
8439 off = 3;
8440 uswa:
8441 used_at = 1;
8442 load_address (AT, &offset_expr, &used_at);
8443 if (breg != 0)
8444 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8445 if (!target_big_endian)
8446 expr1.X_add_number = off;
8447 else
8448 expr1.X_add_number = 0;
8449 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8450 if (!target_big_endian)
8451 expr1.X_add_number = 0;
8452 else
8453 expr1.X_add_number = off;
8454 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
8455 break;
8456
8457 case M_USH_A:
8458 used_at = 1;
8459 load_address (AT, &offset_expr, &used_at);
8460 if (breg != 0)
8461 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
8462 if (!target_big_endian)
8463 expr1.X_add_number = 0;
8464 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8465 macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
8466 if (!target_big_endian)
8467 expr1.X_add_number = 1;
8468 else
8469 expr1.X_add_number = 0;
8470 macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
8471 if (!target_big_endian)
8472 expr1.X_add_number = 0;
8473 else
8474 expr1.X_add_number = 1;
8475 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
8476 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
8477 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
8478 break;
8479
8480 default:
8481 /* FIXME: Check if this is one of the itbl macros, since they
8482 are added dynamically. */
8483 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
8484 break;
8485 }
8486 if (!mips_opts.at && used_at)
8487 as_bad (_("Macro used $at after \".set noat\""));
8488}
8489
8490/* Implement macros in mips16 mode. */
8491
8492static void
8493mips16_macro (struct mips_cl_insn *ip)
8494{
8495 int mask;
8496 int xreg, yreg, zreg, tmp;
8497 expressionS expr1;
8498 int dbl;
8499 const char *s, *s2, *s3;
8500
8501 mask = ip->insn_mo->mask;
8502
8503 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
8504 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
8505 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
8506
8507 expr1.X_op = O_constant;
8508 expr1.X_op_symbol = NULL;
8509 expr1.X_add_symbol = NULL;
8510 expr1.X_add_number = 1;
8511
8512 dbl = 0;
8513
8514 switch (mask)
8515 {
8516 default:
8517 internalError ();
8518
8519 case M_DDIV_3:
8520 dbl = 1;
8521 case M_DIV_3:
8522 s = "mflo";
8523 goto do_div3;
8524 case M_DREM_3:
8525 dbl = 1;
8526 case M_REM_3:
8527 s = "mfhi";
8528 do_div3:
8529 start_noreorder ();
8530 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
8531 expr1.X_add_number = 2;
8532 macro_build (&expr1, "bnez", "x,p", yreg);
8533 macro_build (NULL, "break", "6", 7);
8534
8535 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8536 since that causes an overflow. We should do that as well,
8537 but I don't see how to do the comparisons without a temporary
8538 register. */
8539 end_noreorder ();
8540 macro_build (NULL, s, "x", zreg);
8541 break;
8542
8543 case M_DIVU_3:
8544 s = "divu";
8545 s2 = "mflo";
8546 goto do_divu3;
8547 case M_REMU_3:
8548 s = "divu";
8549 s2 = "mfhi";
8550 goto do_divu3;
8551 case M_DDIVU_3:
8552 s = "ddivu";
8553 s2 = "mflo";
8554 goto do_divu3;
8555 case M_DREMU_3:
8556 s = "ddivu";
8557 s2 = "mfhi";
8558 do_divu3:
8559 start_noreorder ();
8560 macro_build (NULL, s, "0,x,y", xreg, yreg);
8561 expr1.X_add_number = 2;
8562 macro_build (&expr1, "bnez", "x,p", yreg);
8563 macro_build (NULL, "break", "6", 7);
8564 end_noreorder ();
8565 macro_build (NULL, s2, "x", zreg);
8566 break;
8567
8568 case M_DMUL:
8569 dbl = 1;
8570 case M_MUL:
8571 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
8572 macro_build (NULL, "mflo", "x", zreg);
8573 break;
8574
8575 case M_DSUBU_I:
8576 dbl = 1;
8577 goto do_subu;
8578 case M_SUBU_I:
8579 do_subu:
8580 if (imm_expr.X_op != O_constant)
8581 as_bad (_("Unsupported large constant"));
8582 imm_expr.X_add_number = -imm_expr.X_add_number;
8583 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
8584 break;
8585
8586 case M_SUBU_I_2:
8587 if (imm_expr.X_op != O_constant)
8588 as_bad (_("Unsupported large constant"));
8589 imm_expr.X_add_number = -imm_expr.X_add_number;
8590 macro_build (&imm_expr, "addiu", "x,k", xreg);
8591 break;
8592
8593 case M_DSUBU_I_2:
8594 if (imm_expr.X_op != O_constant)
8595 as_bad (_("Unsupported large constant"));
8596 imm_expr.X_add_number = -imm_expr.X_add_number;
8597 macro_build (&imm_expr, "daddiu", "y,j", yreg);
8598 break;
8599
8600 case M_BEQ:
8601 s = "cmp";
8602 s2 = "bteqz";
8603 goto do_branch;
8604 case M_BNE:
8605 s = "cmp";
8606 s2 = "btnez";
8607 goto do_branch;
8608 case M_BLT:
8609 s = "slt";
8610 s2 = "btnez";
8611 goto do_branch;
8612 case M_BLTU:
8613 s = "sltu";
8614 s2 = "btnez";
8615 goto do_branch;
8616 case M_BLE:
8617 s = "slt";
8618 s2 = "bteqz";
8619 goto do_reverse_branch;
8620 case M_BLEU:
8621 s = "sltu";
8622 s2 = "bteqz";
8623 goto do_reverse_branch;
8624 case M_BGE:
8625 s = "slt";
8626 s2 = "bteqz";
8627 goto do_branch;
8628 case M_BGEU:
8629 s = "sltu";
8630 s2 = "bteqz";
8631 goto do_branch;
8632 case M_BGT:
8633 s = "slt";
8634 s2 = "btnez";
8635 goto do_reverse_branch;
8636 case M_BGTU:
8637 s = "sltu";
8638 s2 = "btnez";
8639
8640 do_reverse_branch:
8641 tmp = xreg;
8642 xreg = yreg;
8643 yreg = tmp;
8644
8645 do_branch:
8646 macro_build (NULL, s, "x,y", xreg, yreg);
8647 macro_build (&offset_expr, s2, "p");
8648 break;
8649
8650 case M_BEQ_I:
8651 s = "cmpi";
8652 s2 = "bteqz";
8653 s3 = "x,U";
8654 goto do_branch_i;
8655 case M_BNE_I:
8656 s = "cmpi";
8657 s2 = "btnez";
8658 s3 = "x,U";
8659 goto do_branch_i;
8660 case M_BLT_I:
8661 s = "slti";
8662 s2 = "btnez";
8663 s3 = "x,8";
8664 goto do_branch_i;
8665 case M_BLTU_I:
8666 s = "sltiu";
8667 s2 = "btnez";
8668 s3 = "x,8";
8669 goto do_branch_i;
8670 case M_BLE_I:
8671 s = "slti";
8672 s2 = "btnez";
8673 s3 = "x,8";
8674 goto do_addone_branch_i;
8675 case M_BLEU_I:
8676 s = "sltiu";
8677 s2 = "btnez";
8678 s3 = "x,8";
8679 goto do_addone_branch_i;
8680 case M_BGE_I:
8681 s = "slti";
8682 s2 = "bteqz";
8683 s3 = "x,8";
8684 goto do_branch_i;
8685 case M_BGEU_I:
8686 s = "sltiu";
8687 s2 = "bteqz";
8688 s3 = "x,8";
8689 goto do_branch_i;
8690 case M_BGT_I:
8691 s = "slti";
8692 s2 = "bteqz";
8693 s3 = "x,8";
8694 goto do_addone_branch_i;
8695 case M_BGTU_I:
8696 s = "sltiu";
8697 s2 = "bteqz";
8698 s3 = "x,8";
8699
8700 do_addone_branch_i:
8701 if (imm_expr.X_op != O_constant)
8702 as_bad (_("Unsupported large constant"));
8703 ++imm_expr.X_add_number;
8704
8705 do_branch_i:
8706 macro_build (&imm_expr, s, s3, xreg);
8707 macro_build (&offset_expr, s2, "p");
8708 break;
8709
8710 case M_ABS:
8711 expr1.X_add_number = 0;
8712 macro_build (&expr1, "slti", "x,8", yreg);
8713 if (xreg != yreg)
8714 move_register (xreg, yreg);
8715 expr1.X_add_number = 2;
8716 macro_build (&expr1, "bteqz", "p");
8717 macro_build (NULL, "neg", "x,w", xreg, xreg);
8718 }
8719}
8720
8721/* For consistency checking, verify that all bits are specified either
8722 by the match/mask part of the instruction definition, or by the
8723 operand list. */
8724static int
8725validate_mips_insn (const struct mips_opcode *opc)
8726{
8727 const char *p = opc->args;
8728 char c;
8729 unsigned long used_bits = opc->mask;
8730
8731 if ((used_bits & opc->match) != opc->match)
8732 {
8733 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8734 opc->name, opc->args);
8735 return 0;
8736 }
8737#define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8738 while (*p)
8739 switch (c = *p++)
8740 {
8741 case ',': break;
8742 case '(': break;
8743 case ')': break;
8744 case '+':
8745 switch (c = *p++)
8746 {
8747 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8748 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8749 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8750 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
8751 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8752 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8753 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8754 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8755 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8756 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8757 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8758 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8759 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8760 case 'I': break;
8761 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8762 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
8763 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8764 case 'x': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8765 case 'X': USE_BITS (OP_MASK_BBITIND, OP_SH_BBITIND); break;
8766 case 'p': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8767 case 'P': USE_BITS (OP_MASK_CINSPOS, OP_SH_CINSPOS); break;
8768 case 'Q': USE_BITS (OP_MASK_SEQI, OP_SH_SEQI); break;
8769 case 's': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8770 case 'S': USE_BITS (OP_MASK_CINSLM1, OP_SH_CINSLM1); break;
8771 case 'z': USE_BITS (OP_MASK_RZ, OP_SH_RZ); break;
8772 case 'Z': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
8773 case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
8774 case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
8775 case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
8776
8777 default:
8778 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8779 c, opc->name, opc->args);
8780 return 0;
8781 }
8782 break;
8783 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8784 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8785 case 'A': break;
8786 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
8787 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
8788 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8789 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8790 case 'F': break;
8791 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8792 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8793 case 'I': break;
8794 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
8795 case 'K': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8796 case 'L': break;
8797 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
8798 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
8799 case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
8800 case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
8801 USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8802 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
8803 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8804 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8805 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8806 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8807 case 'X': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
8808 case 'Y': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
8809 case 'Z': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
8810 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
8811 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8812 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
8813 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8814 case 'f': break;
8815 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
8816 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8817 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8818 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
8819 case 'l': break;
8820 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8821 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
8822 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8823 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8824 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8825 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8826 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8827 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8828 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8829 case 'x': break;
8830 case 'z': break;
8831 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8832 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8833 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8834 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8835 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8836 case '[': break;
8837 case ']': break;
8838 case '1': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8839 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8840 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8841 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8842 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8843 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8844 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8845 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8846 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8847 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8848 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8849 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8850 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8851 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8852 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8853 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8854 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8855 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8856 default:
8857 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8858 c, opc->name, opc->args);
8859 return 0;
8860 }
8861#undef USE_BITS
8862 if (used_bits != 0xffffffff)
8863 {
8864 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8865 ~used_bits & 0xffffffff, opc->name, opc->args);
8866 return 0;
8867 }
8868 return 1;
8869}
8870
8871/* UDI immediates. */
8872struct mips_immed {
8873 char type;
8874 unsigned int shift;
8875 unsigned long mask;
8876 const char * desc;
8877};
8878
8879static const struct mips_immed mips_immed[] = {
8880 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8881 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8882 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8883 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8884 { 0,0,0,0 }
8885};
8886
8887/* Check whether an odd floating-point register is allowed. */
8888static int
8889mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8890{
8891 const char *s = insn->name;
8892
8893 if (insn->pinfo == INSN_MACRO)
8894 /* Let a macro pass, we'll catch it later when it is expanded. */
8895 return 1;
8896
8897 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8898 {
8899 /* Allow odd registers for single-precision ops. */
8900 switch (insn->pinfo & (FP_S | FP_D))
8901 {
8902 case FP_S:
8903 case 0:
8904 return 1; /* both single precision - ok */
8905 case FP_D:
8906 return 0; /* both double precision - fail */
8907 default:
8908 break;
8909 }
8910
8911 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8912 s = strchr (insn->name, '.');
8913 if (argnum == 2)
8914 s = s != NULL ? strchr (s + 1, '.') : NULL;
8915 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8916 }
8917
8918 /* Single-precision coprocessor loads and moves are OK too. */
8919 if ((insn->pinfo & FP_S)
8920 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8921 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8922 return 1;
8923
8924 return 0;
8925}
8926
8927/* This routine assembles an instruction into its binary format. As a
8928 side effect, it sets one of the global variables imm_reloc or
8929 offset_reloc to the type of relocation to do if one of the operands
8930 is an address expression. */
8931
8932static void
8933mips_ip (char *str, struct mips_cl_insn *ip)
8934{
8935 char *s;
8936 const char *args;
8937 char c = 0;
8938 struct mips_opcode *insn;
8939 char *argsStart;
8940 unsigned int regno;
8941 unsigned int lastregno;
8942 unsigned int lastpos = 0;
8943 unsigned int limlo, limhi;
8944 char *s_reset;
8945 char save_c = 0;
8946 offsetT min_range, max_range;
8947 int argnum;
8948 unsigned int rtype;
8949
8950 insn_error = NULL;
8951
8952 /* If the instruction contains a '.', we first try to match an instruction
8953 including the '.'. Then we try again without the '.'. */
8954 insn = NULL;
8955 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8956 continue;
8957
8958 /* If we stopped on whitespace, then replace the whitespace with null for
8959 the call to hash_find. Save the character we replaced just in case we
8960 have to re-parse the instruction. */
8961 if (ISSPACE (*s))
8962 {
8963 save_c = *s;
8964 *s++ = '\0';
8965 }
8966
8967 insn = (struct mips_opcode *) hash_find (op_hash, str);
8968
8969 /* If we didn't find the instruction in the opcode table, try again, but
8970 this time with just the instruction up to, but not including the
8971 first '.'. */
8972 if (insn == NULL)
8973 {
8974 /* Restore the character we overwrite above (if any). */
8975 if (save_c)
8976 *(--s) = save_c;
8977
8978 /* Scan up to the first '.' or whitespace. */
8979 for (s = str;
8980 *s != '\0' && *s != '.' && !ISSPACE (*s);
8981 ++s)
8982 continue;
8983
8984 /* If we did not find a '.', then we can quit now. */
8985 if (*s != '.')
8986 {
8987 insn_error = _("Unrecognized opcode");
8988 return;
8989 }
8990
8991 /* Lookup the instruction in the hash table. */
8992 *s++ = '\0';
8993 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
8994 {
8995 insn_error = _("Unrecognized opcode");
8996 return;
8997 }
8998 }
8999
9000 argsStart = s;
9001 for (;;)
9002 {
9003 bfd_boolean ok;
9004
9005 gas_assert (strcmp (insn->name, str) == 0);
9006
9007 ok = is_opcode_valid (insn);
9008 if (! ok)
9009 {
9010 if (insn + 1 < &mips_opcodes[NUMOPCODES]
9011 && strcmp (insn->name, insn[1].name) == 0)
9012 {
9013 ++insn;
9014 continue;
9015 }
9016 else
9017 {
9018 if (!insn_error)
9019 {
9020 static char buf[100];
9021 sprintf (buf,
9022 _("opcode not supported on this processor: %s (%s)"),
9023 mips_cpu_info_from_arch (mips_opts.arch)->name,
9024 mips_cpu_info_from_isa (mips_opts.isa)->name);
9025 insn_error = buf;
9026 }
9027 if (save_c)
9028 *(--s) = save_c;
9029 return;
9030 }
9031 }
9032
9033 create_insn (ip, insn);
9034 insn_error = NULL;
9035 argnum = 1;
9036 lastregno = 0xffffffff;
9037 for (args = insn->args;; ++args)
9038 {
9039 int is_mdmx;
9040
9041 s += strspn (s, " \t");
9042 is_mdmx = 0;
9043 switch (*args)
9044 {
9045 case '\0': /* end of args */
9046 if (*s == '\0')
9047 return;
9048 break;
9049
9050 case '2': /* DSP 2-bit unsigned immediate in bit 11. */
9051 my_getExpression (&imm_expr, s);
9052 check_absolute_expr (ip, &imm_expr);
9053 if ((unsigned long) imm_expr.X_add_number != 1
9054 && (unsigned long) imm_expr.X_add_number != 3)
9055 {
9056 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
9057 (unsigned long) imm_expr.X_add_number);
9058 }
9059 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
9060 imm_expr.X_op = O_absent;
9061 s = expr_end;
9062 continue;
9063
9064 case '3': /* DSP 3-bit unsigned immediate in bit 21. */
9065 my_getExpression (&imm_expr, s);
9066 check_absolute_expr (ip, &imm_expr);
9067 if (imm_expr.X_add_number & ~OP_MASK_SA3)
9068 {
9069 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9070 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
9071 }
9072 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
9073 imm_expr.X_op = O_absent;
9074 s = expr_end;
9075 continue;
9076
9077 case '4': /* DSP 4-bit unsigned immediate in bit 21. */
9078 my_getExpression (&imm_expr, s);
9079 check_absolute_expr (ip, &imm_expr);
9080 if (imm_expr.X_add_number & ~OP_MASK_SA4)
9081 {
9082 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9083 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
9084 }
9085 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
9086 imm_expr.X_op = O_absent;
9087 s = expr_end;
9088 continue;
9089
9090 case '5': /* DSP 8-bit unsigned immediate in bit 16. */
9091 my_getExpression (&imm_expr, s);
9092 check_absolute_expr (ip, &imm_expr);
9093 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
9094 {
9095 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9096 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
9097 }
9098 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
9099 imm_expr.X_op = O_absent;
9100 s = expr_end;
9101 continue;
9102
9103 case '6': /* DSP 5-bit unsigned immediate in bit 21. */
9104 my_getExpression (&imm_expr, s);
9105 check_absolute_expr (ip, &imm_expr);
9106 if (imm_expr.X_add_number & ~OP_MASK_RS)
9107 {
9108 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9109 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
9110 }
9111 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
9112 imm_expr.X_op = O_absent;
9113 s = expr_end;
9114 continue;
9115
9116 case '7': /* Four DSP accumulators in bits 11,12. */
9117 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9118 s[3] >= '0' && s[3] <= '3')
9119 {
9120 regno = s[3] - '0';
9121 s += 4;
9122 INSERT_OPERAND (DSPACC, *ip, regno);
9123 continue;
9124 }
9125 else
9126 as_bad (_("Invalid dsp acc register"));
9127 break;
9128
9129 case '8': /* DSP 6-bit unsigned immediate in bit 11. */
9130 my_getExpression (&imm_expr, s);
9131 check_absolute_expr (ip, &imm_expr);
9132 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
9133 {
9134 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9135 OP_MASK_WRDSP,
9136 (unsigned long) imm_expr.X_add_number);
9137 }
9138 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
9139 imm_expr.X_op = O_absent;
9140 s = expr_end;
9141 continue;
9142
9143 case '9': /* Four DSP accumulators in bits 21,22. */
9144 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9145 s[3] >= '0' && s[3] <= '3')
9146 {
9147 regno = s[3] - '0';
9148 s += 4;
9149 INSERT_OPERAND (DSPACC_S, *ip, regno);
9150 continue;
9151 }
9152 else
9153 as_bad (_("Invalid dsp acc register"));
9154 break;
9155
9156 case '0': /* DSP 6-bit signed immediate in bit 20. */
9157 my_getExpression (&imm_expr, s);
9158 check_absolute_expr (ip, &imm_expr);
9159 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
9160 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
9161 if (imm_expr.X_add_number < min_range ||
9162 imm_expr.X_add_number > max_range)
9163 {
9164 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9165 (long) min_range, (long) max_range,
9166 (long) imm_expr.X_add_number);
9167 }
9168 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
9169 imm_expr.X_op = O_absent;
9170 s = expr_end;
9171 continue;
9172
9173 case '\'': /* DSP 6-bit unsigned immediate in bit 16. */
9174 my_getExpression (&imm_expr, s);
9175 check_absolute_expr (ip, &imm_expr);
9176 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
9177 {
9178 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
9179 OP_MASK_RDDSP,
9180 (unsigned long) imm_expr.X_add_number);
9181 }
9182 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
9183 imm_expr.X_op = O_absent;
9184 s = expr_end;
9185 continue;
9186
9187 case ':': /* DSP 7-bit signed immediate in bit 19. */
9188 my_getExpression (&imm_expr, s);
9189 check_absolute_expr (ip, &imm_expr);
9190 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
9191 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
9192 if (imm_expr.X_add_number < min_range ||
9193 imm_expr.X_add_number > max_range)
9194 {
9195 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9196 (long) min_range, (long) max_range,
9197 (long) imm_expr.X_add_number);
9198 }
9199 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
9200 imm_expr.X_op = O_absent;
9201 s = expr_end;
9202 continue;
9203
9204 case '@': /* DSP 10-bit signed immediate in bit 16. */
9205 my_getExpression (&imm_expr, s);
9206 check_absolute_expr (ip, &imm_expr);
9207 min_range = -((OP_MASK_IMM10 + 1) >> 1);
9208 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
9209 if (imm_expr.X_add_number < min_range ||
9210 imm_expr.X_add_number > max_range)
9211 {
9212 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
9213 (long) min_range, (long) max_range,
9214 (long) imm_expr.X_add_number);
9215 }
9216 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
9217 imm_expr.X_op = O_absent;
9218 s = expr_end;
9219 continue;
9220
9221 case '!': /* MT usermode flag bit. */
9222 my_getExpression (&imm_expr, s);
9223 check_absolute_expr (ip, &imm_expr);
9224 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
9225 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
9226 (unsigned long) imm_expr.X_add_number);
9227 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
9228 imm_expr.X_op = O_absent;
9229 s = expr_end;
9230 continue;
9231
9232 case '$': /* MT load high flag bit. */
9233 my_getExpression (&imm_expr, s);
9234 check_absolute_expr (ip, &imm_expr);
9235 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
9236 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
9237 (unsigned long) imm_expr.X_add_number);
9238 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
9239 imm_expr.X_op = O_absent;
9240 s = expr_end;
9241 continue;
9242
9243 case '*': /* Four DSP accumulators in bits 18,19. */
9244 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9245 s[3] >= '0' && s[3] <= '3')
9246 {
9247 regno = s[3] - '0';
9248 s += 4;
9249 INSERT_OPERAND (MTACC_T, *ip, regno);
9250 continue;
9251 }
9252 else
9253 as_bad (_("Invalid dsp/smartmips acc register"));
9254 break;
9255
9256 case '&': /* Four DSP accumulators in bits 13,14. */
9257 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
9258 s[3] >= '0' && s[3] <= '3')
9259 {
9260 regno = s[3] - '0';
9261 s += 4;
9262 INSERT_OPERAND (MTACC_D, *ip, regno);
9263 continue;
9264 }
9265 else
9266 as_bad (_("Invalid dsp/smartmips acc register"));
9267 break;
9268
9269 case ',':
9270 ++argnum;
9271 if (*s++ == *args)
9272 continue;
9273 s--;
9274 switch (*++args)
9275 {
9276 case 'r':
9277 case 'v':
9278 INSERT_OPERAND (RS, *ip, lastregno);
9279 continue;
9280
9281 case 'w':
9282 INSERT_OPERAND (RT, *ip, lastregno);
9283 continue;
9284
9285 case 'W':
9286 INSERT_OPERAND (FT, *ip, lastregno);
9287 continue;
9288
9289 case 'V':
9290 INSERT_OPERAND (FS, *ip, lastregno);
9291 continue;
9292 }
9293 break;
9294
9295 case '(':
9296 /* Handle optional base register.
9297 Either the base register is omitted or
9298 we must have a left paren. */
9299 /* This is dependent on the next operand specifier
9300 is a base register specification. */
9301 gas_assert (args[1] == 'b');
9302 if (*s == '\0')
9303 return;
9304
9305 case ')': /* These must match exactly. */
9306 case '[':
9307 case ']':
9308 if (*s++ == *args)
9309 continue;
9310 break;
9311
9312 case '+': /* Opcode extension character. */
9313 switch (*++args)
9314 {
9315 case '1': /* UDI immediates. */
9316 case '2':
9317 case '3':
9318 case '4':
9319 {
9320 const struct mips_immed *imm = mips_immed;
9321
9322 while (imm->type && imm->type != *args)
9323 ++imm;
9324 if (! imm->type)
9325 internalError ();
9326 my_getExpression (&imm_expr, s);
9327 check_absolute_expr (ip, &imm_expr);
9328 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9329 {
9330 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9331 imm->desc ? imm->desc : ip->insn_mo->name,
9332 (unsigned long) imm_expr.X_add_number,
9333 (unsigned long) imm_expr.X_add_number);
9334 imm_expr.X_add_number &= imm->mask;
9335 }
9336 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9337 << imm->shift);
9338 imm_expr.X_op = O_absent;
9339 s = expr_end;
9340 }
9341 continue;
9342
9343 case 'A': /* ins/ext position, becomes LSB. */
9344 limlo = 0;
9345 limhi = 31;
9346 goto do_lsb;
9347 case 'E':
9348 limlo = 32;
9349 limhi = 63;
9350 goto do_lsb;
9351 do_lsb:
9352 my_getExpression (&imm_expr, s);
9353 check_absolute_expr (ip, &imm_expr);
9354 if ((unsigned long) imm_expr.X_add_number < limlo
9355 || (unsigned long) imm_expr.X_add_number > limhi)
9356 {
9357 as_bad (_("Improper position (%lu)"),
9358 (unsigned long) imm_expr.X_add_number);
9359 imm_expr.X_add_number = limlo;
9360 }
9361 lastpos = imm_expr.X_add_number;
9362 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9363 imm_expr.X_op = O_absent;
9364 s = expr_end;
9365 continue;
9366
9367 case 'B': /* ins size, becomes MSB. */
9368 limlo = 1;
9369 limhi = 32;
9370 goto do_msb;
9371 case 'F':
9372 limlo = 33;
9373 limhi = 64;
9374 goto do_msb;
9375 do_msb:
9376 my_getExpression (&imm_expr, s);
9377 check_absolute_expr (ip, &imm_expr);
9378 /* Check for negative input so that small negative numbers
9379 will not succeed incorrectly. The checks against
9380 (pos+size) transitively check "size" itself,
9381 assuming that "pos" is reasonable. */
9382 if ((long) imm_expr.X_add_number < 0
9383 || ((unsigned long) imm_expr.X_add_number
9384 + lastpos) < limlo
9385 || ((unsigned long) imm_expr.X_add_number
9386 + lastpos) > limhi)
9387 {
9388 as_bad (_("Improper insert size (%lu, position %lu)"),
9389 (unsigned long) imm_expr.X_add_number,
9390 (unsigned long) lastpos);
9391 imm_expr.X_add_number = limlo - lastpos;
9392 }
9393 INSERT_OPERAND (INSMSB, *ip,
9394 lastpos + imm_expr.X_add_number - 1);
9395 imm_expr.X_op = O_absent;
9396 s = expr_end;
9397 continue;
9398
9399 case 'C': /* ext size, becomes MSBD. */
9400 limlo = 1;
9401 limhi = 32;
9402 goto do_msbd;
9403 case 'G':
9404 limlo = 33;
9405 limhi = 64;
9406 goto do_msbd;
9407 case 'H':
9408 limlo = 33;
9409 limhi = 64;
9410 goto do_msbd;
9411 do_msbd:
9412 my_getExpression (&imm_expr, s);
9413 check_absolute_expr (ip, &imm_expr);
9414 /* Check for negative input so that small negative numbers
9415 will not succeed incorrectly. The checks against
9416 (pos+size) transitively check "size" itself,
9417 assuming that "pos" is reasonable. */
9418 if ((long) imm_expr.X_add_number < 0
9419 || ((unsigned long) imm_expr.X_add_number
9420 + lastpos) < limlo
9421 || ((unsigned long) imm_expr.X_add_number
9422 + lastpos) > limhi)
9423 {
9424 as_bad (_("Improper extract size (%lu, position %lu)"),
9425 (unsigned long) imm_expr.X_add_number,
9426 (unsigned long) lastpos);
9427 imm_expr.X_add_number = limlo - lastpos;
9428 }
9429 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
9430 imm_expr.X_op = O_absent;
9431 s = expr_end;
9432 continue;
9433
9434 case 'D':
9435 /* +D is for disassembly only; never match. */
9436 break;
9437
9438 case 'I':
9439 /* "+I" is like "I", except that imm2_expr is used. */
9440 my_getExpression (&imm2_expr, s);
9441 if (imm2_expr.X_op != O_big
9442 && imm2_expr.X_op != O_constant)
9443 insn_error = _("absolute expression required");
9444 if (HAVE_32BIT_GPRS)
9445 normalize_constant_expr (&imm2_expr);
9446 s = expr_end;
9447 continue;
9448
9449 case 'T': /* Coprocessor register. */
9450 /* +T is for disassembly only; never match. */
9451 break;
9452
9453 case 't': /* Coprocessor register number. */
9454 if (s[0] == '$' && ISDIGIT (s[1]))
9455 {
9456 ++s;
9457 regno = 0;
9458 do
9459 {
9460 regno *= 10;
9461 regno += *s - '0';
9462 ++s;
9463 }
9464 while (ISDIGIT (*s));
9465 if (regno > 31)
9466 as_bad (_("Invalid register number (%d)"), regno);
9467 else
9468 {
9469 INSERT_OPERAND (RT, *ip, regno);
9470 continue;
9471 }
9472 }
9473 else
9474 as_bad (_("Invalid coprocessor 0 register number"));
9475 break;
9476
9477 case 'x':
9478 /* bbit[01] and bbit[01]32 bit index. Give error if index
9479 is not in the valid range. */
9480 my_getExpression (&imm_expr, s);
9481 check_absolute_expr (ip, &imm_expr);
9482 if ((unsigned) imm_expr.X_add_number > 31)
9483 {
9484 as_bad (_("Improper bit index (%lu)"),
9485 (unsigned long) imm_expr.X_add_number);
9486 imm_expr.X_add_number = 0;
9487 }
9488 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number);
9489 imm_expr.X_op = O_absent;
9490 s = expr_end;
9491 continue;
9492
9493 case 'X':
9494 /* bbit[01] bit index when bbit is used but we generate
9495 bbit[01]32 because the index is over 32. Move to the
9496 next candidate if index is not in the valid range. */
9497 my_getExpression (&imm_expr, s);
9498 check_absolute_expr (ip, &imm_expr);
9499 if ((unsigned) imm_expr.X_add_number < 32
9500 || (unsigned) imm_expr.X_add_number > 63)
9501 break;
9502 INSERT_OPERAND (BBITIND, *ip, imm_expr.X_add_number - 32);
9503 imm_expr.X_op = O_absent;
9504 s = expr_end;
9505 continue;
9506
9507 case 'p':
9508 /* cins, cins32, exts and exts32 position field. Give error
9509 if it's not in the valid range. */
9510 my_getExpression (&imm_expr, s);
9511 check_absolute_expr (ip, &imm_expr);
9512 if ((unsigned) imm_expr.X_add_number > 31)
9513 {
9514 as_bad (_("Improper position (%lu)"),
9515 (unsigned long) imm_expr.X_add_number);
9516 imm_expr.X_add_number = 0;
9517 }
9518 /* Make the pos explicit to simplify +S. */
9519 lastpos = imm_expr.X_add_number + 32;
9520 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number);
9521 imm_expr.X_op = O_absent;
9522 s = expr_end;
9523 continue;
9524
9525 case 'P':
9526 /* cins, cins32, exts and exts32 position field. Move to
9527 the next candidate if it's not in the valid range. */
9528 my_getExpression (&imm_expr, s);
9529 check_absolute_expr (ip, &imm_expr);
9530 if ((unsigned) imm_expr.X_add_number < 32
9531 || (unsigned) imm_expr.X_add_number > 63)
9532 break;
9533 lastpos = imm_expr.X_add_number;
9534 INSERT_OPERAND (CINSPOS, *ip, imm_expr.X_add_number - 32);
9535 imm_expr.X_op = O_absent;
9536 s = expr_end;
9537 continue;
9538
9539 case 's':
9540 /* cins and exts length-minus-one field. */
9541 my_getExpression (&imm_expr, s);
9542 check_absolute_expr (ip, &imm_expr);
9543 if ((unsigned long) imm_expr.X_add_number > 31)
9544 {
9545 as_bad (_("Improper size (%lu)"),
9546 (unsigned long) imm_expr.X_add_number);
9547 imm_expr.X_add_number = 0;
9548 }
9549 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9550 imm_expr.X_op = O_absent;
9551 s = expr_end;
9552 continue;
9553
9554 case 'S':
9555 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9556 length-minus-one field. */
9557 my_getExpression (&imm_expr, s);
9558 check_absolute_expr (ip, &imm_expr);
9559 if ((long) imm_expr.X_add_number < 0
9560 || (unsigned long) imm_expr.X_add_number + lastpos > 63)
9561 {
9562 as_bad (_("Improper size (%lu)"),
9563 (unsigned long) imm_expr.X_add_number);
9564 imm_expr.X_add_number = 0;
9565 }
9566 INSERT_OPERAND (CINSLM1, *ip, imm_expr.X_add_number);
9567 imm_expr.X_op = O_absent;
9568 s = expr_end;
9569 continue;
9570
9571 case 'Q':
9572 /* seqi/snei immediate field. */
9573 my_getExpression (&imm_expr, s);
9574 check_absolute_expr (ip, &imm_expr);
9575 if ((long) imm_expr.X_add_number < -512
9576 || (long) imm_expr.X_add_number >= 512)
9577 {
9578 as_bad (_("Improper immediate (%ld)"),
9579 (long) imm_expr.X_add_number);
9580 imm_expr.X_add_number = 0;
9581 }
9582 INSERT_OPERAND (SEQI, *ip, imm_expr.X_add_number);
9583 imm_expr.X_op = O_absent;
9584 s = expr_end;
9585 continue;
9586
9587 case 'a': /* 8-bit signed offset in bit 6 */
9588 my_getExpression (&imm_expr, s);
9589 check_absolute_expr (ip, &imm_expr);
9590 min_range = -((OP_MASK_OFFSET_A + 1) >> 1);
9591 max_range = ((OP_MASK_OFFSET_A + 1) >> 1) - 1;
9592 if (imm_expr.X_add_number < min_range
9593 || imm_expr.X_add_number > max_range)
9594 {
9595 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9596 (long) min_range, (long) max_range,
9597 (long) imm_expr.X_add_number);
9598 }
9599 INSERT_OPERAND (OFFSET_A, *ip, imm_expr.X_add_number);
9600 imm_expr.X_op = O_absent;
9601 s = expr_end;
9602 continue;
9603
9604 case 'b': /* 8-bit signed offset in bit 3 */
9605 my_getExpression (&imm_expr, s);
9606 check_absolute_expr (ip, &imm_expr);
9607 min_range = -((OP_MASK_OFFSET_B + 1) >> 1);
9608 max_range = ((OP_MASK_OFFSET_B + 1) >> 1) - 1;
9609 if (imm_expr.X_add_number < min_range
9610 || imm_expr.X_add_number > max_range)
9611 {
9612 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9613 (long) min_range, (long) max_range,
9614 (long) imm_expr.X_add_number);
9615 }
9616 INSERT_OPERAND (OFFSET_B, *ip, imm_expr.X_add_number);
9617 imm_expr.X_op = O_absent;
9618 s = expr_end;
9619 continue;
9620
9621 case 'c': /* 9-bit signed offset in bit 6 */
9622 my_getExpression (&imm_expr, s);
9623 check_absolute_expr (ip, &imm_expr);
9624 min_range = -((OP_MASK_OFFSET_C + 1) >> 1);
9625 max_range = ((OP_MASK_OFFSET_C + 1) >> 1) - 1;
9626 /* We check the offset range before adjusted. */
9627 min_range <<= 4;
9628 max_range <<= 4;
9629 if (imm_expr.X_add_number < min_range
9630 || imm_expr.X_add_number > max_range)
9631 {
9632 as_bad (_("Offset not in range %ld..%ld (%ld)"),
9633 (long) min_range, (long) max_range,
9634 (long) imm_expr.X_add_number);
9635 }
9636 if (imm_expr.X_add_number & 0xf)
9637 {
9638 as_bad (_("Offset not 16 bytes alignment (%ld)"),
9639 (long) imm_expr.X_add_number);
9640 }
9641 /* Right shift 4 bits to adjust the offset operand. */
9642 INSERT_OPERAND (OFFSET_C, *ip, imm_expr.X_add_number >> 4);
9643 imm_expr.X_op = O_absent;
9644 s = expr_end;
9645 continue;
9646
9647 case 'z':
9648 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno))
9649 break;
9650 if (regno == AT && mips_opts.at)
9651 {
9652 if (mips_opts.at == ATREG)
9653 as_warn (_("used $at without \".set noat\""));
9654 else
9655 as_warn (_("used $%u with \".set at=$%u\""),
9656 regno, mips_opts.at);
9657 }
9658 INSERT_OPERAND (RZ, *ip, regno);
9659 continue;
9660
9661 case 'Z':
9662 if (!reg_lookup (&s, RTYPE_FPU, &regno))
9663 break;
9664 INSERT_OPERAND (FZ, *ip, regno);
9665 continue;
9666
9667 default:
9668 as_bad (_("Internal error: bad mips opcode "
9669 "(unknown extension operand type `+%c'): %s %s"),
9670 *args, insn->name, insn->args);
9671 /* Further processing is fruitless. */
9672 return;
9673 }
9674 break;
9675
9676 case '<': /* must be at least one digit */
9677 /*
9678 * According to the manual, if the shift amount is greater
9679 * than 31 or less than 0, then the shift amount should be
9680 * mod 32. In reality the mips assembler issues an error.
9681 * We issue a warning and mask out all but the low 5 bits.
9682 */
9683 my_getExpression (&imm_expr, s);
9684 check_absolute_expr (ip, &imm_expr);
9685 if ((unsigned long) imm_expr.X_add_number > 31)
9686 as_warn (_("Improper shift amount (%lu)"),
9687 (unsigned long) imm_expr.X_add_number);
9688 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9689 imm_expr.X_op = O_absent;
9690 s = expr_end;
9691 continue;
9692
9693 case '>': /* shift amount minus 32 */
9694 my_getExpression (&imm_expr, s);
9695 check_absolute_expr (ip, &imm_expr);
9696 if ((unsigned long) imm_expr.X_add_number < 32
9697 || (unsigned long) imm_expr.X_add_number > 63)
9698 break;
9699 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
9700 imm_expr.X_op = O_absent;
9701 s = expr_end;
9702 continue;
9703
9704 case 'k': /* CACHE code. */
9705 case 'h': /* PREFX code. */
9706 case '1': /* SYNC type. */
9707 my_getExpression (&imm_expr, s);
9708 check_absolute_expr (ip, &imm_expr);
9709 if ((unsigned long) imm_expr.X_add_number > 31)
9710 as_warn (_("Invalid value for `%s' (%lu)"),
9711 ip->insn_mo->name,
9712 (unsigned long) imm_expr.X_add_number);
9713 if (*args == 'k')
9714 {
9715 if (mips_fix_cn63xxp1 && strcmp ("pref", insn->name) == 0)
9716 switch (imm_expr.X_add_number)
9717 {
9718 case 5:
9719 case 25:
9720 case 26:
9721 case 27:
9722 case 28:
9723 case 29:
9724 case 30:
9725 case 31: /* These are ok. */
9726 break;
9727
9728 default: /* The rest must be changed to 28. */
9729 imm_expr.X_add_number = 28;
9730 break;
9731 }
9732 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
9733 }
9734 else if (*args == 'h')
9735 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9736 else
9737 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
9738 imm_expr.X_op = O_absent;
9739 s = expr_end;
9740 continue;
9741
9742 case 'c': /* BREAK code. */
9743 my_getExpression (&imm_expr, s);
9744 check_absolute_expr (ip, &imm_expr);
9745 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9746 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9747 ip->insn_mo->name,
9748 (unsigned long) imm_expr.X_add_number);
9749 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9750 imm_expr.X_op = O_absent;
9751 s = expr_end;
9752 continue;
9753
9754 case 'q': /* Lower BREAK code. */
9755 my_getExpression (&imm_expr, s);
9756 check_absolute_expr (ip, &imm_expr);
9757 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9758 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9759 ip->insn_mo->name,
9760 (unsigned long) imm_expr.X_add_number);
9761 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9762 imm_expr.X_op = O_absent;
9763 s = expr_end;
9764 continue;
9765
9766 case 'B': /* 20-bit SYSCALL/BREAK code. */
9767 my_getExpression (&imm_expr, s);
9768 check_absolute_expr (ip, &imm_expr);
9769 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9770 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9771 ip->insn_mo->name,
9772 (unsigned long) imm_expr.X_add_number);
9773 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9774 imm_expr.X_op = O_absent;
9775 s = expr_end;
9776 continue;
9777
9778 case 'C': /* Coprocessor code. */
9779 my_getExpression (&imm_expr, s);
9780 check_absolute_expr (ip, &imm_expr);
9781 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
9782 {
9783 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9784 (unsigned long) imm_expr.X_add_number);
9785 imm_expr.X_add_number &= OP_MASK_COPZ;
9786 }
9787 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
9788 imm_expr.X_op = O_absent;
9789 s = expr_end;
9790 continue;
9791
9792 case 'J': /* 19-bit WAIT code. */
9793 my_getExpression (&imm_expr, s);
9794 check_absolute_expr (ip, &imm_expr);
9795 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9796 {
9797 as_warn (_("Illegal 19-bit code (%lu)"),
9798 (unsigned long) imm_expr.X_add_number);
9799 imm_expr.X_add_number &= OP_MASK_CODE19;
9800 }
9801 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9802 imm_expr.X_op = O_absent;
9803 s = expr_end;
9804 continue;
9805
9806 case 'P': /* Performance register. */
9807 my_getExpression (&imm_expr, s);
9808 check_absolute_expr (ip, &imm_expr);
9809 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9810 as_warn (_("Invalid performance register (%lu)"),
9811 (unsigned long) imm_expr.X_add_number);
9812 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9813 imm_expr.X_op = O_absent;
9814 s = expr_end;
9815 continue;
9816
9817 case 'G': /* Coprocessor destination register. */
9818 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9819 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, &regno);
9820 else
9821 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
9822 INSERT_OPERAND (RD, *ip, regno);
9823 if (ok)
9824 {
9825 lastregno = regno;
9826 continue;
9827 }
9828 else
9829 break;
9830
9831 case 'b': /* Base register. */
9832 case 'd': /* Destination register. */
9833 case 's': /* Source register. */
9834 case 't': /* Target register. */
9835 case 'r': /* Both target and source. */
9836 case 'v': /* Both dest and source. */
9837 case 'w': /* Both dest and target. */
9838 case 'E': /* Coprocessor target register. */
9839 case 'K': /* RDHWR destination register. */
9840 case 'x': /* Ignore register name. */
9841 case 'z': /* Must be zero register. */
9842 case 'U': /* Destination register (CLO/CLZ). */
9843 case 'g': /* Coprocessor destination register. */
9844 s_reset = s;
9845 if (*args == 'E' || *args == 'K')
9846 ok = reg_lookup (&s, RTYPE_NUM, &regno);
9847 else
9848 {
9849 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
9850 if (regno == AT && mips_opts.at)
9851 {
9852 if (mips_opts.at == ATREG)
9853 as_warn (_("Used $at without \".set noat\""));
9854 else
9855 as_warn (_("Used $%u with \".set at=$%u\""),
9856 regno, mips_opts.at);
9857 }
9858 }
9859 if (ok)
9860 {
9861 c = *args;
9862 if (*s == ' ')
9863 ++s;
9864 if (args[1] != *s)
9865 {
9866 if (c == 'r' || c == 'v' || c == 'w')
9867 {
9868 regno = lastregno;
9869 s = s_reset;
9870 ++args;
9871 }
9872 }
9873 /* 'z' only matches $0. */
9874 if (c == 'z' && regno != 0)
9875 break;
9876
9877 if (c == 's' && !strncmp (ip->insn_mo->name, "jalr", 4))
9878 {
9879 if (regno == lastregno)
9880 {
9881 insn_error
9882 = _("Source and destination must be different");
9883 continue;
9884 }
9885 if (regno == 31 && lastregno == 0xffffffff)
9886 {
9887 insn_error
9888 = _("A destination register must be supplied");
9889 continue;
9890 }
9891 }
9892 /* Now that we have assembled one operand, we use the args
9893 string to figure out where it goes in the instruction. */
9894 switch (c)
9895 {
9896 case 'r':
9897 case 's':
9898 case 'v':
9899 case 'b':
9900 INSERT_OPERAND (RS, *ip, regno);
9901 break;
9902 case 'd':
9903 case 'K':
9904 case 'g':
9905 INSERT_OPERAND (RD, *ip, regno);
9906 break;
9907 case 'U':
9908 INSERT_OPERAND (RD, *ip, regno);
9909 INSERT_OPERAND (RT, *ip, regno);
9910 break;
9911 case 'w':
9912 case 't':
9913 case 'E':
9914 INSERT_OPERAND (RT, *ip, regno);
9915 break;
9916 case 'x':
9917 /* This case exists because on the r3000 trunc
9918 expands into a macro which requires a gp
9919 register. On the r6000 or r4000 it is
9920 assembled into a single instruction which
9921 ignores the register. Thus the insn version
9922 is MIPS_ISA2 and uses 'x', and the macro
9923 version is MIPS_ISA1 and uses 't'. */
9924 break;
9925 case 'z':
9926 /* This case is for the div instruction, which
9927 acts differently if the destination argument
9928 is $0. This only matches $0, and is checked
9929 outside the switch. */
9930 break;
9931 }
9932 lastregno = regno;
9933 continue;
9934 }
9935 switch (*args++)
9936 {
9937 case 'r':
9938 case 'v':
9939 INSERT_OPERAND (RS, *ip, lastregno);
9940 continue;
9941 case 'w':
9942 INSERT_OPERAND (RT, *ip, lastregno);
9943 continue;
9944 }
9945 break;
9946
9947 case 'O': /* MDMX alignment immediate constant. */
9948 my_getExpression (&imm_expr, s);
9949 check_absolute_expr (ip, &imm_expr);
9950 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9951 as_warn (_("Improper align amount (%ld), using low bits"),
9952 (long) imm_expr.X_add_number);
9953 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
9954 imm_expr.X_op = O_absent;
9955 s = expr_end;
9956 continue;
9957
9958 case 'Q': /* MDMX vector, element sel, or const. */
9959 if (s[0] != '$')
9960 {
9961 /* MDMX Immediate. */
9962 my_getExpression (&imm_expr, s);
9963 check_absolute_expr (ip, &imm_expr);
9964 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9965 as_warn (_("Invalid MDMX Immediate (%ld)"),
9966 (long) imm_expr.X_add_number);
9967 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
9968 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9969 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9970 else
9971 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9972 imm_expr.X_op = O_absent;
9973 s = expr_end;
9974 continue;
9975 }
9976 /* Not MDMX Immediate. Fall through. */
9977 case 'X': /* MDMX destination register. */
9978 case 'Y': /* MDMX source register. */
9979 case 'Z': /* MDMX target register. */
9980 is_mdmx = 1;
9981 case 'D': /* Floating point destination register. */
9982 case 'S': /* Floating point source register. */
9983 case 'T': /* Floating point target register. */
9984 case 'R': /* Floating point source register. */
9985 case 'V':
9986 case 'W':
9987 rtype = RTYPE_FPU;
9988 if (is_mdmx
9989 || (mips_opts.ase_mdmx
9990 && (ip->insn_mo->pinfo & FP_D)
9991 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9992 | INSN_COPROC_MEMORY_DELAY
9993 | INSN_LOAD_COPROC_DELAY
9994 | INSN_LOAD_MEMORY_DELAY
9995 | INSN_STORE_MEMORY))))
9996 rtype |= RTYPE_VEC;
9997 s_reset = s;
9998 if (reg_lookup (&s, rtype, &regno))
9999 {
10000 if ((regno & 1) != 0
10001 && HAVE_32BIT_FPRS
10002 && !mips_oddfpreg_ok (ip->insn_mo, argnum))
10003 as_warn (_("Float register should be even, was %d"),
10004 regno);
10005
10006 c = *args;
10007 if (*s == ' ')
10008 ++s;
10009 if (args[1] != *s)
10010 {
10011 if (c == 'V' || c == 'W')
10012 {
10013 regno = lastregno;
10014 s = s_reset;
10015 ++args;
10016 }
10017 }
10018 switch (c)
10019 {
10020 case 'D':
10021 case 'X':
10022 INSERT_OPERAND (FD, *ip, regno);
10023 break;
10024 case 'V':
10025 case 'S':
10026 case 'Y':
10027 INSERT_OPERAND (FS, *ip, regno);
10028 break;
10029 case 'Q':
10030 /* This is like 'Z', but also needs to fix the MDMX
10031 vector/scalar select bits. Note that the
10032 scalar immediate case is handled above. */
10033 if (*s == '[')
10034 {
10035 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));
10036 int max_el = (is_qh ? 3 : 7);
10037 s++;
10038 my_getExpression(&imm_expr, s);
10039 check_absolute_expr (ip, &imm_expr);
10040 s = expr_end;
10041 if (imm_expr.X_add_number > max_el)
10042 as_bad (_("Bad element selector %ld"),
10043 (long) imm_expr.X_add_number);
10044 imm_expr.X_add_number &= max_el;
10045 ip->insn_opcode |= (imm_expr.X_add_number
10046 << (OP_SH_VSEL +
10047 (is_qh ? 2 : 1)));
10048 imm_expr.X_op = O_absent;
10049 if (*s != ']')
10050 as_warn (_("Expecting ']' found '%s'"), s);
10051 else
10052 s++;
10053 }
10054 else
10055 {
10056 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
10057 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
10058 << OP_SH_VSEL);
10059 else
10060 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
10061 OP_SH_VSEL);
10062 }
10063 /* Fall through. */
10064 case 'W':
10065 case 'T':
10066 case 'Z':
10067 INSERT_OPERAND (FT, *ip, regno);
10068 break;
10069 case 'R':
10070 INSERT_OPERAND (FR, *ip, regno);
10071 break;
10072 }
10073 lastregno = regno;
10074 continue;
10075 }
10076
10077 switch (*args++)
10078 {
10079 case 'V':
10080 INSERT_OPERAND (FS, *ip, lastregno);
10081 continue;
10082 case 'W':
10083 INSERT_OPERAND (FT, *ip, lastregno);
10084 continue;
10085 }
10086 break;
10087
10088 case 'I':
10089 my_getExpression (&imm_expr, s);
10090 if (imm_expr.X_op != O_big
10091 && imm_expr.X_op != O_constant)
10092 insn_error = _("absolute expression required");
10093 if (HAVE_32BIT_GPRS)
10094 normalize_constant_expr (&imm_expr);
10095 s = expr_end;
10096 continue;
10097
10098 case 'A':
10099 my_getExpression (&offset_expr, s);
10100 normalize_address_expr (&offset_expr);
10101 *imm_reloc = BFD_RELOC_32;
10102 s = expr_end;
10103 continue;
10104
10105 case 'F':
10106 case 'L':
10107 case 'f':
10108 case 'l':
10109 {
10110 int f64;
10111 int using_gprs;
10112 char *save_in;
10113 char *err;
10114 unsigned char temp[8];
10115 int len;
10116 unsigned int length;
10117 segT seg;
10118 subsegT subseg;
10119 char *p;
10120
10121 /* These only appear as the last operand in an
10122 instruction, and every instruction that accepts
10123 them in any variant accepts them in all variants.
10124 This means we don't have to worry about backing out
10125 any changes if the instruction does not match.
10126
10127 The difference between them is the size of the
10128 floating point constant and where it goes. For 'F'
10129 and 'L' the constant is 64 bits; for 'f' and 'l' it
10130 is 32 bits. Where the constant is placed is based
10131 on how the MIPS assembler does things:
10132 F -- .rdata
10133 L -- .lit8
10134 f -- immediate value
10135 l -- .lit4
10136
10137 The .lit4 and .lit8 sections are only used if
10138 permitted by the -G argument.
10139
10140 The code below needs to know whether the target register
10141 is 32 or 64 bits wide. It relies on the fact 'f' and
10142 'F' are used with GPR-based instructions and 'l' and
10143 'L' are used with FPR-based instructions. */
10144
10145 f64 = *args == 'F' || *args == 'L';
10146 using_gprs = *args == 'F' || *args == 'f';
10147
10148 save_in = input_line_pointer;
10149 input_line_pointer = s;
10150 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
10151 length = len;
10152 s = input_line_pointer;
10153 input_line_pointer = save_in;
10154 if (err != NULL && *err != '\0')
10155 {
10156 as_bad (_("Bad floating point constant: %s"), err);
10157 memset (temp, '\0', sizeof temp);
10158 length = f64 ? 8 : 4;
10159 }
10160
10161 gas_assert (length == (unsigned) (f64 ? 8 : 4));
10162
10163 if (*args == 'f'
10164 || (*args == 'l'
10165 && (g_switch_value < 4
10166 || (temp[0] == 0 && temp[1] == 0)
10167 || (temp[2] == 0 && temp[3] == 0))))
10168 {
10169 imm_expr.X_op = O_constant;
10170 if (!target_big_endian)
10171 imm_expr.X_add_number = bfd_getl32 (temp);
10172 else
10173 imm_expr.X_add_number = bfd_getb32 (temp);
10174 }
10175 else if (length > 4
10176 && !mips_disable_float_construction
10177 /* Constants can only be constructed in GPRs and
10178 copied to FPRs if the GPRs are at least as wide
10179 as the FPRs. Force the constant into memory if
10180 we are using 64-bit FPRs but the GPRs are only
10181 32 bits wide. */
10182 && (using_gprs
10183 || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
10184 && ((temp[0] == 0 && temp[1] == 0)
10185 || (temp[2] == 0 && temp[3] == 0))
10186 && ((temp[4] == 0 && temp[5] == 0)
10187 || (temp[6] == 0 && temp[7] == 0)))
10188 {
10189 /* The value is simple enough to load with a couple of
10190 instructions. If using 32-bit registers, set
10191 imm_expr to the high order 32 bits and offset_expr to
10192 the low order 32 bits. Otherwise, set imm_expr to
10193 the entire 64 bit constant. */
10194 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
10195 {
10196 imm_expr.X_op = O_constant;
10197 offset_expr.X_op = O_constant;
10198 if (!target_big_endian)
10199 {
10200 imm_expr.X_add_number = bfd_getl32 (temp + 4);
10201 offset_expr.X_add_number = bfd_getl32 (temp);
10202 }
10203 else
10204 {
10205 imm_expr.X_add_number = bfd_getb32 (temp);
10206 offset_expr.X_add_number = bfd_getb32 (temp + 4);
10207 }
10208 if (offset_expr.X_add_number == 0)
10209 offset_expr.X_op = O_absent;
10210 }
10211 else if (sizeof (imm_expr.X_add_number) > 4)
10212 {
10213 imm_expr.X_op = O_constant;
10214 if (!target_big_endian)
10215 imm_expr.X_add_number = bfd_getl64 (temp);
10216 else
10217 imm_expr.X_add_number = bfd_getb64 (temp);
10218 }
10219 else
10220 {
10221 imm_expr.X_op = O_big;
10222 imm_expr.X_add_number = 4;
10223 if (!target_big_endian)
10224 {
10225 generic_bignum[0] = bfd_getl16 (temp);
10226 generic_bignum[1] = bfd_getl16 (temp + 2);
10227 generic_bignum[2] = bfd_getl16 (temp + 4);
10228 generic_bignum[3] = bfd_getl16 (temp + 6);
10229 }
10230 else
10231 {
10232 generic_bignum[0] = bfd_getb16 (temp + 6);
10233 generic_bignum[1] = bfd_getb16 (temp + 4);
10234 generic_bignum[2] = bfd_getb16 (temp + 2);
10235 generic_bignum[3] = bfd_getb16 (temp);
10236 }
10237 }
10238 }
10239 else
10240 {
10241 const char *newname;
10242 segT new_seg;
10243
10244 /* Switch to the right section. */
10245 seg = now_seg;
10246 subseg = now_subseg;
10247 switch (*args)
10248 {
10249 default: /* unused default case avoids warnings. */
10250 case 'L':
10251 newname = RDATA_SECTION_NAME;
10252 if (g_switch_value >= 8)
10253 newname = ".lit8";
10254 break;
10255 case 'F':
10256 newname = RDATA_SECTION_NAME;
10257 break;
10258 case 'l':
10259 gas_assert (g_switch_value >= 4);
10260 newname = ".lit4";
10261 break;
10262 }
10263 new_seg = subseg_new (newname, (subsegT) 0);
10264 if (IS_ELF)
10265 bfd_set_section_flags (stdoutput, new_seg,
10266 (SEC_ALLOC
10267 | SEC_LOAD
10268 | SEC_READONLY
10269 | SEC_DATA));
10270 frag_align (*args == 'l' ? 2 : 3, 0, 0);
10271 if (IS_ELF && strncmp (TARGET_OS, "elf", 3) != 0)
10272 record_alignment (new_seg, 4);
10273 else
10274 record_alignment (new_seg, *args == 'l' ? 2 : 3);
10275 if (seg == now_seg)
10276 as_bad (_("Can't use floating point insn in this section"));
10277
10278 /* Set the argument to the current address in the
10279 section. */
10280 offset_expr.X_op = O_symbol;
10281 offset_expr.X_add_symbol = symbol_temp_new_now ();
10282 offset_expr.X_add_number = 0;
10283
10284 /* Put the floating point number into the section. */
10285 p = frag_more ((int) length);
10286 memcpy (p, temp, length);
10287
10288 /* Switch back to the original section. */
10289 subseg_set (seg, subseg);
10290 }
10291 }
10292 continue;
10293
10294 case 'i': /* 16-bit unsigned immediate. */
10295 case 'j': /* 16-bit signed immediate. */
10296 *imm_reloc = BFD_RELOC_LO16;
10297 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0)
10298 {
10299 int more;
10300 offsetT minval, maxval;
10301
10302 more = (insn + 1 < &mips_opcodes[NUMOPCODES]
10303 && strcmp (insn->name, insn[1].name) == 0);
10304
10305 /* If the expression was written as an unsigned number,
10306 only treat it as signed if there are no more
10307 alternatives. */
10308 if (more
10309 && *args == 'j'
10310 && sizeof (imm_expr.X_add_number) <= 4
10311 && imm_expr.X_op == O_constant
10312 && imm_expr.X_add_number < 0
10313 && imm_expr.X_unsigned
10314 && HAVE_64BIT_GPRS)
10315 break;
10316
10317 /* For compatibility with older assemblers, we accept
10318 0x8000-0xffff as signed 16-bit numbers when only
10319 signed numbers are allowed. */
10320 if (*args == 'i')
10321 minval = 0, maxval = 0xffff;
10322 else if (more)
10323 minval = -0x8000, maxval = 0x7fff;
10324 else
10325 minval = -0x8000, maxval = 0xffff;
10326
10327 if (imm_expr.X_op != O_constant
10328 || imm_expr.X_add_number < minval
10329 || imm_expr.X_add_number > maxval)
10330 {
10331 if (more)
10332 break;
10333 if (imm_expr.X_op == O_constant
10334 || imm_expr.X_op == O_big)
10335 as_bad (_("Expression out of range"));
10336 }
10337 }
10338 s = expr_end;
10339 continue;
10340
10341 case 'o': /* 16-bit offset. */
10342 offset_reloc[0] = BFD_RELOC_LO16;
10343 offset_reloc[1] = BFD_RELOC_UNUSED;
10344 offset_reloc[2] = BFD_RELOC_UNUSED;
10345
10346 /* Check whether there is only a single bracketed expression
10347 left. If so, it must be the base register and the
10348 constant must be zero. */
10349 if (*s == '(' && strchr (s + 1, '(') == 0)
10350 {
10351 offset_expr.X_op = O_constant;
10352 offset_expr.X_add_number = 0;
10353 continue;
10354 }
10355
10356 /* If this value won't fit into a 16 bit offset, then go
10357 find a macro that will generate the 32 bit offset
10358 code pattern. */
10359 if (my_getSmallExpression (&offset_expr, offset_reloc, s) == 0
10360 && (offset_expr.X_op != O_constant
10361 || offset_expr.X_add_number >= 0x8000
10362 || offset_expr.X_add_number < -0x8000))
10363 break;
10364
10365 s = expr_end;
10366 continue;
10367
10368 case 'p': /* PC-relative offset. */
10369 *offset_reloc = BFD_RELOC_16_PCREL_S2;
10370 my_getExpression (&offset_expr, s);
10371 s = expr_end;
10372 continue;
10373
10374 case 'u': /* Upper 16 bits. */
10375 if (my_getSmallExpression (&imm_expr, imm_reloc, s) == 0
10376 && imm_expr.X_op == O_constant
10377 && (imm_expr.X_add_number < 0
10378 || imm_expr.X_add_number >= 0x10000))
10379 as_bad (_("lui expression (%lu) not in range 0..65535"),
10380 (unsigned long) imm_expr.X_add_number);
10381 s = expr_end;
10382 continue;
10383
10384 case 'a': /* 26-bit address. */
10385 my_getExpression (&offset_expr, s);
10386 s = expr_end;
10387 *offset_reloc = BFD_RELOC_MIPS_JMP;
10388 continue;
10389
10390 case 'N': /* 3-bit branch condition code. */
10391 case 'M': /* 3-bit compare condition code. */
10392 rtype = RTYPE_CCC;
10393 if (ip->insn_mo->pinfo & (FP_D | FP_S))
10394 rtype |= RTYPE_FCC;
10395 if (!reg_lookup (&s, rtype, &regno))
10396 break;
10397 if ((strcmp (str + strlen (str) - 3, ".ps") == 0
10398 || strcmp (str + strlen (str) - 5, "any2f") == 0
10399 || strcmp (str + strlen (str) - 5, "any2t") == 0)
10400 && (regno & 1) != 0)
10401 as_warn (_("Condition code register should be even for %s, "
10402 "was %d"),
10403 str, regno);
10404 if ((strcmp (str + strlen (str) - 5, "any4f") == 0
10405 || strcmp (str + strlen (str) - 5, "any4t") == 0)
10406 && (regno & 3) != 0)
10407 as_warn (_("Condition code register should be 0 or 4 for %s, "
10408 "was %d"),
10409 str, regno);
10410 if (*args == 'N')
10411 INSERT_OPERAND (BCC, *ip, regno);
10412 else
10413 INSERT_OPERAND (CCC, *ip, regno);
10414 continue;
10415
10416 case 'H':
10417 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
10418 s += 2;
10419 if (ISDIGIT (*s))
10420 {
10421 c = 0;
10422 do
10423 {
10424 c *= 10;
10425 c += *s - '0';
10426 ++s;
10427 }
10428 while (ISDIGIT (*s));
10429 }
10430 else
10431 c = 8; /* Invalid sel value. */
10432
10433 if (c > 7)
10434 as_bad (_("Invalid coprocessor sub-selection value (0-7)"));
10435 ip->insn_opcode |= c;
10436 continue;
10437
10438 case 'e':
10439 /* Must be at least one digit. */
10440 my_getExpression (&imm_expr, s);
10441 check_absolute_expr (ip, &imm_expr);
10442
10443 if ((unsigned long) imm_expr.X_add_number
10444 > (unsigned long) OP_MASK_VECBYTE)
10445 {
10446 as_bad (_("bad byte vector index (%ld)"),
10447 (long) imm_expr.X_add_number);
10448 imm_expr.X_add_number = 0;
10449 }
10450
10451 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
10452 imm_expr.X_op = O_absent;
10453 s = expr_end;
10454 continue;
10455
10456 case '%':
10457 my_getExpression (&imm_expr, s);
10458 check_absolute_expr (ip, &imm_expr);
10459
10460 if ((unsigned long) imm_expr.X_add_number
10461 > (unsigned long) OP_MASK_VECALIGN)
10462 {
10463 as_bad (_("bad byte vector index (%ld)"),
10464 (long) imm_expr.X_add_number);
10465 imm_expr.X_add_number = 0;
10466 }
10467
10468 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
10469 imm_expr.X_op = O_absent;
10470 s = expr_end;
10471 continue;
10472
10473 default:
10474 as_bad (_("Bad char = '%c'\n"), *args);
10475 internalError ();
10476 }
10477 break;
10478 }
10479 /* Args don't match. */
10480 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
10481 !strcmp (insn->name, insn[1].name))
10482 {
10483 ++insn;
10484 s = argsStart;
10485 insn_error = _("Illegal operands");
10486 continue;
10487 }
10488 if (save_c)
10489 *(--argsStart) = save_c;
10490 insn_error = _("Illegal operands");
10491 return;
10492 }
10493}
10494
10495#define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10496
10497/* This routine assembles an instruction into its binary format when
10498 assembling for the mips16. As a side effect, it sets one of the
10499 global variables imm_reloc or offset_reloc to the type of
10500 relocation to do if one of the operands is an address expression.
10501 It also sets mips16_small and mips16_ext if the user explicitly
10502 requested a small or extended instruction. */
10503
10504static void
10505mips16_ip (char *str, struct mips_cl_insn *ip)
10506{
10507 char *s;
10508 const char *args;
10509 struct mips_opcode *insn;
10510 char *argsstart;
10511 unsigned int regno;
10512 unsigned int lastregno = 0;
10513 char *s_reset;
10514 size_t i;
10515
10516 insn_error = NULL;
10517
10518 mips16_small = FALSE;
10519 mips16_ext = FALSE;
10520
10521 for (s = str; ISLOWER (*s); ++s)
10522 ;
10523 switch (*s)
10524 {
10525 case '\0':
10526 break;
10527
10528 case ' ':
10529 *s++ = '\0';
10530 break;
10531
10532 case '.':
10533 if (s[1] == 't' && s[2] == ' ')
10534 {
10535 *s = '\0';
10536 mips16_small = TRUE;
10537 s += 3;
10538 break;
10539 }
10540 else if (s[1] == 'e' && s[2] == ' ')
10541 {
10542 *s = '\0';
10543 mips16_ext = TRUE;
10544 s += 3;
10545 break;
10546 }
10547 /* Fall through. */
10548 default:
10549 insn_error = _("unknown opcode");
10550 return;
10551 }
10552
10553 if (mips_opts.noautoextend && ! mips16_ext)
10554 mips16_small = TRUE;
10555
10556 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
10557 {
10558 insn_error = _("unrecognized opcode");
10559 return;
10560 }
10561
10562 argsstart = s;
10563 for (;;)
10564 {
10565 bfd_boolean ok;
10566
10567 gas_assert (strcmp (insn->name, str) == 0);
10568
10569 ok = is_opcode_valid_16 (insn);
10570 if (! ok)
10571 {
10572 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10573 && strcmp (insn->name, insn[1].name) == 0)
10574 {
10575 ++insn;
10576 continue;
10577 }
10578 else
10579 {
10580 if (!insn_error)
10581 {
10582 static char buf[100];
10583 sprintf (buf,
10584 _("opcode not supported on this processor: %s (%s)"),
10585 mips_cpu_info_from_arch (mips_opts.arch)->name,
10586 mips_cpu_info_from_isa (mips_opts.isa)->name);
10587 insn_error = buf;
10588 }
10589 return;
10590 }
10591 }
10592
10593 create_insn (ip, insn);
10594 imm_expr.X_op = O_absent;
10595 imm_reloc[0] = BFD_RELOC_UNUSED;
10596 imm_reloc[1] = BFD_RELOC_UNUSED;
10597 imm_reloc[2] = BFD_RELOC_UNUSED;
10598 imm2_expr.X_op = O_absent;
10599 offset_expr.X_op = O_absent;
10600 offset_reloc[0] = BFD_RELOC_UNUSED;
10601 offset_reloc[1] = BFD_RELOC_UNUSED;
10602 offset_reloc[2] = BFD_RELOC_UNUSED;
10603 for (args = insn->args; 1; ++args)
10604 {
10605 int c;
10606
10607 if (*s == ' ')
10608 ++s;
10609
10610 /* In this switch statement we call break if we did not find
10611 a match, continue if we did find a match, or return if we
10612 are done. */
10613
10614 c = *args;
10615 switch (c)
10616 {
10617 case '\0':
10618 if (*s == '\0')
10619 {
10620 /* Stuff the immediate value in now, if we can. */
10621 if (imm_expr.X_op == O_constant
10622 && *imm_reloc > BFD_RELOC_UNUSED
10623 && *imm_reloc != BFD_RELOC_MIPS16_GOT16
10624 && *imm_reloc != BFD_RELOC_MIPS16_CALL16
10625 && insn->pinfo != INSN_MACRO)
10626 {
10627 valueT tmp;
10628
10629 switch (*offset_reloc)
10630 {
10631 case BFD_RELOC_MIPS16_HI16_S:
10632 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10633 break;
10634
10635 case BFD_RELOC_MIPS16_HI16:
10636 tmp = imm_expr.X_add_number >> 16;
10637 break;
10638
10639 case BFD_RELOC_MIPS16_LO16:
10640 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10641 - 0x8000;
10642 break;
10643
10644 case BFD_RELOC_UNUSED:
10645 tmp = imm_expr.X_add_number;
10646 break;
10647
10648 default:
10649 internalError ();
10650 }
10651 *offset_reloc = BFD_RELOC_UNUSED;
10652
10653 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10654 tmp, TRUE, mips16_small,
10655 mips16_ext, &ip->insn_opcode,
10656 &ip->use_extend, &ip->extend);
10657 imm_expr.X_op = O_absent;
10658 *imm_reloc = BFD_RELOC_UNUSED;
10659 }
10660
10661 return;
10662 }
10663 break;
10664
10665 case ',':
10666 if (*s++ == c)
10667 continue;
10668 s--;
10669 switch (*++args)
10670 {
10671 case 'v':
10672 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10673 continue;
10674 case 'w':
10675 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10676 continue;
10677 }
10678 break;
10679
10680 case '(':
10681 case ')':
10682 if (*s++ == c)
10683 continue;
10684 break;
10685
10686 case 'v':
10687 case 'w':
10688 if (s[0] != '$')
10689 {
10690 if (c == 'v')
10691 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10692 else
10693 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10694 ++args;
10695 continue;
10696 }
10697 /* Fall through. */
10698 case 'x':
10699 case 'y':
10700 case 'z':
10701 case 'Z':
10702 case '0':
10703 case 'S':
10704 case 'R':
10705 case 'X':
10706 case 'Y':
10707 s_reset = s;
10708 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno))
10709 {
10710 if (c == 'v' || c == 'w')
10711 {
10712 if (c == 'v')
10713 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10714 else
10715 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10716 ++args;
10717 continue;
10718 }
10719 break;
10720 }
10721
10722 if (*s == ' ')
10723 ++s;
10724 if (args[1] != *s)
10725 {
10726 if (c == 'v' || c == 'w')
10727 {
10728 regno = mips16_to_32_reg_map[lastregno];
10729 s = s_reset;
10730 ++args;
10731 }
10732 }
10733
10734 switch (c)
10735 {
10736 case 'x':
10737 case 'y':
10738 case 'z':
10739 case 'v':
10740 case 'w':
10741 case 'Z':
10742 regno = mips32_to_16_reg_map[regno];
10743 break;
10744
10745 case '0':
10746 if (regno != 0)
10747 regno = ILLEGAL_REG;
10748 break;
10749
10750 case 'S':
10751 if (regno != SP)
10752 regno = ILLEGAL_REG;
10753 break;
10754
10755 case 'R':
10756 if (regno != RA)
10757 regno = ILLEGAL_REG;
10758 break;
10759
10760 case 'X':
10761 case 'Y':
10762 if (regno == AT && mips_opts.at)
10763 {
10764 if (mips_opts.at == ATREG)
10765 as_warn (_("used $at without \".set noat\""));
10766 else
10767 as_warn (_("used $%u with \".set at=$%u\""),
10768 regno, mips_opts.at);
10769 }
10770 break;
10771
10772 default:
10773 internalError ();
10774 }
10775
10776 if (regno == ILLEGAL_REG)
10777 break;
10778
10779 switch (c)
10780 {
10781 case 'x':
10782 case 'v':
10783 MIPS16_INSERT_OPERAND (RX, *ip, regno);
10784 break;
10785 case 'y':
10786 case 'w':
10787 MIPS16_INSERT_OPERAND (RY, *ip, regno);
10788 break;
10789 case 'z':
10790 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
10791 break;
10792 case 'Z':
10793 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
10794 case '0':
10795 case 'S':
10796 case 'R':
10797 break;
10798 case 'X':
10799 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
10800 break;
10801 case 'Y':
10802 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
10803 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
10804 break;
10805 default:
10806 internalError ();
10807 }
10808
10809 lastregno = regno;
10810 continue;
10811
10812 case 'P':
10813 if (strncmp (s, "$pc", 3) == 0)
10814 {
10815 s += 3;
10816 continue;
10817 }
10818 break;
10819
10820 case '5':
10821 case 'H':
10822 case 'W':
10823 case 'D':
10824 case 'j':
10825 case 'V':
10826 case 'C':
10827 case 'U':
10828 case 'k':
10829 case 'K':
10830 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
10831 if (i > 0)
10832 {
10833 if (imm_expr.X_op != O_constant)
10834 {
10835 mips16_ext = TRUE;
10836 ip->use_extend = TRUE;
10837 ip->extend = 0;
10838 }
10839 else
10840 {
10841 /* We need to relax this instruction. */
10842 *offset_reloc = *imm_reloc;
10843 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10844 }
10845 s = expr_end;
10846 continue;
10847 }
10848 *imm_reloc = BFD_RELOC_UNUSED;
10849 /* Fall through. */
10850 case '<':
10851 case '>':
10852 case '[':
10853 case ']':
10854 case '4':
10855 case '8':
10856 my_getExpression (&imm_expr, s);
10857 if (imm_expr.X_op == O_register)
10858 {
10859 /* What we thought was an expression turned out to
10860 be a register. */
10861
10862 if (s[0] == '(' && args[1] == '(')
10863 {
10864 /* It looks like the expression was omitted
10865 before a register indirection, which means
10866 that the expression is implicitly zero. We
10867 still set up imm_expr, so that we handle
10868 explicit extensions correctly. */
10869 imm_expr.X_op = O_constant;
10870 imm_expr.X_add_number = 0;
10871 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10872 continue;
10873 }
10874
10875 break;
10876 }
10877
10878 /* We need to relax this instruction. */
10879 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
10880 s = expr_end;
10881 continue;
10882
10883 case 'p':
10884 case 'q':
10885 case 'A':
10886 case 'B':
10887 case 'E':
10888 /* We use offset_reloc rather than imm_reloc for the PC
10889 relative operands. This lets macros with both
10890 immediate and address operands work correctly. */
10891 my_getExpression (&offset_expr, s);
10892
10893 if (offset_expr.X_op == O_register)
10894 break;
10895
10896 /* We need to relax this instruction. */
10897 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10898 s = expr_end;
10899 continue;
10900
10901 case '6': /* break code */
10902 my_getExpression (&imm_expr, s);
10903 check_absolute_expr (ip, &imm_expr);
10904 if ((unsigned long) imm_expr.X_add_number > 63)
10905 as_warn (_("Invalid value for `%s' (%lu)"),
10906 ip->insn_mo->name,
10907 (unsigned long) imm_expr.X_add_number);
10908 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
10909 imm_expr.X_op = O_absent;
10910 s = expr_end;
10911 continue;
10912
10913 case 'a': /* 26 bit address */
10914 my_getExpression (&offset_expr, s);
10915 s = expr_end;
10916 *offset_reloc = BFD_RELOC_MIPS16_JMP;
10917 ip->insn_opcode <<= 16;
10918 continue;
10919
10920 case 'l': /* register list for entry macro */
10921 case 'L': /* register list for exit macro */
10922 {
10923 int mask;
10924
10925 if (c == 'l')
10926 mask = 0;
10927 else
10928 mask = 7 << 3;
10929 while (*s != '\0')
10930 {
10931 unsigned int freg, reg1, reg2;
10932
10933 while (*s == ' ' || *s == ',')
10934 ++s;
10935 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
10936 freg = 0;
10937 else if (reg_lookup (&s, RTYPE_FPU, &reg1))
10938 freg = 1;
10939 else
10940 {
10941 as_bad (_("can't parse register list"));
10942 break;
10943 }
10944 if (*s == ' ')
10945 ++s;
10946 if (*s != '-')
10947 reg2 = reg1;
10948 else
10949 {
10950 ++s;
10951 if (!reg_lookup (&s, freg ? RTYPE_FPU
10952 : (RTYPE_GP | RTYPE_NUM), &reg2))
10953 {
10954 as_bad (_("invalid register list"));
10955 break;
10956 }
10957 }
10958 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10959 {
10960 mask &= ~ (7 << 3);
10961 mask |= 5 << 3;
10962 }
10963 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10964 {
10965 mask &= ~ (7 << 3);
10966 mask |= 6 << 3;
10967 }
10968 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
10969 mask |= (reg2 - 3) << 3;
10970 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
10971 mask |= (reg2 - 15) << 1;
10972 else if (reg1 == RA && reg2 == RA)
10973 mask |= 1;
10974 else
10975 {
10976 as_bad (_("invalid register list"));
10977 break;
10978 }
10979 }
10980 /* The mask is filled in in the opcode table for the
10981 benefit of the disassembler. We remove it before
10982 applying the actual mask. */
10983 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10984 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10985 }
10986 continue;
10987
10988 case 'm': /* Register list for save insn. */
10989 case 'M': /* Register list for restore insn. */
10990 {
10991 int opcode = 0;
10992 int framesz = 0, seen_framesz = 0;
10993 int nargs = 0, statics = 0, sregs = 0;
10994
10995 while (*s != '\0')
10996 {
10997 unsigned int reg1, reg2;
10998
10999 SKIP_SPACE_TABS (s);
11000 while (*s == ',')
11001 ++s;
11002 SKIP_SPACE_TABS (s);
11003
11004 my_getExpression (&imm_expr, s);
11005 if (imm_expr.X_op == O_constant)
11006 {
11007 /* Handle the frame size. */
11008 if (seen_framesz)
11009 {
11010 as_bad (_("more than one frame size in list"));
11011 break;
11012 }
11013 seen_framesz = 1;
11014 framesz = imm_expr.X_add_number;
11015 imm_expr.X_op = O_absent;
11016 s = expr_end;
11017 continue;
11018 }
11019
11020 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
11021 {
11022 as_bad (_("can't parse register list"));
11023 break;
11024 }
11025
11026 while (*s == ' ')
11027 ++s;
11028
11029 if (*s != '-')
11030 reg2 = reg1;
11031 else
11032 {
11033 ++s;
11034 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg2)
11035 || reg2 < reg1)
11036 {
11037 as_bad (_("can't parse register list"));
11038 break;
11039 }
11040 }
11041
11042 while (reg1 <= reg2)
11043 {
11044 if (reg1 >= 4 && reg1 <= 7)
11045 {
11046 if (!seen_framesz)
11047 /* args $a0-$a3 */
11048 nargs |= 1 << (reg1 - 4);
11049 else
11050 /* statics $a0-$a3 */
11051 statics |= 1 << (reg1 - 4);
11052 }
11053 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
11054 {
11055 /* $s0-$s8 */
11056 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
11057 }
11058 else if (reg1 == 31)
11059 {
11060 /* Add $ra to insn. */
11061 opcode |= 0x40;
11062 }
11063 else
11064 {
11065 as_bad (_("unexpected register in list"));
11066 break;
11067 }
11068 if (++reg1 == 24)
11069 reg1 = 30;
11070 }
11071 }
11072
11073 /* Encode args/statics combination. */
11074 if (nargs & statics)
11075 as_bad (_("arg/static registers overlap"));
11076 else if (nargs == 0xf)
11077 /* All $a0-$a3 are args. */
11078 opcode |= MIPS16_ALL_ARGS << 16;
11079 else if (statics == 0xf)
11080 /* All $a0-$a3 are statics. */
11081 opcode |= MIPS16_ALL_STATICS << 16;
11082 else
11083 {
11084 int narg = 0, nstat = 0;
11085
11086 /* Count arg registers. */
11087 while (nargs & 0x1)
11088 {
11089 nargs >>= 1;
11090 narg++;
11091 }
11092 if (nargs != 0)
11093 as_bad (_("invalid arg register list"));
11094
11095 /* Count static registers. */
11096 while (statics & 0x8)
11097 {
11098 statics = (statics << 1) & 0xf;
11099 nstat++;
11100 }
11101 if (statics != 0)
11102 as_bad (_("invalid static register list"));
11103
11104 /* Encode args/statics. */
11105 opcode |= ((narg << 2) | nstat) << 16;
11106 }
11107
11108 /* Encode $s0/$s1. */
11109 if (sregs & (1 << 0)) /* $s0 */
11110 opcode |= 0x20;
11111 if (sregs & (1 << 1)) /* $s1 */
11112 opcode |= 0x10;
11113 sregs >>= 2;
11114
11115 if (sregs != 0)
11116 {
11117 /* Count regs $s2-$s8. */
11118 int nsreg = 0;
11119 while (sregs & 1)
11120 {
11121 sregs >>= 1;
11122 nsreg++;
11123 }
11124 if (sregs != 0)
11125 as_bad (_("invalid static register list"));
11126 /* Encode $s2-$s8. */
11127 opcode |= nsreg << 24;
11128 }
11129
11130 /* Encode frame size. */
11131 if (!seen_framesz)
11132 as_bad (_("missing frame size"));
11133 else if ((framesz & 7) != 0 || framesz < 0
11134 || framesz > 0xff * 8)
11135 as_bad (_("invalid frame size"));
11136 else if (framesz != 128 || (opcode >> 16) != 0)
11137 {
11138 framesz /= 8;
11139 opcode |= (((framesz & 0xf0) << 16)
11140 | (framesz & 0x0f));
11141 }
11142
11143 /* Finally build the instruction. */
11144 if ((opcode >> 16) != 0 || framesz == 0)
11145 {
11146 ip->use_extend = TRUE;
11147 ip->extend = opcode >> 16;
11148 }
11149 ip->insn_opcode |= opcode & 0x7f;
11150 }
11151 continue;
11152
11153 case 'e': /* extend code */
11154 my_getExpression (&imm_expr, s);
11155 check_absolute_expr (ip, &imm_expr);
11156 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
11157 {
11158 as_warn (_("Invalid value for `%s' (%lu)"),
11159 ip->insn_mo->name,
11160 (unsigned long) imm_expr.X_add_number);
11161 imm_expr.X_add_number &= 0x7ff;
11162 }
11163 ip->insn_opcode |= imm_expr.X_add_number;
11164 imm_expr.X_op = O_absent;
11165 s = expr_end;
11166 continue;
11167
11168 default:
11169 internalError ();
11170 }
11171 break;
11172 }
11173
11174 /* Args don't match. */
11175 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
11176 strcmp (insn->name, insn[1].name) == 0)
11177 {
11178 ++insn;
11179 s = argsstart;
11180 continue;
11181 }
11182
11183 insn_error = _("illegal operands");
11184
11185 return;
11186 }
11187}
11188
11189/* This structure holds information we know about a mips16 immediate
11190 argument type. */
11191
11192struct mips16_immed_operand
11193{
11194 /* The type code used in the argument string in the opcode table. */
11195 int type;
11196 /* The number of bits in the short form of the opcode. */
11197 int nbits;
11198 /* The number of bits in the extended form of the opcode. */
11199 int extbits;
11200 /* The amount by which the short form is shifted when it is used;
11201 for example, the sw instruction has a shift count of 2. */
11202 int shift;
11203 /* The amount by which the short form is shifted when it is stored
11204 into the instruction code. */
11205 int op_shift;
11206 /* Non-zero if the short form is unsigned. */
11207 int unsp;
11208 /* Non-zero if the extended form is unsigned. */
11209 int extu;
11210 /* Non-zero if the value is PC relative. */
11211 int pcrel;
11212};
11213
11214/* The mips16 immediate operand types. */
11215
11216static const struct mips16_immed_operand mips16_immed_operands[] =
11217{
11218 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11219 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11220 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
11221 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
11222 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
11223 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
11224 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
11225 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
11226 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
11227 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
11228 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
11229 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
11230 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
11231 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
11232 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
11233 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
11234 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11235 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
11236 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
11237 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
11238 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
11239};
11240
11241#define MIPS16_NUM_IMMED \
11242 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
11243
11244/* Handle a mips16 instruction with an immediate value. This or's the
11245 small immediate value into *INSN. It sets *USE_EXTEND to indicate
11246 whether an extended value is needed; if one is needed, it sets
11247 *EXTEND to the value. The argument type is TYPE. The value is VAL.
11248 If SMALL is true, an unextended opcode was explicitly requested.
11249 If EXT is true, an extended opcode was explicitly requested. If
11250 WARN is true, warn if EXT does not match reality. */
11251
11252static void
11253mips16_immed (char *file, unsigned int line, int type, offsetT val,
11254 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
11255 unsigned long *insn, bfd_boolean *use_extend,
11256 unsigned short *extend)
11257{
11258 const struct mips16_immed_operand *op;
11259 int mintiny, maxtiny;
11260 bfd_boolean needext;
11261
11262 op = mips16_immed_operands;
11263 while (op->type != type)
11264 {
11265 ++op;
11266 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
11267 }
11268
11269 if (op->unsp)
11270 {
11271 if (type == '<' || type == '>' || type == '[' || type == ']')
11272 {
11273 mintiny = 1;
11274 maxtiny = 1 << op->nbits;
11275 }
11276 else
11277 {
11278 mintiny = 0;
11279 maxtiny = (1 << op->nbits) - 1;
11280 }
11281 }
11282 else
11283 {
11284 mintiny = - (1 << (op->nbits - 1));
11285 maxtiny = (1 << (op->nbits - 1)) - 1;
11286 }
11287
11288 /* Branch offsets have an implicit 0 in the lowest bit. */
11289 if (type == 'p' || type == 'q')
11290 val /= 2;
11291
11292 if ((val & ((1 << op->shift) - 1)) != 0
11293 || val < (mintiny << op->shift)
11294 || val > (maxtiny << op->shift))
11295 needext = TRUE;
11296 else
11297 needext = FALSE;
11298
11299 if (warn && ext && ! needext)
11300 as_warn_where (file, line,
11301 _("extended operand requested but not required"));
11302 if (small && needext)
11303 as_bad_where (file, line, _("invalid unextended operand value"));
11304
11305 if (small || (! ext && ! needext))
11306 {
11307 int insnval;
11308
11309 *use_extend = FALSE;
11310 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
11311 insnval <<= op->op_shift;
11312 *insn |= insnval;
11313 }
11314 else
11315 {
11316 long minext, maxext;
11317 int extval;
11318
11319 if (op->extu)
11320 {
11321 minext = 0;
11322 maxext = (1 << op->extbits) - 1;
11323 }
11324 else
11325 {
11326 minext = - (1 << (op->extbits - 1));
11327 maxext = (1 << (op->extbits - 1)) - 1;
11328 }
11329 if (val < minext || val > maxext)
11330 as_bad_where (file, line,
11331 _("operand value out of range for instruction"));
11332
11333 *use_extend = TRUE;
11334 if (op->extbits == 16)
11335 {
11336 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
11337 val &= 0x1f;
11338 }
11339 else if (op->extbits == 15)
11340 {
11341 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
11342 val &= 0xf;
11343 }
11344 else
11345 {
11346 extval = ((val & 0x1f) << 6) | (val & 0x20);
11347 val = 0;
11348 }
11349
11350 *extend = (unsigned short) extval;
11351 *insn |= val;
11352 }
11353}
11354\f
11355struct percent_op_match
11356{
11357 const char *str;
11358 bfd_reloc_code_real_type reloc;
11359};
11360
11361static const struct percent_op_match mips_percent_op[] =
11362{
11363 {"%lo", BFD_RELOC_LO16},
11364#ifdef OBJ_ELF
11365 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
11366 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
11367 {"%call16", BFD_RELOC_MIPS_CALL16},
11368 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
11369 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},
11370 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST},
11371 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
11372 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
11373 {"%got", BFD_RELOC_MIPS_GOT16},
11374 {"%gp_rel", BFD_RELOC_GPREL16},
11375 {"%half", BFD_RELOC_16},
11376 {"%highest", BFD_RELOC_MIPS_HIGHEST},
11377 {"%higher", BFD_RELOC_MIPS_HIGHER},
11378 {"%neg", BFD_RELOC_MIPS_SUB},
11379 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
11380 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
11381 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
11382 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
11383 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
11384 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
11385 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
11386#endif
11387 {"%hi", BFD_RELOC_HI16_S}
11388};
11389
11390static const struct percent_op_match mips16_percent_op[] =
11391{
11392 {"%lo", BFD_RELOC_MIPS16_LO16},
11393 {"%gprel", BFD_RELOC_MIPS16_GPREL},
11394 {"%got", BFD_RELOC_MIPS16_GOT16},
11395 {"%call16", BFD_RELOC_MIPS16_CALL16},
11396 {"%hi", BFD_RELOC_MIPS16_HI16_S}
11397};
11398
11399
11400/* Return true if *STR points to a relocation operator. When returning true,
11401 move *STR over the operator and store its relocation code in *RELOC.
11402 Leave both *STR and *RELOC alone when returning false. */
11403
11404static bfd_boolean
11405parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
11406{
11407 const struct percent_op_match *percent_op;
11408 size_t limit, i;
11409
11410 if (mips_opts.mips16)
11411 {
11412 percent_op = mips16_percent_op;
11413 limit = ARRAY_SIZE (mips16_percent_op);
11414 }
11415 else
11416 {
11417 percent_op = mips_percent_op;
11418 limit = ARRAY_SIZE (mips_percent_op);
11419 }
11420
11421 for (i = 0; i < limit; i++)
11422 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
11423 {
11424 int len = strlen (percent_op[i].str);
11425
11426 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
11427 continue;
11428
11429 *str += strlen (percent_op[i].str);
11430 *reloc = percent_op[i].reloc;
11431
11432 /* Check whether the output BFD supports this relocation.
11433 If not, issue an error and fall back on something safe. */
11434 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
11435 {
11436 as_bad (_("relocation %s isn't supported by the current ABI"),
11437 percent_op[i].str);
11438 *reloc = BFD_RELOC_UNUSED;
11439 }
11440 return TRUE;
11441 }
11442 return FALSE;
11443}
11444
11445
11446/* Parse string STR as a 16-bit relocatable operand. Store the
11447 expression in *EP and the relocations in the array starting
11448 at RELOC. Return the number of relocation operators used.
11449
11450 On exit, EXPR_END points to the first character after the expression. */
11451
11452static size_t
11453my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
11454 char *str)
11455{
11456 bfd_reloc_code_real_type reversed_reloc[3];
11457 size_t reloc_index, i;
11458 int crux_depth, str_depth;
11459 char *crux;
11460
11461 /* Search for the start of the main expression, recoding relocations
11462 in REVERSED_RELOC. End the loop with CRUX pointing to the start
11463 of the main expression and with CRUX_DEPTH containing the number
11464 of open brackets at that point. */
11465 reloc_index = -1;
11466 str_depth = 0;
11467 do
11468 {
11469 reloc_index++;
11470 crux = str;
11471 crux_depth = str_depth;
11472
11473 /* Skip over whitespace and brackets, keeping count of the number
11474 of brackets. */
11475 while (*str == ' ' || *str == '\t' || *str == '(')
11476 if (*str++ == '(')
11477 str_depth++;
11478 }
11479 while (*str == '%'
11480 && reloc_index < (HAVE_NEWABI ? 3 : 1)
11481 && parse_relocation (&str, &reversed_reloc[reloc_index]));
11482
11483 my_getExpression (ep, crux);
11484 str = expr_end;
11485
11486 /* Match every open bracket. */
11487 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
11488 if (*str++ == ')')
11489 crux_depth--;
11490
11491 if (crux_depth > 0)
11492 as_bad (_("unclosed '('"));
11493
11494 expr_end = str;
11495
11496 if (reloc_index != 0)
11497 {
11498 prev_reloc_op_frag = frag_now;
11499 for (i = 0; i < reloc_index; i++)
11500 reloc[i] = reversed_reloc[reloc_index - 1 - i];
11501 }
11502
11503 return reloc_index;
11504}
11505
11506static void
11507my_getExpression (expressionS *ep, char *str)
11508{
11509 char *save_in;
11510
11511 save_in = input_line_pointer;
11512 input_line_pointer = str;
11513 expression (ep);
11514 expr_end = input_line_pointer;
11515 input_line_pointer = save_in;
11516}
11517
11518char *
11519md_atof (int type, char *litP, int *sizeP)
11520{
11521 return ieee_md_atof (type, litP, sizeP, target_big_endian);
11522}
11523
11524void
11525md_number_to_chars (char *buf, valueT val, int n)
11526{
11527 if (target_big_endian)
11528 number_to_chars_bigendian (buf, val, n);
11529 else
11530 number_to_chars_littleendian (buf, val, n);
11531}
11532\f
11533#ifdef OBJ_ELF
11534static int support_64bit_objects(void)
11535{
11536 const char **list, **l;
11537 int yes;
11538
11539 list = bfd_target_list ();
11540 for (l = list; *l != NULL; l++)
11541 if (strcmp (*l, ELF_TARGET ("elf64-", "big")) == 0
11542 || strcmp (*l, ELF_TARGET ("elf64-", "little")) == 0)
11543 break;
11544 yes = (*l != NULL);
11545 free (list);
11546 return yes;
11547}
11548#endif /* OBJ_ELF */
11549
11550const char *md_shortopts = "O::g::G:";
11551
11552enum options
11553 {
11554 OPTION_MARCH = OPTION_MD_BASE,
11555 OPTION_MTUNE,
11556 OPTION_MIPS1,
11557 OPTION_MIPS2,
11558 OPTION_MIPS3,
11559 OPTION_MIPS4,
11560 OPTION_MIPS5,
11561 OPTION_MIPS32,
11562 OPTION_MIPS64,
11563 OPTION_MIPS32R2,
11564 OPTION_MIPS64R2,
11565 OPTION_MIPS16,
11566 OPTION_NO_MIPS16,
11567 OPTION_MIPS3D,
11568 OPTION_NO_MIPS3D,
11569 OPTION_MDMX,
11570 OPTION_NO_MDMX,
11571 OPTION_DSP,
11572 OPTION_NO_DSP,
11573 OPTION_MT,
11574 OPTION_NO_MT,
11575 OPTION_SMARTMIPS,
11576 OPTION_NO_SMARTMIPS,
11577 OPTION_DSPR2,
11578 OPTION_NO_DSPR2,
11579 OPTION_COMPAT_ARCH_BASE,
11580 OPTION_M4650,
11581 OPTION_NO_M4650,
11582 OPTION_M4010,
11583 OPTION_NO_M4010,
11584 OPTION_M4100,
11585 OPTION_NO_M4100,
11586 OPTION_M3900,
11587 OPTION_NO_M3900,
11588 OPTION_M7000_HILO_FIX,
11589 OPTION_MNO_7000_HILO_FIX,
11590 OPTION_FIX_24K,
11591 OPTION_NO_FIX_24K,
11592 OPTION_FIX_LOONGSON2F_JUMP,
11593 OPTION_NO_FIX_LOONGSON2F_JUMP,
11594 OPTION_FIX_LOONGSON2F_NOP,
11595 OPTION_NO_FIX_LOONGSON2F_NOP,
11596 OPTION_FIX_VR4120,
11597 OPTION_NO_FIX_VR4120,
11598 OPTION_FIX_VR4130,
11599 OPTION_NO_FIX_VR4130,
11600 OPTION_FIX_CN63XXP1,
11601 OPTION_NO_FIX_CN63XXP1,
11602 OPTION_TRAP,
11603 OPTION_BREAK,
11604 OPTION_EB,
11605 OPTION_EL,
11606 OPTION_FP32,
11607 OPTION_GP32,
11608 OPTION_CONSTRUCT_FLOATS,
11609 OPTION_NO_CONSTRUCT_FLOATS,
11610 OPTION_FP64,
11611 OPTION_GP64,
11612 OPTION_RELAX_BRANCH,
11613 OPTION_NO_RELAX_BRANCH,
11614 OPTION_MSHARED,
11615 OPTION_MNO_SHARED,
11616 OPTION_MSYM32,
11617 OPTION_MNO_SYM32,
11618 OPTION_SOFT_FLOAT,
11619 OPTION_HARD_FLOAT,
11620 OPTION_SINGLE_FLOAT,
11621 OPTION_DOUBLE_FLOAT,
11622 OPTION_32,
11623#ifdef OBJ_ELF
11624 OPTION_CALL_SHARED,
11625 OPTION_CALL_NONPIC,
11626 OPTION_NON_SHARED,
11627 OPTION_XGOT,
11628 OPTION_MABI,
11629 OPTION_N32,
11630 OPTION_64,
11631 OPTION_MDEBUG,
11632 OPTION_NO_MDEBUG,
11633 OPTION_PDR,
11634 OPTION_NO_PDR,
11635 OPTION_MVXWORKS_PIC,
11636#endif /* OBJ_ELF */
11637 OPTION_END_OF_ENUM
11638 };
11639
11640struct option md_longopts[] =
11641{
11642 /* Options which specify architecture. */
11643 {"march", required_argument, NULL, OPTION_MARCH},
11644 {"mtune", required_argument, NULL, OPTION_MTUNE},
11645 {"mips0", no_argument, NULL, OPTION_MIPS1},
11646 {"mips1", no_argument, NULL, OPTION_MIPS1},
11647 {"mips2", no_argument, NULL, OPTION_MIPS2},
11648 {"mips3", no_argument, NULL, OPTION_MIPS3},
11649 {"mips4", no_argument, NULL, OPTION_MIPS4},
11650 {"mips5", no_argument, NULL, OPTION_MIPS5},
11651 {"mips32", no_argument, NULL, OPTION_MIPS32},
11652 {"mips64", no_argument, NULL, OPTION_MIPS64},
11653 {"mips32r2", no_argument, NULL, OPTION_MIPS32R2},
11654 {"mips64r2", no_argument, NULL, OPTION_MIPS64R2},
11655
11656 /* Options which specify Application Specific Extensions (ASEs). */
11657 {"mips16", no_argument, NULL, OPTION_MIPS16},
11658 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
11659 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
11660 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
11661 {"mdmx", no_argument, NULL, OPTION_MDMX},
11662 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
11663 {"mdsp", no_argument, NULL, OPTION_DSP},
11664 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11665 {"mmt", no_argument, NULL, OPTION_MT},
11666 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11667 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11668 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11669 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11670 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
11671
11672 /* Old-style architecture options. Don't add more of these. */
11673 {"m4650", no_argument, NULL, OPTION_M4650},
11674 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11675 {"m4010", no_argument, NULL, OPTION_M4010},
11676 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
11677 {"m4100", no_argument, NULL, OPTION_M4100},
11678 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
11679 {"m3900", no_argument, NULL, OPTION_M3900},
11680 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
11681
11682 /* Options which enable bug fixes. */
11683 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
11684 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11685 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
11686 {"mfix-loongson2f-jump", no_argument, NULL, OPTION_FIX_LOONGSON2F_JUMP},
11687 {"mno-fix-loongson2f-jump", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_JUMP},
11688 {"mfix-loongson2f-nop", no_argument, NULL, OPTION_FIX_LOONGSON2F_NOP},
11689 {"mno-fix-loongson2f-nop", no_argument, NULL, OPTION_NO_FIX_LOONGSON2F_NOP},
11690 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
11691 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
11692 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
11693 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
11694 {"mfix-24k", no_argument, NULL, OPTION_FIX_24K},
11695 {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K},
11696 {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1},
11697 {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1},
11698
11699 /* Miscellaneous options. */
11700 {"trap", no_argument, NULL, OPTION_TRAP},
11701 {"no-break", no_argument, NULL, OPTION_TRAP},
11702 {"break", no_argument, NULL, OPTION_BREAK},
11703 {"no-trap", no_argument, NULL, OPTION_BREAK},
11704 {"EB", no_argument, NULL, OPTION_EB},
11705 {"EL", no_argument, NULL, OPTION_EL},
11706 {"mfp32", no_argument, NULL, OPTION_FP32},
11707 {"mgp32", no_argument, NULL, OPTION_GP32},
11708 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
11709 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
11710 {"mfp64", no_argument, NULL, OPTION_FP64},
11711 {"mgp64", no_argument, NULL, OPTION_GP64},
11712 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
11713 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
11714 {"mshared", no_argument, NULL, OPTION_MSHARED},
11715 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
11716 {"msym32", no_argument, NULL, OPTION_MSYM32},
11717 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
11718 {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT},
11719 {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT},
11720 {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT},
11721 {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT},
11722
11723 /* Strictly speaking this next option is ELF specific,
11724 but we allow it for other ports as well in order to
11725 make testing easier. */
11726 {"32", no_argument, NULL, OPTION_32},
11727
11728 /* ELF-specific options. */
11729#ifdef OBJ_ELF
11730 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
11731 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
11732 {"call_nonpic", no_argument, NULL, OPTION_CALL_NONPIC},
11733 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
11734 {"xgot", no_argument, NULL, OPTION_XGOT},
11735 {"mabi", required_argument, NULL, OPTION_MABI},
11736 {"n32", no_argument, NULL, OPTION_N32},
11737 {"64", no_argument, NULL, OPTION_64},
11738 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11739 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11740 {"mpdr", no_argument, NULL, OPTION_PDR},
11741 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11742 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
11743#endif /* OBJ_ELF */
11744
11745 {NULL, no_argument, NULL, 0}
11746};
11747size_t md_longopts_size = sizeof (md_longopts);
11748
11749/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11750 NEW_VALUE. Warn if another value was already specified. Note:
11751 we have to defer parsing the -march and -mtune arguments in order
11752 to handle 'from-abi' correctly, since the ABI might be specified
11753 in a later argument. */
11754
11755static void
11756mips_set_option_string (const char **string_ptr, const char *new_value)
11757{
11758 if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
11759 as_warn (_("A different %s was already specified, is now %s"),
11760 string_ptr == &mips_arch_string ? "-march" : "-mtune",
11761 new_value);
11762
11763 *string_ptr = new_value;
11764}
11765
11766int
11767md_parse_option (int c, char *arg)
11768{
11769 switch (c)
11770 {
11771 case OPTION_CONSTRUCT_FLOATS:
11772 mips_disable_float_construction = 0;
11773 break;
11774
11775 case OPTION_NO_CONSTRUCT_FLOATS:
11776 mips_disable_float_construction = 1;
11777 break;
11778
11779 case OPTION_TRAP:
11780 mips_trap = 1;
11781 break;
11782
11783 case OPTION_BREAK:
11784 mips_trap = 0;
11785 break;
11786
11787 case OPTION_EB:
11788 target_big_endian = 1;
11789 break;
11790
11791 case OPTION_EL:
11792 target_big_endian = 0;
11793 break;
11794
11795 case 'O':
11796 if (arg == NULL)
11797 mips_optimize = 1;
11798 else if (arg[0] == '0')
11799 mips_optimize = 0;
11800 else if (arg[0] == '1')
11801 mips_optimize = 1;
11802 else
11803 mips_optimize = 2;
11804 break;
11805
11806 case 'g':
11807 if (arg == NULL)
11808 mips_debug = 2;
11809 else
11810 mips_debug = atoi (arg);
11811 break;
11812
11813 case OPTION_MIPS1:
11814 file_mips_isa = ISA_MIPS1;
11815 break;
11816
11817 case OPTION_MIPS2:
11818 file_mips_isa = ISA_MIPS2;
11819 break;
11820
11821 case OPTION_MIPS3:
11822 file_mips_isa = ISA_MIPS3;
11823 break;
11824
11825 case OPTION_MIPS4:
11826 file_mips_isa = ISA_MIPS4;
11827 break;
11828
11829 case OPTION_MIPS5:
11830 file_mips_isa = ISA_MIPS5;
11831 break;
11832
11833 case OPTION_MIPS32:
11834 file_mips_isa = ISA_MIPS32;
11835 break;
11836
11837 case OPTION_MIPS32R2:
11838 file_mips_isa = ISA_MIPS32R2;
11839 break;
11840
11841 case OPTION_MIPS64R2:
11842 file_mips_isa = ISA_MIPS64R2;
11843 break;
11844
11845 case OPTION_MIPS64:
11846 file_mips_isa = ISA_MIPS64;
11847 break;
11848
11849 case OPTION_MTUNE:
11850 mips_set_option_string (&mips_tune_string, arg);
11851 break;
11852
11853 case OPTION_MARCH:
11854 mips_set_option_string (&mips_arch_string, arg);
11855 break;
11856
11857 case OPTION_M4650:
11858 mips_set_option_string (&mips_arch_string, "4650");
11859 mips_set_option_string (&mips_tune_string, "4650");
11860 break;
11861
11862 case OPTION_NO_M4650:
11863 break;
11864
11865 case OPTION_M4010:
11866 mips_set_option_string (&mips_arch_string, "4010");
11867 mips_set_option_string (&mips_tune_string, "4010");
11868 break;
11869
11870 case OPTION_NO_M4010:
11871 break;
11872
11873 case OPTION_M4100:
11874 mips_set_option_string (&mips_arch_string, "4100");
11875 mips_set_option_string (&mips_tune_string, "4100");
11876 break;
11877
11878 case OPTION_NO_M4100:
11879 break;
11880
11881 case OPTION_M3900:
11882 mips_set_option_string (&mips_arch_string, "3900");
11883 mips_set_option_string (&mips_tune_string, "3900");
11884 break;
11885
11886 case OPTION_NO_M3900:
11887 break;
11888
11889 case OPTION_MDMX:
11890 mips_opts.ase_mdmx = 1;
11891 break;
11892
11893 case OPTION_NO_MDMX:
11894 mips_opts.ase_mdmx = 0;
11895 break;
11896
11897 case OPTION_DSP:
11898 mips_opts.ase_dsp = 1;
11899 mips_opts.ase_dspr2 = 0;
11900 break;
11901
11902 case OPTION_NO_DSP:
11903 mips_opts.ase_dsp = 0;
11904 mips_opts.ase_dspr2 = 0;
11905 break;
11906
11907 case OPTION_DSPR2:
11908 mips_opts.ase_dspr2 = 1;
11909 mips_opts.ase_dsp = 1;
11910 break;
11911
11912 case OPTION_NO_DSPR2:
11913 mips_opts.ase_dspr2 = 0;
11914 mips_opts.ase_dsp = 0;
11915 break;
11916
11917 case OPTION_MT:
11918 mips_opts.ase_mt = 1;
11919 break;
11920
11921 case OPTION_NO_MT:
11922 mips_opts.ase_mt = 0;
11923 break;
11924
11925 case OPTION_MIPS16:
11926 mips_opts.mips16 = 1;
11927 mips_no_prev_insn ();
11928 break;
11929
11930 case OPTION_NO_MIPS16:
11931 mips_opts.mips16 = 0;
11932 mips_no_prev_insn ();
11933 break;
11934
11935 case OPTION_MIPS3D:
11936 mips_opts.ase_mips3d = 1;
11937 break;
11938
11939 case OPTION_NO_MIPS3D:
11940 mips_opts.ase_mips3d = 0;
11941 break;
11942
11943 case OPTION_SMARTMIPS:
11944 mips_opts.ase_smartmips = 1;
11945 break;
11946
11947 case OPTION_NO_SMARTMIPS:
11948 mips_opts.ase_smartmips = 0;
11949 break;
11950
11951 case OPTION_FIX_24K:
11952 mips_fix_24k = 1;
11953 break;
11954
11955 case OPTION_NO_FIX_24K:
11956 mips_fix_24k = 0;
11957 break;
11958
11959 case OPTION_FIX_LOONGSON2F_JUMP:
11960 mips_fix_loongson2f_jump = TRUE;
11961 break;
11962
11963 case OPTION_NO_FIX_LOONGSON2F_JUMP:
11964 mips_fix_loongson2f_jump = FALSE;
11965 break;
11966
11967 case OPTION_FIX_LOONGSON2F_NOP:
11968 mips_fix_loongson2f_nop = TRUE;
11969 break;
11970
11971 case OPTION_NO_FIX_LOONGSON2F_NOP:
11972 mips_fix_loongson2f_nop = FALSE;
11973 break;
11974
11975 case OPTION_FIX_VR4120:
11976 mips_fix_vr4120 = 1;
11977 break;
11978
11979 case OPTION_NO_FIX_VR4120:
11980 mips_fix_vr4120 = 0;
11981 break;
11982
11983 case OPTION_FIX_VR4130:
11984 mips_fix_vr4130 = 1;
11985 break;
11986
11987 case OPTION_NO_FIX_VR4130:
11988 mips_fix_vr4130 = 0;
11989 break;
11990
11991 case OPTION_FIX_CN63XXP1:
11992 mips_fix_cn63xxp1 = TRUE;
11993 break;
11994
11995 case OPTION_NO_FIX_CN63XXP1:
11996 mips_fix_cn63xxp1 = FALSE;
11997 break;
11998
11999 case OPTION_RELAX_BRANCH:
12000 mips_relax_branch = 1;
12001 break;
12002
12003 case OPTION_NO_RELAX_BRANCH:
12004 mips_relax_branch = 0;
12005 break;
12006
12007 case OPTION_MSHARED:
12008 mips_in_shared = TRUE;
12009 break;
12010
12011 case OPTION_MNO_SHARED:
12012 mips_in_shared = FALSE;
12013 break;
12014
12015 case OPTION_MSYM32:
12016 mips_opts.sym32 = TRUE;
12017 break;
12018
12019 case OPTION_MNO_SYM32:
12020 mips_opts.sym32 = FALSE;
12021 break;
12022
12023#ifdef OBJ_ELF
12024 /* When generating ELF code, we permit -KPIC and -call_shared to
12025 select SVR4_PIC, and -non_shared to select no PIC. This is
12026 intended to be compatible with Irix 5. */
12027 case OPTION_CALL_SHARED:
12028 if (!IS_ELF)
12029 {
12030 as_bad (_("-call_shared is supported only for ELF format"));
12031 return 0;
12032 }
12033 mips_pic = SVR4_PIC;
12034 mips_abicalls = TRUE;
12035 break;
12036
12037 case OPTION_CALL_NONPIC:
12038 if (!IS_ELF)
12039 {
12040 as_bad (_("-call_nonpic is supported only for ELF format"));
12041 return 0;
12042 }
12043 mips_pic = NO_PIC;
12044 mips_abicalls = TRUE;
12045 break;
12046
12047 case OPTION_NON_SHARED:
12048 if (!IS_ELF)
12049 {
12050 as_bad (_("-non_shared is supported only for ELF format"));
12051 return 0;
12052 }
12053 mips_pic = NO_PIC;
12054 mips_abicalls = FALSE;
12055 break;
12056
12057 /* The -xgot option tells the assembler to use 32 bit offsets
12058 when accessing the got in SVR4_PIC mode. It is for Irix
12059 compatibility. */
12060 case OPTION_XGOT:
12061 mips_big_got = 1;
12062 break;
12063#endif /* OBJ_ELF */
12064
12065 case 'G':
12066 g_switch_value = atoi (arg);
12067 g_switch_seen = 1;
12068 break;
12069
12070 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
12071 and -mabi=64. */
12072 case OPTION_32:
12073 if (IS_ELF)
12074 mips_abi = O32_ABI;
12075 /* We silently ignore -32 for non-ELF targets. This greatly
12076 simplifies the construction of the MIPS GAS test cases. */
12077 break;
12078
12079#ifdef OBJ_ELF
12080 case OPTION_N32:
12081 if (!IS_ELF)
12082 {
12083 as_bad (_("-n32 is supported for ELF format only"));
12084 return 0;
12085 }
12086 mips_abi = N32_ABI;
12087 break;
12088
12089 case OPTION_64:
12090 if (!IS_ELF)
12091 {
12092 as_bad (_("-64 is supported for ELF format only"));
12093 return 0;
12094 }
12095 mips_abi = N64_ABI;
12096 if (!support_64bit_objects())
12097 as_fatal (_("No compiled in support for 64 bit object file format"));
12098 break;
12099#endif /* OBJ_ELF */
12100
12101 case OPTION_GP32:
12102 file_mips_gp32 = 1;
12103 break;
12104
12105 case OPTION_GP64:
12106 file_mips_gp32 = 0;
12107 break;
12108
12109 case OPTION_FP32:
12110 file_mips_fp32 = 1;
12111 break;
12112
12113 case OPTION_FP64:
12114 file_mips_fp32 = 0;
12115 break;
12116
12117 case OPTION_SINGLE_FLOAT:
12118 file_mips_single_float = 1;
12119 break;
12120
12121 case OPTION_DOUBLE_FLOAT:
12122 file_mips_single_float = 0;
12123 break;
12124
12125 case OPTION_SOFT_FLOAT:
12126 file_mips_soft_float = 1;
12127 break;
12128
12129 case OPTION_HARD_FLOAT:
12130 file_mips_soft_float = 0;
12131 break;
12132
12133#ifdef OBJ_ELF
12134 case OPTION_MABI:
12135 if (!IS_ELF)
12136 {
12137 as_bad (_("-mabi is supported for ELF format only"));
12138 return 0;
12139 }
12140 if (strcmp (arg, "32") == 0)
12141 mips_abi = O32_ABI;
12142 else if (strcmp (arg, "o64") == 0)
12143 mips_abi = O64_ABI;
12144 else if (strcmp (arg, "n32") == 0)
12145 mips_abi = N32_ABI;
12146 else if (strcmp (arg, "64") == 0)
12147 {
12148 mips_abi = N64_ABI;
12149 if (! support_64bit_objects())
12150 as_fatal (_("No compiled in support for 64 bit object file "
12151 "format"));
12152 }
12153 else if (strcmp (arg, "eabi") == 0)
12154 mips_abi = EABI_ABI;
12155 else
12156 {
12157 as_fatal (_("invalid abi -mabi=%s"), arg);
12158 return 0;
12159 }
12160 break;
12161#endif /* OBJ_ELF */
12162
12163 case OPTION_M7000_HILO_FIX:
12164 mips_7000_hilo_fix = TRUE;
12165 break;
12166
12167 case OPTION_MNO_7000_HILO_FIX:
12168 mips_7000_hilo_fix = FALSE;
12169 break;
12170
12171#ifdef OBJ_ELF
12172 case OPTION_MDEBUG:
12173 mips_flag_mdebug = TRUE;
12174 break;
12175
12176 case OPTION_NO_MDEBUG:
12177 mips_flag_mdebug = FALSE;
12178 break;
12179
12180 case OPTION_PDR:
12181 mips_flag_pdr = TRUE;
12182 break;
12183
12184 case OPTION_NO_PDR:
12185 mips_flag_pdr = FALSE;
12186 break;
12187
12188 case OPTION_MVXWORKS_PIC:
12189 mips_pic = VXWORKS_PIC;
12190 break;
12191#endif /* OBJ_ELF */
12192
12193 default:
12194 return 0;
12195 }
12196
12197 mips_fix_loongson2f = mips_fix_loongson2f_nop || mips_fix_loongson2f_jump;
12198
12199 return 1;
12200}
12201\f
12202/* Set up globals to generate code for the ISA or processor
12203 described by INFO. */
12204
12205static void
12206mips_set_architecture (const struct mips_cpu_info *info)
12207{
12208 if (info != 0)
12209 {
12210 file_mips_arch = info->cpu;
12211 mips_opts.arch = info->cpu;
12212 mips_opts.isa = info->isa;
12213 }
12214}
12215
12216
12217/* Likewise for tuning. */
12218
12219static void
12220mips_set_tune (const struct mips_cpu_info *info)
12221{
12222 if (info != 0)
12223 mips_tune = info->cpu;
12224}
12225
12226
12227void
12228mips_after_parse_args (void)
12229{
12230 const struct mips_cpu_info *arch_info = 0;
12231 const struct mips_cpu_info *tune_info = 0;
12232
12233 /* GP relative stuff not working for PE */
12234 if (strncmp (TARGET_OS, "pe", 2) == 0)
12235 {
12236 if (g_switch_seen && g_switch_value != 0)
12237 as_bad (_("-G not supported in this configuration."));
12238 g_switch_value = 0;
12239 }
12240
12241 if (mips_abi == NO_ABI)
12242 mips_abi = MIPS_DEFAULT_ABI;
12243
12244 /* The following code determines the architecture and register size.
12245 Similar code was added to GCC 3.3 (see override_options() in
12246 config/mips/mips.c). The GAS and GCC code should be kept in sync
12247 as much as possible. */
12248
12249 if (mips_arch_string != 0)
12250 arch_info = mips_parse_cpu ("-march", mips_arch_string);
12251
12252 if (file_mips_isa != ISA_UNKNOWN)
12253 {
12254 /* Handle -mipsN. At this point, file_mips_isa contains the
12255 ISA level specified by -mipsN, while arch_info->isa contains
12256 the -march selection (if any). */
12257 if (arch_info != 0)
12258 {
12259 /* -march takes precedence over -mipsN, since it is more descriptive.
12260 There's no harm in specifying both as long as the ISA levels
12261 are the same. */
12262 if (file_mips_isa != arch_info->isa)
12263 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
12264 mips_cpu_info_from_isa (file_mips_isa)->name,
12265 mips_cpu_info_from_isa (arch_info->isa)->name);
12266 }
12267 else
12268 arch_info = mips_cpu_info_from_isa (file_mips_isa);
12269 }
12270
12271 if (arch_info == 0)
12272 arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);
12273
12274 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
12275 as_bad (_("-march=%s is not compatible with the selected ABI"),
12276 arch_info->name);
12277
12278 mips_set_architecture (arch_info);
12279
12280 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
12281 if (mips_tune_string != 0)
12282 tune_info = mips_parse_cpu ("-mtune", mips_tune_string);
12283
12284 if (tune_info == 0)
12285 mips_set_tune (arch_info);
12286 else
12287 mips_set_tune (tune_info);
12288
12289 if (file_mips_gp32 >= 0)
12290 {
12291 /* The user specified the size of the integer registers. Make sure
12292 it agrees with the ABI and ISA. */
12293 if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
12294 as_bad (_("-mgp64 used with a 32-bit processor"));
12295 else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
12296 as_bad (_("-mgp32 used with a 64-bit ABI"));
12297 else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
12298 as_bad (_("-mgp64 used with a 32-bit ABI"));
12299 }
12300 else
12301 {
12302 /* Infer the integer register size from the ABI and processor.
12303 Restrict ourselves to 32-bit registers if that's all the
12304 processor has, or if the ABI cannot handle 64-bit registers. */
12305 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
12306 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
12307 }
12308
12309 switch (file_mips_fp32)
12310 {
12311 default:
12312 case -1:
12313 /* No user specified float register size.
12314 ??? GAS treats single-float processors as though they had 64-bit
12315 float registers (although it complains when double-precision
12316 instructions are used). As things stand, saying they have 32-bit
12317 registers would lead to spurious "register must be even" messages.
12318 So here we assume float registers are never smaller than the
12319 integer ones. */
12320 if (file_mips_gp32 == 0)
12321 /* 64-bit integer registers implies 64-bit float registers. */
12322 file_mips_fp32 = 0;
12323 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
12324 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
12325 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
12326 file_mips_fp32 = 0;
12327 else
12328 /* 32-bit float registers. */
12329 file_mips_fp32 = 1;
12330 break;
12331
12332 /* The user specified the size of the float registers. Check if it
12333 agrees with the ABI and ISA. */
12334 case 0:
12335 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12336 as_bad (_("-mfp64 used with a 32-bit fpu"));
12337 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
12338 && !ISA_HAS_MXHC1 (mips_opts.isa))
12339 as_warn (_("-mfp64 used with a 32-bit ABI"));
12340 break;
12341 case 1:
12342 if (ABI_NEEDS_64BIT_REGS (mips_abi))
12343 as_warn (_("-mfp32 used with a 64-bit ABI"));
12344 break;
12345 }
12346
12347 /* End of GCC-shared inference code. */
12348
12349 /* This flag is set when we have a 64-bit capable CPU but use only
12350 32-bit wide registers. Note that EABI does not use it. */
12351 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
12352 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
12353 || mips_abi == O32_ABI))
12354 mips_32bitmode = 1;
12355
12356 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
12357 as_bad (_("trap exception not supported at ISA 1"));
12358
12359 /* If the selected architecture includes support for ASEs, enable
12360 generation of code for them. */
12361 if (mips_opts.mips16 == -1)
12362 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
12363 if (mips_opts.ase_mips3d == -1)
12364 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
12365 && file_mips_fp32 == 0) ? 1 : 0;
12366 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
12367 as_bad (_("-mfp32 used with -mips3d"));
12368
12369 if (mips_opts.ase_mdmx == -1)
12370 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
12371 && file_mips_fp32 == 0) ? 1 : 0;
12372 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
12373 as_bad (_("-mfp32 used with -mdmx"));
12374
12375 if (mips_opts.ase_smartmips == -1)
12376 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
12377 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
12378 as_warn (_("%s ISA does not support SmartMIPS"),
12379 mips_cpu_info_from_isa (mips_opts.isa)->name);
12380
12381 if (mips_opts.ase_dsp == -1)
12382 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12383 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
12384 as_warn (_("%s ISA does not support DSP ASE"),
12385 mips_cpu_info_from_isa (mips_opts.isa)->name);
12386
12387 if (mips_opts.ase_dspr2 == -1)
12388 {
12389 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
12390 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
12391 }
12392 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
12393 as_warn (_("%s ISA does not support DSP R2 ASE"),
12394 mips_cpu_info_from_isa (mips_opts.isa)->name);
12395
12396 if (mips_opts.ase_mt == -1)
12397 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
12398 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
12399 as_warn (_("%s ISA does not support MT ASE"),
12400 mips_cpu_info_from_isa (mips_opts.isa)->name);
12401
12402 file_mips_isa = mips_opts.isa;
12403 file_ase_mips3d = mips_opts.ase_mips3d;
12404 file_ase_mdmx = mips_opts.ase_mdmx;
12405 file_ase_smartmips = mips_opts.ase_smartmips;
12406 file_ase_dsp = mips_opts.ase_dsp;
12407 file_ase_dspr2 = mips_opts.ase_dspr2;
12408 file_ase_mt = mips_opts.ase_mt;
12409 mips_opts.gp32 = file_mips_gp32;
12410 mips_opts.fp32 = file_mips_fp32;
12411 mips_opts.soft_float = file_mips_soft_float;
12412 mips_opts.single_float = file_mips_single_float;
12413
12414 if (mips_flag_mdebug < 0)
12415 {
12416#ifdef OBJ_MAYBE_ECOFF
12417 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
12418 mips_flag_mdebug = 1;
12419 else
12420#endif /* OBJ_MAYBE_ECOFF */
12421 mips_flag_mdebug = 0;
12422 }
12423}
12424\f
12425void
12426mips_init_after_args (void)
12427{
12428 /* initialize opcodes */
12429 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
12430 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
12431}
12432
12433long
12434md_pcrel_from (fixS *fixP)
12435{
12436 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
12437 switch (fixP->fx_r_type)
12438 {
12439 case BFD_RELOC_16_PCREL_S2:
12440 case BFD_RELOC_MIPS_JMP:
12441 /* Return the address of the delay slot. */
12442 return addr + 4;
12443 default:
12444 /* We have no relocation type for PC relative MIPS16 instructions. */
12445 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
12446 as_bad_where (fixP->fx_file, fixP->fx_line,
12447 _("PC relative MIPS16 instruction references a different section"));
12448 return addr;
12449 }
12450}
12451
12452/* This is called before the symbol table is processed. In order to
12453 work with gcc when using mips-tfile, we must keep all local labels.
12454 However, in other cases, we want to discard them. If we were
12455 called with -g, but we didn't see any debugging information, it may
12456 mean that gcc is smuggling debugging information through to
12457 mips-tfile, in which case we must generate all local labels. */
12458
12459void
12460mips_frob_file_before_adjust (void)
12461{
12462#ifndef NO_ECOFF_DEBUGGING
12463 if (ECOFF_DEBUGGING
12464 && mips_debug != 0
12465 && ! ecoff_debugging_seen)
12466 flag_keep_locals = 1;
12467#endif
12468}
12469
12470/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
12471 the corresponding LO16 reloc. This is called before md_apply_fix and
12472 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
12473 relocation operators.
12474
12475 For our purposes, a %lo() expression matches a %got() or %hi()
12476 expression if:
12477
12478 (a) it refers to the same symbol; and
12479 (b) the offset applied in the %lo() expression is no lower than
12480 the offset applied in the %got() or %hi().
12481
12482 (b) allows us to cope with code like:
12483
12484 lui $4,%hi(foo)
12485 lh $4,%lo(foo+2)($4)
12486
12487 ...which is legal on RELA targets, and has a well-defined behaviour
12488 if the user knows that adding 2 to "foo" will not induce a carry to
12489 the high 16 bits.
12490
12491 When several %lo()s match a particular %got() or %hi(), we use the
12492 following rules to distinguish them:
12493
12494 (1) %lo()s with smaller offsets are a better match than %lo()s with
12495 higher offsets.
12496
12497 (2) %lo()s with no matching %got() or %hi() are better than those
12498 that already have a matching %got() or %hi().
12499
12500 (3) later %lo()s are better than earlier %lo()s.
12501
12502 These rules are applied in order.
12503
12504 (1) means, among other things, that %lo()s with identical offsets are
12505 chosen if they exist.
12506
12507 (2) means that we won't associate several high-part relocations with
12508 the same low-part relocation unless there's no alternative. Having
12509 several high parts for the same low part is a GNU extension; this rule
12510 allows careful users to avoid it.
12511
12512 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12513 with the last high-part relocation being at the front of the list.
12514 It therefore makes sense to choose the last matching low-part
12515 relocation, all other things being equal. It's also easier
12516 to code that way. */
12517
12518void
12519mips_frob_file (void)
12520{
12521 struct mips_hi_fixup *l;
12522 bfd_reloc_code_real_type looking_for_rtype = BFD_RELOC_UNUSED;
12523
12524 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
12525 {
12526 segment_info_type *seginfo;
12527 bfd_boolean matched_lo_p;
12528 fixS **hi_pos, **lo_pos, **pos;
12529
12530 gas_assert (reloc_needs_lo_p (l->fixp->fx_r_type));
12531
12532 /* If a GOT16 relocation turns out to be against a global symbol,
12533 there isn't supposed to be a matching LO. */
12534 if (got16_reloc_p (l->fixp->fx_r_type)
12535 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
12536 continue;
12537
12538 /* Check quickly whether the next fixup happens to be a matching %lo. */
12539 if (fixup_has_matching_lo_p (l->fixp))
12540 continue;
12541
12542 seginfo = seg_info (l->seg);
12543
12544 /* Set HI_POS to the position of this relocation in the chain.
12545 Set LO_POS to the position of the chosen low-part relocation.
12546 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12547 relocation that matches an immediately-preceding high-part
12548 relocation. */
12549 hi_pos = NULL;
12550 lo_pos = NULL;
12551 matched_lo_p = FALSE;
12552 looking_for_rtype = matching_lo_reloc (l->fixp->fx_r_type);
12553
12554 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12555 {
12556 if (*pos == l->fixp)
12557 hi_pos = pos;
12558
12559 if ((*pos)->fx_r_type == looking_for_rtype
12560 && symbol_same_p ((*pos)->fx_addsy, l->fixp->fx_addsy)
12561 && (*pos)->fx_offset >= l->fixp->fx_offset
12562 && (lo_pos == NULL
12563 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12564 || (!matched_lo_p
12565 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12566 lo_pos = pos;
12567
12568 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
12569 && fixup_has_matching_lo_p (*pos));
12570 }
12571
12572 /* If we found a match, remove the high-part relocation from its
12573 current position and insert it before the low-part relocation.
12574 Make the offsets match so that fixup_has_matching_lo_p()
12575 will return true.
12576
12577 We don't warn about unmatched high-part relocations since some
12578 versions of gcc have been known to emit dead "lui ...%hi(...)"
12579 instructions. */
12580 if (lo_pos != NULL)
12581 {
12582 l->fixp->fx_offset = (*lo_pos)->fx_offset;
12583 if (l->fixp->fx_next != *lo_pos)
12584 {
12585 *hi_pos = l->fixp->fx_next;
12586 l->fixp->fx_next = *lo_pos;
12587 *lo_pos = l->fixp;
12588 }
12589 }
12590 }
12591}
12592
12593/* We may have combined relocations without symbols in the N32/N64 ABI.
12594 We have to prevent gas from dropping them. */
12595
12596int
12597mips_force_relocation (fixS *fixp)
12598{
12599 if (generic_force_reloc (fixp))
12600 return 1;
12601
12602 if (HAVE_NEWABI
12603 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
12604 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
12605 || hi16_reloc_p (fixp->fx_r_type)
12606 || lo16_reloc_p (fixp->fx_r_type)))
12607 return 1;
12608
12609 return 0;
12610}
12611
12612/* Apply a fixup to the object file. */
12613
12614void
12615md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12616{
12617 bfd_byte *buf;
12618 long insn;
12619 reloc_howto_type *howto;
12620
12621 /* We ignore generic BFD relocations we don't know about. */
12622 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12623 if (! howto)
12624 return;
12625
12626 gas_assert (fixP->fx_size == 4
12627 || fixP->fx_r_type == BFD_RELOC_16
12628 || fixP->fx_r_type == BFD_RELOC_64
12629 || fixP->fx_r_type == BFD_RELOC_CTOR
12630 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12631 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12632 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12633 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
12634
12635 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12636
12637 gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12638
12639 /* Don't treat parts of a composite relocation as done. There are two
12640 reasons for this:
12641
12642 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12643 should nevertheless be emitted if the first part is.
12644
12645 (2) In normal usage, composite relocations are never assembly-time
12646 constants. The easiest way of dealing with the pathological
12647 exceptions is to generate a relocation against STN_UNDEF and
12648 leave everything up to the linker. */
12649 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
12650 fixP->fx_done = 1;
12651
12652 switch (fixP->fx_r_type)
12653 {
12654 case BFD_RELOC_MIPS_TLS_GD:
12655 case BFD_RELOC_MIPS_TLS_LDM:
12656 case BFD_RELOC_MIPS_TLS_DTPREL32:
12657 case BFD_RELOC_MIPS_TLS_DTPREL64:
12658 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12659 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12660 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12661 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12662 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12663 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12664 /* fall through */
12665
12666 case BFD_RELOC_MIPS_JMP:
12667 case BFD_RELOC_MIPS_SHIFT5:
12668 case BFD_RELOC_MIPS_SHIFT6:
12669 case BFD_RELOC_MIPS_GOT_DISP:
12670 case BFD_RELOC_MIPS_GOT_PAGE:
12671 case BFD_RELOC_MIPS_GOT_OFST:
12672 case BFD_RELOC_MIPS_SUB:
12673 case BFD_RELOC_MIPS_INSERT_A:
12674 case BFD_RELOC_MIPS_INSERT_B:
12675 case BFD_RELOC_MIPS_DELETE:
12676 case BFD_RELOC_MIPS_HIGHEST:
12677 case BFD_RELOC_MIPS_HIGHER:
12678 case BFD_RELOC_MIPS_SCN_DISP:
12679 case BFD_RELOC_MIPS_REL16:
12680 case BFD_RELOC_MIPS_RELGOT:
12681 case BFD_RELOC_MIPS_JALR:
12682 case BFD_RELOC_HI16:
12683 case BFD_RELOC_HI16_S:
12684 case BFD_RELOC_GPREL16:
12685 case BFD_RELOC_MIPS_LITERAL:
12686 case BFD_RELOC_MIPS_CALL16:
12687 case BFD_RELOC_MIPS_GOT16:
12688 case BFD_RELOC_GPREL32:
12689 case BFD_RELOC_MIPS_GOT_HI16:
12690 case BFD_RELOC_MIPS_GOT_LO16:
12691 case BFD_RELOC_MIPS_CALL_HI16:
12692 case BFD_RELOC_MIPS_CALL_LO16:
12693 case BFD_RELOC_MIPS16_GPREL:
12694 case BFD_RELOC_MIPS16_GOT16:
12695 case BFD_RELOC_MIPS16_CALL16:
12696 case BFD_RELOC_MIPS16_HI16:
12697 case BFD_RELOC_MIPS16_HI16_S:
12698 case BFD_RELOC_MIPS16_JMP:
12699 /* Nothing needed to do. The value comes from the reloc entry. */
12700 break;
12701
12702 case BFD_RELOC_64:
12703 /* This is handled like BFD_RELOC_32, but we output a sign
12704 extended value if we are only 32 bits. */
12705 if (fixP->fx_done)
12706 {
12707 if (8 <= sizeof (valueT))
12708 md_number_to_chars ((char *) buf, *valP, 8);
12709 else
12710 {
12711 valueT hiv;
12712
12713 if ((*valP & 0x80000000) != 0)
12714 hiv = 0xffffffff;
12715 else
12716 hiv = 0;
12717 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
12718 *valP, 4);
12719 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12720 hiv, 4);
12721 }
12722 }
12723 break;
12724
12725 case BFD_RELOC_RVA:
12726 case BFD_RELOC_32:
12727 case BFD_RELOC_16:
12728 /* If we are deleting this reloc entry, we must fill in the
12729 value now. This can happen if we have a .word which is not
12730 resolved when it appears but is later defined. */
12731 if (fixP->fx_done)
12732 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
12733 break;
12734
12735 case BFD_RELOC_LO16:
12736 case BFD_RELOC_MIPS16_LO16:
12737 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12738 may be safe to remove, but if so it's not obvious. */
12739 /* When handling an embedded PIC switch statement, we can wind
12740 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12741 if (fixP->fx_done)
12742 {
12743 if (*valP + 0x8000 > 0xffff)
12744 as_bad_where (fixP->fx_file, fixP->fx_line,
12745 _("relocation overflow"));
12746 if (target_big_endian)
12747 buf += 2;
12748 md_number_to_chars ((char *) buf, *valP, 2);
12749 }
12750 break;
12751
12752 case BFD_RELOC_16_PCREL_S2:
12753 if ((*valP & 0x3) != 0)
12754 as_bad_where (fixP->fx_file, fixP->fx_line,
12755 _("Branch to misaligned address (%lx)"), (long) *valP);
12756
12757 /* We need to save the bits in the instruction since fixup_segment()
12758 might be deleting the relocation entry (i.e., a branch within
12759 the current segment). */
12760 if (! fixP->fx_done)
12761 break;
12762
12763 /* Update old instruction data. */
12764 if (target_big_endian)
12765 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12766 else
12767 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12768
12769 if (*valP + 0x20000 <= 0x3ffff)
12770 {
12771 insn |= (*valP >> 2) & 0xffff;
12772 md_number_to_chars ((char *) buf, insn, 4);
12773 }
12774 else if (mips_pic == NO_PIC
12775 && fixP->fx_done
12776 && fixP->fx_frag->fr_address >= text_section->vma
12777 && (fixP->fx_frag->fr_address
12778 < text_section->vma + bfd_get_section_size (text_section))
12779 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12780 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12781 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12782 {
12783 /* The branch offset is too large. If this is an
12784 unconditional branch, and we are not generating PIC code,
12785 we can convert it to an absolute jump instruction. */
12786 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
12787 insn = 0x0c000000; /* jal */
12788 else
12789 insn = 0x08000000; /* j */
12790 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
12791 fixP->fx_done = 0;
12792 fixP->fx_addsy = section_symbol (text_section);
12793 *valP += md_pcrel_from (fixP);
12794 md_number_to_chars ((char *) buf, insn, 4);
12795 }
12796 else
12797 {
12798 /* If we got here, we have branch-relaxation disabled,
12799 and there's nothing we can do to fix this instruction
12800 without turning it into a longer sequence. */
12801 as_bad_where (fixP->fx_file, fixP->fx_line,
12802 _("Branch out of range"));
12803 }
12804 break;
12805
12806 case BFD_RELOC_VTABLE_INHERIT:
12807 fixP->fx_done = 0;
12808 if (fixP->fx_addsy
12809 && !S_IS_DEFINED (fixP->fx_addsy)
12810 && !S_IS_WEAK (fixP->fx_addsy))
12811 S_SET_WEAK (fixP->fx_addsy);
12812 break;
12813
12814 case BFD_RELOC_VTABLE_ENTRY:
12815 fixP->fx_done = 0;
12816 break;
12817
12818 default:
12819 internalError ();
12820 }
12821
12822 /* Remember value for tc_gen_reloc. */
12823 fixP->fx_addnumber = *valP;
12824}
12825
12826static symbolS *
12827get_symbol (void)
12828{
12829 int c;
12830 char *name;
12831 symbolS *p;
12832
12833 name = input_line_pointer;
12834 c = get_symbol_end ();
12835 p = (symbolS *) symbol_find_or_make (name);
12836 *input_line_pointer = c;
12837 return p;
12838}
12839
12840/* Align the current frag to a given power of two. If a particular
12841 fill byte should be used, FILL points to an integer that contains
12842 that byte, otherwise FILL is null.
12843
12844 The MIPS assembler also automatically adjusts any preceding
12845 label. */
12846
12847static void
12848mips_align (int to, int *fill, symbolS *label)
12849{
12850 mips_emit_delays ();
12851 mips_record_mips16_mode ();
12852 if (fill == NULL && subseg_text_p (now_seg))
12853 frag_align_code (to, 0);
12854 else
12855 frag_align (to, fill ? *fill : 0, 0);
12856 record_alignment (now_seg, to);
12857 if (label != NULL)
12858 {
12859 gas_assert (S_GET_SEGMENT (label) == now_seg);
12860 symbol_set_frag (label, frag_now);
12861 S_SET_VALUE (label, (valueT) frag_now_fix ());
12862 }
12863}
12864
12865/* Align to a given power of two. .align 0 turns off the automatic
12866 alignment used by the data creating pseudo-ops. */
12867
12868static void
12869s_align (int x ATTRIBUTE_UNUSED)
12870{
12871 int temp, fill_value, *fill_ptr;
12872 long max_alignment = 28;
12873
12874 /* o Note that the assembler pulls down any immediately preceding label
12875 to the aligned address.
12876 o It's not documented but auto alignment is reinstated by
12877 a .align pseudo instruction.
12878 o Note also that after auto alignment is turned off the mips assembler
12879 issues an error on attempt to assemble an improperly aligned data item.
12880 We don't. */
12881
12882 temp = get_absolute_expression ();
12883 if (temp > max_alignment)
12884 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12885 else if (temp < 0)
12886 {
12887 as_warn (_("Alignment negative: 0 assumed."));
12888 temp = 0;
12889 }
12890 if (*input_line_pointer == ',')
12891 {
12892 ++input_line_pointer;
12893 fill_value = get_absolute_expression ();
12894 fill_ptr = &fill_value;
12895 }
12896 else
12897 fill_ptr = 0;
12898 if (temp)
12899 {
12900 segment_info_type *si = seg_info (now_seg);
12901 struct insn_label_list *l = si->label_list;
12902 /* Auto alignment should be switched on by next section change. */
12903 auto_align = 1;
12904 mips_align (temp, fill_ptr, l != NULL ? l->label : NULL);
12905 }
12906 else
12907 {
12908 auto_align = 0;
12909 }
12910
12911 demand_empty_rest_of_line ();
12912}
12913
12914static void
12915s_change_sec (int sec)
12916{
12917 segT seg;
12918
12919#ifdef OBJ_ELF
12920 /* The ELF backend needs to know that we are changing sections, so
12921 that .previous works correctly. We could do something like check
12922 for an obj_section_change_hook macro, but that might be confusing
12923 as it would not be appropriate to use it in the section changing
12924 functions in read.c, since obj-elf.c intercepts those. FIXME:
12925 This should be cleaner, somehow. */
12926 if (IS_ELF)
12927 obj_elf_section_change_hook ();
12928#endif
12929
12930 mips_emit_delays ();
12931
12932 switch (sec)
12933 {
12934 case 't':
12935 s_text (0);
12936 break;
12937 case 'd':
12938 s_data (0);
12939 break;
12940 case 'b':
12941 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12942 demand_empty_rest_of_line ();
12943 break;
12944
12945 case 'r':
12946 seg = subseg_new (RDATA_SECTION_NAME,
12947 (subsegT) get_absolute_expression ());
12948 if (IS_ELF)
12949 {
12950 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12951 | SEC_READONLY | SEC_RELOC
12952 | SEC_DATA));
12953 if (strncmp (TARGET_OS, "elf", 3) != 0)
12954 record_alignment (seg, 4);
12955 }
12956 demand_empty_rest_of_line ();
12957 break;
12958
12959 case 's':
12960 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12961 if (IS_ELF)
12962 {
12963 bfd_set_section_flags (stdoutput, seg,
12964 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12965 if (strncmp (TARGET_OS, "elf", 3) != 0)
12966 record_alignment (seg, 4);
12967 }
12968 demand_empty_rest_of_line ();
12969 break;
12970
12971 case 'B':
12972 seg = subseg_new (".sbss", (subsegT) get_absolute_expression ());
12973 if (IS_ELF)
12974 {
12975 bfd_set_section_flags (stdoutput, seg, SEC_ALLOC);
12976 if (strncmp (TARGET_OS, "elf", 3) != 0)
12977 record_alignment (seg, 4);
12978 }
12979 demand_empty_rest_of_line ();
12980 break;
12981 }
12982
12983 auto_align = 1;
12984}
12985
12986void
12987s_change_section (int ignore ATTRIBUTE_UNUSED)
12988{
12989#ifdef OBJ_ELF
12990 char *section_name;
12991 char c;
12992 char next_c = 0;
12993 int section_type;
12994 int section_flag;
12995 int section_entry_size;
12996 int section_alignment;
12997
12998 if (!IS_ELF)
12999 return;
13000
13001 section_name = input_line_pointer;
13002 c = get_symbol_end ();
13003 if (c)
13004 next_c = *(input_line_pointer + 1);
13005
13006 /* Do we have .section Name<,"flags">? */
13007 if (c != ',' || (c == ',' && next_c == '"'))
13008 {
13009 /* just after name is now '\0'. */
13010 *input_line_pointer = c;
13011 input_line_pointer = section_name;
13012 obj_elf_section (ignore);
13013 return;
13014 }
13015 input_line_pointer++;
13016
13017 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
13018 if (c == ',')
13019 section_type = get_absolute_expression ();
13020 else
13021 section_type = 0;
13022 if (*input_line_pointer++ == ',')
13023 section_flag = get_absolute_expression ();
13024 else
13025 section_flag = 0;
13026 if (*input_line_pointer++ == ',')
13027 section_entry_size = get_absolute_expression ();
13028 else
13029 section_entry_size = 0;
13030 if (*input_line_pointer++ == ',')
13031 section_alignment = get_absolute_expression ();
13032 else
13033 section_alignment = 0;
13034 /* FIXME: really ignore? */
13035 (void) section_alignment;
13036
13037 section_name = xstrdup (section_name);
13038
13039 /* When using the generic form of .section (as implemented by obj-elf.c),
13040 there's no way to set the section type to SHT_MIPS_DWARF. Users have
13041 traditionally had to fall back on the more common @progbits instead.
13042
13043 There's nothing really harmful in this, since bfd will correct
13044 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
13045 means that, for backwards compatibility, the special_section entries
13046 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
13047
13048 Even so, we shouldn't force users of the MIPS .section syntax to
13049 incorrectly label the sections as SHT_PROGBITS. The best compromise
13050 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
13051 generic type-checking code. */
13052 if (section_type == SHT_MIPS_DWARF)
13053 section_type = SHT_PROGBITS;
13054
13055 obj_elf_change_section (section_name, section_type, section_flag,
13056 section_entry_size, 0, 0, 0);
13057
13058 if (now_seg->name != section_name)
13059 free (section_name);
13060#endif /* OBJ_ELF */
13061}
13062
13063void
13064mips_enable_auto_align (void)
13065{
13066 auto_align = 1;
13067}
13068
13069static void
13070s_cons (int log_size)
13071{
13072 segment_info_type *si = seg_info (now_seg);
13073 struct insn_label_list *l = si->label_list;
13074 symbolS *label;
13075
13076 label = l != NULL ? l->label : NULL;
13077 mips_emit_delays ();
13078 if (log_size > 0 && auto_align)
13079 mips_align (log_size, 0, label);
13080 cons (1 << log_size);
13081 mips_clear_insn_labels ();
13082}
13083
13084static void
13085s_float_cons (int type)
13086{
13087 segment_info_type *si = seg_info (now_seg);
13088 struct insn_label_list *l = si->label_list;
13089 symbolS *label;
13090
13091 label = l != NULL ? l->label : NULL;
13092
13093 mips_emit_delays ();
13094
13095 if (auto_align)
13096 {
13097 if (type == 'd')
13098 mips_align (3, 0, label);
13099 else
13100 mips_align (2, 0, label);
13101 }
13102
13103 float_cons (type);
13104 mips_clear_insn_labels ();
13105}
13106
13107/* Handle .globl. We need to override it because on Irix 5 you are
13108 permitted to say
13109 .globl foo .text
13110 where foo is an undefined symbol, to mean that foo should be
13111 considered to be the address of a function. */
13112
13113static void
13114s_mips_globl (int x ATTRIBUTE_UNUSED)
13115{
13116 char *name;
13117 int c;
13118 symbolS *symbolP;
13119 flagword flag;
13120
13121 do
13122 {
13123 name = input_line_pointer;
13124 c = get_symbol_end ();
13125 symbolP = symbol_find_or_make (name);
13126 S_SET_EXTERNAL (symbolP);
13127
13128 *input_line_pointer = c;
13129 SKIP_WHITESPACE ();
13130
13131 /* On Irix 5, every global symbol that is not explicitly labelled as
13132 being a function is apparently labelled as being an object. */
13133 flag = BSF_OBJECT;
13134
13135 if (!is_end_of_line[(unsigned char) *input_line_pointer]
13136 && (*input_line_pointer != ','))
13137 {
13138 char *secname;
13139 asection *sec;
13140
13141 secname = input_line_pointer;
13142 c = get_symbol_end ();
13143 sec = bfd_get_section_by_name (stdoutput, secname);
13144 if (sec == NULL)
13145 as_bad (_("%s: no such section"), secname);
13146 *input_line_pointer = c;
13147
13148 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
13149 flag = BSF_FUNCTION;
13150 }
13151
13152 symbol_get_bfdsym (symbolP)->flags |= flag;
13153
13154 c = *input_line_pointer;
13155 if (c == ',')
13156 {
13157 input_line_pointer++;
13158 SKIP_WHITESPACE ();
13159 if (is_end_of_line[(unsigned char) *input_line_pointer])
13160 c = '\n';
13161 }
13162 }
13163 while (c == ',');
13164
13165 demand_empty_rest_of_line ();
13166}
13167
13168static void
13169s_option (int x ATTRIBUTE_UNUSED)
13170{
13171 char *opt;
13172 char c;
13173
13174 opt = input_line_pointer;
13175 c = get_symbol_end ();
13176
13177 if (*opt == 'O')
13178 {
13179 /* FIXME: What does this mean? */
13180 }
13181 else if (strncmp (opt, "pic", 3) == 0)
13182 {
13183 int i;
13184
13185 i = atoi (opt + 3);
13186 if (i == 0)
13187 mips_pic = NO_PIC;
13188 else if (i == 2)
13189 {
13190 mips_pic = SVR4_PIC;
13191 mips_abicalls = TRUE;
13192 }
13193 else
13194 as_bad (_(".option pic%d not supported"), i);
13195
13196 if (mips_pic == SVR4_PIC)
13197 {
13198 if (g_switch_seen && g_switch_value != 0)
13199 as_warn (_("-G may not be used with SVR4 PIC code"));
13200 g_switch_value = 0;
13201 bfd_set_gp_size (stdoutput, 0);
13202 }
13203 }
13204 else
13205 as_warn (_("Unrecognized option \"%s\""), opt);
13206
13207 *input_line_pointer = c;
13208 demand_empty_rest_of_line ();
13209}
13210
13211/* This structure is used to hold a stack of .set values. */
13212
13213struct mips_option_stack
13214{
13215 struct mips_option_stack *next;
13216 struct mips_set_options options;
13217};
13218
13219static struct mips_option_stack *mips_opts_stack;
13220
13221/* Handle the .set pseudo-op. */
13222
13223static void
13224s_mipsset (int x ATTRIBUTE_UNUSED)
13225{
13226 char *name = input_line_pointer, ch;
13227
13228 while (!is_end_of_line[(unsigned char) *input_line_pointer])
13229 ++input_line_pointer;
13230 ch = *input_line_pointer;
13231 *input_line_pointer = '\0';
13232
13233 if (strcmp (name, "reorder") == 0)
13234 {
13235 if (mips_opts.noreorder)
13236 end_noreorder ();
13237 }
13238 else if (strcmp (name, "noreorder") == 0)
13239 {
13240 if (!mips_opts.noreorder)
13241 start_noreorder ();
13242 }
13243 else if (strncmp (name, "at=", 3) == 0)
13244 {
13245 char *s = name + 3;
13246
13247 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
13248 as_bad (_("Unrecognized register name `%s'"), s);
13249 }
13250 else if (strcmp (name, "at") == 0)
13251 {
13252 mips_opts.at = ATREG;
13253 }
13254 else if (strcmp (name, "noat") == 0)
13255 {
13256 mips_opts.at = ZERO;
13257 }
13258 else if (strcmp (name, "macro") == 0)
13259 {
13260 mips_opts.warn_about_macros = 0;
13261 }
13262 else if (strcmp (name, "nomacro") == 0)
13263 {
13264 if (mips_opts.noreorder == 0)
13265 as_bad (_("`noreorder' must be set before `nomacro'"));
13266 mips_opts.warn_about_macros = 1;
13267 }
13268 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
13269 {
13270 mips_opts.nomove = 0;
13271 }
13272 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
13273 {
13274 mips_opts.nomove = 1;
13275 }
13276 else if (strcmp (name, "bopt") == 0)
13277 {
13278 mips_opts.nobopt = 0;
13279 }
13280 else if (strcmp (name, "nobopt") == 0)
13281 {
13282 mips_opts.nobopt = 1;
13283 }
13284 else if (strcmp (name, "gp=default") == 0)
13285 mips_opts.gp32 = file_mips_gp32;
13286 else if (strcmp (name, "gp=32") == 0)
13287 mips_opts.gp32 = 1;
13288 else if (strcmp (name, "gp=64") == 0)
13289 {
13290 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
13291 as_warn (_("%s isa does not support 64-bit registers"),
13292 mips_cpu_info_from_isa (mips_opts.isa)->name);
13293 mips_opts.gp32 = 0;
13294 }
13295 else if (strcmp (name, "fp=default") == 0)
13296 mips_opts.fp32 = file_mips_fp32;
13297 else if (strcmp (name, "fp=32") == 0)
13298 mips_opts.fp32 = 1;
13299 else if (strcmp (name, "fp=64") == 0)
13300 {
13301 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
13302 as_warn (_("%s isa does not support 64-bit floating point registers"),
13303 mips_cpu_info_from_isa (mips_opts.isa)->name);
13304 mips_opts.fp32 = 0;
13305 }
13306 else if (strcmp (name, "softfloat") == 0)
13307 mips_opts.soft_float = 1;
13308 else if (strcmp (name, "hardfloat") == 0)
13309 mips_opts.soft_float = 0;
13310 else if (strcmp (name, "singlefloat") == 0)
13311 mips_opts.single_float = 1;
13312 else if (strcmp (name, "doublefloat") == 0)
13313 mips_opts.single_float = 0;
13314 else if (strcmp (name, "mips16") == 0
13315 || strcmp (name, "MIPS-16") == 0)
13316 mips_opts.mips16 = 1;
13317 else if (strcmp (name, "nomips16") == 0
13318 || strcmp (name, "noMIPS-16") == 0)
13319 mips_opts.mips16 = 0;
13320 else if (strcmp (name, "smartmips") == 0)
13321 {
13322 if (!ISA_SUPPORTS_SMARTMIPS)
13323 as_warn (_("%s ISA does not support SmartMIPS ASE"),
13324 mips_cpu_info_from_isa (mips_opts.isa)->name);
13325 mips_opts.ase_smartmips = 1;
13326 }
13327 else if (strcmp (name, "nosmartmips") == 0)
13328 mips_opts.ase_smartmips = 0;
13329 else if (strcmp (name, "mips3d") == 0)
13330 mips_opts.ase_mips3d = 1;
13331 else if (strcmp (name, "nomips3d") == 0)
13332 mips_opts.ase_mips3d = 0;
13333 else if (strcmp (name, "mdmx") == 0)
13334 mips_opts.ase_mdmx = 1;
13335 else if (strcmp (name, "nomdmx") == 0)
13336 mips_opts.ase_mdmx = 0;
13337 else if (strcmp (name, "dsp") == 0)
13338 {
13339 if (!ISA_SUPPORTS_DSP_ASE)
13340 as_warn (_("%s ISA does not support DSP ASE"),
13341 mips_cpu_info_from_isa (mips_opts.isa)->name);
13342 mips_opts.ase_dsp = 1;
13343 mips_opts.ase_dspr2 = 0;
13344 }
13345 else if (strcmp (name, "nodsp") == 0)
13346 {
13347 mips_opts.ase_dsp = 0;
13348 mips_opts.ase_dspr2 = 0;
13349 }
13350 else if (strcmp (name, "dspr2") == 0)
13351 {
13352 if (!ISA_SUPPORTS_DSPR2_ASE)
13353 as_warn (_("%s ISA does not support DSP R2 ASE"),
13354 mips_cpu_info_from_isa (mips_opts.isa)->name);
13355 mips_opts.ase_dspr2 = 1;
13356 mips_opts.ase_dsp = 1;
13357 }
13358 else if (strcmp (name, "nodspr2") == 0)
13359 {
13360 mips_opts.ase_dspr2 = 0;
13361 mips_opts.ase_dsp = 0;
13362 }
13363 else if (strcmp (name, "mt") == 0)
13364 {
13365 if (!ISA_SUPPORTS_MT_ASE)
13366 as_warn (_("%s ISA does not support MT ASE"),
13367 mips_cpu_info_from_isa (mips_opts.isa)->name);
13368 mips_opts.ase_mt = 1;
13369 }
13370 else if (strcmp (name, "nomt") == 0)
13371 mips_opts.ase_mt = 0;
13372 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
13373 {
13374 int reset = 0;
13375
13376 /* Permit the user to change the ISA and architecture on the fly.
13377 Needless to say, misuse can cause serious problems. */
13378 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
13379 {
13380 reset = 1;
13381 mips_opts.isa = file_mips_isa;
13382 mips_opts.arch = file_mips_arch;
13383 }
13384 else if (strncmp (name, "arch=", 5) == 0)
13385 {
13386 const struct mips_cpu_info *p;
13387
13388 p = mips_parse_cpu("internal use", name + 5);
13389 if (!p)
13390 as_bad (_("unknown architecture %s"), name + 5);
13391 else
13392 {
13393 mips_opts.arch = p->cpu;
13394 mips_opts.isa = p->isa;
13395 }
13396 }
13397 else if (strncmp (name, "mips", 4) == 0)
13398 {
13399 const struct mips_cpu_info *p;
13400
13401 p = mips_parse_cpu("internal use", name);
13402 if (!p)
13403 as_bad (_("unknown ISA level %s"), name + 4);
13404 else
13405 {
13406 mips_opts.arch = p->cpu;
13407 mips_opts.isa = p->isa;
13408 }
13409 }
13410 else
13411 as_bad (_("unknown ISA or architecture %s"), name);
13412
13413 switch (mips_opts.isa)
13414 {
13415 case 0:
13416 break;
13417 case ISA_MIPS1:
13418 case ISA_MIPS2:
13419 case ISA_MIPS32:
13420 case ISA_MIPS32R2:
13421 mips_opts.gp32 = 1;
13422 mips_opts.fp32 = 1;
13423 break;
13424 case ISA_MIPS3:
13425 case ISA_MIPS4:
13426 case ISA_MIPS5:
13427 case ISA_MIPS64:
13428 case ISA_MIPS64R2:
13429 mips_opts.gp32 = 0;
13430 mips_opts.fp32 = 0;
13431 break;
13432 default:
13433 as_bad (_("unknown ISA level %s"), name + 4);
13434 break;
13435 }
13436 if (reset)
13437 {
13438 mips_opts.gp32 = file_mips_gp32;
13439 mips_opts.fp32 = file_mips_fp32;
13440 }
13441 }
13442 else if (strcmp (name, "autoextend") == 0)
13443 mips_opts.noautoextend = 0;
13444 else if (strcmp (name, "noautoextend") == 0)
13445 mips_opts.noautoextend = 1;
13446 else if (strcmp (name, "push") == 0)
13447 {
13448 struct mips_option_stack *s;
13449
13450 s = (struct mips_option_stack *) xmalloc (sizeof *s);
13451 s->next = mips_opts_stack;
13452 s->options = mips_opts;
13453 mips_opts_stack = s;
13454 }
13455 else if (strcmp (name, "pop") == 0)
13456 {
13457 struct mips_option_stack *s;
13458
13459 s = mips_opts_stack;
13460 if (s == NULL)
13461 as_bad (_(".set pop with no .set push"));
13462 else
13463 {
13464 /* If we're changing the reorder mode we need to handle
13465 delay slots correctly. */
13466 if (s->options.noreorder && ! mips_opts.noreorder)
13467 start_noreorder ();
13468 else if (! s->options.noreorder && mips_opts.noreorder)
13469 end_noreorder ();
13470
13471 mips_opts = s->options;
13472 mips_opts_stack = s->next;
13473 free (s);
13474 }
13475 }
13476 else if (strcmp (name, "sym32") == 0)
13477 mips_opts.sym32 = TRUE;
13478 else if (strcmp (name, "nosym32") == 0)
13479 mips_opts.sym32 = FALSE;
13480 else if (strchr (name, ','))
13481 {
13482 /* Generic ".set" directive; use the generic handler. */
13483 *input_line_pointer = ch;
13484 input_line_pointer = name;
13485 s_set (0);
13486 return;
13487 }
13488 else
13489 {
13490 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
13491 }
13492 *input_line_pointer = ch;
13493 demand_empty_rest_of_line ();
13494}
13495
13496/* Handle the .abicalls pseudo-op. I believe this is equivalent to
13497 .option pic2. It means to generate SVR4 PIC calls. */
13498
13499static void
13500s_abicalls (int ignore ATTRIBUTE_UNUSED)
13501{
13502 mips_pic = SVR4_PIC;
13503 mips_abicalls = TRUE;
13504
13505 if (g_switch_seen && g_switch_value != 0)
13506 as_warn (_("-G may not be used with SVR4 PIC code"));
13507 g_switch_value = 0;
13508
13509 bfd_set_gp_size (stdoutput, 0);
13510 demand_empty_rest_of_line ();
13511}
13512
13513/* Handle the .cpload pseudo-op. This is used when generating SVR4
13514 PIC code. It sets the $gp register for the function based on the
13515 function address, which is in the register named in the argument.
13516 This uses a relocation against _gp_disp, which is handled specially
13517 by the linker. The result is:
13518 lui $gp,%hi(_gp_disp)
13519 addiu $gp,$gp,%lo(_gp_disp)
13520 addu $gp,$gp,.cpload argument
13521 The .cpload argument is normally $25 == $t9.
13522
13523 The -mno-shared option changes this to:
13524 lui $gp,%hi(__gnu_local_gp)
13525 addiu $gp,$gp,%lo(__gnu_local_gp)
13526 and the argument is ignored. This saves an instruction, but the
13527 resulting code is not position independent; it uses an absolute
13528 address for __gnu_local_gp. Thus code assembled with -mno-shared
13529 can go into an ordinary executable, but not into a shared library. */
13530
13531static void
13532s_cpload (int ignore ATTRIBUTE_UNUSED)
13533{
13534 expressionS ex;
13535 int reg;
13536 int in_shared;
13537
13538 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13539 .cpload is ignored. */
13540 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13541 {
13542 s_ignore (0);
13543 return;
13544 }
13545
13546 /* .cpload should be in a .set noreorder section. */
13547 if (mips_opts.noreorder == 0)
13548 as_warn (_(".cpload not in noreorder section"));
13549
13550 reg = tc_get_register (0);
13551
13552 /* If we need to produce a 64-bit address, we are better off using
13553 the default instruction sequence. */
13554 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
13555
13556 ex.X_op = O_symbol;
13557 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
13558 "__gnu_local_gp");
13559 ex.X_op_symbol = NULL;
13560 ex.X_add_number = 0;
13561
13562 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13563 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13564
13565 macro_start ();
13566 macro_build_lui (&ex, mips_gp_register);
13567 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13568 mips_gp_register, BFD_RELOC_LO16);
13569 if (in_shared)
13570 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
13571 mips_gp_register, reg);
13572 macro_end ();
13573
13574 demand_empty_rest_of_line ();
13575}
13576
13577/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13578 .cpsetup $reg1, offset|$reg2, label
13579
13580 If offset is given, this results in:
13581 sd $gp, offset($sp)
13582 lui $gp, %hi(%neg(%gp_rel(label)))
13583 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13584 daddu $gp, $gp, $reg1
13585
13586 If $reg2 is given, this results in:
13587 daddu $reg2, $gp, $0
13588 lui $gp, %hi(%neg(%gp_rel(label)))
13589 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13590 daddu $gp, $gp, $reg1
13591 $reg1 is normally $25 == $t9.
13592
13593 The -mno-shared option replaces the last three instructions with
13594 lui $gp,%hi(_gp)
13595 addiu $gp,$gp,%lo(_gp) */
13596
13597static void
13598s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13599{
13600 expressionS ex_off;
13601 expressionS ex_sym;
13602 int reg1;
13603
13604 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13605 We also need NewABI support. */
13606 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13607 {
13608 s_ignore (0);
13609 return;
13610 }
13611
13612 reg1 = tc_get_register (0);
13613 SKIP_WHITESPACE ();
13614 if (*input_line_pointer != ',')
13615 {
13616 as_bad (_("missing argument separator ',' for .cpsetup"));
13617 return;
13618 }
13619 else
13620 ++input_line_pointer;
13621 SKIP_WHITESPACE ();
13622 if (*input_line_pointer == '$')
13623 {
13624 mips_cpreturn_register = tc_get_register (0);
13625 mips_cpreturn_offset = -1;
13626 }
13627 else
13628 {
13629 mips_cpreturn_offset = get_absolute_expression ();
13630 mips_cpreturn_register = -1;
13631 }
13632 SKIP_WHITESPACE ();
13633 if (*input_line_pointer != ',')
13634 {
13635 as_bad (_("missing argument separator ',' for .cpsetup"));
13636 return;
13637 }
13638 else
13639 ++input_line_pointer;
13640 SKIP_WHITESPACE ();
13641 expression (&ex_sym);
13642
13643 macro_start ();
13644 if (mips_cpreturn_register == -1)
13645 {
13646 ex_off.X_op = O_constant;
13647 ex_off.X_add_symbol = NULL;
13648 ex_off.X_op_symbol = NULL;
13649 ex_off.X_add_number = mips_cpreturn_offset;
13650
13651 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
13652 BFD_RELOC_LO16, SP);
13653 }
13654 else
13655 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
13656 mips_gp_register, 0);
13657
13658 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
13659 {
13660 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
13661 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
13662 BFD_RELOC_HI16_S);
13663
13664 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
13665 mips_gp_register, -1, BFD_RELOC_GPREL16,
13666 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
13667
13668 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
13669 mips_gp_register, reg1);
13670 }
13671 else
13672 {
13673 expressionS ex;
13674
13675 ex.X_op = O_symbol;
13676 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
13677 ex.X_op_symbol = NULL;
13678 ex.X_add_number = 0;
13679
13680 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13681 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
13682
13683 macro_build_lui (&ex, mips_gp_register);
13684 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
13685 mips_gp_register, BFD_RELOC_LO16);
13686 }
13687
13688 macro_end ();
13689
13690 demand_empty_rest_of_line ();
13691}
13692
13693static void
13694s_cplocal (int ignore ATTRIBUTE_UNUSED)
13695{
13696 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13697 .cplocal is ignored. */
13698 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13699 {
13700 s_ignore (0);
13701 return;
13702 }
13703
13704 mips_gp_register = tc_get_register (0);
13705 demand_empty_rest_of_line ();
13706}
13707
13708/* Handle the .cprestore pseudo-op. This stores $gp into a given
13709 offset from $sp. The offset is remembered, and after making a PIC
13710 call $gp is restored from that location. */
13711
13712static void
13713s_cprestore (int ignore ATTRIBUTE_UNUSED)
13714{
13715 expressionS ex;
13716
13717 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13718 .cprestore is ignored. */
13719 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
13720 {
13721 s_ignore (0);
13722 return;
13723 }
13724
13725 mips_cprestore_offset = get_absolute_expression ();
13726 mips_cprestore_valid = 1;
13727
13728 ex.X_op = O_constant;
13729 ex.X_add_symbol = NULL;
13730 ex.X_op_symbol = NULL;
13731 ex.X_add_number = mips_cprestore_offset;
13732
13733 macro_start ();
13734 macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
13735 SP, HAVE_64BIT_ADDRESSES);
13736 macro_end ();
13737
13738 demand_empty_rest_of_line ();
13739}
13740
13741/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13742 was given in the preceding .cpsetup, it results in:
13743 ld $gp, offset($sp)
13744
13745 If a register $reg2 was given there, it results in:
13746 daddu $gp, $reg2, $0 */
13747
13748static void
13749s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13750{
13751 expressionS ex;
13752
13753 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13754 We also need NewABI support. */
13755 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13756 {
13757 s_ignore (0);
13758 return;
13759 }
13760
13761 macro_start ();
13762 if (mips_cpreturn_register == -1)
13763 {
13764 ex.X_op = O_constant;
13765 ex.X_add_symbol = NULL;
13766 ex.X_op_symbol = NULL;
13767 ex.X_add_number = mips_cpreturn_offset;
13768
13769 macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
13770 }
13771 else
13772 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13773 mips_cpreturn_register, 0);
13774 macro_end ();
13775
13776 demand_empty_rest_of_line ();
13777}
13778
13779/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13780 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13781 use in DWARF debug information. */
13782
13783static void
13784s_dtprel_internal (size_t bytes)
13785{
13786 expressionS ex;
13787 char *p;
13788
13789 expression (&ex);
13790
13791 if (ex.X_op != O_symbol)
13792 {
13793 as_bad (_("Unsupported use of %s"), (bytes == 8
13794 ? ".dtpreldword"
13795 : ".dtprelword"));
13796 ignore_rest_of_line ();
13797 }
13798
13799 p = frag_more (bytes);
13800 md_number_to_chars (p, 0, bytes);
13801 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13802 (bytes == 8
13803 ? BFD_RELOC_MIPS_TLS_DTPREL64
13804 : BFD_RELOC_MIPS_TLS_DTPREL32));
13805
13806 demand_empty_rest_of_line ();
13807}
13808
13809/* Handle .dtprelword. */
13810
13811static void
13812s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13813{
13814 s_dtprel_internal (4);
13815}
13816
13817/* Handle .dtpreldword. */
13818
13819static void
13820s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13821{
13822 s_dtprel_internal (8);
13823}
13824
13825/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13826 code. It sets the offset to use in gp_rel relocations. */
13827
13828static void
13829s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13830{
13831 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13832 We also need NewABI support. */
13833 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13834 {
13835 s_ignore (0);
13836 return;
13837 }
13838
13839 mips_gprel_offset = get_absolute_expression ();
13840
13841 demand_empty_rest_of_line ();
13842}
13843
13844/* Handle the .gpword pseudo-op. This is used when generating PIC
13845 code. It generates a 32 bit GP relative reloc. */
13846
13847static void
13848s_gpword (int ignore ATTRIBUTE_UNUSED)
13849{
13850 segment_info_type *si;
13851 struct insn_label_list *l;
13852 symbolS *label;
13853 expressionS ex;
13854 char *p;
13855
13856 /* When not generating PIC code, this is treated as .word. */
13857 if (mips_pic != SVR4_PIC)
13858 {
13859 s_cons (2);
13860 return;
13861 }
13862
13863 si = seg_info (now_seg);
13864 l = si->label_list;
13865 label = l != NULL ? l->label : NULL;
13866 mips_emit_delays ();
13867 if (auto_align)
13868 mips_align (2, 0, label);
13869
13870 expression (&ex);
13871 mips_clear_insn_labels ();
13872
13873 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13874 {
13875 as_bad (_("Unsupported use of .gpword"));
13876 ignore_rest_of_line ();
13877 }
13878
13879 p = frag_more (4);
13880 md_number_to_chars (p, 0, 4);
13881 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13882 BFD_RELOC_GPREL32);
13883
13884 demand_empty_rest_of_line ();
13885}
13886
13887static void
13888s_gpdword (int ignore ATTRIBUTE_UNUSED)
13889{
13890 segment_info_type *si;
13891 struct insn_label_list *l;
13892 symbolS *label;
13893 expressionS ex;
13894 char *p;
13895
13896 /* When not generating PIC code, this is treated as .dword. */
13897 if (mips_pic != SVR4_PIC)
13898 {
13899 s_cons (3);
13900 return;
13901 }
13902
13903 si = seg_info (now_seg);
13904 l = si->label_list;
13905 label = l != NULL ? l->label : NULL;
13906 mips_emit_delays ();
13907 if (auto_align)
13908 mips_align (3, 0, label);
13909
13910 expression (&ex);
13911 mips_clear_insn_labels ();
13912
13913 if (ex.X_op != O_symbol || ex.X_add_number != 0)
13914 {
13915 as_bad (_("Unsupported use of .gpdword"));
13916 ignore_rest_of_line ();
13917 }
13918
13919 p = frag_more (8);
13920 md_number_to_chars (p, 0, 8);
13921 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
13922 BFD_RELOC_GPREL32)->fx_tcbit = 1;
13923
13924 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13925 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
13926 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
13927
13928 demand_empty_rest_of_line ();
13929}
13930
13931/* Handle the .cpadd pseudo-op. This is used when dealing with switch
13932 tables in SVR4 PIC code. */
13933
13934static void
13935s_cpadd (int ignore ATTRIBUTE_UNUSED)
13936{
13937 int reg;
13938
13939 /* This is ignored when not generating SVR4 PIC code. */
13940 if (mips_pic != SVR4_PIC)
13941 {
13942 s_ignore (0);
13943 return;
13944 }
13945
13946 /* Add $gp to the register named as an argument. */
13947 macro_start ();
13948 reg = tc_get_register (0);
13949 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
13950 macro_end ();
13951
13952 demand_empty_rest_of_line ();
13953}
13954
13955/* Handle the .insn pseudo-op. This marks instruction labels in
13956 mips16 mode. This permits the linker to handle them specially,
13957 such as generating jalx instructions when needed. We also make
13958 them odd for the duration of the assembly, in order to generate the
13959 right sort of code. We will make them even in the adjust_symtab
13960 routine, while leaving them marked. This is convenient for the
13961 debugger and the disassembler. The linker knows to make them odd
13962 again. */
13963
13964static void
13965s_insn (int ignore ATTRIBUTE_UNUSED)
13966{
13967 mips16_mark_labels ();
13968
13969 demand_empty_rest_of_line ();
13970}
13971
13972/* Handle a .stabn directive. We need these in order to mark a label
13973 as being a mips16 text label correctly. Sometimes the compiler
13974 will emit a label, followed by a .stabn, and then switch sections.
13975 If the label and .stabn are in mips16 mode, then the label is
13976 really a mips16 text label. */
13977
13978static void
13979s_mips_stab (int type)
13980{
13981 if (type == 'n')
13982 mips16_mark_labels ();
13983
13984 s_stab (type);
13985}
13986
13987/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13988
13989static void
13990s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13991{
13992 char *name;
13993 int c;
13994 symbolS *symbolP;
13995 expressionS exp;
13996
13997 name = input_line_pointer;
13998 c = get_symbol_end ();
13999 symbolP = symbol_find_or_make (name);
14000 S_SET_WEAK (symbolP);
14001 *input_line_pointer = c;
14002
14003 SKIP_WHITESPACE ();
14004
14005 if (! is_end_of_line[(unsigned char) *input_line_pointer])
14006 {
14007 if (S_IS_DEFINED (symbolP))
14008 {
14009 as_bad (_("ignoring attempt to redefine symbol %s"),
14010 S_GET_NAME (symbolP));
14011 ignore_rest_of_line ();
14012 return;
14013 }
14014
14015 if (*input_line_pointer == ',')
14016 {
14017 ++input_line_pointer;
14018 SKIP_WHITESPACE ();
14019 }
14020
14021 expression (&exp);
14022 if (exp.X_op != O_symbol)
14023 {
14024 as_bad (_("bad .weakext directive"));
14025 ignore_rest_of_line ();
14026 return;
14027 }
14028 symbol_set_value_expression (symbolP, &exp);
14029 }
14030
14031 demand_empty_rest_of_line ();
14032}
14033
14034/* Parse a register string into a number. Called from the ECOFF code
14035 to parse .frame. The argument is non-zero if this is the frame
14036 register, so that we can record it in mips_frame_reg. */
14037
14038int
14039tc_get_register (int frame)
14040{
14041 unsigned int reg;
14042
14043 SKIP_WHITESPACE ();
14044 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
14045 reg = 0;
14046 if (frame)
14047 {
14048 mips_frame_reg = reg != 0 ? reg : SP;
14049 mips_frame_reg_valid = 1;
14050 mips_cprestore_valid = 0;
14051 }
14052 return reg;
14053}
14054
14055valueT
14056md_section_align (asection *seg, valueT addr)
14057{
14058 int align = bfd_get_section_alignment (stdoutput, seg);
14059
14060 if (IS_ELF)
14061 {
14062 /* We don't need to align ELF sections to the full alignment.
14063 However, Irix 5 may prefer that we align them at least to a 16
14064 byte boundary. We don't bother to align the sections if we
14065 are targeted for an embedded system. */
14066 if (strncmp (TARGET_OS, "elf", 3) == 0)
14067 return addr;
14068 if (align > 4)
14069 align = 4;
14070 }
14071
14072 return ((addr + (1 << align) - 1) & (-1 << align));
14073}
14074
14075/* Utility routine, called from above as well. If called while the
14076 input file is still being read, it's only an approximation. (For
14077 example, a symbol may later become defined which appeared to be
14078 undefined earlier.) */
14079
14080static int
14081nopic_need_relax (symbolS *sym, int before_relaxing)
14082{
14083 if (sym == 0)
14084 return 0;
14085
14086 if (g_switch_value > 0)
14087 {
14088 const char *symname;
14089 int change;
14090
14091 /* Find out whether this symbol can be referenced off the $gp
14092 register. It can be if it is smaller than the -G size or if
14093 it is in the .sdata or .sbss section. Certain symbols can
14094 not be referenced off the $gp, although it appears as though
14095 they can. */
14096 symname = S_GET_NAME (sym);
14097 if (symname != (const char *) NULL
14098 && (strcmp (symname, "eprol") == 0
14099 || strcmp (symname, "etext") == 0
14100 || strcmp (symname, "_gp") == 0
14101 || strcmp (symname, "edata") == 0
14102 || strcmp (symname, "_fbss") == 0
14103 || strcmp (symname, "_fdata") == 0
14104 || strcmp (symname, "_ftext") == 0
14105 || strcmp (symname, "end") == 0
14106 || strcmp (symname, "_gp_disp") == 0))
14107 change = 1;
14108 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
14109 && (0
14110#ifndef NO_ECOFF_DEBUGGING
14111 || (symbol_get_obj (sym)->ecoff_extern_size != 0
14112 && (symbol_get_obj (sym)->ecoff_extern_size
14113 <= g_switch_value))
14114#endif
14115 /* We must defer this decision until after the whole
14116 file has been read, since there might be a .extern
14117 after the first use of this symbol. */
14118 || (before_relaxing
14119#ifndef NO_ECOFF_DEBUGGING
14120 && symbol_get_obj (sym)->ecoff_extern_size == 0
14121#endif
14122 && S_GET_VALUE (sym) == 0)
14123 || (S_GET_VALUE (sym) != 0
14124 && S_GET_VALUE (sym) <= g_switch_value)))
14125 change = 0;
14126 else
14127 {
14128 const char *segname;
14129
14130 segname = segment_name (S_GET_SEGMENT (sym));
14131 gas_assert (strcmp (segname, ".lit8") != 0
14132 && strcmp (segname, ".lit4") != 0);
14133 change = (strcmp (segname, ".sdata") != 0
14134 && strcmp (segname, ".sbss") != 0
14135 && strncmp (segname, ".sdata.", 7) != 0
14136 && strncmp (segname, ".sbss.", 6) != 0
14137 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
14138 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
14139 }
14140 return change;
14141 }
14142 else
14143 /* We are not optimizing for the $gp register. */
14144 return 1;
14145}
14146
14147
14148/* Return true if the given symbol should be considered local for SVR4 PIC. */
14149
14150static bfd_boolean
14151pic_need_relax (symbolS *sym, asection *segtype)
14152{
14153 asection *symsec;
14154
14155 /* Handle the case of a symbol equated to another symbol. */
14156 while (symbol_equated_reloc_p (sym))
14157 {
14158 symbolS *n;
14159
14160 /* It's possible to get a loop here in a badly written program. */
14161 n = symbol_get_value_expression (sym)->X_add_symbol;
14162 if (n == sym)
14163 break;
14164 sym = n;
14165 }
14166
14167 if (symbol_section_p (sym))
14168 return TRUE;
14169
14170 symsec = S_GET_SEGMENT (sym);
14171
14172 /* This must duplicate the test in adjust_reloc_syms. */
14173 return (symsec != &bfd_und_section
14174 && symsec != &bfd_abs_section
14175 && !bfd_is_com_section (symsec)
14176 && !s_is_linkonce (sym, segtype)
14177#ifdef OBJ_ELF
14178 /* A global or weak symbol is treated as external. */
14179 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
14180#endif
14181 );
14182}
14183
14184
14185/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
14186 extended opcode. SEC is the section the frag is in. */
14187
14188static int
14189mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
14190{
14191 int type;
14192 const struct mips16_immed_operand *op;
14193 offsetT val;
14194 int mintiny, maxtiny;
14195 segT symsec;
14196 fragS *sym_frag;
14197
14198 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
14199 return 0;
14200 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
14201 return 1;
14202
14203 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14204 op = mips16_immed_operands;
14205 while (op->type != type)
14206 {
14207 ++op;
14208 gas_assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
14209 }
14210
14211 if (op->unsp)
14212 {
14213 if (type == '<' || type == '>' || type == '[' || type == ']')
14214 {
14215 mintiny = 1;
14216 maxtiny = 1 << op->nbits;
14217 }
14218 else
14219 {
14220 mintiny = 0;
14221 maxtiny = (1 << op->nbits) - 1;
14222 }
14223 }
14224 else
14225 {
14226 mintiny = - (1 << (op->nbits - 1));
14227 maxtiny = (1 << (op->nbits - 1)) - 1;
14228 }
14229
14230 sym_frag = symbol_get_frag (fragp->fr_symbol);
14231 val = S_GET_VALUE (fragp->fr_symbol);
14232 symsec = S_GET_SEGMENT (fragp->fr_symbol);
14233
14234 if (op->pcrel)
14235 {
14236 addressT addr;
14237
14238 /* We won't have the section when we are called from
14239 mips_relax_frag. However, we will always have been called
14240 from md_estimate_size_before_relax first. If this is a
14241 branch to a different section, we mark it as such. If SEC is
14242 NULL, and the frag is not marked, then it must be a branch to
14243 the same section. */
14244 if (sec == NULL)
14245 {
14246 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
14247 return 1;
14248 }
14249 else
14250 {
14251 /* Must have been called from md_estimate_size_before_relax. */
14252 if (symsec != sec)
14253 {
14254 fragp->fr_subtype =
14255 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14256
14257 /* FIXME: We should support this, and let the linker
14258 catch branches and loads that are out of range. */
14259 as_bad_where (fragp->fr_file, fragp->fr_line,
14260 _("unsupported PC relative reference to different section"));
14261
14262 return 1;
14263 }
14264 if (fragp != sym_frag && sym_frag->fr_address == 0)
14265 /* Assume non-extended on the first relaxation pass.
14266 The address we have calculated will be bogus if this is
14267 a forward branch to another frag, as the forward frag
14268 will have fr_address == 0. */
14269 return 0;
14270 }
14271
14272 /* In this case, we know for sure that the symbol fragment is in
14273 the same section. If the relax_marker of the symbol fragment
14274 differs from the relax_marker of this fragment, we have not
14275 yet adjusted the symbol fragment fr_address. We want to add
14276 in STRETCH in order to get a better estimate of the address.
14277 This particularly matters because of the shift bits. */
14278 if (stretch != 0
14279 && sym_frag->relax_marker != fragp->relax_marker)
14280 {
14281 fragS *f;
14282
14283 /* Adjust stretch for any alignment frag. Note that if have
14284 been expanding the earlier code, the symbol may be
14285 defined in what appears to be an earlier frag. FIXME:
14286 This doesn't handle the fr_subtype field, which specifies
14287 a maximum number of bytes to skip when doing an
14288 alignment. */
14289 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
14290 {
14291 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
14292 {
14293 if (stretch < 0)
14294 stretch = - ((- stretch)
14295 & ~ ((1 << (int) f->fr_offset) - 1));
14296 else
14297 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
14298 if (stretch == 0)
14299 break;
14300 }
14301 }
14302 if (f != NULL)
14303 val += stretch;
14304 }
14305
14306 addr = fragp->fr_address + fragp->fr_fix;
14307
14308 /* The base address rules are complicated. The base address of
14309 a branch is the following instruction. The base address of a
14310 PC relative load or add is the instruction itself, but if it
14311 is in a delay slot (in which case it can not be extended) use
14312 the address of the instruction whose delay slot it is in. */
14313 if (type == 'p' || type == 'q')
14314 {
14315 addr += 2;
14316
14317 /* If we are currently assuming that this frag should be
14318 extended, then, the current address is two bytes
14319 higher. */
14320 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14321 addr += 2;
14322
14323 /* Ignore the low bit in the target, since it will be set
14324 for a text label. */
14325 if ((val & 1) != 0)
14326 --val;
14327 }
14328 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14329 addr -= 4;
14330 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14331 addr -= 2;
14332
14333 val -= addr & ~ ((1 << op->shift) - 1);
14334
14335 /* Branch offsets have an implicit 0 in the lowest bit. */
14336 if (type == 'p' || type == 'q')
14337 val /= 2;
14338
14339 /* If any of the shifted bits are set, we must use an extended
14340 opcode. If the address depends on the size of this
14341 instruction, this can lead to a loop, so we arrange to always
14342 use an extended opcode. We only check this when we are in
14343 the main relaxation loop, when SEC is NULL. */
14344 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
14345 {
14346 fragp->fr_subtype =
14347 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14348 return 1;
14349 }
14350
14351 /* If we are about to mark a frag as extended because the value
14352 is precisely maxtiny + 1, then there is a chance of an
14353 infinite loop as in the following code:
14354 la $4,foo
14355 .skip 1020
14356 .align 2
14357 foo:
14358 In this case when the la is extended, foo is 0x3fc bytes
14359 away, so the la can be shrunk, but then foo is 0x400 away, so
14360 the la must be extended. To avoid this loop, we mark the
14361 frag as extended if it was small, and is about to become
14362 extended with a value of maxtiny + 1. */
14363 if (val == ((maxtiny + 1) << op->shift)
14364 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
14365 && sec == NULL)
14366 {
14367 fragp->fr_subtype =
14368 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
14369 return 1;
14370 }
14371 }
14372 else if (symsec != absolute_section && sec != NULL)
14373 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
14374
14375 if ((val & ((1 << op->shift) - 1)) != 0
14376 || val < (mintiny << op->shift)
14377 || val > (maxtiny << op->shift))
14378 return 1;
14379 else
14380 return 0;
14381}
14382
14383/* Compute the length of a branch sequence, and adjust the
14384 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
14385 worst-case length is computed, with UPDATE being used to indicate
14386 whether an unconditional (-1), branch-likely (+1) or regular (0)
14387 branch is to be computed. */
14388static int
14389relaxed_branch_length (fragS *fragp, asection *sec, int update)
14390{
14391 bfd_boolean toofar;
14392 int length;
14393
14394 if (fragp
14395 && S_IS_DEFINED (fragp->fr_symbol)
14396 && sec == S_GET_SEGMENT (fragp->fr_symbol))
14397 {
14398 addressT addr;
14399 offsetT val;
14400
14401 val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
14402
14403 addr = fragp->fr_address + fragp->fr_fix + 4;
14404
14405 val -= addr;
14406
14407 toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
14408 }
14409 else if (fragp)
14410 /* If the symbol is not defined or it's in a different segment,
14411 assume the user knows what's going on and emit a short
14412 branch. */
14413 toofar = FALSE;
14414 else
14415 toofar = TRUE;
14416
14417 if (fragp && update && toofar != RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14418 fragp->fr_subtype
14419 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp->fr_subtype),
14420 RELAX_BRANCH_UNCOND (fragp->fr_subtype),
14421 RELAX_BRANCH_LIKELY (fragp->fr_subtype),
14422 RELAX_BRANCH_LINK (fragp->fr_subtype),
14423 toofar);
14424
14425 length = 4;
14426 if (toofar)
14427 {
14428 if (fragp ? RELAX_BRANCH_LIKELY (fragp->fr_subtype) : (update > 0))
14429 length += 8;
14430
14431 if (mips_pic != NO_PIC)
14432 {
14433 /* Additional space for PIC loading of target address. */
14434 length += 8;
14435 if (mips_opts.isa == ISA_MIPS1)
14436 /* Additional space for $at-stabilizing nop. */
14437 length += 4;
14438 }
14439
14440 /* If branch is conditional. */
14441 if (fragp ? !RELAX_BRANCH_UNCOND (fragp->fr_subtype) : (update >= 0))
14442 length += 8;
14443 }
14444
14445 return length;
14446}
14447
14448/* Estimate the size of a frag before relaxing. Unless this is the
14449 mips16, we are not really relaxing here, and the final size is
14450 encoded in the subtype information. For the mips16, we have to
14451 decide whether we are using an extended opcode or not. */
14452
14453int
14454md_estimate_size_before_relax (fragS *fragp, asection *segtype)
14455{
14456 int change;
14457
14458 if (RELAX_BRANCH_P (fragp->fr_subtype))
14459 {
14460
14461 fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE);
14462
14463 return fragp->fr_var;
14464 }
14465
14466 if (RELAX_MIPS16_P (fragp->fr_subtype))
14467 /* We don't want to modify the EXTENDED bit here; it might get us
14468 into infinite loops. We change it only in mips_relax_frag(). */
14469 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
14470
14471 if (mips_pic == NO_PIC)
14472 change = nopic_need_relax (fragp->fr_symbol, 0);
14473 else if (mips_pic == SVR4_PIC)
14474 change = pic_need_relax (fragp->fr_symbol, segtype);
14475 else if (mips_pic == VXWORKS_PIC)
14476 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
14477 change = 0;
14478 else
14479 abort ();
14480
14481 if (change)
14482 {
14483 fragp->fr_subtype |= RELAX_USE_SECOND;
14484 return -RELAX_FIRST (fragp->fr_subtype);
14485 }
14486 else
14487 return -RELAX_SECOND (fragp->fr_subtype);
14488}
14489
14490/* This is called to see whether a reloc against a defined symbol
14491 should be converted into a reloc against a section. */
14492
14493int
14494mips_fix_adjustable (fixS *fixp)
14495{
14496 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
14497 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14498 return 0;
14499
14500 if (fixp->fx_addsy == NULL)
14501 return 1;
14502
14503 /* If symbol SYM is in a mergeable section, relocations of the form
14504 SYM + 0 can usually be made section-relative. The mergeable data
14505 is then identified by the section offset rather than by the symbol.
14506
14507 However, if we're generating REL LO16 relocations, the offset is split
14508 between the LO16 and parterning high part relocation. The linker will
14509 need to recalculate the complete offset in order to correctly identify
14510 the merge data.
14511
14512 The linker has traditionally not looked for the parterning high part
14513 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14514 placed anywhere. Rather than break backwards compatibility by changing
14515 this, it seems better not to force the issue, and instead keep the
14516 original symbol. This will work with either linker behavior. */
14517 if ((lo16_reloc_p (fixp->fx_r_type)
14518 || reloc_needs_lo_p (fixp->fx_r_type))
14519 && HAVE_IN_PLACE_ADDENDS
14520 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14521 return 0;
14522
14523 /* There is no place to store an in-place offset for JALR relocations.
14524 Likewise an in-range offset of PC-relative relocations may overflow
14525 the in-place relocatable field if recalculated against the start
14526 address of the symbol's containing section. */
14527 if (HAVE_IN_PLACE_ADDENDS
14528 && (fixp->fx_pcrel || fixp->fx_r_type == BFD_RELOC_MIPS_JALR))
14529 return 0;
14530
14531#ifdef OBJ_ELF
14532 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14533 to a floating-point stub. The same is true for non-R_MIPS16_26
14534 relocations against MIPS16 functions; in this case, the stub becomes
14535 the function's canonical address.
14536
14537 Floating-point stubs are stored in unique .mips16.call.* or
14538 .mips16.fn.* sections. If a stub T for function F is in section S,
14539 the first relocation in section S must be against F; this is how the
14540 linker determines the target function. All relocations that might
14541 resolve to T must also be against F. We therefore have the following
14542 restrictions, which are given in an intentionally-redundant way:
14543
14544 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14545 symbols.
14546
14547 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14548 if that stub might be used.
14549
14550 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14551 symbols.
14552
14553 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14554 that stub might be used.
14555
14556 There is a further restriction:
14557
14558 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14559 on targets with in-place addends; the relocation field cannot
14560 encode the low bit.
14561
14562 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14563 against a MIPS16 symbol.
14564
14565 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14566 relocation against some symbol R, no relocation against R may be
14567 reduced. (Note that this deals with (2) as well as (1) because
14568 relocations against global symbols will never be reduced on ELF
14569 targets.) This approach is a little simpler than trying to detect
14570 stub sections, and gives the "all or nothing" per-symbol consistency
14571 that we have for MIPS16 symbols. */
14572 if (IS_ELF
14573 && fixp->fx_subsy == NULL
14574 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp->fx_addsy))
14575 || *symbol_get_tc (fixp->fx_addsy)))
14576 return 0;
14577#endif
14578
14579 return 1;
14580}
14581
14582/* Translate internal representation of relocation info to BFD target
14583 format. */
14584
14585arelent **
14586tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
14587{
14588 static arelent *retval[4];
14589 arelent *reloc;
14590 bfd_reloc_code_real_type code;
14591
14592 memset (retval, 0, sizeof(retval));
14593 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
14594 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
14595 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
14596 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
14597
14598 if (fixp->fx_pcrel)
14599 {
14600 gas_assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14601
14602 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14603 Relocations want only the symbol offset. */
14604 reloc->addend = fixp->fx_addnumber + reloc->address;
14605 if (!IS_ELF)
14606 {
14607 /* A gruesome hack which is a result of the gruesome gas
14608 reloc handling. What's worse, for COFF (as opposed to
14609 ECOFF), we might need yet another copy of reloc->address.
14610 See bfd_install_relocation. */
14611 reloc->addend += reloc->address;
14612 }
14613 }
14614 else
14615 reloc->addend = fixp->fx_addnumber;
14616
14617 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14618 entry to be used in the relocation's section offset. */
14619 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
14620 {
14621 reloc->address = reloc->addend;
14622 reloc->addend = 0;
14623 }
14624
14625 code = fixp->fx_r_type;
14626
14627 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
14628 if (reloc->howto == NULL)
14629 {
14630 as_bad_where (fixp->fx_file, fixp->fx_line,
14631 _("Can not represent %s relocation in this object file format"),
14632 bfd_get_reloc_code_name (code));
14633 retval[0] = NULL;
14634 }
14635
14636 return retval;
14637}
14638
14639/* Relax a machine dependent frag. This returns the amount by which
14640 the current size of the frag should change. */
14641
14642int
14643mips_relax_frag (asection *sec, fragS *fragp, long stretch)
14644{
14645 if (RELAX_BRANCH_P (fragp->fr_subtype))
14646 {
14647 offsetT old_var = fragp->fr_var;
14648
14649 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE);
14650
14651 return fragp->fr_var - old_var;
14652 }
14653
14654 if (! RELAX_MIPS16_P (fragp->fr_subtype))
14655 return 0;
14656
14657 if (mips16_extended_frag (fragp, NULL, stretch))
14658 {
14659 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14660 return 0;
14661 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
14662 return 2;
14663 }
14664 else
14665 {
14666 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14667 return 0;
14668 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
14669 return -2;
14670 }
14671
14672 return 0;
14673}
14674
14675/* Convert a machine dependent frag. */
14676
14677void
14678md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
14679{
14680 if (RELAX_BRANCH_P (fragp->fr_subtype))
14681 {
14682 bfd_byte *buf;
14683 unsigned long insn;
14684 expressionS exp;
14685 fixS *fixp;
14686
14687 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
14688
14689 if (target_big_endian)
14690 insn = bfd_getb32 (buf);
14691 else
14692 insn = bfd_getl32 (buf);
14693
14694 if (!RELAX_BRANCH_TOOFAR (fragp->fr_subtype))
14695 {
14696 /* We generate a fixup instead of applying it right now
14697 because, if there are linker relaxations, we're going to
14698 need the relocations. */
14699 exp.X_op = O_symbol;
14700 exp.X_add_symbol = fragp->fr_symbol;
14701 exp.X_add_number = fragp->fr_offset;
14702
14703 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14704 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
14705 fixp->fx_file = fragp->fr_file;
14706 fixp->fx_line = fragp->fr_line;
14707
14708 md_number_to_chars ((char *) buf, insn, 4);
14709 buf += 4;
14710 }
14711 else
14712 {
14713 int i;
14714
14715 as_warn_where (fragp->fr_file, fragp->fr_line,
14716 _("Relaxed out-of-range branch into a jump"));
14717
14718 if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
14719 goto uncond;
14720
14721 if (!RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14722 {
14723 /* Reverse the branch. */
14724 switch ((insn >> 28) & 0xf)
14725 {
14726 case 4:
14727 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14728 have the condition reversed by tweaking a single
14729 bit, and their opcodes all have 0x4???????. */
14730 gas_assert ((insn & 0xf1000000) == 0x41000000);
14731 insn ^= 0x00010000;
14732 break;
14733
14734 case 0:
14735 /* bltz 0x04000000 bgez 0x04010000
14736 bltzal 0x04100000 bgezal 0x04110000 */
14737 gas_assert ((insn & 0xfc0e0000) == 0x04000000);
14738 insn ^= 0x00010000;
14739 break;
14740
14741 case 1:
14742 /* beq 0x10000000 bne 0x14000000
14743 blez 0x18000000 bgtz 0x1c000000 */
14744 insn ^= 0x04000000;
14745 break;
14746
14747 default:
14748 abort ();
14749 }
14750 }
14751
14752 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14753 {
14754 /* Clear the and-link bit. */
14755 gas_assert ((insn & 0xfc1c0000) == 0x04100000);
14756
14757 /* bltzal 0x04100000 bgezal 0x04110000
14758 bltzall 0x04120000 bgezall 0x04130000 */
14759 insn &= ~0x00100000;
14760 }
14761
14762 /* Branch over the branch (if the branch was likely) or the
14763 full jump (not likely case). Compute the offset from the
14764 current instruction to branch to. */
14765 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14766 i = 16;
14767 else
14768 {
14769 /* How many bytes in instructions we've already emitted? */
14770 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14771 /* How many bytes in instructions from here to the end? */
14772 i = fragp->fr_var - i;
14773 }
14774 /* Convert to instruction count. */
14775 i >>= 2;
14776 /* Branch counts from the next instruction. */
14777 i--;
14778 insn |= i;
14779 /* Branch over the jump. */
14780 md_number_to_chars ((char *) buf, insn, 4);
14781 buf += 4;
14782
14783 /* nop */
14784 md_number_to_chars ((char *) buf, 0, 4);
14785 buf += 4;
14786
14787 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14788 {
14789 /* beql $0, $0, 2f */
14790 insn = 0x50000000;
14791 /* Compute the PC offset from the current instruction to
14792 the end of the variable frag. */
14793 /* How many bytes in instructions we've already emitted? */
14794 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
14795 /* How many bytes in instructions from here to the end? */
14796 i = fragp->fr_var - i;
14797 /* Convert to instruction count. */
14798 i >>= 2;
14799 /* Don't decrement i, because we want to branch over the
14800 delay slot. */
14801
14802 insn |= i;
14803 md_number_to_chars ((char *) buf, insn, 4);
14804 buf += 4;
14805
14806 md_number_to_chars ((char *) buf, 0, 4);
14807 buf += 4;
14808 }
14809
14810 uncond:
14811 if (mips_pic == NO_PIC)
14812 {
14813 /* j or jal. */
14814 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14815 ? 0x0c000000 : 0x08000000);
14816 exp.X_op = O_symbol;
14817 exp.X_add_symbol = fragp->fr_symbol;
14818 exp.X_add_number = fragp->fr_offset;
14819
14820 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14821 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
14822 fixp->fx_file = fragp->fr_file;
14823 fixp->fx_line = fragp->fr_line;
14824
14825 md_number_to_chars ((char *) buf, insn, 4);
14826 buf += 4;
14827 }
14828 else
14829 {
14830 unsigned long at = RELAX_BRANCH_AT (fragp->fr_subtype);
14831
14832 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14833 insn = HAVE_64BIT_ADDRESSES ? 0xdf800000 : 0x8f800000;
14834 insn |= at << OP_SH_RT;
14835 exp.X_op = O_symbol;
14836 exp.X_add_symbol = fragp->fr_symbol;
14837 exp.X_add_number = fragp->fr_offset;
14838
14839 if (fragp->fr_offset)
14840 {
14841 exp.X_add_symbol = make_expr_symbol (&exp);
14842 exp.X_add_number = 0;
14843 }
14844
14845 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14846 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
14847 fixp->fx_file = fragp->fr_file;
14848 fixp->fx_line = fragp->fr_line;
14849
14850 md_number_to_chars ((char *) buf, insn, 4);
14851 buf += 4;
14852
14853 if (mips_opts.isa == ISA_MIPS1)
14854 {
14855 /* nop */
14856 md_number_to_chars ((char *) buf, 0, 4);
14857 buf += 4;
14858 }
14859
14860 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14861 insn = HAVE_64BIT_ADDRESSES ? 0x64000000 : 0x24000000;
14862 insn |= at << OP_SH_RS | at << OP_SH_RT;
14863
14864 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14865 4, &exp, FALSE, BFD_RELOC_LO16);
14866 fixp->fx_file = fragp->fr_file;
14867 fixp->fx_line = fragp->fr_line;
14868
14869 md_number_to_chars ((char *) buf, insn, 4);
14870 buf += 4;
14871
14872 /* j(al)r $at. */
14873 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14874 insn = 0x0000f809;
14875 else
14876 insn = 0x00000008;
14877 insn |= at << OP_SH_RS;
14878
14879 md_number_to_chars ((char *) buf, insn, 4);
14880 buf += 4;
14881 }
14882 }
14883
14884 gas_assert (buf == (bfd_byte *)fragp->fr_literal
14885 + fragp->fr_fix + fragp->fr_var);
14886
14887 fragp->fr_fix += fragp->fr_var;
14888
14889 return;
14890 }
14891
14892 if (RELAX_MIPS16_P (fragp->fr_subtype))
14893 {
14894 int type;
14895 const struct mips16_immed_operand *op;
14896 bfd_boolean small, ext;
14897 offsetT val;
14898 bfd_byte *buf;
14899 unsigned long insn;
14900 bfd_boolean use_extend;
14901 unsigned short extend;
14902
14903 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
14904 op = mips16_immed_operands;
14905 while (op->type != type)
14906 ++op;
14907
14908 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
14909 {
14910 small = FALSE;
14911 ext = TRUE;
14912 }
14913 else
14914 {
14915 small = TRUE;
14916 ext = FALSE;
14917 }
14918
14919 val = resolve_symbol_value (fragp->fr_symbol);
14920 if (op->pcrel)
14921 {
14922 addressT addr;
14923
14924 addr = fragp->fr_address + fragp->fr_fix;
14925
14926 /* The rules for the base address of a PC relative reloc are
14927 complicated; see mips16_extended_frag. */
14928 if (type == 'p' || type == 'q')
14929 {
14930 addr += 2;
14931 if (ext)
14932 addr += 2;
14933 /* Ignore the low bit in the target, since it will be
14934 set for a text label. */
14935 if ((val & 1) != 0)
14936 --val;
14937 }
14938 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
14939 addr -= 4;
14940 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
14941 addr -= 2;
14942
14943 addr &= ~ (addressT) ((1 << op->shift) - 1);
14944 val -= addr;
14945
14946 /* Make sure the section winds up with the alignment we have
14947 assumed. */
14948 if (op->shift > 0)
14949 record_alignment (asec, op->shift);
14950 }
14951
14952 if (ext
14953 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
14954 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
14955 as_warn_where (fragp->fr_file, fragp->fr_line,
14956 _("extended instruction in delay slot"));
14957
14958 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
14959
14960 if (target_big_endian)
14961 insn = bfd_getb16 (buf);
14962 else
14963 insn = bfd_getl16 (buf);
14964
14965 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
14966 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
14967 small, ext, &insn, &use_extend, &extend);
14968
14969 if (use_extend)
14970 {
14971 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
14972 fragp->fr_fix += 2;
14973 buf += 2;
14974 }
14975
14976 md_number_to_chars ((char *) buf, insn, 2);
14977 fragp->fr_fix += 2;
14978 buf += 2;
14979 }
14980 else
14981 {
14982 int first, second;
14983 fixS *fixp;
14984
14985 first = RELAX_FIRST (fragp->fr_subtype);
14986 second = RELAX_SECOND (fragp->fr_subtype);
14987 fixp = (fixS *) fragp->fr_opcode;
14988
14989 /* Possibly emit a warning if we've chosen the longer option. */
14990 if (((fragp->fr_subtype & RELAX_USE_SECOND) != 0)
14991 == ((fragp->fr_subtype & RELAX_SECOND_LONGER) != 0))
14992 {
14993 const char *msg = macro_warning (fragp->fr_subtype);
14994 if (msg != 0)
14995 as_warn_where (fragp->fr_file, fragp->fr_line, "%s", msg);
14996 }
14997
14998 /* Go through all the fixups for the first sequence. Disable them
14999 (by marking them as done) if we're going to use the second
15000 sequence instead. */
15001 while (fixp
15002 && fixp->fx_frag == fragp
15003 && fixp->fx_where < fragp->fr_fix - second)
15004 {
15005 if (fragp->fr_subtype & RELAX_USE_SECOND)
15006 fixp->fx_done = 1;
15007 fixp = fixp->fx_next;
15008 }
15009
15010 /* Go through the fixups for the second sequence. Disable them if
15011 we're going to use the first sequence, otherwise adjust their
15012 addresses to account for the relaxation. */
15013 while (fixp && fixp->fx_frag == fragp)
15014 {
15015 if (fragp->fr_subtype & RELAX_USE_SECOND)
15016 fixp->fx_where -= first;
15017 else
15018 fixp->fx_done = 1;
15019 fixp = fixp->fx_next;
15020 }
15021
15022 /* Now modify the frag contents. */
15023 if (fragp->fr_subtype & RELAX_USE_SECOND)
15024 {
15025 char *start;
15026
15027 start = fragp->fr_literal + fragp->fr_fix - first - second;
15028 memmove (start, start + first, second);
15029 fragp->fr_fix -= first;
15030 }
15031 else
15032 fragp->fr_fix -= second;
15033 }
15034}
15035
15036#ifdef OBJ_ELF
15037
15038/* This function is called after the relocs have been generated.
15039 We've been storing mips16 text labels as odd. Here we convert them
15040 back to even for the convenience of the debugger. */
15041
15042void
15043mips_frob_file_after_relocs (void)
15044{
15045 asymbol **syms;
15046 unsigned int count, i;
15047
15048 if (!IS_ELF)
15049 return;
15050
15051 syms = bfd_get_outsymbols (stdoutput);
15052 count = bfd_get_symcount (stdoutput);
15053 for (i = 0; i < count; i++, syms++)
15054 {
15055 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms)->internal_elf_sym.st_other)
15056 && ((*syms)->value & 1) != 0)
15057 {
15058 (*syms)->value &= ~1;
15059 /* If the symbol has an odd size, it was probably computed
15060 incorrectly, so adjust that as well. */
15061 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
15062 ++elf_symbol (*syms)->internal_elf_sym.st_size;
15063 }
15064 }
15065}
15066
15067#endif
15068
15069/* This function is called whenever a label is defined, including fake
15070 labels instantiated off the dot special symbol. It is used when
15071 handling branch delays; if a branch has a label, we assume we cannot
15072 move it. This also bumps the value of the symbol by 1 in compressed
15073 code. */
15074
15075void
15076mips_record_label (symbolS *sym)
15077{
15078 segment_info_type *si = seg_info (now_seg);
15079 struct insn_label_list *l;
15080
15081 if (free_insn_labels == NULL)
15082 l = (struct insn_label_list *) xmalloc (sizeof *l);
15083 else
15084 {
15085 l = free_insn_labels;
15086 free_insn_labels = l->next;
15087 }
15088
15089 l->label = sym;
15090 l->next = si->label_list;
15091 si->label_list = l;
15092}
15093
15094/* This function is called as tc_frob_label() whenever a label is defined
15095 and adds a DWARF-2 record we only want for true labels. */
15096
15097void
15098mips_define_label (symbolS *sym)
15099{
15100 mips_record_label (sym);
15101#ifdef OBJ_ELF
15102 dwarf2_emit_label (sym);
15103#endif
15104}
15105\f
15106#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15107
15108/* Some special processing for a MIPS ELF file. */
15109
15110void
15111mips_elf_final_processing (void)
15112{
15113 /* Write out the register information. */
15114 if (mips_abi != N64_ABI)
15115 {
15116 Elf32_RegInfo s;
15117
15118 s.ri_gprmask = mips_gprmask;
15119 s.ri_cprmask[0] = mips_cprmask[0];
15120 s.ri_cprmask[1] = mips_cprmask[1];
15121 s.ri_cprmask[2] = mips_cprmask[2];
15122 s.ri_cprmask[3] = mips_cprmask[3];
15123 /* The gp_value field is set by the MIPS ELF backend. */
15124
15125 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
15126 ((Elf32_External_RegInfo *)
15127 mips_regmask_frag));
15128 }
15129 else
15130 {
15131 Elf64_Internal_RegInfo s;
15132
15133 s.ri_gprmask = mips_gprmask;
15134 s.ri_pad = 0;
15135 s.ri_cprmask[0] = mips_cprmask[0];
15136 s.ri_cprmask[1] = mips_cprmask[1];
15137 s.ri_cprmask[2] = mips_cprmask[2];
15138 s.ri_cprmask[3] = mips_cprmask[3];
15139 /* The gp_value field is set by the MIPS ELF backend. */
15140
15141 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
15142 ((Elf64_External_RegInfo *)
15143 mips_regmask_frag));
15144 }
15145
15146 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
15147 sort of BFD interface for this. */
15148 if (mips_any_noreorder)
15149 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
15150 if (mips_pic != NO_PIC)
15151 {
15152 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
15153 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15154 }
15155 if (mips_abicalls)
15156 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
15157
15158 /* Set MIPS ELF flags for ASEs. */
15159 /* We may need to define a new flag for DSP ASE, and set this flag when
15160 file_ase_dsp is true. */
15161 /* Same for DSP R2. */
15162 /* We may need to define a new flag for MT ASE, and set this flag when
15163 file_ase_mt is true. */
15164 if (file_ase_mips16)
15165 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
15166#if 0 /* XXX FIXME */
15167 if (file_ase_mips3d)
15168 elf_elfheader (stdoutput)->e_flags |= ???;
15169#endif
15170 if (file_ase_mdmx)
15171 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
15172
15173 /* Set the MIPS ELF ABI flags. */
15174 if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
15175 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
15176 else if (mips_abi == O64_ABI)
15177 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
15178 else if (mips_abi == EABI_ABI)
15179 {
15180 if (!file_mips_gp32)
15181 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
15182 else
15183 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
15184 }
15185 else if (mips_abi == N32_ABI)
15186 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
15187
15188 /* Nothing to do for N64_ABI. */
15189
15190 if (mips_32bitmode)
15191 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
15192
15193#if 0 /* XXX FIXME */
15194 /* 32 bit code with 64 bit FP registers. */
15195 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
15196 elf_elfheader (stdoutput)->e_flags |= ???;
15197#endif
15198}
15199
15200#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
15201\f
15202typedef struct proc {
15203 symbolS *func_sym;
15204 symbolS *func_end_sym;
15205 unsigned long reg_mask;
15206 unsigned long reg_offset;
15207 unsigned long fpreg_mask;
15208 unsigned long fpreg_offset;
15209 unsigned long frame_offset;
15210 unsigned long frame_reg;
15211 unsigned long pc_reg;
15212} procS;
15213
15214static procS cur_proc;
15215static procS *cur_proc_ptr;
15216static int numprocs;
15217
15218/* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
15219 nop as "0". */
15220
15221char
15222mips_nop_opcode (void)
15223{
15224 return seg_info (now_seg)->tc_segment_info_data.mips16;
15225}
15226
15227/* Fill in an rs_align_code fragment. This only needs to do something
15228 for MIPS16 code, where 0 is not a nop. */
15229
15230void
15231mips_handle_align (fragS *fragp)
15232{
15233 char *p;
15234 int bytes, size, excess;
15235 valueT opcode;
15236
15237 if (fragp->fr_type != rs_align_code)
15238 return;
15239
15240 p = fragp->fr_literal + fragp->fr_fix;
15241 if (*p)
15242 {
15243 opcode = mips16_nop_insn.insn_opcode;
15244 size = 2;
15245 }
15246 else
15247 {
15248 opcode = nop_insn.insn_opcode;
15249 size = 4;
15250 }
15251
15252 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
15253 excess = bytes % size;
15254 if (excess != 0)
15255 {
15256 /* If we're not inserting a whole number of instructions,
15257 pad the end of the fixed part of the frag with zeros. */
15258 memset (p, 0, excess);
15259 p += excess;
15260 fragp->fr_fix += excess;
15261 }
15262
15263 md_number_to_chars (p, opcode, size);
15264 fragp->fr_var = size;
15265}
15266
15267static void
15268md_obj_begin (void)
15269{
15270}
15271
15272static void
15273md_obj_end (void)
15274{
15275 /* Check for premature end, nesting errors, etc. */
15276 if (cur_proc_ptr)
15277 as_warn (_("missing .end at end of assembly"));
15278}
15279
15280static long
15281get_number (void)
15282{
15283 int negative = 0;
15284 long val = 0;
15285
15286 if (*input_line_pointer == '-')
15287 {
15288 ++input_line_pointer;
15289 negative = 1;
15290 }
15291 if (!ISDIGIT (*input_line_pointer))
15292 as_bad (_("expected simple number"));
15293 if (input_line_pointer[0] == '0')
15294 {
15295 if (input_line_pointer[1] == 'x')
15296 {
15297 input_line_pointer += 2;
15298 while (ISXDIGIT (*input_line_pointer))
15299 {
15300 val <<= 4;
15301 val |= hex_value (*input_line_pointer++);
15302 }
15303 return negative ? -val : val;
15304 }
15305 else
15306 {
15307 ++input_line_pointer;
15308 while (ISDIGIT (*input_line_pointer))
15309 {
15310 val <<= 3;
15311 val |= *input_line_pointer++ - '0';
15312 }
15313 return negative ? -val : val;
15314 }
15315 }
15316 if (!ISDIGIT (*input_line_pointer))
15317 {
15318 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
15319 *input_line_pointer, *input_line_pointer);
15320 as_warn (_("invalid number"));
15321 return -1;
15322 }
15323 while (ISDIGIT (*input_line_pointer))
15324 {
15325 val *= 10;
15326 val += *input_line_pointer++ - '0';
15327 }
15328 return negative ? -val : val;
15329}
15330
15331/* The .file directive; just like the usual .file directive, but there
15332 is an initial number which is the ECOFF file index. In the non-ECOFF
15333 case .file implies DWARF-2. */
15334
15335static void
15336s_mips_file (int x ATTRIBUTE_UNUSED)
15337{
15338 static int first_file_directive = 0;
15339
15340 if (ECOFF_DEBUGGING)
15341 {
15342 get_number ();
15343 s_app_file (0);
15344 }
15345 else
15346 {
15347 char *filename;
15348
15349 filename = dwarf2_directive_file (0);
15350
15351 /* Versions of GCC up to 3.1 start files with a ".file"
15352 directive even for stabs output. Make sure that this
15353 ".file" is handled. Note that you need a version of GCC
15354 after 3.1 in order to support DWARF-2 on MIPS. */
15355 if (filename != NULL && ! first_file_directive)
15356 {
15357 (void) new_logical_line (filename, -1);
15358 s_app_file_string (filename, 0);
15359 }
15360 first_file_directive = 1;
15361 }
15362}
15363
15364/* The .loc directive, implying DWARF-2. */
15365
15366static void
15367s_mips_loc (int x ATTRIBUTE_UNUSED)
15368{
15369 if (!ECOFF_DEBUGGING)
15370 dwarf2_directive_loc (0);
15371}
15372
15373/* The .end directive. */
15374
15375static void
15376s_mips_end (int x ATTRIBUTE_UNUSED)
15377{
15378 symbolS *p;
15379
15380 /* Following functions need their own .frame and .cprestore directives. */
15381 mips_frame_reg_valid = 0;
15382 mips_cprestore_valid = 0;
15383
15384 if (!is_end_of_line[(unsigned char) *input_line_pointer])
15385 {
15386 p = get_symbol ();
15387 demand_empty_rest_of_line ();
15388 }
15389 else
15390 p = NULL;
15391
15392 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15393 as_warn (_(".end not in text section"));
15394
15395 if (!cur_proc_ptr)
15396 {
15397 as_warn (_(".end directive without a preceding .ent directive."));
15398 demand_empty_rest_of_line ();
15399 return;
15400 }
15401
15402 if (p != NULL)
15403 {
15404 gas_assert (S_GET_NAME (p));
15405 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
15406 as_warn (_(".end symbol does not match .ent symbol."));
15407
15408 if (debug_type == DEBUG_STABS)
15409 stabs_generate_asm_endfunc (S_GET_NAME (p),
15410 S_GET_NAME (p));
15411 }
15412 else
15413 as_warn (_(".end directive missing or unknown symbol"));
15414
15415#ifdef OBJ_ELF
15416 /* Create an expression to calculate the size of the function. */
15417 if (p && cur_proc_ptr)
15418 {
15419 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
15420 expressionS *exp = xmalloc (sizeof (expressionS));
15421
15422 obj->size = exp;
15423 exp->X_op = O_subtract;
15424 exp->X_add_symbol = symbol_temp_new_now ();
15425 exp->X_op_symbol = p;
15426 exp->X_add_number = 0;
15427
15428 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
15429 }
15430
15431 /* Generate a .pdr section. */
15432 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
15433 {
15434 segT saved_seg = now_seg;
15435 subsegT saved_subseg = now_subseg;
15436 expressionS exp;
15437 char *fragp;
15438
15439#ifdef md_flush_pending_output
15440 md_flush_pending_output ();
15441#endif
15442
15443 gas_assert (pdr_seg);
15444 subseg_set (pdr_seg, 0);
15445
15446 /* Write the symbol. */
15447 exp.X_op = O_symbol;
15448 exp.X_add_symbol = p;
15449 exp.X_add_number = 0;
15450 emit_expr (&exp, 4);
15451
15452 fragp = frag_more (7 * 4);
15453
15454 md_number_to_chars (fragp, cur_proc_ptr->reg_mask, 4);
15455 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4);
15456 md_number_to_chars (fragp + 8, cur_proc_ptr->fpreg_mask, 4);
15457 md_number_to_chars (fragp + 12, cur_proc_ptr->fpreg_offset, 4);
15458 md_number_to_chars (fragp + 16, cur_proc_ptr->frame_offset, 4);
15459 md_number_to_chars (fragp + 20, cur_proc_ptr->frame_reg, 4);
15460 md_number_to_chars (fragp + 24, cur_proc_ptr->pc_reg, 4);
15461
15462 subseg_set (saved_seg, saved_subseg);
15463 }
15464#endif /* OBJ_ELF */
15465
15466 cur_proc_ptr = NULL;
15467}
15468
15469/* The .aent and .ent directives. */
15470
15471static void
15472s_mips_ent (int aent)
15473{
15474 symbolS *symbolP;
15475
15476 symbolP = get_symbol ();
15477 if (*input_line_pointer == ',')
15478 ++input_line_pointer;
15479 SKIP_WHITESPACE ();
15480 if (ISDIGIT (*input_line_pointer)
15481 || *input_line_pointer == '-')
15482 get_number ();
15483
15484 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
15485 as_warn (_(".ent or .aent not in text section."));
15486
15487 if (!aent && cur_proc_ptr)
15488 as_warn (_("missing .end"));
15489
15490 if (!aent)
15491 {
15492 /* This function needs its own .frame and .cprestore directives. */
15493 mips_frame_reg_valid = 0;
15494 mips_cprestore_valid = 0;
15495
15496 cur_proc_ptr = &cur_proc;
15497 memset (cur_proc_ptr, '\0', sizeof (procS));
15498
15499 cur_proc_ptr->func_sym = symbolP;
15500
15501 ++numprocs;
15502
15503 if (debug_type == DEBUG_STABS)
15504 stabs_generate_asm_func (S_GET_NAME (symbolP),
15505 S_GET_NAME (symbolP));
15506 }
15507
15508 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
15509
15510 demand_empty_rest_of_line ();
15511}
15512
15513/* The .frame directive. If the mdebug section is present (IRIX 5 native)
15514 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
15515 s_mips_frame is used so that we can set the PDR information correctly.
15516 We can't use the ecoff routines because they make reference to the ecoff
15517 symbol table (in the mdebug section). */
15518
15519static void
15520s_mips_frame (int ignore ATTRIBUTE_UNUSED)
15521{
15522#ifdef OBJ_ELF
15523 if (IS_ELF && !ECOFF_DEBUGGING)
15524 {
15525 long val;
15526
15527 if (cur_proc_ptr == (procS *) NULL)
15528 {
15529 as_warn (_(".frame outside of .ent"));
15530 demand_empty_rest_of_line ();
15531 return;
15532 }
15533
15534 cur_proc_ptr->frame_reg = tc_get_register (1);
15535
15536 SKIP_WHITESPACE ();
15537 if (*input_line_pointer++ != ','
15538 || get_absolute_expression_and_terminator (&val) != ',')
15539 {
15540 as_warn (_("Bad .frame directive"));
15541 --input_line_pointer;
15542 demand_empty_rest_of_line ();
15543 return;
15544 }
15545
15546 cur_proc_ptr->frame_offset = val;
15547 cur_proc_ptr->pc_reg = tc_get_register (0);
15548
15549 demand_empty_rest_of_line ();
15550 }
15551 else
15552#endif /* OBJ_ELF */
15553 s_ignore (ignore);
15554}
15555
15556/* The .fmask and .mask directives. If the mdebug section is present
15557 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15558 embedded targets, s_mips_mask is used so that we can set the PDR
15559 information correctly. We can't use the ecoff routines because they
15560 make reference to the ecoff symbol table (in the mdebug section). */
15561
15562static void
15563s_mips_mask (int reg_type)
15564{
15565#ifdef OBJ_ELF
15566 if (IS_ELF && !ECOFF_DEBUGGING)
15567 {
15568 long mask, off;
15569
15570 if (cur_proc_ptr == (procS *) NULL)
15571 {
15572 as_warn (_(".mask/.fmask outside of .ent"));
15573 demand_empty_rest_of_line ();
15574 return;
15575 }
15576
15577 if (get_absolute_expression_and_terminator (&mask) != ',')
15578 {
15579 as_warn (_("Bad .mask/.fmask directive"));
15580 --input_line_pointer;
15581 demand_empty_rest_of_line ();
15582 return;
15583 }
15584
15585 off = get_absolute_expression ();
15586
15587 if (reg_type == 'F')
15588 {
15589 cur_proc_ptr->fpreg_mask = mask;
15590 cur_proc_ptr->fpreg_offset = off;
15591 }
15592 else
15593 {
15594 cur_proc_ptr->reg_mask = mask;
15595 cur_proc_ptr->reg_offset = off;
15596 }
15597
15598 demand_empty_rest_of_line ();
15599 }
15600 else
15601#endif /* OBJ_ELF */
15602 s_ignore (reg_type);
15603}
15604
15605/* A table describing all the processors gas knows about. Names are
15606 matched in the order listed.
15607
15608 To ease comparison, please keep this table in the same order as
15609 gcc's mips_cpu_info_table[]. */
15610static const struct mips_cpu_info mips_cpu_info_table[] =
15611{
15612 /* Entries for generic ISAs */
15613 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15614 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15615 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15616 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15617 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15618 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15619 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15620 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15621 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
15622
15623 /* MIPS I */
15624 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15625 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15626 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15627
15628 /* MIPS II */
15629 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15630
15631 /* MIPS III */
15632 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15633 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15634 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15635 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15636 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15637 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15638 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15639 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15640 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15641 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15642 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15643 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15644 /* ST Microelectronics Loongson 2E and 2F cores */
15645 { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
15646 { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
15647
15648 /* MIPS IV */
15649 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15650 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15651 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15652 { "r14000", 0, ISA_MIPS4, CPU_R14000 },
15653 { "r16000", 0, ISA_MIPS4, CPU_R16000 },
15654 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15655 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15656 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15657 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15658 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15659 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15660 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15661 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15662 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15663 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15664
15665 /* MIPS 32 */
15666 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15667 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15668 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15669 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
15670
15671 /* MIPS 32 Release 2 */
15672 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15673 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15674 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15675 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15676 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15677 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15678 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15679 { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15680 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15681 { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15682 /* Deprecated forms of the above. */
15683 { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15684 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15685 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15686 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15687 { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15688 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15689 { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15690 /* Deprecated forms of the above. */
15691 { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15692 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15693 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15694 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15695 ISA_MIPS32R2, CPU_MIPS32R2 },
15696 { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15697 ISA_MIPS32R2, CPU_MIPS32R2 },
15698 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15699 ISA_MIPS32R2, CPU_MIPS32R2 },
15700 { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15701 ISA_MIPS32R2, CPU_MIPS32R2 },
15702 /* Deprecated forms of the above. */
15703 { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15704 ISA_MIPS32R2, CPU_MIPS32R2 },
15705 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15706 ISA_MIPS32R2, CPU_MIPS32R2 },
15707 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15708 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15709 ISA_MIPS32R2, CPU_MIPS32R2 },
15710 { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15711 ISA_MIPS32R2, CPU_MIPS32R2 },
15712 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15713 ISA_MIPS32R2, CPU_MIPS32R2 },
15714 { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15715 ISA_MIPS32R2, CPU_MIPS32R2 },
15716 { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15717 ISA_MIPS32R2, CPU_MIPS32R2 },
15718 /* Deprecated forms of the above. */
15719 { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15720 ISA_MIPS32R2, CPU_MIPS32R2 },
15721 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15722 ISA_MIPS32R2, CPU_MIPS32R2 },
15723 /* 1004K cores are multiprocessor versions of the 34K. */
15724 { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15725 ISA_MIPS32R2, CPU_MIPS32R2 },
15726 { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15727 ISA_MIPS32R2, CPU_MIPS32R2 },
15728 { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15729 ISA_MIPS32R2, CPU_MIPS32R2 },
15730 { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15731 ISA_MIPS32R2, CPU_MIPS32R2 },
15732
15733 /* MIPS 64 */
15734 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15735 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15736 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15737 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15738
15739 /* Broadcom SB-1 CPU core */
15740 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15741 ISA_MIPS64, CPU_SB1 },
15742 /* Broadcom SB-1A CPU core */
15743 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15744 ISA_MIPS64, CPU_SB1 },
15745
15746 { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
15747
15748 /* MIPS 64 Release 2 */
15749
15750 /* Cavium Networks Octeon CPU core */
15751 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15752
15753 /* RMI Xlr */
15754 { "xlr", 0, ISA_MIPS64, CPU_XLR },
15755
15756 /* End marker */
15757 { NULL, 0, 0, 0 }
15758};
15759
15760
15761/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15762 with a final "000" replaced by "k". Ignore case.
15763
15764 Note: this function is shared between GCC and GAS. */
15765
15766static bfd_boolean
15767mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15768{
15769 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15770 given++, canonical++;
15771
15772 return ((*given == 0 && *canonical == 0)
15773 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15774}
15775
15776
15777/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15778 CPU name. We've traditionally allowed a lot of variation here.
15779
15780 Note: this function is shared between GCC and GAS. */
15781
15782static bfd_boolean
15783mips_matching_cpu_name_p (const char *canonical, const char *given)
15784{
15785 /* First see if the name matches exactly, or with a final "000"
15786 turned into "k". */
15787 if (mips_strict_matching_cpu_name_p (canonical, given))
15788 return TRUE;
15789
15790 /* If not, try comparing based on numerical designation alone.
15791 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15792 if (TOLOWER (*given) == 'r')
15793 given++;
15794 if (!ISDIGIT (*given))
15795 return FALSE;
15796
15797 /* Skip over some well-known prefixes in the canonical name,
15798 hoping to find a number there too. */
15799 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15800 canonical += 2;
15801 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15802 canonical += 2;
15803 else if (TOLOWER (canonical[0]) == 'r')
15804 canonical += 1;
15805
15806 return mips_strict_matching_cpu_name_p (canonical, given);
15807}
15808
15809
15810/* Parse an option that takes the name of a processor as its argument.
15811 OPTION is the name of the option and CPU_STRING is the argument.
15812 Return the corresponding processor enumeration if the CPU_STRING is
15813 recognized, otherwise report an error and return null.
15814
15815 A similar function exists in GCC. */
15816
15817static const struct mips_cpu_info *
15818mips_parse_cpu (const char *option, const char *cpu_string)
15819{
15820 const struct mips_cpu_info *p;
15821
15822 /* 'from-abi' selects the most compatible architecture for the given
15823 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15824 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15825 version. Look first at the -mgp options, if given, otherwise base
15826 the choice on MIPS_DEFAULT_64BIT.
15827
15828 Treat NO_ABI like the EABIs. One reason to do this is that the
15829 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15830 architecture. This code picks MIPS I for 'mips' and MIPS III for
15831 'mips64', just as we did in the days before 'from-abi'. */
15832 if (strcasecmp (cpu_string, "from-abi") == 0)
15833 {
15834 if (ABI_NEEDS_32BIT_REGS (mips_abi))
15835 return mips_cpu_info_from_isa (ISA_MIPS1);
15836
15837 if (ABI_NEEDS_64BIT_REGS (mips_abi))
15838 return mips_cpu_info_from_isa (ISA_MIPS3);
15839
15840 if (file_mips_gp32 >= 0)
15841 return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3);
15842
15843 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15844 ? ISA_MIPS3
15845 : ISA_MIPS1);
15846 }
15847
15848 /* 'default' has traditionally been a no-op. Probably not very useful. */
15849 if (strcasecmp (cpu_string, "default") == 0)
15850 return 0;
15851
15852 for (p = mips_cpu_info_table; p->name != 0; p++)
15853 if (mips_matching_cpu_name_p (p->name, cpu_string))
15854 return p;
15855
15856 as_bad (_("Bad value (%s) for %s"), cpu_string, option);
15857 return 0;
15858}
15859
15860/* Return the canonical processor information for ISA (a member of the
15861 ISA_MIPS* enumeration). */
15862
15863static const struct mips_cpu_info *
15864mips_cpu_info_from_isa (int isa)
15865{
15866 int i;
15867
15868 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15869 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
15870 && isa == mips_cpu_info_table[i].isa)
15871 return (&mips_cpu_info_table[i]);
15872
15873 return NULL;
15874}
15875
15876static const struct mips_cpu_info *
15877mips_cpu_info_from_arch (int arch)
15878{
15879 int i;
15880
15881 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15882 if (arch == mips_cpu_info_table[i].cpu)
15883 return (&mips_cpu_info_table[i]);
15884
15885 return NULL;
15886}
15887\f
15888static void
15889show (FILE *stream, const char *string, int *col_p, int *first_p)
15890{
15891 if (*first_p)
15892 {
15893 fprintf (stream, "%24s", "");
15894 *col_p = 24;
15895 }
15896 else
15897 {
15898 fprintf (stream, ", ");
15899 *col_p += 2;
15900 }
15901
15902 if (*col_p + strlen (string) > 72)
15903 {
15904 fprintf (stream, "\n%24s", "");
15905 *col_p = 24;
15906 }
15907
15908 fprintf (stream, "%s", string);
15909 *col_p += strlen (string);
15910
15911 *first_p = 0;
15912}
15913
15914void
15915md_show_usage (FILE *stream)
15916{
15917 int column, first;
15918 size_t i;
15919
15920 fprintf (stream, _("\
15921MIPS options:\n\
15922-EB generate big endian output\n\
15923-EL generate little endian output\n\
15924-g, -g2 do not remove unneeded NOPs or swap branches\n\
15925-G NUM allow referencing objects up to NUM bytes\n\
15926 implicitly with the gp register [default 8]\n"));
15927 fprintf (stream, _("\
15928-mips1 generate MIPS ISA I instructions\n\
15929-mips2 generate MIPS ISA II instructions\n\
15930-mips3 generate MIPS ISA III instructions\n\
15931-mips4 generate MIPS ISA IV instructions\n\
15932-mips5 generate MIPS ISA V instructions\n\
15933-mips32 generate MIPS32 ISA instructions\n\
15934-mips32r2 generate MIPS32 release 2 ISA instructions\n\
15935-mips64 generate MIPS64 ISA instructions\n\
15936-mips64r2 generate MIPS64 release 2 ISA instructions\n\
15937-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15938
15939 first = 1;
15940
15941 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15942 show (stream, mips_cpu_info_table[i].name, &column, &first);
15943 show (stream, "from-abi", &column, &first);
15944 fputc ('\n', stream);
15945
15946 fprintf (stream, _("\
15947-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15948-no-mCPU don't generate code specific to CPU.\n\
15949 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15950
15951 first = 1;
15952
15953 show (stream, "3900", &column, &first);
15954 show (stream, "4010", &column, &first);
15955 show (stream, "4100", &column, &first);
15956 show (stream, "4650", &column, &first);
15957 fputc ('\n', stream);
15958
15959 fprintf (stream, _("\
15960-mips16 generate mips16 instructions\n\
15961-no-mips16 do not generate mips16 instructions\n"));
15962 fprintf (stream, _("\
15963-msmartmips generate smartmips instructions\n\
15964-mno-smartmips do not generate smartmips instructions\n"));
15965 fprintf (stream, _("\
15966-mdsp generate DSP instructions\n\
15967-mno-dsp do not generate DSP instructions\n"));
15968 fprintf (stream, _("\
15969-mdspr2 generate DSP R2 instructions\n\
15970-mno-dspr2 do not generate DSP R2 instructions\n"));
15971 fprintf (stream, _("\
15972-mmt generate MT instructions\n\
15973-mno-mt do not generate MT instructions\n"));
15974 fprintf (stream, _("\
15975-mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
15976-mfix-loongson2f-nop work around Loongson2F NOP errata\n\
15977-mfix-vr4120 work around certain VR4120 errata\n\
15978-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15979-mfix-24k insert a nop after ERET and DERET instructions\n\
15980-mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
15981-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15982-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15983-msym32 assume all symbols have 32-bit values\n\
15984-O0 remove unneeded NOPs, do not swap branches\n\
15985-O remove unneeded NOPs and swap branches\n\
15986--trap, --no-break trap exception on div by 0 and mult overflow\n\
15987--break, --no-trap break exception on div by 0 and mult overflow\n"));
15988 fprintf (stream, _("\
15989-mhard-float allow floating-point instructions\n\
15990-msoft-float do not allow floating-point instructions\n\
15991-msingle-float only allow 32-bit floating-point operations\n\
15992-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15993--[no-]construct-floats [dis]allow floating point values to be constructed\n"
15994 ));
15995#ifdef OBJ_ELF
15996 fprintf (stream, _("\
15997-KPIC, -call_shared generate SVR4 position independent code\n\
15998-call_nonpic generate non-PIC code that can operate with DSOs\n\
15999-mvxworks-pic generate VxWorks position independent code\n\
16000-non_shared do not generate code that can operate with DSOs\n\
16001-xgot assume a 32 bit GOT\n\
16002-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
16003-mshared, -mno-shared disable/enable .cpload optimization for\n\
16004 position dependent (non shared) code\n\
16005-mabi=ABI create ABI conformant object file for:\n"));
16006
16007 first = 1;
16008
16009 show (stream, "32", &column, &first);
16010 show (stream, "o64", &column, &first);
16011 show (stream, "n32", &column, &first);
16012 show (stream, "64", &column, &first);
16013 show (stream, "eabi", &column, &first);
16014
16015 fputc ('\n', stream);
16016
16017 fprintf (stream, _("\
16018-32 create o32 ABI object file (default)\n\
16019-n32 create n32 ABI object file\n\
16020-64 create 64 ABI object file\n"));
16021#endif
16022}
16023
16024#ifdef TE_IRIX
16025enum dwarf2_format
16026mips_dwarf2_format (asection *sec ATTRIBUTE_UNUSED)
16027{
16028 if (HAVE_64BIT_SYMBOLS)
16029 return dwarf2_format_64bit_irix;
16030 else
16031 return dwarf2_format_32bit;
16032}
16033#endif
16034
16035int
16036mips_dwarf2_addr_size (void)
16037{
16038 if (HAVE_64BIT_OBJECTS)
16039 return 8;
16040 else
16041 return 4;
16042}
16043
16044/* Standard calling conventions leave the CFA at SP on entry. */
16045void
16046mips_cfi_frame_initial_instructions (void)
16047{
16048 cfi_add_CFA_def_cfa_register (SP);
16049}
16050
16051int
16052tc_mips_regname_to_dw2regnum (char *regname)
16053{
16054 unsigned int regnum = -1;
16055 unsigned int reg;
16056
16057 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
16058 regnum = reg;
16059
16060 return regnum;
16061}
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