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1/* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22#include "as.h"
23#include "safe-ctype.h"
24#include "subsegs.h"
25#include "dw2gencfi.h"
26#include "opcode/ppc.h"
27
28#ifdef OBJ_ELF
29#include "elf/ppc.h"
30#include "elf/ppc64.h"
31#include "dwarf2dbg.h"
32#endif
33
34#ifdef TE_PE
35#include "coff/pe.h"
36#endif
37
38#ifdef OBJ_XCOFF
39#include "coff/xcoff.h"
40#include "libxcoff.h"
41#endif
42
43/* This is the assembler for the PowerPC or POWER (RS/6000) chips. */
44
45/* Tell the main code what the endianness is. */
46extern int target_big_endian;
47
48/* Whether or not, we've set target_big_endian. */
49static int set_target_endian = 0;
50
51/* Whether to use user friendly register names. */
52#ifndef TARGET_REG_NAMES_P
53#ifdef TE_PE
54#define TARGET_REG_NAMES_P TRUE
55#else
56#define TARGET_REG_NAMES_P FALSE
57#endif
58#endif
59
60/* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST,
61 HIGHESTA. */
62
63/* #lo(value) denotes the least significant 16 bits of the indicated. */
64#define PPC_LO(v) ((v) & 0xffff)
65
66/* #hi(value) denotes bits 16 through 31 of the indicated value. */
67#define PPC_HI(v) (((v) >> 16) & 0xffff)
68
69/* #ha(value) denotes the high adjusted value: bits 16 through 31 of
70 the indicated value, compensating for #lo() being treated as a
71 signed number. */
72#define PPC_HA(v) PPC_HI ((v) + 0x8000)
73
74/* #higher(value) denotes bits 32 through 47 of the indicated value. */
75#define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff)
76
77/* #highera(value) denotes bits 32 through 47 of the indicated value,
78 compensating for #lo() being treated as a signed number. */
79#define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000)
80
81/* #highest(value) denotes bits 48 through 63 of the indicated value. */
82#define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff)
83
84/* #highesta(value) denotes bits 48 through 63 of the indicated value,
85 compensating for #lo being treated as a signed number. */
86#define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000)
87
88#define SEX16(val) (((val) ^ 0x8000) - 0x8000)
89
90/* For the time being on ppc64, don't report overflow on @h and @ha
91 applied to constants. */
92#define REPORT_OVERFLOW_HI 0
93
94static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
95
96static void ppc_macro (char *, const struct powerpc_macro *);
97static void ppc_byte (int);
98
99#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
100static void ppc_tc (int);
101static void ppc_machine (int);
102#endif
103
104#ifdef OBJ_XCOFF
105static void ppc_comm (int);
106static void ppc_bb (int);
107static void ppc_bc (int);
108static void ppc_bf (int);
109static void ppc_biei (int);
110static void ppc_bs (int);
111static void ppc_eb (int);
112static void ppc_ec (int);
113static void ppc_ef (int);
114static void ppc_es (int);
115static void ppc_csect (int);
116static void ppc_dwsect (int);
117static void ppc_change_csect (symbolS *, offsetT);
118static void ppc_function (int);
119static void ppc_extern (int);
120static void ppc_lglobl (int);
121static void ppc_ref (int);
122static void ppc_section (int);
123static void ppc_named_section (int);
124static void ppc_stabx (int);
125static void ppc_rename (int);
126static void ppc_toc (int);
127static void ppc_xcoff_cons (int);
128static void ppc_vbyte (int);
129#endif
130
131#ifdef OBJ_ELF
132static void ppc_elf_rdata (int);
133static void ppc_elf_lcomm (int);
134static void ppc_elf_localentry (int);
135static void ppc_elf_abiversion (int);
136static void ppc_elf_gnu_attribute (int);
137#endif
138
139#ifdef TE_PE
140static void ppc_previous (int);
141static void ppc_pdata (int);
142static void ppc_ydata (int);
143static void ppc_reldata (int);
144static void ppc_rdata (int);
145static void ppc_ualong (int);
146static void ppc_znop (int);
147static void ppc_pe_comm (int);
148static void ppc_pe_section (int);
149static void ppc_pe_function (int);
150static void ppc_pe_tocd (int);
151#endif
152\f
153/* Generic assembler global variables which must be defined by all
154 targets. */
155
156#ifdef OBJ_ELF
157/* This string holds the chars that always start a comment. If the
158 pre-processor is disabled, these aren't very useful. The macro
159 tc_comment_chars points to this. We use this, rather than the
160 usual comment_chars, so that we can switch for Solaris conventions. */
161static const char ppc_solaris_comment_chars[] = "#!";
162static const char ppc_eabi_comment_chars[] = "#";
163
164#ifdef TARGET_SOLARIS_COMMENT
165const char *ppc_comment_chars = ppc_solaris_comment_chars;
166#else
167const char *ppc_comment_chars = ppc_eabi_comment_chars;
168#endif
169#else
170const char comment_chars[] = "#";
171#endif
172
173/* Characters which start a comment at the beginning of a line. */
174const char line_comment_chars[] = "#";
175
176/* Characters which may be used to separate multiple commands on a
177 single line. */
178const char line_separator_chars[] = ";";
179
180/* Characters which are used to indicate an exponent in a floating
181 point number. */
182const char EXP_CHARS[] = "eE";
183
184/* Characters which mean that a number is a floating point constant,
185 as in 0d1.0. */
186const char FLT_CHARS[] = "dD";
187
188/* Anything that can start an operand needs to be mentioned here,
189 to stop the input scrubber eating whitespace. */
190const char ppc_symbol_chars[] = "%[";
191
192/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
193int ppc_cie_data_alignment;
194
195/* The dwarf2 minimum instruction length. */
196int ppc_dwarf2_line_min_insn_length;
197
198/* More than this number of nops in an alignment op gets a branch
199 instead. */
200unsigned long nop_limit = 4;
201
202/* The type of processor we are assembling for. This is one or more
203 of the PPC_OPCODE flags defined in opcode/ppc.h. */
204ppc_cpu_t ppc_cpu = 0;
205ppc_cpu_t sticky = 0;
206
207/* Value for ELF e_flags EF_PPC64_ABI. */
208unsigned int ppc_abiversion = 0;
209
210#ifdef OBJ_ELF
211/* Flags set on encountering toc relocs. */
212static enum {
213 has_large_toc_reloc = 1,
214 has_small_toc_reloc = 2
215} toc_reloc_types;
216#endif
217
218/* Warn on emitting data to code sections. */
219int warn_476;
220uint64_t last_insn;
221segT last_seg;
222subsegT last_subseg;
223\f
224/* The target specific pseudo-ops which we support. */
225
226const pseudo_typeS md_pseudo_table[] =
227{
228 /* Pseudo-ops which must be overridden. */
229 { "byte", ppc_byte, 0 },
230
231#ifdef OBJ_XCOFF
232 /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these
233 legitimately belong in the obj-*.c file. However, XCOFF is based
234 on COFF, and is only implemented for the RS/6000. We just use
235 obj-coff.c, and add what we need here. */
236 { "comm", ppc_comm, 0 },
237 { "lcomm", ppc_comm, 1 },
238 { "bb", ppc_bb, 0 },
239 { "bc", ppc_bc, 0 },
240 { "bf", ppc_bf, 0 },
241 { "bi", ppc_biei, 0 },
242 { "bs", ppc_bs, 0 },
243 { "csect", ppc_csect, 0 },
244 { "dwsect", ppc_dwsect, 0 },
245 { "data", ppc_section, 'd' },
246 { "eb", ppc_eb, 0 },
247 { "ec", ppc_ec, 0 },
248 { "ef", ppc_ef, 0 },
249 { "ei", ppc_biei, 1 },
250 { "es", ppc_es, 0 },
251 { "extern", ppc_extern, 0 },
252 { "function", ppc_function, 0 },
253 { "lglobl", ppc_lglobl, 0 },
254 { "ref", ppc_ref, 0 },
255 { "rename", ppc_rename, 0 },
256 { "section", ppc_named_section, 0 },
257 { "stabx", ppc_stabx, 0 },
258 { "text", ppc_section, 't' },
259 { "toc", ppc_toc, 0 },
260 { "long", ppc_xcoff_cons, 2 },
261 { "llong", ppc_xcoff_cons, 3 },
262 { "word", ppc_xcoff_cons, 1 },
263 { "short", ppc_xcoff_cons, 1 },
264 { "vbyte", ppc_vbyte, 0 },
265#endif
266
267#ifdef OBJ_ELF
268 { "llong", cons, 8 },
269 { "rdata", ppc_elf_rdata, 0 },
270 { "rodata", ppc_elf_rdata, 0 },
271 { "lcomm", ppc_elf_lcomm, 0 },
272 { "localentry", ppc_elf_localentry, 0 },
273 { "abiversion", ppc_elf_abiversion, 0 },
274 { "gnu_attribute", ppc_elf_gnu_attribute, 0},
275#endif
276
277#ifdef TE_PE
278 /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */
279 { "previous", ppc_previous, 0 },
280 { "pdata", ppc_pdata, 0 },
281 { "ydata", ppc_ydata, 0 },
282 { "reldata", ppc_reldata, 0 },
283 { "rdata", ppc_rdata, 0 },
284 { "ualong", ppc_ualong, 0 },
285 { "znop", ppc_znop, 0 },
286 { "comm", ppc_pe_comm, 0 },
287 { "lcomm", ppc_pe_comm, 1 },
288 { "section", ppc_pe_section, 0 },
289 { "function", ppc_pe_function,0 },
290 { "tocd", ppc_pe_tocd, 0 },
291#endif
292
293#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
294 { "tc", ppc_tc, 0 },
295 { "machine", ppc_machine, 0 },
296#endif
297
298 { NULL, NULL, 0 }
299};
300
301\f
302/* Predefined register names if -mregnames (or default for Windows NT).
303 In general, there are lots of them, in an attempt to be compatible
304 with a number of other Windows NT assemblers. */
305
306/* Structure to hold information about predefined registers. */
307struct pd_reg
308 {
309 const char *name;
310 unsigned short value;
311 unsigned short flags;
312 };
313
314/* List of registers that are pre-defined:
315
316 Each general register has predefined names of the form:
317 1. r<reg_num> which has the value <reg_num>.
318 2. r.<reg_num> which has the value <reg_num>.
319
320 Each floating point register has predefined names of the form:
321 1. f<reg_num> which has the value <reg_num>.
322 2. f.<reg_num> which has the value <reg_num>.
323
324 Each vector unit register has predefined names of the form:
325 1. v<reg_num> which has the value <reg_num>.
326 2. v.<reg_num> which has the value <reg_num>.
327
328 Each condition register has predefined names of the form:
329 1. cr<reg_num> which has the value <reg_num>.
330 2. cr.<reg_num> which has the value <reg_num>.
331
332 There are individual registers as well:
333 sp or r.sp has the value 1
334 rtoc or r.toc has the value 2
335 xer has the value 1
336 lr has the value 8
337 ctr has the value 9
338 dar has the value 19
339 dsisr has the value 18
340 dec has the value 22
341 sdr1 has the value 25
342 srr0 has the value 26
343 srr1 has the value 27
344
345 The table is sorted. Suitable for searching by a binary search. */
346
347static const struct pd_reg pre_defined_registers[] =
348{
349 /* Condition Registers */
350 { "cr.0", 0, PPC_OPERAND_CR_REG },
351 { "cr.1", 1, PPC_OPERAND_CR_REG },
352 { "cr.2", 2, PPC_OPERAND_CR_REG },
353 { "cr.3", 3, PPC_OPERAND_CR_REG },
354 { "cr.4", 4, PPC_OPERAND_CR_REG },
355 { "cr.5", 5, PPC_OPERAND_CR_REG },
356 { "cr.6", 6, PPC_OPERAND_CR_REG },
357 { "cr.7", 7, PPC_OPERAND_CR_REG },
358
359 { "cr0", 0, PPC_OPERAND_CR_REG },
360 { "cr1", 1, PPC_OPERAND_CR_REG },
361 { "cr2", 2, PPC_OPERAND_CR_REG },
362 { "cr3", 3, PPC_OPERAND_CR_REG },
363 { "cr4", 4, PPC_OPERAND_CR_REG },
364 { "cr5", 5, PPC_OPERAND_CR_REG },
365 { "cr6", 6, PPC_OPERAND_CR_REG },
366 { "cr7", 7, PPC_OPERAND_CR_REG },
367
368 { "ctr", 9, PPC_OPERAND_SPR },
369 { "dar", 19, PPC_OPERAND_SPR },
370 { "dec", 22, PPC_OPERAND_SPR },
371 { "dsisr", 18, PPC_OPERAND_SPR },
372
373 /* Floating point registers */
374 { "f.0", 0, PPC_OPERAND_FPR },
375 { "f.1", 1, PPC_OPERAND_FPR },
376 { "f.10", 10, PPC_OPERAND_FPR },
377 { "f.11", 11, PPC_OPERAND_FPR },
378 { "f.12", 12, PPC_OPERAND_FPR },
379 { "f.13", 13, PPC_OPERAND_FPR },
380 { "f.14", 14, PPC_OPERAND_FPR },
381 { "f.15", 15, PPC_OPERAND_FPR },
382 { "f.16", 16, PPC_OPERAND_FPR },
383 { "f.17", 17, PPC_OPERAND_FPR },
384 { "f.18", 18, PPC_OPERAND_FPR },
385 { "f.19", 19, PPC_OPERAND_FPR },
386 { "f.2", 2, PPC_OPERAND_FPR },
387 { "f.20", 20, PPC_OPERAND_FPR },
388 { "f.21", 21, PPC_OPERAND_FPR },
389 { "f.22", 22, PPC_OPERAND_FPR },
390 { "f.23", 23, PPC_OPERAND_FPR },
391 { "f.24", 24, PPC_OPERAND_FPR },
392 { "f.25", 25, PPC_OPERAND_FPR },
393 { "f.26", 26, PPC_OPERAND_FPR },
394 { "f.27", 27, PPC_OPERAND_FPR },
395 { "f.28", 28, PPC_OPERAND_FPR },
396 { "f.29", 29, PPC_OPERAND_FPR },
397 { "f.3", 3, PPC_OPERAND_FPR },
398 { "f.30", 30, PPC_OPERAND_FPR },
399 { "f.31", 31, PPC_OPERAND_FPR },
400 { "f.32", 32, PPC_OPERAND_VSR },
401 { "f.33", 33, PPC_OPERAND_VSR },
402 { "f.34", 34, PPC_OPERAND_VSR },
403 { "f.35", 35, PPC_OPERAND_VSR },
404 { "f.36", 36, PPC_OPERAND_VSR },
405 { "f.37", 37, PPC_OPERAND_VSR },
406 { "f.38", 38, PPC_OPERAND_VSR },
407 { "f.39", 39, PPC_OPERAND_VSR },
408 { "f.4", 4, PPC_OPERAND_FPR },
409 { "f.40", 40, PPC_OPERAND_VSR },
410 { "f.41", 41, PPC_OPERAND_VSR },
411 { "f.42", 42, PPC_OPERAND_VSR },
412 { "f.43", 43, PPC_OPERAND_VSR },
413 { "f.44", 44, PPC_OPERAND_VSR },
414 { "f.45", 45, PPC_OPERAND_VSR },
415 { "f.46", 46, PPC_OPERAND_VSR },
416 { "f.47", 47, PPC_OPERAND_VSR },
417 { "f.48", 48, PPC_OPERAND_VSR },
418 { "f.49", 49, PPC_OPERAND_VSR },
419 { "f.5", 5, PPC_OPERAND_FPR },
420 { "f.50", 50, PPC_OPERAND_VSR },
421 { "f.51", 51, PPC_OPERAND_VSR },
422 { "f.52", 52, PPC_OPERAND_VSR },
423 { "f.53", 53, PPC_OPERAND_VSR },
424 { "f.54", 54, PPC_OPERAND_VSR },
425 { "f.55", 55, PPC_OPERAND_VSR },
426 { "f.56", 56, PPC_OPERAND_VSR },
427 { "f.57", 57, PPC_OPERAND_VSR },
428 { "f.58", 58, PPC_OPERAND_VSR },
429 { "f.59", 59, PPC_OPERAND_VSR },
430 { "f.6", 6, PPC_OPERAND_FPR },
431 { "f.60", 60, PPC_OPERAND_VSR },
432 { "f.61", 61, PPC_OPERAND_VSR },
433 { "f.62", 62, PPC_OPERAND_VSR },
434 { "f.63", 63, PPC_OPERAND_VSR },
435 { "f.7", 7, PPC_OPERAND_FPR },
436 { "f.8", 8, PPC_OPERAND_FPR },
437 { "f.9", 9, PPC_OPERAND_FPR },
438
439 { "f0", 0, PPC_OPERAND_FPR },
440 { "f1", 1, PPC_OPERAND_FPR },
441 { "f10", 10, PPC_OPERAND_FPR },
442 { "f11", 11, PPC_OPERAND_FPR },
443 { "f12", 12, PPC_OPERAND_FPR },
444 { "f13", 13, PPC_OPERAND_FPR },
445 { "f14", 14, PPC_OPERAND_FPR },
446 { "f15", 15, PPC_OPERAND_FPR },
447 { "f16", 16, PPC_OPERAND_FPR },
448 { "f17", 17, PPC_OPERAND_FPR },
449 { "f18", 18, PPC_OPERAND_FPR },
450 { "f19", 19, PPC_OPERAND_FPR },
451 { "f2", 2, PPC_OPERAND_FPR },
452 { "f20", 20, PPC_OPERAND_FPR },
453 { "f21", 21, PPC_OPERAND_FPR },
454 { "f22", 22, PPC_OPERAND_FPR },
455 { "f23", 23, PPC_OPERAND_FPR },
456 { "f24", 24, PPC_OPERAND_FPR },
457 { "f25", 25, PPC_OPERAND_FPR },
458 { "f26", 26, PPC_OPERAND_FPR },
459 { "f27", 27, PPC_OPERAND_FPR },
460 { "f28", 28, PPC_OPERAND_FPR },
461 { "f29", 29, PPC_OPERAND_FPR },
462 { "f3", 3, PPC_OPERAND_FPR },
463 { "f30", 30, PPC_OPERAND_FPR },
464 { "f31", 31, PPC_OPERAND_FPR },
465 { "f32", 32, PPC_OPERAND_VSR },
466 { "f33", 33, PPC_OPERAND_VSR },
467 { "f34", 34, PPC_OPERAND_VSR },
468 { "f35", 35, PPC_OPERAND_VSR },
469 { "f36", 36, PPC_OPERAND_VSR },
470 { "f37", 37, PPC_OPERAND_VSR },
471 { "f38", 38, PPC_OPERAND_VSR },
472 { "f39", 39, PPC_OPERAND_VSR },
473 { "f4", 4, PPC_OPERAND_FPR },
474 { "f40", 40, PPC_OPERAND_VSR },
475 { "f41", 41, PPC_OPERAND_VSR },
476 { "f42", 42, PPC_OPERAND_VSR },
477 { "f43", 43, PPC_OPERAND_VSR },
478 { "f44", 44, PPC_OPERAND_VSR },
479 { "f45", 45, PPC_OPERAND_VSR },
480 { "f46", 46, PPC_OPERAND_VSR },
481 { "f47", 47, PPC_OPERAND_VSR },
482 { "f48", 48, PPC_OPERAND_VSR },
483 { "f49", 49, PPC_OPERAND_VSR },
484 { "f5", 5, PPC_OPERAND_FPR },
485 { "f50", 50, PPC_OPERAND_VSR },
486 { "f51", 51, PPC_OPERAND_VSR },
487 { "f52", 52, PPC_OPERAND_VSR },
488 { "f53", 53, PPC_OPERAND_VSR },
489 { "f54", 54, PPC_OPERAND_VSR },
490 { "f55", 55, PPC_OPERAND_VSR },
491 { "f56", 56, PPC_OPERAND_VSR },
492 { "f57", 57, PPC_OPERAND_VSR },
493 { "f58", 58, PPC_OPERAND_VSR },
494 { "f59", 59, PPC_OPERAND_VSR },
495 { "f6", 6, PPC_OPERAND_FPR },
496 { "f60", 60, PPC_OPERAND_VSR },
497 { "f61", 61, PPC_OPERAND_VSR },
498 { "f62", 62, PPC_OPERAND_VSR },
499 { "f63", 63, PPC_OPERAND_VSR },
500 { "f7", 7, PPC_OPERAND_FPR },
501 { "f8", 8, PPC_OPERAND_FPR },
502 { "f9", 9, PPC_OPERAND_FPR },
503
504 /* Quantization registers used with pair single instructions. */
505 { "gqr.0", 0, PPC_OPERAND_GQR },
506 { "gqr.1", 1, PPC_OPERAND_GQR },
507 { "gqr.2", 2, PPC_OPERAND_GQR },
508 { "gqr.3", 3, PPC_OPERAND_GQR },
509 { "gqr.4", 4, PPC_OPERAND_GQR },
510 { "gqr.5", 5, PPC_OPERAND_GQR },
511 { "gqr.6", 6, PPC_OPERAND_GQR },
512 { "gqr.7", 7, PPC_OPERAND_GQR },
513 { "gqr0", 0, PPC_OPERAND_GQR },
514 { "gqr1", 1, PPC_OPERAND_GQR },
515 { "gqr2", 2, PPC_OPERAND_GQR },
516 { "gqr3", 3, PPC_OPERAND_GQR },
517 { "gqr4", 4, PPC_OPERAND_GQR },
518 { "gqr5", 5, PPC_OPERAND_GQR },
519 { "gqr6", 6, PPC_OPERAND_GQR },
520 { "gqr7", 7, PPC_OPERAND_GQR },
521
522 { "lr", 8, PPC_OPERAND_SPR },
523
524 /* General Purpose Registers */
525 { "r.0", 0, PPC_OPERAND_GPR },
526 { "r.1", 1, PPC_OPERAND_GPR },
527 { "r.10", 10, PPC_OPERAND_GPR },
528 { "r.11", 11, PPC_OPERAND_GPR },
529 { "r.12", 12, PPC_OPERAND_GPR },
530 { "r.13", 13, PPC_OPERAND_GPR },
531 { "r.14", 14, PPC_OPERAND_GPR },
532 { "r.15", 15, PPC_OPERAND_GPR },
533 { "r.16", 16, PPC_OPERAND_GPR },
534 { "r.17", 17, PPC_OPERAND_GPR },
535 { "r.18", 18, PPC_OPERAND_GPR },
536 { "r.19", 19, PPC_OPERAND_GPR },
537 { "r.2", 2, PPC_OPERAND_GPR },
538 { "r.20", 20, PPC_OPERAND_GPR },
539 { "r.21", 21, PPC_OPERAND_GPR },
540 { "r.22", 22, PPC_OPERAND_GPR },
541 { "r.23", 23, PPC_OPERAND_GPR },
542 { "r.24", 24, PPC_OPERAND_GPR },
543 { "r.25", 25, PPC_OPERAND_GPR },
544 { "r.26", 26, PPC_OPERAND_GPR },
545 { "r.27", 27, PPC_OPERAND_GPR },
546 { "r.28", 28, PPC_OPERAND_GPR },
547 { "r.29", 29, PPC_OPERAND_GPR },
548 { "r.3", 3, PPC_OPERAND_GPR },
549 { "r.30", 30, PPC_OPERAND_GPR },
550 { "r.31", 31, PPC_OPERAND_GPR },
551 { "r.4", 4, PPC_OPERAND_GPR },
552 { "r.5", 5, PPC_OPERAND_GPR },
553 { "r.6", 6, PPC_OPERAND_GPR },
554 { "r.7", 7, PPC_OPERAND_GPR },
555 { "r.8", 8, PPC_OPERAND_GPR },
556 { "r.9", 9, PPC_OPERAND_GPR },
557
558 { "r.sp", 1, PPC_OPERAND_GPR },
559
560 { "r.toc", 2, PPC_OPERAND_GPR },
561
562 { "r0", 0, PPC_OPERAND_GPR },
563 { "r1", 1, PPC_OPERAND_GPR },
564 { "r10", 10, PPC_OPERAND_GPR },
565 { "r11", 11, PPC_OPERAND_GPR },
566 { "r12", 12, PPC_OPERAND_GPR },
567 { "r13", 13, PPC_OPERAND_GPR },
568 { "r14", 14, PPC_OPERAND_GPR },
569 { "r15", 15, PPC_OPERAND_GPR },
570 { "r16", 16, PPC_OPERAND_GPR },
571 { "r17", 17, PPC_OPERAND_GPR },
572 { "r18", 18, PPC_OPERAND_GPR },
573 { "r19", 19, PPC_OPERAND_GPR },
574 { "r2", 2, PPC_OPERAND_GPR },
575 { "r20", 20, PPC_OPERAND_GPR },
576 { "r21", 21, PPC_OPERAND_GPR },
577 { "r22", 22, PPC_OPERAND_GPR },
578 { "r23", 23, PPC_OPERAND_GPR },
579 { "r24", 24, PPC_OPERAND_GPR },
580 { "r25", 25, PPC_OPERAND_GPR },
581 { "r26", 26, PPC_OPERAND_GPR },
582 { "r27", 27, PPC_OPERAND_GPR },
583 { "r28", 28, PPC_OPERAND_GPR },
584 { "r29", 29, PPC_OPERAND_GPR },
585 { "r3", 3, PPC_OPERAND_GPR },
586 { "r30", 30, PPC_OPERAND_GPR },
587 { "r31", 31, PPC_OPERAND_GPR },
588 { "r4", 4, PPC_OPERAND_GPR },
589 { "r5", 5, PPC_OPERAND_GPR },
590 { "r6", 6, PPC_OPERAND_GPR },
591 { "r7", 7, PPC_OPERAND_GPR },
592 { "r8", 8, PPC_OPERAND_GPR },
593 { "r9", 9, PPC_OPERAND_GPR },
594
595 { "rtoc", 2, PPC_OPERAND_GPR },
596
597 { "sdr1", 25, PPC_OPERAND_SPR },
598
599 { "sp", 1, PPC_OPERAND_GPR },
600
601 { "srr0", 26, PPC_OPERAND_SPR },
602 { "srr1", 27, PPC_OPERAND_SPR },
603
604 /* Vector (Altivec/VMX) registers */
605 { "v.0", 0, PPC_OPERAND_VR },
606 { "v.1", 1, PPC_OPERAND_VR },
607 { "v.10", 10, PPC_OPERAND_VR },
608 { "v.11", 11, PPC_OPERAND_VR },
609 { "v.12", 12, PPC_OPERAND_VR },
610 { "v.13", 13, PPC_OPERAND_VR },
611 { "v.14", 14, PPC_OPERAND_VR },
612 { "v.15", 15, PPC_OPERAND_VR },
613 { "v.16", 16, PPC_OPERAND_VR },
614 { "v.17", 17, PPC_OPERAND_VR },
615 { "v.18", 18, PPC_OPERAND_VR },
616 { "v.19", 19, PPC_OPERAND_VR },
617 { "v.2", 2, PPC_OPERAND_VR },
618 { "v.20", 20, PPC_OPERAND_VR },
619 { "v.21", 21, PPC_OPERAND_VR },
620 { "v.22", 22, PPC_OPERAND_VR },
621 { "v.23", 23, PPC_OPERAND_VR },
622 { "v.24", 24, PPC_OPERAND_VR },
623 { "v.25", 25, PPC_OPERAND_VR },
624 { "v.26", 26, PPC_OPERAND_VR },
625 { "v.27", 27, PPC_OPERAND_VR },
626 { "v.28", 28, PPC_OPERAND_VR },
627 { "v.29", 29, PPC_OPERAND_VR },
628 { "v.3", 3, PPC_OPERAND_VR },
629 { "v.30", 30, PPC_OPERAND_VR },
630 { "v.31", 31, PPC_OPERAND_VR },
631 { "v.4", 4, PPC_OPERAND_VR },
632 { "v.5", 5, PPC_OPERAND_VR },
633 { "v.6", 6, PPC_OPERAND_VR },
634 { "v.7", 7, PPC_OPERAND_VR },
635 { "v.8", 8, PPC_OPERAND_VR },
636 { "v.9", 9, PPC_OPERAND_VR },
637
638 { "v0", 0, PPC_OPERAND_VR },
639 { "v1", 1, PPC_OPERAND_VR },
640 { "v10", 10, PPC_OPERAND_VR },
641 { "v11", 11, PPC_OPERAND_VR },
642 { "v12", 12, PPC_OPERAND_VR },
643 { "v13", 13, PPC_OPERAND_VR },
644 { "v14", 14, PPC_OPERAND_VR },
645 { "v15", 15, PPC_OPERAND_VR },
646 { "v16", 16, PPC_OPERAND_VR },
647 { "v17", 17, PPC_OPERAND_VR },
648 { "v18", 18, PPC_OPERAND_VR },
649 { "v19", 19, PPC_OPERAND_VR },
650 { "v2", 2, PPC_OPERAND_VR },
651 { "v20", 20, PPC_OPERAND_VR },
652 { "v21", 21, PPC_OPERAND_VR },
653 { "v22", 22, PPC_OPERAND_VR },
654 { "v23", 23, PPC_OPERAND_VR },
655 { "v24", 24, PPC_OPERAND_VR },
656 { "v25", 25, PPC_OPERAND_VR },
657 { "v26", 26, PPC_OPERAND_VR },
658 { "v27", 27, PPC_OPERAND_VR },
659 { "v28", 28, PPC_OPERAND_VR },
660 { "v29", 29, PPC_OPERAND_VR },
661 { "v3", 3, PPC_OPERAND_VR },
662 { "v30", 30, PPC_OPERAND_VR },
663 { "v31", 31, PPC_OPERAND_VR },
664 { "v4", 4, PPC_OPERAND_VR },
665 { "v5", 5, PPC_OPERAND_VR },
666 { "v6", 6, PPC_OPERAND_VR },
667 { "v7", 7, PPC_OPERAND_VR },
668 { "v8", 8, PPC_OPERAND_VR },
669 { "v9", 9, PPC_OPERAND_VR },
670
671 /* Vector Scalar (VSX) registers (ISA 2.06). */
672 { "vs.0", 0, PPC_OPERAND_VSR },
673 { "vs.1", 1, PPC_OPERAND_VSR },
674 { "vs.10", 10, PPC_OPERAND_VSR },
675 { "vs.11", 11, PPC_OPERAND_VSR },
676 { "vs.12", 12, PPC_OPERAND_VSR },
677 { "vs.13", 13, PPC_OPERAND_VSR },
678 { "vs.14", 14, PPC_OPERAND_VSR },
679 { "vs.15", 15, PPC_OPERAND_VSR },
680 { "vs.16", 16, PPC_OPERAND_VSR },
681 { "vs.17", 17, PPC_OPERAND_VSR },
682 { "vs.18", 18, PPC_OPERAND_VSR },
683 { "vs.19", 19, PPC_OPERAND_VSR },
684 { "vs.2", 2, PPC_OPERAND_VSR },
685 { "vs.20", 20, PPC_OPERAND_VSR },
686 { "vs.21", 21, PPC_OPERAND_VSR },
687 { "vs.22", 22, PPC_OPERAND_VSR },
688 { "vs.23", 23, PPC_OPERAND_VSR },
689 { "vs.24", 24, PPC_OPERAND_VSR },
690 { "vs.25", 25, PPC_OPERAND_VSR },
691 { "vs.26", 26, PPC_OPERAND_VSR },
692 { "vs.27", 27, PPC_OPERAND_VSR },
693 { "vs.28", 28, PPC_OPERAND_VSR },
694 { "vs.29", 29, PPC_OPERAND_VSR },
695 { "vs.3", 3, PPC_OPERAND_VSR },
696 { "vs.30", 30, PPC_OPERAND_VSR },
697 { "vs.31", 31, PPC_OPERAND_VSR },
698 { "vs.32", 32, PPC_OPERAND_VSR },
699 { "vs.33", 33, PPC_OPERAND_VSR },
700 { "vs.34", 34, PPC_OPERAND_VSR },
701 { "vs.35", 35, PPC_OPERAND_VSR },
702 { "vs.36", 36, PPC_OPERAND_VSR },
703 { "vs.37", 37, PPC_OPERAND_VSR },
704 { "vs.38", 38, PPC_OPERAND_VSR },
705 { "vs.39", 39, PPC_OPERAND_VSR },
706 { "vs.4", 4, PPC_OPERAND_VSR },
707 { "vs.40", 40, PPC_OPERAND_VSR },
708 { "vs.41", 41, PPC_OPERAND_VSR },
709 { "vs.42", 42, PPC_OPERAND_VSR },
710 { "vs.43", 43, PPC_OPERAND_VSR },
711 { "vs.44", 44, PPC_OPERAND_VSR },
712 { "vs.45", 45, PPC_OPERAND_VSR },
713 { "vs.46", 46, PPC_OPERAND_VSR },
714 { "vs.47", 47, PPC_OPERAND_VSR },
715 { "vs.48", 48, PPC_OPERAND_VSR },
716 { "vs.49", 49, PPC_OPERAND_VSR },
717 { "vs.5", 5, PPC_OPERAND_VSR },
718 { "vs.50", 50, PPC_OPERAND_VSR },
719 { "vs.51", 51, PPC_OPERAND_VSR },
720 { "vs.52", 52, PPC_OPERAND_VSR },
721 { "vs.53", 53, PPC_OPERAND_VSR },
722 { "vs.54", 54, PPC_OPERAND_VSR },
723 { "vs.55", 55, PPC_OPERAND_VSR },
724 { "vs.56", 56, PPC_OPERAND_VSR },
725 { "vs.57", 57, PPC_OPERAND_VSR },
726 { "vs.58", 58, PPC_OPERAND_VSR },
727 { "vs.59", 59, PPC_OPERAND_VSR },
728 { "vs.6", 6, PPC_OPERAND_VSR },
729 { "vs.60", 60, PPC_OPERAND_VSR },
730 { "vs.61", 61, PPC_OPERAND_VSR },
731 { "vs.62", 62, PPC_OPERAND_VSR },
732 { "vs.63", 63, PPC_OPERAND_VSR },
733 { "vs.7", 7, PPC_OPERAND_VSR },
734 { "vs.8", 8, PPC_OPERAND_VSR },
735 { "vs.9", 9, PPC_OPERAND_VSR },
736
737 { "vs0", 0, PPC_OPERAND_VSR },
738 { "vs1", 1, PPC_OPERAND_VSR },
739 { "vs10", 10, PPC_OPERAND_VSR },
740 { "vs11", 11, PPC_OPERAND_VSR },
741 { "vs12", 12, PPC_OPERAND_VSR },
742 { "vs13", 13, PPC_OPERAND_VSR },
743 { "vs14", 14, PPC_OPERAND_VSR },
744 { "vs15", 15, PPC_OPERAND_VSR },
745 { "vs16", 16, PPC_OPERAND_VSR },
746 { "vs17", 17, PPC_OPERAND_VSR },
747 { "vs18", 18, PPC_OPERAND_VSR },
748 { "vs19", 19, PPC_OPERAND_VSR },
749 { "vs2", 2, PPC_OPERAND_VSR },
750 { "vs20", 20, PPC_OPERAND_VSR },
751 { "vs21", 21, PPC_OPERAND_VSR },
752 { "vs22", 22, PPC_OPERAND_VSR },
753 { "vs23", 23, PPC_OPERAND_VSR },
754 { "vs24", 24, PPC_OPERAND_VSR },
755 { "vs25", 25, PPC_OPERAND_VSR },
756 { "vs26", 26, PPC_OPERAND_VSR },
757 { "vs27", 27, PPC_OPERAND_VSR },
758 { "vs28", 28, PPC_OPERAND_VSR },
759 { "vs29", 29, PPC_OPERAND_VSR },
760 { "vs3", 3, PPC_OPERAND_VSR },
761 { "vs30", 30, PPC_OPERAND_VSR },
762 { "vs31", 31, PPC_OPERAND_VSR },
763 { "vs32", 32, PPC_OPERAND_VSR },
764 { "vs33", 33, PPC_OPERAND_VSR },
765 { "vs34", 34, PPC_OPERAND_VSR },
766 { "vs35", 35, PPC_OPERAND_VSR },
767 { "vs36", 36, PPC_OPERAND_VSR },
768 { "vs37", 37, PPC_OPERAND_VSR },
769 { "vs38", 38, PPC_OPERAND_VSR },
770 { "vs39", 39, PPC_OPERAND_VSR },
771 { "vs4", 4, PPC_OPERAND_VSR },
772 { "vs40", 40, PPC_OPERAND_VSR },
773 { "vs41", 41, PPC_OPERAND_VSR },
774 { "vs42", 42, PPC_OPERAND_VSR },
775 { "vs43", 43, PPC_OPERAND_VSR },
776 { "vs44", 44, PPC_OPERAND_VSR },
777 { "vs45", 45, PPC_OPERAND_VSR },
778 { "vs46", 46, PPC_OPERAND_VSR },
779 { "vs47", 47, PPC_OPERAND_VSR },
780 { "vs48", 48, PPC_OPERAND_VSR },
781 { "vs49", 49, PPC_OPERAND_VSR },
782 { "vs5", 5, PPC_OPERAND_VSR },
783 { "vs50", 50, PPC_OPERAND_VSR },
784 { "vs51", 51, PPC_OPERAND_VSR },
785 { "vs52", 52, PPC_OPERAND_VSR },
786 { "vs53", 53, PPC_OPERAND_VSR },
787 { "vs54", 54, PPC_OPERAND_VSR },
788 { "vs55", 55, PPC_OPERAND_VSR },
789 { "vs56", 56, PPC_OPERAND_VSR },
790 { "vs57", 57, PPC_OPERAND_VSR },
791 { "vs58", 58, PPC_OPERAND_VSR },
792 { "vs59", 59, PPC_OPERAND_VSR },
793 { "vs6", 6, PPC_OPERAND_VSR },
794 { "vs60", 60, PPC_OPERAND_VSR },
795 { "vs61", 61, PPC_OPERAND_VSR },
796 { "vs62", 62, PPC_OPERAND_VSR },
797 { "vs63", 63, PPC_OPERAND_VSR },
798 { "vs7", 7, PPC_OPERAND_VSR },
799 { "vs8", 8, PPC_OPERAND_VSR },
800 { "vs9", 9, PPC_OPERAND_VSR },
801
802 { "xer", 1, PPC_OPERAND_SPR }
803};
804
805#define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg))
806
807/* Given NAME, find the register number associated with that name, return
808 the integer value associated with the given name or -1 on failure. */
809
810static const struct pd_reg *
811reg_name_search (const struct pd_reg *regs, int regcount, const char *name)
812{
813 int middle, low, high;
814 int cmp;
815
816 low = 0;
817 high = regcount - 1;
818
819 do
820 {
821 middle = (low + high) / 2;
822 cmp = strcasecmp (name, regs[middle].name);
823 if (cmp < 0)
824 high = middle - 1;
825 else if (cmp > 0)
826 low = middle + 1;
827 else
828 return &regs[middle];
829 }
830 while (low <= high);
831
832 return NULL;
833}
834
835/*
836 * Summary of register_name.
837 *
838 * in: Input_line_pointer points to 1st char of operand.
839 *
840 * out: A expressionS.
841 * The operand may have been a register: in this case, X_op == O_register,
842 * X_add_number is set to the register number, and truth is returned.
843 * Input_line_pointer->(next non-blank) char after operand, or is in its
844 * original state.
845 */
846
847static bfd_boolean
848register_name (expressionS *expressionP)
849{
850 const struct pd_reg *reg;
851 char *name;
852 char *start;
853 char c;
854
855 /* Find the spelling of the operand. */
856 start = name = input_line_pointer;
857 if (name[0] == '%' && ISALPHA (name[1]))
858 name = ++input_line_pointer;
859
860 else if (!reg_names_p || !ISALPHA (name[0]))
861 return FALSE;
862
863 c = get_symbol_name (&name);
864 reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name);
865
866 /* Put back the delimiting char. */
867 *input_line_pointer = c;
868
869 /* Look to see if it's in the register table. */
870 if (reg != NULL)
871 {
872 expressionP->X_op = O_register;
873 expressionP->X_add_number = reg->value;
874 expressionP->X_md = reg->flags;
875
876 /* Make the rest nice. */
877 expressionP->X_add_symbol = NULL;
878 expressionP->X_op_symbol = NULL;
879 return TRUE;
880 }
881
882 /* Reset the line as if we had not done anything. */
883 input_line_pointer = start;
884 return FALSE;
885}
886\f
887/* This function is called for each symbol seen in an expression. It
888 handles the special parsing which PowerPC assemblers are supposed
889 to use for condition codes. */
890
891/* Whether to do the special parsing. */
892static bfd_boolean cr_operand;
893
894/* Names to recognize in a condition code. This table is sorted. */
895static const struct pd_reg cr_names[] =
896{
897 { "cr0", 0, PPC_OPERAND_CR_REG },
898 { "cr1", 1, PPC_OPERAND_CR_REG },
899 { "cr2", 2, PPC_OPERAND_CR_REG },
900 { "cr3", 3, PPC_OPERAND_CR_REG },
901 { "cr4", 4, PPC_OPERAND_CR_REG },
902 { "cr5", 5, PPC_OPERAND_CR_REG },
903 { "cr6", 6, PPC_OPERAND_CR_REG },
904 { "cr7", 7, PPC_OPERAND_CR_REG },
905 { "eq", 2, PPC_OPERAND_CR_BIT },
906 { "gt", 1, PPC_OPERAND_CR_BIT },
907 { "lt", 0, PPC_OPERAND_CR_BIT },
908 { "so", 3, PPC_OPERAND_CR_BIT },
909 { "un", 3, PPC_OPERAND_CR_BIT }
910};
911
912/* Parsing function. This returns non-zero if it recognized an
913 expression. */
914
915int
916ppc_parse_name (const char *name, expressionS *exp)
917{
918 const struct pd_reg *reg;
919
920 if (! cr_operand)
921 return 0;
922
923 if (*name == '%')
924 ++name;
925 reg = reg_name_search (cr_names, sizeof cr_names / sizeof cr_names[0],
926 name);
927 if (reg == NULL)
928 return 0;
929
930 exp->X_op = O_register;
931 exp->X_add_number = reg->value;
932 exp->X_md = reg->flags;
933
934 return 1;
935}
936
937/* Propagate X_md and check register expressions. This is to support
938 condition codes like 4*cr5+eq. */
939
940int
941ppc_optimize_expr (expressionS *left, operatorT op, expressionS *right)
942{
943 /* Accept 4*cr<n> and cr<n>*4. */
944 if (op == O_multiply
945 && ((right->X_op == O_register
946 && right->X_md == PPC_OPERAND_CR_REG
947 && left->X_op == O_constant
948 && left->X_add_number == 4)
949 || (left->X_op == O_register
950 && left->X_md == PPC_OPERAND_CR_REG
951 && right->X_op == O_constant
952 && right->X_add_number == 4)))
953 {
954 left->X_op = O_register;
955 left->X_md = PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT;
956 left->X_add_number *= right->X_add_number;
957 return 1;
958 }
959
960 /* Accept the above plus <cr bit>, and <cr bit> plus the above. */
961 if (right->X_op == O_register
962 && left->X_op == O_register
963 && op == O_add
964 && ((right->X_md == PPC_OPERAND_CR_BIT
965 && left->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT))
966 || (right->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT)
967 && left->X_md == PPC_OPERAND_CR_BIT)))
968 {
969 left->X_md = PPC_OPERAND_CR_BIT;
970 right->X_op = O_constant;
971 return 0;
972 }
973
974 /* Accept reg +/- constant. */
975 if (left->X_op == O_register
976 && !((op == O_add || op == O_subtract) && right->X_op == O_constant))
977 as_warn (_("invalid register expression"));
978
979 /* Accept constant + reg. */
980 if (right->X_op == O_register)
981 {
982 if (op == O_add && left->X_op == O_constant)
983 left->X_md = right->X_md;
984 else
985 as_warn (_("invalid register expression"));
986 }
987
988 return 0;
989}
990\f
991/* Local variables. */
992
993/* Whether to target xcoff64/elf64. */
994static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64;
995
996/* Opcode hash table. */
997static struct hash_control *ppc_hash;
998
999/* Macro hash table. */
1000static struct hash_control *ppc_macro_hash;
1001
1002#ifdef OBJ_ELF
1003/* What type of shared library support to use. */
1004static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE;
1005
1006/* Flags to set in the elf header. */
1007static flagword ppc_flags = 0;
1008
1009/* Whether this is Solaris or not. */
1010#ifdef TARGET_SOLARIS_COMMENT
1011#define SOLARIS_P TRUE
1012#else
1013#define SOLARIS_P FALSE
1014#endif
1015
1016static bfd_boolean msolaris = SOLARIS_P;
1017#endif
1018
1019#ifdef OBJ_XCOFF
1020
1021/* The RS/6000 assembler uses the .csect pseudo-op to generate code
1022 using a bunch of different sections. These assembler sections,
1023 however, are all encompassed within the .text or .data sections of
1024 the final output file. We handle this by using different
1025 subsegments within these main segments. */
1026
1027/* Next subsegment to allocate within the .text segment. */
1028static subsegT ppc_text_subsegment = 2;
1029
1030/* Linked list of csects in the text section. */
1031static symbolS *ppc_text_csects;
1032
1033/* Next subsegment to allocate within the .data segment. */
1034static subsegT ppc_data_subsegment = 2;
1035
1036/* Linked list of csects in the data section. */
1037static symbolS *ppc_data_csects;
1038
1039/* The current csect. */
1040static symbolS *ppc_current_csect;
1041
1042/* The RS/6000 assembler uses a TOC which holds addresses of functions
1043 and variables. Symbols are put in the TOC with the .tc pseudo-op.
1044 A special relocation is used when accessing TOC entries. We handle
1045 the TOC as a subsegment within the .data segment. We set it up if
1046 we see a .toc pseudo-op, and save the csect symbol here. */
1047static symbolS *ppc_toc_csect;
1048
1049/* The first frag in the TOC subsegment. */
1050static fragS *ppc_toc_frag;
1051
1052/* The first frag in the first subsegment after the TOC in the .data
1053 segment. NULL if there are no subsegments after the TOC. */
1054static fragS *ppc_after_toc_frag;
1055
1056/* The current static block. */
1057static symbolS *ppc_current_block;
1058
1059/* The COFF debugging section; set by md_begin. This is not the
1060 .debug section, but is instead the secret BFD section which will
1061 cause BFD to set the section number of a symbol to N_DEBUG. */
1062static asection *ppc_coff_debug_section;
1063
1064/* Structure to set the length field of the dwarf sections. */
1065struct dw_subsection {
1066 /* Subsections are simply linked. */
1067 struct dw_subsection *link;
1068
1069 /* The subsection number. */
1070 subsegT subseg;
1071
1072 /* Expression to compute the length of the section. */
1073 expressionS end_exp;
1074};
1075
1076static struct dw_section {
1077 /* Corresponding section. */
1078 segT sect;
1079
1080 /* Simply linked list of subsections with a label. */
1081 struct dw_subsection *list_subseg;
1082
1083 /* The anonymous subsection. */
1084 struct dw_subsection *anon_subseg;
1085} dw_sections[XCOFF_DWSECT_NBR_NAMES];
1086#endif /* OBJ_XCOFF */
1087
1088#ifdef TE_PE
1089
1090/* Various sections that we need for PE coff support. */
1091static segT ydata_section;
1092static segT pdata_section;
1093static segT reldata_section;
1094static segT rdata_section;
1095static segT tocdata_section;
1096
1097/* The current section and the previous section. See ppc_previous. */
1098static segT ppc_previous_section;
1099static segT ppc_current_section;
1100
1101#endif /* TE_PE */
1102
1103#ifdef OBJ_ELF
1104symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */
1105unsigned long *ppc_apuinfo_list;
1106unsigned int ppc_apuinfo_num;
1107unsigned int ppc_apuinfo_num_alloc;
1108#endif /* OBJ_ELF */
1109\f
1110#ifdef OBJ_ELF
1111const char *const md_shortopts = "b:l:usm:K:VQ:";
1112#else
1113const char *const md_shortopts = "um:";
1114#endif
1115#define OPTION_NOPS (OPTION_MD_BASE + 0)
1116const struct option md_longopts[] = {
1117 {"nops", required_argument, NULL, OPTION_NOPS},
1118 {"ppc476-workaround", no_argument, &warn_476, 1},
1119 {"no-ppc476-workaround", no_argument, &warn_476, 0},
1120 {NULL, no_argument, NULL, 0}
1121};
1122const size_t md_longopts_size = sizeof (md_longopts);
1123
1124int
1125md_parse_option (int c, const char *arg)
1126{
1127 ppc_cpu_t new_cpu;
1128
1129 switch (c)
1130 {
1131 case 'u':
1132 /* -u means that any undefined symbols should be treated as
1133 external, which is the default for gas anyhow. */
1134 break;
1135
1136#ifdef OBJ_ELF
1137 case 'l':
1138 /* Solaris as takes -le (presumably for little endian). For completeness
1139 sake, recognize -be also. */
1140 if (strcmp (arg, "e") == 0)
1141 {
1142 target_big_endian = 0;
1143 set_target_endian = 1;
1144 if (ppc_cpu & PPC_OPCODE_VLE)
1145 as_bad (_("the use of -mvle requires big endian."));
1146 }
1147 else
1148 return 0;
1149
1150 break;
1151
1152 case 'b':
1153 if (strcmp (arg, "e") == 0)
1154 {
1155 target_big_endian = 1;
1156 set_target_endian = 1;
1157 }
1158 else
1159 return 0;
1160
1161 break;
1162
1163 case 'K':
1164 /* Recognize -K PIC. */
1165 if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0)
1166 {
1167 shlib = SHLIB_PIC;
1168 ppc_flags |= EF_PPC_RELOCATABLE_LIB;
1169 }
1170 else
1171 return 0;
1172
1173 break;
1174#endif
1175
1176 /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */
1177 case 'a':
1178 if (strcmp (arg, "64") == 0)
1179 {
1180#ifdef BFD64
1181 ppc_obj64 = 1;
1182 if (ppc_cpu & PPC_OPCODE_VLE)
1183 as_bad (_("the use of -mvle requires -a32."));
1184#else
1185 as_fatal (_("%s unsupported"), "-a64");
1186#endif
1187 }
1188 else if (strcmp (arg, "32") == 0)
1189 ppc_obj64 = 0;
1190 else
1191 return 0;
1192 break;
1193
1194 case 'm':
1195 new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg);
1196 /* "raw" is only valid for the disassembler. */
1197 if (new_cpu != 0 && (new_cpu & PPC_OPCODE_RAW) == 0)
1198 {
1199 ppc_cpu = new_cpu;
1200 if (strcmp (arg, "vle") == 0)
1201 {
1202 if (set_target_endian && target_big_endian == 0)
1203 as_bad (_("the use of -mvle requires big endian."));
1204 if (ppc_obj64)
1205 as_bad (_("the use of -mvle requires -a32."));
1206 }
1207 }
1208
1209 else if (strcmp (arg, "no-vle") == 0)
1210 {
1211 sticky &= ~PPC_OPCODE_VLE;
1212
1213 new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke");
1214 new_cpu &= ~PPC_OPCODE_VLE;
1215
1216 ppc_cpu = new_cpu;
1217 }
1218
1219 else if (strcmp (arg, "regnames") == 0)
1220 reg_names_p = TRUE;
1221
1222 else if (strcmp (arg, "no-regnames") == 0)
1223 reg_names_p = FALSE;
1224
1225#ifdef OBJ_ELF
1226 /* -mrelocatable/-mrelocatable-lib -- warn about initializations
1227 that require relocation. */
1228 else if (strcmp (arg, "relocatable") == 0)
1229 {
1230 shlib = SHLIB_MRELOCATABLE;
1231 ppc_flags |= EF_PPC_RELOCATABLE;
1232 }
1233
1234 else if (strcmp (arg, "relocatable-lib") == 0)
1235 {
1236 shlib = SHLIB_MRELOCATABLE;
1237 ppc_flags |= EF_PPC_RELOCATABLE_LIB;
1238 }
1239
1240 /* -memb, set embedded bit. */
1241 else if (strcmp (arg, "emb") == 0)
1242 ppc_flags |= EF_PPC_EMB;
1243
1244 /* -mlittle/-mbig set the endianness. */
1245 else if (strcmp (arg, "little") == 0
1246 || strcmp (arg, "little-endian") == 0)
1247 {
1248 target_big_endian = 0;
1249 set_target_endian = 1;
1250 if (ppc_cpu & PPC_OPCODE_VLE)
1251 as_bad (_("the use of -mvle requires big endian."));
1252 }
1253
1254 else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0)
1255 {
1256 target_big_endian = 1;
1257 set_target_endian = 1;
1258 }
1259
1260 else if (strcmp (arg, "solaris") == 0)
1261 {
1262 msolaris = TRUE;
1263 ppc_comment_chars = ppc_solaris_comment_chars;
1264 }
1265
1266 else if (strcmp (arg, "no-solaris") == 0)
1267 {
1268 msolaris = FALSE;
1269 ppc_comment_chars = ppc_eabi_comment_chars;
1270 }
1271 else if (strcmp (arg, "spe2") == 0)
1272 {
1273 ppc_cpu |= PPC_OPCODE_SPE2;
1274 }
1275#endif
1276 else
1277 {
1278 as_bad (_("invalid switch -m%s"), arg);
1279 return 0;
1280 }
1281 break;
1282
1283#ifdef OBJ_ELF
1284 /* -V: SVR4 argument to print version ID. */
1285 case 'V':
1286 print_version_id ();
1287 break;
1288
1289 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
1290 should be emitted or not. FIXME: Not implemented. */
1291 case 'Q':
1292 break;
1293
1294 /* Solaris takes -s to specify that .stabs go in a .stabs section,
1295 rather than .stabs.excl, which is ignored by the linker.
1296 FIXME: Not implemented. */
1297 case 's':
1298 if (arg)
1299 return 0;
1300
1301 break;
1302#endif
1303
1304 case OPTION_NOPS:
1305 {
1306 char *end;
1307 nop_limit = strtoul (optarg, &end, 0);
1308 if (*end)
1309 as_bad (_("--nops needs a numeric argument"));
1310 }
1311 break;
1312
1313 case 0:
1314 break;
1315
1316 default:
1317 return 0;
1318 }
1319
1320 return 1;
1321}
1322
1323void
1324md_show_usage (FILE *stream)
1325{
1326 fprintf (stream, _("\
1327PowerPC options:\n\
1328-a32 generate ELF32/XCOFF32\n\
1329-a64 generate ELF64/XCOFF64\n\
1330-u ignored\n\
1331-mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n\
1332-mpwr generate code for POWER (RIOS1)\n\
1333-m601 generate code for PowerPC 601\n\
1334-mppc, -mppc32, -m603, -m604\n\
1335 generate code for PowerPC 603/604\n\
1336-m403 generate code for PowerPC 403\n\
1337-m405 generate code for PowerPC 405\n\
1338-m440 generate code for PowerPC 440\n\
1339-m464 generate code for PowerPC 464\n\
1340-m476 generate code for PowerPC 476\n\
1341-m7400, -m7410, -m7450, -m7455\n\
1342 generate code for PowerPC 7400/7410/7450/7455\n\
1343-m750cl, -mgekko, -mbroadway\n\
1344 generate code for PowerPC 750cl/Gekko/Broadway\n\
1345-m821, -m850, -m860 generate code for PowerPC 821/850/860\n"));
1346 fprintf (stream, _("\
1347-mppc64, -m620 generate code for PowerPC 620/625/630\n\
1348-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
1349-mbooke generate code for 32-bit PowerPC BookE\n\
1350-ma2 generate code for A2 architecture\n\
1351-mpower4, -mpwr4 generate code for Power4 architecture\n\
1352-mpower5, -mpwr5, -mpwr5x\n\
1353 generate code for Power5 architecture\n\
1354-mpower6, -mpwr6 generate code for Power6 architecture\n\
1355-mpower7, -mpwr7 generate code for Power7 architecture\n\
1356-mpower8, -mpwr8 generate code for Power8 architecture\n\
1357-mpower9, -mpwr9 generate code for Power9 architecture\n\
1358-mcell generate code for Cell Broadband Engine architecture\n\
1359-mcom generate code for Power/PowerPC common instructions\n\
1360-many generate code for any architecture (PWR/PWRX/PPC)\n"));
1361 fprintf (stream, _("\
1362-maltivec generate code for AltiVec\n\
1363-mvsx generate code for Vector-Scalar (VSX) instructions\n\
1364-me300 generate code for PowerPC e300 family\n\
1365-me500, -me500x2 generate code for Motorola e500 core complex\n\
1366-me500mc, generate code for Freescale e500mc core complex\n\
1367-me500mc64, generate code for Freescale e500mc64 core complex\n\
1368-me5500, generate code for Freescale e5500 core complex\n\
1369-me6500, generate code for Freescale e6500 core complex\n\
1370-mspe generate code for Motorola SPE instructions\n\
1371-mspe2 generate code for Freescale SPE2 instructions\n\
1372-mvle generate code for Freescale VLE instructions\n\
1373-mtitan generate code for AppliedMicro Titan core complex\n\
1374-mregnames Allow symbolic names for registers\n\
1375-mno-regnames Do not allow symbolic names for registers\n"));
1376#ifdef OBJ_ELF
1377 fprintf (stream, _("\
1378-mrelocatable support for GCC's -mrelocatble option\n\
1379-mrelocatable-lib support for GCC's -mrelocatble-lib option\n\
1380-memb set PPC_EMB bit in ELF flags\n\
1381-mlittle, -mlittle-endian, -le\n\
1382 generate code for a little endian machine\n\
1383-mbig, -mbig-endian, -be\n\
1384 generate code for a big endian machine\n\
1385-msolaris generate code for Solaris\n\
1386-mno-solaris do not generate code for Solaris\n\
1387-K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n\
1388-V print assembler version number\n\
1389-Qy, -Qn ignored\n"));
1390#endif
1391 fprintf (stream, _("\
1392-nops=count when aligning, more than COUNT nops uses a branch\n\
1393-ppc476-workaround warn if emitting data to code sections\n"));
1394}
1395\f
1396/* Set ppc_cpu if it is not already set. */
1397
1398static void
1399ppc_set_cpu (void)
1400{
1401 const char *default_os = TARGET_OS;
1402 const char *default_cpu = TARGET_CPU;
1403
1404 if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0)
1405 {
1406 if (ppc_obj64)
1407 if (target_big_endian)
1408 ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64;
1409 else
1410 /* The minimum supported cpu for 64-bit little-endian is power8. */
1411 ppc_cpu |= ppc_parse_cpu (ppc_cpu, &sticky, "power8");
1412 else if (strncmp (default_os, "aix", 3) == 0
1413 && default_os[3] >= '4' && default_os[3] <= '9')
1414 ppc_cpu |= PPC_OPCODE_COMMON;
1415 else if (strncmp (default_os, "aix3", 4) == 0)
1416 ppc_cpu |= PPC_OPCODE_POWER;
1417 else if (strcmp (default_cpu, "rs6000") == 0)
1418 ppc_cpu |= PPC_OPCODE_POWER;
1419 else if (strncmp (default_cpu, "powerpc", 7) == 0)
1420 ppc_cpu |= PPC_OPCODE_PPC;
1421 else
1422 as_fatal (_("unknown default cpu = %s, os = %s"),
1423 default_cpu, default_os);
1424 }
1425}
1426
1427/* Figure out the BFD architecture to use. This function and ppc_mach
1428 are called well before md_begin, when the output file is opened. */
1429
1430enum bfd_architecture
1431ppc_arch (void)
1432{
1433 const char *default_cpu = TARGET_CPU;
1434 ppc_set_cpu ();
1435
1436 if ((ppc_cpu & PPC_OPCODE_PPC) != 0)
1437 return bfd_arch_powerpc;
1438 if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
1439 return bfd_arch_powerpc;
1440 if ((ppc_cpu & PPC_OPCODE_POWER) != 0)
1441 return bfd_arch_rs6000;
1442 if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0)
1443 {
1444 if (strcmp (default_cpu, "rs6000") == 0)
1445 return bfd_arch_rs6000;
1446 else if (strncmp (default_cpu, "powerpc", 7) == 0)
1447 return bfd_arch_powerpc;
1448 }
1449
1450 as_fatal (_("neither Power nor PowerPC opcodes were selected."));
1451 return bfd_arch_unknown;
1452}
1453
1454unsigned long
1455ppc_mach (void)
1456{
1457 if (ppc_obj64)
1458 return bfd_mach_ppc64;
1459 else if (ppc_arch () == bfd_arch_rs6000)
1460 return bfd_mach_rs6k;
1461 else if (ppc_cpu & PPC_OPCODE_TITAN)
1462 return bfd_mach_ppc_titan;
1463 else if (ppc_cpu & PPC_OPCODE_VLE)
1464 return bfd_mach_ppc_vle;
1465 else
1466 return bfd_mach_ppc;
1467}
1468
1469extern const char*
1470ppc_target_format (void)
1471{
1472#ifdef OBJ_COFF
1473#ifdef TE_PE
1474 return target_big_endian ? "pe-powerpc" : "pe-powerpcle";
1475#elif TE_POWERMAC
1476 return "xcoff-powermac";
1477#else
1478# ifdef TE_AIX5
1479 return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000");
1480# else
1481 return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000");
1482# endif
1483#endif
1484#endif
1485#ifdef OBJ_ELF
1486# ifdef TE_FreeBSD
1487 return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd");
1488# elif defined (TE_VXWORKS)
1489 return "elf32-powerpc-vxworks";
1490# else
1491 return (target_big_endian
1492 ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc")
1493 : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle"));
1494# endif
1495#endif
1496}
1497
1498/* Validate one entry in powerpc_opcodes[] or vle_opcodes[].
1499 Return TRUE if there's a problem, otherwise FALSE. */
1500
1501static bfd_boolean
1502insn_validate (const struct powerpc_opcode *op)
1503{
1504 const unsigned char *o;
1505 uint64_t omask = op->mask;
1506
1507 /* The mask had better not trim off opcode bits. */
1508 if ((op->opcode & omask) != op->opcode)
1509 {
1510 as_bad (_("mask trims opcode bits for %s"), op->name);
1511 return TRUE;
1512 }
1513
1514 /* The operands must not overlap the opcode or each other. */
1515 for (o = op->operands; *o; ++o)
1516 {
1517 bfd_boolean optional = FALSE;
1518 if (*o >= num_powerpc_operands)
1519 {
1520 as_bad (_("operand index error for %s"), op->name);
1521 return TRUE;
1522 }
1523 else
1524 {
1525 uint64_t mask;
1526 const struct powerpc_operand *operand = &powerpc_operands[*o];
1527 if (operand->shift == (int) PPC_OPSHIFT_INV)
1528 {
1529 const char *errmsg;
1530 int64_t val;
1531
1532 errmsg = NULL;
1533 val = -1;
1534 if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
1535 val = -val;
1536 else if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
1537 val += 1;
1538 mask = (*operand->insert) (0, val, ppc_cpu, &errmsg);
1539 }
1540 else if (operand->shift >= 0)
1541 mask = operand->bitm << operand->shift;
1542 else
1543 mask = operand->bitm >> -operand->shift;
1544 if (omask & mask)
1545 {
1546 as_bad (_("operand %d overlap in %s"),
1547 (int) (o - op->operands), op->name);
1548 return TRUE;
1549 }
1550 omask |= mask;
1551 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
1552 optional = TRUE;
1553 else if (optional)
1554 {
1555 as_bad (_("non-optional operand %d follows optional operand in %s"),
1556 (int) (o - op->operands), op->name);
1557 return TRUE;
1558 }
1559 }
1560 }
1561 return FALSE;
1562}
1563
1564/* Insert opcodes and macros into hash tables. Called at startup and
1565 for .machine pseudo. */
1566
1567static void
1568ppc_setup_opcodes (void)
1569{
1570 const struct powerpc_opcode *op;
1571 const struct powerpc_opcode *op_end;
1572 const struct powerpc_macro *macro;
1573 const struct powerpc_macro *macro_end;
1574 bfd_boolean bad_insn = FALSE;
1575
1576 if (ppc_hash != NULL)
1577 hash_die (ppc_hash);
1578 if (ppc_macro_hash != NULL)
1579 hash_die (ppc_macro_hash);
1580
1581 /* Insert the opcodes into a hash table. */
1582 ppc_hash = hash_new ();
1583
1584 if (ENABLE_CHECKING)
1585 {
1586 unsigned int i;
1587
1588 /* An index into powerpc_operands is stored in struct fix
1589 fx_pcrel_adjust which is 8 bits wide. */
1590 gas_assert (num_powerpc_operands < 256);
1591
1592 /* Check operand masks. Code here and in the disassembler assumes
1593 all the 1's in the mask are contiguous. */
1594 for (i = 0; i < num_powerpc_operands; ++i)
1595 {
1596 uint64_t mask = powerpc_operands[i].bitm;
1597 uint64_t right_bit;
1598 unsigned int j;
1599
1600 right_bit = mask & -mask;
1601 mask += right_bit;
1602 right_bit = mask & -mask;
1603 if (mask != right_bit)
1604 {
1605 as_bad (_("powerpc_operands[%d].bitm invalid"), i);
1606 bad_insn = TRUE;
1607 }
1608 for (j = i + 1; j < num_powerpc_operands; ++j)
1609 if (memcmp (&powerpc_operands[i], &powerpc_operands[j],
1610 sizeof (powerpc_operands[0])) == 0)
1611 {
1612 as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
1613 j, i);
1614 bad_insn = TRUE;
1615 }
1616 }
1617 }
1618
1619 op_end = powerpc_opcodes + powerpc_num_opcodes;
1620 for (op = powerpc_opcodes; op < op_end; op++)
1621 {
1622 if (ENABLE_CHECKING)
1623 {
1624 unsigned int new_opcode = PPC_OP (op[0].opcode);
1625
1626#ifdef PRINT_OPCODE_TABLE
1627 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1628 op->name, (unsigned int) (op - powerpc_opcodes),
1629 new_opcode, (unsigned long long) op->opcode,
1630 (unsigned long long) op->mask, (unsigned long long) op->flags);
1631#endif
1632
1633 /* The major opcodes had better be sorted. Code in the disassembler
1634 assumes the insns are sorted according to major opcode. */
1635 if (op != powerpc_opcodes
1636 && new_opcode < PPC_OP (op[-1].opcode))
1637 {
1638 as_bad (_("major opcode is not sorted for %s"), op->name);
1639 bad_insn = TRUE;
1640 }
1641
1642 if ((op->flags & PPC_OPCODE_VLE) != 0)
1643 {
1644 as_bad (_("%s is enabled by vle flag"), op->name);
1645 bad_insn = TRUE;
1646 }
1647 if (PPC_OP (op->opcode) != 4
1648 && PPC_OP (op->opcode) != 31
1649 && (op->deprecated & PPC_OPCODE_VLE) == 0)
1650 {
1651 as_bad (_("%s not disabled by vle flag"), op->name);
1652 bad_insn = TRUE;
1653 }
1654 bad_insn |= insn_validate (op);
1655 }
1656
1657 if ((ppc_cpu & op->flags) != 0
1658 && !(ppc_cpu & op->deprecated))
1659 {
1660 const char *retval;
1661
1662 retval = hash_insert (ppc_hash, op->name, (void *) op);
1663 if (retval != NULL)
1664 {
1665 as_bad (_("duplicate instruction %s"),
1666 op->name);
1667 bad_insn = TRUE;
1668 }
1669 }
1670 }
1671
1672 if ((ppc_cpu & PPC_OPCODE_ANY) != 0)
1673 for (op = powerpc_opcodes; op < op_end; op++)
1674 hash_insert (ppc_hash, op->name, (void *) op);
1675
1676 op_end = vle_opcodes + vle_num_opcodes;
1677 for (op = vle_opcodes; op < op_end; op++)
1678 {
1679 if (ENABLE_CHECKING)
1680 {
1681 unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask));
1682
1683#ifdef PRINT_OPCODE_TABLE
1684 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1685 op->name, (unsigned int) (op - vle_opcodes),
1686 (unsigned int) new_seg, (unsigned long long) op->opcode,
1687 (unsigned long long) op->mask, (unsigned long long) op->flags);
1688#endif
1689
1690 /* The major opcodes had better be sorted. Code in the disassembler
1691 assumes the insns are sorted according to major opcode. */
1692 if (op != vle_opcodes
1693 && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask)))
1694 {
1695 as_bad (_("major opcode is not sorted for %s"), op->name);
1696 bad_insn = TRUE;
1697 }
1698
1699 bad_insn |= insn_validate (op);
1700 }
1701
1702 if ((ppc_cpu & op->flags) != 0
1703 && !(ppc_cpu & op->deprecated))
1704 {
1705 const char *retval;
1706
1707 retval = hash_insert (ppc_hash, op->name, (void *) op);
1708 if (retval != NULL)
1709 {
1710 as_bad (_("duplicate instruction %s"),
1711 op->name);
1712 bad_insn = TRUE;
1713 }
1714 }
1715 }
1716
1717 /* SPE2 instructions */
1718 if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2)
1719 {
1720 op_end = spe2_opcodes + spe2_num_opcodes;
1721 for (op = spe2_opcodes; op < op_end; op++)
1722 {
1723 if (ENABLE_CHECKING)
1724 {
1725 if (op != spe2_opcodes)
1726 {
1727 unsigned old_seg, new_seg;
1728
1729 old_seg = VLE_OP (op[-1].opcode, op[-1].mask);
1730 old_seg = VLE_OP_TO_SEG (old_seg);
1731 new_seg = VLE_OP (op[0].opcode, op[0].mask);
1732 new_seg = VLE_OP_TO_SEG (new_seg);
1733
1734 /* The major opcodes had better be sorted. Code in the
1735 disassembler assumes the insns are sorted according to
1736 major opcode. */
1737 if (new_seg < old_seg)
1738 {
1739 as_bad (_("major opcode is not sorted for %s"), op->name);
1740 bad_insn = TRUE;
1741 }
1742 }
1743
1744 bad_insn |= insn_validate (op);
1745 }
1746
1747 if ((ppc_cpu & op->flags) != 0 && !(ppc_cpu & op->deprecated))
1748 {
1749 const char *retval;
1750
1751 retval = hash_insert (ppc_hash, op->name, (void *) op);
1752 if (retval != NULL)
1753 {
1754 as_bad (_("duplicate instruction %s"),
1755 op->name);
1756 bad_insn = TRUE;
1757 }
1758 }
1759 }
1760
1761 for (op = spe2_opcodes; op < op_end; op++)
1762 hash_insert (ppc_hash, op->name, (void *) op);
1763 }
1764
1765 /* Insert the macros into a hash table. */
1766 ppc_macro_hash = hash_new ();
1767
1768 macro_end = powerpc_macros + powerpc_num_macros;
1769 for (macro = powerpc_macros; macro < macro_end; macro++)
1770 {
1771 if ((macro->flags & ppc_cpu) != 0 || (ppc_cpu & PPC_OPCODE_ANY) != 0)
1772 {
1773 const char *retval;
1774
1775 retval = hash_insert (ppc_macro_hash, macro->name, (void *) macro);
1776 if (retval != (const char *) NULL)
1777 {
1778 as_bad (_("duplicate macro %s"), macro->name);
1779 bad_insn = TRUE;
1780 }
1781 }
1782 }
1783
1784 if (bad_insn)
1785 abort ();
1786}
1787
1788/* This function is called when the assembler starts up. It is called
1789 after the options have been parsed and the output file has been
1790 opened. */
1791
1792void
1793md_begin (void)
1794{
1795 ppc_set_cpu ();
1796
1797 ppc_cie_data_alignment = ppc_obj64 ? -8 : -4;
1798 ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4;
1799
1800#ifdef OBJ_ELF
1801 /* Set the ELF flags if desired. */
1802 if (ppc_flags && !msolaris)
1803 bfd_set_private_flags (stdoutput, ppc_flags);
1804#endif
1805
1806 ppc_setup_opcodes ();
1807
1808 /* Tell the main code what the endianness is if it is not overridden
1809 by the user. */
1810 if (!set_target_endian)
1811 {
1812 set_target_endian = 1;
1813 target_big_endian = PPC_BIG_ENDIAN;
1814 }
1815
1816#ifdef OBJ_XCOFF
1817 ppc_coff_debug_section = coff_section_from_bfd_index (stdoutput, N_DEBUG);
1818
1819 /* Create dummy symbols to serve as initial csects. This forces the
1820 text csects to precede the data csects. These symbols will not
1821 be output. */
1822 ppc_text_csects = symbol_make ("dummy\001");
1823 symbol_get_tc (ppc_text_csects)->within = ppc_text_csects;
1824 ppc_data_csects = symbol_make ("dummy\001");
1825 symbol_get_tc (ppc_data_csects)->within = ppc_data_csects;
1826#endif
1827
1828#ifdef TE_PE
1829
1830 ppc_current_section = text_section;
1831 ppc_previous_section = 0;
1832
1833#endif
1834}
1835
1836void
1837ppc_cleanup (void)
1838{
1839#ifdef OBJ_ELF
1840 if (ppc_apuinfo_list == NULL)
1841 return;
1842
1843 /* Ok, so write the section info out. We have this layout:
1844
1845 byte data what
1846 ---- ---- ----
1847 0 8 length of "APUinfo\0"
1848 4 (n*4) number of APU's (4 bytes each)
1849 8 2 note type 2
1850 12 "APUinfo\0" name
1851 20 APU#1 first APU's info
1852 24 APU#2 second APU's info
1853 ... ...
1854 */
1855 {
1856 char *p;
1857 asection *seg = now_seg;
1858 subsegT subseg = now_subseg;
1859 asection *apuinfo_secp = (asection *) NULL;
1860 unsigned int i;
1861
1862 /* Create the .PPC.EMB.apuinfo section. */
1863 apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0);
1864 bfd_set_section_flags (stdoutput,
1865 apuinfo_secp,
1866 SEC_HAS_CONTENTS | SEC_READONLY);
1867
1868 p = frag_more (4);
1869 md_number_to_chars (p, (valueT) 8, 4);
1870
1871 p = frag_more (4);
1872 md_number_to_chars (p, (valueT) ppc_apuinfo_num * 4, 4);
1873
1874 p = frag_more (4);
1875 md_number_to_chars (p, (valueT) 2, 4);
1876
1877 p = frag_more (8);
1878 strcpy (p, APUINFO_LABEL);
1879
1880 for (i = 0; i < ppc_apuinfo_num; i++)
1881 {
1882 p = frag_more (4);
1883 md_number_to_chars (p, (valueT) ppc_apuinfo_list[i], 4);
1884 }
1885
1886 frag_align (2, 0, 0);
1887
1888 /* We probably can't restore the current segment, for there likely
1889 isn't one yet... */
1890 if (seg && subseg)
1891 subseg_set (seg, subseg);
1892 }
1893#endif
1894}
1895
1896/* Insert an operand value into an instruction. */
1897
1898static uint64_t
1899ppc_insert_operand (uint64_t insn,
1900 const struct powerpc_operand *operand,
1901 int64_t val,
1902 ppc_cpu_t cpu,
1903 const char *file,
1904 unsigned int line)
1905{
1906 int64_t min, max, right;
1907
1908 max = operand->bitm;
1909 right = max & -max;
1910 min = 0;
1911
1912 if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0)
1913 {
1914 /* Extend the allowed range for addis to [-32768, 65535].
1915 Similarly for cmpli and some VLE high part insns. For 64-bit
1916 it would be good to disable this for signed fields since the
1917 value is sign extended into the high 32 bits of the register.
1918 If the value is, say, an address, then we might care about
1919 the high bits. However, gcc as of 2014-06 uses unsigned
1920 values when loading the high part of 64-bit constants using
1921 lis. */
1922 min = ~(max >> 1) & -right;
1923 }
1924 else if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
1925 {
1926 max = (max >> 1) & -right;
1927 min = ~max & -right;
1928 }
1929
1930 if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
1931 max++;
1932
1933 if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
1934 {
1935 int64_t tmp = min;
1936 min = -max;
1937 max = -tmp;
1938 }
1939
1940 if (min <= max)
1941 {
1942 /* Some people write constants with the sign extension done by
1943 hand but only up to 32 bits. This shouldn't really be valid,
1944 but, to permit this code to assemble on a 64-bit host, we
1945 sign extend the 32-bit value to 64 bits if so doing makes the
1946 value valid. */
1947 if (val > max
1948 && (val - (1LL << 32)) >= min
1949 && (val - (1LL << 32)) <= max
1950 && ((val - (1LL << 32)) & (right - 1)) == 0)
1951 val = val - (1LL << 32);
1952
1953 /* Similarly, people write expressions like ~(1<<15), and expect
1954 this to be OK for a 32-bit unsigned value. */
1955 else if (val < min
1956 && (val + (1LL << 32)) >= min
1957 && (val + (1LL << 32)) <= max
1958 && ((val + (1LL << 32)) & (right - 1)) == 0)
1959 val = val + (1LL << 32);
1960
1961 else if (val < min
1962 || val > max
1963 || (val & (right - 1)) != 0)
1964 as_bad_value_out_of_range (_("operand"), val, min, max, file, line);
1965 }
1966
1967 if (operand->insert)
1968 {
1969 const char *errmsg;
1970
1971 errmsg = NULL;
1972 insn = (*operand->insert) (insn, val, cpu, &errmsg);
1973 if (errmsg != (const char *) NULL)
1974 as_bad_where (file, line, "%s", errmsg);
1975 }
1976 else if (operand->shift >= 0)
1977 insn |= (val & operand->bitm) << operand->shift;
1978 else
1979 insn |= (val & operand->bitm) >> -operand->shift;
1980
1981 return insn;
1982}
1983
1984\f
1985#ifdef OBJ_ELF
1986/* Parse @got, etc. and return the desired relocation. */
1987static bfd_reloc_code_real_type
1988ppc_elf_suffix (char **str_p, expressionS *exp_p)
1989{
1990 struct map_bfd {
1991 const char *string;
1992 unsigned int length : 8;
1993 unsigned int valid32 : 1;
1994 unsigned int valid64 : 1;
1995 unsigned int reloc;
1996 };
1997
1998 char ident[20];
1999 char *str = *str_p;
2000 char *str2;
2001 int ch;
2002 int len;
2003 const struct map_bfd *ptr;
2004
2005#define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc }
2006#define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc }
2007#define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc }
2008
2009 static const struct map_bfd mapping[] = {
2010 MAP ("l", BFD_RELOC_LO16),
2011 MAP ("h", BFD_RELOC_HI16),
2012 MAP ("ha", BFD_RELOC_HI16_S),
2013 MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN),
2014 MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN),
2015 MAP ("got", BFD_RELOC_16_GOTOFF),
2016 MAP ("got@l", BFD_RELOC_LO16_GOTOFF),
2017 MAP ("got@h", BFD_RELOC_HI16_GOTOFF),
2018 MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF),
2019 MAP ("plt@l", BFD_RELOC_LO16_PLTOFF),
2020 MAP ("plt@h", BFD_RELOC_HI16_PLTOFF),
2021 MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF),
2022 MAP ("copy", BFD_RELOC_PPC_COPY),
2023 MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT),
2024 MAP ("sectoff", BFD_RELOC_16_BASEREL),
2025 MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL),
2026 MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL),
2027 MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL),
2028 MAP ("tls", BFD_RELOC_PPC_TLS),
2029 MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD),
2030 MAP ("dtprel", BFD_RELOC_PPC_DTPREL),
2031 MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO),
2032 MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI),
2033 MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA),
2034 MAP ("tprel", BFD_RELOC_PPC_TPREL),
2035 MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO),
2036 MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI),
2037 MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA),
2038 MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16),
2039 MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO),
2040 MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI),
2041 MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA),
2042 MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16),
2043 MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO),
2044 MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI),
2045 MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA),
2046 MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16),
2047 MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO),
2048 MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI),
2049 MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA),
2050 MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16),
2051 MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO),
2052 MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI),
2053 MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA),
2054 MAP32 ("fixup", BFD_RELOC_CTOR),
2055 MAP32 ("plt", BFD_RELOC_24_PLT_PCREL),
2056 MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL),
2057 MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC),
2058 MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC),
2059 MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL),
2060 MAP32 ("sdarel", BFD_RELOC_GPREL16),
2061 MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A),
2062 MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A),
2063 MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A),
2064 MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32),
2065 MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16),
2066 MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO),
2067 MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI),
2068 MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA),
2069 MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16),
2070 MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL),
2071 MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16),
2072 MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21),
2073 MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO),
2074 MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF),
2075 MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16),
2076 MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO),
2077 MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI),
2078 MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA),
2079 MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD),
2080 MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA),
2081 MAP32 ("xgot", BFD_RELOC_PPC_TOC16),
2082 MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH),
2083 MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA),
2084 MAP64 ("higher", BFD_RELOC_PPC64_HIGHER),
2085 MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S),
2086 MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST),
2087 MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S),
2088 MAP64 ("tocbase", BFD_RELOC_PPC64_TOC),
2089 MAP64 ("toc", BFD_RELOC_PPC_TOC16),
2090 MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO),
2091 MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI),
2092 MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA),
2093 MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH),
2094 MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA),
2095 MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER),
2096 MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA),
2097 MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST),
2098 MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA),
2099 MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL),
2100 MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH),
2101 MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA),
2102 MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER),
2103 MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA),
2104 MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST),
2105 MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA),
2106 MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC),
2107 { (char *) 0, 0, 0, 0, BFD_RELOC_NONE }
2108 };
2109
2110 if (*str++ != '@')
2111 return BFD_RELOC_NONE;
2112
2113 for (ch = *str, str2 = ident;
2114 (str2 < ident + sizeof (ident) - 1
2115 && (ISALNUM (ch) || ch == '@'));
2116 ch = *++str)
2117 {
2118 *str2++ = TOLOWER (ch);
2119 }
2120
2121 *str2 = '\0';
2122 len = str2 - ident;
2123
2124 ch = ident[0];
2125 for (ptr = &mapping[0]; ptr->length > 0; ptr++)
2126 if (ch == ptr->string[0]
2127 && len == ptr->length
2128 && memcmp (ident, ptr->string, ptr->length) == 0
2129 && (ppc_obj64 ? ptr->valid64 : ptr->valid32))
2130 {
2131 int reloc = ptr->reloc;
2132
2133 if (!ppc_obj64 && exp_p->X_add_number != 0)
2134 {
2135 switch (reloc)
2136 {
2137 case BFD_RELOC_16_GOTOFF:
2138 case BFD_RELOC_LO16_GOTOFF:
2139 case BFD_RELOC_HI16_GOTOFF:
2140 case BFD_RELOC_HI16_S_GOTOFF:
2141 as_warn (_("identifier+constant@got means "
2142 "identifier@got+constant"));
2143 break;
2144
2145 case BFD_RELOC_PPC_GOT_TLSGD16:
2146 case BFD_RELOC_PPC_GOT_TLSGD16_LO:
2147 case BFD_RELOC_PPC_GOT_TLSGD16_HI:
2148 case BFD_RELOC_PPC_GOT_TLSGD16_HA:
2149 case BFD_RELOC_PPC_GOT_TLSLD16:
2150 case BFD_RELOC_PPC_GOT_TLSLD16_LO:
2151 case BFD_RELOC_PPC_GOT_TLSLD16_HI:
2152 case BFD_RELOC_PPC_GOT_TLSLD16_HA:
2153 case BFD_RELOC_PPC_GOT_DTPREL16:
2154 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
2155 case BFD_RELOC_PPC_GOT_DTPREL16_HI:
2156 case BFD_RELOC_PPC_GOT_DTPREL16_HA:
2157 case BFD_RELOC_PPC_GOT_TPREL16:
2158 case BFD_RELOC_PPC_GOT_TPREL16_LO:
2159 case BFD_RELOC_PPC_GOT_TPREL16_HI:
2160 case BFD_RELOC_PPC_GOT_TPREL16_HA:
2161 as_bad (_("symbol+offset not supported for got tls"));
2162 break;
2163 }
2164 }
2165
2166 /* Now check for identifier@suffix+constant. */
2167 if (*str == '-' || *str == '+')
2168 {
2169 char *orig_line = input_line_pointer;
2170 expressionS new_exp;
2171
2172 input_line_pointer = str;
2173 expression (&new_exp);
2174 if (new_exp.X_op == O_constant)
2175 {
2176 exp_p->X_add_number += new_exp.X_add_number;
2177 str = input_line_pointer;
2178 }
2179
2180 if (&input_line_pointer != str_p)
2181 input_line_pointer = orig_line;
2182 }
2183 *str_p = str;
2184
2185 if (reloc == (int) BFD_RELOC_PPC64_TOC
2186 && exp_p->X_op == O_symbol
2187 && strcmp (S_GET_NAME (exp_p->X_add_symbol), ".TOC.") == 0)
2188 {
2189 /* Change the symbol so that the dummy .TOC. symbol can be
2190 omitted from the object file. */
2191 exp_p->X_add_symbol = &abs_symbol;
2192 }
2193
2194 return (bfd_reloc_code_real_type) reloc;
2195 }
2196
2197 return BFD_RELOC_NONE;
2198}
2199
2200/* Support @got, etc. on constants emitted via .short, .int etc. */
2201
2202bfd_reloc_code_real_type
2203ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes)
2204{
2205 expression (exp);
2206 if (nbytes >= 2 && *input_line_pointer == '@')
2207 return ppc_elf_suffix (&input_line_pointer, exp);
2208 return BFD_RELOC_NONE;
2209}
2210
2211/* Warn when emitting data to code sections, unless we are emitting
2212 a relocation that ld --ppc476-workaround uses to recognise data
2213 *and* there was an unconditional branch prior to the data. */
2214
2215void
2216ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED,
2217 unsigned int nbytes, fixS *fix)
2218{
2219 if (warn_476
2220 && (now_seg->flags & SEC_CODE) != 0
2221 && (nbytes != 4
2222 || fix == NULL
2223 || !(fix->fx_r_type == BFD_RELOC_32
2224 || fix->fx_r_type == BFD_RELOC_CTOR
2225 || fix->fx_r_type == BFD_RELOC_32_PCREL)
2226 || !(last_seg == now_seg && last_subseg == now_subseg)
2227 || !((last_insn & (0x3f << 26)) == (18u << 26)
2228 || ((last_insn & (0x3f << 26)) == (16u << 26)
2229 && (last_insn & (0x14 << 21)) == (0x14 << 21))
2230 || ((last_insn & (0x3f << 26)) == (19u << 26)
2231 && (last_insn & (0x3ff << 1)) == (16u << 1)
2232 && (last_insn & (0x14 << 21)) == (0x14 << 21)))))
2233 {
2234 /* Flag that we've warned. */
2235 if (fix != NULL)
2236 fix->fx_tcbit = 1;
2237
2238 as_warn (_("data in executable section"));
2239 }
2240}
2241
2242/* Solaris pseduo op to change to the .rodata section. */
2243static void
2244ppc_elf_rdata (int xxx)
2245{
2246 char *save_line = input_line_pointer;
2247 static char section[] = ".rodata\n";
2248
2249 /* Just pretend this is .section .rodata */
2250 input_line_pointer = section;
2251 obj_elf_section (xxx);
2252
2253 input_line_pointer = save_line;
2254}
2255
2256/* Pseudo op to make file scope bss items. */
2257static void
2258ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED)
2259{
2260 char *name;
2261 char c;
2262 char *p;
2263 offsetT size;
2264 symbolS *symbolP;
2265 offsetT align;
2266 segT old_sec;
2267 int old_subsec;
2268 char *pfrag;
2269 int align2;
2270
2271 c = get_symbol_name (&name);
2272
2273 /* Just after name is now '\0'. */
2274 p = input_line_pointer;
2275 *p = c;
2276 SKIP_WHITESPACE_AFTER_NAME ();
2277 if (*input_line_pointer != ',')
2278 {
2279 as_bad (_("expected comma after symbol-name: rest of line ignored."));
2280 ignore_rest_of_line ();
2281 return;
2282 }
2283
2284 input_line_pointer++; /* skip ',' */
2285 if ((size = get_absolute_expression ()) < 0)
2286 {
2287 as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size);
2288 ignore_rest_of_line ();
2289 return;
2290 }
2291
2292 /* The third argument to .lcomm is the alignment. */
2293 if (*input_line_pointer != ',')
2294 align = 8;
2295 else
2296 {
2297 ++input_line_pointer;
2298 align = get_absolute_expression ();
2299 if (align <= 0)
2300 {
2301 as_warn (_("ignoring bad alignment"));
2302 align = 8;
2303 }
2304 }
2305
2306 *p = 0;
2307 symbolP = symbol_find_or_make (name);
2308 *p = c;
2309
2310 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
2311 {
2312 as_bad (_("ignoring attempt to re-define symbol `%s'."),
2313 S_GET_NAME (symbolP));
2314 ignore_rest_of_line ();
2315 return;
2316 }
2317
2318 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
2319 {
2320 as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."),
2321 S_GET_NAME (symbolP),
2322 (long) S_GET_VALUE (symbolP),
2323 (long) size);
2324
2325 ignore_rest_of_line ();
2326 return;
2327 }
2328
2329 /* Allocate_bss. */
2330 old_sec = now_seg;
2331 old_subsec = now_subseg;
2332 if (align)
2333 {
2334 /* Convert to a power of 2 alignment. */
2335 for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2);
2336 if (align != 1)
2337 {
2338 as_bad (_("common alignment not a power of 2"));
2339 ignore_rest_of_line ();
2340 return;
2341 }
2342 }
2343 else
2344 align2 = 0;
2345
2346 record_alignment (bss_section, align2);
2347 subseg_set (bss_section, 1);
2348 if (align2)
2349 frag_align (align2, 0, 0);
2350 if (S_GET_SEGMENT (symbolP) == bss_section)
2351 symbol_get_frag (symbolP)->fr_symbol = 0;
2352 symbol_set_frag (symbolP, frag_now);
2353 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
2354 (char *) 0);
2355 *pfrag = 0;
2356 S_SET_SIZE (symbolP, size);
2357 S_SET_SEGMENT (symbolP, bss_section);
2358 subseg_set (old_sec, old_subsec);
2359 demand_empty_rest_of_line ();
2360}
2361
2362/* Pseudo op to set symbol local entry point. */
2363static void
2364ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED)
2365{
2366 char *name;
2367 char c = get_symbol_name (&name);
2368 char *p;
2369 expressionS exp;
2370 symbolS *sym;
2371 asymbol *bfdsym;
2372 elf_symbol_type *elfsym;
2373
2374 p = input_line_pointer;
2375 *p = c;
2376 SKIP_WHITESPACE_AFTER_NAME ();
2377 if (*input_line_pointer != ',')
2378 {
2379 *p = 0;
2380 as_bad (_("expected comma after name `%s' in .localentry directive"),
2381 name);
2382 *p = c;
2383 ignore_rest_of_line ();
2384 return;
2385 }
2386 input_line_pointer++;
2387 expression (&exp);
2388 if (exp.X_op == O_absent)
2389 {
2390 as_bad (_("missing expression in .localentry directive"));
2391 exp.X_op = O_constant;
2392 exp.X_add_number = 0;
2393 }
2394 *p = 0;
2395 sym = symbol_find_or_make (name);
2396 *p = c;
2397
2398 if (resolve_expression (&exp)
2399 && exp.X_op == O_constant)
2400 {
2401 unsigned int encoded, ok;
2402
2403 ok = 1;
2404 if (exp.X_add_number == 1 || exp.X_add_number == 7)
2405 encoded = exp.X_add_number << STO_PPC64_LOCAL_BIT;
2406 else
2407 {
2408 encoded = PPC64_SET_LOCAL_ENTRY_OFFSET (exp.X_add_number);
2409 if (exp.X_add_number != (offsetT) PPC64_LOCAL_ENTRY_OFFSET (encoded))
2410 {
2411 as_bad (_(".localentry expression for `%s' "
2412 "is not a valid power of 2"), S_GET_NAME (sym));
2413 ok = 0;
2414 }
2415 }
2416 if (ok)
2417 {
2418 bfdsym = symbol_get_bfdsym (sym);
2419 elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
2420 gas_assert (elfsym);
2421 elfsym->internal_elf_sym.st_other &= ~STO_PPC64_LOCAL_MASK;
2422 elfsym->internal_elf_sym.st_other |= encoded;
2423 if (ppc_abiversion == 0)
2424 ppc_abiversion = 2;
2425 }
2426 }
2427 else
2428 as_bad (_(".localentry expression for `%s' "
2429 "does not evaluate to a constant"), S_GET_NAME (sym));
2430
2431 demand_empty_rest_of_line ();
2432}
2433
2434/* Pseudo op to set ABI version. */
2435static void
2436ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED)
2437{
2438 expressionS exp;
2439
2440 expression (&exp);
2441 if (exp.X_op == O_absent)
2442 {
2443 as_bad (_("missing expression in .abiversion directive"));
2444 exp.X_op = O_constant;
2445 exp.X_add_number = 0;
2446 }
2447
2448 if (resolve_expression (&exp)
2449 && exp.X_op == O_constant)
2450 ppc_abiversion = exp.X_add_number;
2451 else
2452 as_bad (_(".abiversion expression does not evaluate to a constant"));
2453 demand_empty_rest_of_line ();
2454}
2455
2456/* Parse a .gnu_attribute directive. */
2457static void
2458ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED)
2459{
2460 int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU);
2461
2462 /* Check validity of defined powerpc tags. */
2463 if (tag == Tag_GNU_Power_ABI_FP
2464 || tag == Tag_GNU_Power_ABI_Vector
2465 || tag == Tag_GNU_Power_ABI_Struct_Return)
2466 {
2467 unsigned int val;
2468
2469 val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag);
2470
2471 if ((tag == Tag_GNU_Power_ABI_FP && val > 15)
2472 || (tag == Tag_GNU_Power_ABI_Vector && val > 3)
2473 || (tag == Tag_GNU_Power_ABI_Struct_Return && val > 2))
2474 as_warn (_("unknown .gnu_attribute value"));
2475 }
2476}
2477
2478/* Set ABI version in output file. */
2479void
2480ppc_elf_end (void)
2481{
2482 if (ppc_obj64 && ppc_abiversion != 0)
2483 {
2484 elf_elfheader (stdoutput)->e_flags &= ~EF_PPC64_ABI;
2485 elf_elfheader (stdoutput)->e_flags |= ppc_abiversion & EF_PPC64_ABI;
2486 }
2487}
2488
2489/* Validate any relocations emitted for -mrelocatable, possibly adding
2490 fixups for word relocations in writable segments, so we can adjust
2491 them at runtime. */
2492static void
2493ppc_elf_validate_fix (fixS *fixp, segT seg)
2494{
2495 if (fixp->fx_done || fixp->fx_pcrel)
2496 return;
2497
2498 switch (shlib)
2499 {
2500 case SHLIB_NONE:
2501 case SHLIB_PIC:
2502 return;
2503
2504 case SHLIB_MRELOCATABLE:
2505 if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF
2506 && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF
2507 && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF
2508 && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF
2509 && fixp->fx_r_type != BFD_RELOC_16_BASEREL
2510 && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL
2511 && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL
2512 && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL
2513 && (seg->flags & SEC_LOAD) != 0
2514 && strcmp (segment_name (seg), ".got2") != 0
2515 && strcmp (segment_name (seg), ".dtors") != 0
2516 && strcmp (segment_name (seg), ".ctors") != 0
2517 && strcmp (segment_name (seg), ".fixup") != 0
2518 && strcmp (segment_name (seg), ".gcc_except_table") != 0
2519 && strcmp (segment_name (seg), ".eh_frame") != 0
2520 && strcmp (segment_name (seg), ".ex_shared") != 0)
2521 {
2522 if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0
2523 || fixp->fx_r_type != BFD_RELOC_CTOR)
2524 {
2525 as_bad_where (fixp->fx_file, fixp->fx_line,
2526 _("relocation cannot be done when using -mrelocatable"));
2527 }
2528 }
2529 return;
2530 }
2531}
2532
2533/* Prevent elf_frob_file_before_adjust removing a weak undefined
2534 function descriptor sym if the corresponding code sym is used. */
2535
2536void
2537ppc_frob_file_before_adjust (void)
2538{
2539 symbolS *symp;
2540 asection *toc;
2541
2542 if (!ppc_obj64)
2543 return;
2544
2545 for (symp = symbol_rootP; symp; symp = symbol_next (symp))
2546 {
2547 const char *name;
2548 char *dotname;
2549 symbolS *dotsym;
2550
2551 name = S_GET_NAME (symp);
2552 if (name[0] == '.')
2553 continue;
2554
2555 if (! S_IS_WEAK (symp)
2556 || S_IS_DEFINED (symp))
2557 continue;
2558
2559 dotname = concat (".", name, (char *) NULL);
2560 dotsym = symbol_find_noref (dotname, 1);
2561 free (dotname);
2562 if (dotsym != NULL && (symbol_used_p (dotsym)
2563 || symbol_used_in_reloc_p (dotsym)))
2564 symbol_mark_used (symp);
2565
2566 }
2567
2568 toc = bfd_get_section_by_name (stdoutput, ".toc");
2569 if (toc != NULL
2570 && toc_reloc_types != has_large_toc_reloc
2571 && bfd_section_size (stdoutput, toc) > 0x10000)
2572 as_warn (_("TOC section size exceeds 64k"));
2573}
2574
2575/* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be
2576 emitted. Other uses of .TOC. will cause the symbol to be marked
2577 with BSF_KEEP in md_apply_fix. */
2578
2579void
2580ppc_elf_adjust_symtab (void)
2581{
2582 if (ppc_obj64)
2583 {
2584 symbolS *symp;
2585 symp = symbol_find (".TOC.");
2586 if (symp != NULL)
2587 {
2588 asymbol *bsym = symbol_get_bfdsym (symp);
2589 if ((bsym->flags & BSF_KEEP) == 0)
2590 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2591 }
2592 }
2593}
2594#endif /* OBJ_ELF */
2595\f
2596#ifdef TE_PE
2597
2598/*
2599 * Summary of parse_toc_entry.
2600 *
2601 * in: Input_line_pointer points to the '[' in one of:
2602 *
2603 * [toc] [tocv] [toc32] [toc64]
2604 *
2605 * Anything else is an error of one kind or another.
2606 *
2607 * out:
2608 * return value: success or failure
2609 * toc_kind: kind of toc reference
2610 * input_line_pointer:
2611 * success: first char after the ']'
2612 * failure: unchanged
2613 *
2614 * settings:
2615 *
2616 * [toc] - rv == success, toc_kind = default_toc
2617 * [tocv] - rv == success, toc_kind = data_in_toc
2618 * [toc32] - rv == success, toc_kind = must_be_32
2619 * [toc64] - rv == success, toc_kind = must_be_64
2620 *
2621 */
2622
2623enum toc_size_qualifier
2624{
2625 default_toc, /* The toc cell constructed should be the system default size */
2626 data_in_toc, /* This is a direct reference to a toc cell */
2627 must_be_32, /* The toc cell constructed must be 32 bits wide */
2628 must_be_64 /* The toc cell constructed must be 64 bits wide */
2629};
2630
2631static int
2632parse_toc_entry (enum toc_size_qualifier *toc_kind)
2633{
2634 char *start;
2635 char *toc_spec;
2636 char c;
2637 enum toc_size_qualifier t;
2638
2639 /* Save the input_line_pointer. */
2640 start = input_line_pointer;
2641
2642 /* Skip over the '[' , and whitespace. */
2643 ++input_line_pointer;
2644 SKIP_WHITESPACE ();
2645
2646 /* Find the spelling of the operand. */
2647 c = get_symbol_name (&toc_spec);
2648
2649 if (strcmp (toc_spec, "toc") == 0)
2650 {
2651 t = default_toc;
2652 }
2653 else if (strcmp (toc_spec, "tocv") == 0)
2654 {
2655 t = data_in_toc;
2656 }
2657 else if (strcmp (toc_spec, "toc32") == 0)
2658 {
2659 t = must_be_32;
2660 }
2661 else if (strcmp (toc_spec, "toc64") == 0)
2662 {
2663 t = must_be_64;
2664 }
2665 else
2666 {
2667 as_bad (_("syntax error: invalid toc specifier `%s'"), toc_spec);
2668 *input_line_pointer = c;
2669 input_line_pointer = start;
2670 return 0;
2671 }
2672
2673 /* Now find the ']'. */
2674 *input_line_pointer = c;
2675
2676 SKIP_WHITESPACE_AFTER_NAME (); /* leading whitespace could be there. */
2677 c = *input_line_pointer++; /* input_line_pointer->past char in c. */
2678
2679 if (c != ']')
2680 {
2681 as_bad (_("syntax error: expected `]', found `%c'"), c);
2682 input_line_pointer = start;
2683 return 0;
2684 }
2685
2686 *toc_kind = t;
2687 return 1;
2688}
2689#endif
2690
2691#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
2692/* See whether a symbol is in the TOC section. */
2693
2694static int
2695ppc_is_toc_sym (symbolS *sym)
2696{
2697#ifdef OBJ_XCOFF
2698 return (symbol_get_tc (sym)->symbol_class == XMC_TC
2699 || symbol_get_tc (sym)->symbol_class == XMC_TC0);
2700#endif
2701#ifdef OBJ_ELF
2702 const char *sname = segment_name (S_GET_SEGMENT (sym));
2703 if (ppc_obj64)
2704 return strcmp (sname, ".toc") == 0;
2705 else
2706 return strcmp (sname, ".got") == 0;
2707#endif
2708}
2709#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
2710\f
2711
2712#ifdef OBJ_ELF
2713#define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff))
2714static void
2715ppc_apuinfo_section_add (unsigned int apu, unsigned int version)
2716{
2717 unsigned int i;
2718
2719 /* Check we don't already exist. */
2720 for (i = 0; i < ppc_apuinfo_num; i++)
2721 if (ppc_apuinfo_list[i] == APUID (apu, version))
2722 return;
2723
2724 if (ppc_apuinfo_num == ppc_apuinfo_num_alloc)
2725 {
2726 if (ppc_apuinfo_num_alloc == 0)
2727 {
2728 ppc_apuinfo_num_alloc = 4;
2729 ppc_apuinfo_list = XNEWVEC (unsigned long, ppc_apuinfo_num_alloc);
2730 }
2731 else
2732 {
2733 ppc_apuinfo_num_alloc += 4;
2734 ppc_apuinfo_list = XRESIZEVEC (unsigned long, ppc_apuinfo_list,
2735 ppc_apuinfo_num_alloc);
2736 }
2737 }
2738 ppc_apuinfo_list[ppc_apuinfo_num++] = APUID (apu, version);
2739}
2740#undef APUID
2741#endif
2742\f
2743
2744/* We need to keep a list of fixups. We can't simply generate them as
2745 we go, because that would require us to first create the frag, and
2746 that would screw up references to ``.''. */
2747
2748struct ppc_fixup
2749{
2750 expressionS exp;
2751 int opindex;
2752 bfd_reloc_code_real_type reloc;
2753};
2754
2755#define MAX_INSN_FIXUPS (5)
2756
2757/* Return the field size operated on by RELOC, and whether it is
2758 pc-relative in PC_RELATIVE. */
2759
2760static unsigned int
2761fixup_size (bfd_reloc_code_real_type reloc, bfd_boolean *pc_relative)
2762{
2763 unsigned int size = 0;
2764 bfd_boolean pcrel = FALSE;
2765
2766 switch (reloc)
2767 {
2768 /* This switch statement must handle all BFD_RELOC values
2769 possible in instruction fixups. As is, it handles all
2770 BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c,
2771 bfd/coff-ppc, bfd/coff-rs6000.c and bfd/coff64-rs6000.c.
2772 Overkill since data and marker relocs need not be handled
2773 here, but this way we can be sure a needed fixup reloc isn't
2774 accidentally omitted. */
2775 case BFD_RELOC_PPC_EMB_MRKREF:
2776 case BFD_RELOC_VTABLE_ENTRY:
2777 case BFD_RELOC_VTABLE_INHERIT:
2778 break;
2779
2780 case BFD_RELOC_8:
2781 size = 1;
2782 break;
2783
2784 case BFD_RELOC_16:
2785 case BFD_RELOC_16_BASEREL:
2786 case BFD_RELOC_16_GOTOFF:
2787 case BFD_RELOC_GPREL16:
2788 case BFD_RELOC_HI16:
2789 case BFD_RELOC_HI16_BASEREL:
2790 case BFD_RELOC_HI16_GOTOFF:
2791 case BFD_RELOC_HI16_PLTOFF:
2792 case BFD_RELOC_HI16_S:
2793 case BFD_RELOC_HI16_S_BASEREL:
2794 case BFD_RELOC_HI16_S_GOTOFF:
2795 case BFD_RELOC_HI16_S_PLTOFF:
2796 case BFD_RELOC_LO16:
2797 case BFD_RELOC_LO16_BASEREL:
2798 case BFD_RELOC_LO16_GOTOFF:
2799 case BFD_RELOC_LO16_PLTOFF:
2800 case BFD_RELOC_PPC64_ADDR16_DS:
2801 case BFD_RELOC_PPC64_ADDR16_HIGH:
2802 case BFD_RELOC_PPC64_ADDR16_HIGHA:
2803 case BFD_RELOC_PPC64_ADDR16_LO_DS:
2804 case BFD_RELOC_PPC64_DTPREL16_DS:
2805 case BFD_RELOC_PPC64_DTPREL16_HIGH:
2806 case BFD_RELOC_PPC64_DTPREL16_HIGHA:
2807 case BFD_RELOC_PPC64_DTPREL16_HIGHER:
2808 case BFD_RELOC_PPC64_DTPREL16_HIGHERA:
2809 case BFD_RELOC_PPC64_DTPREL16_HIGHEST:
2810 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA:
2811 case BFD_RELOC_PPC64_DTPREL16_LO_DS:
2812 case BFD_RELOC_PPC64_GOT16_DS:
2813 case BFD_RELOC_PPC64_GOT16_LO_DS:
2814 case BFD_RELOC_PPC64_HIGHER:
2815 case BFD_RELOC_PPC64_HIGHER_S:
2816 case BFD_RELOC_PPC64_HIGHEST:
2817 case BFD_RELOC_PPC64_HIGHEST_S:
2818 case BFD_RELOC_PPC64_PLT16_LO_DS:
2819 case BFD_RELOC_PPC64_PLTGOT16:
2820 case BFD_RELOC_PPC64_PLTGOT16_DS:
2821 case BFD_RELOC_PPC64_PLTGOT16_HA:
2822 case BFD_RELOC_PPC64_PLTGOT16_HI:
2823 case BFD_RELOC_PPC64_PLTGOT16_LO:
2824 case BFD_RELOC_PPC64_PLTGOT16_LO_DS:
2825 case BFD_RELOC_PPC64_SECTOFF_DS:
2826 case BFD_RELOC_PPC64_SECTOFF_LO_DS:
2827 case BFD_RELOC_PPC64_TOC16_DS:
2828 case BFD_RELOC_PPC64_TOC16_HA:
2829 case BFD_RELOC_PPC64_TOC16_HI:
2830 case BFD_RELOC_PPC64_TOC16_LO:
2831 case BFD_RELOC_PPC64_TOC16_LO_DS:
2832 case BFD_RELOC_PPC64_TPREL16_DS:
2833 case BFD_RELOC_PPC64_TPREL16_HIGH:
2834 case BFD_RELOC_PPC64_TPREL16_HIGHA:
2835 case BFD_RELOC_PPC64_TPREL16_HIGHER:
2836 case BFD_RELOC_PPC64_TPREL16_HIGHERA:
2837 case BFD_RELOC_PPC64_TPREL16_HIGHEST:
2838 case BFD_RELOC_PPC64_TPREL16_HIGHESTA:
2839 case BFD_RELOC_PPC64_TPREL16_LO_DS:
2840#ifdef OBJ_XCOFF
2841 case BFD_RELOC_PPC_BA16:
2842#endif
2843 case BFD_RELOC_PPC_DTPREL16:
2844 case BFD_RELOC_PPC_DTPREL16_HA:
2845 case BFD_RELOC_PPC_DTPREL16_HI:
2846 case BFD_RELOC_PPC_DTPREL16_LO:
2847 case BFD_RELOC_PPC_EMB_NADDR16:
2848 case BFD_RELOC_PPC_EMB_NADDR16_HA:
2849 case BFD_RELOC_PPC_EMB_NADDR16_HI:
2850 case BFD_RELOC_PPC_EMB_NADDR16_LO:
2851 case BFD_RELOC_PPC_EMB_RELSDA:
2852 case BFD_RELOC_PPC_EMB_RELSEC16:
2853 case BFD_RELOC_PPC_EMB_RELST_LO:
2854 case BFD_RELOC_PPC_EMB_RELST_HI:
2855 case BFD_RELOC_PPC_EMB_RELST_HA:
2856 case BFD_RELOC_PPC_EMB_SDA2I16:
2857 case BFD_RELOC_PPC_EMB_SDA2REL:
2858 case BFD_RELOC_PPC_EMB_SDAI16:
2859 case BFD_RELOC_PPC_GOT_DTPREL16:
2860 case BFD_RELOC_PPC_GOT_DTPREL16_HA:
2861 case BFD_RELOC_PPC_GOT_DTPREL16_HI:
2862 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
2863 case BFD_RELOC_PPC_GOT_TLSGD16:
2864 case BFD_RELOC_PPC_GOT_TLSGD16_HA:
2865 case BFD_RELOC_PPC_GOT_TLSGD16_HI:
2866 case BFD_RELOC_PPC_GOT_TLSGD16_LO:
2867 case BFD_RELOC_PPC_GOT_TLSLD16:
2868 case BFD_RELOC_PPC_GOT_TLSLD16_HA:
2869 case BFD_RELOC_PPC_GOT_TLSLD16_HI:
2870 case BFD_RELOC_PPC_GOT_TLSLD16_LO:
2871 case BFD_RELOC_PPC_GOT_TPREL16:
2872 case BFD_RELOC_PPC_GOT_TPREL16_HA:
2873 case BFD_RELOC_PPC_GOT_TPREL16_HI:
2874 case BFD_RELOC_PPC_GOT_TPREL16_LO:
2875 case BFD_RELOC_PPC_TOC16:
2876 case BFD_RELOC_PPC_TPREL16:
2877 case BFD_RELOC_PPC_TPREL16_HA:
2878 case BFD_RELOC_PPC_TPREL16_HI:
2879 case BFD_RELOC_PPC_TPREL16_LO:
2880 size = 2;
2881 break;
2882
2883 case BFD_RELOC_16_PCREL:
2884 case BFD_RELOC_HI16_PCREL:
2885 case BFD_RELOC_HI16_S_PCREL:
2886 case BFD_RELOC_LO16_PCREL:
2887 case BFD_RELOC_PPC64_REL16_HIGH:
2888 case BFD_RELOC_PPC64_REL16_HIGHA:
2889 case BFD_RELOC_PPC64_REL16_HIGHER:
2890 case BFD_RELOC_PPC64_REL16_HIGHERA:
2891 case BFD_RELOC_PPC64_REL16_HIGHEST:
2892 case BFD_RELOC_PPC64_REL16_HIGHESTA:
2893#ifdef OBJ_XCOFF
2894 case BFD_RELOC_PPC_B16:
2895#endif
2896 case BFD_RELOC_PPC_VLE_REL8:
2897 size = 2;
2898 pcrel = TRUE;
2899 break;
2900
2901 case BFD_RELOC_16_GOT_PCREL: /* coff reloc, bad name re size. */
2902 case BFD_RELOC_32:
2903 case BFD_RELOC_32_GOTOFF:
2904 case BFD_RELOC_32_PLTOFF:
2905#ifdef OBJ_XCOFF
2906 case BFD_RELOC_CTOR:
2907#endif
2908 case BFD_RELOC_PPC64_ENTRY:
2909 case BFD_RELOC_PPC_16DX_HA:
2910#ifndef OBJ_XCOFF
2911 case BFD_RELOC_PPC_BA16:
2912#endif
2913 case BFD_RELOC_PPC_BA16_BRNTAKEN:
2914 case BFD_RELOC_PPC_BA16_BRTAKEN:
2915 case BFD_RELOC_PPC_BA26:
2916 case BFD_RELOC_PPC_EMB_BIT_FLD:
2917 case BFD_RELOC_PPC_EMB_NADDR32:
2918 case BFD_RELOC_PPC_EMB_SDA21:
2919 case BFD_RELOC_PPC_TLS:
2920 case BFD_RELOC_PPC_TLSGD:
2921 case BFD_RELOC_PPC_TLSLD:
2922 case BFD_RELOC_PPC_VLE_HA16A:
2923 case BFD_RELOC_PPC_VLE_HA16D:
2924 case BFD_RELOC_PPC_VLE_HI16A:
2925 case BFD_RELOC_PPC_VLE_HI16D:
2926 case BFD_RELOC_PPC_VLE_LO16A:
2927 case BFD_RELOC_PPC_VLE_LO16D:
2928 case BFD_RELOC_PPC_VLE_SDA21:
2929 case BFD_RELOC_PPC_VLE_SDA21_LO:
2930 case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
2931 case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
2932 case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
2933 case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
2934 case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
2935 case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
2936 case BFD_RELOC_RVA:
2937 size = 4;
2938 break;
2939
2940 case BFD_RELOC_24_PLT_PCREL:
2941 case BFD_RELOC_32_PCREL:
2942 case BFD_RELOC_32_PLT_PCREL:
2943 case BFD_RELOC_PPC64_REL24_NOTOC:
2944#ifndef OBJ_XCOFF
2945 case BFD_RELOC_PPC_B16:
2946#endif
2947 case BFD_RELOC_PPC_B16_BRNTAKEN:
2948 case BFD_RELOC_PPC_B16_BRTAKEN:
2949 case BFD_RELOC_PPC_B26:
2950 case BFD_RELOC_PPC_LOCAL24PC:
2951 case BFD_RELOC_PPC_REL16DX_HA:
2952 case BFD_RELOC_PPC_VLE_REL15:
2953 case BFD_RELOC_PPC_VLE_REL24:
2954 size = 4;
2955 pcrel = TRUE;
2956 break;
2957
2958#ifndef OBJ_XCOFF
2959 case BFD_RELOC_CTOR:
2960#endif
2961 case BFD_RELOC_PPC_COPY:
2962 case BFD_RELOC_PPC_DTPMOD:
2963 case BFD_RELOC_PPC_DTPREL:
2964 case BFD_RELOC_PPC_GLOB_DAT:
2965 case BFD_RELOC_PPC_TPREL:
2966 size = ppc_obj64 ? 8 : 4;
2967 break;
2968
2969 case BFD_RELOC_64:
2970 case BFD_RELOC_64_PLTOFF:
2971 case BFD_RELOC_PPC64_ADDR64_LOCAL:
2972 case BFD_RELOC_PPC64_TOC:
2973 size = 8;
2974 break;
2975
2976 case BFD_RELOC_64_PCREL:
2977 case BFD_RELOC_64_PLT_PCREL:
2978 size = 8;
2979 pcrel = TRUE;
2980 break;
2981
2982 default:
2983 abort ();
2984 }
2985
2986 if (ENABLE_CHECKING)
2987 {
2988 reloc_howto_type *reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
2989 if (reloc_howto != NULL
2990 && (size != bfd_get_reloc_size (reloc_howto)
2991 || pcrel != reloc_howto->pc_relative))
2992 {
2993 as_bad (_("%s howto doesn't match size/pcrel in gas"),
2994 reloc_howto->name);
2995 abort ();
2996 }
2997 }
2998 *pc_relative = pcrel;
2999 return size;
3000}
3001
3002/* This routine is called for each instruction to be assembled. */
3003
3004void
3005md_assemble (char *str)
3006{
3007 char *s;
3008 const struct powerpc_opcode *opcode;
3009 uint64_t insn;
3010 const unsigned char *opindex_ptr;
3011 int need_paren;
3012 int next_opindex;
3013 struct ppc_fixup fixups[MAX_INSN_FIXUPS];
3014 int fc;
3015 char *f;
3016 int addr_mask;
3017 int i;
3018 unsigned int insn_length;
3019
3020 /* Get the opcode. */
3021 for (s = str; *s != '\0' && ! ISSPACE (*s); s++)
3022 ;
3023 if (*s != '\0')
3024 *s++ = '\0';
3025
3026 /* Look up the opcode in the hash table. */
3027 opcode = (const struct powerpc_opcode *) hash_find (ppc_hash, str);
3028 if (opcode == (const struct powerpc_opcode *) NULL)
3029 {
3030 const struct powerpc_macro *macro;
3031
3032 macro = (const struct powerpc_macro *) hash_find (ppc_macro_hash, str);
3033 if (macro == (const struct powerpc_macro *) NULL)
3034 as_bad (_("unrecognized opcode: `%s'"), str);
3035 else
3036 ppc_macro (s, macro);
3037
3038 return;
3039 }
3040
3041 insn = opcode->opcode;
3042
3043 str = s;
3044 while (ISSPACE (*str))
3045 ++str;
3046
3047 /* PowerPC operands are just expressions. The only real issue is
3048 that a few operand types are optional. If an instruction has
3049 multiple optional operands and one is omitted, then all optional
3050 operands past the first omitted one must also be omitted. */
3051 int num_optional_operands = 0;
3052 int num_optional_provided = 0;
3053
3054 /* Gather the operands. */
3055 need_paren = 0;
3056 next_opindex = 0;
3057 fc = 0;
3058 for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
3059 {
3060 const struct powerpc_operand *operand;
3061 const char *errmsg;
3062 char *hold;
3063 expressionS ex;
3064 char endc;
3065
3066 if (next_opindex == 0)
3067 operand = &powerpc_operands[*opindex_ptr];
3068 else
3069 {
3070 operand = &powerpc_operands[next_opindex];
3071 next_opindex = 0;
3072 }
3073 errmsg = NULL;
3074
3075 /* If this is an optional operand, and we are skipping it, just
3076 insert the default value, usually a zero. */
3077 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
3078 && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64))
3079 {
3080 if (num_optional_operands == 0)
3081 {
3082 const unsigned char *optr;
3083 int total = 0;
3084 int provided = 0;
3085 int omitted;
3086
3087 s = str;
3088 for (optr = opindex_ptr; *optr != 0; optr++)
3089 {
3090 const struct powerpc_operand *op;
3091 op = &powerpc_operands[*optr];
3092
3093 ++total;
3094
3095 if ((op->flags & PPC_OPERAND_OPTIONAL) != 0
3096 && !((op->flags & PPC_OPERAND_OPTIONAL32) != 0
3097 && ppc_obj64))
3098 ++num_optional_operands;
3099
3100 if (s != NULL && *s != '\0')
3101 {
3102 ++provided;
3103
3104 /* Look for the start of the next operand. */
3105 if ((op->flags & PPC_OPERAND_PARENS) != 0)
3106 s = strpbrk (s, "(,");
3107 else
3108 s = strchr (s, ',');
3109
3110 if (s != NULL)
3111 ++s;
3112 }
3113 }
3114 omitted = total - provided;
3115 num_optional_provided = num_optional_operands - omitted;
3116 }
3117 if (--num_optional_provided < 0)
3118 {
3119 int64_t val = ppc_optional_operand_value (operand, insn, ppc_cpu,
3120 num_optional_provided);
3121 if (operand->insert)
3122 {
3123 insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg);
3124 if (errmsg != (const char *) NULL)
3125 as_bad ("%s", errmsg);
3126 }
3127 else if (operand->shift >= 0)
3128 insn |= (val & operand->bitm) << operand->shift;
3129 else
3130 insn |= (val & operand->bitm) >> -operand->shift;
3131
3132 if ((operand->flags & PPC_OPERAND_NEXT) != 0)
3133 next_opindex = *opindex_ptr + 1;
3134 continue;
3135 }
3136 }
3137
3138 /* Gather the operand. */
3139 hold = input_line_pointer;
3140 input_line_pointer = str;
3141
3142#ifdef TE_PE
3143 if (*input_line_pointer == '[')
3144 {
3145 /* We are expecting something like the second argument here:
3146 *
3147 * lwz r4,[toc].GS.0.static_int(rtoc)
3148 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
3149 * The argument following the `]' must be a symbol name, and the
3150 * register must be the toc register: 'rtoc' or '2'
3151 *
3152 * The effect is to 0 as the displacement field
3153 * in the instruction, and issue an IMAGE_REL_PPC_TOCREL16 (or
3154 * the appropriate variation) reloc against it based on the symbol.
3155 * The linker will build the toc, and insert the resolved toc offset.
3156 *
3157 * Note:
3158 * o The size of the toc entry is currently assumed to be
3159 * 32 bits. This should not be assumed to be a hard coded
3160 * number.
3161 * o In an effort to cope with a change from 32 to 64 bits,
3162 * there are also toc entries that are specified to be
3163 * either 32 or 64 bits:
3164 * lwz r4,[toc32].GS.0.static_int(rtoc)
3165 * lwz r4,[toc64].GS.0.static_int(rtoc)
3166 * These demand toc entries of the specified size, and the
3167 * instruction probably requires it.
3168 */
3169
3170 int valid_toc;
3171 enum toc_size_qualifier toc_kind;
3172 bfd_reloc_code_real_type toc_reloc;
3173
3174 /* Go parse off the [tocXX] part. */
3175 valid_toc = parse_toc_entry (&toc_kind);
3176
3177 if (!valid_toc)
3178 {
3179 ignore_rest_of_line ();
3180 break;
3181 }
3182
3183 /* Now get the symbol following the ']'. */
3184 expression (&ex);
3185
3186 switch (toc_kind)
3187 {
3188 case default_toc:
3189 /* In this case, we may not have seen the symbol yet,
3190 since it is allowed to appear on a .extern or .globl
3191 or just be a label in the .data section. */
3192 toc_reloc = BFD_RELOC_PPC_TOC16;
3193 break;
3194 case data_in_toc:
3195 /* 1. The symbol must be defined and either in the toc
3196 section, or a global.
3197 2. The reloc generated must have the TOCDEFN flag set
3198 in upper bit mess of the reloc type.
3199 FIXME: It's a little confusing what the tocv
3200 qualifier can be used for. At the very least, I've
3201 seen three uses, only one of which I'm sure I can
3202 explain. */
3203 if (ex.X_op == O_symbol)
3204 {
3205 gas_assert (ex.X_add_symbol != NULL);
3206 if (symbol_get_bfdsym (ex.X_add_symbol)->section
3207 != tocdata_section)
3208 {
3209 as_bad (_("[tocv] symbol is not a toc symbol"));
3210 }
3211 }
3212
3213 toc_reloc = BFD_RELOC_PPC_TOC16;
3214 break;
3215 case must_be_32:
3216 /* FIXME: these next two specifically specify 32/64 bit
3217 toc entries. We don't support them today. Is this
3218 the right way to say that? */
3219 toc_reloc = BFD_RELOC_NONE;
3220 as_bad (_("unimplemented toc32 expression modifier"));
3221 break;
3222 case must_be_64:
3223 /* FIXME: see above. */
3224 toc_reloc = BFD_RELOC_NONE;
3225 as_bad (_("unimplemented toc64 expression modifier"));
3226 break;
3227 default:
3228 fprintf (stderr,
3229 _("Unexpected return value [%d] from parse_toc_entry!\n"),
3230 toc_kind);
3231 abort ();
3232 break;
3233 }
3234
3235 /* We need to generate a fixup for this expression. */
3236 if (fc >= MAX_INSN_FIXUPS)
3237 as_fatal (_("too many fixups"));
3238
3239 fixups[fc].reloc = toc_reloc;
3240 fixups[fc].exp = ex;
3241 fixups[fc].opindex = *opindex_ptr;
3242 ++fc;
3243
3244 /* Ok. We've set up the fixup for the instruction. Now make it
3245 look like the constant 0 was found here. */
3246 ex.X_unsigned = 1;
3247 ex.X_op = O_constant;
3248 ex.X_add_number = 0;
3249 ex.X_add_symbol = NULL;
3250 ex.X_op_symbol = NULL;
3251 }
3252
3253 else
3254#endif /* TE_PE */
3255 {
3256 if ((reg_names_p
3257 && (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
3258 || ((operand->flags & PPC_OPERAND_CR_REG) != 0)))
3259 || !register_name (&ex))
3260 {
3261 char save_lex = lex_type['%'];
3262
3263 if (((operand->flags & PPC_OPERAND_CR_REG) != 0)
3264 || (operand->flags & PPC_OPERAND_CR_BIT) != 0)
3265 {
3266 cr_operand = TRUE;
3267 lex_type['%'] |= LEX_BEGIN_NAME;
3268 }
3269 expression (&ex);
3270 cr_operand = FALSE;
3271 lex_type['%'] = save_lex;
3272 }
3273 }
3274
3275 str = input_line_pointer;
3276 input_line_pointer = hold;
3277
3278 if (ex.X_op == O_illegal)
3279 as_bad (_("illegal operand"));
3280 else if (ex.X_op == O_absent)
3281 as_bad (_("missing operand"));
3282 else if (ex.X_op == O_register)
3283 {
3284 if ((ex.X_md
3285 & ~operand->flags
3286 & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR
3287 | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG
3288 | PPC_OPERAND_SPR | PPC_OPERAND_GQR)) != 0
3289 && !((ex.X_md & PPC_OPERAND_GPR) != 0
3290 && ex.X_add_number != 0
3291 && (operand->flags & PPC_OPERAND_GPR_0) != 0))
3292 as_warn (_("invalid register expression"));
3293 insn = ppc_insert_operand (insn, operand, ex.X_add_number,
3294 ppc_cpu, (char *) NULL, 0);
3295 }
3296 else if (ex.X_op == O_constant)
3297 {
3298#ifdef OBJ_ELF
3299 /* Allow @HA, @L, @H on constants. */
3300 bfd_reloc_code_real_type reloc;
3301 char *orig_str = str;
3302
3303 if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE)
3304 switch (reloc)
3305 {
3306 default:
3307 str = orig_str;
3308 break;
3309
3310 case BFD_RELOC_LO16:
3311 ex.X_add_number &= 0xffff;
3312 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3313 ex.X_add_number = SEX16 (ex.X_add_number);
3314 break;
3315
3316 case BFD_RELOC_HI16:
3317 if (REPORT_OVERFLOW_HI && ppc_obj64)
3318 {
3319 /* PowerPC64 @h is tested for overflow. */
3320 ex.X_add_number = (addressT) ex.X_add_number >> 16;
3321 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3322 {
3323 addressT sign = (((addressT) -1 >> 16) + 1) >> 1;
3324 ex.X_add_number
3325 = ((addressT) ex.X_add_number ^ sign) - sign;
3326 }
3327 break;
3328 }
3329 /* Fallthru */
3330
3331 case BFD_RELOC_PPC64_ADDR16_HIGH:
3332 ex.X_add_number = PPC_HI (ex.X_add_number);
3333 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3334 ex.X_add_number = SEX16 (ex.X_add_number);
3335 break;
3336
3337 case BFD_RELOC_HI16_S:
3338 if (REPORT_OVERFLOW_HI && ppc_obj64)
3339 {
3340 /* PowerPC64 @ha is tested for overflow. */
3341 ex.X_add_number
3342 = ((addressT) ex.X_add_number + 0x8000) >> 16;
3343 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3344 {
3345 addressT sign = (((addressT) -1 >> 16) + 1) >> 1;
3346 ex.X_add_number
3347 = ((addressT) ex.X_add_number ^ sign) - sign;
3348 }
3349 break;
3350 }
3351 /* Fallthru */
3352
3353 case BFD_RELOC_PPC64_ADDR16_HIGHA:
3354 ex.X_add_number = PPC_HA (ex.X_add_number);
3355 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3356 ex.X_add_number = SEX16 (ex.X_add_number);
3357 break;
3358
3359 case BFD_RELOC_PPC64_HIGHER:
3360 ex.X_add_number = PPC_HIGHER (ex.X_add_number);
3361 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3362 ex.X_add_number = SEX16 (ex.X_add_number);
3363 break;
3364
3365 case BFD_RELOC_PPC64_HIGHER_S:
3366 ex.X_add_number = PPC_HIGHERA (ex.X_add_number);
3367 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3368 ex.X_add_number = SEX16 (ex.X_add_number);
3369 break;
3370
3371 case BFD_RELOC_PPC64_HIGHEST:
3372 ex.X_add_number = PPC_HIGHEST (ex.X_add_number);
3373 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3374 ex.X_add_number = SEX16 (ex.X_add_number);
3375 break;
3376
3377 case BFD_RELOC_PPC64_HIGHEST_S:
3378 ex.X_add_number = PPC_HIGHESTA (ex.X_add_number);
3379 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
3380 ex.X_add_number = SEX16 (ex.X_add_number);
3381 break;
3382 }
3383#endif /* OBJ_ELF */
3384 insn = ppc_insert_operand (insn, operand, ex.X_add_number,
3385 ppc_cpu, (char *) NULL, 0);
3386 }
3387 else
3388 {
3389 bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
3390#ifdef OBJ_ELF
3391 if (ex.X_op == O_symbol && str[0] == '(')
3392 {
3393 const char *sym_name = S_GET_NAME (ex.X_add_symbol);
3394 if (sym_name[0] == '.')
3395 ++sym_name;
3396
3397 if (strcasecmp (sym_name, "__tls_get_addr") == 0)
3398 {
3399 expressionS tls_exp;
3400
3401 hold = input_line_pointer;
3402 input_line_pointer = str + 1;
3403 expression (&tls_exp);
3404 if (tls_exp.X_op == O_symbol)
3405 {
3406 reloc = BFD_RELOC_NONE;
3407 if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0)
3408 {
3409 reloc = BFD_RELOC_PPC_TLSGD;
3410 input_line_pointer += 7;
3411 }
3412 else if (strncasecmp (input_line_pointer, "@tlsld)", 7) == 0)
3413 {
3414 reloc = BFD_RELOC_PPC_TLSLD;
3415 input_line_pointer += 7;
3416 }
3417 if (reloc != BFD_RELOC_NONE)
3418 {
3419 SKIP_WHITESPACE ();
3420 str = input_line_pointer;
3421
3422 if (fc >= MAX_INSN_FIXUPS)
3423 as_fatal (_("too many fixups"));
3424 fixups[fc].exp = tls_exp;
3425 fixups[fc].opindex = *opindex_ptr;
3426 fixups[fc].reloc = reloc;
3427 ++fc;
3428 }
3429 }
3430 input_line_pointer = hold;
3431 }
3432 }
3433
3434 if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE)
3435 {
3436 /* If VLE-mode convert LO/HI/HA relocations. */
3437 if (opcode->flags & PPC_OPCODE_VLE)
3438 {
3439 uint64_t tmp_insn = insn & opcode->mask;
3440
3441 int use_a_reloc = (tmp_insn == E_OR2I_INSN
3442 || tmp_insn == E_AND2I_DOT_INSN
3443 || tmp_insn == E_OR2IS_INSN
3444 || tmp_insn == E_LI_INSN
3445 || tmp_insn == E_LIS_INSN
3446 || tmp_insn == E_AND2IS_DOT_INSN);
3447
3448
3449 int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN
3450 || tmp_insn == E_ADD2IS_INSN
3451 || tmp_insn == E_CMP16I_INSN
3452 || tmp_insn == E_MULL2I_INSN
3453 || tmp_insn == E_CMPL16I_INSN
3454 || tmp_insn == E_CMPH16I_INSN
3455 || tmp_insn == E_CMPHL16I_INSN);
3456
3457 switch (reloc)
3458 {
3459 default:
3460 break;
3461
3462 case BFD_RELOC_PPC_EMB_SDA21:
3463 reloc = BFD_RELOC_PPC_VLE_SDA21;
3464 break;
3465
3466 case BFD_RELOC_LO16:
3467 if (use_d_reloc)
3468 reloc = BFD_RELOC_PPC_VLE_LO16D;
3469 else if (use_a_reloc)
3470 reloc = BFD_RELOC_PPC_VLE_LO16A;
3471 break;
3472
3473 case BFD_RELOC_HI16:
3474 if (use_d_reloc)
3475 reloc = BFD_RELOC_PPC_VLE_HI16D;
3476 else if (use_a_reloc)
3477 reloc = BFD_RELOC_PPC_VLE_HI16A;
3478 break;
3479
3480 case BFD_RELOC_HI16_S:
3481 if (use_d_reloc)
3482 reloc = BFD_RELOC_PPC_VLE_HA16D;
3483 else if (use_a_reloc)
3484 reloc = BFD_RELOC_PPC_VLE_HA16A;
3485 break;
3486
3487 case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
3488 if (use_d_reloc)
3489 reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D;
3490 break;
3491
3492 case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
3493 if (use_d_reloc)
3494 reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D;
3495 break;
3496
3497 case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
3498 if (use_d_reloc)
3499 reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D;
3500 break;
3501 }
3502 }
3503
3504 /* TLS and other tweaks. */
3505 switch (reloc)
3506 {
3507 default:
3508 break;
3509
3510 case BFD_RELOC_PPC_TLS:
3511 if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0))
3512 as_bad (_("@tls may not be used with \"%s\" operands"),
3513 opcode->name);
3514 else if (operand->shift != 11)
3515 as_bad (_("@tls may only be used in last operand"));
3516 else
3517 insn = ppc_insert_operand (insn, operand,
3518 ppc_obj64 ? 13 : 2,
3519 ppc_cpu, (char *) NULL, 0);
3520 break;
3521
3522 /* We'll only use the 32 (or 64) bit form of these relocations
3523 in constants. Instructions get the 16 bit form. */
3524 case BFD_RELOC_PPC_DTPREL:
3525 reloc = BFD_RELOC_PPC_DTPREL16;
3526 break;
3527
3528 case BFD_RELOC_PPC_TPREL:
3529 reloc = BFD_RELOC_PPC_TPREL16;
3530 break;
3531
3532 case BFD_RELOC_LO16:
3533 if ((operand->bitm | 0xf) != 0xffff
3534 || operand->shift != 0
3535 || (operand->flags & PPC_OPERAND_NEGATIVE) != 0)
3536 as_warn (_("%s unsupported on this instruction"), "@l");
3537 break;
3538
3539 case BFD_RELOC_HI16:
3540 if (operand->bitm != 0xffff
3541 || operand->shift != 0
3542 || (operand->flags & PPC_OPERAND_NEGATIVE) != 0)
3543 as_warn (_("%s unsupported on this instruction"), "@h");
3544 break;
3545
3546 case BFD_RELOC_HI16_S:
3547 if (operand->bitm == 0xffff
3548 && operand->shift == (int) PPC_OPSHIFT_INV
3549 && opcode->opcode == (19 << 26) + (2 << 1))
3550 /* addpcis. */
3551 reloc = BFD_RELOC_PPC_16DX_HA;
3552 else if (operand->bitm != 0xffff
3553 || operand->shift != 0
3554 || (operand->flags & PPC_OPERAND_NEGATIVE) != 0)
3555 as_warn (_("%s unsupported on this instruction"), "@ha");
3556 }
3557 }
3558#endif /* OBJ_ELF */
3559
3560 if (reloc != BFD_RELOC_NONE)
3561 ;
3562 /* Determine a BFD reloc value based on the operand information.
3563 We are only prepared to turn a few of the operands into
3564 relocs. */
3565 else if ((operand->flags & (PPC_OPERAND_RELATIVE
3566 | PPC_OPERAND_ABSOLUTE)) != 0
3567 && operand->bitm == 0x3fffffc
3568 && operand->shift == 0)
3569 reloc = BFD_RELOC_PPC_B26;
3570 else if ((operand->flags & (PPC_OPERAND_RELATIVE
3571 | PPC_OPERAND_ABSOLUTE)) != 0
3572 && operand->bitm == 0xfffc
3573 && operand->shift == 0)
3574 reloc = BFD_RELOC_PPC_B16;
3575 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
3576 && operand->bitm == 0x1fe
3577 && operand->shift == -1)
3578 reloc = BFD_RELOC_PPC_VLE_REL8;
3579 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
3580 && operand->bitm == 0xfffe
3581 && operand->shift == 0)
3582 reloc = BFD_RELOC_PPC_VLE_REL15;
3583 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
3584 && operand->bitm == 0x1fffffe
3585 && operand->shift == 0)
3586 reloc = BFD_RELOC_PPC_VLE_REL24;
3587 else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0
3588 && (operand->bitm & 0xfff0) == 0xfff0
3589 && operand->shift == 0)
3590 {
3591 reloc = BFD_RELOC_16;
3592#if defined OBJ_XCOFF || defined OBJ_ELF
3593 /* Note: the symbol may be not yet defined. */
3594 if ((operand->flags & PPC_OPERAND_PARENS) != 0
3595 && ppc_is_toc_sym (ex.X_add_symbol))
3596 {
3597 reloc = BFD_RELOC_PPC_TOC16;
3598#ifdef OBJ_ELF
3599 as_warn (_("assuming %s on symbol"),
3600 ppc_obj64 ? "@toc" : "@xgot");
3601#endif
3602 }
3603#endif
3604 }
3605
3606 /* For the absolute forms of branches, convert the PC
3607 relative form back into the absolute. */
3608 if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
3609 {
3610 switch (reloc)
3611 {
3612 case BFD_RELOC_PPC_B26:
3613 reloc = BFD_RELOC_PPC_BA26;
3614 break;
3615 case BFD_RELOC_PPC_B16:
3616 reloc = BFD_RELOC_PPC_BA16;
3617 break;
3618#ifdef OBJ_ELF
3619 case BFD_RELOC_PPC_B16_BRTAKEN:
3620 reloc = BFD_RELOC_PPC_BA16_BRTAKEN;
3621 break;
3622 case BFD_RELOC_PPC_B16_BRNTAKEN:
3623 reloc = BFD_RELOC_PPC_BA16_BRNTAKEN;
3624 break;
3625#endif
3626 default:
3627 break;
3628 }
3629 }
3630
3631#ifdef OBJ_ELF
3632 switch (reloc)
3633 {
3634 case BFD_RELOC_PPC_TOC16:
3635 toc_reloc_types |= has_small_toc_reloc;
3636 break;
3637 case BFD_RELOC_PPC64_TOC16_LO:
3638 case BFD_RELOC_PPC64_TOC16_HI:
3639 case BFD_RELOC_PPC64_TOC16_HA:
3640 toc_reloc_types |= has_large_toc_reloc;
3641 break;
3642 default:
3643 break;
3644 }
3645
3646 if (ppc_obj64
3647 && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
3648 {
3649 switch (reloc)
3650 {
3651 case BFD_RELOC_16:
3652 reloc = BFD_RELOC_PPC64_ADDR16_DS;
3653 break;
3654 case BFD_RELOC_LO16:
3655 reloc = BFD_RELOC_PPC64_ADDR16_LO_DS;
3656 break;
3657 case BFD_RELOC_16_GOTOFF:
3658 reloc = BFD_RELOC_PPC64_GOT16_DS;
3659 break;
3660 case BFD_RELOC_LO16_GOTOFF:
3661 reloc = BFD_RELOC_PPC64_GOT16_LO_DS;
3662 break;
3663 case BFD_RELOC_LO16_PLTOFF:
3664 reloc = BFD_RELOC_PPC64_PLT16_LO_DS;
3665 break;
3666 case BFD_RELOC_16_BASEREL:
3667 reloc = BFD_RELOC_PPC64_SECTOFF_DS;
3668 break;
3669 case BFD_RELOC_LO16_BASEREL:
3670 reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS;
3671 break;
3672 case BFD_RELOC_PPC_TOC16:
3673 reloc = BFD_RELOC_PPC64_TOC16_DS;
3674 break;
3675 case BFD_RELOC_PPC64_TOC16_LO:
3676 reloc = BFD_RELOC_PPC64_TOC16_LO_DS;
3677 break;
3678 case BFD_RELOC_PPC64_PLTGOT16:
3679 reloc = BFD_RELOC_PPC64_PLTGOT16_DS;
3680 break;
3681 case BFD_RELOC_PPC64_PLTGOT16_LO:
3682 reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS;
3683 break;
3684 case BFD_RELOC_PPC_DTPREL16:
3685 reloc = BFD_RELOC_PPC64_DTPREL16_DS;
3686 break;
3687 case BFD_RELOC_PPC_DTPREL16_LO:
3688 reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS;
3689 break;
3690 case BFD_RELOC_PPC_TPREL16:
3691 reloc = BFD_RELOC_PPC64_TPREL16_DS;
3692 break;
3693 case BFD_RELOC_PPC_TPREL16_LO:
3694 reloc = BFD_RELOC_PPC64_TPREL16_LO_DS;
3695 break;
3696 case BFD_RELOC_PPC_GOT_DTPREL16:
3697 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
3698 case BFD_RELOC_PPC_GOT_TPREL16:
3699 case BFD_RELOC_PPC_GOT_TPREL16_LO:
3700 break;
3701 default:
3702 as_bad (_("unsupported relocation for DS offset field"));
3703 break;
3704 }
3705 }
3706#endif
3707
3708 /* We need to generate a fixup for this expression. */
3709 if (fc >= MAX_INSN_FIXUPS)
3710 as_fatal (_("too many fixups"));
3711 fixups[fc].exp = ex;
3712 fixups[fc].opindex = *opindex_ptr;
3713 fixups[fc].reloc = reloc;
3714 ++fc;
3715 }
3716
3717 if (need_paren)
3718 {
3719 endc = ')';
3720 need_paren = 0;
3721 /* If expecting more operands, then we want to see "),". */
3722 if (*str == endc && opindex_ptr[1] != 0)
3723 {
3724 do
3725 ++str;
3726 while (ISSPACE (*str));
3727 endc = ',';
3728 }
3729 }
3730 else if ((operand->flags & PPC_OPERAND_PARENS) != 0)
3731 endc = '(';
3732 else
3733 endc = ',';
3734
3735 /* The call to expression should have advanced str past any
3736 whitespace. */
3737 if (*str == endc)
3738 {
3739 ++str;
3740 if (endc == '(')
3741 need_paren = 1;
3742 }
3743 else if (*str != '\0')
3744 {
3745 as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc);
3746 break;
3747 }
3748 else if (endc == ')')
3749 {
3750 as_bad (_("syntax error; end of line, expected `%c'"), endc);
3751 break;
3752 }
3753 }
3754
3755 while (ISSPACE (*str))
3756 ++str;
3757
3758 if (*str != '\0')
3759 as_bad (_("junk at end of line: `%s'"), str);
3760
3761#ifdef OBJ_ELF
3762 /* Do we need/want an APUinfo section? */
3763 if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0
3764 && !ppc_obj64)
3765 {
3766 /* These are all version "1". */
3767 if (opcode->flags & PPC_OPCODE_SPE)
3768 ppc_apuinfo_section_add (PPC_APUINFO_SPE, 1);
3769 if (opcode->flags & PPC_OPCODE_ISEL)
3770 ppc_apuinfo_section_add (PPC_APUINFO_ISEL, 1);
3771 if (opcode->flags & PPC_OPCODE_EFS)
3772 ppc_apuinfo_section_add (PPC_APUINFO_EFS, 1);
3773 if (opcode->flags & PPC_OPCODE_BRLOCK)
3774 ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK, 1);
3775 if (opcode->flags & PPC_OPCODE_PMR)
3776 ppc_apuinfo_section_add (PPC_APUINFO_PMR, 1);
3777 if (opcode->flags & PPC_OPCODE_CACHELCK)
3778 ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1);
3779 if (opcode->flags & PPC_OPCODE_RFMCI)
3780 ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1);
3781 /* Only set the VLE flag if the instruction has been pulled via
3782 the VLE instruction set. This way the flag is guaranteed to
3783 be set for VLE-only instructions or for VLE-only processors,
3784 however it'll remain clear for dual-mode instructions on
3785 dual-mode and, more importantly, standard-mode processors. */
3786 if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE)
3787 {
3788 ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
3789 if (elf_section_data (now_seg) != NULL)
3790 elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE;
3791 }
3792 }
3793#endif
3794
3795 /* Write out the instruction. */
3796
3797 addr_mask = 3;
3798 if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
3799 /* All instructions can start on a 2 byte boundary for VLE. */
3800 addr_mask = 1;
3801
3802 if (frag_now->insn_addr != addr_mask)
3803 {
3804 /* Don't emit instructions to a frag started for data, or for a
3805 CPU differing in VLE mode. Data is allowed to be misaligned,
3806 and it's possible to start a new frag in the middle of
3807 misaligned data. */
3808 frag_wane (frag_now);
3809 frag_new (0);
3810 }
3811
3812 /* Check that insns within the frag are aligned. ppc_frag_check
3813 will ensure that the frag start address is aligned. */
3814 if ((frag_now_fix () & addr_mask) != 0)
3815 as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1);
3816
3817 /* Differentiate between two and four byte insns. */
3818 insn_length = 4;
3819 if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn))
3820 insn_length = 2;
3821
3822 f = frag_more (insn_length);
3823 frag_now->insn_addr = addr_mask;
3824 md_number_to_chars (f, insn, insn_length);
3825 last_insn = insn;
3826 last_seg = now_seg;
3827 last_subseg = now_subseg;
3828
3829#ifdef OBJ_ELF
3830 dwarf2_emit_insn (insn_length);
3831#endif
3832
3833 /* Create any fixups. */
3834 for (i = 0; i < fc; i++)
3835 {
3836 fixS *fixP;
3837 if (fixups[i].reloc != BFD_RELOC_NONE)
3838 {
3839 bfd_boolean pcrel;
3840 unsigned int size = fixup_size (fixups[i].reloc, &pcrel);
3841 int offset = target_big_endian ? (insn_length - size) : 0;
3842
3843 fixP = fix_new_exp (frag_now,
3844 f - frag_now->fr_literal + offset,
3845 size,
3846 &fixups[i].exp,
3847 pcrel,
3848 fixups[i].reloc);
3849 }
3850 else
3851 {
3852 const struct powerpc_operand *operand;
3853
3854 operand = &powerpc_operands[fixups[i].opindex];
3855 fixP = fix_new_exp (frag_now,
3856 f - frag_now->fr_literal,
3857 insn_length,
3858 &fixups[i].exp,
3859 (operand->flags & PPC_OPERAND_RELATIVE) != 0,
3860 BFD_RELOC_NONE);
3861 }
3862 fixP->fx_pcrel_adjust = fixups[i].opindex;
3863 }
3864}
3865
3866/* Handle a macro. Gather all the operands, transform them as
3867 described by the macro, and call md_assemble recursively. All the
3868 operands are separated by commas; we don't accept parentheses
3869 around operands here. */
3870
3871static void
3872ppc_macro (char *str, const struct powerpc_macro *macro)
3873{
3874 char *operands[10];
3875 unsigned int count;
3876 char *s;
3877 unsigned int len;
3878 const char *format;
3879 unsigned int arg;
3880 char *send;
3881 char *complete;
3882
3883 /* Gather the users operands into the operands array. */
3884 count = 0;
3885 s = str;
3886 while (1)
3887 {
3888 if (count >= sizeof operands / sizeof operands[0])
3889 break;
3890 operands[count++] = s;
3891 s = strchr (s, ',');
3892 if (s == (char *) NULL)
3893 break;
3894 *s++ = '\0';
3895 }
3896
3897 if (count != macro->operands)
3898 {
3899 as_bad (_("wrong number of operands"));
3900 return;
3901 }
3902
3903 /* Work out how large the string must be (the size is unbounded
3904 because it includes user input). */
3905 len = 0;
3906 format = macro->format;
3907 while (*format != '\0')
3908 {
3909 if (*format != '%')
3910 {
3911 ++len;
3912 ++format;
3913 }
3914 else
3915 {
3916 arg = strtol (format + 1, &send, 10);
3917 know (send != format && arg < count);
3918 len += strlen (operands[arg]);
3919 format = send;
3920 }
3921 }
3922
3923 /* Put the string together. */
3924 complete = s = XNEWVEC (char, len + 1);
3925 format = macro->format;
3926 while (*format != '\0')
3927 {
3928 if (*format != '%')
3929 *s++ = *format++;
3930 else
3931 {
3932 arg = strtol (format + 1, &send, 10);
3933 strcpy (s, operands[arg]);
3934 s += strlen (s);
3935 format = send;
3936 }
3937 }
3938 *s = '\0';
3939
3940 /* Assemble the constructed instruction. */
3941 md_assemble (complete);
3942 free (complete);
3943}
3944\f
3945#ifdef OBJ_ELF
3946/* For ELF, add support for SHT_ORDERED. */
3947
3948int
3949ppc_section_type (char *str, size_t len)
3950{
3951 if (len == 7 && strncmp (str, "ordered", 7) == 0)
3952 return SHT_ORDERED;
3953
3954 return -1;
3955}
3956
3957int
3958ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type)
3959{
3960 if (type == SHT_ORDERED)
3961 flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES;
3962
3963 return flags;
3964}
3965
3966bfd_vma
3967ppc_elf_section_letter (int letter, const char **ptrmsg)
3968{
3969 if (letter == 'v')
3970 return SHF_PPC_VLE;
3971
3972 *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string");
3973 return -1;
3974}
3975#endif /* OBJ_ELF */
3976
3977\f
3978/* Pseudo-op handling. */
3979
3980/* The .byte pseudo-op. This is similar to the normal .byte
3981 pseudo-op, but it can also take a single ASCII string. */
3982
3983static void
3984ppc_byte (int ignore ATTRIBUTE_UNUSED)
3985{
3986 int count = 0;
3987
3988 if (*input_line_pointer != '\"')
3989 {
3990 cons (1);
3991 return;
3992 }
3993
3994 /* Gather characters. A real double quote is doubled. Unusual
3995 characters are not permitted. */
3996 ++input_line_pointer;
3997 while (1)
3998 {
3999 char c;
4000
4001 c = *input_line_pointer++;
4002
4003 if (c == '\"')
4004 {
4005 if (*input_line_pointer != '\"')
4006 break;
4007 ++input_line_pointer;
4008 }
4009
4010 FRAG_APPEND_1_CHAR (c);
4011 ++count;
4012 }
4013
4014 if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0)
4015 as_warn (_("data in executable section"));
4016 demand_empty_rest_of_line ();
4017}
4018\f
4019#ifdef OBJ_XCOFF
4020
4021/* XCOFF specific pseudo-op handling. */
4022
4023/* This is set if we are creating a .stabx symbol, since we don't want
4024 to handle symbol suffixes for such symbols. */
4025static bfd_boolean ppc_stab_symbol;
4026
4027/* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common
4028 symbols in the .bss segment as though they were local common
4029 symbols, and uses a different smclas. The native Aix 4.3.3 assembler
4030 aligns .comm and .lcomm to 4 bytes. */
4031
4032static void
4033ppc_comm (int lcomm)
4034{
4035 asection *current_seg = now_seg;
4036 subsegT current_subseg = now_subseg;
4037 char *name;
4038 char endc;
4039 char *end_name;
4040 offsetT size;
4041 offsetT align;
4042 symbolS *lcomm_sym = NULL;
4043 symbolS *sym;
4044 char *pfrag;
4045
4046 endc = get_symbol_name (&name);
4047 end_name = input_line_pointer;
4048 (void) restore_line_pointer (endc);
4049
4050 if (*input_line_pointer != ',')
4051 {
4052 as_bad (_("missing size"));
4053 ignore_rest_of_line ();
4054 return;
4055 }
4056 ++input_line_pointer;
4057
4058 size = get_absolute_expression ();
4059 if (size < 0)
4060 {
4061 as_bad (_("negative size"));
4062 ignore_rest_of_line ();
4063 return;
4064 }
4065
4066 if (! lcomm)
4067 {
4068 /* The third argument to .comm is the alignment. */
4069 if (*input_line_pointer != ',')
4070 align = 2;
4071 else
4072 {
4073 ++input_line_pointer;
4074 align = get_absolute_expression ();
4075 if (align <= 0)
4076 {
4077 as_warn (_("ignoring bad alignment"));
4078 align = 2;
4079 }
4080 }
4081 }
4082 else
4083 {
4084 char *lcomm_name;
4085 char lcomm_endc;
4086
4087 /* The third argument to .lcomm appears to be the real local
4088 common symbol to create. References to the symbol named in
4089 the first argument are turned into references to the third
4090 argument. */
4091 if (*input_line_pointer != ',')
4092 {
4093 as_bad (_("missing real symbol name"));
4094 ignore_rest_of_line ();
4095 return;
4096 }
4097 ++input_line_pointer;
4098
4099 lcomm_endc = get_symbol_name (&lcomm_name);
4100
4101 lcomm_sym = symbol_find_or_make (lcomm_name);
4102
4103 (void) restore_line_pointer (lcomm_endc);
4104
4105 /* The fourth argument to .lcomm is the alignment. */
4106 if (*input_line_pointer != ',')
4107 {
4108 if (size <= 4)
4109 align = 2;
4110 else
4111 align = 3;
4112 }
4113 else
4114 {
4115 ++input_line_pointer;
4116 align = get_absolute_expression ();
4117 if (align <= 0)
4118 {
4119 as_warn (_("ignoring bad alignment"));
4120 align = 2;
4121 }
4122 }
4123 }
4124
4125 *end_name = '\0';
4126 sym = symbol_find_or_make (name);
4127 *end_name = endc;
4128
4129 if (S_IS_DEFINED (sym)
4130 || S_GET_VALUE (sym) != 0)
4131 {
4132 as_bad (_("attempt to redefine symbol"));
4133 ignore_rest_of_line ();
4134 return;
4135 }
4136
4137 record_alignment (bss_section, align);
4138
4139 if (! lcomm
4140 || ! S_IS_DEFINED (lcomm_sym))
4141 {
4142 symbolS *def_sym;
4143 offsetT def_size;
4144
4145 if (! lcomm)
4146 {
4147 def_sym = sym;
4148 def_size = size;
4149 S_SET_EXTERNAL (sym);
4150 }
4151 else
4152 {
4153 symbol_get_tc (lcomm_sym)->output = 1;
4154 def_sym = lcomm_sym;
4155 def_size = 0;
4156 }
4157
4158 subseg_set (bss_section, 1);
4159 frag_align (align, 0, 0);
4160
4161 symbol_set_frag (def_sym, frag_now);
4162 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, def_sym,
4163 def_size, (char *) NULL);
4164 *pfrag = 0;
4165 S_SET_SEGMENT (def_sym, bss_section);
4166 symbol_get_tc (def_sym)->align = align;
4167 }
4168 else if (lcomm)
4169 {
4170 /* Align the size of lcomm_sym. */
4171 symbol_get_frag (lcomm_sym)->fr_offset =
4172 ((symbol_get_frag (lcomm_sym)->fr_offset + (1 << align) - 1)
4173 &~ ((1 << align) - 1));
4174 if (align > symbol_get_tc (lcomm_sym)->align)
4175 symbol_get_tc (lcomm_sym)->align = align;
4176 }
4177
4178 if (lcomm)
4179 {
4180 /* Make sym an offset from lcomm_sym. */
4181 S_SET_SEGMENT (sym, bss_section);
4182 symbol_set_frag (sym, symbol_get_frag (lcomm_sym));
4183 S_SET_VALUE (sym, symbol_get_frag (lcomm_sym)->fr_offset);
4184 symbol_get_frag (lcomm_sym)->fr_offset += size;
4185 }
4186
4187 subseg_set (current_seg, current_subseg);
4188
4189 demand_empty_rest_of_line ();
4190}
4191
4192/* The .csect pseudo-op. This switches us into a different
4193 subsegment. The first argument is a symbol whose value is the
4194 start of the .csect. In COFF, csect symbols get special aux
4195 entries defined by the x_csect field of union internal_auxent. The
4196 optional second argument is the alignment (the default is 2). */
4197
4198static void
4199ppc_csect (int ignore ATTRIBUTE_UNUSED)
4200{
4201 char *name;
4202 char endc;
4203 symbolS *sym;
4204 offsetT align;
4205
4206 endc = get_symbol_name (&name);
4207
4208 sym = symbol_find_or_make (name);
4209
4210 (void) restore_line_pointer (endc);
4211
4212 if (S_GET_NAME (sym)[0] == '\0')
4213 {
4214 /* An unnamed csect is assumed to be [PR]. */
4215 symbol_get_tc (sym)->symbol_class = XMC_PR;
4216 }
4217
4218 align = 2;
4219 if (*input_line_pointer == ',')
4220 {
4221 ++input_line_pointer;
4222 align = get_absolute_expression ();
4223 }
4224
4225 ppc_change_csect (sym, align);
4226
4227 demand_empty_rest_of_line ();
4228}
4229
4230/* Change to a different csect. */
4231
4232static void
4233ppc_change_csect (symbolS *sym, offsetT align)
4234{
4235 if (S_IS_DEFINED (sym))
4236 subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg);
4237 else
4238 {
4239 symbolS **list_ptr;
4240 int after_toc;
4241 int hold_chunksize;
4242 symbolS *list;
4243 int is_code;
4244 segT sec;
4245
4246 /* This is a new csect. We need to look at the symbol class to
4247 figure out whether it should go in the text section or the
4248 data section. */
4249 after_toc = 0;
4250 is_code = 0;
4251 switch (symbol_get_tc (sym)->symbol_class)
4252 {
4253 case XMC_PR:
4254 case XMC_RO:
4255 case XMC_DB:
4256 case XMC_GL:
4257 case XMC_XO:
4258 case XMC_SV:
4259 case XMC_TI:
4260 case XMC_TB:
4261 S_SET_SEGMENT (sym, text_section);
4262 symbol_get_tc (sym)->subseg = ppc_text_subsegment;
4263 ++ppc_text_subsegment;
4264 list_ptr = &ppc_text_csects;
4265 is_code = 1;
4266 break;
4267 case XMC_RW:
4268 case XMC_TC0:
4269 case XMC_TC:
4270 case XMC_DS:
4271 case XMC_UA:
4272 case XMC_BS:
4273 case XMC_UC:
4274 if (ppc_toc_csect != NULL
4275 && (symbol_get_tc (ppc_toc_csect)->subseg + 1
4276 == ppc_data_subsegment))
4277 after_toc = 1;
4278 S_SET_SEGMENT (sym, data_section);
4279 symbol_get_tc (sym)->subseg = ppc_data_subsegment;
4280 ++ppc_data_subsegment;
4281 list_ptr = &ppc_data_csects;
4282 break;
4283 default:
4284 abort ();
4285 }
4286
4287 /* We set the obstack chunk size to a small value before
4288 changing subsegments, so that we don't use a lot of memory
4289 space for what may be a small section. */
4290 hold_chunksize = chunksize;
4291 chunksize = 64;
4292
4293 sec = subseg_new (segment_name (S_GET_SEGMENT (sym)),
4294 symbol_get_tc (sym)->subseg);
4295
4296 chunksize = hold_chunksize;
4297
4298 if (after_toc)
4299 ppc_after_toc_frag = frag_now;
4300
4301 record_alignment (sec, align);
4302 if (is_code)
4303 frag_align_code (align, 0);
4304 else
4305 frag_align (align, 0, 0);
4306
4307 symbol_set_frag (sym, frag_now);
4308 S_SET_VALUE (sym, (valueT) frag_now_fix ());
4309
4310 symbol_get_tc (sym)->align = align;
4311 symbol_get_tc (sym)->output = 1;
4312 symbol_get_tc (sym)->within = sym;
4313
4314 for (list = *list_ptr;
4315 symbol_get_tc (list)->next != (symbolS *) NULL;
4316 list = symbol_get_tc (list)->next)
4317 ;
4318 symbol_get_tc (list)->next = sym;
4319
4320 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4321 symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP,
4322 &symbol_lastP);
4323 }
4324
4325 ppc_current_csect = sym;
4326}
4327
4328static void
4329ppc_change_debug_section (unsigned int idx, subsegT subseg)
4330{
4331 segT sec;
4332 flagword oldflags;
4333 const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx];
4334
4335 sec = subseg_new (dw->name, subseg);
4336 oldflags = bfd_get_section_flags (stdoutput, sec);
4337 if (oldflags == SEC_NO_FLAGS)
4338 {
4339 /* Just created section. */
4340 gas_assert (dw_sections[idx].sect == NULL);
4341
4342 bfd_set_section_flags (stdoutput, sec, SEC_DEBUGGING);
4343 bfd_set_section_alignment (stdoutput, sec, 0);
4344 dw_sections[idx].sect = sec;
4345 }
4346
4347 /* Not anymore in a csect. */
4348 ppc_current_csect = NULL;
4349}
4350
4351/* The .dwsect pseudo-op. Defines a DWARF section. Syntax is:
4352 .dwsect flag [, opt-label ]
4353*/
4354
4355static void
4356ppc_dwsect (int ignore ATTRIBUTE_UNUSED)
4357{
4358 valueT flag;
4359 symbolS *opt_label;
4360 const struct xcoff_dwsect_name *dw;
4361 struct dw_subsection *subseg;
4362 struct dw_section *dws;
4363 int i;
4364
4365 /* Find section. */
4366 flag = get_absolute_expression ();
4367 dw = NULL;
4368 for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++)
4369 if (xcoff_dwsect_names[i].flag == flag)
4370 {
4371 dw = &xcoff_dwsect_names[i];
4372 break;
4373 }
4374
4375 /* Parse opt-label. */
4376 if (*input_line_pointer == ',')
4377 {
4378 char *label;
4379 char c;
4380
4381 ++input_line_pointer;
4382
4383 c = get_symbol_name (&label);
4384 opt_label = symbol_find_or_make (label);
4385 (void) restore_line_pointer (c);
4386 }
4387 else
4388 opt_label = NULL;
4389
4390 demand_empty_rest_of_line ();
4391
4392 /* Return now in case of unknown subsection. */
4393 if (dw == NULL)
4394 {
4395 as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"),
4396 (unsigned)flag);
4397 return;
4398 }
4399
4400 /* Find the subsection. */
4401 dws = &dw_sections[i];
4402 subseg = NULL;
4403 if (opt_label != NULL && S_IS_DEFINED (opt_label))
4404 {
4405 /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */
4406 if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect)
4407 {
4408 as_bad (_("label %s was not defined in this dwarf section"),
4409 S_GET_NAME (opt_label));
4410 subseg = dws->anon_subseg;
4411 opt_label = NULL;
4412 }
4413 else
4414 subseg = symbol_get_tc (opt_label)->u.dw;
4415 }
4416
4417 if (subseg != NULL)
4418 {
4419 /* Switch to the subsection. */
4420 ppc_change_debug_section (i, subseg->subseg);
4421 }
4422 else
4423 {
4424 /* Create a new dw subsection. */
4425 subseg = XNEW (struct dw_subsection);
4426
4427 if (opt_label == NULL)
4428 {
4429 /* The anonymous one. */
4430 subseg->subseg = 0;
4431 subseg->link = NULL;
4432 dws->anon_subseg = subseg;
4433 }
4434 else
4435 {
4436 /* A named one. */
4437 if (dws->list_subseg != NULL)
4438 subseg->subseg = dws->list_subseg->subseg + 1;
4439 else
4440 subseg->subseg = 1;
4441
4442 subseg->link = dws->list_subseg;
4443 dws->list_subseg = subseg;
4444 symbol_get_tc (opt_label)->u.dw = subseg;
4445 }
4446
4447 ppc_change_debug_section (i, subseg->subseg);
4448
4449 if (dw->def_size)
4450 {
4451 /* Add the length field. */
4452 expressionS *exp = &subseg->end_exp;
4453 int sz;
4454
4455 if (opt_label != NULL)
4456 symbol_set_value_now (opt_label);
4457
4458 /* Add the length field. Note that according to the AIX assembler
4459 manual, the size of the length field is 4 for powerpc32 but
4460 12 for powerpc64. */
4461 if (ppc_obj64)
4462 {
4463 /* Write the 64bit marker. */
4464 md_number_to_chars (frag_more (4), -1, 4);
4465 }
4466
4467 exp->X_op = O_subtract;
4468 exp->X_op_symbol = symbol_temp_new_now ();
4469 exp->X_add_symbol = symbol_temp_make ();
4470
4471 sz = ppc_obj64 ? 8 : 4;
4472 exp->X_add_number = -sz;
4473 emit_expr (exp, sz);
4474 }
4475 }
4476}
4477
4478/* This function handles the .text and .data pseudo-ops. These
4479 pseudo-ops aren't really used by XCOFF; we implement them for the
4480 convenience of people who aren't used to XCOFF. */
4481
4482static void
4483ppc_section (int type)
4484{
4485 const char *name;
4486 symbolS *sym;
4487
4488 if (type == 't')
4489 name = ".text[PR]";
4490 else if (type == 'd')
4491 name = ".data[RW]";
4492 else
4493 abort ();
4494
4495 sym = symbol_find_or_make (name);
4496
4497 ppc_change_csect (sym, 2);
4498
4499 demand_empty_rest_of_line ();
4500}
4501
4502/* This function handles the .section pseudo-op. This is mostly to
4503 give an error, since XCOFF only supports .text, .data and .bss, but
4504 we do permit the user to name the text or data section. */
4505
4506static void
4507ppc_named_section (int ignore ATTRIBUTE_UNUSED)
4508{
4509 char *user_name;
4510 const char *real_name;
4511 char c;
4512 symbolS *sym;
4513
4514 c = get_symbol_name (&user_name);
4515
4516 if (strcmp (user_name, ".text") == 0)
4517 real_name = ".text[PR]";
4518 else if (strcmp (user_name, ".data") == 0)
4519 real_name = ".data[RW]";
4520 else
4521 {
4522 as_bad (_("the XCOFF file format does not support arbitrary sections"));
4523 (void) restore_line_pointer (c);
4524 ignore_rest_of_line ();
4525 return;
4526 }
4527
4528 (void) restore_line_pointer (c);
4529
4530 sym = symbol_find_or_make (real_name);
4531
4532 ppc_change_csect (sym, 2);
4533
4534 demand_empty_rest_of_line ();
4535}
4536
4537/* The .extern pseudo-op. We create an undefined symbol. */
4538
4539static void
4540ppc_extern (int ignore ATTRIBUTE_UNUSED)
4541{
4542 char *name;
4543 char endc;
4544
4545 endc = get_symbol_name (&name);
4546
4547 (void) symbol_find_or_make (name);
4548
4549 (void) restore_line_pointer (endc);
4550
4551 demand_empty_rest_of_line ();
4552}
4553
4554/* The .lglobl pseudo-op. Keep the symbol in the symbol table. */
4555
4556static void
4557ppc_lglobl (int ignore ATTRIBUTE_UNUSED)
4558{
4559 char *name;
4560 char endc;
4561 symbolS *sym;
4562
4563 endc = get_symbol_name (&name);
4564
4565 sym = symbol_find_or_make (name);
4566
4567 (void) restore_line_pointer (endc);
4568
4569 symbol_get_tc (sym)->output = 1;
4570
4571 demand_empty_rest_of_line ();
4572}
4573
4574/* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF
4575 relocations at the beginning of the current csect.
4576
4577 (In principle, there's no reason why the relocations _have_ to be at
4578 the beginning. Anywhere in the csect would do. However, inserting
4579 at the beginning is what the native assembler does, and it helps to
4580 deal with cases where the .ref statements follow the section contents.)
4581
4582 ??? .refs don't work for empty .csects. However, the native assembler
4583 doesn't report an error in this case, and neither yet do we. */
4584
4585static void
4586ppc_ref (int ignore ATTRIBUTE_UNUSED)
4587{
4588 char *name;
4589 char c;
4590
4591 if (ppc_current_csect == NULL)
4592 {
4593 as_bad (_(".ref outside .csect"));
4594 ignore_rest_of_line ();
4595 return;
4596 }
4597
4598 do
4599 {
4600 c = get_symbol_name (&name);
4601
4602 fix_at_start (symbol_get_frag (ppc_current_csect), 0,
4603 symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE);
4604
4605 *input_line_pointer = c;
4606 SKIP_WHITESPACE_AFTER_NAME ();
4607 c = *input_line_pointer;
4608 if (c == ',')
4609 {
4610 input_line_pointer++;
4611 SKIP_WHITESPACE ();
4612 if (is_end_of_line[(unsigned char) *input_line_pointer])
4613 {
4614 as_bad (_("missing symbol name"));
4615 ignore_rest_of_line ();
4616 return;
4617 }
4618 }
4619 }
4620 while (c == ',');
4621
4622 demand_empty_rest_of_line ();
4623}
4624
4625/* The .rename pseudo-op. The RS/6000 assembler can rename symbols,
4626 although I don't know why it bothers. */
4627
4628static void
4629ppc_rename (int ignore ATTRIBUTE_UNUSED)
4630{
4631 char *name;
4632 char endc;
4633 symbolS *sym;
4634 int len;
4635
4636 endc = get_symbol_name (&name);
4637
4638 sym = symbol_find_or_make (name);
4639
4640 (void) restore_line_pointer (endc);
4641
4642 if (*input_line_pointer != ',')
4643 {
4644 as_bad (_("missing rename string"));
4645 ignore_rest_of_line ();
4646 return;
4647 }
4648 ++input_line_pointer;
4649
4650 symbol_get_tc (sym)->real_name = demand_copy_C_string (&len);
4651
4652 demand_empty_rest_of_line ();
4653}
4654
4655/* The .stabx pseudo-op. This is similar to a normal .stabs
4656 pseudo-op, but slightly different. A sample is
4657 .stabx "main:F-1",.main,142,0
4658 The first argument is the symbol name to create. The second is the
4659 value, and the third is the storage class. The fourth seems to be
4660 always zero, and I am assuming it is the type. */
4661
4662static void
4663ppc_stabx (int ignore ATTRIBUTE_UNUSED)
4664{
4665 char *name;
4666 int len;
4667 symbolS *sym;
4668 expressionS exp;
4669
4670 name = demand_copy_C_string (&len);
4671
4672 if (*input_line_pointer != ',')
4673 {
4674 as_bad (_("missing value"));
4675 return;
4676 }
4677 ++input_line_pointer;
4678
4679 ppc_stab_symbol = TRUE;
4680 sym = symbol_make (name);
4681 ppc_stab_symbol = FALSE;
4682
4683 symbol_get_tc (sym)->real_name = name;
4684
4685 (void) expression (&exp);
4686
4687 switch (exp.X_op)
4688 {
4689 case O_illegal:
4690 case O_absent:
4691 case O_big:
4692 as_bad (_("illegal .stabx expression; zero assumed"));
4693 exp.X_add_number = 0;
4694 /* Fall through. */
4695 case O_constant:
4696 S_SET_VALUE (sym, (valueT) exp.X_add_number);
4697 symbol_set_frag (sym, &zero_address_frag);
4698 break;
4699
4700 case O_symbol:
4701 if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section)
4702 symbol_set_value_expression (sym, &exp);
4703 else
4704 {
4705 S_SET_VALUE (sym,
4706 exp.X_add_number + S_GET_VALUE (exp.X_add_symbol));
4707 symbol_set_frag (sym, symbol_get_frag (exp.X_add_symbol));
4708 }
4709 break;
4710
4711 default:
4712 /* The value is some complex expression. This will probably
4713 fail at some later point, but this is probably the right
4714 thing to do here. */
4715 symbol_set_value_expression (sym, &exp);
4716 break;
4717 }
4718
4719 S_SET_SEGMENT (sym, ppc_coff_debug_section);
4720 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
4721
4722 if (*input_line_pointer != ',')
4723 {
4724 as_bad (_("missing class"));
4725 return;
4726 }
4727 ++input_line_pointer;
4728
4729 S_SET_STORAGE_CLASS (sym, get_absolute_expression ());
4730
4731 if (*input_line_pointer != ',')
4732 {
4733 as_bad (_("missing type"));
4734 return;
4735 }
4736 ++input_line_pointer;
4737
4738 S_SET_DATA_TYPE (sym, get_absolute_expression ());
4739
4740 symbol_get_tc (sym)->output = 1;
4741
4742 if (S_GET_STORAGE_CLASS (sym) == C_STSYM)
4743 {
4744 /* In this case :
4745
4746 .bs name
4747 .stabx "z",arrays_,133,0
4748 .es
4749
4750 .comm arrays_,13768,3
4751
4752 resolve_symbol_value will copy the exp's "within" into sym's when the
4753 offset is 0. Since this seems to be corner case problem,
4754 only do the correction for storage class C_STSYM. A better solution
4755 would be to have the tc field updated in ppc_symbol_new_hook. */
4756
4757 if (exp.X_op == O_symbol)
4758 {
4759 if (ppc_current_block == NULL)
4760 as_bad (_(".stabx of storage class stsym must be within .bs/.es"));
4761
4762 symbol_get_tc (sym)->within = ppc_current_block;
4763 symbol_get_tc (exp.X_add_symbol)->within = ppc_current_block;
4764 }
4765 }
4766
4767 if (exp.X_op != O_symbol
4768 || ! S_IS_EXTERNAL (exp.X_add_symbol)
4769 || S_GET_SEGMENT (exp.X_add_symbol) != bss_section)
4770 ppc_frob_label (sym);
4771 else
4772 {
4773 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4774 symbol_append (sym, exp.X_add_symbol, &symbol_rootP, &symbol_lastP);
4775 if (symbol_get_tc (ppc_current_csect)->within == exp.X_add_symbol)
4776 symbol_get_tc (ppc_current_csect)->within = sym;
4777 }
4778
4779 demand_empty_rest_of_line ();
4780}
4781
4782/* The .function pseudo-op. This takes several arguments. The first
4783 argument seems to be the external name of the symbol. The second
4784 argument seems to be the label for the start of the function. gcc
4785 uses the same name for both. I have no idea what the third and
4786 fourth arguments are meant to be. The optional fifth argument is
4787 an expression for the size of the function. In COFF this symbol
4788 gets an aux entry like that used for a csect. */
4789
4790static void
4791ppc_function (int ignore ATTRIBUTE_UNUSED)
4792{
4793 char *name;
4794 char endc;
4795 char *s;
4796 symbolS *ext_sym;
4797 symbolS *lab_sym;
4798
4799 endc = get_symbol_name (&name);
4800
4801 /* Ignore any [PR] suffix. */
4802 name = ppc_canonicalize_symbol_name (name);
4803 s = strchr (name, '[');
4804 if (s != (char *) NULL
4805 && strcmp (s + 1, "PR]") == 0)
4806 *s = '\0';
4807
4808 ext_sym = symbol_find_or_make (name);
4809
4810 (void) restore_line_pointer (endc);
4811
4812 if (*input_line_pointer != ',')
4813 {
4814 as_bad (_("missing symbol name"));
4815 ignore_rest_of_line ();
4816 return;
4817 }
4818 ++input_line_pointer;
4819
4820 endc = get_symbol_name (&name);
4821
4822 lab_sym = symbol_find_or_make (name);
4823
4824 (void) restore_line_pointer (endc);
4825
4826 if (ext_sym != lab_sym)
4827 {
4828 expressionS exp;
4829
4830 exp.X_op = O_symbol;
4831 exp.X_add_symbol = lab_sym;
4832 exp.X_op_symbol = NULL;
4833 exp.X_add_number = 0;
4834 exp.X_unsigned = 0;
4835 symbol_set_value_expression (ext_sym, &exp);
4836 }
4837
4838 if (symbol_get_tc (ext_sym)->symbol_class == -1)
4839 symbol_get_tc (ext_sym)->symbol_class = XMC_PR;
4840 symbol_get_tc (ext_sym)->output = 1;
4841
4842 if (*input_line_pointer == ',')
4843 {
4844 expressionS exp;
4845
4846 /* Ignore the third argument. */
4847 ++input_line_pointer;
4848 expression (& exp);
4849 if (*input_line_pointer == ',')
4850 {
4851 /* Ignore the fourth argument. */
4852 ++input_line_pointer;
4853 expression (& exp);
4854 if (*input_line_pointer == ',')
4855 {
4856 /* The fifth argument is the function size. */
4857 ++input_line_pointer;
4858 symbol_get_tc (ext_sym)->u.size = symbol_new
4859 ("L0\001", absolute_section,(valueT) 0, &zero_address_frag);
4860 pseudo_set (symbol_get_tc (ext_sym)->u.size);
4861 }
4862 }
4863 }
4864
4865 S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT);
4866 SF_SET_FUNCTION (ext_sym);
4867 SF_SET_PROCESS (ext_sym);
4868 coff_add_linesym (ext_sym);
4869
4870 demand_empty_rest_of_line ();
4871}
4872
4873/* The .bf pseudo-op. This is just like a COFF C_FCN symbol named
4874 ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym
4875 with the correct line number */
4876
4877static symbolS *saved_bi_sym = 0;
4878
4879static void
4880ppc_bf (int ignore ATTRIBUTE_UNUSED)
4881{
4882 symbolS *sym;
4883
4884 sym = symbol_make (".bf");
4885 S_SET_SEGMENT (sym, text_section);
4886 symbol_set_frag (sym, frag_now);
4887 S_SET_VALUE (sym, frag_now_fix ());
4888 S_SET_STORAGE_CLASS (sym, C_FCN);
4889
4890 coff_line_base = get_absolute_expression ();
4891
4892 S_SET_NUMBER_AUXILIARY (sym, 1);
4893 SA_SET_SYM_LNNO (sym, coff_line_base);
4894
4895 /* Line number for bi. */
4896 if (saved_bi_sym)
4897 {
4898 S_SET_VALUE (saved_bi_sym, coff_n_line_nos);
4899 saved_bi_sym = 0;
4900 }
4901
4902
4903 symbol_get_tc (sym)->output = 1;
4904
4905 ppc_frob_label (sym);
4906
4907 demand_empty_rest_of_line ();
4908}
4909
4910/* The .ef pseudo-op. This is just like a COFF C_FCN symbol named
4911 ".ef", except that the line number is absolute, not relative to the
4912 most recent ".bf" symbol. */
4913
4914static void
4915ppc_ef (int ignore ATTRIBUTE_UNUSED)
4916{
4917 symbolS *sym;
4918
4919 sym = symbol_make (".ef");
4920 S_SET_SEGMENT (sym, text_section);
4921 symbol_set_frag (sym, frag_now);
4922 S_SET_VALUE (sym, frag_now_fix ());
4923 S_SET_STORAGE_CLASS (sym, C_FCN);
4924 S_SET_NUMBER_AUXILIARY (sym, 1);
4925 SA_SET_SYM_LNNO (sym, get_absolute_expression ());
4926 symbol_get_tc (sym)->output = 1;
4927
4928 ppc_frob_label (sym);
4929
4930 demand_empty_rest_of_line ();
4931}
4932
4933/* The .bi and .ei pseudo-ops. These take a string argument and
4934 generates a C_BINCL or C_EINCL symbol, which goes at the start of
4935 the symbol list. The value of .bi will be know when the next .bf
4936 is encountered. */
4937
4938static void
4939ppc_biei (int ei)
4940{
4941 static symbolS *last_biei;
4942
4943 char *name;
4944 int len;
4945 symbolS *sym;
4946 symbolS *look;
4947
4948 name = demand_copy_C_string (&len);
4949
4950 /* The value of these symbols is actually file offset. Here we set
4951 the value to the index into the line number entries. In
4952 ppc_frob_symbols we set the fix_line field, which will cause BFD
4953 to do the right thing. */
4954
4955 sym = symbol_make (name);
4956 /* obj-coff.c currently only handles line numbers correctly in the
4957 .text section. */
4958 S_SET_SEGMENT (sym, text_section);
4959 S_SET_VALUE (sym, coff_n_line_nos);
4960 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
4961
4962 S_SET_STORAGE_CLASS (sym, ei ? C_EINCL : C_BINCL);
4963 symbol_get_tc (sym)->output = 1;
4964
4965 /* Save bi. */
4966 if (ei)
4967 saved_bi_sym = 0;
4968 else
4969 saved_bi_sym = sym;
4970
4971 for (look = last_biei ? last_biei : symbol_rootP;
4972 (look != (symbolS *) NULL
4973 && (S_GET_STORAGE_CLASS (look) == C_FILE
4974 || S_GET_STORAGE_CLASS (look) == C_BINCL
4975 || S_GET_STORAGE_CLASS (look) == C_EINCL));
4976 look = symbol_next (look))
4977 ;
4978 if (look != (symbolS *) NULL)
4979 {
4980 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4981 symbol_insert (sym, look, &symbol_rootP, &symbol_lastP);
4982 last_biei = sym;
4983 }
4984
4985 demand_empty_rest_of_line ();
4986}
4987
4988/* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs".
4989 There is one argument, which is a csect symbol. The value of the
4990 .bs symbol is the index of this csect symbol. */
4991
4992static void
4993ppc_bs (int ignore ATTRIBUTE_UNUSED)
4994{
4995 char *name;
4996 char endc;
4997 symbolS *csect;
4998 symbolS *sym;
4999
5000 if (ppc_current_block != NULL)
5001 as_bad (_("nested .bs blocks"));
5002
5003 endc = get_symbol_name (&name);
5004
5005 csect = symbol_find_or_make (name);
5006
5007 (void) restore_line_pointer (endc);
5008
5009 sym = symbol_make (".bs");
5010 S_SET_SEGMENT (sym, now_seg);
5011 S_SET_STORAGE_CLASS (sym, C_BSTAT);
5012 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
5013 symbol_get_tc (sym)->output = 1;
5014
5015 symbol_get_tc (sym)->within = csect;
5016
5017 ppc_frob_label (sym);
5018
5019 ppc_current_block = sym;
5020
5021 demand_empty_rest_of_line ();
5022}
5023
5024/* The .es pseudo-op. Generate a C_ESTART symbol named .es. */
5025
5026static void
5027ppc_es (int ignore ATTRIBUTE_UNUSED)
5028{
5029 symbolS *sym;
5030
5031 if (ppc_current_block == NULL)
5032 as_bad (_(".es without preceding .bs"));
5033
5034 sym = symbol_make (".es");
5035 S_SET_SEGMENT (sym, now_seg);
5036 S_SET_STORAGE_CLASS (sym, C_ESTAT);
5037 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
5038 symbol_get_tc (sym)->output = 1;
5039
5040 ppc_frob_label (sym);
5041
5042 ppc_current_block = NULL;
5043
5044 demand_empty_rest_of_line ();
5045}
5046
5047/* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a
5048 line number. */
5049
5050static void
5051ppc_bb (int ignore ATTRIBUTE_UNUSED)
5052{
5053 symbolS *sym;
5054
5055 sym = symbol_make (".bb");
5056 S_SET_SEGMENT (sym, text_section);
5057 symbol_set_frag (sym, frag_now);
5058 S_SET_VALUE (sym, frag_now_fix ());
5059 S_SET_STORAGE_CLASS (sym, C_BLOCK);
5060
5061 S_SET_NUMBER_AUXILIARY (sym, 1);
5062 SA_SET_SYM_LNNO (sym, get_absolute_expression ());
5063
5064 symbol_get_tc (sym)->output = 1;
5065
5066 SF_SET_PROCESS (sym);
5067
5068 ppc_frob_label (sym);
5069
5070 demand_empty_rest_of_line ();
5071}
5072
5073/* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a
5074 line number. */
5075
5076static void
5077ppc_eb (int ignore ATTRIBUTE_UNUSED)
5078{
5079 symbolS *sym;
5080
5081 sym = symbol_make (".eb");
5082 S_SET_SEGMENT (sym, text_section);
5083 symbol_set_frag (sym, frag_now);
5084 S_SET_VALUE (sym, frag_now_fix ());
5085 S_SET_STORAGE_CLASS (sym, C_BLOCK);
5086 S_SET_NUMBER_AUXILIARY (sym, 1);
5087 SA_SET_SYM_LNNO (sym, get_absolute_expression ());
5088 symbol_get_tc (sym)->output = 1;
5089
5090 SF_SET_PROCESS (sym);
5091
5092 ppc_frob_label (sym);
5093
5094 demand_empty_rest_of_line ();
5095}
5096
5097/* The .bc pseudo-op. This just creates a C_BCOMM symbol with a
5098 specified name. */
5099
5100static void
5101ppc_bc (int ignore ATTRIBUTE_UNUSED)
5102{
5103 char *name;
5104 int len;
5105 symbolS *sym;
5106
5107 name = demand_copy_C_string (&len);
5108 sym = symbol_make (name);
5109 S_SET_SEGMENT (sym, ppc_coff_debug_section);
5110 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
5111 S_SET_STORAGE_CLASS (sym, C_BCOMM);
5112 S_SET_VALUE (sym, 0);
5113 symbol_get_tc (sym)->output = 1;
5114
5115 ppc_frob_label (sym);
5116
5117 demand_empty_rest_of_line ();
5118}
5119
5120/* The .ec pseudo-op. This just creates a C_ECOMM symbol. */
5121
5122static void
5123ppc_ec (int ignore ATTRIBUTE_UNUSED)
5124{
5125 symbolS *sym;
5126
5127 sym = symbol_make (".ec");
5128 S_SET_SEGMENT (sym, ppc_coff_debug_section);
5129 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
5130 S_SET_STORAGE_CLASS (sym, C_ECOMM);
5131 S_SET_VALUE (sym, 0);
5132 symbol_get_tc (sym)->output = 1;
5133
5134 ppc_frob_label (sym);
5135
5136 demand_empty_rest_of_line ();
5137}
5138
5139/* The .toc pseudo-op. Switch to the .toc subsegment. */
5140
5141static void
5142ppc_toc (int ignore ATTRIBUTE_UNUSED)
5143{
5144 if (ppc_toc_csect != (symbolS *) NULL)
5145 subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg);
5146 else
5147 {
5148 subsegT subseg;
5149 symbolS *sym;
5150 symbolS *list;
5151
5152 subseg = ppc_data_subsegment;
5153 ++ppc_data_subsegment;
5154
5155 subseg_new (segment_name (data_section), subseg);
5156 ppc_toc_frag = frag_now;
5157
5158 sym = symbol_find_or_make ("TOC[TC0]");
5159 symbol_set_frag (sym, frag_now);
5160 S_SET_SEGMENT (sym, data_section);
5161 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5162 symbol_get_tc (sym)->subseg = subseg;
5163 symbol_get_tc (sym)->output = 1;
5164 symbol_get_tc (sym)->within = sym;
5165
5166 ppc_toc_csect = sym;
5167
5168 for (list = ppc_data_csects;
5169 symbol_get_tc (list)->next != (symbolS *) NULL;
5170 list = symbol_get_tc (list)->next)
5171 ;
5172 symbol_get_tc (list)->next = sym;
5173
5174 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
5175 symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP,
5176 &symbol_lastP);
5177 }
5178
5179 ppc_current_csect = ppc_toc_csect;
5180
5181 demand_empty_rest_of_line ();
5182}
5183
5184/* The AIX assembler automatically aligns the operands of a .long or
5185 .short pseudo-op, and we want to be compatible. */
5186
5187static void
5188ppc_xcoff_cons (int log_size)
5189{
5190 frag_align (log_size, 0, 0);
5191 record_alignment (now_seg, log_size);
5192 cons (1 << log_size);
5193}
5194
5195static void
5196ppc_vbyte (int dummy ATTRIBUTE_UNUSED)
5197{
5198 expressionS exp;
5199 int byte_count;
5200
5201 (void) expression (&exp);
5202
5203 if (exp.X_op != O_constant)
5204 {
5205 as_bad (_("non-constant byte count"));
5206 return;
5207 }
5208
5209 byte_count = exp.X_add_number;
5210
5211 if (*input_line_pointer != ',')
5212 {
5213 as_bad (_("missing value"));
5214 return;
5215 }
5216
5217 ++input_line_pointer;
5218 cons (byte_count);
5219}
5220
5221void
5222ppc_xcoff_end (void)
5223{
5224 int i;
5225
5226 for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++)
5227 {
5228 struct dw_section *dws = &dw_sections[i];
5229 struct dw_subsection *dwss;
5230
5231 if (dws->anon_subseg)
5232 {
5233 dwss = dws->anon_subseg;
5234 dwss->link = dws->list_subseg;
5235 }
5236 else
5237 dwss = dws->list_subseg;
5238
5239 for (; dwss != NULL; dwss = dwss->link)
5240 if (dwss->end_exp.X_add_symbol != NULL)
5241 {
5242 subseg_set (dws->sect, dwss->subseg);
5243 symbol_set_value_now (dwss->end_exp.X_add_symbol);
5244 }
5245 }
5246}
5247
5248#endif /* OBJ_XCOFF */
5249#if defined (OBJ_XCOFF) || defined (OBJ_ELF)
5250\f
5251/* The .tc pseudo-op. This is used when generating either XCOFF or
5252 ELF. This takes two or more arguments.
5253
5254 When generating XCOFF output, the first argument is the name to
5255 give to this location in the toc; this will be a symbol with class
5256 TC. The rest of the arguments are N-byte values to actually put at
5257 this location in the TOC; often there is just one more argument, a
5258 relocatable symbol reference. The size of the value to store
5259 depends on target word size. A 32-bit target uses 4-byte values, a
5260 64-bit target uses 8-byte values.
5261
5262 When not generating XCOFF output, the arguments are the same, but
5263 the first argument is simply ignored. */
5264
5265static void
5266ppc_tc (int ignore ATTRIBUTE_UNUSED)
5267{
5268#ifdef OBJ_XCOFF
5269
5270 /* Define the TOC symbol name. */
5271 {
5272 char *name;
5273 char endc;
5274 symbolS *sym;
5275
5276 if (ppc_toc_csect == (symbolS *) NULL
5277 || ppc_toc_csect != ppc_current_csect)
5278 {
5279 as_bad (_(".tc not in .toc section"));
5280 ignore_rest_of_line ();
5281 return;
5282 }
5283
5284 endc = get_symbol_name (&name);
5285
5286 sym = symbol_find_or_make (name);
5287
5288 (void) restore_line_pointer (endc);
5289
5290 if (S_IS_DEFINED (sym))
5291 {
5292 symbolS *label;
5293
5294 label = symbol_get_tc (ppc_current_csect)->within;
5295 if (symbol_get_tc (label)->symbol_class != XMC_TC0)
5296 {
5297 as_bad (_(".tc with no label"));
5298 ignore_rest_of_line ();
5299 return;
5300 }
5301
5302 S_SET_SEGMENT (label, S_GET_SEGMENT (sym));
5303 symbol_set_frag (label, symbol_get_frag (sym));
5304 S_SET_VALUE (label, S_GET_VALUE (sym));
5305
5306 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5307 ++input_line_pointer;
5308
5309 return;
5310 }
5311
5312 S_SET_SEGMENT (sym, now_seg);
5313 symbol_set_frag (sym, frag_now);
5314 S_SET_VALUE (sym, (valueT) frag_now_fix ());
5315 symbol_get_tc (sym)->symbol_class = XMC_TC;
5316 symbol_get_tc (sym)->output = 1;
5317
5318 ppc_frob_label (sym);
5319 }
5320
5321#endif /* OBJ_XCOFF */
5322#ifdef OBJ_ELF
5323 int align;
5324
5325 /* Skip the TOC symbol name. */
5326 while (is_part_of_name (*input_line_pointer)
5327 || *input_line_pointer == ' '
5328 || *input_line_pointer == '['
5329 || *input_line_pointer == ']'
5330 || *input_line_pointer == '{'
5331 || *input_line_pointer == '}')
5332 ++input_line_pointer;
5333
5334 /* Align to a four/eight byte boundary. */
5335 align = ppc_obj64 ? 3 : 2;
5336 frag_align (align, 0, 0);
5337 record_alignment (now_seg, align);
5338#endif /* OBJ_ELF */
5339
5340 if (*input_line_pointer != ',')
5341 demand_empty_rest_of_line ();
5342 else
5343 {
5344 ++input_line_pointer;
5345 cons (ppc_obj64 ? 8 : 4);
5346 }
5347}
5348
5349/* Pseudo-op .machine. */
5350
5351static void
5352ppc_machine (int ignore ATTRIBUTE_UNUSED)
5353{
5354 char c;
5355 char *cpu_string;
5356#define MAX_HISTORY 100
5357 static ppc_cpu_t *cpu_history;
5358 static int curr_hist;
5359
5360 SKIP_WHITESPACE ();
5361
5362 c = get_symbol_name (&cpu_string);
5363 cpu_string = xstrdup (cpu_string);
5364 (void) restore_line_pointer (c);
5365
5366 if (cpu_string != NULL)
5367 {
5368 ppc_cpu_t old_cpu = ppc_cpu;
5369 ppc_cpu_t new_cpu;
5370 char *p;
5371
5372 for (p = cpu_string; *p != 0; p++)
5373 *p = TOLOWER (*p);
5374
5375 if (strcmp (cpu_string, "push") == 0)
5376 {
5377 if (cpu_history == NULL)
5378 cpu_history = XNEWVEC (ppc_cpu_t, MAX_HISTORY);
5379
5380 if (curr_hist >= MAX_HISTORY)
5381 as_bad (_(".machine stack overflow"));
5382 else
5383 cpu_history[curr_hist++] = ppc_cpu;
5384 }
5385 else if (strcmp (cpu_string, "pop") == 0)
5386 {
5387 if (curr_hist <= 0)
5388 as_bad (_(".machine stack underflow"));
5389 else
5390 ppc_cpu = cpu_history[--curr_hist];
5391 }
5392 else if ((new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, cpu_string)) != 0)
5393 ppc_cpu = new_cpu;
5394 else
5395 as_bad (_("invalid machine `%s'"), cpu_string);
5396
5397 if (ppc_cpu != old_cpu)
5398 ppc_setup_opcodes ();
5399 }
5400
5401 demand_empty_rest_of_line ();
5402}
5403#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
5404\f
5405#ifdef TE_PE
5406
5407/* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */
5408
5409/* Set the current section. */
5410static void
5411ppc_set_current_section (segT new)
5412{
5413 ppc_previous_section = ppc_current_section;
5414 ppc_current_section = new;
5415}
5416
5417/* pseudo-op: .previous
5418 behaviour: toggles the current section with the previous section.
5419 errors: None
5420 warnings: "No previous section" */
5421
5422static void
5423ppc_previous (int ignore ATTRIBUTE_UNUSED)
5424{
5425 if (ppc_previous_section == NULL)
5426 {
5427 as_warn (_("no previous section to return to, ignored."));
5428 return;
5429 }
5430
5431 subseg_set (ppc_previous_section, 0);
5432
5433 ppc_set_current_section (ppc_previous_section);
5434}
5435
5436/* pseudo-op: .pdata
5437 behaviour: predefined read only data section
5438 double word aligned
5439 errors: None
5440 warnings: None
5441 initial: .section .pdata "adr3"
5442 a - don't know -- maybe a misprint
5443 d - initialized data
5444 r - readable
5445 3 - double word aligned (that would be 4 byte boundary)
5446
5447 commentary:
5448 Tag index tables (also known as the function table) for exception
5449 handling, debugging, etc. */
5450
5451static void
5452ppc_pdata (int ignore ATTRIBUTE_UNUSED)
5453{
5454 if (pdata_section == 0)
5455 {
5456 pdata_section = subseg_new (".pdata", 0);
5457
5458 bfd_set_section_flags (stdoutput, pdata_section,
5459 (SEC_ALLOC | SEC_LOAD | SEC_RELOC
5460 | SEC_READONLY | SEC_DATA ));
5461
5462 bfd_set_section_alignment (stdoutput, pdata_section, 2);
5463 }
5464 else
5465 {
5466 pdata_section = subseg_new (".pdata", 0);
5467 }
5468 ppc_set_current_section (pdata_section);
5469}
5470
5471/* pseudo-op: .ydata
5472 behaviour: predefined read only data section
5473 double word aligned
5474 errors: None
5475 warnings: None
5476 initial: .section .ydata "drw3"
5477 a - don't know -- maybe a misprint
5478 d - initialized data
5479 r - readable
5480 3 - double word aligned (that would be 4 byte boundary)
5481 commentary:
5482 Tag tables (also known as the scope table) for exception handling,
5483 debugging, etc. */
5484
5485static void
5486ppc_ydata (int ignore ATTRIBUTE_UNUSED)
5487{
5488 if (ydata_section == 0)
5489 {
5490 ydata_section = subseg_new (".ydata", 0);
5491 bfd_set_section_flags (stdoutput, ydata_section,
5492 (SEC_ALLOC | SEC_LOAD | SEC_RELOC
5493 | SEC_READONLY | SEC_DATA ));
5494
5495 bfd_set_section_alignment (stdoutput, ydata_section, 3);
5496 }
5497 else
5498 {
5499 ydata_section = subseg_new (".ydata", 0);
5500 }
5501 ppc_set_current_section (ydata_section);
5502}
5503
5504/* pseudo-op: .reldata
5505 behaviour: predefined read write data section
5506 double word aligned (4-byte)
5507 FIXME: relocation is applied to it
5508 FIXME: what's the difference between this and .data?
5509 errors: None
5510 warnings: None
5511 initial: .section .reldata "drw3"
5512 d - initialized data
5513 r - readable
5514 w - writable
5515 3 - double word aligned (that would be 8 byte boundary)
5516
5517 commentary:
5518 Like .data, but intended to hold data subject to relocation, such as
5519 function descriptors, etc. */
5520
5521static void
5522ppc_reldata (int ignore ATTRIBUTE_UNUSED)
5523{
5524 if (reldata_section == 0)
5525 {
5526 reldata_section = subseg_new (".reldata", 0);
5527
5528 bfd_set_section_flags (stdoutput, reldata_section,
5529 (SEC_ALLOC | SEC_LOAD | SEC_RELOC
5530 | SEC_DATA));
5531
5532 bfd_set_section_alignment (stdoutput, reldata_section, 2);
5533 }
5534 else
5535 {
5536 reldata_section = subseg_new (".reldata", 0);
5537 }
5538 ppc_set_current_section (reldata_section);
5539}
5540
5541/* pseudo-op: .rdata
5542 behaviour: predefined read only data section
5543 double word aligned
5544 errors: None
5545 warnings: None
5546 initial: .section .rdata "dr3"
5547 d - initialized data
5548 r - readable
5549 3 - double word aligned (that would be 4 byte boundary) */
5550
5551static void
5552ppc_rdata (int ignore ATTRIBUTE_UNUSED)
5553{
5554 if (rdata_section == 0)
5555 {
5556 rdata_section = subseg_new (".rdata", 0);
5557 bfd_set_section_flags (stdoutput, rdata_section,
5558 (SEC_ALLOC | SEC_LOAD | SEC_RELOC
5559 | SEC_READONLY | SEC_DATA ));
5560
5561 bfd_set_section_alignment (stdoutput, rdata_section, 2);
5562 }
5563 else
5564 {
5565 rdata_section = subseg_new (".rdata", 0);
5566 }
5567 ppc_set_current_section (rdata_section);
5568}
5569
5570/* pseudo-op: .ualong
5571 behaviour: much like .int, with the exception that no alignment is
5572 performed.
5573 FIXME: test the alignment statement
5574 errors: None
5575 warnings: None */
5576
5577static void
5578ppc_ualong (int ignore ATTRIBUTE_UNUSED)
5579{
5580 /* Try for long. */
5581 cons (4);
5582}
5583
5584/* pseudo-op: .znop <symbol name>
5585 behaviour: Issue a nop instruction
5586 Issue a IMAGE_REL_PPC_IFGLUE relocation against it, using
5587 the supplied symbol name.
5588 errors: None
5589 warnings: Missing symbol name */
5590
5591static void
5592ppc_znop (int ignore ATTRIBUTE_UNUSED)
5593{
5594 unsigned long insn;
5595 const struct powerpc_opcode *opcode;
5596 char *f;
5597 symbolS *sym;
5598 char *symbol_name;
5599 char c;
5600 char *name;
5601
5602 /* Strip out the symbol name. */
5603 c = get_symbol_name (&symbol_name);
5604
5605 name = xstrdup (symbol_name);
5606
5607 sym = symbol_find_or_make (name);
5608
5609 *input_line_pointer = c;
5610
5611 SKIP_WHITESPACE_AFTER_NAME ();
5612
5613 /* Look up the opcode in the hash table. */
5614 opcode = (const struct powerpc_opcode *) hash_find (ppc_hash, "nop");
5615
5616 /* Stick in the nop. */
5617 insn = opcode->opcode;
5618
5619 /* Write out the instruction. */
5620 f = frag_more (4);
5621 md_number_to_chars (f, insn, 4);
5622 fix_new (frag_now,
5623 f - frag_now->fr_literal,
5624 4,
5625 sym,
5626 0,
5627 0,
5628 BFD_RELOC_16_GOT_PCREL);
5629
5630}
5631
5632/* pseudo-op:
5633 behaviour:
5634 errors:
5635 warnings: */
5636
5637static void
5638ppc_pe_comm (int lcomm)
5639{
5640 char *name;
5641 char c;
5642 char *p;
5643 offsetT temp;
5644 symbolS *symbolP;
5645 offsetT align;
5646
5647 c = get_symbol_name (&name);
5648
5649 /* just after name is now '\0'. */
5650 p = input_line_pointer;
5651 *p = c;
5652 SKIP_WHITESPACE_AFTER_NAME ();
5653 if (*input_line_pointer != ',')
5654 {
5655 as_bad (_("expected comma after symbol-name: rest of line ignored."));
5656 ignore_rest_of_line ();
5657 return;
5658 }
5659
5660 input_line_pointer++; /* skip ',' */
5661 if ((temp = get_absolute_expression ()) < 0)
5662 {
5663 as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) temp);
5664 ignore_rest_of_line ();
5665 return;
5666 }
5667
5668 if (! lcomm)
5669 {
5670 /* The third argument to .comm is the alignment. */
5671 if (*input_line_pointer != ',')
5672 align = 3;
5673 else
5674 {
5675 ++input_line_pointer;
5676 align = get_absolute_expression ();
5677 if (align <= 0)
5678 {
5679 as_warn (_("ignoring bad alignment"));
5680 align = 3;
5681 }
5682 }
5683 }
5684
5685 *p = 0;
5686 symbolP = symbol_find_or_make (name);
5687
5688 *p = c;
5689 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
5690 {
5691 as_bad (_("ignoring attempt to re-define symbol `%s'."),
5692 S_GET_NAME (symbolP));
5693 ignore_rest_of_line ();
5694 return;
5695 }
5696
5697 if (S_GET_VALUE (symbolP))
5698 {
5699 if (S_GET_VALUE (symbolP) != (valueT) temp)
5700 as_bad (_("length of .comm \"%s\" is already %ld. Not changed to %ld."),
5701 S_GET_NAME (symbolP),
5702 (long) S_GET_VALUE (symbolP),
5703 (long) temp);
5704 }
5705 else
5706 {
5707 S_SET_VALUE (symbolP, (valueT) temp);
5708 S_SET_EXTERNAL (symbolP);
5709 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
5710 }
5711
5712 demand_empty_rest_of_line ();
5713}
5714
5715/*
5716 * implement the .section pseudo op:
5717 * .section name {, "flags"}
5718 * ^ ^
5719 * | +--- optional flags: 'b' for bss
5720 * | 'i' for info
5721 * +-- section name 'l' for lib
5722 * 'n' for noload
5723 * 'o' for over
5724 * 'w' for data
5725 * 'd' (apparently m88k for data)
5726 * 'x' for text
5727 * But if the argument is not a quoted string, treat it as a
5728 * subsegment number.
5729 *
5730 * FIXME: this is a copy of the section processing from obj-coff.c, with
5731 * additions/changes for the moto-pas assembler support. There are three
5732 * categories:
5733 *
5734 * FIXME: I just noticed this. This doesn't work at all really. It it
5735 * setting bits that bfd probably neither understands or uses. The
5736 * correct approach (?) will have to incorporate extra fields attached
5737 * to the section to hold the system specific stuff. (krk)
5738 *
5739 * Section Contents:
5740 * 'a' - unknown - referred to in documentation, but no definition supplied
5741 * 'c' - section has code
5742 * 'd' - section has initialized data
5743 * 'u' - section has uninitialized data
5744 * 'i' - section contains directives (info)
5745 * 'n' - section can be discarded
5746 * 'R' - remove section at link time
5747 *
5748 * Section Protection:
5749 * 'r' - section is readable
5750 * 'w' - section is writable
5751 * 'x' - section is executable
5752 * 's' - section is sharable
5753 *
5754 * Section Alignment:
5755 * '0' - align to byte boundary
5756 * '1' - align to halfword boundary
5757 * '2' - align to word boundary
5758 * '3' - align to doubleword boundary
5759 * '4' - align to quadword boundary
5760 * '5' - align to 32 byte boundary
5761 * '6' - align to 64 byte boundary
5762 *
5763 */
5764
5765void
5766ppc_pe_section (int ignore ATTRIBUTE_UNUSED)
5767{
5768 /* Strip out the section name. */
5769 char *section_name;
5770 char c;
5771 char *name;
5772 unsigned int exp;
5773 flagword flags;
5774 segT sec;
5775 int align;
5776
5777 c = get_symbol_name (&section_name);
5778
5779 name = xstrdup (section_name);
5780
5781 *input_line_pointer = c;
5782
5783 SKIP_WHITESPACE_AFTER_NAME ();
5784
5785 exp = 0;
5786 flags = SEC_NO_FLAGS;
5787
5788 if (strcmp (name, ".idata$2") == 0)
5789 {
5790 align = 0;
5791 }
5792 else if (strcmp (name, ".idata$3") == 0)
5793 {
5794 align = 0;
5795 }
5796 else if (strcmp (name, ".idata$4") == 0)
5797 {
5798 align = 2;
5799 }
5800 else if (strcmp (name, ".idata$5") == 0)
5801 {
5802 align = 2;
5803 }
5804 else if (strcmp (name, ".idata$6") == 0)
5805 {
5806 align = 1;
5807 }
5808 else
5809 /* Default alignment to 16 byte boundary. */
5810 align = 4;
5811
5812 if (*input_line_pointer == ',')
5813 {
5814 ++input_line_pointer;
5815 SKIP_WHITESPACE ();
5816 if (*input_line_pointer != '"')
5817 exp = get_absolute_expression ();
5818 else
5819 {
5820 ++input_line_pointer;
5821 while (*input_line_pointer != '"'
5822 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5823 {
5824 switch (*input_line_pointer)
5825 {
5826 /* Section Contents */
5827 case 'a': /* unknown */
5828 as_bad (_("unsupported section attribute -- 'a'"));
5829 break;
5830 case 'c': /* code section */
5831 flags |= SEC_CODE;
5832 break;
5833 case 'd': /* section has initialized data */
5834 flags |= SEC_DATA;
5835 break;
5836 case 'u': /* section has uninitialized data */
5837 /* FIXME: This is IMAGE_SCN_CNT_UNINITIALIZED_DATA
5838 in winnt.h */
5839 flags |= SEC_ROM;
5840 break;
5841 case 'i': /* section contains directives (info) */
5842 /* FIXME: This is IMAGE_SCN_LNK_INFO
5843 in winnt.h */
5844 flags |= SEC_HAS_CONTENTS;
5845 break;
5846 case 'n': /* section can be discarded */
5847 flags &=~ SEC_LOAD;
5848 break;
5849 case 'R': /* Remove section at link time */
5850 flags |= SEC_NEVER_LOAD;
5851 break;
5852#if IFLICT_BRAIN_DAMAGE
5853 /* Section Protection */
5854 case 'r': /* section is readable */
5855 flags |= IMAGE_SCN_MEM_READ;
5856 break;
5857 case 'w': /* section is writable */
5858 flags |= IMAGE_SCN_MEM_WRITE;
5859 break;
5860 case 'x': /* section is executable */
5861 flags |= IMAGE_SCN_MEM_EXECUTE;
5862 break;
5863 case 's': /* section is sharable */
5864 flags |= IMAGE_SCN_MEM_SHARED;
5865 break;
5866
5867 /* Section Alignment */
5868 case '0': /* align to byte boundary */
5869 flags |= IMAGE_SCN_ALIGN_1BYTES;
5870 align = 0;
5871 break;
5872 case '1': /* align to halfword boundary */
5873 flags |= IMAGE_SCN_ALIGN_2BYTES;
5874 align = 1;
5875 break;
5876 case '2': /* align to word boundary */
5877 flags |= IMAGE_SCN_ALIGN_4BYTES;
5878 align = 2;
5879 break;
5880 case '3': /* align to doubleword boundary */
5881 flags |= IMAGE_SCN_ALIGN_8BYTES;
5882 align = 3;
5883 break;
5884 case '4': /* align to quadword boundary */
5885 flags |= IMAGE_SCN_ALIGN_16BYTES;
5886 align = 4;
5887 break;
5888 case '5': /* align to 32 byte boundary */
5889 flags |= IMAGE_SCN_ALIGN_32BYTES;
5890 align = 5;
5891 break;
5892 case '6': /* align to 64 byte boundary */
5893 flags |= IMAGE_SCN_ALIGN_64BYTES;
5894 align = 6;
5895 break;
5896#endif
5897 default:
5898 as_bad (_("unknown section attribute '%c'"),
5899 *input_line_pointer);
5900 break;
5901 }
5902 ++input_line_pointer;
5903 }
5904 if (*input_line_pointer == '"')
5905 ++input_line_pointer;
5906 }
5907 }
5908
5909 sec = subseg_new (name, (subsegT) exp);
5910
5911 ppc_set_current_section (sec);
5912
5913 if (flags != SEC_NO_FLAGS)
5914 {
5915 if (! bfd_set_section_flags (stdoutput, sec, flags))
5916 as_bad (_("error setting flags for \"%s\": %s"),
5917 bfd_section_name (stdoutput, sec),
5918 bfd_errmsg (bfd_get_error ()));
5919 }
5920
5921 bfd_set_section_alignment (stdoutput, sec, align);
5922}
5923
5924static void
5925ppc_pe_function (int ignore ATTRIBUTE_UNUSED)
5926{
5927 char *name;
5928 char endc;
5929 symbolS *ext_sym;
5930
5931 endc = get_symbol_name (&name);
5932
5933 ext_sym = symbol_find_or_make (name);
5934
5935 (void) restore_line_pointer (endc);
5936
5937 S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT);
5938 SF_SET_FUNCTION (ext_sym);
5939 SF_SET_PROCESS (ext_sym);
5940 coff_add_linesym (ext_sym);
5941
5942 demand_empty_rest_of_line ();
5943}
5944
5945static void
5946ppc_pe_tocd (int ignore ATTRIBUTE_UNUSED)
5947{
5948 if (tocdata_section == 0)
5949 {
5950 tocdata_section = subseg_new (".tocd", 0);
5951 /* FIXME: section flags won't work. */
5952 bfd_set_section_flags (stdoutput, tocdata_section,
5953 (SEC_ALLOC | SEC_LOAD | SEC_RELOC
5954 | SEC_READONLY | SEC_DATA));
5955
5956 bfd_set_section_alignment (stdoutput, tocdata_section, 2);
5957 }
5958 else
5959 {
5960 rdata_section = subseg_new (".tocd", 0);
5961 }
5962
5963 ppc_set_current_section (tocdata_section);
5964
5965 demand_empty_rest_of_line ();
5966}
5967
5968/* Don't adjust TOC relocs to use the section symbol. */
5969
5970int
5971ppc_pe_fix_adjustable (fixS *fix)
5972{
5973 return fix->fx_r_type != BFD_RELOC_PPC_TOC16;
5974}
5975
5976#endif
5977\f
5978#ifdef OBJ_XCOFF
5979
5980/* XCOFF specific symbol and file handling. */
5981
5982/* Canonicalize the symbol name. We use the to force the suffix, if
5983 any, to use square brackets, and to be in upper case. */
5984
5985char *
5986ppc_canonicalize_symbol_name (char *name)
5987{
5988 char *s;
5989
5990 if (ppc_stab_symbol)
5991 return name;
5992
5993 for (s = name; *s != '\0' && *s != '{' && *s != '['; s++)
5994 ;
5995 if (*s != '\0')
5996 {
5997 char brac;
5998
5999 if (*s == '[')
6000 brac = ']';
6001 else
6002 {
6003 *s = '[';
6004 brac = '}';
6005 }
6006
6007 for (s++; *s != '\0' && *s != brac; s++)
6008 *s = TOUPPER (*s);
6009
6010 if (*s == '\0' || s[1] != '\0')
6011 as_bad (_("bad symbol suffix"));
6012
6013 *s = ']';
6014 }
6015
6016 return name;
6017}
6018
6019/* Set the class of a symbol based on the suffix, if any. This is
6020 called whenever a new symbol is created. */
6021
6022void
6023ppc_symbol_new_hook (symbolS *sym)
6024{
6025 struct ppc_tc_sy *tc;
6026 const char *s;
6027
6028 tc = symbol_get_tc (sym);
6029 tc->next = NULL;
6030 tc->output = 0;
6031 tc->symbol_class = -1;
6032 tc->real_name = NULL;
6033 tc->subseg = 0;
6034 tc->align = 0;
6035 tc->u.size = NULL;
6036 tc->u.dw = NULL;
6037 tc->within = NULL;
6038
6039 if (ppc_stab_symbol)
6040 return;
6041
6042 s = strchr (S_GET_NAME (sym), '[');
6043 if (s == (const char *) NULL)
6044 {
6045 /* There is no suffix. */
6046 return;
6047 }
6048
6049 ++s;
6050
6051 switch (s[0])
6052 {
6053 case 'B':
6054 if (strcmp (s, "BS]") == 0)
6055 tc->symbol_class = XMC_BS;
6056 break;
6057 case 'D':
6058 if (strcmp (s, "DB]") == 0)
6059 tc->symbol_class = XMC_DB;
6060 else if (strcmp (s, "DS]") == 0)
6061 tc->symbol_class = XMC_DS;
6062 break;
6063 case 'G':
6064 if (strcmp (s, "GL]") == 0)
6065 tc->symbol_class = XMC_GL;
6066 break;
6067 case 'P':
6068 if (strcmp (s, "PR]") == 0)
6069 tc->symbol_class = XMC_PR;
6070 break;
6071 case 'R':
6072 if (strcmp (s, "RO]") == 0)
6073 tc->symbol_class = XMC_RO;
6074 else if (strcmp (s, "RW]") == 0)
6075 tc->symbol_class = XMC_RW;
6076 break;
6077 case 'S':
6078 if (strcmp (s, "SV]") == 0)
6079 tc->symbol_class = XMC_SV;
6080 break;
6081 case 'T':
6082 if (strcmp (s, "TC]") == 0)
6083 tc->symbol_class = XMC_TC;
6084 else if (strcmp (s, "TI]") == 0)
6085 tc->symbol_class = XMC_TI;
6086 else if (strcmp (s, "TB]") == 0)
6087 tc->symbol_class = XMC_TB;
6088 else if (strcmp (s, "TC0]") == 0 || strcmp (s, "T0]") == 0)
6089 tc->symbol_class = XMC_TC0;
6090 break;
6091 case 'U':
6092 if (strcmp (s, "UA]") == 0)
6093 tc->symbol_class = XMC_UA;
6094 else if (strcmp (s, "UC]") == 0)
6095 tc->symbol_class = XMC_UC;
6096 break;
6097 case 'X':
6098 if (strcmp (s, "XO]") == 0)
6099 tc->symbol_class = XMC_XO;
6100 break;
6101 }
6102
6103 if (tc->symbol_class == -1)
6104 as_bad (_("unrecognized symbol suffix"));
6105}
6106
6107/* Set the class of a label based on where it is defined. This
6108 handles symbols without suffixes. Also, move the symbol so that it
6109 follows the csect symbol. */
6110
6111void
6112ppc_frob_label (symbolS *sym)
6113{
6114 if (ppc_current_csect != (symbolS *) NULL)
6115 {
6116 if (symbol_get_tc (sym)->symbol_class == -1)
6117 symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class;
6118
6119 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
6120 symbol_append (sym, symbol_get_tc (ppc_current_csect)->within,
6121 &symbol_rootP, &symbol_lastP);
6122 symbol_get_tc (ppc_current_csect)->within = sym;
6123 symbol_get_tc (sym)->within = ppc_current_csect;
6124 }
6125
6126#ifdef OBJ_ELF
6127 dwarf2_emit_label (sym);
6128#endif
6129}
6130
6131/* This variable is set by ppc_frob_symbol if any absolute symbols are
6132 seen. It tells ppc_adjust_symtab whether it needs to look through
6133 the symbols. */
6134
6135static bfd_boolean ppc_saw_abs;
6136
6137/* Change the name of a symbol just before writing it out. Set the
6138 real name if the .rename pseudo-op was used. Otherwise, remove any
6139 class suffix. Return 1 if the symbol should not be included in the
6140 symbol table. */
6141
6142int
6143ppc_frob_symbol (symbolS *sym)
6144{
6145 static symbolS *ppc_last_function;
6146 static symbolS *set_end;
6147
6148 /* Discard symbols that should not be included in the output symbol
6149 table. */
6150 if (! symbol_used_in_reloc_p (sym)
6151 && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0
6152 || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym))
6153 && ! symbol_get_tc (sym)->output
6154 && S_GET_STORAGE_CLASS (sym) != C_FILE)))
6155 return 1;
6156
6157 /* This one will disappear anyway. Don't make a csect sym for it. */
6158 if (sym == abs_section_sym)
6159 return 1;
6160
6161 if (symbol_get_tc (sym)->real_name != (char *) NULL)
6162 S_SET_NAME (sym, symbol_get_tc (sym)->real_name);
6163 else
6164 {
6165 const char *name;
6166 const char *s;
6167
6168 name = S_GET_NAME (sym);
6169 s = strchr (name, '[');
6170 if (s != (char *) NULL)
6171 {
6172 unsigned int len;
6173 char *snew;
6174
6175 len = s - name;
6176 snew = xstrndup (name, len);
6177
6178 S_SET_NAME (sym, snew);
6179 }
6180 }
6181
6182 if (set_end != (symbolS *) NULL)
6183 {
6184 SA_SET_SYM_ENDNDX (set_end, sym);
6185 set_end = NULL;
6186 }
6187
6188 if (SF_GET_FUNCTION (sym))
6189 {
6190 if (ppc_last_function != (symbolS *) NULL)
6191 as_bad (_("two .function pseudo-ops with no intervening .ef"));
6192 ppc_last_function = sym;
6193 if (symbol_get_tc (sym)->u.size != (symbolS *) NULL)
6194 {
6195 resolve_symbol_value (symbol_get_tc (sym)->u.size);
6196 SA_SET_SYM_FSIZE (sym,
6197 (long) S_GET_VALUE (symbol_get_tc (sym)->u.size));
6198 }
6199 }
6200 else if (S_GET_STORAGE_CLASS (sym) == C_FCN
6201 && strcmp (S_GET_NAME (sym), ".ef") == 0)
6202 {
6203 if (ppc_last_function == (symbolS *) NULL)
6204 as_bad (_(".ef with no preceding .function"));
6205 else
6206 {
6207 set_end = ppc_last_function;
6208 ppc_last_function = NULL;
6209
6210 /* We don't have a C_EFCN symbol, but we need to force the
6211 COFF backend to believe that it has seen one. */
6212 coff_last_function = NULL;
6213 }
6214 }
6215
6216 if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym))
6217 && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0
6218 && S_GET_STORAGE_CLASS (sym) != C_FILE
6219 && S_GET_STORAGE_CLASS (sym) != C_FCN
6220 && S_GET_STORAGE_CLASS (sym) != C_BLOCK
6221 && S_GET_STORAGE_CLASS (sym) != C_BSTAT
6222 && S_GET_STORAGE_CLASS (sym) != C_ESTAT
6223 && S_GET_STORAGE_CLASS (sym) != C_BINCL
6224 && S_GET_STORAGE_CLASS (sym) != C_EINCL
6225 && S_GET_SEGMENT (sym) != ppc_coff_debug_section)
6226 S_SET_STORAGE_CLASS (sym, C_HIDEXT);
6227
6228 if (S_GET_STORAGE_CLASS (sym) == C_EXT
6229 || S_GET_STORAGE_CLASS (sym) == C_AIX_WEAKEXT
6230 || S_GET_STORAGE_CLASS (sym) == C_HIDEXT)
6231 {
6232 int i;
6233 union internal_auxent *a;
6234
6235 /* Create a csect aux. */
6236 i = S_GET_NUMBER_AUXILIARY (sym);
6237 S_SET_NUMBER_AUXILIARY (sym, i + 1);
6238 a = &coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].u.auxent;
6239 if (symbol_get_tc (sym)->symbol_class == XMC_TC0)
6240 {
6241 /* This is the TOC table. */
6242 know (strcmp (S_GET_NAME (sym), "TOC") == 0);
6243 a->x_csect.x_scnlen.l = 0;
6244 a->x_csect.x_smtyp = (2 << 3) | XTY_SD;
6245 }
6246 else if (symbol_get_tc (sym)->subseg != 0)
6247 {
6248 /* This is a csect symbol. x_scnlen is the size of the
6249 csect. */
6250 if (symbol_get_tc (sym)->next == (symbolS *) NULL)
6251 a->x_csect.x_scnlen.l = (bfd_section_size (stdoutput,
6252 S_GET_SEGMENT (sym))
6253 - S_GET_VALUE (sym));
6254 else
6255 {
6256 resolve_symbol_value (symbol_get_tc (sym)->next);
6257 a->x_csect.x_scnlen.l = (S_GET_VALUE (symbol_get_tc (sym)->next)
6258 - S_GET_VALUE (sym));
6259 }
6260 a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_SD;
6261 }
6262 else if (S_GET_SEGMENT (sym) == bss_section)
6263 {
6264 /* This is a common symbol. */
6265 a->x_csect.x_scnlen.l = symbol_get_frag (sym)->fr_offset;
6266 a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM;
6267 if (S_IS_EXTERNAL (sym))
6268 symbol_get_tc (sym)->symbol_class = XMC_RW;
6269 else
6270 symbol_get_tc (sym)->symbol_class = XMC_BS;
6271 }
6272 else if (S_GET_SEGMENT (sym) == absolute_section)
6273 {
6274 /* This is an absolute symbol. The csect will be created by
6275 ppc_adjust_symtab. */
6276 ppc_saw_abs = TRUE;
6277 a->x_csect.x_smtyp = XTY_LD;
6278 if (symbol_get_tc (sym)->symbol_class == -1)
6279 symbol_get_tc (sym)->symbol_class = XMC_XO;
6280 }
6281 else if (! S_IS_DEFINED (sym))
6282 {
6283 /* This is an external symbol. */
6284 a->x_csect.x_scnlen.l = 0;
6285 a->x_csect.x_smtyp = XTY_ER;
6286 }
6287 else if (symbol_get_tc (sym)->symbol_class == XMC_TC)
6288 {
6289 symbolS *next;
6290
6291 /* This is a TOC definition. x_scnlen is the size of the
6292 TOC entry. */
6293 next = symbol_next (sym);
6294 while (symbol_get_tc (next)->symbol_class == XMC_TC0)
6295 next = symbol_next (next);
6296 if (next == (symbolS *) NULL
6297 || symbol_get_tc (next)->symbol_class != XMC_TC)
6298 {
6299 if (ppc_after_toc_frag == (fragS *) NULL)
6300 a->x_csect.x_scnlen.l = (bfd_section_size (stdoutput,
6301 data_section)
6302 - S_GET_VALUE (sym));
6303 else
6304 a->x_csect.x_scnlen.l = (ppc_after_toc_frag->fr_address
6305 - S_GET_VALUE (sym));
6306 }
6307 else
6308 {
6309 resolve_symbol_value (next);
6310 a->x_csect.x_scnlen.l = (S_GET_VALUE (next)
6311 - S_GET_VALUE (sym));
6312 }
6313 a->x_csect.x_smtyp = (2 << 3) | XTY_SD;
6314 }
6315 else
6316 {
6317 symbolS *csect;
6318
6319 /* This is a normal symbol definition. x_scnlen is the
6320 symbol index of the containing csect. */
6321 if (S_GET_SEGMENT (sym) == text_section)
6322 csect = ppc_text_csects;
6323 else if (S_GET_SEGMENT (sym) == data_section)
6324 csect = ppc_data_csects;
6325 else
6326 abort ();
6327
6328 /* Skip the initial dummy symbol. */
6329 csect = symbol_get_tc (csect)->next;
6330
6331 if (csect == (symbolS *) NULL)
6332 {
6333 as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym));
6334 a->x_csect.x_scnlen.l = 0;
6335 }
6336 else
6337 {
6338 while (symbol_get_tc (csect)->next != (symbolS *) NULL)
6339 {
6340 resolve_symbol_value (symbol_get_tc (csect)->next);
6341 if (S_GET_VALUE (symbol_get_tc (csect)->next)
6342 > S_GET_VALUE (sym))
6343 break;
6344 csect = symbol_get_tc (csect)->next;
6345 }
6346
6347 a->x_csect.x_scnlen.p =
6348 coffsymbol (symbol_get_bfdsym (csect))->native;
6349 coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].fix_scnlen =
6350 1;
6351 }
6352 a->x_csect.x_smtyp = XTY_LD;
6353 }
6354
6355 a->x_csect.x_parmhash = 0;
6356 a->x_csect.x_snhash = 0;
6357 if (symbol_get_tc (sym)->symbol_class == -1)
6358 a->x_csect.x_smclas = XMC_PR;
6359 else
6360 a->x_csect.x_smclas = symbol_get_tc (sym)->symbol_class;
6361 a->x_csect.x_stab = 0;
6362 a->x_csect.x_snstab = 0;
6363
6364 /* Don't let the COFF backend resort these symbols. */
6365 symbol_get_bfdsym (sym)->flags |= BSF_NOT_AT_END;
6366 }
6367 else if (S_GET_STORAGE_CLASS (sym) == C_BSTAT)
6368 {
6369 /* We want the value to be the symbol index of the referenced
6370 csect symbol. BFD will do that for us if we set the right
6371 flags. */
6372 asymbol *bsym = symbol_get_bfdsym (symbol_get_tc (sym)->within);
6373 combined_entry_type *c = coffsymbol (bsym)->native;
6374
6375 S_SET_VALUE (sym, (valueT) (size_t) c);
6376 coffsymbol (symbol_get_bfdsym (sym))->native->fix_value = 1;
6377 }
6378 else if (S_GET_STORAGE_CLASS (sym) == C_STSYM)
6379 {
6380 symbolS *block;
6381 valueT base;
6382
6383 block = symbol_get_tc (sym)->within;
6384 if (block)
6385 {
6386 /* The value is the offset from the enclosing csect. */
6387 symbolS *csect;
6388
6389 csect = symbol_get_tc (block)->within;
6390 resolve_symbol_value (csect);
6391 base = S_GET_VALUE (csect);
6392 }
6393 else
6394 base = 0;
6395
6396 S_SET_VALUE (sym, S_GET_VALUE (sym) - base);
6397 }
6398 else if (S_GET_STORAGE_CLASS (sym) == C_BINCL
6399 || S_GET_STORAGE_CLASS (sym) == C_EINCL)
6400 {
6401 /* We want the value to be a file offset into the line numbers.
6402 BFD will do that for us if we set the right flags. We have
6403 already set the value correctly. */
6404 coffsymbol (symbol_get_bfdsym (sym))->native->fix_line = 1;
6405 }
6406
6407 return 0;
6408}
6409
6410/* Adjust the symbol table. This creates csect symbols for all
6411 absolute symbols. */
6412
6413void
6414ppc_adjust_symtab (void)
6415{
6416 symbolS *sym;
6417
6418 if (! ppc_saw_abs)
6419 return;
6420
6421 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6422 {
6423 symbolS *csect;
6424 int i;
6425 union internal_auxent *a;
6426
6427 if (S_GET_SEGMENT (sym) != absolute_section)
6428 continue;
6429
6430 csect = symbol_create (".abs[XO]", absolute_section,
6431 S_GET_VALUE (sym), &zero_address_frag);
6432 symbol_get_bfdsym (csect)->value = S_GET_VALUE (sym);
6433 S_SET_STORAGE_CLASS (csect, C_HIDEXT);
6434 i = S_GET_NUMBER_AUXILIARY (csect);
6435 S_SET_NUMBER_AUXILIARY (csect, i + 1);
6436 a = &coffsymbol (symbol_get_bfdsym (csect))->native[i + 1].u.auxent;
6437 a->x_csect.x_scnlen.l = 0;
6438 a->x_csect.x_smtyp = XTY_SD;
6439 a->x_csect.x_parmhash = 0;
6440 a->x_csect.x_snhash = 0;
6441 a->x_csect.x_smclas = XMC_XO;
6442 a->x_csect.x_stab = 0;
6443 a->x_csect.x_snstab = 0;
6444
6445 symbol_insert (csect, sym, &symbol_rootP, &symbol_lastP);
6446
6447 i = S_GET_NUMBER_AUXILIARY (sym);
6448 a = &coffsymbol (symbol_get_bfdsym (sym))->native[i].u.auxent;
6449 a->x_csect.x_scnlen.p = coffsymbol (symbol_get_bfdsym (csect))->native;
6450 coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1;
6451 }
6452
6453 ppc_saw_abs = FALSE;
6454}
6455
6456/* Set the VMA for a section. This is called on all the sections in
6457 turn. */
6458
6459void
6460ppc_frob_section (asection *sec)
6461{
6462 static bfd_vma vma = 0;
6463
6464 /* Dwarf sections start at 0. */
6465 if (bfd_get_section_flags (NULL, sec) & SEC_DEBUGGING)
6466 return;
6467
6468 vma = md_section_align (sec, vma);
6469 bfd_set_section_vma (stdoutput, sec, vma);
6470 vma += bfd_section_size (stdoutput, sec);
6471}
6472
6473#endif /* OBJ_XCOFF */
6474\f
6475const char *
6476md_atof (int type, char *litp, int *sizep)
6477{
6478 return ieee_md_atof (type, litp, sizep, target_big_endian);
6479}
6480
6481/* Write a value out to the object file, using the appropriate
6482 endianness. */
6483
6484void
6485md_number_to_chars (char *buf, valueT val, int n)
6486{
6487 if (target_big_endian)
6488 number_to_chars_bigendian (buf, val, n);
6489 else
6490 number_to_chars_littleendian (buf, val, n);
6491}
6492
6493/* Align a section (I don't know why this is machine dependent). */
6494
6495valueT
6496md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr)
6497{
6498#ifdef OBJ_ELF
6499 return addr;
6500#else
6501 int align = bfd_get_section_alignment (stdoutput, seg);
6502
6503 return ((addr + (1 << align) - 1) & -(1 << align));
6504#endif
6505}
6506
6507/* We don't have any form of relaxing. */
6508
6509int
6510md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
6511 asection *seg ATTRIBUTE_UNUSED)
6512{
6513 abort ();
6514 return 0;
6515}
6516
6517/* Convert a machine dependent frag. We never generate these. */
6518
6519void
6520md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
6521 asection *sec ATTRIBUTE_UNUSED,
6522 fragS *fragp ATTRIBUTE_UNUSED)
6523{
6524 abort ();
6525}
6526
6527/* We have no need to default values of symbols. */
6528
6529symbolS *
6530md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
6531{
6532 return 0;
6533}
6534\f
6535/* Functions concerning relocs. */
6536
6537/* The location from which a PC relative jump should be calculated,
6538 given a PC relative reloc. */
6539
6540long
6541md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED)
6542{
6543 return fixp->fx_frag->fr_address + fixp->fx_where;
6544}
6545
6546#ifdef OBJ_XCOFF
6547
6548/* This is called to see whether a fixup should be adjusted to use a
6549 section symbol. We take the opportunity to change a fixup against
6550 a symbol in the TOC subsegment into a reloc against the
6551 corresponding .tc symbol. */
6552
6553int
6554ppc_fix_adjustable (fixS *fix)
6555{
6556 valueT val = resolve_symbol_value (fix->fx_addsy);
6557 segT symseg = S_GET_SEGMENT (fix->fx_addsy);
6558 TC_SYMFIELD_TYPE *tc;
6559
6560 if (symseg == absolute_section)
6561 return 0;
6562
6563 /* Always adjust symbols in debugging sections. */
6564 if (bfd_get_section_flags (stdoutput, symseg) & SEC_DEBUGGING)
6565 return 1;
6566
6567 if (ppc_toc_csect != (symbolS *) NULL
6568 && fix->fx_addsy != ppc_toc_csect
6569 && symseg == data_section
6570 && val >= ppc_toc_frag->fr_address
6571 && (ppc_after_toc_frag == (fragS *) NULL
6572 || val < ppc_after_toc_frag->fr_address))
6573 {
6574 symbolS *sy;
6575
6576 for (sy = symbol_next (ppc_toc_csect);
6577 sy != (symbolS *) NULL;
6578 sy = symbol_next (sy))
6579 {
6580 TC_SYMFIELD_TYPE *sy_tc = symbol_get_tc (sy);
6581
6582 if (sy_tc->symbol_class == XMC_TC0)
6583 continue;
6584 if (sy_tc->symbol_class != XMC_TC)
6585 break;
6586 if (val == resolve_symbol_value (sy))
6587 {
6588 fix->fx_addsy = sy;
6589 fix->fx_addnumber = val - ppc_toc_frag->fr_address;
6590 return 0;
6591 }
6592 }
6593
6594 as_bad_where (fix->fx_file, fix->fx_line,
6595 _("symbol in .toc does not match any .tc"));
6596 }
6597
6598 /* Possibly adjust the reloc to be against the csect. */
6599 tc = symbol_get_tc (fix->fx_addsy);
6600 if (tc->subseg == 0
6601 && tc->symbol_class != XMC_TC0
6602 && tc->symbol_class != XMC_TC
6603 && symseg != bss_section
6604 /* Don't adjust if this is a reloc in the toc section. */
6605 && (symseg != data_section
6606 || ppc_toc_csect == NULL
6607 || val < ppc_toc_frag->fr_address
6608 || (ppc_after_toc_frag != NULL
6609 && val >= ppc_after_toc_frag->fr_address)))
6610 {
6611 symbolS *csect = tc->within;
6612
6613 /* If the symbol was not declared by a label (eg: a section symbol),
6614 use the section instead of the csect. This doesn't happen in
6615 normal AIX assembly code. */
6616 if (csect == NULL)
6617 csect = seg_info (symseg)->sym;
6618
6619 fix->fx_offset += val - symbol_get_frag (csect)->fr_address;
6620 fix->fx_addsy = csect;
6621
6622 return 0;
6623 }
6624
6625 /* Adjust a reloc against a .lcomm symbol to be against the base
6626 .lcomm. */
6627 if (symseg == bss_section
6628 && ! S_IS_EXTERNAL (fix->fx_addsy))
6629 {
6630 symbolS *sy = symbol_get_frag (fix->fx_addsy)->fr_symbol;
6631
6632 fix->fx_offset += val - resolve_symbol_value (sy);
6633 fix->fx_addsy = sy;
6634 }
6635
6636 return 0;
6637}
6638
6639/* A reloc from one csect to another must be kept. The assembler
6640 will, of course, keep relocs between sections, and it will keep
6641 absolute relocs, but we need to force it to keep PC relative relocs
6642 between two csects in the same section. */
6643
6644int
6645ppc_force_relocation (fixS *fix)
6646{
6647 /* At this point fix->fx_addsy should already have been converted to
6648 a csect symbol. If the csect does not include the fragment, then
6649 we need to force the relocation. */
6650 if (fix->fx_pcrel
6651 && fix->fx_addsy != NULL
6652 && symbol_get_tc (fix->fx_addsy)->subseg != 0
6653 && ((symbol_get_frag (fix->fx_addsy)->fr_address
6654 > fix->fx_frag->fr_address)
6655 || (symbol_get_tc (fix->fx_addsy)->next != NULL
6656 && (symbol_get_frag (symbol_get_tc (fix->fx_addsy)->next)->fr_address
6657 <= fix->fx_frag->fr_address))))
6658 return 1;
6659
6660 return generic_force_reloc (fix);
6661}
6662
6663void
6664ppc_new_dot_label (symbolS *sym)
6665{
6666 /* Anchor this label to the current csect for relocations. */
6667 symbol_get_tc (sym)->within = ppc_current_csect;
6668}
6669
6670#endif /* OBJ_XCOFF */
6671
6672#ifdef OBJ_ELF
6673/* If this function returns non-zero, it guarantees that a relocation
6674 will be emitted for a fixup. */
6675
6676int
6677ppc_force_relocation (fixS *fix)
6678{
6679 /* Branch prediction relocations must force a relocation, as must
6680 the vtable description relocs. */
6681 switch (fix->fx_r_type)
6682 {
6683 case BFD_RELOC_PPC_B16_BRTAKEN:
6684 case BFD_RELOC_PPC_B16_BRNTAKEN:
6685 case BFD_RELOC_PPC_BA16_BRTAKEN:
6686 case BFD_RELOC_PPC_BA16_BRNTAKEN:
6687 case BFD_RELOC_24_PLT_PCREL:
6688 case BFD_RELOC_PPC64_TOC:
6689 return 1;
6690 case BFD_RELOC_PPC_B26:
6691 case BFD_RELOC_PPC_BA26:
6692 case BFD_RELOC_PPC_B16:
6693 case BFD_RELOC_PPC_BA16:
6694 case BFD_RELOC_PPC64_REL24_NOTOC:
6695 /* All branch fixups targeting a localentry symbol must
6696 force a relocation. */
6697 if (fix->fx_addsy)
6698 {
6699 asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy);
6700 elf_symbol_type *elfsym
6701 = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
6702 gas_assert (elfsym);
6703 if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0)
6704 return 1;
6705 }
6706 break;
6707 default:
6708 break;
6709 }
6710
6711 if (fix->fx_r_type >= BFD_RELOC_PPC_TLS
6712 && fix->fx_r_type <= BFD_RELOC_PPC64_DTPREL16_HIGHESTA)
6713 return 1;
6714
6715 return generic_force_reloc (fix);
6716}
6717
6718int
6719ppc_fix_adjustable (fixS *fix)
6720{
6721 switch (fix->fx_r_type)
6722 {
6723 /* All branch fixups targeting a localentry symbol must
6724 continue using the symbol. */
6725 case BFD_RELOC_PPC_B26:
6726 case BFD_RELOC_PPC_BA26:
6727 case BFD_RELOC_PPC_B16:
6728 case BFD_RELOC_PPC_BA16:
6729 case BFD_RELOC_PPC_B16_BRTAKEN:
6730 case BFD_RELOC_PPC_B16_BRNTAKEN:
6731 case BFD_RELOC_PPC_BA16_BRTAKEN:
6732 case BFD_RELOC_PPC_BA16_BRNTAKEN:
6733 case BFD_RELOC_PPC64_REL24_NOTOC:
6734 if (fix->fx_addsy)
6735 {
6736 asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy);
6737 elf_symbol_type *elfsym
6738 = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
6739 gas_assert (elfsym);
6740 if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0)
6741 return 0;
6742 }
6743 break;
6744 default:
6745 break;
6746 }
6747
6748 return (fix->fx_r_type != BFD_RELOC_16_GOTOFF
6749 && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF
6750 && fix->fx_r_type != BFD_RELOC_HI16_GOTOFF
6751 && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF
6752 && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS
6753 && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS
6754 && fix->fx_r_type != BFD_RELOC_GPREL16
6755 && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT
6756 && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY
6757 && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS
6758 && fix->fx_r_type <= BFD_RELOC_PPC64_DTPREL16_HIGHESTA));
6759}
6760#endif
6761
6762void
6763ppc_frag_check (struct frag *fragP)
6764{
6765 if ((fragP->fr_address & fragP->insn_addr) != 0)
6766 as_bad_where (fragP->fr_file, fragP->fr_line,
6767 _("instruction address is not a multiple of %d"),
6768 fragP->insn_addr + 1);
6769}
6770
6771/* Implement HANDLE_ALIGN. This writes the NOP pattern into an
6772 rs_align_code frag. */
6773
6774void
6775ppc_handle_align (struct frag *fragP)
6776{
6777 valueT count = (fragP->fr_next->fr_address
6778 - (fragP->fr_address + fragP->fr_fix));
6779
6780 if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && count != 0 && (count & 1) == 0)
6781 {
6782 char *dest = fragP->fr_literal + fragP->fr_fix;
6783
6784 fragP->fr_var = 2;
6785 md_number_to_chars (dest, 0x4400, 2);
6786 }
6787 else if (count != 0 && (count & 3) == 0)
6788 {
6789 char *dest = fragP->fr_literal + fragP->fr_fix;
6790
6791 fragP->fr_var = 4;
6792
6793 if (count > 4 * nop_limit && count < 0x2000000)
6794 {
6795 struct frag *rest;
6796
6797 /* Make a branch, then follow with nops. Insert another
6798 frag to handle the nops. */
6799 md_number_to_chars (dest, 0x48000000 + count, 4);
6800 count -= 4;
6801 if (count == 0)
6802 return;
6803
6804 rest = xmalloc (SIZEOF_STRUCT_FRAG + 4);
6805 memcpy (rest, fragP, SIZEOF_STRUCT_FRAG);
6806 fragP->fr_next = rest;
6807 fragP = rest;
6808 rest->fr_address += rest->fr_fix + 4;
6809 rest->fr_fix = 0;
6810 /* If we leave the next frag as rs_align_code we'll come here
6811 again, resulting in a bunch of branches rather than a
6812 branch followed by nops. */
6813 rest->fr_type = rs_align;
6814 dest = rest->fr_literal;
6815 }
6816
6817 md_number_to_chars (dest, 0x60000000, 4);
6818
6819 if ((ppc_cpu & PPC_OPCODE_POWER6) != 0
6820 && (ppc_cpu & PPC_OPCODE_POWER9) == 0)
6821 {
6822 /* For power6, power7, and power8, we want the last nop to
6823 be a group terminating one. Do this by inserting an
6824 rs_fill frag immediately after this one, with its address
6825 set to the last nop location. This will automatically
6826 reduce the number of nops in the current frag by one. */
6827 if (count > 4)
6828 {
6829 struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4);
6830
6831 memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG);
6832 group_nop->fr_address = group_nop->fr_next->fr_address - 4;
6833 group_nop->fr_fix = 0;
6834 group_nop->fr_offset = 1;
6835 group_nop->fr_type = rs_fill;
6836 fragP->fr_next = group_nop;
6837 dest = group_nop->fr_literal;
6838 }
6839
6840 if ((ppc_cpu & PPC_OPCODE_POWER7) != 0)
6841 {
6842 if (ppc_cpu & PPC_OPCODE_E500MC)
6843 /* e500mc group terminating nop: "ori 0,0,0". */
6844 md_number_to_chars (dest, 0x60000000, 4);
6845 else
6846 /* power7/power8 group terminating nop: "ori 2,2,0". */
6847 md_number_to_chars (dest, 0x60420000, 4);
6848 }
6849 else
6850 /* power6 group terminating nop: "ori 1,1,0". */
6851 md_number_to_chars (dest, 0x60210000, 4);
6852 }
6853 }
6854}
6855
6856/* Apply a fixup to the object code. This is called for all the
6857 fixups we generated by the calls to fix_new_exp, above. */
6858
6859void
6860md_apply_fix (fixS *fixP, valueT *valP, segT seg)
6861{
6862 valueT value = * valP;
6863 offsetT fieldval;
6864 const struct powerpc_operand *operand;
6865
6866#ifdef OBJ_ELF
6867 if (fixP->fx_addsy != NULL)
6868 {
6869 /* Hack around bfd_install_relocation brain damage. */
6870 if (fixP->fx_pcrel)
6871 value += fixP->fx_frag->fr_address + fixP->fx_where;
6872
6873 if (fixP->fx_addsy == abs_section_sym)
6874 fixP->fx_done = 1;
6875 }
6876 else
6877 fixP->fx_done = 1;
6878#else
6879 /* FIXME FIXME FIXME: The value we are passed in *valP includes
6880 the symbol values. If we are doing this relocation the code in
6881 write.c is going to call bfd_install_relocation, which is also
6882 going to use the symbol value. That means that if the reloc is
6883 fully resolved we want to use *valP since bfd_install_relocation is
6884 not being used.
6885 However, if the reloc is not fully resolved we do not want to
6886 use *valP, and must use fx_offset instead. If the relocation
6887 is PC-relative, we then need to re-apply md_pcrel_from_section
6888 to this new relocation value. */
6889 if (fixP->fx_addsy == (symbolS *) NULL)
6890 fixP->fx_done = 1;
6891
6892 else
6893 {
6894 value = fixP->fx_offset;
6895 if (fixP->fx_pcrel)
6896 value -= md_pcrel_from_section (fixP, seg);
6897 }
6898#endif
6899
6900 /* We are only able to convert some relocs to pc-relative. */
6901 if (fixP->fx_pcrel)
6902 {
6903 switch (fixP->fx_r_type)
6904 {
6905 case BFD_RELOC_64:
6906 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6907 break;
6908
6909 case BFD_RELOC_32:
6910 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6911 break;
6912
6913 case BFD_RELOC_16:
6914 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6915 break;
6916
6917 case BFD_RELOC_LO16:
6918 fixP->fx_r_type = BFD_RELOC_LO16_PCREL;
6919 break;
6920
6921 case BFD_RELOC_HI16:
6922 fixP->fx_r_type = BFD_RELOC_HI16_PCREL;
6923 break;
6924
6925 case BFD_RELOC_HI16_S:
6926 fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL;
6927 break;
6928
6929 case BFD_RELOC_PPC64_ADDR16_HIGH:
6930 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGH;
6931 break;
6932
6933 case BFD_RELOC_PPC64_ADDR16_HIGHA:
6934 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHA;
6935 break;
6936
6937 case BFD_RELOC_PPC64_HIGHER:
6938 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER;
6939 break;
6940
6941 case BFD_RELOC_PPC64_HIGHER_S:
6942 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA;
6943 break;
6944
6945 case BFD_RELOC_PPC64_HIGHEST:
6946 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST;
6947 break;
6948
6949 case BFD_RELOC_PPC64_HIGHEST_S:
6950 fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA;
6951 break;
6952
6953 case BFD_RELOC_PPC_16DX_HA:
6954 fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA;
6955 break;
6956
6957 default:
6958 break;
6959 }
6960 }
6961 else if (!fixP->fx_done
6962 && fixP->fx_r_type == BFD_RELOC_PPC_16DX_HA)
6963 {
6964 /* addpcis is relative to next insn address. */
6965 value -= 4;
6966 fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA;
6967 fixP->fx_pcrel = 1;
6968 }
6969
6970 operand = NULL;
6971 if (fixP->fx_pcrel_adjust != 0)
6972 {
6973 /* This is a fixup on an instruction. */
6974 int opindex = fixP->fx_pcrel_adjust & 0xff;
6975
6976 operand = &powerpc_operands[opindex];
6977#ifdef OBJ_XCOFF
6978 /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol
6979 does not generate a reloc. It uses the offset of `sym' within its
6980 csect. Other usages, such as `.long sym', generate relocs. This
6981 is the documented behaviour of non-TOC symbols. */
6982 if ((operand->flags & PPC_OPERAND_PARENS) != 0
6983 && (operand->bitm & 0xfff0) == 0xfff0
6984 && operand->shift == 0
6985 && (operand->insert == NULL || ppc_obj64)
6986 && fixP->fx_addsy != NULL
6987 && symbol_get_tc (fixP->fx_addsy)->subseg != 0
6988 && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC
6989 && symbol_get_tc (fixP->fx_addsy)->symbol_class != XMC_TC0
6990 && S_GET_SEGMENT (fixP->fx_addsy) != bss_section)
6991 {
6992 value = fixP->fx_offset;
6993 fixP->fx_done = 1;
6994 }
6995
6996 /* During parsing of instructions, a TOC16 reloc is generated for
6997 instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined
6998 in the toc. But at parse time, SYM may be not yet defined, so
6999 check again here. */
7000 if (fixP->fx_r_type == BFD_RELOC_16
7001 && fixP->fx_addsy != NULL
7002 && ppc_is_toc_sym (fixP->fx_addsy))
7003 fixP->fx_r_type = BFD_RELOC_PPC_TOC16;
7004#endif
7005 }
7006
7007 /* Calculate value to be stored in field. */
7008 fieldval = value;
7009 switch (fixP->fx_r_type)
7010 {
7011#ifdef OBJ_ELF
7012 case BFD_RELOC_PPC64_ADDR16_LO_DS:
7013 case BFD_RELOC_PPC_VLE_LO16A:
7014 case BFD_RELOC_PPC_VLE_LO16D:
7015#endif
7016 case BFD_RELOC_LO16:
7017 case BFD_RELOC_LO16_PCREL:
7018 fieldval = value & 0xffff;
7019 sign_extend_16:
7020 if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0)
7021 fieldval = SEX16 (fieldval);
7022 fixP->fx_no_overflow = 1;
7023 break;
7024
7025 case BFD_RELOC_HI16:
7026 case BFD_RELOC_HI16_PCREL:
7027#ifdef OBJ_ELF
7028 if (REPORT_OVERFLOW_HI && ppc_obj64)
7029 {
7030 fieldval = value >> 16;
7031 if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0)
7032 {
7033 valueT sign = (((valueT) -1 >> 16) + 1) >> 1;
7034 fieldval = ((valueT) fieldval ^ sign) - sign;
7035 }
7036 break;
7037 }
7038 /* Fallthru */
7039
7040 case BFD_RELOC_PPC_VLE_HI16A:
7041 case BFD_RELOC_PPC_VLE_HI16D:
7042 case BFD_RELOC_PPC64_ADDR16_HIGH:
7043#endif
7044 fieldval = PPC_HI (value);
7045 goto sign_extend_16;
7046
7047 case BFD_RELOC_HI16_S:
7048 case BFD_RELOC_HI16_S_PCREL:
7049 case BFD_RELOC_PPC_16DX_HA:
7050 case BFD_RELOC_PPC_REL16DX_HA:
7051#ifdef OBJ_ELF
7052 if (REPORT_OVERFLOW_HI && ppc_obj64)
7053 {
7054 fieldval = (value + 0x8000) >> 16;
7055 if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0)
7056 {
7057 valueT sign = (((valueT) -1 >> 16) + 1) >> 1;
7058 fieldval = ((valueT) fieldval ^ sign) - sign;
7059 }
7060 break;
7061 }
7062 /* Fallthru */
7063
7064 case BFD_RELOC_PPC_VLE_HA16A:
7065 case BFD_RELOC_PPC_VLE_HA16D:
7066 case BFD_RELOC_PPC64_ADDR16_HIGHA:
7067#endif
7068 fieldval = PPC_HA (value);
7069 goto sign_extend_16;
7070
7071#ifdef OBJ_ELF
7072 case BFD_RELOC_PPC64_HIGHER:
7073 fieldval = PPC_HIGHER (value);
7074 goto sign_extend_16;
7075
7076 case BFD_RELOC_PPC64_HIGHER_S:
7077 fieldval = PPC_HIGHERA (value);
7078 goto sign_extend_16;
7079
7080 case BFD_RELOC_PPC64_HIGHEST:
7081 fieldval = PPC_HIGHEST (value);
7082 goto sign_extend_16;
7083
7084 case BFD_RELOC_PPC64_HIGHEST_S:
7085 fieldval = PPC_HIGHESTA (value);
7086 goto sign_extend_16;
7087#endif
7088
7089 default:
7090 break;
7091 }
7092
7093 if (operand != NULL)
7094 {
7095 /* Handle relocs in an insn. */
7096 switch (fixP->fx_r_type)
7097 {
7098#ifdef OBJ_ELF
7099 /* The following relocs can't be calculated by the assembler.
7100 Leave the field zero. */
7101 case BFD_RELOC_PPC_TPREL16:
7102 case BFD_RELOC_PPC_TPREL16_LO:
7103 case BFD_RELOC_PPC_TPREL16_HI:
7104 case BFD_RELOC_PPC_TPREL16_HA:
7105 case BFD_RELOC_PPC_DTPREL16:
7106 case BFD_RELOC_PPC_DTPREL16_LO:
7107 case BFD_RELOC_PPC_DTPREL16_HI:
7108 case BFD_RELOC_PPC_DTPREL16_HA:
7109 case BFD_RELOC_PPC_GOT_TLSGD16:
7110 case BFD_RELOC_PPC_GOT_TLSGD16_LO:
7111 case BFD_RELOC_PPC_GOT_TLSGD16_HI:
7112 case BFD_RELOC_PPC_GOT_TLSGD16_HA:
7113 case BFD_RELOC_PPC_GOT_TLSLD16:
7114 case BFD_RELOC_PPC_GOT_TLSLD16_LO:
7115 case BFD_RELOC_PPC_GOT_TLSLD16_HI:
7116 case BFD_RELOC_PPC_GOT_TLSLD16_HA:
7117 case BFD_RELOC_PPC_GOT_TPREL16:
7118 case BFD_RELOC_PPC_GOT_TPREL16_LO:
7119 case BFD_RELOC_PPC_GOT_TPREL16_HI:
7120 case BFD_RELOC_PPC_GOT_TPREL16_HA:
7121 case BFD_RELOC_PPC_GOT_DTPREL16:
7122 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
7123 case BFD_RELOC_PPC_GOT_DTPREL16_HI:
7124 case BFD_RELOC_PPC_GOT_DTPREL16_HA:
7125 case BFD_RELOC_PPC64_TPREL16_DS:
7126 case BFD_RELOC_PPC64_TPREL16_LO_DS:
7127 case BFD_RELOC_PPC64_TPREL16_HIGH:
7128 case BFD_RELOC_PPC64_TPREL16_HIGHA:
7129 case BFD_RELOC_PPC64_TPREL16_HIGHER:
7130 case BFD_RELOC_PPC64_TPREL16_HIGHERA:
7131 case BFD_RELOC_PPC64_TPREL16_HIGHEST:
7132 case BFD_RELOC_PPC64_TPREL16_HIGHESTA:
7133 case BFD_RELOC_PPC64_DTPREL16_HIGH:
7134 case BFD_RELOC_PPC64_DTPREL16_HIGHA:
7135 case BFD_RELOC_PPC64_DTPREL16_DS:
7136 case BFD_RELOC_PPC64_DTPREL16_LO_DS:
7137 case BFD_RELOC_PPC64_DTPREL16_HIGHER:
7138 case BFD_RELOC_PPC64_DTPREL16_HIGHERA:
7139 case BFD_RELOC_PPC64_DTPREL16_HIGHEST:
7140 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA:
7141 gas_assert (fixP->fx_addsy != NULL);
7142 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7143 fieldval = 0;
7144 break;
7145
7146 /* These also should leave the field zero for the same
7147 reason. Note that older versions of gas wrote values
7148 here. If we want to go back to the old behaviour, then
7149 all _LO and _LO_DS cases will need to be treated like
7150 BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */
7151 case BFD_RELOC_16_GOTOFF:
7152 case BFD_RELOC_LO16_GOTOFF:
7153 case BFD_RELOC_HI16_GOTOFF:
7154 case BFD_RELOC_HI16_S_GOTOFF:
7155 case BFD_RELOC_LO16_PLTOFF:
7156 case BFD_RELOC_HI16_PLTOFF:
7157 case BFD_RELOC_HI16_S_PLTOFF:
7158 case BFD_RELOC_GPREL16:
7159 case BFD_RELOC_16_BASEREL:
7160 case BFD_RELOC_LO16_BASEREL:
7161 case BFD_RELOC_HI16_BASEREL:
7162 case BFD_RELOC_HI16_S_BASEREL:
7163 case BFD_RELOC_PPC_TOC16:
7164 case BFD_RELOC_PPC64_TOC16_LO:
7165 case BFD_RELOC_PPC64_TOC16_HI:
7166 case BFD_RELOC_PPC64_TOC16_HA:
7167 case BFD_RELOC_PPC64_PLTGOT16:
7168 case BFD_RELOC_PPC64_PLTGOT16_LO:
7169 case BFD_RELOC_PPC64_PLTGOT16_HI:
7170 case BFD_RELOC_PPC64_PLTGOT16_HA:
7171 case BFD_RELOC_PPC64_GOT16_DS:
7172 case BFD_RELOC_PPC64_GOT16_LO_DS:
7173 case BFD_RELOC_PPC64_PLT16_LO_DS:
7174 case BFD_RELOC_PPC64_SECTOFF_DS:
7175 case BFD_RELOC_PPC64_SECTOFF_LO_DS:
7176 case BFD_RELOC_PPC64_TOC16_DS:
7177 case BFD_RELOC_PPC64_TOC16_LO_DS:
7178 case BFD_RELOC_PPC64_PLTGOT16_DS:
7179 case BFD_RELOC_PPC64_PLTGOT16_LO_DS:
7180 case BFD_RELOC_PPC_EMB_NADDR16:
7181 case BFD_RELOC_PPC_EMB_NADDR16_LO:
7182 case BFD_RELOC_PPC_EMB_NADDR16_HI:
7183 case BFD_RELOC_PPC_EMB_NADDR16_HA:
7184 case BFD_RELOC_PPC_EMB_SDAI16:
7185 case BFD_RELOC_PPC_EMB_SDA2I16:
7186 case BFD_RELOC_PPC_EMB_SDA2REL:
7187 case BFD_RELOC_PPC_EMB_SDA21:
7188 case BFD_RELOC_PPC_EMB_MRKREF:
7189 case BFD_RELOC_PPC_EMB_RELSEC16:
7190 case BFD_RELOC_PPC_EMB_RELST_LO:
7191 case BFD_RELOC_PPC_EMB_RELST_HI:
7192 case BFD_RELOC_PPC_EMB_RELST_HA:
7193 case BFD_RELOC_PPC_EMB_BIT_FLD:
7194 case BFD_RELOC_PPC_EMB_RELSDA:
7195 case BFD_RELOC_PPC_VLE_SDA21:
7196 case BFD_RELOC_PPC_VLE_SDA21_LO:
7197 case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
7198 case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
7199 case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
7200 case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
7201 case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
7202 case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
7203 gas_assert (fixP->fx_addsy != NULL);
7204 /* Fallthru */
7205
7206 case BFD_RELOC_PPC_TLS:
7207 case BFD_RELOC_PPC_TLSGD:
7208 case BFD_RELOC_PPC_TLSLD:
7209 fieldval = 0;
7210 break;
7211#endif
7212
7213#ifdef OBJ_XCOFF
7214 case BFD_RELOC_PPC_B16:
7215 /* Adjust the offset to the instruction boundary. */
7216 fieldval += 2;
7217 break;
7218#endif
7219
7220 case BFD_RELOC_VTABLE_INHERIT:
7221 case BFD_RELOC_VTABLE_ENTRY:
7222 case BFD_RELOC_PPC_DTPMOD:
7223 case BFD_RELOC_PPC_TPREL:
7224 case BFD_RELOC_PPC_DTPREL:
7225 case BFD_RELOC_PPC_COPY:
7226 case BFD_RELOC_PPC_GLOB_DAT:
7227 case BFD_RELOC_32_PLT_PCREL:
7228 case BFD_RELOC_PPC_EMB_NADDR32:
7229 case BFD_RELOC_PPC64_TOC:
7230 case BFD_RELOC_CTOR:
7231 case BFD_RELOC_32:
7232 case BFD_RELOC_32_PCREL:
7233 case BFD_RELOC_RVA:
7234 case BFD_RELOC_64:
7235 case BFD_RELOC_64_PCREL:
7236 case BFD_RELOC_PPC64_ADDR64_LOCAL:
7237 as_bad_where (fixP->fx_file, fixP->fx_line,
7238 _("%s unsupported as instruction fixup"),
7239 bfd_get_reloc_code_name (fixP->fx_r_type));
7240 fixP->fx_done = 1;
7241 return;
7242
7243 default:
7244 break;
7245 }
7246
7247#ifdef OBJ_ELF
7248/* powerpc uses RELA style relocs, so if emitting a reloc the field
7249 contents can stay at zero. */
7250#define APPLY_RELOC fixP->fx_done
7251#else
7252#define APPLY_RELOC 1
7253#endif
7254 if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL)
7255 {
7256 unsigned long insn;
7257 unsigned char *where;
7258
7259 /* Fetch the instruction, insert the fully resolved operand
7260 value, and stuff the instruction back again. */
7261 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
7262 if (target_big_endian)
7263 {
7264 if (fixP->fx_size == 4)
7265 insn = bfd_getb32 (where);
7266 else
7267 insn = bfd_getb16 (where);
7268 }
7269 else
7270 {
7271 if (fixP->fx_size == 4)
7272 insn = bfd_getl32 (where);
7273 else
7274 insn = bfd_getl16 (where);
7275 }
7276 insn = ppc_insert_operand (insn, operand, fieldval,
7277 fixP->tc_fix_data.ppc_cpu,
7278 fixP->fx_file, fixP->fx_line);
7279 if (target_big_endian)
7280 {
7281 if (fixP->fx_size == 4)
7282 bfd_putb32 (insn, where);
7283 else
7284 bfd_putb16 (insn, where);
7285 }
7286 else
7287 {
7288 if (fixP->fx_size == 4)
7289 bfd_putl32 (insn, where);
7290 else
7291 bfd_putl16 (insn, where);
7292 }
7293 }
7294
7295 if (fixP->fx_done)
7296 /* Nothing else to do here. */
7297 return;
7298
7299 gas_assert (fixP->fx_addsy != NULL);
7300 if (fixP->fx_r_type == BFD_RELOC_NONE)
7301 {
7302 const char *sfile;
7303 unsigned int sline;
7304
7305 /* Use expr_symbol_where to see if this is an expression
7306 symbol. */
7307 if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline))
7308 as_bad_where (fixP->fx_file, fixP->fx_line,
7309 _("unresolved expression that must be resolved"));
7310 else
7311 as_bad_where (fixP->fx_file, fixP->fx_line,
7312 _("unsupported relocation against %s"),
7313 S_GET_NAME (fixP->fx_addsy));
7314 fixP->fx_done = 1;
7315 return;
7316 }
7317 }
7318 else
7319 {
7320 /* Handle relocs in data. */
7321 switch (fixP->fx_r_type)
7322 {
7323 case BFD_RELOC_VTABLE_INHERIT:
7324 if (fixP->fx_addsy
7325 && !S_IS_DEFINED (fixP->fx_addsy)
7326 && !S_IS_WEAK (fixP->fx_addsy))
7327 S_SET_WEAK (fixP->fx_addsy);
7328 /* Fallthru */
7329
7330 case BFD_RELOC_VTABLE_ENTRY:
7331 fixP->fx_done = 0;
7332 break;
7333
7334#ifdef OBJ_ELF
7335 /* These can appear with @l etc. in data. */
7336 case BFD_RELOC_LO16:
7337 case BFD_RELOC_LO16_PCREL:
7338 case BFD_RELOC_HI16:
7339 case BFD_RELOC_HI16_PCREL:
7340 case BFD_RELOC_HI16_S:
7341 case BFD_RELOC_HI16_S_PCREL:
7342 case BFD_RELOC_PPC64_HIGHER:
7343 case BFD_RELOC_PPC64_HIGHER_S:
7344 case BFD_RELOC_PPC64_HIGHEST:
7345 case BFD_RELOC_PPC64_HIGHEST_S:
7346 case BFD_RELOC_PPC64_ADDR16_HIGH:
7347 case BFD_RELOC_PPC64_ADDR16_HIGHA:
7348 case BFD_RELOC_PPC64_ADDR64_LOCAL:
7349 break;
7350
7351 case BFD_RELOC_PPC_DTPMOD:
7352 case BFD_RELOC_PPC_TPREL:
7353 case BFD_RELOC_PPC_DTPREL:
7354 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7355 break;
7356
7357 /* Just punt all of these to the linker. */
7358 case BFD_RELOC_PPC_B16_BRTAKEN:
7359 case BFD_RELOC_PPC_B16_BRNTAKEN:
7360 case BFD_RELOC_16_GOTOFF:
7361 case BFD_RELOC_LO16_GOTOFF:
7362 case BFD_RELOC_HI16_GOTOFF:
7363 case BFD_RELOC_HI16_S_GOTOFF:
7364 case BFD_RELOC_LO16_PLTOFF:
7365 case BFD_RELOC_HI16_PLTOFF:
7366 case BFD_RELOC_HI16_S_PLTOFF:
7367 case BFD_RELOC_PPC_COPY:
7368 case BFD_RELOC_PPC_GLOB_DAT:
7369 case BFD_RELOC_16_BASEREL:
7370 case BFD_RELOC_LO16_BASEREL:
7371 case BFD_RELOC_HI16_BASEREL:
7372 case BFD_RELOC_HI16_S_BASEREL:
7373 case BFD_RELOC_PPC_TLS:
7374 case BFD_RELOC_PPC_DTPREL16_LO:
7375 case BFD_RELOC_PPC_DTPREL16_HI:
7376 case BFD_RELOC_PPC_DTPREL16_HA:
7377 case BFD_RELOC_PPC_TPREL16_LO:
7378 case BFD_RELOC_PPC_TPREL16_HI:
7379 case BFD_RELOC_PPC_TPREL16_HA:
7380 case BFD_RELOC_PPC_GOT_TLSGD16:
7381 case BFD_RELOC_PPC_GOT_TLSGD16_LO:
7382 case BFD_RELOC_PPC_GOT_TLSGD16_HI:
7383 case BFD_RELOC_PPC_GOT_TLSGD16_HA:
7384 case BFD_RELOC_PPC_GOT_TLSLD16:
7385 case BFD_RELOC_PPC_GOT_TLSLD16_LO:
7386 case BFD_RELOC_PPC_GOT_TLSLD16_HI:
7387 case BFD_RELOC_PPC_GOT_TLSLD16_HA:
7388 case BFD_RELOC_PPC_GOT_DTPREL16:
7389 case BFD_RELOC_PPC_GOT_DTPREL16_LO:
7390 case BFD_RELOC_PPC_GOT_DTPREL16_HI:
7391 case BFD_RELOC_PPC_GOT_DTPREL16_HA:
7392 case BFD_RELOC_PPC_GOT_TPREL16:
7393 case BFD_RELOC_PPC_GOT_TPREL16_LO:
7394 case BFD_RELOC_PPC_GOT_TPREL16_HI:
7395 case BFD_RELOC_PPC_GOT_TPREL16_HA:
7396 case BFD_RELOC_24_PLT_PCREL:
7397 case BFD_RELOC_PPC_LOCAL24PC:
7398 case BFD_RELOC_32_PLT_PCREL:
7399 case BFD_RELOC_GPREL16:
7400 case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
7401 case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
7402 case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
7403 case BFD_RELOC_PPC_EMB_NADDR32:
7404 case BFD_RELOC_PPC_EMB_NADDR16:
7405 case BFD_RELOC_PPC_EMB_NADDR16_LO:
7406 case BFD_RELOC_PPC_EMB_NADDR16_HI:
7407 case BFD_RELOC_PPC_EMB_NADDR16_HA:
7408 case BFD_RELOC_PPC_EMB_SDAI16:
7409 case BFD_RELOC_PPC_EMB_SDA2REL:
7410 case BFD_RELOC_PPC_EMB_SDA2I16:
7411 case BFD_RELOC_PPC_EMB_SDA21:
7412 case BFD_RELOC_PPC_VLE_SDA21_LO:
7413 case BFD_RELOC_PPC_EMB_MRKREF:
7414 case BFD_RELOC_PPC_EMB_RELSEC16:
7415 case BFD_RELOC_PPC_EMB_RELST_LO:
7416 case BFD_RELOC_PPC_EMB_RELST_HI:
7417 case BFD_RELOC_PPC_EMB_RELST_HA:
7418 case BFD_RELOC_PPC_EMB_BIT_FLD:
7419 case BFD_RELOC_PPC_EMB_RELSDA:
7420 case BFD_RELOC_PPC64_TOC:
7421 case BFD_RELOC_PPC_TOC16:
7422 case BFD_RELOC_PPC64_TOC16_LO:
7423 case BFD_RELOC_PPC64_TOC16_HI:
7424 case BFD_RELOC_PPC64_TOC16_HA:
7425 case BFD_RELOC_PPC64_DTPREL16_HIGH:
7426 case BFD_RELOC_PPC64_DTPREL16_HIGHA:
7427 case BFD_RELOC_PPC64_DTPREL16_HIGHER:
7428 case BFD_RELOC_PPC64_DTPREL16_HIGHERA:
7429 case BFD_RELOC_PPC64_DTPREL16_HIGHEST:
7430 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA:
7431 case BFD_RELOC_PPC64_TPREL16_HIGH:
7432 case BFD_RELOC_PPC64_TPREL16_HIGHA:
7433 case BFD_RELOC_PPC64_TPREL16_HIGHER:
7434 case BFD_RELOC_PPC64_TPREL16_HIGHERA:
7435 case BFD_RELOC_PPC64_TPREL16_HIGHEST:
7436 case BFD_RELOC_PPC64_TPREL16_HIGHESTA:
7437 fixP->fx_done = 0;
7438 break;
7439#endif
7440
7441#ifdef OBJ_XCOFF
7442 case BFD_RELOC_NONE:
7443#endif
7444 case BFD_RELOC_CTOR:
7445 case BFD_RELOC_32:
7446 case BFD_RELOC_32_PCREL:
7447 case BFD_RELOC_RVA:
7448 case BFD_RELOC_64:
7449 case BFD_RELOC_64_PCREL:
7450 case BFD_RELOC_16:
7451 case BFD_RELOC_16_PCREL:
7452 case BFD_RELOC_8:
7453 break;
7454
7455 default:
7456 fprintf (stderr,
7457 _("Gas failure, reloc value %d\n"), fixP->fx_r_type);
7458 fflush (stderr);
7459 abort ();
7460 }
7461
7462 if (fixP->fx_size && APPLY_RELOC)
7463 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
7464 fieldval, fixP->fx_size);
7465 if (warn_476
7466 && (seg->flags & SEC_CODE) != 0
7467 && fixP->fx_size == 4
7468 && fixP->fx_done
7469 && !fixP->fx_tcbit
7470 && (fixP->fx_r_type == BFD_RELOC_32
7471 || fixP->fx_r_type == BFD_RELOC_CTOR
7472 || fixP->fx_r_type == BFD_RELOC_32_PCREL))
7473 as_warn_where (fixP->fx_file, fixP->fx_line,
7474 _("data in executable section"));
7475 }
7476
7477#ifdef OBJ_ELF
7478 ppc_elf_validate_fix (fixP, seg);
7479 fixP->fx_addnumber = value;
7480
7481 /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately
7482 from the section contents. If we are going to be emitting a reloc
7483 then the section contents are immaterial, so don't warn if they
7484 happen to overflow. Leave such warnings to ld. */
7485 if (!fixP->fx_done)
7486 {
7487 fixP->fx_no_overflow = 1;
7488
7489 /* Arrange to emit .TOC. as a normal symbol if used in anything
7490 but .TOC.@tocbase. */
7491 if (ppc_obj64
7492 && fixP->fx_r_type != BFD_RELOC_PPC64_TOC
7493 && fixP->fx_addsy != NULL
7494 && strcmp (S_GET_NAME (fixP->fx_addsy), ".TOC.") == 0)
7495 symbol_get_bfdsym (fixP->fx_addsy)->flags |= BSF_KEEP;
7496 }
7497#else
7498 if (fixP->fx_r_type != BFD_RELOC_PPC_TOC16)
7499 fixP->fx_addnumber = 0;
7500 else
7501 {
7502#ifdef TE_PE
7503 fixP->fx_addnumber = 0;
7504#else
7505 /* We want to use the offset within the toc, not the actual VMA
7506 of the symbol. */
7507 fixP->fx_addnumber =
7508 - bfd_get_section_vma (stdoutput, S_GET_SEGMENT (fixP->fx_addsy))
7509 - S_GET_VALUE (ppc_toc_csect);
7510 /* Set *valP to avoid errors. */
7511 *valP = value;
7512#endif
7513 }
7514#endif
7515}
7516
7517/* Generate a reloc for a fixup. */
7518
7519arelent *
7520tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
7521{
7522 arelent *reloc;
7523
7524 reloc = XNEW (arelent);
7525
7526 reloc->sym_ptr_ptr = XNEW (asymbol *);
7527 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7528 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
7529 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
7530 if (reloc->howto == (reloc_howto_type *) NULL)
7531 {
7532 as_bad_where (fixp->fx_file, fixp->fx_line,
7533 _("reloc %d not supported by object file format"),
7534 (int) fixp->fx_r_type);
7535 return NULL;
7536 }
7537 reloc->addend = fixp->fx_addnumber;
7538
7539 return reloc;
7540}
7541
7542void
7543ppc_cfi_frame_initial_instructions (void)
7544{
7545 cfi_add_CFA_def_cfa (1, 0);
7546}
7547
7548int
7549tc_ppc_regname_to_dw2regnum (char *regname)
7550{
7551 unsigned int regnum = -1;
7552 unsigned int i;
7553 const char *p;
7554 char *q;
7555 static struct { const char *name; int dw2regnum; } regnames[] =
7556 {
7557 { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 },
7558 { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 },
7559 { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 },
7560 { "spe_acc", 111 }, { "spefscr", 112 }
7561 };
7562
7563 for (i = 0; i < ARRAY_SIZE (regnames); ++i)
7564 if (strcmp (regnames[i].name, regname) == 0)
7565 return regnames[i].dw2regnum;
7566
7567 if (regname[0] == 'r' || regname[0] == 'f' || regname[0] == 'v')
7568 {
7569 p = regname + 1 + (regname[1] == '.');
7570 regnum = strtoul (p, &q, 10);
7571 if (p == q || *q || regnum >= 32)
7572 return -1;
7573 if (regname[0] == 'f')
7574 regnum += 32;
7575 else if (regname[0] == 'v')
7576 regnum += 77;
7577 }
7578 else if (regname[0] == 'c' && regname[1] == 'r')
7579 {
7580 p = regname + 2 + (regname[2] == '.');
7581 if (p[0] < '0' || p[0] > '7' || p[1])
7582 return -1;
7583 regnum = p[0] - '0' + 68;
7584 }
7585 return regnum;
7586}
GDB Binutils - Deliverables
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