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sim: h8300 special case test
[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c
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1/* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
3
4 Contributed by Andrew Waterman (andrew@sifive.com).
5 Based on MIPS target.
6
7 This file is part of GAS.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
22
23#include "as.h"
24#include "config.h"
25#include "subsegs.h"
26#include "safe-ctype.h"
27
28#include "itbl-ops.h"
29#include "dwarf2dbg.h"
30#include "dw2gencfi.h"
31
32#include "bfd/cpu-riscv.h"
33#include "bfd/elfxx-riscv.h"
34#include "elf/riscv.h"
35#include "opcode/riscv.h"
36
37#include <stdint.h>
38
39/* Information about an instruction, including its format, operands
40 and fixups. */
41struct riscv_cl_insn
42{
43 /* The opcode's entry in riscv_opcodes. */
44 const struct riscv_opcode *insn_mo;
45
46 /* The encoded instruction bits. */
47 insn_t insn_opcode;
48
49 /* The frag that contains the instruction. */
50 struct frag *frag;
51
52 /* The offset into FRAG of the first instruction byte. */
53 long where;
54
55 /* The relocs associated with the instruction, if any. */
56 fixS *fixp;
57};
58
59/* All RISC-V CSR belong to one of these classes. */
60enum riscv_csr_class
61{
62 CSR_CLASS_NONE,
63
64 CSR_CLASS_I,
65 CSR_CLASS_I_32, /* rv32 only */
66 CSR_CLASS_F, /* f-ext only */
67 CSR_CLASS_DEBUG /* debug CSR */
68};
69
70/* This structure holds all restricted conditions for a CSR. */
71struct riscv_csr_extra
72{
73 /* Class to which this CSR belongs. Used to decide whether or
74 not this CSR is legal in the current -march context. */
75 enum riscv_csr_class csr_class;
76
77 /* CSR may have differnet numbers in the previous priv spec. */
78 unsigned address;
79
80 /* Record the CSR is defined/valid in which versions. */
81 enum riscv_spec_class define_version;
82
83 /* Record the CSR is aborted/invalid from which versions. If it isn't
84 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
85 enum riscv_spec_class abort_version;
86
87 /* The CSR may have more than one setting. */
88 struct riscv_csr_extra *next;
89};
90
91/* All standard/Z* extensions defined in all supported ISA spec. */
92struct riscv_ext_version
93{
94 const char *name;
95 enum riscv_spec_class isa_spec_class;
96 int major_version;
97 int minor_version;
98};
99
100static const struct riscv_ext_version ext_version_table[] =
101{
102 {"e", ISA_SPEC_CLASS_20191213, 1, 9},
103 {"e", ISA_SPEC_CLASS_20190608, 1, 9},
104 {"e", ISA_SPEC_CLASS_2P2, 1, 9},
105
106 {"i", ISA_SPEC_CLASS_20191213, 2, 1},
107 {"i", ISA_SPEC_CLASS_20190608, 2, 1},
108 {"i", ISA_SPEC_CLASS_2P2, 2, 0},
109
110 {"m", ISA_SPEC_CLASS_20191213, 2, 0},
111 {"m", ISA_SPEC_CLASS_20190608, 2, 0},
112 {"m", ISA_SPEC_CLASS_2P2, 2, 0},
113
114 {"a", ISA_SPEC_CLASS_20191213, 2, 1},
115 {"a", ISA_SPEC_CLASS_20190608, 2, 0},
116 {"a", ISA_SPEC_CLASS_2P2, 2, 0},
117
118 {"f", ISA_SPEC_CLASS_20191213, 2, 2},
119 {"f", ISA_SPEC_CLASS_20190608, 2, 2},
120 {"f", ISA_SPEC_CLASS_2P2, 2, 0},
121
122 {"d", ISA_SPEC_CLASS_20191213, 2, 2},
123 {"d", ISA_SPEC_CLASS_20190608, 2, 2},
124 {"d", ISA_SPEC_CLASS_2P2, 2, 0},
125
126 {"q", ISA_SPEC_CLASS_20191213, 2, 2},
127 {"q", ISA_SPEC_CLASS_20190608, 2, 2},
128 {"q", ISA_SPEC_CLASS_2P2, 2, 0},
129
130 {"c", ISA_SPEC_CLASS_20191213, 2, 0},
131 {"c", ISA_SPEC_CLASS_20190608, 2, 0},
132 {"c", ISA_SPEC_CLASS_2P2, 2, 0},
133
134 {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
135 {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
136
137 {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
138 {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
139
140 {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
141
142 {"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
143 {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
144 {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
145
146 /* Terminate the list. */
147 {NULL, 0, 0, 0}
148};
149
150#ifndef DEFAULT_ARCH
151#define DEFAULT_ARCH "riscv64"
152#endif
153
154#ifndef DEFAULT_RISCV_ATTR
155#define DEFAULT_RISCV_ATTR 0
156#endif
157
158/* Let riscv_after_parse_args set the default value according to xlen. */
159#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
160#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
161#endif
162
163/* Need to sync the version with RISC-V compiler. */
164#ifndef DEFAULT_RISCV_ISA_SPEC
165#define DEFAULT_RISCV_ISA_SPEC "2.2"
166#endif
167
168#ifndef DEFAULT_RISCV_PRIV_SPEC
169#define DEFAULT_RISCV_PRIV_SPEC "1.11"
170#endif
171
172static const char default_arch[] = DEFAULT_ARCH;
173static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
174static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
175static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
176
177static unsigned xlen = 0; /* The width of an x-register. */
178static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
179static bool rve_abi = false;
180enum float_abi
181{
182 FLOAT_ABI_DEFAULT = -1,
183 FLOAT_ABI_SOFT,
184 FLOAT_ABI_SINGLE,
185 FLOAT_ABI_DOUBLE,
186 FLOAT_ABI_QUAD
187};
188static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
189
190#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
191#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
192
193static unsigned elf_flags = 0;
194
195/* Set the default_isa_spec. Return 0 if the spec isn't supported.
196 Otherwise, return 1. */
197
198static int
199riscv_set_default_isa_spec (const char *s)
200{
201 enum riscv_spec_class class = ISA_SPEC_CLASS_NONE;
202 RISCV_GET_ISA_SPEC_CLASS (s, class);
203 if (class == ISA_SPEC_CLASS_NONE)
204 {
205 as_bad ("unknown default ISA spec `%s' set by "
206 "-misa-spec or --with-isa-spec", s);
207 return 0;
208 }
209 else
210 default_isa_spec = class;
211 return 1;
212}
213
214/* Set the default_priv_spec. Find the privileged elf attributes when
215 the input string is NULL. Return 0 if the spec isn't supported.
216 Otherwise, return 1. */
217
218static int
219riscv_set_default_priv_spec (const char *s)
220{
221 enum riscv_spec_class class = PRIV_SPEC_CLASS_NONE;
222 unsigned major, minor, revision;
223 obj_attribute *attr;
224
225 RISCV_GET_PRIV_SPEC_CLASS (s, class);
226 if (class != PRIV_SPEC_CLASS_NONE)
227 {
228 default_priv_spec = class;
229 return 1;
230 }
231
232 if (s != NULL)
233 {
234 as_bad (_("unknown default privileged spec `%s' set by "
235 "-mpriv-spec or --with-priv-spec"), s);
236 return 0;
237 }
238
239 /* Set the default_priv_spec by the privileged elf attributes. */
240 attr = elf_known_obj_attributes_proc (stdoutput);
241 major = (unsigned) attr[Tag_RISCV_priv_spec].i;
242 minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
243 revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
244 /* Version 0.0.0 is the default value and meningless. */
245 if (major == 0 && minor == 0 && revision == 0)
246 return 1;
247
248 riscv_get_priv_spec_class_from_numbers (major, minor, revision, &class);
249 if (class != PRIV_SPEC_CLASS_NONE)
250 {
251 default_priv_spec = class;
252 return 1;
253 }
254
255 /* Still can not find the privileged spec class. */
256 as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
257 "privileged elf attributes"), major, minor, revision);
258 return 0;
259}
260
261/* This is the set of options which the .option pseudo-op may modify. */
262struct riscv_set_options
263{
264 int pic; /* Generate position-independent code. */
265 int rvc; /* Generate RVC code. */
266 int rve; /* Generate RVE code. */
267 int relax; /* Emit relocs the linker is allowed to relax. */
268 int arch_attr; /* Emit architecture and privileged elf attributes. */
269 int csr_check; /* Enable the CSR checking. */
270};
271
272static struct riscv_set_options riscv_opts =
273{
274 0, /* pic */
275 0, /* rvc */
276 0, /* rve */
277 1, /* relax */
278 DEFAULT_RISCV_ATTR, /* arch_attr */
279 0, /* csr_check */
280};
281
282static void
283riscv_set_rvc (bool rvc_value)
284{
285 if (rvc_value)
286 elf_flags |= EF_RISCV_RVC;
287
288 riscv_opts.rvc = rvc_value;
289}
290
291static void
292riscv_set_rve (bool rve_value)
293{
294 riscv_opts.rve = rve_value;
295}
296
297static riscv_subset_list_t riscv_subsets;
298
299static bool
300riscv_subset_supports (const char *feature)
301{
302 struct riscv_subset_t *subset;
303
304 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
305 return true;
306
307 return riscv_lookup_subset (&riscv_subsets, feature, &subset);
308}
309
310static bool
311riscv_multi_subset_supports (enum riscv_insn_class insn_class)
312{
313 switch (insn_class)
314 {
315 case INSN_CLASS_I: return riscv_subset_supports ("i");
316 case INSN_CLASS_C: return riscv_subset_supports ("c");
317 case INSN_CLASS_A: return riscv_subset_supports ("a");
318 case INSN_CLASS_M: return riscv_subset_supports ("m");
319 case INSN_CLASS_F: return riscv_subset_supports ("f");
320 case INSN_CLASS_D: return riscv_subset_supports ("d");
321 case INSN_CLASS_Q: return riscv_subset_supports ("q");
322
323 case INSN_CLASS_F_AND_C:
324 return (riscv_subset_supports ("f")
325 && riscv_subset_supports ("c"));
326 case INSN_CLASS_D_AND_C:
327 return (riscv_subset_supports ("d")
328 && riscv_subset_supports ("c"));
329
330 case INSN_CLASS_ZICSR:
331 return riscv_subset_supports ("zicsr");
332 case INSN_CLASS_ZIFENCEI:
333 return riscv_subset_supports ("zifencei");
334 case INSN_CLASS_ZIHINTPAUSE:
335 return riscv_subset_supports ("zihintpause");
336
337 case INSN_CLASS_ZBB:
338 return riscv_subset_supports ("zbb");
339
340 case INSN_CLASS_ZBA:
341 return riscv_subset_supports ("zba");
342
343 case INSN_CLASS_ZBC:
344 return riscv_subset_supports ("zbc");
345
346 default:
347 as_fatal ("internal: unreachable");
348 return false;
349 }
350}
351
352/* Handle of the extension with version hash table. */
353static htab_t ext_version_hash = NULL;
354
355static htab_t
356init_ext_version_hash (void)
357{
358 const struct riscv_ext_version *table = ext_version_table;
359 htab_t hash = str_htab_create ();
360 int i = 0;
361
362 while (table[i].name)
363 {
364 const char *name = table[i].name;
365 if (str_hash_insert (hash, name, &table[i], 0) != NULL)
366 as_fatal (_("internal: duplicate %s"), name);
367
368 i++;
369 while (table[i].name
370 && strcmp (table[i].name, name) == 0)
371 i++;
372 }
373
374 return hash;
375}
376
377static void
378riscv_get_default_ext_version (const char *name,
379 int *major_version,
380 int *minor_version)
381{
382 struct riscv_ext_version *ext;
383
384 if (name == NULL || default_isa_spec == ISA_SPEC_CLASS_NONE)
385 return;
386
387 ext = (struct riscv_ext_version *) str_hash_find (ext_version_hash, name);
388 while (ext
389 && ext->name
390 && strcmp (ext->name, name) == 0)
391 {
392 if (ext->isa_spec_class == ISA_SPEC_CLASS_DRAFT
393 || ext->isa_spec_class == default_isa_spec)
394 {
395 *major_version = ext->major_version;
396 *minor_version = ext->minor_version;
397 return;
398 }
399 ext++;
400 }
401}
402
403/* Set which ISA and extensions are available. */
404
405static void
406riscv_set_arch (const char *s)
407{
408 riscv_parse_subset_t rps;
409 rps.subset_list = &riscv_subsets;
410 rps.error_handler = as_bad;
411 rps.xlen = &xlen;
412 rps.get_default_version = riscv_get_default_ext_version;
413
414 if (s == NULL)
415 return;
416
417 riscv_release_subset_list (&riscv_subsets);
418 riscv_parse_subset (&rps, s);
419}
420
421/* Indicate -mabi option is explictly set. */
422static bool explicit_mabi = false;
423
424static void
425riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve)
426{
427 abi_xlen = new_xlen;
428 float_abi = new_float_abi;
429 rve_abi = rve;
430}
431
432/* If the -mabi option isn't set, then set the abi according to the
433 ISA string. Otherwise, check if there is any conflict. */
434
435static void
436riscv_set_abi_by_arch (void)
437{
438 if (!explicit_mabi)
439 {
440 if (riscv_subset_supports ("q"))
441 riscv_set_abi (xlen, FLOAT_ABI_QUAD, false);
442 else if (riscv_subset_supports ("d"))
443 riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false);
444 else
445 riscv_set_abi (xlen, FLOAT_ABI_SOFT, false);
446 }
447 else
448 {
449 gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
450 if (abi_xlen > xlen)
451 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
452 else if (abi_xlen < xlen)
453 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
454 }
455
456 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
457 elf_flags &= ~EF_RISCV_FLOAT_ABI;
458 elf_flags |= float_abi << 1;
459
460 if (rve_abi)
461 elf_flags |= EF_RISCV_RVE;
462}
463
464/* Handle of the OPCODE hash table. */
465static htab_t op_hash = NULL;
466
467/* Handle of the type of .insn hash table. */
468static htab_t insn_type_hash = NULL;
469
470/* This array holds the chars that always start a comment. If the
471 pre-processor is disabled, these aren't very useful. */
472const char comment_chars[] = "#";
473
474/* This array holds the chars that only start a comment at the beginning of
475 a line. If the line seems to have the form '# 123 filename'
476 .line and .file directives will appear in the pre-processed output
477
478 Note that input_file.c hand checks for '#' at the beginning of the
479 first line of the input file. This is because the compiler outputs
480 #NO_APP at the beginning of its output.
481
482 Also note that C style comments are always supported. */
483const char line_comment_chars[] = "#";
484
485/* This array holds machine specific line separator characters. */
486const char line_separator_chars[] = ";";
487
488/* Chars that can be used to separate mant from exp in floating point nums. */
489const char EXP_CHARS[] = "eE";
490
491/* Chars that mean this number is a floating point constant.
492 As in 0f12.456 or 0d1.2345e12. */
493const char FLT_CHARS[] = "rRsSfFdDxXpP";
494
495/* Indicate we are already assemble any instructions or not. */
496static bool start_assemble = false;
497
498/* Indicate ELF attributes are explicitly set. */
499static bool explicit_attr = false;
500
501/* Indicate CSR or priv instructions are explicitly used. */
502static bool explicit_priv_attr = false;
503
504/* Macros for encoding relaxation state for RVC branches and far jumps. */
505#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
506 ((relax_substateT) \
507 (0xc0000000 \
508 | ((uncond) ? 1 : 0) \
509 | ((rvc) ? 2 : 0) \
510 | ((length) << 2)))
511#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
512#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
513#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
514#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
515
516/* Is the given value a sign-extended 32-bit value? */
517#define IS_SEXT_32BIT_NUM(x) \
518 (((x) &~ (offsetT) 0x7fffffff) == 0 \
519 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
520
521/* Is the given value a zero-extended 32-bit value? Or a negated one? */
522#define IS_ZEXT_32BIT_NUM(x) \
523 (((x) &~ (offsetT) 0xffffffff) == 0 \
524 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
525
526/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
527 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
528#define INSERT_OPERAND(FIELD, INSN, VALUE) \
529 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
530
531/* Determine if an instruction matches an opcode. */
532#define OPCODE_MATCHES(OPCODE, OP) \
533 (((OPCODE) & MASK_##OP) == MATCH_##OP)
534
535static char *expr_end;
536
537/* The default target format to use. */
538
539const char *
540riscv_target_format (void)
541{
542 if (target_big_endian)
543 return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
544 else
545 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
546}
547
548/* Return the length of instruction INSN. */
549
550static inline unsigned int
551insn_length (const struct riscv_cl_insn *insn)
552{
553 return riscv_insn_length (insn->insn_opcode);
554}
555
556/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
557
558static void
559create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
560{
561 insn->insn_mo = mo;
562 insn->insn_opcode = mo->match;
563 insn->frag = NULL;
564 insn->where = 0;
565 insn->fixp = NULL;
566}
567
568/* Install INSN at the location specified by its "frag" and "where" fields. */
569
570static void
571install_insn (const struct riscv_cl_insn *insn)
572{
573 char *f = insn->frag->fr_literal + insn->where;
574 number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
575}
576
577/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
578 and install the opcode in the new location. */
579
580static void
581move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
582{
583 insn->frag = frag;
584 insn->where = where;
585 if (insn->fixp != NULL)
586 {
587 insn->fixp->fx_frag = frag;
588 insn->fixp->fx_where = where;
589 }
590 install_insn (insn);
591}
592
593/* Add INSN to the end of the output. */
594
595static void
596add_fixed_insn (struct riscv_cl_insn *insn)
597{
598 char *f = frag_more (insn_length (insn));
599 move_insn (insn, frag_now, f - frag_now->fr_literal);
600}
601
602static void
603add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
604 relax_substateT subtype, symbolS *symbol, offsetT offset)
605{
606 frag_grow (max_chars);
607 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
608 frag_var (rs_machine_dependent, max_chars, var,
609 subtype, symbol, offset, NULL);
610}
611
612/* Compute the length of a branch sequence, and adjust the stored length
613 accordingly. If FRAGP is NULL, the worst-case length is returned. */
614
615static unsigned
616relaxed_branch_length (fragS *fragp, asection *sec, int update)
617{
618 int jump, rvc, length = 8;
619
620 if (!fragp)
621 return length;
622
623 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
624 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
625 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
626
627 /* Assume jumps are in range; the linker will catch any that aren't. */
628 length = jump ? 4 : 8;
629
630 if (fragp->fr_symbol != NULL
631 && S_IS_DEFINED (fragp->fr_symbol)
632 && !S_IS_WEAK (fragp->fr_symbol)
633 && sec == S_GET_SEGMENT (fragp->fr_symbol))
634 {
635 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
636 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
637 val -= fragp->fr_address + fragp->fr_fix;
638
639 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
640 length = 2;
641 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
642 length = 4;
643 else if (!jump && rvc)
644 length = 6;
645 }
646
647 if (update)
648 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
649
650 return length;
651}
652
653/* Information about an opcode name, mnemonics and its value. */
654struct opcode_name_t
655{
656 const char *name;
657 unsigned int val;
658};
659
660/* List for all supported opcode name. */
661static const struct opcode_name_t opcode_name_list[] =
662{
663 {"C0", 0x0},
664 {"C1", 0x1},
665 {"C2", 0x2},
666
667 {"LOAD", 0x03},
668 {"LOAD_FP", 0x07},
669 {"CUSTOM_0", 0x0b},
670 {"MISC_MEM", 0x0f},
671 {"OP_IMM", 0x13},
672 {"AUIPC", 0x17},
673 {"OP_IMM_32", 0x1b},
674 /* 48b 0x1f. */
675
676 {"STORE", 0x23},
677 {"STORE_FP", 0x27},
678 {"CUSTOM_1", 0x2b},
679 {"AMO", 0x2f},
680 {"OP", 0x33},
681 {"LUI", 0x37},
682 {"OP_32", 0x3b},
683 /* 64b 0x3f. */
684
685 {"MADD", 0x43},
686 {"MSUB", 0x47},
687 {"NMADD", 0x4f},
688 {"NMSUB", 0x4b},
689 {"OP_FP", 0x53},
690 /*reserved 0x57. */
691 {"CUSTOM_2", 0x5b},
692 /* 48b 0x5f. */
693
694 {"BRANCH", 0x63},
695 {"JALR", 0x67},
696 /*reserved 0x5b. */
697 {"JAL", 0x6f},
698 {"SYSTEM", 0x73},
699 /*reserved 0x77. */
700 {"CUSTOM_3", 0x7b},
701 /* >80b 0x7f. */
702
703 {NULL, 0}
704};
705
706/* Hash table for lookup opcode name. */
707static htab_t opcode_names_hash = NULL;
708
709/* Initialization for hash table of opcode name. */
710
711static void
712init_opcode_names_hash (void)
713{
714 const struct opcode_name_t *opcode;
715
716 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
717 if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
718 as_fatal (_("internal: duplicate %s"), opcode->name);
719}
720
721/* Find `s` is a valid opcode name or not, return the opcode name info
722 if found. */
723
724static const struct opcode_name_t *
725opcode_name_lookup (char **s)
726{
727 char *e;
728 char save_c;
729 struct opcode_name_t *o;
730
731 /* Find end of name. */
732 e = *s;
733 if (is_name_beginner (*e))
734 ++e;
735 while (is_part_of_name (*e))
736 ++e;
737
738 /* Terminate name. */
739 save_c = *e;
740 *e = '\0';
741
742 o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
743
744 /* Advance to next token if one was recognized. */
745 if (o)
746 *s = e;
747
748 *e = save_c;
749 expr_end = e;
750
751 return o;
752}
753
754enum reg_class
755{
756 RCLASS_GPR,
757 RCLASS_FPR,
758 RCLASS_MAX,
759
760 RCLASS_CSR
761};
762
763static htab_t reg_names_hash = NULL;
764static htab_t csr_extra_hash = NULL;
765
766#define ENCODE_REG_HASH(cls, n) \
767 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
768#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
769#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
770
771static void
772hash_reg_name (enum reg_class class, const char *name, unsigned n)
773{
774 void *hash = ENCODE_REG_HASH (class, n);
775 if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
776 as_fatal (_("internal: duplicate %s"), name);
777}
778
779static void
780hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
781{
782 unsigned i;
783
784 for (i = 0; i < n; i++)
785 hash_reg_name (class, names[i], i);
786}
787
788/* Init hash table csr_extra_hash to handle CSR. */
789
790static void
791riscv_init_csr_hash (const char *name,
792 unsigned address,
793 enum riscv_csr_class class,
794 enum riscv_spec_class define_version,
795 enum riscv_spec_class abort_version)
796{
797 struct riscv_csr_extra *entry, *pre_entry;
798 bool need_enrty = true;
799
800 pre_entry = NULL;
801 entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
802 while (need_enrty && entry != NULL)
803 {
804 if (entry->csr_class == class
805 && entry->address == address
806 && entry->define_version == define_version
807 && entry->abort_version == abort_version)
808 need_enrty = false;
809 pre_entry = entry;
810 entry = entry->next;
811 }
812
813 /* Duplicate CSR. */
814 if (!need_enrty)
815 return;
816
817 entry = XNEW (struct riscv_csr_extra);
818 entry->csr_class = class;
819 entry->address = address;
820 entry->define_version = define_version;
821 entry->abort_version = abort_version;
822 entry->next = NULL;
823
824 if (pre_entry == NULL)
825 str_hash_insert (csr_extra_hash, name, entry, 0);
826 else
827 pre_entry->next = entry;
828}
829
830/* Return the CSR address after checking the ISA dependency and
831 the privileged spec version.
832
833 There are one warning and two errors for CSR,
834
835 Invalid CSR: the CSR was defined, but isn't allowed for the current ISA
836 or the privileged spec, report warning only if -mcsr-check is set.
837 Unknown CSR: the CSR has never been defined, report error.
838 Improper CSR: the CSR number over the range (> 0xfff), report error. */
839
840static unsigned int
841riscv_csr_address (const char *csr_name,
842 struct riscv_csr_extra *entry)
843{
844 struct riscv_csr_extra *saved_entry = entry;
845 enum riscv_csr_class csr_class = entry->csr_class;
846 bool need_check_version = true;
847 bool result = true;
848
849 switch (csr_class)
850 {
851 case CSR_CLASS_I:
852 result = riscv_subset_supports ("i");
853 break;
854 case CSR_CLASS_I_32:
855 result = (xlen == 32 && riscv_subset_supports ("i"));
856 break;
857 case CSR_CLASS_F:
858 result = riscv_subset_supports ("f");
859 need_check_version = false;
860 break;
861 case CSR_CLASS_DEBUG:
862 need_check_version = false;
863 break;
864 default:
865 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
866 }
867
868 if (riscv_opts.csr_check && !result)
869 as_warn (_("invalid CSR `%s' for the current ISA"), csr_name);
870
871 while (entry != NULL)
872 {
873 if (!need_check_version
874 || (default_priv_spec >= entry->define_version
875 && default_priv_spec < entry->abort_version))
876 {
877 /* Find the CSR according to the specific version. */
878 return entry->address;
879 }
880 entry = entry->next;
881 }
882
883 /* Can not find the CSR address from the chosen privileged version,
884 so use the newly defined value. */
885 if (riscv_opts.csr_check)
886 {
887 const char *priv_name = NULL;
888 RISCV_GET_PRIV_SPEC_NAME (priv_name, default_priv_spec);
889 if (priv_name != NULL)
890 as_warn (_("invalid CSR `%s' for the privileged spec `%s'"),
891 csr_name, priv_name);
892 }
893
894 return saved_entry->address;
895}
896
897/* Return -1 if the CSR has never been defined. Otherwise, return
898 the address. */
899
900static unsigned int
901reg_csr_lookup_internal (const char *s)
902{
903 struct riscv_csr_extra *r =
904 (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s);
905
906 if (r == NULL)
907 return -1U;
908
909 return riscv_csr_address (s, r);
910}
911
912static unsigned int
913reg_lookup_internal (const char *s, enum reg_class class)
914{
915 void *r;
916
917 if (class == RCLASS_CSR)
918 return reg_csr_lookup_internal (s);
919
920 r = str_hash_find (reg_names_hash, s);
921 if (r == NULL || DECODE_REG_CLASS (r) != class)
922 return -1;
923
924 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
925 return -1;
926
927 return DECODE_REG_NUM (r);
928}
929
930static bool
931reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
932{
933 char *e;
934 char save_c;
935 int reg = -1;
936
937 /* Find end of name. */
938 e = *s;
939 if (is_name_beginner (*e))
940 ++e;
941 while (is_part_of_name (*e))
942 ++e;
943
944 /* Terminate name. */
945 save_c = *e;
946 *e = '\0';
947
948 /* Look for the register. Advance to next token if one was recognized. */
949 if ((reg = reg_lookup_internal (*s, class)) >= 0)
950 *s = e;
951
952 *e = save_c;
953 if (regnop)
954 *regnop = reg;
955 return reg >= 0;
956}
957
958static bool
959arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
960{
961 const char *p = strchr (*s, ',');
962 size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
963
964 if (len == 0)
965 return false;
966
967 for (i = 0; i < size; i++)
968 if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
969 {
970 *regnop = i;
971 *s += len;
972 return true;
973 }
974
975 return false;
976}
977
978/* For consistency checking, verify that all bits are specified either
979 by the match/mask part of the instruction definition, or by the
980 operand list. The `length` could be 0, 4 or 8, 0 for auto detection. */
981
982static bool
983validate_riscv_insn (const struct riscv_opcode *opc, int length)
984{
985 const char *p = opc->args;
986 char c;
987 insn_t used_bits = opc->mask;
988 int insn_width;
989 insn_t required_bits;
990
991 if (length == 0)
992 insn_width = 8 * riscv_insn_length (opc->match);
993 else
994 insn_width = 8 * length;
995
996 required_bits = ~0ULL >> (64 - insn_width);
997
998 if ((used_bits & opc->match) != (opc->match & required_bits))
999 {
1000 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
1001 opc->name, opc->args);
1002 return false;
1003 }
1004
1005#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
1006 while (*p)
1007 switch (c = *p++)
1008 {
1009 case 'C': /* RVC */
1010 switch (c = *p++)
1011 {
1012 case 'U': break; /* CRS1, constrained to equal RD. */
1013 case 'c': break; /* CRS1, constrained to equal sp. */
1014 case 'T': /* CRS2, floating point. */
1015 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
1016 case 'S': /* CRS1S, floating point. */
1017 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
1018 case 'w': break; /* CRS1S, constrained to equal RD. */
1019 case 'D': /* CRS2S, floating point. */
1020 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
1021 case 'x': break; /* CRS2S, constrained to equal RD. */
1022 case 'z': break; /* CRS2S, constrained to be x0. */
1023 case '>': /* CITYPE immediate, compressed shift. */
1024 case 'u': /* CITYPE immediate, compressed lui. */
1025 case 'v': /* CITYPE immediate, li to compressed lui. */
1026 case 'o': /* CITYPE immediate, allow zero. */
1027 case 'j': used_bits |= ENCODE_CITYPE_IMM (-1U); break;
1028 case 'L': used_bits |= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
1029 case 'm': used_bits |= ENCODE_CITYPE_LWSP_IMM (-1U); break;
1030 case 'n': used_bits |= ENCODE_CITYPE_LDSP_IMM (-1U); break;
1031 case '6': used_bits |= ENCODE_CSSTYPE_IMM (-1U); break;
1032 case 'M': used_bits |= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
1033 case 'N': used_bits |= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
1034 case '8': used_bits |= ENCODE_CIWTYPE_IMM (-1U); break;
1035 case 'K': used_bits |= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
1036 /* CLTYPE and CSTYPE have the same immediate encoding. */
1037 case '5': used_bits |= ENCODE_CLTYPE_IMM (-1U); break;
1038 case 'k': used_bits |= ENCODE_CLTYPE_LW_IMM (-1U); break;
1039 case 'l': used_bits |= ENCODE_CLTYPE_LD_IMM (-1U); break;
1040 case 'p': used_bits |= ENCODE_CBTYPE_IMM (-1U); break;
1041 case 'a': used_bits |= ENCODE_CJTYPE_IMM (-1U); break;
1042 case 'F': /* Compressed funct for .insn directive. */
1043 switch (c = *p++)
1044 {
1045 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
1046 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
1047 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
1048 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
1049 default:
1050 as_bad (_("internal: bad RISC-V opcode "
1051 "(unknown operand type `CF%c'): %s %s"),
1052 c, opc->name, opc->args);
1053 return false;
1054 }
1055 break;
1056 default:
1057 as_bad (_("internal: bad RISC-V opcode "
1058 "(unknown operand type `C%c'): %s %s"),
1059 c, opc->name, opc->args);
1060 return false;
1061 }
1062 break;
1063 case ',': break;
1064 case '(': break;
1065 case ')': break;
1066 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
1067 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
1068 case 'A': break; /* Macro operand, must be symbol. */
1069 case 'B': break; /* Macro operand, must be symbol or constant. */
1070 case 'I': break; /* Macro operand, must be constant. */
1071 case 'D': /* RD, floating point. */
1072 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
1073 case 'Z': /* RS1, CSR number. */
1074 case 'S': /* RS1, floating point. */
1075 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
1076 case 'U': /* RS1 and RS2 are the same, floating point. */
1077 USE_BITS (OP_MASK_RS1, OP_SH_RS1);
1078 /* Fall through. */
1079 case 'T': /* RS2, floating point. */
1080 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
1081 case 'R': /* RS3, floating point. */
1082 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
1083 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
1084 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
1085 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
1086 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
1087 case 'o': /* ITYPE immediate, load displacement. */
1088 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
1089 case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
1090 case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
1091 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
1092 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
1093 case 'z': break; /* Zero immediate. */
1094 case '[': break; /* Unused operand. */
1095 case ']': break; /* Unused operand. */
1096 case '0': break; /* AMO displacement, must to zero. */
1097 case '1': break; /* Relaxation operand. */
1098 case 'F': /* Funct for .insn directive. */
1099 switch (c = *p++)
1100 {
1101 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
1102 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
1103 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
1104 default:
1105 as_bad (_("internal: bad RISC-V opcode "
1106 "(unknown operand type `F%c'): %s %s"),
1107 c, opc->name, opc->args);
1108 return false;
1109 }
1110 break;
1111 case 'O': /* Opcode for .insn directive. */
1112 switch (c = *p++)
1113 {
1114 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
1115 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
1116 default:
1117 as_bad (_("internal: bad RISC-V opcode "
1118 "(unknown operand type `F%c'): %s %s"),
1119 c, opc->name, opc->args);
1120 return false;
1121 }
1122 break;
1123 default:
1124 as_bad (_("internal: bad RISC-V opcode "
1125 "(unknown operand type `%c'): %s %s"),
1126 c, opc->name, opc->args);
1127 return false;
1128 }
1129#undef USE_BITS
1130 if (used_bits != required_bits)
1131 {
1132 as_bad (_("internal: bad RISC-V opcode "
1133 "(bits 0x%lx undefined): %s %s"),
1134 ~(unsigned long)(used_bits & required_bits),
1135 opc->name, opc->args);
1136 return false;
1137 }
1138 return true;
1139}
1140
1141struct percent_op_match
1142{
1143 const char *str;
1144 bfd_reloc_code_real_type reloc;
1145};
1146
1147/* Common hash table initialization function for instruction and .insn
1148 directive. */
1149
1150static htab_t
1151init_opcode_hash (const struct riscv_opcode *opcodes,
1152 bool insn_directive_p)
1153{
1154 int i = 0;
1155 int length;
1156 htab_t hash = str_htab_create ();
1157 while (opcodes[i].name)
1158 {
1159 const char *name = opcodes[i].name;
1160 if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL)
1161 as_fatal (_("internal: duplicate %s"), name);
1162
1163 do
1164 {
1165 if (opcodes[i].pinfo != INSN_MACRO)
1166 {
1167 if (insn_directive_p)
1168 length = ((name[0] == 'c') ? 2 : 4);
1169 else
1170 length = 0; /* Let assembler determine the length. */
1171 if (!validate_riscv_insn (&opcodes[i], length))
1172 as_fatal (_("internal: broken assembler. "
1173 "No assembly attempted"));
1174 }
1175 else
1176 gas_assert (!insn_directive_p);
1177 ++i;
1178 }
1179 while (opcodes[i].name && !strcmp (opcodes[i].name, name));
1180 }
1181
1182 return hash;
1183}
1184
1185/* This function is called once, at assembler startup time. It should set up
1186 all the tables, etc. that the MD part of the assembler will need. */
1187
1188void
1189md_begin (void)
1190{
1191 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
1192
1193 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
1194 as_warn (_("could not set architecture and machine"));
1195
1196 op_hash = init_opcode_hash (riscv_opcodes, false);
1197 insn_type_hash = init_opcode_hash (riscv_insn_types, true);
1198
1199 reg_names_hash = str_htab_create ();
1200 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
1201 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
1202 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
1203 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
1204 /* Add "fp" as an alias for "s0". */
1205 hash_reg_name (RCLASS_GPR, "fp", 8);
1206
1207 /* Create and insert CSR hash tables. */
1208 csr_extra_hash = str_htab_create ();
1209#define DECLARE_CSR(name, num, class, define_version, abort_version) \
1210 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1211#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1212 DECLARE_CSR(name, num, class, define_version, abort_version);
1213#include "opcode/riscv-opc.h"
1214#undef DECLARE_CSR
1215
1216 opcode_names_hash = str_htab_create ();
1217 init_opcode_names_hash ();
1218
1219 /* Set the default alignment for the text section. */
1220 record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
1221}
1222
1223static insn_t
1224riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
1225{
1226 switch (reloc_type)
1227 {
1228 case BFD_RELOC_32:
1229 return value;
1230
1231 case BFD_RELOC_RISCV_HI20:
1232 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
1233
1234 case BFD_RELOC_RISCV_LO12_S:
1235 return ENCODE_STYPE_IMM (value);
1236
1237 case BFD_RELOC_RISCV_LO12_I:
1238 return ENCODE_ITYPE_IMM (value);
1239
1240 default:
1241 abort ();
1242 }
1243}
1244
1245/* Output an instruction. IP is the instruction information.
1246 ADDRESS_EXPR is an operand of the instruction to be used with
1247 RELOC_TYPE. */
1248
1249static void
1250append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
1251 bfd_reloc_code_real_type reloc_type)
1252{
1253 dwarf2_emit_insn (0);
1254
1255 if (reloc_type != BFD_RELOC_UNUSED)
1256 {
1257 reloc_howto_type *howto;
1258
1259 gas_assert (address_expr);
1260 if (reloc_type == BFD_RELOC_12_PCREL
1261 || reloc_type == BFD_RELOC_RISCV_JMP)
1262 {
1263 int j = reloc_type == BFD_RELOC_RISCV_JMP;
1264 int best_case = riscv_insn_length (ip->insn_opcode);
1265 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
1266
1267 if (now_seg == absolute_section)
1268 {
1269 as_bad (_("relaxable branches not supported in absolute section"));
1270 return;
1271 }
1272
1273 add_relaxed_insn (ip, worst_case, best_case,
1274 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
1275 address_expr->X_add_symbol,
1276 address_expr->X_add_number);
1277 return;
1278 }
1279 else
1280 {
1281 howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
1282 if (howto == NULL)
1283 as_bad (_("internal: usupported RISC-V relocation number %d"),
1284 reloc_type);
1285
1286 ip->fixp = fix_new_exp (ip->frag, ip->where,
1287 bfd_get_reloc_size (howto),
1288 address_expr, false, reloc_type);
1289
1290 ip->fixp->fx_tcbit = riscv_opts.relax;
1291 }
1292 }
1293
1294 add_fixed_insn (ip);
1295 install_insn (ip);
1296
1297 /* We need to start a new frag after any instruction that can be
1298 optimized away or compressed by the linker during relaxation, to prevent
1299 the assembler from computing static offsets across such an instruction.
1300 This is necessary to get correct EH info. */
1301 if (reloc_type == BFD_RELOC_RISCV_HI20
1302 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20
1303 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20
1304 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
1305 {
1306 frag_wane (frag_now);
1307 frag_new (0);
1308 }
1309}
1310
1311/* Build an instruction created by a macro expansion. This is passed
1312 a pointer to the count of instructions created so far, an expression,
1313 the name of the instruction to build, an operand format string, and
1314 corresponding arguments. */
1315
1316static void
1317macro_build (expressionS *ep, const char *name, const char *fmt, ...)
1318{
1319 const struct riscv_opcode *mo;
1320 struct riscv_cl_insn insn;
1321 bfd_reloc_code_real_type r;
1322 va_list args;
1323
1324 va_start (args, fmt);
1325
1326 r = BFD_RELOC_UNUSED;
1327 mo = (struct riscv_opcode *) str_hash_find (op_hash, name);
1328 gas_assert (mo);
1329
1330 /* Find a non-RVC variant of the instruction. append_insn will compress
1331 it if possible. */
1332 while (riscv_insn_length (mo->match) < 4)
1333 mo++;
1334 gas_assert (strcmp (name, mo->name) == 0);
1335
1336 create_insn (&insn, mo);
1337 for (;;)
1338 {
1339 switch (*fmt++)
1340 {
1341 case 'd':
1342 INSERT_OPERAND (RD, insn, va_arg (args, int));
1343 continue;
1344
1345 case 's':
1346 INSERT_OPERAND (RS1, insn, va_arg (args, int));
1347 continue;
1348
1349 case 't':
1350 INSERT_OPERAND (RS2, insn, va_arg (args, int));
1351 continue;
1352
1353 case 'j':
1354 case 'u':
1355 case 'q':
1356 gas_assert (ep != NULL);
1357 r = va_arg (args, int);
1358 continue;
1359
1360 case '\0':
1361 break;
1362 case ',':
1363 continue;
1364 default:
1365 as_fatal (_("internal: invalid macro"));
1366 }
1367 break;
1368 }
1369 va_end (args);
1370 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
1371
1372 append_insn (&insn, ep, r);
1373}
1374
1375/* Build an instruction created by a macro expansion. Like md_assemble but
1376 accept a printf-style format string and arguments. */
1377
1378static void
1379md_assemblef (const char *format, ...)
1380{
1381 char *buf = NULL;
1382 va_list ap;
1383 int r;
1384
1385 va_start (ap, format);
1386
1387 r = vasprintf (&buf, format, ap);
1388
1389 if (r < 0)
1390 as_fatal (_("internal: vasprintf failed"));
1391
1392 md_assemble (buf);
1393 free(buf);
1394
1395 va_end (ap);
1396}
1397
1398/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1399 unset. */
1400
1401static void
1402normalize_constant_expr (expressionS *ex)
1403{
1404 if (xlen > 32)
1405 return;
1406 if ((ex->X_op == O_constant || ex->X_op == O_symbol)
1407 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
1408 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
1409 - 0x80000000);
1410}
1411
1412/* Fail if an expression EX is not a constant. IP is the instruction using EX.
1413 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1414
1415static void
1416check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
1417 bool maybe_csr)
1418{
1419 if (ex->X_op == O_big)
1420 as_bad (_("unsupported large constant"));
1421 else if (maybe_csr && ex->X_op == O_symbol)
1422 as_bad (_("unknown CSR `%s'"),
1423 S_GET_NAME (ex->X_add_symbol));
1424 else if (ex->X_op != O_constant)
1425 as_bad (_("instruction %s requires absolute expression"),
1426 ip->insn_mo->name);
1427 normalize_constant_expr (ex);
1428}
1429
1430static symbolS *
1431make_internal_label (void)
1432{
1433 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now,
1434 frag_now_fix ());
1435}
1436
1437/* Load an entry from the GOT. */
1438
1439static void
1440pcrel_access (int destreg, int tempreg, expressionS *ep,
1441 const char *lo_insn, const char *lo_pattern,
1442 bfd_reloc_code_real_type hi_reloc,
1443 bfd_reloc_code_real_type lo_reloc)
1444{
1445 expressionS ep2;
1446 ep2.X_op = O_symbol;
1447 ep2.X_add_symbol = make_internal_label ();
1448 ep2.X_add_number = 0;
1449
1450 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc);
1451 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc);
1452}
1453
1454static void
1455pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn,
1456 bfd_reloc_code_real_type hi_reloc,
1457 bfd_reloc_code_real_type lo_reloc)
1458{
1459 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc);
1460}
1461
1462static void
1463pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn,
1464 bfd_reloc_code_real_type hi_reloc,
1465 bfd_reloc_code_real_type lo_reloc)
1466{
1467 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc);
1468}
1469
1470/* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1471
1472static void
1473riscv_call (int destreg, int tempreg, expressionS *ep,
1474 bfd_reloc_code_real_type reloc)
1475{
1476 /* Ensure the jalr is emitted to the same frag as the auipc. */
1477 frag_grow (8);
1478 macro_build (ep, "auipc", "d,u", tempreg, reloc);
1479 macro_build (NULL, "jalr", "d,s", destreg, tempreg);
1480 /* See comment at end of append_insn. */
1481 frag_wane (frag_now);
1482 frag_new (0);
1483}
1484
1485/* Load an integer constant into a register. */
1486
1487static void
1488load_const (int reg, expressionS *ep)
1489{
1490 int shift = RISCV_IMM_BITS;
1491 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1);
1492 expressionS upper = *ep, lower = *ep;
1493 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign;
1494 upper.X_add_number -= lower.X_add_number;
1495
1496 if (ep->X_op != O_constant)
1497 {
1498 as_bad (_("unsupported large constant"));
1499 return;
1500 }
1501
1502 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number))
1503 {
1504 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1505 while (((upper.X_add_number >> shift) & 1) == 0)
1506 shift++;
1507
1508 upper.X_add_number = (int64_t) upper.X_add_number >> shift;
1509 load_const (reg, &upper);
1510
1511 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift);
1512 if (lower.X_add_number != 0)
1513 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg,
1514 lower.X_add_number);
1515 }
1516 else
1517 {
1518 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1519 int hi_reg = 0;
1520
1521 if (upper.X_add_number != 0)
1522 {
1523 /* Discard low part and zero-extend upper immediate. */
1524 upper_imm = ((uint32_t)upper.X_add_number >> shift);
1525
1526 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm);
1527 hi_reg = reg;
1528 }
1529
1530 if (lower.X_add_number != 0 || hi_reg == 0)
1531 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg,
1532 lower.X_add_number);
1533 }
1534}
1535
1536/* Zero extend and sign extend byte/half-word/word. */
1537
1538static void
1539riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
1540{
1541 if (sign)
1542 {
1543 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1544 md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift);
1545 }
1546 else
1547 {
1548 md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift);
1549 md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift);
1550 }
1551}
1552
1553/* Expand RISC-V assembly macros into one or more instructions. */
1554
1555static void
1556macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
1557 bfd_reloc_code_real_type *imm_reloc)
1558{
1559 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD;
1560 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1;
1561 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2;
1562 int mask = ip->insn_mo->mask;
1563
1564 switch (mask)
1565 {
1566 case M_LI:
1567 load_const (rd, imm_expr);
1568 break;
1569
1570 case M_LA:
1571 case M_LLA:
1572 /* Load the address of a symbol into a register. */
1573 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number))
1574 as_bad (_("offset too large"));
1575
1576 if (imm_expr->X_op == O_constant)
1577 load_const (rd, imm_expr);
1578 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol. */
1579 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1580 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1581 else /* Local PIC symbol, or any non-PIC symbol. */
1582 pcrel_load (rd, rd, imm_expr, "addi",
1583 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1584 break;
1585
1586 case M_LA_TLS_GD:
1587 pcrel_load (rd, rd, imm_expr, "addi",
1588 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1589 break;
1590
1591 case M_LA_TLS_IE:
1592 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN,
1593 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1594 break;
1595
1596 case M_LB:
1597 pcrel_load (rd, rd, imm_expr, "lb",
1598 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1599 break;
1600
1601 case M_LBU:
1602 pcrel_load (rd, rd, imm_expr, "lbu",
1603 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1604 break;
1605
1606 case M_LH:
1607 pcrel_load (rd, rd, imm_expr, "lh",
1608 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1609 break;
1610
1611 case M_LHU:
1612 pcrel_load (rd, rd, imm_expr, "lhu",
1613 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1614 break;
1615
1616 case M_LW:
1617 pcrel_load (rd, rd, imm_expr, "lw",
1618 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1619 break;
1620
1621 case M_LWU:
1622 pcrel_load (rd, rd, imm_expr, "lwu",
1623 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1624 break;
1625
1626 case M_LD:
1627 pcrel_load (rd, rd, imm_expr, "ld",
1628 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1629 break;
1630
1631 case M_FLW:
1632 pcrel_load (rd, rs1, imm_expr, "flw",
1633 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1634 break;
1635
1636 case M_FLD:
1637 pcrel_load (rd, rs1, imm_expr, "fld",
1638 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
1639 break;
1640
1641 case M_SB:
1642 pcrel_store (rs2, rs1, imm_expr, "sb",
1643 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1644 break;
1645
1646 case M_SH:
1647 pcrel_store (rs2, rs1, imm_expr, "sh",
1648 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1649 break;
1650
1651 case M_SW:
1652 pcrel_store (rs2, rs1, imm_expr, "sw",
1653 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1654 break;
1655
1656 case M_SD:
1657 pcrel_store (rs2, rs1, imm_expr, "sd",
1658 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1659 break;
1660
1661 case M_FSW:
1662 pcrel_store (rs2, rs1, imm_expr, "fsw",
1663 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1664 break;
1665
1666 case M_FSD:
1667 pcrel_store (rs2, rs1, imm_expr, "fsd",
1668 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
1669 break;
1670
1671 case M_CALL:
1672 riscv_call (rd, rs1, imm_expr, *imm_reloc);
1673 break;
1674
1675 case M_ZEXTH:
1676 riscv_ext (rd, rs1, xlen - 16, false);
1677 break;
1678
1679 case M_ZEXTW:
1680 riscv_ext (rd, rs1, xlen - 32, false);
1681 break;
1682
1683 case M_SEXTB:
1684 riscv_ext (rd, rs1, xlen - 8, true);
1685 break;
1686
1687 case M_SEXTH:
1688 riscv_ext (rd, rs1, xlen - 16, true);
1689 break;
1690
1691 default:
1692 as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
1693 break;
1694 }
1695}
1696
1697static const struct percent_op_match percent_op_utype[] =
1698{
1699 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20},
1700 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20},
1701 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20},
1702 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20},
1703 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20},
1704 {"%hi", BFD_RELOC_RISCV_HI20},
1705 {0, 0}
1706};
1707
1708static const struct percent_op_match percent_op_itype[] =
1709{
1710 {"%lo", BFD_RELOC_RISCV_LO12_I},
1711 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I},
1712 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I},
1713 {0, 0}
1714};
1715
1716static const struct percent_op_match percent_op_stype[] =
1717{
1718 {"%lo", BFD_RELOC_RISCV_LO12_S},
1719 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S},
1720 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S},
1721 {0, 0}
1722};
1723
1724static const struct percent_op_match percent_op_rtype[] =
1725{
1726 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD},
1727 {0, 0}
1728};
1729
1730static const struct percent_op_match percent_op_null[] =
1731{
1732 {0, 0}
1733};
1734
1735/* Return true if *STR points to a relocation operator. When returning true,
1736 move *STR over the operator and store its relocation code in *RELOC.
1737 Leave both *STR and *RELOC alone when returning false. */
1738
1739static bool
1740parse_relocation (char **str, bfd_reloc_code_real_type *reloc,
1741 const struct percent_op_match *percent_op)
1742{
1743 for ( ; percent_op->str; percent_op++)
1744 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0)
1745 {
1746 int len = strlen (percent_op->str);
1747
1748 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
1749 continue;
1750
1751 *str += strlen (percent_op->str);
1752 *reloc = percent_op->reloc;
1753
1754 /* Check whether the output BFD supports this relocation.
1755 If not, issue an error and fall back on something safe. */
1756 if (*reloc != BFD_RELOC_UNUSED
1757 && !bfd_reloc_type_lookup (stdoutput, *reloc))
1758 {
1759 as_bad ("internal: relocation %s isn't supported by the "
1760 "current ABI", percent_op->str);
1761 *reloc = BFD_RELOC_UNUSED;
1762 }
1763 return true;
1764 }
1765 return false;
1766}
1767
1768static void
1769my_getExpression (expressionS *ep, char *str)
1770{
1771 char *save_in;
1772
1773 save_in = input_line_pointer;
1774 input_line_pointer = str;
1775 expression (ep);
1776 expr_end = input_line_pointer;
1777 input_line_pointer = save_in;
1778}
1779
1780/* Parse string STR as a 16-bit relocatable operand. Store the
1781 expression in *EP and the relocation, if any, in RELOC.
1782 Return the number of relocation operators used (0 or 1).
1783
1784 On exit, EXPR_END points to the first character after the expression. */
1785
1786static size_t
1787my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1788 char *str, const struct percent_op_match *percent_op)
1789{
1790 size_t reloc_index;
1791 unsigned crux_depth, str_depth, regno;
1792 char *crux;
1793
1794 /* First, check for integer registers. No callers can accept a reg, but
1795 we need to avoid accidentally creating a useless undefined symbol below,
1796 if this is an instruction pattern that can't match. A glibc build fails
1797 if this is removed. */
1798 if (reg_lookup (&str, RCLASS_GPR, &regno))
1799 {
1800 ep->X_op = O_register;
1801 ep->X_add_number = regno;
1802 expr_end = str;
1803 return 0;
1804 }
1805
1806 /* Search for the start of the main expression.
1807
1808 End the loop with CRUX pointing to the start of the main expression and
1809 with CRUX_DEPTH containing the number of open brackets at that point. */
1810 reloc_index = -1;
1811 str_depth = 0;
1812 do
1813 {
1814 reloc_index++;
1815 crux = str;
1816 crux_depth = str_depth;
1817
1818 /* Skip over whitespace and brackets, keeping count of the number
1819 of brackets. */
1820 while (*str == ' ' || *str == '\t' || *str == '(')
1821 if (*str++ == '(')
1822 str_depth++;
1823 }
1824 while (*str == '%'
1825 && reloc_index < 1
1826 && parse_relocation (&str, reloc, percent_op));
1827
1828 my_getExpression (ep, crux);
1829 str = expr_end;
1830
1831 /* Match every open bracket. */
1832 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t'))
1833 if (*str++ == ')')
1834 crux_depth--;
1835
1836 if (crux_depth > 0)
1837 as_bad ("unclosed '('");
1838
1839 expr_end = str;
1840
1841 return reloc_index;
1842}
1843
1844/* Parse opcode name, could be an mnemonics or number. */
1845
1846static size_t
1847my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
1848 char *str, const struct percent_op_match *percent_op)
1849{
1850 const struct opcode_name_t *o = opcode_name_lookup (&str);
1851
1852 if (o != NULL)
1853 {
1854 ep->X_op = O_constant;
1855 ep->X_add_number = o->val;
1856 return 0;
1857 }
1858
1859 return my_getSmallExpression (ep, reloc, str, percent_op);
1860}
1861
1862/* Detect and handle implicitly zero load-store offsets. For example,
1863 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1864 an implicit offset was detected. */
1865
1866static bool
1867riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
1868{
1869 /* Check whether there is only a single bracketed expression left.
1870 If so, it must be the base register and the constant must be zero. */
1871 if (*s == '(' && strchr (s + 1, '(') == 0)
1872 {
1873 ep->X_op = O_constant;
1874 ep->X_add_number = 0;
1875 return true;
1876 }
1877
1878 return false;
1879}
1880
1881/* All RISC-V CSR instructions belong to one of these classes. */
1882enum csr_insn_type
1883{
1884 INSN_NOT_CSR,
1885 INSN_CSRRW,
1886 INSN_CSRRS,
1887 INSN_CSRRC
1888};
1889
1890/* Return which CSR instruction is checking. */
1891
1892static enum csr_insn_type
1893riscv_csr_insn_type (insn_t insn)
1894{
1895 if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
1896 || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
1897 return INSN_CSRRW;
1898 else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
1899 || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
1900 return INSN_CSRRS;
1901 else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
1902 || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
1903 return INSN_CSRRC;
1904 else
1905 return INSN_NOT_CSR;
1906}
1907
1908/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1909 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1910 CSR address is 0x3. */
1911
1912static bool
1913riscv_csr_read_only_check (insn_t insn)
1914{
1915 int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
1916 int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
1917 int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
1918 enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
1919
1920 if (readonly
1921 && (((csr_insn == INSN_CSRRS
1922 || csr_insn == INSN_CSRRC)
1923 && rs1 != 0)
1924 || csr_insn == INSN_CSRRW))
1925 return false;
1926
1927 return true;
1928}
1929
1930/* Return True if it is a privileged instruction. Otherwise, return FALSE.
1931
1932 uret is actually a N-ext instruction. So it is better to regard it as
1933 an user instruction rather than the priv instruction.
1934
1935 hret is used to return from traps in H-mode. H-mode is removed since
1936 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1937 Therefore, hret should be controlled by the hypervisor spec rather than
1938 priv spec in the future.
1939
1940 dret is defined in the debug spec, so it should be checked in the future,
1941 too. */
1942
1943static bool
1944riscv_is_priv_insn (insn_t insn)
1945{
1946 return (((insn ^ MATCH_SRET) & MASK_SRET) == 0
1947 || ((insn ^ MATCH_MRET) & MASK_MRET) == 0
1948 || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0
1949 || ((insn ^ MATCH_WFI) & MASK_WFI) == 0
1950 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1951 check it here to keep the compatible. */
1952 || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
1953}
1954
1955/* This routine assembles an instruction into its binary format. As a
1956 side effect, it sets the global variable imm_reloc to the type of
1957 relocation to do if one of the operands is an address expression. */
1958
1959static const char *
1960riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
1961 bfd_reloc_code_real_type *imm_reloc, htab_t hash)
1962{
1963 char *s;
1964 const char *args;
1965 char c = 0;
1966 struct riscv_opcode *insn;
1967 char *argsStart;
1968 unsigned int regno;
1969 char save_c = 0;
1970 int argnum;
1971 const struct percent_op_match *p;
1972 const char *error = "unrecognized opcode";
1973 /* Indicate we are assembling instruction with CSR. */
1974 bool insn_with_csr = false;
1975
1976 /* Parse the name of the instruction. Terminate the string if whitespace
1977 is found so that str_hash_find only sees the name part of the string. */
1978 for (s = str; *s != '\0'; ++s)
1979 if (ISSPACE (*s))
1980 {
1981 save_c = *s;
1982 *s++ = '\0';
1983 break;
1984 }
1985
1986 insn = (struct riscv_opcode *) str_hash_find (hash, str);
1987
1988 argsStart = s;
1989 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++)
1990 {
1991 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement))
1992 continue;
1993
1994 if (!riscv_multi_subset_supports (insn->insn_class))
1995 continue;
1996
1997 create_insn (ip, insn);
1998 argnum = 1;
1999
2000 imm_expr->X_op = O_absent;
2001 *imm_reloc = BFD_RELOC_UNUSED;
2002 p = percent_op_itype;
2003
2004 for (args = insn->args;; ++args)
2005 {
2006 s += strspn (s, " \t");
2007 switch (*args)
2008 {
2009 case '\0': /* End of args. */
2010 if (insn->pinfo != INSN_MACRO)
2011 {
2012 if (!insn->match_func (insn, ip->insn_opcode))
2013 break;
2014
2015 /* For .insn, insn->match and insn->mask are 0. */
2016 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0)
2017 ? ip->insn_opcode
2018 : insn->match) == 2
2019 && !riscv_opts.rvc)
2020 break;
2021
2022 if (riscv_is_priv_insn (ip->insn_opcode))
2023 explicit_priv_attr = true;
2024
2025 /* Check if we write a read-only CSR by the CSR
2026 instruction. */
2027 if (insn_with_csr
2028 && riscv_opts.csr_check
2029 && !riscv_csr_read_only_check (ip->insn_opcode))
2030 {
2031 /* Restore the character in advance, since we want to
2032 report the detailed warning message here. */
2033 if (save_c)
2034 *(argsStart - 1) = save_c;
2035 as_warn (_("read-only CSR is written `%s'"), str);
2036 insn_with_csr = false;
2037 }
2038 }
2039 if (*s != '\0')
2040 break;
2041 /* Successful assembly. */
2042 error = NULL;
2043 insn_with_csr = false;
2044 goto out;
2045
2046 case 'C': /* RVC */
2047 switch (*++args)
2048 {
2049 case 's': /* RS1 x8-x15. */
2050 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2051 || !(regno >= 8 && regno <= 15))
2052 break;
2053 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2054 continue;
2055 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
2056 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2057 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno)
2058 break;
2059 continue;
2060 case 't': /* RS2 x8-x15. */
2061 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2062 || !(regno >= 8 && regno <= 15))
2063 break;
2064 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2065 continue;
2066 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
2067 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2068 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno)
2069 break;
2070 continue;
2071 case 'U': /* RS1, constrained to equal RD. */
2072 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2073 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno)
2074 break;
2075 continue;
2076 case 'V': /* RS2 */
2077 if (!reg_lookup (&s, RCLASS_GPR, &regno))
2078 break;
2079 INSERT_OPERAND (CRS2, *ip, regno);
2080 continue;
2081 case 'c': /* RS1, constrained to equal sp. */
2082 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2083 || regno != X_SP)
2084 break;
2085 continue;
2086 case 'z': /* RS2, constrained to equal x0. */
2087 if (!reg_lookup (&s, RCLASS_GPR, &regno)
2088 || regno != 0)
2089 break;
2090 continue;
2091 case '>': /* Shift amount, 0 - (XLEN-1). */
2092 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2093 || imm_expr->X_op != O_constant
2094 || (unsigned long) imm_expr->X_add_number >= xlen)
2095 break;
2096 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
2097 rvc_imm_done:
2098 s = expr_end;
2099 imm_expr->X_op = O_absent;
2100 continue;
2101 case '5':
2102 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2103 || imm_expr->X_op != O_constant
2104 || imm_expr->X_add_number < 0
2105 || imm_expr->X_add_number >= 32
2106 || !VALID_CLTYPE_IMM ((valueT) imm_expr->X_add_number))
2107 break;
2108 ip->insn_opcode |= ENCODE_CLTYPE_IMM (imm_expr->X_add_number);
2109 goto rvc_imm_done;
2110 case '6':
2111 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2112 || imm_expr->X_op != O_constant
2113 || imm_expr->X_add_number < 0
2114 || imm_expr->X_add_number >= 64
2115 || !VALID_CSSTYPE_IMM ((valueT) imm_expr->X_add_number))
2116 break;
2117 ip->insn_opcode |= ENCODE_CSSTYPE_IMM (imm_expr->X_add_number);
2118 goto rvc_imm_done;
2119 case '8':
2120 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2121 || imm_expr->X_op != O_constant
2122 || imm_expr->X_add_number < 0
2123 || imm_expr->X_add_number >= 256
2124 || !VALID_CIWTYPE_IMM ((valueT) imm_expr->X_add_number))
2125 break;
2126 ip->insn_opcode |= ENCODE_CIWTYPE_IMM (imm_expr->X_add_number);
2127 goto rvc_imm_done;
2128 case 'j':
2129 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2130 || imm_expr->X_op != O_constant
2131 || imm_expr->X_add_number == 0
2132 || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
2133 break;
2134 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
2135 goto rvc_imm_done;
2136 case 'k':
2137 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2138 continue;
2139 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2140 || imm_expr->X_op != O_constant
2141 || !VALID_CLTYPE_LW_IMM ((valueT) imm_expr->X_add_number))
2142 break;
2143 ip->insn_opcode |= ENCODE_CLTYPE_LW_IMM (imm_expr->X_add_number);
2144 goto rvc_imm_done;
2145 case 'l':
2146 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2147 continue;
2148 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2149 || imm_expr->X_op != O_constant
2150 || !VALID_CLTYPE_LD_IMM ((valueT) imm_expr->X_add_number))
2151 break;
2152 ip->insn_opcode |= ENCODE_CLTYPE_LD_IMM (imm_expr->X_add_number);
2153 goto rvc_imm_done;
2154 case 'm':
2155 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2156 continue;
2157 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2158 || imm_expr->X_op != O_constant
2159 || !VALID_CITYPE_LWSP_IMM ((valueT) imm_expr->X_add_number))
2160 break;
2161 ip->insn_opcode |=
2162 ENCODE_CITYPE_LWSP_IMM (imm_expr->X_add_number);
2163 goto rvc_imm_done;
2164 case 'n':
2165 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2166 continue;
2167 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2168 || imm_expr->X_op != O_constant
2169 || !VALID_CITYPE_LDSP_IMM ((valueT) imm_expr->X_add_number))
2170 break;
2171 ip->insn_opcode |=
2172 ENCODE_CITYPE_LDSP_IMM (imm_expr->X_add_number);
2173 goto rvc_imm_done;
2174 case 'o':
2175 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2176 || imm_expr->X_op != O_constant
2177 /* C.addiw, c.li, and c.andi allow zero immediate.
2178 C.addi allows zero immediate as hint. Otherwise this
2179 is same as 'j'. */
2180 || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
2181 break;
2182 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
2183 goto rvc_imm_done;
2184 case 'K':
2185 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2186 || imm_expr->X_op != O_constant
2187 || imm_expr->X_add_number == 0
2188 || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
2189 break;
2190 ip->insn_opcode |=
2191 ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr->X_add_number);
2192 goto rvc_imm_done;
2193 case 'L':
2194 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2195 || imm_expr->X_op != O_constant
2196 || !VALID_CITYPE_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
2197 break;
2198 ip->insn_opcode |=
2199 ENCODE_CITYPE_ADDI16SP_IMM (imm_expr->X_add_number);
2200 goto rvc_imm_done;
2201 case 'M':
2202 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2203 continue;
2204 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2205 || imm_expr->X_op != O_constant
2206 || !VALID_CSSTYPE_SWSP_IMM ((valueT) imm_expr->X_add_number))
2207 break;
2208 ip->insn_opcode |=
2209 ENCODE_CSSTYPE_SWSP_IMM (imm_expr->X_add_number);
2210 goto rvc_imm_done;
2211 case 'N':
2212 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2213 continue;
2214 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2215 || imm_expr->X_op != O_constant
2216 || !VALID_CSSTYPE_SDSP_IMM ((valueT) imm_expr->X_add_number))
2217 break;
2218 ip->insn_opcode |=
2219 ENCODE_CSSTYPE_SDSP_IMM (imm_expr->X_add_number);
2220 goto rvc_imm_done;
2221 case 'u':
2222 p = percent_op_utype;
2223 if (my_getSmallExpression (imm_expr, imm_reloc, s, p))
2224 break;
2225 rvc_lui:
2226 if (imm_expr->X_op != O_constant
2227 || imm_expr->X_add_number <= 0
2228 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH
2229 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2
2230 && (imm_expr->X_add_number <
2231 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
2232 break;
2233 ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
2234 goto rvc_imm_done;
2235 case 'v':
2236 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2237 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1))
2238 || ((int32_t)imm_expr->X_add_number
2239 != imm_expr->X_add_number))
2240 break;
2241 imm_expr->X_add_number =
2242 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS;
2243 goto rvc_lui;
2244 case 'p':
2245 goto branch;
2246 case 'a':
2247 goto jump;
2248 case 'S': /* Floating-point RS1 x8-x15. */
2249 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2250 || !(regno >= 8 && regno <= 15))
2251 break;
2252 INSERT_OPERAND (CRS1S, *ip, regno % 8);
2253 continue;
2254 case 'D': /* Floating-point RS2 x8-x15. */
2255 if (!reg_lookup (&s, RCLASS_FPR, &regno)
2256 || !(regno >= 8 && regno <= 15))
2257 break;
2258 INSERT_OPERAND (CRS2S, *ip, regno % 8);
2259 continue;
2260 case 'T': /* Floating-point RS2. */
2261 if (!reg_lookup (&s, RCLASS_FPR, &regno))
2262 break;
2263 INSERT_OPERAND (CRS2, *ip, regno);
2264 continue;
2265 case 'F':
2266 switch (*++args)
2267 {
2268 case '6':
2269 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2270 || imm_expr->X_op != O_constant
2271 || imm_expr->X_add_number < 0
2272 || imm_expr->X_add_number >= 64)
2273 {
2274 as_bad (_("bad value for compressed funct6 "
2275 "field, value must be 0...64"));
2276 break;
2277 }
2278 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
2279 imm_expr->X_op = O_absent;
2280 s = expr_end;
2281 continue;
2282
2283 case '4':
2284 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2285 || imm_expr->X_op != O_constant
2286 || imm_expr->X_add_number < 0
2287 || imm_expr->X_add_number >= 16)
2288 {
2289 as_bad (_("bad value for compressed funct4 "
2290 "field, value must be 0...15"));
2291 break;
2292 }
2293 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
2294 imm_expr->X_op = O_absent;
2295 s = expr_end;
2296 continue;
2297
2298 case '3':
2299 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2300 || imm_expr->X_op != O_constant
2301 || imm_expr->X_add_number < 0
2302 || imm_expr->X_add_number >= 8)
2303 {
2304 as_bad (_("bad value for compressed funct3 "
2305 "field, value must be 0...7"));
2306 break;
2307 }
2308 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number);
2309 imm_expr->X_op = O_absent;
2310 s = expr_end;
2311 continue;
2312
2313 case '2':
2314 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2315 || imm_expr->X_op != O_constant
2316 || imm_expr->X_add_number < 0
2317 || imm_expr->X_add_number >= 4)
2318 {
2319 as_bad (_("bad value for compressed funct2 "
2320 "field, value must be 0...3"));
2321 break;
2322 }
2323 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number);
2324 imm_expr->X_op = O_absent;
2325 s = expr_end;
2326 continue;
2327
2328 default:
2329 as_bad (_("internal: unknown compressed funct "
2330 "field specifier `CF%c'"), *args);
2331 }
2332 break;
2333
2334 default:
2335 as_bad (_("internal: unknown compressed field "
2336 "specifier `C%c'"), *args);
2337 }
2338 break;
2339
2340 case ',':
2341 ++argnum;
2342 if (*s++ == *args)
2343 continue;
2344 s--;
2345 break;
2346
2347 case '(':
2348 case ')':
2349 case '[':
2350 case ']':
2351 if (*s++ == *args)
2352 continue;
2353 break;
2354
2355 case '<': /* Shift amount, 0 - 31. */
2356 my_getExpression (imm_expr, s);
2357 check_absolute_expr (ip, imm_expr, false);
2358 if ((unsigned long) imm_expr->X_add_number > 31)
2359 as_bad (_("improper shift amount (%lu)"),
2360 (unsigned long) imm_expr->X_add_number);
2361 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number);
2362 imm_expr->X_op = O_absent;
2363 s = expr_end;
2364 continue;
2365
2366 case '>': /* Shift amount, 0 - (XLEN-1). */
2367 my_getExpression (imm_expr, s);
2368 check_absolute_expr (ip, imm_expr, false);
2369 if ((unsigned long) imm_expr->X_add_number >= xlen)
2370 as_bad (_("improper shift amount (%lu)"),
2371 (unsigned long) imm_expr->X_add_number);
2372 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number);
2373 imm_expr->X_op = O_absent;
2374 s = expr_end;
2375 continue;
2376
2377 case 'Z': /* CSRRxI immediate. */
2378 my_getExpression (imm_expr, s);
2379 check_absolute_expr (ip, imm_expr, false);
2380 if ((unsigned long) imm_expr->X_add_number > 31)
2381 as_bad (_("improper CSRxI immediate (%lu)"),
2382 (unsigned long) imm_expr->X_add_number);
2383 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number);
2384 imm_expr->X_op = O_absent;
2385 s = expr_end;
2386 continue;
2387
2388 case 'E': /* Control register. */
2389 insn_with_csr = true;
2390 explicit_priv_attr = true;
2391 if (reg_lookup (&s, RCLASS_CSR, &regno))
2392 INSERT_OPERAND (CSR, *ip, regno);
2393 else
2394 {
2395 my_getExpression (imm_expr, s);
2396 check_absolute_expr (ip, imm_expr, true);
2397 if ((unsigned long) imm_expr->X_add_number > 0xfff)
2398 as_bad (_("improper CSR address (%lu)"),
2399 (unsigned long) imm_expr->X_add_number);
2400 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number);
2401 imm_expr->X_op = O_absent;
2402 s = expr_end;
2403 }
2404 continue;
2405
2406 case 'm': /* Rounding mode. */
2407 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), &regno))
2408 {
2409 INSERT_OPERAND (RM, *ip, regno);
2410 continue;
2411 }
2412 break;
2413
2414 case 'P':
2415 case 'Q': /* Fence predecessor/successor. */
2416 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ),
2417 &regno))
2418 {
2419 if (*args == 'P')
2420 INSERT_OPERAND (PRED, *ip, regno);
2421 else
2422 INSERT_OPERAND (SUCC, *ip, regno);
2423 continue;
2424 }
2425 break;
2426
2427 case 'd': /* Destination register. */
2428 case 's': /* Source register. */
2429 case 't': /* Target register. */
2430 case 'r': /* RS3 */
2431 if (reg_lookup (&s, RCLASS_GPR, &regno))
2432 {
2433 c = *args;
2434 if (*s == ' ')
2435 ++s;
2436
2437 /* Now that we have assembled one operand, we use the args
2438 string to figure out where it goes in the instruction. */
2439 switch (c)
2440 {
2441 case 's':
2442 INSERT_OPERAND (RS1, *ip, regno);
2443 break;
2444 case 'd':
2445 INSERT_OPERAND (RD, *ip, regno);
2446 break;
2447 case 't':
2448 INSERT_OPERAND (RS2, *ip, regno);
2449 break;
2450 case 'r':
2451 INSERT_OPERAND (RS3, *ip, regno);
2452 break;
2453 }
2454 continue;
2455 }
2456 break;
2457
2458 case 'D': /* Floating point RD. */
2459 case 'S': /* Floating point RS1. */
2460 case 'T': /* Floating point RS2. */
2461 case 'U': /* Floating point RS1 and RS2. */
2462 case 'R': /* Floating point RS3. */
2463 if (reg_lookup (&s, RCLASS_FPR, &regno))
2464 {
2465 c = *args;
2466 if (*s == ' ')
2467 ++s;
2468 switch (c)
2469 {
2470 case 'D':
2471 INSERT_OPERAND (RD, *ip, regno);
2472 break;
2473 case 'S':
2474 INSERT_OPERAND (RS1, *ip, regno);
2475 break;
2476 case 'U':
2477 INSERT_OPERAND (RS1, *ip, regno);
2478 /* Fall through. */
2479 case 'T':
2480 INSERT_OPERAND (RS2, *ip, regno);
2481 break;
2482 case 'R':
2483 INSERT_OPERAND (RS3, *ip, regno);
2484 break;
2485 }
2486 continue;
2487 }
2488 break;
2489
2490 case 'I':
2491 my_getExpression (imm_expr, s);
2492 if (imm_expr->X_op != O_big
2493 && imm_expr->X_op != O_constant)
2494 break;
2495 normalize_constant_expr (imm_expr);
2496 s = expr_end;
2497 continue;
2498
2499 case 'A':
2500 my_getExpression (imm_expr, s);
2501 normalize_constant_expr (imm_expr);
2502 /* The 'A' format specifier must be a symbol. */
2503 if (imm_expr->X_op != O_symbol)
2504 break;
2505 *imm_reloc = BFD_RELOC_32;
2506 s = expr_end;
2507 continue;
2508
2509 case 'B':
2510 my_getExpression (imm_expr, s);
2511 normalize_constant_expr (imm_expr);
2512 /* The 'B' format specifier must be a symbol or a constant. */
2513 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant)
2514 break;
2515 if (imm_expr->X_op == O_symbol)
2516 *imm_reloc = BFD_RELOC_32;
2517 s = expr_end;
2518 continue;
2519
2520 case 'j': /* Sign-extended immediate. */
2521 p = percent_op_itype;
2522 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2523 goto alu_op;
2524 case 'q': /* Store displacement. */
2525 p = percent_op_stype;
2526 *imm_reloc = BFD_RELOC_RISCV_LO12_S;
2527 goto load_store;
2528 case 'o': /* Load displacement. */
2529 p = percent_op_itype;
2530 *imm_reloc = BFD_RELOC_RISCV_LO12_I;
2531 goto load_store;
2532 case '1':
2533 /* This is used for TLS, where the fourth operand is
2534 %tprel_add, to get a relocation applied to an add
2535 instruction, for relaxation to use. */
2536 p = percent_op_rtype;
2537 goto alu_op;
2538 case '0': /* AMO displacement, which must be zero. */
2539 p = percent_op_null;
2540 load_store:
2541 if (riscv_handle_implicit_zero_offset (imm_expr, s))
2542 continue;
2543 alu_op:
2544 /* If this value won't fit into a 16 bit offset, then go
2545 find a macro that will generate the 32 bit offset
2546 code pattern. */
2547 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2548 {
2549 normalize_constant_expr (imm_expr);
2550 if (imm_expr->X_op != O_constant
2551 || (*args == '0' && imm_expr->X_add_number != 0)
2552 || (*args == '1')
2553 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2
2554 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
2555 break;
2556 }
2557 s = expr_end;
2558 continue;
2559
2560 case 'p': /* PC-relative offset. */
2561 branch:
2562 *imm_reloc = BFD_RELOC_12_PCREL;
2563 my_getExpression (imm_expr, s);
2564 s = expr_end;
2565 continue;
2566
2567 case 'u': /* Upper 20 bits. */
2568 p = percent_op_utype;
2569 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p))
2570 {
2571 if (imm_expr->X_op != O_constant)
2572 break;
2573
2574 if (imm_expr->X_add_number < 0
2575 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH)
2576 as_bad (_("lui expression not in range 0..1048575"));
2577
2578 *imm_reloc = BFD_RELOC_RISCV_HI20;
2579 imm_expr->X_add_number <<= RISCV_IMM_BITS;
2580 }
2581 s = expr_end;
2582 continue;
2583
2584 case 'a': /* 20-bit PC-relative offset. */
2585 jump:
2586 my_getExpression (imm_expr, s);
2587 s = expr_end;
2588 *imm_reloc = BFD_RELOC_RISCV_JMP;
2589 continue;
2590
2591 case 'c':
2592 my_getExpression (imm_expr, s);
2593 s = expr_end;
2594 if (strcmp (s, "@plt") == 0)
2595 {
2596 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT;
2597 s += 4;
2598 }
2599 else
2600 *imm_reloc = BFD_RELOC_RISCV_CALL;
2601 continue;
2602
2603 case 'O':
2604 switch (*++args)
2605 {
2606 case '4':
2607 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2608 || imm_expr->X_op != O_constant
2609 || imm_expr->X_add_number < 0
2610 || imm_expr->X_add_number >= 128
2611 || (imm_expr->X_add_number & 0x3) != 3)
2612 {
2613 as_bad (_("bad value for opcode field, "
2614 "value must be 0...127 and "
2615 "lower 2 bits must be 0x3"));
2616 break;
2617 }
2618 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
2619 imm_expr->X_op = O_absent;
2620 s = expr_end;
2621 continue;
2622
2623 case '2':
2624 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
2625 || imm_expr->X_op != O_constant
2626 || imm_expr->X_add_number < 0
2627 || imm_expr->X_add_number >= 3)
2628 {
2629 as_bad (_("bad value for opcode field, "
2630 "value must be 0...2"));
2631 break;
2632 }
2633 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
2634 imm_expr->X_op = O_absent;
2635 s = expr_end;
2636 continue;
2637
2638 default:
2639 as_bad (_("internal: unknown opcode field "
2640 "specifier `O%c'"), *args);
2641 }
2642 break;
2643
2644 case 'F':
2645 switch (*++args)
2646 {
2647 case '7':
2648 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2649 || imm_expr->X_op != O_constant
2650 || imm_expr->X_add_number < 0
2651 || imm_expr->X_add_number >= 128)
2652 {
2653 as_bad (_("bad value for funct7 field, "
2654 "value must be 0...127"));
2655 break;
2656 }
2657 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
2658 imm_expr->X_op = O_absent;
2659 s = expr_end;
2660 continue;
2661
2662 case '3':
2663 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2664 || imm_expr->X_op != O_constant
2665 || imm_expr->X_add_number < 0
2666 || imm_expr->X_add_number >= 8)
2667 {
2668 as_bad (_("bad value for funct3 field, "
2669 "value must be 0...7"));
2670 break;
2671 }
2672 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
2673 imm_expr->X_op = O_absent;
2674 s = expr_end;
2675 continue;
2676
2677 case '2':
2678 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2679 || imm_expr->X_op != O_constant
2680 || imm_expr->X_add_number < 0
2681 || imm_expr->X_add_number >= 4)
2682 {
2683 as_bad (_("bad value for funct2 field, "
2684 "value must be 0...3"));
2685 break;
2686 }
2687 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
2688 imm_expr->X_op = O_absent;
2689 s = expr_end;
2690 continue;
2691
2692 default:
2693 as_bad (_("internal: unknown funct field "
2694 "specifier `F%c'\n"), *args);
2695 }
2696 break;
2697
2698 case 'z':
2699 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
2700 || imm_expr->X_op != O_constant
2701 || imm_expr->X_add_number != 0)
2702 break;
2703 s = expr_end;
2704 imm_expr->X_op = O_absent;
2705 continue;
2706
2707 default:
2708 as_fatal (_("internal: unknown argument type `%c'"), *args);
2709 }
2710 break;
2711 }
2712 s = argsStart;
2713 error = _("illegal operands");
2714 insn_with_csr = false;
2715 }
2716
2717 out:
2718 /* Restore the character we might have clobbered above. */
2719 if (save_c)
2720 *(argsStart - 1) = save_c;
2721
2722 return error;
2723}
2724
2725void
2726md_assemble (char *str)
2727{
2728 struct riscv_cl_insn insn;
2729 expressionS imm_expr;
2730 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
2731
2732 /* The architecture and privileged elf attributes should be set
2733 before assembling. */
2734 if (!start_assemble)
2735 {
2736 start_assemble = true;
2737
2738 riscv_set_abi_by_arch ();
2739 if (!riscv_set_default_priv_spec (NULL))
2740 return;
2741 }
2742
2743 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash);
2744
2745 if (error)
2746 {
2747 as_bad ("%s `%s'", error, str);
2748 return;
2749 }
2750
2751 if (insn.insn_mo->pinfo == INSN_MACRO)
2752 macro (&insn, &imm_expr, &imm_reloc);
2753 else
2754 append_insn (&insn, &imm_expr, imm_reloc);
2755}
2756
2757const char *
2758md_atof (int type, char *litP, int *sizeP)
2759{
2760 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN);
2761}
2762
2763void
2764md_number_to_chars (char *buf, valueT val, int n)
2765{
2766 if (target_big_endian)
2767 number_to_chars_bigendian (buf, val, n);
2768 else
2769 number_to_chars_littleendian (buf, val, n);
2770}
2771
2772const char *md_shortopts = "O::g::G:";
2773
2774enum options
2775{
2776 OPTION_MARCH = OPTION_MD_BASE,
2777 OPTION_PIC,
2778 OPTION_NO_PIC,
2779 OPTION_MABI,
2780 OPTION_RELAX,
2781 OPTION_NO_RELAX,
2782 OPTION_ARCH_ATTR,
2783 OPTION_NO_ARCH_ATTR,
2784 OPTION_CSR_CHECK,
2785 OPTION_NO_CSR_CHECK,
2786 OPTION_MISA_SPEC,
2787 OPTION_MPRIV_SPEC,
2788 OPTION_BIG_ENDIAN,
2789 OPTION_LITTLE_ENDIAN,
2790 OPTION_END_OF_ENUM
2791};
2792
2793struct option md_longopts[] =
2794{
2795 {"march", required_argument, NULL, OPTION_MARCH},
2796 {"fPIC", no_argument, NULL, OPTION_PIC},
2797 {"fpic", no_argument, NULL, OPTION_PIC},
2798 {"fno-pic", no_argument, NULL, OPTION_NO_PIC},
2799 {"mabi", required_argument, NULL, OPTION_MABI},
2800 {"mrelax", no_argument, NULL, OPTION_RELAX},
2801 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
2802 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
2803 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
2804 {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
2805 {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
2806 {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
2807 {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
2808 {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN},
2809 {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN},
2810
2811 {NULL, no_argument, NULL, 0}
2812};
2813size_t md_longopts_size = sizeof (md_longopts);
2814
2815int
2816md_parse_option (int c, const char *arg)
2817{
2818 switch (c)
2819 {
2820 case OPTION_MARCH:
2821 default_arch_with_ext = arg;
2822 break;
2823
2824 case OPTION_NO_PIC:
2825 riscv_opts.pic = false;
2826 break;
2827
2828 case OPTION_PIC:
2829 riscv_opts.pic = true;
2830 break;
2831
2832 case OPTION_MABI:
2833 if (strcmp (arg, "ilp32") == 0)
2834 riscv_set_abi (32, FLOAT_ABI_SOFT, false);
2835 else if (strcmp (arg, "ilp32e") == 0)
2836 riscv_set_abi (32, FLOAT_ABI_SOFT, true);
2837 else if (strcmp (arg, "ilp32f") == 0)
2838 riscv_set_abi (32, FLOAT_ABI_SINGLE, false);
2839 else if (strcmp (arg, "ilp32d") == 0)
2840 riscv_set_abi (32, FLOAT_ABI_DOUBLE, false);
2841 else if (strcmp (arg, "ilp32q") == 0)
2842 riscv_set_abi (32, FLOAT_ABI_QUAD, false);
2843 else if (strcmp (arg, "lp64") == 0)
2844 riscv_set_abi (64, FLOAT_ABI_SOFT, false);
2845 else if (strcmp (arg, "lp64f") == 0)
2846 riscv_set_abi (64, FLOAT_ABI_SINGLE, false);
2847 else if (strcmp (arg, "lp64d") == 0)
2848 riscv_set_abi (64, FLOAT_ABI_DOUBLE, false);
2849 else if (strcmp (arg, "lp64q") == 0)
2850 riscv_set_abi (64, FLOAT_ABI_QUAD, false);
2851 else
2852 return 0;
2853 explicit_mabi = true;
2854 break;
2855
2856 case OPTION_RELAX:
2857 riscv_opts.relax = true;
2858 break;
2859
2860 case OPTION_NO_RELAX:
2861 riscv_opts.relax = false;
2862 break;
2863
2864 case OPTION_ARCH_ATTR:
2865 riscv_opts.arch_attr = true;
2866 break;
2867
2868 case OPTION_NO_ARCH_ATTR:
2869 riscv_opts.arch_attr = false;
2870 break;
2871
2872 case OPTION_CSR_CHECK:
2873 riscv_opts.csr_check = true;
2874 break;
2875
2876 case OPTION_NO_CSR_CHECK:
2877 riscv_opts.csr_check = false;
2878 break;
2879
2880 case OPTION_MISA_SPEC:
2881 return riscv_set_default_isa_spec (arg);
2882
2883 case OPTION_MPRIV_SPEC:
2884 return riscv_set_default_priv_spec (arg);
2885
2886 case OPTION_BIG_ENDIAN:
2887 target_big_endian = 1;
2888 break;
2889
2890 case OPTION_LITTLE_ENDIAN:
2891 target_big_endian = 0;
2892 break;
2893
2894 default:
2895 return 0;
2896 }
2897
2898 return 1;
2899}
2900
2901void
2902riscv_after_parse_args (void)
2903{
2904 /* The --with-arch is optional for now, so we still need to set the xlen
2905 according to the default_arch, which is set by the --target. */
2906 if (xlen == 0)
2907 {
2908 if (strcmp (default_arch, "riscv32") == 0)
2909 xlen = 32;
2910 else if (strcmp (default_arch, "riscv64") == 0)
2911 xlen = 64;
2912 else
2913 as_bad ("unknown default architecture `%s'", default_arch);
2914 }
2915 if (default_arch_with_ext == NULL)
2916 default_arch_with_ext = xlen == 64 ? "rv64g" : "rv32g";
2917
2918 /* Initialize the hash table for extensions with default version. */
2919 ext_version_hash = init_ext_version_hash ();
2920
2921 /* Set default specs. */
2922 if (default_isa_spec == ISA_SPEC_CLASS_NONE)
2923 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC);
2924 if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
2925 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC);
2926
2927 riscv_set_arch (default_arch_with_ext);
2928
2929 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2930 riscv_set_rvc (false);
2931 if (riscv_subset_supports ("c"))
2932 riscv_set_rvc (true);
2933
2934 /* Enable RVE if specified by the -march option. */
2935 riscv_set_rve (false);
2936 if (riscv_subset_supports ("e"))
2937 riscv_set_rve (true);
2938
2939 /* If the CIE to be produced has not been overridden on the command line,
2940 then produce version 3 by default. This allows us to use the full
2941 range of registers in a .cfi_return_column directive. */
2942 if (flag_dwarf_cie_version == -1)
2943 flag_dwarf_cie_version = 3;
2944}
2945
2946long
2947md_pcrel_from (fixS *fixP)
2948{
2949 return fixP->fx_where + fixP->fx_frag->fr_address;
2950}
2951
2952/* Apply a fixup to the object file. */
2953
2954void
2955md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
2956{
2957 unsigned int subtype;
2958 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
2959 bool relaxable = false;
2960 offsetT loc;
2961 segT sub_segment;
2962
2963 /* Remember value for tc_gen_reloc. */
2964 fixP->fx_addnumber = *valP;
2965
2966 switch (fixP->fx_r_type)
2967 {
2968 case BFD_RELOC_RISCV_HI20:
2969 case BFD_RELOC_RISCV_LO12_I:
2970 case BFD_RELOC_RISCV_LO12_S:
2971 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
2972 | bfd_getl32 (buf), buf);
2973 if (fixP->fx_addsy == NULL)
2974 fixP->fx_done = true;
2975 relaxable = true;
2976 break;
2977
2978 case BFD_RELOC_RISCV_GOT_HI20:
2979 case BFD_RELOC_RISCV_ADD8:
2980 case BFD_RELOC_RISCV_ADD16:
2981 case BFD_RELOC_RISCV_ADD32:
2982 case BFD_RELOC_RISCV_ADD64:
2983 case BFD_RELOC_RISCV_SUB6:
2984 case BFD_RELOC_RISCV_SUB8:
2985 case BFD_RELOC_RISCV_SUB16:
2986 case BFD_RELOC_RISCV_SUB32:
2987 case BFD_RELOC_RISCV_SUB64:
2988 case BFD_RELOC_RISCV_RELAX:
2989 break;
2990
2991 case BFD_RELOC_RISCV_TPREL_HI20:
2992 case BFD_RELOC_RISCV_TPREL_LO12_I:
2993 case BFD_RELOC_RISCV_TPREL_LO12_S:
2994 case BFD_RELOC_RISCV_TPREL_ADD:
2995 relaxable = true;
2996 /* Fall through. */
2997
2998 case BFD_RELOC_RISCV_TLS_GOT_HI20:
2999 case BFD_RELOC_RISCV_TLS_GD_HI20:
3000 case BFD_RELOC_RISCV_TLS_DTPREL32:
3001 case BFD_RELOC_RISCV_TLS_DTPREL64:
3002 if (fixP->fx_addsy != NULL)
3003 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3004 else
3005 as_bad_where (fixP->fx_file, fixP->fx_line,
3006 _("TLS relocation against a constant"));
3007 break;
3008
3009 case BFD_RELOC_32:
3010 /* Use pc-relative relocation for FDE initial location.
3011 The symbol address in .eh_frame may be adjusted in
3012 _bfd_elf_discard_section_eh_frame, and the content of
3013 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
3014 Therefore, we cannot insert a relocation whose addend symbol is
3015 in .eh_frame. Othrewise, the value may be adjusted twice. */
3016 if (fixP->fx_addsy && fixP->fx_subsy
3017 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy))
3018 && strcmp (sub_segment->name, ".eh_frame") == 0
3019 && S_GET_VALUE (fixP->fx_subsy)
3020 == fixP->fx_frag->fr_address + fixP->fx_where)
3021 {
3022 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL;
3023 fixP->fx_subsy = NULL;
3024 break;
3025 }
3026 /* Fall through. */
3027 case BFD_RELOC_64:
3028 case BFD_RELOC_16:
3029 case BFD_RELOC_8:
3030 case BFD_RELOC_RISCV_CFA:
3031 if (fixP->fx_addsy && fixP->fx_subsy)
3032 {
3033 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3034 fixP->fx_next->fx_addsy = fixP->fx_subsy;
3035 fixP->fx_next->fx_subsy = NULL;
3036 fixP->fx_next->fx_offset = 0;
3037 fixP->fx_subsy = NULL;
3038
3039 switch (fixP->fx_r_type)
3040 {
3041 case BFD_RELOC_64:
3042 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64;
3043 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64;
3044 break;
3045
3046 case BFD_RELOC_32:
3047 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32;
3048 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
3049 break;
3050
3051 case BFD_RELOC_16:
3052 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16;
3053 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
3054 break;
3055
3056 case BFD_RELOC_8:
3057 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8;
3058 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
3059 break;
3060
3061 case BFD_RELOC_RISCV_CFA:
3062 /* Load the byte to get the subtype. */
3063 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
3064 loc = fixP->fx_frag->fr_fix - (subtype & 7);
3065 switch (subtype)
3066 {
3067 case DW_CFA_advance_loc1:
3068 fixP->fx_where = loc + 1;
3069 fixP->fx_next->fx_where = loc + 1;
3070 fixP->fx_r_type = BFD_RELOC_RISCV_SET8;
3071 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8;
3072 break;
3073
3074 case DW_CFA_advance_loc2:
3075 fixP->fx_size = 2;
3076 fixP->fx_next->fx_size = 2;
3077 fixP->fx_where = loc + 1;
3078 fixP->fx_next->fx_where = loc + 1;
3079 fixP->fx_r_type = BFD_RELOC_RISCV_SET16;
3080 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16;
3081 break;
3082
3083 case DW_CFA_advance_loc4:
3084 fixP->fx_size = 4;
3085 fixP->fx_next->fx_size = 4;
3086 fixP->fx_where = loc;
3087 fixP->fx_next->fx_where = loc;
3088 fixP->fx_r_type = BFD_RELOC_RISCV_SET32;
3089 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32;
3090 break;
3091
3092 default:
3093 if (subtype < 0x80 && (subtype & 0x40))
3094 {
3095 /* DW_CFA_advance_loc */
3096 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode;
3097 fixP->fx_next->fx_frag = fixP->fx_frag;
3098 fixP->fx_r_type = BFD_RELOC_RISCV_SET6;
3099 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6;
3100 }
3101 else
3102 as_fatal (_("internal: bad CFA value #%d"), subtype);
3103 break;
3104 }
3105 break;
3106
3107 default:
3108 /* This case is unreachable. */
3109 abort ();
3110 }
3111 }
3112 /* Fall through. */
3113
3114 case BFD_RELOC_RVA:
3115 /* If we are deleting this reloc entry, we must fill in the
3116 value now. This can happen if we have a .word which is not
3117 resolved when it appears but is later defined. */
3118 if (fixP->fx_addsy == NULL)
3119 {
3120 gas_assert (fixP->fx_size <= sizeof (valueT));
3121 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
3122 fixP->fx_done = 1;
3123 }
3124 break;
3125
3126 case BFD_RELOC_RISCV_JMP:
3127 if (fixP->fx_addsy)
3128 {
3129 /* Fill in a tentative value to improve objdump readability. */
3130 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3131 bfd_vma delta = target - md_pcrel_from (fixP);
3132 bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf);
3133 }
3134 break;
3135
3136 case BFD_RELOC_12_PCREL:
3137 if (fixP->fx_addsy)
3138 {
3139 /* Fill in a tentative value to improve objdump readability. */
3140 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3141 bfd_vma delta = target - md_pcrel_from (fixP);
3142 bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf);
3143 }
3144 break;
3145
3146 case BFD_RELOC_RISCV_RVC_BRANCH:
3147 if (fixP->fx_addsy)
3148 {
3149 /* Fill in a tentative value to improve objdump readability. */
3150 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3151 bfd_vma delta = target - md_pcrel_from (fixP);
3152 bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf);
3153 }
3154 break;
3155
3156 case BFD_RELOC_RISCV_RVC_JUMP:
3157 if (fixP->fx_addsy)
3158 {
3159 /* Fill in a tentative value to improve objdump readability. */
3160 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
3161 bfd_vma delta = target - md_pcrel_from (fixP);
3162 bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf);
3163 }
3164 break;
3165
3166 case BFD_RELOC_RISCV_CALL:
3167 case BFD_RELOC_RISCV_CALL_PLT:
3168 relaxable = true;
3169 break;
3170
3171 case BFD_RELOC_RISCV_PCREL_HI20:
3172 case BFD_RELOC_RISCV_PCREL_LO12_S:
3173 case BFD_RELOC_RISCV_PCREL_LO12_I:
3174 relaxable = riscv_opts.relax;
3175 break;
3176
3177 case BFD_RELOC_RISCV_ALIGN:
3178 break;
3179
3180 default:
3181 /* We ignore generic BFD relocations we don't know about. */
3182 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL)
3183 as_fatal (_("internal: bad relocation #%d"), fixP->fx_r_type);
3184 }
3185
3186 if (fixP->fx_subsy != NULL)
3187 as_bad_where (fixP->fx_file, fixP->fx_line,
3188 _("unsupported symbol subtraction"));
3189
3190 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3191 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
3192 {
3193 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
3194 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;
3195 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX;
3196 fixP->fx_next->fx_size = 0;
3197 }
3198}
3199
3200/* Because the value of .cfi_remember_state may changed after relaxation,
3201 we insert a fix to relocate it again in link-time. */
3202
3203void
3204riscv_pre_output_hook (void)
3205{
3206 const frchainS *frch;
3207 segT s;
3208
3209 /* Save the current segment info. */
3210 segT seg = now_seg;
3211 subsegT subseg = now_subseg;
3212
3213 for (s = stdoutput->sections; s; s = s->next)
3214 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next)
3215 {
3216 fragS *frag;
3217
3218 for (frag = frch->frch_root; frag; frag = frag->fr_next)
3219 {
3220 if (frag->fr_type == rs_cfa)
3221 {
3222 expressionS exp;
3223 expressionS *symval;
3224
3225 symval = symbol_get_value_expression (frag->fr_symbol);
3226 exp.X_op = O_subtract;
3227 exp.X_add_symbol = symval->X_add_symbol;
3228 exp.X_add_number = 0;
3229 exp.X_op_symbol = symval->X_op_symbol;
3230
3231 /* We must set the segment before creating a frag after all
3232 frag chains have been chained together. */
3233 subseg_set (s, frch->frch_subseg);
3234
3235 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
3236 BFD_RELOC_RISCV_CFA);
3237 }
3238 }
3239 }
3240
3241 /* Restore the original segment info. */
3242 subseg_set (seg, subseg);
3243}
3244
3245/* This structure is used to hold a stack of .option values. */
3246struct riscv_option_stack
3247{
3248 struct riscv_option_stack *next;
3249 struct riscv_set_options options;
3250};
3251
3252static struct riscv_option_stack *riscv_opts_stack;
3253
3254/* Handle the .option pseudo-op. */
3255
3256static void
3257s_riscv_option (int x ATTRIBUTE_UNUSED)
3258{
3259 char *name = input_line_pointer, ch;
3260
3261 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3262 ++input_line_pointer;
3263 ch = *input_line_pointer;
3264 *input_line_pointer = '\0';
3265
3266 if (strcmp (name, "rvc") == 0)
3267 riscv_set_rvc (true);
3268 else if (strcmp (name, "norvc") == 0)
3269 riscv_set_rvc (false);
3270 else if (strcmp (name, "pic") == 0)
3271 riscv_opts.pic = true;
3272 else if (strcmp (name, "nopic") == 0)
3273 riscv_opts.pic = false;
3274 else if (strcmp (name, "relax") == 0)
3275 riscv_opts.relax = true;
3276 else if (strcmp (name, "norelax") == 0)
3277 riscv_opts.relax = false;
3278 else if (strcmp (name, "csr-check") == 0)
3279 riscv_opts.csr_check = true;
3280 else if (strcmp (name, "no-csr-check") == 0)
3281 riscv_opts.csr_check = false;
3282 else if (strcmp (name, "push") == 0)
3283 {
3284 struct riscv_option_stack *s;
3285
3286 s = (struct riscv_option_stack *) xmalloc (sizeof *s);
3287 s->next = riscv_opts_stack;
3288 s->options = riscv_opts;
3289 riscv_opts_stack = s;
3290 }
3291 else if (strcmp (name, "pop") == 0)
3292 {
3293 struct riscv_option_stack *s;
3294
3295 s = riscv_opts_stack;
3296 if (s == NULL)
3297 as_bad (_(".option pop with no .option push"));
3298 else
3299 {
3300 riscv_opts = s->options;
3301 riscv_opts_stack = s->next;
3302 free (s);
3303 }
3304 }
3305 else
3306 {
3307 as_warn (_("unrecognized .option directive: %s\n"), name);
3308 }
3309 *input_line_pointer = ch;
3310 demand_empty_rest_of_line ();
3311}
3312
3313/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3314 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3315 use in DWARF debug information. */
3316
3317static void
3318s_dtprel (int bytes)
3319{
3320 expressionS ex;
3321 char *p;
3322
3323 expression (&ex);
3324
3325 if (ex.X_op != O_symbol)
3326 {
3327 as_bad (_("unsupported use of %s"), (bytes == 8
3328 ? ".dtpreldword"
3329 : ".dtprelword"));
3330 ignore_rest_of_line ();
3331 }
3332
3333 p = frag_more (bytes);
3334 md_number_to_chars (p, 0, bytes);
3335 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false,
3336 (bytes == 8
3337 ? BFD_RELOC_RISCV_TLS_DTPREL64
3338 : BFD_RELOC_RISCV_TLS_DTPREL32));
3339
3340 demand_empty_rest_of_line ();
3341}
3342
3343/* Handle the .bss pseudo-op. */
3344
3345static void
3346s_bss (int ignore ATTRIBUTE_UNUSED)
3347{
3348 subseg_set (bss_section, 0);
3349 demand_empty_rest_of_line ();
3350}
3351
3352static void
3353riscv_make_nops (char *buf, bfd_vma bytes)
3354{
3355 bfd_vma i = 0;
3356
3357 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3358 means we are not within a valid instruction sequence. It is thus safe
3359 to use a zero byte, even though that is not a valid instruction. */
3360 if (bytes % 2 == 1)
3361 buf[i++] = 0;
3362
3363 /* Use at most one 2-byte NOP. */
3364 if ((bytes - i) % 4 == 2)
3365 {
3366 number_to_chars_littleendian (buf + i, RVC_NOP, 2);
3367 i += 2;
3368 }
3369
3370 /* Fill the remainder with 4-byte NOPs. */
3371 for ( ; i < bytes; i += 4)
3372 number_to_chars_littleendian (buf + i, RISCV_NOP, 4);
3373}
3374
3375/* Called from md_do_align. Used to create an alignment frag in a
3376 code section by emitting a worst-case NOP sequence that the linker
3377 will later relax to the correct number of NOPs. We can't compute
3378 the correct alignment now because of other linker relaxations. */
3379
3380bool
3381riscv_frag_align_code (int n)
3382{
3383 bfd_vma bytes = (bfd_vma) 1 << n;
3384 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
3385 bfd_vma worst_case_bytes = bytes - insn_alignment;
3386 char *nops;
3387 expressionS ex;
3388
3389 /* If we are moving to a smaller alignment than the instruction size, then no
3390 alignment is required. */
3391 if (bytes <= insn_alignment)
3392 return true;
3393
3394 /* When not relaxing, riscv_handle_align handles code alignment. */
3395 if (!riscv_opts.relax)
3396 return false;
3397
3398 nops = frag_more (worst_case_bytes);
3399
3400 ex.X_op = O_constant;
3401 ex.X_add_number = worst_case_bytes;
3402
3403 riscv_make_nops (nops, worst_case_bytes);
3404
3405 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
3406 &ex, false, BFD_RELOC_RISCV_ALIGN);
3407
3408 return true;
3409}
3410
3411/* Implement HANDLE_ALIGN. */
3412
3413void
3414riscv_handle_align (fragS *fragP)
3415{
3416 switch (fragP->fr_type)
3417 {
3418 case rs_align_code:
3419 /* When relaxing, riscv_frag_align_code handles code alignment. */
3420 if (!riscv_opts.relax)
3421 {
3422 bfd_signed_vma bytes = (fragP->fr_next->fr_address
3423 - fragP->fr_address - fragP->fr_fix);
3424 /* We have 4 byte uncompressed nops. */
3425 bfd_signed_vma size = 4;
3426 bfd_signed_vma excess = bytes % size;
3427 char *p = fragP->fr_literal + fragP->fr_fix;
3428
3429 if (bytes <= 0)
3430 break;
3431
3432 /* Insert zeros or compressed nops to get 4 byte alignment. */
3433 if (excess)
3434 {
3435 riscv_make_nops (p, excess);
3436 fragP->fr_fix += excess;
3437 p += excess;
3438 }
3439
3440 /* Insert variable number of 4 byte uncompressed nops. */
3441 riscv_make_nops (p, size);
3442 fragP->fr_var = size;
3443 }
3444 break;
3445
3446 default:
3447 break;
3448 }
3449}
3450
3451int
3452md_estimate_size_before_relax (fragS *fragp, asection *segtype)
3453{
3454 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, false));
3455}
3456
3457/* Translate internal representation of relocation info to BFD target
3458 format. */
3459
3460arelent *
3461tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
3462{
3463 arelent *reloc = (arelent *) xmalloc (sizeof (arelent));
3464
3465 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3466 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3467 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3468 reloc->addend = fixp->fx_addnumber;
3469
3470 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
3471 if (reloc->howto == NULL)
3472 {
3473 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8)
3474 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL)
3475 {
3476 /* We don't have R_RISCV_8/16, but for this special case,
3477 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3478 return reloc;
3479 }
3480
3481 as_bad_where (fixp->fx_file, fixp->fx_line,
3482 _("cannot represent %s relocation in object file"),
3483 bfd_get_reloc_code_name (fixp->fx_r_type));
3484 return NULL;
3485 }
3486
3487 return reloc;
3488}
3489
3490int
3491riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
3492{
3493 if (RELAX_BRANCH_P (fragp->fr_subtype))
3494 {
3495 offsetT old_var = fragp->fr_var;
3496 fragp->fr_var = relaxed_branch_length (fragp, sec, true);
3497 return fragp->fr_var - old_var;
3498 }
3499
3500 return 0;
3501}
3502
3503/* Expand far branches to multi-instruction sequences. */
3504
3505static void
3506md_convert_frag_branch (fragS *fragp)
3507{
3508 bfd_byte *buf;
3509 expressionS exp;
3510 fixS *fixp;
3511 insn_t insn;
3512 int rs1, reloc;
3513
3514 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
3515
3516 exp.X_op = O_symbol;
3517 exp.X_add_symbol = fragp->fr_symbol;
3518 exp.X_add_number = fragp->fr_offset;
3519
3520 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype));
3521
3522 if (RELAX_BRANCH_RVC (fragp->fr_subtype))
3523 {
3524 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3525 {
3526 case 8:
3527 case 4:
3528 /* Expand the RVC branch into a RISC-V one. */
3529 insn = bfd_getl16 (buf);
3530 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S);
3531 if ((insn & MASK_C_J) == MATCH_C_J)
3532 insn = MATCH_JAL;
3533 else if ((insn & MASK_C_JAL) == MATCH_C_JAL)
3534 insn = MATCH_JAL | (X_RA << OP_SH_RD);
3535 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ)
3536 insn = MATCH_BEQ | (rs1 << OP_SH_RS1);
3537 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ)
3538 insn = MATCH_BNE | (rs1 << OP_SH_RS1);
3539 else
3540 abort ();
3541 bfd_putl32 (insn, buf);
3542 break;
3543
3544 case 6:
3545 /* Invert the branch condition. Branch over the jump. */
3546 insn = bfd_getl16 (buf);
3547 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
3548 insn |= ENCODE_CBTYPE_IMM (6);
3549 bfd_putl16 (insn, buf);
3550 buf += 2;
3551 goto jump;
3552
3553 case 2:
3554 /* Just keep the RVC branch. */
3555 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3556 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH;
3557 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3558 2, &exp, false, reloc);
3559 buf += 2;
3560 goto done;
3561
3562 default:
3563 abort ();
3564 }
3565 }
3566
3567 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype))
3568 {
3569 case 8:
3570 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype));
3571
3572 /* Invert the branch condition. Branch over the jump. */
3573 insn = bfd_getl32 (buf);
3574 insn ^= MATCH_BEQ ^ MATCH_BNE;
3575 insn |= ENCODE_BTYPE_IMM (8);
3576 bfd_putl32 (insn, buf);
3577 buf += 4;
3578
3579 jump:
3580 /* Jump to the target. */
3581 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3582 4, &exp, false, BFD_RELOC_RISCV_JMP);
3583 bfd_putl32 (MATCH_JAL, buf);
3584 buf += 4;
3585 break;
3586
3587 case 4:
3588 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype)
3589 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL;
3590 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
3591 4, &exp, false, reloc);
3592 buf += 4;
3593 break;
3594
3595 default:
3596 abort ();
3597 }
3598
3599 done:
3600 fixp->fx_file = fragp->fr_file;
3601 fixp->fx_line = fragp->fr_line;
3602
3603 gas_assert (buf == (bfd_byte *)fragp->fr_literal
3604 + fragp->fr_fix + fragp->fr_var);
3605
3606 fragp->fr_fix += fragp->fr_var;
3607}
3608
3609/* Relax a machine dependent frag. This returns the amount by which
3610 the current size of the frag should change. */
3611
3612void
3613md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
3614 fragS *fragp)
3615{
3616 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype));
3617 md_convert_frag_branch (fragp);
3618}
3619
3620void
3621md_show_usage (FILE *stream)
3622{
3623 fprintf (stream, _("\
3624RISC-V options:\n\
3625 -fpic generate position-independent code\n\
3626 -fno-pic don't generate position-independent code (default)\n\
3627 -march=ISA set the RISC-V architecture\n\
3628 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3629 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3630 -mabi=ABI set the RISC-V ABI\n\
3631 -mrelax enable relax (default)\n\
3632 -mno-relax disable relax\n\
3633 -march-attr generate RISC-V arch attribute\n\
3634 -mno-arch-attr don't generate RISC-V arch attribute\n\
3635"));
3636}
3637
3638/* Standard calling conventions leave the CFA at SP on entry. */
3639
3640void
3641riscv_cfi_frame_initial_instructions (void)
3642{
3643 cfi_add_CFA_def_cfa_register (X_SP);
3644}
3645
3646int
3647tc_riscv_regname_to_dw2regnum (char *regname)
3648{
3649 int reg;
3650
3651 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0)
3652 return reg;
3653
3654 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
3655 return reg + 32;
3656
3657 /* CSRs are numbered 4096 -> 8191. */
3658 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
3659 return reg + 4096;
3660
3661 as_bad (_("unknown register `%s'"), regname);
3662 return -1;
3663}
3664
3665void
3666riscv_elf_final_processing (void)
3667{
3668 riscv_set_abi_by_arch ();
3669 elf_elfheader (stdoutput)->e_flags |= elf_flags;
3670}
3671
3672/* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3673 since these directives break relaxation when used with symbol deltas. */
3674
3675static void
3676s_riscv_leb128 (int sign)
3677{
3678 expressionS exp;
3679 char *save_in = input_line_pointer;
3680
3681 expression (&exp);
3682 if (exp.X_op != O_constant)
3683 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u');
3684 demand_empty_rest_of_line ();
3685
3686 input_line_pointer = save_in;
3687 return s_leb128 (sign);
3688}
3689
3690/* Parse the .insn directive. */
3691
3692static void
3693s_riscv_insn (int x ATTRIBUTE_UNUSED)
3694{
3695 char *str = input_line_pointer;
3696 struct riscv_cl_insn insn;
3697 expressionS imm_expr;
3698 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
3699 char save_c;
3700
3701 while (!is_end_of_line[(unsigned char) *input_line_pointer])
3702 ++input_line_pointer;
3703
3704 save_c = *input_line_pointer;
3705 *input_line_pointer = '\0';
3706
3707 const char *error = riscv_ip (str, &insn, &imm_expr,
3708 &imm_reloc, insn_type_hash);
3709
3710 if (error)
3711 {
3712 as_bad ("%s `%s'", error, str);
3713 }
3714 else
3715 {
3716 gas_assert (insn.insn_mo->pinfo != INSN_MACRO);
3717 append_insn (&insn, &imm_expr, imm_reloc);
3718 }
3719
3720 *input_line_pointer = save_c;
3721 demand_empty_rest_of_line ();
3722}
3723
3724/* Update architecture and privileged elf attributes. If we don't set
3725 them, then try to output the default ones. */
3726
3727static void
3728riscv_write_out_attrs (void)
3729{
3730 const char *arch_str, *priv_str, *p;
3731 /* versions[0]: major version.
3732 versions[1]: minor version.
3733 versions[2]: revision version. */
3734 unsigned versions[3] = {0}, number = 0;
3735 unsigned int i;
3736
3737 /* Re-write architecture elf attribute. */
3738 arch_str = riscv_arch_str (xlen, &riscv_subsets);
3739 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str);
3740 xfree ((void *) arch_str);
3741
3742 /* For the file without any instruction, we don't set the default_priv_spec
3743 according to the privileged elf attributes since the md_assemble isn't
3744 called. */
3745 if (!start_assemble
3746 && !riscv_set_default_priv_spec (NULL))
3747 return;
3748
3749 /* If we already have set privileged elf attributes, then no need to do
3750 anything. Otherwise, don't generate or update them when no CSR and
3751 privileged instructions are used. */
3752 if (!explicit_priv_attr)
3753 return;
3754
3755 RISCV_GET_PRIV_SPEC_NAME (priv_str, default_priv_spec);
3756 p = priv_str;
3757 for (i = 0; *p; ++p)
3758 {
3759 if (*p == '.' && i < 3)
3760 {
3761 versions[i++] = number;
3762 number = 0;
3763 }
3764 else if (ISDIGIT (*p))
3765 number = (number * 10) + (*p - '0');
3766 else
3767 {
3768 as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str);
3769 return;
3770 }
3771 }
3772 versions[i] = number;
3773
3774 /* Re-write privileged elf attributes. */
3775 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]);
3776 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]);
3777 bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]);
3778}
3779
3780/* Add the default contents for the .riscv.attributes section. */
3781
3782static void
3783riscv_set_public_attributes (void)
3784{
3785 if (riscv_opts.arch_attr || explicit_attr)
3786 riscv_write_out_attrs ();
3787}
3788
3789/* Called after all assembly has been done. */
3790
3791void
3792riscv_md_end (void)
3793{
3794 riscv_set_public_attributes ();
3795}
3796
3797/* Given a symbolic attribute NAME, return the proper integer value.
3798 Returns -1 if the attribute is not known. */
3799
3800int
3801riscv_convert_symbolic_attribute (const char *name)
3802{
3803 static const struct
3804 {
3805 const char *name;
3806 const int tag;
3807 }
3808 attribute_table[] =
3809 {
3810 /* When you modify this table you should
3811 also modify the list in doc/c-riscv.texi. */
3812#define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3813 T(arch),
3814 T(priv_spec),
3815 T(priv_spec_minor),
3816 T(priv_spec_revision),
3817 T(unaligned_access),
3818 T(stack_align),
3819#undef T
3820 };
3821
3822 if (name == NULL)
3823 return -1;
3824
3825 unsigned int i;
3826 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
3827 if (strcmp (name, attribute_table[i].name) == 0)
3828 return attribute_table[i].tag;
3829
3830 return -1;
3831}
3832
3833/* Parse a .attribute directive. */
3834
3835static void
3836s_riscv_attribute (int ignored ATTRIBUTE_UNUSED)
3837{
3838 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
3839 unsigned old_xlen;
3840 obj_attribute *attr;
3841
3842 explicit_attr = true;
3843 switch (tag)
3844 {
3845 case Tag_RISCV_arch:
3846 old_xlen = xlen;
3847 attr = elf_known_obj_attributes_proc (stdoutput);
3848 if (!start_assemble)
3849 riscv_set_arch (attr[Tag_RISCV_arch].s);
3850 else
3851 as_fatal (_("architecture elf attributes must set before "
3852 "any instructions"));
3853
3854 if (old_xlen != xlen)
3855 {
3856 /* We must re-init bfd again if xlen is changed. */
3857 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
3858 bfd_find_target (riscv_target_format (), stdoutput);
3859
3860 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
3861 as_warn (_("could not set architecture and machine"));
3862 }
3863 break;
3864
3865 case Tag_RISCV_priv_spec:
3866 case Tag_RISCV_priv_spec_minor:
3867 case Tag_RISCV_priv_spec_revision:
3868 if (start_assemble)
3869 as_fatal (_("privileged elf attributes must set before "
3870 "any instructions"));
3871 break;
3872
3873 default:
3874 break;
3875 }
3876}
3877
3878/* RISC-V pseudo-ops table. */
3879static const pseudo_typeS riscv_pseudo_table[] =
3880{
3881 {"option", s_riscv_option, 0},
3882 {"half", cons, 2},
3883 {"word", cons, 4},
3884 {"dword", cons, 8},
3885 {"dtprelword", s_dtprel, 4},
3886 {"dtpreldword", s_dtprel, 8},
3887 {"bss", s_bss, 0},
3888 {"uleb128", s_riscv_leb128, 0},
3889 {"sleb128", s_riscv_leb128, 1},
3890 {"insn", s_riscv_insn, 0},
3891 {"attribute", s_riscv_attribute, 0},
3892
3893 { NULL, NULL, 0 },
3894};
3895
3896void
3897riscv_pop_insert (void)
3898{
3899 extern void pop_insert (const pseudo_typeS *);
3900
3901 pop_insert (riscv_pseudo_table);
3902}
GDB Binutils - Deliverables
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