| 1 | @c Copyright (C) 2000-2017 Free Software Foundation, Inc. |
| 2 | @c This is part of the GAS manual. |
| 3 | @c For copying conditions, see the file as.texinfo. |
| 4 | |
| 5 | @ifset GENERIC |
| 6 | @page |
| 7 | @node ARC-Dependent |
| 8 | @chapter ARC Dependent Features |
| 9 | @end ifset |
| 10 | |
| 11 | @ifclear GENERIC |
| 12 | @node Machine Dependencies |
| 13 | @chapter ARC Dependent Features |
| 14 | @end ifclear |
| 15 | |
| 16 | @set ARC_CORE_DEFAULT 6 |
| 17 | |
| 18 | @cindex ARC support |
| 19 | @menu |
| 20 | * ARC Options:: Options |
| 21 | * ARC Syntax:: Syntax |
| 22 | * ARC Directives:: ARC Machine Directives |
| 23 | * ARC Modifiers:: ARC Assembler Modifiers |
| 24 | * ARC Symbols:: ARC Pre-defined Symbols |
| 25 | * ARC Opcodes:: Opcodes |
| 26 | @end menu |
| 27 | |
| 28 | @node ARC Options |
| 29 | @section Options |
| 30 | @cindex ARC options |
| 31 | @cindex options for ARC |
| 32 | |
| 33 | The following options control the type of CPU for which code is |
| 34 | assembled, and generic constraints on the code generated: |
| 35 | |
| 36 | @table @code |
| 37 | |
| 38 | @item -mcpu=@var{cpu} |
| 39 | @cindex @code{-mcpu=@var{cpu}} command line option, ARC |
| 40 | Set architecture type and register usage for @var{cpu}. There are |
| 41 | also shortcut alias options available for backward compatibility and |
| 42 | convenience. Supported values for @var{cpu} are |
| 43 | |
| 44 | @table @code |
| 45 | @cindex @code{mA6} command line option, ARC |
| 46 | @cindex @code{marc600} command line option, ARC |
| 47 | @item arc600 |
| 48 | Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}. |
| 49 | |
| 50 | @item arc600_norm |
| 51 | Assemble for ARC 600 with norm instructions. |
| 52 | |
| 53 | @item arc600_mul64 |
| 54 | Assemble for ARC 600 with mul64 instructions. |
| 55 | |
| 56 | @item arc600_mul32x16 |
| 57 | Assemble for ARC 600 with mul32x16 instructions. |
| 58 | |
| 59 | @item arc601 |
| 60 | @cindex @code{mARC601} command line option, ARC |
| 61 | Assemble for ARC 601. Alias: @code{-mARC601}. |
| 62 | |
| 63 | @item arc601_norm |
| 64 | Assemble for ARC 601 with norm instructions. |
| 65 | |
| 66 | @item arc601_mul64 |
| 67 | Assemble for ARC 601 with mul64 instructions. |
| 68 | |
| 69 | @item arc601_mul32x16 |
| 70 | Assemble for ARC 601 with mul32x16 instructions. |
| 71 | |
| 72 | @item arc700 |
| 73 | @cindex @code{mA7} command line option, ARC |
| 74 | @cindex @code{mARC700} command line option, ARC |
| 75 | Assemble for ARC 700. Aliases: @code{-mA7}, @code{-mARC700}. |
| 76 | |
| 77 | @item arcem |
| 78 | @cindex @code{mEM} command line option, ARC |
| 79 | Assemble for ARC EM. Aliases: @code{-mEM} |
| 80 | |
| 81 | @item em |
| 82 | Assemble for ARC EM, identical as arcem variant. |
| 83 | |
| 84 | @item em4 |
| 85 | Assemble for ARC EM with code-density instructions. |
| 86 | |
| 87 | @item em4_dmips |
| 88 | Assemble for ARC EM with code-density instructions. |
| 89 | |
| 90 | @item em4_fpus |
| 91 | Assemble for ARC EM with code-density instructions. |
| 92 | |
| 93 | @item em4_fpuda |
| 94 | Assemble for ARC EM with code-density, and double-precision assist |
| 95 | instructions. |
| 96 | |
| 97 | @item quarkse_em |
| 98 | Assemble for QuarkSE-EM cpu. |
| 99 | |
| 100 | @item archs |
| 101 | @cindex @code{mHS} command line option, ARC |
| 102 | Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}. |
| 103 | |
| 104 | @item hs |
| 105 | Assemble for ARC HS. |
| 106 | |
| 107 | @item hs34 |
| 108 | Assemble for ARC HS34. |
| 109 | |
| 110 | @item hs38 |
| 111 | Assemble for ARC HS38. |
| 112 | |
| 113 | @item hs38_linux |
| 114 | Assemble for ARC HS38 with floating point support on. |
| 115 | |
| 116 | @item nps400 |
| 117 | @cindex @code{mnps400} command line option, ARC |
| 118 | Assemble for ARC 700 with NPS-400 extended instructions. |
| 119 | |
| 120 | @end table |
| 121 | |
| 122 | Note: the @code{.cpu} directive (@pxref{ARC Directives}) can |
| 123 | to be used to select a core variant from within assembly code. |
| 124 | |
| 125 | @cindex @code{-EB} command line option, ARC |
| 126 | @item -EB |
| 127 | This option specifies that the output generated by the assembler should |
| 128 | be marked as being encoded for a big-endian processor. |
| 129 | |
| 130 | @cindex @code{-EL} command line option, ARC |
| 131 | @item -EL |
| 132 | This option specifies that the output generated by the assembler should |
| 133 | be marked as being encoded for a little-endian processor - this is the |
| 134 | default. |
| 135 | |
| 136 | @cindex @code{-mcode-density} command line option, ARC |
| 137 | @item -mcode-density |
| 138 | This option turns on Code Density instructions. Only valid for ARC EM |
| 139 | processors. |
| 140 | |
| 141 | @cindex @code{-mrelax} command line option, ARC |
| 142 | @item -mrelax |
| 143 | Enable support for assembly-time relaxation. The assembler will |
| 144 | replace a longer version of an instruction with a shorter one, |
| 145 | whenever it is possible. |
| 146 | |
| 147 | @cindex @code{-mnps400} command line option, ARC |
| 148 | @item -mnps400 |
| 149 | Enable support for NPS-400 extended instructions. |
| 150 | |
| 151 | @cindex @code{-mspfp} command line option, ARC |
| 152 | @item -mspfp |
| 153 | Enable support for single-precision floating point instructions. |
| 154 | |
| 155 | @cindex @code{-mdpfp} command line option, ARC |
| 156 | @item -mdpfp |
| 157 | Enable support for double-precision floating point instructions. |
| 158 | |
| 159 | @cindex @code{-mfpuda} command line option, ARC |
| 160 | @item -mfpuda |
| 161 | Enable support for double-precision assist floating point instructions. |
| 162 | Only valid for ARC EM processors. |
| 163 | |
| 164 | @end table |
| 165 | |
| 166 | @node ARC Syntax |
| 167 | @section Syntax |
| 168 | @menu |
| 169 | * ARC-Chars:: Special Characters |
| 170 | * ARC-Regs:: Register Names |
| 171 | @end menu |
| 172 | |
| 173 | @node ARC-Chars |
| 174 | @subsection Special Characters |
| 175 | |
| 176 | @table @code |
| 177 | @item % |
| 178 | @cindex register name prefix character, ARC |
| 179 | @cindex ARC register name prefix character |
| 180 | A register name can optionally be prefixed by a @samp{%} character. So |
| 181 | register @code{%r0} is equivalent to @code{r0} in the assembly code. |
| 182 | |
| 183 | @item # |
| 184 | @cindex line comment character, ARC |
| 185 | @cindex ARC line comment character |
| 186 | The presence of a @samp{#} character within a line (but not at the |
| 187 | start of a line) indicates the start of a comment that extends to the |
| 188 | end of the current line. |
| 189 | |
| 190 | @emph{Note:} if a line starts with a @samp{#} character then it can |
| 191 | also be a logical line number directive (@pxref{Comments}) or a |
| 192 | preprocessor control command (@pxref{Preprocessing}). |
| 193 | |
| 194 | @item @@ |
| 195 | @cindex symbol prefix character, ARC |
| 196 | @cindex ARC symbol prefix character |
| 197 | Prefixing an operand with an @samp{@@} specifies that the operand is a |
| 198 | symbol and not a register. This is how the assembler disambiguates |
| 199 | the use of an ARC register name as a symbol. So the instruction |
| 200 | @example |
| 201 | mov r0, @@r0 |
| 202 | @end example |
| 203 | moves the address of symbol @code{r0} into register @code{r0}. |
| 204 | |
| 205 | @item ` |
| 206 | @cindex line separator, ARC |
| 207 | @cindex statement separator, ARC |
| 208 | @cindex ARC line separator |
| 209 | The @samp{`} (backtick) character is used to separate statements on a |
| 210 | single line. |
| 211 | |
| 212 | @cindex line |
| 213 | @item - |
| 214 | @cindex C preprocessor macro separator, ARC |
| 215 | @cindex ARC C preprocessor macro separator |
| 216 | Used as a separator to obtain a sequence of commands from a C |
| 217 | preprocessor macro. |
| 218 | |
| 219 | @end table |
| 220 | |
| 221 | @node ARC-Regs |
| 222 | @subsection Register Names |
| 223 | |
| 224 | @cindex ARC register names |
| 225 | @cindex register names, ARC |
| 226 | The ARC assembler uses the following register names for its core |
| 227 | registers: |
| 228 | |
| 229 | @table @code |
| 230 | @item r0-r31 |
| 231 | @cindex core general registers, ARC |
| 232 | @cindex ARC core general registers |
| 233 | The core general registers. Registers @code{r26} through @code{r31} |
| 234 | have special functions, and are usually referred to by those synonyms. |
| 235 | |
| 236 | @item gp |
| 237 | @cindex global pointer, ARC |
| 238 | @cindex ARC global pointer |
| 239 | The global pointer and a synonym for @code{r26}. |
| 240 | |
| 241 | @item fp |
| 242 | @cindex frame pointer, ARC |
| 243 | @cindex ARC frame pointer |
| 244 | The frame pointer and a synonym for @code{r27}. |
| 245 | |
| 246 | @item sp |
| 247 | @cindex stack pointer, ARC |
| 248 | @cindex ARC stack pointer |
| 249 | The stack pointer and a synonym for @code{r28}. |
| 250 | |
| 251 | @item ilink1 |
| 252 | @cindex level 1 interrupt link register, ARC |
| 253 | @cindex ARC level 1 interrupt link register |
| 254 | For ARC 600 and ARC 700, the level 1 interrupt link register and a |
| 255 | synonym for @code{r29}. Not supported for ARCv2. |
| 256 | |
| 257 | @item ilink |
| 258 | @cindex interrupt link register, ARC |
| 259 | @cindex ARC interrupt link register |
| 260 | For ARCv2, the interrupt link register and a synonym for @code{r29}. |
| 261 | Not supported for ARC 600 and ARC 700. |
| 262 | |
| 263 | @item ilink2 |
| 264 | @cindex level 2 interrupt link register, ARC |
| 265 | @cindex ARC level 2 interrupt link register |
| 266 | For ARC 600 and ARC 700, the level 2 interrupt link register and a |
| 267 | synonym for @code{r30}. Not supported for ARC v2. |
| 268 | |
| 269 | @item blink |
| 270 | @cindex link register, ARC |
| 271 | @cindex ARC link register |
| 272 | The link register and a synonym for @code{r31}. |
| 273 | |
| 274 | @item r32-r59 |
| 275 | @cindex extension core registers, ARC |
| 276 | @cindex ARC extension core registers |
| 277 | The extension core registers. |
| 278 | |
| 279 | @item lp_count |
| 280 | @cindex loop counter, ARC |
| 281 | @cindex ARC loop counter |
| 282 | The loop count register. |
| 283 | |
| 284 | @item pcl |
| 285 | @cindex word aligned program counter, ARC |
| 286 | @cindex ARC word aligned program counter |
| 287 | The word aligned program counter. |
| 288 | |
| 289 | @end table |
| 290 | |
| 291 | In addition the ARC processor has a large number of @emph{auxiliary |
| 292 | registers}. The precise set depends on the extensions being |
| 293 | supported, but the following baseline set are always defined: |
| 294 | |
| 295 | @table @code |
| 296 | @item identity |
| 297 | @cindex Processor Identification register, ARC |
| 298 | @cindex ARC Processor Identification register |
| 299 | Processor Identification register. Auxiliary register address 0x4. |
| 300 | |
| 301 | @item pc |
| 302 | @cindex Program Counter, ARC |
| 303 | @cindex ARC Program Counter |
| 304 | Program Counter. Auxiliary register address 0x6. |
| 305 | |
| 306 | @item status32 |
| 307 | @cindex Status register, ARC |
| 308 | @cindex ARC Status register |
| 309 | Status register. Auxiliary register address 0x0a. |
| 310 | |
| 311 | @item bta |
| 312 | @cindex Branch Target Address, ARC |
| 313 | @cindex ARC Branch Target Address |
| 314 | Branch Target Address. Auxiliary register address 0x412. |
| 315 | |
| 316 | @item ecr |
| 317 | @cindex Exception Cause Register, ARC |
| 318 | @cindex ARC Exception Cause Register |
| 319 | Exception Cause Register. Auxiliary register address 0x403. |
| 320 | |
| 321 | @item int_vector_base |
| 322 | @cindex Interrupt Vector Base address, ARC |
| 323 | @cindex ARC Interrupt Vector Base address |
| 324 | Interrupt Vector Base address. Auxiliary register address 0x25. |
| 325 | |
| 326 | @item status32_p0 |
| 327 | @cindex Stored STATUS32 register on entry to level P0 interrupts, ARC |
| 328 | @cindex ARC Stored STATUS32 register on entry to level P0 interrupts |
| 329 | Stored STATUS32 register on entry to level P0 interrupts. Auxiliary |
| 330 | register address 0xb. |
| 331 | |
| 332 | @item aux_user_sp |
| 333 | @cindex Saved User Stack Pointer, ARC |
| 334 | @cindex ARC Saved User Stack Pointer |
| 335 | Saved User Stack Pointer. Auxiliary register address 0xd. |
| 336 | |
| 337 | @item eret |
| 338 | @cindex Exception Return Address, ARC |
| 339 | @cindex ARC Exception Return Address |
| 340 | Exception Return Address. Auxiliary register address 0x400. |
| 341 | |
| 342 | @item erbta |
| 343 | @cindex BTA saved on exception entry, ARC |
| 344 | @cindex ARC BTA saved on exception entry |
| 345 | BTA saved on exception entry. Auxiliary register address 0x401. |
| 346 | |
| 347 | @item erstatus |
| 348 | @cindex STATUS32 saved on exception, ARC |
| 349 | @cindex ARC STATUS32 saved on exception |
| 350 | STATUS32 saved on exception. Auxiliary register address 0x402. |
| 351 | |
| 352 | @item bcr_ver |
| 353 | @cindex Build Configuration Registers Version, ARC |
| 354 | @cindex ARC Build Configuration Registers Version |
| 355 | Build Configuration Registers Version. Auxiliary register address 0x60. |
| 356 | |
| 357 | @item bta_link_build |
| 358 | @cindex Build configuration for: BTA Registers, ARC |
| 359 | @cindex ARC Build configuration for: BTA Registers |
| 360 | Build configuration for: BTA Registers. Auxiliary register address 0x63. |
| 361 | |
| 362 | @item vecbase_ac_build |
| 363 | @cindex Build configuration for: Interrupts, ARC |
| 364 | @cindex ARC Build configuration for: Interrupts |
| 365 | Build configuration for: Interrupts. Auxiliary register address 0x68. |
| 366 | |
| 367 | @item rf_build |
| 368 | @cindex Build configuration for: Core Registers, ARC |
| 369 | @cindex ARC Build configuration for: Core Registers |
| 370 | Build configuration for: Core Registers. Auxiliary register address 0x6e. |
| 371 | |
| 372 | @item dccm_build |
| 373 | @cindex DCCM RAM Configuration Register, ARC |
| 374 | @cindex ARC DCCM RAM Configuration Register |
| 375 | DCCM RAM Configuration Register. Auxiliary register address 0xc1. |
| 376 | |
| 377 | @end table |
| 378 | |
| 379 | Additional auxiliary register names are defined according to the |
| 380 | processor architecture version and extensions selected by the options. |
| 381 | |
| 382 | @node ARC Directives |
| 383 | @section ARC Machine Directives |
| 384 | |
| 385 | @cindex machine directives, ARC |
| 386 | @cindex ARC machine directives |
| 387 | The ARC version of @code{@value{AS}} supports the following additional |
| 388 | machine directives: |
| 389 | |
| 390 | @table @code |
| 391 | |
| 392 | @cindex @code{lcomm} directive |
| 393 | @item .lcomm @var{symbol}, @var{length}[, @var{alignment}] |
| 394 | Reserve @var{length} (an absolute expression) bytes for a local common |
| 395 | denoted by @var{symbol}. The section and value of @var{symbol} are |
| 396 | those of the new local common. The addresses are allocated in the bss |
| 397 | section, so that at run-time the bytes start off zeroed. Since |
| 398 | @var{symbol} is not declared global, it is normally not visible to |
| 399 | @code{@value{LD}}. The optional third parameter, @var{alignment}, |
| 400 | specifies the desired alignment of the symbol in the bss section, |
| 401 | specified as a byte boundary (for example, an alignment of 16 means |
| 402 | that the least significant 4 bits of the address should be zero). The |
| 403 | alignment must be an absolute expression, and it must be a power of |
| 404 | two. If no alignment is specified, as will set the alignment to the |
| 405 | largest power of two less than or equal to the size of the symbol, up |
| 406 | to a maximum of 16. |
| 407 | |
| 408 | @cindex @code{lcommon} directive, ARC |
| 409 | @item .lcommon @var{symbol}, @var{length}[, @var{alignment}] |
| 410 | The same as @code{lcomm} directive. |
| 411 | |
| 412 | @cindex @code{cpu} directive, ARC |
| 413 | @item .cpu @var{cpu} |
| 414 | The @code{.cpu} directive must be followed by the desired core |
| 415 | version. Permitted values for CPU are: |
| 416 | @table @code |
| 417 | @item ARC600 |
| 418 | Assemble for the ARC600 instruction set. |
| 419 | |
| 420 | @item arc600_norm |
| 421 | Assemble for ARC 600 with norm instructions. |
| 422 | |
| 423 | @item arc600_mul64 |
| 424 | Assemble for ARC 600 with mul64 instructions. |
| 425 | |
| 426 | @item arc600_mul32x16 |
| 427 | Assemble for ARC 600 with mul32x16 instructions. |
| 428 | |
| 429 | @item arc601 |
| 430 | Assemble for ARC 601 instruction set. |
| 431 | |
| 432 | @item arc601_norm |
| 433 | Assemble for ARC 601 with norm instructions. |
| 434 | |
| 435 | @item arc601_mul64 |
| 436 | Assemble for ARC 601 with mul64 instructions. |
| 437 | |
| 438 | @item arc601_mul32x16 |
| 439 | Assemble for ARC 601 with mul32x16 instructions. |
| 440 | |
| 441 | @item ARC700 |
| 442 | Assemble for the ARC700 instruction set. |
| 443 | |
| 444 | @item NPS400 |
| 445 | Assemble for the NPS400 instruction set. |
| 446 | |
| 447 | @item EM |
| 448 | Assemble for the ARC EM instruction set. |
| 449 | |
| 450 | @item arcem |
| 451 | Assemble for ARC EM instruction set |
| 452 | |
| 453 | @item em4 |
| 454 | Assemble for ARC EM with code-density instructions. |
| 455 | |
| 456 | @item em4_dmips |
| 457 | Assemble for ARC EM with code-density instructions. |
| 458 | |
| 459 | @item em4_fpus |
| 460 | Assemble for ARC EM with code-density instructions. |
| 461 | |
| 462 | @item em4_fpuda |
| 463 | Assemble for ARC EM with code-density, and double-precision assist |
| 464 | instructions. |
| 465 | |
| 466 | @item quarkse_em |
| 467 | Assemble for QuarkSE-EM instruction set. |
| 468 | |
| 469 | @item HS |
| 470 | Assemble for the ARC HS instruction set. |
| 471 | |
| 472 | @item archs |
| 473 | Assemble for ARC HS instruction set. |
| 474 | |
| 475 | @item hs |
| 476 | Assemble for ARC HS instruction set. |
| 477 | |
| 478 | @item hs34 |
| 479 | Assemble for ARC HS34 instruction set. |
| 480 | |
| 481 | @item hs38 |
| 482 | Assemble for ARC HS38 instruction set. |
| 483 | |
| 484 | @item hs38_linux |
| 485 | Assemble for ARC HS38 with floating point support on. |
| 486 | |
| 487 | @end table |
| 488 | |
| 489 | Note: the @code{.cpu} directive overrides the command line option |
| 490 | @code{-mcpu=@var{cpu}}; a warning is emitted when the version is not |
| 491 | consistent between the two. |
| 492 | |
| 493 | @item .extAuxRegister @var{name}, @var{addr}, @var{mode} |
| 494 | @cindex @code{extAuxRegister} directive, ARC |
| 495 | Auxiliary registers can be defined in the assembler source code by |
| 496 | using this directive. The first parameter, @var{name}, is the name of the |
| 497 | new auxiliary register. The second parameter, @var{addr}, is |
| 498 | address the of the auxiliary register. The third parameter, |
| 499 | @var{mode}, specifies whether the register is readable and/or writable |
| 500 | and is one of: |
| 501 | @table @code |
| 502 | @item r |
| 503 | Read only; |
| 504 | |
| 505 | @item w |
| 506 | Write only; |
| 507 | |
| 508 | @item r|w |
| 509 | Read and write. |
| 510 | |
| 511 | @end table |
| 512 | |
| 513 | For example: |
| 514 | @example |
| 515 | .extAuxRegister mulhi, 0x12, w |
| 516 | @end example |
| 517 | specifies a write only extension auxiliary register, @var{mulhi} at |
| 518 | address 0x12. |
| 519 | |
| 520 | @item .extCondCode @var{suffix}, @var{val} |
| 521 | @cindex @code{extCondCode} directive, ARC |
| 522 | ARC supports extensible condition codes. This directive defines a new |
| 523 | condition code, to be known by the suffix, @var{suffix} and will |
| 524 | depend on the value, @var{val} in the condition code. |
| 525 | |
| 526 | For example: |
| 527 | @example |
| 528 | .extCondCode is_busy,0x14 |
| 529 | add.is_busy r1,r2,r3 |
| 530 | @end example |
| 531 | will only execute the @code{add} instruction if the condition code |
| 532 | value is 0x14. |
| 533 | |
| 534 | @item .extCoreRegister @var{name}, @var{regnum}, @var{mode}, @var{shortcut} |
| 535 | @cindex @code{extCoreRegister} directive, ARC |
| 536 | Specifies an extension core register named @var{name} as a synonym for |
| 537 | the register numbered @var{regnum}. The register number must be |
| 538 | between 32 and 59. The third argument, @var{mode}, indicates whether |
| 539 | the register is readable and/or writable and is one of: |
| 540 | @table @code |
| 541 | @item r |
| 542 | Read only; |
| 543 | |
| 544 | @item w |
| 545 | Write only; |
| 546 | |
| 547 | @item r|w |
| 548 | Read and write. |
| 549 | |
| 550 | @end table |
| 551 | |
| 552 | The final parameter, @var{shortcut} indicates whether the register has |
| 553 | a short cut in the pipeline. The valid values are: |
| 554 | @table @code |
| 555 | @item can_shortcut |
| 556 | The register has a short cut in the pipeline; |
| 557 | |
| 558 | @item cannot_shortcut |
| 559 | The register does not have a short cut in the pipeline. |
| 560 | @end table |
| 561 | |
| 562 | For example: |
| 563 | @example |
| 564 | .extCoreRegister mlo, 57, r , can_shortcut |
| 565 | @end example |
| 566 | defines a read only extension core register, @code{mlo}, which is |
| 567 | register 57, and can short cut the pipeline. |
| 568 | |
| 569 | @item .extInstruction @var{name}, @var{opcode}, @var{subopcode}, @var{suffixclass}, @var{syntaxclass} |
| 570 | @cindex @code{extInstruction} directive, ARC |
| 571 | ARC allows the user to specify extension instructions. These |
| 572 | extension instructions are not macros; the assembler creates encodings |
| 573 | for use of these instructions according to the specification by the |
| 574 | user. |
| 575 | |
| 576 | The first argument, @var{name}, gives the name of the instruction. |
| 577 | |
| 578 | The second argument, @var{opcode}, is the opcode to be used (bits 31:27 |
| 579 | in the encoding). |
| 580 | |
| 581 | The third argument, @var{subopcode}, is the sub-opcode to be used, but |
| 582 | the correct value also depends on the fifth argument, |
| 583 | @var{syntaxclass} |
| 584 | |
| 585 | The fourth argument, @var{suffixclass}, determines the kinds of |
| 586 | suffixes to be allowed. Valid values are: |
| 587 | @table @code |
| 588 | @item SUFFIX_NONE |
| 589 | No suffixes are permitted; |
| 590 | |
| 591 | @item SUFFIX_COND |
| 592 | Conditional suffixes are permitted; |
| 593 | |
| 594 | @item SUFFIX_FLAG |
| 595 | Flag setting suffixes are permitted. |
| 596 | |
| 597 | @item SUFFIX_COND|SUFFIX_FLAG |
| 598 | Both conditional and flag setting suffices are permitted. |
| 599 | |
| 600 | @end table |
| 601 | |
| 602 | The fifth and final argument, @var{syntaxclass}, determines the syntax |
| 603 | class for the instruction. It can have the following values: |
| 604 | @table @code |
| 605 | @item SYNTAX_2OP |
| 606 | Two Operand Instruction; |
| 607 | |
| 608 | @item SYNTAX_3OP |
| 609 | Three Operand Instruction. |
| 610 | |
| 611 | @item SYNTAX_1OP |
| 612 | One Operand Instruction. |
| 613 | |
| 614 | @item SYNTAX_NOP |
| 615 | No Operand Instruction. |
| 616 | @end table |
| 617 | |
| 618 | The syntax class may be followed by @samp{|} and one of the following |
| 619 | modifiers. |
| 620 | @table @code |
| 621 | |
| 622 | @item OP1_MUST_BE_IMM |
| 623 | Modifies syntax class @code{SYNTAX_3OP}, specifying that the first |
| 624 | operand of a three-operand instruction must be an immediate (i.e., the |
| 625 | result is discarded). This is usually used to set the flags using |
| 626 | specific instructions and not retain results. |
| 627 | |
| 628 | @item OP1_IMM_IMPLIED |
| 629 | Modifies syntax class @code{SYNTAX_20P}, specifying that there is an |
| 630 | implied immediate destination operand which does not appear in the |
| 631 | syntax. |
| 632 | |
| 633 | For example, if the source code contains an instruction like: |
| 634 | @example |
| 635 | inst r1,r2 |
| 636 | @end example |
| 637 | the first argument is an implied immediate (that is, the result is |
| 638 | discarded). This is the same as though the source code were: inst |
| 639 | 0,r1,r2. |
| 640 | |
| 641 | @end table |
| 642 | |
| 643 | For example, defining a 64-bit multiplier with immediate operands: |
| 644 | @example |
| 645 | .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, |
| 646 | SYNTAX_3OP|OP1_MUST_BE_IMM |
| 647 | @end example |
| 648 | which specifies an extension instruction named @code{mp64} with 3 |
| 649 | operands. It sets the flags and can be used with a condition code, |
| 650 | for which the first operand is an immediate, i.e. equivalent to |
| 651 | discarding the result of the operation. |
| 652 | |
| 653 | A two operands instruction variant would be: |
| 654 | @example |
| 655 | .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, |
| 656 | SYNTAX_2OP|OP1_IMM_IMPLIED |
| 657 | @end example |
| 658 | which describes a two operand instruction with an implicit first |
| 659 | immediate operand. The result of this operation would be discarded. |
| 660 | |
| 661 | @cindex @code{.arc_attribute} directive, ARC |
| 662 | @item .arc_attribute @var{tag}, @var{value} |
| 663 | Set the ARC object attribute @var{tag} to @var{value}. |
| 664 | |
| 665 | The @var{tag} is either an attribute number, or one of the following: |
| 666 | @code{Tag_ARC_PCS_config}, @code{Tag_ARC_CPU_base}, |
| 667 | @code{Tag_ARC_CPU_variation}, @code{Tag_ARC_CPU_name}, |
| 668 | @code{Tag_ARC_ABI_rf16}, @code{Tag_ARC_ABI_osver}, @code{Tag_ARC_ABI_sda}, |
| 669 | @code{Tag_ARC_ABI_pic}, @code{Tag_ARC_ABI_tls}, @code{Tag_ARC_ABI_enumsize}, |
| 670 | @code{Tag_ARC_ABI_exceptions}, @code{Tag_ARC_ABI_double_size}, |
| 671 | @code{Tag_ARC_ISA_config}, @code{Tag_ARC_ISA_apex}, |
| 672 | @code{Tag_ARC_ISA_mpy_option} |
| 673 | |
| 674 | The @var{value} is either a @code{number}, @code{"string"}, or |
| 675 | @code{number, "string"} depending on the tag. |
| 676 | |
| 677 | @end table |
| 678 | |
| 679 | @node ARC Modifiers |
| 680 | @section ARC Assembler Modifiers |
| 681 | |
| 682 | The following additional assembler modifiers have been added for |
| 683 | position-independent code. These modifiers are available only with |
| 684 | the ARC 700 and above processors and generate relocation entries, |
| 685 | which are interpreted by the linker as follows: |
| 686 | |
| 687 | @table @code |
| 688 | @item @@pcl(@var{symbol}) |
| 689 | @cindex @@pcl(@var{symbol}), ARC modifier |
| 690 | Relative distance of @var{symbol}'s from the current program counter |
| 691 | location. |
| 692 | |
| 693 | @item @@gotpc(@var{symbol}) |
| 694 | @cindex @@gotpc(@var{symbol}), ARC modifier |
| 695 | Relative distance of @var{symbol}'s Global Offset Table entry from the |
| 696 | current program counter location. |
| 697 | |
| 698 | @item @@gotoff(@var{symbol}) |
| 699 | @cindex @@gotoff(@var{symbol}), ARC modifier |
| 700 | Distance of @var{symbol} from the base of the Global Offset Table. |
| 701 | |
| 702 | @item @@plt(@var{symbol}) |
| 703 | @cindex @@plt(@var{symbol}), ARC modifier |
| 704 | Distance of @var{symbol}'s Procedure Linkage Table entry from the |
| 705 | current program counter. This is valid only with branch and link |
| 706 | instructions and PC-relative calls. |
| 707 | |
| 708 | @item @@sda(@var{symbol}) |
| 709 | @cindex @@sda(@var{symbol}), ARC modifier |
| 710 | Relative distance of @var{symbol} from the base of the Small Data |
| 711 | Pointer. |
| 712 | |
| 713 | @end table |
| 714 | |
| 715 | @node ARC Symbols |
| 716 | @section ARC Pre-defined Symbols |
| 717 | |
| 718 | The following assembler symbols will prove useful when developing |
| 719 | position-independent code. These symbols are available only with the |
| 720 | ARC 700 and above processors. |
| 721 | |
| 722 | @table @code |
| 723 | @item __GLOBAL_OFFSET_TABLE__ |
| 724 | @cindex __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol |
| 725 | Symbol referring to the base of the Global Offset Table. |
| 726 | |
| 727 | @item __DYNAMIC__ |
| 728 | @cindex __DYNAMIC__, ARC pre-defined symbol |
| 729 | An alias for the Global Offset Table |
| 730 | @code{Base__GLOBAL_OFFSET_TABLE__}. It can be used only with |
| 731 | @code{@@gotpc} modifiers. |
| 732 | |
| 733 | @end table |
| 734 | |
| 735 | @node ARC Opcodes |
| 736 | @section Opcodes |
| 737 | |
| 738 | @cindex ARC opcodes |
| 739 | @cindex opcodes for ARC |
| 740 | |
| 741 | For information on the ARC instruction set, see @cite{ARC Programmers |
| 742 | Reference Manual}, available where you download the processor IP library. |