| 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, |
| 2 | @c 2001, 2003, 2004 |
| 3 | @c Free Software Foundation, Inc. |
| 4 | @c This is part of the GAS manual. |
| 5 | @c For copying conditions, see the file as.texinfo. |
| 6 | @ifset GENERIC |
| 7 | @page |
| 8 | @node i386-Dependent |
| 9 | @chapter 80386 Dependent Features |
| 10 | @end ifset |
| 11 | @ifclear GENERIC |
| 12 | @node Machine Dependencies |
| 13 | @chapter 80386 Dependent Features |
| 14 | @end ifclear |
| 15 | |
| 16 | @cindex i386 support |
| 17 | @cindex i80386 support |
| 18 | @cindex x86-64 support |
| 19 | |
| 20 | The i386 version @code{@value{AS}} supports both the original Intel 386 |
| 21 | architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture |
| 22 | extending the Intel architecture to 64-bits. |
| 23 | |
| 24 | @menu |
| 25 | * i386-Options:: Options |
| 26 | * i386-Directives:: X86 specific directives |
| 27 | * i386-Syntax:: AT&T Syntax versus Intel Syntax |
| 28 | * i386-Mnemonics:: Instruction Naming |
| 29 | * i386-Regs:: Register Naming |
| 30 | * i386-Prefixes:: Instruction Prefixes |
| 31 | * i386-Memory:: Memory References |
| 32 | * i386-Jumps:: Handling of Jump Instructions |
| 33 | * i386-Float:: Floating Point |
| 34 | * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations |
| 35 | * i386-16bit:: Writing 16-bit Code |
| 36 | * i386-Arch:: Specifying an x86 CPU architecture |
| 37 | * i386-Bugs:: AT&T Syntax bugs |
| 38 | * i386-Notes:: Notes |
| 39 | @end menu |
| 40 | |
| 41 | @node i386-Options |
| 42 | @section Options |
| 43 | |
| 44 | @cindex options for i386 |
| 45 | @cindex options for x86-64 |
| 46 | @cindex i386 options |
| 47 | @cindex x86-64 options |
| 48 | |
| 49 | The i386 version of @code{@value{AS}} has a few machine |
| 50 | dependent options: |
| 51 | |
| 52 | @table @code |
| 53 | @cindex @samp{--32} option, i386 |
| 54 | @cindex @samp{--32} option, x86-64 |
| 55 | @cindex @samp{--64} option, i386 |
| 56 | @cindex @samp{--64} option, x86-64 |
| 57 | @item --32 | --64 |
| 58 | Select the word size, either 32 bits or 64 bits. Selecting 32-bit |
| 59 | implies Intel i386 architecture, while 64-bit implies AMD x86-64 |
| 60 | architecture. |
| 61 | |
| 62 | These options are only available with the ELF object file format, and |
| 63 | require that the necessary BFD support has been included (on a 32-bit |
| 64 | platform you have to add --enable-64-bit-bfd to configure enable 64-bit |
| 65 | usage and use x86-64 as target platform). |
| 66 | |
| 67 | @item -n |
| 68 | By default, x86 GAS replaces multiple nop instructions used for |
| 69 | alignment within code sections with multi-byte nop instructions such |
| 70 | as leal 0(%esi,1),%esi. This switch disables the optimization. |
| 71 | |
| 72 | @cindex @samp{--divide} option, i386 |
| 73 | @item --divide |
| 74 | On SVR4-derived platforms, the character @samp{/} is treated as a comment |
| 75 | character, which means that it cannot be used in expressions. The |
| 76 | @samp{--divide} option turns @samp{/} into a normal character. This does |
| 77 | not disable @samp{/} at the beginning of a line starting a comment, or |
| 78 | affect using @samp{#} for starting a comment. |
| 79 | |
| 80 | @cindex @samp{-march=} option, i386 |
| 81 | @cindex @samp{-march=} option, x86-64 |
| 82 | @item -march=@var{CPU}[+@var{EXTENSION}@dots{}] |
| 83 | This option specifies the target processor. The assembler will |
| 84 | issue an error message if an attempt is made to assemble an instruction |
| 85 | which will not execute on the target processor. The following |
| 86 | processor names are recognized: |
| 87 | @code{i8086}, |
| 88 | @code{i186}, |
| 89 | @code{i286}, |
| 90 | @code{i386}, |
| 91 | @code{i486}, |
| 92 | @code{i586}, |
| 93 | @code{i686}, |
| 94 | @code{pentium}, |
| 95 | @code{pentiumpro}, |
| 96 | @code{pentiumii}, |
| 97 | @code{pentiumiii}, |
| 98 | @code{pentium4}, |
| 99 | @code{prescott}, |
| 100 | @code{nocona}, |
| 101 | @code{core}, |
| 102 | @code{core2}, |
| 103 | @code{k6}, |
| 104 | @code{k6_2}, |
| 105 | @code{athlon}, |
| 106 | @code{opteron}, |
| 107 | @code{k8}, |
| 108 | @code{amdfam10}, |
| 109 | @code{generic32} and |
| 110 | @code{generic64}. |
| 111 | |
| 112 | In addition to the basic instruction set, the assembler can be told to |
| 113 | accept various extension mnemonics. For example, |
| 114 | @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and |
| 115 | @var{vmx}. The following extensions are currently supported: |
| 116 | @code{mmx}, |
| 117 | @code{sse}, |
| 118 | @code{sse2}, |
| 119 | @code{sse3}, |
| 120 | @code{ssse3}, |
| 121 | @code{sse4.1}, |
| 122 | @code{sse4.2}, |
| 123 | @code{sse4}, |
| 124 | @code{avx}, |
| 125 | @code{vmx}, |
| 126 | @code{smx}, |
| 127 | @code{xsave}, |
| 128 | @code{aes}, |
| 129 | @code{pclmul}, |
| 130 | @code{fma}, |
| 131 | @code{movbe}, |
| 132 | @code{ept}, |
| 133 | @code{rdtscp}, |
| 134 | @code{3dnow}, |
| 135 | @code{3dnowa}, |
| 136 | @code{sse4a}, |
| 137 | @code{sse5}, |
| 138 | @code{svme}, |
| 139 | @code{abm} and |
| 140 | @code{padlock}. |
| 141 | |
| 142 | When the @code{.arch} directive is used with @option{-march}, the |
| 143 | @code{.arch} directive will take precedent. |
| 144 | |
| 145 | @cindex @samp{-mtune=} option, i386 |
| 146 | @cindex @samp{-mtune=} option, x86-64 |
| 147 | @item -mtune=@var{CPU} |
| 148 | This option specifies a processor to optimize for. When used in |
| 149 | conjunction with the @option{-march} option, only instructions |
| 150 | of the processor specified by the @option{-march} option will be |
| 151 | generated. |
| 152 | |
| 153 | Valid @var{CPU} values are identical to the processor list of |
| 154 | @option{-march=@var{CPU}}. |
| 155 | |
| 156 | @cindex @samp{-msse2avx} option, i386 |
| 157 | @cindex @samp{-msse2avx} option, x86-64 |
| 158 | @item -msse2avx |
| 159 | This option specifies that the assembler should encode SSE instructions |
| 160 | with VEX prefix. |
| 161 | |
| 162 | @cindex @samp{-msse-check=} option, i386 |
| 163 | @cindex @samp{-msse-check=} option, x86-64 |
| 164 | @item -msse-check=@var{none} |
| 165 | @item -msse-check=@var{warning} |
| 166 | @item -msse-check=@var{error} |
| 167 | These options control if the assembler should check SSE intructions. |
| 168 | @option{-msse-check=@var{none}} will make the assembler not to check SSE |
| 169 | instructions, which is the default. @option{-msse-check=@var{warning}} |
| 170 | will make the assembler issue a warning for any SSE intruction. |
| 171 | @option{-msse-check=@var{error}} will make the assembler issue an error |
| 172 | for any SSE intruction. |
| 173 | |
| 174 | @cindex @samp{-mmnemonic=} option, i386 |
| 175 | @cindex @samp{-mmnemonic=} option, x86-64 |
| 176 | @item -mmnemonic=@var{att} |
| 177 | @item -mmnemonic=@var{intel} |
| 178 | This option specifies instruction mnemonic for matching instructions. |
| 179 | The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will |
| 180 | take precedent. |
| 181 | |
| 182 | @cindex @samp{-msyntax=} option, i386 |
| 183 | @cindex @samp{-msyntax=} option, x86-64 |
| 184 | @item -msyntax=@var{att} |
| 185 | @item -msyntax=@var{intel} |
| 186 | This option specifies instruction syntax when processing instructions. |
| 187 | The @code{.att_syntax} and @code{.intel_syntax} directives will |
| 188 | take precedent. |
| 189 | |
| 190 | @cindex @samp{-mnaked-reg} option, i386 |
| 191 | @cindex @samp{-mnaked-reg} option, x86-64 |
| 192 | @item -mnaked-reg |
| 193 | This opetion specifies that registers don't require a @samp{%} prefix. |
| 194 | The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. |
| 195 | |
| 196 | @end table |
| 197 | |
| 198 | @node i386-Directives |
| 199 | @section x86 specific Directives |
| 200 | |
| 201 | @cindex machine directives, x86 |
| 202 | @cindex x86 machine directives |
| 203 | @table @code |
| 204 | |
| 205 | @cindex @code{lcomm} directive, COFF |
| 206 | @item .lcomm @var{symbol} , @var{length}[, @var{alignment}] |
| 207 | Reserve @var{length} (an absolute expression) bytes for a local common |
| 208 | denoted by @var{symbol}. The section and value of @var{symbol} are |
| 209 | those of the new local common. The addresses are allocated in the bss |
| 210 | section, so that at run-time the bytes start off zeroed. Since |
| 211 | @var{symbol} is not declared global, it is normally not visible to |
| 212 | @code{@value{LD}}. The optional third parameter, @var{alignment}, |
| 213 | specifies the desired alignment of the symbol in the bss section. |
| 214 | |
| 215 | This directive is only available for COFF based x86 targets. |
| 216 | |
| 217 | @c FIXME: Document other x86 specific directives ? Eg: .code16gcc, |
| 218 | @c .largecomm |
| 219 | |
| 220 | @end table |
| 221 | |
| 222 | @node i386-Syntax |
| 223 | @section AT&T Syntax versus Intel Syntax |
| 224 | |
| 225 | @cindex i386 intel_syntax pseudo op |
| 226 | @cindex intel_syntax pseudo op, i386 |
| 227 | @cindex i386 att_syntax pseudo op |
| 228 | @cindex att_syntax pseudo op, i386 |
| 229 | @cindex i386 syntax compatibility |
| 230 | @cindex syntax compatibility, i386 |
| 231 | @cindex x86-64 intel_syntax pseudo op |
| 232 | @cindex intel_syntax pseudo op, x86-64 |
| 233 | @cindex x86-64 att_syntax pseudo op |
| 234 | @cindex att_syntax pseudo op, x86-64 |
| 235 | @cindex x86-64 syntax compatibility |
| 236 | @cindex syntax compatibility, x86-64 |
| 237 | |
| 238 | @code{@value{AS}} now supports assembly using Intel assembler syntax. |
| 239 | @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches |
| 240 | back to the usual AT&T mode for compatibility with the output of |
| 241 | @code{@value{GCC}}. Either of these directives may have an optional |
| 242 | argument, @code{prefix}, or @code{noprefix} specifying whether registers |
| 243 | require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite |
| 244 | different from Intel syntax. We mention these differences because |
| 245 | almost all 80386 documents use Intel syntax. Notable differences |
| 246 | between the two syntaxes are: |
| 247 | |
| 248 | @cindex immediate operands, i386 |
| 249 | @cindex i386 immediate operands |
| 250 | @cindex register operands, i386 |
| 251 | @cindex i386 register operands |
| 252 | @cindex jump/call operands, i386 |
| 253 | @cindex i386 jump/call operands |
| 254 | @cindex operand delimiters, i386 |
| 255 | |
| 256 | @cindex immediate operands, x86-64 |
| 257 | @cindex x86-64 immediate operands |
| 258 | @cindex register operands, x86-64 |
| 259 | @cindex x86-64 register operands |
| 260 | @cindex jump/call operands, x86-64 |
| 261 | @cindex x86-64 jump/call operands |
| 262 | @cindex operand delimiters, x86-64 |
| 263 | @itemize @bullet |
| 264 | @item |
| 265 | AT&T immediate operands are preceded by @samp{$}; Intel immediate |
| 266 | operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). |
| 267 | AT&T register operands are preceded by @samp{%}; Intel register operands |
| 268 | are undelimited. AT&T absolute (as opposed to PC relative) jump/call |
| 269 | operands are prefixed by @samp{*}; they are undelimited in Intel syntax. |
| 270 | |
| 271 | @cindex i386 source, destination operands |
| 272 | @cindex source, destination operands; i386 |
| 273 | @cindex x86-64 source, destination operands |
| 274 | @cindex source, destination operands; x86-64 |
| 275 | @item |
| 276 | AT&T and Intel syntax use the opposite order for source and destination |
| 277 | operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The |
| 278 | @samp{source, dest} convention is maintained for compatibility with |
| 279 | previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and |
| 280 | instructions with 2 immediate operands, such as the @samp{enter} |
| 281 | instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. |
| 282 | |
| 283 | @cindex mnemonic suffixes, i386 |
| 284 | @cindex sizes operands, i386 |
| 285 | @cindex i386 size suffixes |
| 286 | @cindex mnemonic suffixes, x86-64 |
| 287 | @cindex sizes operands, x86-64 |
| 288 | @cindex x86-64 size suffixes |
| 289 | @item |
| 290 | In AT&T syntax the size of memory operands is determined from the last |
| 291 | character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, |
| 292 | @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long |
| 293 | (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes |
| 294 | this by prefixing memory operands (@emph{not} the instruction mnemonics) with |
| 295 | @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus, |
| 296 | Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T |
| 297 | syntax. |
| 298 | |
| 299 | @cindex return instructions, i386 |
| 300 | @cindex i386 jump, call, return |
| 301 | @cindex return instructions, x86-64 |
| 302 | @cindex x86-64 jump, call, return |
| 303 | @item |
| 304 | Immediate form long jumps and calls are |
| 305 | @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the |
| 306 | Intel syntax is |
| 307 | @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return |
| 308 | instruction |
| 309 | is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is |
| 310 | @samp{ret far @var{stack-adjust}}. |
| 311 | |
| 312 | @cindex sections, i386 |
| 313 | @cindex i386 sections |
| 314 | @cindex sections, x86-64 |
| 315 | @cindex x86-64 sections |
| 316 | @item |
| 317 | The AT&T assembler does not provide support for multiple section |
| 318 | programs. Unix style systems expect all programs to be single sections. |
| 319 | @end itemize |
| 320 | |
| 321 | @node i386-Mnemonics |
| 322 | @section Instruction Naming |
| 323 | |
| 324 | @cindex i386 instruction naming |
| 325 | @cindex instruction naming, i386 |
| 326 | @cindex x86-64 instruction naming |
| 327 | @cindex instruction naming, x86-64 |
| 328 | |
| 329 | Instruction mnemonics are suffixed with one character modifiers which |
| 330 | specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l} |
| 331 | and @samp{q} specify byte, word, long and quadruple word operands. If |
| 332 | no suffix is specified by an instruction then @code{@value{AS}} tries to |
| 333 | fill in the missing suffix based on the destination register operand |
| 334 | (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent |
| 335 | to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to |
| 336 | @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix |
| 337 | assembler which assumes that a missing mnemonic suffix implies long |
| 338 | operand size. (This incompatibility does not affect compiler output |
| 339 | since compilers always explicitly specify the mnemonic suffix.) |
| 340 | |
| 341 | Almost all instructions have the same names in AT&T and Intel format. |
| 342 | There are a few exceptions. The sign extend and zero extend |
| 343 | instructions need two sizes to specify them. They need a size to |
| 344 | sign/zero extend @emph{from} and a size to zero extend @emph{to}. This |
| 345 | is accomplished by using two instruction mnemonic suffixes in AT&T |
| 346 | syntax. Base names for sign extend and zero extend are |
| 347 | @samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} |
| 348 | and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes |
| 349 | are tacked on to this base name, the @emph{from} suffix before the |
| 350 | @emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for |
| 351 | ``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, |
| 352 | thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), |
| 353 | @samp{wl} (from word to long), @samp{bq} (from byte to quadruple word), |
| 354 | @samp{wq} (from word to quadruple word), and @samp{lq} (from long to |
| 355 | quadruple word). |
| 356 | |
| 357 | @cindex encoding options, i386 |
| 358 | @cindex encoding options, x86-64 |
| 359 | |
| 360 | Different encoding options can be specified via optional mnemonic |
| 361 | suffix. @samp{.s} suffix swaps 2 register operands in encoding when |
| 362 | moving from one register to another. |
| 363 | |
| 364 | @cindex conversion instructions, i386 |
| 365 | @cindex i386 conversion instructions |
| 366 | @cindex conversion instructions, x86-64 |
| 367 | @cindex x86-64 conversion instructions |
| 368 | The Intel-syntax conversion instructions |
| 369 | |
| 370 | @itemize @bullet |
| 371 | @item |
| 372 | @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, |
| 373 | |
| 374 | @item |
| 375 | @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, |
| 376 | |
| 377 | @item |
| 378 | @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, |
| 379 | |
| 380 | @item |
| 381 | @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, |
| 382 | |
| 383 | @item |
| 384 | @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax} |
| 385 | (x86-64 only), |
| 386 | |
| 387 | @item |
| 388 | @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in |
| 389 | @samp{%rdx:%rax} (x86-64 only), |
| 390 | @end itemize |
| 391 | |
| 392 | @noindent |
| 393 | are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and |
| 394 | @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these |
| 395 | instructions. |
| 396 | |
| 397 | @cindex jump instructions, i386 |
| 398 | @cindex call instructions, i386 |
| 399 | @cindex jump instructions, x86-64 |
| 400 | @cindex call instructions, x86-64 |
| 401 | Far call/jump instructions are @samp{lcall} and @samp{ljmp} in |
| 402 | AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel |
| 403 | convention. |
| 404 | |
| 405 | @section AT&T Mnemonic versus Intel Mnemonic |
| 406 | |
| 407 | @cindex i386 mnemonic compatibility |
| 408 | @cindex mnemonic compatibility, i386 |
| 409 | |
| 410 | @code{@value{AS}} supports assembly using Intel mnemonic. |
| 411 | @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and |
| 412 | @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T |
| 413 | syntax for compatibility with the output of @code{@value{GCC}}. |
| 414 | Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, |
| 415 | @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, |
| 416 | @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 |
| 417 | assembler with different mnemonics from those in Intel IA32 specification. |
| 418 | @code{@value{GCC}} generates those instructions with AT&T mnemonic. |
| 419 | |
| 420 | @node i386-Regs |
| 421 | @section Register Naming |
| 422 | |
| 423 | @cindex i386 registers |
| 424 | @cindex registers, i386 |
| 425 | @cindex x86-64 registers |
| 426 | @cindex registers, x86-64 |
| 427 | Register operands are always prefixed with @samp{%}. The 80386 registers |
| 428 | consist of |
| 429 | |
| 430 | @itemize @bullet |
| 431 | @item |
| 432 | the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, |
| 433 | @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the |
| 434 | frame pointer), and @samp{%esp} (the stack pointer). |
| 435 | |
| 436 | @item |
| 437 | the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, |
| 438 | @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. |
| 439 | |
| 440 | @item |
| 441 | the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, |
| 442 | @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These |
| 443 | are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, |
| 444 | @samp{%cx}, and @samp{%dx}) |
| 445 | |
| 446 | @item |
| 447 | the 6 section registers @samp{%cs} (code section), @samp{%ds} |
| 448 | (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, |
| 449 | and @samp{%gs}. |
| 450 | |
| 451 | @item |
| 452 | the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and |
| 453 | @samp{%cr3}. |
| 454 | |
| 455 | @item |
| 456 | the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, |
| 457 | @samp{%db3}, @samp{%db6}, and @samp{%db7}. |
| 458 | |
| 459 | @item |
| 460 | the 2 test registers @samp{%tr6} and @samp{%tr7}. |
| 461 | |
| 462 | @item |
| 463 | the 8 floating point register stack @samp{%st} or equivalently |
| 464 | @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, |
| 465 | @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. |
| 466 | These registers are overloaded by 8 MMX registers @samp{%mm0}, |
| 467 | @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5}, |
| 468 | @samp{%mm6} and @samp{%mm7}. |
| 469 | |
| 470 | @item |
| 471 | the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, |
| 472 | @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. |
| 473 | @end itemize |
| 474 | |
| 475 | The AMD x86-64 architecture extends the register set by: |
| 476 | |
| 477 | @itemize @bullet |
| 478 | @item |
| 479 | enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the |
| 480 | accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi}, |
| 481 | @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack |
| 482 | pointer) |
| 483 | |
| 484 | @item |
| 485 | the 8 extended registers @samp{%r8}--@samp{%r15}. |
| 486 | |
| 487 | @item |
| 488 | the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d} |
| 489 | |
| 490 | @item |
| 491 | the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w} |
| 492 | |
| 493 | @item |
| 494 | the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b} |
| 495 | |
| 496 | @item |
| 497 | the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. |
| 498 | |
| 499 | @item |
| 500 | the 8 debug registers: @samp{%db8}--@samp{%db15}. |
| 501 | |
| 502 | @item |
| 503 | the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}. |
| 504 | @end itemize |
| 505 | |
| 506 | @node i386-Prefixes |
| 507 | @section Instruction Prefixes |
| 508 | |
| 509 | @cindex i386 instruction prefixes |
| 510 | @cindex instruction prefixes, i386 |
| 511 | @cindex prefixes, i386 |
| 512 | Instruction prefixes are used to modify the following instruction. They |
| 513 | are used to repeat string instructions, to provide section overrides, to |
| 514 | perform bus lock operations, and to change operand and address sizes. |
| 515 | (Most instructions that normally operate on 32-bit operands will use |
| 516 | 16-bit operands if the instruction has an ``operand size'' prefix.) |
| 517 | Instruction prefixes are best written on the same line as the instruction |
| 518 | they act upon. For example, the @samp{scas} (scan string) instruction is |
| 519 | repeated with: |
| 520 | |
| 521 | @smallexample |
| 522 | repne scas %es:(%edi),%al |
| 523 | @end smallexample |
| 524 | |
| 525 | You may also place prefixes on the lines immediately preceding the |
| 526 | instruction, but this circumvents checks that @code{@value{AS}} does |
| 527 | with prefixes, and will not work with all prefixes. |
| 528 | |
| 529 | Here is a list of instruction prefixes: |
| 530 | |
| 531 | @cindex section override prefixes, i386 |
| 532 | @itemize @bullet |
| 533 | @item |
| 534 | Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, |
| 535 | @samp{fs}, @samp{gs}. These are automatically added by specifying |
| 536 | using the @var{section}:@var{memory-operand} form for memory references. |
| 537 | |
| 538 | @cindex size prefixes, i386 |
| 539 | @item |
| 540 | Operand/Address size prefixes @samp{data16} and @samp{addr16} |
| 541 | change 32-bit operands/addresses into 16-bit operands/addresses, |
| 542 | while @samp{data32} and @samp{addr32} change 16-bit ones (in a |
| 543 | @code{.code16} section) into 32-bit operands/addresses. These prefixes |
| 544 | @emph{must} appear on the same line of code as the instruction they |
| 545 | modify. For example, in a 16-bit @code{.code16} section, you might |
| 546 | write: |
| 547 | |
| 548 | @smallexample |
| 549 | addr32 jmpl *(%ebx) |
| 550 | @end smallexample |
| 551 | |
| 552 | @cindex bus lock prefixes, i386 |
| 553 | @cindex inhibiting interrupts, i386 |
| 554 | @item |
| 555 | The bus lock prefix @samp{lock} inhibits interrupts during execution of |
| 556 | the instruction it precedes. (This is only valid with certain |
| 557 | instructions; see a 80386 manual for details). |
| 558 | |
| 559 | @cindex coprocessor wait, i386 |
| 560 | @item |
| 561 | The wait for coprocessor prefix @samp{wait} waits for the coprocessor to |
| 562 | complete the current instruction. This should never be needed for the |
| 563 | 80386/80387 combination. |
| 564 | |
| 565 | @cindex repeat prefixes, i386 |
| 566 | @item |
| 567 | The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added |
| 568 | to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} |
| 569 | times if the current address size is 16-bits). |
| 570 | @cindex REX prefixes, i386 |
| 571 | @item |
| 572 | The @samp{rex} family of prefixes is used by x86-64 to encode |
| 573 | extensions to i386 instruction set. The @samp{rex} prefix has four |
| 574 | bits --- an operand size overwrite (@code{64}) used to change operand size |
| 575 | from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the |
| 576 | register set. |
| 577 | |
| 578 | You may write the @samp{rex} prefixes directly. The @samp{rex64xyz} |
| 579 | instruction emits @samp{rex} prefix with all the bits set. By omitting |
| 580 | the @code{64}, @code{x}, @code{y} or @code{z} you may write other |
| 581 | prefixes as well. Normally, there is no need to write the prefixes |
| 582 | explicitly, since gas will automatically generate them based on the |
| 583 | instruction operands. |
| 584 | @end itemize |
| 585 | |
| 586 | @node i386-Memory |
| 587 | @section Memory References |
| 588 | |
| 589 | @cindex i386 memory references |
| 590 | @cindex memory references, i386 |
| 591 | @cindex x86-64 memory references |
| 592 | @cindex memory references, x86-64 |
| 593 | An Intel syntax indirect memory reference of the form |
| 594 | |
| 595 | @smallexample |
| 596 | @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] |
| 597 | @end smallexample |
| 598 | |
| 599 | @noindent |
| 600 | is translated into the AT&T syntax |
| 601 | |
| 602 | @smallexample |
| 603 | @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) |
| 604 | @end smallexample |
| 605 | |
| 606 | @noindent |
| 607 | where @var{base} and @var{index} are the optional 32-bit base and |
| 608 | index registers, @var{disp} is the optional displacement, and |
| 609 | @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} |
| 610 | to calculate the address of the operand. If no @var{scale} is |
| 611 | specified, @var{scale} is taken to be 1. @var{section} specifies the |
| 612 | optional section register for the memory operand, and may override the |
| 613 | default section register (see a 80386 manual for section register |
| 614 | defaults). Note that section overrides in AT&T syntax @emph{must} |
| 615 | be preceded by a @samp{%}. If you specify a section override which |
| 616 | coincides with the default section register, @code{@value{AS}} does @emph{not} |
| 617 | output any section register override prefixes to assemble the given |
| 618 | instruction. Thus, section overrides can be specified to emphasize which |
| 619 | section register is used for a given memory operand. |
| 620 | |
| 621 | Here are some examples of Intel and AT&T style memory references: |
| 622 | |
| 623 | @table @asis |
| 624 | @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} |
| 625 | @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is |
| 626 | missing, and the default section is used (@samp{%ss} for addressing with |
| 627 | @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. |
| 628 | |
| 629 | @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} |
| 630 | @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is |
| 631 | @samp{foo}. All other fields are missing. The section register here |
| 632 | defaults to @samp{%ds}. |
| 633 | |
| 634 | @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} |
| 635 | This uses the value pointed to by @samp{foo} as a memory operand. |
| 636 | Note that @var{base} and @var{index} are both missing, but there is only |
| 637 | @emph{one} @samp{,}. This is a syntactic exception. |
| 638 | |
| 639 | @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} |
| 640 | This selects the contents of the variable @samp{foo} with section |
| 641 | register @var{section} being @samp{%gs}. |
| 642 | @end table |
| 643 | |
| 644 | Absolute (as opposed to PC relative) call and jump operands must be |
| 645 | prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} |
| 646 | always chooses PC relative addressing for jump/call labels. |
| 647 | |
| 648 | Any instruction that has a memory operand, but no register operand, |
| 649 | @emph{must} specify its size (byte, word, long, or quadruple) with an |
| 650 | instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q}, |
| 651 | respectively). |
| 652 | |
| 653 | The x86-64 architecture adds an RIP (instruction pointer relative) |
| 654 | addressing. This addressing mode is specified by using @samp{rip} as a |
| 655 | base register. Only constant offsets are valid. For example: |
| 656 | |
| 657 | @table @asis |
| 658 | @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]} |
| 659 | Points to the address 1234 bytes past the end of the current |
| 660 | instruction. |
| 661 | |
| 662 | @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]} |
| 663 | Points to the @code{symbol} in RIP relative way, this is shorter than |
| 664 | the default absolute addressing. |
| 665 | @end table |
| 666 | |
| 667 | Other addressing modes remain unchanged in x86-64 architecture, except |
| 668 | registers used are 64-bit instead of 32-bit. |
| 669 | |
| 670 | @node i386-Jumps |
| 671 | @section Handling of Jump Instructions |
| 672 | |
| 673 | @cindex jump optimization, i386 |
| 674 | @cindex i386 jump optimization |
| 675 | @cindex jump optimization, x86-64 |
| 676 | @cindex x86-64 jump optimization |
| 677 | Jump instructions are always optimized to use the smallest possible |
| 678 | displacements. This is accomplished by using byte (8-bit) displacement |
| 679 | jumps whenever the target is sufficiently close. If a byte displacement |
| 680 | is insufficient a long displacement is used. We do not support |
| 681 | word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump |
| 682 | instruction with the @samp{data16} instruction prefix), since the 80386 |
| 683 | insists upon masking @samp{%eip} to 16 bits after the word displacement |
| 684 | is added. (See also @pxref{i386-Arch}) |
| 685 | |
| 686 | Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, |
| 687 | @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte |
| 688 | displacements, so that if you use these instructions (@code{@value{GCC}} does |
| 689 | not use them) you may get an error message (and incorrect code). The AT&T |
| 690 | 80386 assembler tries to get around this problem by expanding @samp{jcxz foo} |
| 691 | to |
| 692 | |
| 693 | @smallexample |
| 694 | jcxz cx_zero |
| 695 | jmp cx_nonzero |
| 696 | cx_zero: jmp foo |
| 697 | cx_nonzero: |
| 698 | @end smallexample |
| 699 | |
| 700 | @node i386-Float |
| 701 | @section Floating Point |
| 702 | |
| 703 | @cindex i386 floating point |
| 704 | @cindex floating point, i386 |
| 705 | @cindex x86-64 floating point |
| 706 | @cindex floating point, x86-64 |
| 707 | All 80387 floating point types except packed BCD are supported. |
| 708 | (BCD support may be added without much difficulty). These data |
| 709 | types are 16-, 32-, and 64- bit integers, and single (32-bit), |
| 710 | double (64-bit), and extended (80-bit) precision floating point. |
| 711 | Each supported type has an instruction mnemonic suffix and a constructor |
| 712 | associated with it. Instruction mnemonic suffixes specify the operand's |
| 713 | data type. Constructors build these data types into memory. |
| 714 | |
| 715 | @cindex @code{float} directive, i386 |
| 716 | @cindex @code{single} directive, i386 |
| 717 | @cindex @code{double} directive, i386 |
| 718 | @cindex @code{tfloat} directive, i386 |
| 719 | @cindex @code{float} directive, x86-64 |
| 720 | @cindex @code{single} directive, x86-64 |
| 721 | @cindex @code{double} directive, x86-64 |
| 722 | @cindex @code{tfloat} directive, x86-64 |
| 723 | @itemize @bullet |
| 724 | @item |
| 725 | Floating point constructors are @samp{.float} or @samp{.single}, |
| 726 | @samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. |
| 727 | These correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, |
| 728 | and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 |
| 729 | only supports this format via the @samp{fldt} (load 80-bit real to stack |
| 730 | top) and @samp{fstpt} (store 80-bit real and pop stack) instructions. |
| 731 | |
| 732 | @cindex @code{word} directive, i386 |
| 733 | @cindex @code{long} directive, i386 |
| 734 | @cindex @code{int} directive, i386 |
| 735 | @cindex @code{quad} directive, i386 |
| 736 | @cindex @code{word} directive, x86-64 |
| 737 | @cindex @code{long} directive, x86-64 |
| 738 | @cindex @code{int} directive, x86-64 |
| 739 | @cindex @code{quad} directive, x86-64 |
| 740 | @item |
| 741 | Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and |
| 742 | @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The |
| 743 | corresponding instruction mnemonic suffixes are @samp{s} (single), |
| 744 | @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, |
| 745 | the 64-bit @samp{q} format is only present in the @samp{fildq} (load |
| 746 | quad integer to stack top) and @samp{fistpq} (store quad integer and pop |
| 747 | stack) instructions. |
| 748 | @end itemize |
| 749 | |
| 750 | Register to register operations should not use instruction mnemonic suffixes. |
| 751 | @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you |
| 752 | wrote @samp{fst %st, %st(1)}, since all register to register operations |
| 753 | use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, |
| 754 | which converts @samp{%st} from 80-bit to 64-bit floating point format, |
| 755 | then stores the result in the 4 byte location @samp{mem}) |
| 756 | |
| 757 | @node i386-SIMD |
| 758 | @section Intel's MMX and AMD's 3DNow! SIMD Operations |
| 759 | |
| 760 | @cindex MMX, i386 |
| 761 | @cindex 3DNow!, i386 |
| 762 | @cindex SIMD, i386 |
| 763 | @cindex MMX, x86-64 |
| 764 | @cindex 3DNow!, x86-64 |
| 765 | @cindex SIMD, x86-64 |
| 766 | |
| 767 | @code{@value{AS}} supports Intel's MMX instruction set (SIMD |
| 768 | instructions for integer data), available on Intel's Pentium MMX |
| 769 | processors and Pentium II processors, AMD's K6 and K6-2 processors, |
| 770 | Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: |
| 771 | instruction set (SIMD instructions for 32-bit floating point data) |
| 772 | available on AMD's K6-2 processor and possibly others in the future. |
| 773 | |
| 774 | Currently, @code{@value{AS}} does not support Intel's floating point |
| 775 | SIMD, Katmai (KNI). |
| 776 | |
| 777 | The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, |
| 778 | @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four |
| 779 | 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit |
| 780 | floating point values. The MMX registers cannot be used at the same time |
| 781 | as the floating point stack. |
| 782 | |
| 783 | See Intel and AMD documentation, keeping in mind that the operand order in |
| 784 | instructions is reversed from the Intel syntax. |
| 785 | |
| 786 | @node i386-16bit |
| 787 | @section Writing 16-bit Code |
| 788 | |
| 789 | @cindex i386 16-bit code |
| 790 | @cindex 16-bit code, i386 |
| 791 | @cindex real-mode code, i386 |
| 792 | @cindex @code{code16gcc} directive, i386 |
| 793 | @cindex @code{code16} directive, i386 |
| 794 | @cindex @code{code32} directive, i386 |
| 795 | @cindex @code{code64} directive, i386 |
| 796 | @cindex @code{code64} directive, x86-64 |
| 797 | While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code |
| 798 | or 64-bit x86-64 code depending on the default configuration, |
| 799 | it also supports writing code to run in real mode or in 16-bit protected |
| 800 | mode code segments. To do this, put a @samp{.code16} or |
| 801 | @samp{.code16gcc} directive before the assembly language instructions to |
| 802 | be run in 16-bit mode. You can switch @code{@value{AS}} back to writing |
| 803 | normal 32-bit code with the @samp{.code32} directive. |
| 804 | |
| 805 | @samp{.code16gcc} provides experimental support for generating 16-bit |
| 806 | code from gcc, and differs from @samp{.code16} in that @samp{call}, |
| 807 | @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, |
| 808 | @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions |
| 809 | default to 32-bit size. This is so that the stack pointer is |
| 810 | manipulated in the same way over function calls, allowing access to |
| 811 | function parameters at the same stack offsets as in 32-bit mode. |
| 812 | @samp{.code16gcc} also automatically adds address size prefixes where |
| 813 | necessary to use the 32-bit addressing modes that gcc generates. |
| 814 | |
| 815 | The code which @code{@value{AS}} generates in 16-bit mode will not |
| 816 | necessarily run on a 16-bit pre-80386 processor. To write code that |
| 817 | runs on such a processor, you must refrain from using @emph{any} 32-bit |
| 818 | constructs which require @code{@value{AS}} to output address or operand |
| 819 | size prefixes. |
| 820 | |
| 821 | Note that writing 16-bit code instructions by explicitly specifying a |
| 822 | prefix or an instruction mnemonic suffix within a 32-bit code section |
| 823 | generates different machine instructions than those generated for a |
| 824 | 16-bit code segment. In a 32-bit code section, the following code |
| 825 | generates the machine opcode bytes @samp{66 6a 04}, which pushes the |
| 826 | value @samp{4} onto the stack, decrementing @samp{%esp} by 2. |
| 827 | |
| 828 | @smallexample |
| 829 | pushw $4 |
| 830 | @end smallexample |
| 831 | |
| 832 | The same code in a 16-bit code section would generate the machine |
| 833 | opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which |
| 834 | is correct since the processor default operand size is assumed to be 16 |
| 835 | bits in a 16-bit code section. |
| 836 | |
| 837 | @node i386-Bugs |
| 838 | @section AT&T Syntax bugs |
| 839 | |
| 840 | The UnixWare assembler, and probably other AT&T derived ix86 Unix |
| 841 | assemblers, generate floating point instructions with reversed source |
| 842 | and destination registers in certain cases. Unfortunately, gcc and |
| 843 | possibly many other programs use this reversed syntax, so we're stuck |
| 844 | with it. |
| 845 | |
| 846 | For example |
| 847 | |
| 848 | @smallexample |
| 849 | fsub %st,%st(3) |
| 850 | @end smallexample |
| 851 | @noindent |
| 852 | results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather |
| 853 | than the expected @samp{%st(3) - %st}. This happens with all the |
| 854 | non-commutative arithmetic floating point operations with two register |
| 855 | operands where the source register is @samp{%st} and the destination |
| 856 | register is @samp{%st(i)}. |
| 857 | |
| 858 | @node i386-Arch |
| 859 | @section Specifying CPU Architecture |
| 860 | |
| 861 | @cindex arch directive, i386 |
| 862 | @cindex i386 arch directive |
| 863 | @cindex arch directive, x86-64 |
| 864 | @cindex x86-64 arch directive |
| 865 | |
| 866 | @code{@value{AS}} may be told to assemble for a particular CPU |
| 867 | (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This |
| 868 | directive enables a warning when gas detects an instruction that is not |
| 869 | supported on the CPU specified. The choices for @var{cpu_type} are: |
| 870 | |
| 871 | @multitable @columnfractions .20 .20 .20 .20 |
| 872 | @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} |
| 873 | @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} |
| 874 | @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} |
| 875 | @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} |
| 876 | @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} |
| 877 | @item @samp{amdfam10} |
| 878 | @item @samp{generic32} @tab @samp{generic64} |
| 879 | @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} |
| 880 | @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} |
| 881 | @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave} |
| 882 | @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe} |
| 883 | @item @samp{.ept} @tab @samp{.rdtscp} |
| 884 | @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} |
| 885 | @item @samp{.svme} @tab @samp{.abm} |
| 886 | @item @samp{.padlock} |
| 887 | @end multitable |
| 888 | |
| 889 | Apart from the warning, there are only two other effects on |
| 890 | @code{@value{AS}} operation; Firstly, if you specify a CPU other than |
| 891 | @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax} |
| 892 | will automatically use a two byte opcode sequence. The larger three |
| 893 | byte opcode sequence is used on the 486 (and when no architecture is |
| 894 | specified) because it executes faster on the 486. Note that you can |
| 895 | explicitly request the two byte opcode by writing @samp{sarl %eax}. |
| 896 | Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286}, |
| 897 | @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset |
| 898 | conditional jumps will be promoted when necessary to a two instruction |
| 899 | sequence consisting of a conditional jump of the opposite sense around |
| 900 | an unconditional jump to the target. |
| 901 | |
| 902 | Following the CPU architecture (but not a sub-architecture, which are those |
| 903 | starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to |
| 904 | control automatic promotion of conditional jumps. @samp{jumps} is the |
| 905 | default, and enables jump promotion; All external jumps will be of the long |
| 906 | variety, and file-local jumps will be promoted as necessary. |
| 907 | (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as |
| 908 | byte offset jumps, and warns about file-local conditional jumps that |
| 909 | @code{@value{AS}} promotes. |
| 910 | Unconditional jumps are treated as for @samp{jumps}. |
| 911 | |
| 912 | For example |
| 913 | |
| 914 | @smallexample |
| 915 | .arch i8086,nojumps |
| 916 | @end smallexample |
| 917 | |
| 918 | @node i386-Notes |
| 919 | @section Notes |
| 920 | |
| 921 | @cindex i386 @code{mul}, @code{imul} instructions |
| 922 | @cindex @code{mul} instruction, i386 |
| 923 | @cindex @code{imul} instruction, i386 |
| 924 | @cindex @code{mul} instruction, x86-64 |
| 925 | @cindex @code{imul} instruction, x86-64 |
| 926 | There is some trickery concerning the @samp{mul} and @samp{imul} |
| 927 | instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding |
| 928 | multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 |
| 929 | for @samp{imul}) can be output only in the one operand form. Thus, |
| 930 | @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; |
| 931 | the expanding multiply would clobber the @samp{%edx} register, and this |
| 932 | would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the |
| 933 | 64-bit product in @samp{%edx:%eax}. |
| 934 | |
| 935 | We have added a two operand form of @samp{imul} when the first operand |
| 936 | is an immediate mode expression and the second operand is a register. |
| 937 | This is just a shorthand, so that, multiplying @samp{%eax} by 69, for |
| 938 | example, can be done with @samp{imul $69, %eax} rather than @samp{imul |
| 939 | $69, %eax, %eax}. |
| 940 | |