| 1 | @c Copyright 2000, 2003 Free Software Foundation, Inc. |
| 2 | @c This is part of the GAS manual. |
| 3 | @c For copying conditions, see the file as.texinfo. |
| 4 | @ifset GENERIC |
| 5 | @page |
| 6 | @node i860-Dependent |
| 7 | @chapter Intel i860 Dependent Features |
| 8 | @end ifset |
| 9 | @ifclear GENERIC |
| 10 | @node Machine Dependencies |
| 11 | @chapter Intel i860 Dependent Features |
| 12 | @end ifclear |
| 13 | |
| 14 | @ignore |
| 15 | @c FIXME: This is basically a stub for i860. There is tons more information |
| 16 | that I will add later (jle@cygnus.com). |
| 17 | @end ignore |
| 18 | |
| 19 | @cindex i860 support |
| 20 | @menu |
| 21 | * Notes-i860:: i860 Notes |
| 22 | * Options-i860:: i860 Command-line Options |
| 23 | * Directives-i860:: i860 Machine Directives |
| 24 | * Opcodes for i860:: i860 Opcodes |
| 25 | @end menu |
| 26 | |
| 27 | @node Notes-i860 |
| 28 | @section i860 Notes |
| 29 | This is a fairly complete i860 assembler which is compatible with the |
| 30 | UNIX System V/860 Release 4 assembler. However, it does not currently |
| 31 | support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}). |
| 32 | |
| 33 | Like the SVR4/860 assembler, the output object format is ELF32. Currently, |
| 34 | this is the only supported object format. If there is sufficient interest, |
| 35 | other formats such as COFF may be implemented. |
| 36 | |
| 37 | Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter |
| 38 | being the default. One difference is that AT&T syntax requires the '%' |
| 39 | prefix on register names while Intel syntax does not. Another difference |
| 40 | is in the specification of relocatable expressions. The Intel syntax |
| 41 | is @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha} |
| 42 | (and similarly for the "l" and "h" selectors). |
| 43 | @node Options-i860 |
| 44 | @section i860 Command-line Options |
| 45 | @subsection SVR4 compatibility options |
| 46 | @table @code |
| 47 | @item -V |
| 48 | Print assembler version. |
| 49 | @item -Qy |
| 50 | Ignored. |
| 51 | @item -Qn |
| 52 | Ignored. |
| 53 | @end table |
| 54 | @subsection Other options |
| 55 | @table @code |
| 56 | @item -EL |
| 57 | Select little endian output (this is the default). |
| 58 | @item -EB |
| 59 | Select big endian output. Note that the i860 always reads instructions |
| 60 | as little endian data, so this option only effects data and not |
| 61 | instructions. |
| 62 | @item -mwarn-expand |
| 63 | Emit a warning message if any pseudo-instruction expansions occurred. |
| 64 | For example, a @code{or} instruction with an immediate larger than 16-bits |
| 65 | will be expanded into two instructions. This is a very undesirable feature to |
| 66 | rely on, so this flag can help detect any code where it happens. One |
| 67 | use of it, for instance, has been to find and eliminate any place |
| 68 | where @code{gcc} may emit these pseudo-instructions. |
| 69 | @item -mxp |
| 70 | Enable support for the i860XP instructions and control registers. By default, |
| 71 | this option is disabled so that only the base instruction set (i.e., i860XR) |
| 72 | is supported. |
| 73 | @item -mintel-syntax |
| 74 | The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the |
| 75 | Intel syntax. |
| 76 | @end table |
| 77 | |
| 78 | @node Directives-i860 |
| 79 | @section i860 Machine Directives |
| 80 | |
| 81 | @cindex machine directives, i860 |
| 82 | @cindex i860 machine directives |
| 83 | |
| 84 | @table @code |
| 85 | @cindex @code{dual} directive, i860 |
| 86 | @item .dual |
| 87 | Enter dual instruction mode. While this directive is supported, the |
| 88 | preferred way to use dual instruction mode is to explicitly code |
| 89 | the dual bit with the @code{d.} prefix. |
| 90 | @end table |
| 91 | |
| 92 | @table @code |
| 93 | @cindex @code{enddual} directive, i860 |
| 94 | @item .enddual |
| 95 | Exit dual instruction mode. While this directive is supported, the |
| 96 | preferred way to use dual instruction mode is to explicitly code |
| 97 | the dual bit with the @code{d.} prefix. |
| 98 | @end table |
| 99 | |
| 100 | @table @code |
| 101 | @cindex @code{atmp} directive, i860 |
| 102 | @item .atmp |
| 103 | Change the temporary register used when expanding pseudo operations. The |
| 104 | default register is @code{r31}. |
| 105 | @end table |
| 106 | |
| 107 | The @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode. |
| 108 | |
| 109 | @node Opcodes for i860 |
| 110 | @section i860 Opcodes |
| 111 | |
| 112 | @cindex opcodes, i860 |
| 113 | @cindex i860 opcodes |
| 114 | All of the Intel i860XR and i860XP machine instructions are supported. Please see |
| 115 | either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information. |
| 116 | @subsection Other instruction support (pseudo-instructions) |
| 117 | For compatibility with some other i860 assemblers, a number of |
| 118 | pseudo-instructions are supported. While these are supported, they are |
| 119 | a very undesirable feature that should be avoided -- in particular, when |
| 120 | they result in an expansion to multiple actual i860 instructions. Below |
| 121 | are the pseudo-instructions that result in expansions. |
| 122 | @itemize @bullet |
| 123 | @item Load large immediate into general register: |
| 124 | |
| 125 | The pseudo-instruction @code{mov imm,%rn} (where the immediate does |
| 126 | not fit within a signed 16-bit field) will be expanded into: |
| 127 | @smallexample |
| 128 | orh large_imm@@h,%r0,%rn |
| 129 | or large_imm@@l,%rn,%rn |
| 130 | @end smallexample |
| 131 | @item Load/store with relocatable address expression: |
| 132 | |
| 133 | For example, the pseudo-instruction @code{ld.b addr,%rn} |
| 134 | will be expanded into: |
| 135 | @smallexample |
| 136 | orh addr_exp@@ha,%r0,%r31 |
| 137 | ld.l addr_exp@@l(%r31),%rn |
| 138 | @end smallexample |
| 139 | |
| 140 | The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well. |
| 141 | @item Signed large immediate with add/subtract: |
| 142 | |
| 143 | If any of the arithmetic operations @code{adds, addu, subs, subu} are used |
| 144 | with an immediate larger than 16-bits (signed), then they will be expanded. |
| 145 | For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to: |
| 146 | @smallexample |
| 147 | orh large_imm@@h,%r0,%r31 |
| 148 | or large_imm@@l,%r31,%r31 |
| 149 | adds %r31,%rx,%rn |
| 150 | @end smallexample |
| 151 | @item Unsigned large immediate with logical operations: |
| 152 | |
| 153 | Logical operations (@code{or, andnot, or, xor}) also result in expansions. |
| 154 | The pseudo-instruction @code{or large_imm,%rx,%rn} results in: |
| 155 | @smallexample |
| 156 | orh large_imm@@h,%rx,%r31 |
| 157 | or large_imm@@l,%r31,%rn |
| 158 | @end smallexample |
| 159 | |
| 160 | Similarly for the others, except for @code{and} which expands to: |
| 161 | @smallexample |
| 162 | andnot (-1 - large_imm)@@h,%rx,%r31 |
| 163 | andnot (-1 - large_imm)@@l,%r31,%rn |
| 164 | @end smallexample |
| 165 | @end itemize |
| 166 | |