| 1 | @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000 |
| 2 | @c Free Software Foundation, Inc. |
| 3 | @c This is part of the GAS manual. |
| 4 | @c For copying conditions, see the file as.texinfo. |
| 5 | @ifset GENERIC |
| 6 | @page |
| 7 | @node MIPS-Dependent |
| 8 | @chapter MIPS Dependent Features |
| 9 | @end ifset |
| 10 | @ifclear GENERIC |
| 11 | @node Machine Dependencies |
| 12 | @chapter MIPS Dependent Features |
| 13 | @end ifclear |
| 14 | |
| 15 | @cindex MIPS processor |
| 16 | @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several |
| 17 | different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, |
| 18 | and MIPS64. For information about the @sc{mips} instruction set, see |
| 19 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). |
| 20 | For an overview of @sc{mips} assembly conventions, see ``Appendix D: |
| 21 | Assembly Language Programming'' in the same work. |
| 22 | |
| 23 | @menu |
| 24 | * MIPS Opts:: Assembler options |
| 25 | * MIPS Object:: ECOFF object code |
| 26 | * MIPS Stabs:: Directives for debugging information |
| 27 | * MIPS ISA:: Directives to override the ISA level |
| 28 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions |
| 29 | * MIPS insn:: Directive to mark data as an instruction |
| 30 | * MIPS option stack:: Directives to save and restore options |
| 31 | @end menu |
| 32 | |
| 33 | @node MIPS Opts |
| 34 | @section Assembler options |
| 35 | |
| 36 | The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these |
| 37 | special options: |
| 38 | |
| 39 | @table @code |
| 40 | @cindex @code{-G} option (MIPS) |
| 41 | @item -G @var{num} |
| 42 | This option sets the largest size of an object that can be referenced |
| 43 | implicitly with the @code{gp} register. It is only accepted for targets |
| 44 | that use @sc{ecoff} format. The default value is 8. |
| 45 | |
| 46 | @cindex @code{-EB} option (MIPS) |
| 47 | @cindex @code{-EL} option (MIPS) |
| 48 | @cindex MIPS big-endian output |
| 49 | @cindex MIPS little-endian output |
| 50 | @cindex big-endian output, MIPS |
| 51 | @cindex little-endian output, MIPS |
| 52 | @item -EB |
| 53 | @itemx -EL |
| 54 | Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or |
| 55 | little-endian output at run time (unlike the other @sc{gnu} development |
| 56 | tools, which must be configured for one or the other). Use @samp{-EB} |
| 57 | to select big-endian output, and @samp{-EL} for little-endian. |
| 58 | |
| 59 | @cindex MIPS architecture options |
| 60 | @item -mips1 |
| 61 | @itemx -mips2 |
| 62 | @itemx -mips3 |
| 63 | @itemx -mips4 |
| 64 | @itemx -mips5 |
| 65 | @itemx -mips32 |
| 66 | @itemx -mips64 |
| 67 | Generate code for a particular MIPS Instruction Set Architecture level. |
| 68 | @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, |
| 69 | @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the |
| 70 | @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and |
| 71 | @sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, and |
| 72 | @samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, and |
| 73 | @sc{MIPS64} ISA processors, respectively. You can also switch |
| 74 | instruction sets during the assembly; see @ref{MIPS ISA, Directives to |
| 75 | override the ISA level}. |
| 76 | |
| 77 | @item -mgp32 |
| 78 | Assume that 32-bit general purpose registers are available. This |
| 79 | affects synthetic instructions such as @code{move}, which will assemble |
| 80 | to a 32-bit or a 64-bit instruction depending on this flag. On some |
| 81 | MIPS variants there is a 32-bit mode flag; when this flag is set, |
| 82 | 64-bit instructions generate a trap. Also, some 32-bit OSes only save |
| 83 | the 32-bit registers on a context switch, so it is essential never to |
| 84 | use the 64-bit registers. |
| 85 | |
| 86 | @item -mgp64 |
| 87 | Assume that 64-bit general purpose registers are available. This is |
| 88 | provided in the interests of symmetry with -gp32. |
| 89 | |
| 90 | @item -mips16 |
| 91 | @itemx -no-mips16 |
| 92 | Generate code for the MIPS 16 processor. This is equivalent to putting |
| 93 | @samp{.set mips16} at the start of the assembly file. @samp{-no-mips16} |
| 94 | turns off this option. |
| 95 | |
| 96 | @item -mfix7000 |
| 97 | @itemx -no-mfix7000 |
| 98 | Cause nops to be inserted if the read of the destination register |
| 99 | of an mfhi or mflo instruction occurs in the following two instructions. |
| 100 | |
| 101 | @item -m4010 |
| 102 | @itemx -no-m4010 |
| 103 | Generate code for the LSI @sc{r4010} chip. This tells the assembler to |
| 104 | accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, |
| 105 | etc.), and to not schedule @samp{nop} instructions around accesses to |
| 106 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this |
| 107 | option. |
| 108 | |
| 109 | @item -m4650 |
| 110 | @itemx -no-m4650 |
| 111 | Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept |
| 112 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} |
| 113 | instructions around accesses to the @samp{HI} and @samp{LO} registers. |
| 114 | @samp{-no-m4650} turns off this option. |
| 115 | |
| 116 | @itemx -m3900 |
| 117 | @itemx -no-m3900 |
| 118 | @itemx -m4100 |
| 119 | @itemx -no-m4100 |
| 120 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS |
| 121 | @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions |
| 122 | specific to that chip, and to schedule for that chip's hazards. |
| 123 | |
| 124 | @item -march=@var{cpu} |
| 125 | Generate code for a particular MIPS cpu. It is exactly equivalent to |
| 126 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} |
| 127 | understood. Valid @var{cpu} value are: |
| 128 | |
| 129 | @quotation |
| 130 | 2000, |
| 131 | 3000, |
| 132 | 3900, |
| 133 | 4000, |
| 134 | 4010, |
| 135 | 4100, |
| 136 | 4111, |
| 137 | 4300, |
| 138 | 4400, |
| 139 | 4600, |
| 140 | 4650, |
| 141 | 5000, |
| 142 | rm5200, |
| 143 | rm5230, |
| 144 | rm5231, |
| 145 | rm5261, |
| 146 | rm5721, |
| 147 | 6000, |
| 148 | rm7000, |
| 149 | 8000, |
| 150 | 10000, |
| 151 | 12000, |
| 152 | mips32-4k, |
| 153 | sb1 |
| 154 | @end quotation |
| 155 | |
| 156 | @item -mtune=@var{cpu} |
| 157 | Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are |
| 158 | identical to @samp{-march=@var{cpu}}. |
| 159 | |
| 160 | @item -mcpu=@var{cpu} |
| 161 | Generate code and schedule for a particular MIPS cpu. This is exactly |
| 162 | equivalent to @samp{-march=@var{cpu}} and @samp{-mtune=@var{cpu}}. Valid |
| 163 | @var{cpu} values are identical to @samp{-march=@var{cpu}}. |
| 164 | Use of this option is discouraged. |
| 165 | |
| 166 | |
| 167 | @cindex @code{-nocpp} ignored (MIPS) |
| 168 | @item -nocpp |
| 169 | This option is ignored. It is accepted for command-line compatibility with |
| 170 | other assemblers, which use it to turn off C style preprocessing. With |
| 171 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the |
| 172 | @sc{gnu} assembler itself never runs the C preprocessor. |
| 173 | |
| 174 | @item --construct-floats |
| 175 | @itemx --no-construct-floats |
| 176 | @cindex --construct-floats |
| 177 | @cindex --no-construct-floats |
| 178 | The @code{--no-construct-floats} option disables the construction of |
| 179 | double width floating point constants by loading the two halves of the |
| 180 | value into the two single width floating point registers that make up |
| 181 | the double width register. This feature is useful if the processor |
| 182 | support the FR bit in its status register, and this bit is known (by |
| 183 | the programmer) to be set. This bit prevents the aliasing of the double |
| 184 | width register by the single width registers. |
| 185 | |
| 186 | By default @code{--construct-floats} is selected, allowing construction |
| 187 | of these floating point constants. |
| 188 | |
| 189 | @item --trap |
| 190 | @itemx --no-break |
| 191 | @c FIXME! (1) reflect these options (next item too) in option summaries; |
| 192 | @c (2) stop teasing, say _which_ instructions expanded _how_. |
| 193 | @code{@value{AS}} automatically macro expands certain division and |
| 194 | multiplication instructions to check for overflow and division by zero. This |
| 195 | option causes @code{@value{AS}} to generate code to take a trap exception |
| 196 | rather than a break exception when an error is detected. The trap instructions |
| 197 | are only supported at Instruction Set Architecture level 2 and higher. |
| 198 | |
| 199 | @item --break |
| 200 | @itemx --no-trap |
| 201 | Generate code to take a break exception rather than a trap exception when an |
| 202 | error is detected. This is the default. |
| 203 | |
| 204 | @item -n |
| 205 | When this option is used, @code{@value{AS}} will issue a warning every |
| 206 | time it generates a nop instruction from a macro. |
| 207 | @end table |
| 208 | |
| 209 | @node MIPS Object |
| 210 | @section MIPS ECOFF object code |
| 211 | |
| 212 | @cindex ECOFF sections |
| 213 | @cindex MIPS ECOFF sections |
| 214 | Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections |
| 215 | besides the usual @code{.text}, @code{.data} and @code{.bss}. The |
| 216 | additional sections are @code{.rdata}, used for read-only data, |
| 217 | @code{.sdata}, used for small data, and @code{.sbss}, used for small |
| 218 | common objects. |
| 219 | |
| 220 | @cindex small objects, MIPS ECOFF |
| 221 | @cindex @code{gp} register, MIPS |
| 222 | When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) |
| 223 | register to form the address of a ``small object''. Any object in the |
| 224 | @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. |
| 225 | For external objects, or for objects in the @code{.bss} section, you can use |
| 226 | the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via |
| 227 | @code{$gp}; the default value is 8, meaning that a reference to any object |
| 228 | eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to |
| 229 | @code{@value{AS}} prevents it from using the @code{$gp} register on the basis |
| 230 | of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} |
| 231 | or @code{sbss} in any case). The size of an object in the @code{.bss} section |
| 232 | is set by the @code{.comm} or @code{.lcomm} directive that defines it. The |
| 233 | size of an external object may be set with the @code{.extern} directive. For |
| 234 | example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes |
| 235 | in length, whie leaving @code{sym} otherwise undefined. |
| 236 | |
| 237 | Using small @sc{ecoff} objects requires linker support, and assumes that the |
| 238 | @code{$gp} register is correctly initialized (normally done automatically by |
| 239 | the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the |
| 240 | @code{$gp} register. |
| 241 | |
| 242 | @node MIPS Stabs |
| 243 | @section Directives for debugging information |
| 244 | |
| 245 | @cindex MIPS debugging directives |
| 246 | @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for |
| 247 | generating debugging information which are not support by traditional @sc{mips} |
| 248 | assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, |
| 249 | @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, |
| 250 | @code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information |
| 251 | generated by the three @code{.stab} directives can only be read by @sc{gdb}, |
| 252 | not by traditional @sc{mips} debuggers (this enhancement is required to fully |
| 253 | support C++ debugging). These directives are primarily used by compilers, not |
| 254 | assembly language programmers! |
| 255 | |
| 256 | @node MIPS ISA |
| 257 | @section Directives to override the ISA level |
| 258 | |
| 259 | @cindex MIPS ISA override |
| 260 | @kindex @code{.set mips@var{n}} |
| 261 | @sc{gnu} @code{@value{AS}} supports an additional directive to change |
| 262 | the @sc{mips} Instruction Set Architecture level on the fly: @code{.set |
| 263 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64. |
| 264 | The values 1 to 5, 32, and 64 make the assembler accept instructions |
| 265 | for the corresponding @sc{isa} level, from that point on in the |
| 266 | assembly. @code{.set mips@var{n}} affects not only which instructions |
| 267 | are permitted, but also how certain macros are expanded. @code{.set |
| 268 | mips0} restores the @sc{isa} level to its original level: either the |
| 269 | level you selected with command line options, or the default for your |
| 270 | configuration. You can use this feature to permit specific @sc{r4000} |
| 271 | instructions while assembling in 32 bit mode. Use this directive with |
| 272 | care! |
| 273 | |
| 274 | The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, |
| 275 | in which it will assemble instructions for the MIPS 16 processor. Use |
| 276 | @samp{.set nomips16} to return to normal 32 bit mode. |
| 277 | |
| 278 | Traditional @sc{mips} assemblers do not support this directive. |
| 279 | |
| 280 | @node MIPS autoextend |
| 281 | @section Directives for extending MIPS 16 bit instructions |
| 282 | |
| 283 | @kindex @code{.set autoextend} |
| 284 | @kindex @code{.set noautoextend} |
| 285 | By default, MIPS 16 instructions are automatically extended to 32 bits |
| 286 | when necessary. The directive @samp{.set noautoextend} will turn this |
| 287 | off. When @samp{.set noautoextend} is in effect, any 32 bit instruction |
| 288 | must be explicitly extended with the @samp{.e} modifier (e.g., |
| 289 | @samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used |
| 290 | to once again automatically extend instructions when necessary. |
| 291 | |
| 292 | This directive is only meaningful when in MIPS 16 mode. Traditional |
| 293 | @sc{mips} assemblers do not support this directive. |
| 294 | |
| 295 | @node MIPS insn |
| 296 | @section Directive to mark data as an instruction |
| 297 | |
| 298 | @kindex @code{.insn} |
| 299 | The @code{.insn} directive tells @code{@value{AS}} that the following |
| 300 | data is actually instructions. This makes a difference in MIPS 16 mode: |
| 301 | when loading the address of a label which precedes instructions, |
| 302 | @code{@value{AS}} automatically adds 1 to the value, so that jumping to |
| 303 | the loaded address will do the right thing. |
| 304 | |
| 305 | @node MIPS option stack |
| 306 | @section Directives to save and restore options |
| 307 | |
| 308 | @cindex MIPS option stack |
| 309 | @kindex @code{.set push} |
| 310 | @kindex @code{.set pop} |
| 311 | The directives @code{.set push} and @code{.set pop} may be used to save |
| 312 | and restore the current settings for all the options which are |
| 313 | controlled by @code{.set}. The @code{.set push} directive saves the |
| 314 | current settings on a stack. The @code{.set pop} directive pops the |
| 315 | stack and restores the settings. |
| 316 | |
| 317 | These directives can be useful inside an macro which must change an |
| 318 | option such as the ISA level or instruction reordering but does not want |
| 319 | to change the state of the code which invoked the macro. |
| 320 | |
| 321 | Traditional @sc{mips} assemblers do not support these directives. |