| 1 | @c Copyright (C) 1991-2014 Free Software Foundation, Inc. |
| 2 | @c This is part of the GAS manual. |
| 3 | @c For copying conditions, see the file as.texinfo. |
| 4 | @ifset GENERIC |
| 5 | @page |
| 6 | @node Sparc-Dependent |
| 7 | @chapter SPARC Dependent Features |
| 8 | @end ifset |
| 9 | @ifclear GENERIC |
| 10 | @node Machine Dependencies |
| 11 | @chapter SPARC Dependent Features |
| 12 | @end ifclear |
| 13 | |
| 14 | @cindex SPARC support |
| 15 | @menu |
| 16 | * Sparc-Opts:: Options |
| 17 | * Sparc-Aligned-Data:: Option to enforce aligned data |
| 18 | * Sparc-Syntax:: Syntax |
| 19 | * Sparc-Float:: Floating Point |
| 20 | * Sparc-Directives:: Sparc Machine Directives |
| 21 | @end menu |
| 22 | |
| 23 | @node Sparc-Opts |
| 24 | @section Options |
| 25 | |
| 26 | @cindex options for SPARC |
| 27 | @cindex SPARC options |
| 28 | @cindex architectures, SPARC |
| 29 | @cindex SPARC architectures |
| 30 | The SPARC chip family includes several successive versions, using the same |
| 31 | core instruction set, but including a few additional instructions at |
| 32 | each version. There are exceptions to this however. For details on what |
| 33 | instructions each variant supports, please see the chip's architecture |
| 34 | reference manual. |
| 35 | |
| 36 | By default, @code{@value{AS}} assumes the core instruction set (SPARC |
| 37 | v6), but ``bumps'' the architecture level as needed: it switches to |
| 38 | successively higher architectures as it encounters instructions that |
| 39 | only exist in the higher levels. |
| 40 | |
| 41 | If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump |
| 42 | past sparclite by default, an option must be passed to enable the |
| 43 | v9 instructions. |
| 44 | |
| 45 | GAS treats sparclite as being compatible with v8, unless an architecture |
| 46 | is explicitly requested. SPARC v9 is always incompatible with sparclite. |
| 47 | |
| 48 | @c The order here is the same as the order of enum sparc_opcode_arch_val |
| 49 | @c to give the user a sense of the order of the "bumping". |
| 50 | |
| 51 | @table @code |
| 52 | @kindex -Av6 |
| 53 | @kindex -Av7 |
| 54 | @kindex -Av8 |
| 55 | @kindex -Aleon |
| 56 | @kindex -Asparclet |
| 57 | @kindex -Asparclite |
| 58 | @kindex -Av9 |
| 59 | @kindex -Av9a |
| 60 | @kindex -Av9b |
| 61 | @kindex -Av9c |
| 62 | @kindex -Av9d |
| 63 | @kindex -Av9v |
| 64 | @kindex -Asparc |
| 65 | @kindex -Asparcvis |
| 66 | @kindex -Asparcvis2 |
| 67 | @kindex -Asparcfmaf |
| 68 | @kindex -Asparcima |
| 69 | @kindex -Asparcvis3 |
| 70 | @kindex -Asparcvis3r |
| 71 | @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite |
| 72 | @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv |
| 73 | @itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v |
| 74 | @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima |
| 75 | @itemx -Asparcvis3 | -Asparcvis3r |
| 76 | Use one of the @samp{-A} options to select one of the SPARC |
| 77 | architectures explicitly. If you select an architecture explicitly, |
| 78 | @code{@value{AS}} reports a fatal error if it encounters an instruction |
| 79 | or feature requiring an incompatible or higher level. |
| 80 | |
| 81 | @samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc}, |
| 82 | @samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment. |
| 83 | |
| 84 | @samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and |
| 85 | @samp{-Av9v} select a 64 bit environment and are not available unless GAS |
| 86 | is explicitly configured with 64 bit environment support. |
| 87 | |
| 88 | @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with |
| 89 | UltraSPARC VIS 1.0 extensions. |
| 90 | |
| 91 | @samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions, |
| 92 | as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}. |
| 93 | |
| 94 | @samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions, |
| 95 | as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}. |
| 96 | |
| 97 | @samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused |
| 98 | multiply-add, VIS 3.0, and HPC extension instructions, as well as the |
| 99 | instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}. |
| 100 | |
| 101 | @samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional |
| 102 | memory, floating point unfused multiply-add, integer multiply-add, and |
| 103 | cache sparing store instructions, as well as the instructions enabled |
| 104 | by @samp{-Av8plusd} and @samp{-Av9d}. |
| 105 | |
| 106 | @samp{-Asparc} specifies a v9 environment. It is equivalent to |
| 107 | @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise. |
| 108 | |
| 109 | @samp{-Asparcvis} specifies a v9a environment. It is equivalent to |
| 110 | @samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise. |
| 111 | |
| 112 | @samp{-Asparcvis2} specifies a v9b environment. It is equivalent to |
| 113 | @samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise. |
| 114 | |
| 115 | @samp{-Asparcfmaf} specifies a v9b environment with the floating point |
| 116 | fused multiply-add instructions enabled. |
| 117 | |
| 118 | @samp{-Asparcima} specifies a v9b environment with the integer |
| 119 | multiply-add instructions enabled. |
| 120 | |
| 121 | @samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0, |
| 122 | HPC , and floating point fused multiply-add instructions enabled. |
| 123 | |
| 124 | @samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, |
| 125 | HPC, transactional memory, random, and floating point unfused multiply-add |
| 126 | instructions enabled. |
| 127 | |
| 128 | @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc |
| 129 | @itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a |
| 130 | @itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v |
| 131 | @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2 |
| 132 | @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3 |
| 133 | @itemx -xarch=sparcvis3r |
| 134 | For compatibility with the SunOS v9 assembler. These options are |
| 135 | equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, |
| 136 | -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis, |
| 137 | -Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r, |
| 138 | respectively. |
| 139 | |
| 140 | @item -bump |
| 141 | Warn whenever it is necessary to switch to another level. |
| 142 | If an architecture level is explicitly requested, GAS will not issue |
| 143 | warnings until that level is reached, and will then bump the level |
| 144 | as required (except between incompatible levels). |
| 145 | |
| 146 | @item -32 | -64 |
| 147 | Select the word size, either 32 bits or 64 bits. |
| 148 | These options are only available with the ELF object file format, |
| 149 | and require that the necessary BFD support has been included. |
| 150 | @end table |
| 151 | |
| 152 | @node Sparc-Aligned-Data |
| 153 | @section Enforcing aligned data |
| 154 | |
| 155 | @cindex data alignment on SPARC |
| 156 | @cindex SPARC data alignment |
| 157 | SPARC GAS normally permits data to be misaligned. For example, it |
| 158 | permits the @code{.long} pseudo-op to be used on a byte boundary. |
| 159 | However, the native SunOS assemblers issue an error when they see |
| 160 | misaligned data. |
| 161 | |
| 162 | @kindex --enforce-aligned-data |
| 163 | You can use the @code{--enforce-aligned-data} option to make SPARC GAS |
| 164 | also issue an error about misaligned data, just as the SunOS |
| 165 | assemblers do. |
| 166 | |
| 167 | The @code{--enforce-aligned-data} option is not the default because gcc |
| 168 | issues misaligned data pseudo-ops when it initializes certain packed |
| 169 | data structures (structures defined using the @code{packed} attribute). |
| 170 | You may have to assemble with GAS in order to initialize packed data |
| 171 | structures in your own code. |
| 172 | |
| 173 | @cindex SPARC syntax |
| 174 | @cindex syntax, SPARC |
| 175 | @node Sparc-Syntax |
| 176 | @section Sparc Syntax |
| 177 | The assembler syntax closely follows The Sparc Architecture Manual, |
| 178 | versions 8 and 9, as well as most extensions defined by Sun |
| 179 | for their UltraSPARC and Niagara line of processors. |
| 180 | |
| 181 | @menu |
| 182 | * Sparc-Chars:: Special Characters |
| 183 | * Sparc-Regs:: Register Names |
| 184 | * Sparc-Constants:: Constant Names |
| 185 | * Sparc-Relocs:: Relocations |
| 186 | * Sparc-Size-Translations:: Size Translations |
| 187 | @end menu |
| 188 | |
| 189 | @node Sparc-Chars |
| 190 | @subsection Special Characters |
| 191 | |
| 192 | @cindex line comment character, Sparc |
| 193 | @cindex Sparc line comment character |
| 194 | A @samp{!} character appearing anywhere on a line indicates the start |
| 195 | of a comment that extends to the end of that line. |
| 196 | |
| 197 | If a @samp{#} appears as the first character of a line then the whole |
| 198 | line is treated as a comment, but in this case the line could also be |
| 199 | a logical line number directive (@pxref{Comments}) or a preprocessor |
| 200 | control command (@pxref{Preprocessing}). |
| 201 | |
| 202 | @cindex line separator, Sparc |
| 203 | @cindex statement separator, Sparc |
| 204 | @cindex Sparc line separator |
| 205 | @samp{;} can be used instead of a newline to separate statements. |
| 206 | |
| 207 | @node Sparc-Regs |
| 208 | @subsection Register Names |
| 209 | @cindex Sparc registers |
| 210 | @cindex register names, Sparc |
| 211 | |
| 212 | The Sparc integer register file is broken down into global, |
| 213 | outgoing, local, and incoming. |
| 214 | |
| 215 | @itemize @bullet |
| 216 | @item |
| 217 | The 8 global registers are referred to as @samp{%g@var{n}}. |
| 218 | |
| 219 | @item |
| 220 | The 8 outgoing registers are referred to as @samp{%o@var{n}}. |
| 221 | |
| 222 | @item |
| 223 | The 8 local registers are referred to as @samp{%l@var{n}}. |
| 224 | |
| 225 | @item |
| 226 | The 8 incoming registers are referred to as @samp{%i@var{n}}. |
| 227 | |
| 228 | @item |
| 229 | The frame pointer register @samp{%i6} can be referenced using |
| 230 | the alias @samp{%fp}. |
| 231 | |
| 232 | @item |
| 233 | The stack pointer register @samp{%o6} can be referenced using |
| 234 | the alias @samp{%sp}. |
| 235 | @end itemize |
| 236 | |
| 237 | Floating point registers are simply referred to as @samp{%f@var{n}}. |
| 238 | When assembling for pre-V9, only 32 floating point registers |
| 239 | are available. For V9 and later there are 64, but there are |
| 240 | restrictions when referencing the upper 32 registers. They |
| 241 | can only be accessed as double or quad, and thus only even |
| 242 | or quad numbered accesses are allowed. For example, @samp{%f34} |
| 243 | is a legal floating point register, but @samp{%f35} is not. |
| 244 | |
| 245 | Certain V9 instructions allow access to ancillary state registers. |
| 246 | Most simply they can be referred to as @samp{%asr@var{n}} where |
| 247 | @var{n} can be from 16 to 31. However, there are some aliases |
| 248 | defined to reference ASR registers defined for various UltraSPARC |
| 249 | processors: |
| 250 | |
| 251 | @itemize @bullet |
| 252 | @item |
| 253 | The tick compare register is referred to as @samp{%tick_cmpr}. |
| 254 | |
| 255 | @item |
| 256 | The system tick register is referred to as @samp{%stick}. An alias, |
| 257 | @samp{%sys_tick}, exists but is deprecated and should not be used |
| 258 | by new software. |
| 259 | |
| 260 | @item |
| 261 | The system tick compare register is referred to as @samp{%stick_cmpr}. |
| 262 | An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should |
| 263 | not be used by new software. |
| 264 | |
| 265 | @item |
| 266 | The software interrupt register is referred to as @samp{%softint}. |
| 267 | |
| 268 | @item |
| 269 | The set software interrupt register is referred to as @samp{%set_softint}. |
| 270 | The mnemonic @samp{%softint_set} is provided as an alias. |
| 271 | |
| 272 | @item |
| 273 | The clear software interrupt register is referred to as |
| 274 | @samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided |
| 275 | as an alias. |
| 276 | |
| 277 | @item |
| 278 | The performance instrumentation counters register is referred to as |
| 279 | @samp{%pic}. |
| 280 | |
| 281 | @item |
| 282 | The performance control register is referred to as @samp{%pcr}. |
| 283 | |
| 284 | @item |
| 285 | The graphics status register is referred to as @samp{%gsr}. |
| 286 | |
| 287 | @item |
| 288 | The V9 dispatch control register is referred to as @samp{%dcr}. |
| 289 | @end itemize |
| 290 | |
| 291 | Various V9 branch and conditional move instructions allow |
| 292 | specification of which set of integer condition codes to |
| 293 | test. These are referred to as @samp{%xcc} and @samp{%icc}. |
| 294 | |
| 295 | In V9, there are 4 sets of floating point condition codes |
| 296 | which are referred to as @samp{%fcc@var{n}}. |
| 297 | |
| 298 | Several special privileged and non-privileged registers |
| 299 | exist: |
| 300 | |
| 301 | @itemize @bullet |
| 302 | @item |
| 303 | The V9 address space identifier register is referred to as @samp{%asi}. |
| 304 | |
| 305 | @item |
| 306 | The V9 restorable windows register is referred to as @samp{%canrestore}. |
| 307 | |
| 308 | @item |
| 309 | The V9 savable windows register is referred to as @samp{%cansave}. |
| 310 | |
| 311 | @item |
| 312 | The V9 clean windows register is referred to as @samp{%cleanwin}. |
| 313 | |
| 314 | @item |
| 315 | The V9 current window pointer register is referred to as @samp{%cwp}. |
| 316 | |
| 317 | @item |
| 318 | The floating-point queue register is referred to as @samp{%fq}. |
| 319 | |
| 320 | @item |
| 321 | The V8 co-processor queue register is referred to as @samp{%cq}. |
| 322 | |
| 323 | @item |
| 324 | The floating point status register is referred to as @samp{%fsr}. |
| 325 | |
| 326 | @item |
| 327 | The other windows register is referred to as @samp{%otherwin}. |
| 328 | |
| 329 | @item |
| 330 | The V9 program counter register is referred to as @samp{%pc}. |
| 331 | |
| 332 | @item |
| 333 | The V9 next program counter register is referred to as @samp{%npc}. |
| 334 | |
| 335 | @item |
| 336 | The V9 processor interrupt level register is referred to as @samp{%pil}. |
| 337 | |
| 338 | @item |
| 339 | The V9 processor state register is referred to as @samp{%pstate}. |
| 340 | |
| 341 | @item |
| 342 | The trap base address register is referred to as @samp{%tba}. |
| 343 | |
| 344 | @item |
| 345 | The V9 tick register is referred to as @samp{%tick}. |
| 346 | |
| 347 | @item |
| 348 | The V9 trap level is referred to as @samp{%tl}. |
| 349 | |
| 350 | @item |
| 351 | The V9 trap program counter is referred to as @samp{%tpc}. |
| 352 | |
| 353 | @item |
| 354 | The V9 trap next program counter is referred to as @samp{%tnpc}. |
| 355 | |
| 356 | @item |
| 357 | The V9 trap state is referred to as @samp{%tstate}. |
| 358 | |
| 359 | @item |
| 360 | The V9 trap type is referred to as @samp{%tt}. |
| 361 | |
| 362 | @item |
| 363 | The V9 condition codes is referred to as @samp{%ccr}. |
| 364 | |
| 365 | @item |
| 366 | The V9 floating-point registers state is referred to as @samp{%fprs}. |
| 367 | |
| 368 | @item |
| 369 | The V9 version register is referred to as @samp{%ver}. |
| 370 | |
| 371 | @item |
| 372 | The V9 window state register is referred to as @samp{%wstate}. |
| 373 | |
| 374 | @item |
| 375 | The Y register is referred to as @samp{%y}. |
| 376 | |
| 377 | @item |
| 378 | The V8 window invalid mask register is referred to as @samp{%wim}. |
| 379 | |
| 380 | @item |
| 381 | The V8 processor state register is referred to as @samp{%psr}. |
| 382 | |
| 383 | @item |
| 384 | The V9 global register level register is referred to as @samp{%gl}. |
| 385 | @end itemize |
| 386 | |
| 387 | Several special register names exist for hypervisor mode code: |
| 388 | |
| 389 | @itemize @bullet |
| 390 | @item |
| 391 | The hyperprivileged processor state register is referred to as |
| 392 | @samp{%hpstate}. |
| 393 | |
| 394 | @item |
| 395 | The hyperprivileged trap state register is referred to as @samp{%htstate}. |
| 396 | |
| 397 | @item |
| 398 | The hyperprivileged interrupt pending register is referred to as |
| 399 | @samp{%hintp}. |
| 400 | |
| 401 | @item |
| 402 | The hyperprivileged trap base address register is referred to as |
| 403 | @samp{%htba}. |
| 404 | |
| 405 | @item |
| 406 | The hyperprivileged implementation version register is referred |
| 407 | to as @samp{%hver}. |
| 408 | |
| 409 | @item |
| 410 | The hyperprivileged system tick offset register is referred to as |
| 411 | @samp{%hstick_offset}. Note that there is no @samp{%hstick} register, |
| 412 | the normal @samp{%stick} is used. |
| 413 | |
| 414 | @item |
| 415 | The hyperprivileged system tick enable register is referred to as |
| 416 | @samp{%hstick_enable}. |
| 417 | |
| 418 | @item |
| 419 | The hyperprivileged system tick compare register is referred |
| 420 | to as @samp{%hstick_cmpr}. |
| 421 | @end itemize |
| 422 | |
| 423 | @node Sparc-Constants |
| 424 | @subsection Constants |
| 425 | @cindex Sparc constants |
| 426 | @cindex constants, Sparc |
| 427 | |
| 428 | Several Sparc instructions take an immediate operand field for |
| 429 | which mnemonic names exist. Two such examples are @samp{membar} |
| 430 | and @samp{prefetch}. Another example are the set of V9 |
| 431 | memory access instruction that allow specification of an |
| 432 | address space identifier. |
| 433 | |
| 434 | The @samp{membar} instruction specifies a memory barrier that is |
| 435 | the defined by the operand which is a bitmask. The supported |
| 436 | mask mnemonics are: |
| 437 | |
| 438 | @itemize @bullet |
| 439 | @item |
| 440 | @samp{#Sync} requests that all operations (including nonmemory |
| 441 | reference operations) appearing prior to the @code{membar} must have |
| 442 | been performed and the effects of any exceptions become visible before |
| 443 | any instructions after the @code{membar} may be initiated. This |
| 444 | corresponds to @code{membar} cmask field bit 2. |
| 445 | |
| 446 | @item |
| 447 | @samp{#MemIssue} requests that all memory reference operations |
| 448 | appearing prior to the @code{membar} must have been performed before |
| 449 | any memory operation after the @code{membar} may be initiated. This |
| 450 | corresponds to @code{membar} cmask field bit 1. |
| 451 | |
| 452 | @item |
| 453 | @samp{#Lookaside} requests that a store appearing prior to the |
| 454 | @code{membar} must complete before any load following the |
| 455 | @code{membar} referencing the same address can be initiated. This |
| 456 | corresponds to @code{membar} cmask field bit 0. |
| 457 | |
| 458 | @item |
| 459 | @samp{#StoreStore} defines that the effects of all stores appearing |
| 460 | prior to the @code{membar} instruction must be visible to all |
| 461 | processors before the effect of any stores following the |
| 462 | @code{membar}. Equivalent to the deprecated @code{stbar} instruction. |
| 463 | This corresponds to @code{membar} mmask field bit 3. |
| 464 | |
| 465 | @item |
| 466 | @samp{#LoadStore} defines all loads appearing prior to the |
| 467 | @code{membar} instruction must have been performed before the effect |
| 468 | of any stores following the @code{membar} is visible to any other |
| 469 | processor. This corresponds to @code{membar} mmask field bit 2. |
| 470 | |
| 471 | @item |
| 472 | @samp{#StoreLoad} defines that the effects of all stores appearing |
| 473 | prior to the @code{membar} instruction must be visible to all |
| 474 | processors before loads following the @code{membar} may be performed. |
| 475 | This corresponds to @code{membar} mmask field bit 1. |
| 476 | |
| 477 | @item |
| 478 | @samp{#LoadLoad} defines that all loads appearing prior to the |
| 479 | @code{membar} instruction must have been performed before any loads |
| 480 | following the @code{membar} may be performed. This corresponds to |
| 481 | @code{membar} mmask field bit 0. |
| 482 | |
| 483 | @end itemize |
| 484 | |
| 485 | These values can be ored together, for example: |
| 486 | |
| 487 | @example |
| 488 | membar #Sync |
| 489 | membar #StoreLoad | #LoadLoad |
| 490 | membar #StoreLoad | #StoreStore |
| 491 | @end example |
| 492 | |
| 493 | The @code{prefetch} and @code{prefetcha} instructions take a prefetch |
| 494 | function code. The following prefetch function code constant |
| 495 | mnemonics are available: |
| 496 | |
| 497 | @itemize @bullet |
| 498 | @item |
| 499 | @samp{#n_reads} requests a prefetch for several reads, and corresponds |
| 500 | to a prefetch function code of 0. |
| 501 | |
| 502 | @samp{#one_read} requests a prefetch for one read, and corresponds |
| 503 | to a prefetch function code of 1. |
| 504 | |
| 505 | @samp{#n_writes} requests a prefetch for several writes (and possibly |
| 506 | reads), and corresponds to a prefetch function code of 2. |
| 507 | |
| 508 | @samp{#one_write} requests a prefetch for one write, and corresponds |
| 509 | to a prefetch function code of 3. |
| 510 | |
| 511 | @samp{#page} requests a prefetch page, and corresponds to a prefetch |
| 512 | function code of 4. |
| 513 | |
| 514 | @samp{#invalidate} requests a prefetch invalidate, and corresponds to |
| 515 | a prefetch function code of 16. |
| 516 | |
| 517 | @samp{#unified} requests a prefetch to the nearest unified cache, and |
| 518 | corresponds to a prefetch function code of 17. |
| 519 | |
| 520 | @samp{#n_reads_strong} requests a strong prefetch for several reads, |
| 521 | and corresponds to a prefetch function code of 20. |
| 522 | |
| 523 | @samp{#one_read_strong} requests a strong prefetch for one read, |
| 524 | and corresponds to a prefetch function code of 21. |
| 525 | |
| 526 | @samp{#n_writes_strong} requests a strong prefetch for several writes, |
| 527 | and corresponds to a prefetch function code of 22. |
| 528 | |
| 529 | @samp{#one_write_strong} requests a strong prefetch for one write, |
| 530 | and corresponds to a prefetch function code of 23. |
| 531 | |
| 532 | Onle one prefetch code may be specified. Here are some examples: |
| 533 | |
| 534 | @example |
| 535 | prefetch [%l0 + %l2], #one_read |
| 536 | prefetch [%g2 + 8], #n_writes |
| 537 | prefetcha [%g1] 0x8, #unified |
| 538 | prefetcha [%o0 + 0x10] %asi, #n_reads |
| 539 | @end example |
| 540 | |
| 541 | The actual behavior of a given prefetch function code is processor |
| 542 | specific. If a processor does not implement a given prefetch |
| 543 | function code, it will treat the prefetch instruction as a nop. |
| 544 | |
| 545 | For instructions that accept an immediate address space identifier, |
| 546 | @code{@value{AS}} provides many mnemonics corresponding to |
| 547 | V9 defined as well as UltraSPARC and Niagara extended values. |
| 548 | For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}. |
| 549 | See the V9 and processor specific manuals for details. |
| 550 | |
| 551 | @end itemize |
| 552 | |
| 553 | @node Sparc-Relocs |
| 554 | @subsection Relocations |
| 555 | @cindex Sparc relocations |
| 556 | @cindex relocations, Sparc |
| 557 | |
| 558 | ELF relocations are available as defined in the 32-bit and 64-bit |
| 559 | Sparc ELF specifications. |
| 560 | |
| 561 | @code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10} |
| 562 | is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is |
| 563 | obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained |
| 564 | using @samp{%lox}. For example: |
| 565 | |
| 566 | @example |
| 567 | sethi %hi(symbol), %g1 |
| 568 | or %g1, %lo(symbol), %g1 |
| 569 | |
| 570 | sethi %hix(symbol), %g1 |
| 571 | xor %g1, %lox(symbol), %g1 |
| 572 | @end example |
| 573 | |
| 574 | These ``high'' mnemonics extract bits 31:10 of their operand, |
| 575 | and the ``low'' mnemonics extract bits 9:0 of their operand. |
| 576 | |
| 577 | V9 code model relocations can be requested as follows: |
| 578 | |
| 579 | @itemize @bullet |
| 580 | @item |
| 581 | @code{R_SPARC_HH22} is requested using @samp{%hh}. It can |
| 582 | also be generated using @samp{%uhi}. |
| 583 | @item |
| 584 | @code{R_SPARC_HM10} is requested using @samp{%hm}. It can |
| 585 | also be generated using @samp{%ulo}. |
| 586 | @item |
| 587 | @code{R_SPARC_LM22} is requested using @samp{%lm}. |
| 588 | |
| 589 | @item |
| 590 | @code{R_SPARC_H44} is requested using @samp{%h44}. |
| 591 | @item |
| 592 | @code{R_SPARC_M44} is requested using @samp{%m44}. |
| 593 | @item |
| 594 | @code{R_SPARC_L44} is requested using @samp{%l44} or @samp{%l34}. |
| 595 | @item |
| 596 | @code{R_SPARC_H34} is requested using @samp{%h34}. |
| 597 | @end itemize |
| 598 | |
| 599 | The @samp{%l34} generates a @code{R_SPARC_L44} relocation because it |
| 600 | calculates the necessary value, and therefore no explicit |
| 601 | @code{R_SPARC_L34} relocation needed to be created for this purpose. |
| 602 | |
| 603 | The @samp{%h34} and @samp{%l34} relocations are used for the abs34 code |
| 604 | model. Here is an example abs34 address generation sequence: |
| 605 | |
| 606 | @example |
| 607 | sethi %h34(symbol), %g1 |
| 608 | sllx %g1, 2, %g1 |
| 609 | or %g1, %l34(symbol), %g1 |
| 610 | @end example |
| 611 | |
| 612 | The PC relative relocation @code{R_SPARC_PC22} can be obtained by |
| 613 | enclosing an operand inside of @samp{%pc22}. Likewise, the |
| 614 | @code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}. |
| 615 | These are mostly used when assembling PIC code. For example, the |
| 616 | standard PIC sequence on Sparc to get the base of the global offset |
| 617 | table, PC relative, into a register, can be performed as: |
| 618 | |
| 619 | @example |
| 620 | sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 |
| 621 | add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 |
| 622 | @end example |
| 623 | |
| 624 | Several relocations exist to allow the link editor to potentially |
| 625 | optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22} |
| 626 | relocation can obtained by enclosing an operand inside of |
| 627 | @samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10} |
| 628 | relocation can obtained by enclosing an operand inside of |
| 629 | @samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be |
| 630 | obtained by enclosing an operand inside of @samp{%gdop}. |
| 631 | For example, assuming the GOT base is in register @code{%l7}: |
| 632 | |
| 633 | @example |
| 634 | sethi %gdop_hix22(symbol), %l1 |
| 635 | xor %l1, %gdop_lox10(symbol), %l1 |
| 636 | ld [%l7 + %l1], %l2, %gdop(symbol) |
| 637 | @end example |
| 638 | |
| 639 | There are many relocations that can be requested for access to |
| 640 | thread local storage variables. All of the Sparc TLS mnemonics |
| 641 | are supported: |
| 642 | |
| 643 | @itemize @bullet |
| 644 | @item |
| 645 | @code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}. |
| 646 | @item |
| 647 | @code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}. |
| 648 | @item |
| 649 | @code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}. |
| 650 | @item |
| 651 | @code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}. |
| 652 | |
| 653 | @item |
| 654 | @code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}. |
| 655 | @item |
| 656 | @code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}. |
| 657 | @item |
| 658 | @code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}. |
| 659 | @item |
| 660 | @code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}. |
| 661 | |
| 662 | @item |
| 663 | @code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}. |
| 664 | @item |
| 665 | @code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}. |
| 666 | @item |
| 667 | @code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}. |
| 668 | |
| 669 | @item |
| 670 | @code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}. |
| 671 | @item |
| 672 | @code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}. |
| 673 | @item |
| 674 | @code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}. |
| 675 | @item |
| 676 | @code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}. |
| 677 | @item |
| 678 | @code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}. |
| 679 | |
| 680 | @item |
| 681 | @code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}. |
| 682 | @item |
| 683 | @code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}. |
| 684 | @end itemize |
| 685 | |
| 686 | Here are some example TLS model sequences. |
| 687 | |
| 688 | First, General Dynamic: |
| 689 | |
| 690 | @example |
| 691 | sethi %tgd_hi22(symbol), %l1 |
| 692 | add %l1, %tgd_lo10(symbol), %l1 |
| 693 | add %l7, %l1, %o0, %tgd_add(symbol) |
| 694 | call __tls_get_addr, %tgd_call(symbol) |
| 695 | nop |
| 696 | @end example |
| 697 | |
| 698 | Local Dynamic: |
| 699 | |
| 700 | @example |
| 701 | sethi %tldm_hi22(symbol), %l1 |
| 702 | add %l1, %tldm_lo10(symbol), %l1 |
| 703 | add %l7, %l1, %o0, %tldm_add(symbol) |
| 704 | call __tls_get_addr, %tldm_call(symbol) |
| 705 | nop |
| 706 | |
| 707 | sethi %tldo_hix22(symbol), %l1 |
| 708 | xor %l1, %tldo_lox10(symbol), %l1 |
| 709 | add %o0, %l1, %l1, %tldo_add(symbol) |
| 710 | @end example |
| 711 | |
| 712 | Initial Exec: |
| 713 | |
| 714 | @example |
| 715 | sethi %tie_hi22(symbol), %l1 |
| 716 | add %l1, %tie_lo10(symbol), %l1 |
| 717 | ld [%l7 + %l1], %o0, %tie_ld(symbol) |
| 718 | add %g7, %o0, %o0, %tie_add(symbol) |
| 719 | |
| 720 | sethi %tie_hi22(symbol), %l1 |
| 721 | add %l1, %tie_lo10(symbol), %l1 |
| 722 | ldx [%l7 + %l1], %o0, %tie_ldx(symbol) |
| 723 | add %g7, %o0, %o0, %tie_add(symbol) |
| 724 | @end example |
| 725 | |
| 726 | And finally, Local Exec: |
| 727 | |
| 728 | @example |
| 729 | sethi %tle_hix22(symbol), %l1 |
| 730 | add %l1, %tle_lox10(symbol), %l1 |
| 731 | add %g7, %l1, %l1 |
| 732 | @end example |
| 733 | |
| 734 | When assembling for 64-bit, and a secondary constant addend is |
| 735 | specified in an address expression that would normally generate |
| 736 | an @code{R_SPARC_LO10} relocation, the assembler will emit an |
| 737 | @code{R_SPARC_OLO10} instead. |
| 738 | |
| 739 | @node Sparc-Size-Translations |
| 740 | @subsection Size Translations |
| 741 | @cindex Sparc size translations |
| 742 | @cindex size, translations, Sparc |
| 743 | |
| 744 | Often it is desirable to write code in an operand size agnostic |
| 745 | manner. @code{@value{AS}} provides support for this via |
| 746 | operand size opcode translations. Translations are supported |
| 747 | for loads, stores, shifts, compare-and-swap atomics, and the |
| 748 | @samp{clr} synthetic instruction. |
| 749 | |
| 750 | If generating 32-bit code, @code{@value{AS}} will generate the |
| 751 | 32-bit opcode. Whereas if 64-bit code is being generated, |
| 752 | the 64-bit opcode will be emitted. For example @code{ldn} |
| 753 | will be transformed into @code{ld} for 32-bit code and |
| 754 | @code{ldx} for 64-bit code. |
| 755 | |
| 756 | Here is an example meant to demonstrate all the supported |
| 757 | opcode translations: |
| 758 | |
| 759 | @example |
| 760 | ldn [%o0], %o1 |
| 761 | ldna [%o0] %asi, %o2 |
| 762 | stn %o1, [%o0] |
| 763 | stna %o2, [%o0] %asi |
| 764 | slln %o3, 3, %o3 |
| 765 | srln %o4, 8, %o4 |
| 766 | sran %o5, 12, %o5 |
| 767 | casn [%o0], %o1, %o2 |
| 768 | casna [%o0] %asi, %o1, %o2 |
| 769 | clrn %g1 |
| 770 | @end example |
| 771 | |
| 772 | In 32-bit mode @code{@value{AS}} will emit: |
| 773 | |
| 774 | @example |
| 775 | ld [%o0], %o1 |
| 776 | lda [%o0] %asi, %o2 |
| 777 | st %o1, [%o0] |
| 778 | sta %o2, [%o0] %asi |
| 779 | sll %o3, 3, %o3 |
| 780 | srl %o4, 8, %o4 |
| 781 | sra %o5, 12, %o5 |
| 782 | cas [%o0], %o1, %o2 |
| 783 | casa [%o0] %asi, %o1, %o2 |
| 784 | clr %g1 |
| 785 | @end example |
| 786 | |
| 787 | And in 64-bit mode @code{@value{AS}} will emit: |
| 788 | |
| 789 | @example |
| 790 | ldx [%o0], %o1 |
| 791 | ldxa [%o0] %asi, %o2 |
| 792 | stx %o1, [%o0] |
| 793 | stxa %o2, [%o0] %asi |
| 794 | sllx %o3, 3, %o3 |
| 795 | srlx %o4, 8, %o4 |
| 796 | srax %o5, 12, %o5 |
| 797 | casx [%o0], %o1, %o2 |
| 798 | casxa [%o0] %asi, %o1, %o2 |
| 799 | clrx %g1 |
| 800 | @end example |
| 801 | |
| 802 | Finally, the @samp{.nword} translating directive is supported |
| 803 | as well. It is documented in the section on Sparc machine |
| 804 | directives. |
| 805 | |
| 806 | @node Sparc-Float |
| 807 | @section Floating Point |
| 808 | |
| 809 | @cindex floating point, SPARC (@sc{ieee}) |
| 810 | @cindex SPARC floating point (@sc{ieee}) |
| 811 | The Sparc uses @sc{ieee} floating-point numbers. |
| 812 | |
| 813 | @node Sparc-Directives |
| 814 | @section Sparc Machine Directives |
| 815 | |
| 816 | @cindex SPARC machine directives |
| 817 | @cindex machine directives, SPARC |
| 818 | The Sparc version of @code{@value{AS}} supports the following additional |
| 819 | machine directives: |
| 820 | |
| 821 | @table @code |
| 822 | @cindex @code{align} directive, SPARC |
| 823 | @item .align |
| 824 | This must be followed by the desired alignment in bytes. |
| 825 | |
| 826 | @cindex @code{common} directive, SPARC |
| 827 | @item .common |
| 828 | This must be followed by a symbol name, a positive number, and |
| 829 | @code{"bss"}. This behaves somewhat like @code{.comm}, but the |
| 830 | syntax is different. |
| 831 | |
| 832 | @cindex @code{half} directive, SPARC |
| 833 | @item .half |
| 834 | This is functionally identical to @code{.short}. |
| 835 | |
| 836 | @cindex @code{nword} directive, SPARC |
| 837 | @item .nword |
| 838 | On the Sparc, the @code{.nword} directive produces native word sized value, |
| 839 | ie. if assembling with -32 it is equivalent to @code{.word}, if assembling |
| 840 | with -64 it is equivalent to @code{.xword}. |
| 841 | |
| 842 | @cindex @code{proc} directive, SPARC |
| 843 | @item .proc |
| 844 | This directive is ignored. Any text following it on the same |
| 845 | line is also ignored. |
| 846 | |
| 847 | @cindex @code{register} directive, SPARC |
| 848 | @item .register |
| 849 | This directive declares use of a global application or system register. |
| 850 | It must be followed by a register name %g2, %g3, %g6 or %g7, comma and |
| 851 | the symbol name for that register. If symbol name is @code{#scratch}, |
| 852 | it is a scratch register, if it is @code{#ignore}, it just suppresses any |
| 853 | errors about using undeclared global register, but does not emit any |
| 854 | information about it into the object file. This can be useful e.g. if you |
| 855 | save the register before use and restore it after. |
| 856 | |
| 857 | @cindex @code{reserve} directive, SPARC |
| 858 | @item .reserve |
| 859 | This must be followed by a symbol name, a positive number, and |
| 860 | @code{"bss"}. This behaves somewhat like @code{.lcomm}, but the |
| 861 | syntax is different. |
| 862 | |
| 863 | @cindex @code{seg} directive, SPARC |
| 864 | @item .seg |
| 865 | This must be followed by @code{"text"}, @code{"data"}, or |
| 866 | @code{"data1"}. It behaves like @code{.text}, @code{.data}, or |
| 867 | @code{.data 1}. |
| 868 | |
| 869 | @cindex @code{skip} directive, SPARC |
| 870 | @item .skip |
| 871 | This is functionally identical to the @code{.space} directive. |
| 872 | |
| 873 | @cindex @code{word} directive, SPARC |
| 874 | @item .word |
| 875 | On the Sparc, the @code{.word} directive produces 32 bit values, |
| 876 | instead of the 16 bit values it produces on many other machines. |
| 877 | |
| 878 | @cindex @code{xword} directive, SPARC |
| 879 | @item .xword |
| 880 | On the Sparc V9 processor, the @code{.xword} directive produces |
| 881 | 64 bit values. |
| 882 | @end table |