| 1 | /* itbl-ops.c |
| 2 | Copyright 1997, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, |
| 3 | 2009 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GAS, the GNU Assembler. |
| 6 | |
| 7 | GAS is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3, or (at your option) |
| 10 | any later version. |
| 11 | |
| 12 | GAS is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with GAS; see the file COPYING. If not, write to the Free |
| 19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
| 20 | 02110-1301, USA. */ |
| 21 | |
| 22 | /*======================================================================*/ |
| 23 | /* |
| 24 | * Herein lies the support for dynamic specification of processor |
| 25 | * instructions and registers. Mnemonics, values, and formats for each |
| 26 | * instruction and register are specified in an ascii file consisting of |
| 27 | * table entries. The grammar for the table is defined in the document |
| 28 | * "Processor instruction table specification". |
| 29 | * |
| 30 | * Instructions use the gnu assembler syntax, with the addition of |
| 31 | * allowing mnemonics for register. |
| 32 | * Eg. "func $2,reg3,0x100,symbol ; comment" |
| 33 | * func - opcode name |
| 34 | * $n - register n |
| 35 | * reg3 - mnemonic for processor's register defined in table |
| 36 | * 0xddd..d - immediate value |
| 37 | * symbol - address of label or external symbol |
| 38 | * |
| 39 | * First, itbl_parse reads in the table of register and instruction |
| 40 | * names and formats, and builds a list of entries for each |
| 41 | * processor/type combination. lex and yacc are used to parse |
| 42 | * the entries in the table and call functions defined here to |
| 43 | * add each entry to our list. |
| 44 | * |
| 45 | * Then, when assembling or disassembling, these functions are called to |
| 46 | * 1) get information on a processor's registers and |
| 47 | * 2) assemble/disassemble an instruction. |
| 48 | * To assemble(disassemble) an instruction, the function |
| 49 | * itbl_assemble(itbl_disassemble) is called to search the list of |
| 50 | * instruction entries, and if a match is found, uses the format |
| 51 | * described in the instruction entry structure to complete the action. |
| 52 | * |
| 53 | * Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2" |
| 54 | * and we want to define function "pig" which takes two operands. |
| 55 | * |
| 56 | * Given the table entries: |
| 57 | * "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0" |
| 58 | * "p3 dreg d2 0x2" |
| 59 | * and that the instruction encoding for coprocessor pz has encoding: |
| 60 | * #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25) |
| 61 | * #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum) |
| 62 | * |
| 63 | * a structure to describe the instruction might look something like: |
| 64 | * struct itbl_entry = { |
| 65 | * e_processor processor = e_p3 |
| 66 | * e_type type = e_insn |
| 67 | * char *name = "pig" |
| 68 | * uint value = 0x1 |
| 69 | * uint flags = 0 |
| 70 | * struct itbl_range range = 24-21 |
| 71 | * struct itbl_field *field = { |
| 72 | * e_type type = e_dreg |
| 73 | * struct itbl_range range = 20-16 |
| 74 | * struct itbl_field *next = { |
| 75 | * e_type type = e_immed |
| 76 | * struct itbl_range range = 15-0 |
| 77 | * struct itbl_field *next = 0 |
| 78 | * }; |
| 79 | * }; |
| 80 | * struct itbl_entry *next = 0 |
| 81 | * }; |
| 82 | * |
| 83 | * And the assembler instructions: |
| 84 | * "pig d2,0x100" |
| 85 | * "pig $2,0x100" |
| 86 | * |
| 87 | * would both assemble to the hex value: |
| 88 | * "0x4e220100" |
| 89 | * |
| 90 | */ |
| 91 | |
| 92 | #include "as.h" |
| 93 | #include "itbl-ops.h" |
| 94 | #include <itbl-parse.h> |
| 95 | |
| 96 | /* #define DEBUG */ |
| 97 | |
| 98 | #ifdef DEBUG |
| 99 | #include <assert.h> |
| 100 | #define ASSERT(x) assert(x) |
| 101 | #define DBG(x) printf x |
| 102 | #else |
| 103 | #define ASSERT(x) |
| 104 | #define DBG(x) |
| 105 | #endif |
| 106 | |
| 107 | #ifndef min |
| 108 | #define min(a,b) (a<b?a:b) |
| 109 | #endif |
| 110 | |
| 111 | int itbl_have_entries = 0; |
| 112 | |
| 113 | /*======================================================================*/ |
| 114 | /* structures for keeping itbl format entries */ |
| 115 | |
| 116 | struct itbl_range { |
| 117 | int sbit; /* mask starting bit position */ |
| 118 | int ebit; /* mask ending bit position */ |
| 119 | }; |
| 120 | |
| 121 | struct itbl_field { |
| 122 | e_type type; /* dreg/creg/greg/immed/symb */ |
| 123 | struct itbl_range range; /* field's bitfield range within instruction */ |
| 124 | unsigned long flags; /* field flags */ |
| 125 | struct itbl_field *next; /* next field in list */ |
| 126 | }; |
| 127 | |
| 128 | /* These structures define the instructions and registers for a processor. |
| 129 | * If the type is an instruction, the structure defines the format of an |
| 130 | * instruction where the fields are the list of operands. |
| 131 | * The flags field below uses the same values as those defined in the |
| 132 | * gnu assembler and are machine specific. */ |
| 133 | struct itbl_entry { |
| 134 | e_processor processor; /* processor number */ |
| 135 | e_type type; /* dreg/creg/greg/insn */ |
| 136 | char *name; /* mnemionic name for insn/register */ |
| 137 | unsigned long value; /* opcode/instruction mask/register number */ |
| 138 | unsigned long flags; /* effects of the instruction */ |
| 139 | struct itbl_range range; /* bit range within instruction for value */ |
| 140 | struct itbl_field *fields; /* list of operand definitions (if any) */ |
| 141 | struct itbl_entry *next; /* next entry */ |
| 142 | }; |
| 143 | |
| 144 | /* local data and structures */ |
| 145 | |
| 146 | static int itbl_num_opcodes = 0; |
| 147 | /* Array of entries for each processor and entry type */ |
| 148 | static struct itbl_entry *entries[e_nprocs][e_ntypes]; |
| 149 | |
| 150 | /* local prototypes */ |
| 151 | static unsigned long build_opcode (struct itbl_entry *e); |
| 152 | static e_type get_type (int yytype); |
| 153 | static e_processor get_processor (int yyproc); |
| 154 | static struct itbl_entry **get_entries (e_processor processor, |
| 155 | e_type type); |
| 156 | static struct itbl_entry *find_entry_byname (e_processor processor, |
| 157 | e_type type, char *name); |
| 158 | static struct itbl_entry *find_entry_byval (e_processor processor, |
| 159 | e_type type, unsigned long val, struct itbl_range *r); |
| 160 | static struct itbl_entry *alloc_entry (e_processor processor, |
| 161 | e_type type, char *name, unsigned long value); |
| 162 | static unsigned long apply_range (unsigned long value, struct itbl_range r); |
| 163 | static unsigned long extract_range (unsigned long value, struct itbl_range r); |
| 164 | static struct itbl_field *alloc_field (e_type type, int sbit, |
| 165 | int ebit, unsigned long flags); |
| 166 | |
| 167 | /*======================================================================*/ |
| 168 | /* Interfaces to the parser */ |
| 169 | |
| 170 | /* Open the table and use lex and yacc to parse the entries. |
| 171 | * Return 1 for failure; 0 for success. */ |
| 172 | |
| 173 | int |
| 174 | itbl_parse (char *insntbl) |
| 175 | { |
| 176 | extern FILE *yyin; |
| 177 | extern int yyparse (void); |
| 178 | |
| 179 | yyin = fopen (insntbl, FOPEN_RT); |
| 180 | if (yyin == 0) |
| 181 | { |
| 182 | printf ("Can't open processor instruction specification file \"%s\"\n", |
| 183 | insntbl); |
| 184 | return 1; |
| 185 | } |
| 186 | |
| 187 | while (yyparse ()) |
| 188 | ; |
| 189 | |
| 190 | fclose (yyin); |
| 191 | itbl_have_entries = 1; |
| 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | /* Add a register entry */ |
| 196 | |
| 197 | struct itbl_entry * |
| 198 | itbl_add_reg (int yyprocessor, int yytype, char *regname, |
| 199 | int regnum) |
| 200 | { |
| 201 | return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname, |
| 202 | (unsigned long) regnum); |
| 203 | } |
| 204 | |
| 205 | /* Add an instruction entry */ |
| 206 | |
| 207 | struct itbl_entry * |
| 208 | itbl_add_insn (int yyprocessor, char *name, unsigned long value, |
| 209 | int sbit, int ebit, unsigned long flags) |
| 210 | { |
| 211 | struct itbl_entry *e; |
| 212 | e = alloc_entry (get_processor (yyprocessor), e_insn, name, value); |
| 213 | if (e) |
| 214 | { |
| 215 | e->range.sbit = sbit; |
| 216 | e->range.ebit = ebit; |
| 217 | e->flags = flags; |
| 218 | itbl_num_opcodes++; |
| 219 | } |
| 220 | return e; |
| 221 | } |
| 222 | |
| 223 | /* Add an operand to an instruction entry */ |
| 224 | |
| 225 | struct itbl_field * |
| 226 | itbl_add_operand (struct itbl_entry *e, int yytype, int sbit, |
| 227 | int ebit, unsigned long flags) |
| 228 | { |
| 229 | struct itbl_field *f, **last_f; |
| 230 | if (!e) |
| 231 | return 0; |
| 232 | /* Add to end of fields' list. */ |
| 233 | f = alloc_field (get_type (yytype), sbit, ebit, flags); |
| 234 | if (f) |
| 235 | { |
| 236 | last_f = &e->fields; |
| 237 | while (*last_f) |
| 238 | last_f = &(*last_f)->next; |
| 239 | *last_f = f; |
| 240 | f->next = 0; |
| 241 | } |
| 242 | return f; |
| 243 | } |
| 244 | |
| 245 | /*======================================================================*/ |
| 246 | /* Interfaces for assembler and disassembler */ |
| 247 | |
| 248 | #ifndef STAND_ALONE |
| 249 | static void append_insns_as_macros (void); |
| 250 | |
| 251 | /* Initialize for gas. */ |
| 252 | |
| 253 | void |
| 254 | itbl_init (void) |
| 255 | { |
| 256 | struct itbl_entry *e, **es; |
| 257 | e_processor procn; |
| 258 | e_type type; |
| 259 | |
| 260 | if (!itbl_have_entries) |
| 261 | return; |
| 262 | |
| 263 | /* Since register names don't have a prefix, put them in the symbol table so |
| 264 | they can't be used as symbols. This simplifies argument parsing as |
| 265 | we can let gas parse registers for us. */ |
| 266 | /* Use symbol_create instead of symbol_new so we don't try to |
| 267 | output registers into the object file's symbol table. */ |
| 268 | |
| 269 | for (type = e_regtype0; type < e_nregtypes; type++) |
| 270 | for (procn = e_p0; procn < e_nprocs; procn++) |
| 271 | { |
| 272 | es = get_entries (procn, type); |
| 273 | for (e = *es; e; e = e->next) |
| 274 | { |
| 275 | symbol_table_insert (symbol_create (e->name, reg_section, |
| 276 | e->value, &zero_address_frag)); |
| 277 | } |
| 278 | } |
| 279 | append_insns_as_macros (); |
| 280 | } |
| 281 | |
| 282 | /* Append insns to opcodes table and increase number of opcodes |
| 283 | * Structure of opcodes table: |
| 284 | * struct itbl_opcode |
| 285 | * { |
| 286 | * const char *name; |
| 287 | * const char *args; - string describing the arguments. |
| 288 | * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO |
| 289 | * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO |
| 290 | * unsigned long pinfo; - insn flags, or INSN_MACRO |
| 291 | * }; |
| 292 | * examples: |
| 293 | * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, |
| 294 | * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, |
| 295 | */ |
| 296 | |
| 297 | static char *form_args (struct itbl_entry *e); |
| 298 | static void |
| 299 | append_insns_as_macros (void) |
| 300 | { |
| 301 | struct ITBL_OPCODE_STRUCT *new_opcodes, *o; |
| 302 | struct itbl_entry *e, **es; |
| 303 | int n, id, size, new_size, new_num_opcodes; |
| 304 | |
| 305 | if (!itbl_have_entries) |
| 306 | return; |
| 307 | |
| 308 | if (!itbl_num_opcodes) /* no new instructions to add! */ |
| 309 | { |
| 310 | return; |
| 311 | } |
| 312 | DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES)); |
| 313 | |
| 314 | new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes; |
| 315 | ASSERT (new_num_opcodes >= itbl_num_opcodes); |
| 316 | |
| 317 | size = sizeof (struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES; |
| 318 | ASSERT (size >= 0); |
| 319 | DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0]))); |
| 320 | |
| 321 | new_size = sizeof (struct ITBL_OPCODE_STRUCT) * new_num_opcodes; |
| 322 | ASSERT (new_size > size); |
| 323 | |
| 324 | /* FIXME since ITBL_OPCODES culd be a static table, |
| 325 | we can't realloc or delete the old memory. */ |
| 326 | new_opcodes = (struct ITBL_OPCODE_STRUCT *) malloc (new_size); |
| 327 | if (!new_opcodes) |
| 328 | { |
| 329 | printf (_("Unable to allocate memory for new instructions\n")); |
| 330 | return; |
| 331 | } |
| 332 | if (size) /* copy preexisting opcodes table */ |
| 333 | memcpy (new_opcodes, ITBL_OPCODES, size); |
| 334 | |
| 335 | /* FIXME! some NUMOPCODES are calculated expressions. |
| 336 | These need to be changed before itbls can be supported. */ |
| 337 | |
| 338 | id = ITBL_NUM_MACROS; /* begin the next macro id after the last */ |
| 339 | o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */ |
| 340 | for (n = e_p0; n < e_nprocs; n++) |
| 341 | { |
| 342 | es = get_entries (n, e_insn); |
| 343 | for (e = *es; e; e = e->next) |
| 344 | { |
| 345 | /* name, args, mask, match, pinfo |
| 346 | * {"li", "t,i", 0x34000000, 0xffe00000, WR_t }, |
| 347 | * {"li", "t,I", 0, (int) M_LI, INSN_MACRO }, |
| 348 | * Construct args from itbl_fields. |
| 349 | */ |
| 350 | o->name = e->name; |
| 351 | o->args = strdup (form_args (e)); |
| 352 | o->mask = apply_range (e->value, e->range); |
| 353 | /* FIXME how to catch during assembly? */ |
| 354 | /* mask to identify this insn */ |
| 355 | o->match = apply_range (e->value, e->range); |
| 356 | o->pinfo = 0; |
| 357 | |
| 358 | #ifdef USE_MACROS |
| 359 | o->mask = id++; /* FIXME how to catch during assembly? */ |
| 360 | o->match = 0; /* for macros, the insn_isa number */ |
| 361 | o->pinfo = INSN_MACRO; |
| 362 | #endif |
| 363 | |
| 364 | /* Don't add instructions which caused an error */ |
| 365 | if (o->args) |
| 366 | o++; |
| 367 | else |
| 368 | new_num_opcodes--; |
| 369 | } |
| 370 | } |
| 371 | ITBL_OPCODES = new_opcodes; |
| 372 | ITBL_NUM_OPCODES = new_num_opcodes; |
| 373 | |
| 374 | /* FIXME |
| 375 | At this point, we can free the entries, as they should have |
| 376 | been added to the assembler's tables. |
| 377 | Don't free name though, since name is being used by the new |
| 378 | opcodes table. |
| 379 | |
| 380 | Eventually, we should also free the new opcodes table itself |
| 381 | on exit. |
| 382 | */ |
| 383 | } |
| 384 | |
| 385 | static char * |
| 386 | form_args (struct itbl_entry *e) |
| 387 | { |
| 388 | static char s[31]; |
| 389 | char c = 0, *p = s; |
| 390 | struct itbl_field *f; |
| 391 | |
| 392 | ASSERT (e); |
| 393 | for (f = e->fields; f; f = f->next) |
| 394 | { |
| 395 | switch (f->type) |
| 396 | { |
| 397 | case e_dreg: |
| 398 | c = 'd'; |
| 399 | break; |
| 400 | case e_creg: |
| 401 | c = 't'; |
| 402 | break; |
| 403 | case e_greg: |
| 404 | c = 's'; |
| 405 | break; |
| 406 | case e_immed: |
| 407 | c = 'i'; |
| 408 | break; |
| 409 | case e_addr: |
| 410 | c = 'a'; |
| 411 | break; |
| 412 | default: |
| 413 | c = 0; /* ignore; unknown field type */ |
| 414 | } |
| 415 | if (c) |
| 416 | { |
| 417 | if (p != s) |
| 418 | *p++ = ','; |
| 419 | *p++ = c; |
| 420 | } |
| 421 | } |
| 422 | *p = 0; |
| 423 | return s; |
| 424 | } |
| 425 | #endif /* !STAND_ALONE */ |
| 426 | |
| 427 | /* Get processor's register name from val */ |
| 428 | |
| 429 | int |
| 430 | itbl_get_reg_val (char *name, unsigned long *pval) |
| 431 | { |
| 432 | e_type t; |
| 433 | e_processor p; |
| 434 | |
| 435 | for (p = e_p0; p < e_nprocs; p++) |
| 436 | { |
| 437 | for (t = e_regtype0; t < e_nregtypes; t++) |
| 438 | { |
| 439 | if (itbl_get_val (p, t, name, pval)) |
| 440 | return 1; |
| 441 | } |
| 442 | } |
| 443 | return 0; |
| 444 | } |
| 445 | |
| 446 | char * |
| 447 | itbl_get_name (e_processor processor, e_type type, unsigned long val) |
| 448 | { |
| 449 | struct itbl_entry *r; |
| 450 | /* type depends on instruction passed */ |
| 451 | r = find_entry_byval (processor, type, val, 0); |
| 452 | if (r) |
| 453 | return r->name; |
| 454 | else |
| 455 | return 0; /* error; invalid operand */ |
| 456 | } |
| 457 | |
| 458 | /* Get processor's register value from name */ |
| 459 | |
| 460 | int |
| 461 | itbl_get_val (e_processor processor, e_type type, char *name, |
| 462 | unsigned long *pval) |
| 463 | { |
| 464 | struct itbl_entry *r; |
| 465 | /* type depends on instruction passed */ |
| 466 | r = find_entry_byname (processor, type, name); |
| 467 | if (r == NULL) |
| 468 | return 0; |
| 469 | *pval = r->value; |
| 470 | return 1; |
| 471 | } |
| 472 | |
| 473 | /* Assemble instruction "name" with operands "s". |
| 474 | * name - name of instruction |
| 475 | * s - operands |
| 476 | * returns - long word for assembled instruction */ |
| 477 | |
| 478 | unsigned long |
| 479 | itbl_assemble (char *name, char *s) |
| 480 | { |
| 481 | unsigned long opcode; |
| 482 | struct itbl_entry *e = NULL; |
| 483 | struct itbl_field *f; |
| 484 | char *n; |
| 485 | int processor; |
| 486 | |
| 487 | if (!name || !*name) |
| 488 | return 0; /* error! must have an opcode name/expr */ |
| 489 | |
| 490 | /* find entry in list of instructions for all processors */ |
| 491 | for (processor = 0; processor < e_nprocs; processor++) |
| 492 | { |
| 493 | e = find_entry_byname (processor, e_insn, name); |
| 494 | if (e) |
| 495 | break; |
| 496 | } |
| 497 | if (!e) |
| 498 | return 0; /* opcode not in table; invalid instruction */ |
| 499 | opcode = build_opcode (e); |
| 500 | |
| 501 | /* parse opcode's args (if any) */ |
| 502 | for (f = e->fields; f; f = f->next) /* for each arg, ... */ |
| 503 | { |
| 504 | struct itbl_entry *r; |
| 505 | unsigned long value; |
| 506 | if (!s || !*s) |
| 507 | return 0; /* error - not enough operands */ |
| 508 | n = itbl_get_field (&s); |
| 509 | /* n should be in form $n or 0xhhh (are symbol names valid?? */ |
| 510 | switch (f->type) |
| 511 | { |
| 512 | case e_dreg: |
| 513 | case e_creg: |
| 514 | case e_greg: |
| 515 | /* Accept either a string name |
| 516 | * or '$' followed by the register number */ |
| 517 | if (*n == '$') |
| 518 | { |
| 519 | n++; |
| 520 | value = strtol (n, 0, 10); |
| 521 | /* FIXME! could have "0l"... then what?? */ |
| 522 | if (value == 0 && *n != '0') |
| 523 | return 0; /* error; invalid operand */ |
| 524 | } |
| 525 | else |
| 526 | { |
| 527 | r = find_entry_byname (e->processor, f->type, n); |
| 528 | if (r) |
| 529 | value = r->value; |
| 530 | else |
| 531 | return 0; /* error; invalid operand */ |
| 532 | } |
| 533 | break; |
| 534 | case e_addr: |
| 535 | /* use assembler's symbol table to find symbol */ |
| 536 | /* FIXME!! Do we need this? |
| 537 | if so, what about relocs?? |
| 538 | my_getExpression (&imm_expr, s); |
| 539 | return 0; /-* error; invalid operand *-/ |
| 540 | break; |
| 541 | */ |
| 542 | /* If not a symbol, fall thru to IMMED */ |
| 543 | case e_immed: |
| 544 | if (*n == '0' && *(n + 1) == 'x') /* hex begins 0x... */ |
| 545 | { |
| 546 | n += 2; |
| 547 | value = strtol (n, 0, 16); |
| 548 | /* FIXME! could have "0xl"... then what?? */ |
| 549 | } |
| 550 | else |
| 551 | { |
| 552 | value = strtol (n, 0, 10); |
| 553 | /* FIXME! could have "0l"... then what?? */ |
| 554 | if (value == 0 && *n != '0') |
| 555 | return 0; /* error; invalid operand */ |
| 556 | } |
| 557 | break; |
| 558 | default: |
| 559 | return 0; /* error; invalid field spec */ |
| 560 | } |
| 561 | opcode |= apply_range (value, f->range); |
| 562 | } |
| 563 | if (s && *s) |
| 564 | return 0; /* error - too many operands */ |
| 565 | return opcode; /* done! */ |
| 566 | } |
| 567 | |
| 568 | /* Disassemble instruction "insn". |
| 569 | * insn - instruction |
| 570 | * s - buffer to hold disassembled instruction |
| 571 | * returns - 1 if succeeded; 0 if failed |
| 572 | */ |
| 573 | |
| 574 | int |
| 575 | itbl_disassemble (char *s, unsigned long insn) |
| 576 | { |
| 577 | e_processor processor; |
| 578 | struct itbl_entry *e; |
| 579 | struct itbl_field *f; |
| 580 | |
| 581 | if (!ITBL_IS_INSN (insn)) |
| 582 | return 0; /* error */ |
| 583 | processor = get_processor (ITBL_DECODE_PNUM (insn)); |
| 584 | |
| 585 | /* find entry in list */ |
| 586 | e = find_entry_byval (processor, e_insn, insn, 0); |
| 587 | if (!e) |
| 588 | return 0; /* opcode not in table; invalid instruction */ |
| 589 | strcpy (s, e->name); |
| 590 | |
| 591 | /* Parse insn's args (if any). */ |
| 592 | for (f = e->fields; f; f = f->next) /* for each arg, ... */ |
| 593 | { |
| 594 | struct itbl_entry *r; |
| 595 | unsigned long value; |
| 596 | char s_value[20]; |
| 597 | |
| 598 | if (f == e->fields) /* First operand is preceded by tab. */ |
| 599 | strcat (s, "\t"); |
| 600 | else /* ','s separate following operands. */ |
| 601 | strcat (s, ","); |
| 602 | value = extract_range (insn, f->range); |
| 603 | /* n should be in form $n or 0xhhh (are symbol names valid?? */ |
| 604 | switch (f->type) |
| 605 | { |
| 606 | case e_dreg: |
| 607 | case e_creg: |
| 608 | case e_greg: |
| 609 | /* Accept either a string name |
| 610 | or '$' followed by the register number. */ |
| 611 | r = find_entry_byval (e->processor, f->type, value, &f->range); |
| 612 | if (r) |
| 613 | strcat (s, r->name); |
| 614 | else |
| 615 | { |
| 616 | sprintf (s_value, "$%lu", value); |
| 617 | strcat (s, s_value); |
| 618 | } |
| 619 | break; |
| 620 | case e_addr: |
| 621 | /* Use assembler's symbol table to find symbol. */ |
| 622 | /* FIXME!! Do we need this? If so, what about relocs?? */ |
| 623 | /* If not a symbol, fall through to IMMED. */ |
| 624 | case e_immed: |
| 625 | sprintf (s_value, "0x%lx", value); |
| 626 | strcat (s, s_value); |
| 627 | break; |
| 628 | default: |
| 629 | return 0; /* error; invalid field spec */ |
| 630 | } |
| 631 | } |
| 632 | return 1; /* Done! */ |
| 633 | } |
| 634 | |
| 635 | /*======================================================================*/ |
| 636 | /* |
| 637 | * Local functions for manipulating private structures containing |
| 638 | * the names and format for the new instructions and registers |
| 639 | * for each processor. |
| 640 | */ |
| 641 | |
| 642 | /* Calculate instruction's opcode and function values from entry */ |
| 643 | |
| 644 | static unsigned long |
| 645 | build_opcode (struct itbl_entry *e) |
| 646 | { |
| 647 | unsigned long opcode; |
| 648 | |
| 649 | opcode = apply_range (e->value, e->range); |
| 650 | opcode |= ITBL_ENCODE_PNUM (e->processor); |
| 651 | return opcode; |
| 652 | } |
| 653 | |
| 654 | /* Calculate absolute value given the relative value and bit position range |
| 655 | * within the instruction. |
| 656 | * The range is inclusive where 0 is least significant bit. |
| 657 | * A range of { 24, 20 } will have a mask of |
| 658 | * bit 3 2 1 |
| 659 | * pos: 1098 7654 3210 9876 5432 1098 7654 3210 |
| 660 | * bin: 0000 0001 1111 0000 0000 0000 0000 0000 |
| 661 | * hex: 0 1 f 0 0 0 0 0 |
| 662 | * mask: 0x01f00000. |
| 663 | */ |
| 664 | |
| 665 | static unsigned long |
| 666 | apply_range (unsigned long rval, struct itbl_range r) |
| 667 | { |
| 668 | unsigned long mask; |
| 669 | unsigned long aval; |
| 670 | int len = MAX_BITPOS - r.sbit; |
| 671 | |
| 672 | ASSERT (r.sbit >= r.ebit); |
| 673 | ASSERT (MAX_BITPOS >= r.sbit); |
| 674 | ASSERT (r.ebit >= 0); |
| 675 | |
| 676 | /* create mask by truncating 1s by shifting */ |
| 677 | mask = 0xffffffff << len; |
| 678 | mask = mask >> len; |
| 679 | mask = mask >> r.ebit; |
| 680 | mask = mask << r.ebit; |
| 681 | |
| 682 | aval = (rval << r.ebit) & mask; |
| 683 | return aval; |
| 684 | } |
| 685 | |
| 686 | /* Calculate relative value given the absolute value and bit position range |
| 687 | * within the instruction. */ |
| 688 | |
| 689 | static unsigned long |
| 690 | extract_range (unsigned long aval, struct itbl_range r) |
| 691 | { |
| 692 | unsigned long mask; |
| 693 | unsigned long rval; |
| 694 | int len = MAX_BITPOS - r.sbit; |
| 695 | |
| 696 | /* create mask by truncating 1s by shifting */ |
| 697 | mask = 0xffffffff << len; |
| 698 | mask = mask >> len; |
| 699 | mask = mask >> r.ebit; |
| 700 | mask = mask << r.ebit; |
| 701 | |
| 702 | rval = (aval & mask) >> r.ebit; |
| 703 | return rval; |
| 704 | } |
| 705 | |
| 706 | /* Extract processor's assembly instruction field name from s; |
| 707 | * forms are "n args" "n,args" or "n" */ |
| 708 | /* Return next argument from string pointer "s" and advance s. |
| 709 | * delimiters are " ,()" */ |
| 710 | |
| 711 | char * |
| 712 | itbl_get_field (char **S) |
| 713 | { |
| 714 | static char n[128]; |
| 715 | char *s; |
| 716 | int len; |
| 717 | |
| 718 | s = *S; |
| 719 | if (!s || !*s) |
| 720 | return 0; |
| 721 | /* FIXME: This is a weird set of delimiters. */ |
| 722 | len = strcspn (s, " \t,()"); |
| 723 | ASSERT (128 > len + 1); |
| 724 | strncpy (n, s, len); |
| 725 | n[len] = 0; |
| 726 | if (s[len] == '\0') |
| 727 | s = 0; /* no more args */ |
| 728 | else |
| 729 | s += len + 1; /* advance to next arg */ |
| 730 | |
| 731 | *S = s; |
| 732 | return n; |
| 733 | } |
| 734 | |
| 735 | /* Search entries for a given processor and type |
| 736 | * to find one matching the name "n". |
| 737 | * Return a pointer to the entry */ |
| 738 | |
| 739 | static struct itbl_entry * |
| 740 | find_entry_byname (e_processor processor, |
| 741 | e_type type, char *n) |
| 742 | { |
| 743 | struct itbl_entry *e, **es; |
| 744 | |
| 745 | es = get_entries (processor, type); |
| 746 | for (e = *es; e; e = e->next) /* for each entry, ... */ |
| 747 | { |
| 748 | if (!strcmp (e->name, n)) |
| 749 | return e; |
| 750 | } |
| 751 | return 0; |
| 752 | } |
| 753 | |
| 754 | /* Search entries for a given processor and type |
| 755 | * to find one matching the value "val" for the range "r". |
| 756 | * Return a pointer to the entry. |
| 757 | * This function is used for disassembling fields of an instruction. |
| 758 | */ |
| 759 | |
| 760 | static struct itbl_entry * |
| 761 | find_entry_byval (e_processor processor, e_type type, |
| 762 | unsigned long val, struct itbl_range *r) |
| 763 | { |
| 764 | struct itbl_entry *e, **es; |
| 765 | unsigned long eval; |
| 766 | |
| 767 | es = get_entries (processor, type); |
| 768 | for (e = *es; e; e = e->next) /* for each entry, ... */ |
| 769 | { |
| 770 | if (processor != e->processor) |
| 771 | continue; |
| 772 | /* For insns, we might not know the range of the opcode, |
| 773 | * so a range of 0 will allow this routine to match against |
| 774 | * the range of the entry to be compared with. |
| 775 | * This could cause ambiguities. |
| 776 | * For operands, we get an extracted value and a range. |
| 777 | */ |
| 778 | /* if range is 0, mask val against the range of the compared entry. */ |
| 779 | if (r == 0) /* if no range passed, must be whole 32-bits |
| 780 | * so create 32-bit value from entry's range */ |
| 781 | { |
| 782 | eval = apply_range (e->value, e->range); |
| 783 | val &= apply_range (0xffffffff, e->range); |
| 784 | } |
| 785 | else if ((r->sbit == e->range.sbit && r->ebit == e->range.ebit) |
| 786 | || (e->range.sbit == 0 && e->range.ebit == 0)) |
| 787 | { |
| 788 | eval = apply_range (e->value, *r); |
| 789 | val = apply_range (val, *r); |
| 790 | } |
| 791 | else |
| 792 | continue; |
| 793 | if (val == eval) |
| 794 | return e; |
| 795 | } |
| 796 | return 0; |
| 797 | } |
| 798 | |
| 799 | /* Return a pointer to the list of entries for a given processor and type. */ |
| 800 | |
| 801 | static struct itbl_entry ** |
| 802 | get_entries (e_processor processor, e_type type) |
| 803 | { |
| 804 | return &entries[processor][type]; |
| 805 | } |
| 806 | |
| 807 | /* Return an integral value for the processor passed from yyparse. */ |
| 808 | |
| 809 | static e_processor |
| 810 | get_processor (int yyproc) |
| 811 | { |
| 812 | /* translate from yacc's processor to enum */ |
| 813 | if (yyproc >= e_p0 && yyproc < e_nprocs) |
| 814 | return (e_processor) yyproc; |
| 815 | return e_invproc; /* error; invalid processor */ |
| 816 | } |
| 817 | |
| 818 | /* Return an integral value for the entry type passed from yyparse. */ |
| 819 | |
| 820 | static e_type |
| 821 | get_type (int yytype) |
| 822 | { |
| 823 | switch (yytype) |
| 824 | { |
| 825 | /* translate from yacc's type to enum */ |
| 826 | case INSN: |
| 827 | return e_insn; |
| 828 | case DREG: |
| 829 | return e_dreg; |
| 830 | case CREG: |
| 831 | return e_creg; |
| 832 | case GREG: |
| 833 | return e_greg; |
| 834 | case ADDR: |
| 835 | return e_addr; |
| 836 | case IMMED: |
| 837 | return e_immed; |
| 838 | default: |
| 839 | return e_invtype; /* error; invalid type */ |
| 840 | } |
| 841 | } |
| 842 | |
| 843 | /* Allocate and initialize an entry */ |
| 844 | |
| 845 | static struct itbl_entry * |
| 846 | alloc_entry (e_processor processor, e_type type, |
| 847 | char *name, unsigned long value) |
| 848 | { |
| 849 | struct itbl_entry *e, **es; |
| 850 | if (!name) |
| 851 | return 0; |
| 852 | e = (struct itbl_entry *) malloc (sizeof (struct itbl_entry)); |
| 853 | if (e) |
| 854 | { |
| 855 | memset (e, 0, sizeof (struct itbl_entry)); |
| 856 | e->name = (char *) malloc (sizeof (strlen (name)) + 1); |
| 857 | if (e->name) |
| 858 | strcpy (e->name, name); |
| 859 | e->processor = processor; |
| 860 | e->type = type; |
| 861 | e->value = value; |
| 862 | es = get_entries (e->processor, e->type); |
| 863 | e->next = *es; |
| 864 | *es = e; |
| 865 | } |
| 866 | return e; |
| 867 | } |
| 868 | |
| 869 | /* Allocate and initialize an entry's field */ |
| 870 | |
| 871 | static struct itbl_field * |
| 872 | alloc_field (e_type type, int sbit, int ebit, |
| 873 | unsigned long flags) |
| 874 | { |
| 875 | struct itbl_field *f; |
| 876 | f = (struct itbl_field *) malloc (sizeof (struct itbl_field)); |
| 877 | if (f) |
| 878 | { |
| 879 | memset (f, 0, sizeof (struct itbl_field)); |
| 880 | f->type = type; |
| 881 | f->range.sbit = sbit; |
| 882 | f->range.ebit = ebit; |
| 883 | f->flags = flags; |
| 884 | } |
| 885 | return f; |
| 886 | } |