| 1 | #source: x86-64-cet.s |
| 2 | #objdump: -dw -Mintel |
| 3 | #name: x86-64 CET (Intel mode) |
| 4 | |
| 5 | .*: +file format .* |
| 6 | |
| 7 | Disassembly of section .text: |
| 8 | |
| 9 | 0+ <_start>: |
| 10 | +[a-f0-9]+: f3 41 0f ae ec incsspd r12d |
| 11 | +[a-f0-9]+: f3 48 0f ae e8 incsspq rax |
| 12 | +[a-f0-9]+: f3 41 0f 1e cc rdsspd r12d |
| 13 | +[a-f0-9]+: f3 48 0f 1e c8 rdsspq rax |
| 14 | +[a-f0-9]+: f3 0f 01 ea saveprevssp |
| 15 | +[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp QWORD PTR \[r12\] |
| 16 | +[a-f0-9]+: 41 0f 38 f6 04 24 wrssd \[r12\],eax |
| 17 | +[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq \[rcx\+r15\*1\],rdx |
| 18 | +[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd \[r12\],eax |
| 19 | +[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq \[rbx\+rax\*1\],rcx |
| 20 | +[a-f0-9]+: f3 0f 01 e8 setssbsy |
| 21 | +[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy QWORD PTR \[rsi\+r12\*1\] |
| 22 | +[a-f0-9]+: f3 0f 1e fa endbr64 |
| 23 | +[a-f0-9]+: f3 0f 1e fb endbr32 |
| 24 | +[a-f0-9]+: f3 41 0f ae ec incsspd r12d |
| 25 | +[a-f0-9]+: f3 48 0f ae e8 incsspq rax |
| 26 | +[a-f0-9]+: f3 41 0f 1e cc rdsspd r12d |
| 27 | +[a-f0-9]+: f3 48 0f 1e c8 rdsspq rax |
| 28 | +[a-f0-9]+: f3 0f 01 ea saveprevssp |
| 29 | +[a-f0-9]+: f3 41 0f 01 2c 24 rstorssp QWORD PTR \[r12\] |
| 30 | +[a-f0-9]+: 41 0f 38 f6 04 24 wrssd \[r12\],eax |
| 31 | +[a-f0-9]+: 4a 0f 38 f6 14 39 wrssq \[rcx\+r15\*1\],rdx |
| 32 | +[a-f0-9]+: 66 41 0f 38 f5 04 24 wrussd \[r12\],eax |
| 33 | +[a-f0-9]+: 66 48 0f 38 f5 0c 03 wrussq \[rbx\+rax\*1\],rcx |
| 34 | +[a-f0-9]+: f3 0f 01 e8 setssbsy |
| 35 | +[a-f0-9]+: f3 42 0f ae 34 26 clrssbsy QWORD PTR \[rsi\+r12\*1\] |
| 36 | +[a-f0-9]+: f3 0f 1e fa endbr64 |
| 37 | +[a-f0-9]+: f3 0f 1e fb endbr32 |
| 38 | #pass |