| 1 | /* Native-dependent code for GNU/Linux AArch64. |
| 2 | |
| 3 | Copyright (C) 2011-2014 Free Software Foundation, Inc. |
| 4 | Contributed by ARM Ltd. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 20 | |
| 21 | #include "defs.h" |
| 22 | |
| 23 | #include "inferior.h" |
| 24 | #include "gdbcore.h" |
| 25 | #include "regcache.h" |
| 26 | #include "linux-nat.h" |
| 27 | #include "target-descriptions.h" |
| 28 | #include "auxv.h" |
| 29 | #include "gdbcmd.h" |
| 30 | #include "aarch64-tdep.h" |
| 31 | #include "aarch64-linux-tdep.h" |
| 32 | #include "elf/common.h" |
| 33 | |
| 34 | #include <sys/ptrace.h> |
| 35 | #include <sys/utsname.h> |
| 36 | #include <asm/ptrace.h> |
| 37 | |
| 38 | #include "gregset.h" |
| 39 | |
| 40 | #include "features/aarch64.c" |
| 41 | |
| 42 | /* Defines ps_err_e, struct ps_prochandle. */ |
| 43 | #include "gdb_proc_service.h" |
| 44 | |
| 45 | #ifndef TRAP_HWBKPT |
| 46 | #define TRAP_HWBKPT 0x0004 |
| 47 | #endif |
| 48 | |
| 49 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which |
| 50 | case we may be tracing more than one process at a time. In that |
| 51 | case, inferior_ptid will contain the main process ID and the |
| 52 | individual thread (process) ID. get_thread_id () is used to get |
| 53 | the thread id if it's available, and the process id otherwise. */ |
| 54 | |
| 55 | static int |
| 56 | get_thread_id (ptid_t ptid) |
| 57 | { |
| 58 | int tid = ptid_get_lwp (ptid); |
| 59 | |
| 60 | if (0 == tid) |
| 61 | tid = ptid_get_pid (ptid); |
| 62 | return tid; |
| 63 | } |
| 64 | |
| 65 | /* Macro definitions, data structures, and code for the hardware |
| 66 | breakpoint and hardware watchpoint support follow. We use the |
| 67 | following abbreviations throughout the code: |
| 68 | |
| 69 | hw - hardware |
| 70 | bp - breakpoint |
| 71 | wp - watchpoint */ |
| 72 | |
| 73 | /* Maximum number of hardware breakpoint and watchpoint registers. |
| 74 | Neither of these values may exceed the width of dr_changed_t |
| 75 | measured in bits. */ |
| 76 | |
| 77 | #define AARCH64_HBP_MAX_NUM 16 |
| 78 | #define AARCH64_HWP_MAX_NUM 16 |
| 79 | |
| 80 | /* Alignment requirement in bytes for addresses written to |
| 81 | hardware breakpoint and watchpoint value registers. |
| 82 | |
| 83 | A ptrace call attempting to set an address that does not meet the |
| 84 | alignment criteria will fail. Limited support has been provided in |
| 85 | this port for unaligned watchpoints, such that from a GDB user |
| 86 | perspective, an unaligned watchpoint may be requested. |
| 87 | |
| 88 | This is achieved by minimally enlarging the watched area to meet the |
| 89 | alignment requirement, and if necessary, splitting the watchpoint |
| 90 | over several hardware watchpoint registers. */ |
| 91 | |
| 92 | #define AARCH64_HBP_ALIGNMENT 4 |
| 93 | #define AARCH64_HWP_ALIGNMENT 8 |
| 94 | |
| 95 | /* The maximum length of a memory region that can be watched by one |
| 96 | hardware watchpoint register. */ |
| 97 | |
| 98 | #define AARCH64_HWP_MAX_LEN_PER_REG 8 |
| 99 | |
| 100 | /* ptrace hardware breakpoint resource info is formatted as follows: |
| 101 | |
| 102 | 31 24 16 8 0 |
| 103 | +---------------+--------------+---------------+---------------+ |
| 104 | | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS | |
| 105 | +---------------+--------------+---------------+---------------+ */ |
| 106 | |
| 107 | |
| 108 | /* Macros to extract fields from the hardware debug information word. */ |
| 109 | #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff) |
| 110 | #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff) |
| 111 | |
| 112 | /* Macro for the expected version of the ARMv8-A debug architecture. */ |
| 113 | #define AARCH64_DEBUG_ARCH_V8 0x6 |
| 114 | |
| 115 | /* Number of hardware breakpoints/watchpoints the target supports. |
| 116 | They are initialized with values obtained via the ptrace calls |
| 117 | with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */ |
| 118 | |
| 119 | static int aarch64_num_bp_regs; |
| 120 | static int aarch64_num_wp_regs; |
| 121 | |
| 122 | /* Debugging of hardware breakpoint/watchpoint support. */ |
| 123 | |
| 124 | static int debug_hw_points; |
| 125 | |
| 126 | /* Each bit of a variable of this type is used to indicate whether a |
| 127 | hardware breakpoint or watchpoint setting has been changed since |
| 128 | the last update. |
| 129 | |
| 130 | Bit N corresponds to the Nth hardware breakpoint or watchpoint |
| 131 | setting which is managed in aarch64_debug_reg_state, where N is |
| 132 | valid between 0 and the total number of the hardware breakpoint or |
| 133 | watchpoint debug registers minus 1. |
| 134 | |
| 135 | When bit N is 1, the corresponding breakpoint or watchpoint setting |
| 136 | has changed, and therefore the corresponding hardware debug |
| 137 | register needs to be updated via the ptrace interface. |
| 138 | |
| 139 | In the per-thread arch-specific data area, we define two such |
| 140 | variables for per-thread hardware breakpoint and watchpoint |
| 141 | settings respectively. |
| 142 | |
| 143 | This type is part of the mechanism which helps reduce the number of |
| 144 | ptrace calls to the kernel, i.e. avoid asking the kernel to write |
| 145 | to the debug registers with unchanged values. */ |
| 146 | |
| 147 | typedef unsigned LONGEST dr_changed_t; |
| 148 | |
| 149 | /* Set each of the lower M bits of X to 1; assert X is wide enough. */ |
| 150 | |
| 151 | #define DR_MARK_ALL_CHANGED(x, m) \ |
| 152 | do \ |
| 153 | { \ |
| 154 | gdb_assert (sizeof ((x)) * 8 >= (m)); \ |
| 155 | (x) = (((dr_changed_t)1 << (m)) - 1); \ |
| 156 | } while (0) |
| 157 | |
| 158 | #define DR_MARK_N_CHANGED(x, n) \ |
| 159 | do \ |
| 160 | { \ |
| 161 | (x) |= ((dr_changed_t)1 << (n)); \ |
| 162 | } while (0) |
| 163 | |
| 164 | #define DR_CLEAR_CHANGED(x) \ |
| 165 | do \ |
| 166 | { \ |
| 167 | (x) = 0; \ |
| 168 | } while (0) |
| 169 | |
| 170 | #define DR_HAS_CHANGED(x) ((x) != 0) |
| 171 | #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n))) |
| 172 | |
| 173 | /* Structure for managing the hardware breakpoint/watchpoint resources. |
| 174 | DR_ADDR_* stores the address, DR_CTRL_* stores the control register |
| 175 | content, and DR_REF_COUNT_* counts the numbers of references to the |
| 176 | corresponding bp/wp, by which way the limited hardware resources |
| 177 | are not wasted on duplicated bp/wp settings (though so far gdb has |
| 178 | done a good job by not sending duplicated bp/wp requests). */ |
| 179 | |
| 180 | struct aarch64_debug_reg_state |
| 181 | { |
| 182 | /* hardware breakpoint */ |
| 183 | CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]; |
| 184 | unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]; |
| 185 | unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]; |
| 186 | |
| 187 | /* hardware watchpoint */ |
| 188 | CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]; |
| 189 | unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]; |
| 190 | unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]; |
| 191 | }; |
| 192 | |
| 193 | /* Per-process data. We don't bind this to a per-inferior registry |
| 194 | because of targets like x86 GNU/Linux that need to keep track of |
| 195 | processes that aren't bound to any inferior (e.g., fork children, |
| 196 | checkpoints). */ |
| 197 | |
| 198 | struct aarch64_process_info |
| 199 | { |
| 200 | /* Linked list. */ |
| 201 | struct aarch64_process_info *next; |
| 202 | |
| 203 | /* The process identifier. */ |
| 204 | pid_t pid; |
| 205 | |
| 206 | /* Copy of aarch64 hardware debug registers. */ |
| 207 | struct aarch64_debug_reg_state state; |
| 208 | }; |
| 209 | |
| 210 | static struct aarch64_process_info *aarch64_process_list = NULL; |
| 211 | |
| 212 | /* Find process data for process PID. */ |
| 213 | |
| 214 | static struct aarch64_process_info * |
| 215 | aarch64_find_process_pid (pid_t pid) |
| 216 | { |
| 217 | struct aarch64_process_info *proc; |
| 218 | |
| 219 | for (proc = aarch64_process_list; proc; proc = proc->next) |
| 220 | if (proc->pid == pid) |
| 221 | return proc; |
| 222 | |
| 223 | return NULL; |
| 224 | } |
| 225 | |
| 226 | /* Add process data for process PID. Returns newly allocated info |
| 227 | object. */ |
| 228 | |
| 229 | static struct aarch64_process_info * |
| 230 | aarch64_add_process (pid_t pid) |
| 231 | { |
| 232 | struct aarch64_process_info *proc; |
| 233 | |
| 234 | proc = xcalloc (1, sizeof (*proc)); |
| 235 | proc->pid = pid; |
| 236 | |
| 237 | proc->next = aarch64_process_list; |
| 238 | aarch64_process_list = proc; |
| 239 | |
| 240 | return proc; |
| 241 | } |
| 242 | |
| 243 | /* Get data specific info for process PID, creating it if necessary. |
| 244 | Never returns NULL. */ |
| 245 | |
| 246 | static struct aarch64_process_info * |
| 247 | aarch64_process_info_get (pid_t pid) |
| 248 | { |
| 249 | struct aarch64_process_info *proc; |
| 250 | |
| 251 | proc = aarch64_find_process_pid (pid); |
| 252 | if (proc == NULL) |
| 253 | proc = aarch64_add_process (pid); |
| 254 | |
| 255 | return proc; |
| 256 | } |
| 257 | |
| 258 | /* Called whenever GDB is no longer debugging process PID. It deletes |
| 259 | data structures that keep track of debug register state. */ |
| 260 | |
| 261 | static void |
| 262 | aarch64_forget_process (pid_t pid) |
| 263 | { |
| 264 | struct aarch64_process_info *proc, **proc_link; |
| 265 | |
| 266 | proc = aarch64_process_list; |
| 267 | proc_link = &aarch64_process_list; |
| 268 | |
| 269 | while (proc != NULL) |
| 270 | { |
| 271 | if (proc->pid == pid) |
| 272 | { |
| 273 | *proc_link = proc->next; |
| 274 | |
| 275 | xfree (proc); |
| 276 | return; |
| 277 | } |
| 278 | |
| 279 | proc_link = &proc->next; |
| 280 | proc = *proc_link; |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | /* Get debug registers state for process PID. */ |
| 285 | |
| 286 | static struct aarch64_debug_reg_state * |
| 287 | aarch64_get_debug_reg_state (pid_t pid) |
| 288 | { |
| 289 | return &aarch64_process_info_get (pid)->state; |
| 290 | } |
| 291 | |
| 292 | /* Per-thread arch-specific data we want to keep. */ |
| 293 | |
| 294 | struct arch_lwp_info |
| 295 | { |
| 296 | /* When bit N is 1, it indicates the Nth hardware breakpoint or |
| 297 | watchpoint register pair needs to be updated when the thread is |
| 298 | resumed; see aarch64_linux_prepare_to_resume. */ |
| 299 | dr_changed_t dr_changed_bp; |
| 300 | dr_changed_t dr_changed_wp; |
| 301 | }; |
| 302 | |
| 303 | /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint |
| 304 | registers with data from *STATE. */ |
| 305 | |
| 306 | static void |
| 307 | aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state, |
| 308 | int tid, int watchpoint) |
| 309 | { |
| 310 | int i, count; |
| 311 | struct iovec iov; |
| 312 | struct user_hwdebug_state regs; |
| 313 | const CORE_ADDR *addr; |
| 314 | const unsigned int *ctrl; |
| 315 | |
| 316 | memset (®s, 0, sizeof (regs)); |
| 317 | iov.iov_base = ®s; |
| 318 | count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs; |
| 319 | addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; |
| 320 | ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; |
| 321 | if (count == 0) |
| 322 | return; |
| 323 | iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1]) |
| 324 | + sizeof (regs.dbg_regs [count - 1])); |
| 325 | |
| 326 | for (i = 0; i < count; i++) |
| 327 | { |
| 328 | regs.dbg_regs[i].addr = addr[i]; |
| 329 | regs.dbg_regs[i].ctrl = ctrl[i]; |
| 330 | } |
| 331 | |
| 332 | if (ptrace (PTRACE_SETREGSET, tid, |
| 333 | watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK, |
| 334 | (void *) &iov)) |
| 335 | error (_("Unexpected error setting hardware debug registers")); |
| 336 | } |
| 337 | |
| 338 | struct aarch64_dr_update_callback_param |
| 339 | { |
| 340 | int is_watchpoint; |
| 341 | unsigned int idx; |
| 342 | }; |
| 343 | |
| 344 | /* Callback for iterate_over_lwps. Records the |
| 345 | information about the change of one hardware breakpoint/watchpoint |
| 346 | setting for the thread LWP. |
| 347 | The information is passed in via PTR. |
| 348 | N.B. The actual updating of hardware debug registers is not |
| 349 | carried out until the moment the thread is resumed. */ |
| 350 | |
| 351 | static int |
| 352 | debug_reg_change_callback (struct lwp_info *lwp, void *ptr) |
| 353 | { |
| 354 | struct aarch64_dr_update_callback_param *param_p |
| 355 | = (struct aarch64_dr_update_callback_param *) ptr; |
| 356 | int pid = get_thread_id (lwp->ptid); |
| 357 | int idx = param_p->idx; |
| 358 | int is_watchpoint = param_p->is_watchpoint; |
| 359 | struct arch_lwp_info *info = lwp->arch_private; |
| 360 | dr_changed_t *dr_changed_ptr; |
| 361 | dr_changed_t dr_changed; |
| 362 | |
| 363 | if (info == NULL) |
| 364 | info = lwp->arch_private = XCNEW (struct arch_lwp_info); |
| 365 | |
| 366 | if (debug_hw_points) |
| 367 | { |
| 368 | fprintf_unfiltered (gdb_stdlog, |
| 369 | "debug_reg_change_callback: \n\tOn entry:\n"); |
| 370 | fprintf_unfiltered (gdb_stdlog, |
| 371 | "\tpid%d, dr_changed_bp=0x%s, " |
| 372 | "dr_changed_wp=0x%s\n", |
| 373 | pid, phex (info->dr_changed_bp, 8), |
| 374 | phex (info->dr_changed_wp, 8)); |
| 375 | } |
| 376 | |
| 377 | dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp |
| 378 | : &info->dr_changed_bp; |
| 379 | dr_changed = *dr_changed_ptr; |
| 380 | |
| 381 | gdb_assert (idx >= 0 |
| 382 | && (idx <= (is_watchpoint ? aarch64_num_wp_regs |
| 383 | : aarch64_num_bp_regs))); |
| 384 | |
| 385 | /* The actual update is done later just before resuming the lwp, |
| 386 | we just mark that one register pair needs updating. */ |
| 387 | DR_MARK_N_CHANGED (dr_changed, idx); |
| 388 | *dr_changed_ptr = dr_changed; |
| 389 | |
| 390 | /* If the lwp isn't stopped, force it to momentarily pause, so |
| 391 | we can update its debug registers. */ |
| 392 | if (!lwp->stopped) |
| 393 | linux_stop_lwp (lwp); |
| 394 | |
| 395 | if (debug_hw_points) |
| 396 | { |
| 397 | fprintf_unfiltered (gdb_stdlog, |
| 398 | "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, " |
| 399 | "dr_changed_wp=0x%s\n", |
| 400 | pid, phex (info->dr_changed_bp, 8), |
| 401 | phex (info->dr_changed_wp, 8)); |
| 402 | } |
| 403 | |
| 404 | /* Continue the iteration. */ |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | /* Notify each thread that their IDXth breakpoint/watchpoint register |
| 409 | pair needs to be updated. The message will be recorded in each |
| 410 | thread's arch-specific data area, the actual updating will be done |
| 411 | when the thread is resumed. */ |
| 412 | |
| 413 | static void |
| 414 | aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state, |
| 415 | int is_watchpoint, unsigned int idx) |
| 416 | { |
| 417 | struct aarch64_dr_update_callback_param param; |
| 418 | ptid_t pid_ptid = pid_to_ptid (ptid_get_pid (inferior_ptid)); |
| 419 | |
| 420 | param.is_watchpoint = is_watchpoint; |
| 421 | param.idx = idx; |
| 422 | |
| 423 | iterate_over_lwps (pid_ptid, debug_reg_change_callback, (void *) ¶m); |
| 424 | } |
| 425 | |
| 426 | /* Print the values of the cached breakpoint/watchpoint registers. */ |
| 427 | |
| 428 | static void |
| 429 | aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state, |
| 430 | const char *func, CORE_ADDR addr, |
| 431 | int len, int type) |
| 432 | { |
| 433 | int i; |
| 434 | |
| 435 | fprintf_unfiltered (gdb_stdlog, "%s", func); |
| 436 | if (addr || len) |
| 437 | fprintf_unfiltered (gdb_stdlog, " (addr=0x%08lx, len=%d, type=%s)", |
| 438 | (unsigned long) addr, len, |
| 439 | type == hw_write ? "hw-write-watchpoint" |
| 440 | : (type == hw_read ? "hw-read-watchpoint" |
| 441 | : (type == hw_access ? "hw-access-watchpoint" |
| 442 | : (type == hw_execute ? "hw-breakpoint" |
| 443 | : "??unknown??")))); |
| 444 | fprintf_unfiltered (gdb_stdlog, ":\n"); |
| 445 | |
| 446 | fprintf_unfiltered (gdb_stdlog, "\tBREAKPOINTs:\n"); |
| 447 | for (i = 0; i < aarch64_num_bp_regs; i++) |
| 448 | fprintf_unfiltered (gdb_stdlog, |
| 449 | "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", |
| 450 | i, state->dr_addr_bp[i], |
| 451 | state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]); |
| 452 | |
| 453 | fprintf_unfiltered (gdb_stdlog, "\tWATCHPOINTs:\n"); |
| 454 | for (i = 0; i < aarch64_num_wp_regs; i++) |
| 455 | fprintf_unfiltered (gdb_stdlog, |
| 456 | "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", |
| 457 | i, state->dr_addr_wp[i], |
| 458 | state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]); |
| 459 | } |
| 460 | |
| 461 | /* Fill GDB's register array with the general-purpose register values |
| 462 | from the current thread. */ |
| 463 | |
| 464 | static void |
| 465 | fetch_gregs_from_thread (struct regcache *regcache) |
| 466 | { |
| 467 | int ret, regno, tid; |
| 468 | elf_gregset_t regs; |
| 469 | struct iovec iovec; |
| 470 | |
| 471 | tid = get_thread_id (inferior_ptid); |
| 472 | |
| 473 | iovec.iov_base = ®s; |
| 474 | iovec.iov_len = sizeof (regs); |
| 475 | |
| 476 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); |
| 477 | if (ret < 0) |
| 478 | perror_with_name (_("Unable to fetch general registers.")); |
| 479 | |
| 480 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) |
| 481 | regcache_raw_supply (regcache, regno, |
| 482 | (char *) ®s[regno - AARCH64_X0_REGNUM]); |
| 483 | } |
| 484 | |
| 485 | /* Store to the current thread the valid general-purpose register |
| 486 | values in the GDB's register array. */ |
| 487 | |
| 488 | static void |
| 489 | store_gregs_to_thread (const struct regcache *regcache) |
| 490 | { |
| 491 | int ret, regno, tid; |
| 492 | elf_gregset_t regs; |
| 493 | struct iovec iovec; |
| 494 | |
| 495 | tid = get_thread_id (inferior_ptid); |
| 496 | |
| 497 | iovec.iov_base = ®s; |
| 498 | iovec.iov_len = sizeof (regs); |
| 499 | |
| 500 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); |
| 501 | if (ret < 0) |
| 502 | perror_with_name (_("Unable to fetch general registers.")); |
| 503 | |
| 504 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) |
| 505 | if (REG_VALID == regcache_register_status (regcache, regno)) |
| 506 | regcache_raw_collect (regcache, regno, |
| 507 | (char *) ®s[regno - AARCH64_X0_REGNUM]); |
| 508 | |
| 509 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); |
| 510 | if (ret < 0) |
| 511 | perror_with_name (_("Unable to store general registers.")); |
| 512 | } |
| 513 | |
| 514 | /* Fill GDB's register array with the fp/simd register values |
| 515 | from the current thread. */ |
| 516 | |
| 517 | static void |
| 518 | fetch_fpregs_from_thread (struct regcache *regcache) |
| 519 | { |
| 520 | int ret, regno, tid; |
| 521 | elf_fpregset_t regs; |
| 522 | struct iovec iovec; |
| 523 | |
| 524 | tid = get_thread_id (inferior_ptid); |
| 525 | |
| 526 | iovec.iov_base = ®s; |
| 527 | iovec.iov_len = sizeof (regs); |
| 528 | |
| 529 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); |
| 530 | if (ret < 0) |
| 531 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); |
| 532 | |
| 533 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) |
| 534 | regcache_raw_supply (regcache, regno, |
| 535 | (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); |
| 536 | |
| 537 | regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); |
| 538 | regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); |
| 539 | } |
| 540 | |
| 541 | /* Store to the current thread the valid fp/simd register |
| 542 | values in the GDB's register array. */ |
| 543 | |
| 544 | static void |
| 545 | store_fpregs_to_thread (const struct regcache *regcache) |
| 546 | { |
| 547 | int ret, regno, tid; |
| 548 | elf_fpregset_t regs; |
| 549 | struct iovec iovec; |
| 550 | |
| 551 | tid = get_thread_id (inferior_ptid); |
| 552 | |
| 553 | iovec.iov_base = ®s; |
| 554 | iovec.iov_len = sizeof (regs); |
| 555 | |
| 556 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); |
| 557 | if (ret < 0) |
| 558 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); |
| 559 | |
| 560 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) |
| 561 | if (REG_VALID == regcache_register_status (regcache, regno)) |
| 562 | regcache_raw_collect (regcache, regno, |
| 563 | (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); |
| 564 | |
| 565 | if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM)) |
| 566 | regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); |
| 567 | if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM)) |
| 568 | regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); |
| 569 | |
| 570 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); |
| 571 | if (ret < 0) |
| 572 | perror_with_name (_("Unable to store FP/SIMD registers.")); |
| 573 | } |
| 574 | |
| 575 | /* Implement the "to_fetch_register" target_ops method. */ |
| 576 | |
| 577 | static void |
| 578 | aarch64_linux_fetch_inferior_registers (struct target_ops *ops, |
| 579 | struct regcache *regcache, |
| 580 | int regno) |
| 581 | { |
| 582 | if (regno == -1) |
| 583 | { |
| 584 | fetch_gregs_from_thread (regcache); |
| 585 | fetch_fpregs_from_thread (regcache); |
| 586 | } |
| 587 | else if (regno < AARCH64_V0_REGNUM) |
| 588 | fetch_gregs_from_thread (regcache); |
| 589 | else |
| 590 | fetch_fpregs_from_thread (regcache); |
| 591 | } |
| 592 | |
| 593 | /* Implement the "to_store_register" target_ops method. */ |
| 594 | |
| 595 | static void |
| 596 | aarch64_linux_store_inferior_registers (struct target_ops *ops, |
| 597 | struct regcache *regcache, |
| 598 | int regno) |
| 599 | { |
| 600 | if (regno == -1) |
| 601 | { |
| 602 | store_gregs_to_thread (regcache); |
| 603 | store_fpregs_to_thread (regcache); |
| 604 | } |
| 605 | else if (regno < AARCH64_V0_REGNUM) |
| 606 | store_gregs_to_thread (regcache); |
| 607 | else |
| 608 | store_fpregs_to_thread (regcache); |
| 609 | } |
| 610 | |
| 611 | /* Fill register REGNO (if it is a general-purpose register) in |
| 612 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, |
| 613 | do this for all registers. */ |
| 614 | |
| 615 | void |
| 616 | fill_gregset (const struct regcache *regcache, |
| 617 | gdb_gregset_t *gregsetp, int regno) |
| 618 | { |
| 619 | regcache_collect_regset (&aarch64_linux_gregset, regcache, |
| 620 | regno, (gdb_byte *) gregsetp, |
| 621 | AARCH64_LINUX_SIZEOF_GREGSET); |
| 622 | } |
| 623 | |
| 624 | /* Fill GDB's register array with the general-purpose register values |
| 625 | in *GREGSETP. */ |
| 626 | |
| 627 | void |
| 628 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
| 629 | { |
| 630 | regcache_supply_regset (&aarch64_linux_gregset, regcache, -1, |
| 631 | (const gdb_byte *) gregsetp, |
| 632 | AARCH64_LINUX_SIZEOF_GREGSET); |
| 633 | } |
| 634 | |
| 635 | /* Fill register REGNO (if it is a floating-point register) in |
| 636 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, |
| 637 | do this for all registers. */ |
| 638 | |
| 639 | void |
| 640 | fill_fpregset (const struct regcache *regcache, |
| 641 | gdb_fpregset_t *fpregsetp, int regno) |
| 642 | { |
| 643 | regcache_collect_regset (&aarch64_linux_fpregset, regcache, |
| 644 | regno, (gdb_byte *) fpregsetp, |
| 645 | AARCH64_LINUX_SIZEOF_FPREGSET); |
| 646 | } |
| 647 | |
| 648 | /* Fill GDB's register array with the floating-point register values |
| 649 | in *FPREGSETP. */ |
| 650 | |
| 651 | void |
| 652 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
| 653 | { |
| 654 | regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1, |
| 655 | (const gdb_byte *) fpregsetp, |
| 656 | AARCH64_LINUX_SIZEOF_FPREGSET); |
| 657 | } |
| 658 | |
| 659 | /* Called when resuming a thread. |
| 660 | The hardware debug registers are updated when there is any change. */ |
| 661 | |
| 662 | static void |
| 663 | aarch64_linux_prepare_to_resume (struct lwp_info *lwp) |
| 664 | { |
| 665 | struct arch_lwp_info *info = lwp->arch_private; |
| 666 | |
| 667 | /* NULL means this is the main thread still going through the shell, |
| 668 | or, no watchpoint has been set yet. In that case, there's |
| 669 | nothing to do. */ |
| 670 | if (info == NULL) |
| 671 | return; |
| 672 | |
| 673 | if (DR_HAS_CHANGED (info->dr_changed_bp) |
| 674 | || DR_HAS_CHANGED (info->dr_changed_wp)) |
| 675 | { |
| 676 | int tid = ptid_get_lwp (lwp->ptid); |
| 677 | struct aarch64_debug_reg_state *state |
| 678 | = aarch64_get_debug_reg_state (ptid_get_pid (lwp->ptid)); |
| 679 | |
| 680 | if (debug_hw_points) |
| 681 | fprintf_unfiltered (gdb_stdlog, "prepare_to_resume thread %d\n", tid); |
| 682 | |
| 683 | /* Watchpoints. */ |
| 684 | if (DR_HAS_CHANGED (info->dr_changed_wp)) |
| 685 | { |
| 686 | aarch64_linux_set_debug_regs (state, tid, 1); |
| 687 | DR_CLEAR_CHANGED (info->dr_changed_wp); |
| 688 | } |
| 689 | |
| 690 | /* Breakpoints. */ |
| 691 | if (DR_HAS_CHANGED (info->dr_changed_bp)) |
| 692 | { |
| 693 | aarch64_linux_set_debug_regs (state, tid, 0); |
| 694 | DR_CLEAR_CHANGED (info->dr_changed_bp); |
| 695 | } |
| 696 | } |
| 697 | } |
| 698 | |
| 699 | static void |
| 700 | aarch64_linux_new_thread (struct lwp_info *lp) |
| 701 | { |
| 702 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
| 703 | |
| 704 | /* Mark that all the hardware breakpoint/watchpoint register pairs |
| 705 | for this thread need to be initialized. */ |
| 706 | DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs); |
| 707 | DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs); |
| 708 | |
| 709 | lp->arch_private = info; |
| 710 | } |
| 711 | |
| 712 | /* linux_nat_new_fork hook. */ |
| 713 | |
| 714 | static void |
| 715 | aarch64_linux_new_fork (struct lwp_info *parent, pid_t child_pid) |
| 716 | { |
| 717 | pid_t parent_pid; |
| 718 | struct aarch64_debug_reg_state *parent_state; |
| 719 | struct aarch64_debug_reg_state *child_state; |
| 720 | |
| 721 | /* NULL means no watchpoint has ever been set in the parent. In |
| 722 | that case, there's nothing to do. */ |
| 723 | if (parent->arch_private == NULL) |
| 724 | return; |
| 725 | |
| 726 | /* GDB core assumes the child inherits the watchpoints/hw |
| 727 | breakpoints of the parent, and will remove them all from the |
| 728 | forked off process. Copy the debug registers mirrors into the |
| 729 | new process so that all breakpoints and watchpoints can be |
| 730 | removed together. */ |
| 731 | |
| 732 | parent_pid = ptid_get_pid (parent->ptid); |
| 733 | parent_state = aarch64_get_debug_reg_state (parent_pid); |
| 734 | child_state = aarch64_get_debug_reg_state (child_pid); |
| 735 | *child_state = *parent_state; |
| 736 | } |
| 737 | \f |
| 738 | |
| 739 | /* Called by libthread_db. Returns a pointer to the thread local |
| 740 | storage (or its descriptor). */ |
| 741 | |
| 742 | ps_err_e |
| 743 | ps_get_thread_area (const struct ps_prochandle *ph, |
| 744 | lwpid_t lwpid, int idx, void **base) |
| 745 | { |
| 746 | struct iovec iovec; |
| 747 | uint64_t reg; |
| 748 | |
| 749 | iovec.iov_base = ® |
| 750 | iovec.iov_len = sizeof (reg); |
| 751 | |
| 752 | if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) |
| 753 | return PS_ERR; |
| 754 | |
| 755 | /* IDX is the bias from the thread pointer to the beginning of the |
| 756 | thread descriptor. It has to be subtracted due to implementation |
| 757 | quirks in libthread_db. */ |
| 758 | *base = (void *) (reg - idx); |
| 759 | |
| 760 | return PS_OK; |
| 761 | } |
| 762 | \f |
| 763 | |
| 764 | /* Get the hardware debug register capacity information. */ |
| 765 | |
| 766 | static void |
| 767 | aarch64_linux_get_debug_reg_capacity (void) |
| 768 | { |
| 769 | int tid; |
| 770 | struct iovec iov; |
| 771 | struct user_hwdebug_state dreg_state; |
| 772 | |
| 773 | tid = get_thread_id (inferior_ptid); |
| 774 | iov.iov_base = &dreg_state; |
| 775 | iov.iov_len = sizeof (dreg_state); |
| 776 | |
| 777 | /* Get hardware watchpoint register info. */ |
| 778 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0 |
| 779 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) |
| 780 | { |
| 781 | aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); |
| 782 | if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM) |
| 783 | { |
| 784 | warning (_("Unexpected number of hardware watchpoint registers" |
| 785 | " reported by ptrace, got %d, expected %d."), |
| 786 | aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM); |
| 787 | aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM; |
| 788 | } |
| 789 | } |
| 790 | else |
| 791 | { |
| 792 | warning (_("Unable to determine the number of hardware watchpoints" |
| 793 | " available.")); |
| 794 | aarch64_num_wp_regs = 0; |
| 795 | } |
| 796 | |
| 797 | /* Get hardware breakpoint register info. */ |
| 798 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0 |
| 799 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) |
| 800 | { |
| 801 | aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); |
| 802 | if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM) |
| 803 | { |
| 804 | warning (_("Unexpected number of hardware breakpoint registers" |
| 805 | " reported by ptrace, got %d, expected %d."), |
| 806 | aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM); |
| 807 | aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM; |
| 808 | } |
| 809 | } |
| 810 | else |
| 811 | { |
| 812 | warning (_("Unable to determine the number of hardware breakpoints" |
| 813 | " available.")); |
| 814 | aarch64_num_bp_regs = 0; |
| 815 | } |
| 816 | } |
| 817 | |
| 818 | static void (*super_post_startup_inferior) (struct target_ops *self, |
| 819 | ptid_t ptid); |
| 820 | |
| 821 | /* Implement the "to_post_startup_inferior" target_ops method. */ |
| 822 | |
| 823 | static void |
| 824 | aarch64_linux_child_post_startup_inferior (struct target_ops *self, |
| 825 | ptid_t ptid) |
| 826 | { |
| 827 | aarch64_forget_process (ptid_get_pid (ptid)); |
| 828 | aarch64_linux_get_debug_reg_capacity (); |
| 829 | super_post_startup_inferior (self, ptid); |
| 830 | } |
| 831 | |
| 832 | /* Implement the "to_read_description" target_ops method. */ |
| 833 | |
| 834 | static const struct target_desc * |
| 835 | aarch64_linux_read_description (struct target_ops *ops) |
| 836 | { |
| 837 | initialize_tdesc_aarch64 (); |
| 838 | return tdesc_aarch64; |
| 839 | } |
| 840 | |
| 841 | /* Given the (potentially unaligned) watchpoint address in ADDR and |
| 842 | length in LEN, return the aligned address and aligned length in |
| 843 | *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned |
| 844 | aligned address and length will be valid values to write to the |
| 845 | hardware watchpoint value and control registers. |
| 846 | |
| 847 | The given watchpoint may get truncated if more than one hardware |
| 848 | register is needed to cover the watched region. *NEXT_ADDR_P |
| 849 | and *NEXT_LEN_P, if non-NULL, will return the address and length |
| 850 | of the remaining part of the watchpoint (which can be processed |
| 851 | by calling this routine again to generate another aligned address |
| 852 | and length pair. |
| 853 | |
| 854 | See the comment above the function of the same name in |
| 855 | gdbserver/linux-aarch64-low.c for more information. */ |
| 856 | |
| 857 | static void |
| 858 | aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, |
| 859 | int *aligned_len_p, CORE_ADDR *next_addr_p, |
| 860 | int *next_len_p) |
| 861 | { |
| 862 | int aligned_len; |
| 863 | unsigned int offset; |
| 864 | CORE_ADDR aligned_addr; |
| 865 | const unsigned int alignment = AARCH64_HWP_ALIGNMENT; |
| 866 | const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG; |
| 867 | |
| 868 | /* As assumed by the algorithm. */ |
| 869 | gdb_assert (alignment == max_wp_len); |
| 870 | |
| 871 | if (len <= 0) |
| 872 | return; |
| 873 | |
| 874 | /* Address to be put into the hardware watchpoint value register |
| 875 | must be aligned. */ |
| 876 | offset = addr & (alignment - 1); |
| 877 | aligned_addr = addr - offset; |
| 878 | |
| 879 | gdb_assert (offset >= 0 && offset < alignment); |
| 880 | gdb_assert (aligned_addr >= 0 && aligned_addr <= addr); |
| 881 | gdb_assert (offset + len > 0); |
| 882 | |
| 883 | if (offset + len >= max_wp_len) |
| 884 | { |
| 885 | /* Need more than one watchpoint registers; truncate it at the |
| 886 | alignment boundary. */ |
| 887 | aligned_len = max_wp_len; |
| 888 | len -= (max_wp_len - offset); |
| 889 | addr += (max_wp_len - offset); |
| 890 | gdb_assert ((addr & (alignment - 1)) == 0); |
| 891 | } |
| 892 | else |
| 893 | { |
| 894 | /* Find the smallest valid length that is large enough to |
| 895 | accommodate this watchpoint. */ |
| 896 | static const unsigned char |
| 897 | aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] = |
| 898 | { 1, 2, 4, 4, 8, 8, 8, 8 }; |
| 899 | |
| 900 | aligned_len = aligned_len_array[offset + len - 1]; |
| 901 | addr += len; |
| 902 | len = 0; |
| 903 | } |
| 904 | |
| 905 | if (aligned_addr_p) |
| 906 | *aligned_addr_p = aligned_addr; |
| 907 | if (aligned_len_p) |
| 908 | *aligned_len_p = aligned_len; |
| 909 | if (next_addr_p) |
| 910 | *next_addr_p = addr; |
| 911 | if (next_len_p) |
| 912 | *next_len_p = len; |
| 913 | } |
| 914 | |
| 915 | /* Returns the number of hardware watchpoints of type TYPE that we can |
| 916 | set. Value is positive if we can set CNT watchpoints, zero if |
| 917 | setting watchpoints of type TYPE is not supported, and negative if |
| 918 | CNT is more than the maximum number of watchpoints of type TYPE |
| 919 | that we can support. TYPE is one of bp_hardware_watchpoint, |
| 920 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. |
| 921 | CNT is the number of such watchpoints used so far (including this |
| 922 | one). OTHERTYPE is non-zero if other types of watchpoints are |
| 923 | currently enabled. |
| 924 | |
| 925 | We always return 1 here because we don't have enough information |
| 926 | about possible overlap of addresses that they want to watch. As an |
| 927 | extreme example, consider the case where all the watchpoints watch |
| 928 | the same address and the same region length: then we can handle a |
| 929 | virtually unlimited number of watchpoints, due to debug register |
| 930 | sharing implemented via reference counts. */ |
| 931 | |
| 932 | static int |
| 933 | aarch64_linux_can_use_hw_breakpoint (struct target_ops *self, |
| 934 | int type, int cnt, int othertype) |
| 935 | { |
| 936 | return 1; |
| 937 | } |
| 938 | |
| 939 | /* ptrace expects control registers to be formatted as follows: |
| 940 | |
| 941 | 31 13 5 3 1 0 |
| 942 | +--------------------------------+----------+------+------+----+ |
| 943 | | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN | |
| 944 | +--------------------------------+----------+------+------+----+ |
| 945 | |
| 946 | The TYPE field is ignored for breakpoints. */ |
| 947 | |
| 948 | #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1) |
| 949 | #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff) |
| 950 | |
| 951 | /* Utility function that returns the length in bytes of a watchpoint |
| 952 | according to the content of a hardware debug control register CTRL. |
| 953 | Note that the kernel currently only supports the following Byte |
| 954 | Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means |
| 955 | that for a hardware watchpoint, its valid length can only be 1 |
| 956 | byte, 2 bytes, 4 bytes or 8 bytes. */ |
| 957 | |
| 958 | static inline unsigned int |
| 959 | aarch64_watchpoint_length (unsigned int ctrl) |
| 960 | { |
| 961 | switch (DR_CONTROL_LENGTH (ctrl)) |
| 962 | { |
| 963 | case 0x01: |
| 964 | return 1; |
| 965 | case 0x03: |
| 966 | return 2; |
| 967 | case 0x0f: |
| 968 | return 4; |
| 969 | case 0xff: |
| 970 | return 8; |
| 971 | default: |
| 972 | return 0; |
| 973 | } |
| 974 | } |
| 975 | |
| 976 | /* Given the hardware breakpoint or watchpoint type TYPE and its |
| 977 | length LEN, return the expected encoding for a hardware |
| 978 | breakpoint/watchpoint control register. */ |
| 979 | |
| 980 | static unsigned int |
| 981 | aarch64_point_encode_ctrl_reg (int type, int len) |
| 982 | { |
| 983 | unsigned int ctrl, ttype; |
| 984 | |
| 985 | /* type */ |
| 986 | switch (type) |
| 987 | { |
| 988 | case hw_write: |
| 989 | ttype = 2; |
| 990 | break; |
| 991 | case hw_read: |
| 992 | ttype = 1; |
| 993 | break; |
| 994 | case hw_access: |
| 995 | ttype = 3; |
| 996 | break; |
| 997 | case hw_execute: |
| 998 | ttype = 0; |
| 999 | break; |
| 1000 | default: |
| 1001 | perror_with_name (_("Unrecognized breakpoint/watchpoint type")); |
| 1002 | } |
| 1003 | ctrl = ttype << 3; |
| 1004 | |
| 1005 | /* length bitmask */ |
| 1006 | ctrl |= ((1 << len) - 1) << 5; |
| 1007 | /* enabled at el0 */ |
| 1008 | ctrl |= (2 << 1) | 1; |
| 1009 | |
| 1010 | return ctrl; |
| 1011 | } |
| 1012 | |
| 1013 | /* Addresses to be written to the hardware breakpoint and watchpoint |
| 1014 | value registers need to be aligned; the alignment is 4-byte and |
| 1015 | 8-type respectively. Linux kernel rejects any non-aligned address |
| 1016 | it receives from the related ptrace call. Furthermore, the kernel |
| 1017 | currently only supports the following Byte Address Select (BAS) |
| 1018 | values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware |
| 1019 | watchpoint to be accepted by the kernel (via ptrace call), its |
| 1020 | valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes. |
| 1021 | Despite these limitations, the unaligned watchpoint is supported in |
| 1022 | this port. |
| 1023 | |
| 1024 | Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */ |
| 1025 | |
| 1026 | static int |
| 1027 | aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) |
| 1028 | { |
| 1029 | unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT |
| 1030 | : AARCH64_HBP_ALIGNMENT; |
| 1031 | |
| 1032 | if (addr & (alignment - 1)) |
| 1033 | return 0; |
| 1034 | |
| 1035 | if (len != 8 && len != 4 && len != 2 && len != 1) |
| 1036 | return 0; |
| 1037 | |
| 1038 | return 1; |
| 1039 | } |
| 1040 | |
| 1041 | /* Record the insertion of one breakpoint/watchpoint, as represented |
| 1042 | by ADDR and CTRL, in the cached debug register state area *STATE. */ |
| 1043 | |
| 1044 | static int |
| 1045 | aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state, |
| 1046 | int type, CORE_ADDR addr, int len) |
| 1047 | { |
| 1048 | int i, idx, num_regs, is_watchpoint; |
| 1049 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; |
| 1050 | CORE_ADDR *dr_addr_p; |
| 1051 | |
| 1052 | /* Set up state pointers. */ |
| 1053 | is_watchpoint = (type != hw_execute); |
| 1054 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); |
| 1055 | if (is_watchpoint) |
| 1056 | { |
| 1057 | num_regs = aarch64_num_wp_regs; |
| 1058 | dr_addr_p = state->dr_addr_wp; |
| 1059 | dr_ctrl_p = state->dr_ctrl_wp; |
| 1060 | dr_ref_count = state->dr_ref_count_wp; |
| 1061 | } |
| 1062 | else |
| 1063 | { |
| 1064 | num_regs = aarch64_num_bp_regs; |
| 1065 | dr_addr_p = state->dr_addr_bp; |
| 1066 | dr_ctrl_p = state->dr_ctrl_bp; |
| 1067 | dr_ref_count = state->dr_ref_count_bp; |
| 1068 | } |
| 1069 | |
| 1070 | ctrl = aarch64_point_encode_ctrl_reg (type, len); |
| 1071 | |
| 1072 | /* Find an existing or free register in our cache. */ |
| 1073 | idx = -1; |
| 1074 | for (i = 0; i < num_regs; ++i) |
| 1075 | { |
| 1076 | if ((dr_ctrl_p[i] & 1) == 0) |
| 1077 | { |
| 1078 | gdb_assert (dr_ref_count[i] == 0); |
| 1079 | idx = i; |
| 1080 | /* no break; continue hunting for an existing one. */ |
| 1081 | } |
| 1082 | else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) |
| 1083 | { |
| 1084 | gdb_assert (dr_ref_count[i] != 0); |
| 1085 | idx = i; |
| 1086 | break; |
| 1087 | } |
| 1088 | } |
| 1089 | |
| 1090 | /* No space. */ |
| 1091 | if (idx == -1) |
| 1092 | return -1; |
| 1093 | |
| 1094 | /* Update our cache. */ |
| 1095 | if ((dr_ctrl_p[idx] & 1) == 0) |
| 1096 | { |
| 1097 | /* new entry */ |
| 1098 | dr_addr_p[idx] = addr; |
| 1099 | dr_ctrl_p[idx] = ctrl; |
| 1100 | dr_ref_count[idx] = 1; |
| 1101 | /* Notify the change. */ |
| 1102 | aarch64_notify_debug_reg_change (state, is_watchpoint, idx); |
| 1103 | } |
| 1104 | else |
| 1105 | { |
| 1106 | /* existing entry */ |
| 1107 | dr_ref_count[idx]++; |
| 1108 | } |
| 1109 | |
| 1110 | return 0; |
| 1111 | } |
| 1112 | |
| 1113 | /* Record the removal of one breakpoint/watchpoint, as represented by |
| 1114 | ADDR and CTRL, in the cached debug register state area *STATE. */ |
| 1115 | |
| 1116 | static int |
| 1117 | aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state, |
| 1118 | int type, CORE_ADDR addr, int len) |
| 1119 | { |
| 1120 | int i, num_regs, is_watchpoint; |
| 1121 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; |
| 1122 | CORE_ADDR *dr_addr_p; |
| 1123 | |
| 1124 | /* Set up state pointers. */ |
| 1125 | is_watchpoint = (type != hw_execute); |
| 1126 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); |
| 1127 | if (is_watchpoint) |
| 1128 | { |
| 1129 | num_regs = aarch64_num_wp_regs; |
| 1130 | dr_addr_p = state->dr_addr_wp; |
| 1131 | dr_ctrl_p = state->dr_ctrl_wp; |
| 1132 | dr_ref_count = state->dr_ref_count_wp; |
| 1133 | } |
| 1134 | else |
| 1135 | { |
| 1136 | num_regs = aarch64_num_bp_regs; |
| 1137 | dr_addr_p = state->dr_addr_bp; |
| 1138 | dr_ctrl_p = state->dr_ctrl_bp; |
| 1139 | dr_ref_count = state->dr_ref_count_bp; |
| 1140 | } |
| 1141 | |
| 1142 | ctrl = aarch64_point_encode_ctrl_reg (type, len); |
| 1143 | |
| 1144 | /* Find the entry that matches the ADDR and CTRL. */ |
| 1145 | for (i = 0; i < num_regs; ++i) |
| 1146 | if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) |
| 1147 | { |
| 1148 | gdb_assert (dr_ref_count[i] != 0); |
| 1149 | break; |
| 1150 | } |
| 1151 | |
| 1152 | /* Not found. */ |
| 1153 | if (i == num_regs) |
| 1154 | return -1; |
| 1155 | |
| 1156 | /* Clear our cache. */ |
| 1157 | if (--dr_ref_count[i] == 0) |
| 1158 | { |
| 1159 | /* Clear the enable bit. */ |
| 1160 | ctrl &= ~1; |
| 1161 | dr_addr_p[i] = 0; |
| 1162 | dr_ctrl_p[i] = ctrl; |
| 1163 | /* Notify the change. */ |
| 1164 | aarch64_notify_debug_reg_change (state, is_watchpoint, i); |
| 1165 | } |
| 1166 | |
| 1167 | return 0; |
| 1168 | } |
| 1169 | |
| 1170 | /* Implement insertion and removal of a single breakpoint. */ |
| 1171 | |
| 1172 | static int |
| 1173 | aarch64_handle_breakpoint (int type, CORE_ADDR addr, int len, int is_insert) |
| 1174 | { |
| 1175 | struct aarch64_debug_reg_state *state; |
| 1176 | |
| 1177 | /* The hardware breakpoint on AArch64 should always be 4-byte |
| 1178 | aligned. */ |
| 1179 | if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len)) |
| 1180 | return -1; |
| 1181 | |
| 1182 | state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
| 1183 | |
| 1184 | if (is_insert) |
| 1185 | return aarch64_dr_state_insert_one_point (state, type, addr, len); |
| 1186 | else |
| 1187 | return aarch64_dr_state_remove_one_point (state, type, addr, len); |
| 1188 | } |
| 1189 | |
| 1190 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
| 1191 | Return 0 on success, -1 on failure. */ |
| 1192 | |
| 1193 | static int |
| 1194 | aarch64_linux_insert_hw_breakpoint (struct target_ops *self, |
| 1195 | struct gdbarch *gdbarch, |
| 1196 | struct bp_target_info *bp_tgt) |
| 1197 | { |
| 1198 | int ret; |
| 1199 | CORE_ADDR addr = bp_tgt->placed_address; |
| 1200 | const int len = 4; |
| 1201 | const int type = hw_execute; |
| 1202 | |
| 1203 | if (debug_hw_points) |
| 1204 | fprintf_unfiltered |
| 1205 | (gdb_stdlog, |
| 1206 | "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", |
| 1207 | (unsigned long) addr, len); |
| 1208 | |
| 1209 | ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */); |
| 1210 | |
| 1211 | if (debug_hw_points > 1) |
| 1212 | { |
| 1213 | struct aarch64_debug_reg_state *state |
| 1214 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
| 1215 | |
| 1216 | aarch64_show_debug_reg_state (state, |
| 1217 | "insert_hw_watchpoint", addr, len, type); |
| 1218 | } |
| 1219 | |
| 1220 | return ret; |
| 1221 | } |
| 1222 | |
| 1223 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
| 1224 | Return 0 on success, -1 on failure. */ |
| 1225 | |
| 1226 | static int |
| 1227 | aarch64_linux_remove_hw_breakpoint (struct target_ops *self, |
| 1228 | struct gdbarch *gdbarch, |
| 1229 | struct bp_target_info *bp_tgt) |
| 1230 | { |
| 1231 | int ret; |
| 1232 | CORE_ADDR addr = bp_tgt->placed_address; |
| 1233 | const int len = 4; |
| 1234 | const int type = hw_execute; |
| 1235 | |
| 1236 | if (debug_hw_points) |
| 1237 | fprintf_unfiltered |
| 1238 | (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", |
| 1239 | (unsigned long) addr, len); |
| 1240 | |
| 1241 | ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */); |
| 1242 | |
| 1243 | if (debug_hw_points > 1) |
| 1244 | { |
| 1245 | struct aarch64_debug_reg_state *state |
| 1246 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
| 1247 | |
| 1248 | aarch64_show_debug_reg_state (state, |
| 1249 | "remove_hw_watchpoint", addr, len, type); |
| 1250 | } |
| 1251 | |
| 1252 | return ret; |
| 1253 | } |
| 1254 | |
| 1255 | /* This is essentially the same as aarch64_handle_breakpoint, apart |
| 1256 | from that it is an aligned watchpoint to be handled. */ |
| 1257 | |
| 1258 | static int |
| 1259 | aarch64_handle_aligned_watchpoint (int type, CORE_ADDR addr, int len, |
| 1260 | int is_insert) |
| 1261 | { |
| 1262 | struct aarch64_debug_reg_state *state |
| 1263 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
| 1264 | |
| 1265 | if (is_insert) |
| 1266 | return aarch64_dr_state_insert_one_point (state, type, addr, len); |
| 1267 | else |
| 1268 | return aarch64_dr_state_remove_one_point (state, type, addr, len); |
| 1269 | } |
| 1270 | |
| 1271 | /* Insert/remove unaligned watchpoint by calling |
| 1272 | aarch64_align_watchpoint repeatedly until the whole watched region, |
| 1273 | as represented by ADDR and LEN, has been properly aligned and ready |
| 1274 | to be written to one or more hardware watchpoint registers. |
| 1275 | IS_INSERT indicates whether this is an insertion or a deletion. |
| 1276 | Return 0 if succeed. */ |
| 1277 | |
| 1278 | static int |
| 1279 | aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len, |
| 1280 | int is_insert) |
| 1281 | { |
| 1282 | struct aarch64_debug_reg_state *state |
| 1283 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
| 1284 | |
| 1285 | while (len > 0) |
| 1286 | { |
| 1287 | CORE_ADDR aligned_addr; |
| 1288 | int aligned_len, ret; |
| 1289 | |
| 1290 | aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len, |
| 1291 | &addr, &len); |
| 1292 | |
| 1293 | if (is_insert) |
| 1294 | ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr, |
| 1295 | aligned_len); |
| 1296 | else |
| 1297 | ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr, |
| 1298 | aligned_len); |
| 1299 | |
| 1300 | if (debug_hw_points) |
| 1301 | fprintf_unfiltered (gdb_stdlog, |
| 1302 | "handle_unaligned_watchpoint: is_insert: %d\n" |
| 1303 | " aligned_addr: 0x%08lx, aligned_len: %d\n" |
| 1304 | " next_addr: 0x%08lx, next_len: %d\n", |
| 1305 | is_insert, aligned_addr, aligned_len, addr, len); |
| 1306 | |
| 1307 | if (ret != 0) |
| 1308 | return ret; |
| 1309 | } |
| 1310 | |
| 1311 | return 0; |
| 1312 | } |
| 1313 | |
| 1314 | /* Implements insertion and removal of a single watchpoint. */ |
| 1315 | |
| 1316 | static int |
| 1317 | aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert) |
| 1318 | { |
| 1319 | if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len)) |
| 1320 | return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert); |
| 1321 | else |
| 1322 | return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert); |
| 1323 | } |
| 1324 | |
| 1325 | /* Implement the "to_insert_watchpoint" target_ops method. |
| 1326 | |
| 1327 | Insert a watchpoint to watch a memory region which starts at |
| 1328 | address ADDR and whose length is LEN bytes. Watch memory accesses |
| 1329 | of the type TYPE. Return 0 on success, -1 on failure. */ |
| 1330 | |
| 1331 | static int |
| 1332 | aarch64_linux_insert_watchpoint (struct target_ops *self, |
| 1333 | CORE_ADDR addr, int len, int type, |
| 1334 | struct expression *cond) |
| 1335 | { |
| 1336 | int ret; |
| 1337 | |
| 1338 | if (debug_hw_points) |
| 1339 | fprintf_unfiltered (gdb_stdlog, |
| 1340 | "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n", |
| 1341 | (unsigned long) addr, len); |
| 1342 | |
| 1343 | gdb_assert (type != hw_execute); |
| 1344 | |
| 1345 | ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */); |
| 1346 | |
| 1347 | if (debug_hw_points > 1) |
| 1348 | { |
| 1349 | struct aarch64_debug_reg_state *state |
| 1350 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
| 1351 | |
| 1352 | aarch64_show_debug_reg_state (state, |
| 1353 | "insert_watchpoint", addr, len, type); |
| 1354 | } |
| 1355 | |
| 1356 | return ret; |
| 1357 | } |
| 1358 | |
| 1359 | /* Implement the "to_remove_watchpoint" target_ops method. |
| 1360 | Remove a watchpoint that watched the memory region which starts at |
| 1361 | address ADDR, whose length is LEN bytes, and for accesses of the |
| 1362 | type TYPE. Return 0 on success, -1 on failure. */ |
| 1363 | |
| 1364 | static int |
| 1365 | aarch64_linux_remove_watchpoint (struct target_ops *self, |
| 1366 | CORE_ADDR addr, int len, int type, |
| 1367 | struct expression *cond) |
| 1368 | { |
| 1369 | int ret; |
| 1370 | |
| 1371 | if (debug_hw_points) |
| 1372 | fprintf_unfiltered (gdb_stdlog, |
| 1373 | "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n", |
| 1374 | (unsigned long) addr, len); |
| 1375 | |
| 1376 | gdb_assert (type != hw_execute); |
| 1377 | |
| 1378 | ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */); |
| 1379 | |
| 1380 | if (debug_hw_points > 1) |
| 1381 | { |
| 1382 | struct aarch64_debug_reg_state *state |
| 1383 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
| 1384 | |
| 1385 | aarch64_show_debug_reg_state (state, |
| 1386 | "remove_watchpoint", addr, len, type); |
| 1387 | } |
| 1388 | |
| 1389 | return ret; |
| 1390 | } |
| 1391 | |
| 1392 | /* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */ |
| 1393 | |
| 1394 | static int |
| 1395 | aarch64_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
| 1396 | CORE_ADDR addr, int len) |
| 1397 | { |
| 1398 | CORE_ADDR aligned_addr; |
| 1399 | |
| 1400 | /* Can not set watchpoints for zero or negative lengths. */ |
| 1401 | if (len <= 0) |
| 1402 | return 0; |
| 1403 | |
| 1404 | /* Must have hardware watchpoint debug register(s). */ |
| 1405 | if (aarch64_num_wp_regs == 0) |
| 1406 | return 0; |
| 1407 | |
| 1408 | /* We support unaligned watchpoint address and arbitrary length, |
| 1409 | as long as the size of the whole watched area after alignment |
| 1410 | doesn't exceed size of the total area that all watchpoint debug |
| 1411 | registers can watch cooperatively. |
| 1412 | |
| 1413 | This is a very relaxed rule, but unfortunately there are |
| 1414 | limitations, e.g. false-positive hits, due to limited support of |
| 1415 | hardware debug registers in the kernel. See comment above |
| 1416 | aarch64_align_watchpoint for more information. */ |
| 1417 | |
| 1418 | aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1); |
| 1419 | if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG |
| 1420 | < addr + len) |
| 1421 | return 0; |
| 1422 | |
| 1423 | /* All tests passed so we are likely to be able to set the watchpoint. |
| 1424 | The reason that it is 'likely' rather than 'must' is because |
| 1425 | we don't check the current usage of the watchpoint registers, and |
| 1426 | there may not be enough registers available for this watchpoint. |
| 1427 | Ideally we should check the cached debug register state, however |
| 1428 | the checking is costly. */ |
| 1429 | return 1; |
| 1430 | } |
| 1431 | |
| 1432 | /* Implement the "to_stopped_data_address" target_ops method. */ |
| 1433 | |
| 1434 | static int |
| 1435 | aarch64_linux_stopped_data_address (struct target_ops *target, |
| 1436 | CORE_ADDR *addr_p) |
| 1437 | { |
| 1438 | siginfo_t siginfo; |
| 1439 | int i, tid; |
| 1440 | struct aarch64_debug_reg_state *state; |
| 1441 | |
| 1442 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
| 1443 | return 0; |
| 1444 | |
| 1445 | /* This must be a hardware breakpoint. */ |
| 1446 | if (siginfo.si_signo != SIGTRAP |
| 1447 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) |
| 1448 | return 0; |
| 1449 | |
| 1450 | /* Check if the address matches any watched address. */ |
| 1451 | state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
| 1452 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
| 1453 | { |
| 1454 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); |
| 1455 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; |
| 1456 | const CORE_ADDR addr_watch = state->dr_addr_wp[i]; |
| 1457 | |
| 1458 | if (state->dr_ref_count_wp[i] |
| 1459 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) |
| 1460 | && addr_trap >= addr_watch |
| 1461 | && addr_trap < addr_watch + len) |
| 1462 | { |
| 1463 | *addr_p = addr_trap; |
| 1464 | return 1; |
| 1465 | } |
| 1466 | } |
| 1467 | |
| 1468 | return 0; |
| 1469 | } |
| 1470 | |
| 1471 | /* Implement the "to_stopped_by_watchpoint" target_ops method. */ |
| 1472 | |
| 1473 | static int |
| 1474 | aarch64_linux_stopped_by_watchpoint (struct target_ops *ops) |
| 1475 | { |
| 1476 | CORE_ADDR addr; |
| 1477 | |
| 1478 | return aarch64_linux_stopped_data_address (ops, &addr); |
| 1479 | } |
| 1480 | |
| 1481 | /* Implement the "to_watchpoint_addr_within_range" target_ops method. */ |
| 1482 | |
| 1483 | static int |
| 1484 | aarch64_linux_watchpoint_addr_within_range (struct target_ops *target, |
| 1485 | CORE_ADDR addr, |
| 1486 | CORE_ADDR start, int length) |
| 1487 | { |
| 1488 | return start <= addr && start + length - 1 >= addr; |
| 1489 | } |
| 1490 | |
| 1491 | /* Define AArch64 maintenance commands. */ |
| 1492 | |
| 1493 | static void |
| 1494 | add_show_debug_regs_command (void) |
| 1495 | { |
| 1496 | /* A maintenance command to enable printing the internal DRi mirror |
| 1497 | variables. */ |
| 1498 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
| 1499 | &debug_hw_points, _("\ |
| 1500 | Set whether to show variables that mirror the AArch64 debug registers."), _("\ |
| 1501 | Show whether to show variables that mirror the AArch64 debug registers."), _("\ |
| 1502 | Use \"on\" to enable, \"off\" to disable.\n\ |
| 1503 | If enabled, the debug registers values are shown when GDB inserts\n\ |
| 1504 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ |
| 1505 | triggers a breakpoint or watchpoint."), |
| 1506 | NULL, |
| 1507 | NULL, |
| 1508 | &maintenance_set_cmdlist, |
| 1509 | &maintenance_show_cmdlist); |
| 1510 | } |
| 1511 | |
| 1512 | /* -Wmissing-prototypes. */ |
| 1513 | void _initialize_aarch64_linux_nat (void); |
| 1514 | |
| 1515 | void |
| 1516 | _initialize_aarch64_linux_nat (void) |
| 1517 | { |
| 1518 | struct target_ops *t; |
| 1519 | |
| 1520 | /* Fill in the generic GNU/Linux methods. */ |
| 1521 | t = linux_target (); |
| 1522 | |
| 1523 | add_show_debug_regs_command (); |
| 1524 | |
| 1525 | /* Add our register access methods. */ |
| 1526 | t->to_fetch_registers = aarch64_linux_fetch_inferior_registers; |
| 1527 | t->to_store_registers = aarch64_linux_store_inferior_registers; |
| 1528 | |
| 1529 | t->to_read_description = aarch64_linux_read_description; |
| 1530 | |
| 1531 | t->to_can_use_hw_breakpoint = aarch64_linux_can_use_hw_breakpoint; |
| 1532 | t->to_insert_hw_breakpoint = aarch64_linux_insert_hw_breakpoint; |
| 1533 | t->to_remove_hw_breakpoint = aarch64_linux_remove_hw_breakpoint; |
| 1534 | t->to_region_ok_for_hw_watchpoint = |
| 1535 | aarch64_linux_region_ok_for_hw_watchpoint; |
| 1536 | t->to_insert_watchpoint = aarch64_linux_insert_watchpoint; |
| 1537 | t->to_remove_watchpoint = aarch64_linux_remove_watchpoint; |
| 1538 | t->to_stopped_by_watchpoint = aarch64_linux_stopped_by_watchpoint; |
| 1539 | t->to_stopped_data_address = aarch64_linux_stopped_data_address; |
| 1540 | t->to_watchpoint_addr_within_range = |
| 1541 | aarch64_linux_watchpoint_addr_within_range; |
| 1542 | |
| 1543 | /* Override the GNU/Linux inferior startup hook. */ |
| 1544 | super_post_startup_inferior = t->to_post_startup_inferior; |
| 1545 | t->to_post_startup_inferior = aarch64_linux_child_post_startup_inferior; |
| 1546 | |
| 1547 | /* Register the target. */ |
| 1548 | linux_nat_add_target (t); |
| 1549 | linux_nat_set_new_thread (t, aarch64_linux_new_thread); |
| 1550 | linux_nat_set_new_fork (t, aarch64_linux_new_fork); |
| 1551 | linux_nat_set_forget_process (t, aarch64_forget_process); |
| 1552 | linux_nat_set_prepare_to_resume (t, aarch64_linux_prepare_to_resume); |
| 1553 | } |