| 1 | /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger. |
| 2 | |
| 3 | Copyright (C) 1993-2019 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "frame.h" |
| 22 | #include "frame-unwind.h" |
| 23 | #include "frame-base.h" |
| 24 | #include "dwarf2-frame.h" |
| 25 | #include "inferior.h" |
| 26 | #include "symtab.h" |
| 27 | #include "value.h" |
| 28 | #include "gdbcmd.h" |
| 29 | #include "gdbcore.h" |
| 30 | #include "dis-asm.h" |
| 31 | #include "symfile.h" |
| 32 | #include "objfiles.h" |
| 33 | #include "linespec.h" |
| 34 | #include "regcache.h" |
| 35 | #include "reggroups.h" |
| 36 | #include "arch-utils.h" |
| 37 | #include "osabi.h" |
| 38 | #include "block.h" |
| 39 | #include "infcall.h" |
| 40 | #include "trad-frame.h" |
| 41 | |
| 42 | #include "elf-bfd.h" |
| 43 | |
| 44 | #include "alpha-tdep.h" |
| 45 | #include <algorithm> |
| 46 | |
| 47 | /* Instruction decoding. The notations for registers, immediates and |
| 48 | opcodes are the same as the one used in Compaq's Alpha architecture |
| 49 | handbook. */ |
| 50 | |
| 51 | #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26) |
| 52 | |
| 53 | /* Memory instruction format */ |
| 54 | #define MEM_RA(insn) ((insn & 0x03e00000) >> 21) |
| 55 | #define MEM_RB(insn) ((insn & 0x001f0000) >> 16) |
| 56 | #define MEM_DISP(insn) \ |
| 57 | (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff)) |
| 58 | |
| 59 | static const int lda_opcode = 0x08; |
| 60 | static const int stq_opcode = 0x2d; |
| 61 | |
| 62 | /* Branch instruction format */ |
| 63 | #define BR_RA(insn) MEM_RA(insn) |
| 64 | |
| 65 | static const int br_opcode = 0x30; |
| 66 | static const int bne_opcode = 0x3d; |
| 67 | |
| 68 | /* Operate instruction format */ |
| 69 | #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5) |
| 70 | #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000) |
| 71 | #define OPR_RA(insn) MEM_RA(insn) |
| 72 | #define OPR_RC(insn) ((insn & 0x1f)) |
| 73 | #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13) |
| 74 | |
| 75 | static const int subq_opcode = 0x10; |
| 76 | static const int subq_function = 0x29; |
| 77 | |
| 78 | \f |
| 79 | /* Return the name of the REGNO register. |
| 80 | |
| 81 | An empty name corresponds to a register number that used to |
| 82 | be used for a virtual register. That virtual register has |
| 83 | been removed, but the index is still reserved to maintain |
| 84 | compatibility with existing remote alpha targets. */ |
| 85 | |
| 86 | static const char * |
| 87 | alpha_register_name (struct gdbarch *gdbarch, int regno) |
| 88 | { |
| 89 | static const char * const register_names[] = |
| 90 | { |
| 91 | "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", |
| 92 | "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", |
| 93 | "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", |
| 94 | "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", |
| 95 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 96 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 97 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 98 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr", |
| 99 | "pc", "", "unique" |
| 100 | }; |
| 101 | |
| 102 | if (regno < 0) |
| 103 | return NULL; |
| 104 | if (regno >= ARRAY_SIZE(register_names)) |
| 105 | return NULL; |
| 106 | return register_names[regno]; |
| 107 | } |
| 108 | |
| 109 | static int |
| 110 | alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
| 111 | { |
| 112 | return (strlen (alpha_register_name (gdbarch, regno)) == 0); |
| 113 | } |
| 114 | |
| 115 | static int |
| 116 | alpha_cannot_store_register (struct gdbarch *gdbarch, int regno) |
| 117 | { |
| 118 | return (regno == ALPHA_ZERO_REGNUM |
| 119 | || strlen (alpha_register_name (gdbarch, regno)) == 0); |
| 120 | } |
| 121 | |
| 122 | static struct type * |
| 123 | alpha_register_type (struct gdbarch *gdbarch, int regno) |
| 124 | { |
| 125 | if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM) |
| 126 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 127 | if (regno == ALPHA_PC_REGNUM) |
| 128 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 129 | |
| 130 | /* Don't need to worry about little vs big endian until |
| 131 | some jerk tries to port to alpha-unicosmk. */ |
| 132 | if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31) |
| 133 | return builtin_type (gdbarch)->builtin_double; |
| 134 | |
| 135 | return builtin_type (gdbarch)->builtin_int64; |
| 136 | } |
| 137 | |
| 138 | /* Is REGNUM a member of REGGROUP? */ |
| 139 | |
| 140 | static int |
| 141 | alpha_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 142 | struct reggroup *group) |
| 143 | { |
| 144 | /* Filter out any registers eliminated, but whose regnum is |
| 145 | reserved for backward compatibility, e.g. the vfp. */ |
| 146 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
| 147 | || *gdbarch_register_name (gdbarch, regnum) == '\0') |
| 148 | return 0; |
| 149 | |
| 150 | if (group == all_reggroup) |
| 151 | return 1; |
| 152 | |
| 153 | /* Zero should not be saved or restored. Technically it is a general |
| 154 | register (just as $f31 would be a float if we represented it), but |
| 155 | there's no point displaying it during "info regs", so leave it out |
| 156 | of all groups except for "all". */ |
| 157 | if (regnum == ALPHA_ZERO_REGNUM) |
| 158 | return 0; |
| 159 | |
| 160 | /* All other registers are saved and restored. */ |
| 161 | if (group == save_reggroup || group == restore_reggroup) |
| 162 | return 1; |
| 163 | |
| 164 | /* All other groups are non-overlapping. */ |
| 165 | |
| 166 | /* Since this is really a PALcode memory slot... */ |
| 167 | if (regnum == ALPHA_UNIQUE_REGNUM) |
| 168 | return group == system_reggroup; |
| 169 | |
| 170 | /* Force the FPCR to be considered part of the floating point state. */ |
| 171 | if (regnum == ALPHA_FPCR_REGNUM) |
| 172 | return group == float_reggroup; |
| 173 | |
| 174 | if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 31) |
| 175 | return group == float_reggroup; |
| 176 | else |
| 177 | return group == general_reggroup; |
| 178 | } |
| 179 | |
| 180 | /* The following represents exactly the conversion performed by |
| 181 | the LDS instruction. This applies to both single-precision |
| 182 | floating point and 32-bit integers. */ |
| 183 | |
| 184 | static void |
| 185 | alpha_lds (struct gdbarch *gdbarch, void *out, const void *in) |
| 186 | { |
| 187 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 188 | ULONGEST mem |
| 189 | = extract_unsigned_integer ((const gdb_byte *) in, 4, byte_order); |
| 190 | ULONGEST frac = (mem >> 0) & 0x7fffff; |
| 191 | ULONGEST sign = (mem >> 31) & 1; |
| 192 | ULONGEST exp_msb = (mem >> 30) & 1; |
| 193 | ULONGEST exp_low = (mem >> 23) & 0x7f; |
| 194 | ULONGEST exp, reg; |
| 195 | |
| 196 | exp = (exp_msb << 10) | exp_low; |
| 197 | if (exp_msb) |
| 198 | { |
| 199 | if (exp_low == 0x7f) |
| 200 | exp = 0x7ff; |
| 201 | } |
| 202 | else |
| 203 | { |
| 204 | if (exp_low != 0x00) |
| 205 | exp |= 0x380; |
| 206 | } |
| 207 | |
| 208 | reg = (sign << 63) | (exp << 52) | (frac << 29); |
| 209 | store_unsigned_integer ((gdb_byte *) out, 8, byte_order, reg); |
| 210 | } |
| 211 | |
| 212 | /* Similarly, this represents exactly the conversion performed by |
| 213 | the STS instruction. */ |
| 214 | |
| 215 | static void |
| 216 | alpha_sts (struct gdbarch *gdbarch, void *out, const void *in) |
| 217 | { |
| 218 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 219 | ULONGEST reg, mem; |
| 220 | |
| 221 | reg = extract_unsigned_integer ((const gdb_byte *) in, 8, byte_order); |
| 222 | mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff); |
| 223 | store_unsigned_integer ((gdb_byte *) out, 4, byte_order, mem); |
| 224 | } |
| 225 | |
| 226 | /* The alpha needs a conversion between register and memory format if the |
| 227 | register is a floating point register and memory format is float, as the |
| 228 | register format must be double or memory format is an integer with 4 |
| 229 | bytes, as the representation of integers in floating point |
| 230 | registers is different. */ |
| 231 | |
| 232 | static int |
| 233 | alpha_convert_register_p (struct gdbarch *gdbarch, int regno, |
| 234 | struct type *type) |
| 235 | { |
| 236 | return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31 |
| 237 | && TYPE_LENGTH (type) == 4); |
| 238 | } |
| 239 | |
| 240 | static int |
| 241 | alpha_register_to_value (struct frame_info *frame, int regnum, |
| 242 | struct type *valtype, gdb_byte *out, |
| 243 | int *optimizedp, int *unavailablep) |
| 244 | { |
| 245 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 246 | struct value *value = get_frame_register_value (frame, regnum); |
| 247 | |
| 248 | gdb_assert (value != NULL); |
| 249 | *optimizedp = value_optimized_out (value); |
| 250 | *unavailablep = !value_entirely_available (value); |
| 251 | |
| 252 | if (*optimizedp || *unavailablep) |
| 253 | { |
| 254 | release_value (value); |
| 255 | return 0; |
| 256 | } |
| 257 | |
| 258 | /* Convert to VALTYPE. */ |
| 259 | |
| 260 | gdb_assert (TYPE_LENGTH (valtype) == 4); |
| 261 | alpha_sts (gdbarch, out, value_contents_all (value)); |
| 262 | |
| 263 | release_value (value); |
| 264 | return 1; |
| 265 | } |
| 266 | |
| 267 | static void |
| 268 | alpha_value_to_register (struct frame_info *frame, int regnum, |
| 269 | struct type *valtype, const gdb_byte *in) |
| 270 | { |
| 271 | gdb_byte out[ALPHA_REGISTER_SIZE]; |
| 272 | |
| 273 | gdb_assert (TYPE_LENGTH (valtype) == 4); |
| 274 | gdb_assert (register_size (get_frame_arch (frame), regnum) |
| 275 | <= ALPHA_REGISTER_SIZE); |
| 276 | alpha_lds (get_frame_arch (frame), out, in); |
| 277 | |
| 278 | put_frame_register (frame, regnum, out); |
| 279 | } |
| 280 | |
| 281 | \f |
| 282 | /* The alpha passes the first six arguments in the registers, the rest on |
| 283 | the stack. The register arguments are stored in ARG_REG_BUFFER, and |
| 284 | then moved into the register file; this simplifies the passing of a |
| 285 | large struct which extends from the registers to the stack, plus avoids |
| 286 | three ptrace invocations per word. |
| 287 | |
| 288 | We don't bother tracking which register values should go in integer |
| 289 | regs or fp regs; we load the same values into both. |
| 290 | |
| 291 | If the called function is returning a structure, the address of the |
| 292 | structure to be returned is passed as a hidden first argument. */ |
| 293 | |
| 294 | static CORE_ADDR |
| 295 | alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 296 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 297 | int nargs, struct value **args, CORE_ADDR sp, |
| 298 | function_call_return_method return_method, |
| 299 | CORE_ADDR struct_addr) |
| 300 | { |
| 301 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 302 | int i; |
| 303 | int accumulate_size = (return_method == return_method_struct) ? 8 : 0; |
| 304 | struct alpha_arg |
| 305 | { |
| 306 | const gdb_byte *contents; |
| 307 | int len; |
| 308 | int offset; |
| 309 | }; |
| 310 | struct alpha_arg *alpha_args = XALLOCAVEC (struct alpha_arg, nargs); |
| 311 | struct alpha_arg *m_arg; |
| 312 | gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS]; |
| 313 | int required_arg_regs; |
| 314 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 315 | |
| 316 | /* The ABI places the address of the called function in T12. */ |
| 317 | regcache_cooked_write_signed (regcache, ALPHA_T12_REGNUM, func_addr); |
| 318 | |
| 319 | /* Set the return address register to point to the entry point |
| 320 | of the program, where a breakpoint lies in wait. */ |
| 321 | regcache_cooked_write_signed (regcache, ALPHA_RA_REGNUM, bp_addr); |
| 322 | |
| 323 | /* Lay out the arguments in memory. */ |
| 324 | for (i = 0, m_arg = alpha_args; i < nargs; i++, m_arg++) |
| 325 | { |
| 326 | struct value *arg = args[i]; |
| 327 | struct type *arg_type = check_typedef (value_type (arg)); |
| 328 | |
| 329 | /* Cast argument to long if necessary as the compiler does it too. */ |
| 330 | switch (TYPE_CODE (arg_type)) |
| 331 | { |
| 332 | case TYPE_CODE_INT: |
| 333 | case TYPE_CODE_BOOL: |
| 334 | case TYPE_CODE_CHAR: |
| 335 | case TYPE_CODE_RANGE: |
| 336 | case TYPE_CODE_ENUM: |
| 337 | if (TYPE_LENGTH (arg_type) == 4) |
| 338 | { |
| 339 | /* 32-bit values must be sign-extended to 64 bits |
| 340 | even if the base data type is unsigned. */ |
| 341 | arg_type = builtin_type (gdbarch)->builtin_int32; |
| 342 | arg = value_cast (arg_type, arg); |
| 343 | } |
| 344 | if (TYPE_LENGTH (arg_type) < ALPHA_REGISTER_SIZE) |
| 345 | { |
| 346 | arg_type = builtin_type (gdbarch)->builtin_int64; |
| 347 | arg = value_cast (arg_type, arg); |
| 348 | } |
| 349 | break; |
| 350 | |
| 351 | case TYPE_CODE_FLT: |
| 352 | /* "float" arguments loaded in registers must be passed in |
| 353 | register format, aka "double". */ |
| 354 | if (accumulate_size < sizeof (arg_reg_buffer) |
| 355 | && TYPE_LENGTH (arg_type) == 4) |
| 356 | { |
| 357 | arg_type = builtin_type (gdbarch)->builtin_double; |
| 358 | arg = value_cast (arg_type, arg); |
| 359 | } |
| 360 | /* Tru64 5.1 has a 128-bit long double, and passes this by |
| 361 | invisible reference. No one else uses this data type. */ |
| 362 | else if (TYPE_LENGTH (arg_type) == 16) |
| 363 | { |
| 364 | /* Allocate aligned storage. */ |
| 365 | sp = (sp & -16) - 16; |
| 366 | |
| 367 | /* Write the real data into the stack. */ |
| 368 | write_memory (sp, value_contents (arg), 16); |
| 369 | |
| 370 | /* Construct the indirection. */ |
| 371 | arg_type = lookup_pointer_type (arg_type); |
| 372 | arg = value_from_pointer (arg_type, sp); |
| 373 | } |
| 374 | break; |
| 375 | |
| 376 | case TYPE_CODE_COMPLEX: |
| 377 | /* ??? The ABI says that complex values are passed as two |
| 378 | separate scalar values. This distinction only matters |
| 379 | for complex float. However, GCC does not implement this. */ |
| 380 | |
| 381 | /* Tru64 5.1 has a 128-bit long double, and passes this by |
| 382 | invisible reference. */ |
| 383 | if (TYPE_LENGTH (arg_type) == 32) |
| 384 | { |
| 385 | /* Allocate aligned storage. */ |
| 386 | sp = (sp & -16) - 16; |
| 387 | |
| 388 | /* Write the real data into the stack. */ |
| 389 | write_memory (sp, value_contents (arg), 32); |
| 390 | |
| 391 | /* Construct the indirection. */ |
| 392 | arg_type = lookup_pointer_type (arg_type); |
| 393 | arg = value_from_pointer (arg_type, sp); |
| 394 | } |
| 395 | break; |
| 396 | |
| 397 | default: |
| 398 | break; |
| 399 | } |
| 400 | m_arg->len = TYPE_LENGTH (arg_type); |
| 401 | m_arg->offset = accumulate_size; |
| 402 | accumulate_size = (accumulate_size + m_arg->len + 7) & ~7; |
| 403 | m_arg->contents = value_contents (arg); |
| 404 | } |
| 405 | |
| 406 | /* Determine required argument register loads, loading an argument register |
| 407 | is expensive as it uses three ptrace calls. */ |
| 408 | required_arg_regs = accumulate_size / 8; |
| 409 | if (required_arg_regs > ALPHA_NUM_ARG_REGS) |
| 410 | required_arg_regs = ALPHA_NUM_ARG_REGS; |
| 411 | |
| 412 | /* Make room for the arguments on the stack. */ |
| 413 | if (accumulate_size < sizeof(arg_reg_buffer)) |
| 414 | accumulate_size = 0; |
| 415 | else |
| 416 | accumulate_size -= sizeof(arg_reg_buffer); |
| 417 | sp -= accumulate_size; |
| 418 | |
| 419 | /* Keep sp aligned to a multiple of 16 as the ABI requires. */ |
| 420 | sp &= ~15; |
| 421 | |
| 422 | /* `Push' arguments on the stack. */ |
| 423 | for (i = nargs; m_arg--, --i >= 0;) |
| 424 | { |
| 425 | const gdb_byte *contents = m_arg->contents; |
| 426 | int offset = m_arg->offset; |
| 427 | int len = m_arg->len; |
| 428 | |
| 429 | /* Copy the bytes destined for registers into arg_reg_buffer. */ |
| 430 | if (offset < sizeof(arg_reg_buffer)) |
| 431 | { |
| 432 | if (offset + len <= sizeof(arg_reg_buffer)) |
| 433 | { |
| 434 | memcpy (arg_reg_buffer + offset, contents, len); |
| 435 | continue; |
| 436 | } |
| 437 | else |
| 438 | { |
| 439 | int tlen = sizeof(arg_reg_buffer) - offset; |
| 440 | memcpy (arg_reg_buffer + offset, contents, tlen); |
| 441 | offset += tlen; |
| 442 | contents += tlen; |
| 443 | len -= tlen; |
| 444 | } |
| 445 | } |
| 446 | |
| 447 | /* Everything else goes to the stack. */ |
| 448 | write_memory (sp + offset - sizeof(arg_reg_buffer), contents, len); |
| 449 | } |
| 450 | if (return_method == return_method_struct) |
| 451 | store_unsigned_integer (arg_reg_buffer, ALPHA_REGISTER_SIZE, |
| 452 | byte_order, struct_addr); |
| 453 | |
| 454 | /* Load the argument registers. */ |
| 455 | for (i = 0; i < required_arg_regs; i++) |
| 456 | { |
| 457 | regcache->cooked_write (ALPHA_A0_REGNUM + i, |
| 458 | arg_reg_buffer + i * ALPHA_REGISTER_SIZE); |
| 459 | regcache->cooked_write (ALPHA_FPA0_REGNUM + i, |
| 460 | arg_reg_buffer + i * ALPHA_REGISTER_SIZE); |
| 461 | } |
| 462 | |
| 463 | /* Finally, update the stack pointer. */ |
| 464 | regcache_cooked_write_signed (regcache, ALPHA_SP_REGNUM, sp); |
| 465 | |
| 466 | return sp; |
| 467 | } |
| 468 | |
| 469 | /* Extract from REGCACHE the value about to be returned from a function |
| 470 | and copy it into VALBUF. */ |
| 471 | |
| 472 | static void |
| 473 | alpha_extract_return_value (struct type *valtype, struct regcache *regcache, |
| 474 | gdb_byte *valbuf) |
| 475 | { |
| 476 | struct gdbarch *gdbarch = regcache->arch (); |
| 477 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 478 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
| 479 | ULONGEST l; |
| 480 | |
| 481 | switch (TYPE_CODE (valtype)) |
| 482 | { |
| 483 | case TYPE_CODE_FLT: |
| 484 | switch (TYPE_LENGTH (valtype)) |
| 485 | { |
| 486 | case 4: |
| 487 | regcache->cooked_read (ALPHA_FP0_REGNUM, raw_buffer); |
| 488 | alpha_sts (gdbarch, valbuf, raw_buffer); |
| 489 | break; |
| 490 | |
| 491 | case 8: |
| 492 | regcache->cooked_read (ALPHA_FP0_REGNUM, valbuf); |
| 493 | break; |
| 494 | |
| 495 | case 16: |
| 496 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); |
| 497 | read_memory (l, valbuf, 16); |
| 498 | break; |
| 499 | |
| 500 | default: |
| 501 | internal_error (__FILE__, __LINE__, |
| 502 | _("unknown floating point width")); |
| 503 | } |
| 504 | break; |
| 505 | |
| 506 | case TYPE_CODE_COMPLEX: |
| 507 | switch (TYPE_LENGTH (valtype)) |
| 508 | { |
| 509 | case 8: |
| 510 | /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ |
| 511 | regcache->cooked_read (ALPHA_FP0_REGNUM, valbuf); |
| 512 | break; |
| 513 | |
| 514 | case 16: |
| 515 | regcache->cooked_read (ALPHA_FP0_REGNUM, valbuf); |
| 516 | regcache->cooked_read (ALPHA_FP0_REGNUM + 1, valbuf + 8); |
| 517 | break; |
| 518 | |
| 519 | case 32: |
| 520 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); |
| 521 | read_memory (l, valbuf, 32); |
| 522 | break; |
| 523 | |
| 524 | default: |
| 525 | internal_error (__FILE__, __LINE__, |
| 526 | _("unknown floating point width")); |
| 527 | } |
| 528 | break; |
| 529 | |
| 530 | default: |
| 531 | /* Assume everything else degenerates to an integer. */ |
| 532 | regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); |
| 533 | store_unsigned_integer (valbuf, TYPE_LENGTH (valtype), byte_order, l); |
| 534 | break; |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | /* Insert the given value into REGCACHE as if it was being |
| 539 | returned by a function. */ |
| 540 | |
| 541 | static void |
| 542 | alpha_store_return_value (struct type *valtype, struct regcache *regcache, |
| 543 | const gdb_byte *valbuf) |
| 544 | { |
| 545 | struct gdbarch *gdbarch = regcache->arch (); |
| 546 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
| 547 | ULONGEST l; |
| 548 | |
| 549 | switch (TYPE_CODE (valtype)) |
| 550 | { |
| 551 | case TYPE_CODE_FLT: |
| 552 | switch (TYPE_LENGTH (valtype)) |
| 553 | { |
| 554 | case 4: |
| 555 | alpha_lds (gdbarch, raw_buffer, valbuf); |
| 556 | regcache->cooked_write (ALPHA_FP0_REGNUM, raw_buffer); |
| 557 | break; |
| 558 | |
| 559 | case 8: |
| 560 | regcache->cooked_write (ALPHA_FP0_REGNUM, valbuf); |
| 561 | break; |
| 562 | |
| 563 | case 16: |
| 564 | /* FIXME: 128-bit long doubles are returned like structures: |
| 565 | by writing into indirect storage provided by the caller |
| 566 | as the first argument. */ |
| 567 | error (_("Cannot set a 128-bit long double return value.")); |
| 568 | |
| 569 | default: |
| 570 | internal_error (__FILE__, __LINE__, |
| 571 | _("unknown floating point width")); |
| 572 | } |
| 573 | break; |
| 574 | |
| 575 | case TYPE_CODE_COMPLEX: |
| 576 | switch (TYPE_LENGTH (valtype)) |
| 577 | { |
| 578 | case 8: |
| 579 | /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ |
| 580 | regcache->cooked_write (ALPHA_FP0_REGNUM, valbuf); |
| 581 | break; |
| 582 | |
| 583 | case 16: |
| 584 | regcache->cooked_write (ALPHA_FP0_REGNUM, valbuf); |
| 585 | regcache->cooked_write (ALPHA_FP0_REGNUM + 1, valbuf + 8); |
| 586 | break; |
| 587 | |
| 588 | case 32: |
| 589 | /* FIXME: 128-bit long doubles are returned like structures: |
| 590 | by writing into indirect storage provided by the caller |
| 591 | as the first argument. */ |
| 592 | error (_("Cannot set a 128-bit long double return value.")); |
| 593 | |
| 594 | default: |
| 595 | internal_error (__FILE__, __LINE__, |
| 596 | _("unknown floating point width")); |
| 597 | } |
| 598 | break; |
| 599 | |
| 600 | default: |
| 601 | /* Assume everything else degenerates to an integer. */ |
| 602 | /* 32-bit values must be sign-extended to 64 bits |
| 603 | even if the base data type is unsigned. */ |
| 604 | if (TYPE_LENGTH (valtype) == 4) |
| 605 | valtype = builtin_type (gdbarch)->builtin_int32; |
| 606 | l = unpack_long (valtype, valbuf); |
| 607 | regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l); |
| 608 | break; |
| 609 | } |
| 610 | } |
| 611 | |
| 612 | static enum return_value_convention |
| 613 | alpha_return_value (struct gdbarch *gdbarch, struct value *function, |
| 614 | struct type *type, struct regcache *regcache, |
| 615 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 616 | { |
| 617 | enum type_code code = TYPE_CODE (type); |
| 618 | |
| 619 | if ((code == TYPE_CODE_STRUCT |
| 620 | || code == TYPE_CODE_UNION |
| 621 | || code == TYPE_CODE_ARRAY) |
| 622 | && gdbarch_tdep (gdbarch)->return_in_memory (type)) |
| 623 | { |
| 624 | if (readbuf) |
| 625 | { |
| 626 | ULONGEST addr; |
| 627 | regcache_raw_read_unsigned (regcache, ALPHA_V0_REGNUM, &addr); |
| 628 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
| 629 | } |
| 630 | |
| 631 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; |
| 632 | } |
| 633 | |
| 634 | if (readbuf) |
| 635 | alpha_extract_return_value (type, regcache, readbuf); |
| 636 | if (writebuf) |
| 637 | alpha_store_return_value (type, regcache, writebuf); |
| 638 | |
| 639 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 640 | } |
| 641 | |
| 642 | static int |
| 643 | alpha_return_in_memory_always (struct type *type) |
| 644 | { |
| 645 | return 1; |
| 646 | } |
| 647 | \f |
| 648 | |
| 649 | constexpr gdb_byte alpha_break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */ |
| 650 | |
| 651 | typedef BP_MANIPULATION (alpha_break_insn) alpha_breakpoint; |
| 652 | |
| 653 | \f |
| 654 | /* This returns the PC of the first insn after the prologue. |
| 655 | If we can't find the prologue, then return 0. */ |
| 656 | |
| 657 | CORE_ADDR |
| 658 | alpha_after_prologue (CORE_ADDR pc) |
| 659 | { |
| 660 | struct symtab_and_line sal; |
| 661 | CORE_ADDR func_addr, func_end; |
| 662 | |
| 663 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 664 | return 0; |
| 665 | |
| 666 | sal = find_pc_line (func_addr, 0); |
| 667 | if (sal.end < func_end) |
| 668 | return sal.end; |
| 669 | |
| 670 | /* The line after the prologue is after the end of the function. In this |
| 671 | case, tell the caller to find the prologue the hard way. */ |
| 672 | return 0; |
| 673 | } |
| 674 | |
| 675 | /* Read an instruction from memory at PC, looking through breakpoints. */ |
| 676 | |
| 677 | unsigned int |
| 678 | alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 679 | { |
| 680 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 681 | gdb_byte buf[ALPHA_INSN_SIZE]; |
| 682 | int res; |
| 683 | |
| 684 | res = target_read_memory (pc, buf, sizeof (buf)); |
| 685 | if (res != 0) |
| 686 | memory_error (TARGET_XFER_E_IO, pc); |
| 687 | return extract_unsigned_integer (buf, sizeof (buf), byte_order); |
| 688 | } |
| 689 | |
| 690 | /* To skip prologues, I use this predicate. Returns either PC itself |
| 691 | if the code at PC does not look like a function prologue; otherwise |
| 692 | returns an address that (if we're lucky) follows the prologue. If |
| 693 | LENIENT, then we must skip everything which is involved in setting |
| 694 | up the frame (it's OK to skip more, just so long as we don't skip |
| 695 | anything which might clobber the registers which are being saved. */ |
| 696 | |
| 697 | static CORE_ADDR |
| 698 | alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 699 | { |
| 700 | unsigned long inst; |
| 701 | int offset; |
| 702 | CORE_ADDR post_prologue_pc; |
| 703 | gdb_byte buf[ALPHA_INSN_SIZE]; |
| 704 | |
| 705 | /* Silently return the unaltered pc upon memory errors. |
| 706 | This could happen on OSF/1 if decode_line_1 tries to skip the |
| 707 | prologue for quickstarted shared library functions when the |
| 708 | shared library is not yet mapped in. |
| 709 | Reading target memory is slow over serial lines, so we perform |
| 710 | this check only if the target has shared libraries (which all |
| 711 | Alpha targets do). */ |
| 712 | if (target_read_memory (pc, buf, sizeof (buf))) |
| 713 | return pc; |
| 714 | |
| 715 | /* See if we can determine the end of the prologue via the symbol table. |
| 716 | If so, then return either PC, or the PC after the prologue, whichever |
| 717 | is greater. */ |
| 718 | |
| 719 | post_prologue_pc = alpha_after_prologue (pc); |
| 720 | if (post_prologue_pc != 0) |
| 721 | return std::max (pc, post_prologue_pc); |
| 722 | |
| 723 | /* Can't determine prologue from the symbol table, need to examine |
| 724 | instructions. */ |
| 725 | |
| 726 | /* Skip the typical prologue instructions. These are the stack adjustment |
| 727 | instruction and the instructions that save registers on the stack |
| 728 | or in the gcc frame. */ |
| 729 | for (offset = 0; offset < 100; offset += ALPHA_INSN_SIZE) |
| 730 | { |
| 731 | inst = alpha_read_insn (gdbarch, pc + offset); |
| 732 | |
| 733 | if ((inst & 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */ |
| 734 | continue; |
| 735 | if ((inst & 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */ |
| 736 | continue; |
| 737 | if ((inst & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ |
| 738 | continue; |
| 739 | if ((inst & 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */ |
| 740 | continue; |
| 741 | |
| 742 | if (((inst & 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */ |
| 743 | || (inst & 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */ |
| 744 | && (inst & 0x03e00000) != 0x03e00000) /* reg != $zero */ |
| 745 | continue; |
| 746 | |
| 747 | if (inst == 0x47de040f) /* bis sp,sp,fp */ |
| 748 | continue; |
| 749 | if (inst == 0x47fe040f) /* bis zero,sp,fp */ |
| 750 | continue; |
| 751 | |
| 752 | break; |
| 753 | } |
| 754 | return pc + offset; |
| 755 | } |
| 756 | |
| 757 | \f |
| 758 | static const int ldl_l_opcode = 0x2a; |
| 759 | static const int ldq_l_opcode = 0x2b; |
| 760 | static const int stl_c_opcode = 0x2e; |
| 761 | static const int stq_c_opcode = 0x2f; |
| 762 | |
| 763 | /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L |
| 764 | instruction and ending with a STL_C/STQ_C instruction. If such a sequence |
| 765 | is found, attempt to step through it. A breakpoint is placed at the end of |
| 766 | the sequence. */ |
| 767 | |
| 768 | static std::vector<CORE_ADDR> |
| 769 | alpha_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 770 | { |
| 771 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
| 772 | CORE_ADDR loc = pc; |
| 773 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ |
| 774 | unsigned int insn = alpha_read_insn (gdbarch, loc); |
| 775 | int insn_count; |
| 776 | int index; |
| 777 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ |
| 778 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ |
| 779 | int bc_insn_count = 0; /* Conditional branch instruction count. */ |
| 780 | |
| 781 | /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */ |
| 782 | if (INSN_OPCODE (insn) != ldl_l_opcode |
| 783 | && INSN_OPCODE (insn) != ldq_l_opcode) |
| 784 | return {}; |
| 785 | |
| 786 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" |
| 787 | instructions. */ |
| 788 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) |
| 789 | { |
| 790 | loc += ALPHA_INSN_SIZE; |
| 791 | insn = alpha_read_insn (gdbarch, loc); |
| 792 | |
| 793 | /* Assume that there is at most one branch in the atomic |
| 794 | sequence. If a branch is found, put a breakpoint in |
| 795 | its destination address. */ |
| 796 | if (INSN_OPCODE (insn) >= br_opcode) |
| 797 | { |
| 798 | int immediate = (insn & 0x001fffff) << 2; |
| 799 | |
| 800 | immediate = (immediate ^ 0x400000) - 0x400000; |
| 801 | |
| 802 | if (bc_insn_count >= 1) |
| 803 | return {}; /* More than one branch found, fallback |
| 804 | to the standard single-step code. */ |
| 805 | |
| 806 | breaks[1] = loc + ALPHA_INSN_SIZE + immediate; |
| 807 | |
| 808 | bc_insn_count++; |
| 809 | last_breakpoint++; |
| 810 | } |
| 811 | |
| 812 | if (INSN_OPCODE (insn) == stl_c_opcode |
| 813 | || INSN_OPCODE (insn) == stq_c_opcode) |
| 814 | break; |
| 815 | } |
| 816 | |
| 817 | /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */ |
| 818 | if (INSN_OPCODE (insn) != stl_c_opcode |
| 819 | && INSN_OPCODE (insn) != stq_c_opcode) |
| 820 | return {}; |
| 821 | |
| 822 | closing_insn = loc; |
| 823 | loc += ALPHA_INSN_SIZE; |
| 824 | |
| 825 | /* Insert a breakpoint right after the end of the atomic sequence. */ |
| 826 | breaks[0] = loc; |
| 827 | |
| 828 | /* Check for duplicated breakpoints. Check also for a breakpoint |
| 829 | placed (branch instruction's destination) anywhere in sequence. */ |
| 830 | if (last_breakpoint |
| 831 | && (breaks[1] == breaks[0] |
| 832 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) |
| 833 | last_breakpoint = 0; |
| 834 | |
| 835 | std::vector<CORE_ADDR> next_pcs; |
| 836 | |
| 837 | for (index = 0; index <= last_breakpoint; index++) |
| 838 | next_pcs.push_back (breaks[index]); |
| 839 | |
| 840 | return next_pcs; |
| 841 | } |
| 842 | |
| 843 | \f |
| 844 | /* Figure out where the longjmp will land. |
| 845 | We expect the first arg to be a pointer to the jmp_buf structure from |
| 846 | which we extract the PC (JB_PC) that we will land at. The PC is copied |
| 847 | into the "pc". This routine returns true on success. */ |
| 848 | |
| 849 | static int |
| 850 | alpha_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
| 851 | { |
| 852 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 853 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 854 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 855 | CORE_ADDR jb_addr; |
| 856 | gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; |
| 857 | |
| 858 | jb_addr = get_frame_register_unsigned (frame, ALPHA_A0_REGNUM); |
| 859 | |
| 860 | if (target_read_memory (jb_addr + (tdep->jb_pc * tdep->jb_elt_size), |
| 861 | raw_buffer, tdep->jb_elt_size)) |
| 862 | return 0; |
| 863 | |
| 864 | *pc = extract_unsigned_integer (raw_buffer, tdep->jb_elt_size, byte_order); |
| 865 | return 1; |
| 866 | } |
| 867 | |
| 868 | \f |
| 869 | /* Frame unwinder for signal trampolines. We use alpha tdep bits that |
| 870 | describe the location and shape of the sigcontext structure. After |
| 871 | that, all registers are in memory, so it's easy. */ |
| 872 | /* ??? Shouldn't we be able to do this generically, rather than with |
| 873 | OSABI data specific to Alpha? */ |
| 874 | |
| 875 | struct alpha_sigtramp_unwind_cache |
| 876 | { |
| 877 | CORE_ADDR sigcontext_addr; |
| 878 | }; |
| 879 | |
| 880 | static struct alpha_sigtramp_unwind_cache * |
| 881 | alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame, |
| 882 | void **this_prologue_cache) |
| 883 | { |
| 884 | struct alpha_sigtramp_unwind_cache *info; |
| 885 | struct gdbarch_tdep *tdep; |
| 886 | |
| 887 | if (*this_prologue_cache) |
| 888 | return (struct alpha_sigtramp_unwind_cache *) *this_prologue_cache; |
| 889 | |
| 890 | info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache); |
| 891 | *this_prologue_cache = info; |
| 892 | |
| 893 | tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
| 894 | info->sigcontext_addr = tdep->sigcontext_addr (this_frame); |
| 895 | |
| 896 | return info; |
| 897 | } |
| 898 | |
| 899 | /* Return the address of REGNUM in a sigtramp frame. Since this is |
| 900 | all arithmetic, it doesn't seem worthwhile to cache it. */ |
| 901 | |
| 902 | static CORE_ADDR |
| 903 | alpha_sigtramp_register_address (struct gdbarch *gdbarch, |
| 904 | CORE_ADDR sigcontext_addr, int regnum) |
| 905 | { |
| 906 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 907 | |
| 908 | if (regnum >= 0 && regnum < 32) |
| 909 | return sigcontext_addr + tdep->sc_regs_offset + regnum * 8; |
| 910 | else if (regnum >= ALPHA_FP0_REGNUM && regnum < ALPHA_FP0_REGNUM + 32) |
| 911 | return sigcontext_addr + tdep->sc_fpregs_offset + regnum * 8; |
| 912 | else if (regnum == ALPHA_PC_REGNUM) |
| 913 | return sigcontext_addr + tdep->sc_pc_offset; |
| 914 | |
| 915 | return 0; |
| 916 | } |
| 917 | |
| 918 | /* Given a GDB frame, determine the address of the calling function's |
| 919 | frame. This will be used to create a new GDB frame struct. */ |
| 920 | |
| 921 | static void |
| 922 | alpha_sigtramp_frame_this_id (struct frame_info *this_frame, |
| 923 | void **this_prologue_cache, |
| 924 | struct frame_id *this_id) |
| 925 | { |
| 926 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 927 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 928 | struct alpha_sigtramp_unwind_cache *info |
| 929 | = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); |
| 930 | CORE_ADDR stack_addr, code_addr; |
| 931 | |
| 932 | /* If the OSABI couldn't locate the sigcontext, give up. */ |
| 933 | if (info->sigcontext_addr == 0) |
| 934 | return; |
| 935 | |
| 936 | /* If we have dynamic signal trampolines, find their start. |
| 937 | If we do not, then we must assume there is a symbol record |
| 938 | that can provide the start address. */ |
| 939 | if (tdep->dynamic_sigtramp_offset) |
| 940 | { |
| 941 | int offset; |
| 942 | code_addr = get_frame_pc (this_frame); |
| 943 | offset = tdep->dynamic_sigtramp_offset (gdbarch, code_addr); |
| 944 | if (offset >= 0) |
| 945 | code_addr -= offset; |
| 946 | else |
| 947 | code_addr = 0; |
| 948 | } |
| 949 | else |
| 950 | code_addr = get_frame_func (this_frame); |
| 951 | |
| 952 | /* The stack address is trivially read from the sigcontext. */ |
| 953 | stack_addr = alpha_sigtramp_register_address (gdbarch, info->sigcontext_addr, |
| 954 | ALPHA_SP_REGNUM); |
| 955 | stack_addr = get_frame_memory_unsigned (this_frame, stack_addr, |
| 956 | ALPHA_REGISTER_SIZE); |
| 957 | |
| 958 | *this_id = frame_id_build (stack_addr, code_addr); |
| 959 | } |
| 960 | |
| 961 | /* Retrieve the value of REGNUM in FRAME. Don't give up! */ |
| 962 | |
| 963 | static struct value * |
| 964 | alpha_sigtramp_frame_prev_register (struct frame_info *this_frame, |
| 965 | void **this_prologue_cache, int regnum) |
| 966 | { |
| 967 | struct alpha_sigtramp_unwind_cache *info |
| 968 | = alpha_sigtramp_frame_unwind_cache (this_frame, this_prologue_cache); |
| 969 | CORE_ADDR addr; |
| 970 | |
| 971 | if (info->sigcontext_addr != 0) |
| 972 | { |
| 973 | /* All integer and fp registers are stored in memory. */ |
| 974 | addr = alpha_sigtramp_register_address (get_frame_arch (this_frame), |
| 975 | info->sigcontext_addr, regnum); |
| 976 | if (addr != 0) |
| 977 | return frame_unwind_got_memory (this_frame, regnum, addr); |
| 978 | } |
| 979 | |
| 980 | /* This extra register may actually be in the sigcontext, but our |
| 981 | current description of it in alpha_sigtramp_frame_unwind_cache |
| 982 | doesn't include it. Too bad. Fall back on whatever's in the |
| 983 | outer frame. */ |
| 984 | return frame_unwind_got_register (this_frame, regnum, regnum); |
| 985 | } |
| 986 | |
| 987 | static int |
| 988 | alpha_sigtramp_frame_sniffer (const struct frame_unwind *self, |
| 989 | struct frame_info *this_frame, |
| 990 | void **this_prologue_cache) |
| 991 | { |
| 992 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 993 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 994 | const char *name; |
| 995 | |
| 996 | /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead |
| 997 | look at tramp-frame.h and other simplier per-architecture |
| 998 | sigtramp unwinders. */ |
| 999 | |
| 1000 | /* We shouldn't even bother to try if the OSABI didn't register a |
| 1001 | sigcontext_addr handler or pc_in_sigtramp hander. */ |
| 1002 | if (gdbarch_tdep (gdbarch)->sigcontext_addr == NULL) |
| 1003 | return 0; |
| 1004 | if (gdbarch_tdep (gdbarch)->pc_in_sigtramp == NULL) |
| 1005 | return 0; |
| 1006 | |
| 1007 | /* Otherwise we should be in a signal frame. */ |
| 1008 | find_pc_partial_function (pc, &name, NULL, NULL); |
| 1009 | if (gdbarch_tdep (gdbarch)->pc_in_sigtramp (gdbarch, pc, name)) |
| 1010 | return 1; |
| 1011 | |
| 1012 | return 0; |
| 1013 | } |
| 1014 | |
| 1015 | static const struct frame_unwind alpha_sigtramp_frame_unwind = { |
| 1016 | SIGTRAMP_FRAME, |
| 1017 | default_frame_unwind_stop_reason, |
| 1018 | alpha_sigtramp_frame_this_id, |
| 1019 | alpha_sigtramp_frame_prev_register, |
| 1020 | NULL, |
| 1021 | alpha_sigtramp_frame_sniffer |
| 1022 | }; |
| 1023 | |
| 1024 | \f |
| 1025 | |
| 1026 | /* Heuristic_proc_start may hunt through the text section for a long |
| 1027 | time across a 2400 baud serial line. Allows the user to limit this |
| 1028 | search. */ |
| 1029 | static int heuristic_fence_post = 0; |
| 1030 | |
| 1031 | /* Attempt to locate the start of the function containing PC. We assume that |
| 1032 | the previous function ends with an about_to_return insn. Not foolproof by |
| 1033 | any means, since gcc is happy to put the epilogue in the middle of a |
| 1034 | function. But we're guessing anyway... */ |
| 1035 | |
| 1036 | static CORE_ADDR |
| 1037 | alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1038 | { |
| 1039 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1040 | CORE_ADDR last_non_nop = pc; |
| 1041 | CORE_ADDR fence = pc - heuristic_fence_post; |
| 1042 | CORE_ADDR orig_pc = pc; |
| 1043 | CORE_ADDR func; |
| 1044 | struct inferior *inf; |
| 1045 | |
| 1046 | if (pc == 0) |
| 1047 | return 0; |
| 1048 | |
| 1049 | /* First see if we can find the start of the function from minimal |
| 1050 | symbol information. This can succeed with a binary that doesn't |
| 1051 | have debug info, but hasn't been stripped. */ |
| 1052 | func = get_pc_function_start (pc); |
| 1053 | if (func) |
| 1054 | return func; |
| 1055 | |
| 1056 | if (heuristic_fence_post == -1 |
| 1057 | || fence < tdep->vm_min_address) |
| 1058 | fence = tdep->vm_min_address; |
| 1059 | |
| 1060 | /* Search back for previous return; also stop at a 0, which might be |
| 1061 | seen for instance before the start of a code section. Don't include |
| 1062 | nops, since this usually indicates padding between functions. */ |
| 1063 | for (pc -= ALPHA_INSN_SIZE; pc >= fence; pc -= ALPHA_INSN_SIZE) |
| 1064 | { |
| 1065 | unsigned int insn = alpha_read_insn (gdbarch, pc); |
| 1066 | switch (insn) |
| 1067 | { |
| 1068 | case 0: /* invalid insn */ |
| 1069 | case 0x6bfa8001: /* ret $31,($26),1 */ |
| 1070 | return last_non_nop; |
| 1071 | |
| 1072 | case 0x2ffe0000: /* unop: ldq_u $31,0($30) */ |
| 1073 | case 0x47ff041f: /* nop: bis $31,$31,$31 */ |
| 1074 | break; |
| 1075 | |
| 1076 | default: |
| 1077 | last_non_nop = pc; |
| 1078 | break; |
| 1079 | } |
| 1080 | } |
| 1081 | |
| 1082 | inf = current_inferior (); |
| 1083 | |
| 1084 | /* It's not clear to me why we reach this point when stopping quietly, |
| 1085 | but with this test, at least we don't print out warnings for every |
| 1086 | child forked (eg, on decstation). 22apr93 rich@cygnus.com. */ |
| 1087 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
| 1088 | { |
| 1089 | static int blurb_printed = 0; |
| 1090 | |
| 1091 | if (fence == tdep->vm_min_address) |
| 1092 | warning (_("Hit beginning of text section without finding \ |
| 1093 | enclosing function for address %s"), paddress (gdbarch, orig_pc)); |
| 1094 | else |
| 1095 | warning (_("Hit heuristic-fence-post without finding \ |
| 1096 | enclosing function for address %s"), paddress (gdbarch, orig_pc)); |
| 1097 | |
| 1098 | if (!blurb_printed) |
| 1099 | { |
| 1100 | printf_filtered (_("\ |
| 1101 | This warning occurs if you are debugging a function without any symbols\n\ |
| 1102 | (for example, in a stripped executable). In that case, you may wish to\n\ |
| 1103 | increase the size of the search with the `set heuristic-fence-post' command.\n\ |
| 1104 | \n\ |
| 1105 | Otherwise, you told GDB there was a function where there isn't one, or\n\ |
| 1106 | (more likely) you have encountered a bug in GDB.\n")); |
| 1107 | blurb_printed = 1; |
| 1108 | } |
| 1109 | } |
| 1110 | |
| 1111 | return 0; |
| 1112 | } |
| 1113 | |
| 1114 | /* Fallback alpha frame unwinder. Uses instruction scanning and knows |
| 1115 | something about the traditional layout of alpha stack frames. */ |
| 1116 | |
| 1117 | struct alpha_heuristic_unwind_cache |
| 1118 | { |
| 1119 | CORE_ADDR vfp; |
| 1120 | CORE_ADDR start_pc; |
| 1121 | struct trad_frame_saved_reg *saved_regs; |
| 1122 | int return_reg; |
| 1123 | }; |
| 1124 | |
| 1125 | /* If a probing loop sequence starts at PC, simulate it and compute |
| 1126 | FRAME_SIZE and PC after its execution. Otherwise, return with PC and |
| 1127 | FRAME_SIZE unchanged. */ |
| 1128 | |
| 1129 | static void |
| 1130 | alpha_heuristic_analyze_probing_loop (struct gdbarch *gdbarch, CORE_ADDR *pc, |
| 1131 | int *frame_size) |
| 1132 | { |
| 1133 | CORE_ADDR cur_pc = *pc; |
| 1134 | int cur_frame_size = *frame_size; |
| 1135 | int nb_of_iterations, reg_index, reg_probe; |
| 1136 | unsigned int insn; |
| 1137 | |
| 1138 | /* The following pattern is recognized as a probing loop: |
| 1139 | |
| 1140 | lda REG_INDEX,NB_OF_ITERATIONS |
| 1141 | lda REG_PROBE,<immediate>(sp) |
| 1142 | |
| 1143 | LOOP_START: |
| 1144 | stq zero,<immediate>(REG_PROBE) |
| 1145 | subq REG_INDEX,0x1,REG_INDEX |
| 1146 | lda REG_PROBE,<immediate>(REG_PROBE) |
| 1147 | bne REG_INDEX, LOOP_START |
| 1148 | |
| 1149 | lda sp,<immediate>(REG_PROBE) |
| 1150 | |
| 1151 | If anything different is found, the function returns without |
| 1152 | changing PC and FRAME_SIZE. Otherwise, PC will point immediately |
| 1153 | after this sequence, and FRAME_SIZE will be updated. */ |
| 1154 | |
| 1155 | /* lda REG_INDEX,NB_OF_ITERATIONS */ |
| 1156 | |
| 1157 | insn = alpha_read_insn (gdbarch, cur_pc); |
| 1158 | if (INSN_OPCODE (insn) != lda_opcode) |
| 1159 | return; |
| 1160 | reg_index = MEM_RA (insn); |
| 1161 | nb_of_iterations = MEM_DISP (insn); |
| 1162 | |
| 1163 | /* lda REG_PROBE,<immediate>(sp) */ |
| 1164 | |
| 1165 | cur_pc += ALPHA_INSN_SIZE; |
| 1166 | insn = alpha_read_insn (gdbarch, cur_pc); |
| 1167 | if (INSN_OPCODE (insn) != lda_opcode |
| 1168 | || MEM_RB (insn) != ALPHA_SP_REGNUM) |
| 1169 | return; |
| 1170 | reg_probe = MEM_RA (insn); |
| 1171 | cur_frame_size -= MEM_DISP (insn); |
| 1172 | |
| 1173 | /* stq zero,<immediate>(REG_PROBE) */ |
| 1174 | |
| 1175 | cur_pc += ALPHA_INSN_SIZE; |
| 1176 | insn = alpha_read_insn (gdbarch, cur_pc); |
| 1177 | if (INSN_OPCODE (insn) != stq_opcode |
| 1178 | || MEM_RA (insn) != 0x1f |
| 1179 | || MEM_RB (insn) != reg_probe) |
| 1180 | return; |
| 1181 | |
| 1182 | /* subq REG_INDEX,0x1,REG_INDEX */ |
| 1183 | |
| 1184 | cur_pc += ALPHA_INSN_SIZE; |
| 1185 | insn = alpha_read_insn (gdbarch, cur_pc); |
| 1186 | if (INSN_OPCODE (insn) != subq_opcode |
| 1187 | || !OPR_HAS_IMMEDIATE (insn) |
| 1188 | || OPR_FUNCTION (insn) != subq_function |
| 1189 | || OPR_LIT(insn) != 1 |
| 1190 | || OPR_RA (insn) != reg_index |
| 1191 | || OPR_RC (insn) != reg_index) |
| 1192 | return; |
| 1193 | |
| 1194 | /* lda REG_PROBE,<immediate>(REG_PROBE) */ |
| 1195 | |
| 1196 | cur_pc += ALPHA_INSN_SIZE; |
| 1197 | insn = alpha_read_insn (gdbarch, cur_pc); |
| 1198 | if (INSN_OPCODE (insn) != lda_opcode |
| 1199 | || MEM_RA (insn) != reg_probe |
| 1200 | || MEM_RB (insn) != reg_probe) |
| 1201 | return; |
| 1202 | cur_frame_size -= MEM_DISP (insn) * nb_of_iterations; |
| 1203 | |
| 1204 | /* bne REG_INDEX, LOOP_START */ |
| 1205 | |
| 1206 | cur_pc += ALPHA_INSN_SIZE; |
| 1207 | insn = alpha_read_insn (gdbarch, cur_pc); |
| 1208 | if (INSN_OPCODE (insn) != bne_opcode |
| 1209 | || MEM_RA (insn) != reg_index) |
| 1210 | return; |
| 1211 | |
| 1212 | /* lda sp,<immediate>(REG_PROBE) */ |
| 1213 | |
| 1214 | cur_pc += ALPHA_INSN_SIZE; |
| 1215 | insn = alpha_read_insn (gdbarch, cur_pc); |
| 1216 | if (INSN_OPCODE (insn) != lda_opcode |
| 1217 | || MEM_RA (insn) != ALPHA_SP_REGNUM |
| 1218 | || MEM_RB (insn) != reg_probe) |
| 1219 | return; |
| 1220 | cur_frame_size -= MEM_DISP (insn); |
| 1221 | |
| 1222 | *pc = cur_pc; |
| 1223 | *frame_size = cur_frame_size; |
| 1224 | } |
| 1225 | |
| 1226 | static struct alpha_heuristic_unwind_cache * |
| 1227 | alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame, |
| 1228 | void **this_prologue_cache, |
| 1229 | CORE_ADDR start_pc) |
| 1230 | { |
| 1231 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1232 | struct alpha_heuristic_unwind_cache *info; |
| 1233 | ULONGEST val; |
| 1234 | CORE_ADDR limit_pc, cur_pc; |
| 1235 | int frame_reg, frame_size, return_reg, reg; |
| 1236 | |
| 1237 | if (*this_prologue_cache) |
| 1238 | return (struct alpha_heuristic_unwind_cache *) *this_prologue_cache; |
| 1239 | |
| 1240 | info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache); |
| 1241 | *this_prologue_cache = info; |
| 1242 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1243 | |
| 1244 | limit_pc = get_frame_pc (this_frame); |
| 1245 | if (start_pc == 0) |
| 1246 | start_pc = alpha_heuristic_proc_start (gdbarch, limit_pc); |
| 1247 | info->start_pc = start_pc; |
| 1248 | |
| 1249 | frame_reg = ALPHA_SP_REGNUM; |
| 1250 | frame_size = 0; |
| 1251 | return_reg = -1; |
| 1252 | |
| 1253 | /* If we've identified a likely place to start, do code scanning. */ |
| 1254 | if (start_pc != 0) |
| 1255 | { |
| 1256 | /* Limit the forward search to 50 instructions. */ |
| 1257 | if (start_pc + 200 < limit_pc) |
| 1258 | limit_pc = start_pc + 200; |
| 1259 | |
| 1260 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += ALPHA_INSN_SIZE) |
| 1261 | { |
| 1262 | unsigned int word = alpha_read_insn (gdbarch, cur_pc); |
| 1263 | |
| 1264 | if ((word & 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */ |
| 1265 | { |
| 1266 | if (word & 0x8000) |
| 1267 | { |
| 1268 | /* Consider only the first stack allocation instruction |
| 1269 | to contain the static size of the frame. */ |
| 1270 | if (frame_size == 0) |
| 1271 | frame_size = (-word) & 0xffff; |
| 1272 | } |
| 1273 | else |
| 1274 | { |
| 1275 | /* Exit loop if a positive stack adjustment is found, which |
| 1276 | usually means that the stack cleanup code in the function |
| 1277 | epilogue is reached. */ |
| 1278 | break; |
| 1279 | } |
| 1280 | } |
| 1281 | else if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ |
| 1282 | { |
| 1283 | reg = (word & 0x03e00000) >> 21; |
| 1284 | |
| 1285 | /* Ignore this instruction if we have already encountered |
| 1286 | an instruction saving the same register earlier in the |
| 1287 | function code. The current instruction does not tell |
| 1288 | us where the original value upon function entry is saved. |
| 1289 | All it says is that the function we are scanning reused |
| 1290 | that register for some computation of its own, and is now |
| 1291 | saving its result. */ |
| 1292 | if (trad_frame_addr_p(info->saved_regs, reg)) |
| 1293 | continue; |
| 1294 | |
| 1295 | if (reg == 31) |
| 1296 | continue; |
| 1297 | |
| 1298 | /* Do not compute the address where the register was saved yet, |
| 1299 | because we don't know yet if the offset will need to be |
| 1300 | relative to $sp or $fp (we can not compute the address |
| 1301 | relative to $sp if $sp is updated during the execution of |
| 1302 | the current subroutine, for instance when doing some alloca). |
| 1303 | So just store the offset for the moment, and compute the |
| 1304 | address later when we know whether this frame has a frame |
| 1305 | pointer or not. */ |
| 1306 | /* Hack: temporarily add one, so that the offset is non-zero |
| 1307 | and we can tell which registers have save offsets below. */ |
| 1308 | info->saved_regs[reg].addr = (word & 0xffff) + 1; |
| 1309 | |
| 1310 | /* Starting with OSF/1-3.2C, the system libraries are shipped |
| 1311 | without local symbols, but they still contain procedure |
| 1312 | descriptors without a symbol reference. GDB is currently |
| 1313 | unable to find these procedure descriptors and uses |
| 1314 | heuristic_proc_desc instead. |
| 1315 | As some low level compiler support routines (__div*, __add*) |
| 1316 | use a non-standard return address register, we have to |
| 1317 | add some heuristics to determine the return address register, |
| 1318 | or stepping over these routines will fail. |
| 1319 | Usually the return address register is the first register |
| 1320 | saved on the stack, but assembler optimization might |
| 1321 | rearrange the register saves. |
| 1322 | So we recognize only a few registers (t7, t9, ra) within |
| 1323 | the procedure prologue as valid return address registers. |
| 1324 | If we encounter a return instruction, we extract the |
| 1325 | return address register from it. |
| 1326 | |
| 1327 | FIXME: Rewriting GDB to access the procedure descriptors, |
| 1328 | e.g. via the minimal symbol table, might obviate this |
| 1329 | hack. */ |
| 1330 | if (return_reg == -1 |
| 1331 | && cur_pc < (start_pc + 80) |
| 1332 | && (reg == ALPHA_T7_REGNUM |
| 1333 | || reg == ALPHA_T9_REGNUM |
| 1334 | || reg == ALPHA_RA_REGNUM)) |
| 1335 | return_reg = reg; |
| 1336 | } |
| 1337 | else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ |
| 1338 | return_reg = (word >> 16) & 0x1f; |
| 1339 | else if (word == 0x47de040f) /* bis sp,sp,fp */ |
| 1340 | frame_reg = ALPHA_GCC_FP_REGNUM; |
| 1341 | else if (word == 0x47fe040f) /* bis zero,sp,fp */ |
| 1342 | frame_reg = ALPHA_GCC_FP_REGNUM; |
| 1343 | |
| 1344 | alpha_heuristic_analyze_probing_loop (gdbarch, &cur_pc, &frame_size); |
| 1345 | } |
| 1346 | |
| 1347 | /* If we haven't found a valid return address register yet, keep |
| 1348 | searching in the procedure prologue. */ |
| 1349 | if (return_reg == -1) |
| 1350 | { |
| 1351 | while (cur_pc < (limit_pc + 80) && cur_pc < (start_pc + 80)) |
| 1352 | { |
| 1353 | unsigned int word = alpha_read_insn (gdbarch, cur_pc); |
| 1354 | |
| 1355 | if ((word & 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */ |
| 1356 | { |
| 1357 | reg = (word & 0x03e00000) >> 21; |
| 1358 | if (reg == ALPHA_T7_REGNUM |
| 1359 | || reg == ALPHA_T9_REGNUM |
| 1360 | || reg == ALPHA_RA_REGNUM) |
| 1361 | { |
| 1362 | return_reg = reg; |
| 1363 | break; |
| 1364 | } |
| 1365 | } |
| 1366 | else if ((word & 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */ |
| 1367 | { |
| 1368 | return_reg = (word >> 16) & 0x1f; |
| 1369 | break; |
| 1370 | } |
| 1371 | |
| 1372 | cur_pc += ALPHA_INSN_SIZE; |
| 1373 | } |
| 1374 | } |
| 1375 | } |
| 1376 | |
| 1377 | /* Failing that, do default to the customary RA. */ |
| 1378 | if (return_reg == -1) |
| 1379 | return_reg = ALPHA_RA_REGNUM; |
| 1380 | info->return_reg = return_reg; |
| 1381 | |
| 1382 | val = get_frame_register_unsigned (this_frame, frame_reg); |
| 1383 | info->vfp = val + frame_size; |
| 1384 | |
| 1385 | /* Convert offsets to absolute addresses. See above about adding |
| 1386 | one to the offsets to make all detected offsets non-zero. */ |
| 1387 | for (reg = 0; reg < ALPHA_NUM_REGS; ++reg) |
| 1388 | if (trad_frame_addr_p(info->saved_regs, reg)) |
| 1389 | info->saved_regs[reg].addr += val - 1; |
| 1390 | |
| 1391 | /* The stack pointer of the previous frame is computed by popping |
| 1392 | the current stack frame. */ |
| 1393 | if (!trad_frame_addr_p (info->saved_regs, ALPHA_SP_REGNUM)) |
| 1394 | trad_frame_set_value (info->saved_regs, ALPHA_SP_REGNUM, info->vfp); |
| 1395 | |
| 1396 | return info; |
| 1397 | } |
| 1398 | |
| 1399 | /* Given a GDB frame, determine the address of the calling function's |
| 1400 | frame. This will be used to create a new GDB frame struct. */ |
| 1401 | |
| 1402 | static void |
| 1403 | alpha_heuristic_frame_this_id (struct frame_info *this_frame, |
| 1404 | void **this_prologue_cache, |
| 1405 | struct frame_id *this_id) |
| 1406 | { |
| 1407 | struct alpha_heuristic_unwind_cache *info |
| 1408 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
| 1409 | |
| 1410 | *this_id = frame_id_build (info->vfp, info->start_pc); |
| 1411 | } |
| 1412 | |
| 1413 | /* Retrieve the value of REGNUM in FRAME. Don't give up! */ |
| 1414 | |
| 1415 | static struct value * |
| 1416 | alpha_heuristic_frame_prev_register (struct frame_info *this_frame, |
| 1417 | void **this_prologue_cache, int regnum) |
| 1418 | { |
| 1419 | struct alpha_heuristic_unwind_cache *info |
| 1420 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
| 1421 | |
| 1422 | /* The PC of the previous frame is stored in the link register of |
| 1423 | the current frame. Frob regnum so that we pull the value from |
| 1424 | the correct place. */ |
| 1425 | if (regnum == ALPHA_PC_REGNUM) |
| 1426 | regnum = info->return_reg; |
| 1427 | |
| 1428 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 1429 | } |
| 1430 | |
| 1431 | static const struct frame_unwind alpha_heuristic_frame_unwind = { |
| 1432 | NORMAL_FRAME, |
| 1433 | default_frame_unwind_stop_reason, |
| 1434 | alpha_heuristic_frame_this_id, |
| 1435 | alpha_heuristic_frame_prev_register, |
| 1436 | NULL, |
| 1437 | default_frame_sniffer |
| 1438 | }; |
| 1439 | |
| 1440 | static CORE_ADDR |
| 1441 | alpha_heuristic_frame_base_address (struct frame_info *this_frame, |
| 1442 | void **this_prologue_cache) |
| 1443 | { |
| 1444 | struct alpha_heuristic_unwind_cache *info |
| 1445 | = alpha_heuristic_frame_unwind_cache (this_frame, this_prologue_cache, 0); |
| 1446 | |
| 1447 | return info->vfp; |
| 1448 | } |
| 1449 | |
| 1450 | static const struct frame_base alpha_heuristic_frame_base = { |
| 1451 | &alpha_heuristic_frame_unwind, |
| 1452 | alpha_heuristic_frame_base_address, |
| 1453 | alpha_heuristic_frame_base_address, |
| 1454 | alpha_heuristic_frame_base_address |
| 1455 | }; |
| 1456 | |
| 1457 | /* Just like reinit_frame_cache, but with the right arguments to be |
| 1458 | callable as an sfunc. Used by the "set heuristic-fence-post" command. */ |
| 1459 | |
| 1460 | static void |
| 1461 | reinit_frame_cache_sfunc (const char *args, |
| 1462 | int from_tty, struct cmd_list_element *c) |
| 1463 | { |
| 1464 | reinit_frame_cache (); |
| 1465 | } |
| 1466 | \f |
| 1467 | /* Helper routines for alpha*-nat.c files to move register sets to and |
| 1468 | from core files. The UNIQUE pointer is allowed to be NULL, as most |
| 1469 | targets don't supply this value in their core files. */ |
| 1470 | |
| 1471 | void |
| 1472 | alpha_supply_int_regs (struct regcache *regcache, int regno, |
| 1473 | const void *r0_r30, const void *pc, const void *unique) |
| 1474 | { |
| 1475 | const gdb_byte *regs = (const gdb_byte *) r0_r30; |
| 1476 | int i; |
| 1477 | |
| 1478 | for (i = 0; i < 31; ++i) |
| 1479 | if (regno == i || regno == -1) |
| 1480 | regcache->raw_supply (i, regs + i * 8); |
| 1481 | |
| 1482 | if (regno == ALPHA_ZERO_REGNUM || regno == -1) |
| 1483 | { |
| 1484 | const gdb_byte zero[8] = { 0 }; |
| 1485 | |
| 1486 | regcache->raw_supply (ALPHA_ZERO_REGNUM, zero); |
| 1487 | } |
| 1488 | |
| 1489 | if (regno == ALPHA_PC_REGNUM || regno == -1) |
| 1490 | regcache->raw_supply (ALPHA_PC_REGNUM, pc); |
| 1491 | |
| 1492 | if (regno == ALPHA_UNIQUE_REGNUM || regno == -1) |
| 1493 | regcache->raw_supply (ALPHA_UNIQUE_REGNUM, unique); |
| 1494 | } |
| 1495 | |
| 1496 | void |
| 1497 | alpha_fill_int_regs (const struct regcache *regcache, |
| 1498 | int regno, void *r0_r30, void *pc, void *unique) |
| 1499 | { |
| 1500 | gdb_byte *regs = (gdb_byte *) r0_r30; |
| 1501 | int i; |
| 1502 | |
| 1503 | for (i = 0; i < 31; ++i) |
| 1504 | if (regno == i || regno == -1) |
| 1505 | regcache->raw_collect (i, regs + i * 8); |
| 1506 | |
| 1507 | if (regno == ALPHA_PC_REGNUM || regno == -1) |
| 1508 | regcache->raw_collect (ALPHA_PC_REGNUM, pc); |
| 1509 | |
| 1510 | if (unique && (regno == ALPHA_UNIQUE_REGNUM || regno == -1)) |
| 1511 | regcache->raw_collect (ALPHA_UNIQUE_REGNUM, unique); |
| 1512 | } |
| 1513 | |
| 1514 | void |
| 1515 | alpha_supply_fp_regs (struct regcache *regcache, int regno, |
| 1516 | const void *f0_f30, const void *fpcr) |
| 1517 | { |
| 1518 | const gdb_byte *regs = (const gdb_byte *) f0_f30; |
| 1519 | int i; |
| 1520 | |
| 1521 | for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) |
| 1522 | if (regno == i || regno == -1) |
| 1523 | regcache->raw_supply (i, regs + (i - ALPHA_FP0_REGNUM) * 8); |
| 1524 | |
| 1525 | if (regno == ALPHA_FPCR_REGNUM || regno == -1) |
| 1526 | regcache->raw_supply (ALPHA_FPCR_REGNUM, fpcr); |
| 1527 | } |
| 1528 | |
| 1529 | void |
| 1530 | alpha_fill_fp_regs (const struct regcache *regcache, |
| 1531 | int regno, void *f0_f30, void *fpcr) |
| 1532 | { |
| 1533 | gdb_byte *regs = (gdb_byte *) f0_f30; |
| 1534 | int i; |
| 1535 | |
| 1536 | for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) |
| 1537 | if (regno == i || regno == -1) |
| 1538 | regcache->raw_collect (i, regs + (i - ALPHA_FP0_REGNUM) * 8); |
| 1539 | |
| 1540 | if (regno == ALPHA_FPCR_REGNUM || regno == -1) |
| 1541 | regcache->raw_collect (ALPHA_FPCR_REGNUM, fpcr); |
| 1542 | } |
| 1543 | |
| 1544 | \f |
| 1545 | |
| 1546 | /* Return nonzero if the G_floating register value in REG is equal to |
| 1547 | zero for FP control instructions. */ |
| 1548 | |
| 1549 | static int |
| 1550 | fp_register_zero_p (LONGEST reg) |
| 1551 | { |
| 1552 | /* Check that all bits except the sign bit are zero. */ |
| 1553 | const LONGEST zero_mask = ((LONGEST) 1 << 63) ^ -1; |
| 1554 | |
| 1555 | return ((reg & zero_mask) == 0); |
| 1556 | } |
| 1557 | |
| 1558 | /* Return the value of the sign bit for the G_floating register |
| 1559 | value held in REG. */ |
| 1560 | |
| 1561 | static int |
| 1562 | fp_register_sign_bit (LONGEST reg) |
| 1563 | { |
| 1564 | const LONGEST sign_mask = (LONGEST) 1 << 63; |
| 1565 | |
| 1566 | return ((reg & sign_mask) != 0); |
| 1567 | } |
| 1568 | |
| 1569 | /* alpha_software_single_step() is called just before we want to resume |
| 1570 | the inferior, if we want to single-step it but there is no hardware |
| 1571 | or kernel single-step support (NetBSD on Alpha, for example). We find |
| 1572 | the target of the coming instruction and breakpoint it. */ |
| 1573 | |
| 1574 | static CORE_ADDR |
| 1575 | alpha_next_pc (struct regcache *regcache, CORE_ADDR pc) |
| 1576 | { |
| 1577 | struct gdbarch *gdbarch = regcache->arch (); |
| 1578 | unsigned int insn; |
| 1579 | unsigned int op; |
| 1580 | int regno; |
| 1581 | int offset; |
| 1582 | LONGEST rav; |
| 1583 | |
| 1584 | insn = alpha_read_insn (gdbarch, pc); |
| 1585 | |
| 1586 | /* Opcode is top 6 bits. */ |
| 1587 | op = (insn >> 26) & 0x3f; |
| 1588 | |
| 1589 | if (op == 0x1a) |
| 1590 | { |
| 1591 | /* Jump format: target PC is: |
| 1592 | RB & ~3 */ |
| 1593 | return (regcache_raw_get_unsigned (regcache, (insn >> 16) & 0x1f) & ~3); |
| 1594 | } |
| 1595 | |
| 1596 | if ((op & 0x30) == 0x30) |
| 1597 | { |
| 1598 | /* Branch format: target PC is: |
| 1599 | (new PC) + (4 * sext(displacement)) */ |
| 1600 | if (op == 0x30 /* BR */ |
| 1601 | || op == 0x34) /* BSR */ |
| 1602 | { |
| 1603 | branch_taken: |
| 1604 | offset = (insn & 0x001fffff); |
| 1605 | if (offset & 0x00100000) |
| 1606 | offset |= 0xffe00000; |
| 1607 | offset *= ALPHA_INSN_SIZE; |
| 1608 | return (pc + ALPHA_INSN_SIZE + offset); |
| 1609 | } |
| 1610 | |
| 1611 | /* Need to determine if branch is taken; read RA. */ |
| 1612 | regno = (insn >> 21) & 0x1f; |
| 1613 | switch (op) |
| 1614 | { |
| 1615 | case 0x31: /* FBEQ */ |
| 1616 | case 0x36: /* FBGE */ |
| 1617 | case 0x37: /* FBGT */ |
| 1618 | case 0x33: /* FBLE */ |
| 1619 | case 0x32: /* FBLT */ |
| 1620 | case 0x35: /* FBNE */ |
| 1621 | regno += gdbarch_fp0_regnum (gdbarch); |
| 1622 | } |
| 1623 | |
| 1624 | rav = regcache_raw_get_signed (regcache, regno); |
| 1625 | |
| 1626 | switch (op) |
| 1627 | { |
| 1628 | case 0x38: /* BLBC */ |
| 1629 | if ((rav & 1) == 0) |
| 1630 | goto branch_taken; |
| 1631 | break; |
| 1632 | case 0x3c: /* BLBS */ |
| 1633 | if (rav & 1) |
| 1634 | goto branch_taken; |
| 1635 | break; |
| 1636 | case 0x39: /* BEQ */ |
| 1637 | if (rav == 0) |
| 1638 | goto branch_taken; |
| 1639 | break; |
| 1640 | case 0x3d: /* BNE */ |
| 1641 | if (rav != 0) |
| 1642 | goto branch_taken; |
| 1643 | break; |
| 1644 | case 0x3a: /* BLT */ |
| 1645 | if (rav < 0) |
| 1646 | goto branch_taken; |
| 1647 | break; |
| 1648 | case 0x3b: /* BLE */ |
| 1649 | if (rav <= 0) |
| 1650 | goto branch_taken; |
| 1651 | break; |
| 1652 | case 0x3f: /* BGT */ |
| 1653 | if (rav > 0) |
| 1654 | goto branch_taken; |
| 1655 | break; |
| 1656 | case 0x3e: /* BGE */ |
| 1657 | if (rav >= 0) |
| 1658 | goto branch_taken; |
| 1659 | break; |
| 1660 | |
| 1661 | /* Floating point branches. */ |
| 1662 | |
| 1663 | case 0x31: /* FBEQ */ |
| 1664 | if (fp_register_zero_p (rav)) |
| 1665 | goto branch_taken; |
| 1666 | break; |
| 1667 | case 0x36: /* FBGE */ |
| 1668 | if (fp_register_sign_bit (rav) == 0 || fp_register_zero_p (rav)) |
| 1669 | goto branch_taken; |
| 1670 | break; |
| 1671 | case 0x37: /* FBGT */ |
| 1672 | if (fp_register_sign_bit (rav) == 0 && ! fp_register_zero_p (rav)) |
| 1673 | goto branch_taken; |
| 1674 | break; |
| 1675 | case 0x33: /* FBLE */ |
| 1676 | if (fp_register_sign_bit (rav) == 1 || fp_register_zero_p (rav)) |
| 1677 | goto branch_taken; |
| 1678 | break; |
| 1679 | case 0x32: /* FBLT */ |
| 1680 | if (fp_register_sign_bit (rav) == 1 && ! fp_register_zero_p (rav)) |
| 1681 | goto branch_taken; |
| 1682 | break; |
| 1683 | case 0x35: /* FBNE */ |
| 1684 | if (! fp_register_zero_p (rav)) |
| 1685 | goto branch_taken; |
| 1686 | break; |
| 1687 | } |
| 1688 | } |
| 1689 | |
| 1690 | /* Not a branch or branch not taken; target PC is: |
| 1691 | pc + 4 */ |
| 1692 | return (pc + ALPHA_INSN_SIZE); |
| 1693 | } |
| 1694 | |
| 1695 | std::vector<CORE_ADDR> |
| 1696 | alpha_software_single_step (struct regcache *regcache) |
| 1697 | { |
| 1698 | struct gdbarch *gdbarch = regcache->arch (); |
| 1699 | |
| 1700 | CORE_ADDR pc = regcache_read_pc (regcache); |
| 1701 | |
| 1702 | std::vector<CORE_ADDR> next_pcs |
| 1703 | = alpha_deal_with_atomic_sequence (gdbarch, pc); |
| 1704 | if (!next_pcs.empty ()) |
| 1705 | return next_pcs; |
| 1706 | |
| 1707 | CORE_ADDR next_pc = alpha_next_pc (regcache, pc); |
| 1708 | return {next_pc}; |
| 1709 | } |
| 1710 | |
| 1711 | \f |
| 1712 | /* Initialize the current architecture based on INFO. If possible, re-use an |
| 1713 | architecture from ARCHES, which is a list of architectures already created |
| 1714 | during this debugging session. |
| 1715 | |
| 1716 | Called e.g. at program startup, when reading a core file, and when reading |
| 1717 | a binary file. */ |
| 1718 | |
| 1719 | static struct gdbarch * |
| 1720 | alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1721 | { |
| 1722 | struct gdbarch_tdep *tdep; |
| 1723 | struct gdbarch *gdbarch; |
| 1724 | |
| 1725 | /* Find a candidate among extant architectures. */ |
| 1726 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1727 | if (arches != NULL) |
| 1728 | return arches->gdbarch; |
| 1729 | |
| 1730 | tdep = XCNEW (struct gdbarch_tdep); |
| 1731 | gdbarch = gdbarch_alloc (&info, tdep); |
| 1732 | |
| 1733 | /* Lowest text address. This is used by heuristic_proc_start() |
| 1734 | to decide when to stop looking. */ |
| 1735 | tdep->vm_min_address = (CORE_ADDR) 0x120000000LL; |
| 1736 | |
| 1737 | tdep->dynamic_sigtramp_offset = NULL; |
| 1738 | tdep->sigcontext_addr = NULL; |
| 1739 | tdep->sc_pc_offset = 2 * 8; |
| 1740 | tdep->sc_regs_offset = 4 * 8; |
| 1741 | tdep->sc_fpregs_offset = tdep->sc_regs_offset + 32 * 8 + 8; |
| 1742 | |
| 1743 | tdep->jb_pc = -1; /* longjmp support not enabled by default. */ |
| 1744 | |
| 1745 | tdep->return_in_memory = alpha_return_in_memory_always; |
| 1746 | |
| 1747 | /* Type sizes */ |
| 1748 | set_gdbarch_short_bit (gdbarch, 16); |
| 1749 | set_gdbarch_int_bit (gdbarch, 32); |
| 1750 | set_gdbarch_long_bit (gdbarch, 64); |
| 1751 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 1752 | set_gdbarch_wchar_bit (gdbarch, 64); |
| 1753 | set_gdbarch_wchar_signed (gdbarch, 0); |
| 1754 | set_gdbarch_float_bit (gdbarch, 32); |
| 1755 | set_gdbarch_double_bit (gdbarch, 64); |
| 1756 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 1757 | set_gdbarch_ptr_bit (gdbarch, 64); |
| 1758 | |
| 1759 | /* Register info */ |
| 1760 | set_gdbarch_num_regs (gdbarch, ALPHA_NUM_REGS); |
| 1761 | set_gdbarch_sp_regnum (gdbarch, ALPHA_SP_REGNUM); |
| 1762 | set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM); |
| 1763 | set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM); |
| 1764 | |
| 1765 | set_gdbarch_register_name (gdbarch, alpha_register_name); |
| 1766 | set_gdbarch_register_type (gdbarch, alpha_register_type); |
| 1767 | |
| 1768 | set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register); |
| 1769 | set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register); |
| 1770 | |
| 1771 | set_gdbarch_convert_register_p (gdbarch, alpha_convert_register_p); |
| 1772 | set_gdbarch_register_to_value (gdbarch, alpha_register_to_value); |
| 1773 | set_gdbarch_value_to_register (gdbarch, alpha_value_to_register); |
| 1774 | |
| 1775 | set_gdbarch_register_reggroup_p (gdbarch, alpha_register_reggroup_p); |
| 1776 | |
| 1777 | /* Prologue heuristics. */ |
| 1778 | set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue); |
| 1779 | |
| 1780 | /* Call info. */ |
| 1781 | |
| 1782 | set_gdbarch_return_value (gdbarch, alpha_return_value); |
| 1783 | |
| 1784 | /* Settings for calling functions in the inferior. */ |
| 1785 | set_gdbarch_push_dummy_call (gdbarch, alpha_push_dummy_call); |
| 1786 | |
| 1787 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1788 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
| 1789 | |
| 1790 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
| 1791 | alpha_breakpoint::kind_from_pc); |
| 1792 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, |
| 1793 | alpha_breakpoint::bp_from_kind); |
| 1794 | set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE); |
| 1795 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); |
| 1796 | |
| 1797 | /* Handles single stepping of atomic sequences. */ |
| 1798 | set_gdbarch_software_single_step (gdbarch, alpha_software_single_step); |
| 1799 | |
| 1800 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 1801 | gdbarch_init_osabi (info, gdbarch); |
| 1802 | |
| 1803 | /* Now that we have tuned the configuration, set a few final things |
| 1804 | based on what the OS ABI has told us. */ |
| 1805 | |
| 1806 | if (tdep->jb_pc >= 0) |
| 1807 | set_gdbarch_get_longjmp_target (gdbarch, alpha_get_longjmp_target); |
| 1808 | |
| 1809 | frame_unwind_append_unwinder (gdbarch, &alpha_sigtramp_frame_unwind); |
| 1810 | frame_unwind_append_unwinder (gdbarch, &alpha_heuristic_frame_unwind); |
| 1811 | |
| 1812 | frame_base_set_default (gdbarch, &alpha_heuristic_frame_base); |
| 1813 | |
| 1814 | return gdbarch; |
| 1815 | } |
| 1816 | |
| 1817 | void |
| 1818 | alpha_dwarf2_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
| 1819 | { |
| 1820 | dwarf2_append_unwinders (gdbarch); |
| 1821 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
| 1822 | } |
| 1823 | |
| 1824 | void |
| 1825 | _initialize_alpha_tdep (void) |
| 1826 | { |
| 1827 | |
| 1828 | gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL); |
| 1829 | |
| 1830 | /* Let the user set the fence post for heuristic_proc_start. */ |
| 1831 | |
| 1832 | /* We really would like to have both "0" and "unlimited" work, but |
| 1833 | command.c doesn't deal with that. So make it a var_zinteger |
| 1834 | because the user can always use "999999" or some such for unlimited. */ |
| 1835 | /* We need to throw away the frame cache when we set this, since it |
| 1836 | might change our ability to get backtraces. */ |
| 1837 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
| 1838 | &heuristic_fence_post, _("\ |
| 1839 | Set the distance searched for the start of a function."), _("\ |
| 1840 | Show the distance searched for the start of a function."), _("\ |
| 1841 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
| 1842 | program for the start of a function. This command sets the distance of the\n\ |
| 1843 | search. The only need to set it is when debugging a stripped executable."), |
| 1844 | reinit_frame_cache_sfunc, |
| 1845 | NULL, /* FIXME: i18n: The distance searched for |
| 1846 | the start of a function is \"%d\". */ |
| 1847 | &setlist, &showlist); |
| 1848 | } |