| 1 | /* Target-dependent code for AMD64. |
| 2 | |
| 3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
| 4 | |
| 5 | Contributed by Jiri Smid, SuSE Labs. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "opcode/i386.h" |
| 24 | #include "dis-asm.h" |
| 25 | #include "arch-utils.h" |
| 26 | #include "block.h" |
| 27 | #include "dummy-frame.h" |
| 28 | #include "frame.h" |
| 29 | #include "frame-base.h" |
| 30 | #include "frame-unwind.h" |
| 31 | #include "inferior.h" |
| 32 | #include "infrun.h" |
| 33 | #include "gdbcmd.h" |
| 34 | #include "gdbcore.h" |
| 35 | #include "objfiles.h" |
| 36 | #include "regcache.h" |
| 37 | #include "regset.h" |
| 38 | #include "symfile.h" |
| 39 | #include "disasm.h" |
| 40 | #include "exceptions.h" |
| 41 | #include "amd64-tdep.h" |
| 42 | #include "i387-tdep.h" |
| 43 | |
| 44 | #include "features/i386/amd64.c" |
| 45 | #include "features/i386/amd64-avx.c" |
| 46 | #include "features/i386/amd64-mpx.c" |
| 47 | #include "features/i386/amd64-avx512.c" |
| 48 | |
| 49 | #include "features/i386/x32.c" |
| 50 | #include "features/i386/x32-avx.c" |
| 51 | #include "features/i386/x32-avx512.c" |
| 52 | |
| 53 | #include "ax.h" |
| 54 | #include "ax-gdb.h" |
| 55 | |
| 56 | /* Note that the AMD64 architecture was previously known as x86-64. |
| 57 | The latter is (forever) engraved into the canonical system name as |
| 58 | returned by config.guess, and used as the name for the AMD64 port |
| 59 | of GNU/Linux. The BSD's have renamed their ports to amd64; they |
| 60 | don't like to shout. For GDB we prefer the amd64_-prefix over the |
| 61 | x86_64_-prefix since it's so much easier to type. */ |
| 62 | |
| 63 | /* Register information. */ |
| 64 | |
| 65 | static const char *amd64_register_names[] = |
| 66 | { |
| 67 | "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", |
| 68 | |
| 69 | /* %r8 is indeed register number 8. */ |
| 70 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 71 | "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", |
| 72 | |
| 73 | /* %st0 is register number 24. */ |
| 74 | "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", |
| 75 | "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", |
| 76 | |
| 77 | /* %xmm0 is register number 40. */ |
| 78 | "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", |
| 79 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", |
| 80 | "mxcsr", |
| 81 | }; |
| 82 | |
| 83 | static const char *amd64_ymm_names[] = |
| 84 | { |
| 85 | "ymm0", "ymm1", "ymm2", "ymm3", |
| 86 | "ymm4", "ymm5", "ymm6", "ymm7", |
| 87 | "ymm8", "ymm9", "ymm10", "ymm11", |
| 88 | "ymm12", "ymm13", "ymm14", "ymm15" |
| 89 | }; |
| 90 | |
| 91 | static const char *amd64_ymm_avx512_names[] = |
| 92 | { |
| 93 | "ymm16", "ymm17", "ymm18", "ymm19", |
| 94 | "ymm20", "ymm21", "ymm22", "ymm23", |
| 95 | "ymm24", "ymm25", "ymm26", "ymm27", |
| 96 | "ymm28", "ymm29", "ymm30", "ymm31" |
| 97 | }; |
| 98 | |
| 99 | static const char *amd64_ymmh_names[] = |
| 100 | { |
| 101 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", |
| 102 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", |
| 103 | "ymm8h", "ymm9h", "ymm10h", "ymm11h", |
| 104 | "ymm12h", "ymm13h", "ymm14h", "ymm15h" |
| 105 | }; |
| 106 | |
| 107 | static const char *amd64_ymmh_avx512_names[] = |
| 108 | { |
| 109 | "ymm16h", "ymm17h", "ymm18h", "ymm19h", |
| 110 | "ymm20h", "ymm21h", "ymm22h", "ymm23h", |
| 111 | "ymm24h", "ymm25h", "ymm26h", "ymm27h", |
| 112 | "ymm28h", "ymm29h", "ymm30h", "ymm31h" |
| 113 | }; |
| 114 | |
| 115 | static const char *amd64_mpx_names[] = |
| 116 | { |
| 117 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" |
| 118 | }; |
| 119 | |
| 120 | static const char *amd64_k_names[] = |
| 121 | { |
| 122 | "k0", "k1", "k2", "k3", |
| 123 | "k4", "k5", "k6", "k7" |
| 124 | }; |
| 125 | |
| 126 | static const char *amd64_zmmh_names[] = |
| 127 | { |
| 128 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", |
| 129 | "zmm4h", "zmm5h", "zmm6h", "zmm7h", |
| 130 | "zmm8h", "zmm9h", "zmm10h", "zmm11h", |
| 131 | "zmm12h", "zmm13h", "zmm14h", "zmm15h", |
| 132 | "zmm16h", "zmm17h", "zmm18h", "zmm19h", |
| 133 | "zmm20h", "zmm21h", "zmm22h", "zmm23h", |
| 134 | "zmm24h", "zmm25h", "zmm26h", "zmm27h", |
| 135 | "zmm28h", "zmm29h", "zmm30h", "zmm31h" |
| 136 | }; |
| 137 | |
| 138 | static const char *amd64_zmm_names[] = |
| 139 | { |
| 140 | "zmm0", "zmm1", "zmm2", "zmm3", |
| 141 | "zmm4", "zmm5", "zmm6", "zmm7", |
| 142 | "zmm8", "zmm9", "zmm10", "zmm11", |
| 143 | "zmm12", "zmm13", "zmm14", "zmm15", |
| 144 | "zmm16", "zmm17", "zmm18", "zmm19", |
| 145 | "zmm20", "zmm21", "zmm22", "zmm23", |
| 146 | "zmm24", "zmm25", "zmm26", "zmm27", |
| 147 | "zmm28", "zmm29", "zmm30", "zmm31" |
| 148 | }; |
| 149 | |
| 150 | static const char *amd64_xmm_avx512_names[] = { |
| 151 | "xmm16", "xmm17", "xmm18", "xmm19", |
| 152 | "xmm20", "xmm21", "xmm22", "xmm23", |
| 153 | "xmm24", "xmm25", "xmm26", "xmm27", |
| 154 | "xmm28", "xmm29", "xmm30", "xmm31" |
| 155 | }; |
| 156 | |
| 157 | /* DWARF Register Number Mapping as defined in the System V psABI, |
| 158 | section 3.6. */ |
| 159 | |
| 160 | static int amd64_dwarf_regmap[] = |
| 161 | { |
| 162 | /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ |
| 163 | AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, |
| 164 | AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, |
| 165 | AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, |
| 166 | |
| 167 | /* Frame Pointer Register RBP. */ |
| 168 | AMD64_RBP_REGNUM, |
| 169 | |
| 170 | /* Stack Pointer Register RSP. */ |
| 171 | AMD64_RSP_REGNUM, |
| 172 | |
| 173 | /* Extended Integer Registers 8 - 15. */ |
| 174 | AMD64_R8_REGNUM, /* %r8 */ |
| 175 | AMD64_R9_REGNUM, /* %r9 */ |
| 176 | AMD64_R10_REGNUM, /* %r10 */ |
| 177 | AMD64_R11_REGNUM, /* %r11 */ |
| 178 | AMD64_R12_REGNUM, /* %r12 */ |
| 179 | AMD64_R13_REGNUM, /* %r13 */ |
| 180 | AMD64_R14_REGNUM, /* %r14 */ |
| 181 | AMD64_R15_REGNUM, /* %r15 */ |
| 182 | |
| 183 | /* Return Address RA. Mapped to RIP. */ |
| 184 | AMD64_RIP_REGNUM, |
| 185 | |
| 186 | /* SSE Registers 0 - 7. */ |
| 187 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
| 188 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, |
| 189 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, |
| 190 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, |
| 191 | |
| 192 | /* Extended SSE Registers 8 - 15. */ |
| 193 | AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, |
| 194 | AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, |
| 195 | AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, |
| 196 | AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, |
| 197 | |
| 198 | /* Floating Point Registers 0-7. */ |
| 199 | AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, |
| 200 | AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, |
| 201 | AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, |
| 202 | AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, |
| 203 | |
| 204 | /* Control and Status Flags Register. */ |
| 205 | AMD64_EFLAGS_REGNUM, |
| 206 | |
| 207 | /* Selector Registers. */ |
| 208 | AMD64_ES_REGNUM, |
| 209 | AMD64_CS_REGNUM, |
| 210 | AMD64_SS_REGNUM, |
| 211 | AMD64_DS_REGNUM, |
| 212 | AMD64_FS_REGNUM, |
| 213 | AMD64_GS_REGNUM, |
| 214 | -1, |
| 215 | -1, |
| 216 | |
| 217 | /* Segment Base Address Registers. */ |
| 218 | -1, |
| 219 | -1, |
| 220 | -1, |
| 221 | -1, |
| 222 | |
| 223 | /* Special Selector Registers. */ |
| 224 | -1, |
| 225 | -1, |
| 226 | |
| 227 | /* Floating Point Control Registers. */ |
| 228 | AMD64_MXCSR_REGNUM, |
| 229 | AMD64_FCTRL_REGNUM, |
| 230 | AMD64_FSTAT_REGNUM |
| 231 | }; |
| 232 | |
| 233 | static const int amd64_dwarf_regmap_len = |
| 234 | (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); |
| 235 | |
| 236 | /* Convert DWARF register number REG to the appropriate register |
| 237 | number used by GDB. */ |
| 238 | |
| 239 | static int |
| 240 | amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 241 | { |
| 242 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 243 | int ymm0_regnum = tdep->ymm0_regnum; |
| 244 | int regnum = -1; |
| 245 | |
| 246 | if (reg >= 0 && reg < amd64_dwarf_regmap_len) |
| 247 | regnum = amd64_dwarf_regmap[reg]; |
| 248 | |
| 249 | if (regnum == -1) |
| 250 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
| 251 | else if (ymm0_regnum >= 0 |
| 252 | && i386_xmm_regnum_p (gdbarch, regnum)) |
| 253 | regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); |
| 254 | |
| 255 | return regnum; |
| 256 | } |
| 257 | |
| 258 | /* Map architectural register numbers to gdb register numbers. */ |
| 259 | |
| 260 | static const int amd64_arch_regmap[16] = |
| 261 | { |
| 262 | AMD64_RAX_REGNUM, /* %rax */ |
| 263 | AMD64_RCX_REGNUM, /* %rcx */ |
| 264 | AMD64_RDX_REGNUM, /* %rdx */ |
| 265 | AMD64_RBX_REGNUM, /* %rbx */ |
| 266 | AMD64_RSP_REGNUM, /* %rsp */ |
| 267 | AMD64_RBP_REGNUM, /* %rbp */ |
| 268 | AMD64_RSI_REGNUM, /* %rsi */ |
| 269 | AMD64_RDI_REGNUM, /* %rdi */ |
| 270 | AMD64_R8_REGNUM, /* %r8 */ |
| 271 | AMD64_R9_REGNUM, /* %r9 */ |
| 272 | AMD64_R10_REGNUM, /* %r10 */ |
| 273 | AMD64_R11_REGNUM, /* %r11 */ |
| 274 | AMD64_R12_REGNUM, /* %r12 */ |
| 275 | AMD64_R13_REGNUM, /* %r13 */ |
| 276 | AMD64_R14_REGNUM, /* %r14 */ |
| 277 | AMD64_R15_REGNUM /* %r15 */ |
| 278 | }; |
| 279 | |
| 280 | static const int amd64_arch_regmap_len = |
| 281 | (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); |
| 282 | |
| 283 | /* Convert architectural register number REG to the appropriate register |
| 284 | number used by GDB. */ |
| 285 | |
| 286 | static int |
| 287 | amd64_arch_reg_to_regnum (int reg) |
| 288 | { |
| 289 | gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len); |
| 290 | |
| 291 | return amd64_arch_regmap[reg]; |
| 292 | } |
| 293 | |
| 294 | /* Register names for byte pseudo-registers. */ |
| 295 | |
| 296 | static const char *amd64_byte_names[] = |
| 297 | { |
| 298 | "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", |
| 299 | "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", |
| 300 | "ah", "bh", "ch", "dh" |
| 301 | }; |
| 302 | |
| 303 | /* Number of lower byte registers. */ |
| 304 | #define AMD64_NUM_LOWER_BYTE_REGS 16 |
| 305 | |
| 306 | /* Register names for word pseudo-registers. */ |
| 307 | |
| 308 | static const char *amd64_word_names[] = |
| 309 | { |
| 310 | "ax", "bx", "cx", "dx", "si", "di", "bp", "", |
| 311 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" |
| 312 | }; |
| 313 | |
| 314 | /* Register names for dword pseudo-registers. */ |
| 315 | |
| 316 | static const char *amd64_dword_names[] = |
| 317 | { |
| 318 | "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", |
| 319 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", |
| 320 | "eip" |
| 321 | }; |
| 322 | |
| 323 | /* Return the name of register REGNUM. */ |
| 324 | |
| 325 | static const char * |
| 326 | amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
| 327 | { |
| 328 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 329 | if (i386_byte_regnum_p (gdbarch, regnum)) |
| 330 | return amd64_byte_names[regnum - tdep->al_regnum]; |
| 331 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
| 332 | return amd64_zmm_names[regnum - tdep->zmm0_regnum]; |
| 333 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
| 334 | return amd64_ymm_names[regnum - tdep->ymm0_regnum]; |
| 335 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
| 336 | return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum]; |
| 337 | else if (i386_word_regnum_p (gdbarch, regnum)) |
| 338 | return amd64_word_names[regnum - tdep->ax_regnum]; |
| 339 | else if (i386_dword_regnum_p (gdbarch, regnum)) |
| 340 | return amd64_dword_names[regnum - tdep->eax_regnum]; |
| 341 | else |
| 342 | return i386_pseudo_register_name (gdbarch, regnum); |
| 343 | } |
| 344 | |
| 345 | static struct value * |
| 346 | amd64_pseudo_register_read_value (struct gdbarch *gdbarch, |
| 347 | struct regcache *regcache, |
| 348 | int regnum) |
| 349 | { |
| 350 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
| 351 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 352 | enum register_status status; |
| 353 | struct value *result_value; |
| 354 | gdb_byte *buf; |
| 355 | |
| 356 | result_value = allocate_value (register_type (gdbarch, regnum)); |
| 357 | VALUE_LVAL (result_value) = lval_register; |
| 358 | VALUE_REGNUM (result_value) = regnum; |
| 359 | buf = value_contents_raw (result_value); |
| 360 | |
| 361 | if (i386_byte_regnum_p (gdbarch, regnum)) |
| 362 | { |
| 363 | int gpnum = regnum - tdep->al_regnum; |
| 364 | |
| 365 | /* Extract (always little endian). */ |
| 366 | if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) |
| 367 | { |
| 368 | /* Special handling for AH, BH, CH, DH. */ |
| 369 | status = regcache_raw_read (regcache, |
| 370 | gpnum - AMD64_NUM_LOWER_BYTE_REGS, |
| 371 | raw_buf); |
| 372 | if (status == REG_VALID) |
| 373 | memcpy (buf, raw_buf + 1, 1); |
| 374 | else |
| 375 | mark_value_bytes_unavailable (result_value, 0, |
| 376 | TYPE_LENGTH (value_type (result_value))); |
| 377 | } |
| 378 | else |
| 379 | { |
| 380 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
| 381 | if (status == REG_VALID) |
| 382 | memcpy (buf, raw_buf, 1); |
| 383 | else |
| 384 | mark_value_bytes_unavailable (result_value, 0, |
| 385 | TYPE_LENGTH (value_type (result_value))); |
| 386 | } |
| 387 | } |
| 388 | else if (i386_dword_regnum_p (gdbarch, regnum)) |
| 389 | { |
| 390 | int gpnum = regnum - tdep->eax_regnum; |
| 391 | /* Extract (always little endian). */ |
| 392 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
| 393 | if (status == REG_VALID) |
| 394 | memcpy (buf, raw_buf, 4); |
| 395 | else |
| 396 | mark_value_bytes_unavailable (result_value, 0, |
| 397 | TYPE_LENGTH (value_type (result_value))); |
| 398 | } |
| 399 | else |
| 400 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, |
| 401 | result_value); |
| 402 | |
| 403 | return result_value; |
| 404 | } |
| 405 | |
| 406 | static void |
| 407 | amd64_pseudo_register_write (struct gdbarch *gdbarch, |
| 408 | struct regcache *regcache, |
| 409 | int regnum, const gdb_byte *buf) |
| 410 | { |
| 411 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
| 412 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 413 | |
| 414 | if (i386_byte_regnum_p (gdbarch, regnum)) |
| 415 | { |
| 416 | int gpnum = regnum - tdep->al_regnum; |
| 417 | |
| 418 | if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) |
| 419 | { |
| 420 | /* Read ... AH, BH, CH, DH. */ |
| 421 | regcache_raw_read (regcache, |
| 422 | gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); |
| 423 | /* ... Modify ... (always little endian). */ |
| 424 | memcpy (raw_buf + 1, buf, 1); |
| 425 | /* ... Write. */ |
| 426 | regcache_raw_write (regcache, |
| 427 | gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); |
| 428 | } |
| 429 | else |
| 430 | { |
| 431 | /* Read ... */ |
| 432 | regcache_raw_read (regcache, gpnum, raw_buf); |
| 433 | /* ... Modify ... (always little endian). */ |
| 434 | memcpy (raw_buf, buf, 1); |
| 435 | /* ... Write. */ |
| 436 | regcache_raw_write (regcache, gpnum, raw_buf); |
| 437 | } |
| 438 | } |
| 439 | else if (i386_dword_regnum_p (gdbarch, regnum)) |
| 440 | { |
| 441 | int gpnum = regnum - tdep->eax_regnum; |
| 442 | |
| 443 | /* Read ... */ |
| 444 | regcache_raw_read (regcache, gpnum, raw_buf); |
| 445 | /* ... Modify ... (always little endian). */ |
| 446 | memcpy (raw_buf, buf, 4); |
| 447 | /* ... Write. */ |
| 448 | regcache_raw_write (regcache, gpnum, raw_buf); |
| 449 | } |
| 450 | else |
| 451 | i386_pseudo_register_write (gdbarch, regcache, regnum, buf); |
| 452 | } |
| 453 | |
| 454 | \f |
| 455 | |
| 456 | /* Register classes as defined in the psABI. */ |
| 457 | |
| 458 | enum amd64_reg_class |
| 459 | { |
| 460 | AMD64_INTEGER, |
| 461 | AMD64_SSE, |
| 462 | AMD64_SSEUP, |
| 463 | AMD64_X87, |
| 464 | AMD64_X87UP, |
| 465 | AMD64_COMPLEX_X87, |
| 466 | AMD64_NO_CLASS, |
| 467 | AMD64_MEMORY |
| 468 | }; |
| 469 | |
| 470 | /* Return the union class of CLASS1 and CLASS2. See the psABI for |
| 471 | details. */ |
| 472 | |
| 473 | static enum amd64_reg_class |
| 474 | amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) |
| 475 | { |
| 476 | /* Rule (a): If both classes are equal, this is the resulting class. */ |
| 477 | if (class1 == class2) |
| 478 | return class1; |
| 479 | |
| 480 | /* Rule (b): If one of the classes is NO_CLASS, the resulting class |
| 481 | is the other class. */ |
| 482 | if (class1 == AMD64_NO_CLASS) |
| 483 | return class2; |
| 484 | if (class2 == AMD64_NO_CLASS) |
| 485 | return class1; |
| 486 | |
| 487 | /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ |
| 488 | if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) |
| 489 | return AMD64_MEMORY; |
| 490 | |
| 491 | /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ |
| 492 | if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) |
| 493 | return AMD64_INTEGER; |
| 494 | |
| 495 | /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, |
| 496 | MEMORY is used as class. */ |
| 497 | if (class1 == AMD64_X87 || class1 == AMD64_X87UP |
| 498 | || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 |
| 499 | || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) |
| 500 | return AMD64_MEMORY; |
| 501 | |
| 502 | /* Rule (f): Otherwise class SSE is used. */ |
| 503 | return AMD64_SSE; |
| 504 | } |
| 505 | |
| 506 | static void amd64_classify (struct type *type, enum amd64_reg_class class[2]); |
| 507 | |
| 508 | /* Return non-zero if TYPE is a non-POD structure or union type. */ |
| 509 | |
| 510 | static int |
| 511 | amd64_non_pod_p (struct type *type) |
| 512 | { |
| 513 | /* ??? A class with a base class certainly isn't POD, but does this |
| 514 | catch all non-POD structure types? */ |
| 515 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) |
| 516 | return 1; |
| 517 | |
| 518 | return 0; |
| 519 | } |
| 520 | |
| 521 | /* Classify TYPE according to the rules for aggregate (structures and |
| 522 | arrays) and union types, and store the result in CLASS. */ |
| 523 | |
| 524 | static void |
| 525 | amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) |
| 526 | { |
| 527 | /* 1. If the size of an object is larger than two eightbytes, or in |
| 528 | C++, is a non-POD structure or union type, or contains |
| 529 | unaligned fields, it has class memory. */ |
| 530 | if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type)) |
| 531 | { |
| 532 | class[0] = class[1] = AMD64_MEMORY; |
| 533 | return; |
| 534 | } |
| 535 | |
| 536 | /* 2. Both eightbytes get initialized to class NO_CLASS. */ |
| 537 | class[0] = class[1] = AMD64_NO_CLASS; |
| 538 | |
| 539 | /* 3. Each field of an object is classified recursively so that |
| 540 | always two fields are considered. The resulting class is |
| 541 | calculated according to the classes of the fields in the |
| 542 | eightbyte: */ |
| 543 | |
| 544 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
| 545 | { |
| 546 | struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); |
| 547 | |
| 548 | /* All fields in an array have the same type. */ |
| 549 | amd64_classify (subtype, class); |
| 550 | if (TYPE_LENGTH (type) > 8 && class[1] == AMD64_NO_CLASS) |
| 551 | class[1] = class[0]; |
| 552 | } |
| 553 | else |
| 554 | { |
| 555 | int i; |
| 556 | |
| 557 | /* Structure or union. */ |
| 558 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 559 | || TYPE_CODE (type) == TYPE_CODE_UNION); |
| 560 | |
| 561 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 562 | { |
| 563 | struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); |
| 564 | int pos = TYPE_FIELD_BITPOS (type, i) / 64; |
| 565 | enum amd64_reg_class subclass[2]; |
| 566 | int bitsize = TYPE_FIELD_BITSIZE (type, i); |
| 567 | int endpos; |
| 568 | |
| 569 | if (bitsize == 0) |
| 570 | bitsize = TYPE_LENGTH (subtype) * 8; |
| 571 | endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64; |
| 572 | |
| 573 | /* Ignore static fields. */ |
| 574 | if (field_is_static (&TYPE_FIELD (type, i))) |
| 575 | continue; |
| 576 | |
| 577 | gdb_assert (pos == 0 || pos == 1); |
| 578 | |
| 579 | amd64_classify (subtype, subclass); |
| 580 | class[pos] = amd64_merge_classes (class[pos], subclass[0]); |
| 581 | if (bitsize <= 64 && pos == 0 && endpos == 1) |
| 582 | /* This is a bit of an odd case: We have a field that would |
| 583 | normally fit in one of the two eightbytes, except that |
| 584 | it is placed in a way that this field straddles them. |
| 585 | This has been seen with a structure containing an array. |
| 586 | |
| 587 | The ABI is a bit unclear in this case, but we assume that |
| 588 | this field's class (stored in subclass[0]) must also be merged |
| 589 | into class[1]. In other words, our field has a piece stored |
| 590 | in the second eight-byte, and thus its class applies to |
| 591 | the second eight-byte as well. |
| 592 | |
| 593 | In the case where the field length exceeds 8 bytes, |
| 594 | it should not be necessary to merge the field class |
| 595 | into class[1]. As LEN > 8, subclass[1] is necessarily |
| 596 | different from AMD64_NO_CLASS. If subclass[1] is equal |
| 597 | to subclass[0], then the normal class[1]/subclass[1] |
| 598 | merging will take care of everything. For subclass[1] |
| 599 | to be different from subclass[0], I can only see the case |
| 600 | where we have a SSE/SSEUP or X87/X87UP pair, which both |
| 601 | use up all 16 bytes of the aggregate, and are already |
| 602 | handled just fine (because each portion sits on its own |
| 603 | 8-byte). */ |
| 604 | class[1] = amd64_merge_classes (class[1], subclass[0]); |
| 605 | if (pos == 0) |
| 606 | class[1] = amd64_merge_classes (class[1], subclass[1]); |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | /* 4. Then a post merger cleanup is done: */ |
| 611 | |
| 612 | /* Rule (a): If one of the classes is MEMORY, the whole argument is |
| 613 | passed in memory. */ |
| 614 | if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) |
| 615 | class[0] = class[1] = AMD64_MEMORY; |
| 616 | |
| 617 | /* Rule (b): If SSEUP is not preceded by SSE, it is converted to |
| 618 | SSE. */ |
| 619 | if (class[0] == AMD64_SSEUP) |
| 620 | class[0] = AMD64_SSE; |
| 621 | if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) |
| 622 | class[1] = AMD64_SSE; |
| 623 | } |
| 624 | |
| 625 | /* Classify TYPE, and store the result in CLASS. */ |
| 626 | |
| 627 | static void |
| 628 | amd64_classify (struct type *type, enum amd64_reg_class class[2]) |
| 629 | { |
| 630 | enum type_code code = TYPE_CODE (type); |
| 631 | int len = TYPE_LENGTH (type); |
| 632 | |
| 633 | class[0] = class[1] = AMD64_NO_CLASS; |
| 634 | |
| 635 | /* Arguments of types (signed and unsigned) _Bool, char, short, int, |
| 636 | long, long long, and pointers are in the INTEGER class. Similarly, |
| 637 | range types, used by languages such as Ada, are also in the INTEGER |
| 638 | class. */ |
| 639 | if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM |
| 640 | || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE |
| 641 | || code == TYPE_CODE_CHAR |
| 642 | || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) |
| 643 | && (len == 1 || len == 2 || len == 4 || len == 8)) |
| 644 | class[0] = AMD64_INTEGER; |
| 645 | |
| 646 | /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 |
| 647 | are in class SSE. */ |
| 648 | else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) |
| 649 | && (len == 4 || len == 8)) |
| 650 | /* FIXME: __m64 . */ |
| 651 | class[0] = AMD64_SSE; |
| 652 | |
| 653 | /* Arguments of types __float128, _Decimal128 and __m128 are split into |
| 654 | two halves. The least significant ones belong to class SSE, the most |
| 655 | significant one to class SSEUP. */ |
| 656 | else if (code == TYPE_CODE_DECFLOAT && len == 16) |
| 657 | /* FIXME: __float128, __m128. */ |
| 658 | class[0] = AMD64_SSE, class[1] = AMD64_SSEUP; |
| 659 | |
| 660 | /* The 64-bit mantissa of arguments of type long double belongs to |
| 661 | class X87, the 16-bit exponent plus 6 bytes of padding belongs to |
| 662 | class X87UP. */ |
| 663 | else if (code == TYPE_CODE_FLT && len == 16) |
| 664 | /* Class X87 and X87UP. */ |
| 665 | class[0] = AMD64_X87, class[1] = AMD64_X87UP; |
| 666 | |
| 667 | /* Arguments of complex T where T is one of the types float or |
| 668 | double get treated as if they are implemented as: |
| 669 | |
| 670 | struct complexT { |
| 671 | T real; |
| 672 | T imag; |
| 673 | }; |
| 674 | |
| 675 | */ |
| 676 | else if (code == TYPE_CODE_COMPLEX && len == 8) |
| 677 | class[0] = AMD64_SSE; |
| 678 | else if (code == TYPE_CODE_COMPLEX && len == 16) |
| 679 | class[0] = class[1] = AMD64_SSE; |
| 680 | |
| 681 | /* A variable of type complex long double is classified as type |
| 682 | COMPLEX_X87. */ |
| 683 | else if (code == TYPE_CODE_COMPLEX && len == 32) |
| 684 | class[0] = AMD64_COMPLEX_X87; |
| 685 | |
| 686 | /* Aggregates. */ |
| 687 | else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT |
| 688 | || code == TYPE_CODE_UNION) |
| 689 | amd64_classify_aggregate (type, class); |
| 690 | } |
| 691 | |
| 692 | static enum return_value_convention |
| 693 | amd64_return_value (struct gdbarch *gdbarch, struct value *function, |
| 694 | struct type *type, struct regcache *regcache, |
| 695 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 696 | { |
| 697 | enum amd64_reg_class class[2]; |
| 698 | int len = TYPE_LENGTH (type); |
| 699 | static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; |
| 700 | static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; |
| 701 | int integer_reg = 0; |
| 702 | int sse_reg = 0; |
| 703 | int i; |
| 704 | |
| 705 | gdb_assert (!(readbuf && writebuf)); |
| 706 | |
| 707 | /* 1. Classify the return type with the classification algorithm. */ |
| 708 | amd64_classify (type, class); |
| 709 | |
| 710 | /* 2. If the type has class MEMORY, then the caller provides space |
| 711 | for the return value and passes the address of this storage in |
| 712 | %rdi as if it were the first argument to the function. In effect, |
| 713 | this address becomes a hidden first argument. |
| 714 | |
| 715 | On return %rax will contain the address that has been passed in |
| 716 | by the caller in %rdi. */ |
| 717 | if (class[0] == AMD64_MEMORY) |
| 718 | { |
| 719 | /* As indicated by the comment above, the ABI guarantees that we |
| 720 | can always find the return value just after the function has |
| 721 | returned. */ |
| 722 | |
| 723 | if (readbuf) |
| 724 | { |
| 725 | ULONGEST addr; |
| 726 | |
| 727 | regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); |
| 728 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
| 729 | } |
| 730 | |
| 731 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; |
| 732 | } |
| 733 | |
| 734 | /* 8. If the class is COMPLEX_X87, the real part of the value is |
| 735 | returned in %st0 and the imaginary part in %st1. */ |
| 736 | if (class[0] == AMD64_COMPLEX_X87) |
| 737 | { |
| 738 | if (readbuf) |
| 739 | { |
| 740 | regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf); |
| 741 | regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16); |
| 742 | } |
| 743 | |
| 744 | if (writebuf) |
| 745 | { |
| 746 | i387_return_value (gdbarch, regcache); |
| 747 | regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf); |
| 748 | regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16); |
| 749 | |
| 750 | /* Fix up the tag word such that both %st(0) and %st(1) are |
| 751 | marked as valid. */ |
| 752 | regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff); |
| 753 | } |
| 754 | |
| 755 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 756 | } |
| 757 | |
| 758 | gdb_assert (class[1] != AMD64_MEMORY); |
| 759 | gdb_assert (len <= 16); |
| 760 | |
| 761 | for (i = 0; len > 0; i++, len -= 8) |
| 762 | { |
| 763 | int regnum = -1; |
| 764 | int offset = 0; |
| 765 | |
| 766 | switch (class[i]) |
| 767 | { |
| 768 | case AMD64_INTEGER: |
| 769 | /* 3. If the class is INTEGER, the next available register |
| 770 | of the sequence %rax, %rdx is used. */ |
| 771 | regnum = integer_regnum[integer_reg++]; |
| 772 | break; |
| 773 | |
| 774 | case AMD64_SSE: |
| 775 | /* 4. If the class is SSE, the next available SSE register |
| 776 | of the sequence %xmm0, %xmm1 is used. */ |
| 777 | regnum = sse_regnum[sse_reg++]; |
| 778 | break; |
| 779 | |
| 780 | case AMD64_SSEUP: |
| 781 | /* 5. If the class is SSEUP, the eightbyte is passed in the |
| 782 | upper half of the last used SSE register. */ |
| 783 | gdb_assert (sse_reg > 0); |
| 784 | regnum = sse_regnum[sse_reg - 1]; |
| 785 | offset = 8; |
| 786 | break; |
| 787 | |
| 788 | case AMD64_X87: |
| 789 | /* 6. If the class is X87, the value is returned on the X87 |
| 790 | stack in %st0 as 80-bit x87 number. */ |
| 791 | regnum = AMD64_ST0_REGNUM; |
| 792 | if (writebuf) |
| 793 | i387_return_value (gdbarch, regcache); |
| 794 | break; |
| 795 | |
| 796 | case AMD64_X87UP: |
| 797 | /* 7. If the class is X87UP, the value is returned together |
| 798 | with the previous X87 value in %st0. */ |
| 799 | gdb_assert (i > 0 && class[0] == AMD64_X87); |
| 800 | regnum = AMD64_ST0_REGNUM; |
| 801 | offset = 8; |
| 802 | len = 2; |
| 803 | break; |
| 804 | |
| 805 | case AMD64_NO_CLASS: |
| 806 | continue; |
| 807 | |
| 808 | default: |
| 809 | gdb_assert (!"Unexpected register class."); |
| 810 | } |
| 811 | |
| 812 | gdb_assert (regnum != -1); |
| 813 | |
| 814 | if (readbuf) |
| 815 | regcache_raw_read_part (regcache, regnum, offset, min (len, 8), |
| 816 | readbuf + i * 8); |
| 817 | if (writebuf) |
| 818 | regcache_raw_write_part (regcache, regnum, offset, min (len, 8), |
| 819 | writebuf + i * 8); |
| 820 | } |
| 821 | |
| 822 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 823 | } |
| 824 | \f |
| 825 | |
| 826 | static CORE_ADDR |
| 827 | amd64_push_arguments (struct regcache *regcache, int nargs, |
| 828 | struct value **args, CORE_ADDR sp, int struct_return) |
| 829 | { |
| 830 | static int integer_regnum[] = |
| 831 | { |
| 832 | AMD64_RDI_REGNUM, /* %rdi */ |
| 833 | AMD64_RSI_REGNUM, /* %rsi */ |
| 834 | AMD64_RDX_REGNUM, /* %rdx */ |
| 835 | AMD64_RCX_REGNUM, /* %rcx */ |
| 836 | AMD64_R8_REGNUM, /* %r8 */ |
| 837 | AMD64_R9_REGNUM /* %r9 */ |
| 838 | }; |
| 839 | static int sse_regnum[] = |
| 840 | { |
| 841 | /* %xmm0 ... %xmm7 */ |
| 842 | AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, |
| 843 | AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, |
| 844 | AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, |
| 845 | AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, |
| 846 | }; |
| 847 | struct value **stack_args = alloca (nargs * sizeof (struct value *)); |
| 848 | int num_stack_args = 0; |
| 849 | int num_elements = 0; |
| 850 | int element = 0; |
| 851 | int integer_reg = 0; |
| 852 | int sse_reg = 0; |
| 853 | int i; |
| 854 | |
| 855 | /* Reserve a register for the "hidden" argument. */ |
| 856 | if (struct_return) |
| 857 | integer_reg++; |
| 858 | |
| 859 | for (i = 0; i < nargs; i++) |
| 860 | { |
| 861 | struct type *type = value_type (args[i]); |
| 862 | int len = TYPE_LENGTH (type); |
| 863 | enum amd64_reg_class class[2]; |
| 864 | int needed_integer_regs = 0; |
| 865 | int needed_sse_regs = 0; |
| 866 | int j; |
| 867 | |
| 868 | /* Classify argument. */ |
| 869 | amd64_classify (type, class); |
| 870 | |
| 871 | /* Calculate the number of integer and SSE registers needed for |
| 872 | this argument. */ |
| 873 | for (j = 0; j < 2; j++) |
| 874 | { |
| 875 | if (class[j] == AMD64_INTEGER) |
| 876 | needed_integer_regs++; |
| 877 | else if (class[j] == AMD64_SSE) |
| 878 | needed_sse_regs++; |
| 879 | } |
| 880 | |
| 881 | /* Check whether enough registers are available, and if the |
| 882 | argument should be passed in registers at all. */ |
| 883 | if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) |
| 884 | || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) |
| 885 | || (needed_integer_regs == 0 && needed_sse_regs == 0)) |
| 886 | { |
| 887 | /* The argument will be passed on the stack. */ |
| 888 | num_elements += ((len + 7) / 8); |
| 889 | stack_args[num_stack_args++] = args[i]; |
| 890 | } |
| 891 | else |
| 892 | { |
| 893 | /* The argument will be passed in registers. */ |
| 894 | const gdb_byte *valbuf = value_contents (args[i]); |
| 895 | gdb_byte buf[8]; |
| 896 | |
| 897 | gdb_assert (len <= 16); |
| 898 | |
| 899 | for (j = 0; len > 0; j++, len -= 8) |
| 900 | { |
| 901 | int regnum = -1; |
| 902 | int offset = 0; |
| 903 | |
| 904 | switch (class[j]) |
| 905 | { |
| 906 | case AMD64_INTEGER: |
| 907 | regnum = integer_regnum[integer_reg++]; |
| 908 | break; |
| 909 | |
| 910 | case AMD64_SSE: |
| 911 | regnum = sse_regnum[sse_reg++]; |
| 912 | break; |
| 913 | |
| 914 | case AMD64_SSEUP: |
| 915 | gdb_assert (sse_reg > 0); |
| 916 | regnum = sse_regnum[sse_reg - 1]; |
| 917 | offset = 8; |
| 918 | break; |
| 919 | |
| 920 | default: |
| 921 | gdb_assert (!"Unexpected register class."); |
| 922 | } |
| 923 | |
| 924 | gdb_assert (regnum != -1); |
| 925 | memset (buf, 0, sizeof buf); |
| 926 | memcpy (buf, valbuf + j * 8, min (len, 8)); |
| 927 | regcache_raw_write_part (regcache, regnum, offset, 8, buf); |
| 928 | } |
| 929 | } |
| 930 | } |
| 931 | |
| 932 | /* Allocate space for the arguments on the stack. */ |
| 933 | sp -= num_elements * 8; |
| 934 | |
| 935 | /* The psABI says that "The end of the input argument area shall be |
| 936 | aligned on a 16 byte boundary." */ |
| 937 | sp &= ~0xf; |
| 938 | |
| 939 | /* Write out the arguments to the stack. */ |
| 940 | for (i = 0; i < num_stack_args; i++) |
| 941 | { |
| 942 | struct type *type = value_type (stack_args[i]); |
| 943 | const gdb_byte *valbuf = value_contents (stack_args[i]); |
| 944 | int len = TYPE_LENGTH (type); |
| 945 | |
| 946 | write_memory (sp + element * 8, valbuf, len); |
| 947 | element += ((len + 7) / 8); |
| 948 | } |
| 949 | |
| 950 | /* The psABI says that "For calls that may call functions that use |
| 951 | varargs or stdargs (prototype-less calls or calls to functions |
| 952 | containing ellipsis (...) in the declaration) %al is used as |
| 953 | hidden argument to specify the number of SSE registers used. */ |
| 954 | regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); |
| 955 | return sp; |
| 956 | } |
| 957 | |
| 958 | static CORE_ADDR |
| 959 | amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 960 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 961 | int nargs, struct value **args, CORE_ADDR sp, |
| 962 | int struct_return, CORE_ADDR struct_addr) |
| 963 | { |
| 964 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 965 | gdb_byte buf[8]; |
| 966 | |
| 967 | /* Pass arguments. */ |
| 968 | sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); |
| 969 | |
| 970 | /* Pass "hidden" argument". */ |
| 971 | if (struct_return) |
| 972 | { |
| 973 | store_unsigned_integer (buf, 8, byte_order, struct_addr); |
| 974 | regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); |
| 975 | } |
| 976 | |
| 977 | /* Store return address. */ |
| 978 | sp -= 8; |
| 979 | store_unsigned_integer (buf, 8, byte_order, bp_addr); |
| 980 | write_memory (sp, buf, 8); |
| 981 | |
| 982 | /* Finally, update the stack pointer... */ |
| 983 | store_unsigned_integer (buf, 8, byte_order, sp); |
| 984 | regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); |
| 985 | |
| 986 | /* ...and fake a frame pointer. */ |
| 987 | regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); |
| 988 | |
| 989 | return sp + 16; |
| 990 | } |
| 991 | \f |
| 992 | /* Displaced instruction handling. */ |
| 993 | |
| 994 | /* A partially decoded instruction. |
| 995 | This contains enough details for displaced stepping purposes. */ |
| 996 | |
| 997 | struct amd64_insn |
| 998 | { |
| 999 | /* The number of opcode bytes. */ |
| 1000 | int opcode_len; |
| 1001 | /* The offset of the rex prefix or -1 if not present. */ |
| 1002 | int rex_offset; |
| 1003 | /* The offset to the first opcode byte. */ |
| 1004 | int opcode_offset; |
| 1005 | /* The offset to the modrm byte or -1 if not present. */ |
| 1006 | int modrm_offset; |
| 1007 | |
| 1008 | /* The raw instruction. */ |
| 1009 | gdb_byte *raw_insn; |
| 1010 | }; |
| 1011 | |
| 1012 | struct displaced_step_closure |
| 1013 | { |
| 1014 | /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ |
| 1015 | int tmp_used; |
| 1016 | int tmp_regno; |
| 1017 | ULONGEST tmp_save; |
| 1018 | |
| 1019 | /* Details of the instruction. */ |
| 1020 | struct amd64_insn insn_details; |
| 1021 | |
| 1022 | /* Amount of space allocated to insn_buf. */ |
| 1023 | int max_len; |
| 1024 | |
| 1025 | /* The possibly modified insn. |
| 1026 | This is a variable-length field. */ |
| 1027 | gdb_byte insn_buf[1]; |
| 1028 | }; |
| 1029 | |
| 1030 | /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with |
| 1031 | ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative, |
| 1032 | at which point delete these in favor of libopcodes' versions). */ |
| 1033 | |
| 1034 | static const unsigned char onebyte_has_modrm[256] = { |
| 1035 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 1036 | /* ------------------------------- */ |
| 1037 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ |
| 1038 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ |
| 1039 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ |
| 1040 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ |
| 1041 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ |
| 1042 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ |
| 1043 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ |
| 1044 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ |
| 1045 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ |
| 1046 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ |
| 1047 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ |
| 1048 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ |
| 1049 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ |
| 1050 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ |
| 1051 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ |
| 1052 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ |
| 1053 | /* ------------------------------- */ |
| 1054 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 1055 | }; |
| 1056 | |
| 1057 | static const unsigned char twobyte_has_modrm[256] = { |
| 1058 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 1059 | /* ------------------------------- */ |
| 1060 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
| 1061 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
| 1062 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
| 1063 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
| 1064 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
| 1065 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
| 1066 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ |
| 1067 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
| 1068 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
| 1069 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ |
| 1070 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
| 1071 | /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ |
| 1072 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
| 1073 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
| 1074 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
| 1075 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ |
| 1076 | /* ------------------------------- */ |
| 1077 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
| 1078 | }; |
| 1079 | |
| 1080 | static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp); |
| 1081 | |
| 1082 | static int |
| 1083 | rex_prefix_p (gdb_byte pfx) |
| 1084 | { |
| 1085 | return REX_PREFIX_P (pfx); |
| 1086 | } |
| 1087 | |
| 1088 | /* Skip the legacy instruction prefixes in INSN. |
| 1089 | We assume INSN is properly sentineled so we don't have to worry |
| 1090 | about falling off the end of the buffer. */ |
| 1091 | |
| 1092 | static gdb_byte * |
| 1093 | amd64_skip_prefixes (gdb_byte *insn) |
| 1094 | { |
| 1095 | while (1) |
| 1096 | { |
| 1097 | switch (*insn) |
| 1098 | { |
| 1099 | case DATA_PREFIX_OPCODE: |
| 1100 | case ADDR_PREFIX_OPCODE: |
| 1101 | case CS_PREFIX_OPCODE: |
| 1102 | case DS_PREFIX_OPCODE: |
| 1103 | case ES_PREFIX_OPCODE: |
| 1104 | case FS_PREFIX_OPCODE: |
| 1105 | case GS_PREFIX_OPCODE: |
| 1106 | case SS_PREFIX_OPCODE: |
| 1107 | case LOCK_PREFIX_OPCODE: |
| 1108 | case REPE_PREFIX_OPCODE: |
| 1109 | case REPNE_PREFIX_OPCODE: |
| 1110 | ++insn; |
| 1111 | continue; |
| 1112 | default: |
| 1113 | break; |
| 1114 | } |
| 1115 | break; |
| 1116 | } |
| 1117 | |
| 1118 | return insn; |
| 1119 | } |
| 1120 | |
| 1121 | /* Return an integer register (other than RSP) that is unused as an input |
| 1122 | operand in INSN. |
| 1123 | In order to not require adding a rex prefix if the insn doesn't already |
| 1124 | have one, the result is restricted to RAX ... RDI, sans RSP. |
| 1125 | The register numbering of the result follows architecture ordering, |
| 1126 | e.g. RDI = 7. */ |
| 1127 | |
| 1128 | static int |
| 1129 | amd64_get_unused_input_int_reg (const struct amd64_insn *details) |
| 1130 | { |
| 1131 | /* 1 bit for each reg */ |
| 1132 | int used_regs_mask = 0; |
| 1133 | |
| 1134 | /* There can be at most 3 int regs used as inputs in an insn, and we have |
| 1135 | 7 to choose from (RAX ... RDI, sans RSP). |
| 1136 | This allows us to take a conservative approach and keep things simple. |
| 1137 | E.g. By avoiding RAX, we don't have to specifically watch for opcodes |
| 1138 | that implicitly specify RAX. */ |
| 1139 | |
| 1140 | /* Avoid RAX. */ |
| 1141 | used_regs_mask |= 1 << EAX_REG_NUM; |
| 1142 | /* Similarily avoid RDX, implicit operand in divides. */ |
| 1143 | used_regs_mask |= 1 << EDX_REG_NUM; |
| 1144 | /* Avoid RSP. */ |
| 1145 | used_regs_mask |= 1 << ESP_REG_NUM; |
| 1146 | |
| 1147 | /* If the opcode is one byte long and there's no ModRM byte, |
| 1148 | assume the opcode specifies a register. */ |
| 1149 | if (details->opcode_len == 1 && details->modrm_offset == -1) |
| 1150 | used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7); |
| 1151 | |
| 1152 | /* Mark used regs in the modrm/sib bytes. */ |
| 1153 | if (details->modrm_offset != -1) |
| 1154 | { |
| 1155 | int modrm = details->raw_insn[details->modrm_offset]; |
| 1156 | int mod = MODRM_MOD_FIELD (modrm); |
| 1157 | int reg = MODRM_REG_FIELD (modrm); |
| 1158 | int rm = MODRM_RM_FIELD (modrm); |
| 1159 | int have_sib = mod != 3 && rm == 4; |
| 1160 | |
| 1161 | /* Assume the reg field of the modrm byte specifies a register. */ |
| 1162 | used_regs_mask |= 1 << reg; |
| 1163 | |
| 1164 | if (have_sib) |
| 1165 | { |
| 1166 | int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); |
| 1167 | int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); |
| 1168 | used_regs_mask |= 1 << base; |
| 1169 | used_regs_mask |= 1 << idx; |
| 1170 | } |
| 1171 | else |
| 1172 | { |
| 1173 | used_regs_mask |= 1 << rm; |
| 1174 | } |
| 1175 | } |
| 1176 | |
| 1177 | gdb_assert (used_regs_mask < 256); |
| 1178 | gdb_assert (used_regs_mask != 255); |
| 1179 | |
| 1180 | /* Finally, find a free reg. */ |
| 1181 | { |
| 1182 | int i; |
| 1183 | |
| 1184 | for (i = 0; i < 8; ++i) |
| 1185 | { |
| 1186 | if (! (used_regs_mask & (1 << i))) |
| 1187 | return i; |
| 1188 | } |
| 1189 | |
| 1190 | /* We shouldn't get here. */ |
| 1191 | internal_error (__FILE__, __LINE__, _("unable to find free reg")); |
| 1192 | } |
| 1193 | } |
| 1194 | |
| 1195 | /* Extract the details of INSN that we need. */ |
| 1196 | |
| 1197 | static void |
| 1198 | amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) |
| 1199 | { |
| 1200 | gdb_byte *start = insn; |
| 1201 | int need_modrm; |
| 1202 | |
| 1203 | details->raw_insn = insn; |
| 1204 | |
| 1205 | details->opcode_len = -1; |
| 1206 | details->rex_offset = -1; |
| 1207 | details->opcode_offset = -1; |
| 1208 | details->modrm_offset = -1; |
| 1209 | |
| 1210 | /* Skip legacy instruction prefixes. */ |
| 1211 | insn = amd64_skip_prefixes (insn); |
| 1212 | |
| 1213 | /* Skip REX instruction prefix. */ |
| 1214 | if (rex_prefix_p (*insn)) |
| 1215 | { |
| 1216 | details->rex_offset = insn - start; |
| 1217 | ++insn; |
| 1218 | } |
| 1219 | |
| 1220 | details->opcode_offset = insn - start; |
| 1221 | |
| 1222 | if (*insn == TWO_BYTE_OPCODE_ESCAPE) |
| 1223 | { |
| 1224 | /* Two or three-byte opcode. */ |
| 1225 | ++insn; |
| 1226 | need_modrm = twobyte_has_modrm[*insn]; |
| 1227 | |
| 1228 | /* Check for three-byte opcode. */ |
| 1229 | switch (*insn) |
| 1230 | { |
| 1231 | case 0x24: |
| 1232 | case 0x25: |
| 1233 | case 0x38: |
| 1234 | case 0x3a: |
| 1235 | case 0x7a: |
| 1236 | case 0x7b: |
| 1237 | ++insn; |
| 1238 | details->opcode_len = 3; |
| 1239 | break; |
| 1240 | default: |
| 1241 | details->opcode_len = 2; |
| 1242 | break; |
| 1243 | } |
| 1244 | } |
| 1245 | else |
| 1246 | { |
| 1247 | /* One-byte opcode. */ |
| 1248 | need_modrm = onebyte_has_modrm[*insn]; |
| 1249 | details->opcode_len = 1; |
| 1250 | } |
| 1251 | |
| 1252 | if (need_modrm) |
| 1253 | { |
| 1254 | ++insn; |
| 1255 | details->modrm_offset = insn - start; |
| 1256 | } |
| 1257 | } |
| 1258 | |
| 1259 | /* Update %rip-relative addressing in INSN. |
| 1260 | |
| 1261 | %rip-relative addressing only uses a 32-bit displacement. |
| 1262 | 32 bits is not enough to be guaranteed to cover the distance between where |
| 1263 | the real instruction is and where its copy is. |
| 1264 | Convert the insn to use base+disp addressing. |
| 1265 | We set base = pc + insn_length so we can leave disp unchanged. */ |
| 1266 | |
| 1267 | static void |
| 1268 | fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, |
| 1269 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs) |
| 1270 | { |
| 1271 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1272 | const struct amd64_insn *insn_details = &dsc->insn_details; |
| 1273 | int modrm_offset = insn_details->modrm_offset; |
| 1274 | gdb_byte *insn = insn_details->raw_insn + modrm_offset; |
| 1275 | CORE_ADDR rip_base; |
| 1276 | int32_t disp; |
| 1277 | int insn_length; |
| 1278 | int arch_tmp_regno, tmp_regno; |
| 1279 | ULONGEST orig_value; |
| 1280 | |
| 1281 | /* %rip+disp32 addressing mode, displacement follows ModRM byte. */ |
| 1282 | ++insn; |
| 1283 | |
| 1284 | /* Compute the rip-relative address. */ |
| 1285 | disp = extract_signed_integer (insn, sizeof (int32_t), byte_order); |
| 1286 | insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, |
| 1287 | dsc->max_len, from); |
| 1288 | rip_base = from + insn_length; |
| 1289 | |
| 1290 | /* We need a register to hold the address. |
| 1291 | Pick one not used in the insn. |
| 1292 | NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */ |
| 1293 | arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); |
| 1294 | tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); |
| 1295 | |
| 1296 | /* REX.B should be unset as we were using rip-relative addressing, |
| 1297 | but ensure it's unset anyway, tmp_regno is not r8-r15. */ |
| 1298 | if (insn_details->rex_offset != -1) |
| 1299 | dsc->insn_buf[insn_details->rex_offset] &= ~REX_B; |
| 1300 | |
| 1301 | regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); |
| 1302 | dsc->tmp_regno = tmp_regno; |
| 1303 | dsc->tmp_save = orig_value; |
| 1304 | dsc->tmp_used = 1; |
| 1305 | |
| 1306 | /* Convert the ModRM field to be base+disp. */ |
| 1307 | dsc->insn_buf[modrm_offset] &= ~0xc7; |
| 1308 | dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno; |
| 1309 | |
| 1310 | regcache_cooked_write_unsigned (regs, tmp_regno, rip_base); |
| 1311 | |
| 1312 | if (debug_displaced) |
| 1313 | fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n" |
| 1314 | "displaced: using temp reg %d, old value %s, new value %s\n", |
| 1315 | dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), |
| 1316 | paddress (gdbarch, rip_base)); |
| 1317 | } |
| 1318 | |
| 1319 | static void |
| 1320 | fixup_displaced_copy (struct gdbarch *gdbarch, |
| 1321 | struct displaced_step_closure *dsc, |
| 1322 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs) |
| 1323 | { |
| 1324 | const struct amd64_insn *details = &dsc->insn_details; |
| 1325 | |
| 1326 | if (details->modrm_offset != -1) |
| 1327 | { |
| 1328 | gdb_byte modrm = details->raw_insn[details->modrm_offset]; |
| 1329 | |
| 1330 | if ((modrm & 0xc7) == 0x05) |
| 1331 | { |
| 1332 | /* The insn uses rip-relative addressing. |
| 1333 | Deal with it. */ |
| 1334 | fixup_riprel (gdbarch, dsc, from, to, regs); |
| 1335 | } |
| 1336 | } |
| 1337 | } |
| 1338 | |
| 1339 | struct displaced_step_closure * |
| 1340 | amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, |
| 1341 | CORE_ADDR from, CORE_ADDR to, |
| 1342 | struct regcache *regs) |
| 1343 | { |
| 1344 | int len = gdbarch_max_insn_length (gdbarch); |
| 1345 | /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to |
| 1346 | continually watch for running off the end of the buffer. */ |
| 1347 | int fixup_sentinel_space = len; |
| 1348 | struct displaced_step_closure *dsc = |
| 1349 | xmalloc (sizeof (*dsc) + len + fixup_sentinel_space); |
| 1350 | gdb_byte *buf = &dsc->insn_buf[0]; |
| 1351 | struct amd64_insn *details = &dsc->insn_details; |
| 1352 | |
| 1353 | dsc->tmp_used = 0; |
| 1354 | dsc->max_len = len + fixup_sentinel_space; |
| 1355 | |
| 1356 | read_memory (from, buf, len); |
| 1357 | |
| 1358 | /* Set up the sentinel space so we don't have to worry about running |
| 1359 | off the end of the buffer. An excessive number of leading prefixes |
| 1360 | could otherwise cause this. */ |
| 1361 | memset (buf + len, 0, fixup_sentinel_space); |
| 1362 | |
| 1363 | amd64_get_insn_details (buf, details); |
| 1364 | |
| 1365 | /* GDB may get control back after the insn after the syscall. |
| 1366 | Presumably this is a kernel bug. |
| 1367 | If this is a syscall, make sure there's a nop afterwards. */ |
| 1368 | { |
| 1369 | int syscall_length; |
| 1370 | |
| 1371 | if (amd64_syscall_p (details, &syscall_length)) |
| 1372 | buf[details->opcode_offset + syscall_length] = NOP_OPCODE; |
| 1373 | } |
| 1374 | |
| 1375 | /* Modify the insn to cope with the address where it will be executed from. |
| 1376 | In particular, handle any rip-relative addressing. */ |
| 1377 | fixup_displaced_copy (gdbarch, dsc, from, to, regs); |
| 1378 | |
| 1379 | write_memory (to, buf, len); |
| 1380 | |
| 1381 | if (debug_displaced) |
| 1382 | { |
| 1383 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", |
| 1384 | paddress (gdbarch, from), paddress (gdbarch, to)); |
| 1385 | displaced_step_dump_bytes (gdb_stdlog, buf, len); |
| 1386 | } |
| 1387 | |
| 1388 | return dsc; |
| 1389 | } |
| 1390 | |
| 1391 | static int |
| 1392 | amd64_absolute_jmp_p (const struct amd64_insn *details) |
| 1393 | { |
| 1394 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; |
| 1395 | |
| 1396 | if (insn[0] == 0xff) |
| 1397 | { |
| 1398 | /* jump near, absolute indirect (/4) */ |
| 1399 | if ((insn[1] & 0x38) == 0x20) |
| 1400 | return 1; |
| 1401 | |
| 1402 | /* jump far, absolute indirect (/5) */ |
| 1403 | if ((insn[1] & 0x38) == 0x28) |
| 1404 | return 1; |
| 1405 | } |
| 1406 | |
| 1407 | return 0; |
| 1408 | } |
| 1409 | |
| 1410 | /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */ |
| 1411 | |
| 1412 | static int |
| 1413 | amd64_jmp_p (const struct amd64_insn *details) |
| 1414 | { |
| 1415 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; |
| 1416 | |
| 1417 | /* jump short, relative. */ |
| 1418 | if (insn[0] == 0xeb) |
| 1419 | return 1; |
| 1420 | |
| 1421 | /* jump near, relative. */ |
| 1422 | if (insn[0] == 0xe9) |
| 1423 | return 1; |
| 1424 | |
| 1425 | return amd64_absolute_jmp_p (details); |
| 1426 | } |
| 1427 | |
| 1428 | static int |
| 1429 | amd64_absolute_call_p (const struct amd64_insn *details) |
| 1430 | { |
| 1431 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; |
| 1432 | |
| 1433 | if (insn[0] == 0xff) |
| 1434 | { |
| 1435 | /* Call near, absolute indirect (/2) */ |
| 1436 | if ((insn[1] & 0x38) == 0x10) |
| 1437 | return 1; |
| 1438 | |
| 1439 | /* Call far, absolute indirect (/3) */ |
| 1440 | if ((insn[1] & 0x38) == 0x18) |
| 1441 | return 1; |
| 1442 | } |
| 1443 | |
| 1444 | return 0; |
| 1445 | } |
| 1446 | |
| 1447 | static int |
| 1448 | amd64_ret_p (const struct amd64_insn *details) |
| 1449 | { |
| 1450 | /* NOTE: gcc can emit "repz ; ret". */ |
| 1451 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; |
| 1452 | |
| 1453 | switch (insn[0]) |
| 1454 | { |
| 1455 | case 0xc2: /* ret near, pop N bytes */ |
| 1456 | case 0xc3: /* ret near */ |
| 1457 | case 0xca: /* ret far, pop N bytes */ |
| 1458 | case 0xcb: /* ret far */ |
| 1459 | case 0xcf: /* iret */ |
| 1460 | return 1; |
| 1461 | |
| 1462 | default: |
| 1463 | return 0; |
| 1464 | } |
| 1465 | } |
| 1466 | |
| 1467 | static int |
| 1468 | amd64_call_p (const struct amd64_insn *details) |
| 1469 | { |
| 1470 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; |
| 1471 | |
| 1472 | if (amd64_absolute_call_p (details)) |
| 1473 | return 1; |
| 1474 | |
| 1475 | /* call near, relative */ |
| 1476 | if (insn[0] == 0xe8) |
| 1477 | return 1; |
| 1478 | |
| 1479 | return 0; |
| 1480 | } |
| 1481 | |
| 1482 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
| 1483 | length in bytes. Otherwise, return zero. */ |
| 1484 | |
| 1485 | static int |
| 1486 | amd64_syscall_p (const struct amd64_insn *details, int *lengthp) |
| 1487 | { |
| 1488 | const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; |
| 1489 | |
| 1490 | if (insn[0] == 0x0f && insn[1] == 0x05) |
| 1491 | { |
| 1492 | *lengthp = 2; |
| 1493 | return 1; |
| 1494 | } |
| 1495 | |
| 1496 | return 0; |
| 1497 | } |
| 1498 | |
| 1499 | /* Classify the instruction at ADDR using PRED. |
| 1500 | Throw an error if the memory can't be read. */ |
| 1501 | |
| 1502 | static int |
| 1503 | amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr, |
| 1504 | int (*pred) (const struct amd64_insn *)) |
| 1505 | { |
| 1506 | struct amd64_insn details; |
| 1507 | gdb_byte *buf; |
| 1508 | int len, classification; |
| 1509 | |
| 1510 | len = gdbarch_max_insn_length (gdbarch); |
| 1511 | buf = alloca (len); |
| 1512 | |
| 1513 | read_code (addr, buf, len); |
| 1514 | amd64_get_insn_details (buf, &details); |
| 1515 | |
| 1516 | classification = pred (&details); |
| 1517 | |
| 1518 | return classification; |
| 1519 | } |
| 1520 | |
| 1521 | /* The gdbarch insn_is_call method. */ |
| 1522 | |
| 1523 | static int |
| 1524 | amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 1525 | { |
| 1526 | return amd64_classify_insn_at (gdbarch, addr, amd64_call_p); |
| 1527 | } |
| 1528 | |
| 1529 | /* The gdbarch insn_is_ret method. */ |
| 1530 | |
| 1531 | static int |
| 1532 | amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 1533 | { |
| 1534 | return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p); |
| 1535 | } |
| 1536 | |
| 1537 | /* The gdbarch insn_is_jump method. */ |
| 1538 | |
| 1539 | static int |
| 1540 | amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 1541 | { |
| 1542 | return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p); |
| 1543 | } |
| 1544 | |
| 1545 | /* Fix up the state of registers and memory after having single-stepped |
| 1546 | a displaced instruction. */ |
| 1547 | |
| 1548 | void |
| 1549 | amd64_displaced_step_fixup (struct gdbarch *gdbarch, |
| 1550 | struct displaced_step_closure *dsc, |
| 1551 | CORE_ADDR from, CORE_ADDR to, |
| 1552 | struct regcache *regs) |
| 1553 | { |
| 1554 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1555 | /* The offset we applied to the instruction's address. */ |
| 1556 | ULONGEST insn_offset = to - from; |
| 1557 | gdb_byte *insn = dsc->insn_buf; |
| 1558 | const struct amd64_insn *insn_details = &dsc->insn_details; |
| 1559 | |
| 1560 | if (debug_displaced) |
| 1561 | fprintf_unfiltered (gdb_stdlog, |
| 1562 | "displaced: fixup (%s, %s), " |
| 1563 | "insn = 0x%02x 0x%02x ...\n", |
| 1564 | paddress (gdbarch, from), paddress (gdbarch, to), |
| 1565 | insn[0], insn[1]); |
| 1566 | |
| 1567 | /* If we used a tmp reg, restore it. */ |
| 1568 | |
| 1569 | if (dsc->tmp_used) |
| 1570 | { |
| 1571 | if (debug_displaced) |
| 1572 | fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n", |
| 1573 | dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); |
| 1574 | regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); |
| 1575 | } |
| 1576 | |
| 1577 | /* The list of issues to contend with here is taken from |
| 1578 | resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28. |
| 1579 | Yay for Free Software! */ |
| 1580 | |
| 1581 | /* Relocate the %rip back to the program's instruction stream, |
| 1582 | if necessary. */ |
| 1583 | |
| 1584 | /* Except in the case of absolute or indirect jump or call |
| 1585 | instructions, or a return instruction, the new rip is relative to |
| 1586 | the displaced instruction; make it relative to the original insn. |
| 1587 | Well, signal handler returns don't need relocation either, but we use the |
| 1588 | value of %rip to recognize those; see below. */ |
| 1589 | if (! amd64_absolute_jmp_p (insn_details) |
| 1590 | && ! amd64_absolute_call_p (insn_details) |
| 1591 | && ! amd64_ret_p (insn_details)) |
| 1592 | { |
| 1593 | ULONGEST orig_rip; |
| 1594 | int insn_len; |
| 1595 | |
| 1596 | regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip); |
| 1597 | |
| 1598 | /* A signal trampoline system call changes the %rip, resuming |
| 1599 | execution of the main program after the signal handler has |
| 1600 | returned. That makes them like 'return' instructions; we |
| 1601 | shouldn't relocate %rip. |
| 1602 | |
| 1603 | But most system calls don't, and we do need to relocate %rip. |
| 1604 | |
| 1605 | Our heuristic for distinguishing these cases: if stepping |
| 1606 | over the system call instruction left control directly after |
| 1607 | the instruction, the we relocate --- control almost certainly |
| 1608 | doesn't belong in the displaced copy. Otherwise, we assume |
| 1609 | the instruction has put control where it belongs, and leave |
| 1610 | it unrelocated. Goodness help us if there are PC-relative |
| 1611 | system calls. */ |
| 1612 | if (amd64_syscall_p (insn_details, &insn_len) |
| 1613 | && orig_rip != to + insn_len |
| 1614 | /* GDB can get control back after the insn after the syscall. |
| 1615 | Presumably this is a kernel bug. |
| 1616 | Fixup ensures its a nop, we add one to the length for it. */ |
| 1617 | && orig_rip != to + insn_len + 1) |
| 1618 | { |
| 1619 | if (debug_displaced) |
| 1620 | fprintf_unfiltered (gdb_stdlog, |
| 1621 | "displaced: syscall changed %%rip; " |
| 1622 | "not relocating\n"); |
| 1623 | } |
| 1624 | else |
| 1625 | { |
| 1626 | ULONGEST rip = orig_rip - insn_offset; |
| 1627 | |
| 1628 | /* If we just stepped over a breakpoint insn, we don't backup |
| 1629 | the pc on purpose; this is to match behaviour without |
| 1630 | stepping. */ |
| 1631 | |
| 1632 | regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip); |
| 1633 | |
| 1634 | if (debug_displaced) |
| 1635 | fprintf_unfiltered (gdb_stdlog, |
| 1636 | "displaced: " |
| 1637 | "relocated %%rip from %s to %s\n", |
| 1638 | paddress (gdbarch, orig_rip), |
| 1639 | paddress (gdbarch, rip)); |
| 1640 | } |
| 1641 | } |
| 1642 | |
| 1643 | /* If the instruction was PUSHFL, then the TF bit will be set in the |
| 1644 | pushed value, and should be cleared. We'll leave this for later, |
| 1645 | since GDB already messes up the TF flag when stepping over a |
| 1646 | pushfl. */ |
| 1647 | |
| 1648 | /* If the instruction was a call, the return address now atop the |
| 1649 | stack is the address following the copied instruction. We need |
| 1650 | to make it the address following the original instruction. */ |
| 1651 | if (amd64_call_p (insn_details)) |
| 1652 | { |
| 1653 | ULONGEST rsp; |
| 1654 | ULONGEST retaddr; |
| 1655 | const ULONGEST retaddr_len = 8; |
| 1656 | |
| 1657 | regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); |
| 1658 | retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); |
| 1659 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
| 1660 | write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); |
| 1661 | |
| 1662 | if (debug_displaced) |
| 1663 | fprintf_unfiltered (gdb_stdlog, |
| 1664 | "displaced: relocated return addr at %s " |
| 1665 | "to %s\n", |
| 1666 | paddress (gdbarch, rsp), |
| 1667 | paddress (gdbarch, retaddr)); |
| 1668 | } |
| 1669 | } |
| 1670 | |
| 1671 | /* If the instruction INSN uses RIP-relative addressing, return the |
| 1672 | offset into the raw INSN where the displacement to be adjusted is |
| 1673 | found. Returns 0 if the instruction doesn't use RIP-relative |
| 1674 | addressing. */ |
| 1675 | |
| 1676 | static int |
| 1677 | rip_relative_offset (struct amd64_insn *insn) |
| 1678 | { |
| 1679 | if (insn->modrm_offset != -1) |
| 1680 | { |
| 1681 | gdb_byte modrm = insn->raw_insn[insn->modrm_offset]; |
| 1682 | |
| 1683 | if ((modrm & 0xc7) == 0x05) |
| 1684 | { |
| 1685 | /* The displacement is found right after the ModRM byte. */ |
| 1686 | return insn->modrm_offset + 1; |
| 1687 | } |
| 1688 | } |
| 1689 | |
| 1690 | return 0; |
| 1691 | } |
| 1692 | |
| 1693 | static void |
| 1694 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) |
| 1695 | { |
| 1696 | target_write_memory (*to, buf, len); |
| 1697 | *to += len; |
| 1698 | } |
| 1699 | |
| 1700 | static void |
| 1701 | amd64_relocate_instruction (struct gdbarch *gdbarch, |
| 1702 | CORE_ADDR *to, CORE_ADDR oldloc) |
| 1703 | { |
| 1704 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1705 | int len = gdbarch_max_insn_length (gdbarch); |
| 1706 | /* Extra space for sentinels. */ |
| 1707 | int fixup_sentinel_space = len; |
| 1708 | gdb_byte *buf = xmalloc (len + fixup_sentinel_space); |
| 1709 | struct amd64_insn insn_details; |
| 1710 | int offset = 0; |
| 1711 | LONGEST rel32, newrel; |
| 1712 | gdb_byte *insn; |
| 1713 | int insn_length; |
| 1714 | |
| 1715 | read_memory (oldloc, buf, len); |
| 1716 | |
| 1717 | /* Set up the sentinel space so we don't have to worry about running |
| 1718 | off the end of the buffer. An excessive number of leading prefixes |
| 1719 | could otherwise cause this. */ |
| 1720 | memset (buf + len, 0, fixup_sentinel_space); |
| 1721 | |
| 1722 | insn = buf; |
| 1723 | amd64_get_insn_details (insn, &insn_details); |
| 1724 | |
| 1725 | insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc); |
| 1726 | |
| 1727 | /* Skip legacy instruction prefixes. */ |
| 1728 | insn = amd64_skip_prefixes (insn); |
| 1729 | |
| 1730 | /* Adjust calls with 32-bit relative addresses as push/jump, with |
| 1731 | the address pushed being the location where the original call in |
| 1732 | the user program would return to. */ |
| 1733 | if (insn[0] == 0xe8) |
| 1734 | { |
| 1735 | gdb_byte push_buf[16]; |
| 1736 | unsigned int ret_addr; |
| 1737 | |
| 1738 | /* Where "ret" in the original code will return to. */ |
| 1739 | ret_addr = oldloc + insn_length; |
| 1740 | push_buf[0] = 0x68; /* pushq $... */ |
| 1741 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
| 1742 | /* Push the push. */ |
| 1743 | append_insns (to, 5, push_buf); |
| 1744 | |
| 1745 | /* Convert the relative call to a relative jump. */ |
| 1746 | insn[0] = 0xe9; |
| 1747 | |
| 1748 | /* Adjust the destination offset. */ |
| 1749 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); |
| 1750 | newrel = (oldloc - *to) + rel32; |
| 1751 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
| 1752 | |
| 1753 | if (debug_displaced) |
| 1754 | fprintf_unfiltered (gdb_stdlog, |
| 1755 | "Adjusted insn rel32=%s at %s to" |
| 1756 | " rel32=%s at %s\n", |
| 1757 | hex_string (rel32), paddress (gdbarch, oldloc), |
| 1758 | hex_string (newrel), paddress (gdbarch, *to)); |
| 1759 | |
| 1760 | /* Write the adjusted jump into its displaced location. */ |
| 1761 | append_insns (to, 5, insn); |
| 1762 | return; |
| 1763 | } |
| 1764 | |
| 1765 | offset = rip_relative_offset (&insn_details); |
| 1766 | if (!offset) |
| 1767 | { |
| 1768 | /* Adjust jumps with 32-bit relative addresses. Calls are |
| 1769 | already handled above. */ |
| 1770 | if (insn[0] == 0xe9) |
| 1771 | offset = 1; |
| 1772 | /* Adjust conditional jumps. */ |
| 1773 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) |
| 1774 | offset = 2; |
| 1775 | } |
| 1776 | |
| 1777 | if (offset) |
| 1778 | { |
| 1779 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); |
| 1780 | newrel = (oldloc - *to) + rel32; |
| 1781 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
| 1782 | if (debug_displaced) |
| 1783 | fprintf_unfiltered (gdb_stdlog, |
| 1784 | "Adjusted insn rel32=%s at %s to" |
| 1785 | " rel32=%s at %s\n", |
| 1786 | hex_string (rel32), paddress (gdbarch, oldloc), |
| 1787 | hex_string (newrel), paddress (gdbarch, *to)); |
| 1788 | } |
| 1789 | |
| 1790 | /* Write the adjusted instruction into its displaced location. */ |
| 1791 | append_insns (to, insn_length, buf); |
| 1792 | } |
| 1793 | |
| 1794 | \f |
| 1795 | /* The maximum number of saved registers. This should include %rip. */ |
| 1796 | #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS |
| 1797 | |
| 1798 | struct amd64_frame_cache |
| 1799 | { |
| 1800 | /* Base address. */ |
| 1801 | CORE_ADDR base; |
| 1802 | int base_p; |
| 1803 | CORE_ADDR sp_offset; |
| 1804 | CORE_ADDR pc; |
| 1805 | |
| 1806 | /* Saved registers. */ |
| 1807 | CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; |
| 1808 | CORE_ADDR saved_sp; |
| 1809 | int saved_sp_reg; |
| 1810 | |
| 1811 | /* Do we have a frame? */ |
| 1812 | int frameless_p; |
| 1813 | }; |
| 1814 | |
| 1815 | /* Initialize a frame cache. */ |
| 1816 | |
| 1817 | static void |
| 1818 | amd64_init_frame_cache (struct amd64_frame_cache *cache) |
| 1819 | { |
| 1820 | int i; |
| 1821 | |
| 1822 | /* Base address. */ |
| 1823 | cache->base = 0; |
| 1824 | cache->base_p = 0; |
| 1825 | cache->sp_offset = -8; |
| 1826 | cache->pc = 0; |
| 1827 | |
| 1828 | /* Saved registers. We initialize these to -1 since zero is a valid |
| 1829 | offset (that's where %rbp is supposed to be stored). |
| 1830 | The values start out as being offsets, and are later converted to |
| 1831 | addresses (at which point -1 is interpreted as an address, still meaning |
| 1832 | "invalid"). */ |
| 1833 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
| 1834 | cache->saved_regs[i] = -1; |
| 1835 | cache->saved_sp = 0; |
| 1836 | cache->saved_sp_reg = -1; |
| 1837 | |
| 1838 | /* Frameless until proven otherwise. */ |
| 1839 | cache->frameless_p = 1; |
| 1840 | } |
| 1841 | |
| 1842 | /* Allocate and initialize a frame cache. */ |
| 1843 | |
| 1844 | static struct amd64_frame_cache * |
| 1845 | amd64_alloc_frame_cache (void) |
| 1846 | { |
| 1847 | struct amd64_frame_cache *cache; |
| 1848 | |
| 1849 | cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); |
| 1850 | amd64_init_frame_cache (cache); |
| 1851 | return cache; |
| 1852 | } |
| 1853 | |
| 1854 | /* GCC 4.4 and later, can put code in the prologue to realign the |
| 1855 | stack pointer. Check whether PC points to such code, and update |
| 1856 | CACHE accordingly. Return the first instruction after the code |
| 1857 | sequence or CURRENT_PC, whichever is smaller. If we don't |
| 1858 | recognize the code, return PC. */ |
| 1859 | |
| 1860 | static CORE_ADDR |
| 1861 | amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, |
| 1862 | struct amd64_frame_cache *cache) |
| 1863 | { |
| 1864 | /* There are 2 code sequences to re-align stack before the frame |
| 1865 | gets set up: |
| 1866 | |
| 1867 | 1. Use a caller-saved saved register: |
| 1868 | |
| 1869 | leaq 8(%rsp), %reg |
| 1870 | andq $-XXX, %rsp |
| 1871 | pushq -8(%reg) |
| 1872 | |
| 1873 | 2. Use a callee-saved saved register: |
| 1874 | |
| 1875 | pushq %reg |
| 1876 | leaq 16(%rsp), %reg |
| 1877 | andq $-XXX, %rsp |
| 1878 | pushq -8(%reg) |
| 1879 | |
| 1880 | "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: |
| 1881 | |
| 1882 | 0x48 0x83 0xe4 0xf0 andq $-16, %rsp |
| 1883 | 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp |
| 1884 | */ |
| 1885 | |
| 1886 | gdb_byte buf[18]; |
| 1887 | int reg, r; |
| 1888 | int offset, offset_and; |
| 1889 | |
| 1890 | if (target_read_code (pc, buf, sizeof buf)) |
| 1891 | return pc; |
| 1892 | |
| 1893 | /* Check caller-saved saved register. The first instruction has |
| 1894 | to be "leaq 8(%rsp), %reg". */ |
| 1895 | if ((buf[0] & 0xfb) == 0x48 |
| 1896 | && buf[1] == 0x8d |
| 1897 | && buf[3] == 0x24 |
| 1898 | && buf[4] == 0x8) |
| 1899 | { |
| 1900 | /* MOD must be binary 10 and R/M must be binary 100. */ |
| 1901 | if ((buf[2] & 0xc7) != 0x44) |
| 1902 | return pc; |
| 1903 | |
| 1904 | /* REG has register number. */ |
| 1905 | reg = (buf[2] >> 3) & 7; |
| 1906 | |
| 1907 | /* Check the REX.R bit. */ |
| 1908 | if (buf[0] == 0x4c) |
| 1909 | reg += 8; |
| 1910 | |
| 1911 | offset = 5; |
| 1912 | } |
| 1913 | else |
| 1914 | { |
| 1915 | /* Check callee-saved saved register. The first instruction |
| 1916 | has to be "pushq %reg". */ |
| 1917 | reg = 0; |
| 1918 | if ((buf[0] & 0xf8) == 0x50) |
| 1919 | offset = 0; |
| 1920 | else if ((buf[0] & 0xf6) == 0x40 |
| 1921 | && (buf[1] & 0xf8) == 0x50) |
| 1922 | { |
| 1923 | /* Check the REX.B bit. */ |
| 1924 | if ((buf[0] & 1) != 0) |
| 1925 | reg = 8; |
| 1926 | |
| 1927 | offset = 1; |
| 1928 | } |
| 1929 | else |
| 1930 | return pc; |
| 1931 | |
| 1932 | /* Get register. */ |
| 1933 | reg += buf[offset] & 0x7; |
| 1934 | |
| 1935 | offset++; |
| 1936 | |
| 1937 | /* The next instruction has to be "leaq 16(%rsp), %reg". */ |
| 1938 | if ((buf[offset] & 0xfb) != 0x48 |
| 1939 | || buf[offset + 1] != 0x8d |
| 1940 | || buf[offset + 3] != 0x24 |
| 1941 | || buf[offset + 4] != 0x10) |
| 1942 | return pc; |
| 1943 | |
| 1944 | /* MOD must be binary 10 and R/M must be binary 100. */ |
| 1945 | if ((buf[offset + 2] & 0xc7) != 0x44) |
| 1946 | return pc; |
| 1947 | |
| 1948 | /* REG has register number. */ |
| 1949 | r = (buf[offset + 2] >> 3) & 7; |
| 1950 | |
| 1951 | /* Check the REX.R bit. */ |
| 1952 | if (buf[offset] == 0x4c) |
| 1953 | r += 8; |
| 1954 | |
| 1955 | /* Registers in pushq and leaq have to be the same. */ |
| 1956 | if (reg != r) |
| 1957 | return pc; |
| 1958 | |
| 1959 | offset += 5; |
| 1960 | } |
| 1961 | |
| 1962 | /* Rigister can't be %rsp nor %rbp. */ |
| 1963 | if (reg == 4 || reg == 5) |
| 1964 | return pc; |
| 1965 | |
| 1966 | /* The next instruction has to be "andq $-XXX, %rsp". */ |
| 1967 | if (buf[offset] != 0x48 |
| 1968 | || buf[offset + 2] != 0xe4 |
| 1969 | || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) |
| 1970 | return pc; |
| 1971 | |
| 1972 | offset_and = offset; |
| 1973 | offset += buf[offset + 1] == 0x81 ? 7 : 4; |
| 1974 | |
| 1975 | /* The next instruction has to be "pushq -8(%reg)". */ |
| 1976 | r = 0; |
| 1977 | if (buf[offset] == 0xff) |
| 1978 | offset++; |
| 1979 | else if ((buf[offset] & 0xf6) == 0x40 |
| 1980 | && buf[offset + 1] == 0xff) |
| 1981 | { |
| 1982 | /* Check the REX.B bit. */ |
| 1983 | if ((buf[offset] & 0x1) != 0) |
| 1984 | r = 8; |
| 1985 | offset += 2; |
| 1986 | } |
| 1987 | else |
| 1988 | return pc; |
| 1989 | |
| 1990 | /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary |
| 1991 | 01. */ |
| 1992 | if (buf[offset + 1] != 0xf8 |
| 1993 | || (buf[offset] & 0xf8) != 0x70) |
| 1994 | return pc; |
| 1995 | |
| 1996 | /* R/M has register. */ |
| 1997 | r += buf[offset] & 7; |
| 1998 | |
| 1999 | /* Registers in leaq and pushq have to be the same. */ |
| 2000 | if (reg != r) |
| 2001 | return pc; |
| 2002 | |
| 2003 | if (current_pc > pc + offset_and) |
| 2004 | cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); |
| 2005 | |
| 2006 | return min (pc + offset + 2, current_pc); |
| 2007 | } |
| 2008 | |
| 2009 | /* Similar to amd64_analyze_stack_align for x32. */ |
| 2010 | |
| 2011 | static CORE_ADDR |
| 2012 | amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, |
| 2013 | struct amd64_frame_cache *cache) |
| 2014 | { |
| 2015 | /* There are 2 code sequences to re-align stack before the frame |
| 2016 | gets set up: |
| 2017 | |
| 2018 | 1. Use a caller-saved saved register: |
| 2019 | |
| 2020 | leaq 8(%rsp), %reg |
| 2021 | andq $-XXX, %rsp |
| 2022 | pushq -8(%reg) |
| 2023 | |
| 2024 | or |
| 2025 | |
| 2026 | [addr32] leal 8(%rsp), %reg |
| 2027 | andl $-XXX, %esp |
| 2028 | [addr32] pushq -8(%reg) |
| 2029 | |
| 2030 | 2. Use a callee-saved saved register: |
| 2031 | |
| 2032 | pushq %reg |
| 2033 | leaq 16(%rsp), %reg |
| 2034 | andq $-XXX, %rsp |
| 2035 | pushq -8(%reg) |
| 2036 | |
| 2037 | or |
| 2038 | |
| 2039 | pushq %reg |
| 2040 | [addr32] leal 16(%rsp), %reg |
| 2041 | andl $-XXX, %esp |
| 2042 | [addr32] pushq -8(%reg) |
| 2043 | |
| 2044 | "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: |
| 2045 | |
| 2046 | 0x48 0x83 0xe4 0xf0 andq $-16, %rsp |
| 2047 | 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp |
| 2048 | |
| 2049 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: |
| 2050 | |
| 2051 | 0x83 0xe4 0xf0 andl $-16, %esp |
| 2052 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp |
| 2053 | */ |
| 2054 | |
| 2055 | gdb_byte buf[19]; |
| 2056 | int reg, r; |
| 2057 | int offset, offset_and; |
| 2058 | |
| 2059 | if (target_read_memory (pc, buf, sizeof buf)) |
| 2060 | return pc; |
| 2061 | |
| 2062 | /* Skip optional addr32 prefix. */ |
| 2063 | offset = buf[0] == 0x67 ? 1 : 0; |
| 2064 | |
| 2065 | /* Check caller-saved saved register. The first instruction has |
| 2066 | to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */ |
| 2067 | if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40) |
| 2068 | && buf[offset + 1] == 0x8d |
| 2069 | && buf[offset + 3] == 0x24 |
| 2070 | && buf[offset + 4] == 0x8) |
| 2071 | { |
| 2072 | /* MOD must be binary 10 and R/M must be binary 100. */ |
| 2073 | if ((buf[offset + 2] & 0xc7) != 0x44) |
| 2074 | return pc; |
| 2075 | |
| 2076 | /* REG has register number. */ |
| 2077 | reg = (buf[offset + 2] >> 3) & 7; |
| 2078 | |
| 2079 | /* Check the REX.R bit. */ |
| 2080 | if ((buf[offset] & 0x4) != 0) |
| 2081 | reg += 8; |
| 2082 | |
| 2083 | offset += 5; |
| 2084 | } |
| 2085 | else |
| 2086 | { |
| 2087 | /* Check callee-saved saved register. The first instruction |
| 2088 | has to be "pushq %reg". */ |
| 2089 | reg = 0; |
| 2090 | if ((buf[offset] & 0xf6) == 0x40 |
| 2091 | && (buf[offset + 1] & 0xf8) == 0x50) |
| 2092 | { |
| 2093 | /* Check the REX.B bit. */ |
| 2094 | if ((buf[offset] & 1) != 0) |
| 2095 | reg = 8; |
| 2096 | |
| 2097 | offset += 1; |
| 2098 | } |
| 2099 | else if ((buf[offset] & 0xf8) != 0x50) |
| 2100 | return pc; |
| 2101 | |
| 2102 | /* Get register. */ |
| 2103 | reg += buf[offset] & 0x7; |
| 2104 | |
| 2105 | offset++; |
| 2106 | |
| 2107 | /* Skip optional addr32 prefix. */ |
| 2108 | if (buf[offset] == 0x67) |
| 2109 | offset++; |
| 2110 | |
| 2111 | /* The next instruction has to be "leaq 16(%rsp), %reg" or |
| 2112 | "leal 16(%rsp), %reg". */ |
| 2113 | if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40) |
| 2114 | || buf[offset + 1] != 0x8d |
| 2115 | || buf[offset + 3] != 0x24 |
| 2116 | || buf[offset + 4] != 0x10) |
| 2117 | return pc; |
| 2118 | |
| 2119 | /* MOD must be binary 10 and R/M must be binary 100. */ |
| 2120 | if ((buf[offset + 2] & 0xc7) != 0x44) |
| 2121 | return pc; |
| 2122 | |
| 2123 | /* REG has register number. */ |
| 2124 | r = (buf[offset + 2] >> 3) & 7; |
| 2125 | |
| 2126 | /* Check the REX.R bit. */ |
| 2127 | if ((buf[offset] & 0x4) != 0) |
| 2128 | r += 8; |
| 2129 | |
| 2130 | /* Registers in pushq and leaq have to be the same. */ |
| 2131 | if (reg != r) |
| 2132 | return pc; |
| 2133 | |
| 2134 | offset += 5; |
| 2135 | } |
| 2136 | |
| 2137 | /* Rigister can't be %rsp nor %rbp. */ |
| 2138 | if (reg == 4 || reg == 5) |
| 2139 | return pc; |
| 2140 | |
| 2141 | /* The next instruction may be "andq $-XXX, %rsp" or |
| 2142 | "andl $-XXX, %esp". */ |
| 2143 | if (buf[offset] != 0x48) |
| 2144 | offset--; |
| 2145 | |
| 2146 | if (buf[offset + 2] != 0xe4 |
| 2147 | || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) |
| 2148 | return pc; |
| 2149 | |
| 2150 | offset_and = offset; |
| 2151 | offset += buf[offset + 1] == 0x81 ? 7 : 4; |
| 2152 | |
| 2153 | /* Skip optional addr32 prefix. */ |
| 2154 | if (buf[offset] == 0x67) |
| 2155 | offset++; |
| 2156 | |
| 2157 | /* The next instruction has to be "pushq -8(%reg)". */ |
| 2158 | r = 0; |
| 2159 | if (buf[offset] == 0xff) |
| 2160 | offset++; |
| 2161 | else if ((buf[offset] & 0xf6) == 0x40 |
| 2162 | && buf[offset + 1] == 0xff) |
| 2163 | { |
| 2164 | /* Check the REX.B bit. */ |
| 2165 | if ((buf[offset] & 0x1) != 0) |
| 2166 | r = 8; |
| 2167 | offset += 2; |
| 2168 | } |
| 2169 | else |
| 2170 | return pc; |
| 2171 | |
| 2172 | /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary |
| 2173 | 01. */ |
| 2174 | if (buf[offset + 1] != 0xf8 |
| 2175 | || (buf[offset] & 0xf8) != 0x70) |
| 2176 | return pc; |
| 2177 | |
| 2178 | /* R/M has register. */ |
| 2179 | r += buf[offset] & 7; |
| 2180 | |
| 2181 | /* Registers in leaq and pushq have to be the same. */ |
| 2182 | if (reg != r) |
| 2183 | return pc; |
| 2184 | |
| 2185 | if (current_pc > pc + offset_and) |
| 2186 | cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); |
| 2187 | |
| 2188 | return min (pc + offset + 2, current_pc); |
| 2189 | } |
| 2190 | |
| 2191 | /* Do a limited analysis of the prologue at PC and update CACHE |
| 2192 | accordingly. Bail out early if CURRENT_PC is reached. Return the |
| 2193 | address where the analysis stopped. |
| 2194 | |
| 2195 | We will handle only functions beginning with: |
| 2196 | |
| 2197 | pushq %rbp 0x55 |
| 2198 | movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec) |
| 2199 | |
| 2200 | or (for the X32 ABI): |
| 2201 | |
| 2202 | pushq %rbp 0x55 |
| 2203 | movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec) |
| 2204 | |
| 2205 | Any function that doesn't start with one of these sequences will be |
| 2206 | assumed to have no prologue and thus no valid frame pointer in |
| 2207 | %rbp. */ |
| 2208 | |
| 2209 | static CORE_ADDR |
| 2210 | amd64_analyze_prologue (struct gdbarch *gdbarch, |
| 2211 | CORE_ADDR pc, CORE_ADDR current_pc, |
| 2212 | struct amd64_frame_cache *cache) |
| 2213 | { |
| 2214 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2215 | /* There are two variations of movq %rsp, %rbp. */ |
| 2216 | static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 }; |
| 2217 | static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec }; |
| 2218 | /* Ditto for movl %esp, %ebp. */ |
| 2219 | static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 }; |
| 2220 | static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec }; |
| 2221 | |
| 2222 | gdb_byte buf[3]; |
| 2223 | gdb_byte op; |
| 2224 | |
| 2225 | if (current_pc <= pc) |
| 2226 | return current_pc; |
| 2227 | |
| 2228 | if (gdbarch_ptr_bit (gdbarch) == 32) |
| 2229 | pc = amd64_x32_analyze_stack_align (pc, current_pc, cache); |
| 2230 | else |
| 2231 | pc = amd64_analyze_stack_align (pc, current_pc, cache); |
| 2232 | |
| 2233 | op = read_code_unsigned_integer (pc, 1, byte_order); |
| 2234 | |
| 2235 | if (op == 0x55) /* pushq %rbp */ |
| 2236 | { |
| 2237 | /* Take into account that we've executed the `pushq %rbp' that |
| 2238 | starts this instruction sequence. */ |
| 2239 | cache->saved_regs[AMD64_RBP_REGNUM] = 0; |
| 2240 | cache->sp_offset += 8; |
| 2241 | |
| 2242 | /* If that's all, return now. */ |
| 2243 | if (current_pc <= pc + 1) |
| 2244 | return current_pc; |
| 2245 | |
| 2246 | read_code (pc + 1, buf, 3); |
| 2247 | |
| 2248 | /* Check for `movq %rsp, %rbp'. */ |
| 2249 | if (memcmp (buf, mov_rsp_rbp_1, 3) == 0 |
| 2250 | || memcmp (buf, mov_rsp_rbp_2, 3) == 0) |
| 2251 | { |
| 2252 | /* OK, we actually have a frame. */ |
| 2253 | cache->frameless_p = 0; |
| 2254 | return pc + 4; |
| 2255 | } |
| 2256 | |
| 2257 | /* For X32, also check for `movq %esp, %ebp'. */ |
| 2258 | if (gdbarch_ptr_bit (gdbarch) == 32) |
| 2259 | { |
| 2260 | if (memcmp (buf, mov_esp_ebp_1, 2) == 0 |
| 2261 | || memcmp (buf, mov_esp_ebp_2, 2) == 0) |
| 2262 | { |
| 2263 | /* OK, we actually have a frame. */ |
| 2264 | cache->frameless_p = 0; |
| 2265 | return pc + 3; |
| 2266 | } |
| 2267 | } |
| 2268 | |
| 2269 | return pc + 1; |
| 2270 | } |
| 2271 | |
| 2272 | return pc; |
| 2273 | } |
| 2274 | |
| 2275 | /* Work around false termination of prologue - GCC PR debug/48827. |
| 2276 | |
| 2277 | START_PC is the first instruction of a function, PC is its minimal already |
| 2278 | determined advanced address. Function returns PC if it has nothing to do. |
| 2279 | |
| 2280 | 84 c0 test %al,%al |
| 2281 | 74 23 je after |
| 2282 | <-- here is 0 lines advance - the false prologue end marker. |
| 2283 | 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp) |
| 2284 | 0f 29 4d 80 movaps %xmm1,-0x80(%rbp) |
| 2285 | 0f 29 55 90 movaps %xmm2,-0x70(%rbp) |
| 2286 | 0f 29 5d a0 movaps %xmm3,-0x60(%rbp) |
| 2287 | 0f 29 65 b0 movaps %xmm4,-0x50(%rbp) |
| 2288 | 0f 29 6d c0 movaps %xmm5,-0x40(%rbp) |
| 2289 | 0f 29 75 d0 movaps %xmm6,-0x30(%rbp) |
| 2290 | 0f 29 7d e0 movaps %xmm7,-0x20(%rbp) |
| 2291 | after: */ |
| 2292 | |
| 2293 | static CORE_ADDR |
| 2294 | amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) |
| 2295 | { |
| 2296 | struct symtab_and_line start_pc_sal, next_sal; |
| 2297 | gdb_byte buf[4 + 8 * 7]; |
| 2298 | int offset, xmmreg; |
| 2299 | |
| 2300 | if (pc == start_pc) |
| 2301 | return pc; |
| 2302 | |
| 2303 | start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); |
| 2304 | if (start_pc_sal.symtab == NULL |
| 2305 | || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6 |
| 2306 | || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) |
| 2307 | return pc; |
| 2308 | |
| 2309 | next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0); |
| 2310 | if (next_sal.line != start_pc_sal.line) |
| 2311 | return pc; |
| 2312 | |
| 2313 | /* START_PC can be from overlayed memory, ignored here. */ |
| 2314 | if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0) |
| 2315 | return pc; |
| 2316 | |
| 2317 | /* test %al,%al */ |
| 2318 | if (buf[0] != 0x84 || buf[1] != 0xc0) |
| 2319 | return pc; |
| 2320 | /* je AFTER */ |
| 2321 | if (buf[2] != 0x74) |
| 2322 | return pc; |
| 2323 | |
| 2324 | offset = 4; |
| 2325 | for (xmmreg = 0; xmmreg < 8; xmmreg++) |
| 2326 | { |
| 2327 | /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */ |
| 2328 | if (buf[offset] != 0x0f || buf[offset + 1] != 0x29 |
| 2329 | || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5)) |
| 2330 | return pc; |
| 2331 | |
| 2332 | /* 0b01?????? */ |
| 2333 | if ((buf[offset + 2] & 0xc0) == 0x40) |
| 2334 | { |
| 2335 | /* 8-bit displacement. */ |
| 2336 | offset += 4; |
| 2337 | } |
| 2338 | /* 0b10?????? */ |
| 2339 | else if ((buf[offset + 2] & 0xc0) == 0x80) |
| 2340 | { |
| 2341 | /* 32-bit displacement. */ |
| 2342 | offset += 7; |
| 2343 | } |
| 2344 | else |
| 2345 | return pc; |
| 2346 | } |
| 2347 | |
| 2348 | /* je AFTER */ |
| 2349 | if (offset - 4 != buf[3]) |
| 2350 | return pc; |
| 2351 | |
| 2352 | return next_sal.end; |
| 2353 | } |
| 2354 | |
| 2355 | /* Return PC of first real instruction. */ |
| 2356 | |
| 2357 | static CORE_ADDR |
| 2358 | amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
| 2359 | { |
| 2360 | struct amd64_frame_cache cache; |
| 2361 | CORE_ADDR pc; |
| 2362 | CORE_ADDR func_addr; |
| 2363 | |
| 2364 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
| 2365 | { |
| 2366 | CORE_ADDR post_prologue_pc |
| 2367 | = skip_prologue_using_sal (gdbarch, func_addr); |
| 2368 | struct symtab *s = find_pc_symtab (func_addr); |
| 2369 | |
| 2370 | /* Clang always emits a line note before the prologue and another |
| 2371 | one after. We trust clang to emit usable line notes. */ |
| 2372 | if (post_prologue_pc |
| 2373 | && (s != NULL |
| 2374 | && s->producer != NULL |
| 2375 | && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0)) |
| 2376 | return max (start_pc, post_prologue_pc); |
| 2377 | } |
| 2378 | |
| 2379 | amd64_init_frame_cache (&cache); |
| 2380 | pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, |
| 2381 | &cache); |
| 2382 | if (cache.frameless_p) |
| 2383 | return start_pc; |
| 2384 | |
| 2385 | return amd64_skip_xmm_prologue (pc, start_pc); |
| 2386 | } |
| 2387 | \f |
| 2388 | |
| 2389 | /* Normal frames. */ |
| 2390 | |
| 2391 | static void |
| 2392 | amd64_frame_cache_1 (struct frame_info *this_frame, |
| 2393 | struct amd64_frame_cache *cache) |
| 2394 | { |
| 2395 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2396 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2397 | gdb_byte buf[8]; |
| 2398 | int i; |
| 2399 | |
| 2400 | cache->pc = get_frame_func (this_frame); |
| 2401 | if (cache->pc != 0) |
| 2402 | amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
| 2403 | cache); |
| 2404 | |
| 2405 | if (cache->frameless_p) |
| 2406 | { |
| 2407 | /* We didn't find a valid frame. If we're at the start of a |
| 2408 | function, or somewhere half-way its prologue, the function's |
| 2409 | frame probably hasn't been fully setup yet. Try to |
| 2410 | reconstruct the base address for the stack frame by looking |
| 2411 | at the stack pointer. For truly "frameless" functions this |
| 2412 | might work too. */ |
| 2413 | |
| 2414 | if (cache->saved_sp_reg != -1) |
| 2415 | { |
| 2416 | /* Stack pointer has been saved. */ |
| 2417 | get_frame_register (this_frame, cache->saved_sp_reg, buf); |
| 2418 | cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order); |
| 2419 | |
| 2420 | /* We're halfway aligning the stack. */ |
| 2421 | cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8; |
| 2422 | cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8; |
| 2423 | |
| 2424 | /* This will be added back below. */ |
| 2425 | cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base; |
| 2426 | } |
| 2427 | else |
| 2428 | { |
| 2429 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); |
| 2430 | cache->base = extract_unsigned_integer (buf, 8, byte_order) |
| 2431 | + cache->sp_offset; |
| 2432 | } |
| 2433 | } |
| 2434 | else |
| 2435 | { |
| 2436 | get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); |
| 2437 | cache->base = extract_unsigned_integer (buf, 8, byte_order); |
| 2438 | } |
| 2439 | |
| 2440 | /* Now that we have the base address for the stack frame we can |
| 2441 | calculate the value of %rsp in the calling frame. */ |
| 2442 | cache->saved_sp = cache->base + 16; |
| 2443 | |
| 2444 | /* For normal frames, %rip is stored at 8(%rbp). If we don't have a |
| 2445 | frame we find it at the same offset from the reconstructed base |
| 2446 | address. If we're halfway aligning the stack, %rip is handled |
| 2447 | differently (see above). */ |
| 2448 | if (!cache->frameless_p || cache->saved_sp_reg == -1) |
| 2449 | cache->saved_regs[AMD64_RIP_REGNUM] = 8; |
| 2450 | |
| 2451 | /* Adjust all the saved registers such that they contain addresses |
| 2452 | instead of offsets. */ |
| 2453 | for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) |
| 2454 | if (cache->saved_regs[i] != -1) |
| 2455 | cache->saved_regs[i] += cache->base; |
| 2456 | |
| 2457 | cache->base_p = 1; |
| 2458 | } |
| 2459 | |
| 2460 | static struct amd64_frame_cache * |
| 2461 | amd64_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 2462 | { |
| 2463 | volatile struct gdb_exception ex; |
| 2464 | struct amd64_frame_cache *cache; |
| 2465 | |
| 2466 | if (*this_cache) |
| 2467 | return *this_cache; |
| 2468 | |
| 2469 | cache = amd64_alloc_frame_cache (); |
| 2470 | *this_cache = cache; |
| 2471 | |
| 2472 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
| 2473 | { |
| 2474 | amd64_frame_cache_1 (this_frame, cache); |
| 2475 | } |
| 2476 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
| 2477 | throw_exception (ex); |
| 2478 | |
| 2479 | return cache; |
| 2480 | } |
| 2481 | |
| 2482 | static enum unwind_stop_reason |
| 2483 | amd64_frame_unwind_stop_reason (struct frame_info *this_frame, |
| 2484 | void **this_cache) |
| 2485 | { |
| 2486 | struct amd64_frame_cache *cache = |
| 2487 | amd64_frame_cache (this_frame, this_cache); |
| 2488 | |
| 2489 | if (!cache->base_p) |
| 2490 | return UNWIND_UNAVAILABLE; |
| 2491 | |
| 2492 | /* This marks the outermost frame. */ |
| 2493 | if (cache->base == 0) |
| 2494 | return UNWIND_OUTERMOST; |
| 2495 | |
| 2496 | return UNWIND_NO_REASON; |
| 2497 | } |
| 2498 | |
| 2499 | static void |
| 2500 | amd64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 2501 | struct frame_id *this_id) |
| 2502 | { |
| 2503 | struct amd64_frame_cache *cache = |
| 2504 | amd64_frame_cache (this_frame, this_cache); |
| 2505 | |
| 2506 | if (!cache->base_p) |
| 2507 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
| 2508 | else if (cache->base == 0) |
| 2509 | { |
| 2510 | /* This marks the outermost frame. */ |
| 2511 | return; |
| 2512 | } |
| 2513 | else |
| 2514 | (*this_id) = frame_id_build (cache->base + 16, cache->pc); |
| 2515 | } |
| 2516 | |
| 2517 | static struct value * |
| 2518 | amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, |
| 2519 | int regnum) |
| 2520 | { |
| 2521 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2522 | struct amd64_frame_cache *cache = |
| 2523 | amd64_frame_cache (this_frame, this_cache); |
| 2524 | |
| 2525 | gdb_assert (regnum >= 0); |
| 2526 | |
| 2527 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
| 2528 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
| 2529 | |
| 2530 | if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
| 2531 | return frame_unwind_got_memory (this_frame, regnum, |
| 2532 | cache->saved_regs[regnum]); |
| 2533 | |
| 2534 | return frame_unwind_got_register (this_frame, regnum, regnum); |
| 2535 | } |
| 2536 | |
| 2537 | static const struct frame_unwind amd64_frame_unwind = |
| 2538 | { |
| 2539 | NORMAL_FRAME, |
| 2540 | amd64_frame_unwind_stop_reason, |
| 2541 | amd64_frame_this_id, |
| 2542 | amd64_frame_prev_register, |
| 2543 | NULL, |
| 2544 | default_frame_sniffer |
| 2545 | }; |
| 2546 | \f |
| 2547 | /* Generate a bytecode expression to get the value of the saved PC. */ |
| 2548 | |
| 2549 | static void |
| 2550 | amd64_gen_return_address (struct gdbarch *gdbarch, |
| 2551 | struct agent_expr *ax, struct axs_value *value, |
| 2552 | CORE_ADDR scope) |
| 2553 | { |
| 2554 | /* The following sequence assumes the traditional use of the base |
| 2555 | register. */ |
| 2556 | ax_reg (ax, AMD64_RBP_REGNUM); |
| 2557 | ax_const_l (ax, 8); |
| 2558 | ax_simple (ax, aop_add); |
| 2559 | value->type = register_type (gdbarch, AMD64_RIP_REGNUM); |
| 2560 | value->kind = axs_lvalue_memory; |
| 2561 | } |
| 2562 | \f |
| 2563 | |
| 2564 | /* Signal trampolines. */ |
| 2565 | |
| 2566 | /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and |
| 2567 | 64-bit variants. This would require using identical frame caches |
| 2568 | on both platforms. */ |
| 2569 | |
| 2570 | static struct amd64_frame_cache * |
| 2571 | amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 2572 | { |
| 2573 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2574 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2575 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2576 | volatile struct gdb_exception ex; |
| 2577 | struct amd64_frame_cache *cache; |
| 2578 | CORE_ADDR addr; |
| 2579 | gdb_byte buf[8]; |
| 2580 | int i; |
| 2581 | |
| 2582 | if (*this_cache) |
| 2583 | return *this_cache; |
| 2584 | |
| 2585 | cache = amd64_alloc_frame_cache (); |
| 2586 | |
| 2587 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
| 2588 | { |
| 2589 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); |
| 2590 | cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; |
| 2591 | |
| 2592 | addr = tdep->sigcontext_addr (this_frame); |
| 2593 | gdb_assert (tdep->sc_reg_offset); |
| 2594 | gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); |
| 2595 | for (i = 0; i < tdep->sc_num_regs; i++) |
| 2596 | if (tdep->sc_reg_offset[i] != -1) |
| 2597 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
| 2598 | |
| 2599 | cache->base_p = 1; |
| 2600 | } |
| 2601 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
| 2602 | throw_exception (ex); |
| 2603 | |
| 2604 | *this_cache = cache; |
| 2605 | return cache; |
| 2606 | } |
| 2607 | |
| 2608 | static enum unwind_stop_reason |
| 2609 | amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, |
| 2610 | void **this_cache) |
| 2611 | { |
| 2612 | struct amd64_frame_cache *cache = |
| 2613 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
| 2614 | |
| 2615 | if (!cache->base_p) |
| 2616 | return UNWIND_UNAVAILABLE; |
| 2617 | |
| 2618 | return UNWIND_NO_REASON; |
| 2619 | } |
| 2620 | |
| 2621 | static void |
| 2622 | amd64_sigtramp_frame_this_id (struct frame_info *this_frame, |
| 2623 | void **this_cache, struct frame_id *this_id) |
| 2624 | { |
| 2625 | struct amd64_frame_cache *cache = |
| 2626 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
| 2627 | |
| 2628 | if (!cache->base_p) |
| 2629 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
| 2630 | else if (cache->base == 0) |
| 2631 | { |
| 2632 | /* This marks the outermost frame. */ |
| 2633 | return; |
| 2634 | } |
| 2635 | else |
| 2636 | (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); |
| 2637 | } |
| 2638 | |
| 2639 | static struct value * |
| 2640 | amd64_sigtramp_frame_prev_register (struct frame_info *this_frame, |
| 2641 | void **this_cache, int regnum) |
| 2642 | { |
| 2643 | /* Make sure we've initialized the cache. */ |
| 2644 | amd64_sigtramp_frame_cache (this_frame, this_cache); |
| 2645 | |
| 2646 | return amd64_frame_prev_register (this_frame, this_cache, regnum); |
| 2647 | } |
| 2648 | |
| 2649 | static int |
| 2650 | amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, |
| 2651 | struct frame_info *this_frame, |
| 2652 | void **this_cache) |
| 2653 | { |
| 2654 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
| 2655 | |
| 2656 | /* We shouldn't even bother if we don't have a sigcontext_addr |
| 2657 | handler. */ |
| 2658 | if (tdep->sigcontext_addr == NULL) |
| 2659 | return 0; |
| 2660 | |
| 2661 | if (tdep->sigtramp_p != NULL) |
| 2662 | { |
| 2663 | if (tdep->sigtramp_p (this_frame)) |
| 2664 | return 1; |
| 2665 | } |
| 2666 | |
| 2667 | if (tdep->sigtramp_start != 0) |
| 2668 | { |
| 2669 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2670 | |
| 2671 | gdb_assert (tdep->sigtramp_end != 0); |
| 2672 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) |
| 2673 | return 1; |
| 2674 | } |
| 2675 | |
| 2676 | return 0; |
| 2677 | } |
| 2678 | |
| 2679 | static const struct frame_unwind amd64_sigtramp_frame_unwind = |
| 2680 | { |
| 2681 | SIGTRAMP_FRAME, |
| 2682 | amd64_sigtramp_frame_unwind_stop_reason, |
| 2683 | amd64_sigtramp_frame_this_id, |
| 2684 | amd64_sigtramp_frame_prev_register, |
| 2685 | NULL, |
| 2686 | amd64_sigtramp_frame_sniffer |
| 2687 | }; |
| 2688 | \f |
| 2689 | |
| 2690 | static CORE_ADDR |
| 2691 | amd64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 2692 | { |
| 2693 | struct amd64_frame_cache *cache = |
| 2694 | amd64_frame_cache (this_frame, this_cache); |
| 2695 | |
| 2696 | return cache->base; |
| 2697 | } |
| 2698 | |
| 2699 | static const struct frame_base amd64_frame_base = |
| 2700 | { |
| 2701 | &amd64_frame_unwind, |
| 2702 | amd64_frame_base_address, |
| 2703 | amd64_frame_base_address, |
| 2704 | amd64_frame_base_address |
| 2705 | }; |
| 2706 | |
| 2707 | /* Normal frames, but in a function epilogue. */ |
| 2708 | |
| 2709 | /* The epilogue is defined here as the 'ret' instruction, which will |
| 2710 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
| 2711 | the function's stack frame. */ |
| 2712 | |
| 2713 | static int |
| 2714 | amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 2715 | { |
| 2716 | gdb_byte insn; |
| 2717 | struct symtab *symtab; |
| 2718 | |
| 2719 | symtab = find_pc_symtab (pc); |
| 2720 | if (symtab && symtab->epilogue_unwind_valid) |
| 2721 | return 0; |
| 2722 | |
| 2723 | if (target_read_memory (pc, &insn, 1)) |
| 2724 | return 0; /* Can't read memory at pc. */ |
| 2725 | |
| 2726 | if (insn != 0xc3) /* 'ret' instruction. */ |
| 2727 | return 0; |
| 2728 | |
| 2729 | return 1; |
| 2730 | } |
| 2731 | |
| 2732 | static int |
| 2733 | amd64_epilogue_frame_sniffer (const struct frame_unwind *self, |
| 2734 | struct frame_info *this_frame, |
| 2735 | void **this_prologue_cache) |
| 2736 | { |
| 2737 | if (frame_relative_level (this_frame) == 0) |
| 2738 | return amd64_in_function_epilogue_p (get_frame_arch (this_frame), |
| 2739 | get_frame_pc (this_frame)); |
| 2740 | else |
| 2741 | return 0; |
| 2742 | } |
| 2743 | |
| 2744 | static struct amd64_frame_cache * |
| 2745 | amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 2746 | { |
| 2747 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2748 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2749 | volatile struct gdb_exception ex; |
| 2750 | struct amd64_frame_cache *cache; |
| 2751 | gdb_byte buf[8]; |
| 2752 | |
| 2753 | if (*this_cache) |
| 2754 | return *this_cache; |
| 2755 | |
| 2756 | cache = amd64_alloc_frame_cache (); |
| 2757 | *this_cache = cache; |
| 2758 | |
| 2759 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
| 2760 | { |
| 2761 | /* Cache base will be %esp plus cache->sp_offset (-8). */ |
| 2762 | get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); |
| 2763 | cache->base = extract_unsigned_integer (buf, 8, |
| 2764 | byte_order) + cache->sp_offset; |
| 2765 | |
| 2766 | /* Cache pc will be the frame func. */ |
| 2767 | cache->pc = get_frame_pc (this_frame); |
| 2768 | |
| 2769 | /* The saved %esp will be at cache->base plus 16. */ |
| 2770 | cache->saved_sp = cache->base + 16; |
| 2771 | |
| 2772 | /* The saved %eip will be at cache->base plus 8. */ |
| 2773 | cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8; |
| 2774 | |
| 2775 | cache->base_p = 1; |
| 2776 | } |
| 2777 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
| 2778 | throw_exception (ex); |
| 2779 | |
| 2780 | return cache; |
| 2781 | } |
| 2782 | |
| 2783 | static enum unwind_stop_reason |
| 2784 | amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, |
| 2785 | void **this_cache) |
| 2786 | { |
| 2787 | struct amd64_frame_cache *cache |
| 2788 | = amd64_epilogue_frame_cache (this_frame, this_cache); |
| 2789 | |
| 2790 | if (!cache->base_p) |
| 2791 | return UNWIND_UNAVAILABLE; |
| 2792 | |
| 2793 | return UNWIND_NO_REASON; |
| 2794 | } |
| 2795 | |
| 2796 | static void |
| 2797 | amd64_epilogue_frame_this_id (struct frame_info *this_frame, |
| 2798 | void **this_cache, |
| 2799 | struct frame_id *this_id) |
| 2800 | { |
| 2801 | struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame, |
| 2802 | this_cache); |
| 2803 | |
| 2804 | if (!cache->base_p) |
| 2805 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
| 2806 | else |
| 2807 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
| 2808 | } |
| 2809 | |
| 2810 | static const struct frame_unwind amd64_epilogue_frame_unwind = |
| 2811 | { |
| 2812 | NORMAL_FRAME, |
| 2813 | amd64_epilogue_frame_unwind_stop_reason, |
| 2814 | amd64_epilogue_frame_this_id, |
| 2815 | amd64_frame_prev_register, |
| 2816 | NULL, |
| 2817 | amd64_epilogue_frame_sniffer |
| 2818 | }; |
| 2819 | |
| 2820 | static struct frame_id |
| 2821 | amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 2822 | { |
| 2823 | CORE_ADDR fp; |
| 2824 | |
| 2825 | fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); |
| 2826 | |
| 2827 | return frame_id_build (fp + 16, get_frame_pc (this_frame)); |
| 2828 | } |
| 2829 | |
| 2830 | /* 16 byte align the SP per frame requirements. */ |
| 2831 | |
| 2832 | static CORE_ADDR |
| 2833 | amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 2834 | { |
| 2835 | return sp & -(CORE_ADDR)16; |
| 2836 | } |
| 2837 | \f |
| 2838 | |
| 2839 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN |
| 2840 | in the floating-point register set REGSET to register cache |
| 2841 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ |
| 2842 | |
| 2843 | static void |
| 2844 | amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
| 2845 | int regnum, const void *fpregs, size_t len) |
| 2846 | { |
| 2847 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 2848 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2849 | |
| 2850 | gdb_assert (len == tdep->sizeof_fpregset); |
| 2851 | amd64_supply_fxsave (regcache, regnum, fpregs); |
| 2852 | } |
| 2853 | |
| 2854 | /* Collect register REGNUM from the register cache REGCACHE and store |
| 2855 | it in the buffer specified by FPREGS and LEN as described by the |
| 2856 | floating-point register set REGSET. If REGNUM is -1, do this for |
| 2857 | all registers in REGSET. */ |
| 2858 | |
| 2859 | static void |
| 2860 | amd64_collect_fpregset (const struct regset *regset, |
| 2861 | const struct regcache *regcache, |
| 2862 | int regnum, void *fpregs, size_t len) |
| 2863 | { |
| 2864 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 2865 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2866 | |
| 2867 | gdb_assert (len == tdep->sizeof_fpregset); |
| 2868 | amd64_collect_fxsave (regcache, regnum, fpregs); |
| 2869 | } |
| 2870 | |
| 2871 | /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */ |
| 2872 | |
| 2873 | static void |
| 2874 | amd64_supply_xstateregset (const struct regset *regset, |
| 2875 | struct regcache *regcache, int regnum, |
| 2876 | const void *xstateregs, size_t len) |
| 2877 | { |
| 2878 | amd64_supply_xsave (regcache, regnum, xstateregs); |
| 2879 | } |
| 2880 | |
| 2881 | /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */ |
| 2882 | |
| 2883 | static void |
| 2884 | amd64_collect_xstateregset (const struct regset *regset, |
| 2885 | const struct regcache *regcache, |
| 2886 | int regnum, void *xstateregs, size_t len) |
| 2887 | { |
| 2888 | amd64_collect_xsave (regcache, regnum, xstateregs, 1); |
| 2889 | } |
| 2890 | |
| 2891 | static const struct regset amd64_fpregset = |
| 2892 | { |
| 2893 | NULL, amd64_supply_fpregset, amd64_collect_fpregset |
| 2894 | }; |
| 2895 | |
| 2896 | static const struct regset amd64_xstateregset = |
| 2897 | { |
| 2898 | NULL, amd64_supply_xstateregset, amd64_collect_xstateregset |
| 2899 | }; |
| 2900 | |
| 2901 | /* Return the appropriate register set for the core section identified |
| 2902 | by SECT_NAME and SECT_SIZE. */ |
| 2903 | |
| 2904 | static const struct regset * |
| 2905 | amd64_regset_from_core_section (struct gdbarch *gdbarch, |
| 2906 | const char *sect_name, size_t sect_size) |
| 2907 | { |
| 2908 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2909 | |
| 2910 | if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
| 2911 | return &amd64_fpregset; |
| 2912 | |
| 2913 | if (strcmp (sect_name, ".reg-xstate") == 0) |
| 2914 | return &amd64_xstateregset; |
| 2915 | |
| 2916 | return i386_regset_from_core_section (gdbarch, sect_name, sect_size); |
| 2917 | } |
| 2918 | \f |
| 2919 | |
| 2920 | /* Figure out where the longjmp will land. Slurp the jmp_buf out of |
| 2921 | %rdi. We expect its value to be a pointer to the jmp_buf structure |
| 2922 | from which we extract the address that we will land at. This |
| 2923 | address is copied into PC. This routine returns non-zero on |
| 2924 | success. */ |
| 2925 | |
| 2926 | static int |
| 2927 | amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
| 2928 | { |
| 2929 | gdb_byte buf[8]; |
| 2930 | CORE_ADDR jb_addr; |
| 2931 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2932 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
| 2933 | int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr); |
| 2934 | |
| 2935 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
| 2936 | longjmp will land. */ |
| 2937 | if (jb_pc_offset == -1) |
| 2938 | return 0; |
| 2939 | |
| 2940 | get_frame_register (frame, AMD64_RDI_REGNUM, buf); |
| 2941 | jb_addr= extract_typed_address |
| 2942 | (buf, builtin_type (gdbarch)->builtin_data_ptr); |
| 2943 | if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) |
| 2944 | return 0; |
| 2945 | |
| 2946 | *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
| 2947 | |
| 2948 | return 1; |
| 2949 | } |
| 2950 | |
| 2951 | static const int amd64_record_regmap[] = |
| 2952 | { |
| 2953 | AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, |
| 2954 | AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, |
| 2955 | AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, |
| 2956 | AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, |
| 2957 | AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, |
| 2958 | AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM |
| 2959 | }; |
| 2960 | |
| 2961 | void |
| 2962 | amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
| 2963 | { |
| 2964 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2965 | const struct target_desc *tdesc = info.target_desc; |
| 2966 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
| 2967 | static const char *const stap_register_prefixes[] = { "%", NULL }; |
| 2968 | static const char *const stap_register_indirection_prefixes[] = { "(", |
| 2969 | NULL }; |
| 2970 | static const char *const stap_register_indirection_suffixes[] = { ")", |
| 2971 | NULL }; |
| 2972 | |
| 2973 | /* AMD64 generally uses `fxsave' instead of `fsave' for saving its |
| 2974 | floating-point registers. */ |
| 2975 | tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; |
| 2976 | |
| 2977 | if (! tdesc_has_registers (tdesc)) |
| 2978 | tdesc = tdesc_amd64; |
| 2979 | tdep->tdesc = tdesc; |
| 2980 | |
| 2981 | tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; |
| 2982 | tdep->register_names = amd64_register_names; |
| 2983 | |
| 2984 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL) |
| 2985 | { |
| 2986 | tdep->zmmh_register_names = amd64_zmmh_names; |
| 2987 | tdep->k_register_names = amd64_k_names; |
| 2988 | tdep->xmm_avx512_register_names = amd64_xmm_avx512_names; |
| 2989 | tdep->ymm16h_register_names = amd64_ymmh_avx512_names; |
| 2990 | |
| 2991 | tdep->num_zmm_regs = 32; |
| 2992 | tdep->num_xmm_avx512_regs = 16; |
| 2993 | tdep->num_ymm_avx512_regs = 16; |
| 2994 | |
| 2995 | tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM; |
| 2996 | tdep->k0_regnum = AMD64_K0_REGNUM; |
| 2997 | tdep->xmm16_regnum = AMD64_XMM16_REGNUM; |
| 2998 | tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM; |
| 2999 | } |
| 3000 | |
| 3001 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL) |
| 3002 | { |
| 3003 | tdep->ymmh_register_names = amd64_ymmh_names; |
| 3004 | tdep->num_ymm_regs = 16; |
| 3005 | tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM; |
| 3006 | } |
| 3007 | |
| 3008 | if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL) |
| 3009 | { |
| 3010 | tdep->mpx_register_names = amd64_mpx_names; |
| 3011 | tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM; |
| 3012 | tdep->bnd0r_regnum = AMD64_BND0R_REGNUM; |
| 3013 | } |
| 3014 | |
| 3015 | tdep->num_byte_regs = 20; |
| 3016 | tdep->num_word_regs = 16; |
| 3017 | tdep->num_dword_regs = 16; |
| 3018 | /* Avoid wiring in the MMX registers for now. */ |
| 3019 | tdep->num_mmx_regs = 0; |
| 3020 | |
| 3021 | set_gdbarch_pseudo_register_read_value (gdbarch, |
| 3022 | amd64_pseudo_register_read_value); |
| 3023 | set_gdbarch_pseudo_register_write (gdbarch, |
| 3024 | amd64_pseudo_register_write); |
| 3025 | |
| 3026 | set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); |
| 3027 | |
| 3028 | /* AMD64 has an FPU and 16 SSE registers. */ |
| 3029 | tdep->st0_regnum = AMD64_ST0_REGNUM; |
| 3030 | tdep->num_xmm_regs = 16; |
| 3031 | |
| 3032 | /* This is what all the fuss is about. */ |
| 3033 | set_gdbarch_long_bit (gdbarch, 64); |
| 3034 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 3035 | set_gdbarch_ptr_bit (gdbarch, 64); |
| 3036 | |
| 3037 | /* In contrast to the i386, on AMD64 a `long double' actually takes |
| 3038 | up 128 bits, even though it's still based on the i387 extended |
| 3039 | floating-point format which has only 80 significant bits. */ |
| 3040 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 3041 | |
| 3042 | set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); |
| 3043 | |
| 3044 | /* Register numbers of various important registers. */ |
| 3045 | set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ |
| 3046 | set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ |
| 3047 | set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ |
| 3048 | set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ |
| 3049 | |
| 3050 | /* The "default" register numbering scheme for AMD64 is referred to |
| 3051 | as the "DWARF Register Number Mapping" in the System V psABI. |
| 3052 | The preferred debugging format for all known AMD64 targets is |
| 3053 | actually DWARF2, and GCC doesn't seem to support DWARF (that is |
| 3054 | DWARF-1), but we provide the same mapping just in case. This |
| 3055 | mapping is also used for stabs, which GCC does support. */ |
| 3056 | set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); |
| 3057 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); |
| 3058 | |
| 3059 | /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to |
| 3060 | be in use on any of the supported AMD64 targets. */ |
| 3061 | |
| 3062 | /* Call dummy code. */ |
| 3063 | set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); |
| 3064 | set_gdbarch_frame_align (gdbarch, amd64_frame_align); |
| 3065 | set_gdbarch_frame_red_zone_size (gdbarch, 128); |
| 3066 | |
| 3067 | set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); |
| 3068 | set_gdbarch_register_to_value (gdbarch, i387_register_to_value); |
| 3069 | set_gdbarch_value_to_register (gdbarch, i387_value_to_register); |
| 3070 | |
| 3071 | set_gdbarch_return_value (gdbarch, amd64_return_value); |
| 3072 | |
| 3073 | set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); |
| 3074 | |
| 3075 | tdep->record_regmap = amd64_record_regmap; |
| 3076 | |
| 3077 | set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); |
| 3078 | |
| 3079 | /* Hook the function epilogue frame unwinder. This unwinder is |
| 3080 | appended to the list first, so that it supercedes the other |
| 3081 | unwinders in function epilogues. */ |
| 3082 | frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind); |
| 3083 | |
| 3084 | /* Hook the prologue-based frame unwinders. */ |
| 3085 | frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); |
| 3086 | frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); |
| 3087 | frame_base_set_default (gdbarch, &amd64_frame_base); |
| 3088 | |
| 3089 | /* If we have a register mapping, enable the generic core file support. */ |
| 3090 | if (tdep->gregset_reg_offset) |
| 3091 | set_gdbarch_regset_from_core_section (gdbarch, |
| 3092 | amd64_regset_from_core_section); |
| 3093 | |
| 3094 | set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); |
| 3095 | |
| 3096 | set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction); |
| 3097 | |
| 3098 | set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address); |
| 3099 | |
| 3100 | /* SystemTap variables and functions. */ |
| 3101 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
| 3102 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); |
| 3103 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, |
| 3104 | stap_register_indirection_prefixes); |
| 3105 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, |
| 3106 | stap_register_indirection_suffixes); |
| 3107 | set_gdbarch_stap_is_single_operand (gdbarch, |
| 3108 | i386_stap_is_single_operand); |
| 3109 | set_gdbarch_stap_parse_special_token (gdbarch, |
| 3110 | i386_stap_parse_special_token); |
| 3111 | set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call); |
| 3112 | set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret); |
| 3113 | set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump); |
| 3114 | } |
| 3115 | \f |
| 3116 | |
| 3117 | static struct type * |
| 3118 | amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
| 3119 | { |
| 3120 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3121 | |
| 3122 | switch (regnum - tdep->eax_regnum) |
| 3123 | { |
| 3124 | case AMD64_RBP_REGNUM: /* %ebp */ |
| 3125 | case AMD64_RSP_REGNUM: /* %esp */ |
| 3126 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 3127 | case AMD64_RIP_REGNUM: /* %eip */ |
| 3128 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 3129 | } |
| 3130 | |
| 3131 | return i386_pseudo_register_type (gdbarch, regnum); |
| 3132 | } |
| 3133 | |
| 3134 | void |
| 3135 | amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
| 3136 | { |
| 3137 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3138 | const struct target_desc *tdesc = info.target_desc; |
| 3139 | |
| 3140 | amd64_init_abi (info, gdbarch); |
| 3141 | |
| 3142 | if (! tdesc_has_registers (tdesc)) |
| 3143 | tdesc = tdesc_x32; |
| 3144 | tdep->tdesc = tdesc; |
| 3145 | |
| 3146 | tdep->num_dword_regs = 17; |
| 3147 | set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); |
| 3148 | |
| 3149 | set_gdbarch_long_bit (gdbarch, 32); |
| 3150 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 3151 | } |
| 3152 | |
| 3153 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
| 3154 | void _initialize_amd64_tdep (void); |
| 3155 | |
| 3156 | void |
| 3157 | _initialize_amd64_tdep (void) |
| 3158 | { |
| 3159 | initialize_tdesc_amd64 (); |
| 3160 | initialize_tdesc_amd64_avx (); |
| 3161 | initialize_tdesc_amd64_mpx (); |
| 3162 | initialize_tdesc_amd64_avx512 (); |
| 3163 | |
| 3164 | initialize_tdesc_x32 (); |
| 3165 | initialize_tdesc_x32_avx (); |
| 3166 | initialize_tdesc_x32_avx512 (); |
| 3167 | } |
| 3168 | \f |
| 3169 | |
| 3170 | /* The 64-bit FXSAVE format differs from the 32-bit format in the |
| 3171 | sense that the instruction pointer and data pointer are simply |
| 3172 | 64-bit offsets into the code segment and the data segment instead |
| 3173 | of a selector offset pair. The functions below store the upper 32 |
| 3174 | bits of these pointers (instead of just the 16-bits of the segment |
| 3175 | selector). */ |
| 3176 | |
| 3177 | /* Fill register REGNUM in REGCACHE with the appropriate |
| 3178 | floating-point or SSE register value from *FXSAVE. If REGNUM is |
| 3179 | -1, do this for all registers. This function masks off any of the |
| 3180 | reserved bits in *FXSAVE. */ |
| 3181 | |
| 3182 | void |
| 3183 | amd64_supply_fxsave (struct regcache *regcache, int regnum, |
| 3184 | const void *fxsave) |
| 3185 | { |
| 3186 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 3187 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3188 | |
| 3189 | i387_supply_fxsave (regcache, regnum, fxsave); |
| 3190 | |
| 3191 | if (fxsave |
| 3192 | && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
| 3193 | { |
| 3194 | const gdb_byte *regs = fxsave; |
| 3195 | |
| 3196 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
| 3197 | regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); |
| 3198 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) |
| 3199 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); |
| 3200 | } |
| 3201 | } |
| 3202 | |
| 3203 | /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ |
| 3204 | |
| 3205 | void |
| 3206 | amd64_supply_xsave (struct regcache *regcache, int regnum, |
| 3207 | const void *xsave) |
| 3208 | { |
| 3209 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 3210 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3211 | |
| 3212 | i387_supply_xsave (regcache, regnum, xsave); |
| 3213 | |
| 3214 | if (xsave |
| 3215 | && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
| 3216 | { |
| 3217 | const gdb_byte *regs = xsave; |
| 3218 | |
| 3219 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
| 3220 | regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), |
| 3221 | regs + 12); |
| 3222 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) |
| 3223 | regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), |
| 3224 | regs + 20); |
| 3225 | } |
| 3226 | } |
| 3227 | |
| 3228 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
| 3229 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for |
| 3230 | all registers. This function doesn't touch any of the reserved |
| 3231 | bits in *FXSAVE. */ |
| 3232 | |
| 3233 | void |
| 3234 | amd64_collect_fxsave (const struct regcache *regcache, int regnum, |
| 3235 | void *fxsave) |
| 3236 | { |
| 3237 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 3238 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3239 | gdb_byte *regs = fxsave; |
| 3240 | |
| 3241 | i387_collect_fxsave (regcache, regnum, fxsave); |
| 3242 | |
| 3243 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
| 3244 | { |
| 3245 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
| 3246 | regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); |
| 3247 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) |
| 3248 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); |
| 3249 | } |
| 3250 | } |
| 3251 | |
| 3252 | /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */ |
| 3253 | |
| 3254 | void |
| 3255 | amd64_collect_xsave (const struct regcache *regcache, int regnum, |
| 3256 | void *xsave, int gcore) |
| 3257 | { |
| 3258 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 3259 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3260 | gdb_byte *regs = xsave; |
| 3261 | |
| 3262 | i387_collect_xsave (regcache, regnum, xsave, gcore); |
| 3263 | |
| 3264 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) |
| 3265 | { |
| 3266 | if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) |
| 3267 | regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), |
| 3268 | regs + 12); |
| 3269 | if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) |
| 3270 | regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), |
| 3271 | regs + 20); |
| 3272 | } |
| 3273 | } |