| 1 | /* Target dependent code for ARC arhitecture, for GDB. |
| 2 | |
| 3 | Copyright 2005-2017 Free Software Foundation, Inc. |
| 4 | Contributed by Synopsys Inc. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 3 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 20 | |
| 21 | /* GDB header files. */ |
| 22 | #include "defs.h" |
| 23 | #include "arch-utils.h" |
| 24 | #include "disasm.h" |
| 25 | #include "dwarf2-frame.h" |
| 26 | #include "frame-base.h" |
| 27 | #include "frame-unwind.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "gdbcmd.h" |
| 30 | #include "objfiles.h" |
| 31 | #include "prologue-value.h" |
| 32 | #include "trad-frame.h" |
| 33 | |
| 34 | /* ARC header files. */ |
| 35 | #include "opcode/arc.h" |
| 36 | #include "opcodes/arc-dis.h" |
| 37 | #include "arc-tdep.h" |
| 38 | |
| 39 | /* Standard headers. */ |
| 40 | #include <algorithm> |
| 41 | |
| 42 | /* Default target descriptions. */ |
| 43 | #include "features/arc-v2.c" |
| 44 | #include "features/arc-arcompact.c" |
| 45 | |
| 46 | /* The frame unwind cache for ARC. */ |
| 47 | |
| 48 | struct arc_frame_cache |
| 49 | { |
| 50 | /* The stack pointer at the time this frame was created; i.e. the caller's |
| 51 | stack pointer when this function was called. It is used to identify this |
| 52 | frame. */ |
| 53 | CORE_ADDR prev_sp; |
| 54 | |
| 55 | /* Register that is a base for this frame - FP for normal frame, SP for |
| 56 | non-FP frames. */ |
| 57 | int frame_base_reg; |
| 58 | |
| 59 | /* Offset from the previous SP to the current frame base. If GCC uses |
| 60 | `SUB SP,SP,offset` to allocate space for local variables, then it will be |
| 61 | done after setting up a frame pointer, but it still will be considered |
| 62 | part of prologue, therefore SP will be lesser than FP at the end of the |
| 63 | prologue analysis. In this case that would be an offset from old SP to a |
| 64 | new FP. But in case of non-FP frames, frame base is an SP and thus that |
| 65 | would be an offset from old SP to new SP. What is important is that this |
| 66 | is an offset from old SP to a known register, so it can be used to find |
| 67 | old SP. |
| 68 | |
| 69 | Using FP is preferable, when possible, because SP can change in function |
| 70 | body after prologue due to alloca, variadic arguments or other shenanigans. |
| 71 | If that is the case in the caller frame, then PREV_SP will point to SP at |
| 72 | the moment of function call, but it will be different from SP value at the |
| 73 | end of the caller prologue. As a result it will not be possible to |
| 74 | reconstruct caller's frame and go past it in the backtrace. Those things |
| 75 | are unlikely to happen to FP - FP value at the moment of function call (as |
| 76 | stored on stack in callee prologue) is also an FP value at the end of the |
| 77 | caller's prologue. */ |
| 78 | |
| 79 | LONGEST frame_base_offset; |
| 80 | |
| 81 | /* Store addresses for registers saved in prologue. During prologue analysis |
| 82 | GDB stores offsets relatively to "old SP", then after old SP is evaluated, |
| 83 | offsets are replaced with absolute addresses. */ |
| 84 | struct trad_frame_saved_reg *saved_regs; |
| 85 | }; |
| 86 | |
| 87 | /* Global debug flag. */ |
| 88 | |
| 89 | int arc_debug; |
| 90 | |
| 91 | /* List of "maintenance print arc" commands. */ |
| 92 | |
| 93 | static struct cmd_list_element *maintenance_print_arc_list = NULL; |
| 94 | |
| 95 | /* XML target description features. */ |
| 96 | |
| 97 | static const char core_v2_feature_name[] = "org.gnu.gdb.arc.core.v2"; |
| 98 | static const char |
| 99 | core_reduced_v2_feature_name[] = "org.gnu.gdb.arc.core-reduced.v2"; |
| 100 | static const char |
| 101 | core_arcompact_feature_name[] = "org.gnu.gdb.arc.core.arcompact"; |
| 102 | static const char aux_minimal_feature_name[] = "org.gnu.gdb.arc.aux-minimal"; |
| 103 | |
| 104 | /* XML target description known registers. */ |
| 105 | |
| 106 | static const char *const core_v2_register_names[] = { |
| 107 | "r0", "r1", "r2", "r3", |
| 108 | "r4", "r5", "r6", "r7", |
| 109 | "r8", "r9", "r10", "r11", |
| 110 | "r12", "r13", "r14", "r15", |
| 111 | "r16", "r17", "r18", "r19", |
| 112 | "r20", "r21", "r22", "r23", |
| 113 | "r24", "r25", "gp", "fp", |
| 114 | "sp", "ilink", "r30", "blink", |
| 115 | "r32", "r33", "r34", "r35", |
| 116 | "r36", "r37", "r38", "r39", |
| 117 | "r40", "r41", "r42", "r43", |
| 118 | "r44", "r45", "r46", "r47", |
| 119 | "r48", "r49", "r50", "r51", |
| 120 | "r52", "r53", "r54", "r55", |
| 121 | "r56", "r57", "accl", "acch", |
| 122 | "lp_count", "reserved", "limm", "pcl", |
| 123 | }; |
| 124 | |
| 125 | static const char *const aux_minimal_register_names[] = { |
| 126 | "pc", "status32", |
| 127 | }; |
| 128 | |
| 129 | static const char *const core_arcompact_register_names[] = { |
| 130 | "r0", "r1", "r2", "r3", |
| 131 | "r4", "r5", "r6", "r7", |
| 132 | "r8", "r9", "r10", "r11", |
| 133 | "r12", "r13", "r14", "r15", |
| 134 | "r16", "r17", "r18", "r19", |
| 135 | "r20", "r21", "r22", "r23", |
| 136 | "r24", "r25", "gp", "fp", |
| 137 | "sp", "ilink1", "ilink2", "blink", |
| 138 | "r32", "r33", "r34", "r35", |
| 139 | "r36", "r37", "r38", "r39", |
| 140 | "r40", "r41", "r42", "r43", |
| 141 | "r44", "r45", "r46", "r47", |
| 142 | "r48", "r49", "r50", "r51", |
| 143 | "r52", "r53", "r54", "r55", |
| 144 | "r56", "r57", "r58", "r59", |
| 145 | "lp_count", "reserved", "limm", "pcl", |
| 146 | }; |
| 147 | |
| 148 | static char *arc_disassembler_options = NULL; |
| 149 | |
| 150 | /* Functions are sorted in the order as they are used in the |
| 151 | _initialize_arc_tdep (), which uses the same order as gdbarch.h. Static |
| 152 | functions are defined before the first invocation. */ |
| 153 | |
| 154 | /* Returns an unsigned value of OPERAND_NUM in instruction INSN. |
| 155 | For relative branch instructions returned value is an offset, not an actual |
| 156 | branch target. */ |
| 157 | |
| 158 | static ULONGEST |
| 159 | arc_insn_get_operand_value (const struct arc_instruction &insn, |
| 160 | unsigned int operand_num) |
| 161 | { |
| 162 | switch (insn.operands[operand_num].kind) |
| 163 | { |
| 164 | case ARC_OPERAND_KIND_LIMM: |
| 165 | gdb_assert (insn.limm_p); |
| 166 | return insn.limm_value; |
| 167 | case ARC_OPERAND_KIND_SHIMM: |
| 168 | return insn.operands[operand_num].value; |
| 169 | default: |
| 170 | /* Value in instruction is a register number. */ |
| 171 | struct regcache *regcache = get_current_regcache (); |
| 172 | ULONGEST value; |
| 173 | regcache_cooked_read_unsigned (regcache, |
| 174 | insn.operands[operand_num].value, |
| 175 | &value); |
| 176 | return value; |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | /* Like arc_insn_get_operand_value, but returns a signed value. */ |
| 181 | |
| 182 | static LONGEST |
| 183 | arc_insn_get_operand_value_signed (const struct arc_instruction &insn, |
| 184 | unsigned int operand_num) |
| 185 | { |
| 186 | switch (insn.operands[operand_num].kind) |
| 187 | { |
| 188 | case ARC_OPERAND_KIND_LIMM: |
| 189 | gdb_assert (insn.limm_p); |
| 190 | /* Convert unsigned raw value to signed one. This assumes 2's |
| 191 | complement arithmetic, but so is the LONG_MIN value from generic |
| 192 | defs.h and that assumption is true for ARC. */ |
| 193 | gdb_static_assert (sizeof (insn.limm_value) == sizeof (int)); |
| 194 | return (((LONGEST) insn.limm_value) ^ INT_MIN) - INT_MIN; |
| 195 | case ARC_OPERAND_KIND_SHIMM: |
| 196 | /* Sign conversion has been done by binutils. */ |
| 197 | return insn.operands[operand_num].value; |
| 198 | default: |
| 199 | /* Value in instruction is a register number. */ |
| 200 | struct regcache *regcache = get_current_regcache (); |
| 201 | LONGEST value; |
| 202 | regcache_cooked_read_signed (regcache, |
| 203 | insn.operands[operand_num].value, |
| 204 | &value); |
| 205 | return value; |
| 206 | } |
| 207 | } |
| 208 | |
| 209 | /* Get register with base address of memory operation. */ |
| 210 | |
| 211 | int |
| 212 | arc_insn_get_memory_base_reg (const struct arc_instruction &insn) |
| 213 | { |
| 214 | /* POP_S and PUSH_S have SP as an implicit argument in a disassembler. */ |
| 215 | if (insn.insn_class == PUSH || insn.insn_class == POP) |
| 216 | return ARC_SP_REGNUM; |
| 217 | |
| 218 | gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE); |
| 219 | |
| 220 | /* Other instructions all have at least two operands: operand 0 is data, |
| 221 | operand 1 is address. Operand 2 is offset from address. However, see |
| 222 | comment to arc_instruction.operands - in some cases, third operand may be |
| 223 | missing, namely if it is 0. */ |
| 224 | gdb_assert (insn.operands_count >= 2); |
| 225 | return insn.operands[1].value; |
| 226 | } |
| 227 | |
| 228 | /* Get offset of a memory operation INSN. */ |
| 229 | |
| 230 | CORE_ADDR |
| 231 | arc_insn_get_memory_offset (const struct arc_instruction &insn) |
| 232 | { |
| 233 | /* POP_S and PUSH_S have offset as an implicit argument in a |
| 234 | disassembler. */ |
| 235 | if (insn.insn_class == POP) |
| 236 | return 4; |
| 237 | else if (insn.insn_class == PUSH) |
| 238 | return -4; |
| 239 | |
| 240 | gdb_assert (insn.insn_class == LOAD || insn.insn_class == STORE); |
| 241 | |
| 242 | /* Other instructions all have at least two operands: operand 0 is data, |
| 243 | operand 1 is address. Operand 2 is offset from address. However, see |
| 244 | comment to arc_instruction.operands - in some cases, third operand may be |
| 245 | missing, namely if it is 0. */ |
| 246 | if (insn.operands_count < 3) |
| 247 | return 0; |
| 248 | |
| 249 | CORE_ADDR value = arc_insn_get_operand_value (insn, 2); |
| 250 | /* Handle scaling. */ |
| 251 | if (insn.writeback_mode == ARC_WRITEBACK_AS) |
| 252 | { |
| 253 | /* Byte data size is not valid for AS. Halfword means shift by 1 bit. |
| 254 | Word and double word means shift by 2 bits. */ |
| 255 | gdb_assert (insn.data_size_mode != ARC_SCALING_B); |
| 256 | if (insn.data_size_mode == ARC_SCALING_H) |
| 257 | value <<= 1; |
| 258 | else |
| 259 | value <<= 2; |
| 260 | } |
| 261 | return value; |
| 262 | } |
| 263 | |
| 264 | CORE_ADDR |
| 265 | arc_insn_get_branch_target (const struct arc_instruction &insn) |
| 266 | { |
| 267 | gdb_assert (insn.is_control_flow); |
| 268 | |
| 269 | /* BI [c]: PC = nextPC + (c << 2). */ |
| 270 | if (insn.insn_class == BI) |
| 271 | { |
| 272 | ULONGEST reg_value = arc_insn_get_operand_value (insn, 0); |
| 273 | return arc_insn_get_linear_next_pc (insn) + (reg_value << 2); |
| 274 | } |
| 275 | /* BIH [c]: PC = nextPC + (c << 1). */ |
| 276 | else if (insn.insn_class == BIH) |
| 277 | { |
| 278 | ULONGEST reg_value = arc_insn_get_operand_value (insn, 0); |
| 279 | return arc_insn_get_linear_next_pc (insn) + (reg_value << 1); |
| 280 | } |
| 281 | /* JLI and EI. */ |
| 282 | /* JLI and EI depend on optional AUX registers. Not supported right now. */ |
| 283 | else if (insn.insn_class == JLI) |
| 284 | { |
| 285 | fprintf_unfiltered (gdb_stderr, |
| 286 | "JLI_S instruction is not supported by the GDB."); |
| 287 | return 0; |
| 288 | } |
| 289 | else if (insn.insn_class == EI) |
| 290 | { |
| 291 | fprintf_unfiltered (gdb_stderr, |
| 292 | "EI_S instruction is not supported by the GDB."); |
| 293 | return 0; |
| 294 | } |
| 295 | /* LEAVE_S: PC = BLINK. */ |
| 296 | else if (insn.insn_class == LEAVE) |
| 297 | { |
| 298 | struct regcache *regcache = get_current_regcache (); |
| 299 | ULONGEST value; |
| 300 | regcache_cooked_read_unsigned (regcache, ARC_BLINK_REGNUM, &value); |
| 301 | return value; |
| 302 | } |
| 303 | /* BBIT0/1, BRcc: PC = currentPC + operand. */ |
| 304 | else if (insn.insn_class == BBIT0 || insn.insn_class == BBIT1 |
| 305 | || insn.insn_class == BRCC) |
| 306 | { |
| 307 | /* Most instructions has branch target as their sole argument. However |
| 308 | conditional brcc/bbit has it as a third operand. */ |
| 309 | CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 2); |
| 310 | |
| 311 | /* Offset is relative to the 4-byte aligned address of the current |
| 312 | instruction, hence last two bits should be truncated. */ |
| 313 | return pcrel_addr + align_down (insn.address, 4); |
| 314 | } |
| 315 | /* B, Bcc, BL, BLcc, LP, LPcc: PC = currentPC + operand. */ |
| 316 | else if (insn.insn_class == BRANCH || insn.insn_class == LOOP) |
| 317 | { |
| 318 | CORE_ADDR pcrel_addr = arc_insn_get_operand_value (insn, 0); |
| 319 | |
| 320 | /* Offset is relative to the 4-byte aligned address of the current |
| 321 | instruction, hence last two bits should be truncated. */ |
| 322 | return pcrel_addr + align_down (insn.address, 4); |
| 323 | } |
| 324 | /* J, Jcc, JL, JLcc: PC = operand. */ |
| 325 | else if (insn.insn_class == JUMP) |
| 326 | { |
| 327 | /* All jumps are single-operand. */ |
| 328 | return arc_insn_get_operand_value (insn, 0); |
| 329 | } |
| 330 | |
| 331 | /* This is some new and unknown instruction. */ |
| 332 | gdb_assert_not_reached ("Unknown branch instruction."); |
| 333 | } |
| 334 | |
| 335 | /* Dump INSN into gdb_stdlog. */ |
| 336 | |
| 337 | void |
| 338 | arc_insn_dump (const struct arc_instruction &insn) |
| 339 | { |
| 340 | struct gdbarch *gdbarch = target_gdbarch (); |
| 341 | |
| 342 | arc_print ("Dumping arc_instruction at %s\n", |
| 343 | paddress (gdbarch, insn.address)); |
| 344 | arc_print ("\tlength = %u\n", insn.length); |
| 345 | |
| 346 | if (!insn.valid) |
| 347 | { |
| 348 | arc_print ("\tThis is not a valid ARC instruction.\n"); |
| 349 | return; |
| 350 | } |
| 351 | |
| 352 | arc_print ("\tlength_with_limm = %u\n", insn.length + (insn.limm_p ? 4 : 0)); |
| 353 | arc_print ("\tcc = 0x%x\n", insn.condition_code); |
| 354 | arc_print ("\tinsn_class = %u\n", insn.insn_class); |
| 355 | arc_print ("\tis_control_flow = %i\n", insn.is_control_flow); |
| 356 | arc_print ("\thas_delay_slot = %i\n", insn.has_delay_slot); |
| 357 | |
| 358 | CORE_ADDR next_pc = arc_insn_get_linear_next_pc (insn); |
| 359 | arc_print ("\tlinear_next_pc = %s\n", paddress (gdbarch, next_pc)); |
| 360 | |
| 361 | if (insn.is_control_flow) |
| 362 | { |
| 363 | CORE_ADDR t = arc_insn_get_branch_target (insn); |
| 364 | arc_print ("\tbranch_target = %s\n", paddress (gdbarch, t)); |
| 365 | } |
| 366 | |
| 367 | arc_print ("\tlimm_p = %i\n", insn.limm_p); |
| 368 | if (insn.limm_p) |
| 369 | arc_print ("\tlimm_value = 0x%08x\n", insn.limm_value); |
| 370 | |
| 371 | if (insn.insn_class == STORE || insn.insn_class == LOAD |
| 372 | || insn.insn_class == PUSH || insn.insn_class == POP) |
| 373 | { |
| 374 | arc_print ("\twriteback_mode = %u\n", insn.writeback_mode); |
| 375 | arc_print ("\tdata_size_mode = %u\n", insn.data_size_mode); |
| 376 | arc_print ("\tmemory_base_register = %s\n", |
| 377 | gdbarch_register_name (gdbarch, |
| 378 | arc_insn_get_memory_base_reg (insn))); |
| 379 | /* get_memory_offset returns an unsigned CORE_ADDR, but treat it as a |
| 380 | LONGEST for a nicer representation. */ |
| 381 | arc_print ("\taddr_offset = %s\n", |
| 382 | plongest (arc_insn_get_memory_offset (insn))); |
| 383 | } |
| 384 | |
| 385 | arc_print ("\toperands_count = %u\n", insn.operands_count); |
| 386 | for (unsigned int i = 0; i < insn.operands_count; ++i) |
| 387 | { |
| 388 | int is_reg = (insn.operands[i].kind == ARC_OPERAND_KIND_REG); |
| 389 | |
| 390 | arc_print ("\toperand[%u] = {\n", i); |
| 391 | arc_print ("\t\tis_reg = %i\n", is_reg); |
| 392 | if (is_reg) |
| 393 | arc_print ("\t\tregister = %s\n", |
| 394 | gdbarch_register_name (gdbarch, insn.operands[i].value)); |
| 395 | /* Don't know if this value is signed or not, so print both |
| 396 | representations. This tends to look quite ugly, especially for big |
| 397 | numbers. */ |
| 398 | arc_print ("\t\tunsigned value = %s\n", |
| 399 | pulongest (arc_insn_get_operand_value (insn, i))); |
| 400 | arc_print ("\t\tsigned value = %s\n", |
| 401 | plongest (arc_insn_get_operand_value_signed (insn, i))); |
| 402 | arc_print ("\t}\n"); |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | CORE_ADDR |
| 407 | arc_insn_get_linear_next_pc (const struct arc_instruction &insn) |
| 408 | { |
| 409 | /* In ARC long immediate is always 4 bytes. */ |
| 410 | return (insn.address + insn.length + (insn.limm_p ? 4 : 0)); |
| 411 | } |
| 412 | |
| 413 | /* Implement the "write_pc" gdbarch method. |
| 414 | |
| 415 | In ARC PC register is a normal register so in most cases setting PC value |
| 416 | is a straightforward process: debugger just writes PC value. However it |
| 417 | gets trickier in case when current instruction is an instruction in delay |
| 418 | slot. In this case CPU will execute instruction at current PC value, then |
| 419 | will set PC to the current value of BTA register; also current instruction |
| 420 | cannot be branch/jump and some of the other instruction types. Thus if |
| 421 | debugger would try to just change PC value in this case, this instruction |
| 422 | will get executed, but then core will "jump" to the original branch target. |
| 423 | |
| 424 | Whether current instruction is a delay-slot instruction or not is indicated |
| 425 | by DE bit in STATUS32 register indicates if current instruction is a delay |
| 426 | slot instruction. This bit is writable by debug host, which allows debug |
| 427 | host to prevent core from jumping after the delay slot instruction. It |
| 428 | also works in another direction: setting this bit will make core to treat |
| 429 | any current instructions as a delay slot instruction and to set PC to the |
| 430 | current value of BTA register. |
| 431 | |
| 432 | To workaround issues with changing PC register while in delay slot |
| 433 | instruction, debugger should check for the STATUS32.DE bit and reset it if |
| 434 | it is set. No other change is required in this function. Most common |
| 435 | case, where this function might be required is calling inferior functions |
| 436 | from debugger. Generic GDB logic handles this pretty well: current values |
| 437 | of registers are stored, value of PC is changed (that is the job of this |
| 438 | function), and after inferior function is executed, GDB restores all |
| 439 | registers, include BTA and STATUS32, which also means that core is returned |
| 440 | to its original state of being halted on delay slot instructions. |
| 441 | |
| 442 | This method is useless for ARC 600, because it doesn't have externally |
| 443 | exposed BTA register. In the case of ARC 600 it is impossible to restore |
| 444 | core to its state in all occasions thus core should never be halted (from |
| 445 | the perspective of debugger host) in the delay slot. */ |
| 446 | |
| 447 | static void |
| 448 | arc_write_pc (struct regcache *regcache, CORE_ADDR new_pc) |
| 449 | { |
| 450 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 451 | |
| 452 | if (arc_debug) |
| 453 | debug_printf ("arc: Writing PC, new value=%s\n", |
| 454 | paddress (gdbarch, new_pc)); |
| 455 | |
| 456 | regcache_cooked_write_unsigned (regcache, gdbarch_pc_regnum (gdbarch), |
| 457 | new_pc); |
| 458 | |
| 459 | ULONGEST status32; |
| 460 | regcache_cooked_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), |
| 461 | &status32); |
| 462 | |
| 463 | /* Mask for DE bit is 0x40. */ |
| 464 | if (status32 & 0x40) |
| 465 | { |
| 466 | if (arc_debug) |
| 467 | { |
| 468 | debug_printf ("arc: Changing PC while in delay slot. Will " |
| 469 | "reset STATUS32.DE bit to zero. Value of STATUS32 " |
| 470 | "register is 0x%s\n", |
| 471 | phex (status32, ARC_REGISTER_SIZE)); |
| 472 | } |
| 473 | |
| 474 | /* Reset bit and write to the cache. */ |
| 475 | status32 &= ~0x40; |
| 476 | regcache_cooked_write_unsigned (regcache, gdbarch_ps_regnum (gdbarch), |
| 477 | status32); |
| 478 | } |
| 479 | } |
| 480 | |
| 481 | /* Implement the "virtual_frame_pointer" gdbarch method. |
| 482 | |
| 483 | According to ABI the FP (r27) is used to point to the middle of the current |
| 484 | stack frame, just below the saved FP and before local variables, register |
| 485 | spill area and outgoing args. However for optimization levels above O2 and |
| 486 | in any case in leaf functions, the frame pointer is usually not set at all. |
| 487 | The exception being when handling nested functions. |
| 488 | |
| 489 | We use this function to return a "virtual" frame pointer, marking the start |
| 490 | of the current stack frame as a register-offset pair. If the FP is not |
| 491 | being used, then it should return SP, with an offset of the frame size. |
| 492 | |
| 493 | The current implementation doesn't actually know the frame size, nor |
| 494 | whether the FP is actually being used, so for now we just return SP and an |
| 495 | offset of zero. This is no worse than other architectures, but is needed |
| 496 | to avoid assertion failures. |
| 497 | |
| 498 | TODO: Can we determine the frame size to get a correct offset? |
| 499 | |
| 500 | PC is a program counter where we need the virtual FP. REG_PTR is the base |
| 501 | register used for the virtual FP. OFFSET_PTR is the offset used for the |
| 502 | virtual FP. */ |
| 503 | |
| 504 | static void |
| 505 | arc_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, |
| 506 | int *reg_ptr, LONGEST *offset_ptr) |
| 507 | { |
| 508 | *reg_ptr = gdbarch_sp_regnum (gdbarch); |
| 509 | *offset_ptr = 0; |
| 510 | } |
| 511 | |
| 512 | /* Implement the "dummy_id" gdbarch method. |
| 513 | |
| 514 | Tear down a dummy frame created by arc_push_dummy_call (). This data has |
| 515 | to be constructed manually from the data in our hand. The stack pointer |
| 516 | and program counter can be obtained from the frame info. */ |
| 517 | |
| 518 | static struct frame_id |
| 519 | arc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 520 | { |
| 521 | return frame_id_build (get_frame_sp (this_frame), |
| 522 | get_frame_pc (this_frame)); |
| 523 | } |
| 524 | |
| 525 | /* Implement the "push_dummy_call" gdbarch method. |
| 526 | |
| 527 | Stack Frame Layout |
| 528 | |
| 529 | This shows the layout of the stack frame for the general case of a |
| 530 | function call; a given function might not have a variable number of |
| 531 | arguments or local variables, or might not save any registers, so it would |
| 532 | not have the corresponding frame areas. Additionally, a leaf function |
| 533 | (i.e. one which calls no other functions) does not need to save the |
| 534 | contents of the BLINK register (which holds its return address), and a |
| 535 | function might not have a frame pointer. |
| 536 | |
| 537 | The stack grows downward, so SP points below FP in memory; SP always |
| 538 | points to the last used word on the stack, not the first one. |
| 539 | |
| 540 | | | | |
| 541 | | arg word N | | caller's |
| 542 | | : | | frame |
| 543 | | arg word 10 | | |
| 544 | | arg word 9 | | |
| 545 | old SP ---> +-----------------------+ --+ |
| 546 | | | | |
| 547 | | callee-saved | | |
| 548 | | registers | | |
| 549 | | including fp, blink | | |
| 550 | | | | callee's |
| 551 | new FP ---> +-----------------------+ | frame |
| 552 | | | | |
| 553 | | local | | |
| 554 | | variables | | |
| 555 | | | | |
| 556 | | register | | |
| 557 | | spill area | | |
| 558 | | | | |
| 559 | | outgoing args | | |
| 560 | | | | |
| 561 | new SP ---> +-----------------------+ --+ |
| 562 | | | |
| 563 | | unused | |
| 564 | | | |
| 565 | | |
| 566 | | |
| 567 | V |
| 568 | downwards |
| 569 | |
| 570 | The list of arguments to be passed to a function is considered to be a |
| 571 | sequence of _N_ words (as though all the parameters were stored in order in |
| 572 | memory with each parameter occupying an integral number of words). Words |
| 573 | 1..8 are passed in registers 0..7; if the function has more than 8 words of |
| 574 | arguments then words 9..@em N are passed on the stack in the caller's frame. |
| 575 | |
| 576 | If the function has a variable number of arguments, e.g. it has a form such |
| 577 | as `function (p1, p2, ...);' and _P_ words are required to hold the values |
| 578 | of the named parameters (which are passed in registers 0..@em P -1), then |
| 579 | the remaining 8 - _P_ words passed in registers _P_..7 are spilled into the |
| 580 | top of the frame so that the anonymous parameter words occupy a continuous |
| 581 | region. |
| 582 | |
| 583 | Any arguments are already in target byte order. We just need to store |
| 584 | them! |
| 585 | |
| 586 | BP_ADDR is the return address where breakpoint must be placed. NARGS is |
| 587 | the number of arguments to the function. ARGS is the arguments values (in |
| 588 | target byte order). SP is the Current value of SP register. STRUCT_RETURN |
| 589 | is TRUE if structures are returned by the function. STRUCT_ADDR is the |
| 590 | hidden address for returning a struct. Returns SP of a new frame. */ |
| 591 | |
| 592 | static CORE_ADDR |
| 593 | arc_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 594 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
| 595 | struct value **args, CORE_ADDR sp, int struct_return, |
| 596 | CORE_ADDR struct_addr) |
| 597 | { |
| 598 | if (arc_debug) |
| 599 | debug_printf ("arc: push_dummy_call (nargs = %d)\n", nargs); |
| 600 | |
| 601 | int arg_reg = ARC_FIRST_ARG_REGNUM; |
| 602 | |
| 603 | /* Push the return address. */ |
| 604 | regcache_cooked_write_unsigned (regcache, ARC_BLINK_REGNUM, bp_addr); |
| 605 | |
| 606 | /* Are we returning a value using a structure return instead of a normal |
| 607 | value return? If so, struct_addr is the address of the reserved space for |
| 608 | the return structure to be written on the stack, and that address is |
| 609 | passed to that function as a hidden first argument. */ |
| 610 | if (struct_return) |
| 611 | { |
| 612 | /* Pass the return address in the first argument register. */ |
| 613 | regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr); |
| 614 | |
| 615 | if (arc_debug) |
| 616 | debug_printf ("arc: struct return address %s passed in R%d", |
| 617 | print_core_address (gdbarch, struct_addr), arg_reg); |
| 618 | |
| 619 | arg_reg++; |
| 620 | } |
| 621 | |
| 622 | if (nargs > 0) |
| 623 | { |
| 624 | unsigned int total_space = 0; |
| 625 | |
| 626 | /* How much space do the arguments occupy in total? Must round each |
| 627 | argument's size up to an integral number of words. */ |
| 628 | for (int i = 0; i < nargs; i++) |
| 629 | { |
| 630 | unsigned int len = TYPE_LENGTH (value_type (args[i])); |
| 631 | unsigned int space = align_up (len, 4); |
| 632 | |
| 633 | total_space += space; |
| 634 | |
| 635 | if (arc_debug) |
| 636 | debug_printf ("arc: arg %d: %u bytes -> %u\n", i, len, space); |
| 637 | } |
| 638 | |
| 639 | /* Allocate a buffer to hold a memory image of the arguments. */ |
| 640 | gdb_byte *memory_image = XCNEWVEC (gdb_byte, total_space); |
| 641 | |
| 642 | /* Now copy all of the arguments into the buffer, correctly aligned. */ |
| 643 | gdb_byte *data = memory_image; |
| 644 | for (int i = 0; i < nargs; i++) |
| 645 | { |
| 646 | unsigned int len = TYPE_LENGTH (value_type (args[i])); |
| 647 | unsigned int space = align_up (len, 4); |
| 648 | |
| 649 | memcpy (data, value_contents (args[i]), (size_t) len); |
| 650 | if (arc_debug) |
| 651 | debug_printf ("arc: copying arg %d, val 0x%08x, len %d to mem\n", |
| 652 | i, *((int *) value_contents (args[i])), len); |
| 653 | |
| 654 | data += space; |
| 655 | } |
| 656 | |
| 657 | /* Now load as much as possible of the memory image into registers. */ |
| 658 | data = memory_image; |
| 659 | while (arg_reg <= ARC_LAST_ARG_REGNUM) |
| 660 | { |
| 661 | if (arc_debug) |
| 662 | debug_printf ("arc: passing 0x%02x%02x%02x%02x in register R%d\n", |
| 663 | data[0], data[1], data[2], data[3], arg_reg); |
| 664 | |
| 665 | /* Note we don't use write_unsigned here, since that would convert |
| 666 | the byte order, but we are already in the correct byte order. */ |
| 667 | regcache_cooked_write (regcache, arg_reg, data); |
| 668 | |
| 669 | data += ARC_REGISTER_SIZE; |
| 670 | total_space -= ARC_REGISTER_SIZE; |
| 671 | |
| 672 | /* All the data is now in registers. */ |
| 673 | if (total_space == 0) |
| 674 | break; |
| 675 | |
| 676 | arg_reg++; |
| 677 | } |
| 678 | |
| 679 | /* If there is any data left, push it onto the stack (in a single write |
| 680 | operation). */ |
| 681 | if (total_space > 0) |
| 682 | { |
| 683 | if (arc_debug) |
| 684 | debug_printf ("arc: passing %d bytes on stack\n", total_space); |
| 685 | |
| 686 | sp -= total_space; |
| 687 | write_memory (sp, data, (int) total_space); |
| 688 | } |
| 689 | |
| 690 | xfree (memory_image); |
| 691 | } |
| 692 | |
| 693 | /* Finally, update the SP register. */ |
| 694 | regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp); |
| 695 | |
| 696 | return sp; |
| 697 | } |
| 698 | |
| 699 | /* Implement the "push_dummy_code" gdbarch method. |
| 700 | |
| 701 | We don't actually push any code. We just identify where a breakpoint can |
| 702 | be inserted to which we are can return and the resume address where we |
| 703 | should be called. |
| 704 | |
| 705 | ARC does not necessarily have an executable stack, so we can't put the |
| 706 | return breakpoint there. Instead we put it at the entry point of the |
| 707 | function. This means the SP is unchanged. |
| 708 | |
| 709 | SP is a current stack pointer FUNADDR is an address of the function to be |
| 710 | called. ARGS is arguments to pass. NARGS is a number of args to pass. |
| 711 | VALUE_TYPE is a type of value returned. REAL_PC is a resume address when |
| 712 | the function is called. BP_ADDR is an address where breakpoint should be |
| 713 | set. Returns the updated stack pointer. */ |
| 714 | |
| 715 | static CORE_ADDR |
| 716 | arc_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, |
| 717 | struct value **args, int nargs, struct type *value_type, |
| 718 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
| 719 | struct regcache *regcache) |
| 720 | { |
| 721 | *real_pc = funaddr; |
| 722 | *bp_addr = entry_point_address (); |
| 723 | return sp; |
| 724 | } |
| 725 | |
| 726 | /* Implement the "cannot_fetch_register" gdbarch method. */ |
| 727 | |
| 728 | static int |
| 729 | arc_cannot_fetch_register (struct gdbarch *gdbarch, int regnum) |
| 730 | { |
| 731 | /* Assume that register is readable if it is unknown. LIMM and RESERVED are |
| 732 | not real registers, but specific register numbers. They are available as |
| 733 | regnums to align architectural register numbers with GDB internal regnums, |
| 734 | but they shouldn't appear in target descriptions generated by |
| 735 | GDB-servers. */ |
| 736 | switch (regnum) |
| 737 | { |
| 738 | case ARC_RESERVED_REGNUM: |
| 739 | case ARC_LIMM_REGNUM: |
| 740 | return true; |
| 741 | default: |
| 742 | return false; |
| 743 | } |
| 744 | } |
| 745 | |
| 746 | /* Implement the "cannot_store_register" gdbarch method. */ |
| 747 | |
| 748 | static int |
| 749 | arc_cannot_store_register (struct gdbarch *gdbarch, int regnum) |
| 750 | { |
| 751 | /* Assume that register is writable if it is unknown. See comment in |
| 752 | arc_cannot_fetch_register about LIMM and RESERVED. */ |
| 753 | switch (regnum) |
| 754 | { |
| 755 | case ARC_RESERVED_REGNUM: |
| 756 | case ARC_LIMM_REGNUM: |
| 757 | case ARC_PCL_REGNUM: |
| 758 | return true; |
| 759 | default: |
| 760 | return false; |
| 761 | } |
| 762 | } |
| 763 | |
| 764 | /* Get the return value of a function from the registers/memory used to |
| 765 | return it, according to the convention used by the ABI - 4-bytes values are |
| 766 | in the R0, while 8-byte values are in the R0-R1. |
| 767 | |
| 768 | TODO: This implementation ignores the case of "complex double", where |
| 769 | according to ABI, value is returned in the R0-R3 registers. |
| 770 | |
| 771 | TYPE is a returned value's type. VALBUF is a buffer for the returned |
| 772 | value. */ |
| 773 | |
| 774 | static void |
| 775 | arc_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
| 776 | struct regcache *regcache, gdb_byte *valbuf) |
| 777 | { |
| 778 | unsigned int len = TYPE_LENGTH (type); |
| 779 | |
| 780 | if (arc_debug) |
| 781 | debug_printf ("arc: extract_return_value\n"); |
| 782 | |
| 783 | if (len <= ARC_REGISTER_SIZE) |
| 784 | { |
| 785 | ULONGEST val; |
| 786 | |
| 787 | /* Get the return value from one register. */ |
| 788 | regcache_cooked_read_unsigned (regcache, ARC_R0_REGNUM, &val); |
| 789 | store_unsigned_integer (valbuf, (int) len, |
| 790 | gdbarch_byte_order (gdbarch), val); |
| 791 | |
| 792 | if (arc_debug) |
| 793 | debug_printf ("arc: returning 0x%s\n", phex (val, ARC_REGISTER_SIZE)); |
| 794 | } |
| 795 | else if (len <= ARC_REGISTER_SIZE * 2) |
| 796 | { |
| 797 | ULONGEST low, high; |
| 798 | |
| 799 | /* Get the return value from two registers. */ |
| 800 | regcache_cooked_read_unsigned (regcache, ARC_R0_REGNUM, &low); |
| 801 | regcache_cooked_read_unsigned (regcache, ARC_R1_REGNUM, &high); |
| 802 | |
| 803 | store_unsigned_integer (valbuf, ARC_REGISTER_SIZE, |
| 804 | gdbarch_byte_order (gdbarch), low); |
| 805 | store_unsigned_integer (valbuf + ARC_REGISTER_SIZE, |
| 806 | (int) len - ARC_REGISTER_SIZE, |
| 807 | gdbarch_byte_order (gdbarch), high); |
| 808 | |
| 809 | if (arc_debug) |
| 810 | debug_printf ("arc: returning 0x%s%s\n", |
| 811 | phex (high, ARC_REGISTER_SIZE), |
| 812 | phex (low, ARC_REGISTER_SIZE)); |
| 813 | } |
| 814 | else |
| 815 | error (_("arc: extract_return_value: type length %u too large"), len); |
| 816 | } |
| 817 | |
| 818 | |
| 819 | /* Store the return value of a function into the registers/memory used to |
| 820 | return it, according to the convention used by the ABI. |
| 821 | |
| 822 | TODO: This implementation ignores the case of "complex double", where |
| 823 | according to ABI, value is returned in the R0-R3 registers. |
| 824 | |
| 825 | TYPE is a returned value's type. VALBUF is a buffer with the value to |
| 826 | return. */ |
| 827 | |
| 828 | static void |
| 829 | arc_store_return_value (struct gdbarch *gdbarch, struct type *type, |
| 830 | struct regcache *regcache, const gdb_byte *valbuf) |
| 831 | { |
| 832 | unsigned int len = TYPE_LENGTH (type); |
| 833 | |
| 834 | if (arc_debug) |
| 835 | debug_printf ("arc: store_return_value\n"); |
| 836 | |
| 837 | if (len <= ARC_REGISTER_SIZE) |
| 838 | { |
| 839 | ULONGEST val; |
| 840 | |
| 841 | /* Put the return value into one register. */ |
| 842 | val = extract_unsigned_integer (valbuf, (int) len, |
| 843 | gdbarch_byte_order (gdbarch)); |
| 844 | regcache_cooked_write_unsigned (regcache, ARC_R0_REGNUM, val); |
| 845 | |
| 846 | if (arc_debug) |
| 847 | debug_printf ("arc: storing 0x%s\n", phex (val, ARC_REGISTER_SIZE)); |
| 848 | } |
| 849 | else if (len <= ARC_REGISTER_SIZE * 2) |
| 850 | { |
| 851 | ULONGEST low, high; |
| 852 | |
| 853 | /* Put the return value into two registers. */ |
| 854 | low = extract_unsigned_integer (valbuf, ARC_REGISTER_SIZE, |
| 855 | gdbarch_byte_order (gdbarch)); |
| 856 | high = extract_unsigned_integer (valbuf + ARC_REGISTER_SIZE, |
| 857 | (int) len - ARC_REGISTER_SIZE, |
| 858 | gdbarch_byte_order (gdbarch)); |
| 859 | |
| 860 | regcache_cooked_write_unsigned (regcache, ARC_R0_REGNUM, low); |
| 861 | regcache_cooked_write_unsigned (regcache, ARC_R1_REGNUM, high); |
| 862 | |
| 863 | if (arc_debug) |
| 864 | debug_printf ("arc: storing 0x%s%s\n", |
| 865 | phex (high, ARC_REGISTER_SIZE), |
| 866 | phex (low, ARC_REGISTER_SIZE)); |
| 867 | } |
| 868 | else |
| 869 | error (_("arc_store_return_value: type length too large.")); |
| 870 | } |
| 871 | |
| 872 | /* Implement the "get_longjmp_target" gdbarch method. */ |
| 873 | |
| 874 | static int |
| 875 | arc_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
| 876 | { |
| 877 | if (arc_debug) |
| 878 | debug_printf ("arc: get_longjmp_target\n"); |
| 879 | |
| 880 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 881 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 882 | int pc_offset = tdep->jb_pc * ARC_REGISTER_SIZE; |
| 883 | gdb_byte buf[ARC_REGISTER_SIZE]; |
| 884 | CORE_ADDR jb_addr = get_frame_register_unsigned (frame, ARC_FIRST_ARG_REGNUM); |
| 885 | |
| 886 | if (target_read_memory (jb_addr + pc_offset, buf, ARC_REGISTER_SIZE)) |
| 887 | return 0; /* Failed to read from memory. */ |
| 888 | |
| 889 | *pc = extract_unsigned_integer (buf, ARC_REGISTER_SIZE, |
| 890 | gdbarch_byte_order (gdbarch)); |
| 891 | return 1; |
| 892 | } |
| 893 | |
| 894 | /* Implement the "return_value" gdbarch method. */ |
| 895 | |
| 896 | static enum return_value_convention |
| 897 | arc_return_value (struct gdbarch *gdbarch, struct value *function, |
| 898 | struct type *valtype, struct regcache *regcache, |
| 899 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 900 | { |
| 901 | /* If the return type is a struct, or a union, or would occupy more than two |
| 902 | registers, the ABI uses the "struct return convention": the calling |
| 903 | function passes a hidden first parameter to the callee (in R0). That |
| 904 | parameter is the address at which the value being returned should be |
| 905 | stored. Otherwise, the result is returned in registers. */ |
| 906 | int is_struct_return = (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
| 907 | || TYPE_CODE (valtype) == TYPE_CODE_UNION |
| 908 | || TYPE_LENGTH (valtype) > 2 * ARC_REGISTER_SIZE); |
| 909 | |
| 910 | if (arc_debug) |
| 911 | debug_printf ("arc: return_value (readbuf = %s, writebuf = %s)\n", |
| 912 | host_address_to_string (readbuf), |
| 913 | host_address_to_string (writebuf)); |
| 914 | |
| 915 | if (writebuf != NULL) |
| 916 | { |
| 917 | /* Case 1. GDB should not ask us to set a struct return value: it |
| 918 | should know the struct return location and write the value there |
| 919 | itself. */ |
| 920 | gdb_assert (!is_struct_return); |
| 921 | arc_store_return_value (gdbarch, valtype, regcache, writebuf); |
| 922 | } |
| 923 | else if (readbuf != NULL) |
| 924 | { |
| 925 | /* Case 2. GDB should not ask us to get a struct return value: it |
| 926 | should know the struct return location and read the value from there |
| 927 | itself. */ |
| 928 | gdb_assert (!is_struct_return); |
| 929 | arc_extract_return_value (gdbarch, valtype, regcache, readbuf); |
| 930 | } |
| 931 | |
| 932 | return (is_struct_return |
| 933 | ? RETURN_VALUE_STRUCT_CONVENTION |
| 934 | : RETURN_VALUE_REGISTER_CONVENTION); |
| 935 | } |
| 936 | |
| 937 | /* Return the base address of the frame. For ARC, the base address is the |
| 938 | frame pointer. */ |
| 939 | |
| 940 | static CORE_ADDR |
| 941 | arc_frame_base_address (struct frame_info *this_frame, void **prologue_cache) |
| 942 | { |
| 943 | return (CORE_ADDR) get_frame_register_unsigned (this_frame, ARC_FP_REGNUM); |
| 944 | } |
| 945 | |
| 946 | /* Helper function that returns valid pv_t for an instruction operand: |
| 947 | either a register or a constant. */ |
| 948 | |
| 949 | static pv_t |
| 950 | arc_pv_get_operand (pv_t *regs, const struct arc_instruction &insn, int operand) |
| 951 | { |
| 952 | if (insn.operands[operand].kind == ARC_OPERAND_KIND_REG) |
| 953 | return regs[insn.operands[operand].value]; |
| 954 | else |
| 955 | return pv_constant (arc_insn_get_operand_value (insn, operand)); |
| 956 | } |
| 957 | |
| 958 | /* Determine whether the given disassembled instruction may be part of a |
| 959 | function prologue. If it is, the information in the frame unwind cache will |
| 960 | be updated. */ |
| 961 | |
| 962 | static bool |
| 963 | arc_is_in_prologue (struct gdbarch *gdbarch, const struct arc_instruction &insn, |
| 964 | pv_t *regs, struct pv_area *stack) |
| 965 | { |
| 966 | /* It might be that currently analyzed address doesn't contain an |
| 967 | instruction, hence INSN is not valid. It likely means that address points |
| 968 | to a data, non-initialized memory, or middle of a 32-bit instruction. In |
| 969 | practice this may happen if GDB connects to a remote target that has |
| 970 | non-zeroed memory. GDB would read PC value and would try to analyze |
| 971 | prologue, but there is no guarantee that memory contents at the address |
| 972 | specified in PC is address is a valid instruction. There is not much that |
| 973 | that can be done about that. */ |
| 974 | if (!insn.valid) |
| 975 | return false; |
| 976 | |
| 977 | /* Branch/jump or a predicated instruction. */ |
| 978 | if (insn.is_control_flow || insn.condition_code != ARC_CC_AL) |
| 979 | return false; |
| 980 | |
| 981 | /* Store of some register. May or may not update base address register. */ |
| 982 | if (insn.insn_class == STORE || insn.insn_class == PUSH) |
| 983 | { |
| 984 | /* There is definetely at least one operand - register/value being |
| 985 | stored. */ |
| 986 | gdb_assert (insn.operands_count > 0); |
| 987 | |
| 988 | /* Store at some constant address. */ |
| 989 | if (insn.operands_count > 1 |
| 990 | && insn.operands[1].kind != ARC_OPERAND_KIND_REG) |
| 991 | return false; |
| 992 | |
| 993 | /* Writeback modes: |
| 994 | Mode Address used Writeback value |
| 995 | -------------------------------------------------- |
| 996 | No reg + offset no |
| 997 | A/AW reg + offset reg + offset |
| 998 | AB reg reg + offset |
| 999 | AS reg + (offset << scaling) no |
| 1000 | |
| 1001 | "PUSH reg" is an alias to "ST.AW reg, [SP, -4]" encoding. However |
| 1002 | 16-bit PUSH_S is a distinct instruction encoding, where offset and |
| 1003 | base register are implied through opcode. */ |
| 1004 | |
| 1005 | /* Register with base memory address. */ |
| 1006 | int base_reg = arc_insn_get_memory_base_reg (insn); |
| 1007 | |
| 1008 | /* Address where to write. arc_insn_get_memory_offset returns scaled |
| 1009 | value for ARC_WRITEBACK_AS. */ |
| 1010 | pv_t addr; |
| 1011 | if (insn.writeback_mode == ARC_WRITEBACK_AB) |
| 1012 | addr = regs[base_reg]; |
| 1013 | else |
| 1014 | addr = pv_add_constant (regs[base_reg], |
| 1015 | arc_insn_get_memory_offset (insn)); |
| 1016 | |
| 1017 | if (pv_area_store_would_trash (stack, addr)) |
| 1018 | return false; |
| 1019 | |
| 1020 | if (insn.data_size_mode != ARC_SCALING_D) |
| 1021 | { |
| 1022 | /* Find the value being stored. */ |
| 1023 | pv_t store_value = arc_pv_get_operand (regs, insn, 0); |
| 1024 | |
| 1025 | /* What is the size of a the stored value? */ |
| 1026 | CORE_ADDR size; |
| 1027 | if (insn.data_size_mode == ARC_SCALING_B) |
| 1028 | size = 1; |
| 1029 | else if (insn.data_size_mode == ARC_SCALING_H) |
| 1030 | size = 2; |
| 1031 | else |
| 1032 | size = ARC_REGISTER_SIZE; |
| 1033 | |
| 1034 | pv_area_store (stack, addr, size, store_value); |
| 1035 | } |
| 1036 | else |
| 1037 | { |
| 1038 | if (insn.operands[0].kind == ARC_OPERAND_KIND_REG) |
| 1039 | { |
| 1040 | /* If this is a double store, than write N+1 register as well. */ |
| 1041 | pv_t store_value1 = regs[insn.operands[0].value]; |
| 1042 | pv_t store_value2 = regs[insn.operands[0].value + 1]; |
| 1043 | pv_area_store (stack, addr, ARC_REGISTER_SIZE, store_value1); |
| 1044 | pv_area_store (stack, |
| 1045 | pv_add_constant (addr, ARC_REGISTER_SIZE), |
| 1046 | ARC_REGISTER_SIZE, store_value2); |
| 1047 | } |
| 1048 | else |
| 1049 | { |
| 1050 | pv_t store_value |
| 1051 | = pv_constant (arc_insn_get_operand_value (insn, 0)); |
| 1052 | pv_area_store (stack, addr, ARC_REGISTER_SIZE * 2, store_value); |
| 1053 | } |
| 1054 | } |
| 1055 | |
| 1056 | /* Is base register updated? */ |
| 1057 | if (insn.writeback_mode == ARC_WRITEBACK_A |
| 1058 | || insn.writeback_mode == ARC_WRITEBACK_AB) |
| 1059 | regs[base_reg] = pv_add_constant (regs[base_reg], |
| 1060 | arc_insn_get_memory_offset (insn)); |
| 1061 | |
| 1062 | return true; |
| 1063 | } |
| 1064 | else if (insn.insn_class == MOVE) |
| 1065 | { |
| 1066 | gdb_assert (insn.operands_count == 2); |
| 1067 | |
| 1068 | /* Destination argument can be "0", so nothing will happen. */ |
| 1069 | if (insn.operands[0].kind == ARC_OPERAND_KIND_REG) |
| 1070 | { |
| 1071 | int dst_regnum = insn.operands[0].value; |
| 1072 | regs[dst_regnum] = arc_pv_get_operand (regs, insn, 1); |
| 1073 | } |
| 1074 | return true; |
| 1075 | } |
| 1076 | else if (insn.insn_class == SUB) |
| 1077 | { |
| 1078 | gdb_assert (insn.operands_count == 3); |
| 1079 | |
| 1080 | /* SUB 0,b,c. */ |
| 1081 | if (insn.operands[0].kind != ARC_OPERAND_KIND_REG) |
| 1082 | return true; |
| 1083 | |
| 1084 | int dst_regnum = insn.operands[0].value; |
| 1085 | regs[dst_regnum] = pv_subtract (arc_pv_get_operand (regs, insn, 1), |
| 1086 | arc_pv_get_operand (regs, insn, 2)); |
| 1087 | return true; |
| 1088 | } |
| 1089 | else if (insn.insn_class == ENTER) |
| 1090 | { |
| 1091 | /* ENTER_S is a prologue-in-instruction - it saves all callee-saved |
| 1092 | registers according to given arguments thus greatly reducing code |
| 1093 | size. Which registers will be actually saved depends on arguments. |
| 1094 | |
| 1095 | ENTER_S {R13-...,FP,BLINK} stores registers in following order: |
| 1096 | |
| 1097 | new SP -> |
| 1098 | BLINK |
| 1099 | R13 |
| 1100 | R14 |
| 1101 | R15 |
| 1102 | ... |
| 1103 | FP |
| 1104 | old SP -> |
| 1105 | |
| 1106 | There are up to three arguments for this opcode, as presented by ARC |
| 1107 | disassembler: |
| 1108 | 1) amount of general-purpose registers to be saved - this argument is |
| 1109 | always present even when it is 0; |
| 1110 | 2) FP register number (27) if FP has to be stored, otherwise argument |
| 1111 | is not present; |
| 1112 | 3) BLINK register number (31) if BLINK has to be stored, otherwise |
| 1113 | argument is not present. If both FP and BLINK are stored, then FP |
| 1114 | is present before BLINK in argument list. */ |
| 1115 | gdb_assert (insn.operands_count > 0); |
| 1116 | |
| 1117 | int regs_saved = arc_insn_get_operand_value (insn, 0); |
| 1118 | |
| 1119 | bool is_fp_saved; |
| 1120 | if (insn.operands_count > 1) |
| 1121 | is_fp_saved = (insn.operands[1].value == ARC_FP_REGNUM); |
| 1122 | else |
| 1123 | is_fp_saved = false; |
| 1124 | |
| 1125 | bool is_blink_saved; |
| 1126 | if (insn.operands_count > 1) |
| 1127 | is_blink_saved = (insn.operands[insn.operands_count - 1].value |
| 1128 | == ARC_BLINK_REGNUM); |
| 1129 | else |
| 1130 | is_blink_saved = false; |
| 1131 | |
| 1132 | /* Amount of bytes to be allocated to store specified registers. */ |
| 1133 | CORE_ADDR st_size = ((regs_saved + is_fp_saved + is_blink_saved) |
| 1134 | * ARC_REGISTER_SIZE); |
| 1135 | pv_t new_sp = pv_add_constant (regs[ARC_SP_REGNUM], -st_size); |
| 1136 | |
| 1137 | /* Assume that if the last register (closest to new SP) can be written, |
| 1138 | then it is possible to write all of them. */ |
| 1139 | if (pv_area_store_would_trash (stack, new_sp)) |
| 1140 | return false; |
| 1141 | |
| 1142 | /* Current store address. */ |
| 1143 | pv_t addr = regs[ARC_SP_REGNUM]; |
| 1144 | |
| 1145 | if (is_fp_saved) |
| 1146 | { |
| 1147 | addr = pv_add_constant (addr, -ARC_REGISTER_SIZE); |
| 1148 | pv_area_store (stack, addr, ARC_REGISTER_SIZE, regs[ARC_FP_REGNUM]); |
| 1149 | } |
| 1150 | |
| 1151 | /* Registers are stored in backward order: from GP (R26) to R13. */ |
| 1152 | for (int i = ARC_R13_REGNUM + regs_saved - 1; i >= ARC_R13_REGNUM; i--) |
| 1153 | { |
| 1154 | addr = pv_add_constant (addr, -ARC_REGISTER_SIZE); |
| 1155 | pv_area_store (stack, addr, ARC_REGISTER_SIZE, regs[i]); |
| 1156 | } |
| 1157 | |
| 1158 | if (is_blink_saved) |
| 1159 | { |
| 1160 | addr = pv_add_constant (addr, -ARC_REGISTER_SIZE); |
| 1161 | pv_area_store (stack, addr, ARC_REGISTER_SIZE, |
| 1162 | regs[ARC_BLINK_REGNUM]); |
| 1163 | } |
| 1164 | |
| 1165 | gdb_assert (pv_is_identical (addr, new_sp)); |
| 1166 | |
| 1167 | regs[ARC_SP_REGNUM] = new_sp; |
| 1168 | |
| 1169 | if (is_fp_saved) |
| 1170 | regs[ARC_FP_REGNUM] = regs[ARC_SP_REGNUM]; |
| 1171 | |
| 1172 | return true; |
| 1173 | } |
| 1174 | |
| 1175 | /* Some other architectures, like nds32 or arm, try to continue as far as |
| 1176 | possible when building a prologue cache (as opposed to when skipping |
| 1177 | prologue), so that cache will be as full as possible. However current |
| 1178 | code for ARC doesn't recognize some instructions that may modify SP, like |
| 1179 | ADD, AND, OR, etc, hence there is no way to guarantee that SP wasn't |
| 1180 | clobbered by the skipped instruction. Potential existence of extension |
| 1181 | instruction, which may do anything they want makes this even more complex, |
| 1182 | so it is just better to halt on a first unrecognized instruction. */ |
| 1183 | |
| 1184 | return false; |
| 1185 | } |
| 1186 | |
| 1187 | /* Copy of gdb_buffered_insn_length_fprintf from disasm.c. */ |
| 1188 | |
| 1189 | static int ATTRIBUTE_PRINTF (2, 3) |
| 1190 | arc_fprintf_disasm (void *stream, const char *format, ...) |
| 1191 | { |
| 1192 | return 0; |
| 1193 | } |
| 1194 | |
| 1195 | struct disassemble_info |
| 1196 | arc_disassemble_info (struct gdbarch *gdbarch) |
| 1197 | { |
| 1198 | struct disassemble_info di; |
| 1199 | init_disassemble_info (&di, &null_stream, arc_fprintf_disasm); |
| 1200 | di.arch = gdbarch_bfd_arch_info (gdbarch)->arch; |
| 1201 | di.mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
| 1202 | di.endian = gdbarch_byte_order (gdbarch); |
| 1203 | di.read_memory_func = [](bfd_vma memaddr, gdb_byte *myaddr, |
| 1204 | unsigned int len, struct disassemble_info *info) |
| 1205 | { |
| 1206 | return target_read_code (memaddr, myaddr, len); |
| 1207 | }; |
| 1208 | return di; |
| 1209 | } |
| 1210 | |
| 1211 | /* Analyze the prologue and update the corresponding frame cache for the frame |
| 1212 | unwinder for unwinding frames that doesn't have debug info. In such |
| 1213 | situation GDB attempts to parse instructions in the prologue to understand |
| 1214 | where each register is saved. |
| 1215 | |
| 1216 | If CACHE is not NULL, then it will be filled with information about saved |
| 1217 | registers. |
| 1218 | |
| 1219 | There are several variations of prologue which GDB may encouter. "Full" |
| 1220 | prologue looks like this: |
| 1221 | |
| 1222 | sub sp,sp,<imm> ; Space for variadic arguments. |
| 1223 | push blink ; Store return address. |
| 1224 | push r13 ; Store callee saved registers (up to R26/GP). |
| 1225 | push r14 |
| 1226 | push fp ; Store frame pointer. |
| 1227 | mov fp,sp ; Update frame pointer. |
| 1228 | sub sp,sp,<imm> ; Create space for local vars on the stack. |
| 1229 | |
| 1230 | Depending on compiler options lots of things may change: |
| 1231 | |
| 1232 | 1) BLINK is not saved in leaf functions. |
| 1233 | 2) Frame pointer is not saved and updated if -fomit-frame-pointer is used. |
| 1234 | 3) 16-bit versions of those instructions may be used. |
| 1235 | 4) Instead of a sequence of several push'es, compiler may instead prefer to |
| 1236 | do one subtract on stack pointer and then store registers using normal |
| 1237 | store, that doesn't update SP. Like this: |
| 1238 | |
| 1239 | |
| 1240 | sub sp,sp,8 ; Create space for calee-saved registers. |
| 1241 | st r13,[sp,4] ; Store callee saved registers (up to R26/GP). |
| 1242 | st r14,[sp,0] |
| 1243 | |
| 1244 | 5) ENTER_S instruction can encode most of prologue sequence in one |
| 1245 | instruction (except for those subtracts for variadic arguments and local |
| 1246 | variables). |
| 1247 | 6) GCC may use "millicode" functions from libgcc to store callee-saved |
| 1248 | registers with minimal code-size requirements. This function currently |
| 1249 | doesn't support this. |
| 1250 | |
| 1251 | ENTRYPOINT is a function entry point where prologue starts. |
| 1252 | |
| 1253 | LIMIT_PC is a maximum possible end address of prologue (meaning address |
| 1254 | of first instruction after the prologue). It might also point to the middle |
| 1255 | of prologue if execution has been stopped by the breakpoint at this address |
| 1256 | - in this case debugger should analyze prologue only up to this address, |
| 1257 | because further instructions haven't been executed yet. |
| 1258 | |
| 1259 | Returns address of the first instruction after the prologue. */ |
| 1260 | |
| 1261 | static CORE_ADDR |
| 1262 | arc_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR entrypoint, |
| 1263 | const CORE_ADDR limit_pc, struct arc_frame_cache *cache) |
| 1264 | { |
| 1265 | if (arc_debug) |
| 1266 | debug_printf ("arc: analyze_prologue (entrypoint=%s, limit_pc=%s)\n", |
| 1267 | paddress (gdbarch, entrypoint), |
| 1268 | paddress (gdbarch, limit_pc)); |
| 1269 | |
| 1270 | /* Prologue values. Only core registers can be stored. */ |
| 1271 | pv_t regs[ARC_LAST_CORE_REGNUM + 1]; |
| 1272 | for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) |
| 1273 | regs[i] = pv_register (i, 0); |
| 1274 | struct pv_area *stack = make_pv_area (ARC_SP_REGNUM, |
| 1275 | gdbarch_addr_bit (gdbarch)); |
| 1276 | struct cleanup *back_to = make_cleanup_free_pv_area (stack); |
| 1277 | |
| 1278 | CORE_ADDR current_prologue_end = entrypoint; |
| 1279 | |
| 1280 | /* Look at each instruction in the prologue. */ |
| 1281 | while (current_prologue_end < limit_pc) |
| 1282 | { |
| 1283 | struct arc_instruction insn; |
| 1284 | struct disassemble_info di = arc_disassemble_info (gdbarch); |
| 1285 | arc_insn_decode (current_prologue_end, &di, arc_delayed_print_insn, |
| 1286 | &insn); |
| 1287 | |
| 1288 | if (arc_debug >= 2) |
| 1289 | arc_insn_dump (insn); |
| 1290 | |
| 1291 | /* If this instruction is in the prologue, fields in the cache will be |
| 1292 | updated, and the saved registers mask may be updated. */ |
| 1293 | if (!arc_is_in_prologue (gdbarch, insn, regs, stack)) |
| 1294 | { |
| 1295 | /* Found an instruction that is not in the prologue. */ |
| 1296 | if (arc_debug) |
| 1297 | debug_printf ("arc: End of prologue reached at address %s\n", |
| 1298 | paddress (gdbarch, insn.address)); |
| 1299 | break; |
| 1300 | } |
| 1301 | |
| 1302 | current_prologue_end = arc_insn_get_linear_next_pc (insn); |
| 1303 | } |
| 1304 | |
| 1305 | if (cache != NULL) |
| 1306 | { |
| 1307 | /* Figure out if it is a frame pointer or just a stack pointer. */ |
| 1308 | if (pv_is_register (regs[ARC_FP_REGNUM], ARC_SP_REGNUM)) |
| 1309 | { |
| 1310 | cache->frame_base_reg = ARC_FP_REGNUM; |
| 1311 | cache->frame_base_offset = -regs[ARC_FP_REGNUM].k; |
| 1312 | } |
| 1313 | else |
| 1314 | { |
| 1315 | cache->frame_base_reg = ARC_SP_REGNUM; |
| 1316 | cache->frame_base_offset = -regs[ARC_SP_REGNUM].k; |
| 1317 | } |
| 1318 | |
| 1319 | /* Assign offset from old SP to all saved registers. */ |
| 1320 | for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) |
| 1321 | { |
| 1322 | CORE_ADDR offset; |
| 1323 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) |
| 1324 | cache->saved_regs[i].addr = offset; |
| 1325 | } |
| 1326 | } |
| 1327 | |
| 1328 | do_cleanups (back_to); |
| 1329 | return current_prologue_end; |
| 1330 | } |
| 1331 | |
| 1332 | /* Estimated maximum prologue length in bytes. This should include: |
| 1333 | 1) Store instruction for each callee-saved register (R25 - R13 + 1) |
| 1334 | 2) Two instructions for FP |
| 1335 | 3) One for BLINK |
| 1336 | 4) Three substract instructions for SP (for variadic args, for |
| 1337 | callee saved regs and for local vars) and assuming that those SUB use |
| 1338 | long-immediate (hence double length). |
| 1339 | 5) Stores of arguments registers are considered part of prologue too |
| 1340 | (R7 - R1 + 1). |
| 1341 | This is quite an extreme case, because even with -O0 GCC will collapse first |
| 1342 | two SUBs into one and long immediate values are quite unlikely to appear in |
| 1343 | this case, but still better to overshoot a bit - prologue analysis will |
| 1344 | anyway stop at the first instruction that doesn't fit prologue, so this |
| 1345 | limit will be rarely reached. */ |
| 1346 | |
| 1347 | const static int MAX_PROLOGUE_LENGTH |
| 1348 | = 4 * (ARC_R25_REGNUM - ARC_R13_REGNUM + 1 + 2 + 1 + 6 |
| 1349 | + ARC_LAST_ARG_REGNUM - ARC_FIRST_ARG_REGNUM + 1); |
| 1350 | |
| 1351 | /* Implement the "skip_prologue" gdbarch method. |
| 1352 | |
| 1353 | Skip the prologue for the function at PC. This is done by checking from |
| 1354 | the line information read from the DWARF, if possible; otherwise, we scan |
| 1355 | the function prologue to find its end. */ |
| 1356 | |
| 1357 | static CORE_ADDR |
| 1358 | arc_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1359 | { |
| 1360 | if (arc_debug) |
| 1361 | debug_printf ("arc: skip_prologue\n"); |
| 1362 | |
| 1363 | CORE_ADDR func_addr; |
| 1364 | const char *func_name; |
| 1365 | |
| 1366 | /* See what the symbol table says. */ |
| 1367 | if (find_pc_partial_function (pc, &func_name, &func_addr, NULL)) |
| 1368 | { |
| 1369 | /* Found a function. */ |
| 1370 | CORE_ADDR postprologue_pc |
| 1371 | = skip_prologue_using_sal (gdbarch, func_addr); |
| 1372 | |
| 1373 | if (postprologue_pc != 0) |
| 1374 | return std::max (pc, postprologue_pc); |
| 1375 | } |
| 1376 | |
| 1377 | /* No prologue info in symbol table, have to analyze prologue. */ |
| 1378 | |
| 1379 | /* Find an upper limit on the function prologue using the debug |
| 1380 | information. If there is no debug information about prologue end, then |
| 1381 | skip_prologue_using_sal will return 0. */ |
| 1382 | CORE_ADDR limit_pc = skip_prologue_using_sal (gdbarch, pc); |
| 1383 | |
| 1384 | /* If there is no debug information at all, it is required to give some |
| 1385 | semi-arbitrary hard limit on amount of bytes to scan during prologue |
| 1386 | analysis. */ |
| 1387 | if (limit_pc == 0) |
| 1388 | limit_pc = pc + MAX_PROLOGUE_LENGTH; |
| 1389 | |
| 1390 | /* Find the address of the first instruction after the prologue by scanning |
| 1391 | through it - no other information is needed, so pass NULL as a cache. */ |
| 1392 | return arc_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
| 1393 | } |
| 1394 | |
| 1395 | /* Implement the "print_insn" gdbarch method. |
| 1396 | |
| 1397 | arc_get_disassembler () may return different functions depending on bfd |
| 1398 | type, so it is not possible to pass print_insn directly to |
| 1399 | set_gdbarch_print_insn (). Instead this wrapper function is used. It also |
| 1400 | may be used by other functions to get disassemble_info for address. It is |
| 1401 | important to note, that those print_insn from opcodes always print |
| 1402 | instruction to the stream specified in the INFO. If this is not desired, |
| 1403 | then either `print_insn` function in INFO should be set to some function |
| 1404 | that will not print, or `stream` should be different from standard |
| 1405 | gdb_stdlog. */ |
| 1406 | |
| 1407 | int |
| 1408 | arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info) |
| 1409 | { |
| 1410 | /* Standard BFD "machine number" field allows libocodes disassembler to |
| 1411 | distinguish ARC 600, 700 and v2 cores, however v2 encompasses both ARC EM |
| 1412 | and HS, which have some difference between. There are two ways to specify |
| 1413 | what is the target core: |
| 1414 | 1) via the disassemble_info->disassembler_options; |
| 1415 | 2) otherwise libopcodes will use private (architecture-specific) ELF |
| 1416 | header. |
| 1417 | |
| 1418 | Using disassembler_options is preferable, because it comes directly from |
| 1419 | GDBserver which scanned an actual ARC core identification info. However, |
| 1420 | not all GDBservers report core architecture, so as a fallback GDB still |
| 1421 | should support analysis of ELF header. The libopcodes disassembly code |
| 1422 | uses the section to find the BFD and the BFD to find the ELF header, |
| 1423 | therefore this function should set disassemble_info->section properly. |
| 1424 | |
| 1425 | disassembler_options was already set by non-target specific code with |
| 1426 | proper options obtained via gdbarch_disassembler_options (). |
| 1427 | |
| 1428 | This function might be called multiple times in a sequence, reusing same |
| 1429 | disassemble_info. */ |
| 1430 | if ((info->disassembler_options == NULL) && (info->section == NULL)) |
| 1431 | { |
| 1432 | struct obj_section *s = find_pc_section (addr); |
| 1433 | if (s != NULL) |
| 1434 | info->section = s->the_bfd_section; |
| 1435 | } |
| 1436 | |
| 1437 | return default_print_insn (addr, info); |
| 1438 | } |
| 1439 | |
| 1440 | /* Baremetal breakpoint instructions. |
| 1441 | |
| 1442 | ARC supports both big- and little-endian. However, instructions for |
| 1443 | little-endian processors are encoded in the middle-endian: half-words are |
| 1444 | in big-endian, while bytes inside the half-words are in little-endian; data |
| 1445 | is represented in the "normal" little-endian. Big-endian processors treat |
| 1446 | data and code identically. |
| 1447 | |
| 1448 | Assuming the number 0x01020304, it will be presented this way: |
| 1449 | |
| 1450 | Address : N N+1 N+2 N+3 |
| 1451 | little-endian : 0x04 0x03 0x02 0x01 |
| 1452 | big-endian : 0x01 0x02 0x03 0x04 |
| 1453 | ARC middle-endian : 0x02 0x01 0x04 0x03 |
| 1454 | */ |
| 1455 | |
| 1456 | static const gdb_byte arc_brk_s_be[] = { 0x7f, 0xff }; |
| 1457 | static const gdb_byte arc_brk_s_le[] = { 0xff, 0x7f }; |
| 1458 | static const gdb_byte arc_brk_be[] = { 0x25, 0x6f, 0x00, 0x3f }; |
| 1459 | static const gdb_byte arc_brk_le[] = { 0x6f, 0x25, 0x3f, 0x00 }; |
| 1460 | |
| 1461 | /* For ARC ELF, breakpoint uses the 16-bit BRK_S instruction, which is 0x7fff |
| 1462 | (little endian) or 0xff7f (big endian). We used to insert BRK_S even |
| 1463 | instead of 32-bit instructions, which works mostly ok, unless breakpoint is |
| 1464 | inserted into delay slot instruction. In this case if branch is taken |
| 1465 | BLINK value will be set to address of instruction after delay slot, however |
| 1466 | if we replaced 32-bit instruction in delay slot with 16-bit long BRK_S, |
| 1467 | then BLINK value will have an invalid value - it will point to the address |
| 1468 | after the BRK_S (which was there at the moment of branch execution) while |
| 1469 | it should point to the address after the 32-bit long instruction. To avoid |
| 1470 | such issues this function disassembles instruction at target location and |
| 1471 | evaluates it value. |
| 1472 | |
| 1473 | ARC 600 supports only 16-bit BRK_S. |
| 1474 | |
| 1475 | NB: Baremetal GDB uses BRK[_S], while user-space GDB uses TRAP_S. BRK[_S] |
| 1476 | is much better because it doesn't commit unlike TRAP_S, so it can be set in |
| 1477 | delay slots; however it cannot be used in user-mode, hence usage of TRAP_S |
| 1478 | in GDB for user-space. */ |
| 1479 | |
| 1480 | /* Implement the "breakpoint_kind_from_pc" gdbarch method. */ |
| 1481 | |
| 1482 | static int |
| 1483 | arc_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) |
| 1484 | { |
| 1485 | size_t length_with_limm = gdb_insn_length (gdbarch, *pcptr); |
| 1486 | |
| 1487 | /* Replace 16-bit instruction with BRK_S, replace 32-bit instructions with |
| 1488 | BRK. LIMM is part of instruction length, so it can be either 4 or 8 |
| 1489 | bytes for 32-bit instructions. */ |
| 1490 | if ((length_with_limm == 4 || length_with_limm == 8) |
| 1491 | && !arc_mach_is_arc600 (gdbarch)) |
| 1492 | return sizeof (arc_brk_le); |
| 1493 | else |
| 1494 | return sizeof (arc_brk_s_le); |
| 1495 | } |
| 1496 | |
| 1497 | /* Implement the "sw_breakpoint_from_kind" gdbarch method. */ |
| 1498 | |
| 1499 | static const gdb_byte * |
| 1500 | arc_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
| 1501 | { |
| 1502 | *size = kind; |
| 1503 | |
| 1504 | if (kind == sizeof (arc_brk_le)) |
| 1505 | { |
| 1506 | return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 1507 | ? arc_brk_be |
| 1508 | : arc_brk_le); |
| 1509 | } |
| 1510 | else |
| 1511 | { |
| 1512 | return ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 1513 | ? arc_brk_s_be |
| 1514 | : arc_brk_s_le); |
| 1515 | } |
| 1516 | } |
| 1517 | |
| 1518 | /* Implement the "unwind_pc" gdbarch method. */ |
| 1519 | |
| 1520 | static CORE_ADDR |
| 1521 | arc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1522 | { |
| 1523 | int pc_regnum = gdbarch_pc_regnum (gdbarch); |
| 1524 | CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, pc_regnum); |
| 1525 | |
| 1526 | if (arc_debug) |
| 1527 | debug_printf ("arc: unwind PC: %s\n", paddress (gdbarch, pc)); |
| 1528 | |
| 1529 | return pc; |
| 1530 | } |
| 1531 | |
| 1532 | /* Implement the "unwind_sp" gdbarch method. */ |
| 1533 | |
| 1534 | static CORE_ADDR |
| 1535 | arc_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1536 | { |
| 1537 | int sp_regnum = gdbarch_sp_regnum (gdbarch); |
| 1538 | CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, sp_regnum); |
| 1539 | |
| 1540 | if (arc_debug) |
| 1541 | debug_printf ("arc: unwind SP: %s\n", paddress (gdbarch, sp)); |
| 1542 | |
| 1543 | return sp; |
| 1544 | } |
| 1545 | |
| 1546 | /* Implement the "frame_align" gdbarch method. */ |
| 1547 | |
| 1548 | static CORE_ADDR |
| 1549 | arc_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 1550 | { |
| 1551 | return align_down (sp, 4); |
| 1552 | } |
| 1553 | |
| 1554 | /* Dump the frame info. Used for internal debugging only. */ |
| 1555 | |
| 1556 | static void |
| 1557 | arc_print_frame_cache (struct gdbarch *gdbarch, const char *message, |
| 1558 | struct arc_frame_cache *cache, int addresses_known) |
| 1559 | { |
| 1560 | debug_printf ("arc: frame_info %s\n", message); |
| 1561 | debug_printf ("arc: prev_sp = %s\n", paddress (gdbarch, cache->prev_sp)); |
| 1562 | debug_printf ("arc: frame_base_reg = %i\n", cache->frame_base_reg); |
| 1563 | debug_printf ("arc: frame_base_offset = %s\n", |
| 1564 | plongest (cache->frame_base_offset)); |
| 1565 | |
| 1566 | for (int i = 0; i <= ARC_BLINK_REGNUM; i++) |
| 1567 | { |
| 1568 | if (trad_frame_addr_p (cache->saved_regs, i)) |
| 1569 | debug_printf ("arc: saved register %s at %s %s\n", |
| 1570 | gdbarch_register_name (gdbarch, i), |
| 1571 | (addresses_known) ? "address" : "offset", |
| 1572 | paddress (gdbarch, cache->saved_regs[i].addr)); |
| 1573 | } |
| 1574 | } |
| 1575 | |
| 1576 | /* Frame unwinder for normal frames. */ |
| 1577 | |
| 1578 | static struct arc_frame_cache * |
| 1579 | arc_make_frame_cache (struct frame_info *this_frame) |
| 1580 | { |
| 1581 | if (arc_debug) |
| 1582 | debug_printf ("arc: frame_cache\n"); |
| 1583 | |
| 1584 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1585 | |
| 1586 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); |
| 1587 | CORE_ADDR entrypoint, prologue_end; |
| 1588 | if (find_pc_partial_function (block_addr, NULL, &entrypoint, &prologue_end)) |
| 1589 | { |
| 1590 | struct symtab_and_line sal = find_pc_line (entrypoint, 0); |
| 1591 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
| 1592 | if (sal.line == 0) |
| 1593 | /* No line info so use current PC. */ |
| 1594 | prologue_end = prev_pc; |
| 1595 | else if (sal.end < prologue_end) |
| 1596 | /* The next line begins after the function end. */ |
| 1597 | prologue_end = sal.end; |
| 1598 | |
| 1599 | prologue_end = std::min (prologue_end, prev_pc); |
| 1600 | } |
| 1601 | else |
| 1602 | { |
| 1603 | /* If find_pc_partial_function returned nothing then there is no symbol |
| 1604 | information at all for this PC. Currently it is assumed in this case |
| 1605 | that current PC is entrypoint to function and try to construct the |
| 1606 | frame from that. This is, probably, suboptimal, for example ARM |
| 1607 | assumes in this case that program is inside the normal frame (with |
| 1608 | frame pointer). ARC, perhaps, should try to do the same. */ |
| 1609 | entrypoint = get_frame_register_unsigned (this_frame, |
| 1610 | gdbarch_pc_regnum (gdbarch)); |
| 1611 | prologue_end = entrypoint + MAX_PROLOGUE_LENGTH; |
| 1612 | } |
| 1613 | |
| 1614 | /* Allocate new frame cache instance and space for saved register info. |
| 1615 | FRAME_OBSTACK_ZALLOC will initialize fields to zeroes. */ |
| 1616 | struct arc_frame_cache *cache |
| 1617 | = FRAME_OBSTACK_ZALLOC (struct arc_frame_cache); |
| 1618 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1619 | |
| 1620 | arc_analyze_prologue (gdbarch, entrypoint, prologue_end, cache); |
| 1621 | |
| 1622 | if (arc_debug) |
| 1623 | arc_print_frame_cache (gdbarch, "after prologue", cache, false); |
| 1624 | |
| 1625 | CORE_ADDR unwound_fb = get_frame_register_unsigned (this_frame, |
| 1626 | cache->frame_base_reg); |
| 1627 | if (unwound_fb == 0) |
| 1628 | return cache; |
| 1629 | cache->prev_sp = unwound_fb + cache->frame_base_offset; |
| 1630 | |
| 1631 | for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) |
| 1632 | { |
| 1633 | if (trad_frame_addr_p (cache->saved_regs, i)) |
| 1634 | cache->saved_regs[i].addr += cache->prev_sp; |
| 1635 | } |
| 1636 | |
| 1637 | if (arc_debug) |
| 1638 | arc_print_frame_cache (gdbarch, "after previous SP found", cache, true); |
| 1639 | |
| 1640 | return cache; |
| 1641 | } |
| 1642 | |
| 1643 | /* Implement the "this_id" frame_unwind method. */ |
| 1644 | |
| 1645 | static void |
| 1646 | arc_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 1647 | struct frame_id *this_id) |
| 1648 | { |
| 1649 | if (arc_debug) |
| 1650 | debug_printf ("arc: frame_this_id\n"); |
| 1651 | |
| 1652 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1653 | |
| 1654 | if (*this_cache == NULL) |
| 1655 | *this_cache = arc_make_frame_cache (this_frame); |
| 1656 | struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache); |
| 1657 | |
| 1658 | CORE_ADDR stack_addr = cache->prev_sp; |
| 1659 | |
| 1660 | /* There are 4 possible situation which decide how frame_id->code_addr is |
| 1661 | evaluated: |
| 1662 | |
| 1663 | 1) Function is compiled with option -g. Then frame_id will be created |
| 1664 | in dwarf_* function and not in this function. NB: even if target |
| 1665 | binary is compiled with -g, some std functions like __start and _init |
| 1666 | are not, so they still will follow one of the following choices. |
| 1667 | |
| 1668 | 2) Function is compiled without -g and binary hasn't been stripped in |
| 1669 | any way. In this case GDB still has enough information to evaluate |
| 1670 | frame code_addr properly. This case is covered by call to |
| 1671 | get_frame_func (). |
| 1672 | |
| 1673 | 3) Binary has been striped with option -g (strip debug symbols). In |
| 1674 | this case there is still enough symbols for get_frame_func () to work |
| 1675 | properly, so this case is also covered by it. |
| 1676 | |
| 1677 | 4) Binary has been striped with option -s (strip all symbols). In this |
| 1678 | case GDB cannot get function start address properly, so we return current |
| 1679 | PC value instead. |
| 1680 | */ |
| 1681 | CORE_ADDR code_addr = get_frame_func (this_frame); |
| 1682 | if (code_addr == 0) |
| 1683 | code_addr = get_frame_register_unsigned (this_frame, |
| 1684 | gdbarch_pc_regnum (gdbarch)); |
| 1685 | |
| 1686 | *this_id = frame_id_build (stack_addr, code_addr); |
| 1687 | } |
| 1688 | |
| 1689 | /* Implement the "prev_register" frame_unwind method. */ |
| 1690 | |
| 1691 | static struct value * |
| 1692 | arc_frame_prev_register (struct frame_info *this_frame, |
| 1693 | void **this_cache, int regnum) |
| 1694 | { |
| 1695 | if (*this_cache == NULL) |
| 1696 | *this_cache = arc_make_frame_cache (this_frame); |
| 1697 | struct arc_frame_cache *cache = (struct arc_frame_cache *) (*this_cache); |
| 1698 | |
| 1699 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1700 | |
| 1701 | /* If we are asked to unwind the PC, then we need to return BLINK instead: |
| 1702 | the saved value of PC points into this frame's function's prologue, not |
| 1703 | the next frame's function's resume location. */ |
| 1704 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
| 1705 | regnum = ARC_BLINK_REGNUM; |
| 1706 | |
| 1707 | /* SP is a special case - we should return prev_sp, because |
| 1708 | trad_frame_get_prev_register will return _current_ SP value. |
| 1709 | Alternatively we could have stored cache->prev_sp in the cache->saved |
| 1710 | regs, but here we follow the lead of AArch64, ARM and Xtensa and will |
| 1711 | leave that logic in this function, instead of prologue analyzers. That I |
| 1712 | think is a bit more clear as `saved_regs` should contain saved regs, not |
| 1713 | computable. |
| 1714 | |
| 1715 | Because value has been computed, "got_constant" should be used, so that |
| 1716 | returned value will be a "not_lval" - immutable. */ |
| 1717 | |
| 1718 | if (regnum == gdbarch_sp_regnum (gdbarch)) |
| 1719 | return frame_unwind_got_constant (this_frame, regnum, cache->prev_sp); |
| 1720 | |
| 1721 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum); |
| 1722 | } |
| 1723 | |
| 1724 | /* Implement the "init_reg" dwarf2_frame method. */ |
| 1725 | |
| 1726 | static void |
| 1727 | arc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, |
| 1728 | struct dwarf2_frame_state_reg *reg, |
| 1729 | struct frame_info *info) |
| 1730 | { |
| 1731 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
| 1732 | /* The return address column. */ |
| 1733 | reg->how = DWARF2_FRAME_REG_RA; |
| 1734 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
| 1735 | /* The call frame address. */ |
| 1736 | reg->how = DWARF2_FRAME_REG_CFA; |
| 1737 | } |
| 1738 | |
| 1739 | /* Structure defining the ARC ordinary frame unwind functions. Since we are |
| 1740 | the fallback unwinder, we use the default frame sniffer, which always |
| 1741 | accepts the frame. */ |
| 1742 | |
| 1743 | static const struct frame_unwind arc_frame_unwind = { |
| 1744 | NORMAL_FRAME, |
| 1745 | default_frame_unwind_stop_reason, |
| 1746 | arc_frame_this_id, |
| 1747 | arc_frame_prev_register, |
| 1748 | NULL, |
| 1749 | default_frame_sniffer, |
| 1750 | NULL, |
| 1751 | NULL |
| 1752 | }; |
| 1753 | |
| 1754 | |
| 1755 | static const struct frame_base arc_normal_base = { |
| 1756 | &arc_frame_unwind, |
| 1757 | arc_frame_base_address, |
| 1758 | arc_frame_base_address, |
| 1759 | arc_frame_base_address |
| 1760 | }; |
| 1761 | |
| 1762 | /* Initialize target description for the ARC. |
| 1763 | |
| 1764 | Returns TRUE if input tdesc was valid and in this case it will assign TDESC |
| 1765 | and TDESC_DATA output parameters. */ |
| 1766 | |
| 1767 | static int |
| 1768 | arc_tdesc_init (struct gdbarch_info info, const struct target_desc **tdesc, |
| 1769 | struct tdesc_arch_data **tdesc_data) |
| 1770 | { |
| 1771 | if (arc_debug) |
| 1772 | debug_printf ("arc: Target description initialization.\n"); |
| 1773 | |
| 1774 | const struct target_desc *tdesc_loc = info.target_desc; |
| 1775 | |
| 1776 | /* Depending on whether this is ARCompact or ARCv2 we will assign |
| 1777 | different default registers sets (which will differ in exactly two core |
| 1778 | registers). GDB will also refuse to accept register feature from invalid |
| 1779 | ISA - v2 features can be used only with v2 ARChitecture. We read |
| 1780 | bfd_arch_info, which looks like to be a safe bet here, as it looks like it |
| 1781 | is always initialized even when we don't pass any elf file to GDB at all |
| 1782 | (it uses default arch in this case). Also GDB will call this function |
| 1783 | multiple times, and if XML target description file contains architecture |
| 1784 | specifications, then GDB will set this architecture to info.bfd_arch_info, |
| 1785 | overriding value from ELF file if they are different. That means that, |
| 1786 | where matters, this value is always our best guess on what CPU we are |
| 1787 | debugging. It has been noted that architecture specified in tdesc file |
| 1788 | has higher precedence over ELF and even "set architecture" - that is, |
| 1789 | using "set architecture" command will have no effect when tdesc has "arch" |
| 1790 | tag. */ |
| 1791 | /* Cannot use arc_mach_is_arcv2 (), because gdbarch is not created yet. */ |
| 1792 | const int is_arcv2 = (info.bfd_arch_info->mach == bfd_mach_arc_arcv2); |
| 1793 | int is_reduced_rf; |
| 1794 | const char *const *core_regs; |
| 1795 | const char *core_feature_name; |
| 1796 | |
| 1797 | /* If target doesn't provide a description - use default one. */ |
| 1798 | if (!tdesc_has_registers (tdesc_loc)) |
| 1799 | { |
| 1800 | if (is_arcv2) |
| 1801 | { |
| 1802 | tdesc_loc = tdesc_arc_v2; |
| 1803 | if (arc_debug) |
| 1804 | debug_printf ("arc: Using default register set for ARC v2.\n"); |
| 1805 | } |
| 1806 | else |
| 1807 | { |
| 1808 | tdesc_loc = tdesc_arc_arcompact; |
| 1809 | if (arc_debug) |
| 1810 | debug_printf ("arc: Using default register set for ARCompact.\n"); |
| 1811 | } |
| 1812 | } |
| 1813 | else |
| 1814 | { |
| 1815 | if (arc_debug) |
| 1816 | debug_printf ("arc: Using provided register set.\n"); |
| 1817 | } |
| 1818 | gdb_assert (tdesc_loc != NULL); |
| 1819 | |
| 1820 | /* Now we can search for base registers. Core registers can be either full |
| 1821 | or reduced. Summary: |
| 1822 | |
| 1823 | - core.v2 + aux-minimal |
| 1824 | - core-reduced.v2 + aux-minimal |
| 1825 | - core.arcompact + aux-minimal |
| 1826 | |
| 1827 | NB: It is entirely feasible to have ARCompact with reduced core regs, but |
| 1828 | we ignore that because GCC doesn't support that and at the same time |
| 1829 | ARCompact is considered obsolete, so there is not much reason to support |
| 1830 | that. */ |
| 1831 | const struct tdesc_feature *feature |
| 1832 | = tdesc_find_feature (tdesc_loc, core_v2_feature_name); |
| 1833 | if (feature != NULL) |
| 1834 | { |
| 1835 | /* Confirm that register and architecture match, to prevent accidents in |
| 1836 | some situations. This code will trigger an error if: |
| 1837 | |
| 1838 | 1. XML tdesc doesn't specify arch explicitly, registers are for arch |
| 1839 | X, but ELF specifies arch Y. |
| 1840 | |
| 1841 | 2. XML tdesc specifies arch X, but contains registers for arch Y. |
| 1842 | |
| 1843 | It will not protect from case where XML or ELF specify arch X, |
| 1844 | registers are for the same arch X, but the real target is arch Y. To |
| 1845 | detect this case we need to check IDENTITY register. */ |
| 1846 | if (!is_arcv2) |
| 1847 | { |
| 1848 | arc_print (_("Error: ARC v2 target description supplied for " |
| 1849 | "non-ARCv2 target.\n")); |
| 1850 | return FALSE; |
| 1851 | } |
| 1852 | |
| 1853 | is_reduced_rf = FALSE; |
| 1854 | core_feature_name = core_v2_feature_name; |
| 1855 | core_regs = core_v2_register_names; |
| 1856 | } |
| 1857 | else |
| 1858 | { |
| 1859 | feature = tdesc_find_feature (tdesc_loc, core_reduced_v2_feature_name); |
| 1860 | if (feature != NULL) |
| 1861 | { |
| 1862 | if (!is_arcv2) |
| 1863 | { |
| 1864 | arc_print (_("Error: ARC v2 target description supplied for " |
| 1865 | "non-ARCv2 target.\n")); |
| 1866 | return FALSE; |
| 1867 | } |
| 1868 | |
| 1869 | is_reduced_rf = TRUE; |
| 1870 | core_feature_name = core_reduced_v2_feature_name; |
| 1871 | core_regs = core_v2_register_names; |
| 1872 | } |
| 1873 | else |
| 1874 | { |
| 1875 | feature = tdesc_find_feature (tdesc_loc, |
| 1876 | core_arcompact_feature_name); |
| 1877 | if (feature != NULL) |
| 1878 | { |
| 1879 | if (is_arcv2) |
| 1880 | { |
| 1881 | arc_print (_("Error: ARCompact target description supplied " |
| 1882 | "for non-ARCompact target.\n")); |
| 1883 | return FALSE; |
| 1884 | } |
| 1885 | |
| 1886 | is_reduced_rf = FALSE; |
| 1887 | core_feature_name = core_arcompact_feature_name; |
| 1888 | core_regs = core_arcompact_register_names; |
| 1889 | } |
| 1890 | else |
| 1891 | { |
| 1892 | arc_print (_("Error: Couldn't find core register feature in " |
| 1893 | "supplied target description.")); |
| 1894 | return FALSE; |
| 1895 | } |
| 1896 | } |
| 1897 | } |
| 1898 | |
| 1899 | struct tdesc_arch_data *tdesc_data_loc = tdesc_data_alloc (); |
| 1900 | |
| 1901 | gdb_assert (feature != NULL); |
| 1902 | int valid_p = 1; |
| 1903 | |
| 1904 | for (int i = 0; i <= ARC_LAST_CORE_REGNUM; i++) |
| 1905 | { |
| 1906 | /* If rf16, then skip extra registers. */ |
| 1907 | if (is_reduced_rf && ((i >= ARC_R4_REGNUM && i <= ARC_R9_REGNUM) |
| 1908 | || (i >= ARC_R16_REGNUM && i <= ARC_R25_REGNUM))) |
| 1909 | continue; |
| 1910 | |
| 1911 | valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i, |
| 1912 | core_regs[i]); |
| 1913 | |
| 1914 | /* - Ignore errors in extension registers - they are optional. |
| 1915 | - Ignore missing ILINK because it doesn't make sense for Linux. |
| 1916 | - Ignore missing ILINK2 when architecture is ARCompact, because it |
| 1917 | doesn't make sense for Linux targets. |
| 1918 | |
| 1919 | In theory those optional registers should be in separate features, but |
| 1920 | that would create numerous but tiny features, which looks like an |
| 1921 | overengineering of a rather simple task. */ |
| 1922 | if (!valid_p && (i <= ARC_SP_REGNUM || i == ARC_BLINK_REGNUM |
| 1923 | || i == ARC_LP_COUNT_REGNUM || i == ARC_PCL_REGNUM |
| 1924 | || (i == ARC_R30_REGNUM && is_arcv2))) |
| 1925 | { |
| 1926 | arc_print (_("Error: Cannot find required register `%s' in " |
| 1927 | "feature `%s'.\n"), core_regs[i], core_feature_name); |
| 1928 | tdesc_data_cleanup (tdesc_data_loc); |
| 1929 | return FALSE; |
| 1930 | } |
| 1931 | } |
| 1932 | |
| 1933 | /* Mandatory AUX registeres are intentionally few and are common between |
| 1934 | ARCompact and ARC v2, so same code can be used for both. */ |
| 1935 | feature = tdesc_find_feature (tdesc_loc, aux_minimal_feature_name); |
| 1936 | if (feature == NULL) |
| 1937 | { |
| 1938 | arc_print (_("Error: Cannot find required feature `%s' in supplied " |
| 1939 | "target description.\n"), aux_minimal_feature_name); |
| 1940 | tdesc_data_cleanup (tdesc_data_loc); |
| 1941 | return FALSE; |
| 1942 | } |
| 1943 | |
| 1944 | for (int i = ARC_FIRST_AUX_REGNUM; i <= ARC_LAST_AUX_REGNUM; i++) |
| 1945 | { |
| 1946 | const char *name = aux_minimal_register_names[i - ARC_FIRST_AUX_REGNUM]; |
| 1947 | valid_p = tdesc_numbered_register (feature, tdesc_data_loc, i, name); |
| 1948 | if (!valid_p) |
| 1949 | { |
| 1950 | arc_print (_("Error: Cannot find required register `%s' " |
| 1951 | "in feature `%s'.\n"), |
| 1952 | name, tdesc_feature_name (feature)); |
| 1953 | tdesc_data_cleanup (tdesc_data_loc); |
| 1954 | return FALSE; |
| 1955 | } |
| 1956 | } |
| 1957 | |
| 1958 | *tdesc = tdesc_loc; |
| 1959 | *tdesc_data = tdesc_data_loc; |
| 1960 | |
| 1961 | return TRUE; |
| 1962 | } |
| 1963 | |
| 1964 | /* Implement the "init" gdbarch method. */ |
| 1965 | |
| 1966 | static struct gdbarch * |
| 1967 | arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1968 | { |
| 1969 | const struct target_desc *tdesc; |
| 1970 | struct tdesc_arch_data *tdesc_data; |
| 1971 | |
| 1972 | if (arc_debug) |
| 1973 | debug_printf ("arc: Architecture initialization.\n"); |
| 1974 | |
| 1975 | if (!arc_tdesc_init (info, &tdesc, &tdesc_data)) |
| 1976 | return NULL; |
| 1977 | |
| 1978 | /* Allocate the ARC-private target-dependent information structure, and the |
| 1979 | GDB target-independent information structure. */ |
| 1980 | struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep); |
| 1981 | tdep->jb_pc = -1; /* No longjmp support by default. */ |
| 1982 | struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep); |
| 1983 | |
| 1984 | /* Data types. */ |
| 1985 | set_gdbarch_short_bit (gdbarch, 16); |
| 1986 | set_gdbarch_int_bit (gdbarch, 32); |
| 1987 | set_gdbarch_long_bit (gdbarch, 32); |
| 1988 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 1989 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
| 1990 | set_gdbarch_float_bit (gdbarch, 32); |
| 1991 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 1992 | set_gdbarch_double_bit (gdbarch, 64); |
| 1993 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); |
| 1994 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 1995 | set_gdbarch_addr_bit (gdbarch, 32); |
| 1996 | set_gdbarch_char_signed (gdbarch, 0); |
| 1997 | |
| 1998 | set_gdbarch_write_pc (gdbarch, arc_write_pc); |
| 1999 | |
| 2000 | set_gdbarch_virtual_frame_pointer (gdbarch, arc_virtual_frame_pointer); |
| 2001 | |
| 2002 | /* tdesc_use_registers expects gdbarch_num_regs to return number of registers |
| 2003 | parsed by gdbarch_init, and then it will add all of the remaining |
| 2004 | registers and will increase number of registers. */ |
| 2005 | set_gdbarch_num_regs (gdbarch, ARC_LAST_REGNUM + 1); |
| 2006 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
| 2007 | set_gdbarch_sp_regnum (gdbarch, ARC_SP_REGNUM); |
| 2008 | set_gdbarch_pc_regnum (gdbarch, ARC_PC_REGNUM); |
| 2009 | set_gdbarch_ps_regnum (gdbarch, ARC_STATUS32_REGNUM); |
| 2010 | set_gdbarch_fp0_regnum (gdbarch, -1); /* No FPU registers. */ |
| 2011 | |
| 2012 | set_gdbarch_dummy_id (gdbarch, arc_dummy_id); |
| 2013 | set_gdbarch_push_dummy_call (gdbarch, arc_push_dummy_call); |
| 2014 | set_gdbarch_push_dummy_code (gdbarch, arc_push_dummy_code); |
| 2015 | |
| 2016 | set_gdbarch_cannot_fetch_register (gdbarch, arc_cannot_fetch_register); |
| 2017 | set_gdbarch_cannot_store_register (gdbarch, arc_cannot_store_register); |
| 2018 | |
| 2019 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
| 2020 | |
| 2021 | set_gdbarch_return_value (gdbarch, arc_return_value); |
| 2022 | |
| 2023 | set_gdbarch_skip_prologue (gdbarch, arc_skip_prologue); |
| 2024 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 2025 | |
| 2026 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, arc_breakpoint_kind_from_pc); |
| 2027 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, arc_sw_breakpoint_from_kind); |
| 2028 | |
| 2029 | /* On ARC 600 BRK_S instruction advances PC, unlike other ARC cores. */ |
| 2030 | if (!arc_mach_is_arc600 (gdbarch)) |
| 2031 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
| 2032 | else |
| 2033 | set_gdbarch_decr_pc_after_break (gdbarch, 2); |
| 2034 | |
| 2035 | set_gdbarch_unwind_pc (gdbarch, arc_unwind_pc); |
| 2036 | set_gdbarch_unwind_sp (gdbarch, arc_unwind_sp); |
| 2037 | |
| 2038 | set_gdbarch_frame_align (gdbarch, arc_frame_align); |
| 2039 | |
| 2040 | set_gdbarch_print_insn (gdbarch, arc_delayed_print_insn); |
| 2041 | |
| 2042 | set_gdbarch_cannot_step_breakpoint (gdbarch, 1); |
| 2043 | |
| 2044 | /* "nonsteppable" watchpoint means that watchpoint triggers before |
| 2045 | instruction is committed, therefore it is required to remove watchpoint |
| 2046 | to step though instruction that triggers it. ARC watchpoints trigger |
| 2047 | only after instruction is committed, thus there is no need to remove |
| 2048 | them. In fact on ARC watchpoint for memory writes may trigger with more |
| 2049 | significant delay, like one or two instructions, depending on type of |
| 2050 | memory where write is performed (CCM or external) and next instruction |
| 2051 | after the memory write. */ |
| 2052 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 0); |
| 2053 | |
| 2054 | /* This doesn't include possible long-immediate value. */ |
| 2055 | set_gdbarch_max_insn_length (gdbarch, 4); |
| 2056 | |
| 2057 | /* Frame unwinders and sniffers. */ |
| 2058 | dwarf2_frame_set_init_reg (gdbarch, arc_dwarf2_frame_init_reg); |
| 2059 | dwarf2_append_unwinders (gdbarch); |
| 2060 | frame_unwind_append_unwinder (gdbarch, &arc_frame_unwind); |
| 2061 | frame_base_set_default (gdbarch, &arc_normal_base); |
| 2062 | |
| 2063 | /* Setup stuff specific to a particular environment (baremetal or Linux). |
| 2064 | It can override functions set earlier. */ |
| 2065 | gdbarch_init_osabi (info, gdbarch); |
| 2066 | |
| 2067 | if (tdep->jb_pc >= 0) |
| 2068 | set_gdbarch_get_longjmp_target (gdbarch, arc_get_longjmp_target); |
| 2069 | |
| 2070 | /* Disassembler options. Enforce CPU if it was specified in XML target |
| 2071 | description, otherwise use default method of determining CPU (ELF private |
| 2072 | header). */ |
| 2073 | if (info.target_desc != NULL) |
| 2074 | { |
| 2075 | const struct bfd_arch_info *tdesc_arch |
| 2076 | = tdesc_architecture (info.target_desc); |
| 2077 | if (tdesc_arch != NULL) |
| 2078 | { |
| 2079 | xfree (arc_disassembler_options); |
| 2080 | /* FIXME: It is not really good to change disassembler options |
| 2081 | behind the scene, because that might override options |
| 2082 | specified by the user. However as of now ARC doesn't support |
| 2083 | `set disassembler-options' hence this code is the only place |
| 2084 | where options are changed. It also changes options for all |
| 2085 | existing gdbarches, which also can be problematic, if |
| 2086 | arc_gdbarch_init will start reusing existing gdbarch |
| 2087 | instances. */ |
| 2088 | arc_disassembler_options = xstrprintf ("cpu=%s", |
| 2089 | tdesc_arch->printable_name); |
| 2090 | set_gdbarch_disassembler_options (gdbarch, |
| 2091 | &arc_disassembler_options); |
| 2092 | } |
| 2093 | } |
| 2094 | |
| 2095 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
| 2096 | |
| 2097 | return gdbarch; |
| 2098 | } |
| 2099 | |
| 2100 | /* Implement the "dump_tdep" gdbarch method. */ |
| 2101 | |
| 2102 | static void |
| 2103 | arc_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
| 2104 | { |
| 2105 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2106 | |
| 2107 | fprintf_unfiltered (file, "arc_dump_tdep: jb_pc = %i\n", tdep->jb_pc); |
| 2108 | } |
| 2109 | |
| 2110 | /* Wrapper for "maintenance print arc" list of commands. */ |
| 2111 | |
| 2112 | static void |
| 2113 | maintenance_print_arc_command (char *args, int from_tty) |
| 2114 | { |
| 2115 | cmd_show_list (maintenance_print_arc_list, from_tty, ""); |
| 2116 | } |
| 2117 | |
| 2118 | /* This command accepts single argument - address of instruction to |
| 2119 | disassemble. */ |
| 2120 | |
| 2121 | static void |
| 2122 | dump_arc_instruction_command (char *args, int from_tty) |
| 2123 | { |
| 2124 | struct value *val; |
| 2125 | if (args != NULL && strlen (args) > 0) |
| 2126 | val = evaluate_expression (parse_expression (args).get ()); |
| 2127 | else |
| 2128 | val = access_value_history (0); |
| 2129 | record_latest_value (val); |
| 2130 | |
| 2131 | CORE_ADDR address = value_as_address (val); |
| 2132 | struct arc_instruction insn; |
| 2133 | struct disassemble_info di = arc_disassemble_info (target_gdbarch ()); |
| 2134 | arc_insn_decode (address, &di, arc_delayed_print_insn, &insn); |
| 2135 | arc_insn_dump (insn); |
| 2136 | } |
| 2137 | |
| 2138 | void |
| 2139 | _initialize_arc_tdep (void) |
| 2140 | { |
| 2141 | gdbarch_register (bfd_arch_arc, arc_gdbarch_init, arc_dump_tdep); |
| 2142 | |
| 2143 | initialize_tdesc_arc_v2 (); |
| 2144 | initialize_tdesc_arc_arcompact (); |
| 2145 | |
| 2146 | /* Register ARC-specific commands with gdb. */ |
| 2147 | |
| 2148 | /* Add root prefix command for "maintenance print arc" commands. */ |
| 2149 | add_prefix_cmd ("arc", class_maintenance, maintenance_print_arc_command, |
| 2150 | _("ARC-specific maintenance commands for printing GDB " |
| 2151 | "internal state."), |
| 2152 | &maintenance_print_arc_list, "maintenance print arc ", 0, |
| 2153 | &maintenanceprintlist); |
| 2154 | |
| 2155 | add_cmd ("arc-instruction", class_maintenance, |
| 2156 | dump_arc_instruction_command, |
| 2157 | _("Dump arc_instruction structure for specified address."), |
| 2158 | &maintenance_print_arc_list); |
| 2159 | |
| 2160 | /* Debug internals for ARC GDB. */ |
| 2161 | add_setshow_zinteger_cmd ("arc", class_maintenance, |
| 2162 | &arc_debug, |
| 2163 | _("Set ARC specific debugging."), |
| 2164 | _("Show ARC specific debugging."), |
| 2165 | _("Non-zero enables ARC specific debugging."), |
| 2166 | NULL, NULL, &setdebuglist, &showdebuglist); |
| 2167 | } |