| 1 | /* Common target dependent code for GDB on ARM systems. |
| 2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000 |
| 3 | Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 59 Temple Place - Suite 330, |
| 20 | Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "frame.h" |
| 24 | #include "inferior.h" |
| 25 | #include "gdbcmd.h" |
| 26 | #include "gdbcore.h" |
| 27 | #include "symfile.h" |
| 28 | #include "gdb_string.h" |
| 29 | #include "coff/internal.h" /* Internal format of COFF symbols in BFD */ |
| 30 | #include "dis-asm.h" /* For register flavors. */ |
| 31 | #include <ctype.h> /* for isupper () */ |
| 32 | |
| 33 | /* Each OS has a different mechanism for accessing the various |
| 34 | registers stored in the sigcontext structure. |
| 35 | |
| 36 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or |
| 37 | function pointer) which may be used to determine the addresses |
| 38 | of the various saved registers in the sigcontext structure. |
| 39 | |
| 40 | For the ARM target, there are three parameters to this function. |
| 41 | The first is the pc value of the frame under consideration, the |
| 42 | second the stack pointer of this frame, and the last is the |
| 43 | register number to fetch. |
| 44 | |
| 45 | If the tm.h file does not define this macro, then it's assumed that |
| 46 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to |
| 47 | be 0. |
| 48 | |
| 49 | When it comes time to multi-arching this code, see the identically |
| 50 | named machinery in ia64-tdep.c for an example of how it could be |
| 51 | done. It should not be necessary to modify the code below where |
| 52 | this macro is used. */ |
| 53 | |
| 54 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
| 55 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P |
| 56 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 |
| 57 | #endif |
| 58 | #else |
| 59 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 |
| 60 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 |
| 61 | #endif |
| 62 | |
| 63 | extern void _initialize_arm_tdep (void); |
| 64 | |
| 65 | /* Number of different reg name sets (options). */ |
| 66 | static int num_flavor_options; |
| 67 | |
| 68 | /* We have more registers than the disassembler as gdb can print the value |
| 69 | of special registers as well. |
| 70 | The general register names are overwritten by whatever is being used by |
| 71 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
| 72 | |
| 73 | /* Initial value: Register names used in ARM's ISA documentation. */ |
| 74 | static char * arm_register_name_strings[] = |
| 75 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
| 76 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ |
| 77 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ |
| 78 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ |
| 79 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ |
| 80 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ |
| 81 | "fps", "cpsr" }; /* 24 25 */ |
| 82 | char **arm_register_names = arm_register_name_strings; |
| 83 | |
| 84 | /* Valid register name flavors. */ |
| 85 | static const char **valid_flavors; |
| 86 | |
| 87 | /* Disassembly flavor to use. Default to "std" register names. */ |
| 88 | static const char *disassembly_flavor; |
| 89 | static int current_option; /* Index to that option in the opcodes table. */ |
| 90 | |
| 91 | /* This is used to keep the bfd arch_info in sync with the disassembly |
| 92 | flavor. */ |
| 93 | static void set_disassembly_flavor_sfunc(char *, int, |
| 94 | struct cmd_list_element *); |
| 95 | static void set_disassembly_flavor (void); |
| 96 | |
| 97 | static void convert_from_extended (void *ptr, void *dbl); |
| 98 | |
| 99 | /* Define other aspects of the stack frame. We keep the offsets of |
| 100 | all saved registers, 'cause we need 'em a lot! We also keep the |
| 101 | current size of the stack frame, and the offset of the frame |
| 102 | pointer from the stack pointer (for frameless functions, and when |
| 103 | we're still in the prologue of a function with a frame) */ |
| 104 | |
| 105 | struct frame_extra_info |
| 106 | { |
| 107 | struct frame_saved_regs fsr; |
| 108 | int framesize; |
| 109 | int frameoffset; |
| 110 | int framereg; |
| 111 | }; |
| 112 | |
| 113 | /* Addresses for calling Thumb functions have the bit 0 set. |
| 114 | Here are some macros to test, set, or clear bit 0 of addresses. */ |
| 115 | #define IS_THUMB_ADDR(addr) ((addr) & 1) |
| 116 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) |
| 117 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) |
| 118 | |
| 119 | #define SWAP_TARGET_AND_HOST(buffer,len) \ |
| 120 | do \ |
| 121 | { \ |
| 122 | if (TARGET_BYTE_ORDER != HOST_BYTE_ORDER) \ |
| 123 | { \ |
| 124 | char tmp; \ |
| 125 | char *p = (char *)(buffer); \ |
| 126 | char *q = ((char *)(buffer)) + len - 1; \ |
| 127 | for (; p < q; p++, q--) \ |
| 128 | { \ |
| 129 | tmp = *q; \ |
| 130 | *q = *p; \ |
| 131 | *p = tmp; \ |
| 132 | } \ |
| 133 | } \ |
| 134 | } \ |
| 135 | while (0) |
| 136 | |
| 137 | /* Will a function return an aggregate type in memory or in a |
| 138 | register? Return 0 if an aggregate type can be returned in a |
| 139 | register, 1 if it must be returned in memory. */ |
| 140 | |
| 141 | int |
| 142 | arm_use_struct_convention (int gcc_p, struct type *type) |
| 143 | { |
| 144 | int nRc; |
| 145 | register enum type_code code; |
| 146 | |
| 147 | /* In the ARM ABI, "integer" like aggregate types are returned in |
| 148 | registers. For an aggregate type to be integer like, its size |
| 149 | must be less than or equal to REGISTER_SIZE and the offset of |
| 150 | each addressable subfield must be zero. Note that bit fields are |
| 151 | not addressable, and all addressable subfields of unions always |
| 152 | start at offset zero. |
| 153 | |
| 154 | This function is based on the behaviour of GCC 2.95.1. |
| 155 | See: gcc/arm.c: arm_return_in_memory() for details. |
| 156 | |
| 157 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
| 158 | parameters correctly for a function returning the following |
| 159 | structure: struct { float f;}; This should be returned in memory, |
| 160 | not a register. Richard Earnshaw sent me a patch, but I do not |
| 161 | know of any way to detect if a function like the above has been |
| 162 | compiled with the correct calling convention. */ |
| 163 | |
| 164 | /* All aggregate types that won't fit in a register must be returned |
| 165 | in memory. */ |
| 166 | if (TYPE_LENGTH (type) > REGISTER_SIZE) |
| 167 | { |
| 168 | return 1; |
| 169 | } |
| 170 | |
| 171 | /* The only aggregate types that can be returned in a register are |
| 172 | structs and unions. Arrays must be returned in memory. */ |
| 173 | code = TYPE_CODE (type); |
| 174 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) |
| 175 | { |
| 176 | return 1; |
| 177 | } |
| 178 | |
| 179 | /* Assume all other aggregate types can be returned in a register. |
| 180 | Run a check for structures, unions and arrays. */ |
| 181 | nRc = 0; |
| 182 | |
| 183 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
| 184 | { |
| 185 | int i; |
| 186 | /* Need to check if this struct/union is "integer" like. For |
| 187 | this to be true, its size must be less than or equal to |
| 188 | REGISTER_SIZE and the offset of each addressable subfield |
| 189 | must be zero. Note that bit fields are not addressable, and |
| 190 | unions always start at offset zero. If any of the subfields |
| 191 | is a floating point type, the struct/union cannot be an |
| 192 | integer type. */ |
| 193 | |
| 194 | /* For each field in the object, check: |
| 195 | 1) Is it FP? --> yes, nRc = 1; |
| 196 | 2) Is it addressable (bitpos != 0) and |
| 197 | not packed (bitsize == 0)? |
| 198 | --> yes, nRc = 1 |
| 199 | */ |
| 200 | |
| 201 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 202 | { |
| 203 | enum type_code field_type_code; |
| 204 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); |
| 205 | |
| 206 | /* Is it a floating point type field? */ |
| 207 | if (field_type_code == TYPE_CODE_FLT) |
| 208 | { |
| 209 | nRc = 1; |
| 210 | break; |
| 211 | } |
| 212 | |
| 213 | /* If bitpos != 0, then we have to care about it. */ |
| 214 | if (TYPE_FIELD_BITPOS (type, i) != 0) |
| 215 | { |
| 216 | /* Bitfields are not addressable. If the field bitsize is |
| 217 | zero, then the field is not packed. Hence it cannot be |
| 218 | a bitfield or any other packed type. */ |
| 219 | if (TYPE_FIELD_BITSIZE (type, i) == 0) |
| 220 | { |
| 221 | nRc = 1; |
| 222 | break; |
| 223 | } |
| 224 | } |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | return nRc; |
| 229 | } |
| 230 | |
| 231 | int |
| 232 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
| 233 | { |
| 234 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
| 235 | } |
| 236 | |
| 237 | /* Set to true if the 32-bit mode is in use. */ |
| 238 | |
| 239 | int arm_apcs_32 = 1; |
| 240 | |
| 241 | /* Flag set by arm_fix_call_dummy that tells whether the target |
| 242 | function is a Thumb function. This flag is checked by |
| 243 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and |
| 244 | its use in valops.c) to pass the function address as an additional |
| 245 | parameter. */ |
| 246 | |
| 247 | static int target_is_thumb; |
| 248 | |
| 249 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
| 250 | function is a Thumb function. This flag is checked by |
| 251 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ |
| 252 | |
| 253 | static int caller_is_thumb; |
| 254 | |
| 255 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
| 256 | function. */ |
| 257 | |
| 258 | int |
| 259 | arm_pc_is_thumb (CORE_ADDR memaddr) |
| 260 | { |
| 261 | struct minimal_symbol *sym; |
| 262 | |
| 263 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
| 264 | if (IS_THUMB_ADDR (memaddr)) |
| 265 | return 1; |
| 266 | |
| 267 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
| 268 | sym = lookup_minimal_symbol_by_pc (memaddr); |
| 269 | if (sym) |
| 270 | { |
| 271 | return (MSYMBOL_IS_SPECIAL (sym)); |
| 272 | } |
| 273 | else |
| 274 | { |
| 275 | return 0; |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | /* Determine if the program counter specified in MEMADDR is in a call |
| 280 | dummy being called from a Thumb function. */ |
| 281 | |
| 282 | int |
| 283 | arm_pc_is_thumb_dummy (CORE_ADDR memaddr) |
| 284 | { |
| 285 | CORE_ADDR sp = read_sp (); |
| 286 | |
| 287 | /* FIXME: Until we switch for the new call dummy macros, this heuristic |
| 288 | is the best we can do. We are trying to determine if the pc is on |
| 289 | the stack, which (hopefully) will only happen in a call dummy. |
| 290 | We hope the current stack pointer is not so far alway from the dummy |
| 291 | frame location (true if we have not pushed large data structures or |
| 292 | gone too many levels deep) and that our 1024 is not enough to consider |
| 293 | code regions as part of the stack (true for most practical purposes) */ |
| 294 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024)) |
| 295 | return caller_is_thumb; |
| 296 | else |
| 297 | return 0; |
| 298 | } |
| 299 | |
| 300 | CORE_ADDR |
| 301 | arm_addr_bits_remove (CORE_ADDR val) |
| 302 | { |
| 303 | if (arm_pc_is_thumb (val)) |
| 304 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); |
| 305 | else |
| 306 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); |
| 307 | } |
| 308 | |
| 309 | CORE_ADDR |
| 310 | arm_saved_pc_after_call (struct frame_info *frame) |
| 311 | { |
| 312 | return ADDR_BITS_REMOVE (read_register (LR_REGNUM)); |
| 313 | } |
| 314 | |
| 315 | int |
| 316 | arm_frameless_function_invocation (struct frame_info *fi) |
| 317 | { |
| 318 | CORE_ADDR func_start, after_prologue; |
| 319 | int frameless; |
| 320 | |
| 321 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
| 322 | after_prologue = SKIP_PROLOGUE (func_start); |
| 323 | |
| 324 | /* There are some frameless functions whose first two instructions |
| 325 | follow the standard APCS form, in which case after_prologue will |
| 326 | be func_start + 8. */ |
| 327 | |
| 328 | frameless = (after_prologue < func_start + 12); |
| 329 | return frameless; |
| 330 | } |
| 331 | |
| 332 | /* A typical Thumb prologue looks like this: |
| 333 | push {r7, lr} |
| 334 | add sp, sp, #-28 |
| 335 | add r7, sp, #12 |
| 336 | Sometimes the latter instruction may be replaced by: |
| 337 | mov r7, sp |
| 338 | |
| 339 | or like this: |
| 340 | push {r7, lr} |
| 341 | mov r7, sp |
| 342 | sub sp, #12 |
| 343 | |
| 344 | or, on tpcs, like this: |
| 345 | sub sp,#16 |
| 346 | push {r7, lr} |
| 347 | (many instructions) |
| 348 | mov r7, sp |
| 349 | sub sp, #12 |
| 350 | |
| 351 | There is always one instruction of three classes: |
| 352 | 1 - push |
| 353 | 2 - setting of r7 |
| 354 | 3 - adjusting of sp |
| 355 | |
| 356 | When we have found at least one of each class we are done with the prolog. |
| 357 | Note that the "sub sp, #NN" before the push does not count. |
| 358 | */ |
| 359 | |
| 360 | static CORE_ADDR |
| 361 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
| 362 | { |
| 363 | CORE_ADDR current_pc; |
| 364 | int findmask = 0; /* findmask: |
| 365 | bit 0 - push { rlist } |
| 366 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) |
| 367 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) |
| 368 | */ |
| 369 | |
| 370 | for (current_pc = pc; current_pc + 2 < func_end && current_pc < pc + 40; current_pc += 2) |
| 371 | { |
| 372 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); |
| 373 | |
| 374 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 375 | { |
| 376 | findmask |= 1; /* push found */ |
| 377 | } |
| 378 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */ |
| 379 | { |
| 380 | if ((findmask & 1) == 0) /* before push ? */ |
| 381 | continue; |
| 382 | else |
| 383 | findmask |= 4; /* add/sub sp found */ |
| 384 | } |
| 385 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 386 | { |
| 387 | findmask |= 2; /* setting of r7 found */ |
| 388 | } |
| 389 | else if (insn == 0x466f) /* mov r7, sp */ |
| 390 | { |
| 391 | findmask |= 2; /* setting of r7 found */ |
| 392 | } |
| 393 | else |
| 394 | continue; /* something in the prolog that we don't care about or some |
| 395 | instruction from outside the prolog scheduled here for optimization */ |
| 396 | } |
| 397 | |
| 398 | return current_pc; |
| 399 | } |
| 400 | |
| 401 | /* The APCS (ARM Procedure Call Standard) defines the following |
| 402 | prologue: |
| 403 | |
| 404 | mov ip, sp |
| 405 | [stmfd sp!, {a1,a2,a3,a4}] |
| 406 | stmfd sp!, {...,fp,ip,lr,pc} |
| 407 | [stfe f7, [sp, #-12]!] |
| 408 | [stfe f6, [sp, #-12]!] |
| 409 | [stfe f5, [sp, #-12]!] |
| 410 | [stfe f4, [sp, #-12]!] |
| 411 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ |
| 412 | |
| 413 | CORE_ADDR |
| 414 | arm_skip_prologue (CORE_ADDR pc) |
| 415 | { |
| 416 | unsigned long inst; |
| 417 | CORE_ADDR skip_pc; |
| 418 | CORE_ADDR func_addr, func_end; |
| 419 | struct symtab_and_line sal; |
| 420 | |
| 421 | /* See what the symbol table says. */ |
| 422 | |
| 423 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 424 | { |
| 425 | sal = find_pc_line (func_addr, 0); |
| 426 | if ((sal.line != 0) && (sal.end < func_end)) |
| 427 | return sal.end; |
| 428 | } |
| 429 | |
| 430 | /* Check if this is Thumb code. */ |
| 431 | if (arm_pc_is_thumb (pc)) |
| 432 | return thumb_skip_prologue (pc, func_end); |
| 433 | |
| 434 | /* Can't find the prologue end in the symbol table, try it the hard way |
| 435 | by disassembling the instructions. */ |
| 436 | skip_pc = pc; |
| 437 | inst = read_memory_integer (skip_pc, 4); |
| 438 | if (inst != 0xe1a0c00d) /* mov ip, sp */ |
| 439 | return pc; |
| 440 | |
| 441 | skip_pc += 4; |
| 442 | inst = read_memory_integer (skip_pc, 4); |
| 443 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
| 444 | { |
| 445 | skip_pc += 4; |
| 446 | inst = read_memory_integer (skip_pc, 4); |
| 447 | } |
| 448 | |
| 449 | if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */ |
| 450 | return pc; |
| 451 | |
| 452 | skip_pc += 4; |
| 453 | inst = read_memory_integer (skip_pc, 4); |
| 454 | |
| 455 | /* Any insns after this point may float into the code, if it makes |
| 456 | for better instruction scheduling, so we skip them only if we |
| 457 | find them, but still consdier the function to be frame-ful. */ |
| 458 | |
| 459 | /* We may have either one sfmfd instruction here, or several stfe |
| 460 | insns, depending on the version of floating point code we |
| 461 | support. */ |
| 462 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
| 463 | { |
| 464 | skip_pc += 4; |
| 465 | inst = read_memory_integer (skip_pc, 4); |
| 466 | } |
| 467 | else |
| 468 | { |
| 469 | while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
| 470 | { |
| 471 | skip_pc += 4; |
| 472 | inst = read_memory_integer (skip_pc, 4); |
| 473 | } |
| 474 | } |
| 475 | |
| 476 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
| 477 | skip_pc += 4; |
| 478 | |
| 479 | return skip_pc; |
| 480 | } |
| 481 | /* *INDENT-OFF* */ |
| 482 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
| 483 | This function decodes a Thumb function prologue to determine: |
| 484 | 1) the size of the stack frame |
| 485 | 2) which registers are saved on it |
| 486 | 3) the offsets of saved regs |
| 487 | 4) the offset from the stack pointer to the frame pointer |
| 488 | This information is stored in the "extra" fields of the frame_info. |
| 489 | |
| 490 | A typical Thumb function prologue would create this stack frame |
| 491 | (offsets relative to FP) |
| 492 | old SP -> 24 stack parameters |
| 493 | 20 LR |
| 494 | 16 R7 |
| 495 | R7 -> 0 local variables (16 bytes) |
| 496 | SP -> -12 additional stack space (12 bytes) |
| 497 | The frame size would thus be 36 bytes, and the frame offset would be |
| 498 | 12 bytes. The frame register is R7. |
| 499 | |
| 500 | The comments for thumb_skip_prolog() describe the algorithm we use to detect |
| 501 | the end of the prolog */ |
| 502 | /* *INDENT-ON* */ |
| 503 | |
| 504 | static void |
| 505 | thumb_scan_prologue (struct frame_info *fi) |
| 506 | { |
| 507 | CORE_ADDR prologue_start; |
| 508 | CORE_ADDR prologue_end; |
| 509 | CORE_ADDR current_pc; |
| 510 | int saved_reg[16]; /* which register has been copied to register n? */ |
| 511 | int findmask = 0; /* findmask: |
| 512 | bit 0 - push { rlist } |
| 513 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) |
| 514 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) |
| 515 | */ |
| 516 | int i; |
| 517 | |
| 518 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
| 519 | { |
| 520 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 521 | |
| 522 | if (sal.line == 0) /* no line info, use current PC */ |
| 523 | prologue_end = fi->pc; |
| 524 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
| 525 | prologue_end = sal.end; /* (probably means no prologue) */ |
| 526 | } |
| 527 | else |
| 528 | prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */ |
| 529 | /* 16 pushes, an add, and "mv fp,sp" */ |
| 530 | |
| 531 | prologue_end = min (prologue_end, fi->pc); |
| 532 | |
| 533 | /* Initialize the saved register map. When register H is copied to |
| 534 | register L, we will put H in saved_reg[L]. */ |
| 535 | for (i = 0; i < 16; i++) |
| 536 | saved_reg[i] = i; |
| 537 | |
| 538 | /* Search the prologue looking for instructions that set up the |
| 539 | frame pointer, adjust the stack pointer, and save registers. |
| 540 | Do this until all basic prolog instructions are found. */ |
| 541 | |
| 542 | fi->framesize = 0; |
| 543 | for (current_pc = prologue_start; |
| 544 | (current_pc < prologue_end) && ((findmask & 7) != 7); |
| 545 | current_pc += 2) |
| 546 | { |
| 547 | unsigned short insn; |
| 548 | int regno; |
| 549 | int offset; |
| 550 | |
| 551 | insn = read_memory_unsigned_integer (current_pc, 2); |
| 552 | |
| 553 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 554 | { |
| 555 | int mask; |
| 556 | findmask |= 1; /* push found */ |
| 557 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
| 558 | whether to save LR (R14). */ |
| 559 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
| 560 | |
| 561 | /* Calculate offsets of saved R0-R7 and LR. */ |
| 562 | for (regno = LR_REGNUM; regno >= 0; regno--) |
| 563 | if (mask & (1 << regno)) |
| 564 | { |
| 565 | fi->framesize += 4; |
| 566 | fi->fsr.regs[saved_reg[regno]] = -(fi->framesize); |
| 567 | saved_reg[regno] = regno; /* reset saved register map */ |
| 568 | } |
| 569 | } |
| 570 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */ |
| 571 | { |
| 572 | if ((findmask & 1) == 0) /* before push ? */ |
| 573 | continue; |
| 574 | else |
| 575 | findmask |= 4; /* add/sub sp found */ |
| 576 | |
| 577 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
| 578 | if (insn & 0x80) /* is it signed? (==subtracting) */ |
| 579 | { |
| 580 | fi->frameoffset += offset; |
| 581 | offset = -offset; |
| 582 | } |
| 583 | fi->framesize -= offset; |
| 584 | } |
| 585 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 586 | { |
| 587 | findmask |= 2; /* setting of r7 found */ |
| 588 | fi->framereg = THUMB_FP_REGNUM; |
| 589 | fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */ |
| 590 | } |
| 591 | else if (insn == 0x466f) /* mov r7, sp */ |
| 592 | { |
| 593 | findmask |= 2; /* setting of r7 found */ |
| 594 | fi->framereg = THUMB_FP_REGNUM; |
| 595 | fi->frameoffset = 0; |
| 596 | saved_reg[THUMB_FP_REGNUM] = SP_REGNUM; |
| 597 | } |
| 598 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ |
| 599 | { |
| 600 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
| 601 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
| 602 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
| 603 | } |
| 604 | else |
| 605 | continue; /* something in the prolog that we don't care about or some |
| 606 | instruction from outside the prolog scheduled here for optimization */ |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | /* Check if prologue for this frame's PC has already been scanned. If |
| 611 | it has, copy the relevant information about that prologue and |
| 612 | return non-zero. Otherwise do not copy anything and return zero. |
| 613 | |
| 614 | The information saved in the cache includes: |
| 615 | * the frame register number; |
| 616 | * the size of the stack frame; |
| 617 | * the offsets of saved regs (relative to the old SP); and |
| 618 | * the offset from the stack pointer to the frame pointer |
| 619 | |
| 620 | The cache contains only one entry, since this is adequate for the |
| 621 | typical sequence of prologue scan requests we get. When performing |
| 622 | a backtrace, GDB will usually ask to scan the same function twice |
| 623 | in a row (once to get the frame chain, and once to fill in the |
| 624 | extra frame information). */ |
| 625 | |
| 626 | static struct frame_info prologue_cache; |
| 627 | |
| 628 | static int |
| 629 | check_prologue_cache (struct frame_info *fi) |
| 630 | { |
| 631 | int i; |
| 632 | |
| 633 | if (fi->pc == prologue_cache.pc) |
| 634 | { |
| 635 | fi->framereg = prologue_cache.framereg; |
| 636 | fi->framesize = prologue_cache.framesize; |
| 637 | fi->frameoffset = prologue_cache.frameoffset; |
| 638 | for (i = 0; i <= NUM_REGS; i++) |
| 639 | fi->fsr.regs[i] = prologue_cache.fsr.regs[i]; |
| 640 | return 1; |
| 641 | } |
| 642 | else |
| 643 | return 0; |
| 644 | } |
| 645 | |
| 646 | |
| 647 | /* Copy the prologue information from fi to the prologue cache. */ |
| 648 | |
| 649 | static void |
| 650 | save_prologue_cache (struct frame_info *fi) |
| 651 | { |
| 652 | int i; |
| 653 | |
| 654 | prologue_cache.pc = fi->pc; |
| 655 | prologue_cache.framereg = fi->framereg; |
| 656 | prologue_cache.framesize = fi->framesize; |
| 657 | prologue_cache.frameoffset = fi->frameoffset; |
| 658 | |
| 659 | for (i = 0; i <= NUM_REGS; i++) |
| 660 | prologue_cache.fsr.regs[i] = fi->fsr.regs[i]; |
| 661 | } |
| 662 | |
| 663 | |
| 664 | /* This function decodes an ARM function prologue to determine: |
| 665 | 1) the size of the stack frame |
| 666 | 2) which registers are saved on it |
| 667 | 3) the offsets of saved regs |
| 668 | 4) the offset from the stack pointer to the frame pointer |
| 669 | This information is stored in the "extra" fields of the frame_info. |
| 670 | |
| 671 | There are two basic forms for the ARM prologue. The fixed argument |
| 672 | function call will look like: |
| 673 | |
| 674 | mov ip, sp |
| 675 | stmfd sp!, {fp, ip, lr, pc} |
| 676 | sub fp, ip, #4 |
| 677 | [sub sp, sp, #4] |
| 678 | |
| 679 | Which would create this stack frame (offsets relative to FP): |
| 680 | IP -> 4 (caller's stack) |
| 681 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 682 | -4 LR (return address in caller) |
| 683 | -8 IP (copy of caller's SP) |
| 684 | -12 FP (caller's FP) |
| 685 | SP -> -28 Local variables |
| 686 | |
| 687 | The frame size would thus be 32 bytes, and the frame offset would be |
| 688 | 28 bytes. The stmfd call can also save any of the vN registers it |
| 689 | plans to use, which increases the frame size accordingly. |
| 690 | |
| 691 | Note: The stored PC is 8 off of the STMFD instruction that stored it |
| 692 | because the ARM Store instructions always store PC + 8 when you read |
| 693 | the PC register. |
| 694 | |
| 695 | A variable argument function call will look like: |
| 696 | |
| 697 | mov ip, sp |
| 698 | stmfd sp!, {a1, a2, a3, a4} |
| 699 | stmfd sp!, {fp, ip, lr, pc} |
| 700 | sub fp, ip, #20 |
| 701 | |
| 702 | Which would create this stack frame (offsets relative to FP): |
| 703 | IP -> 20 (caller's stack) |
| 704 | 16 A4 |
| 705 | 12 A3 |
| 706 | 8 A2 |
| 707 | 4 A1 |
| 708 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 709 | -4 LR (return address in caller) |
| 710 | -8 IP (copy of caller's SP) |
| 711 | -12 FP (caller's FP) |
| 712 | SP -> -28 Local variables |
| 713 | |
| 714 | The frame size would thus be 48 bytes, and the frame offset would be |
| 715 | 28 bytes. |
| 716 | |
| 717 | There is another potential complication, which is that the optimizer |
| 718 | will try to separate the store of fp in the "stmfd" instruction from |
| 719 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so |
| 720 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... |
| 721 | |
| 722 | Also, note, the original version of the ARM toolchain claimed that there |
| 723 | should be an |
| 724 | |
| 725 | instruction at the end of the prologue. I have never seen GCC produce |
| 726 | this, and the ARM docs don't mention it. We still test for it below in |
| 727 | case it happens... |
| 728 | |
| 729 | */ |
| 730 | |
| 731 | static void |
| 732 | arm_scan_prologue (struct frame_info *fi) |
| 733 | { |
| 734 | int regno, sp_offset, fp_offset; |
| 735 | CORE_ADDR prologue_start, prologue_end, current_pc; |
| 736 | |
| 737 | /* Check if this function is already in the cache of frame information. */ |
| 738 | if (check_prologue_cache (fi)) |
| 739 | return; |
| 740 | |
| 741 | /* Assume there is no frame until proven otherwise. */ |
| 742 | fi->framereg = SP_REGNUM; |
| 743 | fi->framesize = 0; |
| 744 | fi->frameoffset = 0; |
| 745 | |
| 746 | /* Check for Thumb prologue. */ |
| 747 | if (arm_pc_is_thumb (fi->pc)) |
| 748 | { |
| 749 | thumb_scan_prologue (fi); |
| 750 | save_prologue_cache (fi); |
| 751 | return; |
| 752 | } |
| 753 | |
| 754 | /* Find the function prologue. If we can't find the function in |
| 755 | the symbol table, peek in the stack frame to find the PC. */ |
| 756 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
| 757 | { |
| 758 | /* One way to find the end of the prologue (which works well |
| 759 | for unoptimized code) is to do the following: |
| 760 | |
| 761 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 762 | |
| 763 | if (sal.line == 0) |
| 764 | prologue_end = fi->pc; |
| 765 | else if (sal.end < prologue_end) |
| 766 | prologue_end = sal.end; |
| 767 | |
| 768 | This mechanism is very accurate so long as the optimizer |
| 769 | doesn't move any instructions from the function body into the |
| 770 | prologue. If this happens, sal.end will be the last |
| 771 | instruction in the first hunk of prologue code just before |
| 772 | the first instruction that the scheduler has moved from |
| 773 | the body to the prologue. |
| 774 | |
| 775 | In order to make sure that we scan all of the prologue |
| 776 | instructions, we use a slightly less accurate mechanism which |
| 777 | may scan more than necessary. To help compensate for this |
| 778 | lack of accuracy, the prologue scanning loop below contains |
| 779 | several clauses which'll cause the loop to terminate early if |
| 780 | an implausible prologue instruction is encountered. |
| 781 | |
| 782 | The expression |
| 783 | |
| 784 | prologue_start + 64 |
| 785 | |
| 786 | is a suitable endpoint since it accounts for the largest |
| 787 | possible prologue plus up to five instructions inserted by |
| 788 | the scheduler. */ |
| 789 | |
| 790 | if (prologue_end > prologue_start + 64) |
| 791 | { |
| 792 | prologue_end = prologue_start + 64; /* See above. */ |
| 793 | } |
| 794 | } |
| 795 | else |
| 796 | { |
| 797 | /* Get address of the stmfd in the prologue of the callee; the saved |
| 798 | PC is the address of the stmfd + 8. */ |
| 799 | prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4)) |
| 800 | - 8; |
| 801 | prologue_end = prologue_start + 64; /* See above. */ |
| 802 | } |
| 803 | |
| 804 | /* Now search the prologue looking for instructions that set up the |
| 805 | frame pointer, adjust the stack pointer, and save registers. |
| 806 | |
| 807 | Be careful, however, and if it doesn't look like a prologue, |
| 808 | don't try to scan it. If, for instance, a frameless function |
| 809 | begins with stmfd sp!, then we will tell ourselves there is |
| 810 | a frame, which will confuse stack traceback, as well ad"finish" |
| 811 | and other operations that rely on a knowledge of the stack |
| 812 | traceback. |
| 813 | |
| 814 | In the APCS, the prologue should start with "mov ip, sp" so |
| 815 | if we don't see this as the first insn, we will stop. */ |
| 816 | |
| 817 | sp_offset = fp_offset = 0; |
| 818 | |
| 819 | if (read_memory_unsigned_integer (prologue_start, 4) |
| 820 | == 0xe1a0c00d) /* mov ip, sp */ |
| 821 | { |
| 822 | for (current_pc = prologue_start + 4; current_pc < prologue_end; |
| 823 | current_pc += 4) |
| 824 | { |
| 825 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
| 826 | |
| 827 | if ((insn & 0xffff0000) == 0xe92d0000) |
| 828 | /* stmfd sp!, {..., fp, ip, lr, pc} |
| 829 | or |
| 830 | stmfd sp!, {a1, a2, a3, a4} */ |
| 831 | { |
| 832 | int mask = insn & 0xffff; |
| 833 | |
| 834 | /* Calculate offsets of saved registers. */ |
| 835 | for (regno = PC_REGNUM; regno >= 0; regno--) |
| 836 | if (mask & (1 << regno)) |
| 837 | { |
| 838 | sp_offset -= 4; |
| 839 | fi->fsr.regs[regno] = sp_offset; |
| 840 | } |
| 841 | } |
| 842 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
| 843 | { |
| 844 | unsigned imm = insn & 0xff; /* immediate value */ |
| 845 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 846 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 847 | fp_offset = -imm; |
| 848 | fi->framereg = FP_REGNUM; |
| 849 | } |
| 850 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ |
| 851 | { |
| 852 | unsigned imm = insn & 0xff; /* immediate value */ |
| 853 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 854 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 855 | sp_offset -= imm; |
| 856 | } |
| 857 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ |
| 858 | { |
| 859 | sp_offset -= 12; |
| 860 | regno = F0_REGNUM + ((insn >> 12) & 0x07); |
| 861 | fi->fsr.regs[regno] = sp_offset; |
| 862 | } |
| 863 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ |
| 864 | { |
| 865 | int n_saved_fp_regs; |
| 866 | unsigned int fp_start_reg, fp_bound_reg; |
| 867 | |
| 868 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
| 869 | { |
| 870 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 871 | n_saved_fp_regs = 3; |
| 872 | else |
| 873 | n_saved_fp_regs = 1; |
| 874 | } |
| 875 | else |
| 876 | { |
| 877 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 878 | n_saved_fp_regs = 2; |
| 879 | else |
| 880 | n_saved_fp_regs = 4; |
| 881 | } |
| 882 | |
| 883 | fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7); |
| 884 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
| 885 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) |
| 886 | { |
| 887 | sp_offset -= 12; |
| 888 | fi->fsr.regs[fp_start_reg++] = sp_offset; |
| 889 | } |
| 890 | } |
| 891 | else if ((insn & 0xf0000000) != 0xe0000000) |
| 892 | break; /* Condition not true, exit early */ |
| 893 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
| 894 | break; /* Don't scan past a block load */ |
| 895 | else |
| 896 | /* The optimizer might shove anything into the prologue, |
| 897 | so we just skip what we don't recognize. */ |
| 898 | continue; |
| 899 | } |
| 900 | } |
| 901 | |
| 902 | /* The frame size is just the negative of the offset (from the original SP) |
| 903 | of the last thing thing we pushed on the stack. The frame offset is |
| 904 | [new FP] - [new SP]. */ |
| 905 | fi->framesize = -sp_offset; |
| 906 | fi->frameoffset = fp_offset - sp_offset; |
| 907 | |
| 908 | save_prologue_cache (fi); |
| 909 | } |
| 910 | |
| 911 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
| 912 | One thing we might want to do here is to check REGNUM against the |
| 913 | clobber mask, and somehow flag it as invalid if it isn't saved on |
| 914 | the stack somewhere. This would provide a graceful failure mode |
| 915 | when trying to get the value of caller-saves registers for an inner |
| 916 | frame. */ |
| 917 | |
| 918 | static CORE_ADDR |
| 919 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
| 920 | { |
| 921 | for (; fi; fi = fi->next) |
| 922 | |
| 923 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
| 924 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
| 925 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); |
| 926 | else |
| 927 | #endif |
| 928 | if (fi->fsr.regs[regnum] != 0) |
| 929 | return read_memory_integer (fi->fsr.regs[regnum], |
| 930 | REGISTER_RAW_SIZE (regnum)); |
| 931 | return read_register (regnum); |
| 932 | } |
| 933 | /* *INDENT-OFF* */ |
| 934 | /* Function: frame_chain |
| 935 | Given a GDB frame, determine the address of the calling function's frame. |
| 936 | This will be used to create a new GDB frame struct, and then |
| 937 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. |
| 938 | For ARM, we save the frame size when we initialize the frame_info. |
| 939 | |
| 940 | The original definition of this function was a macro in tm-arm.h: |
| 941 | { In the case of the ARM, the frame's nominal address is the FP value, |
| 942 | and 12 bytes before comes the saved previous FP value as a 4-byte word. } |
| 943 | |
| 944 | #define FRAME_CHAIN(thisframe) \ |
| 945 | ((thisframe)->pc >= LOWEST_PC ? \ |
| 946 | read_memory_integer ((thisframe)->frame - 12, 4) :\ |
| 947 | 0) |
| 948 | */ |
| 949 | /* *INDENT-ON* */ |
| 950 | |
| 951 | CORE_ADDR |
| 952 | arm_frame_chain (struct frame_info *fi) |
| 953 | { |
| 954 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
| 955 | CORE_ADDR fn_start, callers_pc, fp; |
| 956 | |
| 957 | /* is this a dummy frame? */ |
| 958 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
| 959 | return fi->frame; /* dummy frame same as caller's frame */ |
| 960 | |
| 961 | /* is caller-of-this a dummy frame? */ |
| 962 | callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */ |
| 963 | fp = arm_find_callers_reg (fi, FP_REGNUM); |
| 964 | if (PC_IN_CALL_DUMMY (callers_pc, fp, fp)) |
| 965 | return fp; /* dummy frame's frame may bear no relation to ours */ |
| 966 | |
| 967 | if (find_pc_partial_function (fi->pc, 0, &fn_start, 0)) |
| 968 | if (fn_start == entry_point_address ()) |
| 969 | return 0; /* in _start fn, don't chain further */ |
| 970 | #endif |
| 971 | CORE_ADDR caller_pc, fn_start; |
| 972 | struct frame_info caller_fi; |
| 973 | int framereg = fi->framereg; |
| 974 | |
| 975 | if (fi->pc < LOWEST_PC) |
| 976 | return 0; |
| 977 | |
| 978 | /* If the caller is the startup code, we're at the end of the chain. */ |
| 979 | caller_pc = FRAME_SAVED_PC (fi); |
| 980 | if (find_pc_partial_function (caller_pc, 0, &fn_start, 0)) |
| 981 | if (fn_start == entry_point_address ()) |
| 982 | return 0; |
| 983 | |
| 984 | /* If the caller is Thumb and the caller is ARM, or vice versa, |
| 985 | the frame register of the caller is different from ours. |
| 986 | So we must scan the prologue of the caller to determine its |
| 987 | frame register number. */ |
| 988 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) |
| 989 | { |
| 990 | memset (&caller_fi, 0, sizeof (caller_fi)); |
| 991 | caller_fi.pc = caller_pc; |
| 992 | arm_scan_prologue (&caller_fi); |
| 993 | framereg = caller_fi.framereg; |
| 994 | } |
| 995 | |
| 996 | /* If the caller used a frame register, return its value. |
| 997 | Otherwise, return the caller's stack pointer. */ |
| 998 | if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM) |
| 999 | return arm_find_callers_reg (fi, framereg); |
| 1000 | else |
| 1001 | return fi->frame + fi->framesize; |
| 1002 | } |
| 1003 | |
| 1004 | /* This function actually figures out the frame address for a given pc |
| 1005 | and sp. This is tricky because we sometimes don't use an explicit |
| 1006 | frame pointer, and the previous stack pointer isn't necessarily |
| 1007 | recorded on the stack. The only reliable way to get this info is |
| 1008 | to examine the prologue. FROMLEAF is a little confusing, it means |
| 1009 | this is the next frame up the chain AFTER a frameless function. If |
| 1010 | this is true, then the frame value for this frame is still in the |
| 1011 | fp register. */ |
| 1012 | |
| 1013 | void |
| 1014 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
| 1015 | { |
| 1016 | int reg; |
| 1017 | |
| 1018 | if (fi->next) |
| 1019 | fi->pc = FRAME_SAVED_PC (fi->next); |
| 1020 | |
| 1021 | memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs); |
| 1022 | |
| 1023 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
| 1024 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
| 1025 | { |
| 1026 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong |
| 1027 | by assuming it's always FP. */ |
| 1028 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); |
| 1029 | fi->framesize = 0; |
| 1030 | fi->frameoffset = 0; |
| 1031 | return; |
| 1032 | } |
| 1033 | else |
| 1034 | #endif |
| 1035 | |
| 1036 | /* Determine whether or not we're in a sigtramp frame. |
| 1037 | Unfortunately, it isn't sufficient to test |
| 1038 | fi->signal_handler_caller because this value is sometimes set |
| 1039 | after invoking INIT_EXTRA_FRAME_INFO. So we test *both* |
| 1040 | fi->signal_handler_caller and IN_SIGTRAMP to determine if we need |
| 1041 | to use the sigcontext addresses for the saved registers. |
| 1042 | |
| 1043 | Note: If an ARM IN_SIGTRAMP method ever needs to compare against |
| 1044 | the name of the function, the code below will have to be changed |
| 1045 | to first fetch the name of the function and then pass this name |
| 1046 | to IN_SIGTRAMP. */ |
| 1047 | |
| 1048 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
| 1049 | && (fi->signal_handler_caller || IN_SIGTRAMP (fi->pc, 0))) |
| 1050 | { |
| 1051 | CORE_ADDR sp; |
| 1052 | |
| 1053 | if (!fi->next) |
| 1054 | sp = read_sp(); |
| 1055 | else |
| 1056 | sp = fi->next->frame - fi->next->frameoffset + fi->next->framesize; |
| 1057 | |
| 1058 | for (reg = 0; reg < NUM_REGS; reg++) |
| 1059 | fi->fsr.regs[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, fi->pc, reg); |
| 1060 | |
| 1061 | /* FIXME: What about thumb mode? */ |
| 1062 | fi->framereg = SP_REGNUM; |
| 1063 | fi->frame = read_memory_integer (fi->fsr.regs[fi->framereg], 4); |
| 1064 | fi->framesize = 0; |
| 1065 | fi->frameoffset = 0; |
| 1066 | |
| 1067 | } |
| 1068 | else |
| 1069 | { |
| 1070 | arm_scan_prologue (fi); |
| 1071 | |
| 1072 | if (!fi->next) |
| 1073 | /* this is the innermost frame? */ |
| 1074 | fi->frame = read_register (fi->framereg); |
| 1075 | else if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM) |
| 1076 | { |
| 1077 | /* not the innermost frame */ |
| 1078 | /* If we have an FP, the callee saved it. */ |
| 1079 | if (fi->next->fsr.regs[fi->framereg] != 0) |
| 1080 | fi->frame = |
| 1081 | read_memory_integer (fi->next->fsr.regs[fi->framereg], 4); |
| 1082 | else if (fromleaf) |
| 1083 | /* If we were called by a frameless fn. then our frame is |
| 1084 | still in the frame pointer register on the board... */ |
| 1085 | fi->frame = read_fp (); |
| 1086 | } |
| 1087 | |
| 1088 | /* Calculate actual addresses of saved registers using offsets |
| 1089 | determined by arm_scan_prologue. */ |
| 1090 | for (reg = 0; reg < NUM_REGS; reg++) |
| 1091 | if (fi->fsr.regs[reg] != 0) |
| 1092 | fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset; |
| 1093 | } |
| 1094 | } |
| 1095 | |
| 1096 | |
| 1097 | /* Find the caller of this frame. We do this by seeing if LR_REGNUM |
| 1098 | is saved in the stack anywhere, otherwise we get it from the |
| 1099 | registers. |
| 1100 | |
| 1101 | The old definition of this function was a macro: |
| 1102 | #define FRAME_SAVED_PC(FRAME) \ |
| 1103 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
| 1104 | |
| 1105 | CORE_ADDR |
| 1106 | arm_frame_saved_pc (struct frame_info *fi) |
| 1107 | { |
| 1108 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
| 1109 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
| 1110 | return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); |
| 1111 | else |
| 1112 | #endif |
| 1113 | { |
| 1114 | CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM); |
| 1115 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
| 1116 | } |
| 1117 | } |
| 1118 | |
| 1119 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
| 1120 | Examine the Program Status Register to decide which state we're in. */ |
| 1121 | |
| 1122 | CORE_ADDR |
| 1123 | arm_target_read_fp (void) |
| 1124 | { |
| 1125 | if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ |
| 1126 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ |
| 1127 | else |
| 1128 | return read_register (FP_REGNUM); /* R11 if ARM */ |
| 1129 | } |
| 1130 | |
| 1131 | /* Calculate the frame offsets of the saved registers (ARM version). */ |
| 1132 | |
| 1133 | void |
| 1134 | arm_frame_find_saved_regs (struct frame_info *fi, |
| 1135 | struct frame_saved_regs *regaddr) |
| 1136 | { |
| 1137 | memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs)); |
| 1138 | } |
| 1139 | |
| 1140 | void |
| 1141 | arm_push_dummy_frame (void) |
| 1142 | { |
| 1143 | CORE_ADDR old_sp = read_register (SP_REGNUM); |
| 1144 | CORE_ADDR sp = old_sp; |
| 1145 | CORE_ADDR fp, prologue_start; |
| 1146 | int regnum; |
| 1147 | |
| 1148 | /* Push the two dummy prologue instructions in reverse order, |
| 1149 | so that they'll be in the correct low-to-high order in memory. */ |
| 1150 | /* sub fp, ip, #4 */ |
| 1151 | sp = push_word (sp, 0xe24cb004); |
| 1152 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ |
| 1153 | prologue_start = sp = push_word (sp, 0xe92ddfff); |
| 1154 | |
| 1155 | /* Push a pointer to the dummy prologue + 12, because when stm |
| 1156 | instruction stores the PC, it stores the address of the stm |
| 1157 | instruction itself plus 12. */ |
| 1158 | fp = sp = push_word (sp, prologue_start + 12); |
| 1159 | sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */ |
| 1160 | sp = push_word (sp, old_sp); |
| 1161 | sp = push_word (sp, read_register (FP_REGNUM)); |
| 1162 | |
| 1163 | for (regnum = 10; regnum >= 0; regnum--) |
| 1164 | sp = push_word (sp, read_register (regnum)); |
| 1165 | |
| 1166 | write_register (FP_REGNUM, fp); |
| 1167 | write_register (THUMB_FP_REGNUM, fp); |
| 1168 | write_register (SP_REGNUM, sp); |
| 1169 | } |
| 1170 | |
| 1171 | /* Fix up the call dummy, based on whether the processor is currently |
| 1172 | in Thumb or ARM mode, and whether the target function is Thumb or |
| 1173 | ARM. There are three different situations requiring three |
| 1174 | different dummies: |
| 1175 | |
| 1176 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already |
| 1177 | been copied into the dummy parameter to this function. |
| 1178 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
| 1179 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
| 1180 | * Thumb calling anything: uses the Thumb dummy defined below, which |
| 1181 | works for calling both ARM and Thumb functions. |
| 1182 | |
| 1183 | All three call dummies expect to receive the target function |
| 1184 | address in R4, with the low bit set if it's a Thumb function. */ |
| 1185 | |
| 1186 | void |
| 1187 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
| 1188 | value_ptr *args, struct type *type, int gcc_p) |
| 1189 | { |
| 1190 | static short thumb_dummy[4] = |
| 1191 | { |
| 1192 | 0xf000, 0xf801, /* bl label */ |
| 1193 | 0xdf18, /* swi 24 */ |
| 1194 | 0x4720, /* label: bx r4 */ |
| 1195 | }; |
| 1196 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ |
| 1197 | |
| 1198 | /* Set flag indicating whether the current PC is in a Thumb function. */ |
| 1199 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
| 1200 | |
| 1201 | /* If the target function is Thumb, set the low bit of the function |
| 1202 | address. And if the CPU is currently in ARM mode, patch the |
| 1203 | second instruction of call dummy to use a BX instruction to |
| 1204 | switch to Thumb mode. */ |
| 1205 | target_is_thumb = arm_pc_is_thumb (fun); |
| 1206 | if (target_is_thumb) |
| 1207 | { |
| 1208 | fun |= 1; |
| 1209 | if (!caller_is_thumb) |
| 1210 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); |
| 1211 | } |
| 1212 | |
| 1213 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy |
| 1214 | instead of the ARM one that's already been copied. This will |
| 1215 | work for both Thumb and ARM target functions. */ |
| 1216 | if (caller_is_thumb) |
| 1217 | { |
| 1218 | int i; |
| 1219 | char *p = dummy; |
| 1220 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); |
| 1221 | |
| 1222 | for (i = 0; i < len; i++) |
| 1223 | { |
| 1224 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); |
| 1225 | p += sizeof (thumb_dummy[0]); |
| 1226 | } |
| 1227 | } |
| 1228 | |
| 1229 | /* Put the target address in r4; the call dummy will copy this to |
| 1230 | the PC. */ |
| 1231 | write_register (4, fun); |
| 1232 | } |
| 1233 | |
| 1234 | /* Return the offset in the call dummy of the instruction that needs |
| 1235 | to have a breakpoint placed on it. This is the offset of the 'swi |
| 1236 | 24' instruction, which is no longer actually used, but simply acts |
| 1237 | as a place-holder now. |
| 1238 | |
| 1239 | This implements the CALL_DUMMY_BREAK_OFFSET macro. */ |
| 1240 | |
| 1241 | int |
| 1242 | arm_call_dummy_breakpoint_offset (void) |
| 1243 | { |
| 1244 | if (caller_is_thumb) |
| 1245 | return 4; |
| 1246 | else |
| 1247 | return 8; |
| 1248 | } |
| 1249 | |
| 1250 | /* Note: ScottB |
| 1251 | |
| 1252 | This function does not support passing parameters using the FPA |
| 1253 | variant of the APCS. It passes any floating point arguments in the |
| 1254 | general registers and/or on the stack. */ |
| 1255 | |
| 1256 | CORE_ADDR |
| 1257 | arm_push_arguments (int nargs, value_ptr * args, CORE_ADDR sp, |
| 1258 | int struct_return, CORE_ADDR struct_addr) |
| 1259 | { |
| 1260 | char *fp; |
| 1261 | int argnum, argreg, nstack_size; |
| 1262 | |
| 1263 | /* Walk through the list of args and determine how large a temporary |
| 1264 | stack is required. Need to take care here as structs may be |
| 1265 | passed on the stack, and we have to to push them. */ |
| 1266 | nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */ |
| 1267 | if (struct_return) /* The struct address goes in A1. */ |
| 1268 | nstack_size += REGISTER_SIZE; |
| 1269 | |
| 1270 | /* Walk through the arguments and add their size to nstack_size. */ |
| 1271 | for (argnum = 0; argnum < nargs; argnum++) |
| 1272 | { |
| 1273 | int len; |
| 1274 | struct type *arg_type; |
| 1275 | |
| 1276 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); |
| 1277 | len = TYPE_LENGTH (arg_type); |
| 1278 | |
| 1279 | /* ANSI C code passes float arguments as integers, K&R code |
| 1280 | passes float arguments as doubles. Correct for this here. */ |
| 1281 | if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len) |
| 1282 | nstack_size += FP_REGISTER_VIRTUAL_SIZE; |
| 1283 | else |
| 1284 | nstack_size += len; |
| 1285 | } |
| 1286 | |
| 1287 | /* Allocate room on the stack, and initialize our stack frame |
| 1288 | pointer. */ |
| 1289 | fp = NULL; |
| 1290 | if (nstack_size > 0) |
| 1291 | { |
| 1292 | sp -= nstack_size; |
| 1293 | fp = (char *) sp; |
| 1294 | } |
| 1295 | |
| 1296 | /* Initialize the integer argument register pointer. */ |
| 1297 | argreg = A1_REGNUM; |
| 1298 | |
| 1299 | /* The struct_return pointer occupies the first parameter passing |
| 1300 | register. */ |
| 1301 | if (struct_return) |
| 1302 | write_register (argreg++, struct_addr); |
| 1303 | |
| 1304 | /* Process arguments from left to right. Store as many as allowed |
| 1305 | in the parameter passing registers (A1-A4), and save the rest on |
| 1306 | the temporary stack. */ |
| 1307 | for (argnum = 0; argnum < nargs; argnum++) |
| 1308 | { |
| 1309 | int len; |
| 1310 | char *val; |
| 1311 | double dbl_arg; |
| 1312 | CORE_ADDR regval; |
| 1313 | enum type_code typecode; |
| 1314 | struct type *arg_type, *target_type; |
| 1315 | |
| 1316 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); |
| 1317 | target_type = TYPE_TARGET_TYPE (arg_type); |
| 1318 | len = TYPE_LENGTH (arg_type); |
| 1319 | typecode = TYPE_CODE (arg_type); |
| 1320 | val = (char *) VALUE_CONTENTS (args[argnum]); |
| 1321 | |
| 1322 | /* ANSI C code passes float arguments as integers, K&R code |
| 1323 | passes float arguments as doubles. The .stabs record for |
| 1324 | for ANSI prototype floating point arguments records the |
| 1325 | type as FP_INTEGER, while a K&R style (no prototype) |
| 1326 | .stabs records the type as FP_FLOAT. In this latter case |
| 1327 | the compiler converts the float arguments to double before |
| 1328 | calling the function. */ |
| 1329 | if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len) |
| 1330 | { |
| 1331 | float f; |
| 1332 | double d; |
| 1333 | char * bufo = (char *) &d; |
| 1334 | char * bufd = (char *) &dbl_arg; |
| 1335 | |
| 1336 | len = sizeof (double); |
| 1337 | f = *(float *) val; |
| 1338 | SWAP_TARGET_AND_HOST (&f, sizeof (float)); /* adjust endianess */ |
| 1339 | d = f; |
| 1340 | /* We must revert the longwords so they get loaded into the |
| 1341 | the right registers. */ |
| 1342 | memcpy (bufd, bufo + len / 2, len / 2); |
| 1343 | SWAP_TARGET_AND_HOST (bufd, len / 2); /* adjust endianess */ |
| 1344 | memcpy (bufd + len / 2, bufo, len / 2); |
| 1345 | SWAP_TARGET_AND_HOST (bufd + len / 2, len / 2); /* adjust endianess */ |
| 1346 | val = (char *) &dbl_arg; |
| 1347 | } |
| 1348 | #if 1 |
| 1349 | /* I don't know why this code was disable. The only logical use |
| 1350 | for a function pointer is to call that function, so setting |
| 1351 | the mode bit is perfectly fine. FN */ |
| 1352 | /* If the argument is a pointer to a function, and it is a Thumb |
| 1353 | function, set the low bit of the pointer. */ |
| 1354 | if (TYPE_CODE_PTR == typecode |
| 1355 | && NULL != target_type |
| 1356 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) |
| 1357 | { |
| 1358 | CORE_ADDR regval = extract_address (val, len); |
| 1359 | if (arm_pc_is_thumb (regval)) |
| 1360 | store_address (val, len, MAKE_THUMB_ADDR (regval)); |
| 1361 | } |
| 1362 | #endif |
| 1363 | /* Copy the argument to general registers or the stack in |
| 1364 | register-sized pieces. Large arguments are split between |
| 1365 | registers and stack. */ |
| 1366 | while (len > 0) |
| 1367 | { |
| 1368 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
| 1369 | |
| 1370 | if (argreg <= ARM_LAST_ARG_REGNUM) |
| 1371 | { |
| 1372 | /* It's an argument being passed in a general register. */ |
| 1373 | regval = extract_address (val, partial_len); |
| 1374 | write_register (argreg++, regval); |
| 1375 | } |
| 1376 | else |
| 1377 | { |
| 1378 | /* Push the arguments onto the stack. */ |
| 1379 | write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE); |
| 1380 | fp += REGISTER_SIZE; |
| 1381 | } |
| 1382 | |
| 1383 | len -= partial_len; |
| 1384 | val += partial_len; |
| 1385 | } |
| 1386 | } |
| 1387 | |
| 1388 | /* Return adjusted stack pointer. */ |
| 1389 | return sp; |
| 1390 | } |
| 1391 | |
| 1392 | void |
| 1393 | arm_pop_frame (void) |
| 1394 | { |
| 1395 | int regnum; |
| 1396 | struct frame_info *frame = get_current_frame (); |
| 1397 | |
| 1398 | if (!PC_IN_CALL_DUMMY(frame->pc, frame->frame, read_fp())) |
| 1399 | { |
| 1400 | CORE_ADDR old_SP; |
| 1401 | |
| 1402 | old_SP = read_register (frame->framereg); |
| 1403 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
| 1404 | if (frame->fsr.regs[regnum] != 0) |
| 1405 | write_register (regnum, |
| 1406 | read_memory_integer (frame->fsr.regs[regnum], 4)); |
| 1407 | |
| 1408 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
| 1409 | write_register (SP_REGNUM, old_SP); |
| 1410 | } |
| 1411 | else |
| 1412 | { |
| 1413 | CORE_ADDR sp; |
| 1414 | |
| 1415 | sp = read_register (FP_REGNUM); |
| 1416 | sp -= sizeof(CORE_ADDR); /* we don't care about this first word */ |
| 1417 | |
| 1418 | write_register (PC_REGNUM, read_memory_integer (sp, 4)); |
| 1419 | sp -= sizeof(CORE_ADDR); |
| 1420 | write_register (SP_REGNUM, read_memory_integer (sp, 4)); |
| 1421 | sp -= sizeof(CORE_ADDR); |
| 1422 | write_register (FP_REGNUM, read_memory_integer (sp, 4)); |
| 1423 | sp -= sizeof(CORE_ADDR); |
| 1424 | |
| 1425 | for (regnum = 10; regnum >= 0; regnum--) |
| 1426 | { |
| 1427 | write_register (regnum, read_memory_integer (sp, 4)); |
| 1428 | sp -= sizeof(CORE_ADDR); |
| 1429 | } |
| 1430 | } |
| 1431 | |
| 1432 | flush_cached_frames (); |
| 1433 | } |
| 1434 | |
| 1435 | static void |
| 1436 | print_fpu_flags (int flags) |
| 1437 | { |
| 1438 | if (flags & (1 << 0)) |
| 1439 | fputs ("IVO ", stdout); |
| 1440 | if (flags & (1 << 1)) |
| 1441 | fputs ("DVZ ", stdout); |
| 1442 | if (flags & (1 << 2)) |
| 1443 | fputs ("OFL ", stdout); |
| 1444 | if (flags & (1 << 3)) |
| 1445 | fputs ("UFL ", stdout); |
| 1446 | if (flags & (1 << 4)) |
| 1447 | fputs ("INX ", stdout); |
| 1448 | putchar ('\n'); |
| 1449 | } |
| 1450 | |
| 1451 | void |
| 1452 | arm_float_info (void) |
| 1453 | { |
| 1454 | register unsigned long status = read_register (FPS_REGNUM); |
| 1455 | int type; |
| 1456 | |
| 1457 | type = (status >> 24) & 127; |
| 1458 | printf ("%s FPU type %d\n", |
| 1459 | (status & (1 << 31)) ? "Hardware" : "Software", |
| 1460 | type); |
| 1461 | fputs ("mask: ", stdout); |
| 1462 | print_fpu_flags (status >> 16); |
| 1463 | fputs ("flags: ", stdout); |
| 1464 | print_fpu_flags (status); |
| 1465 | } |
| 1466 | |
| 1467 | #if 0 |
| 1468 | /* FIXME: The generated assembler works but sucks. Instead of using |
| 1469 | r0, r1 it pushes them on the stack, then loads them into r3, r4 and |
| 1470 | uses those registers. I must be missing something. ScottB */ |
| 1471 | |
| 1472 | void |
| 1473 | convert_from_extended (void *ptr, void *dbl) |
| 1474 | { |
| 1475 | __asm__ (" |
| 1476 | ldfe f0,[%0] |
| 1477 | stfd f0,[%1] " |
| 1478 | : /* no output */ |
| 1479 | : "r" (ptr), "r" (dbl)); |
| 1480 | } |
| 1481 | |
| 1482 | void |
| 1483 | convert_to_extended (void *dbl, void *ptr) |
| 1484 | { |
| 1485 | __asm__ (" |
| 1486 | ldfd f0,[%0] |
| 1487 | stfe f0,[%1] " |
| 1488 | : /* no output */ |
| 1489 | : "r" (dbl), "r" (ptr)); |
| 1490 | } |
| 1491 | #else |
| 1492 | static void |
| 1493 | convert_from_extended (void *ptr, void *dbl) |
| 1494 | { |
| 1495 | *(double *) dbl = *(double *) ptr; |
| 1496 | } |
| 1497 | |
| 1498 | void |
| 1499 | convert_to_extended (void *dbl, void *ptr) |
| 1500 | { |
| 1501 | *(double *) ptr = *(double *) dbl; |
| 1502 | } |
| 1503 | #endif |
| 1504 | |
| 1505 | /* Nonzero if register N requires conversion from raw format to |
| 1506 | virtual format. */ |
| 1507 | |
| 1508 | int |
| 1509 | arm_register_convertible (unsigned int regnum) |
| 1510 | { |
| 1511 | return ((regnum - F0_REGNUM) < 8); |
| 1512 | } |
| 1513 | |
| 1514 | /* Convert data from raw format for register REGNUM in buffer FROM to |
| 1515 | virtual format with type TYPE in buffer TO. */ |
| 1516 | |
| 1517 | void |
| 1518 | arm_register_convert_to_virtual (unsigned int regnum, struct type *type, |
| 1519 | void *from, void *to) |
| 1520 | { |
| 1521 | double val; |
| 1522 | |
| 1523 | convert_from_extended (from, &val); |
| 1524 | store_floating (to, TYPE_LENGTH (type), val); |
| 1525 | } |
| 1526 | |
| 1527 | /* Convert data from virtual format with type TYPE in buffer FROM to |
| 1528 | raw format for register REGNUM in buffer TO. */ |
| 1529 | |
| 1530 | void |
| 1531 | arm_register_convert_to_raw (unsigned int regnum, struct type *type, |
| 1532 | void *from, void *to) |
| 1533 | { |
| 1534 | double val = extract_floating (from, TYPE_LENGTH (type)); |
| 1535 | |
| 1536 | convert_to_extended (&val, to); |
| 1537 | } |
| 1538 | |
| 1539 | static int |
| 1540 | condition_true (unsigned long cond, unsigned long status_reg) |
| 1541 | { |
| 1542 | if (cond == INST_AL || cond == INST_NV) |
| 1543 | return 1; |
| 1544 | |
| 1545 | switch (cond) |
| 1546 | { |
| 1547 | case INST_EQ: |
| 1548 | return ((status_reg & FLAG_Z) != 0); |
| 1549 | case INST_NE: |
| 1550 | return ((status_reg & FLAG_Z) == 0); |
| 1551 | case INST_CS: |
| 1552 | return ((status_reg & FLAG_C) != 0); |
| 1553 | case INST_CC: |
| 1554 | return ((status_reg & FLAG_C) == 0); |
| 1555 | case INST_MI: |
| 1556 | return ((status_reg & FLAG_N) != 0); |
| 1557 | case INST_PL: |
| 1558 | return ((status_reg & FLAG_N) == 0); |
| 1559 | case INST_VS: |
| 1560 | return ((status_reg & FLAG_V) != 0); |
| 1561 | case INST_VC: |
| 1562 | return ((status_reg & FLAG_V) == 0); |
| 1563 | case INST_HI: |
| 1564 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); |
| 1565 | case INST_LS: |
| 1566 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); |
| 1567 | case INST_GE: |
| 1568 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); |
| 1569 | case INST_LT: |
| 1570 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); |
| 1571 | case INST_GT: |
| 1572 | return (((status_reg & FLAG_Z) == 0) && |
| 1573 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
| 1574 | case INST_LE: |
| 1575 | return (((status_reg & FLAG_Z) != 0) || |
| 1576 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
| 1577 | } |
| 1578 | return 1; |
| 1579 | } |
| 1580 | |
| 1581 | #define submask(x) ((1L << ((x) + 1)) - 1) |
| 1582 | #define bit(obj,st) (((obj) >> (st)) & 1) |
| 1583 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) |
| 1584 | #define sbits(obj,st,fn) \ |
| 1585 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) |
| 1586 | #define BranchDest(addr,instr) \ |
| 1587 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) |
| 1588 | #define ARM_PC_32 1 |
| 1589 | |
| 1590 | static unsigned long |
| 1591 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
| 1592 | unsigned long status_reg) |
| 1593 | { |
| 1594 | unsigned long res, shift; |
| 1595 | int rm = bits (inst, 0, 3); |
| 1596 | unsigned long shifttype = bits (inst, 5, 6); |
| 1597 | |
| 1598 | if (bit (inst, 4)) |
| 1599 | { |
| 1600 | int rs = bits (inst, 8, 11); |
| 1601 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; |
| 1602 | } |
| 1603 | else |
| 1604 | shift = bits (inst, 7, 11); |
| 1605 | |
| 1606 | res = (rm == 15 |
| 1607 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
| 1608 | + (bit (inst, 4) ? 12 : 8)) |
| 1609 | : read_register (rm)); |
| 1610 | |
| 1611 | switch (shifttype) |
| 1612 | { |
| 1613 | case 0: /* LSL */ |
| 1614 | res = shift >= 32 ? 0 : res << shift; |
| 1615 | break; |
| 1616 | |
| 1617 | case 1: /* LSR */ |
| 1618 | res = shift >= 32 ? 0 : res >> shift; |
| 1619 | break; |
| 1620 | |
| 1621 | case 2: /* ASR */ |
| 1622 | if (shift >= 32) |
| 1623 | shift = 31; |
| 1624 | res = ((res & 0x80000000L) |
| 1625 | ? ~((~res) >> shift) : res >> shift); |
| 1626 | break; |
| 1627 | |
| 1628 | case 3: /* ROR/RRX */ |
| 1629 | shift &= 31; |
| 1630 | if (shift == 0) |
| 1631 | res = (res >> 1) | (carry ? 0x80000000L : 0); |
| 1632 | else |
| 1633 | res = (res >> shift) | (res << (32 - shift)); |
| 1634 | break; |
| 1635 | } |
| 1636 | |
| 1637 | return res & 0xffffffff; |
| 1638 | } |
| 1639 | |
| 1640 | /* Return number of 1-bits in VAL. */ |
| 1641 | |
| 1642 | static int |
| 1643 | bitcount (unsigned long val) |
| 1644 | { |
| 1645 | int nbits; |
| 1646 | for (nbits = 0; val != 0; nbits++) |
| 1647 | val &= val - 1; /* delete rightmost 1-bit in val */ |
| 1648 | return nbits; |
| 1649 | } |
| 1650 | |
| 1651 | static CORE_ADDR |
| 1652 | thumb_get_next_pc (CORE_ADDR pc) |
| 1653 | { |
| 1654 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
| 1655 | unsigned short inst1 = read_memory_integer (pc, 2); |
| 1656 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
| 1657 | unsigned long offset; |
| 1658 | |
| 1659 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
| 1660 | { |
| 1661 | CORE_ADDR sp; |
| 1662 | |
| 1663 | /* Fetch the saved PC from the stack. It's stored above |
| 1664 | all of the other registers. */ |
| 1665 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; |
| 1666 | sp = read_register (SP_REGNUM); |
| 1667 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
| 1668 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1669 | if (nextpc == pc) |
| 1670 | error ("Infinite loop detected"); |
| 1671 | } |
| 1672 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ |
| 1673 | { |
| 1674 | unsigned long status = read_register (PS_REGNUM); |
| 1675 | unsigned long cond = bits (inst1, 8, 11); |
| 1676 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
| 1677 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
| 1678 | } |
| 1679 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ |
| 1680 | { |
| 1681 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); |
| 1682 | } |
| 1683 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ |
| 1684 | { |
| 1685 | unsigned short inst2 = read_memory_integer (pc + 2, 2); |
| 1686 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
| 1687 | nextpc = pc_val + offset; |
| 1688 | } |
| 1689 | |
| 1690 | return nextpc; |
| 1691 | } |
| 1692 | |
| 1693 | CORE_ADDR |
| 1694 | arm_get_next_pc (CORE_ADDR pc) |
| 1695 | { |
| 1696 | unsigned long pc_val; |
| 1697 | unsigned long this_instr; |
| 1698 | unsigned long status; |
| 1699 | CORE_ADDR nextpc; |
| 1700 | |
| 1701 | if (arm_pc_is_thumb (pc)) |
| 1702 | return thumb_get_next_pc (pc); |
| 1703 | |
| 1704 | pc_val = (unsigned long) pc; |
| 1705 | this_instr = read_memory_integer (pc, 4); |
| 1706 | status = read_register (PS_REGNUM); |
| 1707 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
| 1708 | |
| 1709 | if (condition_true (bits (this_instr, 28, 31), status)) |
| 1710 | { |
| 1711 | switch (bits (this_instr, 24, 27)) |
| 1712 | { |
| 1713 | case 0x0: |
| 1714 | case 0x1: /* data processing */ |
| 1715 | case 0x2: |
| 1716 | case 0x3: |
| 1717 | { |
| 1718 | unsigned long operand1, operand2, result = 0; |
| 1719 | unsigned long rn; |
| 1720 | int c; |
| 1721 | |
| 1722 | if (bits (this_instr, 12, 15) != 15) |
| 1723 | break; |
| 1724 | |
| 1725 | if (bits (this_instr, 22, 25) == 0 |
| 1726 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
| 1727 | error ("Illegal update to pc in instruction"); |
| 1728 | |
| 1729 | /* Multiply into PC */ |
| 1730 | c = (status & FLAG_C) ? 1 : 0; |
| 1731 | rn = bits (this_instr, 16, 19); |
| 1732 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1733 | |
| 1734 | if (bit (this_instr, 25)) |
| 1735 | { |
| 1736 | unsigned long immval = bits (this_instr, 0, 7); |
| 1737 | unsigned long rotate = 2 * bits (this_instr, 8, 11); |
| 1738 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
| 1739 | & 0xffffffff; |
| 1740 | } |
| 1741 | else /* operand 2 is a shifted register */ |
| 1742 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
| 1743 | |
| 1744 | switch (bits (this_instr, 21, 24)) |
| 1745 | { |
| 1746 | case 0x0: /*and */ |
| 1747 | result = operand1 & operand2; |
| 1748 | break; |
| 1749 | |
| 1750 | case 0x1: /*eor */ |
| 1751 | result = operand1 ^ operand2; |
| 1752 | break; |
| 1753 | |
| 1754 | case 0x2: /*sub */ |
| 1755 | result = operand1 - operand2; |
| 1756 | break; |
| 1757 | |
| 1758 | case 0x3: /*rsb */ |
| 1759 | result = operand2 - operand1; |
| 1760 | break; |
| 1761 | |
| 1762 | case 0x4: /*add */ |
| 1763 | result = operand1 + operand2; |
| 1764 | break; |
| 1765 | |
| 1766 | case 0x5: /*adc */ |
| 1767 | result = operand1 + operand2 + c; |
| 1768 | break; |
| 1769 | |
| 1770 | case 0x6: /*sbc */ |
| 1771 | result = operand1 - operand2 + c; |
| 1772 | break; |
| 1773 | |
| 1774 | case 0x7: /*rsc */ |
| 1775 | result = operand2 - operand1 + c; |
| 1776 | break; |
| 1777 | |
| 1778 | case 0x8: |
| 1779 | case 0x9: |
| 1780 | case 0xa: |
| 1781 | case 0xb: /* tst, teq, cmp, cmn */ |
| 1782 | result = (unsigned long) nextpc; |
| 1783 | break; |
| 1784 | |
| 1785 | case 0xc: /*orr */ |
| 1786 | result = operand1 | operand2; |
| 1787 | break; |
| 1788 | |
| 1789 | case 0xd: /*mov */ |
| 1790 | /* Always step into a function. */ |
| 1791 | result = operand2; |
| 1792 | break; |
| 1793 | |
| 1794 | case 0xe: /*bic */ |
| 1795 | result = operand1 & ~operand2; |
| 1796 | break; |
| 1797 | |
| 1798 | case 0xf: /*mvn */ |
| 1799 | result = ~operand2; |
| 1800 | break; |
| 1801 | } |
| 1802 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); |
| 1803 | |
| 1804 | if (nextpc == pc) |
| 1805 | error ("Infinite loop detected"); |
| 1806 | break; |
| 1807 | } |
| 1808 | |
| 1809 | case 0x4: |
| 1810 | case 0x5: /* data transfer */ |
| 1811 | case 0x6: |
| 1812 | case 0x7: |
| 1813 | if (bit (this_instr, 20)) |
| 1814 | { |
| 1815 | /* load */ |
| 1816 | if (bits (this_instr, 12, 15) == 15) |
| 1817 | { |
| 1818 | /* rd == pc */ |
| 1819 | unsigned long rn; |
| 1820 | unsigned long base; |
| 1821 | |
| 1822 | if (bit (this_instr, 22)) |
| 1823 | error ("Illegal update to pc in instruction"); |
| 1824 | |
| 1825 | /* byte write to PC */ |
| 1826 | rn = bits (this_instr, 16, 19); |
| 1827 | base = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1828 | if (bit (this_instr, 24)) |
| 1829 | { |
| 1830 | /* pre-indexed */ |
| 1831 | int c = (status & FLAG_C) ? 1 : 0; |
| 1832 | unsigned long offset = |
| 1833 | (bit (this_instr, 25) |
| 1834 | ? shifted_reg_val (this_instr, c, pc_val, status) |
| 1835 | : bits (this_instr, 0, 11)); |
| 1836 | |
| 1837 | if (bit (this_instr, 23)) |
| 1838 | base += offset; |
| 1839 | else |
| 1840 | base -= offset; |
| 1841 | } |
| 1842 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
| 1843 | 4); |
| 1844 | |
| 1845 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1846 | |
| 1847 | if (nextpc == pc) |
| 1848 | error ("Infinite loop detected"); |
| 1849 | } |
| 1850 | } |
| 1851 | break; |
| 1852 | |
| 1853 | case 0x8: |
| 1854 | case 0x9: /* block transfer */ |
| 1855 | if (bit (this_instr, 20)) |
| 1856 | { |
| 1857 | /* LDM */ |
| 1858 | if (bit (this_instr, 15)) |
| 1859 | { |
| 1860 | /* loading pc */ |
| 1861 | int offset = 0; |
| 1862 | |
| 1863 | if (bit (this_instr, 23)) |
| 1864 | { |
| 1865 | /* up */ |
| 1866 | unsigned long reglist = bits (this_instr, 0, 14); |
| 1867 | offset = bitcount (reglist) * 4; |
| 1868 | if (bit (this_instr, 24)) /* pre */ |
| 1869 | offset += 4; |
| 1870 | } |
| 1871 | else if (bit (this_instr, 24)) |
| 1872 | offset = -4; |
| 1873 | |
| 1874 | { |
| 1875 | unsigned long rn_val = |
| 1876 | read_register (bits (this_instr, 16, 19)); |
| 1877 | nextpc = |
| 1878 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val |
| 1879 | + offset), |
| 1880 | 4); |
| 1881 | } |
| 1882 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1883 | if (nextpc == pc) |
| 1884 | error ("Infinite loop detected"); |
| 1885 | } |
| 1886 | } |
| 1887 | break; |
| 1888 | |
| 1889 | case 0xb: /* branch & link */ |
| 1890 | case 0xa: /* branch */ |
| 1891 | { |
| 1892 | nextpc = BranchDest (pc, this_instr); |
| 1893 | |
| 1894 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1895 | if (nextpc == pc) |
| 1896 | error ("Infinite loop detected"); |
| 1897 | break; |
| 1898 | } |
| 1899 | |
| 1900 | case 0xc: |
| 1901 | case 0xd: |
| 1902 | case 0xe: /* coproc ops */ |
| 1903 | case 0xf: /* SWI */ |
| 1904 | break; |
| 1905 | |
| 1906 | default: |
| 1907 | fprintf (stderr, "Bad bit-field extraction\n"); |
| 1908 | return (pc); |
| 1909 | } |
| 1910 | } |
| 1911 | |
| 1912 | return nextpc; |
| 1913 | } |
| 1914 | |
| 1915 | #include "bfd-in2.h" |
| 1916 | #include "libcoff.h" |
| 1917 | |
| 1918 | static int |
| 1919 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
| 1920 | { |
| 1921 | if (arm_pc_is_thumb (memaddr)) |
| 1922 | { |
| 1923 | static asymbol *asym; |
| 1924 | static combined_entry_type ce; |
| 1925 | static struct coff_symbol_struct csym; |
| 1926 | static struct _bfd fake_bfd; |
| 1927 | static bfd_target fake_target; |
| 1928 | |
| 1929 | if (csym.native == NULL) |
| 1930 | { |
| 1931 | /* Create a fake symbol vector containing a Thumb symbol. This is |
| 1932 | solely so that the code in print_insn_little_arm() and |
| 1933 | print_insn_big_arm() in opcodes/arm-dis.c will detect the presence |
| 1934 | of a Thumb symbol and switch to decoding Thumb instructions. */ |
| 1935 | |
| 1936 | fake_target.flavour = bfd_target_coff_flavour; |
| 1937 | fake_bfd.xvec = &fake_target; |
| 1938 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
| 1939 | csym.native = &ce; |
| 1940 | csym.symbol.the_bfd = &fake_bfd; |
| 1941 | csym.symbol.name = "fake"; |
| 1942 | asym = (asymbol *) & csym; |
| 1943 | } |
| 1944 | |
| 1945 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
| 1946 | info->symbols = &asym; |
| 1947 | } |
| 1948 | else |
| 1949 | info->symbols = NULL; |
| 1950 | |
| 1951 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 1952 | return print_insn_big_arm (memaddr, info); |
| 1953 | else |
| 1954 | return print_insn_little_arm (memaddr, info); |
| 1955 | } |
| 1956 | |
| 1957 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the |
| 1958 | program counter value to determine whether a 16-bit or 32-bit |
| 1959 | breakpoint should be used. It returns a pointer to a string of |
| 1960 | bytes that encode a breakpoint instruction, stores the length of |
| 1961 | the string to *lenptr, and adjusts the program counter (if |
| 1962 | necessary) to point to the actual memory location where the |
| 1963 | breakpoint should be inserted. */ |
| 1964 | |
| 1965 | unsigned char * |
| 1966 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
| 1967 | { |
| 1968 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) |
| 1969 | { |
| 1970 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 1971 | { |
| 1972 | static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT; |
| 1973 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
| 1974 | *lenptr = sizeof (thumb_breakpoint); |
| 1975 | return thumb_breakpoint; |
| 1976 | } |
| 1977 | else |
| 1978 | { |
| 1979 | static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT; |
| 1980 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
| 1981 | *lenptr = sizeof (thumb_breakpoint); |
| 1982 | return thumb_breakpoint; |
| 1983 | } |
| 1984 | } |
| 1985 | else |
| 1986 | { |
| 1987 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 1988 | { |
| 1989 | static char arm_breakpoint[] = ARM_BE_BREAKPOINT; |
| 1990 | *lenptr = sizeof (arm_breakpoint); |
| 1991 | return arm_breakpoint; |
| 1992 | } |
| 1993 | else |
| 1994 | { |
| 1995 | static char arm_breakpoint[] = ARM_LE_BREAKPOINT; |
| 1996 | *lenptr = sizeof (arm_breakpoint); |
| 1997 | return arm_breakpoint; |
| 1998 | } |
| 1999 | } |
| 2000 | } |
| 2001 | |
| 2002 | /* Extract from an array REGBUF containing the (raw) register state a |
| 2003 | function return value of type TYPE, and copy that, in virtual |
| 2004 | format, into VALBUF. */ |
| 2005 | |
| 2006 | void |
| 2007 | arm_extract_return_value (struct type *type, |
| 2008 | char regbuf[REGISTER_BYTES], |
| 2009 | char *valbuf) |
| 2010 | { |
| 2011 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
| 2012 | convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf); |
| 2013 | else |
| 2014 | memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type)); |
| 2015 | } |
| 2016 | |
| 2017 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
| 2018 | |
| 2019 | int |
| 2020 | arm_in_call_stub (CORE_ADDR pc, char *name) |
| 2021 | { |
| 2022 | CORE_ADDR start_addr; |
| 2023 | |
| 2024 | /* Find the starting address of the function containing the PC. If |
| 2025 | the caller didn't give us a name, look it up at the same time. */ |
| 2026 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) |
| 2027 | return 0; |
| 2028 | |
| 2029 | return strncmp (name, "_call_via_r", 11) == 0; |
| 2030 | } |
| 2031 | |
| 2032 | /* If PC is in a Thumb call or return stub, return the address of the |
| 2033 | target PC, which is in a register. The thunk functions are called |
| 2034 | _called_via_xx, where x is the register name. The possible names |
| 2035 | are r0-r9, sl, fp, ip, sp, and lr. */ |
| 2036 | |
| 2037 | CORE_ADDR |
| 2038 | arm_skip_stub (CORE_ADDR pc) |
| 2039 | { |
| 2040 | char *name; |
| 2041 | CORE_ADDR start_addr; |
| 2042 | |
| 2043 | /* Find the starting address and name of the function containing the PC. */ |
| 2044 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 2045 | return 0; |
| 2046 | |
| 2047 | /* Call thunks always start with "_call_via_". */ |
| 2048 | if (strncmp (name, "_call_via_", 10) == 0) |
| 2049 | { |
| 2050 | /* Use the name suffix to determine which register contains the |
| 2051 | target PC. */ |
| 2052 | static char *table[15] = |
| 2053 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 2054 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" |
| 2055 | }; |
| 2056 | int regno; |
| 2057 | |
| 2058 | for (regno = 0; regno <= 14; regno++) |
| 2059 | if (strcmp (&name[10], table[regno]) == 0) |
| 2060 | return read_register (regno); |
| 2061 | } |
| 2062 | |
| 2063 | return 0; /* not a stub */ |
| 2064 | } |
| 2065 | |
| 2066 | /* If the user changes the register disassembly flavor used for info register |
| 2067 | and other commands, we have to also switch the flavor used in opcodes |
| 2068 | for disassembly output. |
| 2069 | This function is run in the set disassembly_flavor command, and does that. */ |
| 2070 | |
| 2071 | static void |
| 2072 | set_disassembly_flavor_sfunc (char *args, int from_tty, |
| 2073 | struct cmd_list_element *c) |
| 2074 | { |
| 2075 | set_disassembly_flavor (); |
| 2076 | } |
| 2077 | \f |
| 2078 | static void |
| 2079 | set_disassembly_flavor (void) |
| 2080 | { |
| 2081 | const char *setname, *setdesc, **regnames; |
| 2082 | int numregs, j; |
| 2083 | |
| 2084 | /* Find the flavor that the user wants in the opcodes table. */ |
| 2085 | int current = 0; |
| 2086 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); |
| 2087 | while ((disassembly_flavor != setname) |
| 2088 | && (current < num_flavor_options)) |
| 2089 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
| 2090 | current_option = current; |
| 2091 | |
| 2092 | /* Fill our copy. */ |
| 2093 | for (j = 0; j < numregs; j++) |
| 2094 | arm_register_names[j] = (char *) regnames[j]; |
| 2095 | |
| 2096 | /* Adjust case. */ |
| 2097 | if (isupper (*regnames[PC_REGNUM])) |
| 2098 | { |
| 2099 | arm_register_names[FPS_REGNUM] = "FPS"; |
| 2100 | arm_register_names[PS_REGNUM] = "CPSR"; |
| 2101 | } |
| 2102 | else |
| 2103 | { |
| 2104 | arm_register_names[FPS_REGNUM] = "fps"; |
| 2105 | arm_register_names[PS_REGNUM] = "cpsr"; |
| 2106 | } |
| 2107 | |
| 2108 | /* Synchronize the disassembler. */ |
| 2109 | set_arm_regname_option (current); |
| 2110 | } |
| 2111 | |
| 2112 | /* arm_othernames implements the "othernames" command. This is kind |
| 2113 | of hacky, and I prefer the set-show disassembly-flavor which is |
| 2114 | also used for the x86 gdb. I will keep this around, however, in |
| 2115 | case anyone is actually using it. */ |
| 2116 | |
| 2117 | static void |
| 2118 | arm_othernames (char *names, int n) |
| 2119 | { |
| 2120 | /* Circle through the various flavors. */ |
| 2121 | current_option = (current_option + 1) % num_flavor_options; |
| 2122 | |
| 2123 | disassembly_flavor = valid_flavors[current_option]; |
| 2124 | set_disassembly_flavor (); |
| 2125 | } |
| 2126 | |
| 2127 | void |
| 2128 | _initialize_arm_tdep (void) |
| 2129 | { |
| 2130 | struct ui_file *stb; |
| 2131 | long length; |
| 2132 | struct cmd_list_element *new_cmd; |
| 2133 | const char *setname; |
| 2134 | const char *setdesc; |
| 2135 | const char **regnames; |
| 2136 | int numregs, i, j; |
| 2137 | static char *helptext; |
| 2138 | |
| 2139 | tm_print_insn = gdb_print_insn_arm; |
| 2140 | |
| 2141 | /* Get the number of possible sets of register names defined in opcodes. */ |
| 2142 | num_flavor_options = get_arm_regname_num_options (); |
| 2143 | |
| 2144 | /* Sync the opcode insn printer with our register viewer: */ |
| 2145 | parse_arm_disassembler_option ("reg-names-std"); |
| 2146 | |
| 2147 | /* Begin creating the help text. */ |
| 2148 | stb = mem_fileopen (); |
| 2149 | fprintf_unfiltered (stb, "Set the disassembly flavor.\n\ |
| 2150 | The valid values are:\n"); |
| 2151 | |
| 2152 | /* Initialize the array that will be passed to add_set_enum_cmd(). */ |
| 2153 | valid_flavors = xmalloc ((num_flavor_options + 1) * sizeof (char *)); |
| 2154 | for (i = 0; i < num_flavor_options; i++) |
| 2155 | { |
| 2156 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); |
| 2157 | valid_flavors[i] = setname; |
| 2158 | fprintf_unfiltered (stb, "%s - %s\n", setname, |
| 2159 | setdesc); |
| 2160 | /* Copy the default names (if found) and synchronize disassembler. */ |
| 2161 | if (!strcmp (setname, "std")) |
| 2162 | { |
| 2163 | disassembly_flavor = setname; |
| 2164 | current_option = i; |
| 2165 | for (j = 0; j < numregs; j++) |
| 2166 | arm_register_names[j] = (char *) regnames[j]; |
| 2167 | set_arm_regname_option (i); |
| 2168 | } |
| 2169 | } |
| 2170 | /* Mark the end of valid options. */ |
| 2171 | valid_flavors[num_flavor_options] = NULL; |
| 2172 | |
| 2173 | /* Finish the creation of the help text. */ |
| 2174 | fprintf_unfiltered (stb, "The default is \"std\"."); |
| 2175 | helptext = ui_file_xstrdup (stb, &length); |
| 2176 | ui_file_delete (stb); |
| 2177 | |
| 2178 | /* Add the disassembly-flavor command */ |
| 2179 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
| 2180 | valid_flavors, |
| 2181 | &disassembly_flavor, |
| 2182 | helptext, |
| 2183 | &setlist); |
| 2184 | new_cmd->function.sfunc = set_disassembly_flavor_sfunc; |
| 2185 | add_show_from_set (new_cmd, &showlist); |
| 2186 | |
| 2187 | /* ??? Maybe this should be a boolean. */ |
| 2188 | add_show_from_set (add_set_cmd ("apcs32", no_class, |
| 2189 | var_zinteger, (char *) &arm_apcs_32, |
| 2190 | "Set usage of ARM 32-bit mode.\n", &setlist), |
| 2191 | &showlist); |
| 2192 | |
| 2193 | /* Add the deprecated "othernames" command */ |
| 2194 | |
| 2195 | add_com ("othernames", class_obscure, arm_othernames, |
| 2196 | "Switch to the next set of register names."); |
| 2197 | } |
| 2198 | |
| 2199 | /* Test whether the coff symbol specific value corresponds to a Thumb |
| 2200 | function. */ |
| 2201 | |
| 2202 | int |
| 2203 | coff_sym_is_thumb (int val) |
| 2204 | { |
| 2205 | return (val == C_THUMBEXT || |
| 2206 | val == C_THUMBSTAT || |
| 2207 | val == C_THUMBEXTFUNC || |
| 2208 | val == C_THUMBSTATFUNC || |
| 2209 | val == C_THUMBLABEL); |
| 2210 | } |