| 1 | /* Common target dependent code for GDB on ARM systems. |
| 2 | |
| 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
| 4 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
| 5 | Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | #include <ctype.h> /* XXX for isupper () */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "frame.h" |
| 26 | #include "inferior.h" |
| 27 | #include "gdbcmd.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "gdb_string.h" |
| 30 | #include "dis-asm.h" /* For register styles. */ |
| 31 | #include "regcache.h" |
| 32 | #include "doublest.h" |
| 33 | #include "value.h" |
| 34 | #include "arch-utils.h" |
| 35 | #include "osabi.h" |
| 36 | #include "frame-unwind.h" |
| 37 | #include "frame-base.h" |
| 38 | #include "trad-frame.h" |
| 39 | #include "objfiles.h" |
| 40 | #include "dwarf2-frame.h" |
| 41 | #include "gdbtypes.h" |
| 42 | #include "prologue-value.h" |
| 43 | #include "target-descriptions.h" |
| 44 | #include "user-regs.h" |
| 45 | |
| 46 | #include "arm-tdep.h" |
| 47 | #include "gdb/sim-arm.h" |
| 48 | |
| 49 | #include "elf-bfd.h" |
| 50 | #include "coff/internal.h" |
| 51 | #include "elf/arm.h" |
| 52 | |
| 53 | #include "gdb_assert.h" |
| 54 | #include "vec.h" |
| 55 | |
| 56 | static int arm_debug; |
| 57 | |
| 58 | /* Macros for setting and testing a bit in a minimal symbol that marks |
| 59 | it as Thumb function. The MSB of the minimal symbol's "info" field |
| 60 | is used for this purpose. |
| 61 | |
| 62 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. |
| 63 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
| 64 | |
| 65 | #define MSYMBOL_SET_SPECIAL(msym) \ |
| 66 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
| 67 | |
| 68 | #define MSYMBOL_IS_SPECIAL(msym) \ |
| 69 | MSYMBOL_TARGET_FLAG_1 (msym) |
| 70 | |
| 71 | /* Per-objfile data used for mapping symbols. */ |
| 72 | static const struct objfile_data *arm_objfile_data_key; |
| 73 | |
| 74 | struct arm_mapping_symbol |
| 75 | { |
| 76 | bfd_vma value; |
| 77 | char type; |
| 78 | }; |
| 79 | typedef struct arm_mapping_symbol arm_mapping_symbol_s; |
| 80 | DEF_VEC_O(arm_mapping_symbol_s); |
| 81 | |
| 82 | struct arm_per_objfile |
| 83 | { |
| 84 | VEC(arm_mapping_symbol_s) **section_maps; |
| 85 | }; |
| 86 | |
| 87 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
| 88 | static struct cmd_list_element *setarmcmdlist = NULL; |
| 89 | static struct cmd_list_element *showarmcmdlist = NULL; |
| 90 | |
| 91 | /* The type of floating-point to use. Keep this in sync with enum |
| 92 | arm_float_model, and the help string in _initialize_arm_tdep. */ |
| 93 | static const char *fp_model_strings[] = |
| 94 | { |
| 95 | "auto", |
| 96 | "softfpa", |
| 97 | "fpa", |
| 98 | "softvfp", |
| 99 | "vfp", |
| 100 | NULL |
| 101 | }; |
| 102 | |
| 103 | /* A variable that can be configured by the user. */ |
| 104 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; |
| 105 | static const char *current_fp_model = "auto"; |
| 106 | |
| 107 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
| 108 | static const char *arm_abi_strings[] = |
| 109 | { |
| 110 | "auto", |
| 111 | "APCS", |
| 112 | "AAPCS", |
| 113 | NULL |
| 114 | }; |
| 115 | |
| 116 | /* A variable that can be configured by the user. */ |
| 117 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; |
| 118 | static const char *arm_abi_string = "auto"; |
| 119 | |
| 120 | /* The execution mode to assume. */ |
| 121 | static const char *arm_mode_strings[] = |
| 122 | { |
| 123 | "auto", |
| 124 | "arm", |
| 125 | "thumb" |
| 126 | }; |
| 127 | |
| 128 | static const char *arm_fallback_mode_string = "auto"; |
| 129 | static const char *arm_force_mode_string = "auto"; |
| 130 | |
| 131 | /* Number of different reg name sets (options). */ |
| 132 | static int num_disassembly_options; |
| 133 | |
| 134 | /* The standard register names, and all the valid aliases for them. */ |
| 135 | static const struct |
| 136 | { |
| 137 | const char *name; |
| 138 | int regnum; |
| 139 | } arm_register_aliases[] = { |
| 140 | /* Basic register numbers. */ |
| 141 | { "r0", 0 }, |
| 142 | { "r1", 1 }, |
| 143 | { "r2", 2 }, |
| 144 | { "r3", 3 }, |
| 145 | { "r4", 4 }, |
| 146 | { "r5", 5 }, |
| 147 | { "r6", 6 }, |
| 148 | { "r7", 7 }, |
| 149 | { "r8", 8 }, |
| 150 | { "r9", 9 }, |
| 151 | { "r10", 10 }, |
| 152 | { "r11", 11 }, |
| 153 | { "r12", 12 }, |
| 154 | { "r13", 13 }, |
| 155 | { "r14", 14 }, |
| 156 | { "r15", 15 }, |
| 157 | /* Synonyms (argument and variable registers). */ |
| 158 | { "a1", 0 }, |
| 159 | { "a2", 1 }, |
| 160 | { "a3", 2 }, |
| 161 | { "a4", 3 }, |
| 162 | { "v1", 4 }, |
| 163 | { "v2", 5 }, |
| 164 | { "v3", 6 }, |
| 165 | { "v4", 7 }, |
| 166 | { "v5", 8 }, |
| 167 | { "v6", 9 }, |
| 168 | { "v7", 10 }, |
| 169 | { "v8", 11 }, |
| 170 | /* Other platform-specific names for r9. */ |
| 171 | { "sb", 9 }, |
| 172 | { "tr", 9 }, |
| 173 | /* Special names. */ |
| 174 | { "ip", 12 }, |
| 175 | { "sp", 13 }, |
| 176 | { "lr", 14 }, |
| 177 | { "pc", 15 }, |
| 178 | /* Names used by GCC (not listed in the ARM EABI). */ |
| 179 | { "sl", 10 }, |
| 180 | { "fp", 11 }, |
| 181 | /* A special name from the older ATPCS. */ |
| 182 | { "wr", 7 }, |
| 183 | }; |
| 184 | |
| 185 | static const char *const arm_register_names[] = |
| 186 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
| 187 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ |
| 188 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ |
| 189 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ |
| 190 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ |
| 191 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ |
| 192 | "fps", "cpsr" }; /* 24 25 */ |
| 193 | |
| 194 | /* Valid register name styles. */ |
| 195 | static const char **valid_disassembly_styles; |
| 196 | |
| 197 | /* Disassembly style to use. Default to "std" register names. */ |
| 198 | static const char *disassembly_style; |
| 199 | |
| 200 | /* This is used to keep the bfd arch_info in sync with the disassembly |
| 201 | style. */ |
| 202 | static void set_disassembly_style_sfunc(char *, int, |
| 203 | struct cmd_list_element *); |
| 204 | static void set_disassembly_style (void); |
| 205 | |
| 206 | static void convert_from_extended (const struct floatformat *, const void *, |
| 207 | void *, int); |
| 208 | static void convert_to_extended (const struct floatformat *, void *, |
| 209 | const void *, int); |
| 210 | |
| 211 | static void arm_neon_quad_read (struct gdbarch *gdbarch, |
| 212 | struct regcache *regcache, |
| 213 | int regnum, gdb_byte *buf); |
| 214 | static void arm_neon_quad_write (struct gdbarch *gdbarch, |
| 215 | struct regcache *regcache, |
| 216 | int regnum, const gdb_byte *buf); |
| 217 | |
| 218 | struct arm_prologue_cache |
| 219 | { |
| 220 | /* The stack pointer at the time this frame was created; i.e. the |
| 221 | caller's stack pointer when this function was called. It is used |
| 222 | to identify this frame. */ |
| 223 | CORE_ADDR prev_sp; |
| 224 | |
| 225 | /* The frame base for this frame is just prev_sp - frame size. |
| 226 | FRAMESIZE is the distance from the frame pointer to the |
| 227 | initial stack pointer. */ |
| 228 | |
| 229 | int framesize; |
| 230 | |
| 231 | /* The register used to hold the frame pointer for this frame. */ |
| 232 | int framereg; |
| 233 | |
| 234 | /* Saved register offsets. */ |
| 235 | struct trad_frame_saved_reg *saved_regs; |
| 236 | }; |
| 237 | |
| 238 | /* Architecture version for displaced stepping. This effects the behaviour of |
| 239 | certain instructions, and really should not be hard-wired. */ |
| 240 | |
| 241 | #define DISPLACED_STEPPING_ARCH_VERSION 5 |
| 242 | |
| 243 | /* Addresses for calling Thumb functions have the bit 0 set. |
| 244 | Here are some macros to test, set, or clear bit 0 of addresses. */ |
| 245 | #define IS_THUMB_ADDR(addr) ((addr) & 1) |
| 246 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) |
| 247 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) |
| 248 | |
| 249 | /* Set to true if the 32-bit mode is in use. */ |
| 250 | |
| 251 | int arm_apcs_32 = 1; |
| 252 | |
| 253 | /* Determine if FRAME is executing in Thumb mode. */ |
| 254 | |
| 255 | static int |
| 256 | arm_frame_is_thumb (struct frame_info *frame) |
| 257 | { |
| 258 | CORE_ADDR cpsr; |
| 259 | |
| 260 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either |
| 261 | directly (from a signal frame or dummy frame) or by interpreting |
| 262 | the saved LR (from a prologue or DWARF frame). So consult it and |
| 263 | trust the unwinders. */ |
| 264 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
| 265 | |
| 266 | return (cpsr & CPSR_T) != 0; |
| 267 | } |
| 268 | |
| 269 | /* Callback for VEC_lower_bound. */ |
| 270 | |
| 271 | static inline int |
| 272 | arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs, |
| 273 | const struct arm_mapping_symbol *rhs) |
| 274 | { |
| 275 | return lhs->value < rhs->value; |
| 276 | } |
| 277 | |
| 278 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
| 279 | function. This function should be called for addresses unrelated to |
| 280 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ |
| 281 | |
| 282 | static int |
| 283 | arm_pc_is_thumb (CORE_ADDR memaddr) |
| 284 | { |
| 285 | struct obj_section *sec; |
| 286 | struct minimal_symbol *sym; |
| 287 | |
| 288 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
| 289 | if (IS_THUMB_ADDR (memaddr)) |
| 290 | return 1; |
| 291 | |
| 292 | /* If the user wants to override the symbol table, let him. */ |
| 293 | if (strcmp (arm_force_mode_string, "arm") == 0) |
| 294 | return 0; |
| 295 | if (strcmp (arm_force_mode_string, "thumb") == 0) |
| 296 | return 1; |
| 297 | |
| 298 | /* If there are mapping symbols, consult them. */ |
| 299 | sec = find_pc_section (memaddr); |
| 300 | if (sec != NULL) |
| 301 | { |
| 302 | struct arm_per_objfile *data; |
| 303 | VEC(arm_mapping_symbol_s) *map; |
| 304 | struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec), |
| 305 | 0 }; |
| 306 | unsigned int idx; |
| 307 | |
| 308 | data = objfile_data (sec->objfile, arm_objfile_data_key); |
| 309 | if (data != NULL) |
| 310 | { |
| 311 | map = data->section_maps[sec->the_bfd_section->index]; |
| 312 | if (!VEC_empty (arm_mapping_symbol_s, map)) |
| 313 | { |
| 314 | struct arm_mapping_symbol *map_sym; |
| 315 | |
| 316 | idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key, |
| 317 | arm_compare_mapping_symbols); |
| 318 | |
| 319 | /* VEC_lower_bound finds the earliest ordered insertion |
| 320 | point. If the following symbol starts at this exact |
| 321 | address, we use that; otherwise, the preceding |
| 322 | mapping symbol covers this address. */ |
| 323 | if (idx < VEC_length (arm_mapping_symbol_s, map)) |
| 324 | { |
| 325 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx); |
| 326 | if (map_sym->value == map_key.value) |
| 327 | return map_sym->type == 't'; |
| 328 | } |
| 329 | |
| 330 | if (idx > 0) |
| 331 | { |
| 332 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1); |
| 333 | return map_sym->type == 't'; |
| 334 | } |
| 335 | } |
| 336 | } |
| 337 | } |
| 338 | |
| 339 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
| 340 | sym = lookup_minimal_symbol_by_pc (memaddr); |
| 341 | if (sym) |
| 342 | return (MSYMBOL_IS_SPECIAL (sym)); |
| 343 | |
| 344 | /* If the user wants to override the fallback mode, let them. */ |
| 345 | if (strcmp (arm_fallback_mode_string, "arm") == 0) |
| 346 | return 0; |
| 347 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) |
| 348 | return 1; |
| 349 | |
| 350 | /* If we couldn't find any symbol, but we're talking to a running |
| 351 | target, then trust the current value of $cpsr. This lets |
| 352 | "display/i $pc" always show the correct mode (though if there is |
| 353 | a symbol table we will not reach here, so it still may not be |
| 354 | displayed in the mode it will be executed). */ |
| 355 | if (target_has_registers) |
| 356 | return arm_frame_is_thumb (get_current_frame ()); |
| 357 | |
| 358 | /* Otherwise we're out of luck; we assume ARM. */ |
| 359 | return 0; |
| 360 | } |
| 361 | |
| 362 | /* Remove useless bits from addresses in a running program. */ |
| 363 | static CORE_ADDR |
| 364 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
| 365 | { |
| 366 | if (arm_apcs_32) |
| 367 | return UNMAKE_THUMB_ADDR (val); |
| 368 | else |
| 369 | return (val & 0x03fffffc); |
| 370 | } |
| 371 | |
| 372 | /* When reading symbols, we need to zap the low bit of the address, |
| 373 | which may be set to 1 for Thumb functions. */ |
| 374 | static CORE_ADDR |
| 375 | arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val) |
| 376 | { |
| 377 | return val & ~1; |
| 378 | } |
| 379 | |
| 380 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
| 381 | and frame pointer. Scan until we encounter a store that could |
| 382 | clobber the stack frame unexpectedly, or an unknown instruction. */ |
| 383 | |
| 384 | static CORE_ADDR |
| 385 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
| 386 | CORE_ADDR start, CORE_ADDR limit, |
| 387 | struct arm_prologue_cache *cache) |
| 388 | { |
| 389 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
| 390 | int i; |
| 391 | pv_t regs[16]; |
| 392 | struct pv_area *stack; |
| 393 | struct cleanup *back_to; |
| 394 | CORE_ADDR offset; |
| 395 | |
| 396 | for (i = 0; i < 16; i++) |
| 397 | regs[i] = pv_register (i, 0); |
| 398 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
| 399 | back_to = make_cleanup_free_pv_area (stack); |
| 400 | |
| 401 | while (start < limit) |
| 402 | { |
| 403 | unsigned short insn; |
| 404 | |
| 405 | insn = read_memory_unsigned_integer (start, 2, byte_order_for_code); |
| 406 | |
| 407 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 408 | { |
| 409 | int regno; |
| 410 | int mask; |
| 411 | |
| 412 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 413 | break; |
| 414 | |
| 415 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
| 416 | whether to save LR (R14). */ |
| 417 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
| 418 | |
| 419 | /* Calculate offsets of saved R0-R7 and LR. */ |
| 420 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
| 421 | if (mask & (1 << regno)) |
| 422 | { |
| 423 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
| 424 | -4); |
| 425 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); |
| 426 | } |
| 427 | } |
| 428 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
| 429 | sub sp, #simm */ |
| 430 | { |
| 431 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
| 432 | if (insn & 0x80) /* Check for SUB. */ |
| 433 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
| 434 | -offset); |
| 435 | else |
| 436 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
| 437 | offset); |
| 438 | } |
| 439 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 440 | regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
| 441 | (insn & 0xff) << 2); |
| 442 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
| 443 | { |
| 444 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
| 445 | int src_reg = (insn & 0x78) >> 3; |
| 446 | regs[dst_reg] = regs[src_reg]; |
| 447 | } |
| 448 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
| 449 | { |
| 450 | /* Handle stores to the stack. Normally pushes are used, |
| 451 | but with GCC -mtpcs-frame, there may be other stores |
| 452 | in the prologue to create the frame. */ |
| 453 | int regno = (insn >> 8) & 0x7; |
| 454 | pv_t addr; |
| 455 | |
| 456 | offset = (insn & 0xff) << 2; |
| 457 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); |
| 458 | |
| 459 | if (pv_area_store_would_trash (stack, addr)) |
| 460 | break; |
| 461 | |
| 462 | pv_area_store (stack, addr, 4, regs[regno]); |
| 463 | } |
| 464 | else |
| 465 | { |
| 466 | /* We don't know what this instruction is. We're finished |
| 467 | scanning. NOTE: Recognizing more safe-to-ignore |
| 468 | instructions here will improve support for optimized |
| 469 | code. */ |
| 470 | break; |
| 471 | } |
| 472 | |
| 473 | start += 2; |
| 474 | } |
| 475 | |
| 476 | if (cache == NULL) |
| 477 | { |
| 478 | do_cleanups (back_to); |
| 479 | return start; |
| 480 | } |
| 481 | |
| 482 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
| 483 | { |
| 484 | /* Frame pointer is fp. Frame size is constant. */ |
| 485 | cache->framereg = ARM_FP_REGNUM; |
| 486 | cache->framesize = -regs[ARM_FP_REGNUM].k; |
| 487 | } |
| 488 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) |
| 489 | { |
| 490 | /* Frame pointer is r7. Frame size is constant. */ |
| 491 | cache->framereg = THUMB_FP_REGNUM; |
| 492 | cache->framesize = -regs[THUMB_FP_REGNUM].k; |
| 493 | } |
| 494 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) |
| 495 | { |
| 496 | /* Try the stack pointer... this is a bit desperate. */ |
| 497 | cache->framereg = ARM_SP_REGNUM; |
| 498 | cache->framesize = -regs[ARM_SP_REGNUM].k; |
| 499 | } |
| 500 | else |
| 501 | { |
| 502 | /* We're just out of luck. We don't know where the frame is. */ |
| 503 | cache->framereg = -1; |
| 504 | cache->framesize = 0; |
| 505 | } |
| 506 | |
| 507 | for (i = 0; i < 16; i++) |
| 508 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) |
| 509 | cache->saved_regs[i].addr = offset; |
| 510 | |
| 511 | do_cleanups (back_to); |
| 512 | return start; |
| 513 | } |
| 514 | |
| 515 | /* Advance the PC across any function entry prologue instructions to |
| 516 | reach some "real" code. |
| 517 | |
| 518 | The APCS (ARM Procedure Call Standard) defines the following |
| 519 | prologue: |
| 520 | |
| 521 | mov ip, sp |
| 522 | [stmfd sp!, {a1,a2,a3,a4}] |
| 523 | stmfd sp!, {...,fp,ip,lr,pc} |
| 524 | [stfe f7, [sp, #-12]!] |
| 525 | [stfe f6, [sp, #-12]!] |
| 526 | [stfe f5, [sp, #-12]!] |
| 527 | [stfe f4, [sp, #-12]!] |
| 528 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ |
| 529 | |
| 530 | static CORE_ADDR |
| 531 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 532 | { |
| 533 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
| 534 | unsigned long inst; |
| 535 | CORE_ADDR skip_pc; |
| 536 | CORE_ADDR func_addr, limit_pc; |
| 537 | struct symtab_and_line sal; |
| 538 | |
| 539 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
| 540 | if (deprecated_pc_in_call_dummy (gdbarch, pc)) |
| 541 | return pc; |
| 542 | |
| 543 | /* See if we can determine the end of the prologue via the symbol table. |
| 544 | If so, then return either PC, or the PC after the prologue, whichever |
| 545 | is greater. */ |
| 546 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
| 547 | { |
| 548 | CORE_ADDR post_prologue_pc |
| 549 | = skip_prologue_using_sal (gdbarch, func_addr); |
| 550 | if (post_prologue_pc != 0) |
| 551 | return max (pc, post_prologue_pc); |
| 552 | } |
| 553 | |
| 554 | /* Can't determine prologue from the symbol table, need to examine |
| 555 | instructions. */ |
| 556 | |
| 557 | /* Find an upper limit on the function prologue using the debug |
| 558 | information. If the debug information could not be used to provide |
| 559 | that bound, then use an arbitrary large number as the upper bound. */ |
| 560 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
| 561 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
| 562 | if (limit_pc == 0) |
| 563 | limit_pc = pc + 64; /* Magic. */ |
| 564 | |
| 565 | |
| 566 | /* Check if this is Thumb code. */ |
| 567 | if (arm_pc_is_thumb (pc)) |
| 568 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
| 569 | |
| 570 | for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4) |
| 571 | { |
| 572 | inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code); |
| 573 | |
| 574 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
| 575 | if (inst == 0xe1a0c00d) /* mov ip, sp */ |
| 576 | continue; |
| 577 | |
| 578 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
| 579 | continue; |
| 580 | |
| 581 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ |
| 582 | continue; |
| 583 | |
| 584 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
| 585 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 586 | continue; |
| 587 | |
| 588 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
| 589 | continue; |
| 590 | |
| 591 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
| 592 | continue; |
| 593 | |
| 594 | /* Any insns after this point may float into the code, if it makes |
| 595 | for better instruction scheduling, so we skip them only if we |
| 596 | find them, but still consider the function to be frame-ful. */ |
| 597 | |
| 598 | /* We may have either one sfmfd instruction here, or several stfe |
| 599 | insns, depending on the version of floating point code we |
| 600 | support. */ |
| 601 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
| 602 | continue; |
| 603 | |
| 604 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
| 605 | continue; |
| 606 | |
| 607 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
| 608 | continue; |
| 609 | |
| 610 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ |
| 611 | continue; |
| 612 | |
| 613 | if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */ |
| 614 | || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */ |
| 615 | || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ |
| 616 | continue; |
| 617 | |
| 618 | if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */ |
| 619 | || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */ |
| 620 | || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ |
| 621 | continue; |
| 622 | |
| 623 | /* Un-recognized instruction; stop scanning. */ |
| 624 | break; |
| 625 | } |
| 626 | |
| 627 | return skip_pc; /* End of prologue */ |
| 628 | } |
| 629 | |
| 630 | /* *INDENT-OFF* */ |
| 631 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
| 632 | This function decodes a Thumb function prologue to determine: |
| 633 | 1) the size of the stack frame |
| 634 | 2) which registers are saved on it |
| 635 | 3) the offsets of saved regs |
| 636 | 4) the offset from the stack pointer to the frame pointer |
| 637 | |
| 638 | A typical Thumb function prologue would create this stack frame |
| 639 | (offsets relative to FP) |
| 640 | old SP -> 24 stack parameters |
| 641 | 20 LR |
| 642 | 16 R7 |
| 643 | R7 -> 0 local variables (16 bytes) |
| 644 | SP -> -12 additional stack space (12 bytes) |
| 645 | The frame size would thus be 36 bytes, and the frame offset would be |
| 646 | 12 bytes. The frame register is R7. |
| 647 | |
| 648 | The comments for thumb_skip_prolog() describe the algorithm we use |
| 649 | to detect the end of the prolog. */ |
| 650 | /* *INDENT-ON* */ |
| 651 | |
| 652 | static void |
| 653 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
| 654 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
| 655 | { |
| 656 | CORE_ADDR prologue_start; |
| 657 | CORE_ADDR prologue_end; |
| 658 | CORE_ADDR current_pc; |
| 659 | |
| 660 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
| 661 | &prologue_end)) |
| 662 | { |
| 663 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 664 | |
| 665 | if (sal.line == 0) /* no line info, use current PC */ |
| 666 | prologue_end = prev_pc; |
| 667 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
| 668 | prologue_end = sal.end; /* (probably means no prologue) */ |
| 669 | } |
| 670 | else |
| 671 | /* We're in the boondocks: we have no idea where the start of the |
| 672 | function is. */ |
| 673 | return; |
| 674 | |
| 675 | prologue_end = min (prologue_end, prev_pc); |
| 676 | |
| 677 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
| 678 | } |
| 679 | |
| 680 | /* This function decodes an ARM function prologue to determine: |
| 681 | 1) the size of the stack frame |
| 682 | 2) which registers are saved on it |
| 683 | 3) the offsets of saved regs |
| 684 | 4) the offset from the stack pointer to the frame pointer |
| 685 | This information is stored in the "extra" fields of the frame_info. |
| 686 | |
| 687 | There are two basic forms for the ARM prologue. The fixed argument |
| 688 | function call will look like: |
| 689 | |
| 690 | mov ip, sp |
| 691 | stmfd sp!, {fp, ip, lr, pc} |
| 692 | sub fp, ip, #4 |
| 693 | [sub sp, sp, #4] |
| 694 | |
| 695 | Which would create this stack frame (offsets relative to FP): |
| 696 | IP -> 4 (caller's stack) |
| 697 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 698 | -4 LR (return address in caller) |
| 699 | -8 IP (copy of caller's SP) |
| 700 | -12 FP (caller's FP) |
| 701 | SP -> -28 Local variables |
| 702 | |
| 703 | The frame size would thus be 32 bytes, and the frame offset would be |
| 704 | 28 bytes. The stmfd call can also save any of the vN registers it |
| 705 | plans to use, which increases the frame size accordingly. |
| 706 | |
| 707 | Note: The stored PC is 8 off of the STMFD instruction that stored it |
| 708 | because the ARM Store instructions always store PC + 8 when you read |
| 709 | the PC register. |
| 710 | |
| 711 | A variable argument function call will look like: |
| 712 | |
| 713 | mov ip, sp |
| 714 | stmfd sp!, {a1, a2, a3, a4} |
| 715 | stmfd sp!, {fp, ip, lr, pc} |
| 716 | sub fp, ip, #20 |
| 717 | |
| 718 | Which would create this stack frame (offsets relative to FP): |
| 719 | IP -> 20 (caller's stack) |
| 720 | 16 A4 |
| 721 | 12 A3 |
| 722 | 8 A2 |
| 723 | 4 A1 |
| 724 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 725 | -4 LR (return address in caller) |
| 726 | -8 IP (copy of caller's SP) |
| 727 | -12 FP (caller's FP) |
| 728 | SP -> -28 Local variables |
| 729 | |
| 730 | The frame size would thus be 48 bytes, and the frame offset would be |
| 731 | 28 bytes. |
| 732 | |
| 733 | There is another potential complication, which is that the optimizer |
| 734 | will try to separate the store of fp in the "stmfd" instruction from |
| 735 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so |
| 736 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... |
| 737 | |
| 738 | Also, note, the original version of the ARM toolchain claimed that there |
| 739 | should be an |
| 740 | |
| 741 | instruction at the end of the prologue. I have never seen GCC produce |
| 742 | this, and the ARM docs don't mention it. We still test for it below in |
| 743 | case it happens... |
| 744 | |
| 745 | */ |
| 746 | |
| 747 | static void |
| 748 | arm_scan_prologue (struct frame_info *this_frame, |
| 749 | struct arm_prologue_cache *cache) |
| 750 | { |
| 751 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 752 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 753 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
| 754 | int regno; |
| 755 | CORE_ADDR prologue_start, prologue_end, current_pc; |
| 756 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
| 757 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); |
| 758 | pv_t regs[ARM_FPS_REGNUM]; |
| 759 | struct pv_area *stack; |
| 760 | struct cleanup *back_to; |
| 761 | CORE_ADDR offset; |
| 762 | |
| 763 | /* Assume there is no frame until proven otherwise. */ |
| 764 | cache->framereg = ARM_SP_REGNUM; |
| 765 | cache->framesize = 0; |
| 766 | |
| 767 | /* Check for Thumb prologue. */ |
| 768 | if (arm_frame_is_thumb (this_frame)) |
| 769 | { |
| 770 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); |
| 771 | return; |
| 772 | } |
| 773 | |
| 774 | /* Find the function prologue. If we can't find the function in |
| 775 | the symbol table, peek in the stack frame to find the PC. */ |
| 776 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
| 777 | &prologue_end)) |
| 778 | { |
| 779 | /* One way to find the end of the prologue (which works well |
| 780 | for unoptimized code) is to do the following: |
| 781 | |
| 782 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 783 | |
| 784 | if (sal.line == 0) |
| 785 | prologue_end = prev_pc; |
| 786 | else if (sal.end < prologue_end) |
| 787 | prologue_end = sal.end; |
| 788 | |
| 789 | This mechanism is very accurate so long as the optimizer |
| 790 | doesn't move any instructions from the function body into the |
| 791 | prologue. If this happens, sal.end will be the last |
| 792 | instruction in the first hunk of prologue code just before |
| 793 | the first instruction that the scheduler has moved from |
| 794 | the body to the prologue. |
| 795 | |
| 796 | In order to make sure that we scan all of the prologue |
| 797 | instructions, we use a slightly less accurate mechanism which |
| 798 | may scan more than necessary. To help compensate for this |
| 799 | lack of accuracy, the prologue scanning loop below contains |
| 800 | several clauses which'll cause the loop to terminate early if |
| 801 | an implausible prologue instruction is encountered. |
| 802 | |
| 803 | The expression |
| 804 | |
| 805 | prologue_start + 64 |
| 806 | |
| 807 | is a suitable endpoint since it accounts for the largest |
| 808 | possible prologue plus up to five instructions inserted by |
| 809 | the scheduler. */ |
| 810 | |
| 811 | if (prologue_end > prologue_start + 64) |
| 812 | { |
| 813 | prologue_end = prologue_start + 64; /* See above. */ |
| 814 | } |
| 815 | } |
| 816 | else |
| 817 | { |
| 818 | /* We have no symbol information. Our only option is to assume this |
| 819 | function has a standard stack frame and the normal frame register. |
| 820 | Then, we can find the value of our frame pointer on entrance to |
| 821 | the callee (or at the present moment if this is the innermost frame). |
| 822 | The value stored there should be the address of the stmfd + 8. */ |
| 823 | CORE_ADDR frame_loc; |
| 824 | LONGEST return_value; |
| 825 | |
| 826 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
| 827 | if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value)) |
| 828 | return; |
| 829 | else |
| 830 | { |
| 831 | prologue_start = gdbarch_addr_bits_remove |
| 832 | (gdbarch, return_value) - 8; |
| 833 | prologue_end = prologue_start + 64; /* See above. */ |
| 834 | } |
| 835 | } |
| 836 | |
| 837 | if (prev_pc < prologue_end) |
| 838 | prologue_end = prev_pc; |
| 839 | |
| 840 | /* Now search the prologue looking for instructions that set up the |
| 841 | frame pointer, adjust the stack pointer, and save registers. |
| 842 | |
| 843 | Be careful, however, and if it doesn't look like a prologue, |
| 844 | don't try to scan it. If, for instance, a frameless function |
| 845 | begins with stmfd sp!, then we will tell ourselves there is |
| 846 | a frame, which will confuse stack traceback, as well as "finish" |
| 847 | and other operations that rely on a knowledge of the stack |
| 848 | traceback. |
| 849 | |
| 850 | In the APCS, the prologue should start with "mov ip, sp" so |
| 851 | if we don't see this as the first insn, we will stop. |
| 852 | |
| 853 | [Note: This doesn't seem to be true any longer, so it's now an |
| 854 | optional part of the prologue. - Kevin Buettner, 2001-11-20] |
| 855 | |
| 856 | [Note further: The "mov ip,sp" only seems to be missing in |
| 857 | frameless functions at optimization level "-O2" or above, |
| 858 | in which case it is often (but not always) replaced by |
| 859 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
| 860 | |
| 861 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
| 862 | regs[regno] = pv_register (regno, 0); |
| 863 | stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
| 864 | back_to = make_cleanup_free_pv_area (stack); |
| 865 | |
| 866 | for (current_pc = prologue_start; |
| 867 | current_pc < prologue_end; |
| 868 | current_pc += 4) |
| 869 | { |
| 870 | unsigned int insn |
| 871 | = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code); |
| 872 | |
| 873 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
| 874 | { |
| 875 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
| 876 | continue; |
| 877 | } |
| 878 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
| 879 | { |
| 880 | unsigned imm = insn & 0xff; /* immediate value */ |
| 881 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 882 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 883 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm); |
| 884 | continue; |
| 885 | } |
| 886 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ |
| 887 | { |
| 888 | unsigned imm = insn & 0xff; /* immediate value */ |
| 889 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 890 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 891 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
| 892 | continue; |
| 893 | } |
| 894 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 895 | { |
| 896 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 897 | break; |
| 898 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); |
| 899 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]); |
| 900 | continue; |
| 901 | } |
| 902 | else if ((insn & 0xffff0000) == 0xe92d0000) |
| 903 | /* stmfd sp!, {..., fp, ip, lr, pc} |
| 904 | or |
| 905 | stmfd sp!, {a1, a2, a3, a4} */ |
| 906 | { |
| 907 | int mask = insn & 0xffff; |
| 908 | |
| 909 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 910 | break; |
| 911 | |
| 912 | /* Calculate offsets of saved registers. */ |
| 913 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
| 914 | if (mask & (1 << regno)) |
| 915 | { |
| 916 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); |
| 917 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); |
| 918 | } |
| 919 | } |
| 920 | else if ((insn & 0xffffc000) == 0xe54b0000 /* strb rx,[r11,#-n] */ |
| 921 | || (insn & 0xffffc0f0) == 0xe14b00b0 /* strh rx,[r11,#-n] */ |
| 922 | || (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
| 923 | { |
| 924 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 925 | continue; |
| 926 | } |
| 927 | else if ((insn & 0xffffc000) == 0xe5cd0000 /* strb rx,[sp,#n] */ |
| 928 | || (insn & 0xffffc0f0) == 0xe1cd00b0 /* strh rx,[sp,#n] */ |
| 929 | || (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
| 930 | { |
| 931 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 932 | continue; |
| 933 | } |
| 934 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
| 935 | { |
| 936 | unsigned imm = insn & 0xff; /* immediate value */ |
| 937 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 938 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 939 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
| 940 | } |
| 941 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ |
| 942 | { |
| 943 | unsigned imm = insn & 0xff; /* immediate value */ |
| 944 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 945 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 946 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
| 947 | } |
| 948 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ |
| 949 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
| 950 | { |
| 951 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 952 | break; |
| 953 | |
| 954 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
| 955 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
| 956 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); |
| 957 | } |
| 958 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ |
| 959 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
| 960 | { |
| 961 | int n_saved_fp_regs; |
| 962 | unsigned int fp_start_reg, fp_bound_reg; |
| 963 | |
| 964 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 965 | break; |
| 966 | |
| 967 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
| 968 | { |
| 969 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 970 | n_saved_fp_regs = 3; |
| 971 | else |
| 972 | n_saved_fp_regs = 1; |
| 973 | } |
| 974 | else |
| 975 | { |
| 976 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 977 | n_saved_fp_regs = 2; |
| 978 | else |
| 979 | n_saved_fp_regs = 4; |
| 980 | } |
| 981 | |
| 982 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
| 983 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
| 984 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) |
| 985 | { |
| 986 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
| 987 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, |
| 988 | regs[fp_start_reg++]); |
| 989 | } |
| 990 | } |
| 991 | else if ((insn & 0xf0000000) != 0xe0000000) |
| 992 | break; /* Condition not true, exit early */ |
| 993 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
| 994 | break; /* Don't scan past a block load */ |
| 995 | else |
| 996 | /* The optimizer might shove anything into the prologue, |
| 997 | so we just skip what we don't recognize. */ |
| 998 | continue; |
| 999 | } |
| 1000 | |
| 1001 | /* The frame size is just the distance from the frame register |
| 1002 | to the original stack pointer. */ |
| 1003 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
| 1004 | { |
| 1005 | /* Frame pointer is fp. */ |
| 1006 | cache->framereg = ARM_FP_REGNUM; |
| 1007 | cache->framesize = -regs[ARM_FP_REGNUM].k; |
| 1008 | } |
| 1009 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) |
| 1010 | { |
| 1011 | /* Try the stack pointer... this is a bit desperate. */ |
| 1012 | cache->framereg = ARM_SP_REGNUM; |
| 1013 | cache->framesize = -regs[ARM_SP_REGNUM].k; |
| 1014 | } |
| 1015 | else |
| 1016 | { |
| 1017 | /* We're just out of luck. We don't know where the frame is. */ |
| 1018 | cache->framereg = -1; |
| 1019 | cache->framesize = 0; |
| 1020 | } |
| 1021 | |
| 1022 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
| 1023 | if (pv_area_find_reg (stack, gdbarch, regno, &offset)) |
| 1024 | cache->saved_regs[regno].addr = offset; |
| 1025 | |
| 1026 | do_cleanups (back_to); |
| 1027 | } |
| 1028 | |
| 1029 | static struct arm_prologue_cache * |
| 1030 | arm_make_prologue_cache (struct frame_info *this_frame) |
| 1031 | { |
| 1032 | int reg; |
| 1033 | struct arm_prologue_cache *cache; |
| 1034 | CORE_ADDR unwound_fp; |
| 1035 | |
| 1036 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
| 1037 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1038 | |
| 1039 | arm_scan_prologue (this_frame, cache); |
| 1040 | |
| 1041 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
| 1042 | if (unwound_fp == 0) |
| 1043 | return cache; |
| 1044 | |
| 1045 | cache->prev_sp = unwound_fp + cache->framesize; |
| 1046 | |
| 1047 | /* Calculate actual addresses of saved registers using offsets |
| 1048 | determined by arm_scan_prologue. */ |
| 1049 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
| 1050 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
| 1051 | cache->saved_regs[reg].addr += cache->prev_sp; |
| 1052 | |
| 1053 | return cache; |
| 1054 | } |
| 1055 | |
| 1056 | /* Our frame ID for a normal frame is the current function's starting PC |
| 1057 | and the caller's SP when we were called. */ |
| 1058 | |
| 1059 | static void |
| 1060 | arm_prologue_this_id (struct frame_info *this_frame, |
| 1061 | void **this_cache, |
| 1062 | struct frame_id *this_id) |
| 1063 | { |
| 1064 | struct arm_prologue_cache *cache; |
| 1065 | struct frame_id id; |
| 1066 | CORE_ADDR pc, func; |
| 1067 | |
| 1068 | if (*this_cache == NULL) |
| 1069 | *this_cache = arm_make_prologue_cache (this_frame); |
| 1070 | cache = *this_cache; |
| 1071 | |
| 1072 | /* This is meant to halt the backtrace at "_start". */ |
| 1073 | pc = get_frame_pc (this_frame); |
| 1074 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) |
| 1075 | return; |
| 1076 | |
| 1077 | /* If we've hit a wall, stop. */ |
| 1078 | if (cache->prev_sp == 0) |
| 1079 | return; |
| 1080 | |
| 1081 | func = get_frame_func (this_frame); |
| 1082 | id = frame_id_build (cache->prev_sp, func); |
| 1083 | *this_id = id; |
| 1084 | } |
| 1085 | |
| 1086 | static struct value * |
| 1087 | arm_prologue_prev_register (struct frame_info *this_frame, |
| 1088 | void **this_cache, |
| 1089 | int prev_regnum) |
| 1090 | { |
| 1091 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1092 | struct arm_prologue_cache *cache; |
| 1093 | |
| 1094 | if (*this_cache == NULL) |
| 1095 | *this_cache = arm_make_prologue_cache (this_frame); |
| 1096 | cache = *this_cache; |
| 1097 | |
| 1098 | /* If we are asked to unwind the PC, then we need to return the LR |
| 1099 | instead. The prologue may save PC, but it will point into this |
| 1100 | frame's prologue, not the next frame's resume location. Also |
| 1101 | strip the saved T bit. A valid LR may have the low bit set, but |
| 1102 | a valid PC never does. */ |
| 1103 | if (prev_regnum == ARM_PC_REGNUM) |
| 1104 | { |
| 1105 | CORE_ADDR lr; |
| 1106 | |
| 1107 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
| 1108 | return frame_unwind_got_constant (this_frame, prev_regnum, |
| 1109 | arm_addr_bits_remove (gdbarch, lr)); |
| 1110 | } |
| 1111 | |
| 1112 | /* SP is generally not saved to the stack, but this frame is |
| 1113 | identified by the next frame's stack pointer at the time of the call. |
| 1114 | The value was already reconstructed into PREV_SP. */ |
| 1115 | if (prev_regnum == ARM_SP_REGNUM) |
| 1116 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
| 1117 | |
| 1118 | /* The CPSR may have been changed by the call instruction and by the |
| 1119 | called function. The only bit we can reconstruct is the T bit, |
| 1120 | by checking the low bit of LR as of the call. This is a reliable |
| 1121 | indicator of Thumb-ness except for some ARM v4T pre-interworking |
| 1122 | Thumb code, which could get away with a clear low bit as long as |
| 1123 | the called function did not use bx. Guess that all other |
| 1124 | bits are unchanged; the condition flags are presumably lost, |
| 1125 | but the processor status is likely valid. */ |
| 1126 | if (prev_regnum == ARM_PS_REGNUM) |
| 1127 | { |
| 1128 | CORE_ADDR lr, cpsr; |
| 1129 | |
| 1130 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); |
| 1131 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
| 1132 | if (IS_THUMB_ADDR (lr)) |
| 1133 | cpsr |= CPSR_T; |
| 1134 | else |
| 1135 | cpsr &= ~CPSR_T; |
| 1136 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
| 1137 | } |
| 1138 | |
| 1139 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
| 1140 | prev_regnum); |
| 1141 | } |
| 1142 | |
| 1143 | struct frame_unwind arm_prologue_unwind = { |
| 1144 | NORMAL_FRAME, |
| 1145 | arm_prologue_this_id, |
| 1146 | arm_prologue_prev_register, |
| 1147 | NULL, |
| 1148 | default_frame_sniffer |
| 1149 | }; |
| 1150 | |
| 1151 | static struct arm_prologue_cache * |
| 1152 | arm_make_stub_cache (struct frame_info *this_frame) |
| 1153 | { |
| 1154 | int reg; |
| 1155 | struct arm_prologue_cache *cache; |
| 1156 | CORE_ADDR unwound_fp; |
| 1157 | |
| 1158 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
| 1159 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1160 | |
| 1161 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
| 1162 | |
| 1163 | return cache; |
| 1164 | } |
| 1165 | |
| 1166 | /* Our frame ID for a stub frame is the current SP and LR. */ |
| 1167 | |
| 1168 | static void |
| 1169 | arm_stub_this_id (struct frame_info *this_frame, |
| 1170 | void **this_cache, |
| 1171 | struct frame_id *this_id) |
| 1172 | { |
| 1173 | struct arm_prologue_cache *cache; |
| 1174 | |
| 1175 | if (*this_cache == NULL) |
| 1176 | *this_cache = arm_make_stub_cache (this_frame); |
| 1177 | cache = *this_cache; |
| 1178 | |
| 1179 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
| 1180 | } |
| 1181 | |
| 1182 | static int |
| 1183 | arm_stub_unwind_sniffer (const struct frame_unwind *self, |
| 1184 | struct frame_info *this_frame, |
| 1185 | void **this_prologue_cache) |
| 1186 | { |
| 1187 | CORE_ADDR addr_in_block; |
| 1188 | char dummy[4]; |
| 1189 | |
| 1190 | addr_in_block = get_frame_address_in_block (this_frame); |
| 1191 | if (in_plt_section (addr_in_block, NULL) |
| 1192 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
| 1193 | return 1; |
| 1194 | |
| 1195 | return 0; |
| 1196 | } |
| 1197 | |
| 1198 | struct frame_unwind arm_stub_unwind = { |
| 1199 | NORMAL_FRAME, |
| 1200 | arm_stub_this_id, |
| 1201 | arm_prologue_prev_register, |
| 1202 | NULL, |
| 1203 | arm_stub_unwind_sniffer |
| 1204 | }; |
| 1205 | |
| 1206 | static CORE_ADDR |
| 1207 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
| 1208 | { |
| 1209 | struct arm_prologue_cache *cache; |
| 1210 | |
| 1211 | if (*this_cache == NULL) |
| 1212 | *this_cache = arm_make_prologue_cache (this_frame); |
| 1213 | cache = *this_cache; |
| 1214 | |
| 1215 | return cache->prev_sp - cache->framesize; |
| 1216 | } |
| 1217 | |
| 1218 | struct frame_base arm_normal_base = { |
| 1219 | &arm_prologue_unwind, |
| 1220 | arm_normal_frame_base, |
| 1221 | arm_normal_frame_base, |
| 1222 | arm_normal_frame_base |
| 1223 | }; |
| 1224 | |
| 1225 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
| 1226 | dummy frame. The frame ID's base needs to match the TOS value |
| 1227 | saved by save_dummy_frame_tos() and returned from |
| 1228 | arm_push_dummy_call, and the PC needs to match the dummy frame's |
| 1229 | breakpoint. */ |
| 1230 | |
| 1231 | static struct frame_id |
| 1232 | arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1233 | { |
| 1234 | return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM), |
| 1235 | get_frame_pc (this_frame)); |
| 1236 | } |
| 1237 | |
| 1238 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
| 1239 | be used to construct the previous frame's ID, after looking up the |
| 1240 | containing function). */ |
| 1241 | |
| 1242 | static CORE_ADDR |
| 1243 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1244 | { |
| 1245 | CORE_ADDR pc; |
| 1246 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); |
| 1247 | return arm_addr_bits_remove (gdbarch, pc); |
| 1248 | } |
| 1249 | |
| 1250 | static CORE_ADDR |
| 1251 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1252 | { |
| 1253 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); |
| 1254 | } |
| 1255 | |
| 1256 | static struct value * |
| 1257 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, |
| 1258 | int regnum) |
| 1259 | { |
| 1260 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
| 1261 | CORE_ADDR lr, cpsr; |
| 1262 | |
| 1263 | switch (regnum) |
| 1264 | { |
| 1265 | case ARM_PC_REGNUM: |
| 1266 | /* The PC is normally copied from the return column, which |
| 1267 | describes saves of LR. However, that version may have an |
| 1268 | extra bit set to indicate Thumb state. The bit is not |
| 1269 | part of the PC. */ |
| 1270 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
| 1271 | return frame_unwind_got_constant (this_frame, regnum, |
| 1272 | arm_addr_bits_remove (gdbarch, lr)); |
| 1273 | |
| 1274 | case ARM_PS_REGNUM: |
| 1275 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ |
| 1276 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
| 1277 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
| 1278 | if (IS_THUMB_ADDR (lr)) |
| 1279 | cpsr |= CPSR_T; |
| 1280 | else |
| 1281 | cpsr &= ~CPSR_T; |
| 1282 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
| 1283 | |
| 1284 | default: |
| 1285 | internal_error (__FILE__, __LINE__, |
| 1286 | _("Unexpected register %d"), regnum); |
| 1287 | } |
| 1288 | } |
| 1289 | |
| 1290 | static void |
| 1291 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, |
| 1292 | struct dwarf2_frame_state_reg *reg, |
| 1293 | struct frame_info *this_frame) |
| 1294 | { |
| 1295 | switch (regnum) |
| 1296 | { |
| 1297 | case ARM_PC_REGNUM: |
| 1298 | case ARM_PS_REGNUM: |
| 1299 | reg->how = DWARF2_FRAME_REG_FN; |
| 1300 | reg->loc.fn = arm_dwarf2_prev_register; |
| 1301 | break; |
| 1302 | case ARM_SP_REGNUM: |
| 1303 | reg->how = DWARF2_FRAME_REG_CFA; |
| 1304 | break; |
| 1305 | } |
| 1306 | } |
| 1307 | |
| 1308 | /* When arguments must be pushed onto the stack, they go on in reverse |
| 1309 | order. The code below implements a FILO (stack) to do this. */ |
| 1310 | |
| 1311 | struct stack_item |
| 1312 | { |
| 1313 | int len; |
| 1314 | struct stack_item *prev; |
| 1315 | void *data; |
| 1316 | }; |
| 1317 | |
| 1318 | static struct stack_item * |
| 1319 | push_stack_item (struct stack_item *prev, void *contents, int len) |
| 1320 | { |
| 1321 | struct stack_item *si; |
| 1322 | si = xmalloc (sizeof (struct stack_item)); |
| 1323 | si->data = xmalloc (len); |
| 1324 | si->len = len; |
| 1325 | si->prev = prev; |
| 1326 | memcpy (si->data, contents, len); |
| 1327 | return si; |
| 1328 | } |
| 1329 | |
| 1330 | static struct stack_item * |
| 1331 | pop_stack_item (struct stack_item *si) |
| 1332 | { |
| 1333 | struct stack_item *dead = si; |
| 1334 | si = si->prev; |
| 1335 | xfree (dead->data); |
| 1336 | xfree (dead); |
| 1337 | return si; |
| 1338 | } |
| 1339 | |
| 1340 | |
| 1341 | /* Return the alignment (in bytes) of the given type. */ |
| 1342 | |
| 1343 | static int |
| 1344 | arm_type_align (struct type *t) |
| 1345 | { |
| 1346 | int n; |
| 1347 | int align; |
| 1348 | int falign; |
| 1349 | |
| 1350 | t = check_typedef (t); |
| 1351 | switch (TYPE_CODE (t)) |
| 1352 | { |
| 1353 | default: |
| 1354 | /* Should never happen. */ |
| 1355 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); |
| 1356 | return 4; |
| 1357 | |
| 1358 | case TYPE_CODE_PTR: |
| 1359 | case TYPE_CODE_ENUM: |
| 1360 | case TYPE_CODE_INT: |
| 1361 | case TYPE_CODE_FLT: |
| 1362 | case TYPE_CODE_SET: |
| 1363 | case TYPE_CODE_RANGE: |
| 1364 | case TYPE_CODE_BITSTRING: |
| 1365 | case TYPE_CODE_REF: |
| 1366 | case TYPE_CODE_CHAR: |
| 1367 | case TYPE_CODE_BOOL: |
| 1368 | return TYPE_LENGTH (t); |
| 1369 | |
| 1370 | case TYPE_CODE_ARRAY: |
| 1371 | case TYPE_CODE_COMPLEX: |
| 1372 | /* TODO: What about vector types? */ |
| 1373 | return arm_type_align (TYPE_TARGET_TYPE (t)); |
| 1374 | |
| 1375 | case TYPE_CODE_STRUCT: |
| 1376 | case TYPE_CODE_UNION: |
| 1377 | align = 1; |
| 1378 | for (n = 0; n < TYPE_NFIELDS (t); n++) |
| 1379 | { |
| 1380 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); |
| 1381 | if (falign > align) |
| 1382 | align = falign; |
| 1383 | } |
| 1384 | return align; |
| 1385 | } |
| 1386 | } |
| 1387 | |
| 1388 | /* Possible base types for a candidate for passing and returning in |
| 1389 | VFP registers. */ |
| 1390 | |
| 1391 | enum arm_vfp_cprc_base_type |
| 1392 | { |
| 1393 | VFP_CPRC_UNKNOWN, |
| 1394 | VFP_CPRC_SINGLE, |
| 1395 | VFP_CPRC_DOUBLE, |
| 1396 | VFP_CPRC_VEC64, |
| 1397 | VFP_CPRC_VEC128 |
| 1398 | }; |
| 1399 | |
| 1400 | /* The length of one element of base type B. */ |
| 1401 | |
| 1402 | static unsigned |
| 1403 | arm_vfp_cprc_unit_length (enum arm_vfp_cprc_base_type b) |
| 1404 | { |
| 1405 | switch (b) |
| 1406 | { |
| 1407 | case VFP_CPRC_SINGLE: |
| 1408 | return 4; |
| 1409 | case VFP_CPRC_DOUBLE: |
| 1410 | return 8; |
| 1411 | case VFP_CPRC_VEC64: |
| 1412 | return 8; |
| 1413 | case VFP_CPRC_VEC128: |
| 1414 | return 16; |
| 1415 | default: |
| 1416 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), |
| 1417 | (int) b); |
| 1418 | } |
| 1419 | } |
| 1420 | |
| 1421 | /* The character ('s', 'd' or 'q') for the type of VFP register used |
| 1422 | for passing base type B. */ |
| 1423 | |
| 1424 | static int |
| 1425 | arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) |
| 1426 | { |
| 1427 | switch (b) |
| 1428 | { |
| 1429 | case VFP_CPRC_SINGLE: |
| 1430 | return 's'; |
| 1431 | case VFP_CPRC_DOUBLE: |
| 1432 | return 'd'; |
| 1433 | case VFP_CPRC_VEC64: |
| 1434 | return 'd'; |
| 1435 | case VFP_CPRC_VEC128: |
| 1436 | return 'q'; |
| 1437 | default: |
| 1438 | internal_error (__FILE__, __LINE__, _("Invalid VFP CPRC type: %d."), |
| 1439 | (int) b); |
| 1440 | } |
| 1441 | } |
| 1442 | |
| 1443 | /* Determine whether T may be part of a candidate for passing and |
| 1444 | returning in VFP registers, ignoring the limit on the total number |
| 1445 | of components. If *BASE_TYPE is VFP_CPRC_UNKNOWN, set it to the |
| 1446 | classification of the first valid component found; if it is not |
| 1447 | VFP_CPRC_UNKNOWN, all components must have the same classification |
| 1448 | as *BASE_TYPE. If it is found that T contains a type not permitted |
| 1449 | for passing and returning in VFP registers, a type differently |
| 1450 | classified from *BASE_TYPE, or two types differently classified |
| 1451 | from each other, return -1, otherwise return the total number of |
| 1452 | base-type elements found (possibly 0 in an empty structure or |
| 1453 | array). Vectors and complex types are not currently supported, |
| 1454 | matching the generic AAPCS support. */ |
| 1455 | |
| 1456 | static int |
| 1457 | arm_vfp_cprc_sub_candidate (struct type *t, |
| 1458 | enum arm_vfp_cprc_base_type *base_type) |
| 1459 | { |
| 1460 | t = check_typedef (t); |
| 1461 | switch (TYPE_CODE (t)) |
| 1462 | { |
| 1463 | case TYPE_CODE_FLT: |
| 1464 | switch (TYPE_LENGTH (t)) |
| 1465 | { |
| 1466 | case 4: |
| 1467 | if (*base_type == VFP_CPRC_UNKNOWN) |
| 1468 | *base_type = VFP_CPRC_SINGLE; |
| 1469 | else if (*base_type != VFP_CPRC_SINGLE) |
| 1470 | return -1; |
| 1471 | return 1; |
| 1472 | |
| 1473 | case 8: |
| 1474 | if (*base_type == VFP_CPRC_UNKNOWN) |
| 1475 | *base_type = VFP_CPRC_DOUBLE; |
| 1476 | else if (*base_type != VFP_CPRC_DOUBLE) |
| 1477 | return -1; |
| 1478 | return 1; |
| 1479 | |
| 1480 | default: |
| 1481 | return -1; |
| 1482 | } |
| 1483 | break; |
| 1484 | |
| 1485 | case TYPE_CODE_ARRAY: |
| 1486 | { |
| 1487 | int count; |
| 1488 | unsigned unitlen; |
| 1489 | count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type); |
| 1490 | if (count == -1) |
| 1491 | return -1; |
| 1492 | if (TYPE_LENGTH (t) == 0) |
| 1493 | { |
| 1494 | gdb_assert (count == 0); |
| 1495 | return 0; |
| 1496 | } |
| 1497 | else if (count == 0) |
| 1498 | return -1; |
| 1499 | unitlen = arm_vfp_cprc_unit_length (*base_type); |
| 1500 | gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); |
| 1501 | return TYPE_LENGTH (t) / unitlen; |
| 1502 | } |
| 1503 | break; |
| 1504 | |
| 1505 | case TYPE_CODE_STRUCT: |
| 1506 | { |
| 1507 | int count = 0; |
| 1508 | unsigned unitlen; |
| 1509 | int i; |
| 1510 | for (i = 0; i < TYPE_NFIELDS (t); i++) |
| 1511 | { |
| 1512 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), |
| 1513 | base_type); |
| 1514 | if (sub_count == -1) |
| 1515 | return -1; |
| 1516 | count += sub_count; |
| 1517 | } |
| 1518 | if (TYPE_LENGTH (t) == 0) |
| 1519 | { |
| 1520 | gdb_assert (count == 0); |
| 1521 | return 0; |
| 1522 | } |
| 1523 | else if (count == 0) |
| 1524 | return -1; |
| 1525 | unitlen = arm_vfp_cprc_unit_length (*base_type); |
| 1526 | if (TYPE_LENGTH (t) != unitlen * count) |
| 1527 | return -1; |
| 1528 | return count; |
| 1529 | } |
| 1530 | |
| 1531 | case TYPE_CODE_UNION: |
| 1532 | { |
| 1533 | int count = 0; |
| 1534 | unsigned unitlen; |
| 1535 | int i; |
| 1536 | for (i = 0; i < TYPE_NFIELDS (t); i++) |
| 1537 | { |
| 1538 | int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), |
| 1539 | base_type); |
| 1540 | if (sub_count == -1) |
| 1541 | return -1; |
| 1542 | count = (count > sub_count ? count : sub_count); |
| 1543 | } |
| 1544 | if (TYPE_LENGTH (t) == 0) |
| 1545 | { |
| 1546 | gdb_assert (count == 0); |
| 1547 | return 0; |
| 1548 | } |
| 1549 | else if (count == 0) |
| 1550 | return -1; |
| 1551 | unitlen = arm_vfp_cprc_unit_length (*base_type); |
| 1552 | if (TYPE_LENGTH (t) != unitlen * count) |
| 1553 | return -1; |
| 1554 | return count; |
| 1555 | } |
| 1556 | |
| 1557 | default: |
| 1558 | break; |
| 1559 | } |
| 1560 | |
| 1561 | return -1; |
| 1562 | } |
| 1563 | |
| 1564 | /* Determine whether T is a VFP co-processor register candidate (CPRC) |
| 1565 | if passed to or returned from a non-variadic function with the VFP |
| 1566 | ABI in effect. Return 1 if it is, 0 otherwise. If it is, set |
| 1567 | *BASE_TYPE to the base type for T and *COUNT to the number of |
| 1568 | elements of that base type before returning. */ |
| 1569 | |
| 1570 | static int |
| 1571 | arm_vfp_call_candidate (struct type *t, enum arm_vfp_cprc_base_type *base_type, |
| 1572 | int *count) |
| 1573 | { |
| 1574 | enum arm_vfp_cprc_base_type b = VFP_CPRC_UNKNOWN; |
| 1575 | int c = arm_vfp_cprc_sub_candidate (t, &b); |
| 1576 | if (c <= 0 || c > 4) |
| 1577 | return 0; |
| 1578 | *base_type = b; |
| 1579 | *count = c; |
| 1580 | return 1; |
| 1581 | } |
| 1582 | |
| 1583 | /* Return 1 if the VFP ABI should be used for passing arguments to and |
| 1584 | returning values from a function of type FUNC_TYPE, 0 |
| 1585 | otherwise. */ |
| 1586 | |
| 1587 | static int |
| 1588 | arm_vfp_abi_for_function (struct gdbarch *gdbarch, struct type *func_type) |
| 1589 | { |
| 1590 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1591 | /* Variadic functions always use the base ABI. Assume that functions |
| 1592 | without debug info are not variadic. */ |
| 1593 | if (func_type && TYPE_VARARGS (check_typedef (func_type))) |
| 1594 | return 0; |
| 1595 | /* The VFP ABI is only supported as a variant of AAPCS. */ |
| 1596 | if (tdep->arm_abi != ARM_ABI_AAPCS) |
| 1597 | return 0; |
| 1598 | return gdbarch_tdep (gdbarch)->fp_model == ARM_FLOAT_VFP; |
| 1599 | } |
| 1600 | |
| 1601 | /* We currently only support passing parameters in integer registers, which |
| 1602 | conforms with GCC's default model, and VFP argument passing following |
| 1603 | the VFP variant of AAPCS. Several other variants exist and |
| 1604 | we should probably support some of them based on the selected ABI. */ |
| 1605 | |
| 1606 | static CORE_ADDR |
| 1607 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1608 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
| 1609 | struct value **args, CORE_ADDR sp, int struct_return, |
| 1610 | CORE_ADDR struct_addr) |
| 1611 | { |
| 1612 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1613 | int argnum; |
| 1614 | int argreg; |
| 1615 | int nstack; |
| 1616 | struct stack_item *si = NULL; |
| 1617 | int use_vfp_abi; |
| 1618 | struct type *ftype; |
| 1619 | unsigned vfp_regs_free = (1 << 16) - 1; |
| 1620 | |
| 1621 | /* Determine the type of this function and whether the VFP ABI |
| 1622 | applies. */ |
| 1623 | ftype = check_typedef (value_type (function)); |
| 1624 | if (TYPE_CODE (ftype) == TYPE_CODE_PTR) |
| 1625 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); |
| 1626 | use_vfp_abi = arm_vfp_abi_for_function (gdbarch, ftype); |
| 1627 | |
| 1628 | /* Set the return address. For the ARM, the return breakpoint is |
| 1629 | always at BP_ADDR. */ |
| 1630 | if (arm_pc_is_thumb (bp_addr)) |
| 1631 | bp_addr |= 1; |
| 1632 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
| 1633 | |
| 1634 | /* Walk through the list of args and determine how large a temporary |
| 1635 | stack is required. Need to take care here as structs may be |
| 1636 | passed on the stack, and we have to to push them. */ |
| 1637 | nstack = 0; |
| 1638 | |
| 1639 | argreg = ARM_A1_REGNUM; |
| 1640 | nstack = 0; |
| 1641 | |
| 1642 | /* The struct_return pointer occupies the first parameter |
| 1643 | passing register. */ |
| 1644 | if (struct_return) |
| 1645 | { |
| 1646 | if (arm_debug) |
| 1647 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n", |
| 1648 | gdbarch_register_name (gdbarch, argreg), |
| 1649 | paddress (gdbarch, struct_addr)); |
| 1650 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
| 1651 | argreg++; |
| 1652 | } |
| 1653 | |
| 1654 | for (argnum = 0; argnum < nargs; argnum++) |
| 1655 | { |
| 1656 | int len; |
| 1657 | struct type *arg_type; |
| 1658 | struct type *target_type; |
| 1659 | enum type_code typecode; |
| 1660 | bfd_byte *val; |
| 1661 | int align; |
| 1662 | enum arm_vfp_cprc_base_type vfp_base_type; |
| 1663 | int vfp_base_count; |
| 1664 | int may_use_core_reg = 1; |
| 1665 | |
| 1666 | arg_type = check_typedef (value_type (args[argnum])); |
| 1667 | len = TYPE_LENGTH (arg_type); |
| 1668 | target_type = TYPE_TARGET_TYPE (arg_type); |
| 1669 | typecode = TYPE_CODE (arg_type); |
| 1670 | val = value_contents_writeable (args[argnum]); |
| 1671 | |
| 1672 | align = arm_type_align (arg_type); |
| 1673 | /* Round alignment up to a whole number of words. */ |
| 1674 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); |
| 1675 | /* Different ABIs have different maximum alignments. */ |
| 1676 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) |
| 1677 | { |
| 1678 | /* The APCS ABI only requires word alignment. */ |
| 1679 | align = INT_REGISTER_SIZE; |
| 1680 | } |
| 1681 | else |
| 1682 | { |
| 1683 | /* The AAPCS requires at most doubleword alignment. */ |
| 1684 | if (align > INT_REGISTER_SIZE * 2) |
| 1685 | align = INT_REGISTER_SIZE * 2; |
| 1686 | } |
| 1687 | |
| 1688 | if (use_vfp_abi |
| 1689 | && arm_vfp_call_candidate (arg_type, &vfp_base_type, |
| 1690 | &vfp_base_count)) |
| 1691 | { |
| 1692 | int regno; |
| 1693 | int unit_length; |
| 1694 | int shift; |
| 1695 | unsigned mask; |
| 1696 | |
| 1697 | /* Because this is a CPRC it cannot go in a core register or |
| 1698 | cause a core register to be skipped for alignment. |
| 1699 | Either it goes in VFP registers and the rest of this loop |
| 1700 | iteration is skipped for this argument, or it goes on the |
| 1701 | stack (and the stack alignment code is correct for this |
| 1702 | case). */ |
| 1703 | may_use_core_reg = 0; |
| 1704 | |
| 1705 | unit_length = arm_vfp_cprc_unit_length (vfp_base_type); |
| 1706 | shift = unit_length / 4; |
| 1707 | mask = (1 << (shift * vfp_base_count)) - 1; |
| 1708 | for (regno = 0; regno < 16; regno += shift) |
| 1709 | if (((vfp_regs_free >> regno) & mask) == mask) |
| 1710 | break; |
| 1711 | |
| 1712 | if (regno < 16) |
| 1713 | { |
| 1714 | int reg_char; |
| 1715 | int reg_scaled; |
| 1716 | int i; |
| 1717 | |
| 1718 | vfp_regs_free &= ~(mask << regno); |
| 1719 | reg_scaled = regno / shift; |
| 1720 | reg_char = arm_vfp_cprc_reg_char (vfp_base_type); |
| 1721 | for (i = 0; i < vfp_base_count; i++) |
| 1722 | { |
| 1723 | char name_buf[4]; |
| 1724 | int regnum; |
| 1725 | if (reg_char == 'q') |
| 1726 | arm_neon_quad_write (gdbarch, regcache, reg_scaled + i, |
| 1727 | val + i * unit_length); |
| 1728 | else |
| 1729 | { |
| 1730 | sprintf (name_buf, "%c%d", reg_char, reg_scaled + i); |
| 1731 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
| 1732 | strlen (name_buf)); |
| 1733 | regcache_cooked_write (regcache, regnum, |
| 1734 | val + i * unit_length); |
| 1735 | } |
| 1736 | } |
| 1737 | continue; |
| 1738 | } |
| 1739 | else |
| 1740 | { |
| 1741 | /* This CPRC could not go in VFP registers, so all VFP |
| 1742 | registers are now marked as used. */ |
| 1743 | vfp_regs_free = 0; |
| 1744 | } |
| 1745 | } |
| 1746 | |
| 1747 | /* Push stack padding for dowubleword alignment. */ |
| 1748 | if (nstack & (align - 1)) |
| 1749 | { |
| 1750 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
| 1751 | nstack += INT_REGISTER_SIZE; |
| 1752 | } |
| 1753 | |
| 1754 | /* Doubleword aligned quantities must go in even register pairs. */ |
| 1755 | if (may_use_core_reg |
| 1756 | && argreg <= ARM_LAST_ARG_REGNUM |
| 1757 | && align > INT_REGISTER_SIZE |
| 1758 | && argreg & 1) |
| 1759 | argreg++; |
| 1760 | |
| 1761 | /* If the argument is a pointer to a function, and it is a |
| 1762 | Thumb function, create a LOCAL copy of the value and set |
| 1763 | the THUMB bit in it. */ |
| 1764 | if (TYPE_CODE_PTR == typecode |
| 1765 | && target_type != NULL |
| 1766 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) |
| 1767 | { |
| 1768 | CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); |
| 1769 | if (arm_pc_is_thumb (regval)) |
| 1770 | { |
| 1771 | val = alloca (len); |
| 1772 | store_unsigned_integer (val, len, byte_order, |
| 1773 | MAKE_THUMB_ADDR (regval)); |
| 1774 | } |
| 1775 | } |
| 1776 | |
| 1777 | /* Copy the argument to general registers or the stack in |
| 1778 | register-sized pieces. Large arguments are split between |
| 1779 | registers and stack. */ |
| 1780 | while (len > 0) |
| 1781 | { |
| 1782 | int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; |
| 1783 | |
| 1784 | if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) |
| 1785 | { |
| 1786 | /* The argument is being passed in a general purpose |
| 1787 | register. */ |
| 1788 | CORE_ADDR regval |
| 1789 | = extract_unsigned_integer (val, partial_len, byte_order); |
| 1790 | if (byte_order == BFD_ENDIAN_BIG) |
| 1791 | regval <<= (INT_REGISTER_SIZE - partial_len) * 8; |
| 1792 | if (arm_debug) |
| 1793 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", |
| 1794 | argnum, |
| 1795 | gdbarch_register_name |
| 1796 | (gdbarch, argreg), |
| 1797 | phex (regval, INT_REGISTER_SIZE)); |
| 1798 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 1799 | argreg++; |
| 1800 | } |
| 1801 | else |
| 1802 | { |
| 1803 | /* Push the arguments onto the stack. */ |
| 1804 | if (arm_debug) |
| 1805 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", |
| 1806 | argnum, nstack); |
| 1807 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
| 1808 | nstack += INT_REGISTER_SIZE; |
| 1809 | } |
| 1810 | |
| 1811 | len -= partial_len; |
| 1812 | val += partial_len; |
| 1813 | } |
| 1814 | } |
| 1815 | /* If we have an odd number of words to push, then decrement the stack |
| 1816 | by one word now, so first stack argument will be dword aligned. */ |
| 1817 | if (nstack & 4) |
| 1818 | sp -= 4; |
| 1819 | |
| 1820 | while (si) |
| 1821 | { |
| 1822 | sp -= si->len; |
| 1823 | write_memory (sp, si->data, si->len); |
| 1824 | si = pop_stack_item (si); |
| 1825 | } |
| 1826 | |
| 1827 | /* Finally, update teh SP register. */ |
| 1828 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); |
| 1829 | |
| 1830 | return sp; |
| 1831 | } |
| 1832 | |
| 1833 | |
| 1834 | /* Always align the frame to an 8-byte boundary. This is required on |
| 1835 | some platforms and harmless on the rest. */ |
| 1836 | |
| 1837 | static CORE_ADDR |
| 1838 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 1839 | { |
| 1840 | /* Align the stack to eight bytes. */ |
| 1841 | return sp & ~ (CORE_ADDR) 7; |
| 1842 | } |
| 1843 | |
| 1844 | static void |
| 1845 | print_fpu_flags (int flags) |
| 1846 | { |
| 1847 | if (flags & (1 << 0)) |
| 1848 | fputs ("IVO ", stdout); |
| 1849 | if (flags & (1 << 1)) |
| 1850 | fputs ("DVZ ", stdout); |
| 1851 | if (flags & (1 << 2)) |
| 1852 | fputs ("OFL ", stdout); |
| 1853 | if (flags & (1 << 3)) |
| 1854 | fputs ("UFL ", stdout); |
| 1855 | if (flags & (1 << 4)) |
| 1856 | fputs ("INX ", stdout); |
| 1857 | putchar ('\n'); |
| 1858 | } |
| 1859 | |
| 1860 | /* Print interesting information about the floating point processor |
| 1861 | (if present) or emulator. */ |
| 1862 | static void |
| 1863 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 1864 | struct frame_info *frame, const char *args) |
| 1865 | { |
| 1866 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
| 1867 | int type; |
| 1868 | |
| 1869 | type = (status >> 24) & 127; |
| 1870 | if (status & (1 << 31)) |
| 1871 | printf (_("Hardware FPU type %d\n"), type); |
| 1872 | else |
| 1873 | printf (_("Software FPU type %d\n"), type); |
| 1874 | /* i18n: [floating point unit] mask */ |
| 1875 | fputs (_("mask: "), stdout); |
| 1876 | print_fpu_flags (status >> 16); |
| 1877 | /* i18n: [floating point unit] flags */ |
| 1878 | fputs (_("flags: "), stdout); |
| 1879 | print_fpu_flags (status); |
| 1880 | } |
| 1881 | |
| 1882 | /* Construct the ARM extended floating point type. */ |
| 1883 | static struct type * |
| 1884 | arm_ext_type (struct gdbarch *gdbarch) |
| 1885 | { |
| 1886 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1887 | |
| 1888 | if (!tdep->arm_ext_type) |
| 1889 | tdep->arm_ext_type |
| 1890 | = arch_float_type (gdbarch, -1, "builtin_type_arm_ext", |
| 1891 | floatformats_arm_ext); |
| 1892 | |
| 1893 | return tdep->arm_ext_type; |
| 1894 | } |
| 1895 | |
| 1896 | static struct type * |
| 1897 | arm_neon_double_type (struct gdbarch *gdbarch) |
| 1898 | { |
| 1899 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1900 | |
| 1901 | if (tdep->neon_double_type == NULL) |
| 1902 | { |
| 1903 | struct type *t, *elem; |
| 1904 | |
| 1905 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_d", |
| 1906 | TYPE_CODE_UNION); |
| 1907 | elem = builtin_type (gdbarch)->builtin_uint8; |
| 1908 | append_composite_type_field (t, "u8", init_vector_type (elem, 8)); |
| 1909 | elem = builtin_type (gdbarch)->builtin_uint16; |
| 1910 | append_composite_type_field (t, "u16", init_vector_type (elem, 4)); |
| 1911 | elem = builtin_type (gdbarch)->builtin_uint32; |
| 1912 | append_composite_type_field (t, "u32", init_vector_type (elem, 2)); |
| 1913 | elem = builtin_type (gdbarch)->builtin_uint64; |
| 1914 | append_composite_type_field (t, "u64", elem); |
| 1915 | elem = builtin_type (gdbarch)->builtin_float; |
| 1916 | append_composite_type_field (t, "f32", init_vector_type (elem, 2)); |
| 1917 | elem = builtin_type (gdbarch)->builtin_double; |
| 1918 | append_composite_type_field (t, "f64", elem); |
| 1919 | |
| 1920 | TYPE_VECTOR (t) = 1; |
| 1921 | TYPE_NAME (t) = "neon_d"; |
| 1922 | tdep->neon_double_type = t; |
| 1923 | } |
| 1924 | |
| 1925 | return tdep->neon_double_type; |
| 1926 | } |
| 1927 | |
| 1928 | /* FIXME: The vector types are not correctly ordered on big-endian |
| 1929 | targets. Just as s0 is the low bits of d0, d0[0] is also the low |
| 1930 | bits of d0 - regardless of what unit size is being held in d0. So |
| 1931 | the offset of the first uint8 in d0 is 7, but the offset of the |
| 1932 | first float is 4. This code works as-is for little-endian |
| 1933 | targets. */ |
| 1934 | |
| 1935 | static struct type * |
| 1936 | arm_neon_quad_type (struct gdbarch *gdbarch) |
| 1937 | { |
| 1938 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1939 | |
| 1940 | if (tdep->neon_quad_type == NULL) |
| 1941 | { |
| 1942 | struct type *t, *elem; |
| 1943 | |
| 1944 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_neon_q", |
| 1945 | TYPE_CODE_UNION); |
| 1946 | elem = builtin_type (gdbarch)->builtin_uint8; |
| 1947 | append_composite_type_field (t, "u8", init_vector_type (elem, 16)); |
| 1948 | elem = builtin_type (gdbarch)->builtin_uint16; |
| 1949 | append_composite_type_field (t, "u16", init_vector_type (elem, 8)); |
| 1950 | elem = builtin_type (gdbarch)->builtin_uint32; |
| 1951 | append_composite_type_field (t, "u32", init_vector_type (elem, 4)); |
| 1952 | elem = builtin_type (gdbarch)->builtin_uint64; |
| 1953 | append_composite_type_field (t, "u64", init_vector_type (elem, 2)); |
| 1954 | elem = builtin_type (gdbarch)->builtin_float; |
| 1955 | append_composite_type_field (t, "f32", init_vector_type (elem, 4)); |
| 1956 | elem = builtin_type (gdbarch)->builtin_double; |
| 1957 | append_composite_type_field (t, "f64", init_vector_type (elem, 2)); |
| 1958 | |
| 1959 | TYPE_VECTOR (t) = 1; |
| 1960 | TYPE_NAME (t) = "neon_q"; |
| 1961 | tdep->neon_quad_type = t; |
| 1962 | } |
| 1963 | |
| 1964 | return tdep->neon_quad_type; |
| 1965 | } |
| 1966 | |
| 1967 | /* Return the GDB type object for the "standard" data type of data in |
| 1968 | register N. */ |
| 1969 | |
| 1970 | static struct type * |
| 1971 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
| 1972 | { |
| 1973 | int num_regs = gdbarch_num_regs (gdbarch); |
| 1974 | |
| 1975 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos |
| 1976 | && regnum >= num_regs && regnum < num_regs + 32) |
| 1977 | return builtin_type (gdbarch)->builtin_float; |
| 1978 | |
| 1979 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos |
| 1980 | && regnum >= num_regs + 32 && regnum < num_regs + 32 + 16) |
| 1981 | return arm_neon_quad_type (gdbarch); |
| 1982 | |
| 1983 | /* If the target description has register information, we are only |
| 1984 | in this function so that we can override the types of |
| 1985 | double-precision registers for NEON. */ |
| 1986 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
| 1987 | { |
| 1988 | struct type *t = tdesc_register_type (gdbarch, regnum); |
| 1989 | |
| 1990 | if (regnum >= ARM_D0_REGNUM && regnum < ARM_D0_REGNUM + 32 |
| 1991 | && TYPE_CODE (t) == TYPE_CODE_FLT |
| 1992 | && gdbarch_tdep (gdbarch)->have_neon) |
| 1993 | return arm_neon_double_type (gdbarch); |
| 1994 | else |
| 1995 | return t; |
| 1996 | } |
| 1997 | |
| 1998 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
| 1999 | { |
| 2000 | if (!gdbarch_tdep (gdbarch)->have_fpa_registers) |
| 2001 | return builtin_type (gdbarch)->builtin_void; |
| 2002 | |
| 2003 | return arm_ext_type (gdbarch); |
| 2004 | } |
| 2005 | else if (regnum == ARM_SP_REGNUM) |
| 2006 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 2007 | else if (regnum == ARM_PC_REGNUM) |
| 2008 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 2009 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
| 2010 | /* These registers are only supported on targets which supply |
| 2011 | an XML description. */ |
| 2012 | return builtin_type (gdbarch)->builtin_int0; |
| 2013 | else |
| 2014 | return builtin_type (gdbarch)->builtin_uint32; |
| 2015 | } |
| 2016 | |
| 2017 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
| 2018 | number. */ |
| 2019 | |
| 2020 | static int |
| 2021 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 2022 | { |
| 2023 | /* Core integer regs. */ |
| 2024 | if (reg >= 0 && reg <= 15) |
| 2025 | return reg; |
| 2026 | |
| 2027 | /* Legacy FPA encoding. These were once used in a way which |
| 2028 | overlapped with VFP register numbering, so their use is |
| 2029 | discouraged, but GDB doesn't support the ARM toolchain |
| 2030 | which used them for VFP. */ |
| 2031 | if (reg >= 16 && reg <= 23) |
| 2032 | return ARM_F0_REGNUM + reg - 16; |
| 2033 | |
| 2034 | /* New assignments for the FPA registers. */ |
| 2035 | if (reg >= 96 && reg <= 103) |
| 2036 | return ARM_F0_REGNUM + reg - 96; |
| 2037 | |
| 2038 | /* WMMX register assignments. */ |
| 2039 | if (reg >= 104 && reg <= 111) |
| 2040 | return ARM_WCGR0_REGNUM + reg - 104; |
| 2041 | |
| 2042 | if (reg >= 112 && reg <= 127) |
| 2043 | return ARM_WR0_REGNUM + reg - 112; |
| 2044 | |
| 2045 | if (reg >= 192 && reg <= 199) |
| 2046 | return ARM_WC0_REGNUM + reg - 192; |
| 2047 | |
| 2048 | /* VFP v2 registers. A double precision value is actually |
| 2049 | in d1 rather than s2, but the ABI only defines numbering |
| 2050 | for the single precision registers. This will "just work" |
| 2051 | in GDB for little endian targets (we'll read eight bytes, |
| 2052 | starting in s0 and then progressing to s1), but will be |
| 2053 | reversed on big endian targets with VFP. This won't |
| 2054 | be a problem for the new Neon quad registers; you're supposed |
| 2055 | to use DW_OP_piece for those. */ |
| 2056 | if (reg >= 64 && reg <= 95) |
| 2057 | { |
| 2058 | char name_buf[4]; |
| 2059 | |
| 2060 | sprintf (name_buf, "s%d", reg - 64); |
| 2061 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
| 2062 | strlen (name_buf)); |
| 2063 | } |
| 2064 | |
| 2065 | /* VFP v3 / Neon registers. This range is also used for VFP v2 |
| 2066 | registers, except that it now describes d0 instead of s0. */ |
| 2067 | if (reg >= 256 && reg <= 287) |
| 2068 | { |
| 2069 | char name_buf[4]; |
| 2070 | |
| 2071 | sprintf (name_buf, "d%d", reg - 256); |
| 2072 | return user_reg_map_name_to_regnum (gdbarch, name_buf, |
| 2073 | strlen (name_buf)); |
| 2074 | } |
| 2075 | |
| 2076 | return -1; |
| 2077 | } |
| 2078 | |
| 2079 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
| 2080 | static int |
| 2081 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
| 2082 | { |
| 2083 | int reg = regnum; |
| 2084 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
| 2085 | |
| 2086 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
| 2087 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; |
| 2088 | |
| 2089 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) |
| 2090 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; |
| 2091 | |
| 2092 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) |
| 2093 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; |
| 2094 | |
| 2095 | if (reg < NUM_GREGS) |
| 2096 | return SIM_ARM_R0_REGNUM + reg; |
| 2097 | reg -= NUM_GREGS; |
| 2098 | |
| 2099 | if (reg < NUM_FREGS) |
| 2100 | return SIM_ARM_FP0_REGNUM + reg; |
| 2101 | reg -= NUM_FREGS; |
| 2102 | |
| 2103 | if (reg < NUM_SREGS) |
| 2104 | return SIM_ARM_FPS_REGNUM + reg; |
| 2105 | reg -= NUM_SREGS; |
| 2106 | |
| 2107 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
| 2108 | } |
| 2109 | |
| 2110 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
| 2111 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. |
| 2112 | It is thought that this is is the floating-point register format on |
| 2113 | little-endian systems. */ |
| 2114 | |
| 2115 | static void |
| 2116 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
| 2117 | void *dbl, int endianess) |
| 2118 | { |
| 2119 | DOUBLEST d; |
| 2120 | |
| 2121 | if (endianess == BFD_ENDIAN_BIG) |
| 2122 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
| 2123 | else |
| 2124 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 2125 | ptr, &d); |
| 2126 | floatformat_from_doublest (fmt, &d, dbl); |
| 2127 | } |
| 2128 | |
| 2129 | static void |
| 2130 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, |
| 2131 | int endianess) |
| 2132 | { |
| 2133 | DOUBLEST d; |
| 2134 | |
| 2135 | floatformat_to_doublest (fmt, ptr, &d); |
| 2136 | if (endianess == BFD_ENDIAN_BIG) |
| 2137 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
| 2138 | else |
| 2139 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 2140 | &d, dbl); |
| 2141 | } |
| 2142 | |
| 2143 | static int |
| 2144 | condition_true (unsigned long cond, unsigned long status_reg) |
| 2145 | { |
| 2146 | if (cond == INST_AL || cond == INST_NV) |
| 2147 | return 1; |
| 2148 | |
| 2149 | switch (cond) |
| 2150 | { |
| 2151 | case INST_EQ: |
| 2152 | return ((status_reg & FLAG_Z) != 0); |
| 2153 | case INST_NE: |
| 2154 | return ((status_reg & FLAG_Z) == 0); |
| 2155 | case INST_CS: |
| 2156 | return ((status_reg & FLAG_C) != 0); |
| 2157 | case INST_CC: |
| 2158 | return ((status_reg & FLAG_C) == 0); |
| 2159 | case INST_MI: |
| 2160 | return ((status_reg & FLAG_N) != 0); |
| 2161 | case INST_PL: |
| 2162 | return ((status_reg & FLAG_N) == 0); |
| 2163 | case INST_VS: |
| 2164 | return ((status_reg & FLAG_V) != 0); |
| 2165 | case INST_VC: |
| 2166 | return ((status_reg & FLAG_V) == 0); |
| 2167 | case INST_HI: |
| 2168 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); |
| 2169 | case INST_LS: |
| 2170 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); |
| 2171 | case INST_GE: |
| 2172 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); |
| 2173 | case INST_LT: |
| 2174 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); |
| 2175 | case INST_GT: |
| 2176 | return (((status_reg & FLAG_Z) == 0) |
| 2177 | && (((status_reg & FLAG_N) == 0) |
| 2178 | == ((status_reg & FLAG_V) == 0))); |
| 2179 | case INST_LE: |
| 2180 | return (((status_reg & FLAG_Z) != 0) |
| 2181 | || (((status_reg & FLAG_N) == 0) |
| 2182 | != ((status_reg & FLAG_V) == 0))); |
| 2183 | } |
| 2184 | return 1; |
| 2185 | } |
| 2186 | |
| 2187 | /* Support routines for single stepping. Calculate the next PC value. */ |
| 2188 | #define submask(x) ((1L << ((x) + 1)) - 1) |
| 2189 | #define bit(obj,st) (((obj) >> (st)) & 1) |
| 2190 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) |
| 2191 | #define sbits(obj,st,fn) \ |
| 2192 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) |
| 2193 | #define BranchDest(addr,instr) \ |
| 2194 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) |
| 2195 | #define ARM_PC_32 1 |
| 2196 | |
| 2197 | static unsigned long |
| 2198 | shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, |
| 2199 | unsigned long pc_val, unsigned long status_reg) |
| 2200 | { |
| 2201 | unsigned long res, shift; |
| 2202 | int rm = bits (inst, 0, 3); |
| 2203 | unsigned long shifttype = bits (inst, 5, 6); |
| 2204 | |
| 2205 | if (bit (inst, 4)) |
| 2206 | { |
| 2207 | int rs = bits (inst, 8, 11); |
| 2208 | shift = (rs == 15 ? pc_val + 8 |
| 2209 | : get_frame_register_unsigned (frame, rs)) & 0xFF; |
| 2210 | } |
| 2211 | else |
| 2212 | shift = bits (inst, 7, 11); |
| 2213 | |
| 2214 | res = (rm == 15 |
| 2215 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
| 2216 | + (bit (inst, 4) ? 12 : 8)) |
| 2217 | : get_frame_register_unsigned (frame, rm)); |
| 2218 | |
| 2219 | switch (shifttype) |
| 2220 | { |
| 2221 | case 0: /* LSL */ |
| 2222 | res = shift >= 32 ? 0 : res << shift; |
| 2223 | break; |
| 2224 | |
| 2225 | case 1: /* LSR */ |
| 2226 | res = shift >= 32 ? 0 : res >> shift; |
| 2227 | break; |
| 2228 | |
| 2229 | case 2: /* ASR */ |
| 2230 | if (shift >= 32) |
| 2231 | shift = 31; |
| 2232 | res = ((res & 0x80000000L) |
| 2233 | ? ~((~res) >> shift) : res >> shift); |
| 2234 | break; |
| 2235 | |
| 2236 | case 3: /* ROR/RRX */ |
| 2237 | shift &= 31; |
| 2238 | if (shift == 0) |
| 2239 | res = (res >> 1) | (carry ? 0x80000000L : 0); |
| 2240 | else |
| 2241 | res = (res >> shift) | (res << (32 - shift)); |
| 2242 | break; |
| 2243 | } |
| 2244 | |
| 2245 | return res & 0xffffffff; |
| 2246 | } |
| 2247 | |
| 2248 | /* Return number of 1-bits in VAL. */ |
| 2249 | |
| 2250 | static int |
| 2251 | bitcount (unsigned long val) |
| 2252 | { |
| 2253 | int nbits; |
| 2254 | for (nbits = 0; val != 0; nbits++) |
| 2255 | val &= val - 1; /* delete rightmost 1-bit in val */ |
| 2256 | return nbits; |
| 2257 | } |
| 2258 | |
| 2259 | static CORE_ADDR |
| 2260 | thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 2261 | { |
| 2262 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2263 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2264 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
| 2265 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
| 2266 | unsigned short inst1; |
| 2267 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
| 2268 | unsigned long offset; |
| 2269 | ULONGEST status, it; |
| 2270 | |
| 2271 | inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); |
| 2272 | |
| 2273 | /* Thumb-2 conditional execution support. There are eight bits in |
| 2274 | the CPSR which describe conditional execution state. Once |
| 2275 | reconstructed (they're in a funny order), the low five bits |
| 2276 | describe the low bit of the condition for each instruction and |
| 2277 | how many instructions remain. The high three bits describe the |
| 2278 | base condition. One of the low four bits will be set if an IT |
| 2279 | block is active. These bits read as zero on earlier |
| 2280 | processors. */ |
| 2281 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
| 2282 | it = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3); |
| 2283 | |
| 2284 | /* On GNU/Linux, where this routine is used, we use an undefined |
| 2285 | instruction as a breakpoint. Unlike BKPT, IT can disable execution |
| 2286 | of the undefined instruction. So we might miss the breakpoint! */ |
| 2287 | if (((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) || (it & 0x0f)) |
| 2288 | error (_("Stepping through Thumb-2 IT blocks is not yet supported")); |
| 2289 | |
| 2290 | if (it & 0x0f) |
| 2291 | { |
| 2292 | /* We are in a conditional block. Check the condition. */ |
| 2293 | int cond = it >> 4; |
| 2294 | |
| 2295 | if (! condition_true (cond, status)) |
| 2296 | { |
| 2297 | /* Advance to the next instruction. All the 32-bit |
| 2298 | instructions share a common prefix. */ |
| 2299 | if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0) |
| 2300 | return pc + 4; |
| 2301 | else |
| 2302 | return pc + 2; |
| 2303 | } |
| 2304 | } |
| 2305 | |
| 2306 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
| 2307 | { |
| 2308 | CORE_ADDR sp; |
| 2309 | |
| 2310 | /* Fetch the saved PC from the stack. It's stored above |
| 2311 | all of the other registers. */ |
| 2312 | offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; |
| 2313 | sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
| 2314 | nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order); |
| 2315 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 2316 | if (nextpc == pc) |
| 2317 | error (_("Infinite loop detected")); |
| 2318 | } |
| 2319 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ |
| 2320 | { |
| 2321 | unsigned long cond = bits (inst1, 8, 11); |
| 2322 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
| 2323 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
| 2324 | } |
| 2325 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ |
| 2326 | { |
| 2327 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); |
| 2328 | } |
| 2329 | else if ((inst1 & 0xe000) == 0xe000) /* 32-bit instruction */ |
| 2330 | { |
| 2331 | unsigned short inst2; |
| 2332 | inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); |
| 2333 | |
| 2334 | /* Default to the next instruction. */ |
| 2335 | nextpc = pc + 4; |
| 2336 | |
| 2337 | if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000) |
| 2338 | { |
| 2339 | /* Branches and miscellaneous control instructions. */ |
| 2340 | |
| 2341 | if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000) |
| 2342 | { |
| 2343 | /* B, BL, BLX. */ |
| 2344 | int j1, j2, imm1, imm2; |
| 2345 | |
| 2346 | imm1 = sbits (inst1, 0, 10); |
| 2347 | imm2 = bits (inst2, 0, 10); |
| 2348 | j1 = bit (inst2, 13); |
| 2349 | j2 = bit (inst2, 11); |
| 2350 | |
| 2351 | offset = ((imm1 << 12) + (imm2 << 1)); |
| 2352 | offset ^= ((!j2) << 22) | ((!j1) << 23); |
| 2353 | |
| 2354 | nextpc = pc_val + offset; |
| 2355 | /* For BLX make sure to clear the low bits. */ |
| 2356 | if (bit (inst2, 12) == 0) |
| 2357 | nextpc = nextpc & 0xfffffffc; |
| 2358 | } |
| 2359 | else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00) |
| 2360 | { |
| 2361 | /* SUBS PC, LR, #imm8. */ |
| 2362 | nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM); |
| 2363 | nextpc -= inst2 & 0x00ff; |
| 2364 | } |
| 2365 | else if ((inst2 & 0xd000) == 0xc000 && (inst1 & 0x0380) != 0x0380) |
| 2366 | { |
| 2367 | /* Conditional branch. */ |
| 2368 | if (condition_true (bits (inst1, 6, 9), status)) |
| 2369 | { |
| 2370 | int sign, j1, j2, imm1, imm2; |
| 2371 | |
| 2372 | sign = sbits (inst1, 10, 10); |
| 2373 | imm1 = bits (inst1, 0, 5); |
| 2374 | imm2 = bits (inst2, 0, 10); |
| 2375 | j1 = bit (inst2, 13); |
| 2376 | j2 = bit (inst2, 11); |
| 2377 | |
| 2378 | offset = (sign << 20) + (j2 << 19) + (j1 << 18); |
| 2379 | offset += (imm1 << 12) + (imm2 << 1); |
| 2380 | |
| 2381 | nextpc = pc_val + offset; |
| 2382 | } |
| 2383 | } |
| 2384 | } |
| 2385 | else if ((inst1 & 0xfe50) == 0xe810) |
| 2386 | { |
| 2387 | /* Load multiple or RFE. */ |
| 2388 | int rn, offset, load_pc = 1; |
| 2389 | |
| 2390 | rn = bits (inst1, 0, 3); |
| 2391 | if (bit (inst1, 7) && !bit (inst1, 8)) |
| 2392 | { |
| 2393 | /* LDMIA or POP */ |
| 2394 | if (!bit (inst2, 15)) |
| 2395 | load_pc = 0; |
| 2396 | offset = bitcount (inst2) * 4 - 4; |
| 2397 | } |
| 2398 | else if (!bit (inst1, 7) && bit (inst1, 8)) |
| 2399 | { |
| 2400 | /* LDMDB */ |
| 2401 | if (!bit (inst2, 15)) |
| 2402 | load_pc = 0; |
| 2403 | offset = -4; |
| 2404 | } |
| 2405 | else if (bit (inst1, 7) && bit (inst1, 8)) |
| 2406 | { |
| 2407 | /* RFEIA */ |
| 2408 | offset = 0; |
| 2409 | } |
| 2410 | else if (!bit (inst1, 7) && !bit (inst1, 8)) |
| 2411 | { |
| 2412 | /* RFEDB */ |
| 2413 | offset = -8; |
| 2414 | } |
| 2415 | else |
| 2416 | load_pc = 0; |
| 2417 | |
| 2418 | if (load_pc) |
| 2419 | { |
| 2420 | CORE_ADDR addr = get_frame_register_unsigned (frame, rn); |
| 2421 | nextpc = get_frame_memory_unsigned (frame, addr + offset, 4); |
| 2422 | } |
| 2423 | } |
| 2424 | else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00) |
| 2425 | { |
| 2426 | /* MOV PC or MOVS PC. */ |
| 2427 | nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); |
| 2428 | } |
| 2429 | else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000) |
| 2430 | { |
| 2431 | /* LDR PC. */ |
| 2432 | CORE_ADDR base; |
| 2433 | int rn, load_pc = 1; |
| 2434 | |
| 2435 | rn = bits (inst1, 0, 3); |
| 2436 | base = get_frame_register_unsigned (frame, rn); |
| 2437 | if (rn == 15) |
| 2438 | { |
| 2439 | base = (base + 4) & ~(CORE_ADDR) 0x3; |
| 2440 | if (bit (inst1, 7)) |
| 2441 | base += bits (inst2, 0, 11); |
| 2442 | else |
| 2443 | base -= bits (inst2, 0, 11); |
| 2444 | } |
| 2445 | else if (bit (inst1, 7)) |
| 2446 | base += bits (inst2, 0, 11); |
| 2447 | else if (bit (inst2, 11)) |
| 2448 | { |
| 2449 | if (bit (inst2, 10)) |
| 2450 | { |
| 2451 | if (bit (inst2, 9)) |
| 2452 | base += bits (inst2, 0, 7); |
| 2453 | else |
| 2454 | base -= bits (inst2, 0, 7); |
| 2455 | } |
| 2456 | } |
| 2457 | else if ((inst2 & 0x0fc0) == 0x0000) |
| 2458 | { |
| 2459 | int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3); |
| 2460 | base += get_frame_register_unsigned (frame, rm) << shift; |
| 2461 | } |
| 2462 | else |
| 2463 | /* Reserved. */ |
| 2464 | load_pc = 0; |
| 2465 | |
| 2466 | if (load_pc) |
| 2467 | nextpc = get_frame_memory_unsigned (frame, base, 4); |
| 2468 | } |
| 2469 | else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) |
| 2470 | { |
| 2471 | /* TBB. */ |
| 2472 | CORE_ADDR table, offset, length; |
| 2473 | |
| 2474 | table = get_frame_register_unsigned (frame, bits (inst1, 0, 3)); |
| 2475 | offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); |
| 2476 | length = 2 * get_frame_memory_unsigned (frame, table + offset, 1); |
| 2477 | nextpc = pc_val + length; |
| 2478 | } |
| 2479 | else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) |
| 2480 | { |
| 2481 | /* TBH. */ |
| 2482 | CORE_ADDR table, offset, length; |
| 2483 | |
| 2484 | table = get_frame_register_unsigned (frame, bits (inst1, 0, 3)); |
| 2485 | offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3)); |
| 2486 | length = 2 * get_frame_memory_unsigned (frame, table + offset, 2); |
| 2487 | nextpc = pc_val + length; |
| 2488 | } |
| 2489 | } |
| 2490 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
| 2491 | { |
| 2492 | if (bits (inst1, 3, 6) == 0x0f) |
| 2493 | nextpc = pc_val; |
| 2494 | else |
| 2495 | nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); |
| 2496 | |
| 2497 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 2498 | if (nextpc == pc) |
| 2499 | error (_("Infinite loop detected")); |
| 2500 | } |
| 2501 | else if ((inst1 & 0xf500) == 0xb100) |
| 2502 | { |
| 2503 | /* CBNZ or CBZ. */ |
| 2504 | int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1); |
| 2505 | ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2)); |
| 2506 | |
| 2507 | if (bit (inst1, 11) && reg != 0) |
| 2508 | nextpc = pc_val + imm; |
| 2509 | else if (!bit (inst1, 11) && reg == 0) |
| 2510 | nextpc = pc_val + imm; |
| 2511 | } |
| 2512 | |
| 2513 | return nextpc; |
| 2514 | } |
| 2515 | |
| 2516 | CORE_ADDR |
| 2517 | arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 2518 | { |
| 2519 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2520 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2521 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
| 2522 | unsigned long pc_val; |
| 2523 | unsigned long this_instr; |
| 2524 | unsigned long status; |
| 2525 | CORE_ADDR nextpc; |
| 2526 | |
| 2527 | if (arm_frame_is_thumb (frame)) |
| 2528 | return thumb_get_next_pc (frame, pc); |
| 2529 | |
| 2530 | pc_val = (unsigned long) pc; |
| 2531 | this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code); |
| 2532 | |
| 2533 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
| 2534 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
| 2535 | |
| 2536 | if (bits (this_instr, 28, 31) == INST_NV) |
| 2537 | switch (bits (this_instr, 24, 27)) |
| 2538 | { |
| 2539 | case 0xa: |
| 2540 | case 0xb: |
| 2541 | { |
| 2542 | /* Branch with Link and change to Thumb. */ |
| 2543 | nextpc = BranchDest (pc, this_instr); |
| 2544 | nextpc |= bit (this_instr, 24) << 1; |
| 2545 | |
| 2546 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 2547 | if (nextpc == pc) |
| 2548 | error (_("Infinite loop detected")); |
| 2549 | break; |
| 2550 | } |
| 2551 | case 0xc: |
| 2552 | case 0xd: |
| 2553 | case 0xe: |
| 2554 | /* Coprocessor register transfer. */ |
| 2555 | if (bits (this_instr, 12, 15) == 15) |
| 2556 | error (_("Invalid update to pc in instruction")); |
| 2557 | break; |
| 2558 | } |
| 2559 | else if (condition_true (bits (this_instr, 28, 31), status)) |
| 2560 | { |
| 2561 | switch (bits (this_instr, 24, 27)) |
| 2562 | { |
| 2563 | case 0x0: |
| 2564 | case 0x1: /* data processing */ |
| 2565 | case 0x2: |
| 2566 | case 0x3: |
| 2567 | { |
| 2568 | unsigned long operand1, operand2, result = 0; |
| 2569 | unsigned long rn; |
| 2570 | int c; |
| 2571 | |
| 2572 | if (bits (this_instr, 12, 15) != 15) |
| 2573 | break; |
| 2574 | |
| 2575 | if (bits (this_instr, 22, 25) == 0 |
| 2576 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
| 2577 | error (_("Invalid update to pc in instruction")); |
| 2578 | |
| 2579 | /* BX <reg>, BLX <reg> */ |
| 2580 | if (bits (this_instr, 4, 27) == 0x12fff1 |
| 2581 | || bits (this_instr, 4, 27) == 0x12fff3) |
| 2582 | { |
| 2583 | rn = bits (this_instr, 0, 3); |
| 2584 | result = (rn == 15) ? pc_val + 8 |
| 2585 | : get_frame_register_unsigned (frame, rn); |
| 2586 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
| 2587 | (gdbarch, result); |
| 2588 | |
| 2589 | if (nextpc == pc) |
| 2590 | error (_("Infinite loop detected")); |
| 2591 | |
| 2592 | return nextpc; |
| 2593 | } |
| 2594 | |
| 2595 | /* Multiply into PC */ |
| 2596 | c = (status & FLAG_C) ? 1 : 0; |
| 2597 | rn = bits (this_instr, 16, 19); |
| 2598 | operand1 = (rn == 15) ? pc_val + 8 |
| 2599 | : get_frame_register_unsigned (frame, rn); |
| 2600 | |
| 2601 | if (bit (this_instr, 25)) |
| 2602 | { |
| 2603 | unsigned long immval = bits (this_instr, 0, 7); |
| 2604 | unsigned long rotate = 2 * bits (this_instr, 8, 11); |
| 2605 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
| 2606 | & 0xffffffff; |
| 2607 | } |
| 2608 | else /* operand 2 is a shifted register */ |
| 2609 | operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status); |
| 2610 | |
| 2611 | switch (bits (this_instr, 21, 24)) |
| 2612 | { |
| 2613 | case 0x0: /*and */ |
| 2614 | result = operand1 & operand2; |
| 2615 | break; |
| 2616 | |
| 2617 | case 0x1: /*eor */ |
| 2618 | result = operand1 ^ operand2; |
| 2619 | break; |
| 2620 | |
| 2621 | case 0x2: /*sub */ |
| 2622 | result = operand1 - operand2; |
| 2623 | break; |
| 2624 | |
| 2625 | case 0x3: /*rsb */ |
| 2626 | result = operand2 - operand1; |
| 2627 | break; |
| 2628 | |
| 2629 | case 0x4: /*add */ |
| 2630 | result = operand1 + operand2; |
| 2631 | break; |
| 2632 | |
| 2633 | case 0x5: /*adc */ |
| 2634 | result = operand1 + operand2 + c; |
| 2635 | break; |
| 2636 | |
| 2637 | case 0x6: /*sbc */ |
| 2638 | result = operand1 - operand2 + c; |
| 2639 | break; |
| 2640 | |
| 2641 | case 0x7: /*rsc */ |
| 2642 | result = operand2 - operand1 + c; |
| 2643 | break; |
| 2644 | |
| 2645 | case 0x8: |
| 2646 | case 0x9: |
| 2647 | case 0xa: |
| 2648 | case 0xb: /* tst, teq, cmp, cmn */ |
| 2649 | result = (unsigned long) nextpc; |
| 2650 | break; |
| 2651 | |
| 2652 | case 0xc: /*orr */ |
| 2653 | result = operand1 | operand2; |
| 2654 | break; |
| 2655 | |
| 2656 | case 0xd: /*mov */ |
| 2657 | /* Always step into a function. */ |
| 2658 | result = operand2; |
| 2659 | break; |
| 2660 | |
| 2661 | case 0xe: /*bic */ |
| 2662 | result = operand1 & ~operand2; |
| 2663 | break; |
| 2664 | |
| 2665 | case 0xf: /*mvn */ |
| 2666 | result = ~operand2; |
| 2667 | break; |
| 2668 | } |
| 2669 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
| 2670 | (gdbarch, result); |
| 2671 | |
| 2672 | if (nextpc == pc) |
| 2673 | error (_("Infinite loop detected")); |
| 2674 | break; |
| 2675 | } |
| 2676 | |
| 2677 | case 0x4: |
| 2678 | case 0x5: /* data transfer */ |
| 2679 | case 0x6: |
| 2680 | case 0x7: |
| 2681 | if (bit (this_instr, 20)) |
| 2682 | { |
| 2683 | /* load */ |
| 2684 | if (bits (this_instr, 12, 15) == 15) |
| 2685 | { |
| 2686 | /* rd == pc */ |
| 2687 | unsigned long rn; |
| 2688 | unsigned long base; |
| 2689 | |
| 2690 | if (bit (this_instr, 22)) |
| 2691 | error (_("Invalid update to pc in instruction")); |
| 2692 | |
| 2693 | /* byte write to PC */ |
| 2694 | rn = bits (this_instr, 16, 19); |
| 2695 | base = (rn == 15) ? pc_val + 8 |
| 2696 | : get_frame_register_unsigned (frame, rn); |
| 2697 | if (bit (this_instr, 24)) |
| 2698 | { |
| 2699 | /* pre-indexed */ |
| 2700 | int c = (status & FLAG_C) ? 1 : 0; |
| 2701 | unsigned long offset = |
| 2702 | (bit (this_instr, 25) |
| 2703 | ? shifted_reg_val (frame, this_instr, c, pc_val, status) |
| 2704 | : bits (this_instr, 0, 11)); |
| 2705 | |
| 2706 | if (bit (this_instr, 23)) |
| 2707 | base += offset; |
| 2708 | else |
| 2709 | base -= offset; |
| 2710 | } |
| 2711 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
| 2712 | 4, byte_order); |
| 2713 | |
| 2714 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 2715 | |
| 2716 | if (nextpc == pc) |
| 2717 | error (_("Infinite loop detected")); |
| 2718 | } |
| 2719 | } |
| 2720 | break; |
| 2721 | |
| 2722 | case 0x8: |
| 2723 | case 0x9: /* block transfer */ |
| 2724 | if (bit (this_instr, 20)) |
| 2725 | { |
| 2726 | /* LDM */ |
| 2727 | if (bit (this_instr, 15)) |
| 2728 | { |
| 2729 | /* loading pc */ |
| 2730 | int offset = 0; |
| 2731 | |
| 2732 | if (bit (this_instr, 23)) |
| 2733 | { |
| 2734 | /* up */ |
| 2735 | unsigned long reglist = bits (this_instr, 0, 14); |
| 2736 | offset = bitcount (reglist) * 4; |
| 2737 | if (bit (this_instr, 24)) /* pre */ |
| 2738 | offset += 4; |
| 2739 | } |
| 2740 | else if (bit (this_instr, 24)) |
| 2741 | offset = -4; |
| 2742 | |
| 2743 | { |
| 2744 | unsigned long rn_val = |
| 2745 | get_frame_register_unsigned (frame, |
| 2746 | bits (this_instr, 16, 19)); |
| 2747 | nextpc = |
| 2748 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val |
| 2749 | + offset), |
| 2750 | 4, byte_order); |
| 2751 | } |
| 2752 | nextpc = gdbarch_addr_bits_remove |
| 2753 | (gdbarch, nextpc); |
| 2754 | if (nextpc == pc) |
| 2755 | error (_("Infinite loop detected")); |
| 2756 | } |
| 2757 | } |
| 2758 | break; |
| 2759 | |
| 2760 | case 0xb: /* branch & link */ |
| 2761 | case 0xa: /* branch */ |
| 2762 | { |
| 2763 | nextpc = BranchDest (pc, this_instr); |
| 2764 | |
| 2765 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 2766 | if (nextpc == pc) |
| 2767 | error (_("Infinite loop detected")); |
| 2768 | break; |
| 2769 | } |
| 2770 | |
| 2771 | case 0xc: |
| 2772 | case 0xd: |
| 2773 | case 0xe: /* coproc ops */ |
| 2774 | case 0xf: /* SWI */ |
| 2775 | break; |
| 2776 | |
| 2777 | default: |
| 2778 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
| 2779 | return (pc); |
| 2780 | } |
| 2781 | } |
| 2782 | |
| 2783 | return nextpc; |
| 2784 | } |
| 2785 | |
| 2786 | /* single_step() is called just before we want to resume the inferior, |
| 2787 | if we want to single-step it but there is no hardware or kernel |
| 2788 | single-step support. We find the target of the coming instruction |
| 2789 | and breakpoint it. */ |
| 2790 | |
| 2791 | int |
| 2792 | arm_software_single_step (struct frame_info *frame) |
| 2793 | { |
| 2794 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2795 | struct address_space *aspace = get_frame_address_space (frame); |
| 2796 | |
| 2797 | /* NOTE: This may insert the wrong breakpoint instruction when |
| 2798 | single-stepping over a mode-changing instruction, if the |
| 2799 | CPSR heuristics are used. */ |
| 2800 | |
| 2801 | CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); |
| 2802 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
| 2803 | |
| 2804 | return 1; |
| 2805 | } |
| 2806 | |
| 2807 | /* ARM displaced stepping support. |
| 2808 | |
| 2809 | Generally ARM displaced stepping works as follows: |
| 2810 | |
| 2811 | 1. When an instruction is to be single-stepped, it is first decoded by |
| 2812 | arm_process_displaced_insn (called from arm_displaced_step_copy_insn). |
| 2813 | Depending on the type of instruction, it is then copied to a scratch |
| 2814 | location, possibly in a modified form. The copy_* set of functions |
| 2815 | performs such modification, as necessary. A breakpoint is placed after |
| 2816 | the modified instruction in the scratch space to return control to GDB. |
| 2817 | Note in particular that instructions which modify the PC will no longer |
| 2818 | do so after modification. |
| 2819 | |
| 2820 | 2. The instruction is single-stepped, by setting the PC to the scratch |
| 2821 | location address, and resuming. Control returns to GDB when the |
| 2822 | breakpoint is hit. |
| 2823 | |
| 2824 | 3. A cleanup function (cleanup_*) is called corresponding to the copy_* |
| 2825 | function used for the current instruction. This function's job is to |
| 2826 | put the CPU/memory state back to what it would have been if the |
| 2827 | instruction had been executed unmodified in its original location. */ |
| 2828 | |
| 2829 | /* NOP instruction (mov r0, r0). */ |
| 2830 | #define ARM_NOP 0xe1a00000 |
| 2831 | |
| 2832 | /* Helper for register reads for displaced stepping. In particular, this |
| 2833 | returns the PC as it would be seen by the instruction at its original |
| 2834 | location. */ |
| 2835 | |
| 2836 | ULONGEST |
| 2837 | displaced_read_reg (struct regcache *regs, CORE_ADDR from, int regno) |
| 2838 | { |
| 2839 | ULONGEST ret; |
| 2840 | |
| 2841 | if (regno == 15) |
| 2842 | { |
| 2843 | if (debug_displaced) |
| 2844 | fprintf_unfiltered (gdb_stdlog, "displaced: read pc value %.8lx\n", |
| 2845 | (unsigned long) from + 8); |
| 2846 | return (ULONGEST) from + 8; /* Pipeline offset. */ |
| 2847 | } |
| 2848 | else |
| 2849 | { |
| 2850 | regcache_cooked_read_unsigned (regs, regno, &ret); |
| 2851 | if (debug_displaced) |
| 2852 | fprintf_unfiltered (gdb_stdlog, "displaced: read r%d value %.8lx\n", |
| 2853 | regno, (unsigned long) ret); |
| 2854 | return ret; |
| 2855 | } |
| 2856 | } |
| 2857 | |
| 2858 | static int |
| 2859 | displaced_in_arm_mode (struct regcache *regs) |
| 2860 | { |
| 2861 | ULONGEST ps; |
| 2862 | |
| 2863 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
| 2864 | |
| 2865 | return (ps & CPSR_T) == 0; |
| 2866 | } |
| 2867 | |
| 2868 | /* Write to the PC as from a branch instruction. */ |
| 2869 | |
| 2870 | static void |
| 2871 | branch_write_pc (struct regcache *regs, ULONGEST val) |
| 2872 | { |
| 2873 | if (displaced_in_arm_mode (regs)) |
| 2874 | /* Note: If bits 0/1 are set, this branch would be unpredictable for |
| 2875 | architecture versions < 6. */ |
| 2876 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x3); |
| 2877 | else |
| 2878 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & ~(ULONGEST) 0x1); |
| 2879 | } |
| 2880 | |
| 2881 | /* Write to the PC as from a branch-exchange instruction. */ |
| 2882 | |
| 2883 | static void |
| 2884 | bx_write_pc (struct regcache *regs, ULONGEST val) |
| 2885 | { |
| 2886 | ULONGEST ps; |
| 2887 | |
| 2888 | regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps); |
| 2889 | |
| 2890 | if ((val & 1) == 1) |
| 2891 | { |
| 2892 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps | CPSR_T); |
| 2893 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffe); |
| 2894 | } |
| 2895 | else if ((val & 2) == 0) |
| 2896 | { |
| 2897 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, |
| 2898 | ps & ~(ULONGEST) CPSR_T); |
| 2899 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val); |
| 2900 | } |
| 2901 | else |
| 2902 | { |
| 2903 | /* Unpredictable behaviour. Try to do something sensible (switch to ARM |
| 2904 | mode, align dest to 4 bytes). */ |
| 2905 | warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); |
| 2906 | regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, |
| 2907 | ps & ~(ULONGEST) CPSR_T); |
| 2908 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, val & 0xfffffffc); |
| 2909 | } |
| 2910 | } |
| 2911 | |
| 2912 | /* Write to the PC as if from a load instruction. */ |
| 2913 | |
| 2914 | static void |
| 2915 | load_write_pc (struct regcache *regs, ULONGEST val) |
| 2916 | { |
| 2917 | if (DISPLACED_STEPPING_ARCH_VERSION >= 5) |
| 2918 | bx_write_pc (regs, val); |
| 2919 | else |
| 2920 | branch_write_pc (regs, val); |
| 2921 | } |
| 2922 | |
| 2923 | /* Write to the PC as if from an ALU instruction. */ |
| 2924 | |
| 2925 | static void |
| 2926 | alu_write_pc (struct regcache *regs, ULONGEST val) |
| 2927 | { |
| 2928 | if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && displaced_in_arm_mode (regs)) |
| 2929 | bx_write_pc (regs, val); |
| 2930 | else |
| 2931 | branch_write_pc (regs, val); |
| 2932 | } |
| 2933 | |
| 2934 | /* Helper for writing to registers for displaced stepping. Writing to the PC |
| 2935 | has a varying effects depending on the instruction which does the write: |
| 2936 | this is controlled by the WRITE_PC argument. */ |
| 2937 | |
| 2938 | void |
| 2939 | displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc, |
| 2940 | int regno, ULONGEST val, enum pc_write_style write_pc) |
| 2941 | { |
| 2942 | if (regno == 15) |
| 2943 | { |
| 2944 | if (debug_displaced) |
| 2945 | fprintf_unfiltered (gdb_stdlog, "displaced: writing pc %.8lx\n", |
| 2946 | (unsigned long) val); |
| 2947 | switch (write_pc) |
| 2948 | { |
| 2949 | case BRANCH_WRITE_PC: |
| 2950 | branch_write_pc (regs, val); |
| 2951 | break; |
| 2952 | |
| 2953 | case BX_WRITE_PC: |
| 2954 | bx_write_pc (regs, val); |
| 2955 | break; |
| 2956 | |
| 2957 | case LOAD_WRITE_PC: |
| 2958 | load_write_pc (regs, val); |
| 2959 | break; |
| 2960 | |
| 2961 | case ALU_WRITE_PC: |
| 2962 | alu_write_pc (regs, val); |
| 2963 | break; |
| 2964 | |
| 2965 | case CANNOT_WRITE_PC: |
| 2966 | warning (_("Instruction wrote to PC in an unexpected way when " |
| 2967 | "single-stepping")); |
| 2968 | break; |
| 2969 | |
| 2970 | default: |
| 2971 | internal_error (__FILE__, __LINE__, |
| 2972 | _("Invalid argument to displaced_write_reg")); |
| 2973 | } |
| 2974 | |
| 2975 | dsc->wrote_to_pc = 1; |
| 2976 | } |
| 2977 | else |
| 2978 | { |
| 2979 | if (debug_displaced) |
| 2980 | fprintf_unfiltered (gdb_stdlog, "displaced: writing r%d value %.8lx\n", |
| 2981 | regno, (unsigned long) val); |
| 2982 | regcache_cooked_write_unsigned (regs, regno, val); |
| 2983 | } |
| 2984 | } |
| 2985 | |
| 2986 | /* This function is used to concisely determine if an instruction INSN |
| 2987 | references PC. Register fields of interest in INSN should have the |
| 2988 | corresponding fields of BITMASK set to 0b1111. The function returns return 1 |
| 2989 | if any of these fields in INSN reference the PC (also 0b1111, r15), else it |
| 2990 | returns 0. */ |
| 2991 | |
| 2992 | static int |
| 2993 | insn_references_pc (uint32_t insn, uint32_t bitmask) |
| 2994 | { |
| 2995 | uint32_t lowbit = 1; |
| 2996 | |
| 2997 | while (bitmask != 0) |
| 2998 | { |
| 2999 | uint32_t mask; |
| 3000 | |
| 3001 | for (; lowbit && (bitmask & lowbit) == 0; lowbit <<= 1) |
| 3002 | ; |
| 3003 | |
| 3004 | if (!lowbit) |
| 3005 | break; |
| 3006 | |
| 3007 | mask = lowbit * 0xf; |
| 3008 | |
| 3009 | if ((insn & mask) == mask) |
| 3010 | return 1; |
| 3011 | |
| 3012 | bitmask &= ~mask; |
| 3013 | } |
| 3014 | |
| 3015 | return 0; |
| 3016 | } |
| 3017 | |
| 3018 | /* The simplest copy function. Many instructions have the same effect no |
| 3019 | matter what address they are executed at: in those cases, use this. */ |
| 3020 | |
| 3021 | static int |
| 3022 | copy_unmodified (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, |
| 3023 | const char *iname, struct displaced_step_closure *dsc) |
| 3024 | { |
| 3025 | if (debug_displaced) |
| 3026 | fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, " |
| 3027 | "opcode/class '%s' unmodified\n", (unsigned long) insn, |
| 3028 | iname); |
| 3029 | |
| 3030 | dsc->modinsn[0] = insn; |
| 3031 | |
| 3032 | return 0; |
| 3033 | } |
| 3034 | |
| 3035 | /* Preload instructions with immediate offset. */ |
| 3036 | |
| 3037 | static void |
| 3038 | cleanup_preload (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, |
| 3039 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 3040 | { |
| 3041 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
| 3042 | if (!dsc->u.preload.immed) |
| 3043 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); |
| 3044 | } |
| 3045 | |
| 3046 | static int |
| 3047 | copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
| 3048 | struct displaced_step_closure *dsc) |
| 3049 | { |
| 3050 | unsigned int rn = bits (insn, 16, 19); |
| 3051 | ULONGEST rn_val; |
| 3052 | CORE_ADDR from = dsc->insn_addr; |
| 3053 | |
| 3054 | if (!insn_references_pc (insn, 0x000f0000ul)) |
| 3055 | return copy_unmodified (gdbarch, insn, "preload", dsc); |
| 3056 | |
| 3057 | if (debug_displaced) |
| 3058 | fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", |
| 3059 | (unsigned long) insn); |
| 3060 | |
| 3061 | /* Preload instructions: |
| 3062 | |
| 3063 | {pli/pld} [rn, #+/-imm] |
| 3064 | -> |
| 3065 | {pli/pld} [r0, #+/-imm]. */ |
| 3066 | |
| 3067 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); |
| 3068 | rn_val = displaced_read_reg (regs, from, rn); |
| 3069 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
| 3070 | |
| 3071 | dsc->u.preload.immed = 1; |
| 3072 | |
| 3073 | dsc->modinsn[0] = insn & 0xfff0ffff; |
| 3074 | |
| 3075 | dsc->cleanup = &cleanup_preload; |
| 3076 | |
| 3077 | return 0; |
| 3078 | } |
| 3079 | |
| 3080 | /* Preload instructions with register offset. */ |
| 3081 | |
| 3082 | static int |
| 3083 | copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
| 3084 | struct displaced_step_closure *dsc) |
| 3085 | { |
| 3086 | unsigned int rn = bits (insn, 16, 19); |
| 3087 | unsigned int rm = bits (insn, 0, 3); |
| 3088 | ULONGEST rn_val, rm_val; |
| 3089 | CORE_ADDR from = dsc->insn_addr; |
| 3090 | |
| 3091 | if (!insn_references_pc (insn, 0x000f000ful)) |
| 3092 | return copy_unmodified (gdbarch, insn, "preload reg", dsc); |
| 3093 | |
| 3094 | if (debug_displaced) |
| 3095 | fprintf_unfiltered (gdb_stdlog, "displaced: copying preload insn %.8lx\n", |
| 3096 | (unsigned long) insn); |
| 3097 | |
| 3098 | /* Preload register-offset instructions: |
| 3099 | |
| 3100 | {pli/pld} [rn, rm {, shift}] |
| 3101 | -> |
| 3102 | {pli/pld} [r0, r1 {, shift}]. */ |
| 3103 | |
| 3104 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); |
| 3105 | dsc->tmp[1] = displaced_read_reg (regs, from, 1); |
| 3106 | rn_val = displaced_read_reg (regs, from, rn); |
| 3107 | rm_val = displaced_read_reg (regs, from, rm); |
| 3108 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
| 3109 | displaced_write_reg (regs, dsc, 1, rm_val, CANNOT_WRITE_PC); |
| 3110 | |
| 3111 | dsc->u.preload.immed = 0; |
| 3112 | |
| 3113 | dsc->modinsn[0] = (insn & 0xfff0fff0) | 0x1; |
| 3114 | |
| 3115 | dsc->cleanup = &cleanup_preload; |
| 3116 | |
| 3117 | return 0; |
| 3118 | } |
| 3119 | |
| 3120 | /* Copy/cleanup coprocessor load and store instructions. */ |
| 3121 | |
| 3122 | static void |
| 3123 | cleanup_copro_load_store (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, |
| 3124 | struct regcache *regs, |
| 3125 | struct displaced_step_closure *dsc) |
| 3126 | { |
| 3127 | ULONGEST rn_val = displaced_read_reg (regs, dsc->insn_addr, 0); |
| 3128 | |
| 3129 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
| 3130 | |
| 3131 | if (dsc->u.ldst.writeback) |
| 3132 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC); |
| 3133 | } |
| 3134 | |
| 3135 | static int |
| 3136 | copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn, |
| 3137 | struct regcache *regs, |
| 3138 | struct displaced_step_closure *dsc) |
| 3139 | { |
| 3140 | unsigned int rn = bits (insn, 16, 19); |
| 3141 | ULONGEST rn_val; |
| 3142 | CORE_ADDR from = dsc->insn_addr; |
| 3143 | |
| 3144 | if (!insn_references_pc (insn, 0x000f0000ul)) |
| 3145 | return copy_unmodified (gdbarch, insn, "copro load/store", dsc); |
| 3146 | |
| 3147 | if (debug_displaced) |
| 3148 | fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor " |
| 3149 | "load/store insn %.8lx\n", (unsigned long) insn); |
| 3150 | |
| 3151 | /* Coprocessor load/store instructions: |
| 3152 | |
| 3153 | {stc/stc2} [<Rn>, #+/-imm] (and other immediate addressing modes) |
| 3154 | -> |
| 3155 | {stc/stc2} [r0, #+/-imm]. |
| 3156 | |
| 3157 | ldc/ldc2 are handled identically. */ |
| 3158 | |
| 3159 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); |
| 3160 | rn_val = displaced_read_reg (regs, from, rn); |
| 3161 | displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC); |
| 3162 | |
| 3163 | dsc->u.ldst.writeback = bit (insn, 25); |
| 3164 | dsc->u.ldst.rn = rn; |
| 3165 | |
| 3166 | dsc->modinsn[0] = insn & 0xfff0ffff; |
| 3167 | |
| 3168 | dsc->cleanup = &cleanup_copro_load_store; |
| 3169 | |
| 3170 | return 0; |
| 3171 | } |
| 3172 | |
| 3173 | /* Clean up branch instructions (actually perform the branch, by setting |
| 3174 | PC). */ |
| 3175 | |
| 3176 | static void |
| 3177 | cleanup_branch (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, struct regcache *regs, |
| 3178 | struct displaced_step_closure *dsc) |
| 3179 | { |
| 3180 | ULONGEST from = dsc->insn_addr; |
| 3181 | uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); |
| 3182 | int branch_taken = condition_true (dsc->u.branch.cond, status); |
| 3183 | enum pc_write_style write_pc = dsc->u.branch.exchange |
| 3184 | ? BX_WRITE_PC : BRANCH_WRITE_PC; |
| 3185 | |
| 3186 | if (!branch_taken) |
| 3187 | return; |
| 3188 | |
| 3189 | if (dsc->u.branch.link) |
| 3190 | { |
| 3191 | ULONGEST pc = displaced_read_reg (regs, from, 15); |
| 3192 | displaced_write_reg (regs, dsc, 14, pc - 4, CANNOT_WRITE_PC); |
| 3193 | } |
| 3194 | |
| 3195 | displaced_write_reg (regs, dsc, 15, dsc->u.branch.dest, write_pc); |
| 3196 | } |
| 3197 | |
| 3198 | /* Copy B/BL/BLX instructions with immediate destinations. */ |
| 3199 | |
| 3200 | static int |
| 3201 | copy_b_bl_blx (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, |
| 3202 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 3203 | { |
| 3204 | unsigned int cond = bits (insn, 28, 31); |
| 3205 | int exchange = (cond == 0xf); |
| 3206 | int link = exchange || bit (insn, 24); |
| 3207 | CORE_ADDR from = dsc->insn_addr; |
| 3208 | long offset; |
| 3209 | |
| 3210 | if (debug_displaced) |
| 3211 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s immediate insn " |
| 3212 | "%.8lx\n", (exchange) ? "blx" : (link) ? "bl" : "b", |
| 3213 | (unsigned long) insn); |
| 3214 | |
| 3215 | /* Implement "BL<cond> <label>" as: |
| 3216 | |
| 3217 | Preparation: cond <- instruction condition |
| 3218 | Insn: mov r0, r0 (nop) |
| 3219 | Cleanup: if (condition true) { r14 <- pc; pc <- label }. |
| 3220 | |
| 3221 | B<cond> similar, but don't set r14 in cleanup. */ |
| 3222 | |
| 3223 | if (exchange) |
| 3224 | /* For BLX, set bit 0 of the destination. The cleanup_branch function will |
| 3225 | then arrange the switch into Thumb mode. */ |
| 3226 | offset = (bits (insn, 0, 23) << 2) | (bit (insn, 24) << 1) | 1; |
| 3227 | else |
| 3228 | offset = bits (insn, 0, 23) << 2; |
| 3229 | |
| 3230 | if (bit (offset, 25)) |
| 3231 | offset = offset | ~0x3ffffff; |
| 3232 | |
| 3233 | dsc->u.branch.cond = cond; |
| 3234 | dsc->u.branch.link = link; |
| 3235 | dsc->u.branch.exchange = exchange; |
| 3236 | dsc->u.branch.dest = from + 8 + offset; |
| 3237 | |
| 3238 | dsc->modinsn[0] = ARM_NOP; |
| 3239 | |
| 3240 | dsc->cleanup = &cleanup_branch; |
| 3241 | |
| 3242 | return 0; |
| 3243 | } |
| 3244 | |
| 3245 | /* Copy BX/BLX with register-specified destinations. */ |
| 3246 | |
| 3247 | static int |
| 3248 | copy_bx_blx_reg (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, |
| 3249 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 3250 | { |
| 3251 | unsigned int cond = bits (insn, 28, 31); |
| 3252 | /* BX: x12xxx1x |
| 3253 | BLX: x12xxx3x. */ |
| 3254 | int link = bit (insn, 5); |
| 3255 | unsigned int rm = bits (insn, 0, 3); |
| 3256 | CORE_ADDR from = dsc->insn_addr; |
| 3257 | |
| 3258 | if (debug_displaced) |
| 3259 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s register insn " |
| 3260 | "%.8lx\n", (link) ? "blx" : "bx", (unsigned long) insn); |
| 3261 | |
| 3262 | /* Implement {BX,BLX}<cond> <reg>" as: |
| 3263 | |
| 3264 | Preparation: cond <- instruction condition |
| 3265 | Insn: mov r0, r0 (nop) |
| 3266 | Cleanup: if (condition true) { r14 <- pc; pc <- dest; }. |
| 3267 | |
| 3268 | Don't set r14 in cleanup for BX. */ |
| 3269 | |
| 3270 | dsc->u.branch.dest = displaced_read_reg (regs, from, rm); |
| 3271 | |
| 3272 | dsc->u.branch.cond = cond; |
| 3273 | dsc->u.branch.link = link; |
| 3274 | dsc->u.branch.exchange = 1; |
| 3275 | |
| 3276 | dsc->modinsn[0] = ARM_NOP; |
| 3277 | |
| 3278 | dsc->cleanup = &cleanup_branch; |
| 3279 | |
| 3280 | return 0; |
| 3281 | } |
| 3282 | |
| 3283 | /* Copy/cleanup arithmetic/logic instruction with immediate RHS. */ |
| 3284 | |
| 3285 | static void |
| 3286 | cleanup_alu_imm (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, |
| 3287 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 3288 | { |
| 3289 | ULONGEST rd_val = displaced_read_reg (regs, dsc->insn_addr, 0); |
| 3290 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
| 3291 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); |
| 3292 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); |
| 3293 | } |
| 3294 | |
| 3295 | static int |
| 3296 | copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
| 3297 | struct displaced_step_closure *dsc) |
| 3298 | { |
| 3299 | unsigned int rn = bits (insn, 16, 19); |
| 3300 | unsigned int rd = bits (insn, 12, 15); |
| 3301 | unsigned int op = bits (insn, 21, 24); |
| 3302 | int is_mov = (op == 0xd); |
| 3303 | ULONGEST rd_val, rn_val; |
| 3304 | CORE_ADDR from = dsc->insn_addr; |
| 3305 | |
| 3306 | if (!insn_references_pc (insn, 0x000ff000ul)) |
| 3307 | return copy_unmodified (gdbarch, insn, "ALU immediate", dsc); |
| 3308 | |
| 3309 | if (debug_displaced) |
| 3310 | fprintf_unfiltered (gdb_stdlog, "displaced: copying immediate %s insn " |
| 3311 | "%.8lx\n", is_mov ? "move" : "ALU", |
| 3312 | (unsigned long) insn); |
| 3313 | |
| 3314 | /* Instruction is of form: |
| 3315 | |
| 3316 | <op><cond> rd, [rn,] #imm |
| 3317 | |
| 3318 | Rewrite as: |
| 3319 | |
| 3320 | Preparation: tmp1, tmp2 <- r0, r1; |
| 3321 | r0, r1 <- rd, rn |
| 3322 | Insn: <op><cond> r0, r1, #imm |
| 3323 | Cleanup: rd <- r0; r0 <- tmp1; r1 <- tmp2 |
| 3324 | */ |
| 3325 | |
| 3326 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); |
| 3327 | dsc->tmp[1] = displaced_read_reg (regs, from, 1); |
| 3328 | rn_val = displaced_read_reg (regs, from, rn); |
| 3329 | rd_val = displaced_read_reg (regs, from, rd); |
| 3330 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
| 3331 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); |
| 3332 | dsc->rd = rd; |
| 3333 | |
| 3334 | if (is_mov) |
| 3335 | dsc->modinsn[0] = insn & 0xfff00fff; |
| 3336 | else |
| 3337 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x10000; |
| 3338 | |
| 3339 | dsc->cleanup = &cleanup_alu_imm; |
| 3340 | |
| 3341 | return 0; |
| 3342 | } |
| 3343 | |
| 3344 | /* Copy/cleanup arithmetic/logic insns with register RHS. */ |
| 3345 | |
| 3346 | static void |
| 3347 | cleanup_alu_reg (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, |
| 3348 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 3349 | { |
| 3350 | ULONGEST rd_val; |
| 3351 | int i; |
| 3352 | |
| 3353 | rd_val = displaced_read_reg (regs, dsc->insn_addr, 0); |
| 3354 | |
| 3355 | for (i = 0; i < 3; i++) |
| 3356 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); |
| 3357 | |
| 3358 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); |
| 3359 | } |
| 3360 | |
| 3361 | static int |
| 3362 | copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
| 3363 | struct displaced_step_closure *dsc) |
| 3364 | { |
| 3365 | unsigned int rn = bits (insn, 16, 19); |
| 3366 | unsigned int rm = bits (insn, 0, 3); |
| 3367 | unsigned int rd = bits (insn, 12, 15); |
| 3368 | unsigned int op = bits (insn, 21, 24); |
| 3369 | int is_mov = (op == 0xd); |
| 3370 | ULONGEST rd_val, rn_val, rm_val; |
| 3371 | CORE_ADDR from = dsc->insn_addr; |
| 3372 | |
| 3373 | if (!insn_references_pc (insn, 0x000ff00ful)) |
| 3374 | return copy_unmodified (gdbarch, insn, "ALU reg", dsc); |
| 3375 | |
| 3376 | if (debug_displaced) |
| 3377 | fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.8lx\n", |
| 3378 | is_mov ? "move" : "ALU", (unsigned long) insn); |
| 3379 | |
| 3380 | /* Instruction is of form: |
| 3381 | |
| 3382 | <op><cond> rd, [rn,] rm [, <shift>] |
| 3383 | |
| 3384 | Rewrite as: |
| 3385 | |
| 3386 | Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; |
| 3387 | r0, r1, r2 <- rd, rn, rm |
| 3388 | Insn: <op><cond> r0, r1, r2 [, <shift>] |
| 3389 | Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 |
| 3390 | */ |
| 3391 | |
| 3392 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); |
| 3393 | dsc->tmp[1] = displaced_read_reg (regs, from, 1); |
| 3394 | dsc->tmp[2] = displaced_read_reg (regs, from, 2); |
| 3395 | rd_val = displaced_read_reg (regs, from, rd); |
| 3396 | rn_val = displaced_read_reg (regs, from, rn); |
| 3397 | rm_val = displaced_read_reg (regs, from, rm); |
| 3398 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
| 3399 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); |
| 3400 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); |
| 3401 | dsc->rd = rd; |
| 3402 | |
| 3403 | if (is_mov) |
| 3404 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x2; |
| 3405 | else |
| 3406 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x10002; |
| 3407 | |
| 3408 | dsc->cleanup = &cleanup_alu_reg; |
| 3409 | |
| 3410 | return 0; |
| 3411 | } |
| 3412 | |
| 3413 | /* Cleanup/copy arithmetic/logic insns with shifted register RHS. */ |
| 3414 | |
| 3415 | static void |
| 3416 | cleanup_alu_shifted_reg (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, |
| 3417 | struct regcache *regs, |
| 3418 | struct displaced_step_closure *dsc) |
| 3419 | { |
| 3420 | ULONGEST rd_val = displaced_read_reg (regs, dsc->insn_addr, 0); |
| 3421 | int i; |
| 3422 | |
| 3423 | for (i = 0; i < 4; i++) |
| 3424 | displaced_write_reg (regs, dsc, i, dsc->tmp[i], CANNOT_WRITE_PC); |
| 3425 | |
| 3426 | displaced_write_reg (regs, dsc, dsc->rd, rd_val, ALU_WRITE_PC); |
| 3427 | } |
| 3428 | |
| 3429 | static int |
| 3430 | copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn, |
| 3431 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 3432 | { |
| 3433 | unsigned int rn = bits (insn, 16, 19); |
| 3434 | unsigned int rm = bits (insn, 0, 3); |
| 3435 | unsigned int rd = bits (insn, 12, 15); |
| 3436 | unsigned int rs = bits (insn, 8, 11); |
| 3437 | unsigned int op = bits (insn, 21, 24); |
| 3438 | int is_mov = (op == 0xd), i; |
| 3439 | ULONGEST rd_val, rn_val, rm_val, rs_val; |
| 3440 | CORE_ADDR from = dsc->insn_addr; |
| 3441 | |
| 3442 | if (!insn_references_pc (insn, 0x000fff0ful)) |
| 3443 | return copy_unmodified (gdbarch, insn, "ALU shifted reg", dsc); |
| 3444 | |
| 3445 | if (debug_displaced) |
| 3446 | fprintf_unfiltered (gdb_stdlog, "displaced: copying shifted reg %s insn " |
| 3447 | "%.8lx\n", is_mov ? "move" : "ALU", |
| 3448 | (unsigned long) insn); |
| 3449 | |
| 3450 | /* Instruction is of form: |
| 3451 | |
| 3452 | <op><cond> rd, [rn,] rm, <shift> rs |
| 3453 | |
| 3454 | Rewrite as: |
| 3455 | |
| 3456 | Preparation: tmp1, tmp2, tmp3, tmp4 <- r0, r1, r2, r3 |
| 3457 | r0, r1, r2, r3 <- rd, rn, rm, rs |
| 3458 | Insn: <op><cond> r0, r1, r2, <shift> r3 |
| 3459 | Cleanup: tmp5 <- r0 |
| 3460 | r0, r1, r2, r3 <- tmp1, tmp2, tmp3, tmp4 |
| 3461 | rd <- tmp5 |
| 3462 | */ |
| 3463 | |
| 3464 | for (i = 0; i < 4; i++) |
| 3465 | dsc->tmp[i] = displaced_read_reg (regs, from, i); |
| 3466 | |
| 3467 | rd_val = displaced_read_reg (regs, from, rd); |
| 3468 | rn_val = displaced_read_reg (regs, from, rn); |
| 3469 | rm_val = displaced_read_reg (regs, from, rm); |
| 3470 | rs_val = displaced_read_reg (regs, from, rs); |
| 3471 | displaced_write_reg (regs, dsc, 0, rd_val, CANNOT_WRITE_PC); |
| 3472 | displaced_write_reg (regs, dsc, 1, rn_val, CANNOT_WRITE_PC); |
| 3473 | displaced_write_reg (regs, dsc, 2, rm_val, CANNOT_WRITE_PC); |
| 3474 | displaced_write_reg (regs, dsc, 3, rs_val, CANNOT_WRITE_PC); |
| 3475 | dsc->rd = rd; |
| 3476 | |
| 3477 | if (is_mov) |
| 3478 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x302; |
| 3479 | else |
| 3480 | dsc->modinsn[0] = (insn & 0xfff000f0) | 0x10302; |
| 3481 | |
| 3482 | dsc->cleanup = &cleanup_alu_shifted_reg; |
| 3483 | |
| 3484 | return 0; |
| 3485 | } |
| 3486 | |
| 3487 | /* Clean up load instructions. */ |
| 3488 | |
| 3489 | static void |
| 3490 | cleanup_load (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, struct regcache *regs, |
| 3491 | struct displaced_step_closure *dsc) |
| 3492 | { |
| 3493 | ULONGEST rt_val, rt_val2 = 0, rn_val; |
| 3494 | CORE_ADDR from = dsc->insn_addr; |
| 3495 | |
| 3496 | rt_val = displaced_read_reg (regs, from, 0); |
| 3497 | if (dsc->u.ldst.xfersize == 8) |
| 3498 | rt_val2 = displaced_read_reg (regs, from, 1); |
| 3499 | rn_val = displaced_read_reg (regs, from, 2); |
| 3500 | |
| 3501 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
| 3502 | if (dsc->u.ldst.xfersize > 4) |
| 3503 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); |
| 3504 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); |
| 3505 | if (!dsc->u.ldst.immed) |
| 3506 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); |
| 3507 | |
| 3508 | /* Handle register writeback. */ |
| 3509 | if (dsc->u.ldst.writeback) |
| 3510 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); |
| 3511 | /* Put result in right place. */ |
| 3512 | displaced_write_reg (regs, dsc, dsc->rd, rt_val, LOAD_WRITE_PC); |
| 3513 | if (dsc->u.ldst.xfersize == 8) |
| 3514 | displaced_write_reg (regs, dsc, dsc->rd + 1, rt_val2, LOAD_WRITE_PC); |
| 3515 | } |
| 3516 | |
| 3517 | /* Clean up store instructions. */ |
| 3518 | |
| 3519 | static void |
| 3520 | cleanup_store (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, struct regcache *regs, |
| 3521 | struct displaced_step_closure *dsc) |
| 3522 | { |
| 3523 | CORE_ADDR from = dsc->insn_addr; |
| 3524 | ULONGEST rn_val = displaced_read_reg (regs, from, 2); |
| 3525 | |
| 3526 | displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC); |
| 3527 | if (dsc->u.ldst.xfersize > 4) |
| 3528 | displaced_write_reg (regs, dsc, 1, dsc->tmp[1], CANNOT_WRITE_PC); |
| 3529 | displaced_write_reg (regs, dsc, 2, dsc->tmp[2], CANNOT_WRITE_PC); |
| 3530 | if (!dsc->u.ldst.immed) |
| 3531 | displaced_write_reg (regs, dsc, 3, dsc->tmp[3], CANNOT_WRITE_PC); |
| 3532 | if (!dsc->u.ldst.restore_r4) |
| 3533 | displaced_write_reg (regs, dsc, 4, dsc->tmp[4], CANNOT_WRITE_PC); |
| 3534 | |
| 3535 | /* Writeback. */ |
| 3536 | if (dsc->u.ldst.writeback) |
| 3537 | displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, CANNOT_WRITE_PC); |
| 3538 | } |
| 3539 | |
| 3540 | /* Copy "extra" load/store instructions. These are halfword/doubleword |
| 3541 | transfers, which have a different encoding to byte/word transfers. */ |
| 3542 | |
| 3543 | static int |
| 3544 | copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged, |
| 3545 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 3546 | { |
| 3547 | unsigned int op1 = bits (insn, 20, 24); |
| 3548 | unsigned int op2 = bits (insn, 5, 6); |
| 3549 | unsigned int rt = bits (insn, 12, 15); |
| 3550 | unsigned int rn = bits (insn, 16, 19); |
| 3551 | unsigned int rm = bits (insn, 0, 3); |
| 3552 | char load[12] = {0, 1, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1}; |
| 3553 | char bytesize[12] = {2, 2, 2, 2, 8, 1, 8, 1, 8, 2, 8, 2}; |
| 3554 | int immed = (op1 & 0x4) != 0; |
| 3555 | int opcode; |
| 3556 | ULONGEST rt_val, rt_val2 = 0, rn_val, rm_val = 0; |
| 3557 | CORE_ADDR from = dsc->insn_addr; |
| 3558 | |
| 3559 | if (!insn_references_pc (insn, 0x000ff00ful)) |
| 3560 | return copy_unmodified (gdbarch, insn, "extra load/store", dsc); |
| 3561 | |
| 3562 | if (debug_displaced) |
| 3563 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store " |
| 3564 | "insn %.8lx\n", unpriveleged ? "unpriveleged " : "", |
| 3565 | (unsigned long) insn); |
| 3566 | |
| 3567 | opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; |
| 3568 | |
| 3569 | if (opcode < 0) |
| 3570 | internal_error (__FILE__, __LINE__, |
| 3571 | _("copy_extra_ld_st: instruction decode error")); |
| 3572 | |
| 3573 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); |
| 3574 | dsc->tmp[1] = displaced_read_reg (regs, from, 1); |
| 3575 | dsc->tmp[2] = displaced_read_reg (regs, from, 2); |
| 3576 | if (!immed) |
| 3577 | dsc->tmp[3] = displaced_read_reg (regs, from, 3); |
| 3578 | |
| 3579 | rt_val = displaced_read_reg (regs, from, rt); |
| 3580 | if (bytesize[opcode] == 8) |
| 3581 | rt_val2 = displaced_read_reg (regs, from, rt + 1); |
| 3582 | rn_val = displaced_read_reg (regs, from, rn); |
| 3583 | if (!immed) |
| 3584 | rm_val = displaced_read_reg (regs, from, rm); |
| 3585 | |
| 3586 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); |
| 3587 | if (bytesize[opcode] == 8) |
| 3588 | displaced_write_reg (regs, dsc, 1, rt_val2, CANNOT_WRITE_PC); |
| 3589 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); |
| 3590 | if (!immed) |
| 3591 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); |
| 3592 | |
| 3593 | dsc->rd = rt; |
| 3594 | dsc->u.ldst.xfersize = bytesize[opcode]; |
| 3595 | dsc->u.ldst.rn = rn; |
| 3596 | dsc->u.ldst.immed = immed; |
| 3597 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; |
| 3598 | dsc->u.ldst.restore_r4 = 0; |
| 3599 | |
| 3600 | if (immed) |
| 3601 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, #imm] |
| 3602 | -> |
| 3603 | {ldr,str}<width><cond> r0, [r1,] [r2, #imm]. */ |
| 3604 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; |
| 3605 | else |
| 3606 | /* {ldr,str}<width><cond> rt, [rt2,] [rn, +/-rm] |
| 3607 | -> |
| 3608 | {ldr,str}<width><cond> r0, [r1,] [r2, +/-r3]. */ |
| 3609 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; |
| 3610 | |
| 3611 | dsc->cleanup = load[opcode] ? &cleanup_load : &cleanup_store; |
| 3612 | |
| 3613 | return 0; |
| 3614 | } |
| 3615 | |
| 3616 | /* Copy byte/word loads and stores. */ |
| 3617 | |
| 3618 | static int |
| 3619 | copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn, |
| 3620 | struct regcache *regs, |
| 3621 | struct displaced_step_closure *dsc, int load, int byte, |
| 3622 | int usermode) |
| 3623 | { |
| 3624 | int immed = !bit (insn, 25); |
| 3625 | unsigned int rt = bits (insn, 12, 15); |
| 3626 | unsigned int rn = bits (insn, 16, 19); |
| 3627 | unsigned int rm = bits (insn, 0, 3); /* Only valid if !immed. */ |
| 3628 | ULONGEST rt_val, rn_val, rm_val = 0; |
| 3629 | CORE_ADDR from = dsc->insn_addr; |
| 3630 | |
| 3631 | if (!insn_references_pc (insn, 0x000ff00ful)) |
| 3632 | return copy_unmodified (gdbarch, insn, "load/store", dsc); |
| 3633 | |
| 3634 | if (debug_displaced) |
| 3635 | fprintf_unfiltered (gdb_stdlog, "displaced: copying %s%s insn %.8lx\n", |
| 3636 | load ? (byte ? "ldrb" : "ldr") |
| 3637 | : (byte ? "strb" : "str"), usermode ? "t" : "", |
| 3638 | (unsigned long) insn); |
| 3639 | |
| 3640 | dsc->tmp[0] = displaced_read_reg (regs, from, 0); |
| 3641 | dsc->tmp[2] = displaced_read_reg (regs, from, 2); |
| 3642 | if (!immed) |
| 3643 | dsc->tmp[3] = displaced_read_reg (regs, from, 3); |
| 3644 | if (!load) |
| 3645 | dsc->tmp[4] = displaced_read_reg (regs, from, 4); |
| 3646 | |
| 3647 | rt_val = displaced_read_reg (regs, from, rt); |
| 3648 | rn_val = displaced_read_reg (regs, from, rn); |
| 3649 | if (!immed) |
| 3650 | rm_val = displaced_read_reg (regs, from, rm); |
| 3651 | |
| 3652 | displaced_write_reg (regs, dsc, 0, rt_val, CANNOT_WRITE_PC); |
| 3653 | displaced_write_reg (regs, dsc, 2, rn_val, CANNOT_WRITE_PC); |
| 3654 | if (!immed) |
| 3655 | displaced_write_reg (regs, dsc, 3, rm_val, CANNOT_WRITE_PC); |
| 3656 | |
| 3657 | dsc->rd = rt; |
| 3658 | dsc->u.ldst.xfersize = byte ? 1 : 4; |
| 3659 | dsc->u.ldst.rn = rn; |
| 3660 | dsc->u.ldst.immed = immed; |
| 3661 | dsc->u.ldst.writeback = bit (insn, 24) == 0 || bit (insn, 21) != 0; |
| 3662 | |
| 3663 | /* To write PC we can do: |
| 3664 | |
| 3665 | scratch+0: str pc, temp (*temp = scratch + 8 + offset) |
| 3666 | scratch+4: ldr r4, temp |
| 3667 | scratch+8: sub r4, r4, pc (r4 = scratch + 8 + offset - scratch - 8 - 8) |
| 3668 | scratch+12: add r4, r4, #8 (r4 = offset) |
| 3669 | scratch+16: add r0, r0, r4 |
| 3670 | scratch+20: str r0, [r2, #imm] (or str r0, [r2, r3]) |
| 3671 | scratch+24: <temp> |
| 3672 | |
| 3673 | Otherwise we don't know what value to write for PC, since the offset is |
| 3674 | architecture-dependent (sometimes PC+8, sometimes PC+12). */ |
| 3675 | |
| 3676 | if (load || rt != 15) |
| 3677 | { |
| 3678 | dsc->u.ldst.restore_r4 = 0; |
| 3679 | |
| 3680 | if (immed) |
| 3681 | /* {ldr,str}[b]<cond> rt, [rn, #imm], etc. |
| 3682 | -> |
| 3683 | {ldr,str}[b]<cond> r0, [r2, #imm]. */ |
| 3684 | dsc->modinsn[0] = (insn & 0xfff00fff) | 0x20000; |
| 3685 | else |
| 3686 | /* {ldr,str}[b]<cond> rt, [rn, rm], etc. |
| 3687 | -> |
| 3688 | {ldr,str}[b]<cond> r0, [r2, r3]. */ |
| 3689 | dsc->modinsn[0] = (insn & 0xfff00ff0) | 0x20003; |
| 3690 | } |
| 3691 | else |
| 3692 | { |
| 3693 | /* We need to use r4 as scratch. Make sure it's restored afterwards. */ |
| 3694 | dsc->u.ldst.restore_r4 = 1; |
| 3695 | |
| 3696 | dsc->modinsn[0] = 0xe58ff014; /* str pc, [pc, #20]. */ |
| 3697 | dsc->modinsn[1] = 0xe59f4010; /* ldr r4, [pc, #16]. */ |
| 3698 | dsc->modinsn[2] = 0xe044400f; /* sub r4, r4, pc. */ |
| 3699 | dsc->modinsn[3] = 0xe2844008; /* add r4, r4, #8. */ |
| 3700 | dsc->modinsn[4] = 0xe0800004; /* add r0, r0, r4. */ |
| 3701 | |
| 3702 | /* As above. */ |
| 3703 | if (immed) |
| 3704 | dsc->modinsn[5] = (insn & 0xfff00fff) | 0x20000; |
| 3705 | else |
| 3706 | dsc->modinsn[5] = (insn & 0xfff00ff0) | 0x20003; |
| 3707 | |
| 3708 | dsc->modinsn[6] = 0x0; /* breakpoint location. */ |
| 3709 | dsc->modinsn[7] = 0x0; /* scratch space. */ |
| 3710 | |
| 3711 | dsc->numinsns = 6; |
| 3712 | } |
| 3713 | |
| 3714 | dsc->cleanup = load ? &cleanup_load : &cleanup_store; |
| 3715 | |
| 3716 | return 0; |
| 3717 | } |
| 3718 | |
| 3719 | /* Cleanup LDM instructions with fully-populated register list. This is an |
| 3720 | unfortunate corner case: it's impossible to implement correctly by modifying |
| 3721 | the instruction. The issue is as follows: we have an instruction, |
| 3722 | |
| 3723 | ldm rN, {r0-r15} |
| 3724 | |
| 3725 | which we must rewrite to avoid loading PC. A possible solution would be to |
| 3726 | do the load in two halves, something like (with suitable cleanup |
| 3727 | afterwards): |
| 3728 | |
| 3729 | mov r8, rN |
| 3730 | ldm[id][ab] r8!, {r0-r7} |
| 3731 | str r7, <temp> |
| 3732 | ldm[id][ab] r8, {r7-r14} |
| 3733 | <bkpt> |
| 3734 | |
| 3735 | but at present there's no suitable place for <temp>, since the scratch space |
| 3736 | is overwritten before the cleanup routine is called. For now, we simply |
| 3737 | emulate the instruction. */ |
| 3738 | |
| 3739 | static void |
| 3740 | cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs, |
| 3741 | struct displaced_step_closure *dsc) |
| 3742 | { |
| 3743 | ULONGEST from = dsc->insn_addr; |
| 3744 | int inc = dsc->u.block.increment; |
| 3745 | int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0; |
| 3746 | int bump_after = dsc->u.block.before ? 0 : (inc ? 4 : -4); |
| 3747 | uint32_t regmask = dsc->u.block.regmask; |
| 3748 | int regno = inc ? 0 : 15; |
| 3749 | CORE_ADDR xfer_addr = dsc->u.block.xfer_addr; |
| 3750 | int exception_return = dsc->u.block.load && dsc->u.block.user |
| 3751 | && (regmask & 0x8000) != 0; |
| 3752 | uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); |
| 3753 | int do_transfer = condition_true (dsc->u.block.cond, status); |
| 3754 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3755 | |
| 3756 | if (!do_transfer) |
| 3757 | return; |
| 3758 | |
| 3759 | /* If the instruction is ldm rN, {...pc}^, I don't think there's anything |
| 3760 | sensible we can do here. Complain loudly. */ |
| 3761 | if (exception_return) |
| 3762 | error (_("Cannot single-step exception return")); |
| 3763 | |
| 3764 | /* We don't handle any stores here for now. */ |
| 3765 | gdb_assert (dsc->u.block.load != 0); |
| 3766 | |
| 3767 | if (debug_displaced) |
| 3768 | fprintf_unfiltered (gdb_stdlog, "displaced: emulating block transfer: " |
| 3769 | "%s %s %s\n", dsc->u.block.load ? "ldm" : "stm", |
| 3770 | dsc->u.block.increment ? "inc" : "dec", |
| 3771 | dsc->u.block.before ? "before" : "after"); |
| 3772 | |
| 3773 | while (regmask) |
| 3774 | { |
| 3775 | uint32_t memword; |
| 3776 | |
| 3777 | if (inc) |
| 3778 | while (regno <= 15 && (regmask & (1 << regno)) == 0) |
| 3779 | regno++; |
| 3780 | else |
| 3781 | while (regno >= 0 && (regmask & (1 << regno)) == 0) |
| 3782 | regno--; |
| 3783 | |
| 3784 | xfer_addr += bump_before; |
| 3785 | |
| 3786 | memword = read_memory_unsigned_integer (xfer_addr, 4, byte_order); |
| 3787 | displaced_write_reg (regs, dsc, regno, memword, LOAD_WRITE_PC); |
| 3788 | |
| 3789 | xfer_addr += bump_after; |
| 3790 | |
| 3791 | regmask &= ~(1 << regno); |
| 3792 | } |
| 3793 | |
| 3794 | if (dsc->u.block.writeback) |
| 3795 | displaced_write_reg (regs, dsc, dsc->u.block.rn, xfer_addr, |
| 3796 | CANNOT_WRITE_PC); |
| 3797 | } |
| 3798 | |
| 3799 | /* Clean up an STM which included the PC in the register list. */ |
| 3800 | |
| 3801 | static void |
| 3802 | cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs, |
| 3803 | struct displaced_step_closure *dsc) |
| 3804 | { |
| 3805 | ULONGEST from = dsc->insn_addr; |
| 3806 | uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); |
| 3807 | int store_executed = condition_true (dsc->u.block.cond, status); |
| 3808 | CORE_ADDR pc_stored_at, transferred_regs = bitcount (dsc->u.block.regmask); |
| 3809 | CORE_ADDR stm_insn_addr; |
| 3810 | uint32_t pc_val; |
| 3811 | long offset; |
| 3812 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3813 | |
| 3814 | /* If condition code fails, there's nothing else to do. */ |
| 3815 | if (!store_executed) |
| 3816 | return; |
| 3817 | |
| 3818 | if (dsc->u.block.increment) |
| 3819 | { |
| 3820 | pc_stored_at = dsc->u.block.xfer_addr + 4 * transferred_regs; |
| 3821 | |
| 3822 | if (dsc->u.block.before) |
| 3823 | pc_stored_at += 4; |
| 3824 | } |
| 3825 | else |
| 3826 | { |
| 3827 | pc_stored_at = dsc->u.block.xfer_addr; |
| 3828 | |
| 3829 | if (dsc->u.block.before) |
| 3830 | pc_stored_at -= 4; |
| 3831 | } |
| 3832 | |
| 3833 | pc_val = read_memory_unsigned_integer (pc_stored_at, 4, byte_order); |
| 3834 | stm_insn_addr = dsc->scratch_base; |
| 3835 | offset = pc_val - stm_insn_addr; |
| 3836 | |
| 3837 | if (debug_displaced) |
| 3838 | fprintf_unfiltered (gdb_stdlog, "displaced: detected PC offset %.8lx for " |
| 3839 | "STM instruction\n", offset); |
| 3840 | |
| 3841 | /* Rewrite the stored PC to the proper value for the non-displaced original |
| 3842 | instruction. */ |
| 3843 | write_memory_unsigned_integer (pc_stored_at, 4, byte_order, |
| 3844 | dsc->insn_addr + offset); |
| 3845 | } |
| 3846 | |
| 3847 | /* Clean up an LDM which includes the PC in the register list. We clumped all |
| 3848 | the registers in the transferred list into a contiguous range r0...rX (to |
| 3849 | avoid loading PC directly and losing control of the debugged program), so we |
| 3850 | must undo that here. */ |
| 3851 | |
| 3852 | static void |
| 3853 | cleanup_block_load_pc (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, |
| 3854 | struct regcache *regs, |
| 3855 | struct displaced_step_closure *dsc) |
| 3856 | { |
| 3857 | ULONGEST from = dsc->insn_addr; |
| 3858 | uint32_t status = displaced_read_reg (regs, from, ARM_PS_REGNUM); |
| 3859 | int load_executed = condition_true (dsc->u.block.cond, status), i; |
| 3860 | unsigned int mask = dsc->u.block.regmask, write_reg = 15; |
| 3861 | unsigned int regs_loaded = bitcount (mask); |
| 3862 | unsigned int num_to_shuffle = regs_loaded, clobbered; |
| 3863 | |
| 3864 | /* The method employed here will fail if the register list is fully populated |
| 3865 | (we need to avoid loading PC directly). */ |
| 3866 | gdb_assert (num_to_shuffle < 16); |
| 3867 | |
| 3868 | if (!load_executed) |
| 3869 | return; |
| 3870 | |
| 3871 | clobbered = (1 << num_to_shuffle) - 1; |
| 3872 | |
| 3873 | while (num_to_shuffle > 0) |
| 3874 | { |
| 3875 | if ((mask & (1 << write_reg)) != 0) |
| 3876 | { |
| 3877 | unsigned int read_reg = num_to_shuffle - 1; |
| 3878 | |
| 3879 | if (read_reg != write_reg) |
| 3880 | { |
| 3881 | ULONGEST rval = displaced_read_reg (regs, from, read_reg); |
| 3882 | displaced_write_reg (regs, dsc, write_reg, rval, LOAD_WRITE_PC); |
| 3883 | if (debug_displaced) |
| 3884 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: move " |
| 3885 | "loaded register r%d to r%d\n"), read_reg, |
| 3886 | write_reg); |
| 3887 | } |
| 3888 | else if (debug_displaced) |
| 3889 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: register " |
| 3890 | "r%d already in the right place\n"), |
| 3891 | write_reg); |
| 3892 | |
| 3893 | clobbered &= ~(1 << write_reg); |
| 3894 | |
| 3895 | num_to_shuffle--; |
| 3896 | } |
| 3897 | |
| 3898 | write_reg--; |
| 3899 | } |
| 3900 | |
| 3901 | /* Restore any registers we scribbled over. */ |
| 3902 | for (write_reg = 0; clobbered != 0; write_reg++) |
| 3903 | { |
| 3904 | if ((clobbered & (1 << write_reg)) != 0) |
| 3905 | { |
| 3906 | displaced_write_reg (regs, dsc, write_reg, dsc->tmp[write_reg], |
| 3907 | CANNOT_WRITE_PC); |
| 3908 | if (debug_displaced) |
| 3909 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM: restored " |
| 3910 | "clobbered register r%d\n"), write_reg); |
| 3911 | clobbered &= ~(1 << write_reg); |
| 3912 | } |
| 3913 | } |
| 3914 | |
| 3915 | /* Perform register writeback manually. */ |
| 3916 | if (dsc->u.block.writeback) |
| 3917 | { |
| 3918 | ULONGEST new_rn_val = dsc->u.block.xfer_addr; |
| 3919 | |
| 3920 | if (dsc->u.block.increment) |
| 3921 | new_rn_val += regs_loaded * 4; |
| 3922 | else |
| 3923 | new_rn_val -= regs_loaded * 4; |
| 3924 | |
| 3925 | displaced_write_reg (regs, dsc, dsc->u.block.rn, new_rn_val, |
| 3926 | CANNOT_WRITE_PC); |
| 3927 | } |
| 3928 | } |
| 3929 | |
| 3930 | /* Handle ldm/stm, apart from some tricky cases which are unlikely to occur |
| 3931 | in user-level code (in particular exception return, ldm rn, {...pc}^). */ |
| 3932 | |
| 3933 | static int |
| 3934 | copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
| 3935 | struct displaced_step_closure *dsc) |
| 3936 | { |
| 3937 | int load = bit (insn, 20); |
| 3938 | int user = bit (insn, 22); |
| 3939 | int increment = bit (insn, 23); |
| 3940 | int before = bit (insn, 24); |
| 3941 | int writeback = bit (insn, 21); |
| 3942 | int rn = bits (insn, 16, 19); |
| 3943 | CORE_ADDR from = dsc->insn_addr; |
| 3944 | |
| 3945 | /* Block transfers which don't mention PC can be run directly out-of-line. */ |
| 3946 | if (rn != 15 && (insn & 0x8000) == 0) |
| 3947 | return copy_unmodified (gdbarch, insn, "ldm/stm", dsc); |
| 3948 | |
| 3949 | if (rn == 15) |
| 3950 | { |
| 3951 | warning (_("displaced: Unpredictable LDM or STM with base register r15")); |
| 3952 | return copy_unmodified (gdbarch, insn, "unpredictable ldm/stm", dsc); |
| 3953 | } |
| 3954 | |
| 3955 | if (debug_displaced) |
| 3956 | fprintf_unfiltered (gdb_stdlog, "displaced: copying block transfer insn " |
| 3957 | "%.8lx\n", (unsigned long) insn); |
| 3958 | |
| 3959 | dsc->u.block.xfer_addr = displaced_read_reg (regs, from, rn); |
| 3960 | dsc->u.block.rn = rn; |
| 3961 | |
| 3962 | dsc->u.block.load = load; |
| 3963 | dsc->u.block.user = user; |
| 3964 | dsc->u.block.increment = increment; |
| 3965 | dsc->u.block.before = before; |
| 3966 | dsc->u.block.writeback = writeback; |
| 3967 | dsc->u.block.cond = bits (insn, 28, 31); |
| 3968 | |
| 3969 | dsc->u.block.regmask = insn & 0xffff; |
| 3970 | |
| 3971 | if (load) |
| 3972 | { |
| 3973 | if ((insn & 0xffff) == 0xffff) |
| 3974 | { |
| 3975 | /* LDM with a fully-populated register list. This case is |
| 3976 | particularly tricky. Implement for now by fully emulating the |
| 3977 | instruction (which might not behave perfectly in all cases, but |
| 3978 | these instructions should be rare enough for that not to matter |
| 3979 | too much). */ |
| 3980 | dsc->modinsn[0] = ARM_NOP; |
| 3981 | |
| 3982 | dsc->cleanup = &cleanup_block_load_all; |
| 3983 | } |
| 3984 | else |
| 3985 | { |
| 3986 | /* LDM of a list of registers which includes PC. Implement by |
| 3987 | rewriting the list of registers to be transferred into a |
| 3988 | contiguous chunk r0...rX before doing the transfer, then shuffling |
| 3989 | registers into the correct places in the cleanup routine. */ |
| 3990 | unsigned int regmask = insn & 0xffff; |
| 3991 | unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1; |
| 3992 | unsigned int to = 0, from = 0, i, new_rn; |
| 3993 | |
| 3994 | for (i = 0; i < num_in_list; i++) |
| 3995 | dsc->tmp[i] = displaced_read_reg (regs, from, i); |
| 3996 | |
| 3997 | /* Writeback makes things complicated. We need to avoid clobbering |
| 3998 | the base register with one of the registers in our modified |
| 3999 | register list, but just using a different register can't work in |
| 4000 | all cases, e.g.: |
| 4001 | |
| 4002 | ldm r14!, {r0-r13,pc} |
| 4003 | |
| 4004 | which would need to be rewritten as: |
| 4005 | |
| 4006 | ldm rN!, {r0-r14} |
| 4007 | |
| 4008 | but that can't work, because there's no free register for N. |
| 4009 | |
| 4010 | Solve this by turning off the writeback bit, and emulating |
| 4011 | writeback manually in the cleanup routine. */ |
| 4012 | |
| 4013 | if (writeback) |
| 4014 | insn &= ~(1 << 21); |
| 4015 | |
| 4016 | new_regmask = (1 << num_in_list) - 1; |
| 4017 | |
| 4018 | if (debug_displaced) |
| 4019 | fprintf_unfiltered (gdb_stdlog, _("displaced: LDM r%d%s, " |
| 4020 | "{..., pc}: original reg list %.4x, modified " |
| 4021 | "list %.4x\n"), rn, writeback ? "!" : "", |
| 4022 | (int) insn & 0xffff, new_regmask); |
| 4023 | |
| 4024 | dsc->modinsn[0] = (insn & ~0xffff) | (new_regmask & 0xffff); |
| 4025 | |
| 4026 | dsc->cleanup = &cleanup_block_load_pc; |
| 4027 | } |
| 4028 | } |
| 4029 | else |
| 4030 | { |
| 4031 | /* STM of a list of registers which includes PC. Run the instruction |
| 4032 | as-is, but out of line: this will store the wrong value for the PC, |
| 4033 | so we must manually fix up the memory in the cleanup routine. |
| 4034 | Doing things this way has the advantage that we can auto-detect |
| 4035 | the offset of the PC write (which is architecture-dependent) in |
| 4036 | the cleanup routine. */ |
| 4037 | dsc->modinsn[0] = insn; |
| 4038 | |
| 4039 | dsc->cleanup = &cleanup_block_store_pc; |
| 4040 | } |
| 4041 | |
| 4042 | return 0; |
| 4043 | } |
| 4044 | |
| 4045 | /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden |
| 4046 | for Linux, where some SVC instructions must be treated specially. */ |
| 4047 | |
| 4048 | static void |
| 4049 | cleanup_svc (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, struct regcache *regs, |
| 4050 | struct displaced_step_closure *dsc) |
| 4051 | { |
| 4052 | CORE_ADDR from = dsc->insn_addr; |
| 4053 | CORE_ADDR resume_addr = from + 4; |
| 4054 | |
| 4055 | if (debug_displaced) |
| 4056 | fprintf_unfiltered (gdb_stdlog, "displaced: cleanup for svc, resume at " |
| 4057 | "%.8lx\n", (unsigned long) resume_addr); |
| 4058 | |
| 4059 | displaced_write_reg (regs, dsc, ARM_PC_REGNUM, resume_addr, BRANCH_WRITE_PC); |
| 4060 | } |
| 4061 | |
| 4062 | static int |
| 4063 | copy_svc (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, |
| 4064 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 4065 | { |
| 4066 | CORE_ADDR from = dsc->insn_addr; |
| 4067 | |
| 4068 | /* Allow OS-specific code to override SVC handling. */ |
| 4069 | if (dsc->u.svc.copy_svc_os) |
| 4070 | return dsc->u.svc.copy_svc_os (gdbarch, insn, to, regs, dsc); |
| 4071 | |
| 4072 | if (debug_displaced) |
| 4073 | fprintf_unfiltered (gdb_stdlog, "displaced: copying svc insn %.8lx\n", |
| 4074 | (unsigned long) insn); |
| 4075 | |
| 4076 | /* Preparation: none. |
| 4077 | Insn: unmodified svc. |
| 4078 | Cleanup: pc <- insn_addr + 4. */ |
| 4079 | |
| 4080 | dsc->modinsn[0] = insn; |
| 4081 | |
| 4082 | dsc->cleanup = &cleanup_svc; |
| 4083 | /* Pretend we wrote to the PC, so cleanup doesn't set PC to the next |
| 4084 | instruction. */ |
| 4085 | dsc->wrote_to_pc = 1; |
| 4086 | |
| 4087 | return 0; |
| 4088 | } |
| 4089 | |
| 4090 | /* Copy undefined instructions. */ |
| 4091 | |
| 4092 | static int |
| 4093 | copy_undef (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, |
| 4094 | struct displaced_step_closure *dsc) |
| 4095 | { |
| 4096 | if (debug_displaced) |
| 4097 | fprintf_unfiltered (gdb_stdlog, "displaced: copying undefined insn %.8lx\n", |
| 4098 | (unsigned long) insn); |
| 4099 | |
| 4100 | dsc->modinsn[0] = insn; |
| 4101 | |
| 4102 | return 0; |
| 4103 | } |
| 4104 | |
| 4105 | /* Copy unpredictable instructions. */ |
| 4106 | |
| 4107 | static int |
| 4108 | copy_unpred (struct gdbarch *gdbarch ATTRIBUTE_UNUSED, uint32_t insn, |
| 4109 | struct displaced_step_closure *dsc) |
| 4110 | { |
| 4111 | if (debug_displaced) |
| 4112 | fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn " |
| 4113 | "%.8lx\n", (unsigned long) insn); |
| 4114 | |
| 4115 | dsc->modinsn[0] = insn; |
| 4116 | |
| 4117 | return 0; |
| 4118 | } |
| 4119 | |
| 4120 | /* The decode_* functions are instruction decoding helpers. They mostly follow |
| 4121 | the presentation in the ARM ARM. */ |
| 4122 | |
| 4123 | static int |
| 4124 | decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn, |
| 4125 | struct regcache *regs, |
| 4126 | struct displaced_step_closure *dsc) |
| 4127 | { |
| 4128 | unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7); |
| 4129 | unsigned int rn = bits (insn, 16, 19); |
| 4130 | |
| 4131 | if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0) |
| 4132 | return copy_unmodified (gdbarch, insn, "cps", dsc); |
| 4133 | else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1) |
| 4134 | return copy_unmodified (gdbarch, insn, "setend", dsc); |
| 4135 | else if ((op1 & 0x60) == 0x20) |
| 4136 | return copy_unmodified (gdbarch, insn, "neon dataproc", dsc); |
| 4137 | else if ((op1 & 0x71) == 0x40) |
| 4138 | return copy_unmodified (gdbarch, insn, "neon elt/struct load/store", dsc); |
| 4139 | else if ((op1 & 0x77) == 0x41) |
| 4140 | return copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
| 4141 | else if ((op1 & 0x77) == 0x45) |
| 4142 | return copy_preload (gdbarch, insn, regs, dsc); /* pli. */ |
| 4143 | else if ((op1 & 0x77) == 0x51) |
| 4144 | { |
| 4145 | if (rn != 0xf) |
| 4146 | return copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
| 4147 | else |
| 4148 | return copy_unpred (gdbarch, insn, dsc); |
| 4149 | } |
| 4150 | else if ((op1 & 0x77) == 0x55) |
| 4151 | return copy_preload (gdbarch, insn, regs, dsc); /* pld/pldw. */ |
| 4152 | else if (op1 == 0x57) |
| 4153 | switch (op2) |
| 4154 | { |
| 4155 | case 0x1: return copy_unmodified (gdbarch, insn, "clrex", dsc); |
| 4156 | case 0x4: return copy_unmodified (gdbarch, insn, "dsb", dsc); |
| 4157 | case 0x5: return copy_unmodified (gdbarch, insn, "dmb", dsc); |
| 4158 | case 0x6: return copy_unmodified (gdbarch, insn, "isb", dsc); |
| 4159 | default: return copy_unpred (gdbarch, insn, dsc); |
| 4160 | } |
| 4161 | else if ((op1 & 0x63) == 0x43) |
| 4162 | return copy_unpred (gdbarch, insn, dsc); |
| 4163 | else if ((op2 & 0x1) == 0x0) |
| 4164 | switch (op1 & ~0x80) |
| 4165 | { |
| 4166 | case 0x61: |
| 4167 | return copy_unmodified (gdbarch, insn, "unallocated mem hint", dsc); |
| 4168 | case 0x65: |
| 4169 | return copy_preload_reg (gdbarch, insn, regs, dsc); /* pli reg. */ |
| 4170 | case 0x71: case 0x75: |
| 4171 | /* pld/pldw reg. */ |
| 4172 | return copy_preload_reg (gdbarch, insn, regs, dsc); |
| 4173 | case 0x63: case 0x67: case 0x73: case 0x77: |
| 4174 | return copy_unpred (gdbarch, insn, dsc); |
| 4175 | default: |
| 4176 | return copy_undef (gdbarch, insn, dsc); |
| 4177 | } |
| 4178 | else |
| 4179 | return copy_undef (gdbarch, insn, dsc); /* Probably unreachable. */ |
| 4180 | } |
| 4181 | |
| 4182 | static int |
| 4183 | decode_unconditional (struct gdbarch *gdbarch, uint32_t insn, |
| 4184 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 4185 | { |
| 4186 | if (bit (insn, 27) == 0) |
| 4187 | return decode_misc_memhint_neon (gdbarch, insn, regs, dsc); |
| 4188 | /* Switch on bits: 0bxxxxx321xxx0xxxxxxxxxxxxxxxxxxxx. */ |
| 4189 | else switch (((insn & 0x7000000) >> 23) | ((insn & 0x100000) >> 20)) |
| 4190 | { |
| 4191 | case 0x0: case 0x2: |
| 4192 | return copy_unmodified (gdbarch, insn, "srs", dsc); |
| 4193 | |
| 4194 | case 0x1: case 0x3: |
| 4195 | return copy_unmodified (gdbarch, insn, "rfe", dsc); |
| 4196 | |
| 4197 | case 0x4: case 0x5: case 0x6: case 0x7: |
| 4198 | return copy_b_bl_blx (gdbarch, insn, regs, dsc); |
| 4199 | |
| 4200 | case 0x8: |
| 4201 | switch ((insn & 0xe00000) >> 21) |
| 4202 | { |
| 4203 | case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: |
| 4204 | /* stc/stc2. */ |
| 4205 | return copy_copro_load_store (gdbarch, insn, regs, dsc); |
| 4206 | |
| 4207 | case 0x2: |
| 4208 | return copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
| 4209 | |
| 4210 | default: |
| 4211 | return copy_undef (gdbarch, insn, dsc); |
| 4212 | } |
| 4213 | |
| 4214 | case 0x9: |
| 4215 | { |
| 4216 | int rn_f = (bits (insn, 16, 19) == 0xf); |
| 4217 | switch ((insn & 0xe00000) >> 21) |
| 4218 | { |
| 4219 | case 0x1: case 0x3: |
| 4220 | /* ldc/ldc2 imm (undefined for rn == pc). */ |
| 4221 | return rn_f ? copy_undef (gdbarch, insn, dsc) |
| 4222 | : copy_copro_load_store (gdbarch, insn, regs, dsc); |
| 4223 | |
| 4224 | case 0x2: |
| 4225 | return copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
| 4226 | |
| 4227 | case 0x4: case 0x5: case 0x6: case 0x7: |
| 4228 | /* ldc/ldc2 lit (undefined for rn != pc). */ |
| 4229 | return rn_f ? copy_copro_load_store (gdbarch, insn, regs, dsc) |
| 4230 | : copy_undef (gdbarch, insn, dsc); |
| 4231 | |
| 4232 | default: |
| 4233 | return copy_undef (gdbarch, insn, dsc); |
| 4234 | } |
| 4235 | } |
| 4236 | |
| 4237 | case 0xa: |
| 4238 | return copy_unmodified (gdbarch, insn, "stc/stc2", dsc); |
| 4239 | |
| 4240 | case 0xb: |
| 4241 | if (bits (insn, 16, 19) == 0xf) |
| 4242 | /* ldc/ldc2 lit. */ |
| 4243 | return copy_copro_load_store (gdbarch, insn, regs, dsc); |
| 4244 | else |
| 4245 | return copy_undef (gdbarch, insn, dsc); |
| 4246 | |
| 4247 | case 0xc: |
| 4248 | if (bit (insn, 4)) |
| 4249 | return copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
| 4250 | else |
| 4251 | return copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
| 4252 | |
| 4253 | case 0xd: |
| 4254 | if (bit (insn, 4)) |
| 4255 | return copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
| 4256 | else |
| 4257 | return copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
| 4258 | |
| 4259 | default: |
| 4260 | return copy_undef (gdbarch, insn, dsc); |
| 4261 | } |
| 4262 | } |
| 4263 | |
| 4264 | /* Decode miscellaneous instructions in dp/misc encoding space. */ |
| 4265 | |
| 4266 | static int |
| 4267 | decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, |
| 4268 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 4269 | { |
| 4270 | unsigned int op2 = bits (insn, 4, 6); |
| 4271 | unsigned int op = bits (insn, 21, 22); |
| 4272 | unsigned int op1 = bits (insn, 16, 19); |
| 4273 | |
| 4274 | switch (op2) |
| 4275 | { |
| 4276 | case 0x0: |
| 4277 | return copy_unmodified (gdbarch, insn, "mrs/msr", dsc); |
| 4278 | |
| 4279 | case 0x1: |
| 4280 | if (op == 0x1) /* bx. */ |
| 4281 | return copy_bx_blx_reg (gdbarch, insn, regs, dsc); |
| 4282 | else if (op == 0x3) |
| 4283 | return copy_unmodified (gdbarch, insn, "clz", dsc); |
| 4284 | else |
| 4285 | return copy_undef (gdbarch, insn, dsc); |
| 4286 | |
| 4287 | case 0x2: |
| 4288 | if (op == 0x1) |
| 4289 | /* Not really supported. */ |
| 4290 | return copy_unmodified (gdbarch, insn, "bxj", dsc); |
| 4291 | else |
| 4292 | return copy_undef (gdbarch, insn, dsc); |
| 4293 | |
| 4294 | case 0x3: |
| 4295 | if (op == 0x1) |
| 4296 | return copy_bx_blx_reg (gdbarch, insn, regs, dsc); /* blx register. */ |
| 4297 | else |
| 4298 | return copy_undef (gdbarch, insn, dsc); |
| 4299 | |
| 4300 | case 0x5: |
| 4301 | return copy_unmodified (gdbarch, insn, "saturating add/sub", dsc); |
| 4302 | |
| 4303 | case 0x7: |
| 4304 | if (op == 0x1) |
| 4305 | return copy_unmodified (gdbarch, insn, "bkpt", dsc); |
| 4306 | else if (op == 0x3) |
| 4307 | /* Not really supported. */ |
| 4308 | return copy_unmodified (gdbarch, insn, "smc", dsc); |
| 4309 | |
| 4310 | default: |
| 4311 | return copy_undef (gdbarch, insn, dsc); |
| 4312 | } |
| 4313 | } |
| 4314 | |
| 4315 | static int |
| 4316 | decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, |
| 4317 | struct displaced_step_closure *dsc) |
| 4318 | { |
| 4319 | if (bit (insn, 25)) |
| 4320 | switch (bits (insn, 20, 24)) |
| 4321 | { |
| 4322 | case 0x10: |
| 4323 | return copy_unmodified (gdbarch, insn, "movw", dsc); |
| 4324 | |
| 4325 | case 0x14: |
| 4326 | return copy_unmodified (gdbarch, insn, "movt", dsc); |
| 4327 | |
| 4328 | case 0x12: case 0x16: |
| 4329 | return copy_unmodified (gdbarch, insn, "msr imm", dsc); |
| 4330 | |
| 4331 | default: |
| 4332 | return copy_alu_imm (gdbarch, insn, regs, dsc); |
| 4333 | } |
| 4334 | else |
| 4335 | { |
| 4336 | uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); |
| 4337 | |
| 4338 | if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) |
| 4339 | return copy_alu_reg (gdbarch, insn, regs, dsc); |
| 4340 | else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) |
| 4341 | return copy_alu_shifted_reg (gdbarch, insn, regs, dsc); |
| 4342 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) |
| 4343 | return decode_miscellaneous (gdbarch, insn, regs, dsc); |
| 4344 | else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) |
| 4345 | return copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); |
| 4346 | else if ((op1 & 0x10) == 0x00 && op2 == 0x9) |
| 4347 | return copy_unmodified (gdbarch, insn, "mul/mla", dsc); |
| 4348 | else if ((op1 & 0x10) == 0x10 && op2 == 0x9) |
| 4349 | return copy_unmodified (gdbarch, insn, "synch", dsc); |
| 4350 | else if (op2 == 0xb || (op2 & 0xd) == 0xd) |
| 4351 | /* 2nd arg means "unpriveleged". */ |
| 4352 | return copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, |
| 4353 | dsc); |
| 4354 | } |
| 4355 | |
| 4356 | /* Should be unreachable. */ |
| 4357 | return 1; |
| 4358 | } |
| 4359 | |
| 4360 | static int |
| 4361 | decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, |
| 4362 | struct regcache *regs, |
| 4363 | struct displaced_step_closure *dsc) |
| 4364 | { |
| 4365 | int a = bit (insn, 25), b = bit (insn, 4); |
| 4366 | uint32_t op1 = bits (insn, 20, 24); |
| 4367 | int rn_f = bits (insn, 16, 19) == 0xf; |
| 4368 | |
| 4369 | if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) |
| 4370 | || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) |
| 4371 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 0, 0); |
| 4372 | else if ((!a && (op1 & 0x17) == 0x02) |
| 4373 | || (a && (op1 & 0x17) == 0x02 && !b)) |
| 4374 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 0, 1); |
| 4375 | else if ((!a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03) |
| 4376 | || (a && (op1 & 0x05) == 0x01 && (op1 & 0x17) != 0x03 && !b)) |
| 4377 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 0, 0); |
| 4378 | else if ((!a && (op1 & 0x17) == 0x03) |
| 4379 | || (a && (op1 & 0x17) == 0x03 && !b)) |
| 4380 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 0, 1); |
| 4381 | else if ((!a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06) |
| 4382 | || (a && (op1 & 0x05) == 0x04 && (op1 & 0x17) != 0x06 && !b)) |
| 4383 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 0); |
| 4384 | else if ((!a && (op1 & 0x17) == 0x06) |
| 4385 | || (a && (op1 & 0x17) == 0x06 && !b)) |
| 4386 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 0, 1, 1); |
| 4387 | else if ((!a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07) |
| 4388 | || (a && (op1 & 0x05) == 0x05 && (op1 & 0x17) != 0x07 && !b)) |
| 4389 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 0); |
| 4390 | else if ((!a && (op1 & 0x17) == 0x07) |
| 4391 | || (a && (op1 & 0x17) == 0x07 && !b)) |
| 4392 | return copy_ldr_str_ldrb_strb (gdbarch, insn, regs, dsc, 1, 1, 1); |
| 4393 | |
| 4394 | /* Should be unreachable. */ |
| 4395 | return 1; |
| 4396 | } |
| 4397 | |
| 4398 | static int |
| 4399 | decode_media (struct gdbarch *gdbarch, uint32_t insn, |
| 4400 | struct displaced_step_closure *dsc) |
| 4401 | { |
| 4402 | switch (bits (insn, 20, 24)) |
| 4403 | { |
| 4404 | case 0x00: case 0x01: case 0x02: case 0x03: |
| 4405 | return copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc); |
| 4406 | |
| 4407 | case 0x04: case 0x05: case 0x06: case 0x07: |
| 4408 | return copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc); |
| 4409 | |
| 4410 | case 0x08: case 0x09: case 0x0a: case 0x0b: |
| 4411 | case 0x0c: case 0x0d: case 0x0e: case 0x0f: |
| 4412 | return copy_unmodified (gdbarch, insn, |
| 4413 | "decode/pack/unpack/saturate/reverse", dsc); |
| 4414 | |
| 4415 | case 0x18: |
| 4416 | if (bits (insn, 5, 7) == 0) /* op2. */ |
| 4417 | { |
| 4418 | if (bits (insn, 12, 15) == 0xf) |
| 4419 | return copy_unmodified (gdbarch, insn, "usad8", dsc); |
| 4420 | else |
| 4421 | return copy_unmodified (gdbarch, insn, "usada8", dsc); |
| 4422 | } |
| 4423 | else |
| 4424 | return copy_undef (gdbarch, insn, dsc); |
| 4425 | |
| 4426 | case 0x1a: case 0x1b: |
| 4427 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ |
| 4428 | return copy_unmodified (gdbarch, insn, "sbfx", dsc); |
| 4429 | else |
| 4430 | return copy_undef (gdbarch, insn, dsc); |
| 4431 | |
| 4432 | case 0x1c: case 0x1d: |
| 4433 | if (bits (insn, 5, 6) == 0x0) /* op2[1:0]. */ |
| 4434 | { |
| 4435 | if (bits (insn, 0, 3) == 0xf) |
| 4436 | return copy_unmodified (gdbarch, insn, "bfc", dsc); |
| 4437 | else |
| 4438 | return copy_unmodified (gdbarch, insn, "bfi", dsc); |
| 4439 | } |
| 4440 | else |
| 4441 | return copy_undef (gdbarch, insn, dsc); |
| 4442 | |
| 4443 | case 0x1e: case 0x1f: |
| 4444 | if (bits (insn, 5, 6) == 0x2) /* op2[1:0]. */ |
| 4445 | return copy_unmodified (gdbarch, insn, "ubfx", dsc); |
| 4446 | else |
| 4447 | return copy_undef (gdbarch, insn, dsc); |
| 4448 | } |
| 4449 | |
| 4450 | /* Should be unreachable. */ |
| 4451 | return 1; |
| 4452 | } |
| 4453 | |
| 4454 | static int |
| 4455 | decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn, |
| 4456 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 4457 | { |
| 4458 | if (bit (insn, 25)) |
| 4459 | return copy_b_bl_blx (gdbarch, insn, regs, dsc); |
| 4460 | else |
| 4461 | return copy_block_xfer (gdbarch, insn, regs, dsc); |
| 4462 | } |
| 4463 | |
| 4464 | static int |
| 4465 | decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn, |
| 4466 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 4467 | { |
| 4468 | unsigned int opcode = bits (insn, 20, 24); |
| 4469 | |
| 4470 | switch (opcode) |
| 4471 | { |
| 4472 | case 0x04: case 0x05: /* VFP/Neon mrrc/mcrr. */ |
| 4473 | return copy_unmodified (gdbarch, insn, "vfp/neon mrrc/mcrr", dsc); |
| 4474 | |
| 4475 | case 0x08: case 0x0a: case 0x0c: case 0x0e: |
| 4476 | case 0x12: case 0x16: |
| 4477 | return copy_unmodified (gdbarch, insn, "vfp/neon vstm/vpush", dsc); |
| 4478 | |
| 4479 | case 0x09: case 0x0b: case 0x0d: case 0x0f: |
| 4480 | case 0x13: case 0x17: |
| 4481 | return copy_unmodified (gdbarch, insn, "vfp/neon vldm/vpop", dsc); |
| 4482 | |
| 4483 | case 0x10: case 0x14: case 0x18: case 0x1c: /* vstr. */ |
| 4484 | case 0x11: case 0x15: case 0x19: case 0x1d: /* vldr. */ |
| 4485 | /* Note: no writeback for these instructions. Bit 25 will always be |
| 4486 | zero though (via caller), so the following works OK. */ |
| 4487 | return copy_copro_load_store (gdbarch, insn, regs, dsc); |
| 4488 | } |
| 4489 | |
| 4490 | /* Should be unreachable. */ |
| 4491 | return 1; |
| 4492 | } |
| 4493 | |
| 4494 | static int |
| 4495 | decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, |
| 4496 | struct regcache *regs, struct displaced_step_closure *dsc) |
| 4497 | { |
| 4498 | unsigned int op1 = bits (insn, 20, 25); |
| 4499 | int op = bit (insn, 4); |
| 4500 | unsigned int coproc = bits (insn, 8, 11); |
| 4501 | unsigned int rn = bits (insn, 16, 19); |
| 4502 | |
| 4503 | if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) |
| 4504 | return decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); |
| 4505 | else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00 |
| 4506 | && (coproc & 0xe) != 0xa) |
| 4507 | /* stc/stc2. */ |
| 4508 | return copy_copro_load_store (gdbarch, insn, regs, dsc); |
| 4509 | else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00 |
| 4510 | && (coproc & 0xe) != 0xa) |
| 4511 | /* ldc/ldc2 imm/lit. */ |
| 4512 | return copy_copro_load_store (gdbarch, insn, regs, dsc); |
| 4513 | else if ((op1 & 0x3e) == 0x00) |
| 4514 | return copy_undef (gdbarch, insn, dsc); |
| 4515 | else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa) |
| 4516 | return copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc); |
| 4517 | else if (op1 == 0x04 && (coproc & 0xe) != 0xa) |
| 4518 | return copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc); |
| 4519 | else if (op1 == 0x05 && (coproc & 0xe) != 0xa) |
| 4520 | return copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc); |
| 4521 | else if ((op1 & 0x30) == 0x20 && !op) |
| 4522 | { |
| 4523 | if ((coproc & 0xe) == 0xa) |
| 4524 | return copy_unmodified (gdbarch, insn, "vfp dataproc", dsc); |
| 4525 | else |
| 4526 | return copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc); |
| 4527 | } |
| 4528 | else if ((op1 & 0x30) == 0x20 && op) |
| 4529 | return copy_unmodified (gdbarch, insn, "neon 8/16/32 bit xfer", dsc); |
| 4530 | else if ((op1 & 0x31) == 0x20 && op && (coproc & 0xe) != 0xa) |
| 4531 | return copy_unmodified (gdbarch, insn, "mcr/mcr2", dsc); |
| 4532 | else if ((op1 & 0x31) == 0x21 && op && (coproc & 0xe) != 0xa) |
| 4533 | return copy_unmodified (gdbarch, insn, "mrc/mrc2", dsc); |
| 4534 | else if ((op1 & 0x30) == 0x30) |
| 4535 | return copy_svc (gdbarch, insn, to, regs, dsc); |
| 4536 | else |
| 4537 | return copy_undef (gdbarch, insn, dsc); /* Possibly unreachable. */ |
| 4538 | } |
| 4539 | |
| 4540 | void |
| 4541 | arm_process_displaced_insn (struct gdbarch *gdbarch, uint32_t insn, |
| 4542 | CORE_ADDR from, CORE_ADDR to, struct regcache *regs, |
| 4543 | struct displaced_step_closure *dsc) |
| 4544 | { |
| 4545 | int err = 0; |
| 4546 | |
| 4547 | if (!displaced_in_arm_mode (regs)) |
| 4548 | error (_("Displaced stepping is only supported in ARM mode")); |
| 4549 | |
| 4550 | /* Most displaced instructions use a 1-instruction scratch space, so set this |
| 4551 | here and override below if/when necessary. */ |
| 4552 | dsc->numinsns = 1; |
| 4553 | dsc->insn_addr = from; |
| 4554 | dsc->scratch_base = to; |
| 4555 | dsc->cleanup = NULL; |
| 4556 | dsc->wrote_to_pc = 0; |
| 4557 | |
| 4558 | if ((insn & 0xf0000000) == 0xf0000000) |
| 4559 | err = decode_unconditional (gdbarch, insn, regs, dsc); |
| 4560 | else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) |
| 4561 | { |
| 4562 | case 0x0: case 0x1: case 0x2: case 0x3: |
| 4563 | err = decode_dp_misc (gdbarch, insn, regs, dsc); |
| 4564 | break; |
| 4565 | |
| 4566 | case 0x4: case 0x5: case 0x6: |
| 4567 | err = decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); |
| 4568 | break; |
| 4569 | |
| 4570 | case 0x7: |
| 4571 | err = decode_media (gdbarch, insn, dsc); |
| 4572 | break; |
| 4573 | |
| 4574 | case 0x8: case 0x9: case 0xa: case 0xb: |
| 4575 | err = decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); |
| 4576 | break; |
| 4577 | |
| 4578 | case 0xc: case 0xd: case 0xe: case 0xf: |
| 4579 | err = decode_svc_copro (gdbarch, insn, to, regs, dsc); |
| 4580 | break; |
| 4581 | } |
| 4582 | |
| 4583 | if (err) |
| 4584 | internal_error (__FILE__, __LINE__, |
| 4585 | _("arm_process_displaced_insn: Instruction decode error")); |
| 4586 | } |
| 4587 | |
| 4588 | /* Actually set up the scratch space for a displaced instruction. */ |
| 4589 | |
| 4590 | void |
| 4591 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, |
| 4592 | CORE_ADDR to, struct displaced_step_closure *dsc) |
| 4593 | { |
| 4594 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 4595 | unsigned int i; |
| 4596 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
| 4597 | |
| 4598 | /* Poke modified instruction(s). */ |
| 4599 | for (i = 0; i < dsc->numinsns; i++) |
| 4600 | { |
| 4601 | if (debug_displaced) |
| 4602 | fprintf_unfiltered (gdb_stdlog, "displaced: writing insn %.8lx at " |
| 4603 | "%.8lx\n", (unsigned long) dsc->modinsn[i], |
| 4604 | (unsigned long) to + i * 4); |
| 4605 | write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code, |
| 4606 | dsc->modinsn[i]); |
| 4607 | } |
| 4608 | |
| 4609 | /* Put breakpoint afterwards. */ |
| 4610 | write_memory (to + dsc->numinsns * 4, tdep->arm_breakpoint, |
| 4611 | tdep->arm_breakpoint_size); |
| 4612 | |
| 4613 | if (debug_displaced) |
| 4614 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", |
| 4615 | paddress (gdbarch, from), paddress (gdbarch, to)); |
| 4616 | } |
| 4617 | |
| 4618 | /* Entry point for copying an instruction into scratch space for displaced |
| 4619 | stepping. */ |
| 4620 | |
| 4621 | struct displaced_step_closure * |
| 4622 | arm_displaced_step_copy_insn (struct gdbarch *gdbarch, |
| 4623 | CORE_ADDR from, CORE_ADDR to, |
| 4624 | struct regcache *regs) |
| 4625 | { |
| 4626 | struct displaced_step_closure *dsc |
| 4627 | = xmalloc (sizeof (struct displaced_step_closure)); |
| 4628 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
| 4629 | uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); |
| 4630 | |
| 4631 | if (debug_displaced) |
| 4632 | fprintf_unfiltered (gdb_stdlog, "displaced: stepping insn %.8lx " |
| 4633 | "at %.8lx\n", (unsigned long) insn, |
| 4634 | (unsigned long) from); |
| 4635 | |
| 4636 | arm_process_displaced_insn (gdbarch, insn, from, to, regs, dsc); |
| 4637 | arm_displaced_init_closure (gdbarch, from, to, dsc); |
| 4638 | |
| 4639 | return dsc; |
| 4640 | } |
| 4641 | |
| 4642 | /* Entry point for cleaning things up after a displaced instruction has been |
| 4643 | single-stepped. */ |
| 4644 | |
| 4645 | void |
| 4646 | arm_displaced_step_fixup (struct gdbarch *gdbarch, |
| 4647 | struct displaced_step_closure *dsc, |
| 4648 | CORE_ADDR from, CORE_ADDR to, |
| 4649 | struct regcache *regs) |
| 4650 | { |
| 4651 | if (dsc->cleanup) |
| 4652 | dsc->cleanup (gdbarch, regs, dsc); |
| 4653 | |
| 4654 | if (!dsc->wrote_to_pc) |
| 4655 | regcache_cooked_write_unsigned (regs, ARM_PC_REGNUM, dsc->insn_addr + 4); |
| 4656 | } |
| 4657 | |
| 4658 | #include "bfd-in2.h" |
| 4659 | #include "libcoff.h" |
| 4660 | |
| 4661 | static int |
| 4662 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
| 4663 | { |
| 4664 | if (arm_pc_is_thumb (memaddr)) |
| 4665 | { |
| 4666 | static asymbol *asym; |
| 4667 | static combined_entry_type ce; |
| 4668 | static struct coff_symbol_struct csym; |
| 4669 | static struct bfd fake_bfd; |
| 4670 | static bfd_target fake_target; |
| 4671 | |
| 4672 | if (csym.native == NULL) |
| 4673 | { |
| 4674 | /* Create a fake symbol vector containing a Thumb symbol. |
| 4675 | This is solely so that the code in print_insn_little_arm() |
| 4676 | and print_insn_big_arm() in opcodes/arm-dis.c will detect |
| 4677 | the presence of a Thumb symbol and switch to decoding |
| 4678 | Thumb instructions. */ |
| 4679 | |
| 4680 | fake_target.flavour = bfd_target_coff_flavour; |
| 4681 | fake_bfd.xvec = &fake_target; |
| 4682 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
| 4683 | csym.native = &ce; |
| 4684 | csym.symbol.the_bfd = &fake_bfd; |
| 4685 | csym.symbol.name = "fake"; |
| 4686 | asym = (asymbol *) & csym; |
| 4687 | } |
| 4688 | |
| 4689 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
| 4690 | info->symbols = &asym; |
| 4691 | } |
| 4692 | else |
| 4693 | info->symbols = NULL; |
| 4694 | |
| 4695 | if (info->endian == BFD_ENDIAN_BIG) |
| 4696 | return print_insn_big_arm (memaddr, info); |
| 4697 | else |
| 4698 | return print_insn_little_arm (memaddr, info); |
| 4699 | } |
| 4700 | |
| 4701 | /* The following define instruction sequences that will cause ARM |
| 4702 | cpu's to take an undefined instruction trap. These are used to |
| 4703 | signal a breakpoint to GDB. |
| 4704 | |
| 4705 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb |
| 4706 | modes. A different instruction is required for each mode. The ARM |
| 4707 | cpu's can also be big or little endian. Thus four different |
| 4708 | instructions are needed to support all cases. |
| 4709 | |
| 4710 | Note: ARMv4 defines several new instructions that will take the |
| 4711 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does |
| 4712 | not in fact add the new instructions. The new undefined |
| 4713 | instructions in ARMv4 are all instructions that had no defined |
| 4714 | behaviour in earlier chips. There is no guarantee that they will |
| 4715 | raise an exception, but may be treated as NOP's. In practice, it |
| 4716 | may only safe to rely on instructions matching: |
| 4717 | |
| 4718 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
| 4719 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
| 4720 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x |
| 4721 | |
| 4722 | Even this may only true if the condition predicate is true. The |
| 4723 | following use a condition predicate of ALWAYS so it is always TRUE. |
| 4724 | |
| 4725 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, |
| 4726 | and NetBSD all use a software interrupt rather than an undefined |
| 4727 | instruction to force a trap. This can be handled by by the |
| 4728 | abi-specific code during establishment of the gdbarch vector. */ |
| 4729 | |
| 4730 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} |
| 4731 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} |
| 4732 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} |
| 4733 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} |
| 4734 | |
| 4735 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
| 4736 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; |
| 4737 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; |
| 4738 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; |
| 4739 | |
| 4740 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
| 4741 | the program counter value to determine whether a 16-bit or 32-bit |
| 4742 | breakpoint should be used. It returns a pointer to a string of |
| 4743 | bytes that encode a breakpoint instruction, stores the length of |
| 4744 | the string to *lenptr, and adjusts the program counter (if |
| 4745 | necessary) to point to the actual memory location where the |
| 4746 | breakpoint should be inserted. */ |
| 4747 | |
| 4748 | static const unsigned char * |
| 4749 | arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
| 4750 | { |
| 4751 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 4752 | |
| 4753 | if (arm_pc_is_thumb (*pcptr)) |
| 4754 | { |
| 4755 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
| 4756 | *lenptr = tdep->thumb_breakpoint_size; |
| 4757 | return tdep->thumb_breakpoint; |
| 4758 | } |
| 4759 | else |
| 4760 | { |
| 4761 | *lenptr = tdep->arm_breakpoint_size; |
| 4762 | return tdep->arm_breakpoint; |
| 4763 | } |
| 4764 | } |
| 4765 | |
| 4766 | /* Extract from an array REGBUF containing the (raw) register state a |
| 4767 | function return value of type TYPE, and copy that, in virtual |
| 4768 | format, into VALBUF. */ |
| 4769 | |
| 4770 | static void |
| 4771 | arm_extract_return_value (struct type *type, struct regcache *regs, |
| 4772 | gdb_byte *valbuf) |
| 4773 | { |
| 4774 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
| 4775 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 4776 | |
| 4777 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
| 4778 | { |
| 4779 | switch (gdbarch_tdep (gdbarch)->fp_model) |
| 4780 | { |
| 4781 | case ARM_FLOAT_FPA: |
| 4782 | { |
| 4783 | /* The value is in register F0 in internal format. We need to |
| 4784 | extract the raw value and then convert it to the desired |
| 4785 | internal type. */ |
| 4786 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
| 4787 | |
| 4788 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); |
| 4789 | convert_from_extended (floatformat_from_type (type), tmpbuf, |
| 4790 | valbuf, gdbarch_byte_order (gdbarch)); |
| 4791 | } |
| 4792 | break; |
| 4793 | |
| 4794 | case ARM_FLOAT_SOFT_FPA: |
| 4795 | case ARM_FLOAT_SOFT_VFP: |
| 4796 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
| 4797 | not using the VFP ABI code. */ |
| 4798 | case ARM_FLOAT_VFP: |
| 4799 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
| 4800 | if (TYPE_LENGTH (type) > 4) |
| 4801 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, |
| 4802 | valbuf + INT_REGISTER_SIZE); |
| 4803 | break; |
| 4804 | |
| 4805 | default: |
| 4806 | internal_error |
| 4807 | (__FILE__, __LINE__, |
| 4808 | _("arm_extract_return_value: Floating point model not supported")); |
| 4809 | break; |
| 4810 | } |
| 4811 | } |
| 4812 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 4813 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 4814 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 4815 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 4816 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 4817 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 4818 | { |
| 4819 | /* If the the type is a plain integer, then the access is |
| 4820 | straight-forward. Otherwise we have to play around a bit more. */ |
| 4821 | int len = TYPE_LENGTH (type); |
| 4822 | int regno = ARM_A1_REGNUM; |
| 4823 | ULONGEST tmp; |
| 4824 | |
| 4825 | while (len > 0) |
| 4826 | { |
| 4827 | /* By using store_unsigned_integer we avoid having to do |
| 4828 | anything special for small big-endian values. */ |
| 4829 | regcache_cooked_read_unsigned (regs, regno++, &tmp); |
| 4830 | store_unsigned_integer (valbuf, |
| 4831 | (len > INT_REGISTER_SIZE |
| 4832 | ? INT_REGISTER_SIZE : len), |
| 4833 | byte_order, tmp); |
| 4834 | len -= INT_REGISTER_SIZE; |
| 4835 | valbuf += INT_REGISTER_SIZE; |
| 4836 | } |
| 4837 | } |
| 4838 | else |
| 4839 | { |
| 4840 | /* For a structure or union the behaviour is as if the value had |
| 4841 | been stored to word-aligned memory and then loaded into |
| 4842 | registers with 32-bit load instruction(s). */ |
| 4843 | int len = TYPE_LENGTH (type); |
| 4844 | int regno = ARM_A1_REGNUM; |
| 4845 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 4846 | |
| 4847 | while (len > 0) |
| 4848 | { |
| 4849 | regcache_cooked_read (regs, regno++, tmpbuf); |
| 4850 | memcpy (valbuf, tmpbuf, |
| 4851 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
| 4852 | len -= INT_REGISTER_SIZE; |
| 4853 | valbuf += INT_REGISTER_SIZE; |
| 4854 | } |
| 4855 | } |
| 4856 | } |
| 4857 | |
| 4858 | |
| 4859 | /* Will a function return an aggregate type in memory or in a |
| 4860 | register? Return 0 if an aggregate type can be returned in a |
| 4861 | register, 1 if it must be returned in memory. */ |
| 4862 | |
| 4863 | static int |
| 4864 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
| 4865 | { |
| 4866 | int nRc; |
| 4867 | enum type_code code; |
| 4868 | |
| 4869 | CHECK_TYPEDEF (type); |
| 4870 | |
| 4871 | /* In the ARM ABI, "integer" like aggregate types are returned in |
| 4872 | registers. For an aggregate type to be integer like, its size |
| 4873 | must be less than or equal to INT_REGISTER_SIZE and the |
| 4874 | offset of each addressable subfield must be zero. Note that bit |
| 4875 | fields are not addressable, and all addressable subfields of |
| 4876 | unions always start at offset zero. |
| 4877 | |
| 4878 | This function is based on the behaviour of GCC 2.95.1. |
| 4879 | See: gcc/arm.c: arm_return_in_memory() for details. |
| 4880 | |
| 4881 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
| 4882 | parameters correctly for a function returning the following |
| 4883 | structure: struct { float f;}; This should be returned in memory, |
| 4884 | not a register. Richard Earnshaw sent me a patch, but I do not |
| 4885 | know of any way to detect if a function like the above has been |
| 4886 | compiled with the correct calling convention. */ |
| 4887 | |
| 4888 | /* All aggregate types that won't fit in a register must be returned |
| 4889 | in memory. */ |
| 4890 | if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) |
| 4891 | { |
| 4892 | return 1; |
| 4893 | } |
| 4894 | |
| 4895 | /* The AAPCS says all aggregates not larger than a word are returned |
| 4896 | in a register. */ |
| 4897 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) |
| 4898 | return 0; |
| 4899 | |
| 4900 | /* The only aggregate types that can be returned in a register are |
| 4901 | structs and unions. Arrays must be returned in memory. */ |
| 4902 | code = TYPE_CODE (type); |
| 4903 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) |
| 4904 | { |
| 4905 | return 1; |
| 4906 | } |
| 4907 | |
| 4908 | /* Assume all other aggregate types can be returned in a register. |
| 4909 | Run a check for structures, unions and arrays. */ |
| 4910 | nRc = 0; |
| 4911 | |
| 4912 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
| 4913 | { |
| 4914 | int i; |
| 4915 | /* Need to check if this struct/union is "integer" like. For |
| 4916 | this to be true, its size must be less than or equal to |
| 4917 | INT_REGISTER_SIZE and the offset of each addressable |
| 4918 | subfield must be zero. Note that bit fields are not |
| 4919 | addressable, and unions always start at offset zero. If any |
| 4920 | of the subfields is a floating point type, the struct/union |
| 4921 | cannot be an integer type. */ |
| 4922 | |
| 4923 | /* For each field in the object, check: |
| 4924 | 1) Is it FP? --> yes, nRc = 1; |
| 4925 | 2) Is it addressable (bitpos != 0) and |
| 4926 | not packed (bitsize == 0)? |
| 4927 | --> yes, nRc = 1 |
| 4928 | */ |
| 4929 | |
| 4930 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 4931 | { |
| 4932 | enum type_code field_type_code; |
| 4933 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
| 4934 | |
| 4935 | /* Is it a floating point type field? */ |
| 4936 | if (field_type_code == TYPE_CODE_FLT) |
| 4937 | { |
| 4938 | nRc = 1; |
| 4939 | break; |
| 4940 | } |
| 4941 | |
| 4942 | /* If bitpos != 0, then we have to care about it. */ |
| 4943 | if (TYPE_FIELD_BITPOS (type, i) != 0) |
| 4944 | { |
| 4945 | /* Bitfields are not addressable. If the field bitsize is |
| 4946 | zero, then the field is not packed. Hence it cannot be |
| 4947 | a bitfield or any other packed type. */ |
| 4948 | if (TYPE_FIELD_BITSIZE (type, i) == 0) |
| 4949 | { |
| 4950 | nRc = 1; |
| 4951 | break; |
| 4952 | } |
| 4953 | } |
| 4954 | } |
| 4955 | } |
| 4956 | |
| 4957 | return nRc; |
| 4958 | } |
| 4959 | |
| 4960 | /* Write into appropriate registers a function return value of type |
| 4961 | TYPE, given in virtual format. */ |
| 4962 | |
| 4963 | static void |
| 4964 | arm_store_return_value (struct type *type, struct regcache *regs, |
| 4965 | const gdb_byte *valbuf) |
| 4966 | { |
| 4967 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
| 4968 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 4969 | |
| 4970 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 4971 | { |
| 4972 | char buf[MAX_REGISTER_SIZE]; |
| 4973 | |
| 4974 | switch (gdbarch_tdep (gdbarch)->fp_model) |
| 4975 | { |
| 4976 | case ARM_FLOAT_FPA: |
| 4977 | |
| 4978 | convert_to_extended (floatformat_from_type (type), buf, valbuf, |
| 4979 | gdbarch_byte_order (gdbarch)); |
| 4980 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
| 4981 | break; |
| 4982 | |
| 4983 | case ARM_FLOAT_SOFT_FPA: |
| 4984 | case ARM_FLOAT_SOFT_VFP: |
| 4985 | /* ARM_FLOAT_VFP can arise if this is a variadic function so |
| 4986 | not using the VFP ABI code. */ |
| 4987 | case ARM_FLOAT_VFP: |
| 4988 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
| 4989 | if (TYPE_LENGTH (type) > 4) |
| 4990 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, |
| 4991 | valbuf + INT_REGISTER_SIZE); |
| 4992 | break; |
| 4993 | |
| 4994 | default: |
| 4995 | internal_error |
| 4996 | (__FILE__, __LINE__, |
| 4997 | _("arm_store_return_value: Floating point model not supported")); |
| 4998 | break; |
| 4999 | } |
| 5000 | } |
| 5001 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 5002 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 5003 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 5004 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 5005 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 5006 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 5007 | { |
| 5008 | if (TYPE_LENGTH (type) <= 4) |
| 5009 | { |
| 5010 | /* Values of one word or less are zero/sign-extended and |
| 5011 | returned in r0. */ |
| 5012 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 5013 | LONGEST val = unpack_long (type, valbuf); |
| 5014 | |
| 5015 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val); |
| 5016 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
| 5017 | } |
| 5018 | else |
| 5019 | { |
| 5020 | /* Integral values greater than one word are stored in consecutive |
| 5021 | registers starting with r0. This will always be a multiple of |
| 5022 | the regiser size. */ |
| 5023 | int len = TYPE_LENGTH (type); |
| 5024 | int regno = ARM_A1_REGNUM; |
| 5025 | |
| 5026 | while (len > 0) |
| 5027 | { |
| 5028 | regcache_cooked_write (regs, regno++, valbuf); |
| 5029 | len -= INT_REGISTER_SIZE; |
| 5030 | valbuf += INT_REGISTER_SIZE; |
| 5031 | } |
| 5032 | } |
| 5033 | } |
| 5034 | else |
| 5035 | { |
| 5036 | /* For a structure or union the behaviour is as if the value had |
| 5037 | been stored to word-aligned memory and then loaded into |
| 5038 | registers with 32-bit load instruction(s). */ |
| 5039 | int len = TYPE_LENGTH (type); |
| 5040 | int regno = ARM_A1_REGNUM; |
| 5041 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 5042 | |
| 5043 | while (len > 0) |
| 5044 | { |
| 5045 | memcpy (tmpbuf, valbuf, |
| 5046 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
| 5047 | regcache_cooked_write (regs, regno++, tmpbuf); |
| 5048 | len -= INT_REGISTER_SIZE; |
| 5049 | valbuf += INT_REGISTER_SIZE; |
| 5050 | } |
| 5051 | } |
| 5052 | } |
| 5053 | |
| 5054 | |
| 5055 | /* Handle function return values. */ |
| 5056 | |
| 5057 | static enum return_value_convention |
| 5058 | arm_return_value (struct gdbarch *gdbarch, struct type *func_type, |
| 5059 | struct type *valtype, struct regcache *regcache, |
| 5060 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 5061 | { |
| 5062 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 5063 | enum arm_vfp_cprc_base_type vfp_base_type; |
| 5064 | int vfp_base_count; |
| 5065 | |
| 5066 | if (arm_vfp_abi_for_function (gdbarch, func_type) |
| 5067 | && arm_vfp_call_candidate (valtype, &vfp_base_type, &vfp_base_count)) |
| 5068 | { |
| 5069 | int reg_char = arm_vfp_cprc_reg_char (vfp_base_type); |
| 5070 | int unit_length = arm_vfp_cprc_unit_length (vfp_base_type); |
| 5071 | int i; |
| 5072 | for (i = 0; i < vfp_base_count; i++) |
| 5073 | { |
| 5074 | if (reg_char == 'q') |
| 5075 | { |
| 5076 | if (writebuf) |
| 5077 | arm_neon_quad_write (gdbarch, regcache, i, |
| 5078 | writebuf + i * unit_length); |
| 5079 | |
| 5080 | if (readbuf) |
| 5081 | arm_neon_quad_read (gdbarch, regcache, i, |
| 5082 | readbuf + i * unit_length); |
| 5083 | } |
| 5084 | else |
| 5085 | { |
| 5086 | char name_buf[4]; |
| 5087 | int regnum; |
| 5088 | |
| 5089 | sprintf (name_buf, "%c%d", reg_char, i); |
| 5090 | regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
| 5091 | strlen (name_buf)); |
| 5092 | if (writebuf) |
| 5093 | regcache_cooked_write (regcache, regnum, |
| 5094 | writebuf + i * unit_length); |
| 5095 | if (readbuf) |
| 5096 | regcache_cooked_read (regcache, regnum, |
| 5097 | readbuf + i * unit_length); |
| 5098 | } |
| 5099 | } |
| 5100 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5101 | } |
| 5102 | |
| 5103 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
| 5104 | || TYPE_CODE (valtype) == TYPE_CODE_UNION |
| 5105 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) |
| 5106 | { |
| 5107 | if (tdep->struct_return == pcc_struct_return |
| 5108 | || arm_return_in_memory (gdbarch, valtype)) |
| 5109 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 5110 | } |
| 5111 | |
| 5112 | if (writebuf) |
| 5113 | arm_store_return_value (valtype, regcache, writebuf); |
| 5114 | |
| 5115 | if (readbuf) |
| 5116 | arm_extract_return_value (valtype, regcache, readbuf); |
| 5117 | |
| 5118 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 5119 | } |
| 5120 | |
| 5121 | |
| 5122 | static int |
| 5123 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
| 5124 | { |
| 5125 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 5126 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 5127 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 5128 | CORE_ADDR jb_addr; |
| 5129 | char buf[INT_REGISTER_SIZE]; |
| 5130 | |
| 5131 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
| 5132 | |
| 5133 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, |
| 5134 | INT_REGISTER_SIZE)) |
| 5135 | return 0; |
| 5136 | |
| 5137 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order); |
| 5138 | return 1; |
| 5139 | } |
| 5140 | |
| 5141 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
| 5142 | return the target PC. Otherwise return 0. */ |
| 5143 | |
| 5144 | CORE_ADDR |
| 5145 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
| 5146 | { |
| 5147 | char *name; |
| 5148 | int namelen; |
| 5149 | CORE_ADDR start_addr; |
| 5150 | |
| 5151 | /* Find the starting address and name of the function containing the PC. */ |
| 5152 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 5153 | return 0; |
| 5154 | |
| 5155 | /* If PC is in a Thumb call or return stub, return the address of the |
| 5156 | target PC, which is in a register. The thunk functions are called |
| 5157 | _call_via_xx, where x is the register name. The possible names |
| 5158 | are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar |
| 5159 | functions, named __ARM_call_via_r[0-7]. */ |
| 5160 | if (strncmp (name, "_call_via_", 10) == 0 |
| 5161 | || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0) |
| 5162 | { |
| 5163 | /* Use the name suffix to determine which register contains the |
| 5164 | target PC. */ |
| 5165 | static char *table[15] = |
| 5166 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 5167 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" |
| 5168 | }; |
| 5169 | int regno; |
| 5170 | int offset = strlen (name) - 2; |
| 5171 | |
| 5172 | for (regno = 0; regno <= 14; regno++) |
| 5173 | if (strcmp (&name[offset], table[regno]) == 0) |
| 5174 | return get_frame_register_unsigned (frame, regno); |
| 5175 | } |
| 5176 | |
| 5177 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
| 5178 | non-interworking calls to foo. We could decode the stubs |
| 5179 | to find the target but it's easier to use the symbol table. */ |
| 5180 | namelen = strlen (name); |
| 5181 | if (name[0] == '_' && name[1] == '_' |
| 5182 | && ((namelen > 2 + strlen ("_from_thumb") |
| 5183 | && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb", |
| 5184 | strlen ("_from_thumb")) == 0) |
| 5185 | || (namelen > 2 + strlen ("_from_arm") |
| 5186 | && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm", |
| 5187 | strlen ("_from_arm")) == 0))) |
| 5188 | { |
| 5189 | char *target_name; |
| 5190 | int target_len = namelen - 2; |
| 5191 | struct minimal_symbol *minsym; |
| 5192 | struct objfile *objfile; |
| 5193 | struct obj_section *sec; |
| 5194 | |
| 5195 | if (name[namelen - 1] == 'b') |
| 5196 | target_len -= strlen ("_from_thumb"); |
| 5197 | else |
| 5198 | target_len -= strlen ("_from_arm"); |
| 5199 | |
| 5200 | target_name = alloca (target_len + 1); |
| 5201 | memcpy (target_name, name + 2, target_len); |
| 5202 | target_name[target_len] = '\0'; |
| 5203 | |
| 5204 | sec = find_pc_section (pc); |
| 5205 | objfile = (sec == NULL) ? NULL : sec->objfile; |
| 5206 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); |
| 5207 | if (minsym != NULL) |
| 5208 | return SYMBOL_VALUE_ADDRESS (minsym); |
| 5209 | else |
| 5210 | return 0; |
| 5211 | } |
| 5212 | |
| 5213 | return 0; /* not a stub */ |
| 5214 | } |
| 5215 | |
| 5216 | static void |
| 5217 | set_arm_command (char *args, int from_tty) |
| 5218 | { |
| 5219 | printf_unfiltered (_("\ |
| 5220 | \"set arm\" must be followed by an apporpriate subcommand.\n")); |
| 5221 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
| 5222 | } |
| 5223 | |
| 5224 | static void |
| 5225 | show_arm_command (char *args, int from_tty) |
| 5226 | { |
| 5227 | cmd_show_list (showarmcmdlist, from_tty, ""); |
| 5228 | } |
| 5229 | |
| 5230 | static void |
| 5231 | arm_update_current_architecture (void) |
| 5232 | { |
| 5233 | struct gdbarch_info info; |
| 5234 | |
| 5235 | /* If the current architecture is not ARM, we have nothing to do. */ |
| 5236 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm) |
| 5237 | return; |
| 5238 | |
| 5239 | /* Update the architecture. */ |
| 5240 | gdbarch_info_init (&info); |
| 5241 | |
| 5242 | if (!gdbarch_update_p (info)) |
| 5243 | internal_error (__FILE__, __LINE__, "could not update architecture"); |
| 5244 | } |
| 5245 | |
| 5246 | static void |
| 5247 | set_fp_model_sfunc (char *args, int from_tty, |
| 5248 | struct cmd_list_element *c) |
| 5249 | { |
| 5250 | enum arm_float_model fp_model; |
| 5251 | |
| 5252 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) |
| 5253 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) |
| 5254 | { |
| 5255 | arm_fp_model = fp_model; |
| 5256 | break; |
| 5257 | } |
| 5258 | |
| 5259 | if (fp_model == ARM_FLOAT_LAST) |
| 5260 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
| 5261 | current_fp_model); |
| 5262 | |
| 5263 | arm_update_current_architecture (); |
| 5264 | } |
| 5265 | |
| 5266 | static void |
| 5267 | show_fp_model (struct ui_file *file, int from_tty, |
| 5268 | struct cmd_list_element *c, const char *value) |
| 5269 | { |
| 5270 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 5271 | |
| 5272 | if (arm_fp_model == ARM_FLOAT_AUTO |
| 5273 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
| 5274 | fprintf_filtered (file, _("\ |
| 5275 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), |
| 5276 | fp_model_strings[tdep->fp_model]); |
| 5277 | else |
| 5278 | fprintf_filtered (file, _("\ |
| 5279 | The current ARM floating point model is \"%s\".\n"), |
| 5280 | fp_model_strings[arm_fp_model]); |
| 5281 | } |
| 5282 | |
| 5283 | static void |
| 5284 | arm_set_abi (char *args, int from_tty, |
| 5285 | struct cmd_list_element *c) |
| 5286 | { |
| 5287 | enum arm_abi_kind arm_abi; |
| 5288 | |
| 5289 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) |
| 5290 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) |
| 5291 | { |
| 5292 | arm_abi_global = arm_abi; |
| 5293 | break; |
| 5294 | } |
| 5295 | |
| 5296 | if (arm_abi == ARM_ABI_LAST) |
| 5297 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), |
| 5298 | arm_abi_string); |
| 5299 | |
| 5300 | arm_update_current_architecture (); |
| 5301 | } |
| 5302 | |
| 5303 | static void |
| 5304 | arm_show_abi (struct ui_file *file, int from_tty, |
| 5305 | struct cmd_list_element *c, const char *value) |
| 5306 | { |
| 5307 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 5308 | |
| 5309 | if (arm_abi_global == ARM_ABI_AUTO |
| 5310 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
| 5311 | fprintf_filtered (file, _("\ |
| 5312 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), |
| 5313 | arm_abi_strings[tdep->arm_abi]); |
| 5314 | else |
| 5315 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), |
| 5316 | arm_abi_string); |
| 5317 | } |
| 5318 | |
| 5319 | static void |
| 5320 | arm_show_fallback_mode (struct ui_file *file, int from_tty, |
| 5321 | struct cmd_list_element *c, const char *value) |
| 5322 | { |
| 5323 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 5324 | |
| 5325 | fprintf_filtered (file, _("\ |
| 5326 | The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"), |
| 5327 | arm_fallback_mode_string); |
| 5328 | } |
| 5329 | |
| 5330 | static void |
| 5331 | arm_show_force_mode (struct ui_file *file, int from_tty, |
| 5332 | struct cmd_list_element *c, const char *value) |
| 5333 | { |
| 5334 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 5335 | |
| 5336 | fprintf_filtered (file, _("\ |
| 5337 | The current execution mode assumed (even when symbols are available) is \"%s\".\n"), |
| 5338 | arm_force_mode_string); |
| 5339 | } |
| 5340 | |
| 5341 | /* If the user changes the register disassembly style used for info |
| 5342 | register and other commands, we have to also switch the style used |
| 5343 | in opcodes for disassembly output. This function is run in the "set |
| 5344 | arm disassembly" command, and does that. */ |
| 5345 | |
| 5346 | static void |
| 5347 | set_disassembly_style_sfunc (char *args, int from_tty, |
| 5348 | struct cmd_list_element *c) |
| 5349 | { |
| 5350 | set_disassembly_style (); |
| 5351 | } |
| 5352 | \f |
| 5353 | /* Return the ARM register name corresponding to register I. */ |
| 5354 | static const char * |
| 5355 | arm_register_name (struct gdbarch *gdbarch, int i) |
| 5356 | { |
| 5357 | const int num_regs = gdbarch_num_regs (gdbarch); |
| 5358 | |
| 5359 | if (gdbarch_tdep (gdbarch)->have_vfp_pseudos |
| 5360 | && i >= num_regs && i < num_regs + 32) |
| 5361 | { |
| 5362 | static const char *const vfp_pseudo_names[] = { |
| 5363 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 5364 | "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", |
| 5365 | "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", |
| 5366 | "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", |
| 5367 | }; |
| 5368 | |
| 5369 | return vfp_pseudo_names[i - num_regs]; |
| 5370 | } |
| 5371 | |
| 5372 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos |
| 5373 | && i >= num_regs + 32 && i < num_regs + 32 + 16) |
| 5374 | { |
| 5375 | static const char *const neon_pseudo_names[] = { |
| 5376 | "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", |
| 5377 | "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", |
| 5378 | }; |
| 5379 | |
| 5380 | return neon_pseudo_names[i - num_regs - 32]; |
| 5381 | } |
| 5382 | |
| 5383 | if (i >= ARRAY_SIZE (arm_register_names)) |
| 5384 | /* These registers are only supported on targets which supply |
| 5385 | an XML description. */ |
| 5386 | return ""; |
| 5387 | |
| 5388 | return arm_register_names[i]; |
| 5389 | } |
| 5390 | |
| 5391 | static void |
| 5392 | set_disassembly_style (void) |
| 5393 | { |
| 5394 | int current; |
| 5395 | |
| 5396 | /* Find the style that the user wants. */ |
| 5397 | for (current = 0; current < num_disassembly_options; current++) |
| 5398 | if (disassembly_style == valid_disassembly_styles[current]) |
| 5399 | break; |
| 5400 | gdb_assert (current < num_disassembly_options); |
| 5401 | |
| 5402 | /* Synchronize the disassembler. */ |
| 5403 | set_arm_regname_option (current); |
| 5404 | } |
| 5405 | |
| 5406 | /* Test whether the coff symbol specific value corresponds to a Thumb |
| 5407 | function. */ |
| 5408 | |
| 5409 | static int |
| 5410 | coff_sym_is_thumb (int val) |
| 5411 | { |
| 5412 | return (val == C_THUMBEXT |
| 5413 | || val == C_THUMBSTAT |
| 5414 | || val == C_THUMBEXTFUNC |
| 5415 | || val == C_THUMBSTATFUNC |
| 5416 | || val == C_THUMBLABEL); |
| 5417 | } |
| 5418 | |
| 5419 | /* arm_coff_make_msymbol_special() |
| 5420 | arm_elf_make_msymbol_special() |
| 5421 | |
| 5422 | These functions test whether the COFF or ELF symbol corresponds to |
| 5423 | an address in thumb code, and set a "special" bit in a minimal |
| 5424 | symbol to indicate that it does. */ |
| 5425 | |
| 5426 | static void |
| 5427 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
| 5428 | { |
| 5429 | /* Thumb symbols are of type STT_LOPROC, (synonymous with |
| 5430 | STT_ARM_TFUNC). */ |
| 5431 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) |
| 5432 | == STT_LOPROC) |
| 5433 | MSYMBOL_SET_SPECIAL (msym); |
| 5434 | } |
| 5435 | |
| 5436 | static void |
| 5437 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
| 5438 | { |
| 5439 | if (coff_sym_is_thumb (val)) |
| 5440 | MSYMBOL_SET_SPECIAL (msym); |
| 5441 | } |
| 5442 | |
| 5443 | static void |
| 5444 | arm_objfile_data_free (struct objfile *objfile, void *arg) |
| 5445 | { |
| 5446 | struct arm_per_objfile *data = arg; |
| 5447 | unsigned int i; |
| 5448 | |
| 5449 | for (i = 0; i < objfile->obfd->section_count; i++) |
| 5450 | VEC_free (arm_mapping_symbol_s, data->section_maps[i]); |
| 5451 | } |
| 5452 | |
| 5453 | static void |
| 5454 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, |
| 5455 | asymbol *sym) |
| 5456 | { |
| 5457 | const char *name = bfd_asymbol_name (sym); |
| 5458 | struct arm_per_objfile *data; |
| 5459 | VEC(arm_mapping_symbol_s) **map_p; |
| 5460 | struct arm_mapping_symbol new_map_sym; |
| 5461 | |
| 5462 | gdb_assert (name[0] == '$'); |
| 5463 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') |
| 5464 | return; |
| 5465 | |
| 5466 | data = objfile_data (objfile, arm_objfile_data_key); |
| 5467 | if (data == NULL) |
| 5468 | { |
| 5469 | data = OBSTACK_ZALLOC (&objfile->objfile_obstack, |
| 5470 | struct arm_per_objfile); |
| 5471 | set_objfile_data (objfile, arm_objfile_data_key, data); |
| 5472 | data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack, |
| 5473 | objfile->obfd->section_count, |
| 5474 | VEC(arm_mapping_symbol_s) *); |
| 5475 | } |
| 5476 | map_p = &data->section_maps[bfd_get_section (sym)->index]; |
| 5477 | |
| 5478 | new_map_sym.value = sym->value; |
| 5479 | new_map_sym.type = name[1]; |
| 5480 | |
| 5481 | /* Assume that most mapping symbols appear in order of increasing |
| 5482 | value. If they were randomly distributed, it would be faster to |
| 5483 | always push here and then sort at first use. */ |
| 5484 | if (!VEC_empty (arm_mapping_symbol_s, *map_p)) |
| 5485 | { |
| 5486 | struct arm_mapping_symbol *prev_map_sym; |
| 5487 | |
| 5488 | prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p); |
| 5489 | if (prev_map_sym->value >= sym->value) |
| 5490 | { |
| 5491 | unsigned int idx; |
| 5492 | idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym, |
| 5493 | arm_compare_mapping_symbols); |
| 5494 | VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym); |
| 5495 | return; |
| 5496 | } |
| 5497 | } |
| 5498 | |
| 5499 | VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym); |
| 5500 | } |
| 5501 | |
| 5502 | static void |
| 5503 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
| 5504 | { |
| 5505 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
| 5506 | |
| 5507 | /* If necessary, set the T bit. */ |
| 5508 | if (arm_apcs_32) |
| 5509 | { |
| 5510 | ULONGEST val; |
| 5511 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
| 5512 | if (arm_pc_is_thumb (pc)) |
| 5513 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T); |
| 5514 | else |
| 5515 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
| 5516 | val & ~(ULONGEST) CPSR_T); |
| 5517 | } |
| 5518 | } |
| 5519 | |
| 5520 | /* Read the contents of a NEON quad register, by reading from two |
| 5521 | double registers. This is used to implement the quad pseudo |
| 5522 | registers, and for argument passing in case the quad registers are |
| 5523 | missing; vectors are passed in quad registers when using the VFP |
| 5524 | ABI, even if a NEON unit is not present. REGNUM is the index of |
| 5525 | the quad register, in [0, 15]. */ |
| 5526 | |
| 5527 | static void |
| 5528 | arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 5529 | int regnum, gdb_byte *buf) |
| 5530 | { |
| 5531 | char name_buf[4]; |
| 5532 | gdb_byte reg_buf[8]; |
| 5533 | int offset, double_regnum; |
| 5534 | |
| 5535 | sprintf (name_buf, "d%d", regnum << 1); |
| 5536 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
| 5537 | strlen (name_buf)); |
| 5538 | |
| 5539 | /* d0 is always the least significant half of q0. */ |
| 5540 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 5541 | offset = 8; |
| 5542 | else |
| 5543 | offset = 0; |
| 5544 | |
| 5545 | regcache_raw_read (regcache, double_regnum, reg_buf); |
| 5546 | memcpy (buf + offset, reg_buf, 8); |
| 5547 | |
| 5548 | offset = 8 - offset; |
| 5549 | regcache_raw_read (regcache, double_regnum + 1, reg_buf); |
| 5550 | memcpy (buf + offset, reg_buf, 8); |
| 5551 | } |
| 5552 | |
| 5553 | static void |
| 5554 | arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 5555 | int regnum, gdb_byte *buf) |
| 5556 | { |
| 5557 | const int num_regs = gdbarch_num_regs (gdbarch); |
| 5558 | char name_buf[4]; |
| 5559 | gdb_byte reg_buf[8]; |
| 5560 | int offset, double_regnum; |
| 5561 | |
| 5562 | gdb_assert (regnum >= num_regs); |
| 5563 | regnum -= num_regs; |
| 5564 | |
| 5565 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) |
| 5566 | /* Quad-precision register. */ |
| 5567 | arm_neon_quad_read (gdbarch, regcache, regnum - 32, buf); |
| 5568 | else |
| 5569 | { |
| 5570 | /* Single-precision register. */ |
| 5571 | gdb_assert (regnum < 32); |
| 5572 | |
| 5573 | /* s0 is always the least significant half of d0. */ |
| 5574 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 5575 | offset = (regnum & 1) ? 0 : 4; |
| 5576 | else |
| 5577 | offset = (regnum & 1) ? 4 : 0; |
| 5578 | |
| 5579 | sprintf (name_buf, "d%d", regnum >> 1); |
| 5580 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
| 5581 | strlen (name_buf)); |
| 5582 | |
| 5583 | regcache_raw_read (regcache, double_regnum, reg_buf); |
| 5584 | memcpy (buf, reg_buf + offset, 4); |
| 5585 | } |
| 5586 | } |
| 5587 | |
| 5588 | /* Store the contents of BUF to a NEON quad register, by writing to |
| 5589 | two double registers. This is used to implement the quad pseudo |
| 5590 | registers, and for argument passing in case the quad registers are |
| 5591 | missing; vectors are passed in quad registers when using the VFP |
| 5592 | ABI, even if a NEON unit is not present. REGNUM is the index |
| 5593 | of the quad register, in [0, 15]. */ |
| 5594 | |
| 5595 | static void |
| 5596 | arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 5597 | int regnum, const gdb_byte *buf) |
| 5598 | { |
| 5599 | char name_buf[4]; |
| 5600 | gdb_byte reg_buf[8]; |
| 5601 | int offset, double_regnum; |
| 5602 | |
| 5603 | sprintf (name_buf, "d%d", regnum << 1); |
| 5604 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
| 5605 | strlen (name_buf)); |
| 5606 | |
| 5607 | /* d0 is always the least significant half of q0. */ |
| 5608 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 5609 | offset = 8; |
| 5610 | else |
| 5611 | offset = 0; |
| 5612 | |
| 5613 | regcache_raw_write (regcache, double_regnum, buf + offset); |
| 5614 | offset = 8 - offset; |
| 5615 | regcache_raw_write (regcache, double_regnum + 1, buf + offset); |
| 5616 | } |
| 5617 | |
| 5618 | static void |
| 5619 | arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 5620 | int regnum, const gdb_byte *buf) |
| 5621 | { |
| 5622 | const int num_regs = gdbarch_num_regs (gdbarch); |
| 5623 | char name_buf[4]; |
| 5624 | gdb_byte reg_buf[8]; |
| 5625 | int offset, double_regnum; |
| 5626 | |
| 5627 | gdb_assert (regnum >= num_regs); |
| 5628 | regnum -= num_regs; |
| 5629 | |
| 5630 | if (gdbarch_tdep (gdbarch)->have_neon_pseudos && regnum >= 32 && regnum < 48) |
| 5631 | /* Quad-precision register. */ |
| 5632 | arm_neon_quad_write (gdbarch, regcache, regnum - 32, buf); |
| 5633 | else |
| 5634 | { |
| 5635 | /* Single-precision register. */ |
| 5636 | gdb_assert (regnum < 32); |
| 5637 | |
| 5638 | /* s0 is always the least significant half of d0. */ |
| 5639 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 5640 | offset = (regnum & 1) ? 0 : 4; |
| 5641 | else |
| 5642 | offset = (regnum & 1) ? 4 : 0; |
| 5643 | |
| 5644 | sprintf (name_buf, "d%d", regnum >> 1); |
| 5645 | double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, |
| 5646 | strlen (name_buf)); |
| 5647 | |
| 5648 | regcache_raw_read (regcache, double_regnum, reg_buf); |
| 5649 | memcpy (reg_buf + offset, buf, 4); |
| 5650 | regcache_raw_write (regcache, double_regnum, reg_buf); |
| 5651 | } |
| 5652 | } |
| 5653 | |
| 5654 | static struct value * |
| 5655 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) |
| 5656 | { |
| 5657 | const int *reg_p = baton; |
| 5658 | return value_of_register (*reg_p, frame); |
| 5659 | } |
| 5660 | \f |
| 5661 | static enum gdb_osabi |
| 5662 | arm_elf_osabi_sniffer (bfd *abfd) |
| 5663 | { |
| 5664 | unsigned int elfosabi; |
| 5665 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
| 5666 | |
| 5667 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
| 5668 | |
| 5669 | if (elfosabi == ELFOSABI_ARM) |
| 5670 | /* GNU tools use this value. Check note sections in this case, |
| 5671 | as well. */ |
| 5672 | bfd_map_over_sections (abfd, |
| 5673 | generic_elf_osabi_sniff_abi_tag_sections, |
| 5674 | &osabi); |
| 5675 | |
| 5676 | /* Anything else will be handled by the generic ELF sniffer. */ |
| 5677 | return osabi; |
| 5678 | } |
| 5679 | |
| 5680 | \f |
| 5681 | /* Initialize the current architecture based on INFO. If possible, |
| 5682 | re-use an architecture from ARCHES, which is a list of |
| 5683 | architectures already created during this debugging session. |
| 5684 | |
| 5685 | Called e.g. at program startup, when reading a core file, and when |
| 5686 | reading a binary file. */ |
| 5687 | |
| 5688 | static struct gdbarch * |
| 5689 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 5690 | { |
| 5691 | struct gdbarch_tdep *tdep; |
| 5692 | struct gdbarch *gdbarch; |
| 5693 | struct gdbarch_list *best_arch; |
| 5694 | enum arm_abi_kind arm_abi = arm_abi_global; |
| 5695 | enum arm_float_model fp_model = arm_fp_model; |
| 5696 | struct tdesc_arch_data *tdesc_data = NULL; |
| 5697 | int i; |
| 5698 | int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0; |
| 5699 | int have_neon = 0; |
| 5700 | int have_fpa_registers = 1; |
| 5701 | |
| 5702 | /* Check any target description for validity. */ |
| 5703 | if (tdesc_has_registers (info.target_desc)) |
| 5704 | { |
| 5705 | /* For most registers we require GDB's default names; but also allow |
| 5706 | the numeric names for sp / lr / pc, as a convenience. */ |
| 5707 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; |
| 5708 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; |
| 5709 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; |
| 5710 | |
| 5711 | const struct tdesc_feature *feature; |
| 5712 | int valid_p; |
| 5713 | |
| 5714 | feature = tdesc_find_feature (info.target_desc, |
| 5715 | "org.gnu.gdb.arm.core"); |
| 5716 | if (feature == NULL) |
| 5717 | return NULL; |
| 5718 | |
| 5719 | tdesc_data = tdesc_data_alloc (); |
| 5720 | |
| 5721 | valid_p = 1; |
| 5722 | for (i = 0; i < ARM_SP_REGNUM; i++) |
| 5723 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
| 5724 | arm_register_names[i]); |
| 5725 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, |
| 5726 | ARM_SP_REGNUM, |
| 5727 | arm_sp_names); |
| 5728 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, |
| 5729 | ARM_LR_REGNUM, |
| 5730 | arm_lr_names); |
| 5731 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, |
| 5732 | ARM_PC_REGNUM, |
| 5733 | arm_pc_names); |
| 5734 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5735 | ARM_PS_REGNUM, "cpsr"); |
| 5736 | |
| 5737 | if (!valid_p) |
| 5738 | { |
| 5739 | tdesc_data_cleanup (tdesc_data); |
| 5740 | return NULL; |
| 5741 | } |
| 5742 | |
| 5743 | feature = tdesc_find_feature (info.target_desc, |
| 5744 | "org.gnu.gdb.arm.fpa"); |
| 5745 | if (feature != NULL) |
| 5746 | { |
| 5747 | valid_p = 1; |
| 5748 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) |
| 5749 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
| 5750 | arm_register_names[i]); |
| 5751 | if (!valid_p) |
| 5752 | { |
| 5753 | tdesc_data_cleanup (tdesc_data); |
| 5754 | return NULL; |
| 5755 | } |
| 5756 | } |
| 5757 | else |
| 5758 | have_fpa_registers = 0; |
| 5759 | |
| 5760 | feature = tdesc_find_feature (info.target_desc, |
| 5761 | "org.gnu.gdb.xscale.iwmmxt"); |
| 5762 | if (feature != NULL) |
| 5763 | { |
| 5764 | static const char *const iwmmxt_names[] = { |
| 5765 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", |
| 5766 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", |
| 5767 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", |
| 5768 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", |
| 5769 | }; |
| 5770 | |
| 5771 | valid_p = 1; |
| 5772 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) |
| 5773 | valid_p |
| 5774 | &= tdesc_numbered_register (feature, tdesc_data, i, |
| 5775 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
| 5776 | |
| 5777 | /* Check for the control registers, but do not fail if they |
| 5778 | are missing. */ |
| 5779 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) |
| 5780 | tdesc_numbered_register (feature, tdesc_data, i, |
| 5781 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
| 5782 | |
| 5783 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) |
| 5784 | valid_p |
| 5785 | &= tdesc_numbered_register (feature, tdesc_data, i, |
| 5786 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
| 5787 | |
| 5788 | if (!valid_p) |
| 5789 | { |
| 5790 | tdesc_data_cleanup (tdesc_data); |
| 5791 | return NULL; |
| 5792 | } |
| 5793 | } |
| 5794 | |
| 5795 | /* If we have a VFP unit, check whether the single precision registers |
| 5796 | are present. If not, then we will synthesize them as pseudo |
| 5797 | registers. */ |
| 5798 | feature = tdesc_find_feature (info.target_desc, |
| 5799 | "org.gnu.gdb.arm.vfp"); |
| 5800 | if (feature != NULL) |
| 5801 | { |
| 5802 | static const char *const vfp_double_names[] = { |
| 5803 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", |
| 5804 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", |
| 5805 | "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", |
| 5806 | "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", |
| 5807 | }; |
| 5808 | |
| 5809 | /* Require the double precision registers. There must be either |
| 5810 | 16 or 32. */ |
| 5811 | valid_p = 1; |
| 5812 | for (i = 0; i < 32; i++) |
| 5813 | { |
| 5814 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 5815 | ARM_D0_REGNUM + i, |
| 5816 | vfp_double_names[i]); |
| 5817 | if (!valid_p) |
| 5818 | break; |
| 5819 | } |
| 5820 | |
| 5821 | if (!valid_p && i != 16) |
| 5822 | { |
| 5823 | tdesc_data_cleanup (tdesc_data); |
| 5824 | return NULL; |
| 5825 | } |
| 5826 | |
| 5827 | if (tdesc_unnumbered_register (feature, "s0") == 0) |
| 5828 | have_vfp_pseudos = 1; |
| 5829 | |
| 5830 | have_vfp_registers = 1; |
| 5831 | |
| 5832 | /* If we have VFP, also check for NEON. The architecture allows |
| 5833 | NEON without VFP (integer vector operations only), but GDB |
| 5834 | does not support that. */ |
| 5835 | feature = tdesc_find_feature (info.target_desc, |
| 5836 | "org.gnu.gdb.arm.neon"); |
| 5837 | if (feature != NULL) |
| 5838 | { |
| 5839 | /* NEON requires 32 double-precision registers. */ |
| 5840 | if (i != 32) |
| 5841 | { |
| 5842 | tdesc_data_cleanup (tdesc_data); |
| 5843 | return NULL; |
| 5844 | } |
| 5845 | |
| 5846 | /* If there are quad registers defined by the stub, use |
| 5847 | their type; otherwise (normally) provide them with |
| 5848 | the default type. */ |
| 5849 | if (tdesc_unnumbered_register (feature, "q0") == 0) |
| 5850 | have_neon_pseudos = 1; |
| 5851 | |
| 5852 | have_neon = 1; |
| 5853 | } |
| 5854 | } |
| 5855 | } |
| 5856 | |
| 5857 | /* If we have an object to base this architecture on, try to determine |
| 5858 | its ABI. */ |
| 5859 | |
| 5860 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
| 5861 | { |
| 5862 | int ei_osabi, e_flags; |
| 5863 | |
| 5864 | switch (bfd_get_flavour (info.abfd)) |
| 5865 | { |
| 5866 | case bfd_target_aout_flavour: |
| 5867 | /* Assume it's an old APCS-style ABI. */ |
| 5868 | arm_abi = ARM_ABI_APCS; |
| 5869 | break; |
| 5870 | |
| 5871 | case bfd_target_coff_flavour: |
| 5872 | /* Assume it's an old APCS-style ABI. */ |
| 5873 | /* XXX WinCE? */ |
| 5874 | arm_abi = ARM_ABI_APCS; |
| 5875 | break; |
| 5876 | |
| 5877 | case bfd_target_elf_flavour: |
| 5878 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; |
| 5879 | e_flags = elf_elfheader (info.abfd)->e_flags; |
| 5880 | |
| 5881 | if (ei_osabi == ELFOSABI_ARM) |
| 5882 | { |
| 5883 | /* GNU tools used to use this value, but do not for EABI |
| 5884 | objects. There's nowhere to tag an EABI version |
| 5885 | anyway, so assume APCS. */ |
| 5886 | arm_abi = ARM_ABI_APCS; |
| 5887 | } |
| 5888 | else if (ei_osabi == ELFOSABI_NONE) |
| 5889 | { |
| 5890 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
| 5891 | |
| 5892 | switch (eabi_ver) |
| 5893 | { |
| 5894 | case EF_ARM_EABI_UNKNOWN: |
| 5895 | /* Assume GNU tools. */ |
| 5896 | arm_abi = ARM_ABI_APCS; |
| 5897 | break; |
| 5898 | |
| 5899 | case EF_ARM_EABI_VER4: |
| 5900 | case EF_ARM_EABI_VER5: |
| 5901 | arm_abi = ARM_ABI_AAPCS; |
| 5902 | /* EABI binaries default to VFP float ordering. |
| 5903 | They may also contain build attributes that can |
| 5904 | be used to identify if the VFP argument-passing |
| 5905 | ABI is in use. */ |
| 5906 | if (fp_model == ARM_FLOAT_AUTO) |
| 5907 | { |
| 5908 | #ifdef HAVE_ELF |
| 5909 | switch (bfd_elf_get_obj_attr_int (info.abfd, |
| 5910 | OBJ_ATTR_PROC, |
| 5911 | Tag_ABI_VFP_args)) |
| 5912 | { |
| 5913 | case 0: |
| 5914 | /* "The user intended FP parameter/result |
| 5915 | passing to conform to AAPCS, base |
| 5916 | variant". */ |
| 5917 | fp_model = ARM_FLOAT_SOFT_VFP; |
| 5918 | break; |
| 5919 | case 1: |
| 5920 | /* "The user intended FP parameter/result |
| 5921 | passing to conform to AAPCS, VFP |
| 5922 | variant". */ |
| 5923 | fp_model = ARM_FLOAT_VFP; |
| 5924 | break; |
| 5925 | case 2: |
| 5926 | /* "The user intended FP parameter/result |
| 5927 | passing to conform to tool chain-specific |
| 5928 | conventions" - we don't know any such |
| 5929 | conventions, so leave it as "auto". */ |
| 5930 | break; |
| 5931 | default: |
| 5932 | /* Attribute value not mentioned in the |
| 5933 | October 2008 ABI, so leave it as |
| 5934 | "auto". */ |
| 5935 | break; |
| 5936 | } |
| 5937 | #else |
| 5938 | fp_model = ARM_FLOAT_SOFT_VFP; |
| 5939 | #endif |
| 5940 | } |
| 5941 | break; |
| 5942 | |
| 5943 | default: |
| 5944 | /* Leave it as "auto". */ |
| 5945 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
| 5946 | break; |
| 5947 | } |
| 5948 | } |
| 5949 | |
| 5950 | if (fp_model == ARM_FLOAT_AUTO) |
| 5951 | { |
| 5952 | int e_flags = elf_elfheader (info.abfd)->e_flags; |
| 5953 | |
| 5954 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) |
| 5955 | { |
| 5956 | case 0: |
| 5957 | /* Leave it as "auto". Strictly speaking this case |
| 5958 | means FPA, but almost nobody uses that now, and |
| 5959 | many toolchains fail to set the appropriate bits |
| 5960 | for the floating-point model they use. */ |
| 5961 | break; |
| 5962 | case EF_ARM_SOFT_FLOAT: |
| 5963 | fp_model = ARM_FLOAT_SOFT_FPA; |
| 5964 | break; |
| 5965 | case EF_ARM_VFP_FLOAT: |
| 5966 | fp_model = ARM_FLOAT_VFP; |
| 5967 | break; |
| 5968 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: |
| 5969 | fp_model = ARM_FLOAT_SOFT_VFP; |
| 5970 | break; |
| 5971 | } |
| 5972 | } |
| 5973 | |
| 5974 | if (e_flags & EF_ARM_BE8) |
| 5975 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; |
| 5976 | |
| 5977 | break; |
| 5978 | |
| 5979 | default: |
| 5980 | /* Leave it as "auto". */ |
| 5981 | break; |
| 5982 | } |
| 5983 | } |
| 5984 | |
| 5985 | /* If there is already a candidate, use it. */ |
| 5986 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); |
| 5987 | best_arch != NULL; |
| 5988 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) |
| 5989 | { |
| 5990 | if (arm_abi != ARM_ABI_AUTO |
| 5991 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) |
| 5992 | continue; |
| 5993 | |
| 5994 | if (fp_model != ARM_FLOAT_AUTO |
| 5995 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) |
| 5996 | continue; |
| 5997 | |
| 5998 | /* There are various other properties in tdep that we do not |
| 5999 | need to check here: those derived from a target description, |
| 6000 | since gdbarches with a different target description are |
| 6001 | automatically disqualified. */ |
| 6002 | |
| 6003 | /* Found a match. */ |
| 6004 | break; |
| 6005 | } |
| 6006 | |
| 6007 | if (best_arch != NULL) |
| 6008 | { |
| 6009 | if (tdesc_data != NULL) |
| 6010 | tdesc_data_cleanup (tdesc_data); |
| 6011 | return best_arch->gdbarch; |
| 6012 | } |
| 6013 | |
| 6014 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); |
| 6015 | gdbarch = gdbarch_alloc (&info, tdep); |
| 6016 | |
| 6017 | /* Record additional information about the architecture we are defining. |
| 6018 | These are gdbarch discriminators, like the OSABI. */ |
| 6019 | tdep->arm_abi = arm_abi; |
| 6020 | tdep->fp_model = fp_model; |
| 6021 | tdep->have_fpa_registers = have_fpa_registers; |
| 6022 | tdep->have_vfp_registers = have_vfp_registers; |
| 6023 | tdep->have_vfp_pseudos = have_vfp_pseudos; |
| 6024 | tdep->have_neon_pseudos = have_neon_pseudos; |
| 6025 | tdep->have_neon = have_neon; |
| 6026 | |
| 6027 | /* Breakpoints. */ |
| 6028 | switch (info.byte_order_for_code) |
| 6029 | { |
| 6030 | case BFD_ENDIAN_BIG: |
| 6031 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
| 6032 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); |
| 6033 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; |
| 6034 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); |
| 6035 | |
| 6036 | break; |
| 6037 | |
| 6038 | case BFD_ENDIAN_LITTLE: |
| 6039 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
| 6040 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); |
| 6041 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; |
| 6042 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); |
| 6043 | |
| 6044 | break; |
| 6045 | |
| 6046 | default: |
| 6047 | internal_error (__FILE__, __LINE__, |
| 6048 | _("arm_gdbarch_init: bad byte order for float format")); |
| 6049 | } |
| 6050 | |
| 6051 | /* On ARM targets char defaults to unsigned. */ |
| 6052 | set_gdbarch_char_signed (gdbarch, 0); |
| 6053 | |
| 6054 | /* Note: for displaced stepping, this includes the breakpoint, and one word |
| 6055 | of additional scratch space. This setting isn't used for anything beside |
| 6056 | displaced stepping at present. */ |
| 6057 | set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS); |
| 6058 | |
| 6059 | /* This should be low enough for everything. */ |
| 6060 | tdep->lowest_pc = 0x20; |
| 6061 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
| 6062 | |
| 6063 | /* The default, for both APCS and AAPCS, is to return small |
| 6064 | structures in registers. */ |
| 6065 | tdep->struct_return = reg_struct_return; |
| 6066 | |
| 6067 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
| 6068 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
| 6069 | |
| 6070 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
| 6071 | |
| 6072 | /* Frame handling. */ |
| 6073 | set_gdbarch_dummy_id (gdbarch, arm_dummy_id); |
| 6074 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
| 6075 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); |
| 6076 | |
| 6077 | frame_base_set_default (gdbarch, &arm_normal_base); |
| 6078 | |
| 6079 | /* Address manipulation. */ |
| 6080 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); |
| 6081 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
| 6082 | |
| 6083 | /* Advance PC across function entry code. */ |
| 6084 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); |
| 6085 | |
| 6086 | /* Skip trampolines. */ |
| 6087 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); |
| 6088 | |
| 6089 | /* The stack grows downward. */ |
| 6090 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 6091 | |
| 6092 | /* Breakpoint manipulation. */ |
| 6093 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); |
| 6094 | |
| 6095 | /* Information about registers, etc. */ |
| 6096 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
| 6097 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
| 6098 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); |
| 6099 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
| 6100 | set_gdbarch_register_type (gdbarch, arm_register_type); |
| 6101 | |
| 6102 | /* This "info float" is FPA-specific. Use the generic version if we |
| 6103 | do not have FPA. */ |
| 6104 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) |
| 6105 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); |
| 6106 | |
| 6107 | /* Internal <-> external register number maps. */ |
| 6108 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
| 6109 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
| 6110 | |
| 6111 | set_gdbarch_register_name (gdbarch, arm_register_name); |
| 6112 | |
| 6113 | /* Returning results. */ |
| 6114 | set_gdbarch_return_value (gdbarch, arm_return_value); |
| 6115 | |
| 6116 | /* Disassembly. */ |
| 6117 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); |
| 6118 | |
| 6119 | /* Minsymbol frobbing. */ |
| 6120 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); |
| 6121 | set_gdbarch_coff_make_msymbol_special (gdbarch, |
| 6122 | arm_coff_make_msymbol_special); |
| 6123 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
| 6124 | |
| 6125 | /* Virtual tables. */ |
| 6126 | set_gdbarch_vbit_in_delta (gdbarch, 1); |
| 6127 | |
| 6128 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
| 6129 | gdbarch_init_osabi (info, gdbarch); |
| 6130 | |
| 6131 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
| 6132 | |
| 6133 | /* Add some default predicates. */ |
| 6134 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
| 6135 | dwarf2_append_unwinders (gdbarch); |
| 6136 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
| 6137 | |
| 6138 | /* Now we have tuned the configuration, set a few final things, |
| 6139 | based on what the OS ABI has told us. */ |
| 6140 | |
| 6141 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
| 6142 | binaries are always marked. */ |
| 6143 | if (tdep->arm_abi == ARM_ABI_AUTO) |
| 6144 | tdep->arm_abi = ARM_ABI_APCS; |
| 6145 | |
| 6146 | /* We used to default to FPA for generic ARM, but almost nobody |
| 6147 | uses that now, and we now provide a way for the user to force |
| 6148 | the model. So default to the most useful variant. */ |
| 6149 | if (tdep->fp_model == ARM_FLOAT_AUTO) |
| 6150 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; |
| 6151 | |
| 6152 | if (tdep->jb_pc >= 0) |
| 6153 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); |
| 6154 | |
| 6155 | /* Floating point sizes and format. */ |
| 6156 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 6157 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
| 6158 | { |
| 6159 | set_gdbarch_double_format |
| 6160 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); |
| 6161 | set_gdbarch_long_double_format |
| 6162 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); |
| 6163 | } |
| 6164 | else |
| 6165 | { |
| 6166 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); |
| 6167 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); |
| 6168 | } |
| 6169 | |
| 6170 | if (have_vfp_pseudos) |
| 6171 | { |
| 6172 | /* NOTE: These are the only pseudo registers used by |
| 6173 | the ARM target at the moment. If more are added, a |
| 6174 | little more care in numbering will be needed. */ |
| 6175 | |
| 6176 | int num_pseudos = 32; |
| 6177 | if (have_neon_pseudos) |
| 6178 | num_pseudos += 16; |
| 6179 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); |
| 6180 | set_gdbarch_pseudo_register_read (gdbarch, arm_pseudo_read); |
| 6181 | set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); |
| 6182 | } |
| 6183 | |
| 6184 | if (tdesc_data) |
| 6185 | { |
| 6186 | set_tdesc_pseudo_register_name (gdbarch, arm_register_name); |
| 6187 | |
| 6188 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
| 6189 | |
| 6190 | /* Override tdesc_register_type to adjust the types of VFP |
| 6191 | registers for NEON. */ |
| 6192 | set_gdbarch_register_type (gdbarch, arm_register_type); |
| 6193 | } |
| 6194 | |
| 6195 | /* Add standard register aliases. We add aliases even for those |
| 6196 | nanes which are used by the current architecture - it's simpler, |
| 6197 | and does no harm, since nothing ever lists user registers. */ |
| 6198 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) |
| 6199 | user_reg_add (gdbarch, arm_register_aliases[i].name, |
| 6200 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); |
| 6201 | |
| 6202 | return gdbarch; |
| 6203 | } |
| 6204 | |
| 6205 | static void |
| 6206 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
| 6207 | { |
| 6208 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 6209 | |
| 6210 | if (tdep == NULL) |
| 6211 | return; |
| 6212 | |
| 6213 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
| 6214 | (unsigned long) tdep->lowest_pc); |
| 6215 | } |
| 6216 | |
| 6217 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
| 6218 | |
| 6219 | void |
| 6220 | _initialize_arm_tdep (void) |
| 6221 | { |
| 6222 | struct ui_file *stb; |
| 6223 | long length; |
| 6224 | struct cmd_list_element *new_set, *new_show; |
| 6225 | const char *setname; |
| 6226 | const char *setdesc; |
| 6227 | const char *const *regnames; |
| 6228 | int numregs, i, j; |
| 6229 | static char *helptext; |
| 6230 | char regdesc[1024], *rdptr = regdesc; |
| 6231 | size_t rest = sizeof (regdesc); |
| 6232 | |
| 6233 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
| 6234 | |
| 6235 | arm_objfile_data_key |
| 6236 | = register_objfile_data_with_cleanup (NULL, arm_objfile_data_free); |
| 6237 | |
| 6238 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
| 6239 | gdbarch_register_osabi_sniffer (bfd_arch_arm, |
| 6240 | bfd_target_elf_flavour, |
| 6241 | arm_elf_osabi_sniffer); |
| 6242 | |
| 6243 | /* Get the number of possible sets of register names defined in opcodes. */ |
| 6244 | num_disassembly_options = get_arm_regname_num_options (); |
| 6245 | |
| 6246 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
| 6247 | add_prefix_cmd ("arm", no_class, set_arm_command, |
| 6248 | _("Various ARM-specific commands."), |
| 6249 | &setarmcmdlist, "set arm ", 0, &setlist); |
| 6250 | |
| 6251 | add_prefix_cmd ("arm", no_class, show_arm_command, |
| 6252 | _("Various ARM-specific commands."), |
| 6253 | &showarmcmdlist, "show arm ", 0, &showlist); |
| 6254 | |
| 6255 | /* Sync the opcode insn printer with our register viewer. */ |
| 6256 | parse_arm_disassembler_option ("reg-names-std"); |
| 6257 | |
| 6258 | /* Initialize the array that will be passed to |
| 6259 | add_setshow_enum_cmd(). */ |
| 6260 | valid_disassembly_styles |
| 6261 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); |
| 6262 | for (i = 0; i < num_disassembly_options; i++) |
| 6263 | { |
| 6264 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); |
| 6265 | valid_disassembly_styles[i] = setname; |
| 6266 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
| 6267 | rdptr += length; |
| 6268 | rest -= length; |
| 6269 | /* When we find the default names, tell the disassembler to use |
| 6270 | them. */ |
| 6271 | if (!strcmp (setname, "std")) |
| 6272 | { |
| 6273 | disassembly_style = setname; |
| 6274 | set_arm_regname_option (i); |
| 6275 | } |
| 6276 | } |
| 6277 | /* Mark the end of valid options. */ |
| 6278 | valid_disassembly_styles[num_disassembly_options] = NULL; |
| 6279 | |
| 6280 | /* Create the help text. */ |
| 6281 | stb = mem_fileopen (); |
| 6282 | fprintf_unfiltered (stb, "%s%s%s", |
| 6283 | _("The valid values are:\n"), |
| 6284 | regdesc, |
| 6285 | _("The default is \"std\".")); |
| 6286 | helptext = ui_file_xstrdup (stb, NULL); |
| 6287 | ui_file_delete (stb); |
| 6288 | |
| 6289 | add_setshow_enum_cmd("disassembler", no_class, |
| 6290 | valid_disassembly_styles, &disassembly_style, |
| 6291 | _("Set the disassembly style."), |
| 6292 | _("Show the disassembly style."), |
| 6293 | helptext, |
| 6294 | set_disassembly_style_sfunc, |
| 6295 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
| 6296 | &setarmcmdlist, &showarmcmdlist); |
| 6297 | |
| 6298 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, |
| 6299 | _("Set usage of ARM 32-bit mode."), |
| 6300 | _("Show usage of ARM 32-bit mode."), |
| 6301 | _("When off, a 26-bit PC will be used."), |
| 6302 | NULL, |
| 6303 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
| 6304 | &setarmcmdlist, &showarmcmdlist); |
| 6305 | |
| 6306 | /* Add a command to allow the user to force the FPU model. */ |
| 6307 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
| 6308 | _("Set the floating point type."), |
| 6309 | _("Show the floating point type."), |
| 6310 | _("auto - Determine the FP typefrom the OS-ABI.\n\ |
| 6311 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ |
| 6312 | fpa - FPA co-processor (GCC compiled).\n\ |
| 6313 | softvfp - Software FP with pure-endian doubles.\n\ |
| 6314 | vfp - VFP co-processor."), |
| 6315 | set_fp_model_sfunc, show_fp_model, |
| 6316 | &setarmcmdlist, &showarmcmdlist); |
| 6317 | |
| 6318 | /* Add a command to allow the user to force the ABI. */ |
| 6319 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, |
| 6320 | _("Set the ABI."), |
| 6321 | _("Show the ABI."), |
| 6322 | NULL, arm_set_abi, arm_show_abi, |
| 6323 | &setarmcmdlist, &showarmcmdlist); |
| 6324 | |
| 6325 | /* Add two commands to allow the user to force the assumed |
| 6326 | execution mode. */ |
| 6327 | add_setshow_enum_cmd ("fallback-mode", class_support, |
| 6328 | arm_mode_strings, &arm_fallback_mode_string, |
| 6329 | _("Set the mode assumed when symbols are unavailable."), |
| 6330 | _("Show the mode assumed when symbols are unavailable."), |
| 6331 | NULL, NULL, arm_show_fallback_mode, |
| 6332 | &setarmcmdlist, &showarmcmdlist); |
| 6333 | add_setshow_enum_cmd ("force-mode", class_support, |
| 6334 | arm_mode_strings, &arm_force_mode_string, |
| 6335 | _("Set the mode assumed even when symbols are available."), |
| 6336 | _("Show the mode assumed even when symbols are available."), |
| 6337 | NULL, NULL, arm_show_force_mode, |
| 6338 | &setarmcmdlist, &showarmcmdlist); |
| 6339 | |
| 6340 | /* Debugging flag. */ |
| 6341 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
| 6342 | _("Set ARM debugging."), |
| 6343 | _("Show ARM debugging."), |
| 6344 | _("When on, arm-specific debugging is enabled."), |
| 6345 | NULL, |
| 6346 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
| 6347 | &setdebuglist, &showdebuglist); |
| 6348 | } |