| 1 | /* Common target dependent code for GDB on ARM systems. |
| 2 | |
| 3 | Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, |
| 4 | 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 2 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program; if not, write to the Free Software |
| 20 | Foundation, Inc., 59 Temple Place - Suite 330, |
| 21 | Boston, MA 02111-1307, USA. */ |
| 22 | |
| 23 | #include <ctype.h> /* XXX for isupper () */ |
| 24 | |
| 25 | #include "defs.h" |
| 26 | #include "frame.h" |
| 27 | #include "inferior.h" |
| 28 | #include "gdbcmd.h" |
| 29 | #include "gdbcore.h" |
| 30 | #include "gdb_string.h" |
| 31 | #include "dis-asm.h" /* For register styles. */ |
| 32 | #include "regcache.h" |
| 33 | #include "doublest.h" |
| 34 | #include "value.h" |
| 35 | #include "arch-utils.h" |
| 36 | #include "osabi.h" |
| 37 | #include "frame-unwind.h" |
| 38 | #include "frame-base.h" |
| 39 | #include "trad-frame.h" |
| 40 | #include "objfiles.h" |
| 41 | #include "dwarf2-frame.h" |
| 42 | |
| 43 | #include "arm-tdep.h" |
| 44 | #include "gdb/sim-arm.h" |
| 45 | |
| 46 | #include "elf-bfd.h" |
| 47 | #include "coff/internal.h" |
| 48 | #include "elf/arm.h" |
| 49 | |
| 50 | #include "gdb_assert.h" |
| 51 | |
| 52 | static int arm_debug; |
| 53 | |
| 54 | /* Each OS has a different mechanism for accessing the various |
| 55 | registers stored in the sigcontext structure. |
| 56 | |
| 57 | SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or |
| 58 | function pointer) which may be used to determine the addresses |
| 59 | of the various saved registers in the sigcontext structure. |
| 60 | |
| 61 | For the ARM target, there are three parameters to this function. |
| 62 | The first is the pc value of the frame under consideration, the |
| 63 | second the stack pointer of this frame, and the last is the |
| 64 | register number to fetch. |
| 65 | |
| 66 | If the tm.h file does not define this macro, then it's assumed that |
| 67 | no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to |
| 68 | be 0. |
| 69 | |
| 70 | When it comes time to multi-arching this code, see the identically |
| 71 | named machinery in ia64-tdep.c for an example of how it could be |
| 72 | done. It should not be necessary to modify the code below where |
| 73 | this macro is used. */ |
| 74 | |
| 75 | #ifdef SIGCONTEXT_REGISTER_ADDRESS |
| 76 | #ifndef SIGCONTEXT_REGISTER_ADDRESS_P |
| 77 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 1 |
| 78 | #endif |
| 79 | #else |
| 80 | #define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0 |
| 81 | #define SIGCONTEXT_REGISTER_ADDRESS_P() 0 |
| 82 | #endif |
| 83 | |
| 84 | /* Macros for setting and testing a bit in a minimal symbol that marks |
| 85 | it as Thumb function. The MSB of the minimal symbol's "info" field |
| 86 | is used for this purpose. |
| 87 | |
| 88 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. |
| 89 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
| 90 | |
| 91 | #define MSYMBOL_SET_SPECIAL(msym) \ |
| 92 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ |
| 93 | | 0x80000000) |
| 94 | |
| 95 | #define MSYMBOL_IS_SPECIAL(msym) \ |
| 96 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) |
| 97 | |
| 98 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
| 99 | static struct cmd_list_element *setarmcmdlist = NULL; |
| 100 | static struct cmd_list_element *showarmcmdlist = NULL; |
| 101 | |
| 102 | /* The type of floating-point to use. Keep this in sync with enum |
| 103 | arm_float_model, and the help string in _initialize_arm_tdep. */ |
| 104 | static const char *fp_model_strings[] = |
| 105 | { |
| 106 | "auto", |
| 107 | "softfpa", |
| 108 | "fpa", |
| 109 | "softvfp", |
| 110 | "vfp", |
| 111 | NULL |
| 112 | }; |
| 113 | |
| 114 | /* A variable that can be configured by the user. */ |
| 115 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; |
| 116 | static const char *current_fp_model = "auto"; |
| 117 | |
| 118 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
| 119 | static const char *arm_abi_strings[] = |
| 120 | { |
| 121 | "auto", |
| 122 | "APCS", |
| 123 | "AAPCS", |
| 124 | NULL |
| 125 | }; |
| 126 | |
| 127 | /* A variable that can be configured by the user. */ |
| 128 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; |
| 129 | static const char *arm_abi_string = "auto"; |
| 130 | |
| 131 | /* Number of different reg name sets (options). */ |
| 132 | static int num_disassembly_options; |
| 133 | |
| 134 | /* We have more registers than the disassembler as gdb can print the value |
| 135 | of special registers as well. |
| 136 | The general register names are overwritten by whatever is being used by |
| 137 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
| 138 | |
| 139 | /* Initial value: Register names used in ARM's ISA documentation. */ |
| 140 | static char * arm_register_name_strings[] = |
| 141 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
| 142 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ |
| 143 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ |
| 144 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ |
| 145 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ |
| 146 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ |
| 147 | "fps", "cpsr" }; /* 24 25 */ |
| 148 | static char **arm_register_names = arm_register_name_strings; |
| 149 | |
| 150 | /* Valid register name styles. */ |
| 151 | static const char **valid_disassembly_styles; |
| 152 | |
| 153 | /* Disassembly style to use. Default to "std" register names. */ |
| 154 | static const char *disassembly_style; |
| 155 | /* Index to that option in the opcodes table. */ |
| 156 | static int current_option; |
| 157 | |
| 158 | /* This is used to keep the bfd arch_info in sync with the disassembly |
| 159 | style. */ |
| 160 | static void set_disassembly_style_sfunc(char *, int, |
| 161 | struct cmd_list_element *); |
| 162 | static void set_disassembly_style (void); |
| 163 | |
| 164 | static void convert_from_extended (const struct floatformat *, const void *, |
| 165 | void *); |
| 166 | static void convert_to_extended (const struct floatformat *, void *, |
| 167 | const void *); |
| 168 | |
| 169 | struct arm_prologue_cache |
| 170 | { |
| 171 | /* The stack pointer at the time this frame was created; i.e. the |
| 172 | caller's stack pointer when this function was called. It is used |
| 173 | to identify this frame. */ |
| 174 | CORE_ADDR prev_sp; |
| 175 | |
| 176 | /* The frame base for this frame is just prev_sp + frame offset - |
| 177 | frame size. FRAMESIZE is the size of this stack frame, and |
| 178 | FRAMEOFFSET if the initial offset from the stack pointer (this |
| 179 | frame's stack pointer, not PREV_SP) to the frame base. */ |
| 180 | |
| 181 | int framesize; |
| 182 | int frameoffset; |
| 183 | |
| 184 | /* The register used to hold the frame pointer for this frame. */ |
| 185 | int framereg; |
| 186 | |
| 187 | /* Saved register offsets. */ |
| 188 | struct trad_frame_saved_reg *saved_regs; |
| 189 | }; |
| 190 | |
| 191 | /* Addresses for calling Thumb functions have the bit 0 set. |
| 192 | Here are some macros to test, set, or clear bit 0 of addresses. */ |
| 193 | #define IS_THUMB_ADDR(addr) ((addr) & 1) |
| 194 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) |
| 195 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) |
| 196 | |
| 197 | /* Set to true if the 32-bit mode is in use. */ |
| 198 | |
| 199 | int arm_apcs_32 = 1; |
| 200 | |
| 201 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
| 202 | function. */ |
| 203 | |
| 204 | int |
| 205 | arm_pc_is_thumb (CORE_ADDR memaddr) |
| 206 | { |
| 207 | struct minimal_symbol *sym; |
| 208 | |
| 209 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
| 210 | if (IS_THUMB_ADDR (memaddr)) |
| 211 | return 1; |
| 212 | |
| 213 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
| 214 | sym = lookup_minimal_symbol_by_pc (memaddr); |
| 215 | if (sym) |
| 216 | { |
| 217 | return (MSYMBOL_IS_SPECIAL (sym)); |
| 218 | } |
| 219 | else |
| 220 | { |
| 221 | return 0; |
| 222 | } |
| 223 | } |
| 224 | |
| 225 | /* Remove useless bits from addresses in a running program. */ |
| 226 | static CORE_ADDR |
| 227 | arm_addr_bits_remove (CORE_ADDR val) |
| 228 | { |
| 229 | if (arm_apcs_32) |
| 230 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); |
| 231 | else |
| 232 | return (val & 0x03fffffc); |
| 233 | } |
| 234 | |
| 235 | /* When reading symbols, we need to zap the low bit of the address, |
| 236 | which may be set to 1 for Thumb functions. */ |
| 237 | static CORE_ADDR |
| 238 | arm_smash_text_address (CORE_ADDR val) |
| 239 | { |
| 240 | return val & ~1; |
| 241 | } |
| 242 | |
| 243 | /* Immediately after a function call, return the saved pc. Can't |
| 244 | always go through the frames for this because on some machines the |
| 245 | new frame is not set up until the new function executes some |
| 246 | instructions. */ |
| 247 | |
| 248 | static CORE_ADDR |
| 249 | arm_saved_pc_after_call (struct frame_info *frame) |
| 250 | { |
| 251 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
| 252 | } |
| 253 | |
| 254 | /* A typical Thumb prologue looks like this: |
| 255 | push {r7, lr} |
| 256 | add sp, sp, #-28 |
| 257 | add r7, sp, #12 |
| 258 | Sometimes the latter instruction may be replaced by: |
| 259 | mov r7, sp |
| 260 | |
| 261 | or like this: |
| 262 | push {r7, lr} |
| 263 | mov r7, sp |
| 264 | sub sp, #12 |
| 265 | |
| 266 | or, on tpcs, like this: |
| 267 | sub sp,#16 |
| 268 | push {r7, lr} |
| 269 | (many instructions) |
| 270 | mov r7, sp |
| 271 | sub sp, #12 |
| 272 | |
| 273 | There is always one instruction of three classes: |
| 274 | 1 - push |
| 275 | 2 - setting of r7 |
| 276 | 3 - adjusting of sp |
| 277 | |
| 278 | When we have found at least one of each class we are done with the prolog. |
| 279 | Note that the "sub sp, #NN" before the push does not count. |
| 280 | */ |
| 281 | |
| 282 | static CORE_ADDR |
| 283 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
| 284 | { |
| 285 | CORE_ADDR current_pc; |
| 286 | /* findmask: |
| 287 | bit 0 - push { rlist } |
| 288 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) |
| 289 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) |
| 290 | */ |
| 291 | int findmask = 0; |
| 292 | |
| 293 | for (current_pc = pc; |
| 294 | current_pc + 2 < func_end && current_pc < pc + 40; |
| 295 | current_pc += 2) |
| 296 | { |
| 297 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); |
| 298 | |
| 299 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 300 | { |
| 301 | findmask |= 1; /* push found */ |
| 302 | } |
| 303 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
| 304 | sub sp, #simm */ |
| 305 | { |
| 306 | if ((findmask & 1) == 0) /* before push ? */ |
| 307 | continue; |
| 308 | else |
| 309 | findmask |= 4; /* add/sub sp found */ |
| 310 | } |
| 311 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 312 | { |
| 313 | findmask |= 2; /* setting of r7 found */ |
| 314 | } |
| 315 | else if (insn == 0x466f) /* mov r7, sp */ |
| 316 | { |
| 317 | findmask |= 2; /* setting of r7 found */ |
| 318 | } |
| 319 | else if (findmask == (4+2+1)) |
| 320 | { |
| 321 | /* We have found one of each type of prologue instruction */ |
| 322 | break; |
| 323 | } |
| 324 | else |
| 325 | /* Something in the prolog that we don't care about or some |
| 326 | instruction from outside the prolog scheduled here for |
| 327 | optimization. */ |
| 328 | continue; |
| 329 | } |
| 330 | |
| 331 | return current_pc; |
| 332 | } |
| 333 | |
| 334 | /* Advance the PC across any function entry prologue instructions to |
| 335 | reach some "real" code. |
| 336 | |
| 337 | The APCS (ARM Procedure Call Standard) defines the following |
| 338 | prologue: |
| 339 | |
| 340 | mov ip, sp |
| 341 | [stmfd sp!, {a1,a2,a3,a4}] |
| 342 | stmfd sp!, {...,fp,ip,lr,pc} |
| 343 | [stfe f7, [sp, #-12]!] |
| 344 | [stfe f6, [sp, #-12]!] |
| 345 | [stfe f5, [sp, #-12]!] |
| 346 | [stfe f4, [sp, #-12]!] |
| 347 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ |
| 348 | |
| 349 | static CORE_ADDR |
| 350 | arm_skip_prologue (CORE_ADDR pc) |
| 351 | { |
| 352 | unsigned long inst; |
| 353 | CORE_ADDR skip_pc; |
| 354 | CORE_ADDR func_addr, func_end = 0; |
| 355 | char *func_name; |
| 356 | struct symtab_and_line sal; |
| 357 | |
| 358 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
| 359 | if (deprecated_pc_in_call_dummy (pc)) |
| 360 | return pc; |
| 361 | |
| 362 | /* See what the symbol table says. */ |
| 363 | |
| 364 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
| 365 | { |
| 366 | struct symbol *sym; |
| 367 | |
| 368 | /* Found a function. */ |
| 369 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
| 370 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
| 371 | { |
| 372 | /* Don't use this trick for assembly source files. */ |
| 373 | sal = find_pc_line (func_addr, 0); |
| 374 | if ((sal.line != 0) && (sal.end < func_end)) |
| 375 | return sal.end; |
| 376 | } |
| 377 | } |
| 378 | |
| 379 | /* Check if this is Thumb code. */ |
| 380 | if (arm_pc_is_thumb (pc)) |
| 381 | return thumb_skip_prologue (pc, func_end); |
| 382 | |
| 383 | /* Can't find the prologue end in the symbol table, try it the hard way |
| 384 | by disassembling the instructions. */ |
| 385 | |
| 386 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
| 387 | if (func_end == 0 || func_end > pc + 64) |
| 388 | func_end = pc + 64; |
| 389 | |
| 390 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
| 391 | { |
| 392 | inst = read_memory_integer (skip_pc, 4); |
| 393 | |
| 394 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
| 395 | if (inst == 0xe1a0c00d) /* mov ip, sp */ |
| 396 | continue; |
| 397 | |
| 398 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
| 399 | continue; |
| 400 | |
| 401 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ |
| 402 | continue; |
| 403 | |
| 404 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
| 405 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 406 | continue; |
| 407 | |
| 408 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
| 409 | continue; |
| 410 | |
| 411 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
| 412 | continue; |
| 413 | |
| 414 | /* Any insns after this point may float into the code, if it makes |
| 415 | for better instruction scheduling, so we skip them only if we |
| 416 | find them, but still consider the function to be frame-ful. */ |
| 417 | |
| 418 | /* We may have either one sfmfd instruction here, or several stfe |
| 419 | insns, depending on the version of floating point code we |
| 420 | support. */ |
| 421 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
| 422 | continue; |
| 423 | |
| 424 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
| 425 | continue; |
| 426 | |
| 427 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
| 428 | continue; |
| 429 | |
| 430 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ |
| 431 | continue; |
| 432 | |
| 433 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ |
| 434 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ |
| 435 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ |
| 436 | continue; |
| 437 | |
| 438 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ |
| 439 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ |
| 440 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ |
| 441 | continue; |
| 442 | |
| 443 | /* Un-recognized instruction; stop scanning. */ |
| 444 | break; |
| 445 | } |
| 446 | |
| 447 | return skip_pc; /* End of prologue */ |
| 448 | } |
| 449 | |
| 450 | /* *INDENT-OFF* */ |
| 451 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
| 452 | This function decodes a Thumb function prologue to determine: |
| 453 | 1) the size of the stack frame |
| 454 | 2) which registers are saved on it |
| 455 | 3) the offsets of saved regs |
| 456 | 4) the offset from the stack pointer to the frame pointer |
| 457 | |
| 458 | A typical Thumb function prologue would create this stack frame |
| 459 | (offsets relative to FP) |
| 460 | old SP -> 24 stack parameters |
| 461 | 20 LR |
| 462 | 16 R7 |
| 463 | R7 -> 0 local variables (16 bytes) |
| 464 | SP -> -12 additional stack space (12 bytes) |
| 465 | The frame size would thus be 36 bytes, and the frame offset would be |
| 466 | 12 bytes. The frame register is R7. |
| 467 | |
| 468 | The comments for thumb_skip_prolog() describe the algorithm we use |
| 469 | to detect the end of the prolog. */ |
| 470 | /* *INDENT-ON* */ |
| 471 | |
| 472 | static void |
| 473 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
| 474 | { |
| 475 | CORE_ADDR prologue_start; |
| 476 | CORE_ADDR prologue_end; |
| 477 | CORE_ADDR current_pc; |
| 478 | /* Which register has been copied to register n? */ |
| 479 | int saved_reg[16]; |
| 480 | /* findmask: |
| 481 | bit 0 - push { rlist } |
| 482 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) |
| 483 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) |
| 484 | */ |
| 485 | int findmask = 0; |
| 486 | int i; |
| 487 | |
| 488 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
| 489 | { |
| 490 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 491 | |
| 492 | if (sal.line == 0) /* no line info, use current PC */ |
| 493 | prologue_end = prev_pc; |
| 494 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
| 495 | prologue_end = sal.end; /* (probably means no prologue) */ |
| 496 | } |
| 497 | else |
| 498 | /* We're in the boondocks: allow for |
| 499 | 16 pushes, an add, and "mv fp,sp". */ |
| 500 | prologue_end = prologue_start + 40; |
| 501 | |
| 502 | prologue_end = min (prologue_end, prev_pc); |
| 503 | |
| 504 | /* Initialize the saved register map. When register H is copied to |
| 505 | register L, we will put H in saved_reg[L]. */ |
| 506 | for (i = 0; i < 16; i++) |
| 507 | saved_reg[i] = i; |
| 508 | |
| 509 | /* Search the prologue looking for instructions that set up the |
| 510 | frame pointer, adjust the stack pointer, and save registers. |
| 511 | Do this until all basic prolog instructions are found. */ |
| 512 | |
| 513 | cache->framesize = 0; |
| 514 | for (current_pc = prologue_start; |
| 515 | (current_pc < prologue_end) && ((findmask & 7) != 7); |
| 516 | current_pc += 2) |
| 517 | { |
| 518 | unsigned short insn; |
| 519 | int regno; |
| 520 | int offset; |
| 521 | |
| 522 | insn = read_memory_unsigned_integer (current_pc, 2); |
| 523 | |
| 524 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 525 | { |
| 526 | int mask; |
| 527 | findmask |= 1; /* push found */ |
| 528 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
| 529 | whether to save LR (R14). */ |
| 530 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
| 531 | |
| 532 | /* Calculate offsets of saved R0-R7 and LR. */ |
| 533 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
| 534 | if (mask & (1 << regno)) |
| 535 | { |
| 536 | cache->framesize += 4; |
| 537 | cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; |
| 538 | /* Reset saved register map. */ |
| 539 | saved_reg[regno] = regno; |
| 540 | } |
| 541 | } |
| 542 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
| 543 | sub sp, #simm */ |
| 544 | { |
| 545 | if ((findmask & 1) == 0) /* before push? */ |
| 546 | continue; |
| 547 | else |
| 548 | findmask |= 4; /* add/sub sp found */ |
| 549 | |
| 550 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
| 551 | if (insn & 0x80) /* is it signed? (==subtracting) */ |
| 552 | { |
| 553 | cache->frameoffset += offset; |
| 554 | offset = -offset; |
| 555 | } |
| 556 | cache->framesize -= offset; |
| 557 | } |
| 558 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 559 | { |
| 560 | findmask |= 2; /* setting of r7 found */ |
| 561 | cache->framereg = THUMB_FP_REGNUM; |
| 562 | /* get scaled offset */ |
| 563 | cache->frameoffset = (insn & 0xff) << 2; |
| 564 | } |
| 565 | else if (insn == 0x466f) /* mov r7, sp */ |
| 566 | { |
| 567 | findmask |= 2; /* setting of r7 found */ |
| 568 | cache->framereg = THUMB_FP_REGNUM; |
| 569 | cache->frameoffset = 0; |
| 570 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
| 571 | } |
| 572 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ |
| 573 | { |
| 574 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
| 575 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
| 576 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
| 577 | } |
| 578 | else |
| 579 | /* Something in the prolog that we don't care about or some |
| 580 | instruction from outside the prolog scheduled here for |
| 581 | optimization. */ |
| 582 | continue; |
| 583 | } |
| 584 | } |
| 585 | |
| 586 | /* This function decodes an ARM function prologue to determine: |
| 587 | 1) the size of the stack frame |
| 588 | 2) which registers are saved on it |
| 589 | 3) the offsets of saved regs |
| 590 | 4) the offset from the stack pointer to the frame pointer |
| 591 | This information is stored in the "extra" fields of the frame_info. |
| 592 | |
| 593 | There are two basic forms for the ARM prologue. The fixed argument |
| 594 | function call will look like: |
| 595 | |
| 596 | mov ip, sp |
| 597 | stmfd sp!, {fp, ip, lr, pc} |
| 598 | sub fp, ip, #4 |
| 599 | [sub sp, sp, #4] |
| 600 | |
| 601 | Which would create this stack frame (offsets relative to FP): |
| 602 | IP -> 4 (caller's stack) |
| 603 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 604 | -4 LR (return address in caller) |
| 605 | -8 IP (copy of caller's SP) |
| 606 | -12 FP (caller's FP) |
| 607 | SP -> -28 Local variables |
| 608 | |
| 609 | The frame size would thus be 32 bytes, and the frame offset would be |
| 610 | 28 bytes. The stmfd call can also save any of the vN registers it |
| 611 | plans to use, which increases the frame size accordingly. |
| 612 | |
| 613 | Note: The stored PC is 8 off of the STMFD instruction that stored it |
| 614 | because the ARM Store instructions always store PC + 8 when you read |
| 615 | the PC register. |
| 616 | |
| 617 | A variable argument function call will look like: |
| 618 | |
| 619 | mov ip, sp |
| 620 | stmfd sp!, {a1, a2, a3, a4} |
| 621 | stmfd sp!, {fp, ip, lr, pc} |
| 622 | sub fp, ip, #20 |
| 623 | |
| 624 | Which would create this stack frame (offsets relative to FP): |
| 625 | IP -> 20 (caller's stack) |
| 626 | 16 A4 |
| 627 | 12 A3 |
| 628 | 8 A2 |
| 629 | 4 A1 |
| 630 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 631 | -4 LR (return address in caller) |
| 632 | -8 IP (copy of caller's SP) |
| 633 | -12 FP (caller's FP) |
| 634 | SP -> -28 Local variables |
| 635 | |
| 636 | The frame size would thus be 48 bytes, and the frame offset would be |
| 637 | 28 bytes. |
| 638 | |
| 639 | There is another potential complication, which is that the optimizer |
| 640 | will try to separate the store of fp in the "stmfd" instruction from |
| 641 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so |
| 642 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... |
| 643 | |
| 644 | Also, note, the original version of the ARM toolchain claimed that there |
| 645 | should be an |
| 646 | |
| 647 | instruction at the end of the prologue. I have never seen GCC produce |
| 648 | this, and the ARM docs don't mention it. We still test for it below in |
| 649 | case it happens... |
| 650 | |
| 651 | */ |
| 652 | |
| 653 | static void |
| 654 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
| 655 | { |
| 656 | int regno, sp_offset, fp_offset, ip_offset; |
| 657 | CORE_ADDR prologue_start, prologue_end, current_pc; |
| 658 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
| 659 | |
| 660 | /* Assume there is no frame until proven otherwise. */ |
| 661 | cache->framereg = ARM_SP_REGNUM; |
| 662 | cache->framesize = 0; |
| 663 | cache->frameoffset = 0; |
| 664 | |
| 665 | /* Check for Thumb prologue. */ |
| 666 | if (arm_pc_is_thumb (prev_pc)) |
| 667 | { |
| 668 | thumb_scan_prologue (prev_pc, cache); |
| 669 | return; |
| 670 | } |
| 671 | |
| 672 | /* Find the function prologue. If we can't find the function in |
| 673 | the symbol table, peek in the stack frame to find the PC. */ |
| 674 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
| 675 | { |
| 676 | /* One way to find the end of the prologue (which works well |
| 677 | for unoptimized code) is to do the following: |
| 678 | |
| 679 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 680 | |
| 681 | if (sal.line == 0) |
| 682 | prologue_end = prev_pc; |
| 683 | else if (sal.end < prologue_end) |
| 684 | prologue_end = sal.end; |
| 685 | |
| 686 | This mechanism is very accurate so long as the optimizer |
| 687 | doesn't move any instructions from the function body into the |
| 688 | prologue. If this happens, sal.end will be the last |
| 689 | instruction in the first hunk of prologue code just before |
| 690 | the first instruction that the scheduler has moved from |
| 691 | the body to the prologue. |
| 692 | |
| 693 | In order to make sure that we scan all of the prologue |
| 694 | instructions, we use a slightly less accurate mechanism which |
| 695 | may scan more than necessary. To help compensate for this |
| 696 | lack of accuracy, the prologue scanning loop below contains |
| 697 | several clauses which'll cause the loop to terminate early if |
| 698 | an implausible prologue instruction is encountered. |
| 699 | |
| 700 | The expression |
| 701 | |
| 702 | prologue_start + 64 |
| 703 | |
| 704 | is a suitable endpoint since it accounts for the largest |
| 705 | possible prologue plus up to five instructions inserted by |
| 706 | the scheduler. */ |
| 707 | |
| 708 | if (prologue_end > prologue_start + 64) |
| 709 | { |
| 710 | prologue_end = prologue_start + 64; /* See above. */ |
| 711 | } |
| 712 | } |
| 713 | else |
| 714 | { |
| 715 | /* We have no symbol information. Our only option is to assume this |
| 716 | function has a standard stack frame and the normal frame register. |
| 717 | Then, we can find the value of our frame pointer on entrance to |
| 718 | the callee (or at the present moment if this is the innermost frame). |
| 719 | The value stored there should be the address of the stmfd + 8. */ |
| 720 | CORE_ADDR frame_loc; |
| 721 | LONGEST return_value; |
| 722 | |
| 723 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); |
| 724 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) |
| 725 | return; |
| 726 | else |
| 727 | { |
| 728 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; |
| 729 | prologue_end = prologue_start + 64; /* See above. */ |
| 730 | } |
| 731 | } |
| 732 | |
| 733 | if (prev_pc < prologue_end) |
| 734 | prologue_end = prev_pc; |
| 735 | |
| 736 | /* Now search the prologue looking for instructions that set up the |
| 737 | frame pointer, adjust the stack pointer, and save registers. |
| 738 | |
| 739 | Be careful, however, and if it doesn't look like a prologue, |
| 740 | don't try to scan it. If, for instance, a frameless function |
| 741 | begins with stmfd sp!, then we will tell ourselves there is |
| 742 | a frame, which will confuse stack traceback, as well as "finish" |
| 743 | and other operations that rely on a knowledge of the stack |
| 744 | traceback. |
| 745 | |
| 746 | In the APCS, the prologue should start with "mov ip, sp" so |
| 747 | if we don't see this as the first insn, we will stop. |
| 748 | |
| 749 | [Note: This doesn't seem to be true any longer, so it's now an |
| 750 | optional part of the prologue. - Kevin Buettner, 2001-11-20] |
| 751 | |
| 752 | [Note further: The "mov ip,sp" only seems to be missing in |
| 753 | frameless functions at optimization level "-O2" or above, |
| 754 | in which case it is often (but not always) replaced by |
| 755 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
| 756 | |
| 757 | sp_offset = fp_offset = ip_offset = 0; |
| 758 | |
| 759 | for (current_pc = prologue_start; |
| 760 | current_pc < prologue_end; |
| 761 | current_pc += 4) |
| 762 | { |
| 763 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
| 764 | |
| 765 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
| 766 | { |
| 767 | ip_offset = 0; |
| 768 | continue; |
| 769 | } |
| 770 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
| 771 | { |
| 772 | unsigned imm = insn & 0xff; /* immediate value */ |
| 773 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 774 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 775 | ip_offset = imm; |
| 776 | continue; |
| 777 | } |
| 778 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ |
| 779 | { |
| 780 | unsigned imm = insn & 0xff; /* immediate value */ |
| 781 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 782 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 783 | ip_offset = -imm; |
| 784 | continue; |
| 785 | } |
| 786 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 787 | { |
| 788 | sp_offset -= 4; |
| 789 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; |
| 790 | continue; |
| 791 | } |
| 792 | else if ((insn & 0xffff0000) == 0xe92d0000) |
| 793 | /* stmfd sp!, {..., fp, ip, lr, pc} |
| 794 | or |
| 795 | stmfd sp!, {a1, a2, a3, a4} */ |
| 796 | { |
| 797 | int mask = insn & 0xffff; |
| 798 | |
| 799 | /* Calculate offsets of saved registers. */ |
| 800 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
| 801 | if (mask & (1 << regno)) |
| 802 | { |
| 803 | sp_offset -= 4; |
| 804 | cache->saved_regs[regno].addr = sp_offset; |
| 805 | } |
| 806 | } |
| 807 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
| 808 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ |
| 809 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
| 810 | { |
| 811 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 812 | continue; |
| 813 | } |
| 814 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ |
| 815 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ |
| 816 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
| 817 | { |
| 818 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 819 | continue; |
| 820 | } |
| 821 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
| 822 | { |
| 823 | unsigned imm = insn & 0xff; /* immediate value */ |
| 824 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 825 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 826 | fp_offset = -imm + ip_offset; |
| 827 | cache->framereg = ARM_FP_REGNUM; |
| 828 | } |
| 829 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ |
| 830 | { |
| 831 | unsigned imm = insn & 0xff; /* immediate value */ |
| 832 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 833 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 834 | sp_offset -= imm; |
| 835 | } |
| 836 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ |
| 837 | { |
| 838 | sp_offset -= 12; |
| 839 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
| 840 | cache->saved_regs[regno].addr = sp_offset; |
| 841 | } |
| 842 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ |
| 843 | { |
| 844 | int n_saved_fp_regs; |
| 845 | unsigned int fp_start_reg, fp_bound_reg; |
| 846 | |
| 847 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
| 848 | { |
| 849 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 850 | n_saved_fp_regs = 3; |
| 851 | else |
| 852 | n_saved_fp_regs = 1; |
| 853 | } |
| 854 | else |
| 855 | { |
| 856 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 857 | n_saved_fp_regs = 2; |
| 858 | else |
| 859 | n_saved_fp_regs = 4; |
| 860 | } |
| 861 | |
| 862 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
| 863 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
| 864 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) |
| 865 | { |
| 866 | sp_offset -= 12; |
| 867 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
| 868 | } |
| 869 | } |
| 870 | else if ((insn & 0xf0000000) != 0xe0000000) |
| 871 | break; /* Condition not true, exit early */ |
| 872 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
| 873 | break; /* Don't scan past a block load */ |
| 874 | else |
| 875 | /* The optimizer might shove anything into the prologue, |
| 876 | so we just skip what we don't recognize. */ |
| 877 | continue; |
| 878 | } |
| 879 | |
| 880 | /* The frame size is just the negative of the offset (from the |
| 881 | original SP) of the last thing thing we pushed on the stack. |
| 882 | The frame offset is [new FP] - [new SP]. */ |
| 883 | cache->framesize = -sp_offset; |
| 884 | if (cache->framereg == ARM_FP_REGNUM) |
| 885 | cache->frameoffset = fp_offset - sp_offset; |
| 886 | else |
| 887 | cache->frameoffset = 0; |
| 888 | } |
| 889 | |
| 890 | static struct arm_prologue_cache * |
| 891 | arm_make_prologue_cache (struct frame_info *next_frame) |
| 892 | { |
| 893 | int reg; |
| 894 | struct arm_prologue_cache *cache; |
| 895 | CORE_ADDR unwound_fp; |
| 896 | |
| 897 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
| 898 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 899 | |
| 900 | arm_scan_prologue (next_frame, cache); |
| 901 | |
| 902 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
| 903 | if (unwound_fp == 0) |
| 904 | return cache; |
| 905 | |
| 906 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
| 907 | |
| 908 | /* Calculate actual addresses of saved registers using offsets |
| 909 | determined by arm_scan_prologue. */ |
| 910 | for (reg = 0; reg < NUM_REGS; reg++) |
| 911 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
| 912 | cache->saved_regs[reg].addr += cache->prev_sp; |
| 913 | |
| 914 | return cache; |
| 915 | } |
| 916 | |
| 917 | /* Our frame ID for a normal frame is the current function's starting PC |
| 918 | and the caller's SP when we were called. */ |
| 919 | |
| 920 | static void |
| 921 | arm_prologue_this_id (struct frame_info *next_frame, |
| 922 | void **this_cache, |
| 923 | struct frame_id *this_id) |
| 924 | { |
| 925 | struct arm_prologue_cache *cache; |
| 926 | struct frame_id id; |
| 927 | CORE_ADDR func; |
| 928 | |
| 929 | if (*this_cache == NULL) |
| 930 | *this_cache = arm_make_prologue_cache (next_frame); |
| 931 | cache = *this_cache; |
| 932 | |
| 933 | func = frame_func_unwind (next_frame); |
| 934 | |
| 935 | /* This is meant to halt the backtrace at "_start". Make sure we |
| 936 | don't halt it at a generic dummy frame. */ |
| 937 | if (func <= LOWEST_PC) |
| 938 | return; |
| 939 | |
| 940 | /* If we've hit a wall, stop. */ |
| 941 | if (cache->prev_sp == 0) |
| 942 | return; |
| 943 | |
| 944 | id = frame_id_build (cache->prev_sp, func); |
| 945 | *this_id = id; |
| 946 | } |
| 947 | |
| 948 | static void |
| 949 | arm_prologue_prev_register (struct frame_info *next_frame, |
| 950 | void **this_cache, |
| 951 | int prev_regnum, |
| 952 | int *optimized, |
| 953 | enum lval_type *lvalp, |
| 954 | CORE_ADDR *addrp, |
| 955 | int *realnump, |
| 956 | void *valuep) |
| 957 | { |
| 958 | struct arm_prologue_cache *cache; |
| 959 | |
| 960 | if (*this_cache == NULL) |
| 961 | *this_cache = arm_make_prologue_cache (next_frame); |
| 962 | cache = *this_cache; |
| 963 | |
| 964 | /* If we are asked to unwind the PC, then we need to return the LR |
| 965 | instead. The saved value of PC points into this frame's |
| 966 | prologue, not the next frame's resume location. */ |
| 967 | if (prev_regnum == ARM_PC_REGNUM) |
| 968 | prev_regnum = ARM_LR_REGNUM; |
| 969 | |
| 970 | /* SP is generally not saved to the stack, but this frame is |
| 971 | identified by NEXT_FRAME's stack pointer at the time of the call. |
| 972 | The value was already reconstructed into PREV_SP. */ |
| 973 | if (prev_regnum == ARM_SP_REGNUM) |
| 974 | { |
| 975 | *lvalp = not_lval; |
| 976 | if (valuep) |
| 977 | store_unsigned_integer (valuep, 4, cache->prev_sp); |
| 978 | return; |
| 979 | } |
| 980 | |
| 981 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
| 982 | optimized, lvalp, addrp, realnump, valuep); |
| 983 | } |
| 984 | |
| 985 | struct frame_unwind arm_prologue_unwind = { |
| 986 | NORMAL_FRAME, |
| 987 | arm_prologue_this_id, |
| 988 | arm_prologue_prev_register |
| 989 | }; |
| 990 | |
| 991 | static const struct frame_unwind * |
| 992 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) |
| 993 | { |
| 994 | return &arm_prologue_unwind; |
| 995 | } |
| 996 | |
| 997 | static struct arm_prologue_cache * |
| 998 | arm_make_stub_cache (struct frame_info *next_frame) |
| 999 | { |
| 1000 | int reg; |
| 1001 | struct arm_prologue_cache *cache; |
| 1002 | CORE_ADDR unwound_fp; |
| 1003 | |
| 1004 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
| 1005 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 1006 | |
| 1007 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); |
| 1008 | |
| 1009 | return cache; |
| 1010 | } |
| 1011 | |
| 1012 | /* Our frame ID for a stub frame is the current SP and LR. */ |
| 1013 | |
| 1014 | static void |
| 1015 | arm_stub_this_id (struct frame_info *next_frame, |
| 1016 | void **this_cache, |
| 1017 | struct frame_id *this_id) |
| 1018 | { |
| 1019 | struct arm_prologue_cache *cache; |
| 1020 | |
| 1021 | if (*this_cache == NULL) |
| 1022 | *this_cache = arm_make_stub_cache (next_frame); |
| 1023 | cache = *this_cache; |
| 1024 | |
| 1025 | *this_id = frame_id_build (cache->prev_sp, |
| 1026 | frame_pc_unwind (next_frame)); |
| 1027 | } |
| 1028 | |
| 1029 | struct frame_unwind arm_stub_unwind = { |
| 1030 | NORMAL_FRAME, |
| 1031 | arm_stub_this_id, |
| 1032 | arm_prologue_prev_register |
| 1033 | }; |
| 1034 | |
| 1035 | static const struct frame_unwind * |
| 1036 | arm_stub_unwind_sniffer (struct frame_info *next_frame) |
| 1037 | { |
| 1038 | char dummy[4]; |
| 1039 | |
| 1040 | if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL) |
| 1041 | || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) |
| 1042 | return &arm_stub_unwind; |
| 1043 | |
| 1044 | return NULL; |
| 1045 | } |
| 1046 | |
| 1047 | static CORE_ADDR |
| 1048 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
| 1049 | { |
| 1050 | struct arm_prologue_cache *cache; |
| 1051 | |
| 1052 | if (*this_cache == NULL) |
| 1053 | *this_cache = arm_make_prologue_cache (next_frame); |
| 1054 | cache = *this_cache; |
| 1055 | |
| 1056 | return cache->prev_sp + cache->frameoffset - cache->framesize; |
| 1057 | } |
| 1058 | |
| 1059 | struct frame_base arm_normal_base = { |
| 1060 | &arm_prologue_unwind, |
| 1061 | arm_normal_frame_base, |
| 1062 | arm_normal_frame_base, |
| 1063 | arm_normal_frame_base |
| 1064 | }; |
| 1065 | |
| 1066 | static struct arm_prologue_cache * |
| 1067 | arm_make_sigtramp_cache (struct frame_info *next_frame) |
| 1068 | { |
| 1069 | struct arm_prologue_cache *cache; |
| 1070 | int reg; |
| 1071 | |
| 1072 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
| 1073 | |
| 1074 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); |
| 1075 | |
| 1076 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 1077 | |
| 1078 | for (reg = 0; reg < NUM_REGS; reg++) |
| 1079 | cache->saved_regs[reg].addr |
| 1080 | = SIGCONTEXT_REGISTER_ADDRESS (cache->prev_sp, |
| 1081 | frame_pc_unwind (next_frame), reg); |
| 1082 | |
| 1083 | /* FIXME: What about thumb mode? */ |
| 1084 | cache->framereg = ARM_SP_REGNUM; |
| 1085 | cache->prev_sp |
| 1086 | = read_memory_integer (cache->saved_regs[cache->framereg].addr, |
| 1087 | register_size (current_gdbarch, cache->framereg)); |
| 1088 | |
| 1089 | return cache; |
| 1090 | } |
| 1091 | |
| 1092 | static void |
| 1093 | arm_sigtramp_this_id (struct frame_info *next_frame, |
| 1094 | void **this_cache, |
| 1095 | struct frame_id *this_id) |
| 1096 | { |
| 1097 | struct arm_prologue_cache *cache; |
| 1098 | |
| 1099 | if (*this_cache == NULL) |
| 1100 | *this_cache = arm_make_sigtramp_cache (next_frame); |
| 1101 | cache = *this_cache; |
| 1102 | |
| 1103 | /* FIXME drow/2003-07-07: This isn't right if we single-step within |
| 1104 | the sigtramp frame; the PC should be the beginning of the trampoline. */ |
| 1105 | *this_id = frame_id_build (cache->prev_sp, frame_pc_unwind (next_frame)); |
| 1106 | } |
| 1107 | |
| 1108 | static void |
| 1109 | arm_sigtramp_prev_register (struct frame_info *next_frame, |
| 1110 | void **this_cache, |
| 1111 | int prev_regnum, |
| 1112 | int *optimized, |
| 1113 | enum lval_type *lvalp, |
| 1114 | CORE_ADDR *addrp, |
| 1115 | int *realnump, |
| 1116 | void *valuep) |
| 1117 | { |
| 1118 | struct arm_prologue_cache *cache; |
| 1119 | |
| 1120 | if (*this_cache == NULL) |
| 1121 | *this_cache = arm_make_sigtramp_cache (next_frame); |
| 1122 | cache = *this_cache; |
| 1123 | |
| 1124 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
| 1125 | optimized, lvalp, addrp, realnump, valuep); |
| 1126 | } |
| 1127 | |
| 1128 | struct frame_unwind arm_sigtramp_unwind = { |
| 1129 | SIGTRAMP_FRAME, |
| 1130 | arm_sigtramp_this_id, |
| 1131 | arm_sigtramp_prev_register |
| 1132 | }; |
| 1133 | |
| 1134 | static const struct frame_unwind * |
| 1135 | arm_sigtramp_unwind_sniffer (struct frame_info *next_frame) |
| 1136 | { |
| 1137 | if (SIGCONTEXT_REGISTER_ADDRESS_P () |
| 1138 | && legacy_pc_in_sigtramp (frame_pc_unwind (next_frame), (char *) 0)) |
| 1139 | return &arm_sigtramp_unwind; |
| 1140 | |
| 1141 | return NULL; |
| 1142 | } |
| 1143 | |
| 1144 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
| 1145 | dummy frame. The frame ID's base needs to match the TOS value |
| 1146 | saved by save_dummy_frame_tos() and returned from |
| 1147 | arm_push_dummy_call, and the PC needs to match the dummy frame's |
| 1148 | breakpoint. */ |
| 1149 | |
| 1150 | static struct frame_id |
| 1151 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1152 | { |
| 1153 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
| 1154 | frame_pc_unwind (next_frame)); |
| 1155 | } |
| 1156 | |
| 1157 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
| 1158 | be used to construct the previous frame's ID, after looking up the |
| 1159 | containing function). */ |
| 1160 | |
| 1161 | static CORE_ADDR |
| 1162 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1163 | { |
| 1164 | CORE_ADDR pc; |
| 1165 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); |
| 1166 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
| 1167 | } |
| 1168 | |
| 1169 | static CORE_ADDR |
| 1170 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1171 | { |
| 1172 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); |
| 1173 | } |
| 1174 | |
| 1175 | /* When arguments must be pushed onto the stack, they go on in reverse |
| 1176 | order. The code below implements a FILO (stack) to do this. */ |
| 1177 | |
| 1178 | struct stack_item |
| 1179 | { |
| 1180 | int len; |
| 1181 | struct stack_item *prev; |
| 1182 | void *data; |
| 1183 | }; |
| 1184 | |
| 1185 | static struct stack_item * |
| 1186 | push_stack_item (struct stack_item *prev, void *contents, int len) |
| 1187 | { |
| 1188 | struct stack_item *si; |
| 1189 | si = xmalloc (sizeof (struct stack_item)); |
| 1190 | si->data = xmalloc (len); |
| 1191 | si->len = len; |
| 1192 | si->prev = prev; |
| 1193 | memcpy (si->data, contents, len); |
| 1194 | return si; |
| 1195 | } |
| 1196 | |
| 1197 | static struct stack_item * |
| 1198 | pop_stack_item (struct stack_item *si) |
| 1199 | { |
| 1200 | struct stack_item *dead = si; |
| 1201 | si = si->prev; |
| 1202 | xfree (dead->data); |
| 1203 | xfree (dead); |
| 1204 | return si; |
| 1205 | } |
| 1206 | |
| 1207 | /* We currently only support passing parameters in integer registers. This |
| 1208 | conforms with GCC's default model. Several other variants exist and |
| 1209 | we should probably support some of them based on the selected ABI. */ |
| 1210 | |
| 1211 | static CORE_ADDR |
| 1212 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1213 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
| 1214 | struct value **args, CORE_ADDR sp, int struct_return, |
| 1215 | CORE_ADDR struct_addr) |
| 1216 | { |
| 1217 | int argnum; |
| 1218 | int argreg; |
| 1219 | int nstack; |
| 1220 | struct stack_item *si = NULL; |
| 1221 | |
| 1222 | /* Set the return address. For the ARM, the return breakpoint is |
| 1223 | always at BP_ADDR. */ |
| 1224 | /* XXX Fix for Thumb. */ |
| 1225 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
| 1226 | |
| 1227 | /* Walk through the list of args and determine how large a temporary |
| 1228 | stack is required. Need to take care here as structs may be |
| 1229 | passed on the stack, and we have to to push them. */ |
| 1230 | nstack = 0; |
| 1231 | |
| 1232 | argreg = ARM_A1_REGNUM; |
| 1233 | nstack = 0; |
| 1234 | |
| 1235 | /* Some platforms require a double-word aligned stack. Make sure sp |
| 1236 | is correctly aligned before we start. We always do this even if |
| 1237 | it isn't really needed -- it can never hurt things. */ |
| 1238 | sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); |
| 1239 | |
| 1240 | /* The struct_return pointer occupies the first parameter |
| 1241 | passing register. */ |
| 1242 | if (struct_return) |
| 1243 | { |
| 1244 | if (arm_debug) |
| 1245 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", |
| 1246 | REGISTER_NAME (argreg), paddr (struct_addr)); |
| 1247 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
| 1248 | argreg++; |
| 1249 | } |
| 1250 | |
| 1251 | for (argnum = 0; argnum < nargs; argnum++) |
| 1252 | { |
| 1253 | int len; |
| 1254 | struct type *arg_type; |
| 1255 | struct type *target_type; |
| 1256 | enum type_code typecode; |
| 1257 | bfd_byte *val; |
| 1258 | |
| 1259 | arg_type = check_typedef (value_type (args[argnum])); |
| 1260 | len = TYPE_LENGTH (arg_type); |
| 1261 | target_type = TYPE_TARGET_TYPE (arg_type); |
| 1262 | typecode = TYPE_CODE (arg_type); |
| 1263 | val = value_contents_writeable (args[argnum]); |
| 1264 | |
| 1265 | /* If the argument is a pointer to a function, and it is a |
| 1266 | Thumb function, create a LOCAL copy of the value and set |
| 1267 | the THUMB bit in it. */ |
| 1268 | if (TYPE_CODE_PTR == typecode |
| 1269 | && target_type != NULL |
| 1270 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) |
| 1271 | { |
| 1272 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
| 1273 | if (arm_pc_is_thumb (regval)) |
| 1274 | { |
| 1275 | val = alloca (len); |
| 1276 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
| 1277 | } |
| 1278 | } |
| 1279 | |
| 1280 | /* Copy the argument to general registers or the stack in |
| 1281 | register-sized pieces. Large arguments are split between |
| 1282 | registers and stack. */ |
| 1283 | while (len > 0) |
| 1284 | { |
| 1285 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
| 1286 | |
| 1287 | if (argreg <= ARM_LAST_ARG_REGNUM) |
| 1288 | { |
| 1289 | /* The argument is being passed in a general purpose |
| 1290 | register. */ |
| 1291 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
| 1292 | if (arm_debug) |
| 1293 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", |
| 1294 | argnum, REGISTER_NAME (argreg), |
| 1295 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
| 1296 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 1297 | argreg++; |
| 1298 | } |
| 1299 | else |
| 1300 | { |
| 1301 | /* Push the arguments onto the stack. */ |
| 1302 | if (arm_debug) |
| 1303 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", |
| 1304 | argnum, nstack); |
| 1305 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
| 1306 | nstack += DEPRECATED_REGISTER_SIZE; |
| 1307 | } |
| 1308 | |
| 1309 | len -= partial_len; |
| 1310 | val += partial_len; |
| 1311 | } |
| 1312 | } |
| 1313 | /* If we have an odd number of words to push, then decrement the stack |
| 1314 | by one word now, so first stack argument will be dword aligned. */ |
| 1315 | if (nstack & 4) |
| 1316 | sp -= 4; |
| 1317 | |
| 1318 | while (si) |
| 1319 | { |
| 1320 | sp -= si->len; |
| 1321 | write_memory (sp, si->data, si->len); |
| 1322 | si = pop_stack_item (si); |
| 1323 | } |
| 1324 | |
| 1325 | /* Finally, update teh SP register. */ |
| 1326 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); |
| 1327 | |
| 1328 | return sp; |
| 1329 | } |
| 1330 | |
| 1331 | static void |
| 1332 | print_fpu_flags (int flags) |
| 1333 | { |
| 1334 | if (flags & (1 << 0)) |
| 1335 | fputs ("IVO ", stdout); |
| 1336 | if (flags & (1 << 1)) |
| 1337 | fputs ("DVZ ", stdout); |
| 1338 | if (flags & (1 << 2)) |
| 1339 | fputs ("OFL ", stdout); |
| 1340 | if (flags & (1 << 3)) |
| 1341 | fputs ("UFL ", stdout); |
| 1342 | if (flags & (1 << 4)) |
| 1343 | fputs ("INX ", stdout); |
| 1344 | putchar ('\n'); |
| 1345 | } |
| 1346 | |
| 1347 | /* Print interesting information about the floating point processor |
| 1348 | (if present) or emulator. */ |
| 1349 | static void |
| 1350 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 1351 | struct frame_info *frame, const char *args) |
| 1352 | { |
| 1353 | unsigned long status = read_register (ARM_FPS_REGNUM); |
| 1354 | int type; |
| 1355 | |
| 1356 | type = (status >> 24) & 127; |
| 1357 | if (status & (1 << 31)) |
| 1358 | printf (_("Hardware FPU type %d\n"), type); |
| 1359 | else |
| 1360 | printf (_("Software FPU type %d\n"), type); |
| 1361 | /* i18n: [floating point unit] mask */ |
| 1362 | fputs (_("mask: "), stdout); |
| 1363 | print_fpu_flags (status >> 16); |
| 1364 | /* i18n: [floating point unit] flags */ |
| 1365 | fputs (_("flags: "), stdout); |
| 1366 | print_fpu_flags (status); |
| 1367 | } |
| 1368 | |
| 1369 | /* Return the GDB type object for the "standard" data type of data in |
| 1370 | register N. */ |
| 1371 | |
| 1372 | static struct type * |
| 1373 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
| 1374 | { |
| 1375 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
| 1376 | { |
| 1377 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1378 | return builtin_type_arm_ext_big; |
| 1379 | else |
| 1380 | return builtin_type_arm_ext_littlebyte_bigword; |
| 1381 | } |
| 1382 | else |
| 1383 | return builtin_type_int32; |
| 1384 | } |
| 1385 | |
| 1386 | /* Index within `registers' of the first byte of the space for |
| 1387 | register N. */ |
| 1388 | |
| 1389 | static int |
| 1390 | arm_register_byte (int regnum) |
| 1391 | { |
| 1392 | if (regnum < ARM_F0_REGNUM) |
| 1393 | return regnum * INT_REGISTER_SIZE; |
| 1394 | else if (regnum < ARM_PS_REGNUM) |
| 1395 | return (NUM_GREGS * INT_REGISTER_SIZE |
| 1396 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); |
| 1397 | else |
| 1398 | return (NUM_GREGS * INT_REGISTER_SIZE |
| 1399 | + NUM_FREGS * FP_REGISTER_SIZE |
| 1400 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
| 1401 | } |
| 1402 | |
| 1403 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
| 1404 | static int |
| 1405 | arm_register_sim_regno (int regnum) |
| 1406 | { |
| 1407 | int reg = regnum; |
| 1408 | gdb_assert (reg >= 0 && reg < NUM_REGS); |
| 1409 | |
| 1410 | if (reg < NUM_GREGS) |
| 1411 | return SIM_ARM_R0_REGNUM + reg; |
| 1412 | reg -= NUM_GREGS; |
| 1413 | |
| 1414 | if (reg < NUM_FREGS) |
| 1415 | return SIM_ARM_FP0_REGNUM + reg; |
| 1416 | reg -= NUM_FREGS; |
| 1417 | |
| 1418 | if (reg < NUM_SREGS) |
| 1419 | return SIM_ARM_FPS_REGNUM + reg; |
| 1420 | reg -= NUM_SREGS; |
| 1421 | |
| 1422 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
| 1423 | } |
| 1424 | |
| 1425 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
| 1426 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. |
| 1427 | It is thought that this is is the floating-point register format on |
| 1428 | little-endian systems. */ |
| 1429 | |
| 1430 | static void |
| 1431 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
| 1432 | void *dbl) |
| 1433 | { |
| 1434 | DOUBLEST d; |
| 1435 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1436 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
| 1437 | else |
| 1438 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 1439 | ptr, &d); |
| 1440 | floatformat_from_doublest (fmt, &d, dbl); |
| 1441 | } |
| 1442 | |
| 1443 | static void |
| 1444 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
| 1445 | { |
| 1446 | DOUBLEST d; |
| 1447 | floatformat_to_doublest (fmt, ptr, &d); |
| 1448 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1449 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
| 1450 | else |
| 1451 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 1452 | &d, dbl); |
| 1453 | } |
| 1454 | |
| 1455 | static int |
| 1456 | condition_true (unsigned long cond, unsigned long status_reg) |
| 1457 | { |
| 1458 | if (cond == INST_AL || cond == INST_NV) |
| 1459 | return 1; |
| 1460 | |
| 1461 | switch (cond) |
| 1462 | { |
| 1463 | case INST_EQ: |
| 1464 | return ((status_reg & FLAG_Z) != 0); |
| 1465 | case INST_NE: |
| 1466 | return ((status_reg & FLAG_Z) == 0); |
| 1467 | case INST_CS: |
| 1468 | return ((status_reg & FLAG_C) != 0); |
| 1469 | case INST_CC: |
| 1470 | return ((status_reg & FLAG_C) == 0); |
| 1471 | case INST_MI: |
| 1472 | return ((status_reg & FLAG_N) != 0); |
| 1473 | case INST_PL: |
| 1474 | return ((status_reg & FLAG_N) == 0); |
| 1475 | case INST_VS: |
| 1476 | return ((status_reg & FLAG_V) != 0); |
| 1477 | case INST_VC: |
| 1478 | return ((status_reg & FLAG_V) == 0); |
| 1479 | case INST_HI: |
| 1480 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); |
| 1481 | case INST_LS: |
| 1482 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); |
| 1483 | case INST_GE: |
| 1484 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); |
| 1485 | case INST_LT: |
| 1486 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); |
| 1487 | case INST_GT: |
| 1488 | return (((status_reg & FLAG_Z) == 0) && |
| 1489 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
| 1490 | case INST_LE: |
| 1491 | return (((status_reg & FLAG_Z) != 0) || |
| 1492 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
| 1493 | } |
| 1494 | return 1; |
| 1495 | } |
| 1496 | |
| 1497 | /* Support routines for single stepping. Calculate the next PC value. */ |
| 1498 | #define submask(x) ((1L << ((x) + 1)) - 1) |
| 1499 | #define bit(obj,st) (((obj) >> (st)) & 1) |
| 1500 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) |
| 1501 | #define sbits(obj,st,fn) \ |
| 1502 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) |
| 1503 | #define BranchDest(addr,instr) \ |
| 1504 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) |
| 1505 | #define ARM_PC_32 1 |
| 1506 | |
| 1507 | static unsigned long |
| 1508 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
| 1509 | unsigned long status_reg) |
| 1510 | { |
| 1511 | unsigned long res, shift; |
| 1512 | int rm = bits (inst, 0, 3); |
| 1513 | unsigned long shifttype = bits (inst, 5, 6); |
| 1514 | |
| 1515 | if (bit (inst, 4)) |
| 1516 | { |
| 1517 | int rs = bits (inst, 8, 11); |
| 1518 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; |
| 1519 | } |
| 1520 | else |
| 1521 | shift = bits (inst, 7, 11); |
| 1522 | |
| 1523 | res = (rm == 15 |
| 1524 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
| 1525 | + (bit (inst, 4) ? 12 : 8)) |
| 1526 | : read_register (rm)); |
| 1527 | |
| 1528 | switch (shifttype) |
| 1529 | { |
| 1530 | case 0: /* LSL */ |
| 1531 | res = shift >= 32 ? 0 : res << shift; |
| 1532 | break; |
| 1533 | |
| 1534 | case 1: /* LSR */ |
| 1535 | res = shift >= 32 ? 0 : res >> shift; |
| 1536 | break; |
| 1537 | |
| 1538 | case 2: /* ASR */ |
| 1539 | if (shift >= 32) |
| 1540 | shift = 31; |
| 1541 | res = ((res & 0x80000000L) |
| 1542 | ? ~((~res) >> shift) : res >> shift); |
| 1543 | break; |
| 1544 | |
| 1545 | case 3: /* ROR/RRX */ |
| 1546 | shift &= 31; |
| 1547 | if (shift == 0) |
| 1548 | res = (res >> 1) | (carry ? 0x80000000L : 0); |
| 1549 | else |
| 1550 | res = (res >> shift) | (res << (32 - shift)); |
| 1551 | break; |
| 1552 | } |
| 1553 | |
| 1554 | return res & 0xffffffff; |
| 1555 | } |
| 1556 | |
| 1557 | /* Return number of 1-bits in VAL. */ |
| 1558 | |
| 1559 | static int |
| 1560 | bitcount (unsigned long val) |
| 1561 | { |
| 1562 | int nbits; |
| 1563 | for (nbits = 0; val != 0; nbits++) |
| 1564 | val &= val - 1; /* delete rightmost 1-bit in val */ |
| 1565 | return nbits; |
| 1566 | } |
| 1567 | |
| 1568 | CORE_ADDR |
| 1569 | thumb_get_next_pc (CORE_ADDR pc) |
| 1570 | { |
| 1571 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
| 1572 | unsigned short inst1 = read_memory_integer (pc, 2); |
| 1573 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
| 1574 | unsigned long offset; |
| 1575 | |
| 1576 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
| 1577 | { |
| 1578 | CORE_ADDR sp; |
| 1579 | |
| 1580 | /* Fetch the saved PC from the stack. It's stored above |
| 1581 | all of the other registers. */ |
| 1582 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
| 1583 | sp = read_register (ARM_SP_REGNUM); |
| 1584 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); |
| 1585 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1586 | if (nextpc == pc) |
| 1587 | error (_("Infinite loop detected")); |
| 1588 | } |
| 1589 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ |
| 1590 | { |
| 1591 | unsigned long status = read_register (ARM_PS_REGNUM); |
| 1592 | unsigned long cond = bits (inst1, 8, 11); |
| 1593 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
| 1594 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
| 1595 | } |
| 1596 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ |
| 1597 | { |
| 1598 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); |
| 1599 | } |
| 1600 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
| 1601 | { |
| 1602 | unsigned short inst2 = read_memory_integer (pc + 2, 2); |
| 1603 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
| 1604 | nextpc = pc_val + offset; |
| 1605 | /* For BLX make sure to clear the low bits. */ |
| 1606 | if (bits (inst2, 11, 12) == 1) |
| 1607 | nextpc = nextpc & 0xfffffffc; |
| 1608 | } |
| 1609 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
| 1610 | { |
| 1611 | if (bits (inst1, 3, 6) == 0x0f) |
| 1612 | nextpc = pc_val; |
| 1613 | else |
| 1614 | nextpc = read_register (bits (inst1, 3, 6)); |
| 1615 | |
| 1616 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1617 | if (nextpc == pc) |
| 1618 | error (_("Infinite loop detected")); |
| 1619 | } |
| 1620 | |
| 1621 | return nextpc; |
| 1622 | } |
| 1623 | |
| 1624 | CORE_ADDR |
| 1625 | arm_get_next_pc (CORE_ADDR pc) |
| 1626 | { |
| 1627 | unsigned long pc_val; |
| 1628 | unsigned long this_instr; |
| 1629 | unsigned long status; |
| 1630 | CORE_ADDR nextpc; |
| 1631 | |
| 1632 | if (arm_pc_is_thumb (pc)) |
| 1633 | return thumb_get_next_pc (pc); |
| 1634 | |
| 1635 | pc_val = (unsigned long) pc; |
| 1636 | this_instr = read_memory_integer (pc, 4); |
| 1637 | status = read_register (ARM_PS_REGNUM); |
| 1638 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
| 1639 | |
| 1640 | if (condition_true (bits (this_instr, 28, 31), status)) |
| 1641 | { |
| 1642 | switch (bits (this_instr, 24, 27)) |
| 1643 | { |
| 1644 | case 0x0: |
| 1645 | case 0x1: /* data processing */ |
| 1646 | case 0x2: |
| 1647 | case 0x3: |
| 1648 | { |
| 1649 | unsigned long operand1, operand2, result = 0; |
| 1650 | unsigned long rn; |
| 1651 | int c; |
| 1652 | |
| 1653 | if (bits (this_instr, 12, 15) != 15) |
| 1654 | break; |
| 1655 | |
| 1656 | if (bits (this_instr, 22, 25) == 0 |
| 1657 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
| 1658 | error (_("Invalid update to pc in instruction")); |
| 1659 | |
| 1660 | /* BX <reg>, BLX <reg> */ |
| 1661 | if (bits (this_instr, 4, 28) == 0x12fff1 |
| 1662 | || bits (this_instr, 4, 28) == 0x12fff3) |
| 1663 | { |
| 1664 | rn = bits (this_instr, 0, 3); |
| 1665 | result = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1666 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); |
| 1667 | |
| 1668 | if (nextpc == pc) |
| 1669 | error (_("Infinite loop detected")); |
| 1670 | |
| 1671 | return nextpc; |
| 1672 | } |
| 1673 | |
| 1674 | /* Multiply into PC */ |
| 1675 | c = (status & FLAG_C) ? 1 : 0; |
| 1676 | rn = bits (this_instr, 16, 19); |
| 1677 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1678 | |
| 1679 | if (bit (this_instr, 25)) |
| 1680 | { |
| 1681 | unsigned long immval = bits (this_instr, 0, 7); |
| 1682 | unsigned long rotate = 2 * bits (this_instr, 8, 11); |
| 1683 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
| 1684 | & 0xffffffff; |
| 1685 | } |
| 1686 | else /* operand 2 is a shifted register */ |
| 1687 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
| 1688 | |
| 1689 | switch (bits (this_instr, 21, 24)) |
| 1690 | { |
| 1691 | case 0x0: /*and */ |
| 1692 | result = operand1 & operand2; |
| 1693 | break; |
| 1694 | |
| 1695 | case 0x1: /*eor */ |
| 1696 | result = operand1 ^ operand2; |
| 1697 | break; |
| 1698 | |
| 1699 | case 0x2: /*sub */ |
| 1700 | result = operand1 - operand2; |
| 1701 | break; |
| 1702 | |
| 1703 | case 0x3: /*rsb */ |
| 1704 | result = operand2 - operand1; |
| 1705 | break; |
| 1706 | |
| 1707 | case 0x4: /*add */ |
| 1708 | result = operand1 + operand2; |
| 1709 | break; |
| 1710 | |
| 1711 | case 0x5: /*adc */ |
| 1712 | result = operand1 + operand2 + c; |
| 1713 | break; |
| 1714 | |
| 1715 | case 0x6: /*sbc */ |
| 1716 | result = operand1 - operand2 + c; |
| 1717 | break; |
| 1718 | |
| 1719 | case 0x7: /*rsc */ |
| 1720 | result = operand2 - operand1 + c; |
| 1721 | break; |
| 1722 | |
| 1723 | case 0x8: |
| 1724 | case 0x9: |
| 1725 | case 0xa: |
| 1726 | case 0xb: /* tst, teq, cmp, cmn */ |
| 1727 | result = (unsigned long) nextpc; |
| 1728 | break; |
| 1729 | |
| 1730 | case 0xc: /*orr */ |
| 1731 | result = operand1 | operand2; |
| 1732 | break; |
| 1733 | |
| 1734 | case 0xd: /*mov */ |
| 1735 | /* Always step into a function. */ |
| 1736 | result = operand2; |
| 1737 | break; |
| 1738 | |
| 1739 | case 0xe: /*bic */ |
| 1740 | result = operand1 & ~operand2; |
| 1741 | break; |
| 1742 | |
| 1743 | case 0xf: /*mvn */ |
| 1744 | result = ~operand2; |
| 1745 | break; |
| 1746 | } |
| 1747 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); |
| 1748 | |
| 1749 | if (nextpc == pc) |
| 1750 | error (_("Infinite loop detected")); |
| 1751 | break; |
| 1752 | } |
| 1753 | |
| 1754 | case 0x4: |
| 1755 | case 0x5: /* data transfer */ |
| 1756 | case 0x6: |
| 1757 | case 0x7: |
| 1758 | if (bit (this_instr, 20)) |
| 1759 | { |
| 1760 | /* load */ |
| 1761 | if (bits (this_instr, 12, 15) == 15) |
| 1762 | { |
| 1763 | /* rd == pc */ |
| 1764 | unsigned long rn; |
| 1765 | unsigned long base; |
| 1766 | |
| 1767 | if (bit (this_instr, 22)) |
| 1768 | error (_("Invalid update to pc in instruction")); |
| 1769 | |
| 1770 | /* byte write to PC */ |
| 1771 | rn = bits (this_instr, 16, 19); |
| 1772 | base = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1773 | if (bit (this_instr, 24)) |
| 1774 | { |
| 1775 | /* pre-indexed */ |
| 1776 | int c = (status & FLAG_C) ? 1 : 0; |
| 1777 | unsigned long offset = |
| 1778 | (bit (this_instr, 25) |
| 1779 | ? shifted_reg_val (this_instr, c, pc_val, status) |
| 1780 | : bits (this_instr, 0, 11)); |
| 1781 | |
| 1782 | if (bit (this_instr, 23)) |
| 1783 | base += offset; |
| 1784 | else |
| 1785 | base -= offset; |
| 1786 | } |
| 1787 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
| 1788 | 4); |
| 1789 | |
| 1790 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1791 | |
| 1792 | if (nextpc == pc) |
| 1793 | error (_("Infinite loop detected")); |
| 1794 | } |
| 1795 | } |
| 1796 | break; |
| 1797 | |
| 1798 | case 0x8: |
| 1799 | case 0x9: /* block transfer */ |
| 1800 | if (bit (this_instr, 20)) |
| 1801 | { |
| 1802 | /* LDM */ |
| 1803 | if (bit (this_instr, 15)) |
| 1804 | { |
| 1805 | /* loading pc */ |
| 1806 | int offset = 0; |
| 1807 | |
| 1808 | if (bit (this_instr, 23)) |
| 1809 | { |
| 1810 | /* up */ |
| 1811 | unsigned long reglist = bits (this_instr, 0, 14); |
| 1812 | offset = bitcount (reglist) * 4; |
| 1813 | if (bit (this_instr, 24)) /* pre */ |
| 1814 | offset += 4; |
| 1815 | } |
| 1816 | else if (bit (this_instr, 24)) |
| 1817 | offset = -4; |
| 1818 | |
| 1819 | { |
| 1820 | unsigned long rn_val = |
| 1821 | read_register (bits (this_instr, 16, 19)); |
| 1822 | nextpc = |
| 1823 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val |
| 1824 | + offset), |
| 1825 | 4); |
| 1826 | } |
| 1827 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1828 | if (nextpc == pc) |
| 1829 | error (_("Infinite loop detected")); |
| 1830 | } |
| 1831 | } |
| 1832 | break; |
| 1833 | |
| 1834 | case 0xb: /* branch & link */ |
| 1835 | case 0xa: /* branch */ |
| 1836 | { |
| 1837 | nextpc = BranchDest (pc, this_instr); |
| 1838 | |
| 1839 | /* BLX */ |
| 1840 | if (bits (this_instr, 28, 31) == INST_NV) |
| 1841 | nextpc |= bit (this_instr, 24) << 1; |
| 1842 | |
| 1843 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1844 | if (nextpc == pc) |
| 1845 | error (_("Infinite loop detected")); |
| 1846 | break; |
| 1847 | } |
| 1848 | |
| 1849 | case 0xc: |
| 1850 | case 0xd: |
| 1851 | case 0xe: /* coproc ops */ |
| 1852 | case 0xf: /* SWI */ |
| 1853 | break; |
| 1854 | |
| 1855 | default: |
| 1856 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
| 1857 | return (pc); |
| 1858 | } |
| 1859 | } |
| 1860 | |
| 1861 | return nextpc; |
| 1862 | } |
| 1863 | |
| 1864 | /* single_step() is called just before we want to resume the inferior, |
| 1865 | if we want to single-step it but there is no hardware or kernel |
| 1866 | single-step support. We find the target of the coming instruction |
| 1867 | and breakpoint it. |
| 1868 | |
| 1869 | single_step() is also called just after the inferior stops. If we |
| 1870 | had set up a simulated single-step, we undo our damage. */ |
| 1871 | |
| 1872 | static void |
| 1873 | arm_software_single_step (enum target_signal sig, int insert_bpt) |
| 1874 | { |
| 1875 | static int next_pc; /* State between setting and unsetting. */ |
| 1876 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
| 1877 | |
| 1878 | if (insert_bpt) |
| 1879 | { |
| 1880 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
| 1881 | target_insert_breakpoint (next_pc, break_mem); |
| 1882 | } |
| 1883 | else |
| 1884 | target_remove_breakpoint (next_pc, break_mem); |
| 1885 | } |
| 1886 | |
| 1887 | #include "bfd-in2.h" |
| 1888 | #include "libcoff.h" |
| 1889 | |
| 1890 | static int |
| 1891 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
| 1892 | { |
| 1893 | if (arm_pc_is_thumb (memaddr)) |
| 1894 | { |
| 1895 | static asymbol *asym; |
| 1896 | static combined_entry_type ce; |
| 1897 | static struct coff_symbol_struct csym; |
| 1898 | static struct bfd fake_bfd; |
| 1899 | static bfd_target fake_target; |
| 1900 | |
| 1901 | if (csym.native == NULL) |
| 1902 | { |
| 1903 | /* Create a fake symbol vector containing a Thumb symbol. |
| 1904 | This is solely so that the code in print_insn_little_arm() |
| 1905 | and print_insn_big_arm() in opcodes/arm-dis.c will detect |
| 1906 | the presence of a Thumb symbol and switch to decoding |
| 1907 | Thumb instructions. */ |
| 1908 | |
| 1909 | fake_target.flavour = bfd_target_coff_flavour; |
| 1910 | fake_bfd.xvec = &fake_target; |
| 1911 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
| 1912 | csym.native = &ce; |
| 1913 | csym.symbol.the_bfd = &fake_bfd; |
| 1914 | csym.symbol.name = "fake"; |
| 1915 | asym = (asymbol *) & csym; |
| 1916 | } |
| 1917 | |
| 1918 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
| 1919 | info->symbols = &asym; |
| 1920 | } |
| 1921 | else |
| 1922 | info->symbols = NULL; |
| 1923 | |
| 1924 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1925 | return print_insn_big_arm (memaddr, info); |
| 1926 | else |
| 1927 | return print_insn_little_arm (memaddr, info); |
| 1928 | } |
| 1929 | |
| 1930 | /* The following define instruction sequences that will cause ARM |
| 1931 | cpu's to take an undefined instruction trap. These are used to |
| 1932 | signal a breakpoint to GDB. |
| 1933 | |
| 1934 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb |
| 1935 | modes. A different instruction is required for each mode. The ARM |
| 1936 | cpu's can also be big or little endian. Thus four different |
| 1937 | instructions are needed to support all cases. |
| 1938 | |
| 1939 | Note: ARMv4 defines several new instructions that will take the |
| 1940 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does |
| 1941 | not in fact add the new instructions. The new undefined |
| 1942 | instructions in ARMv4 are all instructions that had no defined |
| 1943 | behaviour in earlier chips. There is no guarantee that they will |
| 1944 | raise an exception, but may be treated as NOP's. In practice, it |
| 1945 | may only safe to rely on instructions matching: |
| 1946 | |
| 1947 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
| 1948 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
| 1949 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x |
| 1950 | |
| 1951 | Even this may only true if the condition predicate is true. The |
| 1952 | following use a condition predicate of ALWAYS so it is always TRUE. |
| 1953 | |
| 1954 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, |
| 1955 | and NetBSD all use a software interrupt rather than an undefined |
| 1956 | instruction to force a trap. This can be handled by by the |
| 1957 | abi-specific code during establishment of the gdbarch vector. */ |
| 1958 | |
| 1959 | |
| 1960 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
| 1961 | override these definitions. */ |
| 1962 | #ifndef ARM_LE_BREAKPOINT |
| 1963 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} |
| 1964 | #endif |
| 1965 | #ifndef ARM_BE_BREAKPOINT |
| 1966 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} |
| 1967 | #endif |
| 1968 | #ifndef THUMB_LE_BREAKPOINT |
| 1969 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} |
| 1970 | #endif |
| 1971 | #ifndef THUMB_BE_BREAKPOINT |
| 1972 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} |
| 1973 | #endif |
| 1974 | |
| 1975 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
| 1976 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; |
| 1977 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; |
| 1978 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; |
| 1979 | |
| 1980 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
| 1981 | the program counter value to determine whether a 16-bit or 32-bit |
| 1982 | breakpoint should be used. It returns a pointer to a string of |
| 1983 | bytes that encode a breakpoint instruction, stores the length of |
| 1984 | the string to *lenptr, and adjusts the program counter (if |
| 1985 | necessary) to point to the actual memory location where the |
| 1986 | breakpoint should be inserted. */ |
| 1987 | |
| 1988 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
| 1989 | breakpoints and storing their handles instread of what was in |
| 1990 | memory. It is nice that this is the same size as a handle - |
| 1991 | otherwise remote-rdp will have to change. */ |
| 1992 | |
| 1993 | static const unsigned char * |
| 1994 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
| 1995 | { |
| 1996 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 1997 | |
| 1998 | if (arm_pc_is_thumb (*pcptr)) |
| 1999 | { |
| 2000 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
| 2001 | *lenptr = tdep->thumb_breakpoint_size; |
| 2002 | return tdep->thumb_breakpoint; |
| 2003 | } |
| 2004 | else |
| 2005 | { |
| 2006 | *lenptr = tdep->arm_breakpoint_size; |
| 2007 | return tdep->arm_breakpoint; |
| 2008 | } |
| 2009 | } |
| 2010 | |
| 2011 | /* Extract from an array REGBUF containing the (raw) register state a |
| 2012 | function return value of type TYPE, and copy that, in virtual |
| 2013 | format, into VALBUF. */ |
| 2014 | |
| 2015 | static void |
| 2016 | arm_extract_return_value (struct type *type, |
| 2017 | struct regcache *regs, |
| 2018 | void *dst) |
| 2019 | { |
| 2020 | bfd_byte *valbuf = dst; |
| 2021 | |
| 2022 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
| 2023 | { |
| 2024 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
| 2025 | { |
| 2026 | case ARM_FLOAT_FPA: |
| 2027 | { |
| 2028 | /* The value is in register F0 in internal format. We need to |
| 2029 | extract the raw value and then convert it to the desired |
| 2030 | internal type. */ |
| 2031 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
| 2032 | |
| 2033 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); |
| 2034 | convert_from_extended (floatformat_from_type (type), tmpbuf, |
| 2035 | valbuf); |
| 2036 | } |
| 2037 | break; |
| 2038 | |
| 2039 | case ARM_FLOAT_SOFT_FPA: |
| 2040 | case ARM_FLOAT_SOFT_VFP: |
| 2041 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
| 2042 | if (TYPE_LENGTH (type) > 4) |
| 2043 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, |
| 2044 | valbuf + INT_REGISTER_SIZE); |
| 2045 | break; |
| 2046 | |
| 2047 | default: |
| 2048 | internal_error |
| 2049 | (__FILE__, __LINE__, |
| 2050 | _("arm_extract_return_value: Floating point model not supported")); |
| 2051 | break; |
| 2052 | } |
| 2053 | } |
| 2054 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 2055 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 2056 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 2057 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 2058 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 2059 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 2060 | { |
| 2061 | /* If the the type is a plain integer, then the access is |
| 2062 | straight-forward. Otherwise we have to play around a bit more. */ |
| 2063 | int len = TYPE_LENGTH (type); |
| 2064 | int regno = ARM_A1_REGNUM; |
| 2065 | ULONGEST tmp; |
| 2066 | |
| 2067 | while (len > 0) |
| 2068 | { |
| 2069 | /* By using store_unsigned_integer we avoid having to do |
| 2070 | anything special for small big-endian values. */ |
| 2071 | regcache_cooked_read_unsigned (regs, regno++, &tmp); |
| 2072 | store_unsigned_integer (valbuf, |
| 2073 | (len > INT_REGISTER_SIZE |
| 2074 | ? INT_REGISTER_SIZE : len), |
| 2075 | tmp); |
| 2076 | len -= INT_REGISTER_SIZE; |
| 2077 | valbuf += INT_REGISTER_SIZE; |
| 2078 | } |
| 2079 | } |
| 2080 | else |
| 2081 | { |
| 2082 | /* For a structure or union the behaviour is as if the value had |
| 2083 | been stored to word-aligned memory and then loaded into |
| 2084 | registers with 32-bit load instruction(s). */ |
| 2085 | int len = TYPE_LENGTH (type); |
| 2086 | int regno = ARM_A1_REGNUM; |
| 2087 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 2088 | |
| 2089 | while (len > 0) |
| 2090 | { |
| 2091 | regcache_cooked_read (regs, regno++, tmpbuf); |
| 2092 | memcpy (valbuf, tmpbuf, |
| 2093 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
| 2094 | len -= INT_REGISTER_SIZE; |
| 2095 | valbuf += INT_REGISTER_SIZE; |
| 2096 | } |
| 2097 | } |
| 2098 | } |
| 2099 | |
| 2100 | /* Extract from an array REGBUF containing the (raw) register state |
| 2101 | the address in which a function should return its structure value. */ |
| 2102 | |
| 2103 | static CORE_ADDR |
| 2104 | arm_extract_struct_value_address (struct regcache *regcache) |
| 2105 | { |
| 2106 | ULONGEST ret; |
| 2107 | |
| 2108 | regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret); |
| 2109 | return ret; |
| 2110 | } |
| 2111 | |
| 2112 | /* Will a function return an aggregate type in memory or in a |
| 2113 | register? Return 0 if an aggregate type can be returned in a |
| 2114 | register, 1 if it must be returned in memory. */ |
| 2115 | |
| 2116 | static int |
| 2117 | arm_use_struct_convention (int gcc_p, struct type *type) |
| 2118 | { |
| 2119 | int nRc; |
| 2120 | enum type_code code; |
| 2121 | |
| 2122 | CHECK_TYPEDEF (type); |
| 2123 | |
| 2124 | /* In the ARM ABI, "integer" like aggregate types are returned in |
| 2125 | registers. For an aggregate type to be integer like, its size |
| 2126 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
| 2127 | offset of each addressable subfield must be zero. Note that bit |
| 2128 | fields are not addressable, and all addressable subfields of |
| 2129 | unions always start at offset zero. |
| 2130 | |
| 2131 | This function is based on the behaviour of GCC 2.95.1. |
| 2132 | See: gcc/arm.c: arm_return_in_memory() for details. |
| 2133 | |
| 2134 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
| 2135 | parameters correctly for a function returning the following |
| 2136 | structure: struct { float f;}; This should be returned in memory, |
| 2137 | not a register. Richard Earnshaw sent me a patch, but I do not |
| 2138 | know of any way to detect if a function like the above has been |
| 2139 | compiled with the correct calling convention. */ |
| 2140 | |
| 2141 | /* All aggregate types that won't fit in a register must be returned |
| 2142 | in memory. */ |
| 2143 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
| 2144 | { |
| 2145 | return 1; |
| 2146 | } |
| 2147 | |
| 2148 | /* The only aggregate types that can be returned in a register are |
| 2149 | structs and unions. Arrays must be returned in memory. */ |
| 2150 | code = TYPE_CODE (type); |
| 2151 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) |
| 2152 | { |
| 2153 | return 1; |
| 2154 | } |
| 2155 | |
| 2156 | /* Assume all other aggregate types can be returned in a register. |
| 2157 | Run a check for structures, unions and arrays. */ |
| 2158 | nRc = 0; |
| 2159 | |
| 2160 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
| 2161 | { |
| 2162 | int i; |
| 2163 | /* Need to check if this struct/union is "integer" like. For |
| 2164 | this to be true, its size must be less than or equal to |
| 2165 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
| 2166 | subfield must be zero. Note that bit fields are not |
| 2167 | addressable, and unions always start at offset zero. If any |
| 2168 | of the subfields is a floating point type, the struct/union |
| 2169 | cannot be an integer type. */ |
| 2170 | |
| 2171 | /* For each field in the object, check: |
| 2172 | 1) Is it FP? --> yes, nRc = 1; |
| 2173 | 2) Is it addressable (bitpos != 0) and |
| 2174 | not packed (bitsize == 0)? |
| 2175 | --> yes, nRc = 1 |
| 2176 | */ |
| 2177 | |
| 2178 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 2179 | { |
| 2180 | enum type_code field_type_code; |
| 2181 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
| 2182 | |
| 2183 | /* Is it a floating point type field? */ |
| 2184 | if (field_type_code == TYPE_CODE_FLT) |
| 2185 | { |
| 2186 | nRc = 1; |
| 2187 | break; |
| 2188 | } |
| 2189 | |
| 2190 | /* If bitpos != 0, then we have to care about it. */ |
| 2191 | if (TYPE_FIELD_BITPOS (type, i) != 0) |
| 2192 | { |
| 2193 | /* Bitfields are not addressable. If the field bitsize is |
| 2194 | zero, then the field is not packed. Hence it cannot be |
| 2195 | a bitfield or any other packed type. */ |
| 2196 | if (TYPE_FIELD_BITSIZE (type, i) == 0) |
| 2197 | { |
| 2198 | nRc = 1; |
| 2199 | break; |
| 2200 | } |
| 2201 | } |
| 2202 | } |
| 2203 | } |
| 2204 | |
| 2205 | return nRc; |
| 2206 | } |
| 2207 | |
| 2208 | /* Write into appropriate registers a function return value of type |
| 2209 | TYPE, given in virtual format. */ |
| 2210 | |
| 2211 | static void |
| 2212 | arm_store_return_value (struct type *type, struct regcache *regs, |
| 2213 | const void *src) |
| 2214 | { |
| 2215 | const bfd_byte *valbuf = src; |
| 2216 | |
| 2217 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 2218 | { |
| 2219 | char buf[MAX_REGISTER_SIZE]; |
| 2220 | |
| 2221 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
| 2222 | { |
| 2223 | case ARM_FLOAT_FPA: |
| 2224 | |
| 2225 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
| 2226 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
| 2227 | break; |
| 2228 | |
| 2229 | case ARM_FLOAT_SOFT_FPA: |
| 2230 | case ARM_FLOAT_SOFT_VFP: |
| 2231 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
| 2232 | if (TYPE_LENGTH (type) > 4) |
| 2233 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, |
| 2234 | valbuf + INT_REGISTER_SIZE); |
| 2235 | break; |
| 2236 | |
| 2237 | default: |
| 2238 | internal_error |
| 2239 | (__FILE__, __LINE__, |
| 2240 | _("arm_store_return_value: Floating point model not supported")); |
| 2241 | break; |
| 2242 | } |
| 2243 | } |
| 2244 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 2245 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 2246 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 2247 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 2248 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 2249 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 2250 | { |
| 2251 | if (TYPE_LENGTH (type) <= 4) |
| 2252 | { |
| 2253 | /* Values of one word or less are zero/sign-extended and |
| 2254 | returned in r0. */ |
| 2255 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 2256 | LONGEST val = unpack_long (type, valbuf); |
| 2257 | |
| 2258 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
| 2259 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
| 2260 | } |
| 2261 | else |
| 2262 | { |
| 2263 | /* Integral values greater than one word are stored in consecutive |
| 2264 | registers starting with r0. This will always be a multiple of |
| 2265 | the regiser size. */ |
| 2266 | int len = TYPE_LENGTH (type); |
| 2267 | int regno = ARM_A1_REGNUM; |
| 2268 | |
| 2269 | while (len > 0) |
| 2270 | { |
| 2271 | regcache_cooked_write (regs, regno++, valbuf); |
| 2272 | len -= INT_REGISTER_SIZE; |
| 2273 | valbuf += INT_REGISTER_SIZE; |
| 2274 | } |
| 2275 | } |
| 2276 | } |
| 2277 | else |
| 2278 | { |
| 2279 | /* For a structure or union the behaviour is as if the value had |
| 2280 | been stored to word-aligned memory and then loaded into |
| 2281 | registers with 32-bit load instruction(s). */ |
| 2282 | int len = TYPE_LENGTH (type); |
| 2283 | int regno = ARM_A1_REGNUM; |
| 2284 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 2285 | |
| 2286 | while (len > 0) |
| 2287 | { |
| 2288 | memcpy (tmpbuf, valbuf, |
| 2289 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
| 2290 | regcache_cooked_write (regs, regno++, tmpbuf); |
| 2291 | len -= INT_REGISTER_SIZE; |
| 2292 | valbuf += INT_REGISTER_SIZE; |
| 2293 | } |
| 2294 | } |
| 2295 | } |
| 2296 | |
| 2297 | static int |
| 2298 | arm_get_longjmp_target (CORE_ADDR *pc) |
| 2299 | { |
| 2300 | CORE_ADDR jb_addr; |
| 2301 | char buf[INT_REGISTER_SIZE]; |
| 2302 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2303 | |
| 2304 | jb_addr = read_register (ARM_A1_REGNUM); |
| 2305 | |
| 2306 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, |
| 2307 | INT_REGISTER_SIZE)) |
| 2308 | return 0; |
| 2309 | |
| 2310 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
| 2311 | return 1; |
| 2312 | } |
| 2313 | |
| 2314 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
| 2315 | |
| 2316 | int |
| 2317 | arm_in_call_stub (CORE_ADDR pc, char *name) |
| 2318 | { |
| 2319 | CORE_ADDR start_addr; |
| 2320 | |
| 2321 | /* Find the starting address of the function containing the PC. If |
| 2322 | the caller didn't give us a name, look it up at the same time. */ |
| 2323 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
| 2324 | &start_addr, NULL)) |
| 2325 | return 0; |
| 2326 | |
| 2327 | return strncmp (name, "_call_via_r", 11) == 0; |
| 2328 | } |
| 2329 | |
| 2330 | /* If PC is in a Thumb call or return stub, return the address of the |
| 2331 | target PC, which is in a register. The thunk functions are called |
| 2332 | _called_via_xx, where x is the register name. The possible names |
| 2333 | are r0-r9, sl, fp, ip, sp, and lr. */ |
| 2334 | |
| 2335 | CORE_ADDR |
| 2336 | arm_skip_stub (CORE_ADDR pc) |
| 2337 | { |
| 2338 | char *name; |
| 2339 | CORE_ADDR start_addr; |
| 2340 | |
| 2341 | /* Find the starting address and name of the function containing the PC. */ |
| 2342 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 2343 | return 0; |
| 2344 | |
| 2345 | /* Call thunks always start with "_call_via_". */ |
| 2346 | if (strncmp (name, "_call_via_", 10) == 0) |
| 2347 | { |
| 2348 | /* Use the name suffix to determine which register contains the |
| 2349 | target PC. */ |
| 2350 | static char *table[15] = |
| 2351 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 2352 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" |
| 2353 | }; |
| 2354 | int regno; |
| 2355 | |
| 2356 | for (regno = 0; regno <= 14; regno++) |
| 2357 | if (strcmp (&name[10], table[regno]) == 0) |
| 2358 | return read_register (regno); |
| 2359 | } |
| 2360 | |
| 2361 | return 0; /* not a stub */ |
| 2362 | } |
| 2363 | |
| 2364 | static void |
| 2365 | set_arm_command (char *args, int from_tty) |
| 2366 | { |
| 2367 | printf_unfiltered (_("\ |
| 2368 | \"set arm\" must be followed by an apporpriate subcommand.\n")); |
| 2369 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
| 2370 | } |
| 2371 | |
| 2372 | static void |
| 2373 | show_arm_command (char *args, int from_tty) |
| 2374 | { |
| 2375 | cmd_show_list (showarmcmdlist, from_tty, ""); |
| 2376 | } |
| 2377 | |
| 2378 | static void |
| 2379 | arm_update_current_architecture (void) |
| 2380 | { |
| 2381 | struct gdbarch_info info; |
| 2382 | |
| 2383 | /* If the current architecture is not ARM, we have nothing to do. */ |
| 2384 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm) |
| 2385 | return; |
| 2386 | |
| 2387 | /* Update the architecture. */ |
| 2388 | gdbarch_info_init (&info); |
| 2389 | |
| 2390 | if (!gdbarch_update_p (info)) |
| 2391 | internal_error (__FILE__, __LINE__, "could not update architecture"); |
| 2392 | } |
| 2393 | |
| 2394 | static void |
| 2395 | set_fp_model_sfunc (char *args, int from_tty, |
| 2396 | struct cmd_list_element *c) |
| 2397 | { |
| 2398 | enum arm_float_model fp_model; |
| 2399 | |
| 2400 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) |
| 2401 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) |
| 2402 | { |
| 2403 | arm_fp_model = fp_model; |
| 2404 | break; |
| 2405 | } |
| 2406 | |
| 2407 | if (fp_model == ARM_FLOAT_LAST) |
| 2408 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
| 2409 | current_fp_model); |
| 2410 | |
| 2411 | arm_update_current_architecture (); |
| 2412 | } |
| 2413 | |
| 2414 | static void |
| 2415 | show_fp_model (struct ui_file *file, int from_tty, |
| 2416 | struct cmd_list_element *c, const char *value) |
| 2417 | { |
| 2418 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2419 | |
| 2420 | if (arm_fp_model == ARM_FLOAT_AUTO |
| 2421 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
| 2422 | fprintf_filtered (file, _("\ |
| 2423 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), |
| 2424 | fp_model_strings[tdep->fp_model]); |
| 2425 | else |
| 2426 | fprintf_filtered (file, _("\ |
| 2427 | The current ARM floating point model is \"%s\".\n"), |
| 2428 | fp_model_strings[arm_fp_model]); |
| 2429 | } |
| 2430 | |
| 2431 | static void |
| 2432 | arm_set_abi (char *args, int from_tty, |
| 2433 | struct cmd_list_element *c) |
| 2434 | { |
| 2435 | enum arm_abi_kind arm_abi; |
| 2436 | |
| 2437 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) |
| 2438 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) |
| 2439 | { |
| 2440 | arm_abi_global = arm_abi; |
| 2441 | break; |
| 2442 | } |
| 2443 | |
| 2444 | if (arm_abi == ARM_ABI_LAST) |
| 2445 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), |
| 2446 | arm_abi_string); |
| 2447 | |
| 2448 | arm_update_current_architecture (); |
| 2449 | } |
| 2450 | |
| 2451 | static void |
| 2452 | arm_show_abi (struct ui_file *file, int from_tty, |
| 2453 | struct cmd_list_element *c, const char *value) |
| 2454 | { |
| 2455 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2456 | |
| 2457 | if (arm_abi_global == ARM_ABI_AUTO |
| 2458 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
| 2459 | fprintf_filtered (file, _("\ |
| 2460 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), |
| 2461 | arm_abi_strings[tdep->arm_abi]); |
| 2462 | else |
| 2463 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), |
| 2464 | arm_abi_string); |
| 2465 | } |
| 2466 | |
| 2467 | /* If the user changes the register disassembly style used for info |
| 2468 | register and other commands, we have to also switch the style used |
| 2469 | in opcodes for disassembly output. This function is run in the "set |
| 2470 | arm disassembly" command, and does that. */ |
| 2471 | |
| 2472 | static void |
| 2473 | set_disassembly_style_sfunc (char *args, int from_tty, |
| 2474 | struct cmd_list_element *c) |
| 2475 | { |
| 2476 | set_disassembly_style (); |
| 2477 | } |
| 2478 | \f |
| 2479 | /* Return the ARM register name corresponding to register I. */ |
| 2480 | static const char * |
| 2481 | arm_register_name (int i) |
| 2482 | { |
| 2483 | return arm_register_names[i]; |
| 2484 | } |
| 2485 | |
| 2486 | static void |
| 2487 | set_disassembly_style (void) |
| 2488 | { |
| 2489 | const char *setname, *setdesc, **regnames; |
| 2490 | int numregs, j; |
| 2491 | |
| 2492 | /* Find the style that the user wants in the opcodes table. */ |
| 2493 | int current = 0; |
| 2494 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); |
| 2495 | while ((disassembly_style != setname) |
| 2496 | && (current < num_disassembly_options)) |
| 2497 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
| 2498 | current_option = current; |
| 2499 | |
| 2500 | /* Fill our copy. */ |
| 2501 | for (j = 0; j < numregs; j++) |
| 2502 | arm_register_names[j] = (char *) regnames[j]; |
| 2503 | |
| 2504 | /* Adjust case. */ |
| 2505 | if (isupper (*regnames[ARM_PC_REGNUM])) |
| 2506 | { |
| 2507 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
| 2508 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; |
| 2509 | } |
| 2510 | else |
| 2511 | { |
| 2512 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
| 2513 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; |
| 2514 | } |
| 2515 | |
| 2516 | /* Synchronize the disassembler. */ |
| 2517 | set_arm_regname_option (current); |
| 2518 | } |
| 2519 | |
| 2520 | /* Test whether the coff symbol specific value corresponds to a Thumb |
| 2521 | function. */ |
| 2522 | |
| 2523 | static int |
| 2524 | coff_sym_is_thumb (int val) |
| 2525 | { |
| 2526 | return (val == C_THUMBEXT || |
| 2527 | val == C_THUMBSTAT || |
| 2528 | val == C_THUMBEXTFUNC || |
| 2529 | val == C_THUMBSTATFUNC || |
| 2530 | val == C_THUMBLABEL); |
| 2531 | } |
| 2532 | |
| 2533 | /* arm_coff_make_msymbol_special() |
| 2534 | arm_elf_make_msymbol_special() |
| 2535 | |
| 2536 | These functions test whether the COFF or ELF symbol corresponds to |
| 2537 | an address in thumb code, and set a "special" bit in a minimal |
| 2538 | symbol to indicate that it does. */ |
| 2539 | |
| 2540 | static void |
| 2541 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
| 2542 | { |
| 2543 | /* Thumb symbols are of type STT_LOPROC, (synonymous with |
| 2544 | STT_ARM_TFUNC). */ |
| 2545 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) |
| 2546 | == STT_LOPROC) |
| 2547 | MSYMBOL_SET_SPECIAL (msym); |
| 2548 | } |
| 2549 | |
| 2550 | static void |
| 2551 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
| 2552 | { |
| 2553 | if (coff_sym_is_thumb (val)) |
| 2554 | MSYMBOL_SET_SPECIAL (msym); |
| 2555 | } |
| 2556 | |
| 2557 | static void |
| 2558 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) |
| 2559 | { |
| 2560 | write_register_pid (ARM_PC_REGNUM, pc, ptid); |
| 2561 | |
| 2562 | /* If necessary, set the T bit. */ |
| 2563 | if (arm_apcs_32) |
| 2564 | { |
| 2565 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); |
| 2566 | if (arm_pc_is_thumb (pc)) |
| 2567 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); |
| 2568 | else |
| 2569 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); |
| 2570 | } |
| 2571 | } |
| 2572 | \f |
| 2573 | static enum gdb_osabi |
| 2574 | arm_elf_osabi_sniffer (bfd *abfd) |
| 2575 | { |
| 2576 | unsigned int elfosabi, eflags; |
| 2577 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
| 2578 | |
| 2579 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
| 2580 | |
| 2581 | if (elfosabi == ELFOSABI_ARM) |
| 2582 | /* GNU tools use this value. Check note sections in this case, |
| 2583 | as well. */ |
| 2584 | bfd_map_over_sections (abfd, |
| 2585 | generic_elf_osabi_sniff_abi_tag_sections, |
| 2586 | &osabi); |
| 2587 | |
| 2588 | /* Anything else will be handled by the generic ELF sniffer. */ |
| 2589 | return osabi; |
| 2590 | } |
| 2591 | |
| 2592 | \f |
| 2593 | /* Initialize the current architecture based on INFO. If possible, |
| 2594 | re-use an architecture from ARCHES, which is a list of |
| 2595 | architectures already created during this debugging session. |
| 2596 | |
| 2597 | Called e.g. at program startup, when reading a core file, and when |
| 2598 | reading a binary file. */ |
| 2599 | |
| 2600 | static struct gdbarch * |
| 2601 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 2602 | { |
| 2603 | struct gdbarch_tdep *tdep; |
| 2604 | struct gdbarch *gdbarch; |
| 2605 | struct gdbarch_list *best_arch; |
| 2606 | enum arm_abi_kind arm_abi = arm_abi_global; |
| 2607 | enum arm_float_model fp_model = arm_fp_model; |
| 2608 | |
| 2609 | /* If we have an object to base this architecture on, try to determine |
| 2610 | its ABI. */ |
| 2611 | |
| 2612 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
| 2613 | { |
| 2614 | int ei_osabi; |
| 2615 | |
| 2616 | switch (bfd_get_flavour (info.abfd)) |
| 2617 | { |
| 2618 | case bfd_target_aout_flavour: |
| 2619 | /* Assume it's an old APCS-style ABI. */ |
| 2620 | arm_abi = ARM_ABI_APCS; |
| 2621 | break; |
| 2622 | |
| 2623 | case bfd_target_coff_flavour: |
| 2624 | /* Assume it's an old APCS-style ABI. */ |
| 2625 | /* XXX WinCE? */ |
| 2626 | arm_abi = ARM_ABI_APCS; |
| 2627 | break; |
| 2628 | |
| 2629 | case bfd_target_elf_flavour: |
| 2630 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; |
| 2631 | if (ei_osabi == ELFOSABI_ARM) |
| 2632 | { |
| 2633 | /* GNU tools used to use this value, but do not for EABI |
| 2634 | objects. There's nowhere to tag an EABI version anyway, |
| 2635 | so assume APCS. */ |
| 2636 | arm_abi = ARM_ABI_APCS; |
| 2637 | } |
| 2638 | else if (ei_osabi == ELFOSABI_NONE) |
| 2639 | { |
| 2640 | int e_flags, eabi_ver; |
| 2641 | |
| 2642 | e_flags = elf_elfheader (info.abfd)->e_flags; |
| 2643 | eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
| 2644 | |
| 2645 | switch (eabi_ver) |
| 2646 | { |
| 2647 | case EF_ARM_EABI_UNKNOWN: |
| 2648 | /* Assume GNU tools. */ |
| 2649 | arm_abi = ARM_ABI_APCS; |
| 2650 | break; |
| 2651 | |
| 2652 | case EF_ARM_EABI_VER4: |
| 2653 | arm_abi = ARM_ABI_AAPCS; |
| 2654 | break; |
| 2655 | |
| 2656 | default: |
| 2657 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
| 2658 | arm_abi = ARM_ABI_APCS; |
| 2659 | break; |
| 2660 | } |
| 2661 | } |
| 2662 | break; |
| 2663 | |
| 2664 | default: |
| 2665 | /* Leave it as "auto". */ |
| 2666 | break; |
| 2667 | } |
| 2668 | } |
| 2669 | |
| 2670 | /* Now that we have inferred any architecture settings that we |
| 2671 | can, try to inherit from the last ARM ABI. */ |
| 2672 | if (arches != NULL) |
| 2673 | { |
| 2674 | if (arm_abi == ARM_ABI_AUTO) |
| 2675 | arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi; |
| 2676 | |
| 2677 | if (fp_model == ARM_FLOAT_AUTO) |
| 2678 | fp_model = gdbarch_tdep (arches->gdbarch)->fp_model; |
| 2679 | } |
| 2680 | else |
| 2681 | { |
| 2682 | /* There was no prior ARM architecture; fill in default values. */ |
| 2683 | |
| 2684 | if (arm_abi == ARM_ABI_AUTO) |
| 2685 | arm_abi = ARM_ABI_APCS; |
| 2686 | |
| 2687 | /* We used to default to FPA for generic ARM, but almost nobody |
| 2688 | uses that now, and we now provide a way for the user to force |
| 2689 | the model. So default to the most useful variant. */ |
| 2690 | if (fp_model == ARM_FLOAT_AUTO) |
| 2691 | fp_model = ARM_FLOAT_SOFT_FPA; |
| 2692 | } |
| 2693 | |
| 2694 | /* If there is already a candidate, use it. */ |
| 2695 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); |
| 2696 | best_arch != NULL; |
| 2697 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) |
| 2698 | { |
| 2699 | if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) |
| 2700 | continue; |
| 2701 | |
| 2702 | if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) |
| 2703 | continue; |
| 2704 | |
| 2705 | /* Found a match. */ |
| 2706 | break; |
| 2707 | } |
| 2708 | |
| 2709 | if (best_arch != NULL) |
| 2710 | return best_arch->gdbarch; |
| 2711 | |
| 2712 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); |
| 2713 | gdbarch = gdbarch_alloc (&info, tdep); |
| 2714 | |
| 2715 | /* Record additional information about the architecture we are defining. |
| 2716 | These are gdbarch discriminators, like the OSABI. */ |
| 2717 | tdep->arm_abi = arm_abi; |
| 2718 | tdep->fp_model = fp_model; |
| 2719 | |
| 2720 | /* Breakpoints. */ |
| 2721 | switch (info.byte_order) |
| 2722 | { |
| 2723 | case BFD_ENDIAN_BIG: |
| 2724 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
| 2725 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); |
| 2726 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; |
| 2727 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); |
| 2728 | |
| 2729 | break; |
| 2730 | |
| 2731 | case BFD_ENDIAN_LITTLE: |
| 2732 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
| 2733 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); |
| 2734 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; |
| 2735 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); |
| 2736 | |
| 2737 | break; |
| 2738 | |
| 2739 | default: |
| 2740 | internal_error (__FILE__, __LINE__, |
| 2741 | _("arm_gdbarch_init: bad byte order for float format")); |
| 2742 | } |
| 2743 | |
| 2744 | /* On ARM targets char defaults to unsigned. */ |
| 2745 | set_gdbarch_char_signed (gdbarch, 0); |
| 2746 | |
| 2747 | /* This should be low enough for everything. */ |
| 2748 | tdep->lowest_pc = 0x20; |
| 2749 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
| 2750 | |
| 2751 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
| 2752 | |
| 2753 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
| 2754 | |
| 2755 | /* Frame handling. */ |
| 2756 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
| 2757 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
| 2758 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); |
| 2759 | |
| 2760 | frame_base_set_default (gdbarch, &arm_normal_base); |
| 2761 | |
| 2762 | /* Address manipulation. */ |
| 2763 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); |
| 2764 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
| 2765 | |
| 2766 | /* Advance PC across function entry code. */ |
| 2767 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); |
| 2768 | |
| 2769 | /* Get the PC when a frame might not be available. */ |
| 2770 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
| 2771 | |
| 2772 | /* The stack grows downward. */ |
| 2773 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 2774 | |
| 2775 | /* Breakpoint manipulation. */ |
| 2776 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); |
| 2777 | |
| 2778 | /* Information about registers, etc. */ |
| 2779 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); |
| 2780 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
| 2781 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
| 2782 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); |
| 2783 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
| 2784 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
| 2785 | set_gdbarch_register_type (gdbarch, arm_register_type); |
| 2786 | |
| 2787 | /* Internal <-> external register number maps. */ |
| 2788 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
| 2789 | |
| 2790 | /* Integer registers are 4 bytes. */ |
| 2791 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
| 2792 | set_gdbarch_register_name (gdbarch, arm_register_name); |
| 2793 | |
| 2794 | /* Returning results. */ |
| 2795 | set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value); |
| 2796 | set_gdbarch_store_return_value (gdbarch, arm_store_return_value); |
| 2797 | set_gdbarch_deprecated_use_struct_convention (gdbarch, arm_use_struct_convention); |
| 2798 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, arm_extract_struct_value_address); |
| 2799 | |
| 2800 | /* Single stepping. */ |
| 2801 | /* XXX For an RDI target we should ask the target if it can single-step. */ |
| 2802 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); |
| 2803 | |
| 2804 | /* Disassembly. */ |
| 2805 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); |
| 2806 | |
| 2807 | /* Minsymbol frobbing. */ |
| 2808 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); |
| 2809 | set_gdbarch_coff_make_msymbol_special (gdbarch, |
| 2810 | arm_coff_make_msymbol_special); |
| 2811 | |
| 2812 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
| 2813 | gdbarch_init_osabi (info, gdbarch); |
| 2814 | |
| 2815 | /* Add some default predicates. */ |
| 2816 | frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer); |
| 2817 | frame_unwind_append_sniffer (gdbarch, arm_sigtramp_unwind_sniffer); |
| 2818 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
| 2819 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); |
| 2820 | |
| 2821 | /* Now we have tuned the configuration, set a few final things, |
| 2822 | based on what the OS ABI has told us. */ |
| 2823 | |
| 2824 | if (tdep->jb_pc >= 0) |
| 2825 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); |
| 2826 | |
| 2827 | /* Floating point sizes and format. */ |
| 2828 | switch (info.byte_order) |
| 2829 | { |
| 2830 | case BFD_ENDIAN_BIG: |
| 2831 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
| 2832 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); |
| 2833 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); |
| 2834 | break; |
| 2835 | |
| 2836 | case BFD_ENDIAN_LITTLE: |
| 2837 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
| 2838 | if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA) |
| 2839 | { |
| 2840 | set_gdbarch_double_format |
| 2841 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); |
| 2842 | set_gdbarch_long_double_format |
| 2843 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); |
| 2844 | } |
| 2845 | else |
| 2846 | { |
| 2847 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); |
| 2848 | set_gdbarch_long_double_format (gdbarch, |
| 2849 | &floatformat_ieee_double_little); |
| 2850 | } |
| 2851 | break; |
| 2852 | |
| 2853 | default: |
| 2854 | internal_error (__FILE__, __LINE__, |
| 2855 | _("arm_gdbarch_init: bad byte order for float format")); |
| 2856 | } |
| 2857 | |
| 2858 | return gdbarch; |
| 2859 | } |
| 2860 | |
| 2861 | static void |
| 2862 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) |
| 2863 | { |
| 2864 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2865 | |
| 2866 | if (tdep == NULL) |
| 2867 | return; |
| 2868 | |
| 2869 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
| 2870 | (unsigned long) tdep->lowest_pc); |
| 2871 | } |
| 2872 | |
| 2873 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
| 2874 | |
| 2875 | void |
| 2876 | _initialize_arm_tdep (void) |
| 2877 | { |
| 2878 | struct ui_file *stb; |
| 2879 | long length; |
| 2880 | struct cmd_list_element *new_set, *new_show; |
| 2881 | const char *setname; |
| 2882 | const char *setdesc; |
| 2883 | const char **regnames; |
| 2884 | int numregs, i, j; |
| 2885 | static char *helptext; |
| 2886 | char regdesc[1024], *rdptr = regdesc; |
| 2887 | size_t rest = sizeof (regdesc); |
| 2888 | |
| 2889 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
| 2890 | |
| 2891 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
| 2892 | gdbarch_register_osabi_sniffer (bfd_arch_arm, |
| 2893 | bfd_target_elf_flavour, |
| 2894 | arm_elf_osabi_sniffer); |
| 2895 | |
| 2896 | /* Get the number of possible sets of register names defined in opcodes. */ |
| 2897 | num_disassembly_options = get_arm_regname_num_options (); |
| 2898 | |
| 2899 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
| 2900 | add_prefix_cmd ("arm", no_class, set_arm_command, |
| 2901 | _("Various ARM-specific commands."), |
| 2902 | &setarmcmdlist, "set arm ", 0, &setlist); |
| 2903 | |
| 2904 | add_prefix_cmd ("arm", no_class, show_arm_command, |
| 2905 | _("Various ARM-specific commands."), |
| 2906 | &showarmcmdlist, "show arm ", 0, &showlist); |
| 2907 | |
| 2908 | /* Sync the opcode insn printer with our register viewer. */ |
| 2909 | parse_arm_disassembler_option ("reg-names-std"); |
| 2910 | |
| 2911 | /* Initialize the array that will be passed to |
| 2912 | add_setshow_enum_cmd(). */ |
| 2913 | valid_disassembly_styles |
| 2914 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); |
| 2915 | for (i = 0; i < num_disassembly_options; i++) |
| 2916 | { |
| 2917 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); |
| 2918 | valid_disassembly_styles[i] = setname; |
| 2919 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
| 2920 | rdptr += length; |
| 2921 | rest -= length; |
| 2922 | /* Copy the default names (if found) and synchronize disassembler. */ |
| 2923 | if (!strcmp (setname, "std")) |
| 2924 | { |
| 2925 | disassembly_style = setname; |
| 2926 | current_option = i; |
| 2927 | for (j = 0; j < numregs; j++) |
| 2928 | arm_register_names[j] = (char *) regnames[j]; |
| 2929 | set_arm_regname_option (i); |
| 2930 | } |
| 2931 | } |
| 2932 | /* Mark the end of valid options. */ |
| 2933 | valid_disassembly_styles[num_disassembly_options] = NULL; |
| 2934 | |
| 2935 | /* Create the help text. */ |
| 2936 | stb = mem_fileopen (); |
| 2937 | fprintf_unfiltered (stb, "%s%s%s", |
| 2938 | _("The valid values are:\n"), |
| 2939 | regdesc, |
| 2940 | _("The default is \"std\".")); |
| 2941 | helptext = ui_file_xstrdup (stb, &length); |
| 2942 | ui_file_delete (stb); |
| 2943 | |
| 2944 | add_setshow_enum_cmd("disassembler", no_class, |
| 2945 | valid_disassembly_styles, &disassembly_style, |
| 2946 | _("Set the disassembly style."), |
| 2947 | _("Show the disassembly style."), |
| 2948 | helptext, |
| 2949 | set_disassembly_style_sfunc, |
| 2950 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
| 2951 | &setarmcmdlist, &showarmcmdlist); |
| 2952 | |
| 2953 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, |
| 2954 | _("Set usage of ARM 32-bit mode."), |
| 2955 | _("Show usage of ARM 32-bit mode."), |
| 2956 | _("When off, a 26-bit PC will be used."), |
| 2957 | NULL, |
| 2958 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
| 2959 | &setarmcmdlist, &showarmcmdlist); |
| 2960 | |
| 2961 | /* Add a command to allow the user to force the FPU model. */ |
| 2962 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
| 2963 | _("Set the floating point type."), |
| 2964 | _("Show the floating point type."), |
| 2965 | _("auto - Determine the FP typefrom the OS-ABI.\n\ |
| 2966 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ |
| 2967 | fpa - FPA co-processor (GCC compiled).\n\ |
| 2968 | softvfp - Software FP with pure-endian doubles.\n\ |
| 2969 | vfp - VFP co-processor."), |
| 2970 | set_fp_model_sfunc, show_fp_model, |
| 2971 | &setarmcmdlist, &showarmcmdlist); |
| 2972 | |
| 2973 | /* Add a command to allow the user to force the ABI. */ |
| 2974 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, |
| 2975 | _("Set the ABI."), |
| 2976 | _("Show the ABI."), |
| 2977 | NULL, arm_set_abi, arm_show_abi, |
| 2978 | &setarmcmdlist, &showarmcmdlist); |
| 2979 | |
| 2980 | /* Debugging flag. */ |
| 2981 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
| 2982 | _("Set ARM debugging."), |
| 2983 | _("Show ARM debugging."), |
| 2984 | _("When on, arm-specific debugging is enabled."), |
| 2985 | NULL, |
| 2986 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
| 2987 | &setdebuglist, &showdebuglist); |
| 2988 | } |