| 1 | /* Common target dependent code for GDB on ARM systems. |
| 2 | |
| 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, |
| 4 | 2000, 2001, 2002, 2003, 2004, 2005, 2006 |
| 5 | Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; if not, write to the Free Software |
| 21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 22 | Boston, MA 02110-1301, USA. */ |
| 23 | |
| 24 | #include <ctype.h> /* XXX for isupper () */ |
| 25 | |
| 26 | #include "defs.h" |
| 27 | #include "frame.h" |
| 28 | #include "inferior.h" |
| 29 | #include "gdbcmd.h" |
| 30 | #include "gdbcore.h" |
| 31 | #include "gdb_string.h" |
| 32 | #include "dis-asm.h" /* For register styles. */ |
| 33 | #include "regcache.h" |
| 34 | #include "doublest.h" |
| 35 | #include "value.h" |
| 36 | #include "arch-utils.h" |
| 37 | #include "osabi.h" |
| 38 | #include "frame-unwind.h" |
| 39 | #include "frame-base.h" |
| 40 | #include "trad-frame.h" |
| 41 | #include "objfiles.h" |
| 42 | #include "dwarf2-frame.h" |
| 43 | |
| 44 | #include "arm-tdep.h" |
| 45 | #include "gdb/sim-arm.h" |
| 46 | |
| 47 | #include "elf-bfd.h" |
| 48 | #include "coff/internal.h" |
| 49 | #include "elf/arm.h" |
| 50 | |
| 51 | #include "gdb_assert.h" |
| 52 | |
| 53 | static int arm_debug; |
| 54 | |
| 55 | /* Macros for setting and testing a bit in a minimal symbol that marks |
| 56 | it as Thumb function. The MSB of the minimal symbol's "info" field |
| 57 | is used for this purpose. |
| 58 | |
| 59 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. |
| 60 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
| 61 | |
| 62 | #define MSYMBOL_SET_SPECIAL(msym) \ |
| 63 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \ |
| 64 | | 0x80000000) |
| 65 | |
| 66 | #define MSYMBOL_IS_SPECIAL(msym) \ |
| 67 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) |
| 68 | |
| 69 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
| 70 | static struct cmd_list_element *setarmcmdlist = NULL; |
| 71 | static struct cmd_list_element *showarmcmdlist = NULL; |
| 72 | |
| 73 | /* The type of floating-point to use. Keep this in sync with enum |
| 74 | arm_float_model, and the help string in _initialize_arm_tdep. */ |
| 75 | static const char *fp_model_strings[] = |
| 76 | { |
| 77 | "auto", |
| 78 | "softfpa", |
| 79 | "fpa", |
| 80 | "softvfp", |
| 81 | "vfp", |
| 82 | NULL |
| 83 | }; |
| 84 | |
| 85 | /* A variable that can be configured by the user. */ |
| 86 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; |
| 87 | static const char *current_fp_model = "auto"; |
| 88 | |
| 89 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
| 90 | static const char *arm_abi_strings[] = |
| 91 | { |
| 92 | "auto", |
| 93 | "APCS", |
| 94 | "AAPCS", |
| 95 | NULL |
| 96 | }; |
| 97 | |
| 98 | /* A variable that can be configured by the user. */ |
| 99 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; |
| 100 | static const char *arm_abi_string = "auto"; |
| 101 | |
| 102 | /* Number of different reg name sets (options). */ |
| 103 | static int num_disassembly_options; |
| 104 | |
| 105 | /* We have more registers than the disassembler as gdb can print the value |
| 106 | of special registers as well. |
| 107 | The general register names are overwritten by whatever is being used by |
| 108 | the disassembler at the moment. We also adjust the case of cpsr and fps. */ |
| 109 | |
| 110 | /* Initial value: Register names used in ARM's ISA documentation. */ |
| 111 | static char * arm_register_name_strings[] = |
| 112 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
| 113 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ |
| 114 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ |
| 115 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ |
| 116 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ |
| 117 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ |
| 118 | "fps", "cpsr" }; /* 24 25 */ |
| 119 | static char **arm_register_names = arm_register_name_strings; |
| 120 | |
| 121 | /* Valid register name styles. */ |
| 122 | static const char **valid_disassembly_styles; |
| 123 | |
| 124 | /* Disassembly style to use. Default to "std" register names. */ |
| 125 | static const char *disassembly_style; |
| 126 | /* Index to that option in the opcodes table. */ |
| 127 | static int current_option; |
| 128 | |
| 129 | /* This is used to keep the bfd arch_info in sync with the disassembly |
| 130 | style. */ |
| 131 | static void set_disassembly_style_sfunc(char *, int, |
| 132 | struct cmd_list_element *); |
| 133 | static void set_disassembly_style (void); |
| 134 | |
| 135 | static void convert_from_extended (const struct floatformat *, const void *, |
| 136 | void *); |
| 137 | static void convert_to_extended (const struct floatformat *, void *, |
| 138 | const void *); |
| 139 | |
| 140 | struct arm_prologue_cache |
| 141 | { |
| 142 | /* The stack pointer at the time this frame was created; i.e. the |
| 143 | caller's stack pointer when this function was called. It is used |
| 144 | to identify this frame. */ |
| 145 | CORE_ADDR prev_sp; |
| 146 | |
| 147 | /* The frame base for this frame is just prev_sp + frame offset - |
| 148 | frame size. FRAMESIZE is the size of this stack frame, and |
| 149 | FRAMEOFFSET if the initial offset from the stack pointer (this |
| 150 | frame's stack pointer, not PREV_SP) to the frame base. */ |
| 151 | |
| 152 | int framesize; |
| 153 | int frameoffset; |
| 154 | |
| 155 | /* The register used to hold the frame pointer for this frame. */ |
| 156 | int framereg; |
| 157 | |
| 158 | /* Saved register offsets. */ |
| 159 | struct trad_frame_saved_reg *saved_regs; |
| 160 | }; |
| 161 | |
| 162 | /* Addresses for calling Thumb functions have the bit 0 set. |
| 163 | Here are some macros to test, set, or clear bit 0 of addresses. */ |
| 164 | #define IS_THUMB_ADDR(addr) ((addr) & 1) |
| 165 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) |
| 166 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) |
| 167 | |
| 168 | /* Set to true if the 32-bit mode is in use. */ |
| 169 | |
| 170 | int arm_apcs_32 = 1; |
| 171 | |
| 172 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
| 173 | function. */ |
| 174 | |
| 175 | int |
| 176 | arm_pc_is_thumb (CORE_ADDR memaddr) |
| 177 | { |
| 178 | struct minimal_symbol *sym; |
| 179 | |
| 180 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
| 181 | if (IS_THUMB_ADDR (memaddr)) |
| 182 | return 1; |
| 183 | |
| 184 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
| 185 | sym = lookup_minimal_symbol_by_pc (memaddr); |
| 186 | if (sym) |
| 187 | { |
| 188 | return (MSYMBOL_IS_SPECIAL (sym)); |
| 189 | } |
| 190 | else |
| 191 | { |
| 192 | return 0; |
| 193 | } |
| 194 | } |
| 195 | |
| 196 | /* Remove useless bits from addresses in a running program. */ |
| 197 | static CORE_ADDR |
| 198 | arm_addr_bits_remove (CORE_ADDR val) |
| 199 | { |
| 200 | if (arm_apcs_32) |
| 201 | return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc)); |
| 202 | else |
| 203 | return (val & 0x03fffffc); |
| 204 | } |
| 205 | |
| 206 | /* When reading symbols, we need to zap the low bit of the address, |
| 207 | which may be set to 1 for Thumb functions. */ |
| 208 | static CORE_ADDR |
| 209 | arm_smash_text_address (CORE_ADDR val) |
| 210 | { |
| 211 | return val & ~1; |
| 212 | } |
| 213 | |
| 214 | /* Immediately after a function call, return the saved pc. Can't |
| 215 | always go through the frames for this because on some machines the |
| 216 | new frame is not set up until the new function executes some |
| 217 | instructions. */ |
| 218 | |
| 219 | static CORE_ADDR |
| 220 | arm_saved_pc_after_call (struct frame_info *frame) |
| 221 | { |
| 222 | return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM)); |
| 223 | } |
| 224 | |
| 225 | /* A typical Thumb prologue looks like this: |
| 226 | push {r7, lr} |
| 227 | add sp, sp, #-28 |
| 228 | add r7, sp, #12 |
| 229 | Sometimes the latter instruction may be replaced by: |
| 230 | mov r7, sp |
| 231 | |
| 232 | or like this: |
| 233 | push {r7, lr} |
| 234 | mov r7, sp |
| 235 | sub sp, #12 |
| 236 | |
| 237 | or, on tpcs, like this: |
| 238 | sub sp,#16 |
| 239 | push {r7, lr} |
| 240 | (many instructions) |
| 241 | mov r7, sp |
| 242 | sub sp, #12 |
| 243 | |
| 244 | There is always one instruction of three classes: |
| 245 | 1 - push |
| 246 | 2 - setting of r7 |
| 247 | 3 - adjusting of sp |
| 248 | |
| 249 | When we have found at least one of each class we are done with the prolog. |
| 250 | Note that the "sub sp, #NN" before the push does not count. |
| 251 | */ |
| 252 | |
| 253 | static CORE_ADDR |
| 254 | thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end) |
| 255 | { |
| 256 | CORE_ADDR current_pc; |
| 257 | /* findmask: |
| 258 | bit 0 - push { rlist } |
| 259 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) |
| 260 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) |
| 261 | */ |
| 262 | int findmask = 0; |
| 263 | |
| 264 | for (current_pc = pc; |
| 265 | current_pc + 2 < func_end && current_pc < pc + 40; |
| 266 | current_pc += 2) |
| 267 | { |
| 268 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); |
| 269 | |
| 270 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 271 | { |
| 272 | findmask |= 1; /* push found */ |
| 273 | } |
| 274 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
| 275 | sub sp, #simm */ |
| 276 | { |
| 277 | if ((findmask & 1) == 0) /* before push ? */ |
| 278 | continue; |
| 279 | else |
| 280 | findmask |= 4; /* add/sub sp found */ |
| 281 | } |
| 282 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 283 | { |
| 284 | findmask |= 2; /* setting of r7 found */ |
| 285 | } |
| 286 | else if (insn == 0x466f) /* mov r7, sp */ |
| 287 | { |
| 288 | findmask |= 2; /* setting of r7 found */ |
| 289 | } |
| 290 | else if (findmask == (4+2+1)) |
| 291 | { |
| 292 | /* We have found one of each type of prologue instruction */ |
| 293 | break; |
| 294 | } |
| 295 | else |
| 296 | /* Something in the prolog that we don't care about or some |
| 297 | instruction from outside the prolog scheduled here for |
| 298 | optimization. */ |
| 299 | continue; |
| 300 | } |
| 301 | |
| 302 | return current_pc; |
| 303 | } |
| 304 | |
| 305 | /* Advance the PC across any function entry prologue instructions to |
| 306 | reach some "real" code. |
| 307 | |
| 308 | The APCS (ARM Procedure Call Standard) defines the following |
| 309 | prologue: |
| 310 | |
| 311 | mov ip, sp |
| 312 | [stmfd sp!, {a1,a2,a3,a4}] |
| 313 | stmfd sp!, {...,fp,ip,lr,pc} |
| 314 | [stfe f7, [sp, #-12]!] |
| 315 | [stfe f6, [sp, #-12]!] |
| 316 | [stfe f5, [sp, #-12]!] |
| 317 | [stfe f4, [sp, #-12]!] |
| 318 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ |
| 319 | |
| 320 | static CORE_ADDR |
| 321 | arm_skip_prologue (CORE_ADDR pc) |
| 322 | { |
| 323 | unsigned long inst; |
| 324 | CORE_ADDR skip_pc; |
| 325 | CORE_ADDR func_addr, func_end = 0; |
| 326 | char *func_name; |
| 327 | struct symtab_and_line sal; |
| 328 | |
| 329 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
| 330 | if (deprecated_pc_in_call_dummy (pc)) |
| 331 | return pc; |
| 332 | |
| 333 | /* See what the symbol table says. */ |
| 334 | |
| 335 | if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end)) |
| 336 | { |
| 337 | struct symbol *sym; |
| 338 | |
| 339 | /* Found a function. */ |
| 340 | sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL); |
| 341 | if (sym && SYMBOL_LANGUAGE (sym) != language_asm) |
| 342 | { |
| 343 | /* Don't use this trick for assembly source files. */ |
| 344 | sal = find_pc_line (func_addr, 0); |
| 345 | if ((sal.line != 0) && (sal.end < func_end)) |
| 346 | return sal.end; |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | /* Check if this is Thumb code. */ |
| 351 | if (arm_pc_is_thumb (pc)) |
| 352 | return thumb_skip_prologue (pc, func_end); |
| 353 | |
| 354 | /* Can't find the prologue end in the symbol table, try it the hard way |
| 355 | by disassembling the instructions. */ |
| 356 | |
| 357 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
| 358 | if (func_end == 0 || func_end > pc + 64) |
| 359 | func_end = pc + 64; |
| 360 | |
| 361 | for (skip_pc = pc; skip_pc < func_end; skip_pc += 4) |
| 362 | { |
| 363 | inst = read_memory_unsigned_integer (skip_pc, 4); |
| 364 | |
| 365 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
| 366 | if (inst == 0xe1a0c00d) /* mov ip, sp */ |
| 367 | continue; |
| 368 | |
| 369 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
| 370 | continue; |
| 371 | |
| 372 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ |
| 373 | continue; |
| 374 | |
| 375 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
| 376 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 377 | continue; |
| 378 | |
| 379 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
| 380 | continue; |
| 381 | |
| 382 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
| 383 | continue; |
| 384 | |
| 385 | /* Any insns after this point may float into the code, if it makes |
| 386 | for better instruction scheduling, so we skip them only if we |
| 387 | find them, but still consider the function to be frame-ful. */ |
| 388 | |
| 389 | /* We may have either one sfmfd instruction here, or several stfe |
| 390 | insns, depending on the version of floating point code we |
| 391 | support. */ |
| 392 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
| 393 | continue; |
| 394 | |
| 395 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
| 396 | continue; |
| 397 | |
| 398 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
| 399 | continue; |
| 400 | |
| 401 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ |
| 402 | continue; |
| 403 | |
| 404 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ |
| 405 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ |
| 406 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ |
| 407 | continue; |
| 408 | |
| 409 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ |
| 410 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ |
| 411 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ |
| 412 | continue; |
| 413 | |
| 414 | /* Un-recognized instruction; stop scanning. */ |
| 415 | break; |
| 416 | } |
| 417 | |
| 418 | return skip_pc; /* End of prologue */ |
| 419 | } |
| 420 | |
| 421 | /* *INDENT-OFF* */ |
| 422 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
| 423 | This function decodes a Thumb function prologue to determine: |
| 424 | 1) the size of the stack frame |
| 425 | 2) which registers are saved on it |
| 426 | 3) the offsets of saved regs |
| 427 | 4) the offset from the stack pointer to the frame pointer |
| 428 | |
| 429 | A typical Thumb function prologue would create this stack frame |
| 430 | (offsets relative to FP) |
| 431 | old SP -> 24 stack parameters |
| 432 | 20 LR |
| 433 | 16 R7 |
| 434 | R7 -> 0 local variables (16 bytes) |
| 435 | SP -> -12 additional stack space (12 bytes) |
| 436 | The frame size would thus be 36 bytes, and the frame offset would be |
| 437 | 12 bytes. The frame register is R7. |
| 438 | |
| 439 | The comments for thumb_skip_prolog() describe the algorithm we use |
| 440 | to detect the end of the prolog. */ |
| 441 | /* *INDENT-ON* */ |
| 442 | |
| 443 | static void |
| 444 | thumb_scan_prologue (CORE_ADDR prev_pc, struct arm_prologue_cache *cache) |
| 445 | { |
| 446 | CORE_ADDR prologue_start; |
| 447 | CORE_ADDR prologue_end; |
| 448 | CORE_ADDR current_pc; |
| 449 | /* Which register has been copied to register n? */ |
| 450 | int saved_reg[16]; |
| 451 | /* findmask: |
| 452 | bit 0 - push { rlist } |
| 453 | bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7) |
| 454 | bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp) |
| 455 | */ |
| 456 | int findmask = 0; |
| 457 | int i; |
| 458 | |
| 459 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
| 460 | { |
| 461 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 462 | |
| 463 | if (sal.line == 0) /* no line info, use current PC */ |
| 464 | prologue_end = prev_pc; |
| 465 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
| 466 | prologue_end = sal.end; /* (probably means no prologue) */ |
| 467 | } |
| 468 | else |
| 469 | /* We're in the boondocks: allow for |
| 470 | 16 pushes, an add, and "mv fp,sp". */ |
| 471 | prologue_end = prologue_start + 40; |
| 472 | |
| 473 | prologue_end = min (prologue_end, prev_pc); |
| 474 | |
| 475 | /* Initialize the saved register map. When register H is copied to |
| 476 | register L, we will put H in saved_reg[L]. */ |
| 477 | for (i = 0; i < 16; i++) |
| 478 | saved_reg[i] = i; |
| 479 | |
| 480 | /* Search the prologue looking for instructions that set up the |
| 481 | frame pointer, adjust the stack pointer, and save registers. |
| 482 | Do this until all basic prolog instructions are found. */ |
| 483 | |
| 484 | cache->framesize = 0; |
| 485 | for (current_pc = prologue_start; |
| 486 | (current_pc < prologue_end) && ((findmask & 7) != 7); |
| 487 | current_pc += 2) |
| 488 | { |
| 489 | unsigned short insn; |
| 490 | int regno; |
| 491 | int offset; |
| 492 | |
| 493 | insn = read_memory_unsigned_integer (current_pc, 2); |
| 494 | |
| 495 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 496 | { |
| 497 | int mask; |
| 498 | findmask |= 1; /* push found */ |
| 499 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
| 500 | whether to save LR (R14). */ |
| 501 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
| 502 | |
| 503 | /* Calculate offsets of saved R0-R7 and LR. */ |
| 504 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
| 505 | if (mask & (1 << regno)) |
| 506 | { |
| 507 | cache->framesize += 4; |
| 508 | cache->saved_regs[saved_reg[regno]].addr = -cache->framesize; |
| 509 | /* Reset saved register map. */ |
| 510 | saved_reg[regno] = regno; |
| 511 | } |
| 512 | } |
| 513 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
| 514 | sub sp, #simm */ |
| 515 | { |
| 516 | if ((findmask & 1) == 0) /* before push? */ |
| 517 | continue; |
| 518 | else |
| 519 | findmask |= 4; /* add/sub sp found */ |
| 520 | |
| 521 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
| 522 | if (insn & 0x80) /* is it signed? (==subtracting) */ |
| 523 | { |
| 524 | cache->frameoffset += offset; |
| 525 | offset = -offset; |
| 526 | } |
| 527 | cache->framesize -= offset; |
| 528 | } |
| 529 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 530 | { |
| 531 | findmask |= 2; /* setting of r7 found */ |
| 532 | cache->framereg = THUMB_FP_REGNUM; |
| 533 | /* get scaled offset */ |
| 534 | cache->frameoffset = (insn & 0xff) << 2; |
| 535 | } |
| 536 | else if (insn == 0x466f) /* mov r7, sp */ |
| 537 | { |
| 538 | findmask |= 2; /* setting of r7 found */ |
| 539 | cache->framereg = THUMB_FP_REGNUM; |
| 540 | cache->frameoffset = 0; |
| 541 | saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM; |
| 542 | } |
| 543 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ |
| 544 | { |
| 545 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
| 546 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
| 547 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
| 548 | } |
| 549 | else |
| 550 | /* Something in the prolog that we don't care about or some |
| 551 | instruction from outside the prolog scheduled here for |
| 552 | optimization. */ |
| 553 | continue; |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | /* This function decodes an ARM function prologue to determine: |
| 558 | 1) the size of the stack frame |
| 559 | 2) which registers are saved on it |
| 560 | 3) the offsets of saved regs |
| 561 | 4) the offset from the stack pointer to the frame pointer |
| 562 | This information is stored in the "extra" fields of the frame_info. |
| 563 | |
| 564 | There are two basic forms for the ARM prologue. The fixed argument |
| 565 | function call will look like: |
| 566 | |
| 567 | mov ip, sp |
| 568 | stmfd sp!, {fp, ip, lr, pc} |
| 569 | sub fp, ip, #4 |
| 570 | [sub sp, sp, #4] |
| 571 | |
| 572 | Which would create this stack frame (offsets relative to FP): |
| 573 | IP -> 4 (caller's stack) |
| 574 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 575 | -4 LR (return address in caller) |
| 576 | -8 IP (copy of caller's SP) |
| 577 | -12 FP (caller's FP) |
| 578 | SP -> -28 Local variables |
| 579 | |
| 580 | The frame size would thus be 32 bytes, and the frame offset would be |
| 581 | 28 bytes. The stmfd call can also save any of the vN registers it |
| 582 | plans to use, which increases the frame size accordingly. |
| 583 | |
| 584 | Note: The stored PC is 8 off of the STMFD instruction that stored it |
| 585 | because the ARM Store instructions always store PC + 8 when you read |
| 586 | the PC register. |
| 587 | |
| 588 | A variable argument function call will look like: |
| 589 | |
| 590 | mov ip, sp |
| 591 | stmfd sp!, {a1, a2, a3, a4} |
| 592 | stmfd sp!, {fp, ip, lr, pc} |
| 593 | sub fp, ip, #20 |
| 594 | |
| 595 | Which would create this stack frame (offsets relative to FP): |
| 596 | IP -> 20 (caller's stack) |
| 597 | 16 A4 |
| 598 | 12 A3 |
| 599 | 8 A2 |
| 600 | 4 A1 |
| 601 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 602 | -4 LR (return address in caller) |
| 603 | -8 IP (copy of caller's SP) |
| 604 | -12 FP (caller's FP) |
| 605 | SP -> -28 Local variables |
| 606 | |
| 607 | The frame size would thus be 48 bytes, and the frame offset would be |
| 608 | 28 bytes. |
| 609 | |
| 610 | There is another potential complication, which is that the optimizer |
| 611 | will try to separate the store of fp in the "stmfd" instruction from |
| 612 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so |
| 613 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... |
| 614 | |
| 615 | Also, note, the original version of the ARM toolchain claimed that there |
| 616 | should be an |
| 617 | |
| 618 | instruction at the end of the prologue. I have never seen GCC produce |
| 619 | this, and the ARM docs don't mention it. We still test for it below in |
| 620 | case it happens... |
| 621 | |
| 622 | */ |
| 623 | |
| 624 | static void |
| 625 | arm_scan_prologue (struct frame_info *next_frame, struct arm_prologue_cache *cache) |
| 626 | { |
| 627 | int regno, sp_offset, fp_offset, ip_offset; |
| 628 | CORE_ADDR prologue_start, prologue_end, current_pc; |
| 629 | CORE_ADDR prev_pc = frame_pc_unwind (next_frame); |
| 630 | |
| 631 | /* Assume there is no frame until proven otherwise. */ |
| 632 | cache->framereg = ARM_SP_REGNUM; |
| 633 | cache->framesize = 0; |
| 634 | cache->frameoffset = 0; |
| 635 | |
| 636 | /* Check for Thumb prologue. */ |
| 637 | if (arm_pc_is_thumb (prev_pc)) |
| 638 | { |
| 639 | thumb_scan_prologue (prev_pc, cache); |
| 640 | return; |
| 641 | } |
| 642 | |
| 643 | /* Find the function prologue. If we can't find the function in |
| 644 | the symbol table, peek in the stack frame to find the PC. */ |
| 645 | if (find_pc_partial_function (prev_pc, NULL, &prologue_start, &prologue_end)) |
| 646 | { |
| 647 | /* One way to find the end of the prologue (which works well |
| 648 | for unoptimized code) is to do the following: |
| 649 | |
| 650 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 651 | |
| 652 | if (sal.line == 0) |
| 653 | prologue_end = prev_pc; |
| 654 | else if (sal.end < prologue_end) |
| 655 | prologue_end = sal.end; |
| 656 | |
| 657 | This mechanism is very accurate so long as the optimizer |
| 658 | doesn't move any instructions from the function body into the |
| 659 | prologue. If this happens, sal.end will be the last |
| 660 | instruction in the first hunk of prologue code just before |
| 661 | the first instruction that the scheduler has moved from |
| 662 | the body to the prologue. |
| 663 | |
| 664 | In order to make sure that we scan all of the prologue |
| 665 | instructions, we use a slightly less accurate mechanism which |
| 666 | may scan more than necessary. To help compensate for this |
| 667 | lack of accuracy, the prologue scanning loop below contains |
| 668 | several clauses which'll cause the loop to terminate early if |
| 669 | an implausible prologue instruction is encountered. |
| 670 | |
| 671 | The expression |
| 672 | |
| 673 | prologue_start + 64 |
| 674 | |
| 675 | is a suitable endpoint since it accounts for the largest |
| 676 | possible prologue plus up to five instructions inserted by |
| 677 | the scheduler. */ |
| 678 | |
| 679 | if (prologue_end > prologue_start + 64) |
| 680 | { |
| 681 | prologue_end = prologue_start + 64; /* See above. */ |
| 682 | } |
| 683 | } |
| 684 | else |
| 685 | { |
| 686 | /* We have no symbol information. Our only option is to assume this |
| 687 | function has a standard stack frame and the normal frame register. |
| 688 | Then, we can find the value of our frame pointer on entrance to |
| 689 | the callee (or at the present moment if this is the innermost frame). |
| 690 | The value stored there should be the address of the stmfd + 8. */ |
| 691 | CORE_ADDR frame_loc; |
| 692 | LONGEST return_value; |
| 693 | |
| 694 | frame_loc = frame_unwind_register_unsigned (next_frame, ARM_FP_REGNUM); |
| 695 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) |
| 696 | return; |
| 697 | else |
| 698 | { |
| 699 | prologue_start = ADDR_BITS_REMOVE (return_value) - 8; |
| 700 | prologue_end = prologue_start + 64; /* See above. */ |
| 701 | } |
| 702 | } |
| 703 | |
| 704 | if (prev_pc < prologue_end) |
| 705 | prologue_end = prev_pc; |
| 706 | |
| 707 | /* Now search the prologue looking for instructions that set up the |
| 708 | frame pointer, adjust the stack pointer, and save registers. |
| 709 | |
| 710 | Be careful, however, and if it doesn't look like a prologue, |
| 711 | don't try to scan it. If, for instance, a frameless function |
| 712 | begins with stmfd sp!, then we will tell ourselves there is |
| 713 | a frame, which will confuse stack traceback, as well as "finish" |
| 714 | and other operations that rely on a knowledge of the stack |
| 715 | traceback. |
| 716 | |
| 717 | In the APCS, the prologue should start with "mov ip, sp" so |
| 718 | if we don't see this as the first insn, we will stop. |
| 719 | |
| 720 | [Note: This doesn't seem to be true any longer, so it's now an |
| 721 | optional part of the prologue. - Kevin Buettner, 2001-11-20] |
| 722 | |
| 723 | [Note further: The "mov ip,sp" only seems to be missing in |
| 724 | frameless functions at optimization level "-O2" or above, |
| 725 | in which case it is often (but not always) replaced by |
| 726 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
| 727 | |
| 728 | sp_offset = fp_offset = ip_offset = 0; |
| 729 | |
| 730 | for (current_pc = prologue_start; |
| 731 | current_pc < prologue_end; |
| 732 | current_pc += 4) |
| 733 | { |
| 734 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
| 735 | |
| 736 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
| 737 | { |
| 738 | ip_offset = 0; |
| 739 | continue; |
| 740 | } |
| 741 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
| 742 | { |
| 743 | unsigned imm = insn & 0xff; /* immediate value */ |
| 744 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 745 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 746 | ip_offset = imm; |
| 747 | continue; |
| 748 | } |
| 749 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ |
| 750 | { |
| 751 | unsigned imm = insn & 0xff; /* immediate value */ |
| 752 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 753 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 754 | ip_offset = -imm; |
| 755 | continue; |
| 756 | } |
| 757 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 758 | { |
| 759 | sp_offset -= 4; |
| 760 | cache->saved_regs[ARM_LR_REGNUM].addr = sp_offset; |
| 761 | continue; |
| 762 | } |
| 763 | else if ((insn & 0xffff0000) == 0xe92d0000) |
| 764 | /* stmfd sp!, {..., fp, ip, lr, pc} |
| 765 | or |
| 766 | stmfd sp!, {a1, a2, a3, a4} */ |
| 767 | { |
| 768 | int mask = insn & 0xffff; |
| 769 | |
| 770 | /* Calculate offsets of saved registers. */ |
| 771 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
| 772 | if (mask & (1 << regno)) |
| 773 | { |
| 774 | sp_offset -= 4; |
| 775 | cache->saved_regs[regno].addr = sp_offset; |
| 776 | } |
| 777 | } |
| 778 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
| 779 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ |
| 780 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
| 781 | { |
| 782 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 783 | continue; |
| 784 | } |
| 785 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ |
| 786 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ |
| 787 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
| 788 | { |
| 789 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 790 | continue; |
| 791 | } |
| 792 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
| 793 | { |
| 794 | unsigned imm = insn & 0xff; /* immediate value */ |
| 795 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 796 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 797 | fp_offset = -imm + ip_offset; |
| 798 | cache->framereg = ARM_FP_REGNUM; |
| 799 | } |
| 800 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ |
| 801 | { |
| 802 | unsigned imm = insn & 0xff; /* immediate value */ |
| 803 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 804 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 805 | sp_offset -= imm; |
| 806 | } |
| 807 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ |
| 808 | { |
| 809 | sp_offset -= 12; |
| 810 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
| 811 | cache->saved_regs[regno].addr = sp_offset; |
| 812 | } |
| 813 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ |
| 814 | { |
| 815 | int n_saved_fp_regs; |
| 816 | unsigned int fp_start_reg, fp_bound_reg; |
| 817 | |
| 818 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
| 819 | { |
| 820 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 821 | n_saved_fp_regs = 3; |
| 822 | else |
| 823 | n_saved_fp_regs = 1; |
| 824 | } |
| 825 | else |
| 826 | { |
| 827 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 828 | n_saved_fp_regs = 2; |
| 829 | else |
| 830 | n_saved_fp_regs = 4; |
| 831 | } |
| 832 | |
| 833 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
| 834 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
| 835 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) |
| 836 | { |
| 837 | sp_offset -= 12; |
| 838 | cache->saved_regs[fp_start_reg++].addr = sp_offset; |
| 839 | } |
| 840 | } |
| 841 | else if ((insn & 0xf0000000) != 0xe0000000) |
| 842 | break; /* Condition not true, exit early */ |
| 843 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
| 844 | break; /* Don't scan past a block load */ |
| 845 | else |
| 846 | /* The optimizer might shove anything into the prologue, |
| 847 | so we just skip what we don't recognize. */ |
| 848 | continue; |
| 849 | } |
| 850 | |
| 851 | /* The frame size is just the negative of the offset (from the |
| 852 | original SP) of the last thing thing we pushed on the stack. |
| 853 | The frame offset is [new FP] - [new SP]. */ |
| 854 | cache->framesize = -sp_offset; |
| 855 | if (cache->framereg == ARM_FP_REGNUM) |
| 856 | cache->frameoffset = fp_offset - sp_offset; |
| 857 | else |
| 858 | cache->frameoffset = 0; |
| 859 | } |
| 860 | |
| 861 | static struct arm_prologue_cache * |
| 862 | arm_make_prologue_cache (struct frame_info *next_frame) |
| 863 | { |
| 864 | int reg; |
| 865 | struct arm_prologue_cache *cache; |
| 866 | CORE_ADDR unwound_fp; |
| 867 | |
| 868 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
| 869 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 870 | |
| 871 | arm_scan_prologue (next_frame, cache); |
| 872 | |
| 873 | unwound_fp = frame_unwind_register_unsigned (next_frame, cache->framereg); |
| 874 | if (unwound_fp == 0) |
| 875 | return cache; |
| 876 | |
| 877 | cache->prev_sp = unwound_fp + cache->framesize - cache->frameoffset; |
| 878 | |
| 879 | /* Calculate actual addresses of saved registers using offsets |
| 880 | determined by arm_scan_prologue. */ |
| 881 | for (reg = 0; reg < NUM_REGS; reg++) |
| 882 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
| 883 | cache->saved_regs[reg].addr += cache->prev_sp; |
| 884 | |
| 885 | return cache; |
| 886 | } |
| 887 | |
| 888 | /* Our frame ID for a normal frame is the current function's starting PC |
| 889 | and the caller's SP when we were called. */ |
| 890 | |
| 891 | static void |
| 892 | arm_prologue_this_id (struct frame_info *next_frame, |
| 893 | void **this_cache, |
| 894 | struct frame_id *this_id) |
| 895 | { |
| 896 | struct arm_prologue_cache *cache; |
| 897 | struct frame_id id; |
| 898 | CORE_ADDR func; |
| 899 | |
| 900 | if (*this_cache == NULL) |
| 901 | *this_cache = arm_make_prologue_cache (next_frame); |
| 902 | cache = *this_cache; |
| 903 | |
| 904 | func = frame_func_unwind (next_frame); |
| 905 | |
| 906 | /* This is meant to halt the backtrace at "_start". Make sure we |
| 907 | don't halt it at a generic dummy frame. */ |
| 908 | if (func <= LOWEST_PC) |
| 909 | return; |
| 910 | |
| 911 | /* If we've hit a wall, stop. */ |
| 912 | if (cache->prev_sp == 0) |
| 913 | return; |
| 914 | |
| 915 | id = frame_id_build (cache->prev_sp, func); |
| 916 | *this_id = id; |
| 917 | } |
| 918 | |
| 919 | static void |
| 920 | arm_prologue_prev_register (struct frame_info *next_frame, |
| 921 | void **this_cache, |
| 922 | int prev_regnum, |
| 923 | int *optimized, |
| 924 | enum lval_type *lvalp, |
| 925 | CORE_ADDR *addrp, |
| 926 | int *realnump, |
| 927 | gdb_byte *valuep) |
| 928 | { |
| 929 | struct arm_prologue_cache *cache; |
| 930 | |
| 931 | if (*this_cache == NULL) |
| 932 | *this_cache = arm_make_prologue_cache (next_frame); |
| 933 | cache = *this_cache; |
| 934 | |
| 935 | /* If we are asked to unwind the PC, then we need to return the LR |
| 936 | instead. The saved value of PC points into this frame's |
| 937 | prologue, not the next frame's resume location. */ |
| 938 | if (prev_regnum == ARM_PC_REGNUM) |
| 939 | prev_regnum = ARM_LR_REGNUM; |
| 940 | |
| 941 | /* SP is generally not saved to the stack, but this frame is |
| 942 | identified by NEXT_FRAME's stack pointer at the time of the call. |
| 943 | The value was already reconstructed into PREV_SP. */ |
| 944 | if (prev_regnum == ARM_SP_REGNUM) |
| 945 | { |
| 946 | *lvalp = not_lval; |
| 947 | if (valuep) |
| 948 | store_unsigned_integer (valuep, 4, cache->prev_sp); |
| 949 | return; |
| 950 | } |
| 951 | |
| 952 | trad_frame_get_prev_register (next_frame, cache->saved_regs, prev_regnum, |
| 953 | optimized, lvalp, addrp, realnump, valuep); |
| 954 | } |
| 955 | |
| 956 | struct frame_unwind arm_prologue_unwind = { |
| 957 | NORMAL_FRAME, |
| 958 | arm_prologue_this_id, |
| 959 | arm_prologue_prev_register |
| 960 | }; |
| 961 | |
| 962 | static const struct frame_unwind * |
| 963 | arm_prologue_unwind_sniffer (struct frame_info *next_frame) |
| 964 | { |
| 965 | return &arm_prologue_unwind; |
| 966 | } |
| 967 | |
| 968 | static struct arm_prologue_cache * |
| 969 | arm_make_stub_cache (struct frame_info *next_frame) |
| 970 | { |
| 971 | int reg; |
| 972 | struct arm_prologue_cache *cache; |
| 973 | CORE_ADDR unwound_fp; |
| 974 | |
| 975 | cache = frame_obstack_zalloc (sizeof (struct arm_prologue_cache)); |
| 976 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 977 | |
| 978 | cache->prev_sp = frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM); |
| 979 | |
| 980 | return cache; |
| 981 | } |
| 982 | |
| 983 | /* Our frame ID for a stub frame is the current SP and LR. */ |
| 984 | |
| 985 | static void |
| 986 | arm_stub_this_id (struct frame_info *next_frame, |
| 987 | void **this_cache, |
| 988 | struct frame_id *this_id) |
| 989 | { |
| 990 | struct arm_prologue_cache *cache; |
| 991 | |
| 992 | if (*this_cache == NULL) |
| 993 | *this_cache = arm_make_stub_cache (next_frame); |
| 994 | cache = *this_cache; |
| 995 | |
| 996 | *this_id = frame_id_build (cache->prev_sp, |
| 997 | frame_pc_unwind (next_frame)); |
| 998 | } |
| 999 | |
| 1000 | struct frame_unwind arm_stub_unwind = { |
| 1001 | NORMAL_FRAME, |
| 1002 | arm_stub_this_id, |
| 1003 | arm_prologue_prev_register |
| 1004 | }; |
| 1005 | |
| 1006 | static const struct frame_unwind * |
| 1007 | arm_stub_unwind_sniffer (struct frame_info *next_frame) |
| 1008 | { |
| 1009 | char dummy[4]; |
| 1010 | |
| 1011 | if (in_plt_section (frame_unwind_address_in_block (next_frame), NULL) |
| 1012 | || target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) |
| 1013 | return &arm_stub_unwind; |
| 1014 | |
| 1015 | return NULL; |
| 1016 | } |
| 1017 | |
| 1018 | static CORE_ADDR |
| 1019 | arm_normal_frame_base (struct frame_info *next_frame, void **this_cache) |
| 1020 | { |
| 1021 | struct arm_prologue_cache *cache; |
| 1022 | |
| 1023 | if (*this_cache == NULL) |
| 1024 | *this_cache = arm_make_prologue_cache (next_frame); |
| 1025 | cache = *this_cache; |
| 1026 | |
| 1027 | return cache->prev_sp + cache->frameoffset - cache->framesize; |
| 1028 | } |
| 1029 | |
| 1030 | struct frame_base arm_normal_base = { |
| 1031 | &arm_prologue_unwind, |
| 1032 | arm_normal_frame_base, |
| 1033 | arm_normal_frame_base, |
| 1034 | arm_normal_frame_base |
| 1035 | }; |
| 1036 | |
| 1037 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
| 1038 | dummy frame. The frame ID's base needs to match the TOS value |
| 1039 | saved by save_dummy_frame_tos() and returned from |
| 1040 | arm_push_dummy_call, and the PC needs to match the dummy frame's |
| 1041 | breakpoint. */ |
| 1042 | |
| 1043 | static struct frame_id |
| 1044 | arm_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1045 | { |
| 1046 | return frame_id_build (frame_unwind_register_unsigned (next_frame, ARM_SP_REGNUM), |
| 1047 | frame_pc_unwind (next_frame)); |
| 1048 | } |
| 1049 | |
| 1050 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
| 1051 | be used to construct the previous frame's ID, after looking up the |
| 1052 | containing function). */ |
| 1053 | |
| 1054 | static CORE_ADDR |
| 1055 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1056 | { |
| 1057 | CORE_ADDR pc; |
| 1058 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); |
| 1059 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; |
| 1060 | } |
| 1061 | |
| 1062 | static CORE_ADDR |
| 1063 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1064 | { |
| 1065 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); |
| 1066 | } |
| 1067 | |
| 1068 | /* When arguments must be pushed onto the stack, they go on in reverse |
| 1069 | order. The code below implements a FILO (stack) to do this. */ |
| 1070 | |
| 1071 | struct stack_item |
| 1072 | { |
| 1073 | int len; |
| 1074 | struct stack_item *prev; |
| 1075 | void *data; |
| 1076 | }; |
| 1077 | |
| 1078 | static struct stack_item * |
| 1079 | push_stack_item (struct stack_item *prev, void *contents, int len) |
| 1080 | { |
| 1081 | struct stack_item *si; |
| 1082 | si = xmalloc (sizeof (struct stack_item)); |
| 1083 | si->data = xmalloc (len); |
| 1084 | si->len = len; |
| 1085 | si->prev = prev; |
| 1086 | memcpy (si->data, contents, len); |
| 1087 | return si; |
| 1088 | } |
| 1089 | |
| 1090 | static struct stack_item * |
| 1091 | pop_stack_item (struct stack_item *si) |
| 1092 | { |
| 1093 | struct stack_item *dead = si; |
| 1094 | si = si->prev; |
| 1095 | xfree (dead->data); |
| 1096 | xfree (dead); |
| 1097 | return si; |
| 1098 | } |
| 1099 | |
| 1100 | |
| 1101 | /* Return the alignment (in bytes) of the given type. */ |
| 1102 | |
| 1103 | static int |
| 1104 | arm_type_align (struct type *t) |
| 1105 | { |
| 1106 | int n; |
| 1107 | int align; |
| 1108 | int falign; |
| 1109 | |
| 1110 | t = check_typedef (t); |
| 1111 | switch (TYPE_CODE (t)) |
| 1112 | { |
| 1113 | default: |
| 1114 | /* Should never happen. */ |
| 1115 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); |
| 1116 | return 4; |
| 1117 | |
| 1118 | case TYPE_CODE_PTR: |
| 1119 | case TYPE_CODE_ENUM: |
| 1120 | case TYPE_CODE_INT: |
| 1121 | case TYPE_CODE_FLT: |
| 1122 | case TYPE_CODE_SET: |
| 1123 | case TYPE_CODE_RANGE: |
| 1124 | case TYPE_CODE_BITSTRING: |
| 1125 | case TYPE_CODE_REF: |
| 1126 | case TYPE_CODE_CHAR: |
| 1127 | case TYPE_CODE_BOOL: |
| 1128 | return TYPE_LENGTH (t); |
| 1129 | |
| 1130 | case TYPE_CODE_ARRAY: |
| 1131 | case TYPE_CODE_COMPLEX: |
| 1132 | /* TODO: What about vector types? */ |
| 1133 | return arm_type_align (TYPE_TARGET_TYPE (t)); |
| 1134 | |
| 1135 | case TYPE_CODE_STRUCT: |
| 1136 | case TYPE_CODE_UNION: |
| 1137 | align = 1; |
| 1138 | for (n = 0; n < TYPE_NFIELDS (t); n++) |
| 1139 | { |
| 1140 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); |
| 1141 | if (falign > align) |
| 1142 | align = falign; |
| 1143 | } |
| 1144 | return align; |
| 1145 | } |
| 1146 | } |
| 1147 | |
| 1148 | /* We currently only support passing parameters in integer registers. This |
| 1149 | conforms with GCC's default model. Several other variants exist and |
| 1150 | we should probably support some of them based on the selected ABI. */ |
| 1151 | |
| 1152 | static CORE_ADDR |
| 1153 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1154 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
| 1155 | struct value **args, CORE_ADDR sp, int struct_return, |
| 1156 | CORE_ADDR struct_addr) |
| 1157 | { |
| 1158 | int argnum; |
| 1159 | int argreg; |
| 1160 | int nstack; |
| 1161 | struct stack_item *si = NULL; |
| 1162 | |
| 1163 | /* Set the return address. For the ARM, the return breakpoint is |
| 1164 | always at BP_ADDR. */ |
| 1165 | /* XXX Fix for Thumb. */ |
| 1166 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
| 1167 | |
| 1168 | /* Walk through the list of args and determine how large a temporary |
| 1169 | stack is required. Need to take care here as structs may be |
| 1170 | passed on the stack, and we have to to push them. */ |
| 1171 | nstack = 0; |
| 1172 | |
| 1173 | argreg = ARM_A1_REGNUM; |
| 1174 | nstack = 0; |
| 1175 | |
| 1176 | /* Some platforms require a double-word aligned stack. Make sure sp |
| 1177 | is correctly aligned before we start. We always do this even if |
| 1178 | it isn't really needed -- it can never hurt things. */ |
| 1179 | sp &= ~(CORE_ADDR)(2 * DEPRECATED_REGISTER_SIZE - 1); |
| 1180 | |
| 1181 | /* The struct_return pointer occupies the first parameter |
| 1182 | passing register. */ |
| 1183 | if (struct_return) |
| 1184 | { |
| 1185 | if (arm_debug) |
| 1186 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", |
| 1187 | REGISTER_NAME (argreg), paddr (struct_addr)); |
| 1188 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
| 1189 | argreg++; |
| 1190 | } |
| 1191 | |
| 1192 | for (argnum = 0; argnum < nargs; argnum++) |
| 1193 | { |
| 1194 | int len; |
| 1195 | struct type *arg_type; |
| 1196 | struct type *target_type; |
| 1197 | enum type_code typecode; |
| 1198 | bfd_byte *val; |
| 1199 | int align; |
| 1200 | |
| 1201 | arg_type = check_typedef (value_type (args[argnum])); |
| 1202 | len = TYPE_LENGTH (arg_type); |
| 1203 | target_type = TYPE_TARGET_TYPE (arg_type); |
| 1204 | typecode = TYPE_CODE (arg_type); |
| 1205 | val = value_contents_writeable (args[argnum]); |
| 1206 | |
| 1207 | align = arm_type_align (arg_type); |
| 1208 | /* Round alignment up to a whole number of words. */ |
| 1209 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); |
| 1210 | /* Different ABIs have different maximum alignments. */ |
| 1211 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) |
| 1212 | { |
| 1213 | /* The APCS ABI only requires word alignment. */ |
| 1214 | align = INT_REGISTER_SIZE; |
| 1215 | } |
| 1216 | else |
| 1217 | { |
| 1218 | /* The AAPCS requires at most doubleword alignment. */ |
| 1219 | if (align > INT_REGISTER_SIZE * 2) |
| 1220 | align = INT_REGISTER_SIZE * 2; |
| 1221 | } |
| 1222 | |
| 1223 | /* Push stack padding for dowubleword alignment. */ |
| 1224 | if (nstack & (align - 1)) |
| 1225 | { |
| 1226 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
| 1227 | nstack += INT_REGISTER_SIZE; |
| 1228 | } |
| 1229 | |
| 1230 | /* Doubleword aligned quantities must go in even register pairs. */ |
| 1231 | if (argreg <= ARM_LAST_ARG_REGNUM |
| 1232 | && align > INT_REGISTER_SIZE |
| 1233 | && argreg & 1) |
| 1234 | argreg++; |
| 1235 | |
| 1236 | /* If the argument is a pointer to a function, and it is a |
| 1237 | Thumb function, create a LOCAL copy of the value and set |
| 1238 | the THUMB bit in it. */ |
| 1239 | if (TYPE_CODE_PTR == typecode |
| 1240 | && target_type != NULL |
| 1241 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) |
| 1242 | { |
| 1243 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
| 1244 | if (arm_pc_is_thumb (regval)) |
| 1245 | { |
| 1246 | val = alloca (len); |
| 1247 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
| 1248 | } |
| 1249 | } |
| 1250 | |
| 1251 | /* Copy the argument to general registers or the stack in |
| 1252 | register-sized pieces. Large arguments are split between |
| 1253 | registers and stack. */ |
| 1254 | while (len > 0) |
| 1255 | { |
| 1256 | int partial_len = len < DEPRECATED_REGISTER_SIZE ? len : DEPRECATED_REGISTER_SIZE; |
| 1257 | |
| 1258 | if (argreg <= ARM_LAST_ARG_REGNUM) |
| 1259 | { |
| 1260 | /* The argument is being passed in a general purpose |
| 1261 | register. */ |
| 1262 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
| 1263 | if (arm_debug) |
| 1264 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", |
| 1265 | argnum, REGISTER_NAME (argreg), |
| 1266 | phex (regval, DEPRECATED_REGISTER_SIZE)); |
| 1267 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 1268 | argreg++; |
| 1269 | } |
| 1270 | else |
| 1271 | { |
| 1272 | /* Push the arguments onto the stack. */ |
| 1273 | if (arm_debug) |
| 1274 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", |
| 1275 | argnum, nstack); |
| 1276 | si = push_stack_item (si, val, DEPRECATED_REGISTER_SIZE); |
| 1277 | nstack += DEPRECATED_REGISTER_SIZE; |
| 1278 | } |
| 1279 | |
| 1280 | len -= partial_len; |
| 1281 | val += partial_len; |
| 1282 | } |
| 1283 | } |
| 1284 | /* If we have an odd number of words to push, then decrement the stack |
| 1285 | by one word now, so first stack argument will be dword aligned. */ |
| 1286 | if (nstack & 4) |
| 1287 | sp -= 4; |
| 1288 | |
| 1289 | while (si) |
| 1290 | { |
| 1291 | sp -= si->len; |
| 1292 | write_memory (sp, si->data, si->len); |
| 1293 | si = pop_stack_item (si); |
| 1294 | } |
| 1295 | |
| 1296 | /* Finally, update teh SP register. */ |
| 1297 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); |
| 1298 | |
| 1299 | return sp; |
| 1300 | } |
| 1301 | |
| 1302 | static void |
| 1303 | print_fpu_flags (int flags) |
| 1304 | { |
| 1305 | if (flags & (1 << 0)) |
| 1306 | fputs ("IVO ", stdout); |
| 1307 | if (flags & (1 << 1)) |
| 1308 | fputs ("DVZ ", stdout); |
| 1309 | if (flags & (1 << 2)) |
| 1310 | fputs ("OFL ", stdout); |
| 1311 | if (flags & (1 << 3)) |
| 1312 | fputs ("UFL ", stdout); |
| 1313 | if (flags & (1 << 4)) |
| 1314 | fputs ("INX ", stdout); |
| 1315 | putchar ('\n'); |
| 1316 | } |
| 1317 | |
| 1318 | /* Print interesting information about the floating point processor |
| 1319 | (if present) or emulator. */ |
| 1320 | static void |
| 1321 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 1322 | struct frame_info *frame, const char *args) |
| 1323 | { |
| 1324 | unsigned long status = read_register (ARM_FPS_REGNUM); |
| 1325 | int type; |
| 1326 | |
| 1327 | type = (status >> 24) & 127; |
| 1328 | if (status & (1 << 31)) |
| 1329 | printf (_("Hardware FPU type %d\n"), type); |
| 1330 | else |
| 1331 | printf (_("Software FPU type %d\n"), type); |
| 1332 | /* i18n: [floating point unit] mask */ |
| 1333 | fputs (_("mask: "), stdout); |
| 1334 | print_fpu_flags (status >> 16); |
| 1335 | /* i18n: [floating point unit] flags */ |
| 1336 | fputs (_("flags: "), stdout); |
| 1337 | print_fpu_flags (status); |
| 1338 | } |
| 1339 | |
| 1340 | /* Return the GDB type object for the "standard" data type of data in |
| 1341 | register N. */ |
| 1342 | |
| 1343 | static struct type * |
| 1344 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
| 1345 | { |
| 1346 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
| 1347 | { |
| 1348 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1349 | return builtin_type_arm_ext_big; |
| 1350 | else |
| 1351 | return builtin_type_arm_ext_littlebyte_bigword; |
| 1352 | } |
| 1353 | else |
| 1354 | return builtin_type_int32; |
| 1355 | } |
| 1356 | |
| 1357 | /* Index within `registers' of the first byte of the space for |
| 1358 | register N. */ |
| 1359 | |
| 1360 | static int |
| 1361 | arm_register_byte (int regnum) |
| 1362 | { |
| 1363 | if (regnum < ARM_F0_REGNUM) |
| 1364 | return regnum * INT_REGISTER_SIZE; |
| 1365 | else if (regnum < ARM_PS_REGNUM) |
| 1366 | return (NUM_GREGS * INT_REGISTER_SIZE |
| 1367 | + (regnum - ARM_F0_REGNUM) * FP_REGISTER_SIZE); |
| 1368 | else |
| 1369 | return (NUM_GREGS * INT_REGISTER_SIZE |
| 1370 | + NUM_FREGS * FP_REGISTER_SIZE |
| 1371 | + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE); |
| 1372 | } |
| 1373 | |
| 1374 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
| 1375 | static int |
| 1376 | arm_register_sim_regno (int regnum) |
| 1377 | { |
| 1378 | int reg = regnum; |
| 1379 | gdb_assert (reg >= 0 && reg < NUM_REGS); |
| 1380 | |
| 1381 | if (reg < NUM_GREGS) |
| 1382 | return SIM_ARM_R0_REGNUM + reg; |
| 1383 | reg -= NUM_GREGS; |
| 1384 | |
| 1385 | if (reg < NUM_FREGS) |
| 1386 | return SIM_ARM_FP0_REGNUM + reg; |
| 1387 | reg -= NUM_FREGS; |
| 1388 | |
| 1389 | if (reg < NUM_SREGS) |
| 1390 | return SIM_ARM_FPS_REGNUM + reg; |
| 1391 | reg -= NUM_SREGS; |
| 1392 | |
| 1393 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
| 1394 | } |
| 1395 | |
| 1396 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
| 1397 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. |
| 1398 | It is thought that this is is the floating-point register format on |
| 1399 | little-endian systems. */ |
| 1400 | |
| 1401 | static void |
| 1402 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
| 1403 | void *dbl) |
| 1404 | { |
| 1405 | DOUBLEST d; |
| 1406 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1407 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
| 1408 | else |
| 1409 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 1410 | ptr, &d); |
| 1411 | floatformat_from_doublest (fmt, &d, dbl); |
| 1412 | } |
| 1413 | |
| 1414 | static void |
| 1415 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr) |
| 1416 | { |
| 1417 | DOUBLEST d; |
| 1418 | floatformat_to_doublest (fmt, ptr, &d); |
| 1419 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1420 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
| 1421 | else |
| 1422 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 1423 | &d, dbl); |
| 1424 | } |
| 1425 | |
| 1426 | static int |
| 1427 | condition_true (unsigned long cond, unsigned long status_reg) |
| 1428 | { |
| 1429 | if (cond == INST_AL || cond == INST_NV) |
| 1430 | return 1; |
| 1431 | |
| 1432 | switch (cond) |
| 1433 | { |
| 1434 | case INST_EQ: |
| 1435 | return ((status_reg & FLAG_Z) != 0); |
| 1436 | case INST_NE: |
| 1437 | return ((status_reg & FLAG_Z) == 0); |
| 1438 | case INST_CS: |
| 1439 | return ((status_reg & FLAG_C) != 0); |
| 1440 | case INST_CC: |
| 1441 | return ((status_reg & FLAG_C) == 0); |
| 1442 | case INST_MI: |
| 1443 | return ((status_reg & FLAG_N) != 0); |
| 1444 | case INST_PL: |
| 1445 | return ((status_reg & FLAG_N) == 0); |
| 1446 | case INST_VS: |
| 1447 | return ((status_reg & FLAG_V) != 0); |
| 1448 | case INST_VC: |
| 1449 | return ((status_reg & FLAG_V) == 0); |
| 1450 | case INST_HI: |
| 1451 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); |
| 1452 | case INST_LS: |
| 1453 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); |
| 1454 | case INST_GE: |
| 1455 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); |
| 1456 | case INST_LT: |
| 1457 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); |
| 1458 | case INST_GT: |
| 1459 | return (((status_reg & FLAG_Z) == 0) && |
| 1460 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
| 1461 | case INST_LE: |
| 1462 | return (((status_reg & FLAG_Z) != 0) || |
| 1463 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
| 1464 | } |
| 1465 | return 1; |
| 1466 | } |
| 1467 | |
| 1468 | /* Support routines for single stepping. Calculate the next PC value. */ |
| 1469 | #define submask(x) ((1L << ((x) + 1)) - 1) |
| 1470 | #define bit(obj,st) (((obj) >> (st)) & 1) |
| 1471 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) |
| 1472 | #define sbits(obj,st,fn) \ |
| 1473 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) |
| 1474 | #define BranchDest(addr,instr) \ |
| 1475 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) |
| 1476 | #define ARM_PC_32 1 |
| 1477 | |
| 1478 | static unsigned long |
| 1479 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
| 1480 | unsigned long status_reg) |
| 1481 | { |
| 1482 | unsigned long res, shift; |
| 1483 | int rm = bits (inst, 0, 3); |
| 1484 | unsigned long shifttype = bits (inst, 5, 6); |
| 1485 | |
| 1486 | if (bit (inst, 4)) |
| 1487 | { |
| 1488 | int rs = bits (inst, 8, 11); |
| 1489 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; |
| 1490 | } |
| 1491 | else |
| 1492 | shift = bits (inst, 7, 11); |
| 1493 | |
| 1494 | res = (rm == 15 |
| 1495 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
| 1496 | + (bit (inst, 4) ? 12 : 8)) |
| 1497 | : read_register (rm)); |
| 1498 | |
| 1499 | switch (shifttype) |
| 1500 | { |
| 1501 | case 0: /* LSL */ |
| 1502 | res = shift >= 32 ? 0 : res << shift; |
| 1503 | break; |
| 1504 | |
| 1505 | case 1: /* LSR */ |
| 1506 | res = shift >= 32 ? 0 : res >> shift; |
| 1507 | break; |
| 1508 | |
| 1509 | case 2: /* ASR */ |
| 1510 | if (shift >= 32) |
| 1511 | shift = 31; |
| 1512 | res = ((res & 0x80000000L) |
| 1513 | ? ~((~res) >> shift) : res >> shift); |
| 1514 | break; |
| 1515 | |
| 1516 | case 3: /* ROR/RRX */ |
| 1517 | shift &= 31; |
| 1518 | if (shift == 0) |
| 1519 | res = (res >> 1) | (carry ? 0x80000000L : 0); |
| 1520 | else |
| 1521 | res = (res >> shift) | (res << (32 - shift)); |
| 1522 | break; |
| 1523 | } |
| 1524 | |
| 1525 | return res & 0xffffffff; |
| 1526 | } |
| 1527 | |
| 1528 | /* Return number of 1-bits in VAL. */ |
| 1529 | |
| 1530 | static int |
| 1531 | bitcount (unsigned long val) |
| 1532 | { |
| 1533 | int nbits; |
| 1534 | for (nbits = 0; val != 0; nbits++) |
| 1535 | val &= val - 1; /* delete rightmost 1-bit in val */ |
| 1536 | return nbits; |
| 1537 | } |
| 1538 | |
| 1539 | CORE_ADDR |
| 1540 | thumb_get_next_pc (CORE_ADDR pc) |
| 1541 | { |
| 1542 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
| 1543 | unsigned short inst1 = read_memory_unsigned_integer (pc, 2); |
| 1544 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
| 1545 | unsigned long offset; |
| 1546 | |
| 1547 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
| 1548 | { |
| 1549 | CORE_ADDR sp; |
| 1550 | |
| 1551 | /* Fetch the saved PC from the stack. It's stored above |
| 1552 | all of the other registers. */ |
| 1553 | offset = bitcount (bits (inst1, 0, 7)) * DEPRECATED_REGISTER_SIZE; |
| 1554 | sp = read_register (ARM_SP_REGNUM); |
| 1555 | nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4); |
| 1556 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1557 | if (nextpc == pc) |
| 1558 | error (_("Infinite loop detected")); |
| 1559 | } |
| 1560 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ |
| 1561 | { |
| 1562 | unsigned long status = read_register (ARM_PS_REGNUM); |
| 1563 | unsigned long cond = bits (inst1, 8, 11); |
| 1564 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
| 1565 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
| 1566 | } |
| 1567 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ |
| 1568 | { |
| 1569 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); |
| 1570 | } |
| 1571 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
| 1572 | { |
| 1573 | unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2); |
| 1574 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
| 1575 | nextpc = pc_val + offset; |
| 1576 | /* For BLX make sure to clear the low bits. */ |
| 1577 | if (bits (inst2, 11, 12) == 1) |
| 1578 | nextpc = nextpc & 0xfffffffc; |
| 1579 | } |
| 1580 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
| 1581 | { |
| 1582 | if (bits (inst1, 3, 6) == 0x0f) |
| 1583 | nextpc = pc_val; |
| 1584 | else |
| 1585 | nextpc = read_register (bits (inst1, 3, 6)); |
| 1586 | |
| 1587 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1588 | if (nextpc == pc) |
| 1589 | error (_("Infinite loop detected")); |
| 1590 | } |
| 1591 | |
| 1592 | return nextpc; |
| 1593 | } |
| 1594 | |
| 1595 | CORE_ADDR |
| 1596 | arm_get_next_pc (CORE_ADDR pc) |
| 1597 | { |
| 1598 | unsigned long pc_val; |
| 1599 | unsigned long this_instr; |
| 1600 | unsigned long status; |
| 1601 | CORE_ADDR nextpc; |
| 1602 | |
| 1603 | if (arm_pc_is_thumb (pc)) |
| 1604 | return thumb_get_next_pc (pc); |
| 1605 | |
| 1606 | pc_val = (unsigned long) pc; |
| 1607 | this_instr = read_memory_unsigned_integer (pc, 4); |
| 1608 | status = read_register (ARM_PS_REGNUM); |
| 1609 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
| 1610 | |
| 1611 | if (condition_true (bits (this_instr, 28, 31), status)) |
| 1612 | { |
| 1613 | switch (bits (this_instr, 24, 27)) |
| 1614 | { |
| 1615 | case 0x0: |
| 1616 | case 0x1: /* data processing */ |
| 1617 | case 0x2: |
| 1618 | case 0x3: |
| 1619 | { |
| 1620 | unsigned long operand1, operand2, result = 0; |
| 1621 | unsigned long rn; |
| 1622 | int c; |
| 1623 | |
| 1624 | if (bits (this_instr, 12, 15) != 15) |
| 1625 | break; |
| 1626 | |
| 1627 | if (bits (this_instr, 22, 25) == 0 |
| 1628 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
| 1629 | error (_("Invalid update to pc in instruction")); |
| 1630 | |
| 1631 | /* BX <reg>, BLX <reg> */ |
| 1632 | if (bits (this_instr, 4, 28) == 0x12fff1 |
| 1633 | || bits (this_instr, 4, 28) == 0x12fff3) |
| 1634 | { |
| 1635 | rn = bits (this_instr, 0, 3); |
| 1636 | result = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1637 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); |
| 1638 | |
| 1639 | if (nextpc == pc) |
| 1640 | error (_("Infinite loop detected")); |
| 1641 | |
| 1642 | return nextpc; |
| 1643 | } |
| 1644 | |
| 1645 | /* Multiply into PC */ |
| 1646 | c = (status & FLAG_C) ? 1 : 0; |
| 1647 | rn = bits (this_instr, 16, 19); |
| 1648 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1649 | |
| 1650 | if (bit (this_instr, 25)) |
| 1651 | { |
| 1652 | unsigned long immval = bits (this_instr, 0, 7); |
| 1653 | unsigned long rotate = 2 * bits (this_instr, 8, 11); |
| 1654 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
| 1655 | & 0xffffffff; |
| 1656 | } |
| 1657 | else /* operand 2 is a shifted register */ |
| 1658 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
| 1659 | |
| 1660 | switch (bits (this_instr, 21, 24)) |
| 1661 | { |
| 1662 | case 0x0: /*and */ |
| 1663 | result = operand1 & operand2; |
| 1664 | break; |
| 1665 | |
| 1666 | case 0x1: /*eor */ |
| 1667 | result = operand1 ^ operand2; |
| 1668 | break; |
| 1669 | |
| 1670 | case 0x2: /*sub */ |
| 1671 | result = operand1 - operand2; |
| 1672 | break; |
| 1673 | |
| 1674 | case 0x3: /*rsb */ |
| 1675 | result = operand2 - operand1; |
| 1676 | break; |
| 1677 | |
| 1678 | case 0x4: /*add */ |
| 1679 | result = operand1 + operand2; |
| 1680 | break; |
| 1681 | |
| 1682 | case 0x5: /*adc */ |
| 1683 | result = operand1 + operand2 + c; |
| 1684 | break; |
| 1685 | |
| 1686 | case 0x6: /*sbc */ |
| 1687 | result = operand1 - operand2 + c; |
| 1688 | break; |
| 1689 | |
| 1690 | case 0x7: /*rsc */ |
| 1691 | result = operand2 - operand1 + c; |
| 1692 | break; |
| 1693 | |
| 1694 | case 0x8: |
| 1695 | case 0x9: |
| 1696 | case 0xa: |
| 1697 | case 0xb: /* tst, teq, cmp, cmn */ |
| 1698 | result = (unsigned long) nextpc; |
| 1699 | break; |
| 1700 | |
| 1701 | case 0xc: /*orr */ |
| 1702 | result = operand1 | operand2; |
| 1703 | break; |
| 1704 | |
| 1705 | case 0xd: /*mov */ |
| 1706 | /* Always step into a function. */ |
| 1707 | result = operand2; |
| 1708 | break; |
| 1709 | |
| 1710 | case 0xe: /*bic */ |
| 1711 | result = operand1 & ~operand2; |
| 1712 | break; |
| 1713 | |
| 1714 | case 0xf: /*mvn */ |
| 1715 | result = ~operand2; |
| 1716 | break; |
| 1717 | } |
| 1718 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); |
| 1719 | |
| 1720 | if (nextpc == pc) |
| 1721 | error (_("Infinite loop detected")); |
| 1722 | break; |
| 1723 | } |
| 1724 | |
| 1725 | case 0x4: |
| 1726 | case 0x5: /* data transfer */ |
| 1727 | case 0x6: |
| 1728 | case 0x7: |
| 1729 | if (bit (this_instr, 20)) |
| 1730 | { |
| 1731 | /* load */ |
| 1732 | if (bits (this_instr, 12, 15) == 15) |
| 1733 | { |
| 1734 | /* rd == pc */ |
| 1735 | unsigned long rn; |
| 1736 | unsigned long base; |
| 1737 | |
| 1738 | if (bit (this_instr, 22)) |
| 1739 | error (_("Invalid update to pc in instruction")); |
| 1740 | |
| 1741 | /* byte write to PC */ |
| 1742 | rn = bits (this_instr, 16, 19); |
| 1743 | base = (rn == 15) ? pc_val + 8 : read_register (rn); |
| 1744 | if (bit (this_instr, 24)) |
| 1745 | { |
| 1746 | /* pre-indexed */ |
| 1747 | int c = (status & FLAG_C) ? 1 : 0; |
| 1748 | unsigned long offset = |
| 1749 | (bit (this_instr, 25) |
| 1750 | ? shifted_reg_val (this_instr, c, pc_val, status) |
| 1751 | : bits (this_instr, 0, 11)); |
| 1752 | |
| 1753 | if (bit (this_instr, 23)) |
| 1754 | base += offset; |
| 1755 | else |
| 1756 | base -= offset; |
| 1757 | } |
| 1758 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
| 1759 | 4); |
| 1760 | |
| 1761 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1762 | |
| 1763 | if (nextpc == pc) |
| 1764 | error (_("Infinite loop detected")); |
| 1765 | } |
| 1766 | } |
| 1767 | break; |
| 1768 | |
| 1769 | case 0x8: |
| 1770 | case 0x9: /* block transfer */ |
| 1771 | if (bit (this_instr, 20)) |
| 1772 | { |
| 1773 | /* LDM */ |
| 1774 | if (bit (this_instr, 15)) |
| 1775 | { |
| 1776 | /* loading pc */ |
| 1777 | int offset = 0; |
| 1778 | |
| 1779 | if (bit (this_instr, 23)) |
| 1780 | { |
| 1781 | /* up */ |
| 1782 | unsigned long reglist = bits (this_instr, 0, 14); |
| 1783 | offset = bitcount (reglist) * 4; |
| 1784 | if (bit (this_instr, 24)) /* pre */ |
| 1785 | offset += 4; |
| 1786 | } |
| 1787 | else if (bit (this_instr, 24)) |
| 1788 | offset = -4; |
| 1789 | |
| 1790 | { |
| 1791 | unsigned long rn_val = |
| 1792 | read_register (bits (this_instr, 16, 19)); |
| 1793 | nextpc = |
| 1794 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val |
| 1795 | + offset), |
| 1796 | 4); |
| 1797 | } |
| 1798 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1799 | if (nextpc == pc) |
| 1800 | error (_("Infinite loop detected")); |
| 1801 | } |
| 1802 | } |
| 1803 | break; |
| 1804 | |
| 1805 | case 0xb: /* branch & link */ |
| 1806 | case 0xa: /* branch */ |
| 1807 | { |
| 1808 | nextpc = BranchDest (pc, this_instr); |
| 1809 | |
| 1810 | /* BLX */ |
| 1811 | if (bits (this_instr, 28, 31) == INST_NV) |
| 1812 | nextpc |= bit (this_instr, 24) << 1; |
| 1813 | |
| 1814 | nextpc = ADDR_BITS_REMOVE (nextpc); |
| 1815 | if (nextpc == pc) |
| 1816 | error (_("Infinite loop detected")); |
| 1817 | break; |
| 1818 | } |
| 1819 | |
| 1820 | case 0xc: |
| 1821 | case 0xd: |
| 1822 | case 0xe: /* coproc ops */ |
| 1823 | case 0xf: /* SWI */ |
| 1824 | break; |
| 1825 | |
| 1826 | default: |
| 1827 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
| 1828 | return (pc); |
| 1829 | } |
| 1830 | } |
| 1831 | |
| 1832 | return nextpc; |
| 1833 | } |
| 1834 | |
| 1835 | /* single_step() is called just before we want to resume the inferior, |
| 1836 | if we want to single-step it but there is no hardware or kernel |
| 1837 | single-step support. We find the target of the coming instruction |
| 1838 | and breakpoint it. |
| 1839 | |
| 1840 | single_step() is also called just after the inferior stops. If we |
| 1841 | had set up a simulated single-step, we undo our damage. */ |
| 1842 | |
| 1843 | static void |
| 1844 | arm_software_single_step (enum target_signal sig, int insert_bpt) |
| 1845 | { |
| 1846 | static int next_pc; /* State between setting and unsetting. */ |
| 1847 | static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */ |
| 1848 | |
| 1849 | if (insert_bpt) |
| 1850 | { |
| 1851 | next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM)); |
| 1852 | target_insert_breakpoint (next_pc, break_mem); |
| 1853 | } |
| 1854 | else |
| 1855 | target_remove_breakpoint (next_pc, break_mem); |
| 1856 | } |
| 1857 | |
| 1858 | #include "bfd-in2.h" |
| 1859 | #include "libcoff.h" |
| 1860 | |
| 1861 | static int |
| 1862 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
| 1863 | { |
| 1864 | if (arm_pc_is_thumb (memaddr)) |
| 1865 | { |
| 1866 | static asymbol *asym; |
| 1867 | static combined_entry_type ce; |
| 1868 | static struct coff_symbol_struct csym; |
| 1869 | static struct bfd fake_bfd; |
| 1870 | static bfd_target fake_target; |
| 1871 | |
| 1872 | if (csym.native == NULL) |
| 1873 | { |
| 1874 | /* Create a fake symbol vector containing a Thumb symbol. |
| 1875 | This is solely so that the code in print_insn_little_arm() |
| 1876 | and print_insn_big_arm() in opcodes/arm-dis.c will detect |
| 1877 | the presence of a Thumb symbol and switch to decoding |
| 1878 | Thumb instructions. */ |
| 1879 | |
| 1880 | fake_target.flavour = bfd_target_coff_flavour; |
| 1881 | fake_bfd.xvec = &fake_target; |
| 1882 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
| 1883 | csym.native = &ce; |
| 1884 | csym.symbol.the_bfd = &fake_bfd; |
| 1885 | csym.symbol.name = "fake"; |
| 1886 | asym = (asymbol *) & csym; |
| 1887 | } |
| 1888 | |
| 1889 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
| 1890 | info->symbols = &asym; |
| 1891 | } |
| 1892 | else |
| 1893 | info->symbols = NULL; |
| 1894 | |
| 1895 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 1896 | return print_insn_big_arm (memaddr, info); |
| 1897 | else |
| 1898 | return print_insn_little_arm (memaddr, info); |
| 1899 | } |
| 1900 | |
| 1901 | /* The following define instruction sequences that will cause ARM |
| 1902 | cpu's to take an undefined instruction trap. These are used to |
| 1903 | signal a breakpoint to GDB. |
| 1904 | |
| 1905 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb |
| 1906 | modes. A different instruction is required for each mode. The ARM |
| 1907 | cpu's can also be big or little endian. Thus four different |
| 1908 | instructions are needed to support all cases. |
| 1909 | |
| 1910 | Note: ARMv4 defines several new instructions that will take the |
| 1911 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does |
| 1912 | not in fact add the new instructions. The new undefined |
| 1913 | instructions in ARMv4 are all instructions that had no defined |
| 1914 | behaviour in earlier chips. There is no guarantee that they will |
| 1915 | raise an exception, but may be treated as NOP's. In practice, it |
| 1916 | may only safe to rely on instructions matching: |
| 1917 | |
| 1918 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
| 1919 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
| 1920 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x |
| 1921 | |
| 1922 | Even this may only true if the condition predicate is true. The |
| 1923 | following use a condition predicate of ALWAYS so it is always TRUE. |
| 1924 | |
| 1925 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, |
| 1926 | and NetBSD all use a software interrupt rather than an undefined |
| 1927 | instruction to force a trap. This can be handled by by the |
| 1928 | abi-specific code during establishment of the gdbarch vector. */ |
| 1929 | |
| 1930 | |
| 1931 | /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to |
| 1932 | override these definitions. */ |
| 1933 | #ifndef ARM_LE_BREAKPOINT |
| 1934 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} |
| 1935 | #endif |
| 1936 | #ifndef ARM_BE_BREAKPOINT |
| 1937 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} |
| 1938 | #endif |
| 1939 | #ifndef THUMB_LE_BREAKPOINT |
| 1940 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} |
| 1941 | #endif |
| 1942 | #ifndef THUMB_BE_BREAKPOINT |
| 1943 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} |
| 1944 | #endif |
| 1945 | |
| 1946 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
| 1947 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; |
| 1948 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; |
| 1949 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; |
| 1950 | |
| 1951 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
| 1952 | the program counter value to determine whether a 16-bit or 32-bit |
| 1953 | breakpoint should be used. It returns a pointer to a string of |
| 1954 | bytes that encode a breakpoint instruction, stores the length of |
| 1955 | the string to *lenptr, and adjusts the program counter (if |
| 1956 | necessary) to point to the actual memory location where the |
| 1957 | breakpoint should be inserted. */ |
| 1958 | |
| 1959 | /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting |
| 1960 | breakpoints and storing their handles instread of what was in |
| 1961 | memory. It is nice that this is the same size as a handle - |
| 1962 | otherwise remote-rdp will have to change. */ |
| 1963 | |
| 1964 | static const unsigned char * |
| 1965 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
| 1966 | { |
| 1967 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 1968 | |
| 1969 | if (arm_pc_is_thumb (*pcptr)) |
| 1970 | { |
| 1971 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
| 1972 | *lenptr = tdep->thumb_breakpoint_size; |
| 1973 | return tdep->thumb_breakpoint; |
| 1974 | } |
| 1975 | else |
| 1976 | { |
| 1977 | *lenptr = tdep->arm_breakpoint_size; |
| 1978 | return tdep->arm_breakpoint; |
| 1979 | } |
| 1980 | } |
| 1981 | |
| 1982 | /* Extract from an array REGBUF containing the (raw) register state a |
| 1983 | function return value of type TYPE, and copy that, in virtual |
| 1984 | format, into VALBUF. */ |
| 1985 | |
| 1986 | static void |
| 1987 | arm_extract_return_value (struct type *type, struct regcache *regs, |
| 1988 | gdb_byte *valbuf) |
| 1989 | { |
| 1990 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
| 1991 | { |
| 1992 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
| 1993 | { |
| 1994 | case ARM_FLOAT_FPA: |
| 1995 | { |
| 1996 | /* The value is in register F0 in internal format. We need to |
| 1997 | extract the raw value and then convert it to the desired |
| 1998 | internal type. */ |
| 1999 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
| 2000 | |
| 2001 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); |
| 2002 | convert_from_extended (floatformat_from_type (type), tmpbuf, |
| 2003 | valbuf); |
| 2004 | } |
| 2005 | break; |
| 2006 | |
| 2007 | case ARM_FLOAT_SOFT_FPA: |
| 2008 | case ARM_FLOAT_SOFT_VFP: |
| 2009 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
| 2010 | if (TYPE_LENGTH (type) > 4) |
| 2011 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, |
| 2012 | valbuf + INT_REGISTER_SIZE); |
| 2013 | break; |
| 2014 | |
| 2015 | default: |
| 2016 | internal_error |
| 2017 | (__FILE__, __LINE__, |
| 2018 | _("arm_extract_return_value: Floating point model not supported")); |
| 2019 | break; |
| 2020 | } |
| 2021 | } |
| 2022 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 2023 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 2024 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 2025 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 2026 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 2027 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 2028 | { |
| 2029 | /* If the the type is a plain integer, then the access is |
| 2030 | straight-forward. Otherwise we have to play around a bit more. */ |
| 2031 | int len = TYPE_LENGTH (type); |
| 2032 | int regno = ARM_A1_REGNUM; |
| 2033 | ULONGEST tmp; |
| 2034 | |
| 2035 | while (len > 0) |
| 2036 | { |
| 2037 | /* By using store_unsigned_integer we avoid having to do |
| 2038 | anything special for small big-endian values. */ |
| 2039 | regcache_cooked_read_unsigned (regs, regno++, &tmp); |
| 2040 | store_unsigned_integer (valbuf, |
| 2041 | (len > INT_REGISTER_SIZE |
| 2042 | ? INT_REGISTER_SIZE : len), |
| 2043 | tmp); |
| 2044 | len -= INT_REGISTER_SIZE; |
| 2045 | valbuf += INT_REGISTER_SIZE; |
| 2046 | } |
| 2047 | } |
| 2048 | else |
| 2049 | { |
| 2050 | /* For a structure or union the behaviour is as if the value had |
| 2051 | been stored to word-aligned memory and then loaded into |
| 2052 | registers with 32-bit load instruction(s). */ |
| 2053 | int len = TYPE_LENGTH (type); |
| 2054 | int regno = ARM_A1_REGNUM; |
| 2055 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 2056 | |
| 2057 | while (len > 0) |
| 2058 | { |
| 2059 | regcache_cooked_read (regs, regno++, tmpbuf); |
| 2060 | memcpy (valbuf, tmpbuf, |
| 2061 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
| 2062 | len -= INT_REGISTER_SIZE; |
| 2063 | valbuf += INT_REGISTER_SIZE; |
| 2064 | } |
| 2065 | } |
| 2066 | } |
| 2067 | |
| 2068 | |
| 2069 | /* Will a function return an aggregate type in memory or in a |
| 2070 | register? Return 0 if an aggregate type can be returned in a |
| 2071 | register, 1 if it must be returned in memory. */ |
| 2072 | |
| 2073 | static int |
| 2074 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
| 2075 | { |
| 2076 | int nRc; |
| 2077 | enum type_code code; |
| 2078 | |
| 2079 | CHECK_TYPEDEF (type); |
| 2080 | |
| 2081 | /* In the ARM ABI, "integer" like aggregate types are returned in |
| 2082 | registers. For an aggregate type to be integer like, its size |
| 2083 | must be less than or equal to DEPRECATED_REGISTER_SIZE and the |
| 2084 | offset of each addressable subfield must be zero. Note that bit |
| 2085 | fields are not addressable, and all addressable subfields of |
| 2086 | unions always start at offset zero. |
| 2087 | |
| 2088 | This function is based on the behaviour of GCC 2.95.1. |
| 2089 | See: gcc/arm.c: arm_return_in_memory() for details. |
| 2090 | |
| 2091 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
| 2092 | parameters correctly for a function returning the following |
| 2093 | structure: struct { float f;}; This should be returned in memory, |
| 2094 | not a register. Richard Earnshaw sent me a patch, but I do not |
| 2095 | know of any way to detect if a function like the above has been |
| 2096 | compiled with the correct calling convention. */ |
| 2097 | |
| 2098 | /* All aggregate types that won't fit in a register must be returned |
| 2099 | in memory. */ |
| 2100 | if (TYPE_LENGTH (type) > DEPRECATED_REGISTER_SIZE) |
| 2101 | { |
| 2102 | return 1; |
| 2103 | } |
| 2104 | |
| 2105 | /* The AAPCS says all aggregates not larger than a word are returned |
| 2106 | in a register. */ |
| 2107 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) |
| 2108 | return 0; |
| 2109 | |
| 2110 | /* The only aggregate types that can be returned in a register are |
| 2111 | structs and unions. Arrays must be returned in memory. */ |
| 2112 | code = TYPE_CODE (type); |
| 2113 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) |
| 2114 | { |
| 2115 | return 1; |
| 2116 | } |
| 2117 | |
| 2118 | /* Assume all other aggregate types can be returned in a register. |
| 2119 | Run a check for structures, unions and arrays. */ |
| 2120 | nRc = 0; |
| 2121 | |
| 2122 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
| 2123 | { |
| 2124 | int i; |
| 2125 | /* Need to check if this struct/union is "integer" like. For |
| 2126 | this to be true, its size must be less than or equal to |
| 2127 | DEPRECATED_REGISTER_SIZE and the offset of each addressable |
| 2128 | subfield must be zero. Note that bit fields are not |
| 2129 | addressable, and unions always start at offset zero. If any |
| 2130 | of the subfields is a floating point type, the struct/union |
| 2131 | cannot be an integer type. */ |
| 2132 | |
| 2133 | /* For each field in the object, check: |
| 2134 | 1) Is it FP? --> yes, nRc = 1; |
| 2135 | 2) Is it addressable (bitpos != 0) and |
| 2136 | not packed (bitsize == 0)? |
| 2137 | --> yes, nRc = 1 |
| 2138 | */ |
| 2139 | |
| 2140 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 2141 | { |
| 2142 | enum type_code field_type_code; |
| 2143 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
| 2144 | |
| 2145 | /* Is it a floating point type field? */ |
| 2146 | if (field_type_code == TYPE_CODE_FLT) |
| 2147 | { |
| 2148 | nRc = 1; |
| 2149 | break; |
| 2150 | } |
| 2151 | |
| 2152 | /* If bitpos != 0, then we have to care about it. */ |
| 2153 | if (TYPE_FIELD_BITPOS (type, i) != 0) |
| 2154 | { |
| 2155 | /* Bitfields are not addressable. If the field bitsize is |
| 2156 | zero, then the field is not packed. Hence it cannot be |
| 2157 | a bitfield or any other packed type. */ |
| 2158 | if (TYPE_FIELD_BITSIZE (type, i) == 0) |
| 2159 | { |
| 2160 | nRc = 1; |
| 2161 | break; |
| 2162 | } |
| 2163 | } |
| 2164 | } |
| 2165 | } |
| 2166 | |
| 2167 | return nRc; |
| 2168 | } |
| 2169 | |
| 2170 | /* Write into appropriate registers a function return value of type |
| 2171 | TYPE, given in virtual format. */ |
| 2172 | |
| 2173 | static void |
| 2174 | arm_store_return_value (struct type *type, struct regcache *regs, |
| 2175 | const gdb_byte *valbuf) |
| 2176 | { |
| 2177 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 2178 | { |
| 2179 | char buf[MAX_REGISTER_SIZE]; |
| 2180 | |
| 2181 | switch (gdbarch_tdep (current_gdbarch)->fp_model) |
| 2182 | { |
| 2183 | case ARM_FLOAT_FPA: |
| 2184 | |
| 2185 | convert_to_extended (floatformat_from_type (type), buf, valbuf); |
| 2186 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
| 2187 | break; |
| 2188 | |
| 2189 | case ARM_FLOAT_SOFT_FPA: |
| 2190 | case ARM_FLOAT_SOFT_VFP: |
| 2191 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
| 2192 | if (TYPE_LENGTH (type) > 4) |
| 2193 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, |
| 2194 | valbuf + INT_REGISTER_SIZE); |
| 2195 | break; |
| 2196 | |
| 2197 | default: |
| 2198 | internal_error |
| 2199 | (__FILE__, __LINE__, |
| 2200 | _("arm_store_return_value: Floating point model not supported")); |
| 2201 | break; |
| 2202 | } |
| 2203 | } |
| 2204 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 2205 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 2206 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 2207 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 2208 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 2209 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 2210 | { |
| 2211 | if (TYPE_LENGTH (type) <= 4) |
| 2212 | { |
| 2213 | /* Values of one word or less are zero/sign-extended and |
| 2214 | returned in r0. */ |
| 2215 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 2216 | LONGEST val = unpack_long (type, valbuf); |
| 2217 | |
| 2218 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
| 2219 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
| 2220 | } |
| 2221 | else |
| 2222 | { |
| 2223 | /* Integral values greater than one word are stored in consecutive |
| 2224 | registers starting with r0. This will always be a multiple of |
| 2225 | the regiser size. */ |
| 2226 | int len = TYPE_LENGTH (type); |
| 2227 | int regno = ARM_A1_REGNUM; |
| 2228 | |
| 2229 | while (len > 0) |
| 2230 | { |
| 2231 | regcache_cooked_write (regs, regno++, valbuf); |
| 2232 | len -= INT_REGISTER_SIZE; |
| 2233 | valbuf += INT_REGISTER_SIZE; |
| 2234 | } |
| 2235 | } |
| 2236 | } |
| 2237 | else |
| 2238 | { |
| 2239 | /* For a structure or union the behaviour is as if the value had |
| 2240 | been stored to word-aligned memory and then loaded into |
| 2241 | registers with 32-bit load instruction(s). */ |
| 2242 | int len = TYPE_LENGTH (type); |
| 2243 | int regno = ARM_A1_REGNUM; |
| 2244 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 2245 | |
| 2246 | while (len > 0) |
| 2247 | { |
| 2248 | memcpy (tmpbuf, valbuf, |
| 2249 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
| 2250 | regcache_cooked_write (regs, regno++, tmpbuf); |
| 2251 | len -= INT_REGISTER_SIZE; |
| 2252 | valbuf += INT_REGISTER_SIZE; |
| 2253 | } |
| 2254 | } |
| 2255 | } |
| 2256 | |
| 2257 | |
| 2258 | /* Handle function return values. */ |
| 2259 | |
| 2260 | static enum return_value_convention |
| 2261 | arm_return_value (struct gdbarch *gdbarch, struct type *valtype, |
| 2262 | struct regcache *regcache, gdb_byte *readbuf, |
| 2263 | const gdb_byte *writebuf) |
| 2264 | { |
| 2265 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
| 2266 | || TYPE_CODE (valtype) == TYPE_CODE_UNION |
| 2267 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) |
| 2268 | { |
| 2269 | if (arm_return_in_memory (gdbarch, valtype)) |
| 2270 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 2271 | } |
| 2272 | |
| 2273 | if (writebuf) |
| 2274 | arm_store_return_value (valtype, regcache, writebuf); |
| 2275 | |
| 2276 | if (readbuf) |
| 2277 | arm_extract_return_value (valtype, regcache, readbuf); |
| 2278 | |
| 2279 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 2280 | } |
| 2281 | |
| 2282 | |
| 2283 | static int |
| 2284 | arm_get_longjmp_target (CORE_ADDR *pc) |
| 2285 | { |
| 2286 | CORE_ADDR jb_addr; |
| 2287 | char buf[INT_REGISTER_SIZE]; |
| 2288 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2289 | |
| 2290 | jb_addr = read_register (ARM_A1_REGNUM); |
| 2291 | |
| 2292 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, |
| 2293 | INT_REGISTER_SIZE)) |
| 2294 | return 0; |
| 2295 | |
| 2296 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
| 2297 | return 1; |
| 2298 | } |
| 2299 | |
| 2300 | /* Return non-zero if the PC is inside a thumb call thunk. */ |
| 2301 | |
| 2302 | int |
| 2303 | arm_in_call_stub (CORE_ADDR pc, char *name) |
| 2304 | { |
| 2305 | CORE_ADDR start_addr; |
| 2306 | |
| 2307 | /* Find the starting address of the function containing the PC. If |
| 2308 | the caller didn't give us a name, look it up at the same time. */ |
| 2309 | if (0 == find_pc_partial_function (pc, name ? NULL : &name, |
| 2310 | &start_addr, NULL)) |
| 2311 | return 0; |
| 2312 | |
| 2313 | return strncmp (name, "_call_via_r", 11) == 0; |
| 2314 | } |
| 2315 | |
| 2316 | /* If PC is in a Thumb call or return stub, return the address of the |
| 2317 | target PC, which is in a register. The thunk functions are called |
| 2318 | _called_via_xx, where x is the register name. The possible names |
| 2319 | are r0-r9, sl, fp, ip, sp, and lr. */ |
| 2320 | |
| 2321 | CORE_ADDR |
| 2322 | arm_skip_stub (CORE_ADDR pc) |
| 2323 | { |
| 2324 | char *name; |
| 2325 | CORE_ADDR start_addr; |
| 2326 | |
| 2327 | /* Find the starting address and name of the function containing the PC. */ |
| 2328 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 2329 | return 0; |
| 2330 | |
| 2331 | /* Call thunks always start with "_call_via_". */ |
| 2332 | if (strncmp (name, "_call_via_", 10) == 0) |
| 2333 | { |
| 2334 | /* Use the name suffix to determine which register contains the |
| 2335 | target PC. */ |
| 2336 | static char *table[15] = |
| 2337 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 2338 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" |
| 2339 | }; |
| 2340 | int regno; |
| 2341 | |
| 2342 | for (regno = 0; regno <= 14; regno++) |
| 2343 | if (strcmp (&name[10], table[regno]) == 0) |
| 2344 | return read_register (regno); |
| 2345 | } |
| 2346 | |
| 2347 | return 0; /* not a stub */ |
| 2348 | } |
| 2349 | |
| 2350 | static void |
| 2351 | set_arm_command (char *args, int from_tty) |
| 2352 | { |
| 2353 | printf_unfiltered (_("\ |
| 2354 | \"set arm\" must be followed by an apporpriate subcommand.\n")); |
| 2355 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
| 2356 | } |
| 2357 | |
| 2358 | static void |
| 2359 | show_arm_command (char *args, int from_tty) |
| 2360 | { |
| 2361 | cmd_show_list (showarmcmdlist, from_tty, ""); |
| 2362 | } |
| 2363 | |
| 2364 | static void |
| 2365 | arm_update_current_architecture (void) |
| 2366 | { |
| 2367 | struct gdbarch_info info; |
| 2368 | |
| 2369 | /* If the current architecture is not ARM, we have nothing to do. */ |
| 2370 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_arm) |
| 2371 | return; |
| 2372 | |
| 2373 | /* Update the architecture. */ |
| 2374 | gdbarch_info_init (&info); |
| 2375 | |
| 2376 | if (!gdbarch_update_p (info)) |
| 2377 | internal_error (__FILE__, __LINE__, "could not update architecture"); |
| 2378 | } |
| 2379 | |
| 2380 | static void |
| 2381 | set_fp_model_sfunc (char *args, int from_tty, |
| 2382 | struct cmd_list_element *c) |
| 2383 | { |
| 2384 | enum arm_float_model fp_model; |
| 2385 | |
| 2386 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) |
| 2387 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) |
| 2388 | { |
| 2389 | arm_fp_model = fp_model; |
| 2390 | break; |
| 2391 | } |
| 2392 | |
| 2393 | if (fp_model == ARM_FLOAT_LAST) |
| 2394 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
| 2395 | current_fp_model); |
| 2396 | |
| 2397 | arm_update_current_architecture (); |
| 2398 | } |
| 2399 | |
| 2400 | static void |
| 2401 | show_fp_model (struct ui_file *file, int from_tty, |
| 2402 | struct cmd_list_element *c, const char *value) |
| 2403 | { |
| 2404 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2405 | |
| 2406 | if (arm_fp_model == ARM_FLOAT_AUTO |
| 2407 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
| 2408 | fprintf_filtered (file, _("\ |
| 2409 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), |
| 2410 | fp_model_strings[tdep->fp_model]); |
| 2411 | else |
| 2412 | fprintf_filtered (file, _("\ |
| 2413 | The current ARM floating point model is \"%s\".\n"), |
| 2414 | fp_model_strings[arm_fp_model]); |
| 2415 | } |
| 2416 | |
| 2417 | static void |
| 2418 | arm_set_abi (char *args, int from_tty, |
| 2419 | struct cmd_list_element *c) |
| 2420 | { |
| 2421 | enum arm_abi_kind arm_abi; |
| 2422 | |
| 2423 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) |
| 2424 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) |
| 2425 | { |
| 2426 | arm_abi_global = arm_abi; |
| 2427 | break; |
| 2428 | } |
| 2429 | |
| 2430 | if (arm_abi == ARM_ABI_LAST) |
| 2431 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), |
| 2432 | arm_abi_string); |
| 2433 | |
| 2434 | arm_update_current_architecture (); |
| 2435 | } |
| 2436 | |
| 2437 | static void |
| 2438 | arm_show_abi (struct ui_file *file, int from_tty, |
| 2439 | struct cmd_list_element *c, const char *value) |
| 2440 | { |
| 2441 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2442 | |
| 2443 | if (arm_abi_global == ARM_ABI_AUTO |
| 2444 | && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm) |
| 2445 | fprintf_filtered (file, _("\ |
| 2446 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), |
| 2447 | arm_abi_strings[tdep->arm_abi]); |
| 2448 | else |
| 2449 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), |
| 2450 | arm_abi_string); |
| 2451 | } |
| 2452 | |
| 2453 | /* If the user changes the register disassembly style used for info |
| 2454 | register and other commands, we have to also switch the style used |
| 2455 | in opcodes for disassembly output. This function is run in the "set |
| 2456 | arm disassembly" command, and does that. */ |
| 2457 | |
| 2458 | static void |
| 2459 | set_disassembly_style_sfunc (char *args, int from_tty, |
| 2460 | struct cmd_list_element *c) |
| 2461 | { |
| 2462 | set_disassembly_style (); |
| 2463 | } |
| 2464 | \f |
| 2465 | /* Return the ARM register name corresponding to register I. */ |
| 2466 | static const char * |
| 2467 | arm_register_name (int i) |
| 2468 | { |
| 2469 | return arm_register_names[i]; |
| 2470 | } |
| 2471 | |
| 2472 | static void |
| 2473 | set_disassembly_style (void) |
| 2474 | { |
| 2475 | const char *setname, *setdesc, *const *regnames; |
| 2476 | int numregs, j; |
| 2477 | |
| 2478 | /* Find the style that the user wants in the opcodes table. */ |
| 2479 | int current = 0; |
| 2480 | numregs = get_arm_regnames (current, &setname, &setdesc, ®names); |
| 2481 | while ((disassembly_style != setname) |
| 2482 | && (current < num_disassembly_options)) |
| 2483 | get_arm_regnames (++current, &setname, &setdesc, ®names); |
| 2484 | current_option = current; |
| 2485 | |
| 2486 | /* Fill our copy. */ |
| 2487 | for (j = 0; j < numregs; j++) |
| 2488 | arm_register_names[j] = (char *) regnames[j]; |
| 2489 | |
| 2490 | /* Adjust case. */ |
| 2491 | if (isupper (*regnames[ARM_PC_REGNUM])) |
| 2492 | { |
| 2493 | arm_register_names[ARM_FPS_REGNUM] = "FPS"; |
| 2494 | arm_register_names[ARM_PS_REGNUM] = "CPSR"; |
| 2495 | } |
| 2496 | else |
| 2497 | { |
| 2498 | arm_register_names[ARM_FPS_REGNUM] = "fps"; |
| 2499 | arm_register_names[ARM_PS_REGNUM] = "cpsr"; |
| 2500 | } |
| 2501 | |
| 2502 | /* Synchronize the disassembler. */ |
| 2503 | set_arm_regname_option (current); |
| 2504 | } |
| 2505 | |
| 2506 | /* Test whether the coff symbol specific value corresponds to a Thumb |
| 2507 | function. */ |
| 2508 | |
| 2509 | static int |
| 2510 | coff_sym_is_thumb (int val) |
| 2511 | { |
| 2512 | return (val == C_THUMBEXT || |
| 2513 | val == C_THUMBSTAT || |
| 2514 | val == C_THUMBEXTFUNC || |
| 2515 | val == C_THUMBSTATFUNC || |
| 2516 | val == C_THUMBLABEL); |
| 2517 | } |
| 2518 | |
| 2519 | /* arm_coff_make_msymbol_special() |
| 2520 | arm_elf_make_msymbol_special() |
| 2521 | |
| 2522 | These functions test whether the COFF or ELF symbol corresponds to |
| 2523 | an address in thumb code, and set a "special" bit in a minimal |
| 2524 | symbol to indicate that it does. */ |
| 2525 | |
| 2526 | static void |
| 2527 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
| 2528 | { |
| 2529 | /* Thumb symbols are of type STT_LOPROC, (synonymous with |
| 2530 | STT_ARM_TFUNC). */ |
| 2531 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) |
| 2532 | == STT_LOPROC) |
| 2533 | MSYMBOL_SET_SPECIAL (msym); |
| 2534 | } |
| 2535 | |
| 2536 | static void |
| 2537 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
| 2538 | { |
| 2539 | if (coff_sym_is_thumb (val)) |
| 2540 | MSYMBOL_SET_SPECIAL (msym); |
| 2541 | } |
| 2542 | |
| 2543 | static void |
| 2544 | arm_write_pc (CORE_ADDR pc, ptid_t ptid) |
| 2545 | { |
| 2546 | write_register_pid (ARM_PC_REGNUM, pc, ptid); |
| 2547 | |
| 2548 | /* If necessary, set the T bit. */ |
| 2549 | if (arm_apcs_32) |
| 2550 | { |
| 2551 | CORE_ADDR val = read_register_pid (ARM_PS_REGNUM, ptid); |
| 2552 | if (arm_pc_is_thumb (pc)) |
| 2553 | write_register_pid (ARM_PS_REGNUM, val | 0x20, ptid); |
| 2554 | else |
| 2555 | write_register_pid (ARM_PS_REGNUM, val & ~(CORE_ADDR) 0x20, ptid); |
| 2556 | } |
| 2557 | } |
| 2558 | \f |
| 2559 | static enum gdb_osabi |
| 2560 | arm_elf_osabi_sniffer (bfd *abfd) |
| 2561 | { |
| 2562 | unsigned int elfosabi; |
| 2563 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
| 2564 | |
| 2565 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
| 2566 | |
| 2567 | if (elfosabi == ELFOSABI_ARM) |
| 2568 | /* GNU tools use this value. Check note sections in this case, |
| 2569 | as well. */ |
| 2570 | bfd_map_over_sections (abfd, |
| 2571 | generic_elf_osabi_sniff_abi_tag_sections, |
| 2572 | &osabi); |
| 2573 | |
| 2574 | /* Anything else will be handled by the generic ELF sniffer. */ |
| 2575 | return osabi; |
| 2576 | } |
| 2577 | |
| 2578 | \f |
| 2579 | /* Initialize the current architecture based on INFO. If possible, |
| 2580 | re-use an architecture from ARCHES, which is a list of |
| 2581 | architectures already created during this debugging session. |
| 2582 | |
| 2583 | Called e.g. at program startup, when reading a core file, and when |
| 2584 | reading a binary file. */ |
| 2585 | |
| 2586 | static struct gdbarch * |
| 2587 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 2588 | { |
| 2589 | struct gdbarch_tdep *tdep; |
| 2590 | struct gdbarch *gdbarch; |
| 2591 | struct gdbarch_list *best_arch; |
| 2592 | enum arm_abi_kind arm_abi = arm_abi_global; |
| 2593 | enum arm_float_model fp_model = arm_fp_model; |
| 2594 | |
| 2595 | /* If we have an object to base this architecture on, try to determine |
| 2596 | its ABI. */ |
| 2597 | |
| 2598 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
| 2599 | { |
| 2600 | int ei_osabi; |
| 2601 | |
| 2602 | switch (bfd_get_flavour (info.abfd)) |
| 2603 | { |
| 2604 | case bfd_target_aout_flavour: |
| 2605 | /* Assume it's an old APCS-style ABI. */ |
| 2606 | arm_abi = ARM_ABI_APCS; |
| 2607 | break; |
| 2608 | |
| 2609 | case bfd_target_coff_flavour: |
| 2610 | /* Assume it's an old APCS-style ABI. */ |
| 2611 | /* XXX WinCE? */ |
| 2612 | arm_abi = ARM_ABI_APCS; |
| 2613 | break; |
| 2614 | |
| 2615 | case bfd_target_elf_flavour: |
| 2616 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; |
| 2617 | if (ei_osabi == ELFOSABI_ARM) |
| 2618 | { |
| 2619 | /* GNU tools used to use this value, but do not for EABI |
| 2620 | objects. There's nowhere to tag an EABI version anyway, |
| 2621 | so assume APCS. */ |
| 2622 | arm_abi = ARM_ABI_APCS; |
| 2623 | } |
| 2624 | else if (ei_osabi == ELFOSABI_NONE) |
| 2625 | { |
| 2626 | int e_flags, eabi_ver; |
| 2627 | |
| 2628 | e_flags = elf_elfheader (info.abfd)->e_flags; |
| 2629 | eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
| 2630 | |
| 2631 | switch (eabi_ver) |
| 2632 | { |
| 2633 | case EF_ARM_EABI_UNKNOWN: |
| 2634 | /* Assume GNU tools. */ |
| 2635 | arm_abi = ARM_ABI_APCS; |
| 2636 | break; |
| 2637 | |
| 2638 | case EF_ARM_EABI_VER4: |
| 2639 | arm_abi = ARM_ABI_AAPCS; |
| 2640 | /* EABI binaries default to VFP float ordering. */ |
| 2641 | if (fp_model == ARM_FLOAT_AUTO) |
| 2642 | fp_model = ARM_FLOAT_SOFT_VFP; |
| 2643 | break; |
| 2644 | |
| 2645 | default: |
| 2646 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
| 2647 | arm_abi = ARM_ABI_APCS; |
| 2648 | break; |
| 2649 | } |
| 2650 | } |
| 2651 | break; |
| 2652 | |
| 2653 | default: |
| 2654 | /* Leave it as "auto". */ |
| 2655 | break; |
| 2656 | } |
| 2657 | } |
| 2658 | |
| 2659 | /* Now that we have inferred any architecture settings that we |
| 2660 | can, try to inherit from the last ARM ABI. */ |
| 2661 | if (arches != NULL) |
| 2662 | { |
| 2663 | if (arm_abi == ARM_ABI_AUTO) |
| 2664 | arm_abi = gdbarch_tdep (arches->gdbarch)->arm_abi; |
| 2665 | |
| 2666 | if (fp_model == ARM_FLOAT_AUTO) |
| 2667 | fp_model = gdbarch_tdep (arches->gdbarch)->fp_model; |
| 2668 | } |
| 2669 | else |
| 2670 | { |
| 2671 | /* There was no prior ARM architecture; fill in default values. */ |
| 2672 | |
| 2673 | if (arm_abi == ARM_ABI_AUTO) |
| 2674 | arm_abi = ARM_ABI_APCS; |
| 2675 | |
| 2676 | /* We used to default to FPA for generic ARM, but almost nobody |
| 2677 | uses that now, and we now provide a way for the user to force |
| 2678 | the model. So default to the most useful variant. */ |
| 2679 | if (fp_model == ARM_FLOAT_AUTO) |
| 2680 | fp_model = ARM_FLOAT_SOFT_FPA; |
| 2681 | } |
| 2682 | |
| 2683 | /* If there is already a candidate, use it. */ |
| 2684 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); |
| 2685 | best_arch != NULL; |
| 2686 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) |
| 2687 | { |
| 2688 | if (arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) |
| 2689 | continue; |
| 2690 | |
| 2691 | if (fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) |
| 2692 | continue; |
| 2693 | |
| 2694 | /* Found a match. */ |
| 2695 | break; |
| 2696 | } |
| 2697 | |
| 2698 | if (best_arch != NULL) |
| 2699 | return best_arch->gdbarch; |
| 2700 | |
| 2701 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); |
| 2702 | gdbarch = gdbarch_alloc (&info, tdep); |
| 2703 | |
| 2704 | /* Record additional information about the architecture we are defining. |
| 2705 | These are gdbarch discriminators, like the OSABI. */ |
| 2706 | tdep->arm_abi = arm_abi; |
| 2707 | tdep->fp_model = fp_model; |
| 2708 | |
| 2709 | /* Breakpoints. */ |
| 2710 | switch (info.byte_order) |
| 2711 | { |
| 2712 | case BFD_ENDIAN_BIG: |
| 2713 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
| 2714 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); |
| 2715 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; |
| 2716 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); |
| 2717 | |
| 2718 | break; |
| 2719 | |
| 2720 | case BFD_ENDIAN_LITTLE: |
| 2721 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
| 2722 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); |
| 2723 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; |
| 2724 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); |
| 2725 | |
| 2726 | break; |
| 2727 | |
| 2728 | default: |
| 2729 | internal_error (__FILE__, __LINE__, |
| 2730 | _("arm_gdbarch_init: bad byte order for float format")); |
| 2731 | } |
| 2732 | |
| 2733 | /* On ARM targets char defaults to unsigned. */ |
| 2734 | set_gdbarch_char_signed (gdbarch, 0); |
| 2735 | |
| 2736 | /* This should be low enough for everything. */ |
| 2737 | tdep->lowest_pc = 0x20; |
| 2738 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
| 2739 | |
| 2740 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
| 2741 | |
| 2742 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
| 2743 | |
| 2744 | /* Frame handling. */ |
| 2745 | set_gdbarch_unwind_dummy_id (gdbarch, arm_unwind_dummy_id); |
| 2746 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
| 2747 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); |
| 2748 | |
| 2749 | frame_base_set_default (gdbarch, &arm_normal_base); |
| 2750 | |
| 2751 | /* Address manipulation. */ |
| 2752 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); |
| 2753 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
| 2754 | |
| 2755 | /* Advance PC across function entry code. */ |
| 2756 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); |
| 2757 | |
| 2758 | /* Get the PC when a frame might not be available. */ |
| 2759 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, arm_saved_pc_after_call); |
| 2760 | |
| 2761 | /* The stack grows downward. */ |
| 2762 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 2763 | |
| 2764 | /* Breakpoint manipulation. */ |
| 2765 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); |
| 2766 | |
| 2767 | /* Information about registers, etc. */ |
| 2768 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); |
| 2769 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
| 2770 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
| 2771 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); |
| 2772 | set_gdbarch_deprecated_register_byte (gdbarch, arm_register_byte); |
| 2773 | set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS); |
| 2774 | set_gdbarch_register_type (gdbarch, arm_register_type); |
| 2775 | |
| 2776 | /* Internal <-> external register number maps. */ |
| 2777 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
| 2778 | |
| 2779 | /* Integer registers are 4 bytes. */ |
| 2780 | set_gdbarch_deprecated_register_size (gdbarch, 4); |
| 2781 | set_gdbarch_register_name (gdbarch, arm_register_name); |
| 2782 | |
| 2783 | /* Returning results. */ |
| 2784 | set_gdbarch_return_value (gdbarch, arm_return_value); |
| 2785 | |
| 2786 | /* Single stepping. */ |
| 2787 | /* XXX For an RDI target we should ask the target if it can single-step. */ |
| 2788 | set_gdbarch_software_single_step (gdbarch, arm_software_single_step); |
| 2789 | |
| 2790 | /* Disassembly. */ |
| 2791 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); |
| 2792 | |
| 2793 | /* Minsymbol frobbing. */ |
| 2794 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); |
| 2795 | set_gdbarch_coff_make_msymbol_special (gdbarch, |
| 2796 | arm_coff_make_msymbol_special); |
| 2797 | |
| 2798 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
| 2799 | gdbarch_init_osabi (info, gdbarch); |
| 2800 | |
| 2801 | /* Add some default predicates. */ |
| 2802 | frame_unwind_append_sniffer (gdbarch, arm_stub_unwind_sniffer); |
| 2803 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
| 2804 | frame_unwind_append_sniffer (gdbarch, arm_prologue_unwind_sniffer); |
| 2805 | |
| 2806 | /* Now we have tuned the configuration, set a few final things, |
| 2807 | based on what the OS ABI has told us. */ |
| 2808 | |
| 2809 | if (tdep->jb_pc >= 0) |
| 2810 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); |
| 2811 | |
| 2812 | /* Floating point sizes and format. */ |
| 2813 | switch (info.byte_order) |
| 2814 | { |
| 2815 | case BFD_ENDIAN_BIG: |
| 2816 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
| 2817 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big); |
| 2818 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); |
| 2819 | break; |
| 2820 | |
| 2821 | case BFD_ENDIAN_LITTLE: |
| 2822 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
| 2823 | if (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA) |
| 2824 | { |
| 2825 | set_gdbarch_double_format |
| 2826 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); |
| 2827 | set_gdbarch_long_double_format |
| 2828 | (gdbarch, &floatformat_ieee_double_littlebyte_bigword); |
| 2829 | } |
| 2830 | else |
| 2831 | { |
| 2832 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little); |
| 2833 | set_gdbarch_long_double_format (gdbarch, |
| 2834 | &floatformat_ieee_double_little); |
| 2835 | } |
| 2836 | break; |
| 2837 | |
| 2838 | default: |
| 2839 | internal_error (__FILE__, __LINE__, |
| 2840 | _("arm_gdbarch_init: bad byte order for float format")); |
| 2841 | } |
| 2842 | |
| 2843 | return gdbarch; |
| 2844 | } |
| 2845 | |
| 2846 | static void |
| 2847 | arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) |
| 2848 | { |
| 2849 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 2850 | |
| 2851 | if (tdep == NULL) |
| 2852 | return; |
| 2853 | |
| 2854 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
| 2855 | (unsigned long) tdep->lowest_pc); |
| 2856 | } |
| 2857 | |
| 2858 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
| 2859 | |
| 2860 | void |
| 2861 | _initialize_arm_tdep (void) |
| 2862 | { |
| 2863 | struct ui_file *stb; |
| 2864 | long length; |
| 2865 | struct cmd_list_element *new_set, *new_show; |
| 2866 | const char *setname; |
| 2867 | const char *setdesc; |
| 2868 | const char *const *regnames; |
| 2869 | int numregs, i, j; |
| 2870 | static char *helptext; |
| 2871 | char regdesc[1024], *rdptr = regdesc; |
| 2872 | size_t rest = sizeof (regdesc); |
| 2873 | |
| 2874 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
| 2875 | |
| 2876 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
| 2877 | gdbarch_register_osabi_sniffer (bfd_arch_arm, |
| 2878 | bfd_target_elf_flavour, |
| 2879 | arm_elf_osabi_sniffer); |
| 2880 | |
| 2881 | /* Get the number of possible sets of register names defined in opcodes. */ |
| 2882 | num_disassembly_options = get_arm_regname_num_options (); |
| 2883 | |
| 2884 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
| 2885 | add_prefix_cmd ("arm", no_class, set_arm_command, |
| 2886 | _("Various ARM-specific commands."), |
| 2887 | &setarmcmdlist, "set arm ", 0, &setlist); |
| 2888 | |
| 2889 | add_prefix_cmd ("arm", no_class, show_arm_command, |
| 2890 | _("Various ARM-specific commands."), |
| 2891 | &showarmcmdlist, "show arm ", 0, &showlist); |
| 2892 | |
| 2893 | /* Sync the opcode insn printer with our register viewer. */ |
| 2894 | parse_arm_disassembler_option ("reg-names-std"); |
| 2895 | |
| 2896 | /* Initialize the array that will be passed to |
| 2897 | add_setshow_enum_cmd(). */ |
| 2898 | valid_disassembly_styles |
| 2899 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); |
| 2900 | for (i = 0; i < num_disassembly_options; i++) |
| 2901 | { |
| 2902 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); |
| 2903 | valid_disassembly_styles[i] = setname; |
| 2904 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
| 2905 | rdptr += length; |
| 2906 | rest -= length; |
| 2907 | /* Copy the default names (if found) and synchronize disassembler. */ |
| 2908 | if (!strcmp (setname, "std")) |
| 2909 | { |
| 2910 | disassembly_style = setname; |
| 2911 | current_option = i; |
| 2912 | for (j = 0; j < numregs; j++) |
| 2913 | arm_register_names[j] = (char *) regnames[j]; |
| 2914 | set_arm_regname_option (i); |
| 2915 | } |
| 2916 | } |
| 2917 | /* Mark the end of valid options. */ |
| 2918 | valid_disassembly_styles[num_disassembly_options] = NULL; |
| 2919 | |
| 2920 | /* Create the help text. */ |
| 2921 | stb = mem_fileopen (); |
| 2922 | fprintf_unfiltered (stb, "%s%s%s", |
| 2923 | _("The valid values are:\n"), |
| 2924 | regdesc, |
| 2925 | _("The default is \"std\".")); |
| 2926 | helptext = ui_file_xstrdup (stb, &length); |
| 2927 | ui_file_delete (stb); |
| 2928 | |
| 2929 | add_setshow_enum_cmd("disassembler", no_class, |
| 2930 | valid_disassembly_styles, &disassembly_style, |
| 2931 | _("Set the disassembly style."), |
| 2932 | _("Show the disassembly style."), |
| 2933 | helptext, |
| 2934 | set_disassembly_style_sfunc, |
| 2935 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
| 2936 | &setarmcmdlist, &showarmcmdlist); |
| 2937 | |
| 2938 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, |
| 2939 | _("Set usage of ARM 32-bit mode."), |
| 2940 | _("Show usage of ARM 32-bit mode."), |
| 2941 | _("When off, a 26-bit PC will be used."), |
| 2942 | NULL, |
| 2943 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
| 2944 | &setarmcmdlist, &showarmcmdlist); |
| 2945 | |
| 2946 | /* Add a command to allow the user to force the FPU model. */ |
| 2947 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
| 2948 | _("Set the floating point type."), |
| 2949 | _("Show the floating point type."), |
| 2950 | _("auto - Determine the FP typefrom the OS-ABI.\n\ |
| 2951 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ |
| 2952 | fpa - FPA co-processor (GCC compiled).\n\ |
| 2953 | softvfp - Software FP with pure-endian doubles.\n\ |
| 2954 | vfp - VFP co-processor."), |
| 2955 | set_fp_model_sfunc, show_fp_model, |
| 2956 | &setarmcmdlist, &showarmcmdlist); |
| 2957 | |
| 2958 | /* Add a command to allow the user to force the ABI. */ |
| 2959 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, |
| 2960 | _("Set the ABI."), |
| 2961 | _("Show the ABI."), |
| 2962 | NULL, arm_set_abi, arm_show_abi, |
| 2963 | &setarmcmdlist, &showarmcmdlist); |
| 2964 | |
| 2965 | /* Debugging flag. */ |
| 2966 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
| 2967 | _("Set ARM debugging."), |
| 2968 | _("Show ARM debugging."), |
| 2969 | _("When on, arm-specific debugging is enabled."), |
| 2970 | NULL, |
| 2971 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
| 2972 | &setdebuglist, &showdebuglist); |
| 2973 | } |