| 1 | /* Common target dependent code for GDB on ARM systems. |
| 2 | |
| 3 | Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000, |
| 4 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
| 5 | Free Software Foundation, Inc. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | #include <ctype.h> /* XXX for isupper () */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "frame.h" |
| 26 | #include "inferior.h" |
| 27 | #include "gdbcmd.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "gdb_string.h" |
| 30 | #include "dis-asm.h" /* For register styles. */ |
| 31 | #include "regcache.h" |
| 32 | #include "doublest.h" |
| 33 | #include "value.h" |
| 34 | #include "arch-utils.h" |
| 35 | #include "osabi.h" |
| 36 | #include "frame-unwind.h" |
| 37 | #include "frame-base.h" |
| 38 | #include "trad-frame.h" |
| 39 | #include "objfiles.h" |
| 40 | #include "dwarf2-frame.h" |
| 41 | #include "gdbtypes.h" |
| 42 | #include "prologue-value.h" |
| 43 | #include "target-descriptions.h" |
| 44 | #include "user-regs.h" |
| 45 | |
| 46 | #include "arm-tdep.h" |
| 47 | #include "gdb/sim-arm.h" |
| 48 | |
| 49 | #include "elf-bfd.h" |
| 50 | #include "coff/internal.h" |
| 51 | #include "elf/arm.h" |
| 52 | |
| 53 | #include "gdb_assert.h" |
| 54 | #include "vec.h" |
| 55 | |
| 56 | static int arm_debug; |
| 57 | |
| 58 | /* Macros for setting and testing a bit in a minimal symbol that marks |
| 59 | it as Thumb function. The MSB of the minimal symbol's "info" field |
| 60 | is used for this purpose. |
| 61 | |
| 62 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. |
| 63 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */ |
| 64 | |
| 65 | #define MSYMBOL_SET_SPECIAL(msym) \ |
| 66 | MSYMBOL_TARGET_FLAG_1 (msym) = 1 |
| 67 | |
| 68 | #define MSYMBOL_IS_SPECIAL(msym) \ |
| 69 | MSYMBOL_TARGET_FLAG_1 (msym) |
| 70 | |
| 71 | /* Macros for swapping shorts and ints. In the unlikely case that anybody else needs these, |
| 72 | move to a general header. (A better solution might be to define memory read routines that |
| 73 | know whether they are reading code or data.) */ |
| 74 | |
| 75 | #define SWAP_SHORT(x) \ |
| 76 | ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8)); |
| 77 | |
| 78 | #define SWAP_INT(x) \ |
| 79 | ( ((x & 0xff000000) >> 24) \ |
| 80 | | ((x & 0x00ff0000) >> 8) \ |
| 81 | | ((x & 0x0000ff00) << 8) \ |
| 82 | | ((x & 0x000000ff) << 24)) |
| 83 | |
| 84 | /* Per-objfile data used for mapping symbols. */ |
| 85 | static const struct objfile_data *arm_objfile_data_key; |
| 86 | |
| 87 | struct arm_mapping_symbol |
| 88 | { |
| 89 | bfd_vma value; |
| 90 | char type; |
| 91 | }; |
| 92 | typedef struct arm_mapping_symbol arm_mapping_symbol_s; |
| 93 | DEF_VEC_O(arm_mapping_symbol_s); |
| 94 | |
| 95 | struct arm_per_objfile |
| 96 | { |
| 97 | VEC(arm_mapping_symbol_s) **section_maps; |
| 98 | }; |
| 99 | |
| 100 | /* The list of available "set arm ..." and "show arm ..." commands. */ |
| 101 | static struct cmd_list_element *setarmcmdlist = NULL; |
| 102 | static struct cmd_list_element *showarmcmdlist = NULL; |
| 103 | |
| 104 | /* The type of floating-point to use. Keep this in sync with enum |
| 105 | arm_float_model, and the help string in _initialize_arm_tdep. */ |
| 106 | static const char *fp_model_strings[] = |
| 107 | { |
| 108 | "auto", |
| 109 | "softfpa", |
| 110 | "fpa", |
| 111 | "softvfp", |
| 112 | "vfp", |
| 113 | NULL |
| 114 | }; |
| 115 | |
| 116 | /* A variable that can be configured by the user. */ |
| 117 | static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO; |
| 118 | static const char *current_fp_model = "auto"; |
| 119 | |
| 120 | /* The ABI to use. Keep this in sync with arm_abi_kind. */ |
| 121 | static const char *arm_abi_strings[] = |
| 122 | { |
| 123 | "auto", |
| 124 | "APCS", |
| 125 | "AAPCS", |
| 126 | NULL |
| 127 | }; |
| 128 | |
| 129 | /* A variable that can be configured by the user. */ |
| 130 | static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO; |
| 131 | static const char *arm_abi_string = "auto"; |
| 132 | |
| 133 | /* The execution mode to assume. */ |
| 134 | static const char *arm_mode_strings[] = |
| 135 | { |
| 136 | "auto", |
| 137 | "arm", |
| 138 | "thumb" |
| 139 | }; |
| 140 | |
| 141 | static const char *arm_fallback_mode_string = "auto"; |
| 142 | static const char *arm_force_mode_string = "auto"; |
| 143 | |
| 144 | /* Number of different reg name sets (options). */ |
| 145 | static int num_disassembly_options; |
| 146 | |
| 147 | /* The standard register names, and all the valid aliases for them. */ |
| 148 | static const struct |
| 149 | { |
| 150 | const char *name; |
| 151 | int regnum; |
| 152 | } arm_register_aliases[] = { |
| 153 | /* Basic register numbers. */ |
| 154 | { "r0", 0 }, |
| 155 | { "r1", 1 }, |
| 156 | { "r2", 2 }, |
| 157 | { "r3", 3 }, |
| 158 | { "r4", 4 }, |
| 159 | { "r5", 5 }, |
| 160 | { "r6", 6 }, |
| 161 | { "r7", 7 }, |
| 162 | { "r8", 8 }, |
| 163 | { "r9", 9 }, |
| 164 | { "r10", 10 }, |
| 165 | { "r11", 11 }, |
| 166 | { "r12", 12 }, |
| 167 | { "r13", 13 }, |
| 168 | { "r14", 14 }, |
| 169 | { "r15", 15 }, |
| 170 | /* Synonyms (argument and variable registers). */ |
| 171 | { "a1", 0 }, |
| 172 | { "a2", 1 }, |
| 173 | { "a3", 2 }, |
| 174 | { "a4", 3 }, |
| 175 | { "v1", 4 }, |
| 176 | { "v2", 5 }, |
| 177 | { "v3", 6 }, |
| 178 | { "v4", 7 }, |
| 179 | { "v5", 8 }, |
| 180 | { "v6", 9 }, |
| 181 | { "v7", 10 }, |
| 182 | { "v8", 11 }, |
| 183 | /* Other platform-specific names for r9. */ |
| 184 | { "sb", 9 }, |
| 185 | { "tr", 9 }, |
| 186 | /* Special names. */ |
| 187 | { "ip", 12 }, |
| 188 | { "sp", 13 }, |
| 189 | { "lr", 14 }, |
| 190 | { "pc", 15 }, |
| 191 | /* Names used by GCC (not listed in the ARM EABI). */ |
| 192 | { "sl", 10 }, |
| 193 | { "fp", 11 }, |
| 194 | /* A special name from the older ATPCS. */ |
| 195 | { "wr", 7 }, |
| 196 | }; |
| 197 | |
| 198 | static const char *const arm_register_names[] = |
| 199 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
| 200 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ |
| 201 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ |
| 202 | "r12", "sp", "lr", "pc", /* 12 13 14 15 */ |
| 203 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ |
| 204 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ |
| 205 | "fps", "cpsr" }; /* 24 25 */ |
| 206 | |
| 207 | /* Valid register name styles. */ |
| 208 | static const char **valid_disassembly_styles; |
| 209 | |
| 210 | /* Disassembly style to use. Default to "std" register names. */ |
| 211 | static const char *disassembly_style; |
| 212 | |
| 213 | /* This is used to keep the bfd arch_info in sync with the disassembly |
| 214 | style. */ |
| 215 | static void set_disassembly_style_sfunc(char *, int, |
| 216 | struct cmd_list_element *); |
| 217 | static void set_disassembly_style (void); |
| 218 | |
| 219 | static void convert_from_extended (const struct floatformat *, const void *, |
| 220 | void *, int); |
| 221 | static void convert_to_extended (const struct floatformat *, void *, |
| 222 | const void *, int); |
| 223 | |
| 224 | struct arm_prologue_cache |
| 225 | { |
| 226 | /* The stack pointer at the time this frame was created; i.e. the |
| 227 | caller's stack pointer when this function was called. It is used |
| 228 | to identify this frame. */ |
| 229 | CORE_ADDR prev_sp; |
| 230 | |
| 231 | /* The frame base for this frame is just prev_sp - frame size. |
| 232 | FRAMESIZE is the distance from the frame pointer to the |
| 233 | initial stack pointer. */ |
| 234 | |
| 235 | int framesize; |
| 236 | |
| 237 | /* The register used to hold the frame pointer for this frame. */ |
| 238 | int framereg; |
| 239 | |
| 240 | /* Saved register offsets. */ |
| 241 | struct trad_frame_saved_reg *saved_regs; |
| 242 | }; |
| 243 | |
| 244 | /* Addresses for calling Thumb functions have the bit 0 set. |
| 245 | Here are some macros to test, set, or clear bit 0 of addresses. */ |
| 246 | #define IS_THUMB_ADDR(addr) ((addr) & 1) |
| 247 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) |
| 248 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) |
| 249 | |
| 250 | /* Set to true if the 32-bit mode is in use. */ |
| 251 | |
| 252 | int arm_apcs_32 = 1; |
| 253 | |
| 254 | /* Determine if FRAME is executing in Thumb mode. */ |
| 255 | |
| 256 | static int |
| 257 | arm_frame_is_thumb (struct frame_info *frame) |
| 258 | { |
| 259 | CORE_ADDR cpsr; |
| 260 | |
| 261 | /* Every ARM frame unwinder can unwind the T bit of the CPSR, either |
| 262 | directly (from a signal frame or dummy frame) or by interpreting |
| 263 | the saved LR (from a prologue or DWARF frame). So consult it and |
| 264 | trust the unwinders. */ |
| 265 | cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
| 266 | |
| 267 | return (cpsr & CPSR_T) != 0; |
| 268 | } |
| 269 | |
| 270 | /* Callback for VEC_lower_bound. */ |
| 271 | |
| 272 | static inline int |
| 273 | arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs, |
| 274 | const struct arm_mapping_symbol *rhs) |
| 275 | { |
| 276 | return lhs->value < rhs->value; |
| 277 | } |
| 278 | |
| 279 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
| 280 | function. This function should be called for addresses unrelated to |
| 281 | any executing frame; otherwise, prefer arm_frame_is_thumb. */ |
| 282 | |
| 283 | static int |
| 284 | arm_pc_is_thumb (CORE_ADDR memaddr) |
| 285 | { |
| 286 | struct obj_section *sec; |
| 287 | struct minimal_symbol *sym; |
| 288 | |
| 289 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
| 290 | if (IS_THUMB_ADDR (memaddr)) |
| 291 | return 1; |
| 292 | |
| 293 | /* If the user wants to override the symbol table, let him. */ |
| 294 | if (strcmp (arm_force_mode_string, "arm") == 0) |
| 295 | return 0; |
| 296 | if (strcmp (arm_force_mode_string, "thumb") == 0) |
| 297 | return 1; |
| 298 | |
| 299 | /* If there are mapping symbols, consult them. */ |
| 300 | sec = find_pc_section (memaddr); |
| 301 | if (sec != NULL) |
| 302 | { |
| 303 | struct arm_per_objfile *data; |
| 304 | VEC(arm_mapping_symbol_s) *map; |
| 305 | struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec), |
| 306 | 0 }; |
| 307 | unsigned int idx; |
| 308 | |
| 309 | data = objfile_data (sec->objfile, arm_objfile_data_key); |
| 310 | if (data != NULL) |
| 311 | { |
| 312 | map = data->section_maps[sec->the_bfd_section->index]; |
| 313 | if (!VEC_empty (arm_mapping_symbol_s, map)) |
| 314 | { |
| 315 | struct arm_mapping_symbol *map_sym; |
| 316 | |
| 317 | idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key, |
| 318 | arm_compare_mapping_symbols); |
| 319 | |
| 320 | /* VEC_lower_bound finds the earliest ordered insertion |
| 321 | point. If the following symbol starts at this exact |
| 322 | address, we use that; otherwise, the preceding |
| 323 | mapping symbol covers this address. */ |
| 324 | if (idx < VEC_length (arm_mapping_symbol_s, map)) |
| 325 | { |
| 326 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx); |
| 327 | if (map_sym->value == map_key.value) |
| 328 | return map_sym->type == 't'; |
| 329 | } |
| 330 | |
| 331 | if (idx > 0) |
| 332 | { |
| 333 | map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1); |
| 334 | return map_sym->type == 't'; |
| 335 | } |
| 336 | } |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
| 341 | sym = lookup_minimal_symbol_by_pc (memaddr); |
| 342 | if (sym) |
| 343 | return (MSYMBOL_IS_SPECIAL (sym)); |
| 344 | |
| 345 | /* If the user wants to override the fallback mode, let them. */ |
| 346 | if (strcmp (arm_fallback_mode_string, "arm") == 0) |
| 347 | return 0; |
| 348 | if (strcmp (arm_fallback_mode_string, "thumb") == 0) |
| 349 | return 1; |
| 350 | |
| 351 | /* If we couldn't find any symbol, but we're talking to a running |
| 352 | target, then trust the current value of $cpsr. This lets |
| 353 | "display/i $pc" always show the correct mode (though if there is |
| 354 | a symbol table we will not reach here, so it still may not be |
| 355 | displayed in the mode it will be executed). */ |
| 356 | if (target_has_registers) |
| 357 | return arm_frame_is_thumb (get_current_frame ()); |
| 358 | |
| 359 | /* Otherwise we're out of luck; we assume ARM. */ |
| 360 | return 0; |
| 361 | } |
| 362 | |
| 363 | /* Remove useless bits from addresses in a running program. */ |
| 364 | static CORE_ADDR |
| 365 | arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) |
| 366 | { |
| 367 | if (arm_apcs_32) |
| 368 | return UNMAKE_THUMB_ADDR (val); |
| 369 | else |
| 370 | return (val & 0x03fffffc); |
| 371 | } |
| 372 | |
| 373 | /* When reading symbols, we need to zap the low bit of the address, |
| 374 | which may be set to 1 for Thumb functions. */ |
| 375 | static CORE_ADDR |
| 376 | arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val) |
| 377 | { |
| 378 | return val & ~1; |
| 379 | } |
| 380 | |
| 381 | /* Analyze a Thumb prologue, looking for a recognizable stack frame |
| 382 | and frame pointer. Scan until we encounter a store that could |
| 383 | clobber the stack frame unexpectedly, or an unknown instruction. */ |
| 384 | |
| 385 | static CORE_ADDR |
| 386 | thumb_analyze_prologue (struct gdbarch *gdbarch, |
| 387 | CORE_ADDR start, CORE_ADDR limit, |
| 388 | struct arm_prologue_cache *cache) |
| 389 | { |
| 390 | int i; |
| 391 | pv_t regs[16]; |
| 392 | struct pv_area *stack; |
| 393 | struct cleanup *back_to; |
| 394 | CORE_ADDR offset; |
| 395 | |
| 396 | for (i = 0; i < 16; i++) |
| 397 | regs[i] = pv_register (i, 0); |
| 398 | stack = make_pv_area (ARM_SP_REGNUM); |
| 399 | back_to = make_cleanup_free_pv_area (stack); |
| 400 | |
| 401 | while (start < limit) |
| 402 | { |
| 403 | unsigned short insn; |
| 404 | |
| 405 | insn = read_memory_unsigned_integer (start, 2); |
| 406 | |
| 407 | if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch)) |
| 408 | insn = SWAP_SHORT (insn); |
| 409 | |
| 410 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
| 411 | { |
| 412 | int regno; |
| 413 | int mask; |
| 414 | |
| 415 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 416 | break; |
| 417 | |
| 418 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says |
| 419 | whether to save LR (R14). */ |
| 420 | mask = (insn & 0xff) | ((insn & 0x100) << 6); |
| 421 | |
| 422 | /* Calculate offsets of saved R0-R7 and LR. */ |
| 423 | for (regno = ARM_LR_REGNUM; regno >= 0; regno--) |
| 424 | if (mask & (1 << regno)) |
| 425 | { |
| 426 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
| 427 | -4); |
| 428 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); |
| 429 | } |
| 430 | } |
| 431 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR |
| 432 | sub sp, #simm */ |
| 433 | { |
| 434 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
| 435 | if (insn & 0x80) /* Check for SUB. */ |
| 436 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
| 437 | -offset); |
| 438 | else |
| 439 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
| 440 | offset); |
| 441 | } |
| 442 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ |
| 443 | regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], |
| 444 | (insn & 0xff) << 2); |
| 445 | else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */ |
| 446 | { |
| 447 | int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4); |
| 448 | int src_reg = (insn & 0x78) >> 3; |
| 449 | regs[dst_reg] = regs[src_reg]; |
| 450 | } |
| 451 | else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */ |
| 452 | { |
| 453 | /* Handle stores to the stack. Normally pushes are used, |
| 454 | but with GCC -mtpcs-frame, there may be other stores |
| 455 | in the prologue to create the frame. */ |
| 456 | int regno = (insn >> 8) & 0x7; |
| 457 | pv_t addr; |
| 458 | |
| 459 | offset = (insn & 0xff) << 2; |
| 460 | addr = pv_add_constant (regs[ARM_SP_REGNUM], offset); |
| 461 | |
| 462 | if (pv_area_store_would_trash (stack, addr)) |
| 463 | break; |
| 464 | |
| 465 | pv_area_store (stack, addr, 4, regs[regno]); |
| 466 | } |
| 467 | else |
| 468 | { |
| 469 | /* We don't know what this instruction is. We're finished |
| 470 | scanning. NOTE: Recognizing more safe-to-ignore |
| 471 | instructions here will improve support for optimized |
| 472 | code. */ |
| 473 | break; |
| 474 | } |
| 475 | |
| 476 | start += 2; |
| 477 | } |
| 478 | |
| 479 | if (cache == NULL) |
| 480 | { |
| 481 | do_cleanups (back_to); |
| 482 | return start; |
| 483 | } |
| 484 | |
| 485 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
| 486 | { |
| 487 | /* Frame pointer is fp. Frame size is constant. */ |
| 488 | cache->framereg = ARM_FP_REGNUM; |
| 489 | cache->framesize = -regs[ARM_FP_REGNUM].k; |
| 490 | } |
| 491 | else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM)) |
| 492 | { |
| 493 | /* Frame pointer is r7. Frame size is constant. */ |
| 494 | cache->framereg = THUMB_FP_REGNUM; |
| 495 | cache->framesize = -regs[THUMB_FP_REGNUM].k; |
| 496 | } |
| 497 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) |
| 498 | { |
| 499 | /* Try the stack pointer... this is a bit desperate. */ |
| 500 | cache->framereg = ARM_SP_REGNUM; |
| 501 | cache->framesize = -regs[ARM_SP_REGNUM].k; |
| 502 | } |
| 503 | else |
| 504 | { |
| 505 | /* We're just out of luck. We don't know where the frame is. */ |
| 506 | cache->framereg = -1; |
| 507 | cache->framesize = 0; |
| 508 | } |
| 509 | |
| 510 | for (i = 0; i < 16; i++) |
| 511 | if (pv_area_find_reg (stack, gdbarch, i, &offset)) |
| 512 | cache->saved_regs[i].addr = offset; |
| 513 | |
| 514 | do_cleanups (back_to); |
| 515 | return start; |
| 516 | } |
| 517 | |
| 518 | /* Advance the PC across any function entry prologue instructions to |
| 519 | reach some "real" code. |
| 520 | |
| 521 | The APCS (ARM Procedure Call Standard) defines the following |
| 522 | prologue: |
| 523 | |
| 524 | mov ip, sp |
| 525 | [stmfd sp!, {a1,a2,a3,a4}] |
| 526 | stmfd sp!, {...,fp,ip,lr,pc} |
| 527 | [stfe f7, [sp, #-12]!] |
| 528 | [stfe f6, [sp, #-12]!] |
| 529 | [stfe f5, [sp, #-12]!] |
| 530 | [stfe f4, [sp, #-12]!] |
| 531 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ |
| 532 | |
| 533 | static CORE_ADDR |
| 534 | arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 535 | { |
| 536 | unsigned long inst; |
| 537 | CORE_ADDR skip_pc; |
| 538 | CORE_ADDR func_addr, limit_pc; |
| 539 | struct symtab_and_line sal; |
| 540 | |
| 541 | /* If we're in a dummy frame, don't even try to skip the prologue. */ |
| 542 | if (deprecated_pc_in_call_dummy (pc)) |
| 543 | return pc; |
| 544 | |
| 545 | /* See if we can determine the end of the prologue via the symbol table. |
| 546 | If so, then return either PC, or the PC after the prologue, whichever |
| 547 | is greater. */ |
| 548 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
| 549 | { |
| 550 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); |
| 551 | if (post_prologue_pc != 0) |
| 552 | return max (pc, post_prologue_pc); |
| 553 | } |
| 554 | |
| 555 | /* Can't determine prologue from the symbol table, need to examine |
| 556 | instructions. */ |
| 557 | |
| 558 | /* Find an upper limit on the function prologue using the debug |
| 559 | information. If the debug information could not be used to provide |
| 560 | that bound, then use an arbitrary large number as the upper bound. */ |
| 561 | /* Like arm_scan_prologue, stop no later than pc + 64. */ |
| 562 | limit_pc = skip_prologue_using_sal (pc); |
| 563 | if (limit_pc == 0) |
| 564 | limit_pc = pc + 64; /* Magic. */ |
| 565 | |
| 566 | |
| 567 | /* Check if this is Thumb code. */ |
| 568 | if (arm_pc_is_thumb (pc)) |
| 569 | return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); |
| 570 | |
| 571 | for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4) |
| 572 | { |
| 573 | inst = read_memory_unsigned_integer (skip_pc, 4); |
| 574 | |
| 575 | if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch)) |
| 576 | inst = SWAP_INT (inst); |
| 577 | |
| 578 | /* "mov ip, sp" is no longer a required part of the prologue. */ |
| 579 | if (inst == 0xe1a0c00d) /* mov ip, sp */ |
| 580 | continue; |
| 581 | |
| 582 | if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
| 583 | continue; |
| 584 | |
| 585 | if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ |
| 586 | continue; |
| 587 | |
| 588 | /* Some prologues begin with "str lr, [sp, #-4]!". */ |
| 589 | if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 590 | continue; |
| 591 | |
| 592 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
| 593 | continue; |
| 594 | |
| 595 | if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ |
| 596 | continue; |
| 597 | |
| 598 | /* Any insns after this point may float into the code, if it makes |
| 599 | for better instruction scheduling, so we skip them only if we |
| 600 | find them, but still consider the function to be frame-ful. */ |
| 601 | |
| 602 | /* We may have either one sfmfd instruction here, or several stfe |
| 603 | insns, depending on the version of floating point code we |
| 604 | support. */ |
| 605 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
| 606 | continue; |
| 607 | |
| 608 | if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
| 609 | continue; |
| 610 | |
| 611 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
| 612 | continue; |
| 613 | |
| 614 | if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ |
| 615 | continue; |
| 616 | |
| 617 | if ((inst & 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */ |
| 618 | (inst & 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */ |
| 619 | (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ |
| 620 | continue; |
| 621 | |
| 622 | if ((inst & 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */ |
| 623 | (inst & 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */ |
| 624 | (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ |
| 625 | continue; |
| 626 | |
| 627 | /* Un-recognized instruction; stop scanning. */ |
| 628 | break; |
| 629 | } |
| 630 | |
| 631 | return skip_pc; /* End of prologue */ |
| 632 | } |
| 633 | |
| 634 | /* *INDENT-OFF* */ |
| 635 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
| 636 | This function decodes a Thumb function prologue to determine: |
| 637 | 1) the size of the stack frame |
| 638 | 2) which registers are saved on it |
| 639 | 3) the offsets of saved regs |
| 640 | 4) the offset from the stack pointer to the frame pointer |
| 641 | |
| 642 | A typical Thumb function prologue would create this stack frame |
| 643 | (offsets relative to FP) |
| 644 | old SP -> 24 stack parameters |
| 645 | 20 LR |
| 646 | 16 R7 |
| 647 | R7 -> 0 local variables (16 bytes) |
| 648 | SP -> -12 additional stack space (12 bytes) |
| 649 | The frame size would thus be 36 bytes, and the frame offset would be |
| 650 | 12 bytes. The frame register is R7. |
| 651 | |
| 652 | The comments for thumb_skip_prolog() describe the algorithm we use |
| 653 | to detect the end of the prolog. */ |
| 654 | /* *INDENT-ON* */ |
| 655 | |
| 656 | static void |
| 657 | thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, |
| 658 | CORE_ADDR block_addr, struct arm_prologue_cache *cache) |
| 659 | { |
| 660 | CORE_ADDR prologue_start; |
| 661 | CORE_ADDR prologue_end; |
| 662 | CORE_ADDR current_pc; |
| 663 | |
| 664 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
| 665 | &prologue_end)) |
| 666 | { |
| 667 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 668 | |
| 669 | if (sal.line == 0) /* no line info, use current PC */ |
| 670 | prologue_end = prev_pc; |
| 671 | else if (sal.end < prologue_end) /* next line begins after fn end */ |
| 672 | prologue_end = sal.end; /* (probably means no prologue) */ |
| 673 | } |
| 674 | else |
| 675 | /* We're in the boondocks: we have no idea where the start of the |
| 676 | function is. */ |
| 677 | return; |
| 678 | |
| 679 | prologue_end = min (prologue_end, prev_pc); |
| 680 | |
| 681 | thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
| 682 | } |
| 683 | |
| 684 | /* This function decodes an ARM function prologue to determine: |
| 685 | 1) the size of the stack frame |
| 686 | 2) which registers are saved on it |
| 687 | 3) the offsets of saved regs |
| 688 | 4) the offset from the stack pointer to the frame pointer |
| 689 | This information is stored in the "extra" fields of the frame_info. |
| 690 | |
| 691 | There are two basic forms for the ARM prologue. The fixed argument |
| 692 | function call will look like: |
| 693 | |
| 694 | mov ip, sp |
| 695 | stmfd sp!, {fp, ip, lr, pc} |
| 696 | sub fp, ip, #4 |
| 697 | [sub sp, sp, #4] |
| 698 | |
| 699 | Which would create this stack frame (offsets relative to FP): |
| 700 | IP -> 4 (caller's stack) |
| 701 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 702 | -4 LR (return address in caller) |
| 703 | -8 IP (copy of caller's SP) |
| 704 | -12 FP (caller's FP) |
| 705 | SP -> -28 Local variables |
| 706 | |
| 707 | The frame size would thus be 32 bytes, and the frame offset would be |
| 708 | 28 bytes. The stmfd call can also save any of the vN registers it |
| 709 | plans to use, which increases the frame size accordingly. |
| 710 | |
| 711 | Note: The stored PC is 8 off of the STMFD instruction that stored it |
| 712 | because the ARM Store instructions always store PC + 8 when you read |
| 713 | the PC register. |
| 714 | |
| 715 | A variable argument function call will look like: |
| 716 | |
| 717 | mov ip, sp |
| 718 | stmfd sp!, {a1, a2, a3, a4} |
| 719 | stmfd sp!, {fp, ip, lr, pc} |
| 720 | sub fp, ip, #20 |
| 721 | |
| 722 | Which would create this stack frame (offsets relative to FP): |
| 723 | IP -> 20 (caller's stack) |
| 724 | 16 A4 |
| 725 | 12 A3 |
| 726 | 8 A2 |
| 727 | 4 A1 |
| 728 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) |
| 729 | -4 LR (return address in caller) |
| 730 | -8 IP (copy of caller's SP) |
| 731 | -12 FP (caller's FP) |
| 732 | SP -> -28 Local variables |
| 733 | |
| 734 | The frame size would thus be 48 bytes, and the frame offset would be |
| 735 | 28 bytes. |
| 736 | |
| 737 | There is another potential complication, which is that the optimizer |
| 738 | will try to separate the store of fp in the "stmfd" instruction from |
| 739 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so |
| 740 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... |
| 741 | |
| 742 | Also, note, the original version of the ARM toolchain claimed that there |
| 743 | should be an |
| 744 | |
| 745 | instruction at the end of the prologue. I have never seen GCC produce |
| 746 | this, and the ARM docs don't mention it. We still test for it below in |
| 747 | case it happens... |
| 748 | |
| 749 | */ |
| 750 | |
| 751 | static void |
| 752 | arm_scan_prologue (struct frame_info *this_frame, |
| 753 | struct arm_prologue_cache *cache) |
| 754 | { |
| 755 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 756 | int regno; |
| 757 | CORE_ADDR prologue_start, prologue_end, current_pc; |
| 758 | CORE_ADDR prev_pc = get_frame_pc (this_frame); |
| 759 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); |
| 760 | pv_t regs[ARM_FPS_REGNUM]; |
| 761 | struct pv_area *stack; |
| 762 | struct cleanup *back_to; |
| 763 | CORE_ADDR offset; |
| 764 | |
| 765 | /* Assume there is no frame until proven otherwise. */ |
| 766 | cache->framereg = ARM_SP_REGNUM; |
| 767 | cache->framesize = 0; |
| 768 | |
| 769 | /* Check for Thumb prologue. */ |
| 770 | if (arm_frame_is_thumb (this_frame)) |
| 771 | { |
| 772 | thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache); |
| 773 | return; |
| 774 | } |
| 775 | |
| 776 | /* Find the function prologue. If we can't find the function in |
| 777 | the symbol table, peek in the stack frame to find the PC. */ |
| 778 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, |
| 779 | &prologue_end)) |
| 780 | { |
| 781 | /* One way to find the end of the prologue (which works well |
| 782 | for unoptimized code) is to do the following: |
| 783 | |
| 784 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); |
| 785 | |
| 786 | if (sal.line == 0) |
| 787 | prologue_end = prev_pc; |
| 788 | else if (sal.end < prologue_end) |
| 789 | prologue_end = sal.end; |
| 790 | |
| 791 | This mechanism is very accurate so long as the optimizer |
| 792 | doesn't move any instructions from the function body into the |
| 793 | prologue. If this happens, sal.end will be the last |
| 794 | instruction in the first hunk of prologue code just before |
| 795 | the first instruction that the scheduler has moved from |
| 796 | the body to the prologue. |
| 797 | |
| 798 | In order to make sure that we scan all of the prologue |
| 799 | instructions, we use a slightly less accurate mechanism which |
| 800 | may scan more than necessary. To help compensate for this |
| 801 | lack of accuracy, the prologue scanning loop below contains |
| 802 | several clauses which'll cause the loop to terminate early if |
| 803 | an implausible prologue instruction is encountered. |
| 804 | |
| 805 | The expression |
| 806 | |
| 807 | prologue_start + 64 |
| 808 | |
| 809 | is a suitable endpoint since it accounts for the largest |
| 810 | possible prologue plus up to five instructions inserted by |
| 811 | the scheduler. */ |
| 812 | |
| 813 | if (prologue_end > prologue_start + 64) |
| 814 | { |
| 815 | prologue_end = prologue_start + 64; /* See above. */ |
| 816 | } |
| 817 | } |
| 818 | else |
| 819 | { |
| 820 | /* We have no symbol information. Our only option is to assume this |
| 821 | function has a standard stack frame and the normal frame register. |
| 822 | Then, we can find the value of our frame pointer on entrance to |
| 823 | the callee (or at the present moment if this is the innermost frame). |
| 824 | The value stored there should be the address of the stmfd + 8. */ |
| 825 | CORE_ADDR frame_loc; |
| 826 | LONGEST return_value; |
| 827 | |
| 828 | frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); |
| 829 | if (!safe_read_memory_integer (frame_loc, 4, &return_value)) |
| 830 | return; |
| 831 | else |
| 832 | { |
| 833 | prologue_start = gdbarch_addr_bits_remove |
| 834 | (gdbarch, return_value) - 8; |
| 835 | prologue_end = prologue_start + 64; /* See above. */ |
| 836 | } |
| 837 | } |
| 838 | |
| 839 | if (prev_pc < prologue_end) |
| 840 | prologue_end = prev_pc; |
| 841 | |
| 842 | /* Now search the prologue looking for instructions that set up the |
| 843 | frame pointer, adjust the stack pointer, and save registers. |
| 844 | |
| 845 | Be careful, however, and if it doesn't look like a prologue, |
| 846 | don't try to scan it. If, for instance, a frameless function |
| 847 | begins with stmfd sp!, then we will tell ourselves there is |
| 848 | a frame, which will confuse stack traceback, as well as "finish" |
| 849 | and other operations that rely on a knowledge of the stack |
| 850 | traceback. |
| 851 | |
| 852 | In the APCS, the prologue should start with "mov ip, sp" so |
| 853 | if we don't see this as the first insn, we will stop. |
| 854 | |
| 855 | [Note: This doesn't seem to be true any longer, so it's now an |
| 856 | optional part of the prologue. - Kevin Buettner, 2001-11-20] |
| 857 | |
| 858 | [Note further: The "mov ip,sp" only seems to be missing in |
| 859 | frameless functions at optimization level "-O2" or above, |
| 860 | in which case it is often (but not always) replaced by |
| 861 | "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */ |
| 862 | |
| 863 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
| 864 | regs[regno] = pv_register (regno, 0); |
| 865 | stack = make_pv_area (ARM_SP_REGNUM); |
| 866 | back_to = make_cleanup_free_pv_area (stack); |
| 867 | |
| 868 | for (current_pc = prologue_start; |
| 869 | current_pc < prologue_end; |
| 870 | current_pc += 4) |
| 871 | { |
| 872 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
| 873 | |
| 874 | if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch)) |
| 875 | insn = SWAP_INT (insn); |
| 876 | |
| 877 | if (insn == 0xe1a0c00d) /* mov ip, sp */ |
| 878 | { |
| 879 | regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM]; |
| 880 | continue; |
| 881 | } |
| 882 | else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ |
| 883 | { |
| 884 | unsigned imm = insn & 0xff; /* immediate value */ |
| 885 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 886 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 887 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm); |
| 888 | continue; |
| 889 | } |
| 890 | else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ |
| 891 | { |
| 892 | unsigned imm = insn & 0xff; /* immediate value */ |
| 893 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 894 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 895 | regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
| 896 | continue; |
| 897 | } |
| 898 | else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */ |
| 899 | { |
| 900 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 901 | break; |
| 902 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); |
| 903 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]); |
| 904 | continue; |
| 905 | } |
| 906 | else if ((insn & 0xffff0000) == 0xe92d0000) |
| 907 | /* stmfd sp!, {..., fp, ip, lr, pc} |
| 908 | or |
| 909 | stmfd sp!, {a1, a2, a3, a4} */ |
| 910 | { |
| 911 | int mask = insn & 0xffff; |
| 912 | |
| 913 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 914 | break; |
| 915 | |
| 916 | /* Calculate offsets of saved registers. */ |
| 917 | for (regno = ARM_PC_REGNUM; regno >= 0; regno--) |
| 918 | if (mask & (1 << regno)) |
| 919 | { |
| 920 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4); |
| 921 | pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); |
| 922 | } |
| 923 | } |
| 924 | else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */ |
| 925 | (insn & 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */ |
| 926 | (insn & 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */ |
| 927 | { |
| 928 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 929 | continue; |
| 930 | } |
| 931 | else if ((insn & 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */ |
| 932 | (insn & 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */ |
| 933 | (insn & 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */ |
| 934 | { |
| 935 | /* No need to add this to saved_regs -- it's just an arg reg. */ |
| 936 | continue; |
| 937 | } |
| 938 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
| 939 | { |
| 940 | unsigned imm = insn & 0xff; /* immediate value */ |
| 941 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 942 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 943 | regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm); |
| 944 | } |
| 945 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ |
| 946 | { |
| 947 | unsigned imm = insn & 0xff; /* immediate value */ |
| 948 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ |
| 949 | imm = (imm >> rot) | (imm << (32 - rot)); |
| 950 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm); |
| 951 | } |
| 952 | else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */ |
| 953 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
| 954 | { |
| 955 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 956 | break; |
| 957 | |
| 958 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
| 959 | regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07); |
| 960 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]); |
| 961 | } |
| 962 | else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */ |
| 963 | && gdbarch_tdep (gdbarch)->have_fpa_registers) |
| 964 | { |
| 965 | int n_saved_fp_regs; |
| 966 | unsigned int fp_start_reg, fp_bound_reg; |
| 967 | |
| 968 | if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM])) |
| 969 | break; |
| 970 | |
| 971 | if ((insn & 0x800) == 0x800) /* N0 is set */ |
| 972 | { |
| 973 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 974 | n_saved_fp_regs = 3; |
| 975 | else |
| 976 | n_saved_fp_regs = 1; |
| 977 | } |
| 978 | else |
| 979 | { |
| 980 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ |
| 981 | n_saved_fp_regs = 2; |
| 982 | else |
| 983 | n_saved_fp_regs = 4; |
| 984 | } |
| 985 | |
| 986 | fp_start_reg = ARM_F0_REGNUM + ((insn >> 12) & 0x7); |
| 987 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; |
| 988 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) |
| 989 | { |
| 990 | regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12); |
| 991 | pv_area_store (stack, regs[ARM_SP_REGNUM], 12, |
| 992 | regs[fp_start_reg++]); |
| 993 | } |
| 994 | } |
| 995 | else if ((insn & 0xf0000000) != 0xe0000000) |
| 996 | break; /* Condition not true, exit early */ |
| 997 | else if ((insn & 0xfe200000) == 0xe8200000) /* ldm? */ |
| 998 | break; /* Don't scan past a block load */ |
| 999 | else |
| 1000 | /* The optimizer might shove anything into the prologue, |
| 1001 | so we just skip what we don't recognize. */ |
| 1002 | continue; |
| 1003 | } |
| 1004 | |
| 1005 | /* The frame size is just the distance from the frame register |
| 1006 | to the original stack pointer. */ |
| 1007 | if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) |
| 1008 | { |
| 1009 | /* Frame pointer is fp. */ |
| 1010 | cache->framereg = ARM_FP_REGNUM; |
| 1011 | cache->framesize = -regs[ARM_FP_REGNUM].k; |
| 1012 | } |
| 1013 | else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM)) |
| 1014 | { |
| 1015 | /* Try the stack pointer... this is a bit desperate. */ |
| 1016 | cache->framereg = ARM_SP_REGNUM; |
| 1017 | cache->framesize = -regs[ARM_SP_REGNUM].k; |
| 1018 | } |
| 1019 | else |
| 1020 | { |
| 1021 | /* We're just out of luck. We don't know where the frame is. */ |
| 1022 | cache->framereg = -1; |
| 1023 | cache->framesize = 0; |
| 1024 | } |
| 1025 | |
| 1026 | for (regno = 0; regno < ARM_FPS_REGNUM; regno++) |
| 1027 | if (pv_area_find_reg (stack, gdbarch, regno, &offset)) |
| 1028 | cache->saved_regs[regno].addr = offset; |
| 1029 | |
| 1030 | do_cleanups (back_to); |
| 1031 | } |
| 1032 | |
| 1033 | static struct arm_prologue_cache * |
| 1034 | arm_make_prologue_cache (struct frame_info *this_frame) |
| 1035 | { |
| 1036 | int reg; |
| 1037 | struct arm_prologue_cache *cache; |
| 1038 | CORE_ADDR unwound_fp; |
| 1039 | |
| 1040 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
| 1041 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1042 | |
| 1043 | arm_scan_prologue (this_frame, cache); |
| 1044 | |
| 1045 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); |
| 1046 | if (unwound_fp == 0) |
| 1047 | return cache; |
| 1048 | |
| 1049 | cache->prev_sp = unwound_fp + cache->framesize; |
| 1050 | |
| 1051 | /* Calculate actual addresses of saved registers using offsets |
| 1052 | determined by arm_scan_prologue. */ |
| 1053 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) |
| 1054 | if (trad_frame_addr_p (cache->saved_regs, reg)) |
| 1055 | cache->saved_regs[reg].addr += cache->prev_sp; |
| 1056 | |
| 1057 | return cache; |
| 1058 | } |
| 1059 | |
| 1060 | /* Our frame ID for a normal frame is the current function's starting PC |
| 1061 | and the caller's SP when we were called. */ |
| 1062 | |
| 1063 | static void |
| 1064 | arm_prologue_this_id (struct frame_info *this_frame, |
| 1065 | void **this_cache, |
| 1066 | struct frame_id *this_id) |
| 1067 | { |
| 1068 | struct arm_prologue_cache *cache; |
| 1069 | struct frame_id id; |
| 1070 | CORE_ADDR pc, func; |
| 1071 | |
| 1072 | if (*this_cache == NULL) |
| 1073 | *this_cache = arm_make_prologue_cache (this_frame); |
| 1074 | cache = *this_cache; |
| 1075 | |
| 1076 | /* This is meant to halt the backtrace at "_start". */ |
| 1077 | pc = get_frame_pc (this_frame); |
| 1078 | if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) |
| 1079 | return; |
| 1080 | |
| 1081 | /* If we've hit a wall, stop. */ |
| 1082 | if (cache->prev_sp == 0) |
| 1083 | return; |
| 1084 | |
| 1085 | func = get_frame_func (this_frame); |
| 1086 | id = frame_id_build (cache->prev_sp, func); |
| 1087 | *this_id = id; |
| 1088 | } |
| 1089 | |
| 1090 | static struct value * |
| 1091 | arm_prologue_prev_register (struct frame_info *this_frame, |
| 1092 | void **this_cache, |
| 1093 | int prev_regnum) |
| 1094 | { |
| 1095 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1096 | struct arm_prologue_cache *cache; |
| 1097 | |
| 1098 | if (*this_cache == NULL) |
| 1099 | *this_cache = arm_make_prologue_cache (this_frame); |
| 1100 | cache = *this_cache; |
| 1101 | |
| 1102 | /* If we are asked to unwind the PC, then we need to return the LR |
| 1103 | instead. The prologue may save PC, but it will point into this |
| 1104 | frame's prologue, not the next frame's resume location. Also |
| 1105 | strip the saved T bit. A valid LR may have the low bit set, but |
| 1106 | a valid PC never does. */ |
| 1107 | if (prev_regnum == ARM_PC_REGNUM) |
| 1108 | { |
| 1109 | CORE_ADDR lr; |
| 1110 | |
| 1111 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
| 1112 | return frame_unwind_got_constant (this_frame, prev_regnum, |
| 1113 | arm_addr_bits_remove (gdbarch, lr)); |
| 1114 | } |
| 1115 | |
| 1116 | /* SP is generally not saved to the stack, but this frame is |
| 1117 | identified by the next frame's stack pointer at the time of the call. |
| 1118 | The value was already reconstructed into PREV_SP. */ |
| 1119 | if (prev_regnum == ARM_SP_REGNUM) |
| 1120 | return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp); |
| 1121 | |
| 1122 | /* The CPSR may have been changed by the call instruction and by the |
| 1123 | called function. The only bit we can reconstruct is the T bit, |
| 1124 | by checking the low bit of LR as of the call. This is a reliable |
| 1125 | indicator of Thumb-ness except for some ARM v4T pre-interworking |
| 1126 | Thumb code, which could get away with a clear low bit as long as |
| 1127 | the called function did not use bx. Guess that all other |
| 1128 | bits are unchanged; the condition flags are presumably lost, |
| 1129 | but the processor status is likely valid. */ |
| 1130 | if (prev_regnum == ARM_PS_REGNUM) |
| 1131 | { |
| 1132 | CORE_ADDR lr, cpsr; |
| 1133 | |
| 1134 | cpsr = get_frame_register_unsigned (this_frame, prev_regnum); |
| 1135 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
| 1136 | if (IS_THUMB_ADDR (lr)) |
| 1137 | cpsr |= CPSR_T; |
| 1138 | else |
| 1139 | cpsr &= ~CPSR_T; |
| 1140 | return frame_unwind_got_constant (this_frame, prev_regnum, cpsr); |
| 1141 | } |
| 1142 | |
| 1143 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
| 1144 | prev_regnum); |
| 1145 | } |
| 1146 | |
| 1147 | struct frame_unwind arm_prologue_unwind = { |
| 1148 | NORMAL_FRAME, |
| 1149 | arm_prologue_this_id, |
| 1150 | arm_prologue_prev_register, |
| 1151 | NULL, |
| 1152 | default_frame_sniffer |
| 1153 | }; |
| 1154 | |
| 1155 | static struct arm_prologue_cache * |
| 1156 | arm_make_stub_cache (struct frame_info *this_frame) |
| 1157 | { |
| 1158 | int reg; |
| 1159 | struct arm_prologue_cache *cache; |
| 1160 | CORE_ADDR unwound_fp; |
| 1161 | |
| 1162 | cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); |
| 1163 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1164 | |
| 1165 | cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); |
| 1166 | |
| 1167 | return cache; |
| 1168 | } |
| 1169 | |
| 1170 | /* Our frame ID for a stub frame is the current SP and LR. */ |
| 1171 | |
| 1172 | static void |
| 1173 | arm_stub_this_id (struct frame_info *this_frame, |
| 1174 | void **this_cache, |
| 1175 | struct frame_id *this_id) |
| 1176 | { |
| 1177 | struct arm_prologue_cache *cache; |
| 1178 | |
| 1179 | if (*this_cache == NULL) |
| 1180 | *this_cache = arm_make_stub_cache (this_frame); |
| 1181 | cache = *this_cache; |
| 1182 | |
| 1183 | *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); |
| 1184 | } |
| 1185 | |
| 1186 | static int |
| 1187 | arm_stub_unwind_sniffer (const struct frame_unwind *self, |
| 1188 | struct frame_info *this_frame, |
| 1189 | void **this_prologue_cache) |
| 1190 | { |
| 1191 | CORE_ADDR addr_in_block; |
| 1192 | char dummy[4]; |
| 1193 | |
| 1194 | addr_in_block = get_frame_address_in_block (this_frame); |
| 1195 | if (in_plt_section (addr_in_block, NULL) |
| 1196 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
| 1197 | return 1; |
| 1198 | |
| 1199 | return 0; |
| 1200 | } |
| 1201 | |
| 1202 | struct frame_unwind arm_stub_unwind = { |
| 1203 | NORMAL_FRAME, |
| 1204 | arm_stub_this_id, |
| 1205 | arm_prologue_prev_register, |
| 1206 | NULL, |
| 1207 | arm_stub_unwind_sniffer |
| 1208 | }; |
| 1209 | |
| 1210 | static CORE_ADDR |
| 1211 | arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) |
| 1212 | { |
| 1213 | struct arm_prologue_cache *cache; |
| 1214 | |
| 1215 | if (*this_cache == NULL) |
| 1216 | *this_cache = arm_make_prologue_cache (this_frame); |
| 1217 | cache = *this_cache; |
| 1218 | |
| 1219 | return cache->prev_sp - cache->framesize; |
| 1220 | } |
| 1221 | |
| 1222 | struct frame_base arm_normal_base = { |
| 1223 | &arm_prologue_unwind, |
| 1224 | arm_normal_frame_base, |
| 1225 | arm_normal_frame_base, |
| 1226 | arm_normal_frame_base |
| 1227 | }; |
| 1228 | |
| 1229 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
| 1230 | dummy frame. The frame ID's base needs to match the TOS value |
| 1231 | saved by save_dummy_frame_tos() and returned from |
| 1232 | arm_push_dummy_call, and the PC needs to match the dummy frame's |
| 1233 | breakpoint. */ |
| 1234 | |
| 1235 | static struct frame_id |
| 1236 | arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1237 | { |
| 1238 | return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM), |
| 1239 | get_frame_pc (this_frame)); |
| 1240 | } |
| 1241 | |
| 1242 | /* Given THIS_FRAME, find the previous frame's resume PC (which will |
| 1243 | be used to construct the previous frame's ID, after looking up the |
| 1244 | containing function). */ |
| 1245 | |
| 1246 | static CORE_ADDR |
| 1247 | arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1248 | { |
| 1249 | CORE_ADDR pc; |
| 1250 | pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM); |
| 1251 | return arm_addr_bits_remove (gdbarch, pc); |
| 1252 | } |
| 1253 | |
| 1254 | static CORE_ADDR |
| 1255 | arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1256 | { |
| 1257 | return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM); |
| 1258 | } |
| 1259 | |
| 1260 | static struct value * |
| 1261 | arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, |
| 1262 | int regnum) |
| 1263 | { |
| 1264 | struct gdbarch * gdbarch = get_frame_arch (this_frame); |
| 1265 | CORE_ADDR lr, cpsr; |
| 1266 | |
| 1267 | switch (regnum) |
| 1268 | { |
| 1269 | case ARM_PC_REGNUM: |
| 1270 | /* The PC is normally copied from the return column, which |
| 1271 | describes saves of LR. However, that version may have an |
| 1272 | extra bit set to indicate Thumb state. The bit is not |
| 1273 | part of the PC. */ |
| 1274 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
| 1275 | return frame_unwind_got_constant (this_frame, regnum, |
| 1276 | arm_addr_bits_remove (gdbarch, lr)); |
| 1277 | |
| 1278 | case ARM_PS_REGNUM: |
| 1279 | /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ |
| 1280 | cpsr = get_frame_register_unsigned (this_frame, regnum); |
| 1281 | lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); |
| 1282 | if (IS_THUMB_ADDR (lr)) |
| 1283 | cpsr |= CPSR_T; |
| 1284 | else |
| 1285 | cpsr &= ~CPSR_T; |
| 1286 | return frame_unwind_got_constant (this_frame, regnum, cpsr); |
| 1287 | |
| 1288 | default: |
| 1289 | internal_error (__FILE__, __LINE__, |
| 1290 | _("Unexpected register %d"), regnum); |
| 1291 | } |
| 1292 | } |
| 1293 | |
| 1294 | static void |
| 1295 | arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, |
| 1296 | struct dwarf2_frame_state_reg *reg, |
| 1297 | struct frame_info *this_frame) |
| 1298 | { |
| 1299 | switch (regnum) |
| 1300 | { |
| 1301 | case ARM_PC_REGNUM: |
| 1302 | case ARM_PS_REGNUM: |
| 1303 | reg->how = DWARF2_FRAME_REG_FN; |
| 1304 | reg->loc.fn = arm_dwarf2_prev_register; |
| 1305 | break; |
| 1306 | case ARM_SP_REGNUM: |
| 1307 | reg->how = DWARF2_FRAME_REG_CFA; |
| 1308 | break; |
| 1309 | } |
| 1310 | } |
| 1311 | |
| 1312 | /* When arguments must be pushed onto the stack, they go on in reverse |
| 1313 | order. The code below implements a FILO (stack) to do this. */ |
| 1314 | |
| 1315 | struct stack_item |
| 1316 | { |
| 1317 | int len; |
| 1318 | struct stack_item *prev; |
| 1319 | void *data; |
| 1320 | }; |
| 1321 | |
| 1322 | static struct stack_item * |
| 1323 | push_stack_item (struct stack_item *prev, void *contents, int len) |
| 1324 | { |
| 1325 | struct stack_item *si; |
| 1326 | si = xmalloc (sizeof (struct stack_item)); |
| 1327 | si->data = xmalloc (len); |
| 1328 | si->len = len; |
| 1329 | si->prev = prev; |
| 1330 | memcpy (si->data, contents, len); |
| 1331 | return si; |
| 1332 | } |
| 1333 | |
| 1334 | static struct stack_item * |
| 1335 | pop_stack_item (struct stack_item *si) |
| 1336 | { |
| 1337 | struct stack_item *dead = si; |
| 1338 | si = si->prev; |
| 1339 | xfree (dead->data); |
| 1340 | xfree (dead); |
| 1341 | return si; |
| 1342 | } |
| 1343 | |
| 1344 | |
| 1345 | /* Return the alignment (in bytes) of the given type. */ |
| 1346 | |
| 1347 | static int |
| 1348 | arm_type_align (struct type *t) |
| 1349 | { |
| 1350 | int n; |
| 1351 | int align; |
| 1352 | int falign; |
| 1353 | |
| 1354 | t = check_typedef (t); |
| 1355 | switch (TYPE_CODE (t)) |
| 1356 | { |
| 1357 | default: |
| 1358 | /* Should never happen. */ |
| 1359 | internal_error (__FILE__, __LINE__, _("unknown type alignment")); |
| 1360 | return 4; |
| 1361 | |
| 1362 | case TYPE_CODE_PTR: |
| 1363 | case TYPE_CODE_ENUM: |
| 1364 | case TYPE_CODE_INT: |
| 1365 | case TYPE_CODE_FLT: |
| 1366 | case TYPE_CODE_SET: |
| 1367 | case TYPE_CODE_RANGE: |
| 1368 | case TYPE_CODE_BITSTRING: |
| 1369 | case TYPE_CODE_REF: |
| 1370 | case TYPE_CODE_CHAR: |
| 1371 | case TYPE_CODE_BOOL: |
| 1372 | return TYPE_LENGTH (t); |
| 1373 | |
| 1374 | case TYPE_CODE_ARRAY: |
| 1375 | case TYPE_CODE_COMPLEX: |
| 1376 | /* TODO: What about vector types? */ |
| 1377 | return arm_type_align (TYPE_TARGET_TYPE (t)); |
| 1378 | |
| 1379 | case TYPE_CODE_STRUCT: |
| 1380 | case TYPE_CODE_UNION: |
| 1381 | align = 1; |
| 1382 | for (n = 0; n < TYPE_NFIELDS (t); n++) |
| 1383 | { |
| 1384 | falign = arm_type_align (TYPE_FIELD_TYPE (t, n)); |
| 1385 | if (falign > align) |
| 1386 | align = falign; |
| 1387 | } |
| 1388 | return align; |
| 1389 | } |
| 1390 | } |
| 1391 | |
| 1392 | /* We currently only support passing parameters in integer registers. This |
| 1393 | conforms with GCC's default model. Several other variants exist and |
| 1394 | we should probably support some of them based on the selected ABI. */ |
| 1395 | |
| 1396 | static CORE_ADDR |
| 1397 | arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1398 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
| 1399 | struct value **args, CORE_ADDR sp, int struct_return, |
| 1400 | CORE_ADDR struct_addr) |
| 1401 | { |
| 1402 | int argnum; |
| 1403 | int argreg; |
| 1404 | int nstack; |
| 1405 | struct stack_item *si = NULL; |
| 1406 | |
| 1407 | /* Set the return address. For the ARM, the return breakpoint is |
| 1408 | always at BP_ADDR. */ |
| 1409 | /* XXX Fix for Thumb. */ |
| 1410 | regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr); |
| 1411 | |
| 1412 | /* Walk through the list of args and determine how large a temporary |
| 1413 | stack is required. Need to take care here as structs may be |
| 1414 | passed on the stack, and we have to to push them. */ |
| 1415 | nstack = 0; |
| 1416 | |
| 1417 | argreg = ARM_A1_REGNUM; |
| 1418 | nstack = 0; |
| 1419 | |
| 1420 | /* The struct_return pointer occupies the first parameter |
| 1421 | passing register. */ |
| 1422 | if (struct_return) |
| 1423 | { |
| 1424 | if (arm_debug) |
| 1425 | fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n", |
| 1426 | gdbarch_register_name (gdbarch, argreg), |
| 1427 | paddr (struct_addr)); |
| 1428 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); |
| 1429 | argreg++; |
| 1430 | } |
| 1431 | |
| 1432 | for (argnum = 0; argnum < nargs; argnum++) |
| 1433 | { |
| 1434 | int len; |
| 1435 | struct type *arg_type; |
| 1436 | struct type *target_type; |
| 1437 | enum type_code typecode; |
| 1438 | bfd_byte *val; |
| 1439 | int align; |
| 1440 | |
| 1441 | arg_type = check_typedef (value_type (args[argnum])); |
| 1442 | len = TYPE_LENGTH (arg_type); |
| 1443 | target_type = TYPE_TARGET_TYPE (arg_type); |
| 1444 | typecode = TYPE_CODE (arg_type); |
| 1445 | val = value_contents_writeable (args[argnum]); |
| 1446 | |
| 1447 | align = arm_type_align (arg_type); |
| 1448 | /* Round alignment up to a whole number of words. */ |
| 1449 | align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1); |
| 1450 | /* Different ABIs have different maximum alignments. */ |
| 1451 | if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS) |
| 1452 | { |
| 1453 | /* The APCS ABI only requires word alignment. */ |
| 1454 | align = INT_REGISTER_SIZE; |
| 1455 | } |
| 1456 | else |
| 1457 | { |
| 1458 | /* The AAPCS requires at most doubleword alignment. */ |
| 1459 | if (align > INT_REGISTER_SIZE * 2) |
| 1460 | align = INT_REGISTER_SIZE * 2; |
| 1461 | } |
| 1462 | |
| 1463 | /* Push stack padding for dowubleword alignment. */ |
| 1464 | if (nstack & (align - 1)) |
| 1465 | { |
| 1466 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
| 1467 | nstack += INT_REGISTER_SIZE; |
| 1468 | } |
| 1469 | |
| 1470 | /* Doubleword aligned quantities must go in even register pairs. */ |
| 1471 | if (argreg <= ARM_LAST_ARG_REGNUM |
| 1472 | && align > INT_REGISTER_SIZE |
| 1473 | && argreg & 1) |
| 1474 | argreg++; |
| 1475 | |
| 1476 | /* If the argument is a pointer to a function, and it is a |
| 1477 | Thumb function, create a LOCAL copy of the value and set |
| 1478 | the THUMB bit in it. */ |
| 1479 | if (TYPE_CODE_PTR == typecode |
| 1480 | && target_type != NULL |
| 1481 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) |
| 1482 | { |
| 1483 | CORE_ADDR regval = extract_unsigned_integer (val, len); |
| 1484 | if (arm_pc_is_thumb (regval)) |
| 1485 | { |
| 1486 | val = alloca (len); |
| 1487 | store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval)); |
| 1488 | } |
| 1489 | } |
| 1490 | |
| 1491 | /* Copy the argument to general registers or the stack in |
| 1492 | register-sized pieces. Large arguments are split between |
| 1493 | registers and stack. */ |
| 1494 | while (len > 0) |
| 1495 | { |
| 1496 | int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; |
| 1497 | |
| 1498 | if (argreg <= ARM_LAST_ARG_REGNUM) |
| 1499 | { |
| 1500 | /* The argument is being passed in a general purpose |
| 1501 | register. */ |
| 1502 | CORE_ADDR regval = extract_unsigned_integer (val, partial_len); |
| 1503 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
| 1504 | regval <<= (INT_REGISTER_SIZE - partial_len) * 8; |
| 1505 | if (arm_debug) |
| 1506 | fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n", |
| 1507 | argnum, |
| 1508 | gdbarch_register_name |
| 1509 | (gdbarch, argreg), |
| 1510 | phex (regval, INT_REGISTER_SIZE)); |
| 1511 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 1512 | argreg++; |
| 1513 | } |
| 1514 | else |
| 1515 | { |
| 1516 | /* Push the arguments onto the stack. */ |
| 1517 | if (arm_debug) |
| 1518 | fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", |
| 1519 | argnum, nstack); |
| 1520 | si = push_stack_item (si, val, INT_REGISTER_SIZE); |
| 1521 | nstack += INT_REGISTER_SIZE; |
| 1522 | } |
| 1523 | |
| 1524 | len -= partial_len; |
| 1525 | val += partial_len; |
| 1526 | } |
| 1527 | } |
| 1528 | /* If we have an odd number of words to push, then decrement the stack |
| 1529 | by one word now, so first stack argument will be dword aligned. */ |
| 1530 | if (nstack & 4) |
| 1531 | sp -= 4; |
| 1532 | |
| 1533 | while (si) |
| 1534 | { |
| 1535 | sp -= si->len; |
| 1536 | write_memory (sp, si->data, si->len); |
| 1537 | si = pop_stack_item (si); |
| 1538 | } |
| 1539 | |
| 1540 | /* Finally, update teh SP register. */ |
| 1541 | regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp); |
| 1542 | |
| 1543 | return sp; |
| 1544 | } |
| 1545 | |
| 1546 | |
| 1547 | /* Always align the frame to an 8-byte boundary. This is required on |
| 1548 | some platforms and harmless on the rest. */ |
| 1549 | |
| 1550 | static CORE_ADDR |
| 1551 | arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 1552 | { |
| 1553 | /* Align the stack to eight bytes. */ |
| 1554 | return sp & ~ (CORE_ADDR) 7; |
| 1555 | } |
| 1556 | |
| 1557 | static void |
| 1558 | print_fpu_flags (int flags) |
| 1559 | { |
| 1560 | if (flags & (1 << 0)) |
| 1561 | fputs ("IVO ", stdout); |
| 1562 | if (flags & (1 << 1)) |
| 1563 | fputs ("DVZ ", stdout); |
| 1564 | if (flags & (1 << 2)) |
| 1565 | fputs ("OFL ", stdout); |
| 1566 | if (flags & (1 << 3)) |
| 1567 | fputs ("UFL ", stdout); |
| 1568 | if (flags & (1 << 4)) |
| 1569 | fputs ("INX ", stdout); |
| 1570 | putchar ('\n'); |
| 1571 | } |
| 1572 | |
| 1573 | /* Print interesting information about the floating point processor |
| 1574 | (if present) or emulator. */ |
| 1575 | static void |
| 1576 | arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
| 1577 | struct frame_info *frame, const char *args) |
| 1578 | { |
| 1579 | unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM); |
| 1580 | int type; |
| 1581 | |
| 1582 | type = (status >> 24) & 127; |
| 1583 | if (status & (1 << 31)) |
| 1584 | printf (_("Hardware FPU type %d\n"), type); |
| 1585 | else |
| 1586 | printf (_("Software FPU type %d\n"), type); |
| 1587 | /* i18n: [floating point unit] mask */ |
| 1588 | fputs (_("mask: "), stdout); |
| 1589 | print_fpu_flags (status >> 16); |
| 1590 | /* i18n: [floating point unit] flags */ |
| 1591 | fputs (_("flags: "), stdout); |
| 1592 | print_fpu_flags (status); |
| 1593 | } |
| 1594 | |
| 1595 | /* Return the GDB type object for the "standard" data type of data in |
| 1596 | register N. */ |
| 1597 | |
| 1598 | static struct type * |
| 1599 | arm_register_type (struct gdbarch *gdbarch, int regnum) |
| 1600 | { |
| 1601 | if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS) |
| 1602 | return builtin_type_arm_ext; |
| 1603 | else if (regnum == ARM_SP_REGNUM) |
| 1604 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 1605 | else if (regnum == ARM_PC_REGNUM) |
| 1606 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 1607 | else if (regnum >= ARRAY_SIZE (arm_register_names)) |
| 1608 | /* These registers are only supported on targets which supply |
| 1609 | an XML description. */ |
| 1610 | return builtin_type_int0; |
| 1611 | else |
| 1612 | return builtin_type_uint32; |
| 1613 | } |
| 1614 | |
| 1615 | /* Map a DWARF register REGNUM onto the appropriate GDB register |
| 1616 | number. */ |
| 1617 | |
| 1618 | static int |
| 1619 | arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 1620 | { |
| 1621 | /* Core integer regs. */ |
| 1622 | if (reg >= 0 && reg <= 15) |
| 1623 | return reg; |
| 1624 | |
| 1625 | /* Legacy FPA encoding. These were once used in a way which |
| 1626 | overlapped with VFP register numbering, so their use is |
| 1627 | discouraged, but GDB doesn't support the ARM toolchain |
| 1628 | which used them for VFP. */ |
| 1629 | if (reg >= 16 && reg <= 23) |
| 1630 | return ARM_F0_REGNUM + reg - 16; |
| 1631 | |
| 1632 | /* New assignments for the FPA registers. */ |
| 1633 | if (reg >= 96 && reg <= 103) |
| 1634 | return ARM_F0_REGNUM + reg - 96; |
| 1635 | |
| 1636 | /* WMMX register assignments. */ |
| 1637 | if (reg >= 104 && reg <= 111) |
| 1638 | return ARM_WCGR0_REGNUM + reg - 104; |
| 1639 | |
| 1640 | if (reg >= 112 && reg <= 127) |
| 1641 | return ARM_WR0_REGNUM + reg - 112; |
| 1642 | |
| 1643 | if (reg >= 192 && reg <= 199) |
| 1644 | return ARM_WC0_REGNUM + reg - 192; |
| 1645 | |
| 1646 | return -1; |
| 1647 | } |
| 1648 | |
| 1649 | /* Map GDB internal REGNUM onto the Arm simulator register numbers. */ |
| 1650 | static int |
| 1651 | arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
| 1652 | { |
| 1653 | int reg = regnum; |
| 1654 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
| 1655 | |
| 1656 | if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) |
| 1657 | return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; |
| 1658 | |
| 1659 | if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) |
| 1660 | return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; |
| 1661 | |
| 1662 | if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) |
| 1663 | return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; |
| 1664 | |
| 1665 | if (reg < NUM_GREGS) |
| 1666 | return SIM_ARM_R0_REGNUM + reg; |
| 1667 | reg -= NUM_GREGS; |
| 1668 | |
| 1669 | if (reg < NUM_FREGS) |
| 1670 | return SIM_ARM_FP0_REGNUM + reg; |
| 1671 | reg -= NUM_FREGS; |
| 1672 | |
| 1673 | if (reg < NUM_SREGS) |
| 1674 | return SIM_ARM_FPS_REGNUM + reg; |
| 1675 | reg -= NUM_SREGS; |
| 1676 | |
| 1677 | internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); |
| 1678 | } |
| 1679 | |
| 1680 | /* NOTE: cagney/2001-08-20: Both convert_from_extended() and |
| 1681 | convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. |
| 1682 | It is thought that this is is the floating-point register format on |
| 1683 | little-endian systems. */ |
| 1684 | |
| 1685 | static void |
| 1686 | convert_from_extended (const struct floatformat *fmt, const void *ptr, |
| 1687 | void *dbl, int endianess) |
| 1688 | { |
| 1689 | DOUBLEST d; |
| 1690 | |
| 1691 | if (endianess == BFD_ENDIAN_BIG) |
| 1692 | floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); |
| 1693 | else |
| 1694 | floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 1695 | ptr, &d); |
| 1696 | floatformat_from_doublest (fmt, &d, dbl); |
| 1697 | } |
| 1698 | |
| 1699 | static void |
| 1700 | convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, |
| 1701 | int endianess) |
| 1702 | { |
| 1703 | DOUBLEST d; |
| 1704 | |
| 1705 | floatformat_to_doublest (fmt, ptr, &d); |
| 1706 | if (endianess == BFD_ENDIAN_BIG) |
| 1707 | floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); |
| 1708 | else |
| 1709 | floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, |
| 1710 | &d, dbl); |
| 1711 | } |
| 1712 | |
| 1713 | static int |
| 1714 | condition_true (unsigned long cond, unsigned long status_reg) |
| 1715 | { |
| 1716 | if (cond == INST_AL || cond == INST_NV) |
| 1717 | return 1; |
| 1718 | |
| 1719 | switch (cond) |
| 1720 | { |
| 1721 | case INST_EQ: |
| 1722 | return ((status_reg & FLAG_Z) != 0); |
| 1723 | case INST_NE: |
| 1724 | return ((status_reg & FLAG_Z) == 0); |
| 1725 | case INST_CS: |
| 1726 | return ((status_reg & FLAG_C) != 0); |
| 1727 | case INST_CC: |
| 1728 | return ((status_reg & FLAG_C) == 0); |
| 1729 | case INST_MI: |
| 1730 | return ((status_reg & FLAG_N) != 0); |
| 1731 | case INST_PL: |
| 1732 | return ((status_reg & FLAG_N) == 0); |
| 1733 | case INST_VS: |
| 1734 | return ((status_reg & FLAG_V) != 0); |
| 1735 | case INST_VC: |
| 1736 | return ((status_reg & FLAG_V) == 0); |
| 1737 | case INST_HI: |
| 1738 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); |
| 1739 | case INST_LS: |
| 1740 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); |
| 1741 | case INST_GE: |
| 1742 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); |
| 1743 | case INST_LT: |
| 1744 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); |
| 1745 | case INST_GT: |
| 1746 | return (((status_reg & FLAG_Z) == 0) && |
| 1747 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
| 1748 | case INST_LE: |
| 1749 | return (((status_reg & FLAG_Z) != 0) || |
| 1750 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
| 1751 | } |
| 1752 | return 1; |
| 1753 | } |
| 1754 | |
| 1755 | /* Support routines for single stepping. Calculate the next PC value. */ |
| 1756 | #define submask(x) ((1L << ((x) + 1)) - 1) |
| 1757 | #define bit(obj,st) (((obj) >> (st)) & 1) |
| 1758 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) |
| 1759 | #define sbits(obj,st,fn) \ |
| 1760 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) |
| 1761 | #define BranchDest(addr,instr) \ |
| 1762 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) |
| 1763 | #define ARM_PC_32 1 |
| 1764 | |
| 1765 | static unsigned long |
| 1766 | shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, |
| 1767 | unsigned long pc_val, unsigned long status_reg) |
| 1768 | { |
| 1769 | unsigned long res, shift; |
| 1770 | int rm = bits (inst, 0, 3); |
| 1771 | unsigned long shifttype = bits (inst, 5, 6); |
| 1772 | |
| 1773 | if (bit (inst, 4)) |
| 1774 | { |
| 1775 | int rs = bits (inst, 8, 11); |
| 1776 | shift = (rs == 15 ? pc_val + 8 |
| 1777 | : get_frame_register_unsigned (frame, rs)) & 0xFF; |
| 1778 | } |
| 1779 | else |
| 1780 | shift = bits (inst, 7, 11); |
| 1781 | |
| 1782 | res = (rm == 15 |
| 1783 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
| 1784 | + (bit (inst, 4) ? 12 : 8)) |
| 1785 | : get_frame_register_unsigned (frame, rm)); |
| 1786 | |
| 1787 | switch (shifttype) |
| 1788 | { |
| 1789 | case 0: /* LSL */ |
| 1790 | res = shift >= 32 ? 0 : res << shift; |
| 1791 | break; |
| 1792 | |
| 1793 | case 1: /* LSR */ |
| 1794 | res = shift >= 32 ? 0 : res >> shift; |
| 1795 | break; |
| 1796 | |
| 1797 | case 2: /* ASR */ |
| 1798 | if (shift >= 32) |
| 1799 | shift = 31; |
| 1800 | res = ((res & 0x80000000L) |
| 1801 | ? ~((~res) >> shift) : res >> shift); |
| 1802 | break; |
| 1803 | |
| 1804 | case 3: /* ROR/RRX */ |
| 1805 | shift &= 31; |
| 1806 | if (shift == 0) |
| 1807 | res = (res >> 1) | (carry ? 0x80000000L : 0); |
| 1808 | else |
| 1809 | res = (res >> shift) | (res << (32 - shift)); |
| 1810 | break; |
| 1811 | } |
| 1812 | |
| 1813 | return res & 0xffffffff; |
| 1814 | } |
| 1815 | |
| 1816 | /* Return number of 1-bits in VAL. */ |
| 1817 | |
| 1818 | static int |
| 1819 | bitcount (unsigned long val) |
| 1820 | { |
| 1821 | int nbits; |
| 1822 | for (nbits = 0; val != 0; nbits++) |
| 1823 | val &= val - 1; /* delete rightmost 1-bit in val */ |
| 1824 | return nbits; |
| 1825 | } |
| 1826 | |
| 1827 | static CORE_ADDR |
| 1828 | thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 1829 | { |
| 1830 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1831 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
| 1832 | unsigned short inst1 = read_memory_unsigned_integer (pc, 2); |
| 1833 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
| 1834 | unsigned long offset; |
| 1835 | |
| 1836 | if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch)) |
| 1837 | inst1 = SWAP_SHORT (inst1); |
| 1838 | |
| 1839 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ |
| 1840 | { |
| 1841 | CORE_ADDR sp; |
| 1842 | |
| 1843 | /* Fetch the saved PC from the stack. It's stored above |
| 1844 | all of the other registers. */ |
| 1845 | offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; |
| 1846 | sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); |
| 1847 | nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4); |
| 1848 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 1849 | if (nextpc == pc) |
| 1850 | error (_("Infinite loop detected")); |
| 1851 | } |
| 1852 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ |
| 1853 | { |
| 1854 | unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
| 1855 | unsigned long cond = bits (inst1, 8, 11); |
| 1856 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
| 1857 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); |
| 1858 | } |
| 1859 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ |
| 1860 | { |
| 1861 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); |
| 1862 | } |
| 1863 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ |
| 1864 | { |
| 1865 | unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2); |
| 1866 | if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch)) |
| 1867 | inst2 = SWAP_SHORT (inst2); |
| 1868 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
| 1869 | nextpc = pc_val + offset; |
| 1870 | /* For BLX make sure to clear the low bits. */ |
| 1871 | if (bits (inst2, 11, 12) == 1) |
| 1872 | nextpc = nextpc & 0xfffffffc; |
| 1873 | } |
| 1874 | else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ |
| 1875 | { |
| 1876 | if (bits (inst1, 3, 6) == 0x0f) |
| 1877 | nextpc = pc_val; |
| 1878 | else |
| 1879 | nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); |
| 1880 | |
| 1881 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 1882 | if (nextpc == pc) |
| 1883 | error (_("Infinite loop detected")); |
| 1884 | } |
| 1885 | |
| 1886 | return nextpc; |
| 1887 | } |
| 1888 | |
| 1889 | CORE_ADDR |
| 1890 | arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 1891 | { |
| 1892 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1893 | unsigned long pc_val; |
| 1894 | unsigned long this_instr; |
| 1895 | unsigned long status; |
| 1896 | CORE_ADDR nextpc; |
| 1897 | |
| 1898 | if (arm_frame_is_thumb (frame)) |
| 1899 | return thumb_get_next_pc (frame, pc); |
| 1900 | |
| 1901 | pc_val = (unsigned long) pc; |
| 1902 | this_instr = read_memory_unsigned_integer (pc, 4); |
| 1903 | |
| 1904 | if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch)) |
| 1905 | this_instr = SWAP_INT (this_instr); |
| 1906 | |
| 1907 | status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); |
| 1908 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
| 1909 | |
| 1910 | if (bits (this_instr, 28, 31) == INST_NV) |
| 1911 | switch (bits (this_instr, 24, 27)) |
| 1912 | { |
| 1913 | case 0xa: |
| 1914 | case 0xb: |
| 1915 | { |
| 1916 | /* Branch with Link and change to Thumb. */ |
| 1917 | nextpc = BranchDest (pc, this_instr); |
| 1918 | nextpc |= bit (this_instr, 24) << 1; |
| 1919 | |
| 1920 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 1921 | if (nextpc == pc) |
| 1922 | error (_("Infinite loop detected")); |
| 1923 | break; |
| 1924 | } |
| 1925 | case 0xc: |
| 1926 | case 0xd: |
| 1927 | case 0xe: |
| 1928 | /* Coprocessor register transfer. */ |
| 1929 | if (bits (this_instr, 12, 15) == 15) |
| 1930 | error (_("Invalid update to pc in instruction")); |
| 1931 | break; |
| 1932 | } |
| 1933 | else if (condition_true (bits (this_instr, 28, 31), status)) |
| 1934 | { |
| 1935 | switch (bits (this_instr, 24, 27)) |
| 1936 | { |
| 1937 | case 0x0: |
| 1938 | case 0x1: /* data processing */ |
| 1939 | case 0x2: |
| 1940 | case 0x3: |
| 1941 | { |
| 1942 | unsigned long operand1, operand2, result = 0; |
| 1943 | unsigned long rn; |
| 1944 | int c; |
| 1945 | |
| 1946 | if (bits (this_instr, 12, 15) != 15) |
| 1947 | break; |
| 1948 | |
| 1949 | if (bits (this_instr, 22, 25) == 0 |
| 1950 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
| 1951 | error (_("Invalid update to pc in instruction")); |
| 1952 | |
| 1953 | /* BX <reg>, BLX <reg> */ |
| 1954 | if (bits (this_instr, 4, 27) == 0x12fff1 |
| 1955 | || bits (this_instr, 4, 27) == 0x12fff3) |
| 1956 | { |
| 1957 | rn = bits (this_instr, 0, 3); |
| 1958 | result = (rn == 15) ? pc_val + 8 |
| 1959 | : get_frame_register_unsigned (frame, rn); |
| 1960 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
| 1961 | (gdbarch, result); |
| 1962 | |
| 1963 | if (nextpc == pc) |
| 1964 | error (_("Infinite loop detected")); |
| 1965 | |
| 1966 | return nextpc; |
| 1967 | } |
| 1968 | |
| 1969 | /* Multiply into PC */ |
| 1970 | c = (status & FLAG_C) ? 1 : 0; |
| 1971 | rn = bits (this_instr, 16, 19); |
| 1972 | operand1 = (rn == 15) ? pc_val + 8 |
| 1973 | : get_frame_register_unsigned (frame, rn); |
| 1974 | |
| 1975 | if (bit (this_instr, 25)) |
| 1976 | { |
| 1977 | unsigned long immval = bits (this_instr, 0, 7); |
| 1978 | unsigned long rotate = 2 * bits (this_instr, 8, 11); |
| 1979 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
| 1980 | & 0xffffffff; |
| 1981 | } |
| 1982 | else /* operand 2 is a shifted register */ |
| 1983 | operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status); |
| 1984 | |
| 1985 | switch (bits (this_instr, 21, 24)) |
| 1986 | { |
| 1987 | case 0x0: /*and */ |
| 1988 | result = operand1 & operand2; |
| 1989 | break; |
| 1990 | |
| 1991 | case 0x1: /*eor */ |
| 1992 | result = operand1 ^ operand2; |
| 1993 | break; |
| 1994 | |
| 1995 | case 0x2: /*sub */ |
| 1996 | result = operand1 - operand2; |
| 1997 | break; |
| 1998 | |
| 1999 | case 0x3: /*rsb */ |
| 2000 | result = operand2 - operand1; |
| 2001 | break; |
| 2002 | |
| 2003 | case 0x4: /*add */ |
| 2004 | result = operand1 + operand2; |
| 2005 | break; |
| 2006 | |
| 2007 | case 0x5: /*adc */ |
| 2008 | result = operand1 + operand2 + c; |
| 2009 | break; |
| 2010 | |
| 2011 | case 0x6: /*sbc */ |
| 2012 | result = operand1 - operand2 + c; |
| 2013 | break; |
| 2014 | |
| 2015 | case 0x7: /*rsc */ |
| 2016 | result = operand2 - operand1 + c; |
| 2017 | break; |
| 2018 | |
| 2019 | case 0x8: |
| 2020 | case 0x9: |
| 2021 | case 0xa: |
| 2022 | case 0xb: /* tst, teq, cmp, cmn */ |
| 2023 | result = (unsigned long) nextpc; |
| 2024 | break; |
| 2025 | |
| 2026 | case 0xc: /*orr */ |
| 2027 | result = operand1 | operand2; |
| 2028 | break; |
| 2029 | |
| 2030 | case 0xd: /*mov */ |
| 2031 | /* Always step into a function. */ |
| 2032 | result = operand2; |
| 2033 | break; |
| 2034 | |
| 2035 | case 0xe: /*bic */ |
| 2036 | result = operand1 & ~operand2; |
| 2037 | break; |
| 2038 | |
| 2039 | case 0xf: /*mvn */ |
| 2040 | result = ~operand2; |
| 2041 | break; |
| 2042 | } |
| 2043 | nextpc = (CORE_ADDR) gdbarch_addr_bits_remove |
| 2044 | (gdbarch, result); |
| 2045 | |
| 2046 | if (nextpc == pc) |
| 2047 | error (_("Infinite loop detected")); |
| 2048 | break; |
| 2049 | } |
| 2050 | |
| 2051 | case 0x4: |
| 2052 | case 0x5: /* data transfer */ |
| 2053 | case 0x6: |
| 2054 | case 0x7: |
| 2055 | if (bit (this_instr, 20)) |
| 2056 | { |
| 2057 | /* load */ |
| 2058 | if (bits (this_instr, 12, 15) == 15) |
| 2059 | { |
| 2060 | /* rd == pc */ |
| 2061 | unsigned long rn; |
| 2062 | unsigned long base; |
| 2063 | |
| 2064 | if (bit (this_instr, 22)) |
| 2065 | error (_("Invalid update to pc in instruction")); |
| 2066 | |
| 2067 | /* byte write to PC */ |
| 2068 | rn = bits (this_instr, 16, 19); |
| 2069 | base = (rn == 15) ? pc_val + 8 |
| 2070 | : get_frame_register_unsigned (frame, rn); |
| 2071 | if (bit (this_instr, 24)) |
| 2072 | { |
| 2073 | /* pre-indexed */ |
| 2074 | int c = (status & FLAG_C) ? 1 : 0; |
| 2075 | unsigned long offset = |
| 2076 | (bit (this_instr, 25) |
| 2077 | ? shifted_reg_val (frame, this_instr, c, pc_val, status) |
| 2078 | : bits (this_instr, 0, 11)); |
| 2079 | |
| 2080 | if (bit (this_instr, 23)) |
| 2081 | base += offset; |
| 2082 | else |
| 2083 | base -= offset; |
| 2084 | } |
| 2085 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
| 2086 | 4); |
| 2087 | |
| 2088 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 2089 | |
| 2090 | if (nextpc == pc) |
| 2091 | error (_("Infinite loop detected")); |
| 2092 | } |
| 2093 | } |
| 2094 | break; |
| 2095 | |
| 2096 | case 0x8: |
| 2097 | case 0x9: /* block transfer */ |
| 2098 | if (bit (this_instr, 20)) |
| 2099 | { |
| 2100 | /* LDM */ |
| 2101 | if (bit (this_instr, 15)) |
| 2102 | { |
| 2103 | /* loading pc */ |
| 2104 | int offset = 0; |
| 2105 | |
| 2106 | if (bit (this_instr, 23)) |
| 2107 | { |
| 2108 | /* up */ |
| 2109 | unsigned long reglist = bits (this_instr, 0, 14); |
| 2110 | offset = bitcount (reglist) * 4; |
| 2111 | if (bit (this_instr, 24)) /* pre */ |
| 2112 | offset += 4; |
| 2113 | } |
| 2114 | else if (bit (this_instr, 24)) |
| 2115 | offset = -4; |
| 2116 | |
| 2117 | { |
| 2118 | unsigned long rn_val = |
| 2119 | get_frame_register_unsigned (frame, |
| 2120 | bits (this_instr, 16, 19)); |
| 2121 | nextpc = |
| 2122 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val |
| 2123 | + offset), |
| 2124 | 4); |
| 2125 | } |
| 2126 | nextpc = gdbarch_addr_bits_remove |
| 2127 | (gdbarch, nextpc); |
| 2128 | if (nextpc == pc) |
| 2129 | error (_("Infinite loop detected")); |
| 2130 | } |
| 2131 | } |
| 2132 | break; |
| 2133 | |
| 2134 | case 0xb: /* branch & link */ |
| 2135 | case 0xa: /* branch */ |
| 2136 | { |
| 2137 | nextpc = BranchDest (pc, this_instr); |
| 2138 | |
| 2139 | nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc); |
| 2140 | if (nextpc == pc) |
| 2141 | error (_("Infinite loop detected")); |
| 2142 | break; |
| 2143 | } |
| 2144 | |
| 2145 | case 0xc: |
| 2146 | case 0xd: |
| 2147 | case 0xe: /* coproc ops */ |
| 2148 | case 0xf: /* SWI */ |
| 2149 | break; |
| 2150 | |
| 2151 | default: |
| 2152 | fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); |
| 2153 | return (pc); |
| 2154 | } |
| 2155 | } |
| 2156 | |
| 2157 | return nextpc; |
| 2158 | } |
| 2159 | |
| 2160 | /* single_step() is called just before we want to resume the inferior, |
| 2161 | if we want to single-step it but there is no hardware or kernel |
| 2162 | single-step support. We find the target of the coming instruction |
| 2163 | and breakpoint it. */ |
| 2164 | |
| 2165 | int |
| 2166 | arm_software_single_step (struct frame_info *frame) |
| 2167 | { |
| 2168 | /* NOTE: This may insert the wrong breakpoint instruction when |
| 2169 | single-stepping over a mode-changing instruction, if the |
| 2170 | CPSR heuristics are used. */ |
| 2171 | |
| 2172 | CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); |
| 2173 | insert_single_step_breakpoint (next_pc); |
| 2174 | |
| 2175 | return 1; |
| 2176 | } |
| 2177 | |
| 2178 | #include "bfd-in2.h" |
| 2179 | #include "libcoff.h" |
| 2180 | |
| 2181 | static int |
| 2182 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
| 2183 | { |
| 2184 | if (arm_pc_is_thumb (memaddr)) |
| 2185 | { |
| 2186 | static asymbol *asym; |
| 2187 | static combined_entry_type ce; |
| 2188 | static struct coff_symbol_struct csym; |
| 2189 | static struct bfd fake_bfd; |
| 2190 | static bfd_target fake_target; |
| 2191 | |
| 2192 | if (csym.native == NULL) |
| 2193 | { |
| 2194 | /* Create a fake symbol vector containing a Thumb symbol. |
| 2195 | This is solely so that the code in print_insn_little_arm() |
| 2196 | and print_insn_big_arm() in opcodes/arm-dis.c will detect |
| 2197 | the presence of a Thumb symbol and switch to decoding |
| 2198 | Thumb instructions. */ |
| 2199 | |
| 2200 | fake_target.flavour = bfd_target_coff_flavour; |
| 2201 | fake_bfd.xvec = &fake_target; |
| 2202 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
| 2203 | csym.native = &ce; |
| 2204 | csym.symbol.the_bfd = &fake_bfd; |
| 2205 | csym.symbol.name = "fake"; |
| 2206 | asym = (asymbol *) & csym; |
| 2207 | } |
| 2208 | |
| 2209 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
| 2210 | info->symbols = &asym; |
| 2211 | } |
| 2212 | else |
| 2213 | info->symbols = NULL; |
| 2214 | |
| 2215 | if (info->endian == BFD_ENDIAN_BIG) |
| 2216 | return print_insn_big_arm (memaddr, info); |
| 2217 | else |
| 2218 | return print_insn_little_arm (memaddr, info); |
| 2219 | } |
| 2220 | |
| 2221 | /* The following define instruction sequences that will cause ARM |
| 2222 | cpu's to take an undefined instruction trap. These are used to |
| 2223 | signal a breakpoint to GDB. |
| 2224 | |
| 2225 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb |
| 2226 | modes. A different instruction is required for each mode. The ARM |
| 2227 | cpu's can also be big or little endian. Thus four different |
| 2228 | instructions are needed to support all cases. |
| 2229 | |
| 2230 | Note: ARMv4 defines several new instructions that will take the |
| 2231 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does |
| 2232 | not in fact add the new instructions. The new undefined |
| 2233 | instructions in ARMv4 are all instructions that had no defined |
| 2234 | behaviour in earlier chips. There is no guarantee that they will |
| 2235 | raise an exception, but may be treated as NOP's. In practice, it |
| 2236 | may only safe to rely on instructions matching: |
| 2237 | |
| 2238 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
| 2239 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
| 2240 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x |
| 2241 | |
| 2242 | Even this may only true if the condition predicate is true. The |
| 2243 | following use a condition predicate of ALWAYS so it is always TRUE. |
| 2244 | |
| 2245 | There are other ways of forcing a breakpoint. GNU/Linux, RISC iX, |
| 2246 | and NetBSD all use a software interrupt rather than an undefined |
| 2247 | instruction to force a trap. This can be handled by by the |
| 2248 | abi-specific code during establishment of the gdbarch vector. */ |
| 2249 | |
| 2250 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} |
| 2251 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} |
| 2252 | #define THUMB_LE_BREAKPOINT {0xbe,0xbe} |
| 2253 | #define THUMB_BE_BREAKPOINT {0xbe,0xbe} |
| 2254 | |
| 2255 | static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT; |
| 2256 | static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; |
| 2257 | static const char arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; |
| 2258 | static const char arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; |
| 2259 | |
| 2260 | /* Determine the type and size of breakpoint to insert at PCPTR. Uses |
| 2261 | the program counter value to determine whether a 16-bit or 32-bit |
| 2262 | breakpoint should be used. It returns a pointer to a string of |
| 2263 | bytes that encode a breakpoint instruction, stores the length of |
| 2264 | the string to *lenptr, and adjusts the program counter (if |
| 2265 | necessary) to point to the actual memory location where the |
| 2266 | breakpoint should be inserted. */ |
| 2267 | |
| 2268 | static const unsigned char * |
| 2269 | arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
| 2270 | { |
| 2271 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2272 | |
| 2273 | if (arm_pc_is_thumb (*pcptr)) |
| 2274 | { |
| 2275 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); |
| 2276 | *lenptr = tdep->thumb_breakpoint_size; |
| 2277 | return tdep->thumb_breakpoint; |
| 2278 | } |
| 2279 | else |
| 2280 | { |
| 2281 | *lenptr = tdep->arm_breakpoint_size; |
| 2282 | return tdep->arm_breakpoint; |
| 2283 | } |
| 2284 | } |
| 2285 | |
| 2286 | /* Extract from an array REGBUF containing the (raw) register state a |
| 2287 | function return value of type TYPE, and copy that, in virtual |
| 2288 | format, into VALBUF. */ |
| 2289 | |
| 2290 | static void |
| 2291 | arm_extract_return_value (struct type *type, struct regcache *regs, |
| 2292 | gdb_byte *valbuf) |
| 2293 | { |
| 2294 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
| 2295 | |
| 2296 | if (TYPE_CODE_FLT == TYPE_CODE (type)) |
| 2297 | { |
| 2298 | switch (gdbarch_tdep (gdbarch)->fp_model) |
| 2299 | { |
| 2300 | case ARM_FLOAT_FPA: |
| 2301 | { |
| 2302 | /* The value is in register F0 in internal format. We need to |
| 2303 | extract the raw value and then convert it to the desired |
| 2304 | internal type. */ |
| 2305 | bfd_byte tmpbuf[FP_REGISTER_SIZE]; |
| 2306 | |
| 2307 | regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf); |
| 2308 | convert_from_extended (floatformat_from_type (type), tmpbuf, |
| 2309 | valbuf, gdbarch_byte_order (gdbarch)); |
| 2310 | } |
| 2311 | break; |
| 2312 | |
| 2313 | case ARM_FLOAT_SOFT_FPA: |
| 2314 | case ARM_FLOAT_SOFT_VFP: |
| 2315 | regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf); |
| 2316 | if (TYPE_LENGTH (type) > 4) |
| 2317 | regcache_cooked_read (regs, ARM_A1_REGNUM + 1, |
| 2318 | valbuf + INT_REGISTER_SIZE); |
| 2319 | break; |
| 2320 | |
| 2321 | default: |
| 2322 | internal_error |
| 2323 | (__FILE__, __LINE__, |
| 2324 | _("arm_extract_return_value: Floating point model not supported")); |
| 2325 | break; |
| 2326 | } |
| 2327 | } |
| 2328 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 2329 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 2330 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 2331 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 2332 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 2333 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 2334 | { |
| 2335 | /* If the the type is a plain integer, then the access is |
| 2336 | straight-forward. Otherwise we have to play around a bit more. */ |
| 2337 | int len = TYPE_LENGTH (type); |
| 2338 | int regno = ARM_A1_REGNUM; |
| 2339 | ULONGEST tmp; |
| 2340 | |
| 2341 | while (len > 0) |
| 2342 | { |
| 2343 | /* By using store_unsigned_integer we avoid having to do |
| 2344 | anything special for small big-endian values. */ |
| 2345 | regcache_cooked_read_unsigned (regs, regno++, &tmp); |
| 2346 | store_unsigned_integer (valbuf, |
| 2347 | (len > INT_REGISTER_SIZE |
| 2348 | ? INT_REGISTER_SIZE : len), |
| 2349 | tmp); |
| 2350 | len -= INT_REGISTER_SIZE; |
| 2351 | valbuf += INT_REGISTER_SIZE; |
| 2352 | } |
| 2353 | } |
| 2354 | else |
| 2355 | { |
| 2356 | /* For a structure or union the behaviour is as if the value had |
| 2357 | been stored to word-aligned memory and then loaded into |
| 2358 | registers with 32-bit load instruction(s). */ |
| 2359 | int len = TYPE_LENGTH (type); |
| 2360 | int regno = ARM_A1_REGNUM; |
| 2361 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 2362 | |
| 2363 | while (len > 0) |
| 2364 | { |
| 2365 | regcache_cooked_read (regs, regno++, tmpbuf); |
| 2366 | memcpy (valbuf, tmpbuf, |
| 2367 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
| 2368 | len -= INT_REGISTER_SIZE; |
| 2369 | valbuf += INT_REGISTER_SIZE; |
| 2370 | } |
| 2371 | } |
| 2372 | } |
| 2373 | |
| 2374 | |
| 2375 | /* Will a function return an aggregate type in memory or in a |
| 2376 | register? Return 0 if an aggregate type can be returned in a |
| 2377 | register, 1 if it must be returned in memory. */ |
| 2378 | |
| 2379 | static int |
| 2380 | arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) |
| 2381 | { |
| 2382 | int nRc; |
| 2383 | enum type_code code; |
| 2384 | |
| 2385 | CHECK_TYPEDEF (type); |
| 2386 | |
| 2387 | /* In the ARM ABI, "integer" like aggregate types are returned in |
| 2388 | registers. For an aggregate type to be integer like, its size |
| 2389 | must be less than or equal to INT_REGISTER_SIZE and the |
| 2390 | offset of each addressable subfield must be zero. Note that bit |
| 2391 | fields are not addressable, and all addressable subfields of |
| 2392 | unions always start at offset zero. |
| 2393 | |
| 2394 | This function is based on the behaviour of GCC 2.95.1. |
| 2395 | See: gcc/arm.c: arm_return_in_memory() for details. |
| 2396 | |
| 2397 | Note: All versions of GCC before GCC 2.95.2 do not set up the |
| 2398 | parameters correctly for a function returning the following |
| 2399 | structure: struct { float f;}; This should be returned in memory, |
| 2400 | not a register. Richard Earnshaw sent me a patch, but I do not |
| 2401 | know of any way to detect if a function like the above has been |
| 2402 | compiled with the correct calling convention. */ |
| 2403 | |
| 2404 | /* All aggregate types that won't fit in a register must be returned |
| 2405 | in memory. */ |
| 2406 | if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) |
| 2407 | { |
| 2408 | return 1; |
| 2409 | } |
| 2410 | |
| 2411 | /* The AAPCS says all aggregates not larger than a word are returned |
| 2412 | in a register. */ |
| 2413 | if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) |
| 2414 | return 0; |
| 2415 | |
| 2416 | /* The only aggregate types that can be returned in a register are |
| 2417 | structs and unions. Arrays must be returned in memory. */ |
| 2418 | code = TYPE_CODE (type); |
| 2419 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) |
| 2420 | { |
| 2421 | return 1; |
| 2422 | } |
| 2423 | |
| 2424 | /* Assume all other aggregate types can be returned in a register. |
| 2425 | Run a check for structures, unions and arrays. */ |
| 2426 | nRc = 0; |
| 2427 | |
| 2428 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) |
| 2429 | { |
| 2430 | int i; |
| 2431 | /* Need to check if this struct/union is "integer" like. For |
| 2432 | this to be true, its size must be less than or equal to |
| 2433 | INT_REGISTER_SIZE and the offset of each addressable |
| 2434 | subfield must be zero. Note that bit fields are not |
| 2435 | addressable, and unions always start at offset zero. If any |
| 2436 | of the subfields is a floating point type, the struct/union |
| 2437 | cannot be an integer type. */ |
| 2438 | |
| 2439 | /* For each field in the object, check: |
| 2440 | 1) Is it FP? --> yes, nRc = 1; |
| 2441 | 2) Is it addressable (bitpos != 0) and |
| 2442 | not packed (bitsize == 0)? |
| 2443 | --> yes, nRc = 1 |
| 2444 | */ |
| 2445 | |
| 2446 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 2447 | { |
| 2448 | enum type_code field_type_code; |
| 2449 | field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); |
| 2450 | |
| 2451 | /* Is it a floating point type field? */ |
| 2452 | if (field_type_code == TYPE_CODE_FLT) |
| 2453 | { |
| 2454 | nRc = 1; |
| 2455 | break; |
| 2456 | } |
| 2457 | |
| 2458 | /* If bitpos != 0, then we have to care about it. */ |
| 2459 | if (TYPE_FIELD_BITPOS (type, i) != 0) |
| 2460 | { |
| 2461 | /* Bitfields are not addressable. If the field bitsize is |
| 2462 | zero, then the field is not packed. Hence it cannot be |
| 2463 | a bitfield or any other packed type. */ |
| 2464 | if (TYPE_FIELD_BITSIZE (type, i) == 0) |
| 2465 | { |
| 2466 | nRc = 1; |
| 2467 | break; |
| 2468 | } |
| 2469 | } |
| 2470 | } |
| 2471 | } |
| 2472 | |
| 2473 | return nRc; |
| 2474 | } |
| 2475 | |
| 2476 | /* Write into appropriate registers a function return value of type |
| 2477 | TYPE, given in virtual format. */ |
| 2478 | |
| 2479 | static void |
| 2480 | arm_store_return_value (struct type *type, struct regcache *regs, |
| 2481 | const gdb_byte *valbuf) |
| 2482 | { |
| 2483 | struct gdbarch *gdbarch = get_regcache_arch (regs); |
| 2484 | |
| 2485 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 2486 | { |
| 2487 | char buf[MAX_REGISTER_SIZE]; |
| 2488 | |
| 2489 | switch (gdbarch_tdep (gdbarch)->fp_model) |
| 2490 | { |
| 2491 | case ARM_FLOAT_FPA: |
| 2492 | |
| 2493 | convert_to_extended (floatformat_from_type (type), buf, valbuf, |
| 2494 | gdbarch_byte_order (gdbarch)); |
| 2495 | regcache_cooked_write (regs, ARM_F0_REGNUM, buf); |
| 2496 | break; |
| 2497 | |
| 2498 | case ARM_FLOAT_SOFT_FPA: |
| 2499 | case ARM_FLOAT_SOFT_VFP: |
| 2500 | regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf); |
| 2501 | if (TYPE_LENGTH (type) > 4) |
| 2502 | regcache_cooked_write (regs, ARM_A1_REGNUM + 1, |
| 2503 | valbuf + INT_REGISTER_SIZE); |
| 2504 | break; |
| 2505 | |
| 2506 | default: |
| 2507 | internal_error |
| 2508 | (__FILE__, __LINE__, |
| 2509 | _("arm_store_return_value: Floating point model not supported")); |
| 2510 | break; |
| 2511 | } |
| 2512 | } |
| 2513 | else if (TYPE_CODE (type) == TYPE_CODE_INT |
| 2514 | || TYPE_CODE (type) == TYPE_CODE_CHAR |
| 2515 | || TYPE_CODE (type) == TYPE_CODE_BOOL |
| 2516 | || TYPE_CODE (type) == TYPE_CODE_PTR |
| 2517 | || TYPE_CODE (type) == TYPE_CODE_REF |
| 2518 | || TYPE_CODE (type) == TYPE_CODE_ENUM) |
| 2519 | { |
| 2520 | if (TYPE_LENGTH (type) <= 4) |
| 2521 | { |
| 2522 | /* Values of one word or less are zero/sign-extended and |
| 2523 | returned in r0. */ |
| 2524 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 2525 | LONGEST val = unpack_long (type, valbuf); |
| 2526 | |
| 2527 | store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val); |
| 2528 | regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf); |
| 2529 | } |
| 2530 | else |
| 2531 | { |
| 2532 | /* Integral values greater than one word are stored in consecutive |
| 2533 | registers starting with r0. This will always be a multiple of |
| 2534 | the regiser size. */ |
| 2535 | int len = TYPE_LENGTH (type); |
| 2536 | int regno = ARM_A1_REGNUM; |
| 2537 | |
| 2538 | while (len > 0) |
| 2539 | { |
| 2540 | regcache_cooked_write (regs, regno++, valbuf); |
| 2541 | len -= INT_REGISTER_SIZE; |
| 2542 | valbuf += INT_REGISTER_SIZE; |
| 2543 | } |
| 2544 | } |
| 2545 | } |
| 2546 | else |
| 2547 | { |
| 2548 | /* For a structure or union the behaviour is as if the value had |
| 2549 | been stored to word-aligned memory and then loaded into |
| 2550 | registers with 32-bit load instruction(s). */ |
| 2551 | int len = TYPE_LENGTH (type); |
| 2552 | int regno = ARM_A1_REGNUM; |
| 2553 | bfd_byte tmpbuf[INT_REGISTER_SIZE]; |
| 2554 | |
| 2555 | while (len > 0) |
| 2556 | { |
| 2557 | memcpy (tmpbuf, valbuf, |
| 2558 | len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len); |
| 2559 | regcache_cooked_write (regs, regno++, tmpbuf); |
| 2560 | len -= INT_REGISTER_SIZE; |
| 2561 | valbuf += INT_REGISTER_SIZE; |
| 2562 | } |
| 2563 | } |
| 2564 | } |
| 2565 | |
| 2566 | |
| 2567 | /* Handle function return values. */ |
| 2568 | |
| 2569 | static enum return_value_convention |
| 2570 | arm_return_value (struct gdbarch *gdbarch, struct type *func_type, |
| 2571 | struct type *valtype, struct regcache *regcache, |
| 2572 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 2573 | { |
| 2574 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2575 | |
| 2576 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
| 2577 | || TYPE_CODE (valtype) == TYPE_CODE_UNION |
| 2578 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) |
| 2579 | { |
| 2580 | if (tdep->struct_return == pcc_struct_return |
| 2581 | || arm_return_in_memory (gdbarch, valtype)) |
| 2582 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 2583 | } |
| 2584 | |
| 2585 | if (writebuf) |
| 2586 | arm_store_return_value (valtype, regcache, writebuf); |
| 2587 | |
| 2588 | if (readbuf) |
| 2589 | arm_extract_return_value (valtype, regcache, readbuf); |
| 2590 | |
| 2591 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 2592 | } |
| 2593 | |
| 2594 | |
| 2595 | static int |
| 2596 | arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
| 2597 | { |
| 2598 | CORE_ADDR jb_addr; |
| 2599 | char buf[INT_REGISTER_SIZE]; |
| 2600 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); |
| 2601 | |
| 2602 | jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM); |
| 2603 | |
| 2604 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, |
| 2605 | INT_REGISTER_SIZE)) |
| 2606 | return 0; |
| 2607 | |
| 2608 | *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE); |
| 2609 | return 1; |
| 2610 | } |
| 2611 | |
| 2612 | /* Recognize GCC and GNU ld's trampolines. If we are in a trampoline, |
| 2613 | return the target PC. Otherwise return 0. */ |
| 2614 | |
| 2615 | CORE_ADDR |
| 2616 | arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) |
| 2617 | { |
| 2618 | char *name; |
| 2619 | int namelen; |
| 2620 | CORE_ADDR start_addr; |
| 2621 | |
| 2622 | /* Find the starting address and name of the function containing the PC. */ |
| 2623 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 2624 | return 0; |
| 2625 | |
| 2626 | /* If PC is in a Thumb call or return stub, return the address of the |
| 2627 | target PC, which is in a register. The thunk functions are called |
| 2628 | _call_via_xx, where x is the register name. The possible names |
| 2629 | are r0-r9, sl, fp, ip, sp, and lr. */ |
| 2630 | if (strncmp (name, "_call_via_", 10) == 0) |
| 2631 | { |
| 2632 | /* Use the name suffix to determine which register contains the |
| 2633 | target PC. */ |
| 2634 | static char *table[15] = |
| 2635 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 2636 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" |
| 2637 | }; |
| 2638 | int regno; |
| 2639 | int offset = strlen (name) - 2; |
| 2640 | |
| 2641 | for (regno = 0; regno <= 14; regno++) |
| 2642 | if (strcmp (&name[offset], table[regno]) == 0) |
| 2643 | return get_frame_register_unsigned (frame, regno); |
| 2644 | } |
| 2645 | |
| 2646 | /* GNU ld generates __foo_from_arm or __foo_from_thumb for |
| 2647 | non-interworking calls to foo. We could decode the stubs |
| 2648 | to find the target but it's easier to use the symbol table. */ |
| 2649 | namelen = strlen (name); |
| 2650 | if (name[0] == '_' && name[1] == '_' |
| 2651 | && ((namelen > 2 + strlen ("_from_thumb") |
| 2652 | && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb", |
| 2653 | strlen ("_from_thumb")) == 0) |
| 2654 | || (namelen > 2 + strlen ("_from_arm") |
| 2655 | && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm", |
| 2656 | strlen ("_from_arm")) == 0))) |
| 2657 | { |
| 2658 | char *target_name; |
| 2659 | int target_len = namelen - 2; |
| 2660 | struct minimal_symbol *minsym; |
| 2661 | struct objfile *objfile; |
| 2662 | struct obj_section *sec; |
| 2663 | |
| 2664 | if (name[namelen - 1] == 'b') |
| 2665 | target_len -= strlen ("_from_thumb"); |
| 2666 | else |
| 2667 | target_len -= strlen ("_from_arm"); |
| 2668 | |
| 2669 | target_name = alloca (target_len + 1); |
| 2670 | memcpy (target_name, name + 2, target_len); |
| 2671 | target_name[target_len] = '\0'; |
| 2672 | |
| 2673 | sec = find_pc_section (pc); |
| 2674 | objfile = (sec == NULL) ? NULL : sec->objfile; |
| 2675 | minsym = lookup_minimal_symbol (target_name, NULL, objfile); |
| 2676 | if (minsym != NULL) |
| 2677 | return SYMBOL_VALUE_ADDRESS (minsym); |
| 2678 | else |
| 2679 | return 0; |
| 2680 | } |
| 2681 | |
| 2682 | return 0; /* not a stub */ |
| 2683 | } |
| 2684 | |
| 2685 | static void |
| 2686 | set_arm_command (char *args, int from_tty) |
| 2687 | { |
| 2688 | printf_unfiltered (_("\ |
| 2689 | \"set arm\" must be followed by an apporpriate subcommand.\n")); |
| 2690 | help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout); |
| 2691 | } |
| 2692 | |
| 2693 | static void |
| 2694 | show_arm_command (char *args, int from_tty) |
| 2695 | { |
| 2696 | cmd_show_list (showarmcmdlist, from_tty, ""); |
| 2697 | } |
| 2698 | |
| 2699 | static void |
| 2700 | arm_update_current_architecture (void) |
| 2701 | { |
| 2702 | struct gdbarch_info info; |
| 2703 | |
| 2704 | /* If the current architecture is not ARM, we have nothing to do. */ |
| 2705 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm) |
| 2706 | return; |
| 2707 | |
| 2708 | /* Update the architecture. */ |
| 2709 | gdbarch_info_init (&info); |
| 2710 | |
| 2711 | if (!gdbarch_update_p (info)) |
| 2712 | internal_error (__FILE__, __LINE__, "could not update architecture"); |
| 2713 | } |
| 2714 | |
| 2715 | static void |
| 2716 | set_fp_model_sfunc (char *args, int from_tty, |
| 2717 | struct cmd_list_element *c) |
| 2718 | { |
| 2719 | enum arm_float_model fp_model; |
| 2720 | |
| 2721 | for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) |
| 2722 | if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) |
| 2723 | { |
| 2724 | arm_fp_model = fp_model; |
| 2725 | break; |
| 2726 | } |
| 2727 | |
| 2728 | if (fp_model == ARM_FLOAT_LAST) |
| 2729 | internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."), |
| 2730 | current_fp_model); |
| 2731 | |
| 2732 | arm_update_current_architecture (); |
| 2733 | } |
| 2734 | |
| 2735 | static void |
| 2736 | show_fp_model (struct ui_file *file, int from_tty, |
| 2737 | struct cmd_list_element *c, const char *value) |
| 2738 | { |
| 2739 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 2740 | |
| 2741 | if (arm_fp_model == ARM_FLOAT_AUTO |
| 2742 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
| 2743 | fprintf_filtered (file, _("\ |
| 2744 | The current ARM floating point model is \"auto\" (currently \"%s\").\n"), |
| 2745 | fp_model_strings[tdep->fp_model]); |
| 2746 | else |
| 2747 | fprintf_filtered (file, _("\ |
| 2748 | The current ARM floating point model is \"%s\".\n"), |
| 2749 | fp_model_strings[arm_fp_model]); |
| 2750 | } |
| 2751 | |
| 2752 | static void |
| 2753 | arm_set_abi (char *args, int from_tty, |
| 2754 | struct cmd_list_element *c) |
| 2755 | { |
| 2756 | enum arm_abi_kind arm_abi; |
| 2757 | |
| 2758 | for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) |
| 2759 | if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) |
| 2760 | { |
| 2761 | arm_abi_global = arm_abi; |
| 2762 | break; |
| 2763 | } |
| 2764 | |
| 2765 | if (arm_abi == ARM_ABI_LAST) |
| 2766 | internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."), |
| 2767 | arm_abi_string); |
| 2768 | |
| 2769 | arm_update_current_architecture (); |
| 2770 | } |
| 2771 | |
| 2772 | static void |
| 2773 | arm_show_abi (struct ui_file *file, int from_tty, |
| 2774 | struct cmd_list_element *c, const char *value) |
| 2775 | { |
| 2776 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 2777 | |
| 2778 | if (arm_abi_global == ARM_ABI_AUTO |
| 2779 | && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm) |
| 2780 | fprintf_filtered (file, _("\ |
| 2781 | The current ARM ABI is \"auto\" (currently \"%s\").\n"), |
| 2782 | arm_abi_strings[tdep->arm_abi]); |
| 2783 | else |
| 2784 | fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"), |
| 2785 | arm_abi_string); |
| 2786 | } |
| 2787 | |
| 2788 | static void |
| 2789 | arm_show_fallback_mode (struct ui_file *file, int from_tty, |
| 2790 | struct cmd_list_element *c, const char *value) |
| 2791 | { |
| 2792 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 2793 | |
| 2794 | fprintf_filtered (file, _("\ |
| 2795 | The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"), |
| 2796 | arm_fallback_mode_string); |
| 2797 | } |
| 2798 | |
| 2799 | static void |
| 2800 | arm_show_force_mode (struct ui_file *file, int from_tty, |
| 2801 | struct cmd_list_element *c, const char *value) |
| 2802 | { |
| 2803 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 2804 | |
| 2805 | fprintf_filtered (file, _("\ |
| 2806 | The current execution mode assumed (even when symbols are available) is \"%s\".\n"), |
| 2807 | arm_force_mode_string); |
| 2808 | } |
| 2809 | |
| 2810 | /* If the user changes the register disassembly style used for info |
| 2811 | register and other commands, we have to also switch the style used |
| 2812 | in opcodes for disassembly output. This function is run in the "set |
| 2813 | arm disassembly" command, and does that. */ |
| 2814 | |
| 2815 | static void |
| 2816 | set_disassembly_style_sfunc (char *args, int from_tty, |
| 2817 | struct cmd_list_element *c) |
| 2818 | { |
| 2819 | set_disassembly_style (); |
| 2820 | } |
| 2821 | \f |
| 2822 | /* Return the ARM register name corresponding to register I. */ |
| 2823 | static const char * |
| 2824 | arm_register_name (struct gdbarch *gdbarch, int i) |
| 2825 | { |
| 2826 | if (i >= ARRAY_SIZE (arm_register_names)) |
| 2827 | /* These registers are only supported on targets which supply |
| 2828 | an XML description. */ |
| 2829 | return ""; |
| 2830 | |
| 2831 | return arm_register_names[i]; |
| 2832 | } |
| 2833 | |
| 2834 | static void |
| 2835 | set_disassembly_style (void) |
| 2836 | { |
| 2837 | int current; |
| 2838 | |
| 2839 | /* Find the style that the user wants. */ |
| 2840 | for (current = 0; current < num_disassembly_options; current++) |
| 2841 | if (disassembly_style == valid_disassembly_styles[current]) |
| 2842 | break; |
| 2843 | gdb_assert (current < num_disassembly_options); |
| 2844 | |
| 2845 | /* Synchronize the disassembler. */ |
| 2846 | set_arm_regname_option (current); |
| 2847 | } |
| 2848 | |
| 2849 | /* Test whether the coff symbol specific value corresponds to a Thumb |
| 2850 | function. */ |
| 2851 | |
| 2852 | static int |
| 2853 | coff_sym_is_thumb (int val) |
| 2854 | { |
| 2855 | return (val == C_THUMBEXT || |
| 2856 | val == C_THUMBSTAT || |
| 2857 | val == C_THUMBEXTFUNC || |
| 2858 | val == C_THUMBSTATFUNC || |
| 2859 | val == C_THUMBLABEL); |
| 2860 | } |
| 2861 | |
| 2862 | /* arm_coff_make_msymbol_special() |
| 2863 | arm_elf_make_msymbol_special() |
| 2864 | |
| 2865 | These functions test whether the COFF or ELF symbol corresponds to |
| 2866 | an address in thumb code, and set a "special" bit in a minimal |
| 2867 | symbol to indicate that it does. */ |
| 2868 | |
| 2869 | static void |
| 2870 | arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) |
| 2871 | { |
| 2872 | /* Thumb symbols are of type STT_LOPROC, (synonymous with |
| 2873 | STT_ARM_TFUNC). */ |
| 2874 | if (ELF_ST_TYPE (((elf_symbol_type *)sym)->internal_elf_sym.st_info) |
| 2875 | == STT_LOPROC) |
| 2876 | MSYMBOL_SET_SPECIAL (msym); |
| 2877 | } |
| 2878 | |
| 2879 | static void |
| 2880 | arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) |
| 2881 | { |
| 2882 | if (coff_sym_is_thumb (val)) |
| 2883 | MSYMBOL_SET_SPECIAL (msym); |
| 2884 | } |
| 2885 | |
| 2886 | static void |
| 2887 | arm_objfile_data_cleanup (struct objfile *objfile, void *arg) |
| 2888 | { |
| 2889 | struct arm_per_objfile *data = arg; |
| 2890 | unsigned int i; |
| 2891 | |
| 2892 | for (i = 0; i < objfile->obfd->section_count; i++) |
| 2893 | VEC_free (arm_mapping_symbol_s, data->section_maps[i]); |
| 2894 | } |
| 2895 | |
| 2896 | static void |
| 2897 | arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, |
| 2898 | asymbol *sym) |
| 2899 | { |
| 2900 | const char *name = bfd_asymbol_name (sym); |
| 2901 | struct arm_per_objfile *data; |
| 2902 | VEC(arm_mapping_symbol_s) **map_p; |
| 2903 | struct arm_mapping_symbol new_map_sym; |
| 2904 | |
| 2905 | gdb_assert (name[0] == '$'); |
| 2906 | if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') |
| 2907 | return; |
| 2908 | |
| 2909 | data = objfile_data (objfile, arm_objfile_data_key); |
| 2910 | if (data == NULL) |
| 2911 | { |
| 2912 | data = OBSTACK_ZALLOC (&objfile->objfile_obstack, |
| 2913 | struct arm_per_objfile); |
| 2914 | set_objfile_data (objfile, arm_objfile_data_key, data); |
| 2915 | data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack, |
| 2916 | objfile->obfd->section_count, |
| 2917 | VEC(arm_mapping_symbol_s) *); |
| 2918 | } |
| 2919 | map_p = &data->section_maps[bfd_get_section (sym)->index]; |
| 2920 | |
| 2921 | new_map_sym.value = sym->value; |
| 2922 | new_map_sym.type = name[1]; |
| 2923 | |
| 2924 | /* Assume that most mapping symbols appear in order of increasing |
| 2925 | value. If they were randomly distributed, it would be faster to |
| 2926 | always push here and then sort at first use. */ |
| 2927 | if (!VEC_empty (arm_mapping_symbol_s, *map_p)) |
| 2928 | { |
| 2929 | struct arm_mapping_symbol *prev_map_sym; |
| 2930 | |
| 2931 | prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p); |
| 2932 | if (prev_map_sym->value >= sym->value) |
| 2933 | { |
| 2934 | unsigned int idx; |
| 2935 | idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym, |
| 2936 | arm_compare_mapping_symbols); |
| 2937 | VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym); |
| 2938 | return; |
| 2939 | } |
| 2940 | } |
| 2941 | |
| 2942 | VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym); |
| 2943 | } |
| 2944 | |
| 2945 | static void |
| 2946 | arm_write_pc (struct regcache *regcache, CORE_ADDR pc) |
| 2947 | { |
| 2948 | regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc); |
| 2949 | |
| 2950 | /* If necessary, set the T bit. */ |
| 2951 | if (arm_apcs_32) |
| 2952 | { |
| 2953 | ULONGEST val; |
| 2954 | regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val); |
| 2955 | if (arm_pc_is_thumb (pc)) |
| 2956 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T); |
| 2957 | else |
| 2958 | regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, |
| 2959 | val & ~(ULONGEST) CPSR_T); |
| 2960 | } |
| 2961 | } |
| 2962 | |
| 2963 | static struct value * |
| 2964 | value_of_arm_user_reg (struct frame_info *frame, const void *baton) |
| 2965 | { |
| 2966 | const int *reg_p = baton; |
| 2967 | return value_of_register (*reg_p, frame); |
| 2968 | } |
| 2969 | \f |
| 2970 | static enum gdb_osabi |
| 2971 | arm_elf_osabi_sniffer (bfd *abfd) |
| 2972 | { |
| 2973 | unsigned int elfosabi; |
| 2974 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
| 2975 | |
| 2976 | elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI]; |
| 2977 | |
| 2978 | if (elfosabi == ELFOSABI_ARM) |
| 2979 | /* GNU tools use this value. Check note sections in this case, |
| 2980 | as well. */ |
| 2981 | bfd_map_over_sections (abfd, |
| 2982 | generic_elf_osabi_sniff_abi_tag_sections, |
| 2983 | &osabi); |
| 2984 | |
| 2985 | /* Anything else will be handled by the generic ELF sniffer. */ |
| 2986 | return osabi; |
| 2987 | } |
| 2988 | |
| 2989 | \f |
| 2990 | /* Initialize the current architecture based on INFO. If possible, |
| 2991 | re-use an architecture from ARCHES, which is a list of |
| 2992 | architectures already created during this debugging session. |
| 2993 | |
| 2994 | Called e.g. at program startup, when reading a core file, and when |
| 2995 | reading a binary file. */ |
| 2996 | |
| 2997 | static struct gdbarch * |
| 2998 | arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 2999 | { |
| 3000 | struct gdbarch_tdep *tdep; |
| 3001 | struct gdbarch *gdbarch; |
| 3002 | struct gdbarch_list *best_arch; |
| 3003 | enum arm_abi_kind arm_abi = arm_abi_global; |
| 3004 | enum arm_float_model fp_model = arm_fp_model; |
| 3005 | struct tdesc_arch_data *tdesc_data = NULL; |
| 3006 | int i; |
| 3007 | int have_fpa_registers = 1; |
| 3008 | |
| 3009 | /* Check any target description for validity. */ |
| 3010 | if (tdesc_has_registers (info.target_desc)) |
| 3011 | { |
| 3012 | /* For most registers we require GDB's default names; but also allow |
| 3013 | the numeric names for sp / lr / pc, as a convenience. */ |
| 3014 | static const char *const arm_sp_names[] = { "r13", "sp", NULL }; |
| 3015 | static const char *const arm_lr_names[] = { "r14", "lr", NULL }; |
| 3016 | static const char *const arm_pc_names[] = { "r15", "pc", NULL }; |
| 3017 | |
| 3018 | const struct tdesc_feature *feature; |
| 3019 | int i, valid_p; |
| 3020 | |
| 3021 | feature = tdesc_find_feature (info.target_desc, |
| 3022 | "org.gnu.gdb.arm.core"); |
| 3023 | if (feature == NULL) |
| 3024 | return NULL; |
| 3025 | |
| 3026 | tdesc_data = tdesc_data_alloc (); |
| 3027 | |
| 3028 | valid_p = 1; |
| 3029 | for (i = 0; i < ARM_SP_REGNUM; i++) |
| 3030 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
| 3031 | arm_register_names[i]); |
| 3032 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, |
| 3033 | ARM_SP_REGNUM, |
| 3034 | arm_sp_names); |
| 3035 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, |
| 3036 | ARM_LR_REGNUM, |
| 3037 | arm_lr_names); |
| 3038 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, |
| 3039 | ARM_PC_REGNUM, |
| 3040 | arm_pc_names); |
| 3041 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 3042 | ARM_PS_REGNUM, "cpsr"); |
| 3043 | |
| 3044 | if (!valid_p) |
| 3045 | { |
| 3046 | tdesc_data_cleanup (tdesc_data); |
| 3047 | return NULL; |
| 3048 | } |
| 3049 | |
| 3050 | feature = tdesc_find_feature (info.target_desc, |
| 3051 | "org.gnu.gdb.arm.fpa"); |
| 3052 | if (feature != NULL) |
| 3053 | { |
| 3054 | valid_p = 1; |
| 3055 | for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++) |
| 3056 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
| 3057 | arm_register_names[i]); |
| 3058 | if (!valid_p) |
| 3059 | { |
| 3060 | tdesc_data_cleanup (tdesc_data); |
| 3061 | return NULL; |
| 3062 | } |
| 3063 | } |
| 3064 | else |
| 3065 | have_fpa_registers = 0; |
| 3066 | |
| 3067 | feature = tdesc_find_feature (info.target_desc, |
| 3068 | "org.gnu.gdb.xscale.iwmmxt"); |
| 3069 | if (feature != NULL) |
| 3070 | { |
| 3071 | static const char *const iwmmxt_names[] = { |
| 3072 | "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7", |
| 3073 | "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15", |
| 3074 | "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "", |
| 3075 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "", |
| 3076 | }; |
| 3077 | |
| 3078 | valid_p = 1; |
| 3079 | for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++) |
| 3080 | valid_p |
| 3081 | &= tdesc_numbered_register (feature, tdesc_data, i, |
| 3082 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
| 3083 | |
| 3084 | /* Check for the control registers, but do not fail if they |
| 3085 | are missing. */ |
| 3086 | for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++) |
| 3087 | tdesc_numbered_register (feature, tdesc_data, i, |
| 3088 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
| 3089 | |
| 3090 | for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++) |
| 3091 | valid_p |
| 3092 | &= tdesc_numbered_register (feature, tdesc_data, i, |
| 3093 | iwmmxt_names[i - ARM_WR0_REGNUM]); |
| 3094 | |
| 3095 | if (!valid_p) |
| 3096 | { |
| 3097 | tdesc_data_cleanup (tdesc_data); |
| 3098 | return NULL; |
| 3099 | } |
| 3100 | } |
| 3101 | } |
| 3102 | |
| 3103 | /* If we have an object to base this architecture on, try to determine |
| 3104 | its ABI. */ |
| 3105 | |
| 3106 | if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL) |
| 3107 | { |
| 3108 | int ei_osabi, e_flags; |
| 3109 | |
| 3110 | switch (bfd_get_flavour (info.abfd)) |
| 3111 | { |
| 3112 | case bfd_target_aout_flavour: |
| 3113 | /* Assume it's an old APCS-style ABI. */ |
| 3114 | arm_abi = ARM_ABI_APCS; |
| 3115 | break; |
| 3116 | |
| 3117 | case bfd_target_coff_flavour: |
| 3118 | /* Assume it's an old APCS-style ABI. */ |
| 3119 | /* XXX WinCE? */ |
| 3120 | arm_abi = ARM_ABI_APCS; |
| 3121 | break; |
| 3122 | |
| 3123 | case bfd_target_elf_flavour: |
| 3124 | ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI]; |
| 3125 | e_flags = elf_elfheader (info.abfd)->e_flags; |
| 3126 | |
| 3127 | if (ei_osabi == ELFOSABI_ARM) |
| 3128 | { |
| 3129 | /* GNU tools used to use this value, but do not for EABI |
| 3130 | objects. There's nowhere to tag an EABI version |
| 3131 | anyway, so assume APCS. */ |
| 3132 | arm_abi = ARM_ABI_APCS; |
| 3133 | } |
| 3134 | else if (ei_osabi == ELFOSABI_NONE) |
| 3135 | { |
| 3136 | int eabi_ver = EF_ARM_EABI_VERSION (e_flags); |
| 3137 | |
| 3138 | switch (eabi_ver) |
| 3139 | { |
| 3140 | case EF_ARM_EABI_UNKNOWN: |
| 3141 | /* Assume GNU tools. */ |
| 3142 | arm_abi = ARM_ABI_APCS; |
| 3143 | break; |
| 3144 | |
| 3145 | case EF_ARM_EABI_VER4: |
| 3146 | case EF_ARM_EABI_VER5: |
| 3147 | arm_abi = ARM_ABI_AAPCS; |
| 3148 | /* EABI binaries default to VFP float ordering. */ |
| 3149 | if (fp_model == ARM_FLOAT_AUTO) |
| 3150 | fp_model = ARM_FLOAT_SOFT_VFP; |
| 3151 | break; |
| 3152 | |
| 3153 | default: |
| 3154 | /* Leave it as "auto". */ |
| 3155 | warning (_("unknown ARM EABI version 0x%x"), eabi_ver); |
| 3156 | break; |
| 3157 | } |
| 3158 | } |
| 3159 | |
| 3160 | if (fp_model == ARM_FLOAT_AUTO) |
| 3161 | { |
| 3162 | int e_flags = elf_elfheader (info.abfd)->e_flags; |
| 3163 | |
| 3164 | switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT)) |
| 3165 | { |
| 3166 | case 0: |
| 3167 | /* Leave it as "auto". Strictly speaking this case |
| 3168 | means FPA, but almost nobody uses that now, and |
| 3169 | many toolchains fail to set the appropriate bits |
| 3170 | for the floating-point model they use. */ |
| 3171 | break; |
| 3172 | case EF_ARM_SOFT_FLOAT: |
| 3173 | fp_model = ARM_FLOAT_SOFT_FPA; |
| 3174 | break; |
| 3175 | case EF_ARM_VFP_FLOAT: |
| 3176 | fp_model = ARM_FLOAT_VFP; |
| 3177 | break; |
| 3178 | case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT: |
| 3179 | fp_model = ARM_FLOAT_SOFT_VFP; |
| 3180 | break; |
| 3181 | } |
| 3182 | } |
| 3183 | |
| 3184 | if (e_flags & EF_ARM_BE8) |
| 3185 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; |
| 3186 | |
| 3187 | break; |
| 3188 | |
| 3189 | default: |
| 3190 | /* Leave it as "auto". */ |
| 3191 | break; |
| 3192 | } |
| 3193 | } |
| 3194 | |
| 3195 | /* If there is already a candidate, use it. */ |
| 3196 | for (best_arch = gdbarch_list_lookup_by_info (arches, &info); |
| 3197 | best_arch != NULL; |
| 3198 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) |
| 3199 | { |
| 3200 | if (arm_abi != ARM_ABI_AUTO |
| 3201 | && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi) |
| 3202 | continue; |
| 3203 | |
| 3204 | if (fp_model != ARM_FLOAT_AUTO |
| 3205 | && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model) |
| 3206 | continue; |
| 3207 | |
| 3208 | /* Found a match. */ |
| 3209 | break; |
| 3210 | } |
| 3211 | |
| 3212 | if (best_arch != NULL) |
| 3213 | { |
| 3214 | if (tdesc_data != NULL) |
| 3215 | tdesc_data_cleanup (tdesc_data); |
| 3216 | return best_arch->gdbarch; |
| 3217 | } |
| 3218 | |
| 3219 | tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); |
| 3220 | gdbarch = gdbarch_alloc (&info, tdep); |
| 3221 | |
| 3222 | /* Record additional information about the architecture we are defining. |
| 3223 | These are gdbarch discriminators, like the OSABI. */ |
| 3224 | tdep->arm_abi = arm_abi; |
| 3225 | tdep->fp_model = fp_model; |
| 3226 | tdep->have_fpa_registers = have_fpa_registers; |
| 3227 | |
| 3228 | /* Breakpoints. */ |
| 3229 | switch (info.byte_order_for_code) |
| 3230 | { |
| 3231 | case BFD_ENDIAN_BIG: |
| 3232 | tdep->arm_breakpoint = arm_default_arm_be_breakpoint; |
| 3233 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_be_breakpoint); |
| 3234 | tdep->thumb_breakpoint = arm_default_thumb_be_breakpoint; |
| 3235 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_be_breakpoint); |
| 3236 | |
| 3237 | break; |
| 3238 | |
| 3239 | case BFD_ENDIAN_LITTLE: |
| 3240 | tdep->arm_breakpoint = arm_default_arm_le_breakpoint; |
| 3241 | tdep->arm_breakpoint_size = sizeof (arm_default_arm_le_breakpoint); |
| 3242 | tdep->thumb_breakpoint = arm_default_thumb_le_breakpoint; |
| 3243 | tdep->thumb_breakpoint_size = sizeof (arm_default_thumb_le_breakpoint); |
| 3244 | |
| 3245 | break; |
| 3246 | |
| 3247 | default: |
| 3248 | internal_error (__FILE__, __LINE__, |
| 3249 | _("arm_gdbarch_init: bad byte order for float format")); |
| 3250 | } |
| 3251 | |
| 3252 | /* On ARM targets char defaults to unsigned. */ |
| 3253 | set_gdbarch_char_signed (gdbarch, 0); |
| 3254 | |
| 3255 | /* This should be low enough for everything. */ |
| 3256 | tdep->lowest_pc = 0x20; |
| 3257 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ |
| 3258 | |
| 3259 | /* The default, for both APCS and AAPCS, is to return small |
| 3260 | structures in registers. */ |
| 3261 | tdep->struct_return = reg_struct_return; |
| 3262 | |
| 3263 | set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); |
| 3264 | set_gdbarch_frame_align (gdbarch, arm_frame_align); |
| 3265 | |
| 3266 | set_gdbarch_write_pc (gdbarch, arm_write_pc); |
| 3267 | |
| 3268 | /* Frame handling. */ |
| 3269 | set_gdbarch_dummy_id (gdbarch, arm_dummy_id); |
| 3270 | set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc); |
| 3271 | set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp); |
| 3272 | |
| 3273 | frame_base_set_default (gdbarch, &arm_normal_base); |
| 3274 | |
| 3275 | /* Address manipulation. */ |
| 3276 | set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address); |
| 3277 | set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove); |
| 3278 | |
| 3279 | /* Advance PC across function entry code. */ |
| 3280 | set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); |
| 3281 | |
| 3282 | /* Skip trampolines. */ |
| 3283 | set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); |
| 3284 | |
| 3285 | /* The stack grows downward. */ |
| 3286 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 3287 | |
| 3288 | /* Breakpoint manipulation. */ |
| 3289 | set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); |
| 3290 | |
| 3291 | /* Information about registers, etc. */ |
| 3292 | set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */ |
| 3293 | set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); |
| 3294 | set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM); |
| 3295 | set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS); |
| 3296 | set_gdbarch_register_type (gdbarch, arm_register_type); |
| 3297 | |
| 3298 | /* This "info float" is FPA-specific. Use the generic version if we |
| 3299 | do not have FPA. */ |
| 3300 | if (gdbarch_tdep (gdbarch)->have_fpa_registers) |
| 3301 | set_gdbarch_print_float_info (gdbarch, arm_print_float_info); |
| 3302 | |
| 3303 | /* Internal <-> external register number maps. */ |
| 3304 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum); |
| 3305 | set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno); |
| 3306 | |
| 3307 | set_gdbarch_register_name (gdbarch, arm_register_name); |
| 3308 | |
| 3309 | /* Returning results. */ |
| 3310 | set_gdbarch_return_value (gdbarch, arm_return_value); |
| 3311 | |
| 3312 | /* Disassembly. */ |
| 3313 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm); |
| 3314 | |
| 3315 | /* Minsymbol frobbing. */ |
| 3316 | set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special); |
| 3317 | set_gdbarch_coff_make_msymbol_special (gdbarch, |
| 3318 | arm_coff_make_msymbol_special); |
| 3319 | set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol); |
| 3320 | |
| 3321 | /* Virtual tables. */ |
| 3322 | set_gdbarch_vbit_in_delta (gdbarch, 1); |
| 3323 | |
| 3324 | /* Hook in the ABI-specific overrides, if they have been registered. */ |
| 3325 | gdbarch_init_osabi (info, gdbarch); |
| 3326 | |
| 3327 | dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg); |
| 3328 | |
| 3329 | /* Add some default predicates. */ |
| 3330 | frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); |
| 3331 | dwarf2_append_unwinders (gdbarch); |
| 3332 | frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); |
| 3333 | |
| 3334 | /* Now we have tuned the configuration, set a few final things, |
| 3335 | based on what the OS ABI has told us. */ |
| 3336 | |
| 3337 | /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI |
| 3338 | binaries are always marked. */ |
| 3339 | if (tdep->arm_abi == ARM_ABI_AUTO) |
| 3340 | tdep->arm_abi = ARM_ABI_APCS; |
| 3341 | |
| 3342 | /* We used to default to FPA for generic ARM, but almost nobody |
| 3343 | uses that now, and we now provide a way for the user to force |
| 3344 | the model. So default to the most useful variant. */ |
| 3345 | if (tdep->fp_model == ARM_FLOAT_AUTO) |
| 3346 | tdep->fp_model = ARM_FLOAT_SOFT_FPA; |
| 3347 | |
| 3348 | if (tdep->jb_pc >= 0) |
| 3349 | set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target); |
| 3350 | |
| 3351 | /* Floating point sizes and format. */ |
| 3352 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
| 3353 | if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA) |
| 3354 | { |
| 3355 | set_gdbarch_double_format |
| 3356 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); |
| 3357 | set_gdbarch_long_double_format |
| 3358 | (gdbarch, floatformats_ieee_double_littlebyte_bigword); |
| 3359 | } |
| 3360 | else |
| 3361 | { |
| 3362 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); |
| 3363 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); |
| 3364 | } |
| 3365 | |
| 3366 | if (tdesc_data) |
| 3367 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
| 3368 | |
| 3369 | /* Add standard register aliases. We add aliases even for those |
| 3370 | nanes which are used by the current architecture - it's simpler, |
| 3371 | and does no harm, since nothing ever lists user registers. */ |
| 3372 | for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++) |
| 3373 | user_reg_add (gdbarch, arm_register_aliases[i].name, |
| 3374 | value_of_arm_user_reg, &arm_register_aliases[i].regnum); |
| 3375 | |
| 3376 | return gdbarch; |
| 3377 | } |
| 3378 | |
| 3379 | static void |
| 3380 | arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
| 3381 | { |
| 3382 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3383 | |
| 3384 | if (tdep == NULL) |
| 3385 | return; |
| 3386 | |
| 3387 | fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"), |
| 3388 | (unsigned long) tdep->lowest_pc); |
| 3389 | } |
| 3390 | |
| 3391 | extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */ |
| 3392 | |
| 3393 | void |
| 3394 | _initialize_arm_tdep (void) |
| 3395 | { |
| 3396 | struct ui_file *stb; |
| 3397 | long length; |
| 3398 | struct cmd_list_element *new_set, *new_show; |
| 3399 | const char *setname; |
| 3400 | const char *setdesc; |
| 3401 | const char *const *regnames; |
| 3402 | int numregs, i, j; |
| 3403 | static char *helptext; |
| 3404 | char regdesc[1024], *rdptr = regdesc; |
| 3405 | size_t rest = sizeof (regdesc); |
| 3406 | |
| 3407 | gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep); |
| 3408 | |
| 3409 | arm_objfile_data_key |
| 3410 | = register_objfile_data_with_cleanup (arm_objfile_data_cleanup); |
| 3411 | |
| 3412 | /* Register an ELF OS ABI sniffer for ARM binaries. */ |
| 3413 | gdbarch_register_osabi_sniffer (bfd_arch_arm, |
| 3414 | bfd_target_elf_flavour, |
| 3415 | arm_elf_osabi_sniffer); |
| 3416 | |
| 3417 | /* Get the number of possible sets of register names defined in opcodes. */ |
| 3418 | num_disassembly_options = get_arm_regname_num_options (); |
| 3419 | |
| 3420 | /* Add root prefix command for all "set arm"/"show arm" commands. */ |
| 3421 | add_prefix_cmd ("arm", no_class, set_arm_command, |
| 3422 | _("Various ARM-specific commands."), |
| 3423 | &setarmcmdlist, "set arm ", 0, &setlist); |
| 3424 | |
| 3425 | add_prefix_cmd ("arm", no_class, show_arm_command, |
| 3426 | _("Various ARM-specific commands."), |
| 3427 | &showarmcmdlist, "show arm ", 0, &showlist); |
| 3428 | |
| 3429 | /* Sync the opcode insn printer with our register viewer. */ |
| 3430 | parse_arm_disassembler_option ("reg-names-std"); |
| 3431 | |
| 3432 | /* Initialize the array that will be passed to |
| 3433 | add_setshow_enum_cmd(). */ |
| 3434 | valid_disassembly_styles |
| 3435 | = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); |
| 3436 | for (i = 0; i < num_disassembly_options; i++) |
| 3437 | { |
| 3438 | numregs = get_arm_regnames (i, &setname, &setdesc, ®names); |
| 3439 | valid_disassembly_styles[i] = setname; |
| 3440 | length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); |
| 3441 | rdptr += length; |
| 3442 | rest -= length; |
| 3443 | /* When we find the default names, tell the disassembler to use |
| 3444 | them. */ |
| 3445 | if (!strcmp (setname, "std")) |
| 3446 | { |
| 3447 | disassembly_style = setname; |
| 3448 | set_arm_regname_option (i); |
| 3449 | } |
| 3450 | } |
| 3451 | /* Mark the end of valid options. */ |
| 3452 | valid_disassembly_styles[num_disassembly_options] = NULL; |
| 3453 | |
| 3454 | /* Create the help text. */ |
| 3455 | stb = mem_fileopen (); |
| 3456 | fprintf_unfiltered (stb, "%s%s%s", |
| 3457 | _("The valid values are:\n"), |
| 3458 | regdesc, |
| 3459 | _("The default is \"std\".")); |
| 3460 | helptext = ui_file_xstrdup (stb, &length); |
| 3461 | ui_file_delete (stb); |
| 3462 | |
| 3463 | add_setshow_enum_cmd("disassembler", no_class, |
| 3464 | valid_disassembly_styles, &disassembly_style, |
| 3465 | _("Set the disassembly style."), |
| 3466 | _("Show the disassembly style."), |
| 3467 | helptext, |
| 3468 | set_disassembly_style_sfunc, |
| 3469 | NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ |
| 3470 | &setarmcmdlist, &showarmcmdlist); |
| 3471 | |
| 3472 | add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32, |
| 3473 | _("Set usage of ARM 32-bit mode."), |
| 3474 | _("Show usage of ARM 32-bit mode."), |
| 3475 | _("When off, a 26-bit PC will be used."), |
| 3476 | NULL, |
| 3477 | NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */ |
| 3478 | &setarmcmdlist, &showarmcmdlist); |
| 3479 | |
| 3480 | /* Add a command to allow the user to force the FPU model. */ |
| 3481 | add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model, |
| 3482 | _("Set the floating point type."), |
| 3483 | _("Show the floating point type."), |
| 3484 | _("auto - Determine the FP typefrom the OS-ABI.\n\ |
| 3485 | softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\ |
| 3486 | fpa - FPA co-processor (GCC compiled).\n\ |
| 3487 | softvfp - Software FP with pure-endian doubles.\n\ |
| 3488 | vfp - VFP co-processor."), |
| 3489 | set_fp_model_sfunc, show_fp_model, |
| 3490 | &setarmcmdlist, &showarmcmdlist); |
| 3491 | |
| 3492 | /* Add a command to allow the user to force the ABI. */ |
| 3493 | add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string, |
| 3494 | _("Set the ABI."), |
| 3495 | _("Show the ABI."), |
| 3496 | NULL, arm_set_abi, arm_show_abi, |
| 3497 | &setarmcmdlist, &showarmcmdlist); |
| 3498 | |
| 3499 | /* Add two commands to allow the user to force the assumed |
| 3500 | execution mode. */ |
| 3501 | add_setshow_enum_cmd ("fallback-mode", class_support, |
| 3502 | arm_mode_strings, &arm_fallback_mode_string, |
| 3503 | _("Set the mode assumed when symbols are unavailable."), |
| 3504 | _("Show the mode assumed when symbols are unavailable."), |
| 3505 | NULL, NULL, arm_show_fallback_mode, |
| 3506 | &setarmcmdlist, &showarmcmdlist); |
| 3507 | add_setshow_enum_cmd ("force-mode", class_support, |
| 3508 | arm_mode_strings, &arm_force_mode_string, |
| 3509 | _("Set the mode assumed even when symbols are available."), |
| 3510 | _("Show the mode assumed even when symbols are available."), |
| 3511 | NULL, NULL, arm_show_force_mode, |
| 3512 | &setarmcmdlist, &showarmcmdlist); |
| 3513 | |
| 3514 | /* Debugging flag. */ |
| 3515 | add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug, |
| 3516 | _("Set ARM debugging."), |
| 3517 | _("Show ARM debugging."), |
| 3518 | _("When on, arm-specific debugging is enabled."), |
| 3519 | NULL, |
| 3520 | NULL, /* FIXME: i18n: "ARM debugging is %s. */ |
| 3521 | &setdebuglist, &showdebuglist); |
| 3522 | } |