| 1 | /* Common target dependent code for GDB on ARM systems. |
| 2 | Copyright (C) 2002-2018 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GDB. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 3 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 18 | |
| 19 | #ifndef ARM_TDEP_H |
| 20 | #define ARM_TDEP_H |
| 21 | |
| 22 | /* Forward declarations. */ |
| 23 | struct gdbarch; |
| 24 | struct regset; |
| 25 | struct address_space; |
| 26 | struct get_next_pcs; |
| 27 | struct arm_get_next_pcs; |
| 28 | struct gdb_get_next_pcs; |
| 29 | |
| 30 | #include "arch/arm.h" |
| 31 | #include "infrun.h" |
| 32 | |
| 33 | #include <vector> |
| 34 | |
| 35 | /* Say how long FP registers are. Used for documentation purposes and |
| 36 | code readability in this header. IEEE extended doubles are 80 |
| 37 | bits. DWORD aligned they use 96 bits. */ |
| 38 | #define FP_REGISTER_SIZE 12 |
| 39 | |
| 40 | /* Say how long VFP double precision registers are. Used for documentation |
| 41 | purposes and code readability. These are fixed at 64 bits. */ |
| 42 | #define VFP_REGISTER_SIZE 8 |
| 43 | |
| 44 | /* Number of machine registers. The only define actually required |
| 45 | is gdbarch_num_regs. The other definitions are used for documentation |
| 46 | purposes and code readability. */ |
| 47 | /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS) |
| 48 | (and called PS for processor status) so the status bits can be cleared |
| 49 | from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed |
| 50 | in PS. */ |
| 51 | #define NUM_FREGS 8 /* Number of floating point registers. */ |
| 52 | #define NUM_SREGS 2 /* Number of status registers. */ |
| 53 | #define NUM_GREGS 16 /* Number of general purpose registers. */ |
| 54 | |
| 55 | |
| 56 | |
| 57 | /* Type of floating-point code in use by inferior. There are really 3 models |
| 58 | that are traditionally supported (plus the endianness issue), but gcc can |
| 59 | only generate 2 of those. The third is APCS_FLOAT, where arguments to |
| 60 | functions are passed in floating-point registers. |
| 61 | |
| 62 | In addition to the traditional models, VFP adds two more. |
| 63 | |
| 64 | If you update this enum, don't forget to update fp_model_strings in |
| 65 | arm-tdep.c. */ |
| 66 | |
| 67 | enum arm_float_model |
| 68 | { |
| 69 | ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */ |
| 70 | ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */ |
| 71 | ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */ |
| 72 | ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */ |
| 73 | ARM_FLOAT_VFP, /* Full VFP calling convention. */ |
| 74 | ARM_FLOAT_LAST /* Keep at end. */ |
| 75 | }; |
| 76 | |
| 77 | /* ABI used by the inferior. */ |
| 78 | enum arm_abi_kind |
| 79 | { |
| 80 | ARM_ABI_AUTO, |
| 81 | ARM_ABI_APCS, |
| 82 | ARM_ABI_AAPCS, |
| 83 | ARM_ABI_LAST |
| 84 | }; |
| 85 | |
| 86 | /* Convention for returning structures. */ |
| 87 | |
| 88 | enum struct_return |
| 89 | { |
| 90 | pcc_struct_return, /* Return "short" structures in memory. */ |
| 91 | reg_struct_return /* Return "short" structures in registers. */ |
| 92 | }; |
| 93 | |
| 94 | /* Target-dependent structure in gdbarch. */ |
| 95 | struct gdbarch_tdep |
| 96 | { |
| 97 | /* The ABI for this architecture. It should never be set to |
| 98 | ARM_ABI_AUTO. */ |
| 99 | enum arm_abi_kind arm_abi; |
| 100 | |
| 101 | enum arm_float_model fp_model; /* Floating point calling conventions. */ |
| 102 | |
| 103 | int have_fpa_registers; /* Does the target report the FPA registers? */ |
| 104 | int have_wmmx_registers; /* Does the target report the WMMX registers? */ |
| 105 | /* The number of VFP registers reported by the target. It is zero |
| 106 | if VFP registers are not supported. */ |
| 107 | int vfp_register_count; |
| 108 | int have_vfp_pseudos; /* Are we synthesizing the single precision |
| 109 | VFP registers? */ |
| 110 | int have_neon_pseudos; /* Are we synthesizing the quad precision |
| 111 | NEON registers? Requires |
| 112 | have_vfp_pseudos. */ |
| 113 | int have_neon; /* Do we have a NEON unit? */ |
| 114 | |
| 115 | int is_m; /* Does the target follow the "M" profile. */ |
| 116 | CORE_ADDR lowest_pc; /* Lowest address at which instructions |
| 117 | will appear. */ |
| 118 | |
| 119 | const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */ |
| 120 | int arm_breakpoint_size; /* And its size. */ |
| 121 | const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */ |
| 122 | int thumb_breakpoint_size; /* And its size. */ |
| 123 | |
| 124 | /* If the Thumb breakpoint is an undefined instruction (which is |
| 125 | affected by IT blocks) rather than a BKPT instruction (which is |
| 126 | not), then we need a 32-bit Thumb breakpoint to preserve the |
| 127 | instruction count in IT blocks. */ |
| 128 | const gdb_byte *thumb2_breakpoint; |
| 129 | int thumb2_breakpoint_size; |
| 130 | |
| 131 | int jb_pc; /* Offset to PC value in jump buffer. |
| 132 | If this is negative, longjmp support |
| 133 | will be disabled. */ |
| 134 | size_t jb_elt_size; /* And the size of each entry in the buf. */ |
| 135 | |
| 136 | /* Convention for returning structures. */ |
| 137 | enum struct_return struct_return; |
| 138 | |
| 139 | /* ISA-specific data types. */ |
| 140 | struct type *arm_ext_type; |
| 141 | struct type *neon_double_type; |
| 142 | struct type *neon_quad_type; |
| 143 | |
| 144 | /* syscall record. */ |
| 145 | int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number); |
| 146 | }; |
| 147 | |
| 148 | /* Structures used for displaced stepping. */ |
| 149 | |
| 150 | /* The maximum number of temporaries available for displaced instructions. */ |
| 151 | #define DISPLACED_TEMPS 16 |
| 152 | /* The maximum number of modified instructions generated for one single-stepped |
| 153 | instruction, including the breakpoint (usually at the end of the instruction |
| 154 | sequence) and any scratch words, etc. */ |
| 155 | #define DISPLACED_MODIFIED_INSNS 8 |
| 156 | |
| 157 | struct arm_displaced_step_closure : public displaced_step_closure |
| 158 | { |
| 159 | ULONGEST tmp[DISPLACED_TEMPS]; |
| 160 | int rd; |
| 161 | int wrote_to_pc; |
| 162 | union |
| 163 | { |
| 164 | struct |
| 165 | { |
| 166 | int xfersize; |
| 167 | int rn; /* Writeback register. */ |
| 168 | unsigned int immed : 1; /* Offset is immediate. */ |
| 169 | unsigned int writeback : 1; /* Perform base-register writeback. */ |
| 170 | unsigned int restore_r4 : 1; /* Used r4 as scratch. */ |
| 171 | } ldst; |
| 172 | |
| 173 | struct |
| 174 | { |
| 175 | unsigned long dest; |
| 176 | unsigned int link : 1; |
| 177 | unsigned int exchange : 1; |
| 178 | unsigned int cond : 4; |
| 179 | } branch; |
| 180 | |
| 181 | struct |
| 182 | { |
| 183 | unsigned int regmask; |
| 184 | int rn; |
| 185 | CORE_ADDR xfer_addr; |
| 186 | unsigned int load : 1; |
| 187 | unsigned int user : 1; |
| 188 | unsigned int increment : 1; |
| 189 | unsigned int before : 1; |
| 190 | unsigned int writeback : 1; |
| 191 | unsigned int cond : 4; |
| 192 | } block; |
| 193 | |
| 194 | struct |
| 195 | { |
| 196 | unsigned int immed : 1; |
| 197 | } preload; |
| 198 | |
| 199 | struct |
| 200 | { |
| 201 | /* If non-NULL, override generic SVC handling (e.g. for a particular |
| 202 | OS). */ |
| 203 | int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs, |
| 204 | arm_displaced_step_closure *dsc); |
| 205 | } svc; |
| 206 | } u; |
| 207 | |
| 208 | /* The size of original instruction, 2 or 4. */ |
| 209 | unsigned int insn_size; |
| 210 | /* True if the original insn (and thus all replacement insns) are Thumb |
| 211 | instead of ARM. */ |
| 212 | unsigned int is_thumb; |
| 213 | |
| 214 | /* The slots in the array is used in this way below, |
| 215 | - ARM instruction occupies one slot, |
| 216 | - Thumb 16 bit instruction occupies one slot, |
| 217 | - Thumb 32-bit instruction occupies *two* slots, one part for each. */ |
| 218 | unsigned long modinsn[DISPLACED_MODIFIED_INSNS]; |
| 219 | int numinsns; |
| 220 | CORE_ADDR insn_addr; |
| 221 | CORE_ADDR scratch_base; |
| 222 | void (*cleanup) (struct gdbarch *, struct regcache *, |
| 223 | arm_displaced_step_closure *); |
| 224 | }; |
| 225 | |
| 226 | /* Values for the WRITE_PC argument to displaced_write_reg. If the register |
| 227 | write may write to the PC, specifies the way the CPSR T bit, etc. is |
| 228 | modified by the instruction. */ |
| 229 | |
| 230 | enum pc_write_style |
| 231 | { |
| 232 | BRANCH_WRITE_PC, |
| 233 | BX_WRITE_PC, |
| 234 | LOAD_WRITE_PC, |
| 235 | ALU_WRITE_PC, |
| 236 | CANNOT_WRITE_PC |
| 237 | }; |
| 238 | |
| 239 | extern void |
| 240 | arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, |
| 241 | CORE_ADDR to, struct regcache *regs, |
| 242 | arm_displaced_step_closure *dsc); |
| 243 | extern void |
| 244 | arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, |
| 245 | CORE_ADDR to, arm_displaced_step_closure *dsc); |
| 246 | extern ULONGEST |
| 247 | displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc, |
| 248 | int regno); |
| 249 | extern void |
| 250 | displaced_write_reg (struct regcache *regs, |
| 251 | arm_displaced_step_closure *dsc, int regno, |
| 252 | ULONGEST val, enum pc_write_style write_pc); |
| 253 | |
| 254 | CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR); |
| 255 | |
| 256 | ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, |
| 257 | int len, |
| 258 | int byte_order); |
| 259 | |
| 260 | CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, |
| 261 | CORE_ADDR val); |
| 262 | |
| 263 | int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self); |
| 264 | |
| 265 | std::vector<CORE_ADDR> arm_software_single_step (struct regcache *); |
| 266 | int arm_is_thumb (struct regcache *regcache); |
| 267 | int arm_frame_is_thumb (struct frame_info *frame); |
| 268 | |
| 269 | extern void arm_displaced_step_fixup (struct gdbarch *, |
| 270 | struct displaced_step_closure *, |
| 271 | CORE_ADDR, CORE_ADDR, struct regcache *); |
| 272 | |
| 273 | /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ |
| 274 | extern int arm_psr_thumb_bit (struct gdbarch *); |
| 275 | |
| 276 | /* Is the instruction at the given memory address a Thumb or ARM |
| 277 | instruction? */ |
| 278 | extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR); |
| 279 | |
| 280 | extern int arm_process_record (struct gdbarch *gdbarch, |
| 281 | struct regcache *regcache, CORE_ADDR addr); |
| 282 | /* Functions exported from arm-bsd-tdep.h. */ |
| 283 | |
| 284 | /* Return the appropriate register set for the core section identified |
| 285 | by SECT_NAME and SECT_SIZE. */ |
| 286 | |
| 287 | extern void |
| 288 | armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch, |
| 289 | iterate_over_regset_sections_cb *cb, |
| 290 | void *cb_data, |
| 291 | const struct regcache *regcache); |
| 292 | |
| 293 | /* Target descriptions. */ |
| 294 | extern struct target_desc *tdesc_arm_with_m; |
| 295 | extern struct target_desc *tdesc_arm_with_iwmmxt; |
| 296 | extern struct target_desc *tdesc_arm_with_vfpv2; |
| 297 | extern struct target_desc *tdesc_arm_with_vfpv3; |
| 298 | extern struct target_desc *tdesc_arm_with_neon; |
| 299 | |
| 300 | #endif /* arm-tdep.h */ |