| 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
| 2 | Copyright 2001 Free Software Foundation, Inc. |
| 3 | Contributed by Axis Communications AB. |
| 4 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 2 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program; if not, write to the Free Software |
| 20 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "frame.h" |
| 24 | #include "symtab.h" |
| 25 | #include "inferior.h" |
| 26 | #include "gdbtypes.h" |
| 27 | #include "gdbcore.h" |
| 28 | #include "gdbcmd.h" |
| 29 | #include "target.h" |
| 30 | #include "value.h" |
| 31 | #include "opcode/cris.h" |
| 32 | #include "arch-utils.h" |
| 33 | #include "regcache.h" |
| 34 | |
| 35 | /* To get entry_point_address. */ |
| 36 | #include "symfile.h" |
| 37 | |
| 38 | enum cris_num_regs |
| 39 | { |
| 40 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ |
| 41 | NUM_FREGS = 0, |
| 42 | |
| 43 | /* There are 16 general registers. */ |
| 44 | NUM_GENREGS = 16, |
| 45 | |
| 46 | /* There are 16 special registers. */ |
| 47 | NUM_SPECREGS = 16 |
| 48 | }; |
| 49 | |
| 50 | /* Register numbers of various important registers. |
| 51 | FP_REGNUM Contains address of executing stack frame. |
| 52 | STR_REGNUM Contains the address of structure return values. |
| 53 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits |
| 54 | ARG1_REGNUM Contains the first parameter to a function. |
| 55 | ARG2_REGNUM Contains the second parameter to a function. |
| 56 | ARG3_REGNUM Contains the third parameter to a function. |
| 57 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. |
| 58 | SP_REGNUM Contains address of top of stack. |
| 59 | PC_REGNUM Contains address of next instruction. |
| 60 | SRP_REGNUM Subroutine return pointer register. |
| 61 | BRP_REGNUM Breakpoint return pointer register. */ |
| 62 | |
| 63 | /* FP_REGNUM = 8, SP_REGNUM = 14, and PC_REGNUM = 15 have been incorporated |
| 64 | into the multi-arch framework. */ |
| 65 | |
| 66 | enum cris_regnums |
| 67 | { |
| 68 | /* Enums with respect to the general registers, valid for all |
| 69 | CRIS versions. */ |
| 70 | STR_REGNUM = 9, |
| 71 | RET_REGNUM = 10, |
| 72 | ARG1_REGNUM = 10, |
| 73 | ARG2_REGNUM = 11, |
| 74 | ARG3_REGNUM = 12, |
| 75 | ARG4_REGNUM = 13, |
| 76 | |
| 77 | /* Enums with respect to the special registers, some of which may not be |
| 78 | applicable to all CRIS versions. */ |
| 79 | P0_REGNUM = 16, |
| 80 | VR_REGNUM = 17, |
| 81 | P2_REGNUM = 18, |
| 82 | P3_REGNUM = 19, |
| 83 | P4_REGNUM = 20, |
| 84 | CCR_REGNUM = 21, |
| 85 | MOF_REGNUM = 23, |
| 86 | P8_REGNUM = 24, |
| 87 | IBR_REGNUM = 25, |
| 88 | IRP_REGNUM = 26, |
| 89 | SRP_REGNUM = 27, |
| 90 | BAR_REGNUM = 28, |
| 91 | BRP_REGNUM = 30, |
| 92 | USP_REGNUM = 31 |
| 93 | }; |
| 94 | |
| 95 | extern const struct cris_spec_reg cris_spec_regs[]; |
| 96 | |
| 97 | /* CRIS version, set via the user command 'set cris-version'. Affects |
| 98 | register names and sizes.*/ |
| 99 | static int usr_cmd_cris_version; |
| 100 | |
| 101 | /* Indicates whether to trust the above variable. */ |
| 102 | static int usr_cmd_cris_version_valid = 0; |
| 103 | |
| 104 | /* CRIS mode, set via the user command 'set cris-mode'. Affects availability |
| 105 | of some registers. */ |
| 106 | static const char *usr_cmd_cris_mode; |
| 107 | |
| 108 | /* Indicates whether to trust the above variable. */ |
| 109 | static int usr_cmd_cris_mode_valid = 0; |
| 110 | |
| 111 | static const char CRIS_MODE_USER[] = "CRIS_MODE_USER"; |
| 112 | static const char CRIS_MODE_SUPERVISOR[] = "CRIS_MODE_SUPERVISOR"; |
| 113 | static const char *cris_mode_enums[] = |
| 114 | { |
| 115 | CRIS_MODE_USER, |
| 116 | CRIS_MODE_SUPERVISOR, |
| 117 | 0 |
| 118 | }; |
| 119 | |
| 120 | /* CRIS ABI, set via the user command 'set cris-abi'. |
| 121 | There are two flavours: |
| 122 | 1. Original ABI with 32-bit doubles, where arguments <= 4 bytes are |
| 123 | passed by value. |
| 124 | 2. New ABI with 64-bit doubles, where arguments <= 8 bytes are passed by |
| 125 | value. */ |
| 126 | static const char *usr_cmd_cris_abi; |
| 127 | |
| 128 | /* Indicates whether to trust the above variable. */ |
| 129 | static int usr_cmd_cris_abi_valid = 0; |
| 130 | |
| 131 | /* These variables are strings instead of enums to make them usable as |
| 132 | parameters to add_set_enum_cmd. */ |
| 133 | static const char CRIS_ABI_ORIGINAL[] = "CRIS_ABI_ORIGINAL"; |
| 134 | static const char CRIS_ABI_V2[] = "CRIS_ABI_V2"; |
| 135 | static const char CRIS_ABI_SYMBOL[] = ".$CRIS_ABI_V2"; |
| 136 | static const char *cris_abi_enums[] = |
| 137 | { |
| 138 | CRIS_ABI_ORIGINAL, |
| 139 | CRIS_ABI_V2, |
| 140 | 0 |
| 141 | }; |
| 142 | |
| 143 | /* CRIS architecture specific information. */ |
| 144 | struct gdbarch_tdep |
| 145 | { |
| 146 | int cris_version; |
| 147 | const char *cris_mode; |
| 148 | const char *cris_abi; |
| 149 | }; |
| 150 | |
| 151 | /* Functions for accessing target dependent data. */ |
| 152 | |
| 153 | static int |
| 154 | cris_version (void) |
| 155 | { |
| 156 | return (gdbarch_tdep (current_gdbarch)->cris_version); |
| 157 | } |
| 158 | |
| 159 | static const char * |
| 160 | cris_mode (void) |
| 161 | { |
| 162 | return (gdbarch_tdep (current_gdbarch)->cris_mode); |
| 163 | } |
| 164 | |
| 165 | static const char * |
| 166 | cris_abi (void) |
| 167 | { |
| 168 | return (gdbarch_tdep (current_gdbarch)->cris_abi); |
| 169 | } |
| 170 | |
| 171 | /* For saving call-clobbered contents in R9 when returning structs. */ |
| 172 | static CORE_ADDR struct_return_address; |
| 173 | |
| 174 | struct frame_extra_info |
| 175 | { |
| 176 | CORE_ADDR return_pc; |
| 177 | int leaf_function; |
| 178 | }; |
| 179 | |
| 180 | /* The instruction environment needed to find single-step breakpoints. */ |
| 181 | typedef |
| 182 | struct instruction_environment |
| 183 | { |
| 184 | unsigned long reg[NUM_GENREGS]; |
| 185 | unsigned long preg[NUM_SPECREGS]; |
| 186 | unsigned long branch_break_address; |
| 187 | unsigned long delay_slot_pc; |
| 188 | unsigned long prefix_value; |
| 189 | int branch_found; |
| 190 | int prefix_found; |
| 191 | int invalid; |
| 192 | int slot_needed; |
| 193 | int delay_slot_pc_active; |
| 194 | int xflag_found; |
| 195 | int disable_interrupt; |
| 196 | } inst_env_type; |
| 197 | |
| 198 | /* Save old breakpoints in order to restore the state before a single_step. |
| 199 | At most, two breakpoints will have to be remembered. */ |
| 200 | typedef |
| 201 | char binsn_quantum[BREAKPOINT_MAX]; |
| 202 | static binsn_quantum break_mem[2]; |
| 203 | static CORE_ADDR next_pc = 0; |
| 204 | static CORE_ADDR branch_target_address = 0; |
| 205 | static unsigned char branch_break_inserted = 0; |
| 206 | |
| 207 | /* Machine-dependencies in CRIS for opcodes. */ |
| 208 | |
| 209 | /* Instruction sizes. */ |
| 210 | enum cris_instruction_sizes |
| 211 | { |
| 212 | INST_BYTE_SIZE = 0, |
| 213 | INST_WORD_SIZE = 1, |
| 214 | INST_DWORD_SIZE = 2 |
| 215 | }; |
| 216 | |
| 217 | /* Addressing modes. */ |
| 218 | enum cris_addressing_modes |
| 219 | { |
| 220 | REGISTER_MODE = 1, |
| 221 | INDIRECT_MODE = 2, |
| 222 | AUTOINC_MODE = 3 |
| 223 | }; |
| 224 | |
| 225 | /* Prefix addressing modes. */ |
| 226 | enum cris_prefix_addressing_modes |
| 227 | { |
| 228 | PREFIX_INDEX_MODE = 2, |
| 229 | PREFIX_ASSIGN_MODE = 3, |
| 230 | |
| 231 | /* Handle immediate byte offset addressing mode prefix format. */ |
| 232 | PREFIX_OFFSET_MODE = 2 |
| 233 | }; |
| 234 | |
| 235 | /* Masks for opcodes. */ |
| 236 | enum cris_opcode_masks |
| 237 | { |
| 238 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, |
| 239 | SIGNED_EXTEND_BIT_MASK = 0x2, |
| 240 | SIGNED_BYTE_MASK = 0x80, |
| 241 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, |
| 242 | SIGNED_WORD_MASK = 0x8000, |
| 243 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, |
| 244 | SIGNED_DWORD_MASK = 0x80000000, |
| 245 | SIGNED_QUICK_VALUE_MASK = 0x20, |
| 246 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 |
| 247 | }; |
| 248 | |
| 249 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: |
| 250 | Bit 15 - 12 Operand2 |
| 251 | 11 - 10 Mode |
| 252 | 9 - 6 Opcode |
| 253 | 5 - 4 Size |
| 254 | 3 - 0 Operand1 */ |
| 255 | |
| 256 | static int |
| 257 | cris_get_operand2 (unsigned short insn) |
| 258 | { |
| 259 | return ((insn & 0xF000) >> 12); |
| 260 | } |
| 261 | |
| 262 | static int |
| 263 | cris_get_mode (unsigned short insn) |
| 264 | { |
| 265 | return ((insn & 0x0C00) >> 10); |
| 266 | } |
| 267 | |
| 268 | static int |
| 269 | cris_get_opcode (unsigned short insn) |
| 270 | { |
| 271 | return ((insn & 0x03C0) >> 6); |
| 272 | } |
| 273 | |
| 274 | static int |
| 275 | cris_get_size (unsigned short insn) |
| 276 | { |
| 277 | return ((insn & 0x0030) >> 4); |
| 278 | } |
| 279 | |
| 280 | static int |
| 281 | cris_get_operand1 (unsigned short insn) |
| 282 | { |
| 283 | return (insn & 0x000F); |
| 284 | } |
| 285 | |
| 286 | /* Additional functions in order to handle opcodes. */ |
| 287 | |
| 288 | static int |
| 289 | cris_get_wide_opcode (unsigned short insn) |
| 290 | { |
| 291 | return ((insn & 0x03E0) >> 5); |
| 292 | } |
| 293 | |
| 294 | static int |
| 295 | cris_get_short_size (unsigned short insn) |
| 296 | { |
| 297 | return ((insn & 0x0010) >> 4); |
| 298 | } |
| 299 | |
| 300 | static int |
| 301 | cris_get_quick_value (unsigned short insn) |
| 302 | { |
| 303 | return (insn & 0x003F); |
| 304 | } |
| 305 | |
| 306 | static int |
| 307 | cris_get_bdap_quick_offset (unsigned short insn) |
| 308 | { |
| 309 | return (insn & 0x00FF); |
| 310 | } |
| 311 | |
| 312 | static int |
| 313 | cris_get_branch_short_offset (unsigned short insn) |
| 314 | { |
| 315 | return (insn & 0x00FF); |
| 316 | } |
| 317 | |
| 318 | static int |
| 319 | cris_get_asr_shift_steps (unsigned long value) |
| 320 | { |
| 321 | return (value & 0x3F); |
| 322 | } |
| 323 | |
| 324 | static int |
| 325 | cris_get_asr_quick_shift_steps (unsigned short insn) |
| 326 | { |
| 327 | return (insn & 0x1F); |
| 328 | } |
| 329 | |
| 330 | static int |
| 331 | cris_get_clear_size (unsigned short insn) |
| 332 | { |
| 333 | return ((insn) & 0xC000); |
| 334 | } |
| 335 | |
| 336 | static int |
| 337 | cris_is_signed_extend_bit_on (unsigned short insn) |
| 338 | { |
| 339 | return (((insn) & 0x20) == 0x20); |
| 340 | } |
| 341 | |
| 342 | static int |
| 343 | cris_is_xflag_bit_on (unsigned short insn) |
| 344 | { |
| 345 | return (((insn) & 0x1000) == 0x1000); |
| 346 | } |
| 347 | |
| 348 | static void |
| 349 | cris_set_size_to_dword (unsigned short *insn) |
| 350 | { |
| 351 | *insn &= 0xFFCF; |
| 352 | *insn |= 0x20; |
| 353 | } |
| 354 | |
| 355 | static char |
| 356 | cris_get_signed_offset (unsigned short insn) |
| 357 | { |
| 358 | return ((char) (insn & 0x00FF)); |
| 359 | } |
| 360 | |
| 361 | /* Calls an op function given the op-type, working on the insn and the |
| 362 | inst_env. */ |
| 363 | static void cris_gdb_func (enum cris_op_type, unsigned short, inst_env_type *); |
| 364 | |
| 365 | static CORE_ADDR cris_skip_prologue_main (CORE_ADDR pc, int frameless_p); |
| 366 | |
| 367 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
| 368 | struct gdbarch_list *); |
| 369 | |
| 370 | static int cris_delayed_get_disassembler (bfd_vma, disassemble_info *); |
| 371 | |
| 372 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
| 373 | |
| 374 | static void cris_version_update (char *ignore_args, int from_tty, |
| 375 | struct cmd_list_element *c); |
| 376 | |
| 377 | static void cris_mode_update (char *ignore_args, int from_tty, |
| 378 | struct cmd_list_element *c); |
| 379 | |
| 380 | static void cris_abi_update (char *ignore_args, int from_tty, |
| 381 | struct cmd_list_element *c); |
| 382 | |
| 383 | static CORE_ADDR bfd_lookup_symbol (bfd *, const char *); |
| 384 | |
| 385 | /* Frames information. The definition of the struct frame_info is |
| 386 | |
| 387 | CORE_ADDR frame |
| 388 | CORE_ADDR pc |
| 389 | int signal_handler_caller |
| 390 | CORE_ADDR return_pc |
| 391 | int leaf_function |
| 392 | |
| 393 | If the compilation option -fno-omit-frame-pointer is present the |
| 394 | variable frame will be set to the content of R8 which is the frame |
| 395 | pointer register. |
| 396 | |
| 397 | The variable pc contains the address where execution is performed |
| 398 | in the present frame. The innermost frame contains the current content |
| 399 | of the register PC. All other frames contain the content of the |
| 400 | register PC in the next frame. |
| 401 | |
| 402 | The variable signal_handler_caller is non-zero when the frame is |
| 403 | associated with the call of a signal handler. |
| 404 | |
| 405 | The variable return_pc contains the address where execution should be |
| 406 | resumed when the present frame has finished, the return address. |
| 407 | |
| 408 | The variable leaf_function is 1 if the return address is in the register |
| 409 | SRP, and 0 if it is on the stack. |
| 410 | |
| 411 | Prologue instructions C-code. |
| 412 | The prologue may consist of (-fno-omit-frame-pointer) |
| 413 | 1) 2) |
| 414 | push srp |
| 415 | push r8 push r8 |
| 416 | move.d sp,r8 move.d sp,r8 |
| 417 | subq X,sp subq X,sp |
| 418 | movem rY,[sp] movem rY,[sp] |
| 419 | move.S rZ,[r8-U] move.S rZ,[r8-U] |
| 420 | |
| 421 | where 1 is a non-terminal function, and 2 is a leaf-function. |
| 422 | |
| 423 | Note that this assumption is extremely brittle, and will break at the |
| 424 | slightest change in GCC's prologue. |
| 425 | |
| 426 | If local variables are declared or register contents are saved on stack |
| 427 | the subq-instruction will be present with X as the number of bytes |
| 428 | needed for storage. The reshuffle with respect to r8 may be performed |
| 429 | with any size S (b, w, d) and any of the general registers Z={0..13}. |
| 430 | The offset U should be representable by a signed 8-bit value in all cases. |
| 431 | Thus, the prefix word is assumed to be immediate byte offset mode followed |
| 432 | by another word containing the instruction. |
| 433 | |
| 434 | Degenerate cases: |
| 435 | 3) |
| 436 | push r8 |
| 437 | move.d sp,r8 |
| 438 | move.d r8,sp |
| 439 | pop r8 |
| 440 | |
| 441 | Prologue instructions C++-code. |
| 442 | Case 1) and 2) in the C-code may be followed by |
| 443 | |
| 444 | move.d r10,rS ; this |
| 445 | move.d r11,rT ; P1 |
| 446 | move.d r12,rU ; P2 |
| 447 | move.d r13,rV ; P3 |
| 448 | move.S [r8+U],rZ ; P4 |
| 449 | |
| 450 | if any of the call parameters are stored. The host expects these |
| 451 | instructions to be executed in order to get the call parameters right. */ |
| 452 | |
| 453 | /* Examine the prologue of a function. The variable ip is the address of |
| 454 | the first instruction of the prologue. The variable limit is the address |
| 455 | of the first instruction after the prologue. The variable fi contains the |
| 456 | information in struct frame_info. The variable frameless_p controls whether |
| 457 | the entire prologue is examined (0) or just enough instructions to |
| 458 | determine that it is a prologue (1). */ |
| 459 | |
| 460 | CORE_ADDR |
| 461 | cris_examine (CORE_ADDR ip, CORE_ADDR limit, struct frame_info *fi, |
| 462 | int frameless_p) |
| 463 | { |
| 464 | /* Present instruction. */ |
| 465 | unsigned short insn; |
| 466 | |
| 467 | /* Next instruction, lookahead. */ |
| 468 | unsigned short insn_next; |
| 469 | int regno; |
| 470 | |
| 471 | /* Is there a push fp? */ |
| 472 | int have_fp; |
| 473 | |
| 474 | /* Number of byte on stack used for local variables and movem. */ |
| 475 | int val; |
| 476 | |
| 477 | /* Highest register number in a movem. */ |
| 478 | int regsave; |
| 479 | |
| 480 | /* move.d r<source_register>,rS */ |
| 481 | short source_register; |
| 482 | |
| 483 | /* This frame is with respect to a leaf until a push srp is found. */ |
| 484 | fi->extra_info->leaf_function = 1; |
| 485 | |
| 486 | /* This frame is without the FP until a push fp is found. */ |
| 487 | have_fp = 0; |
| 488 | |
| 489 | /* Assume nothing on stack. */ |
| 490 | val = 0; |
| 491 | regsave = -1; |
| 492 | |
| 493 | /* No information about register contents so far. */ |
| 494 | |
| 495 | /* We only want to know the end of the prologue when fi->saved_regs == 0. |
| 496 | When the saved registers are allocated full information is required. */ |
| 497 | if (fi->saved_regs) |
| 498 | { |
| 499 | for (regno = 0; regno < NUM_REGS; regno++) |
| 500 | fi->saved_regs[regno] = 0; |
| 501 | } |
| 502 | |
| 503 | /* Find the prologue instructions. */ |
| 504 | do |
| 505 | { |
| 506 | insn = read_memory_unsigned_integer (ip, sizeof (short)); |
| 507 | ip += sizeof (short); |
| 508 | if (insn == 0xE1FC) |
| 509 | { |
| 510 | /* push <reg> 32 bit instruction */ |
| 511 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); |
| 512 | ip += sizeof (short); |
| 513 | regno = cris_get_operand2 (insn_next); |
| 514 | if (regno == (SRP_REGNUM - NUM_GENREGS)) |
| 515 | { |
| 516 | if (frameless_p) |
| 517 | { |
| 518 | return ip; |
| 519 | } |
| 520 | fi->extra_info->leaf_function = 0; |
| 521 | } |
| 522 | else if (regno == FP_REGNUM) |
| 523 | { |
| 524 | have_fp = 1; |
| 525 | } |
| 526 | } |
| 527 | else if (insn == 0x866E) |
| 528 | { |
| 529 | /* move.d sp,r8 */ |
| 530 | if (frameless_p) |
| 531 | { |
| 532 | return ip; |
| 533 | } |
| 534 | continue; |
| 535 | } |
| 536 | else if (cris_get_operand2 (insn) == SP_REGNUM |
| 537 | && cris_get_mode (insn) == 0x0000 |
| 538 | && cris_get_opcode (insn) == 0x000A) |
| 539 | { |
| 540 | /* subq <val>,sp */ |
| 541 | val = cris_get_quick_value (insn); |
| 542 | } |
| 543 | else if (cris_get_mode (insn) == 0x0002 |
| 544 | && cris_get_opcode (insn) == 0x000F |
| 545 | && cris_get_size (insn) == 0x0003 |
| 546 | && cris_get_operand1 (insn) == SP_REGNUM) |
| 547 | { |
| 548 | /* movem r<regsave>,[sp] */ |
| 549 | if (frameless_p) |
| 550 | { |
| 551 | return ip; |
| 552 | } |
| 553 | regsave = cris_get_operand2 (insn); |
| 554 | } |
| 555 | else if (cris_get_operand2 (insn) == SP_REGNUM |
| 556 | && ((insn & 0x0F00) >> 8) == 0x0001 |
| 557 | && (cris_get_signed_offset (insn) < 0)) |
| 558 | { |
| 559 | /* Immediate byte offset addressing prefix word with sp as base |
| 560 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> |
| 561 | is between 64 and 128. |
| 562 | movem r<regsave>,[sp=sp-<val>] */ |
| 563 | val = -cris_get_signed_offset (insn); |
| 564 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); |
| 565 | ip += sizeof (short); |
| 566 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
| 567 | && cris_get_opcode (insn_next) == 0x000F |
| 568 | && cris_get_size (insn_next) == 0x0003 |
| 569 | && cris_get_operand1 (insn_next) == SP_REGNUM) |
| 570 | { |
| 571 | if (frameless_p) |
| 572 | { |
| 573 | return ip; |
| 574 | } |
| 575 | regsave = cris_get_operand2 (insn_next); |
| 576 | } |
| 577 | else |
| 578 | { |
| 579 | /* The prologue ended before the limit was reached. */ |
| 580 | ip -= 2 * sizeof (short); |
| 581 | break; |
| 582 | } |
| 583 | } |
| 584 | else if (cris_get_mode (insn) == 0x0001 |
| 585 | && cris_get_opcode (insn) == 0x0009 |
| 586 | && cris_get_size (insn) == 0x0002) |
| 587 | { |
| 588 | /* move.d r<10..13>,r<0..15> */ |
| 589 | if (frameless_p) |
| 590 | { |
| 591 | return ip; |
| 592 | } |
| 593 | source_register = cris_get_operand1 (insn); |
| 594 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
| 595 | { |
| 596 | /* The prologue ended before the limit was reached. */ |
| 597 | ip -= sizeof (short); |
| 598 | break; |
| 599 | } |
| 600 | } |
| 601 | else if (cris_get_operand2 (insn) == FP_REGNUM |
| 602 | /* The size is a fixed-size. */ |
| 603 | && ((insn & 0x0F00) >> 8) == 0x0001 |
| 604 | /* A negative offset. */ |
| 605 | && (cris_get_signed_offset (insn) < 0)) |
| 606 | { |
| 607 | /* move.S rZ,[r8-U] (?) */ |
| 608 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); |
| 609 | ip += sizeof (short); |
| 610 | regno = cris_get_operand2 (insn_next); |
| 611 | if ((regno >= 0 && regno < SP_REGNUM) |
| 612 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
| 613 | && cris_get_opcode (insn_next) == 0x000F) |
| 614 | { |
| 615 | /* move.S rZ,[r8-U] */ |
| 616 | continue; |
| 617 | } |
| 618 | else |
| 619 | { |
| 620 | /* The prologue ended before the limit was reached. */ |
| 621 | ip -= 2 * sizeof (short); |
| 622 | break; |
| 623 | } |
| 624 | } |
| 625 | else if (cris_get_operand2 (insn) == FP_REGNUM |
| 626 | /* The size is a fixed-size. */ |
| 627 | && ((insn & 0x0F00) >> 8) == 0x0001 |
| 628 | /* A positive offset. */ |
| 629 | && (cris_get_signed_offset (insn) > 0)) |
| 630 | { |
| 631 | /* move.S [r8+U],rZ (?) */ |
| 632 | insn_next = read_memory_unsigned_integer (ip, sizeof (short)); |
| 633 | ip += sizeof (short); |
| 634 | regno = cris_get_operand2 (insn_next); |
| 635 | if ((regno >= 0 && regno < SP_REGNUM) |
| 636 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
| 637 | && cris_get_opcode (insn_next) == 0x0009 |
| 638 | && cris_get_operand1 (insn_next) == regno) |
| 639 | { |
| 640 | /* move.S [r8+U],rZ */ |
| 641 | continue; |
| 642 | } |
| 643 | else |
| 644 | { |
| 645 | /* The prologue ended before the limit was reached. */ |
| 646 | ip -= 2 * sizeof (short); |
| 647 | break; |
| 648 | } |
| 649 | } |
| 650 | else |
| 651 | { |
| 652 | /* The prologue ended before the limit was reached. */ |
| 653 | ip -= sizeof (short); |
| 654 | break; |
| 655 | } |
| 656 | } |
| 657 | while (ip < limit); |
| 658 | |
| 659 | /* We only want to know the end of the prologue when |
| 660 | fi->saved_regs == 0. */ |
| 661 | if (!fi->saved_regs) |
| 662 | return ip; |
| 663 | |
| 664 | if (have_fp) |
| 665 | { |
| 666 | fi->saved_regs[FP_REGNUM] = FRAME_FP (fi); |
| 667 | |
| 668 | /* Calculate the addresses. */ |
| 669 | for (regno = regsave; regno >= 0; regno--) |
| 670 | { |
| 671 | fi->saved_regs[regno] = FRAME_FP (fi) - val; |
| 672 | val -= 4; |
| 673 | } |
| 674 | if (fi->extra_info->leaf_function) |
| 675 | { |
| 676 | /* Set the register SP to contain the stack pointer of |
| 677 | the caller. */ |
| 678 | fi->saved_regs[SP_REGNUM] = FRAME_FP (fi) + 4; |
| 679 | } |
| 680 | else |
| 681 | { |
| 682 | /* Set the register SP to contain the stack pointer of |
| 683 | the caller. */ |
| 684 | fi->saved_regs[SP_REGNUM] = FRAME_FP (fi) + 8; |
| 685 | |
| 686 | /* Set the register SRP to contain the return address of |
| 687 | the caller. */ |
| 688 | fi->saved_regs[SRP_REGNUM] = FRAME_FP (fi) + 4; |
| 689 | } |
| 690 | } |
| 691 | return ip; |
| 692 | } |
| 693 | |
| 694 | /* Advance pc beyond any function entry prologue instructions at pc |
| 695 | to reach some "real" code. */ |
| 696 | |
| 697 | CORE_ADDR |
| 698 | cris_skip_prologue (CORE_ADDR pc) |
| 699 | { |
| 700 | return cris_skip_prologue_main (pc, 0); |
| 701 | } |
| 702 | |
| 703 | /* As cris_skip_prologue, but stops as soon as it knows that the function |
| 704 | has a frame. Its result is equal to its input pc if the function is |
| 705 | frameless, unequal otherwise. */ |
| 706 | |
| 707 | CORE_ADDR |
| 708 | cris_skip_prologue_frameless_p (CORE_ADDR pc) |
| 709 | { |
| 710 | return cris_skip_prologue_main (pc, 1); |
| 711 | } |
| 712 | |
| 713 | /* Given a PC value corresponding to the start of a function, return the PC |
| 714 | of the first instruction after the function prologue. */ |
| 715 | |
| 716 | CORE_ADDR |
| 717 | cris_skip_prologue_main (CORE_ADDR pc, int frameless_p) |
| 718 | { |
| 719 | struct frame_info fi; |
| 720 | static struct frame_extra_info fei; |
| 721 | struct symtab_and_line sal = find_pc_line (pc, 0); |
| 722 | int best_limit; |
| 723 | CORE_ADDR pc_after_prologue; |
| 724 | |
| 725 | /* frame_info now contains dynamic memory. Since fi is a dummy here, |
| 726 | I use static memory for extra_info, and don't bother allocating |
| 727 | memory for saved_regs. */ |
| 728 | fi.saved_regs = 0; |
| 729 | fi.extra_info = &fei; |
| 730 | |
| 731 | /* If there is no symbol information then sal.end == 0, and we end up |
| 732 | examining only the first instruction in the function prologue. |
| 733 | Exaggerating the limit seems to be harmless. */ |
| 734 | if (sal.end > 0) |
| 735 | best_limit = sal.end; |
| 736 | else |
| 737 | best_limit = pc + 100; |
| 738 | |
| 739 | pc_after_prologue = cris_examine (pc, best_limit, &fi, frameless_p); |
| 740 | return pc_after_prologue; |
| 741 | } |
| 742 | |
| 743 | /* Use the program counter to determine the contents and size of a breakpoint |
| 744 | instruction. It returns a pointer to a string of bytes that encode a |
| 745 | breakpoint instruction, stores the length of the string to *lenptr, and |
| 746 | adjusts pcptr (if necessary) to point to the actual memory location where |
| 747 | the breakpoint should be inserted. */ |
| 748 | |
| 749 | unsigned char * |
| 750 | cris_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
| 751 | { |
| 752 | static unsigned char break_insn[] = {0x38, 0xe9}; |
| 753 | *lenptr = 2; |
| 754 | |
| 755 | return break_insn; |
| 756 | } |
| 757 | |
| 758 | /* Returns the register SRP (subroutine return pointer) which must contain |
| 759 | the content of the register PC after a function call. */ |
| 760 | |
| 761 | CORE_ADDR |
| 762 | cris_saved_pc_after_call () |
| 763 | { |
| 764 | return read_register (SRP_REGNUM); |
| 765 | } |
| 766 | |
| 767 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
| 768 | 0 otherwise. */ |
| 769 | |
| 770 | int |
| 771 | cris_spec_reg_applicable (struct cris_spec_reg spec_reg) |
| 772 | { |
| 773 | int version = cris_version (); |
| 774 | |
| 775 | switch (spec_reg.applicable_version) |
| 776 | { |
| 777 | case cris_ver_version_all: |
| 778 | return 1; |
| 779 | case cris_ver_warning: |
| 780 | /* Indeterminate/obsolete. */ |
| 781 | return 0; |
| 782 | case cris_ver_sim: |
| 783 | /* Simulator only. */ |
| 784 | return 0; |
| 785 | case cris_ver_v0_3: |
| 786 | return (version >= 0 && version <= 3); |
| 787 | case cris_ver_v3p: |
| 788 | return (version >= 3); |
| 789 | case cris_ver_v8: |
| 790 | return (version == 8 || version == 9); |
| 791 | case cris_ver_v8p: |
| 792 | return (version >= 8); |
| 793 | case cris_ver_v10p: |
| 794 | return (version >= 10); |
| 795 | default: |
| 796 | /* Invalid cris version. */ |
| 797 | return 0; |
| 798 | } |
| 799 | } |
| 800 | |
| 801 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
| 802 | register, -1 for an invalid register. */ |
| 803 | |
| 804 | int |
| 805 | cris_register_size (int regno) |
| 806 | { |
| 807 | int i; |
| 808 | int spec_regno; |
| 809 | |
| 810 | if (regno >= 0 && regno < NUM_GENREGS) |
| 811 | { |
| 812 | /* General registers (R0 - R15) are 32 bits. */ |
| 813 | return 4; |
| 814 | } |
| 815 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) |
| 816 | { |
| 817 | /* Special register (R16 - R31). cris_spec_regs is zero-based. |
| 818 | Adjust regno accordingly. */ |
| 819 | spec_regno = regno - NUM_GENREGS; |
| 820 | |
| 821 | /* The entries in cris_spec_regs are stored in register number order, |
| 822 | which means we can shortcut into the array when searching it. */ |
| 823 | for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) |
| 824 | { |
| 825 | if (cris_spec_regs[i].number == spec_regno |
| 826 | && cris_spec_reg_applicable (cris_spec_regs[i])) |
| 827 | /* Go with the first applicable register. */ |
| 828 | return cris_spec_regs[i].reg_size; |
| 829 | } |
| 830 | /* Special register not applicable to this CRIS version. */ |
| 831 | return 0; |
| 832 | } |
| 833 | else |
| 834 | { |
| 835 | /* Invalid register. */ |
| 836 | return -1; |
| 837 | } |
| 838 | } |
| 839 | |
| 840 | /* Nonzero if regno should not be fetched from the target. This is the case |
| 841 | for unimplemented (size 0) and non-existant registers. */ |
| 842 | |
| 843 | int |
| 844 | cris_cannot_fetch_register (int regno) |
| 845 | { |
| 846 | return ((regno < 0 || regno >= NUM_REGS) |
| 847 | || (cris_register_size (regno) == 0)); |
| 848 | } |
| 849 | |
| 850 | /* Nonzero if regno should not be written to the target, for various |
| 851 | reasons. */ |
| 852 | |
| 853 | int |
| 854 | cris_cannot_store_register (int regno) |
| 855 | { |
| 856 | /* There are three kinds of registers we refuse to write to. |
| 857 | 1. Those that not implemented. |
| 858 | 2. Those that are read-only (depends on the processor mode). |
| 859 | 3. Those registers to which a write has no effect. |
| 860 | */ |
| 861 | |
| 862 | if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0) |
| 863 | /* Not implemented. */ |
| 864 | return 1; |
| 865 | |
| 866 | else if (regno == VR_REGNUM) |
| 867 | /* Read-only. */ |
| 868 | return 1; |
| 869 | |
| 870 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) |
| 871 | /* Writing has no effect. */ |
| 872 | return 1; |
| 873 | |
| 874 | else if (cris_mode () == CRIS_MODE_USER) |
| 875 | { |
| 876 | if (regno == IBR_REGNUM || regno == BAR_REGNUM || regno == BRP_REGNUM |
| 877 | || regno == IRP_REGNUM) |
| 878 | /* Read-only in user mode. */ |
| 879 | return 1; |
| 880 | } |
| 881 | |
| 882 | return 0; |
| 883 | } |
| 884 | |
| 885 | /* Returns the register offset for the first byte of register regno's space |
| 886 | in the saved register state. Returns -1 for an invalid or unimplemented |
| 887 | register. */ |
| 888 | |
| 889 | int |
| 890 | cris_register_offset (int regno) |
| 891 | { |
| 892 | int i; |
| 893 | int reg_size; |
| 894 | int offset = 0; |
| 895 | |
| 896 | if (regno >= 0 && regno < NUM_REGS) |
| 897 | { |
| 898 | /* FIXME: The offsets should be cached and calculated only once, |
| 899 | when the architecture being debugged has changed. */ |
| 900 | for (i = 0; i < regno; i++) |
| 901 | offset += cris_register_size (i); |
| 902 | |
| 903 | return offset; |
| 904 | } |
| 905 | else |
| 906 | { |
| 907 | /* Invalid register. */ |
| 908 | return -1; |
| 909 | } |
| 910 | } |
| 911 | |
| 912 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
| 913 | of data in register regno. */ |
| 914 | |
| 915 | struct type * |
| 916 | cris_register_virtual_type (int regno) |
| 917 | { |
| 918 | if (regno == SP_REGNUM || regno == PC_REGNUM |
| 919 | || (regno > P8_REGNUM && regno < USP_REGNUM)) |
| 920 | { |
| 921 | /* SP, PC, IBR, IRP, SRP, BAR, DCCR, BRP */ |
| 922 | return lookup_pointer_type (builtin_type_void); |
| 923 | } |
| 924 | else if (regno == P8_REGNUM || regno == USP_REGNUM |
| 925 | || (regno >= 0 && regno < SP_REGNUM)) |
| 926 | { |
| 927 | /* R0 - R13, P8, P15 */ |
| 928 | return builtin_type_unsigned_long; |
| 929 | } |
| 930 | else if (regno > P3_REGNUM && regno < P8_REGNUM) |
| 931 | { |
| 932 | /* P4, CCR, DCR0, DCR1 */ |
| 933 | return builtin_type_unsigned_short; |
| 934 | } |
| 935 | else if (regno > PC_REGNUM && regno < P4_REGNUM) |
| 936 | { |
| 937 | /* P0, P1, P2, P3 */ |
| 938 | return builtin_type_unsigned_char; |
| 939 | } |
| 940 | else |
| 941 | { |
| 942 | /* Invalid register. */ |
| 943 | return builtin_type_void; |
| 944 | } |
| 945 | } |
| 946 | |
| 947 | /* Stores a function return value of type type, where valbuf is the address |
| 948 | of the value to be stored. */ |
| 949 | |
| 950 | /* In the original CRIS ABI, R10 is used to store return values. */ |
| 951 | |
| 952 | void |
| 953 | cris_abi_original_store_return_value (struct type *type, char *valbuf) |
| 954 | { |
| 955 | int len = TYPE_LENGTH (type); |
| 956 | |
| 957 | if (len <= REGISTER_SIZE) |
| 958 | write_register_bytes (REGISTER_BYTE (RET_REGNUM), valbuf, len); |
| 959 | else |
| 960 | internal_error (__FILE__, __LINE__, "cris_abi_original_store_return_value: type length too large."); |
| 961 | } |
| 962 | |
| 963 | /* In the CRIS ABI V2, R10 and R11 are used to store return values. */ |
| 964 | |
| 965 | void |
| 966 | cris_abi_v2_store_return_value (struct type *type, char *valbuf) |
| 967 | { |
| 968 | int len = TYPE_LENGTH (type); |
| 969 | |
| 970 | if (len <= 2 * REGISTER_SIZE) |
| 971 | { |
| 972 | /* Note that this works since R10 and R11 are consecutive registers. */ |
| 973 | write_register_bytes (REGISTER_BYTE (RET_REGNUM), valbuf, len); |
| 974 | } |
| 975 | else |
| 976 | internal_error (__FILE__, __LINE__, "cris_abi_v2_store_return_value: type length too large."); |
| 977 | } |
| 978 | |
| 979 | /* Return the name of register regno as a string. Return NULL for an invalid or |
| 980 | unimplemented register. */ |
| 981 | |
| 982 | char * |
| 983 | cris_register_name (int regno) |
| 984 | { |
| 985 | static char *cris_genreg_names[] = |
| 986 | { "r0", "r1", "r2", "r3", \ |
| 987 | "r4", "r5", "r6", "r7", \ |
| 988 | "r8", "r9", "r10", "r11", \ |
| 989 | "r12", "r13", "sp", "pc" }; |
| 990 | |
| 991 | int i; |
| 992 | int spec_regno; |
| 993 | |
| 994 | if (regno >= 0 && regno < NUM_GENREGS) |
| 995 | { |
| 996 | /* General register. */ |
| 997 | return cris_genreg_names[regno]; |
| 998 | } |
| 999 | else if (regno >= NUM_GENREGS && regno < NUM_REGS) |
| 1000 | { |
| 1001 | /* Special register (R16 - R31). cris_spec_regs is zero-based. |
| 1002 | Adjust regno accordingly. */ |
| 1003 | spec_regno = regno - NUM_GENREGS; |
| 1004 | |
| 1005 | /* The entries in cris_spec_regs are stored in register number order, |
| 1006 | which means we can shortcut into the array when searching it. */ |
| 1007 | for (i = spec_regno; cris_spec_regs[i].name != NULL; i++) |
| 1008 | { |
| 1009 | if (cris_spec_regs[i].number == spec_regno |
| 1010 | && cris_spec_reg_applicable (cris_spec_regs[i])) |
| 1011 | /* Go with the first applicable register. */ |
| 1012 | return cris_spec_regs[i].name; |
| 1013 | } |
| 1014 | /* Special register not applicable to this CRIS version. */ |
| 1015 | return NULL; |
| 1016 | } |
| 1017 | else |
| 1018 | { |
| 1019 | /* Invalid register. */ |
| 1020 | return NULL; |
| 1021 | } |
| 1022 | } |
| 1023 | |
| 1024 | int |
| 1025 | cris_register_bytes_ok (long bytes) |
| 1026 | { |
| 1027 | return (bytes == REGISTER_BYTES); |
| 1028 | } |
| 1029 | |
| 1030 | /* Extract from an array regbuf containing the raw register state a function |
| 1031 | return value of type type, and copy that, in virtual format, into |
| 1032 | valbuf. */ |
| 1033 | |
| 1034 | /* In the original CRIS ABI, R10 is used to return values. */ |
| 1035 | |
| 1036 | void |
| 1037 | cris_abi_original_extract_return_value (struct type *type, char *regbuf, |
| 1038 | char *valbuf) |
| 1039 | { |
| 1040 | int len = TYPE_LENGTH (type); |
| 1041 | |
| 1042 | if (len <= REGISTER_SIZE) |
| 1043 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET_REGNUM), len); |
| 1044 | else |
| 1045 | internal_error (__FILE__, __LINE__, "cris_abi_original_extract_return_value: type length too large"); |
| 1046 | } |
| 1047 | |
| 1048 | /* In the CRIS ABI V2, R10 and R11 are used to store return values. */ |
| 1049 | |
| 1050 | void |
| 1051 | cris_abi_v2_extract_return_value (struct type *type, char *regbuf, |
| 1052 | char *valbuf) |
| 1053 | { |
| 1054 | int len = TYPE_LENGTH (type); |
| 1055 | |
| 1056 | if (len <= 2 * REGISTER_SIZE) |
| 1057 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET_REGNUM), len); |
| 1058 | else |
| 1059 | internal_error (__FILE__, __LINE__, "cris_abi_v2_extract_return_value: type length too large"); |
| 1060 | } |
| 1061 | |
| 1062 | /* Store the address of the place in which to copy the structure the |
| 1063 | subroutine will return. In the CRIS ABI, R9 is used in order to pass |
| 1064 | the address of the allocated area where a structure return value must |
| 1065 | be stored. R9 is call-clobbered, which means we must save it here for |
| 1066 | later use. */ |
| 1067 | |
| 1068 | void |
| 1069 | cris_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
| 1070 | { |
| 1071 | write_register (STR_REGNUM, addr); |
| 1072 | struct_return_address = addr; |
| 1073 | } |
| 1074 | |
| 1075 | /* Extract from regbuf the address where a function should return a |
| 1076 | structure value. It's not there in the CRIS ABI, so we must do it another |
| 1077 | way. */ |
| 1078 | |
| 1079 | CORE_ADDR |
| 1080 | cris_extract_struct_value_address (char *regbuf) |
| 1081 | { |
| 1082 | return struct_return_address; |
| 1083 | } |
| 1084 | |
| 1085 | /* Returns 1 if a value of the given type being returned from a function |
| 1086 | must have space allocated for it on the stack. gcc_p is true if the |
| 1087 | function being considered is known to have been compiled by GCC. |
| 1088 | In the CRIS ABI, structure return values are passed to the called |
| 1089 | function by reference in register R9 to a caller-allocated area, so |
| 1090 | this is always true. */ |
| 1091 | |
| 1092 | int |
| 1093 | cris_use_struct_convention (int gcc_p, struct type *type) |
| 1094 | { |
| 1095 | return 1; |
| 1096 | } |
| 1097 | |
| 1098 | /* Returns 1 if the given type will be passed by pointer rather than |
| 1099 | directly. */ |
| 1100 | |
| 1101 | /* In the original CRIS ABI, arguments shorter than or equal to 32 bits are |
| 1102 | passed by value. */ |
| 1103 | |
| 1104 | int |
| 1105 | cris_abi_original_reg_struct_has_addr (int gcc_p, struct type *type) |
| 1106 | { |
| 1107 | return (TYPE_LENGTH (type) > 4); |
| 1108 | } |
| 1109 | |
| 1110 | /* In the CRIS ABI V2, arguments shorter than or equal to 64 bits are passed |
| 1111 | by value. */ |
| 1112 | |
| 1113 | int |
| 1114 | cris_abi_v2_reg_struct_has_addr (int gcc_p, struct type *type) |
| 1115 | { |
| 1116 | return (TYPE_LENGTH (type) > 8); |
| 1117 | } |
| 1118 | |
| 1119 | /* Returns 1 if the function invocation represented by fi does not have a |
| 1120 | stack frame associated with it. Otherwise return 0. */ |
| 1121 | |
| 1122 | int |
| 1123 | cris_frameless_function_invocation (struct frame_info *fi) |
| 1124 | { |
| 1125 | if (fi->signal_handler_caller) |
| 1126 | return 0; |
| 1127 | else |
| 1128 | return frameless_look_for_prologue (fi); |
| 1129 | } |
| 1130 | |
| 1131 | /* See frame.h. Determines the address of all registers in the current stack |
| 1132 | frame storing each in frame->saved_regs. Space for frame->saved_regs shall |
| 1133 | be allocated by FRAME_INIT_SAVED_REGS using either frame_saved_regs_zalloc |
| 1134 | or frame_obstack_alloc. */ |
| 1135 | |
| 1136 | void |
| 1137 | cris_frame_init_saved_regs (struct frame_info *fi) |
| 1138 | { |
| 1139 | CORE_ADDR ip; |
| 1140 | struct symtab_and_line sal; |
| 1141 | int best_limit; |
| 1142 | char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame); |
| 1143 | |
| 1144 | /* Examine the entire prologue. */ |
| 1145 | register int frameless_p = 0; |
| 1146 | |
| 1147 | /* Has this frame's registers already been initialized? */ |
| 1148 | if (fi->saved_regs) |
| 1149 | return; |
| 1150 | |
| 1151 | frame_saved_regs_zalloc (fi); |
| 1152 | |
| 1153 | if (dummy_regs) |
| 1154 | { |
| 1155 | /* I don't see this ever happening, considering the context in which |
| 1156 | cris_frame_init_saved_regs is called (always when we're not in |
| 1157 | a dummy frame). */ |
| 1158 | memcpy (&fi->saved_regs, dummy_regs, sizeof (fi->saved_regs)); |
| 1159 | } |
| 1160 | else |
| 1161 | { |
| 1162 | ip = get_pc_function_start (fi->pc); |
| 1163 | sal = find_pc_line (ip, 0); |
| 1164 | |
| 1165 | /* If there is no symbol information then sal.end == 0, and we end up |
| 1166 | examining only the first instruction in the function prologue. |
| 1167 | Exaggerating the limit seems to be harmless. */ |
| 1168 | if (sal.end > 0) |
| 1169 | best_limit = sal.end; |
| 1170 | else |
| 1171 | best_limit = ip + 100; |
| 1172 | |
| 1173 | cris_examine (ip, best_limit, fi, frameless_p); |
| 1174 | } |
| 1175 | } |
| 1176 | |
| 1177 | /* Initialises the extra frame information at the creation of a new frame. |
| 1178 | The inparameter fromleaf is 0 when the call is from create_new_frame. |
| 1179 | When the call is from get_prev_frame_info, fromleaf is determined by |
| 1180 | cris_frameless_function_invocation. */ |
| 1181 | |
| 1182 | void |
| 1183 | cris_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
| 1184 | { |
| 1185 | if (fi->next) |
| 1186 | { |
| 1187 | /* Called from get_prev_frame. */ |
| 1188 | fi->pc = FRAME_SAVED_PC (fi->next); |
| 1189 | } |
| 1190 | |
| 1191 | fi->extra_info = (struct frame_extra_info *) |
| 1192 | frame_obstack_alloc (sizeof (struct frame_extra_info)); |
| 1193 | |
| 1194 | fi->extra_info->return_pc = 0; |
| 1195 | fi->extra_info->leaf_function = 0; |
| 1196 | |
| 1197 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
| 1198 | { |
| 1199 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong |
| 1200 | by assuming it's always FP. */ |
| 1201 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); |
| 1202 | fi->extra_info->return_pc = |
| 1203 | generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); |
| 1204 | |
| 1205 | /* FIXME: Is this necessarily true? */ |
| 1206 | fi->extra_info->leaf_function = 0; |
| 1207 | } |
| 1208 | else |
| 1209 | { |
| 1210 | cris_frame_init_saved_regs (fi); |
| 1211 | |
| 1212 | /* Check fromleaf/frameless_function_invocation. (FIXME) */ |
| 1213 | |
| 1214 | if (fi->saved_regs[SRP_REGNUM] != 0) |
| 1215 | { |
| 1216 | /* SRP was saved on the stack; non-leaf function. */ |
| 1217 | fi->extra_info->return_pc = |
| 1218 | read_memory_integer (fi->saved_regs[SRP_REGNUM], |
| 1219 | REGISTER_RAW_SIZE (SRP_REGNUM)); |
| 1220 | } |
| 1221 | else |
| 1222 | { |
| 1223 | /* SRP is still in a register; leaf function. */ |
| 1224 | fi->extra_info->return_pc = read_register (SRP_REGNUM); |
| 1225 | /* FIXME: Should leaf_function be set to 1 here? */ |
| 1226 | fi->extra_info->leaf_function = 1; |
| 1227 | } |
| 1228 | } |
| 1229 | } |
| 1230 | |
| 1231 | /* Return the content of the frame pointer in the present frame. In other |
| 1232 | words, determine the address of the calling function's frame. */ |
| 1233 | |
| 1234 | CORE_ADDR |
| 1235 | cris_frame_chain (struct frame_info *fi) |
| 1236 | { |
| 1237 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
| 1238 | { |
| 1239 | return fi->frame; |
| 1240 | } |
| 1241 | else if (!inside_entry_file (fi->pc)) |
| 1242 | { |
| 1243 | return read_memory_unsigned_integer (FRAME_FP (fi), 4); |
| 1244 | } |
| 1245 | else |
| 1246 | { |
| 1247 | return 0; |
| 1248 | } |
| 1249 | } |
| 1250 | |
| 1251 | /* Return the saved PC (which equals the return address) of this frame. */ |
| 1252 | |
| 1253 | CORE_ADDR |
| 1254 | cris_frame_saved_pc (struct frame_info *fi) |
| 1255 | { |
| 1256 | return fi->extra_info->return_pc; |
| 1257 | } |
| 1258 | |
| 1259 | /* Return the address of the argument block for the frame described |
| 1260 | by struct frame_info. */ |
| 1261 | |
| 1262 | CORE_ADDR |
| 1263 | cris_frame_args_address (struct frame_info *fi) |
| 1264 | { |
| 1265 | return FRAME_FP (fi); |
| 1266 | } |
| 1267 | |
| 1268 | /* Return the address of the locals block for the frame |
| 1269 | described by struct frame_info. */ |
| 1270 | |
| 1271 | CORE_ADDR |
| 1272 | cris_frame_locals_address (struct frame_info *fi) |
| 1273 | { |
| 1274 | return FRAME_FP (fi); |
| 1275 | } |
| 1276 | |
| 1277 | /* Setup the function arguments for calling a function in the inferior. */ |
| 1278 | |
| 1279 | CORE_ADDR |
| 1280 | cris_abi_original_push_arguments (int nargs, struct value **args, |
| 1281 | CORE_ADDR sp, int struct_return, |
| 1282 | CORE_ADDR struct_addr) |
| 1283 | { |
| 1284 | int stack_alloc; |
| 1285 | int stack_offset; |
| 1286 | int argreg; |
| 1287 | int argnum; |
| 1288 | struct type *type; |
| 1289 | int len; |
| 1290 | CORE_ADDR regval; |
| 1291 | char *val; |
| 1292 | |
| 1293 | /* Data and parameters reside in different areas on the stack. |
| 1294 | Both frame pointers grow toward higher addresses. */ |
| 1295 | CORE_ADDR fp_params; |
| 1296 | CORE_ADDR fp_data; |
| 1297 | |
| 1298 | /* Are we returning a value using a structure return or a normal value |
| 1299 | return? struct_addr is the address of the reserved space for the return |
| 1300 | structure to be written on the stack. */ |
| 1301 | if (struct_return) |
| 1302 | { |
| 1303 | write_register (STR_REGNUM, struct_addr); |
| 1304 | } |
| 1305 | |
| 1306 | /* Make sure there's space on the stack. Allocate space for data and a |
| 1307 | parameter to refer to that data. */ |
| 1308 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
| 1309 | stack_alloc += (TYPE_LENGTH (VALUE_TYPE (args[argnum])) + REGISTER_SIZE); |
| 1310 | sp -= stack_alloc; |
| 1311 | /* We may over-allocate a little here, but that won't hurt anything. */ |
| 1312 | |
| 1313 | /* Initialize stack frame pointers. */ |
| 1314 | fp_params = sp; |
| 1315 | fp_data = sp + (nargs * REGISTER_SIZE); |
| 1316 | |
| 1317 | /* Now load as many as possible of the first arguments into |
| 1318 | registers, and push the rest onto the stack. */ |
| 1319 | argreg = ARG1_REGNUM; |
| 1320 | stack_offset = 0; |
| 1321 | |
| 1322 | for (argnum = 0; argnum < nargs; argnum++) |
| 1323 | { |
| 1324 | type = VALUE_TYPE (args[argnum]); |
| 1325 | len = TYPE_LENGTH (type); |
| 1326 | val = (char *) VALUE_CONTENTS (args[argnum]); |
| 1327 | |
| 1328 | if (len <= REGISTER_SIZE && argreg <= ARG4_REGNUM) |
| 1329 | { |
| 1330 | /* Data fits in a register; put it in the first available |
| 1331 | register. */ |
| 1332 | write_register (argreg, *(unsigned long *) val); |
| 1333 | argreg++; |
| 1334 | } |
| 1335 | else if (len > REGISTER_SIZE && argreg <= ARG4_REGNUM) |
| 1336 | { |
| 1337 | /* Data does not fit in register; pass it on the stack and |
| 1338 | put its address in the first available register. */ |
| 1339 | write_memory (fp_data, val, len); |
| 1340 | write_register (argreg, fp_data); |
| 1341 | fp_data += len; |
| 1342 | argreg++; |
| 1343 | } |
| 1344 | else if (len > REGISTER_SIZE) |
| 1345 | { |
| 1346 | /* Data does not fit in register; put both data and |
| 1347 | parameter on the stack. */ |
| 1348 | write_memory (fp_data, val, len); |
| 1349 | write_memory (fp_params, (char *) (&fp_data), REGISTER_SIZE); |
| 1350 | fp_data += len; |
| 1351 | fp_params += REGISTER_SIZE; |
| 1352 | } |
| 1353 | else |
| 1354 | { |
| 1355 | /* Data fits in a register, but we are out of registers; |
| 1356 | put the parameter on the stack. */ |
| 1357 | write_memory (fp_params, val, REGISTER_SIZE); |
| 1358 | fp_params += REGISTER_SIZE; |
| 1359 | } |
| 1360 | } |
| 1361 | |
| 1362 | return sp; |
| 1363 | } |
| 1364 | |
| 1365 | CORE_ADDR |
| 1366 | cris_abi_v2_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
| 1367 | int struct_return, CORE_ADDR struct_addr) |
| 1368 | { |
| 1369 | int stack_alloc; |
| 1370 | int stack_offset; |
| 1371 | int argreg; |
| 1372 | int argnum; |
| 1373 | |
| 1374 | CORE_ADDR regval; |
| 1375 | |
| 1376 | /* The function's arguments and memory allocated by gdb for the arguments to |
| 1377 | point at reside in separate areas on the stack. |
| 1378 | Both frame pointers grow toward higher addresses. */ |
| 1379 | CORE_ADDR fp_arg; |
| 1380 | CORE_ADDR fp_mem; |
| 1381 | |
| 1382 | /* Are we returning a value using a structure return or a normal value |
| 1383 | return? struct_addr is the address of the reserved space for the return |
| 1384 | structure to be written on the stack. */ |
| 1385 | if (struct_return) |
| 1386 | { |
| 1387 | write_register (STR_REGNUM, struct_addr); |
| 1388 | } |
| 1389 | |
| 1390 | /* Allocate enough to keep things word-aligned on both parts of the |
| 1391 | stack. */ |
| 1392 | stack_alloc = 0; |
| 1393 | for (argnum = 0; argnum < nargs; argnum++) |
| 1394 | { |
| 1395 | int len; |
| 1396 | int reg_demand; |
| 1397 | |
| 1398 | len = TYPE_LENGTH (VALUE_TYPE (args[argnum])); |
| 1399 | reg_demand = (len / REGISTER_SIZE) + (len % REGISTER_SIZE != 0 ? 1 : 0); |
| 1400 | |
| 1401 | /* reg_demand * REGISTER_SIZE is the amount of memory we might need to |
| 1402 | allocate for this argument. 2 * REGISTER_SIZE is the amount of stack |
| 1403 | space we might need to pass the argument itself (either by value or by |
| 1404 | reference). */ |
| 1405 | stack_alloc += (reg_demand * REGISTER_SIZE + 2 * REGISTER_SIZE); |
| 1406 | } |
| 1407 | sp -= stack_alloc; |
| 1408 | /* We may over-allocate a little here, but that won't hurt anything. */ |
| 1409 | |
| 1410 | /* Initialize frame pointers. */ |
| 1411 | fp_arg = sp; |
| 1412 | fp_mem = sp + (nargs * (2 * REGISTER_SIZE)); |
| 1413 | |
| 1414 | /* Now load as many as possible of the first arguments into registers, |
| 1415 | and push the rest onto the stack. */ |
| 1416 | argreg = ARG1_REGNUM; |
| 1417 | stack_offset = 0; |
| 1418 | |
| 1419 | for (argnum = 0; argnum < nargs; argnum++) |
| 1420 | { |
| 1421 | int len; |
| 1422 | char *val; |
| 1423 | int reg_demand; |
| 1424 | int i; |
| 1425 | |
| 1426 | len = TYPE_LENGTH (VALUE_TYPE (args[argnum])); |
| 1427 | val = (char *) VALUE_CONTENTS (args[argnum]); |
| 1428 | |
| 1429 | /* How may registers worth of storage do we need for this argument? */ |
| 1430 | reg_demand = (len / REGISTER_SIZE) + (len % REGISTER_SIZE != 0 ? 1 : 0); |
| 1431 | |
| 1432 | if (len <= (2 * REGISTER_SIZE) |
| 1433 | && (argreg + reg_demand - 1 <= ARG4_REGNUM)) |
| 1434 | { |
| 1435 | /* Data passed by value. Fits in available register(s). */ |
| 1436 | for (i = 0; i < reg_demand; i++) |
| 1437 | { |
| 1438 | write_register (argreg, *(unsigned long *) val); |
| 1439 | argreg++; |
| 1440 | val += REGISTER_SIZE; |
| 1441 | } |
| 1442 | } |
| 1443 | else if (len <= (2 * REGISTER_SIZE) && argreg <= ARG4_REGNUM) |
| 1444 | { |
| 1445 | /* Data passed by value. Does not fit in available register(s). |
| 1446 | Use the register(s) first, then the stack. */ |
| 1447 | for (i = 0; i < reg_demand; i++) |
| 1448 | { |
| 1449 | if (argreg <= ARG4_REGNUM) |
| 1450 | { |
| 1451 | write_register (argreg, *(unsigned long *) val); |
| 1452 | argreg++; |
| 1453 | val += REGISTER_SIZE; |
| 1454 | } |
| 1455 | else |
| 1456 | { |
| 1457 | /* I guess this memory write could write the remaining data |
| 1458 | all at once instead of in REGISTER_SIZE chunks. */ |
| 1459 | write_memory (fp_arg, val, REGISTER_SIZE); |
| 1460 | fp_arg += REGISTER_SIZE; |
| 1461 | val += REGISTER_SIZE; |
| 1462 | } |
| 1463 | } |
| 1464 | } |
| 1465 | else if (len > (2 * REGISTER_SIZE)) |
| 1466 | { |
| 1467 | /* Data passed by reference. Put it on the stack. */ |
| 1468 | write_memory (fp_mem, val, len); |
| 1469 | write_memory (fp_arg, (char *) (&fp_mem), REGISTER_SIZE); |
| 1470 | |
| 1471 | /* fp_mem need not be word-aligned since it's just a chunk of |
| 1472 | memory being pointed at. That is, += len would do. */ |
| 1473 | fp_mem += reg_demand * REGISTER_SIZE; |
| 1474 | fp_arg += REGISTER_SIZE; |
| 1475 | } |
| 1476 | else |
| 1477 | { |
| 1478 | /* Data passed by value. No available registers. Put it on |
| 1479 | the stack. */ |
| 1480 | write_memory (fp_arg, val, len); |
| 1481 | |
| 1482 | /* fp_arg must be word-aligned (i.e., don't += len) to match |
| 1483 | the function prologue. */ |
| 1484 | fp_arg += reg_demand * REGISTER_SIZE; |
| 1485 | } |
| 1486 | } |
| 1487 | |
| 1488 | return sp; |
| 1489 | } |
| 1490 | |
| 1491 | /* Never put the return address on the stack. The register SRP is pushed |
| 1492 | by the called function unless it is a leaf-function. Due to the BRP |
| 1493 | register the PC will change when continue is sent. */ |
| 1494 | |
| 1495 | CORE_ADDR |
| 1496 | cris_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
| 1497 | { |
| 1498 | write_register (SRP_REGNUM, CALL_DUMMY_ADDRESS ()); |
| 1499 | return sp; |
| 1500 | } |
| 1501 | |
| 1502 | /* Restore the machine to the state it had before the current frame |
| 1503 | was created. Discard the innermost frame from the stack and restore |
| 1504 | all saved registers. */ |
| 1505 | |
| 1506 | void |
| 1507 | cris_pop_frame () |
| 1508 | { |
| 1509 | register struct frame_info *fi = get_current_frame (); |
| 1510 | register int regno; |
| 1511 | register int stack_offset = 0; |
| 1512 | |
| 1513 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
| 1514 | { |
| 1515 | /* This happens when we hit a breakpoint set at the entry point, |
| 1516 | when returning from a dummy frame. */ |
| 1517 | generic_pop_dummy_frame (); |
| 1518 | } |
| 1519 | else |
| 1520 | { |
| 1521 | cris_frame_init_saved_regs (fi); |
| 1522 | |
| 1523 | /* For each register, the address of where it was saved on entry to |
| 1524 | the frame now lies in fi->saved_regs[regno], or zero if it was not |
| 1525 | saved. This includes special registers such as PC and FP saved in |
| 1526 | special ways in the stack frame. The SP_REGNUM is even more |
| 1527 | special, the address here is the SP for the next frame, not the |
| 1528 | address where the SP was saved. */ |
| 1529 | |
| 1530 | /* Restore general registers R0 - R7. They were pushed on the stack |
| 1531 | after SP was saved. */ |
| 1532 | for (regno = 0; regno < FP_REGNUM; regno++) |
| 1533 | { |
| 1534 | if (fi->saved_regs[regno]) |
| 1535 | { |
| 1536 | write_register (regno, |
| 1537 | read_memory_integer (fi->saved_regs[regno], 4)); |
| 1538 | } |
| 1539 | } |
| 1540 | |
| 1541 | if (fi->saved_regs[FP_REGNUM]) |
| 1542 | { |
| 1543 | /* Pop the frame pointer (R8). It was pushed before SP |
| 1544 | was saved. */ |
| 1545 | write_register (FP_REGNUM, |
| 1546 | read_memory_integer (fi->saved_regs[FP_REGNUM], 4)); |
| 1547 | stack_offset += 4; |
| 1548 | |
| 1549 | /* Not a leaf function. */ |
| 1550 | if (fi->saved_regs[SRP_REGNUM]) |
| 1551 | { |
| 1552 | /* SRP was pushed before SP was saved. */ |
| 1553 | stack_offset += 4; |
| 1554 | } |
| 1555 | |
| 1556 | /* Restore the SP and adjust for R8 and (possibly) SRP. */ |
| 1557 | write_register (SP_REGNUM, fi->saved_regs[FP_REGNUM] + stack_offset); |
| 1558 | } |
| 1559 | else |
| 1560 | { |
| 1561 | /* Currently, we can't get the correct info into fi->saved_regs |
| 1562 | without a frame pointer. */ |
| 1563 | } |
| 1564 | |
| 1565 | /* Restore the PC. */ |
| 1566 | write_register (PC_REGNUM, fi->extra_info->return_pc); |
| 1567 | } |
| 1568 | flush_cached_frames (); |
| 1569 | } |
| 1570 | |
| 1571 | /* Calculates a value that measures how good inst_args constraints an |
| 1572 | instruction. It stems from cris_constraint, found in cris-dis.c. */ |
| 1573 | |
| 1574 | static int |
| 1575 | constraint (unsigned int insn, const signed char *inst_args, |
| 1576 | inst_env_type *inst_env) |
| 1577 | { |
| 1578 | int retval = 0; |
| 1579 | int tmp, i; |
| 1580 | |
| 1581 | const char *s = inst_args; |
| 1582 | |
| 1583 | for (; *s; s++) |
| 1584 | switch (*s) |
| 1585 | { |
| 1586 | case 'm': |
| 1587 | if ((insn & 0x30) == 0x30) |
| 1588 | return -1; |
| 1589 | break; |
| 1590 | |
| 1591 | case 'S': |
| 1592 | /* A prefix operand. */ |
| 1593 | if (inst_env->prefix_found) |
| 1594 | break; |
| 1595 | else |
| 1596 | return -1; |
| 1597 | |
| 1598 | case 'B': |
| 1599 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for |
| 1600 | valid "push" size. In case of special register, it may be != 4. */ |
| 1601 | if (inst_env->prefix_found) |
| 1602 | break; |
| 1603 | else |
| 1604 | return -1; |
| 1605 | |
| 1606 | case 'D': |
| 1607 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); |
| 1608 | if (!retval) |
| 1609 | return -1; |
| 1610 | else |
| 1611 | retval += 4; |
| 1612 | break; |
| 1613 | |
| 1614 | case 'P': |
| 1615 | tmp = (insn >> 0xC) & 0xF; |
| 1616 | for (i = 0; i < NUM_SPECREGS; i++) |
| 1617 | /* Since we match four bits, we will give a value of |
| 1618 | 4 - 1 = 3 in a match. If there is a corresponding |
| 1619 | exact match of a special register in another pattern, it |
| 1620 | will get a value of 4, which will be higher. This should |
| 1621 | be correct in that an exact pattern would match better that |
| 1622 | a general pattern. |
| 1623 | Note that there is a reason for not returning zero; the |
| 1624 | pattern for "clear" is partly matched in the bit-pattern |
| 1625 | (the two lower bits must be zero), while the bit-pattern |
| 1626 | for a move from a special register is matched in the |
| 1627 | register constraint. |
| 1628 | This also means we will will have a race condition if |
| 1629 | there is a partly match in three bits in the bit pattern. */ |
| 1630 | if (tmp == cris_spec_regs[i].number) |
| 1631 | { |
| 1632 | retval += 3; |
| 1633 | break; |
| 1634 | } |
| 1635 | if (i == NUM_SPECREGS) |
| 1636 | return -1; |
| 1637 | break; |
| 1638 | } |
| 1639 | return retval; |
| 1640 | } |
| 1641 | |
| 1642 | /* Returns the number of bits set in the variable value. */ |
| 1643 | |
| 1644 | static int |
| 1645 | number_of_bits (unsigned int value) |
| 1646 | { |
| 1647 | int number_of_bits = 0; |
| 1648 | |
| 1649 | while (value != 0) |
| 1650 | { |
| 1651 | number_of_bits += 1; |
| 1652 | value &= (value - 1); |
| 1653 | } |
| 1654 | return number_of_bits; |
| 1655 | } |
| 1656 | |
| 1657 | /* Finds the address that should contain the single step breakpoint(s). |
| 1658 | It stems from code in cris-dis.c. */ |
| 1659 | |
| 1660 | static int |
| 1661 | find_cris_op (unsigned short insn, inst_env_type *inst_env) |
| 1662 | { |
| 1663 | int i; |
| 1664 | int max_level_of_match = -1; |
| 1665 | int max_matched = -1; |
| 1666 | int level_of_match; |
| 1667 | |
| 1668 | for (i = 0; cris_opcodes[i].name != NULL; i++) |
| 1669 | { |
| 1670 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) |
| 1671 | && ((cris_opcodes[i].lose & insn) == 0)) |
| 1672 | { |
| 1673 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); |
| 1674 | if (level_of_match >= 0) |
| 1675 | { |
| 1676 | level_of_match += |
| 1677 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); |
| 1678 | if (level_of_match > max_level_of_match) |
| 1679 | { |
| 1680 | max_matched = i; |
| 1681 | max_level_of_match = level_of_match; |
| 1682 | if (level_of_match == 16) |
| 1683 | { |
| 1684 | /* All bits matched, cannot find better. */ |
| 1685 | break; |
| 1686 | } |
| 1687 | } |
| 1688 | } |
| 1689 | } |
| 1690 | } |
| 1691 | return max_matched; |
| 1692 | } |
| 1693 | |
| 1694 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is |
| 1695 | actually an internal error. */ |
| 1696 | |
| 1697 | static int |
| 1698 | find_step_target (inst_env_type *inst_env) |
| 1699 | { |
| 1700 | int i; |
| 1701 | int offset; |
| 1702 | unsigned short insn; |
| 1703 | |
| 1704 | /* Create a local register image and set the initial state. */ |
| 1705 | for (i = 0; i < NUM_GENREGS; i++) |
| 1706 | { |
| 1707 | inst_env->reg[i] = (unsigned long) read_register (i); |
| 1708 | } |
| 1709 | offset = NUM_GENREGS; |
| 1710 | for (i = 0; i < NUM_SPECREGS; i++) |
| 1711 | { |
| 1712 | inst_env->preg[i] = (unsigned long) read_register (offset + i); |
| 1713 | } |
| 1714 | inst_env->branch_found = 0; |
| 1715 | inst_env->slot_needed = 0; |
| 1716 | inst_env->delay_slot_pc_active = 0; |
| 1717 | inst_env->prefix_found = 0; |
| 1718 | inst_env->invalid = 0; |
| 1719 | inst_env->xflag_found = 0; |
| 1720 | inst_env->disable_interrupt = 0; |
| 1721 | |
| 1722 | /* Look for a step target. */ |
| 1723 | do |
| 1724 | { |
| 1725 | /* Read an instruction from the client. */ |
| 1726 | insn = read_memory_unsigned_integer (inst_env->reg[PC_REGNUM], 2); |
| 1727 | |
| 1728 | /* If the instruction is not in a delay slot the new content of the |
| 1729 | PC is [PC] + 2. If the instruction is in a delay slot it is not |
| 1730 | that simple. Since a instruction in a delay slot cannot change |
| 1731 | the content of the PC, it does not matter what value PC will have. |
| 1732 | Just make sure it is a valid instruction. */ |
| 1733 | if (!inst_env->delay_slot_pc_active) |
| 1734 | { |
| 1735 | inst_env->reg[PC_REGNUM] += 2; |
| 1736 | } |
| 1737 | else |
| 1738 | { |
| 1739 | inst_env->delay_slot_pc_active = 0; |
| 1740 | inst_env->reg[PC_REGNUM] = inst_env->delay_slot_pc; |
| 1741 | } |
| 1742 | /* Analyse the present instruction. */ |
| 1743 | i = find_cris_op (insn, inst_env); |
| 1744 | if (i == -1) |
| 1745 | { |
| 1746 | inst_env->invalid = 1; |
| 1747 | } |
| 1748 | else |
| 1749 | { |
| 1750 | cris_gdb_func (cris_opcodes[i].op, insn, inst_env); |
| 1751 | } |
| 1752 | } while (!inst_env->invalid |
| 1753 | && (inst_env->prefix_found || inst_env->xflag_found |
| 1754 | || inst_env->slot_needed)); |
| 1755 | return i; |
| 1756 | } |
| 1757 | |
| 1758 | /* There is no hardware single-step support. The function find_step_target |
| 1759 | digs through the opcodes in order to find all possible targets. |
| 1760 | Either one ordinary target or two targets for branches may be found. */ |
| 1761 | |
| 1762 | void |
| 1763 | cris_software_single_step (enum target_signal ignore, int insert_breakpoints) |
| 1764 | { |
| 1765 | inst_env_type inst_env; |
| 1766 | |
| 1767 | if (insert_breakpoints) |
| 1768 | { |
| 1769 | /* Analyse the present instruction environment and insert |
| 1770 | breakpoints. */ |
| 1771 | int status = find_step_target (&inst_env); |
| 1772 | if (status == -1) |
| 1773 | { |
| 1774 | /* Could not find a target. FIXME: Should do something. */ |
| 1775 | } |
| 1776 | else |
| 1777 | { |
| 1778 | /* Insert at most two breakpoints. One for the next PC content |
| 1779 | and possibly another one for a branch, jump, etc. */ |
| 1780 | next_pc = (CORE_ADDR) inst_env.reg[PC_REGNUM]; |
| 1781 | target_insert_breakpoint (next_pc, break_mem[0]); |
| 1782 | if (inst_env.branch_found |
| 1783 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) |
| 1784 | { |
| 1785 | branch_target_address = |
| 1786 | (CORE_ADDR) inst_env.branch_break_address; |
| 1787 | target_insert_breakpoint (branch_target_address, break_mem[1]); |
| 1788 | branch_break_inserted = 1; |
| 1789 | } |
| 1790 | } |
| 1791 | } |
| 1792 | else |
| 1793 | { |
| 1794 | /* Remove breakpoints. */ |
| 1795 | target_remove_breakpoint (next_pc, break_mem[0]); |
| 1796 | if (branch_break_inserted) |
| 1797 | { |
| 1798 | target_remove_breakpoint (branch_target_address, break_mem[1]); |
| 1799 | branch_break_inserted = 0; |
| 1800 | } |
| 1801 | } |
| 1802 | } |
| 1803 | |
| 1804 | /* Calculates the prefix value for quick offset addressing mode. */ |
| 1805 | |
| 1806 | void |
| 1807 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
| 1808 | { |
| 1809 | /* It's invalid to be in a delay slot. You can't have a prefix to this |
| 1810 | instruction (not 100% sure). */ |
| 1811 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 1812 | { |
| 1813 | inst_env->invalid = 1; |
| 1814 | return; |
| 1815 | } |
| 1816 | |
| 1817 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
| 1818 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); |
| 1819 | |
| 1820 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 1821 | need updating. */ |
| 1822 | inst_env->slot_needed = 0; |
| 1823 | inst_env->prefix_found = 1; |
| 1824 | } |
| 1825 | |
| 1826 | /* Updates the autoincrement register. The size of the increment is derived |
| 1827 | from the size of the operation. The PC is always kept aligned on even |
| 1828 | word addresses. */ |
| 1829 | |
| 1830 | void |
| 1831 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
| 1832 | { |
| 1833 | if (size == INST_BYTE_SIZE) |
| 1834 | { |
| 1835 | inst_env->reg[cris_get_operand1 (inst)] += 1; |
| 1836 | |
| 1837 | /* The PC must be word aligned, so increase the PC with one |
| 1838 | word even if the size is byte. */ |
| 1839 | if (cris_get_operand1 (inst) == REG_PC) |
| 1840 | { |
| 1841 | inst_env->reg[REG_PC] += 1; |
| 1842 | } |
| 1843 | } |
| 1844 | else if (size == INST_WORD_SIZE) |
| 1845 | { |
| 1846 | inst_env->reg[cris_get_operand1 (inst)] += 2; |
| 1847 | } |
| 1848 | else if (size == INST_DWORD_SIZE) |
| 1849 | { |
| 1850 | inst_env->reg[cris_get_operand1 (inst)] += 4; |
| 1851 | } |
| 1852 | else |
| 1853 | { |
| 1854 | /* Invalid size. */ |
| 1855 | inst_env->invalid = 1; |
| 1856 | } |
| 1857 | } |
| 1858 | |
| 1859 | /* Calculates the prefix value for the general case of offset addressing |
| 1860 | mode. */ |
| 1861 | |
| 1862 | void |
| 1863 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
| 1864 | { |
| 1865 | |
| 1866 | long offset; |
| 1867 | |
| 1868 | /* It's invalid to be in a delay slot. */ |
| 1869 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 1870 | { |
| 1871 | inst_env->invalid = 1; |
| 1872 | return; |
| 1873 | } |
| 1874 | |
| 1875 | if (cris_get_mode (inst) == AUTOINC_MODE) |
| 1876 | { |
| 1877 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 1878 | } |
| 1879 | |
| 1880 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
| 1881 | |
| 1882 | /* The offset is an indirection of the contents of the operand1 register. */ |
| 1883 | inst_env->prefix_value += |
| 1884 | read_memory_integer (inst_env->reg[cris_get_operand1 (inst)], cris_get_size (inst)); |
| 1885 | |
| 1886 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 1887 | need updating. */ |
| 1888 | inst_env->slot_needed = 0; |
| 1889 | inst_env->prefix_found = 1; |
| 1890 | } |
| 1891 | |
| 1892 | /* Calculates the prefix value for the index addressing mode. */ |
| 1893 | |
| 1894 | void |
| 1895 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
| 1896 | { |
| 1897 | /* It's invalid to be in a delay slot. I can't see that it's possible to |
| 1898 | have a prefix to this instruction. So I will treat this as invalid. */ |
| 1899 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 1900 | { |
| 1901 | inst_env->invalid = 1; |
| 1902 | return; |
| 1903 | } |
| 1904 | |
| 1905 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; |
| 1906 | |
| 1907 | /* The offset is the operand2 value shifted the size of the instruction |
| 1908 | to the left. */ |
| 1909 | inst_env->prefix_value += |
| 1910 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); |
| 1911 | |
| 1912 | /* If the PC is operand1 (base) the address used is the address after |
| 1913 | the main instruction, i.e. address + 2 (the PC is already compensated |
| 1914 | for the prefix operation). */ |
| 1915 | if (cris_get_operand1 (inst) == REG_PC) |
| 1916 | { |
| 1917 | inst_env->prefix_value += 2; |
| 1918 | } |
| 1919 | |
| 1920 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 1921 | need updating. */ |
| 1922 | inst_env->slot_needed = 0; |
| 1923 | inst_env->xflag_found = 0; |
| 1924 | inst_env->prefix_found = 1; |
| 1925 | } |
| 1926 | |
| 1927 | /* Calculates the prefix value for the double indirect addressing mode. */ |
| 1928 | |
| 1929 | void |
| 1930 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
| 1931 | { |
| 1932 | |
| 1933 | CORE_ADDR address; |
| 1934 | |
| 1935 | /* It's invalid to be in a delay slot. */ |
| 1936 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 1937 | { |
| 1938 | inst_env->invalid = 1; |
| 1939 | return; |
| 1940 | } |
| 1941 | |
| 1942 | /* The prefix value is one dereference of the contents of the operand1 |
| 1943 | register. */ |
| 1944 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; |
| 1945 | inst_env->prefix_value = read_memory_unsigned_integer (address, 4); |
| 1946 | |
| 1947 | /* Check if the mode is autoincrement. */ |
| 1948 | if (cris_get_mode (inst) == AUTOINC_MODE) |
| 1949 | { |
| 1950 | inst_env->reg[cris_get_operand1 (inst)] += 4; |
| 1951 | } |
| 1952 | |
| 1953 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 1954 | need updating. */ |
| 1955 | inst_env->slot_needed = 0; |
| 1956 | inst_env->xflag_found = 0; |
| 1957 | inst_env->prefix_found = 1; |
| 1958 | } |
| 1959 | |
| 1960 | /* Finds the destination for a branch with 8-bits offset. */ |
| 1961 | |
| 1962 | void |
| 1963 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
| 1964 | { |
| 1965 | |
| 1966 | short offset; |
| 1967 | |
| 1968 | /* If we have a prefix or are in a delay slot it's bad. */ |
| 1969 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 1970 | { |
| 1971 | inst_env->invalid = 1; |
| 1972 | return; |
| 1973 | } |
| 1974 | |
| 1975 | /* We have a branch, find out where the branch will land. */ |
| 1976 | offset = cris_get_branch_short_offset (inst); |
| 1977 | |
| 1978 | /* Check if the offset is signed. */ |
| 1979 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) |
| 1980 | { |
| 1981 | offset |= 0xFF00; |
| 1982 | } |
| 1983 | |
| 1984 | /* The offset ends with the sign bit, set it to zero. The address |
| 1985 | should always be word aligned. */ |
| 1986 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; |
| 1987 | |
| 1988 | inst_env->branch_found = 1; |
| 1989 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; |
| 1990 | |
| 1991 | inst_env->slot_needed = 1; |
| 1992 | inst_env->prefix_found = 0; |
| 1993 | inst_env->xflag_found = 0; |
| 1994 | inst_env->disable_interrupt = 1; |
| 1995 | } |
| 1996 | |
| 1997 | /* Finds the destination for a branch with 16-bits offset. */ |
| 1998 | |
| 1999 | void |
| 2000 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
| 2001 | { |
| 2002 | short offset; |
| 2003 | |
| 2004 | /* If we have a prefix or is in a delay slot it's bad. */ |
| 2005 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2006 | { |
| 2007 | inst_env->invalid = 1; |
| 2008 | return; |
| 2009 | } |
| 2010 | |
| 2011 | /* We have a branch, find out the offset for the branch. */ |
| 2012 | offset = read_memory_integer (inst_env->reg[REG_PC], 2); |
| 2013 | |
| 2014 | /* The instruction is one word longer than normal, so add one word |
| 2015 | to the PC. */ |
| 2016 | inst_env->reg[REG_PC] += 2; |
| 2017 | |
| 2018 | inst_env->branch_found = 1; |
| 2019 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; |
| 2020 | |
| 2021 | |
| 2022 | inst_env->slot_needed = 1; |
| 2023 | inst_env->prefix_found = 0; |
| 2024 | inst_env->xflag_found = 0; |
| 2025 | inst_env->disable_interrupt = 1; |
| 2026 | } |
| 2027 | |
| 2028 | /* Handles the ABS instruction. */ |
| 2029 | |
| 2030 | void |
| 2031 | abs_op (unsigned short inst, inst_env_type *inst_env) |
| 2032 | { |
| 2033 | |
| 2034 | long value; |
| 2035 | |
| 2036 | /* ABS can't have a prefix, so it's bad if it does. */ |
| 2037 | if (inst_env->prefix_found) |
| 2038 | { |
| 2039 | inst_env->invalid = 1; |
| 2040 | return; |
| 2041 | } |
| 2042 | |
| 2043 | /* Check if the operation affects the PC. */ |
| 2044 | if (cris_get_operand2 (inst) == REG_PC) |
| 2045 | { |
| 2046 | |
| 2047 | /* It's invalid to change to the PC if we are in a delay slot. */ |
| 2048 | if (inst_env->slot_needed) |
| 2049 | { |
| 2050 | inst_env->invalid = 1; |
| 2051 | return; |
| 2052 | } |
| 2053 | |
| 2054 | value = (long) inst_env->reg[REG_PC]; |
| 2055 | |
| 2056 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ |
| 2057 | if (value != SIGNED_DWORD_MASK) |
| 2058 | { |
| 2059 | value = -value; |
| 2060 | inst_env->reg[REG_PC] = (long) value; |
| 2061 | } |
| 2062 | } |
| 2063 | |
| 2064 | inst_env->slot_needed = 0; |
| 2065 | inst_env->prefix_found = 0; |
| 2066 | inst_env->xflag_found = 0; |
| 2067 | inst_env->disable_interrupt = 0; |
| 2068 | } |
| 2069 | |
| 2070 | /* Handles the ADDI instruction. */ |
| 2071 | |
| 2072 | void |
| 2073 | addi_op (unsigned short inst, inst_env_type *inst_env) |
| 2074 | { |
| 2075 | /* It's invalid to have the PC as base register. And ADDI can't have |
| 2076 | a prefix. */ |
| 2077 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) |
| 2078 | { |
| 2079 | inst_env->invalid = 1; |
| 2080 | return; |
| 2081 | } |
| 2082 | |
| 2083 | inst_env->slot_needed = 0; |
| 2084 | inst_env->prefix_found = 0; |
| 2085 | inst_env->xflag_found = 0; |
| 2086 | inst_env->disable_interrupt = 0; |
| 2087 | } |
| 2088 | |
| 2089 | /* Handles the ASR instruction. */ |
| 2090 | |
| 2091 | void |
| 2092 | asr_op (unsigned short inst, inst_env_type *inst_env) |
| 2093 | { |
| 2094 | int shift_steps; |
| 2095 | unsigned long value; |
| 2096 | unsigned long signed_extend_mask = 0; |
| 2097 | |
| 2098 | /* ASR can't have a prefix, so check that it doesn't. */ |
| 2099 | if (inst_env->prefix_found) |
| 2100 | { |
| 2101 | inst_env->invalid = 1; |
| 2102 | return; |
| 2103 | } |
| 2104 | |
| 2105 | /* Check if the PC is the target register. */ |
| 2106 | if (cris_get_operand2 (inst) == REG_PC) |
| 2107 | { |
| 2108 | /* It's invalid to change the PC in a delay slot. */ |
| 2109 | if (inst_env->slot_needed) |
| 2110 | { |
| 2111 | inst_env->invalid = 1; |
| 2112 | return; |
| 2113 | } |
| 2114 | /* Get the number of bits to shift. */ |
| 2115 | shift_steps = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); |
| 2116 | value = inst_env->reg[REG_PC]; |
| 2117 | |
| 2118 | /* Find out how many bits the operation should apply to. */ |
| 2119 | if (cris_get_size (inst) == INST_BYTE_SIZE) |
| 2120 | { |
| 2121 | if (value & SIGNED_BYTE_MASK) |
| 2122 | { |
| 2123 | signed_extend_mask = 0xFF; |
| 2124 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2125 | signed_extend_mask = ~signed_extend_mask; |
| 2126 | } |
| 2127 | value = value >> shift_steps; |
| 2128 | value |= signed_extend_mask; |
| 2129 | value &= 0xFF; |
| 2130 | inst_env->reg[REG_PC] &= 0xFFFFFF00; |
| 2131 | inst_env->reg[REG_PC] |= value; |
| 2132 | } |
| 2133 | else if (cris_get_size (inst) == INST_WORD_SIZE) |
| 2134 | { |
| 2135 | if (value & SIGNED_WORD_MASK) |
| 2136 | { |
| 2137 | signed_extend_mask = 0xFFFF; |
| 2138 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2139 | signed_extend_mask = ~signed_extend_mask; |
| 2140 | } |
| 2141 | value = value >> shift_steps; |
| 2142 | value |= signed_extend_mask; |
| 2143 | value &= 0xFFFF; |
| 2144 | inst_env->reg[REG_PC] &= 0xFFFF0000; |
| 2145 | inst_env->reg[REG_PC] |= value; |
| 2146 | } |
| 2147 | else if (cris_get_size (inst) == INST_DWORD_SIZE) |
| 2148 | { |
| 2149 | if (value & SIGNED_DWORD_MASK) |
| 2150 | { |
| 2151 | signed_extend_mask = 0xFFFFFFFF; |
| 2152 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2153 | signed_extend_mask = ~signed_extend_mask; |
| 2154 | } |
| 2155 | value = value >> shift_steps; |
| 2156 | value |= signed_extend_mask; |
| 2157 | inst_env->reg[REG_PC] = value; |
| 2158 | } |
| 2159 | } |
| 2160 | inst_env->slot_needed = 0; |
| 2161 | inst_env->prefix_found = 0; |
| 2162 | inst_env->xflag_found = 0; |
| 2163 | inst_env->disable_interrupt = 0; |
| 2164 | } |
| 2165 | |
| 2166 | /* Handles the ASRQ instruction. */ |
| 2167 | |
| 2168 | void |
| 2169 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
| 2170 | { |
| 2171 | |
| 2172 | int shift_steps; |
| 2173 | unsigned long value; |
| 2174 | unsigned long signed_extend_mask = 0; |
| 2175 | |
| 2176 | /* ASRQ can't have a prefix, so check that it doesn't. */ |
| 2177 | if (inst_env->prefix_found) |
| 2178 | { |
| 2179 | inst_env->invalid = 1; |
| 2180 | return; |
| 2181 | } |
| 2182 | |
| 2183 | /* Check if the PC is the target register. */ |
| 2184 | if (cris_get_operand2 (inst) == REG_PC) |
| 2185 | { |
| 2186 | |
| 2187 | /* It's invalid to change the PC in a delay slot. */ |
| 2188 | if (inst_env->slot_needed) |
| 2189 | { |
| 2190 | inst_env->invalid = 1; |
| 2191 | return; |
| 2192 | } |
| 2193 | /* The shift size is given as a 5 bit quick value, i.e. we don't |
| 2194 | want the the sign bit of the quick value. */ |
| 2195 | shift_steps = cris_get_asr_shift_steps (inst); |
| 2196 | value = inst_env->reg[REG_PC]; |
| 2197 | if (value & SIGNED_DWORD_MASK) |
| 2198 | { |
| 2199 | signed_extend_mask = 0xFFFFFFFF; |
| 2200 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2201 | signed_extend_mask = ~signed_extend_mask; |
| 2202 | } |
| 2203 | value = value >> shift_steps; |
| 2204 | value |= signed_extend_mask; |
| 2205 | inst_env->reg[REG_PC] = value; |
| 2206 | } |
| 2207 | inst_env->slot_needed = 0; |
| 2208 | inst_env->prefix_found = 0; |
| 2209 | inst_env->xflag_found = 0; |
| 2210 | inst_env->disable_interrupt = 0; |
| 2211 | } |
| 2212 | |
| 2213 | /* Handles the AX, EI and SETF instruction. */ |
| 2214 | |
| 2215 | void |
| 2216 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
| 2217 | { |
| 2218 | if (inst_env->prefix_found) |
| 2219 | { |
| 2220 | inst_env->invalid = 1; |
| 2221 | return; |
| 2222 | } |
| 2223 | /* Check if the instruction is setting the X flag. */ |
| 2224 | if (cris_is_xflag_bit_on (inst)) |
| 2225 | { |
| 2226 | inst_env->xflag_found = 1; |
| 2227 | } |
| 2228 | else |
| 2229 | { |
| 2230 | inst_env->xflag_found = 0; |
| 2231 | } |
| 2232 | inst_env->slot_needed = 0; |
| 2233 | inst_env->prefix_found = 0; |
| 2234 | inst_env->disable_interrupt = 1; |
| 2235 | } |
| 2236 | |
| 2237 | /* Checks if the instruction is in assign mode. If so, it updates the assign |
| 2238 | register. Note that check_assign assumes that the caller has checked that |
| 2239 | there is a prefix to this instruction. The mode check depends on this. */ |
| 2240 | |
| 2241 | void |
| 2242 | check_assign (unsigned short inst, inst_env_type *inst_env) |
| 2243 | { |
| 2244 | /* Check if it's an assign addressing mode. */ |
| 2245 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 2246 | { |
| 2247 | /* Assign the prefix value to operand 1. */ |
| 2248 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; |
| 2249 | } |
| 2250 | } |
| 2251 | |
| 2252 | /* Handles the 2-operand BOUND instruction. */ |
| 2253 | |
| 2254 | void |
| 2255 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
| 2256 | { |
| 2257 | /* It's invalid to have the PC as the index operand. */ |
| 2258 | if (cris_get_operand2 (inst) == REG_PC) |
| 2259 | { |
| 2260 | inst_env->invalid = 1; |
| 2261 | return; |
| 2262 | } |
| 2263 | /* Check if we have a prefix. */ |
| 2264 | if (inst_env->prefix_found) |
| 2265 | { |
| 2266 | check_assign (inst, inst_env); |
| 2267 | } |
| 2268 | /* Check if this is an autoincrement mode. */ |
| 2269 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2270 | { |
| 2271 | /* It's invalid to change the PC in a delay slot. */ |
| 2272 | if (inst_env->slot_needed) |
| 2273 | { |
| 2274 | inst_env->invalid = 1; |
| 2275 | return; |
| 2276 | } |
| 2277 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 2278 | } |
| 2279 | inst_env->slot_needed = 0; |
| 2280 | inst_env->prefix_found = 0; |
| 2281 | inst_env->xflag_found = 0; |
| 2282 | inst_env->disable_interrupt = 0; |
| 2283 | } |
| 2284 | |
| 2285 | /* Handles the 3-operand BOUND instruction. */ |
| 2286 | |
| 2287 | void |
| 2288 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
| 2289 | { |
| 2290 | /* It's an error if we haven't got a prefix. And it's also an error |
| 2291 | if the PC is the destination register. */ |
| 2292 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) |
| 2293 | { |
| 2294 | inst_env->invalid = 1; |
| 2295 | return; |
| 2296 | } |
| 2297 | inst_env->slot_needed = 0; |
| 2298 | inst_env->prefix_found = 0; |
| 2299 | inst_env->xflag_found = 0; |
| 2300 | inst_env->disable_interrupt = 0; |
| 2301 | } |
| 2302 | |
| 2303 | /* Clears the status flags in inst_env. */ |
| 2304 | |
| 2305 | void |
| 2306 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
| 2307 | { |
| 2308 | /* It's an error if we have got a prefix. */ |
| 2309 | if (inst_env->prefix_found) |
| 2310 | { |
| 2311 | inst_env->invalid = 1; |
| 2312 | return; |
| 2313 | } |
| 2314 | |
| 2315 | inst_env->slot_needed = 0; |
| 2316 | inst_env->prefix_found = 0; |
| 2317 | inst_env->xflag_found = 0; |
| 2318 | inst_env->disable_interrupt = 0; |
| 2319 | } |
| 2320 | |
| 2321 | /* Clears the status flags in inst_env. */ |
| 2322 | |
| 2323 | void |
| 2324 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
| 2325 | { |
| 2326 | /* It's an error if we have got a prefix. */ |
| 2327 | if (inst_env->prefix_found) |
| 2328 | { |
| 2329 | inst_env->invalid = 1; |
| 2330 | return; |
| 2331 | } |
| 2332 | |
| 2333 | inst_env->slot_needed = 0; |
| 2334 | inst_env->prefix_found = 0; |
| 2335 | inst_env->xflag_found = 0; |
| 2336 | inst_env->disable_interrupt = 1; |
| 2337 | } |
| 2338 | |
| 2339 | /* Handles the CLEAR instruction if it's in register mode. */ |
| 2340 | |
| 2341 | void |
| 2342 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
| 2343 | { |
| 2344 | /* Check if the target is the PC. */ |
| 2345 | if (cris_get_operand2 (inst) == REG_PC) |
| 2346 | { |
| 2347 | /* The instruction will clear the instruction's size bits. */ |
| 2348 | int clear_size = cris_get_clear_size (inst); |
| 2349 | if (clear_size == INST_BYTE_SIZE) |
| 2350 | { |
| 2351 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; |
| 2352 | } |
| 2353 | if (clear_size == INST_WORD_SIZE) |
| 2354 | { |
| 2355 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; |
| 2356 | } |
| 2357 | if (clear_size == INST_DWORD_SIZE) |
| 2358 | { |
| 2359 | inst_env->delay_slot_pc = 0x0; |
| 2360 | } |
| 2361 | /* The jump will be delayed with one delay slot. So we need a delay |
| 2362 | slot. */ |
| 2363 | inst_env->slot_needed = 1; |
| 2364 | inst_env->delay_slot_pc_active = 1; |
| 2365 | } |
| 2366 | else |
| 2367 | { |
| 2368 | /* The PC will not change => no delay slot. */ |
| 2369 | inst_env->slot_needed = 0; |
| 2370 | } |
| 2371 | inst_env->prefix_found = 0; |
| 2372 | inst_env->xflag_found = 0; |
| 2373 | inst_env->disable_interrupt = 0; |
| 2374 | } |
| 2375 | |
| 2376 | /* Handles the TEST instruction if it's in register mode. */ |
| 2377 | |
| 2378 | void |
| 2379 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
| 2380 | { |
| 2381 | /* It's an error if we have got a prefix. */ |
| 2382 | if (inst_env->prefix_found) |
| 2383 | { |
| 2384 | inst_env->invalid = 1; |
| 2385 | return; |
| 2386 | } |
| 2387 | inst_env->slot_needed = 0; |
| 2388 | inst_env->prefix_found = 0; |
| 2389 | inst_env->xflag_found = 0; |
| 2390 | inst_env->disable_interrupt = 0; |
| 2391 | |
| 2392 | } |
| 2393 | |
| 2394 | /* Handles the CLEAR and TEST instruction if the instruction isn't |
| 2395 | in register mode. */ |
| 2396 | |
| 2397 | void |
| 2398 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
| 2399 | { |
| 2400 | /* Check if we are in a prefix mode. */ |
| 2401 | if (inst_env->prefix_found) |
| 2402 | { |
| 2403 | /* The only way the PC can change is if this instruction is in |
| 2404 | assign addressing mode. */ |
| 2405 | check_assign (inst, inst_env); |
| 2406 | } |
| 2407 | /* Indirect mode can't change the PC so just check if the mode is |
| 2408 | autoincrement. */ |
| 2409 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2410 | { |
| 2411 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 2412 | } |
| 2413 | inst_env->slot_needed = 0; |
| 2414 | inst_env->prefix_found = 0; |
| 2415 | inst_env->xflag_found = 0; |
| 2416 | inst_env->disable_interrupt = 0; |
| 2417 | } |
| 2418 | |
| 2419 | /* Checks that the PC isn't the destination register or the instructions has |
| 2420 | a prefix. */ |
| 2421 | |
| 2422 | void |
| 2423 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
| 2424 | { |
| 2425 | /* It's invalid to have the PC as the destination. The instruction can't |
| 2426 | have a prefix. */ |
| 2427 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) |
| 2428 | { |
| 2429 | inst_env->invalid = 1; |
| 2430 | return; |
| 2431 | } |
| 2432 | |
| 2433 | inst_env->slot_needed = 0; |
| 2434 | inst_env->prefix_found = 0; |
| 2435 | inst_env->xflag_found = 0; |
| 2436 | inst_env->disable_interrupt = 0; |
| 2437 | } |
| 2438 | |
| 2439 | /* Checks that the instruction doesn't have a prefix. */ |
| 2440 | |
| 2441 | void |
| 2442 | break_op (unsigned short inst, inst_env_type *inst_env) |
| 2443 | { |
| 2444 | /* The instruction can't have a prefix. */ |
| 2445 | if (inst_env->prefix_found) |
| 2446 | { |
| 2447 | inst_env->invalid = 1; |
| 2448 | return; |
| 2449 | } |
| 2450 | |
| 2451 | inst_env->slot_needed = 0; |
| 2452 | inst_env->prefix_found = 0; |
| 2453 | inst_env->xflag_found = 0; |
| 2454 | inst_env->disable_interrupt = 1; |
| 2455 | } |
| 2456 | |
| 2457 | /* Checks that the PC isn't the destination register and that the instruction |
| 2458 | doesn't have a prefix. */ |
| 2459 | |
| 2460 | void |
| 2461 | scc_op (unsigned short inst, inst_env_type *inst_env) |
| 2462 | { |
| 2463 | /* It's invalid to have the PC as the destination. The instruction can't |
| 2464 | have a prefix. */ |
| 2465 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) |
| 2466 | { |
| 2467 | inst_env->invalid = 1; |
| 2468 | return; |
| 2469 | } |
| 2470 | |
| 2471 | inst_env->slot_needed = 0; |
| 2472 | inst_env->prefix_found = 0; |
| 2473 | inst_env->xflag_found = 0; |
| 2474 | inst_env->disable_interrupt = 1; |
| 2475 | } |
| 2476 | |
| 2477 | /* Handles the register mode JUMP instruction. */ |
| 2478 | |
| 2479 | void |
| 2480 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
| 2481 | { |
| 2482 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so |
| 2483 | you can't have a prefix. */ |
| 2484 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) |
| 2485 | { |
| 2486 | inst_env->invalid = 1; |
| 2487 | return; |
| 2488 | } |
| 2489 | |
| 2490 | /* Just change the PC. */ |
| 2491 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; |
| 2492 | inst_env->slot_needed = 0; |
| 2493 | inst_env->prefix_found = 0; |
| 2494 | inst_env->xflag_found = 0; |
| 2495 | inst_env->disable_interrupt = 1; |
| 2496 | } |
| 2497 | |
| 2498 | /* Handles the JUMP instruction for all modes except register. */ |
| 2499 | |
| 2500 | void none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
| 2501 | { |
| 2502 | unsigned long newpc; |
| 2503 | CORE_ADDR address; |
| 2504 | |
| 2505 | /* It's invalid to do a JUMP in a delay slot. */ |
| 2506 | if (inst_env->slot_needed) |
| 2507 | { |
| 2508 | inst_env->invalid = 1; |
| 2509 | } |
| 2510 | else |
| 2511 | { |
| 2512 | /* Check if we have a prefix. */ |
| 2513 | if (inst_env->prefix_found) |
| 2514 | { |
| 2515 | check_assign (inst, inst_env); |
| 2516 | |
| 2517 | /* Get the new value for the the PC. */ |
| 2518 | newpc = |
| 2519 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, |
| 2520 | 4); |
| 2521 | } |
| 2522 | else |
| 2523 | { |
| 2524 | /* Get the new value for the PC. */ |
| 2525 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; |
| 2526 | newpc = read_memory_unsigned_integer (address, 4); |
| 2527 | |
| 2528 | /* Check if we should increment a register. */ |
| 2529 | if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2530 | { |
| 2531 | inst_env->reg[cris_get_operand1 (inst)] += 4; |
| 2532 | } |
| 2533 | } |
| 2534 | inst_env->reg[REG_PC] = newpc; |
| 2535 | } |
| 2536 | inst_env->slot_needed = 0; |
| 2537 | inst_env->prefix_found = 0; |
| 2538 | inst_env->xflag_found = 0; |
| 2539 | inst_env->disable_interrupt = 1; |
| 2540 | } |
| 2541 | |
| 2542 | /* Handles moves to special registers (aka P-register) for all modes. */ |
| 2543 | |
| 2544 | void |
| 2545 | move_to_preg_op (unsigned short inst, inst_env_type *inst_env) |
| 2546 | { |
| 2547 | if (inst_env->prefix_found) |
| 2548 | { |
| 2549 | /* The instruction has a prefix that means we are only interested if |
| 2550 | the instruction is in assign mode. */ |
| 2551 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 2552 | { |
| 2553 | /* The prefix handles the problem if we are in a delay slot. */ |
| 2554 | if (cris_get_operand1 (inst) == REG_PC) |
| 2555 | { |
| 2556 | /* Just take care of the assign. */ |
| 2557 | check_assign (inst, inst_env); |
| 2558 | } |
| 2559 | } |
| 2560 | } |
| 2561 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2562 | { |
| 2563 | /* The instruction doesn't have a prefix, the only case left that we |
| 2564 | are interested in is the autoincrement mode. */ |
| 2565 | if (cris_get_operand1 (inst) == REG_PC) |
| 2566 | { |
| 2567 | /* If the PC is to be incremented it's invalid to be in a |
| 2568 | delay slot. */ |
| 2569 | if (inst_env->slot_needed) |
| 2570 | { |
| 2571 | inst_env->invalid = 1; |
| 2572 | return; |
| 2573 | } |
| 2574 | /* The increment depends on the size of the special register. |
| 2575 | Register P0 to P3 has the size byte, register P4 to P7 has the |
| 2576 | size word and register P8 to P15 has the size dword. */ |
| 2577 | if (cris_get_operand2 (inst) < 4) |
| 2578 | { |
| 2579 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); |
| 2580 | } |
| 2581 | if (cris_get_operand2 (inst) < 8) |
| 2582 | { |
| 2583 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); |
| 2584 | } |
| 2585 | else |
| 2586 | { |
| 2587 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); |
| 2588 | } |
| 2589 | } |
| 2590 | } |
| 2591 | inst_env->slot_needed = 0; |
| 2592 | inst_env->prefix_found = 0; |
| 2593 | inst_env->xflag_found = 0; |
| 2594 | inst_env->disable_interrupt = 1; |
| 2595 | } |
| 2596 | |
| 2597 | /* Handles moves from special registers (aka P-register) for all modes |
| 2598 | except register. */ |
| 2599 | |
| 2600 | void |
| 2601 | none_reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
| 2602 | { |
| 2603 | if (inst_env->prefix_found) |
| 2604 | { |
| 2605 | /* The instruction has a prefix that means we are only interested if |
| 2606 | the instruction is in assign mode. */ |
| 2607 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 2608 | { |
| 2609 | /* The prefix handles the problem if we are in a delay slot. */ |
| 2610 | if (cris_get_operand1 (inst) == REG_PC) |
| 2611 | { |
| 2612 | /* Just take care of the assign. */ |
| 2613 | check_assign (inst, inst_env); |
| 2614 | } |
| 2615 | } |
| 2616 | } |
| 2617 | /* The instruction doesn't have a prefix, the only case left that we |
| 2618 | are interested in is the autoincrement mode. */ |
| 2619 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2620 | { |
| 2621 | if (cris_get_operand1 (inst) == REG_PC) |
| 2622 | { |
| 2623 | /* If the PC is to be incremented it's invalid to be in a |
| 2624 | delay slot. */ |
| 2625 | if (inst_env->slot_needed) |
| 2626 | { |
| 2627 | inst_env->invalid = 1; |
| 2628 | return; |
| 2629 | } |
| 2630 | /* The increment depends on the size of the special register. |
| 2631 | Register P0 to P3 has the size byte, register P4 to P7 has |
| 2632 | the size word and register P8 to P15 has the size dword. */ |
| 2633 | if (cris_get_operand2 (inst) < 4) |
| 2634 | { |
| 2635 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); |
| 2636 | } |
| 2637 | if (cris_get_operand2 (inst) < 8) |
| 2638 | { |
| 2639 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); |
| 2640 | } |
| 2641 | else |
| 2642 | { |
| 2643 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); |
| 2644 | } |
| 2645 | } |
| 2646 | } |
| 2647 | inst_env->slot_needed = 0; |
| 2648 | inst_env->prefix_found = 0; |
| 2649 | inst_env->xflag_found = 0; |
| 2650 | inst_env->disable_interrupt = 1; |
| 2651 | } |
| 2652 | |
| 2653 | /* Handles moves from special registers (aka P-register) when the mode |
| 2654 | is register. */ |
| 2655 | |
| 2656 | void |
| 2657 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
| 2658 | { |
| 2659 | /* Register mode move from special register can't have a prefix. */ |
| 2660 | if (inst_env->prefix_found) |
| 2661 | { |
| 2662 | inst_env->invalid = 1; |
| 2663 | return; |
| 2664 | } |
| 2665 | |
| 2666 | if (cris_get_operand1 (inst) == REG_PC) |
| 2667 | { |
| 2668 | /* It's invalid to change the PC in a delay slot. */ |
| 2669 | if (inst_env->slot_needed) |
| 2670 | { |
| 2671 | inst_env->invalid = 1; |
| 2672 | return; |
| 2673 | } |
| 2674 | /* The destination is the PC, the jump will have a delay slot. */ |
| 2675 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; |
| 2676 | inst_env->slot_needed = 1; |
| 2677 | inst_env->delay_slot_pc_active = 1; |
| 2678 | } |
| 2679 | else |
| 2680 | { |
| 2681 | /* If the destination isn't PC, there will be no jump. */ |
| 2682 | inst_env->slot_needed = 0; |
| 2683 | } |
| 2684 | inst_env->prefix_found = 0; |
| 2685 | inst_env->xflag_found = 0; |
| 2686 | inst_env->disable_interrupt = 1; |
| 2687 | } |
| 2688 | |
| 2689 | /* Handles the MOVEM from memory to general register instruction. */ |
| 2690 | |
| 2691 | void |
| 2692 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
| 2693 | { |
| 2694 | if (inst_env->prefix_found) |
| 2695 | { |
| 2696 | /* The prefix handles the problem if we are in a delay slot. Is the |
| 2697 | MOVEM instruction going to change the PC? */ |
| 2698 | if (cris_get_operand2 (inst) >= REG_PC) |
| 2699 | { |
| 2700 | inst_env->reg[REG_PC] = |
| 2701 | read_memory_unsigned_integer (inst_env->prefix_value, 4); |
| 2702 | } |
| 2703 | /* The assign value is the value after the increment. Normally, the |
| 2704 | assign value is the value before the increment. */ |
| 2705 | if ((cris_get_operand1 (inst) == REG_PC) |
| 2706 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) |
| 2707 | { |
| 2708 | inst_env->reg[REG_PC] = inst_env->prefix_value; |
| 2709 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 2710 | } |
| 2711 | } |
| 2712 | else |
| 2713 | { |
| 2714 | /* Is the MOVEM instruction going to change the PC? */ |
| 2715 | if (cris_get_operand2 (inst) == REG_PC) |
| 2716 | { |
| 2717 | /* It's invalid to change the PC in a delay slot. */ |
| 2718 | if (inst_env->slot_needed) |
| 2719 | { |
| 2720 | inst_env->invalid = 1; |
| 2721 | return; |
| 2722 | } |
| 2723 | inst_env->reg[REG_PC] = |
| 2724 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], |
| 2725 | 4); |
| 2726 | } |
| 2727 | /* The increment is not depending on the size, instead it's depending |
| 2728 | on the number of registers loaded from memory. */ |
| 2729 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 2730 | { |
| 2731 | /* It's invalid to change the PC in a delay slot. */ |
| 2732 | if (inst_env->slot_needed) |
| 2733 | { |
| 2734 | inst_env->invalid = 1; |
| 2735 | return; |
| 2736 | } |
| 2737 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 2738 | } |
| 2739 | } |
| 2740 | inst_env->slot_needed = 0; |
| 2741 | inst_env->prefix_found = 0; |
| 2742 | inst_env->xflag_found = 0; |
| 2743 | inst_env->disable_interrupt = 0; |
| 2744 | } |
| 2745 | |
| 2746 | /* Handles the MOVEM to memory from general register instruction. */ |
| 2747 | |
| 2748 | void |
| 2749 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
| 2750 | { |
| 2751 | if (inst_env->prefix_found) |
| 2752 | { |
| 2753 | /* The assign value is the value after the increment. Normally, the |
| 2754 | assign value is the value before the increment. */ |
| 2755 | if ((cris_get_operand1 (inst) == REG_PC) && |
| 2756 | (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) |
| 2757 | { |
| 2758 | /* The prefix handles the problem if we are in a delay slot. */ |
| 2759 | inst_env->reg[REG_PC] = inst_env->prefix_value; |
| 2760 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 2761 | } |
| 2762 | } |
| 2763 | else |
| 2764 | { |
| 2765 | /* The increment is not depending on the size, instead it's depending |
| 2766 | on the number of registers loaded to memory. */ |
| 2767 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 2768 | { |
| 2769 | /* It's invalid to change the PC in a delay slot. */ |
| 2770 | if (inst_env->slot_needed) |
| 2771 | { |
| 2772 | inst_env->invalid = 1; |
| 2773 | return; |
| 2774 | } |
| 2775 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 2776 | } |
| 2777 | } |
| 2778 | inst_env->slot_needed = 0; |
| 2779 | inst_env->prefix_found = 0; |
| 2780 | inst_env->xflag_found = 0; |
| 2781 | inst_env->disable_interrupt = 0; |
| 2782 | } |
| 2783 | |
| 2784 | /* Handles the pop instruction to a general register. |
| 2785 | POP is a assembler macro for MOVE.D [SP+], Rd. */ |
| 2786 | |
| 2787 | void |
| 2788 | reg_pop_op (unsigned short inst, inst_env_type *inst_env) |
| 2789 | { |
| 2790 | /* POP can't have a prefix. */ |
| 2791 | if (inst_env->prefix_found) |
| 2792 | { |
| 2793 | inst_env->invalid = 1; |
| 2794 | return; |
| 2795 | } |
| 2796 | if (cris_get_operand2 (inst) == REG_PC) |
| 2797 | { |
| 2798 | /* It's invalid to change the PC in a delay slot. */ |
| 2799 | if (inst_env->slot_needed) |
| 2800 | { |
| 2801 | inst_env->invalid = 1; |
| 2802 | return; |
| 2803 | } |
| 2804 | inst_env->reg[REG_PC] = |
| 2805 | read_memory_unsigned_integer (inst_env->reg[REG_SP], 4); |
| 2806 | } |
| 2807 | inst_env->slot_needed = 0; |
| 2808 | inst_env->prefix_found = 0; |
| 2809 | inst_env->xflag_found = 0; |
| 2810 | inst_env->disable_interrupt = 0; |
| 2811 | } |
| 2812 | |
| 2813 | /* Handles moves from register to memory. */ |
| 2814 | |
| 2815 | void |
| 2816 | move_reg_to_mem_index_inc_op (unsigned short inst, inst_env_type *inst_env) |
| 2817 | { |
| 2818 | /* Check if we have a prefix. */ |
| 2819 | if (inst_env->prefix_found) |
| 2820 | { |
| 2821 | /* The only thing that can change the PC is an assign. */ |
| 2822 | check_assign (inst, inst_env); |
| 2823 | } |
| 2824 | else if ((cris_get_operand1 (inst) == REG_PC) |
| 2825 | && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 2826 | { |
| 2827 | /* It's invalid to change the PC in a delay slot. */ |
| 2828 | if (inst_env->slot_needed) |
| 2829 | { |
| 2830 | inst_env->invalid = 1; |
| 2831 | return; |
| 2832 | } |
| 2833 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 2834 | } |
| 2835 | inst_env->slot_needed = 0; |
| 2836 | inst_env->prefix_found = 0; |
| 2837 | inst_env->xflag_found = 0; |
| 2838 | inst_env->disable_interrupt = 0; |
| 2839 | } |
| 2840 | |
| 2841 | /* Handles the intructions that's not yet implemented, by setting |
| 2842 | inst_env->invalid to true. */ |
| 2843 | |
| 2844 | void |
| 2845 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
| 2846 | { |
| 2847 | inst_env->invalid = 1; |
| 2848 | } |
| 2849 | |
| 2850 | /* Handles the XOR instruction. */ |
| 2851 | |
| 2852 | void |
| 2853 | xor_op (unsigned short inst, inst_env_type *inst_env) |
| 2854 | { |
| 2855 | /* XOR can't have a prefix. */ |
| 2856 | if (inst_env->prefix_found) |
| 2857 | { |
| 2858 | inst_env->invalid = 1; |
| 2859 | return; |
| 2860 | } |
| 2861 | |
| 2862 | /* Check if the PC is the target. */ |
| 2863 | if (cris_get_operand2 (inst) == REG_PC) |
| 2864 | { |
| 2865 | /* It's invalid to change the PC in a delay slot. */ |
| 2866 | if (inst_env->slot_needed) |
| 2867 | { |
| 2868 | inst_env->invalid = 1; |
| 2869 | return; |
| 2870 | } |
| 2871 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; |
| 2872 | } |
| 2873 | inst_env->slot_needed = 0; |
| 2874 | inst_env->prefix_found = 0; |
| 2875 | inst_env->xflag_found = 0; |
| 2876 | inst_env->disable_interrupt = 0; |
| 2877 | } |
| 2878 | |
| 2879 | /* Handles the MULS instruction. */ |
| 2880 | |
| 2881 | void |
| 2882 | muls_op (unsigned short inst, inst_env_type *inst_env) |
| 2883 | { |
| 2884 | /* MULS/U can't have a prefix. */ |
| 2885 | if (inst_env->prefix_found) |
| 2886 | { |
| 2887 | inst_env->invalid = 1; |
| 2888 | return; |
| 2889 | } |
| 2890 | |
| 2891 | /* Consider it invalid if the PC is the target. */ |
| 2892 | if (cris_get_operand2 (inst) == REG_PC) |
| 2893 | { |
| 2894 | inst_env->invalid = 1; |
| 2895 | return; |
| 2896 | } |
| 2897 | inst_env->slot_needed = 0; |
| 2898 | inst_env->prefix_found = 0; |
| 2899 | inst_env->xflag_found = 0; |
| 2900 | inst_env->disable_interrupt = 0; |
| 2901 | } |
| 2902 | |
| 2903 | /* Handles the MULU instruction. */ |
| 2904 | |
| 2905 | void |
| 2906 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
| 2907 | { |
| 2908 | /* MULS/U can't have a prefix. */ |
| 2909 | if (inst_env->prefix_found) |
| 2910 | { |
| 2911 | inst_env->invalid = 1; |
| 2912 | return; |
| 2913 | } |
| 2914 | |
| 2915 | /* Consider it invalid if the PC is the target. */ |
| 2916 | if (cris_get_operand2 (inst) == REG_PC) |
| 2917 | { |
| 2918 | inst_env->invalid = 1; |
| 2919 | return; |
| 2920 | } |
| 2921 | inst_env->slot_needed = 0; |
| 2922 | inst_env->prefix_found = 0; |
| 2923 | inst_env->xflag_found = 0; |
| 2924 | inst_env->disable_interrupt = 0; |
| 2925 | } |
| 2926 | |
| 2927 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. |
| 2928 | The MOVE instruction is the move from source to register. */ |
| 2929 | |
| 2930 | void |
| 2931 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
| 2932 | unsigned long source1, unsigned long source2) |
| 2933 | { |
| 2934 | unsigned long pc_mask; |
| 2935 | unsigned long operation_mask; |
| 2936 | |
| 2937 | /* Find out how many bits the operation should apply to. */ |
| 2938 | if (cris_get_size (inst) == INST_BYTE_SIZE) |
| 2939 | { |
| 2940 | pc_mask = 0xFFFFFF00; |
| 2941 | operation_mask = 0xFF; |
| 2942 | } |
| 2943 | else if (cris_get_size (inst) == INST_WORD_SIZE) |
| 2944 | { |
| 2945 | pc_mask = 0xFFFF0000; |
| 2946 | operation_mask = 0xFFFF; |
| 2947 | } |
| 2948 | else if (cris_get_size (inst) == INST_DWORD_SIZE) |
| 2949 | { |
| 2950 | pc_mask = 0x0; |
| 2951 | operation_mask = 0xFFFFFFFF; |
| 2952 | } |
| 2953 | else |
| 2954 | { |
| 2955 | /* The size is out of range. */ |
| 2956 | inst_env->invalid = 1; |
| 2957 | return; |
| 2958 | } |
| 2959 | |
| 2960 | /* The instruction just works on uw_operation_mask bits. */ |
| 2961 | source2 &= operation_mask; |
| 2962 | source1 &= operation_mask; |
| 2963 | |
| 2964 | /* Now calculate the result. The opcode's 3 first bits separates |
| 2965 | the different actions. */ |
| 2966 | switch (cris_get_opcode (inst) & 7) |
| 2967 | { |
| 2968 | case 0: /* add */ |
| 2969 | source1 += source2; |
| 2970 | break; |
| 2971 | |
| 2972 | case 1: /* move */ |
| 2973 | source1 = source2; |
| 2974 | break; |
| 2975 | |
| 2976 | case 2: /* subtract */ |
| 2977 | source1 -= source2; |
| 2978 | break; |
| 2979 | |
| 2980 | case 3: /* compare */ |
| 2981 | break; |
| 2982 | |
| 2983 | case 4: /* and */ |
| 2984 | source1 &= source2; |
| 2985 | break; |
| 2986 | |
| 2987 | case 5: /* or */ |
| 2988 | source1 |= source2; |
| 2989 | break; |
| 2990 | |
| 2991 | default: |
| 2992 | inst_env->invalid = 1; |
| 2993 | return; |
| 2994 | |
| 2995 | break; |
| 2996 | } |
| 2997 | |
| 2998 | /* Make sure that the result doesn't contain more than the instruction |
| 2999 | size bits. */ |
| 3000 | source2 &= operation_mask; |
| 3001 | |
| 3002 | /* Calculate the new breakpoint address. */ |
| 3003 | inst_env->reg[REG_PC] &= pc_mask; |
| 3004 | inst_env->reg[REG_PC] |= source1; |
| 3005 | |
| 3006 | } |
| 3007 | |
| 3008 | /* Extends the value from either byte or word size to a dword. If the mode |
| 3009 | is zero extend then the value is extended with zero. If instead the mode |
| 3010 | is signed extend the sign bit of the value is taken into consideration. */ |
| 3011 | |
| 3012 | unsigned long |
| 3013 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
| 3014 | { |
| 3015 | /* The size can be either byte or word, check which one it is. |
| 3016 | Don't check the highest bit, it's indicating if it's a zero |
| 3017 | or sign extend. */ |
| 3018 | if (cris_get_size (*inst) & INST_WORD_SIZE) |
| 3019 | { |
| 3020 | /* Word size. */ |
| 3021 | value &= 0xFFFF; |
| 3022 | |
| 3023 | /* Check if the instruction is signed extend. If so, check if value has |
| 3024 | the sign bit on. */ |
| 3025 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) |
| 3026 | { |
| 3027 | value |= SIGNED_WORD_EXTEND_MASK; |
| 3028 | } |
| 3029 | } |
| 3030 | else |
| 3031 | { |
| 3032 | /* Byte size. */ |
| 3033 | value &= 0xFF; |
| 3034 | |
| 3035 | /* Check if the instruction is signed extend. If so, check if value has |
| 3036 | the sign bit on. */ |
| 3037 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) |
| 3038 | { |
| 3039 | value |= SIGNED_BYTE_EXTEND_MASK; |
| 3040 | } |
| 3041 | } |
| 3042 | /* The size should now be dword. */ |
| 3043 | cris_set_size_to_dword (inst); |
| 3044 | return value; |
| 3045 | } |
| 3046 | |
| 3047 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE |
| 3048 | instruction. The MOVE instruction is the move from source to register. */ |
| 3049 | |
| 3050 | void |
| 3051 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
| 3052 | inst_env_type *inst_env) |
| 3053 | { |
| 3054 | unsigned long operand1; |
| 3055 | unsigned long operand2; |
| 3056 | |
| 3057 | /* It's invalid to have a prefix to the instruction. This is a register |
| 3058 | mode instruction and can't have a prefix. */ |
| 3059 | if (inst_env->prefix_found) |
| 3060 | { |
| 3061 | inst_env->invalid = 1; |
| 3062 | return; |
| 3063 | } |
| 3064 | /* Check if the instruction has PC as its target. */ |
| 3065 | if (cris_get_operand2 (inst) == REG_PC) |
| 3066 | { |
| 3067 | if (inst_env->slot_needed) |
| 3068 | { |
| 3069 | inst_env->invalid = 1; |
| 3070 | return; |
| 3071 | } |
| 3072 | /* The instruction has the PC as its target register. */ |
| 3073 | operand1 = inst_env->reg[operand1]; |
| 3074 | operand2 = inst_env->reg[REG_PC]; |
| 3075 | |
| 3076 | /* Check if it's a extend, signed or zero instruction. */ |
| 3077 | if (cris_get_opcode (inst) < 4) |
| 3078 | { |
| 3079 | operand1 = do_sign_or_zero_extend (operand1, &inst); |
| 3080 | } |
| 3081 | /* Calculate the PC value after the instruction, i.e. where the |
| 3082 | breakpoint should be. The order of the udw_operands is vital. */ |
| 3083 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
| 3084 | } |
| 3085 | inst_env->slot_needed = 0; |
| 3086 | inst_env->prefix_found = 0; |
| 3087 | inst_env->xflag_found = 0; |
| 3088 | inst_env->disable_interrupt = 0; |
| 3089 | } |
| 3090 | |
| 3091 | /* Returns the data contained at address. The size of the data is derived from |
| 3092 | the size of the operation. If the instruction is a zero or signed |
| 3093 | extend instruction, the size field is changed in instruction. */ |
| 3094 | |
| 3095 | unsigned long |
| 3096 | get_data_from_address (unsigned short *inst, CORE_ADDR address) |
| 3097 | { |
| 3098 | int size = cris_get_size (*inst); |
| 3099 | unsigned long value; |
| 3100 | |
| 3101 | /* If it's an extend instruction we don't want the signed extend bit, |
| 3102 | because it influences the size. */ |
| 3103 | if (cris_get_opcode (*inst) < 4) |
| 3104 | { |
| 3105 | size &= ~SIGNED_EXTEND_BIT_MASK; |
| 3106 | } |
| 3107 | /* Is there a need for checking the size? Size should contain the number of |
| 3108 | bytes to read. */ |
| 3109 | size = 1 << size; |
| 3110 | value = read_memory_unsigned_integer (address, size); |
| 3111 | |
| 3112 | /* Check if it's an extend, signed or zero instruction. */ |
| 3113 | if (cris_get_opcode (*inst) < 4) |
| 3114 | { |
| 3115 | value = do_sign_or_zero_extend (value, inst); |
| 3116 | } |
| 3117 | return value; |
| 3118 | } |
| 3119 | |
| 3120 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE |
| 3121 | instructions. The MOVE instruction is the move from source to register. */ |
| 3122 | |
| 3123 | void |
| 3124 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
| 3125 | inst_env_type *inst_env) |
| 3126 | { |
| 3127 | unsigned long operand2; |
| 3128 | unsigned long operand3; |
| 3129 | |
| 3130 | check_assign (inst, inst_env); |
| 3131 | if (cris_get_operand2 (inst) == REG_PC) |
| 3132 | { |
| 3133 | operand2 = inst_env->reg[REG_PC]; |
| 3134 | |
| 3135 | /* Get the value of the third operand. */ |
| 3136 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); |
| 3137 | |
| 3138 | /* Calculate the PC value after the instruction, i.e. where the |
| 3139 | breakpoint should be. The order of the udw_operands is vital. */ |
| 3140 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
| 3141 | } |
| 3142 | inst_env->slot_needed = 0; |
| 3143 | inst_env->prefix_found = 0; |
| 3144 | inst_env->xflag_found = 0; |
| 3145 | inst_env->disable_interrupt = 0; |
| 3146 | } |
| 3147 | |
| 3148 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and |
| 3149 | OR instructions. Note that for this to work as expected, the calling |
| 3150 | function must have made sure that there is a prefix to this instruction. */ |
| 3151 | |
| 3152 | void |
| 3153 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
| 3154 | inst_env_type *inst_env) |
| 3155 | { |
| 3156 | unsigned long operand2; |
| 3157 | unsigned long operand3; |
| 3158 | |
| 3159 | if (cris_get_operand1 (inst) == REG_PC) |
| 3160 | { |
| 3161 | /* The PC will be changed by the instruction. */ |
| 3162 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; |
| 3163 | |
| 3164 | /* Get the value of the third operand. */ |
| 3165 | operand3 = get_data_from_address (&inst, inst_env->prefix_value); |
| 3166 | |
| 3167 | /* Calculate the PC value after the instruction, i.e. where the |
| 3168 | breakpoint should be. */ |
| 3169 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
| 3170 | } |
| 3171 | inst_env->slot_needed = 0; |
| 3172 | inst_env->prefix_found = 0; |
| 3173 | inst_env->xflag_found = 0; |
| 3174 | inst_env->disable_interrupt = 0; |
| 3175 | } |
| 3176 | |
| 3177 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE |
| 3178 | instructions. The MOVE instruction is the move from source to register. */ |
| 3179 | |
| 3180 | void |
| 3181 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
| 3182 | inst_env_type *inst_env) |
| 3183 | { |
| 3184 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) |
| 3185 | { |
| 3186 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, |
| 3187 | SUB, AND or OR something weird is going on (if everything works these |
| 3188 | instructions should end up in the three operand version). */ |
| 3189 | inst_env->invalid = 1; |
| 3190 | return; |
| 3191 | } |
| 3192 | else |
| 3193 | { |
| 3194 | /* three_operand_add_sub_cmp_and_or does the same as we should do here |
| 3195 | so use it. */ |
| 3196 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); |
| 3197 | } |
| 3198 | inst_env->slot_needed = 0; |
| 3199 | inst_env->prefix_found = 0; |
| 3200 | inst_env->xflag_found = 0; |
| 3201 | inst_env->disable_interrupt = 0; |
| 3202 | } |
| 3203 | |
| 3204 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, |
| 3205 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from |
| 3206 | source to register. */ |
| 3207 | |
| 3208 | void |
| 3209 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
| 3210 | inst_env_type *inst_env) |
| 3211 | { |
| 3212 | unsigned long operand1; |
| 3213 | unsigned long operand2; |
| 3214 | unsigned long operand3; |
| 3215 | int size; |
| 3216 | |
| 3217 | /* The instruction is either an indirect or autoincrement addressing mode. |
| 3218 | Check if the destination register is the PC. */ |
| 3219 | if (cris_get_operand2 (inst) == REG_PC) |
| 3220 | { |
| 3221 | /* Must be done here, get_data_from_address may change the size |
| 3222 | field. */ |
| 3223 | size = cris_get_size (inst); |
| 3224 | operand2 = inst_env->reg[REG_PC]; |
| 3225 | |
| 3226 | /* Get the value of the third operand, i.e. the indirect operand. */ |
| 3227 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
| 3228 | operand3 = get_data_from_address (&inst, operand1); |
| 3229 | |
| 3230 | /* Calculate the PC value after the instruction, i.e. where the |
| 3231 | breakpoint should be. The order of the udw_operands is vital. */ |
| 3232 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
| 3233 | } |
| 3234 | /* If this is an autoincrement addressing mode, check if the increment |
| 3235 | changes the PC. */ |
| 3236 | if ((cris_get_operand1 (inst) == REG_PC) && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 3237 | { |
| 3238 | /* Get the size field. */ |
| 3239 | size = cris_get_size (inst); |
| 3240 | |
| 3241 | /* If it's an extend instruction we don't want the signed extend bit, |
| 3242 | because it influences the size. */ |
| 3243 | if (cris_get_opcode (inst) < 4) |
| 3244 | { |
| 3245 | size &= ~SIGNED_EXTEND_BIT_MASK; |
| 3246 | } |
| 3247 | process_autoincrement (size, inst, inst_env); |
| 3248 | } |
| 3249 | inst_env->slot_needed = 0; |
| 3250 | inst_env->prefix_found = 0; |
| 3251 | inst_env->xflag_found = 0; |
| 3252 | inst_env->disable_interrupt = 0; |
| 3253 | } |
| 3254 | |
| 3255 | /* Handles the two-operand addressing mode, all modes except register, for |
| 3256 | the ADD, SUB CMP, AND and OR instruction. */ |
| 3257 | |
| 3258 | void |
| 3259 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
| 3260 | inst_env_type *inst_env) |
| 3261 | { |
| 3262 | if (inst_env->prefix_found) |
| 3263 | { |
| 3264 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) |
| 3265 | { |
| 3266 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); |
| 3267 | } |
| 3268 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 3269 | { |
| 3270 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); |
| 3271 | } |
| 3272 | else |
| 3273 | { |
| 3274 | /* The mode is invalid for a prefixed base instruction. */ |
| 3275 | inst_env->invalid = 1; |
| 3276 | return; |
| 3277 | } |
| 3278 | } |
| 3279 | else |
| 3280 | { |
| 3281 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); |
| 3282 | } |
| 3283 | } |
| 3284 | |
| 3285 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ |
| 3286 | |
| 3287 | void |
| 3288 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
| 3289 | { |
| 3290 | unsigned long operand1; |
| 3291 | unsigned long operand2; |
| 3292 | |
| 3293 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode |
| 3294 | instruction and can't have a prefix. */ |
| 3295 | if (inst_env->prefix_found) |
| 3296 | { |
| 3297 | inst_env->invalid = 1; |
| 3298 | return; |
| 3299 | } |
| 3300 | |
| 3301 | /* Check if the instruction has PC as its target. */ |
| 3302 | if (cris_get_operand2 (inst) == REG_PC) |
| 3303 | { |
| 3304 | if (inst_env->slot_needed) |
| 3305 | { |
| 3306 | inst_env->invalid = 1; |
| 3307 | return; |
| 3308 | } |
| 3309 | operand1 = cris_get_quick_value (inst); |
| 3310 | operand2 = inst_env->reg[REG_PC]; |
| 3311 | |
| 3312 | /* The size should now be dword. */ |
| 3313 | cris_set_size_to_dword (&inst); |
| 3314 | |
| 3315 | /* Calculate the PC value after the instruction, i.e. where the |
| 3316 | breakpoint should be. */ |
| 3317 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
| 3318 | } |
| 3319 | inst_env->slot_needed = 0; |
| 3320 | inst_env->prefix_found = 0; |
| 3321 | inst_env->xflag_found = 0; |
| 3322 | inst_env->disable_interrupt = 0; |
| 3323 | } |
| 3324 | |
| 3325 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ |
| 3326 | |
| 3327 | void |
| 3328 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
| 3329 | { |
| 3330 | unsigned long operand1; |
| 3331 | unsigned long operand2; |
| 3332 | |
| 3333 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode |
| 3334 | instruction and can't have a prefix. */ |
| 3335 | if (inst_env->prefix_found) |
| 3336 | { |
| 3337 | inst_env->invalid = 1; |
| 3338 | return; |
| 3339 | } |
| 3340 | /* Check if the instruction has PC as its target. */ |
| 3341 | if (cris_get_operand2 (inst) == REG_PC) |
| 3342 | { |
| 3343 | if (inst_env->slot_needed) |
| 3344 | { |
| 3345 | inst_env->invalid = 1; |
| 3346 | return; |
| 3347 | } |
| 3348 | /* The instruction has the PC as its target register. */ |
| 3349 | operand1 = cris_get_quick_value (inst); |
| 3350 | operand2 = inst_env->reg[REG_PC]; |
| 3351 | |
| 3352 | /* The quick value is signed, so check if we must do a signed extend. */ |
| 3353 | if (operand1 & SIGNED_QUICK_VALUE_MASK) |
| 3354 | { |
| 3355 | /* sign extend */ |
| 3356 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; |
| 3357 | } |
| 3358 | /* The size should now be dword. */ |
| 3359 | cris_set_size_to_dword (&inst); |
| 3360 | |
| 3361 | /* Calculate the PC value after the instruction, i.e. where the |
| 3362 | breakpoint should be. */ |
| 3363 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
| 3364 | } |
| 3365 | inst_env->slot_needed = 0; |
| 3366 | inst_env->prefix_found = 0; |
| 3367 | inst_env->xflag_found = 0; |
| 3368 | inst_env->disable_interrupt = 0; |
| 3369 | } |
| 3370 | |
| 3371 | /* Translate op_type to a function and call it. */ |
| 3372 | |
| 3373 | static void cris_gdb_func (enum cris_op_type op_type, unsigned short inst, |
| 3374 | inst_env_type *inst_env) |
| 3375 | { |
| 3376 | switch (op_type) |
| 3377 | { |
| 3378 | case cris_not_implemented_op: |
| 3379 | not_implemented_op (inst, inst_env); |
| 3380 | break; |
| 3381 | |
| 3382 | case cris_abs_op: |
| 3383 | abs_op (inst, inst_env); |
| 3384 | break; |
| 3385 | |
| 3386 | case cris_addi_op: |
| 3387 | addi_op (inst, inst_env); |
| 3388 | break; |
| 3389 | |
| 3390 | case cris_asr_op: |
| 3391 | asr_op (inst, inst_env); |
| 3392 | break; |
| 3393 | |
| 3394 | case cris_asrq_op: |
| 3395 | asrq_op (inst, inst_env); |
| 3396 | break; |
| 3397 | |
| 3398 | case cris_ax_ei_setf_op: |
| 3399 | ax_ei_setf_op (inst, inst_env); |
| 3400 | break; |
| 3401 | |
| 3402 | case cris_bdap_prefix: |
| 3403 | bdap_prefix (inst, inst_env); |
| 3404 | break; |
| 3405 | |
| 3406 | case cris_biap_prefix: |
| 3407 | biap_prefix (inst, inst_env); |
| 3408 | break; |
| 3409 | |
| 3410 | case cris_break_op: |
| 3411 | break_op (inst, inst_env); |
| 3412 | break; |
| 3413 | |
| 3414 | case cris_btst_nop_op: |
| 3415 | btst_nop_op (inst, inst_env); |
| 3416 | break; |
| 3417 | |
| 3418 | case cris_clearf_di_op: |
| 3419 | clearf_di_op (inst, inst_env); |
| 3420 | break; |
| 3421 | |
| 3422 | case cris_dip_prefix: |
| 3423 | dip_prefix (inst, inst_env); |
| 3424 | break; |
| 3425 | |
| 3426 | case cris_dstep_logshift_mstep_neg_not_op: |
| 3427 | dstep_logshift_mstep_neg_not_op (inst, inst_env); |
| 3428 | break; |
| 3429 | |
| 3430 | case cris_eight_bit_offset_branch_op: |
| 3431 | eight_bit_offset_branch_op (inst, inst_env); |
| 3432 | break; |
| 3433 | |
| 3434 | case cris_move_mem_to_reg_movem_op: |
| 3435 | move_mem_to_reg_movem_op (inst, inst_env); |
| 3436 | break; |
| 3437 | |
| 3438 | case cris_move_reg_to_mem_movem_op: |
| 3439 | move_reg_to_mem_movem_op (inst, inst_env); |
| 3440 | break; |
| 3441 | |
| 3442 | case cris_move_to_preg_op: |
| 3443 | move_to_preg_op (inst, inst_env); |
| 3444 | break; |
| 3445 | |
| 3446 | case cris_muls_op: |
| 3447 | muls_op (inst, inst_env); |
| 3448 | break; |
| 3449 | |
| 3450 | case cris_mulu_op: |
| 3451 | mulu_op (inst, inst_env); |
| 3452 | break; |
| 3453 | |
| 3454 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: |
| 3455 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); |
| 3456 | break; |
| 3457 | |
| 3458 | case cris_none_reg_mode_clear_test_op: |
| 3459 | none_reg_mode_clear_test_op (inst, inst_env); |
| 3460 | break; |
| 3461 | |
| 3462 | case cris_none_reg_mode_jump_op: |
| 3463 | none_reg_mode_jump_op (inst, inst_env); |
| 3464 | break; |
| 3465 | |
| 3466 | case cris_none_reg_mode_move_from_preg_op: |
| 3467 | none_reg_mode_move_from_preg_op (inst, inst_env); |
| 3468 | break; |
| 3469 | |
| 3470 | case cris_quick_mode_add_sub_op: |
| 3471 | quick_mode_add_sub_op (inst, inst_env); |
| 3472 | break; |
| 3473 | |
| 3474 | case cris_quick_mode_and_cmp_move_or_op: |
| 3475 | quick_mode_and_cmp_move_or_op (inst, inst_env); |
| 3476 | break; |
| 3477 | |
| 3478 | case cris_quick_mode_bdap_prefix: |
| 3479 | quick_mode_bdap_prefix (inst, inst_env); |
| 3480 | break; |
| 3481 | |
| 3482 | case cris_reg_mode_add_sub_cmp_and_or_move_op: |
| 3483 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); |
| 3484 | break; |
| 3485 | |
| 3486 | case cris_reg_mode_clear_op: |
| 3487 | reg_mode_clear_op (inst, inst_env); |
| 3488 | break; |
| 3489 | |
| 3490 | case cris_reg_mode_jump_op: |
| 3491 | reg_mode_jump_op (inst, inst_env); |
| 3492 | break; |
| 3493 | |
| 3494 | case cris_reg_mode_move_from_preg_op: |
| 3495 | reg_mode_move_from_preg_op (inst, inst_env); |
| 3496 | break; |
| 3497 | |
| 3498 | case cris_reg_mode_test_op: |
| 3499 | reg_mode_test_op (inst, inst_env); |
| 3500 | break; |
| 3501 | |
| 3502 | case cris_scc_op: |
| 3503 | scc_op (inst, inst_env); |
| 3504 | break; |
| 3505 | |
| 3506 | case cris_sixteen_bit_offset_branch_op: |
| 3507 | sixteen_bit_offset_branch_op (inst, inst_env); |
| 3508 | break; |
| 3509 | |
| 3510 | case cris_three_operand_add_sub_cmp_and_or_op: |
| 3511 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); |
| 3512 | break; |
| 3513 | |
| 3514 | case cris_three_operand_bound_op: |
| 3515 | three_operand_bound_op (inst, inst_env); |
| 3516 | break; |
| 3517 | |
| 3518 | case cris_two_operand_bound_op: |
| 3519 | two_operand_bound_op (inst, inst_env); |
| 3520 | break; |
| 3521 | |
| 3522 | case cris_xor_op: |
| 3523 | xor_op (inst, inst_env); |
| 3524 | break; |
| 3525 | } |
| 3526 | } |
| 3527 | |
| 3528 | /* This wrapper is to avoid cris_get_assembler being called before |
| 3529 | exec_bfd has been set. */ |
| 3530 | |
| 3531 | static int |
| 3532 | cris_delayed_get_disassembler (bfd_vma addr, disassemble_info *info) |
| 3533 | { |
| 3534 | tm_print_insn = cris_get_disassembler (exec_bfd); |
| 3535 | return (*tm_print_insn) (addr, info); |
| 3536 | } |
| 3537 | |
| 3538 | void |
| 3539 | _initialize_cris_tdep (void) |
| 3540 | { |
| 3541 | struct cmd_list_element *c; |
| 3542 | |
| 3543 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); |
| 3544 | |
| 3545 | /* Used in disassembly. */ |
| 3546 | tm_print_insn = cris_delayed_get_disassembler; |
| 3547 | |
| 3548 | /* CRIS-specific user-commands. */ |
| 3549 | c = add_set_cmd ("cris-version", class_support, var_integer, |
| 3550 | (char *) &usr_cmd_cris_version, |
| 3551 | "Set the current CRIS version.", &setlist); |
| 3552 | c->function.sfunc = cris_version_update; |
| 3553 | add_show_from_set (c, &showlist); |
| 3554 | |
| 3555 | c = add_set_enum_cmd ("cris-mode", class_support, cris_mode_enums, |
| 3556 | &usr_cmd_cris_mode, |
| 3557 | "Set the current CRIS mode.", &setlist); |
| 3558 | c->function.sfunc = cris_mode_update; |
| 3559 | add_show_from_set (c, &showlist); |
| 3560 | |
| 3561 | c = add_set_enum_cmd ("cris-abi", class_support, cris_abi_enums, |
| 3562 | &usr_cmd_cris_abi, |
| 3563 | "Set the current CRIS ABI version.", &setlist); |
| 3564 | c->function.sfunc = cris_abi_update; |
| 3565 | add_show_from_set (c, &showlist); |
| 3566 | } |
| 3567 | |
| 3568 | /* Prints out all target specific values. */ |
| 3569 | |
| 3570 | static void |
| 3571 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
| 3572 | { |
| 3573 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
| 3574 | if (tdep != NULL) |
| 3575 | { |
| 3576 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", |
| 3577 | tdep->cris_version); |
| 3578 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
| 3579 | tdep->cris_mode); |
| 3580 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_abi = %s\n", |
| 3581 | tdep->cris_abi); |
| 3582 | |
| 3583 | } |
| 3584 | } |
| 3585 | |
| 3586 | static void |
| 3587 | cris_version_update (char *ignore_args, int from_tty, |
| 3588 | struct cmd_list_element *c) |
| 3589 | { |
| 3590 | struct gdbarch_info info; |
| 3591 | |
| 3592 | /* From here on, trust the user's CRIS version setting. */ |
| 3593 | if (c->type == set_cmd) |
| 3594 | { |
| 3595 | usr_cmd_cris_version_valid = 1; |
| 3596 | |
| 3597 | /* Update the current architecture, if needed. */ |
| 3598 | memset (&info, 0, sizeof info); |
| 3599 | if (!gdbarch_update_p (info)) |
| 3600 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); |
| 3601 | } |
| 3602 | } |
| 3603 | |
| 3604 | static void |
| 3605 | cris_mode_update (char *ignore_args, int from_tty, |
| 3606 | struct cmd_list_element *c) |
| 3607 | { |
| 3608 | struct gdbarch_info info; |
| 3609 | |
| 3610 | /* From here on, trust the user's CRIS mode setting. */ |
| 3611 | if (c->type == set_cmd) |
| 3612 | { |
| 3613 | usr_cmd_cris_mode_valid = 1; |
| 3614 | |
| 3615 | /* Update the current architecture, if needed. */ |
| 3616 | memset (&info, 0, sizeof info); |
| 3617 | if (!gdbarch_update_p (info)) |
| 3618 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); |
| 3619 | } |
| 3620 | } |
| 3621 | |
| 3622 | static void |
| 3623 | cris_abi_update (char *ignore_args, int from_tty, |
| 3624 | struct cmd_list_element *c) |
| 3625 | { |
| 3626 | struct gdbarch_info info; |
| 3627 | |
| 3628 | /* From here on, trust the user's CRIS ABI setting. */ |
| 3629 | if (c->type == set_cmd) |
| 3630 | { |
| 3631 | usr_cmd_cris_abi_valid = 1; |
| 3632 | |
| 3633 | /* Update the current architecture, if needed. */ |
| 3634 | memset (&info, 0, sizeof info); |
| 3635 | if (!gdbarch_update_p (info)) |
| 3636 | internal_error (__FILE__, __LINE__, "cris_gdbarch_update: failed to update architecture."); |
| 3637 | } |
| 3638 | } |
| 3639 | |
| 3640 | /* Copied from pa64solib.c, with a couple of minor changes. */ |
| 3641 | |
| 3642 | static CORE_ADDR |
| 3643 | bfd_lookup_symbol (bfd *abfd, const char *symname) |
| 3644 | { |
| 3645 | unsigned int storage_needed; |
| 3646 | asymbol *sym; |
| 3647 | asymbol **symbol_table; |
| 3648 | unsigned int number_of_symbols; |
| 3649 | unsigned int i; |
| 3650 | struct cleanup *back_to; |
| 3651 | CORE_ADDR symaddr = 0; |
| 3652 | |
| 3653 | storage_needed = bfd_get_symtab_upper_bound (abfd); |
| 3654 | |
| 3655 | if (storage_needed > 0) |
| 3656 | { |
| 3657 | symbol_table = (asymbol **) xmalloc (storage_needed); |
| 3658 | back_to = make_cleanup (free, (PTR) symbol_table); |
| 3659 | number_of_symbols = bfd_canonicalize_symtab (abfd, symbol_table); |
| 3660 | |
| 3661 | for (i = 0; i < number_of_symbols; i++) |
| 3662 | { |
| 3663 | sym = *symbol_table++; |
| 3664 | if (!strcmp (sym->name, symname)) |
| 3665 | { |
| 3666 | /* Bfd symbols are section relative. */ |
| 3667 | symaddr = sym->value + sym->section->vma; |
| 3668 | break; |
| 3669 | } |
| 3670 | } |
| 3671 | do_cleanups (back_to); |
| 3672 | } |
| 3673 | return (symaddr); |
| 3674 | } |
| 3675 | |
| 3676 | static struct gdbarch * |
| 3677 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 3678 | { |
| 3679 | struct gdbarch *gdbarch; |
| 3680 | struct gdbarch_tdep *tdep; |
| 3681 | int cris_version; |
| 3682 | const char *cris_mode; |
| 3683 | const char *cris_abi; |
| 3684 | CORE_ADDR cris_abi_sym = 0; |
| 3685 | int register_bytes; |
| 3686 | |
| 3687 | if (usr_cmd_cris_version_valid) |
| 3688 | { |
| 3689 | /* Trust the user's CRIS version setting. */ |
| 3690 | cris_version = usr_cmd_cris_version; |
| 3691 | } |
| 3692 | else |
| 3693 | { |
| 3694 | /* Assume it's CRIS version 10. */ |
| 3695 | cris_version = 10; |
| 3696 | } |
| 3697 | |
| 3698 | if (usr_cmd_cris_mode_valid) |
| 3699 | { |
| 3700 | /* Trust the user's CRIS mode setting. */ |
| 3701 | cris_mode = usr_cmd_cris_mode; |
| 3702 | } |
| 3703 | else if (cris_version == 10) |
| 3704 | { |
| 3705 | /* Assume CRIS version 10 is in user mode. */ |
| 3706 | cris_mode = CRIS_MODE_USER; |
| 3707 | } |
| 3708 | else |
| 3709 | { |
| 3710 | /* Strictly speaking, older CRIS version don't have a supervisor mode, |
| 3711 | but we regard its only mode as supervisor mode. */ |
| 3712 | cris_mode = CRIS_MODE_SUPERVISOR; |
| 3713 | } |
| 3714 | |
| 3715 | if (usr_cmd_cris_abi_valid) |
| 3716 | { |
| 3717 | /* Trust the user's ABI setting. */ |
| 3718 | cris_abi = usr_cmd_cris_abi; |
| 3719 | } |
| 3720 | else if (info.abfd) |
| 3721 | { |
| 3722 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 3723 | { |
| 3724 | /* An elf target uses the new ABI. */ |
| 3725 | cris_abi = CRIS_ABI_V2; |
| 3726 | } |
| 3727 | else if (bfd_get_flavour (info.abfd) == bfd_target_aout_flavour) |
| 3728 | { |
| 3729 | /* An a.out target may use either ABI. Look for hints in the |
| 3730 | symbol table. */ |
| 3731 | cris_abi_sym = bfd_lookup_symbol (info.abfd, CRIS_ABI_SYMBOL); |
| 3732 | cris_abi = cris_abi_sym ? CRIS_ABI_V2 : CRIS_ABI_ORIGINAL; |
| 3733 | } |
| 3734 | else |
| 3735 | { |
| 3736 | /* Unknown bfd flavour. Assume it's the new ABI. */ |
| 3737 | cris_abi = CRIS_ABI_V2; |
| 3738 | } |
| 3739 | } |
| 3740 | else if (gdbarch_tdep (current_gdbarch)) |
| 3741 | { |
| 3742 | /* No bfd available. Stick with whatever ABI we're currently using. |
| 3743 | (This is to avoid changing the ABI when the user updates the |
| 3744 | architecture with the 'set cris-version' command.) */ |
| 3745 | cris_abi = gdbarch_tdep (current_gdbarch)->cris_abi; |
| 3746 | } |
| 3747 | else |
| 3748 | { |
| 3749 | /* No bfd, and no current architecture available. Assume it's the |
| 3750 | new ABI. */ |
| 3751 | cris_abi = CRIS_ABI_V2; |
| 3752 | } |
| 3753 | |
| 3754 | /* Make the current settings visible to the user. */ |
| 3755 | usr_cmd_cris_version = cris_version; |
| 3756 | usr_cmd_cris_mode = cris_mode; |
| 3757 | usr_cmd_cris_abi = cris_abi; |
| 3758 | |
| 3759 | /* Find a candidate among the list of pre-declared architectures. Both |
| 3760 | CRIS version and ABI must match. */ |
| 3761 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 3762 | arches != NULL; |
| 3763 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 3764 | { |
| 3765 | if ((gdbarch_tdep (arches->gdbarch)->cris_version == cris_version) |
| 3766 | && (gdbarch_tdep (arches->gdbarch)->cris_mode == cris_mode) |
| 3767 | && (gdbarch_tdep (arches->gdbarch)->cris_abi == cris_abi)) |
| 3768 | return arches->gdbarch; |
| 3769 | } |
| 3770 | |
| 3771 | /* No matching architecture was found. Create a new one. */ |
| 3772 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
| 3773 | gdbarch = gdbarch_alloc (&info, tdep); |
| 3774 | |
| 3775 | tdep->cris_version = cris_version; |
| 3776 | tdep->cris_mode = cris_mode; |
| 3777 | tdep->cris_abi = cris_abi; |
| 3778 | |
| 3779 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ |
| 3780 | switch (info.byte_order) |
| 3781 | { |
| 3782 | case LITTLE_ENDIAN: |
| 3783 | /* Ok. */ |
| 3784 | break; |
| 3785 | |
| 3786 | case BIG_ENDIAN: |
| 3787 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: big endian byte order in info"); |
| 3788 | break; |
| 3789 | |
| 3790 | default: |
| 3791 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown byte order in info"); |
| 3792 | } |
| 3793 | |
| 3794 | /* Initialize the ABI dependent things. */ |
| 3795 | if (tdep->cris_abi == CRIS_ABI_ORIGINAL) |
| 3796 | { |
| 3797 | set_gdbarch_double_bit (gdbarch, 32); |
| 3798 | set_gdbarch_push_arguments (gdbarch, cris_abi_original_push_arguments); |
| 3799 | set_gdbarch_store_return_value (gdbarch, |
| 3800 | cris_abi_original_store_return_value); |
| 3801 | set_gdbarch_extract_return_value |
| 3802 | (gdbarch, cris_abi_original_extract_return_value); |
| 3803 | set_gdbarch_reg_struct_has_addr |
| 3804 | (gdbarch, cris_abi_original_reg_struct_has_addr); |
| 3805 | } |
| 3806 | else if (tdep->cris_abi == CRIS_ABI_V2) |
| 3807 | { |
| 3808 | set_gdbarch_double_bit (gdbarch, 64); |
| 3809 | set_gdbarch_push_arguments (gdbarch, cris_abi_v2_push_arguments); |
| 3810 | set_gdbarch_store_return_value (gdbarch, cris_abi_v2_store_return_value); |
| 3811 | set_gdbarch_extract_return_value (gdbarch, |
| 3812 | cris_abi_v2_extract_return_value); |
| 3813 | set_gdbarch_reg_struct_has_addr (gdbarch, |
| 3814 | cris_abi_v2_reg_struct_has_addr); |
| 3815 | } |
| 3816 | else |
| 3817 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS ABI"); |
| 3818 | |
| 3819 | /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT, |
| 3820 | which means we have to set this explicitly. */ |
| 3821 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 3822 | |
| 3823 | /* Floating point is IEEE compatible. */ |
| 3824 | set_gdbarch_ieee_float (gdbarch, 1); |
| 3825 | |
| 3826 | /* There are 32 registers (some of which may not be implemented). */ |
| 3827 | set_gdbarch_num_regs (gdbarch, 32); |
| 3828 | set_gdbarch_sp_regnum (gdbarch, 14); |
| 3829 | set_gdbarch_fp_regnum (gdbarch, 8); |
| 3830 | set_gdbarch_pc_regnum (gdbarch, 15); |
| 3831 | |
| 3832 | set_gdbarch_register_name (gdbarch, cris_register_name); |
| 3833 | |
| 3834 | /* Length of ordinary registers used in push_word and a few other places. |
| 3835 | REGISTER_RAW_SIZE is the real way to know how big a register is. */ |
| 3836 | set_gdbarch_register_size (gdbarch, 4); |
| 3837 | |
| 3838 | /* NEW */ |
| 3839 | set_gdbarch_register_bytes_ok (gdbarch, cris_register_bytes_ok); |
| 3840 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); |
| 3841 | |
| 3842 | |
| 3843 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); |
| 3844 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); |
| 3845 | |
| 3846 | |
| 3847 | /* The total amount of space needed to store (in an array called registers) |
| 3848 | GDB's copy of the machine's register state. Note: We can not use |
| 3849 | cris_register_size at this point, since it relies on current_gdbarch |
| 3850 | being set. */ |
| 3851 | switch (tdep->cris_version) |
| 3852 | { |
| 3853 | case 0: |
| 3854 | case 1: |
| 3855 | case 2: |
| 3856 | case 3: |
| 3857 | /* Support for these may be added later. */ |
| 3858 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unsupported CRIS version"); |
| 3859 | break; |
| 3860 | |
| 3861 | case 8: |
| 3862 | case 9: |
| 3863 | /* CRIS v8 and v9, a.k.a. ETRAX 100. General registers R0 - R15 |
| 3864 | (32 bits), special registers P0 - P1 (8 bits), P4 - P5 (16 bits), |
| 3865 | and P8 - P14 (32 bits). */ |
| 3866 | register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (7 * 4); |
| 3867 | break; |
| 3868 | |
| 3869 | case 10: |
| 3870 | case 11: |
| 3871 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, |
| 3872 | P7 (32 bits), and P15 (32 bits) have been implemented. */ |
| 3873 | register_bytes = (16 * 4) + (2 * 1) + (2 * 2) + (9 * 4); |
| 3874 | break; |
| 3875 | |
| 3876 | default: |
| 3877 | internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS version"); |
| 3878 | } |
| 3879 | |
| 3880 | set_gdbarch_register_bytes (gdbarch, register_bytes); |
| 3881 | |
| 3882 | /* Returns the register offset for the first byte of register regno's space |
| 3883 | in the saved register state. */ |
| 3884 | set_gdbarch_register_byte (gdbarch, cris_register_offset); |
| 3885 | |
| 3886 | /* The length of the registers in the actual machine representation. */ |
| 3887 | set_gdbarch_register_raw_size (gdbarch, cris_register_size); |
| 3888 | |
| 3889 | /* The largest value REGISTER_RAW_SIZE can have. */ |
| 3890 | set_gdbarch_max_register_raw_size (gdbarch, 32); |
| 3891 | |
| 3892 | /* The length of the registers in the program's representation. */ |
| 3893 | set_gdbarch_register_virtual_size (gdbarch, cris_register_size); |
| 3894 | |
| 3895 | /* The largest value REGISTER_VIRTUAL_SIZE can have. */ |
| 3896 | set_gdbarch_max_register_virtual_size (gdbarch, 32); |
| 3897 | |
| 3898 | set_gdbarch_register_virtual_type (gdbarch, cris_register_virtual_type); |
| 3899 | |
| 3900 | /* Use generic dummy frames. */ |
| 3901 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); |
| 3902 | |
| 3903 | /* Where to execute the call in the memory segments. */ |
| 3904 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); |
| 3905 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
| 3906 | |
| 3907 | /* Start execution at the beginning of dummy. */ |
| 3908 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); |
| 3909 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); |
| 3910 | |
| 3911 | /* Set to 1 since call_dummy_breakpoint_offset was defined. */ |
| 3912 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); |
| 3913 | |
| 3914 | /* Read all about dummy frames in blockframe.c. */ |
| 3915 | set_gdbarch_call_dummy_length (gdbarch, 0); |
| 3916 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); |
| 3917 | |
| 3918 | /* Defined to 1 to indicate that the target supports inferior function |
| 3919 | calls. */ |
| 3920 | set_gdbarch_call_dummy_p (gdbarch, 1); |
| 3921 | set_gdbarch_call_dummy_words (gdbarch, 0); |
| 3922 | set_gdbarch_sizeof_call_dummy_words (gdbarch, 0); |
| 3923 | |
| 3924 | /* No stack adjustment needed when peforming an inferior function call. */ |
| 3925 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); |
| 3926 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); |
| 3927 | |
| 3928 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); |
| 3929 | |
| 3930 | /* No register requires conversion from raw format to virtual format. */ |
| 3931 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); |
| 3932 | |
| 3933 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); |
| 3934 | set_gdbarch_push_return_address (gdbarch, cris_push_return_address); |
| 3935 | set_gdbarch_pop_frame (gdbarch, cris_pop_frame); |
| 3936 | |
| 3937 | set_gdbarch_store_struct_return (gdbarch, cris_store_struct_return); |
| 3938 | set_gdbarch_extract_struct_value_address (gdbarch, |
| 3939 | cris_extract_struct_value_address); |
| 3940 | set_gdbarch_use_struct_convention (gdbarch, cris_use_struct_convention); |
| 3941 | |
| 3942 | set_gdbarch_frame_init_saved_regs (gdbarch, cris_frame_init_saved_regs); |
| 3943 | set_gdbarch_init_extra_frame_info (gdbarch, cris_init_extra_frame_info); |
| 3944 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
| 3945 | set_gdbarch_prologue_frameless_p (gdbarch, generic_prologue_frameless_p); |
| 3946 | |
| 3947 | /* The stack grows downward. */ |
| 3948 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 3949 | |
| 3950 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); |
| 3951 | |
| 3952 | /* The PC must not be decremented after a breakpoint. (The breakpoint |
| 3953 | handler takes care of that.) */ |
| 3954 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
| 3955 | |
| 3956 | /* Offset from address of function to start of its code. */ |
| 3957 | set_gdbarch_function_start_offset (gdbarch, 0); |
| 3958 | |
| 3959 | /* The number of bytes at the start of arglist that are not really args, |
| 3960 | 0 in the CRIS ABI. */ |
| 3961 | set_gdbarch_frame_args_skip (gdbarch, 0); |
| 3962 | set_gdbarch_frameless_function_invocation |
| 3963 | (gdbarch, cris_frameless_function_invocation); |
| 3964 | set_gdbarch_frame_chain (gdbarch, cris_frame_chain); |
| 3965 | set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid); |
| 3966 | |
| 3967 | set_gdbarch_frame_saved_pc (gdbarch, cris_frame_saved_pc); |
| 3968 | set_gdbarch_frame_args_address (gdbarch, cris_frame_args_address); |
| 3969 | set_gdbarch_frame_locals_address (gdbarch, cris_frame_locals_address); |
| 3970 | set_gdbarch_saved_pc_after_call (gdbarch, cris_saved_pc_after_call); |
| 3971 | |
| 3972 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); |
| 3973 | |
| 3974 | /* No extra stack alignment needed. Set to 1 by default. */ |
| 3975 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
| 3976 | |
| 3977 | /* Helpful for backtracing and returning in a call dummy. */ |
| 3978 | set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
| 3979 | |
| 3980 | return gdbarch; |
| 3981 | } |