| 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, |
| 4 | 2011 Free Software Foundation, Inc. |
| 5 | |
| 6 | Contributed by Axis Communications AB. |
| 7 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. |
| 8 | |
| 9 | This file is part of GDB. |
| 10 | |
| 11 | This program is free software; you can redistribute it and/or modify |
| 12 | it under the terms of the GNU General Public License as published by |
| 13 | the Free Software Foundation; either version 3 of the License, or |
| 14 | (at your option) any later version. |
| 15 | |
| 16 | This program is distributed in the hope that it will be useful, |
| 17 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | GNU General Public License for more details. |
| 20 | |
| 21 | You should have received a copy of the GNU General Public License |
| 22 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "frame.h" |
| 26 | #include "frame-unwind.h" |
| 27 | #include "frame-base.h" |
| 28 | #include "trad-frame.h" |
| 29 | #include "dwarf2-frame.h" |
| 30 | #include "symtab.h" |
| 31 | #include "inferior.h" |
| 32 | #include "gdbtypes.h" |
| 33 | #include "gdbcore.h" |
| 34 | #include "gdbcmd.h" |
| 35 | #include "target.h" |
| 36 | #include "value.h" |
| 37 | #include "opcode/cris.h" |
| 38 | #include "arch-utils.h" |
| 39 | #include "regcache.h" |
| 40 | #include "gdb_assert.h" |
| 41 | |
| 42 | #include "objfiles.h" |
| 43 | |
| 44 | #include "solib.h" /* Support for shared libraries. */ |
| 45 | #include "solib-svr4.h" |
| 46 | #include "gdb_string.h" |
| 47 | #include "dis-asm.h" |
| 48 | |
| 49 | enum cris_num_regs |
| 50 | { |
| 51 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ |
| 52 | NUM_FREGS = 0, |
| 53 | |
| 54 | /* There are 16 general registers. */ |
| 55 | NUM_GENREGS = 16, |
| 56 | |
| 57 | /* There are 16 special registers. */ |
| 58 | NUM_SPECREGS = 16, |
| 59 | |
| 60 | /* CRISv32 has a pseudo PC register, not noted here. */ |
| 61 | |
| 62 | /* CRISv32 has 16 support registers. */ |
| 63 | NUM_SUPPREGS = 16 |
| 64 | }; |
| 65 | |
| 66 | /* Register numbers of various important registers. |
| 67 | CRIS_FP_REGNUM Contains address of executing stack frame. |
| 68 | STR_REGNUM Contains the address of structure return values. |
| 69 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits |
| 70 | ARG1_REGNUM Contains the first parameter to a function. |
| 71 | ARG2_REGNUM Contains the second parameter to a function. |
| 72 | ARG3_REGNUM Contains the third parameter to a function. |
| 73 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. |
| 74 | gdbarch_sp_regnum Contains address of top of stack. |
| 75 | gdbarch_pc_regnum Contains address of next instruction. |
| 76 | SRP_REGNUM Subroutine return pointer register. |
| 77 | BRP_REGNUM Breakpoint return pointer register. */ |
| 78 | |
| 79 | enum cris_regnums |
| 80 | { |
| 81 | /* Enums with respect to the general registers, valid for all |
| 82 | CRIS versions. The frame pointer is always in R8. */ |
| 83 | CRIS_FP_REGNUM = 8, |
| 84 | /* ABI related registers. */ |
| 85 | STR_REGNUM = 9, |
| 86 | RET_REGNUM = 10, |
| 87 | ARG1_REGNUM = 10, |
| 88 | ARG2_REGNUM = 11, |
| 89 | ARG3_REGNUM = 12, |
| 90 | ARG4_REGNUM = 13, |
| 91 | |
| 92 | /* Registers which happen to be common. */ |
| 93 | VR_REGNUM = 17, |
| 94 | MOF_REGNUM = 23, |
| 95 | SRP_REGNUM = 27, |
| 96 | |
| 97 | /* CRISv10 et al. specific registers. */ |
| 98 | P0_REGNUM = 16, |
| 99 | P4_REGNUM = 20, |
| 100 | CCR_REGNUM = 21, |
| 101 | P8_REGNUM = 24, |
| 102 | IBR_REGNUM = 25, |
| 103 | IRP_REGNUM = 26, |
| 104 | BAR_REGNUM = 28, |
| 105 | DCCR_REGNUM = 29, |
| 106 | BRP_REGNUM = 30, |
| 107 | USP_REGNUM = 31, |
| 108 | |
| 109 | /* CRISv32 specific registers. */ |
| 110 | ACR_REGNUM = 15, |
| 111 | BZ_REGNUM = 16, |
| 112 | PID_REGNUM = 18, |
| 113 | SRS_REGNUM = 19, |
| 114 | WZ_REGNUM = 20, |
| 115 | EXS_REGNUM = 21, |
| 116 | EDA_REGNUM = 22, |
| 117 | DZ_REGNUM = 24, |
| 118 | EBP_REGNUM = 25, |
| 119 | ERP_REGNUM = 26, |
| 120 | NRP_REGNUM = 28, |
| 121 | CCS_REGNUM = 29, |
| 122 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ |
| 123 | SPC_REGNUM = 31, |
| 124 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ |
| 125 | |
| 126 | S0_REGNUM = 33, |
| 127 | S1_REGNUM = 34, |
| 128 | S2_REGNUM = 35, |
| 129 | S3_REGNUM = 36, |
| 130 | S4_REGNUM = 37, |
| 131 | S5_REGNUM = 38, |
| 132 | S6_REGNUM = 39, |
| 133 | S7_REGNUM = 40, |
| 134 | S8_REGNUM = 41, |
| 135 | S9_REGNUM = 42, |
| 136 | S10_REGNUM = 43, |
| 137 | S11_REGNUM = 44, |
| 138 | S12_REGNUM = 45, |
| 139 | S13_REGNUM = 46, |
| 140 | S14_REGNUM = 47, |
| 141 | S15_REGNUM = 48, |
| 142 | }; |
| 143 | |
| 144 | extern const struct cris_spec_reg cris_spec_regs[]; |
| 145 | |
| 146 | /* CRIS version, set via the user command 'set cris-version'. Affects |
| 147 | register names and sizes. */ |
| 148 | static int usr_cmd_cris_version; |
| 149 | |
| 150 | /* Indicates whether to trust the above variable. */ |
| 151 | static int usr_cmd_cris_version_valid = 0; |
| 152 | |
| 153 | static const char cris_mode_normal[] = "normal"; |
| 154 | static const char cris_mode_guru[] = "guru"; |
| 155 | static const char *cris_modes[] = { |
| 156 | cris_mode_normal, |
| 157 | cris_mode_guru, |
| 158 | 0 |
| 159 | }; |
| 160 | |
| 161 | /* CRIS mode, set via the user command 'set cris-mode'. Affects |
| 162 | type of break instruction among other things. */ |
| 163 | static const char *usr_cmd_cris_mode = cris_mode_normal; |
| 164 | |
| 165 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
| 166 | static int usr_cmd_cris_dwarf2_cfi = 1; |
| 167 | |
| 168 | /* CRIS architecture specific information. */ |
| 169 | struct gdbarch_tdep |
| 170 | { |
| 171 | int cris_version; |
| 172 | const char *cris_mode; |
| 173 | int cris_dwarf2_cfi; |
| 174 | }; |
| 175 | |
| 176 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
| 177 | |
| 178 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ |
| 179 | #define SIGTRAMP_OFFSET0 0 |
| 180 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ |
| 181 | #define SIGTRAMP_OFFSET1 4 |
| 182 | |
| 183 | static const unsigned short sigtramp_code[] = |
| 184 | { |
| 185 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ |
| 186 | SIGTRAMP_INSN1 /* break 13 */ |
| 187 | }; |
| 188 | |
| 189 | #define SIGTRAMP_LEN (sizeof sigtramp_code) |
| 190 | |
| 191 | /* Note: same length as normal sigtramp code. */ |
| 192 | |
| 193 | static const unsigned short rt_sigtramp_code[] = |
| 194 | { |
| 195 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
| 196 | SIGTRAMP_INSN1 /* break 13 */ |
| 197 | }; |
| 198 | |
| 199 | /* If PC is in a sigtramp routine, return the address of the start of |
| 200 | the routine. Otherwise, return 0. */ |
| 201 | |
| 202 | static CORE_ADDR |
| 203 | cris_sigtramp_start (struct frame_info *this_frame) |
| 204 | { |
| 205 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 206 | gdb_byte buf[SIGTRAMP_LEN]; |
| 207 | |
| 208 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
| 209 | return 0; |
| 210 | |
| 211 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
| 212 | { |
| 213 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
| 214 | return 0; |
| 215 | |
| 216 | pc -= SIGTRAMP_OFFSET1; |
| 217 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
| 218 | return 0; |
| 219 | } |
| 220 | |
| 221 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) |
| 222 | return 0; |
| 223 | |
| 224 | return pc; |
| 225 | } |
| 226 | |
| 227 | /* If PC is in a RT sigtramp routine, return the address of the start of |
| 228 | the routine. Otherwise, return 0. */ |
| 229 | |
| 230 | static CORE_ADDR |
| 231 | cris_rt_sigtramp_start (struct frame_info *this_frame) |
| 232 | { |
| 233 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 234 | gdb_byte buf[SIGTRAMP_LEN]; |
| 235 | |
| 236 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
| 237 | return 0; |
| 238 | |
| 239 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
| 240 | { |
| 241 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
| 242 | return 0; |
| 243 | |
| 244 | pc -= SIGTRAMP_OFFSET1; |
| 245 | if (!safe_frame_unwind_memory (this_frame, pc, buf, SIGTRAMP_LEN)) |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) |
| 250 | return 0; |
| 251 | |
| 252 | return pc; |
| 253 | } |
| 254 | |
| 255 | /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine, |
| 256 | return the address of the associated sigcontext structure. */ |
| 257 | |
| 258 | static CORE_ADDR |
| 259 | cris_sigcontext_addr (struct frame_info *this_frame) |
| 260 | { |
| 261 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 262 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 263 | CORE_ADDR pc; |
| 264 | CORE_ADDR sp; |
| 265 | char buf[4]; |
| 266 | |
| 267 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
| 268 | sp = extract_unsigned_integer (buf, 4, byte_order); |
| 269 | |
| 270 | /* Look for normal sigtramp frame first. */ |
| 271 | pc = cris_sigtramp_start (this_frame); |
| 272 | if (pc) |
| 273 | { |
| 274 | /* struct signal_frame (arch/cris/kernel/signal.c) contains |
| 275 | struct sigcontext as its first member, meaning the SP points to |
| 276 | it already. */ |
| 277 | return sp; |
| 278 | } |
| 279 | |
| 280 | pc = cris_rt_sigtramp_start (this_frame); |
| 281 | if (pc) |
| 282 | { |
| 283 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains |
| 284 | a struct ucontext, which in turn contains a struct sigcontext. |
| 285 | Magic digging: |
| 286 | 4 + 4 + 128 to struct ucontext, then |
| 287 | 4 + 4 + 12 to struct sigcontext. */ |
| 288 | return (sp + 156); |
| 289 | } |
| 290 | |
| 291 | error (_("Couldn't recognize signal trampoline.")); |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | struct cris_unwind_cache |
| 296 | { |
| 297 | /* The previous frame's inner most stack address. Used as this |
| 298 | frame ID's stack_addr. */ |
| 299 | CORE_ADDR prev_sp; |
| 300 | /* The frame's base, optionally used by the high-level debug info. */ |
| 301 | CORE_ADDR base; |
| 302 | int size; |
| 303 | /* How far the SP and r8 (FP) have been offset from the start of |
| 304 | the stack frame (as defined by the previous frame's stack |
| 305 | pointer). */ |
| 306 | LONGEST sp_offset; |
| 307 | LONGEST r8_offset; |
| 308 | int uses_frame; |
| 309 | |
| 310 | /* From old frame_extra_info struct. */ |
| 311 | CORE_ADDR return_pc; |
| 312 | int leaf_function; |
| 313 | |
| 314 | /* Table indicating the location of each and every register. */ |
| 315 | struct trad_frame_saved_reg *saved_regs; |
| 316 | }; |
| 317 | |
| 318 | static struct cris_unwind_cache * |
| 319 | cris_sigtramp_frame_unwind_cache (struct frame_info *this_frame, |
| 320 | void **this_cache) |
| 321 | { |
| 322 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 323 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 324 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 325 | struct cris_unwind_cache *info; |
| 326 | CORE_ADDR pc; |
| 327 | CORE_ADDR sp; |
| 328 | CORE_ADDR addr; |
| 329 | char buf[4]; |
| 330 | int i; |
| 331 | |
| 332 | if ((*this_cache)) |
| 333 | return (*this_cache); |
| 334 | |
| 335 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); |
| 336 | (*this_cache) = info; |
| 337 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 338 | |
| 339 | /* Zero all fields. */ |
| 340 | info->prev_sp = 0; |
| 341 | info->base = 0; |
| 342 | info->size = 0; |
| 343 | info->sp_offset = 0; |
| 344 | info->r8_offset = 0; |
| 345 | info->uses_frame = 0; |
| 346 | info->return_pc = 0; |
| 347 | info->leaf_function = 0; |
| 348 | |
| 349 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
| 350 | info->base = extract_unsigned_integer (buf, 4, byte_order); |
| 351 | |
| 352 | addr = cris_sigcontext_addr (this_frame); |
| 353 | |
| 354 | /* Layout of the sigcontext struct: |
| 355 | struct sigcontext { |
| 356 | struct pt_regs regs; |
| 357 | unsigned long oldmask; |
| 358 | unsigned long usp; |
| 359 | }; */ |
| 360 | |
| 361 | if (tdep->cris_version == 10) |
| 362 | { |
| 363 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in |
| 364 | struct pt_regs. */ |
| 365 | for (i = 0; i <= 13; i++) |
| 366 | info->saved_regs[i].addr = addr + ((15 - i) * 4); |
| 367 | |
| 368 | info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4); |
| 369 | info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4); |
| 370 | info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4); |
| 371 | /* Note: IRP is off by 2 at this point. There's no point in correcting |
| 372 | it though since that will mean that the backtrace will show a PC |
| 373 | different from what is shown when stopped. */ |
| 374 | info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4); |
| 375 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
| 376 | = info->saved_regs[IRP_REGNUM]; |
| 377 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr = addr + (24 * 4); |
| 378 | } |
| 379 | else |
| 380 | { |
| 381 | /* CRISv32. */ |
| 382 | /* R0 to R13 are stored in order at offset (1 * 4) in |
| 383 | struct pt_regs. */ |
| 384 | for (i = 0; i <= 13; i++) |
| 385 | info->saved_regs[i].addr = addr + ((i + 1) * 4); |
| 386 | |
| 387 | info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4); |
| 388 | info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4); |
| 389 | info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4); |
| 390 | info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4); |
| 391 | info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4); |
| 392 | info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4); |
| 393 | info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4); |
| 394 | info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4); |
| 395 | info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4); |
| 396 | |
| 397 | /* FIXME: If ERP is in a delay slot at this point then the PC will |
| 398 | be wrong at this point. This problem manifests itself in the |
| 399 | sigaltstack.exp test case, which occasionally generates FAILs when |
| 400 | the signal is received while in a delay slot. |
| 401 | |
| 402 | This could be solved by a couple of read_memory_unsigned_integer and a |
| 403 | trad_frame_set_value. */ |
| 404 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
| 405 | = info->saved_regs[ERP_REGNUM]; |
| 406 | |
| 407 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].addr |
| 408 | = addr + (25 * 4); |
| 409 | } |
| 410 | |
| 411 | return info; |
| 412 | } |
| 413 | |
| 414 | static void |
| 415 | cris_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 416 | struct frame_id *this_id) |
| 417 | { |
| 418 | struct cris_unwind_cache *cache = |
| 419 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
| 420 | (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame)); |
| 421 | } |
| 422 | |
| 423 | /* Forward declaration. */ |
| 424 | |
| 425 | static struct value *cris_frame_prev_register (struct frame_info *this_frame, |
| 426 | void **this_cache, int regnum); |
| 427 | static struct value * |
| 428 | cris_sigtramp_frame_prev_register (struct frame_info *this_frame, |
| 429 | void **this_cache, int regnum) |
| 430 | { |
| 431 | /* Make sure we've initialized the cache. */ |
| 432 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
| 433 | return cris_frame_prev_register (this_frame, this_cache, regnum); |
| 434 | } |
| 435 | |
| 436 | static int |
| 437 | cris_sigtramp_frame_sniffer (const struct frame_unwind *self, |
| 438 | struct frame_info *this_frame, |
| 439 | void **this_cache) |
| 440 | { |
| 441 | if (cris_sigtramp_start (this_frame) |
| 442 | || cris_rt_sigtramp_start (this_frame)) |
| 443 | return 1; |
| 444 | |
| 445 | return 0; |
| 446 | } |
| 447 | |
| 448 | static const struct frame_unwind cris_sigtramp_frame_unwind = |
| 449 | { |
| 450 | SIGTRAMP_FRAME, |
| 451 | default_frame_unwind_stop_reason, |
| 452 | cris_sigtramp_frame_this_id, |
| 453 | cris_sigtramp_frame_prev_register, |
| 454 | NULL, |
| 455 | cris_sigtramp_frame_sniffer |
| 456 | }; |
| 457 | |
| 458 | static int |
| 459 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, |
| 460 | struct frame_info *this_frame) |
| 461 | { |
| 462 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 463 | ULONGEST erp; |
| 464 | int ret = 0; |
| 465 | |
| 466 | if (tdep->cris_mode == cris_mode_guru) |
| 467 | erp = get_frame_register_unsigned (this_frame, NRP_REGNUM); |
| 468 | else |
| 469 | erp = get_frame_register_unsigned (this_frame, ERP_REGNUM); |
| 470 | |
| 471 | if (erp & 0x1) |
| 472 | { |
| 473 | /* In delay slot - check if there's a breakpoint at the preceding |
| 474 | instruction. */ |
| 475 | if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1)) |
| 476 | ret = 1; |
| 477 | } |
| 478 | return ret; |
| 479 | } |
| 480 | |
| 481 | /* Hardware watchpoint support. */ |
| 482 | |
| 483 | /* We support 6 hardware data watchpoints, but cannot trigger on execute |
| 484 | (any combination of read/write is fine). */ |
| 485 | |
| 486 | int |
| 487 | cris_can_use_hardware_watchpoint (int type, int count, int other) |
| 488 | { |
| 489 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
| 490 | |
| 491 | /* No bookkeeping is done here; it is handled by the remote debug agent. */ |
| 492 | |
| 493 | if (tdep->cris_version != 32) |
| 494 | return 0; |
| 495 | else |
| 496 | /* CRISv32: Six data watchpoints, one for instructions. */ |
| 497 | return (((type == bp_read_watchpoint || type == bp_access_watchpoint |
| 498 | || type == bp_hardware_watchpoint) && count <= 6) |
| 499 | || (type == bp_hardware_breakpoint && count <= 1)); |
| 500 | } |
| 501 | |
| 502 | /* The CRISv32 hardware data watchpoints work by specifying ranges, |
| 503 | which have no alignment or length restrictions. */ |
| 504 | |
| 505 | int |
| 506 | cris_region_ok_for_watchpoint (CORE_ADDR addr, int len) |
| 507 | { |
| 508 | return 1; |
| 509 | } |
| 510 | |
| 511 | /* If the inferior has some watchpoint that triggered, return the |
| 512 | address associated with that watchpoint. Otherwise, return |
| 513 | zero. */ |
| 514 | |
| 515 | CORE_ADDR |
| 516 | cris_stopped_data_address (void) |
| 517 | { |
| 518 | CORE_ADDR eda; |
| 519 | eda = get_frame_register_unsigned (get_current_frame (), EDA_REGNUM); |
| 520 | return eda; |
| 521 | } |
| 522 | |
| 523 | /* The instruction environment needed to find single-step breakpoints. */ |
| 524 | |
| 525 | typedef |
| 526 | struct instruction_environment |
| 527 | { |
| 528 | unsigned long reg[NUM_GENREGS]; |
| 529 | unsigned long preg[NUM_SPECREGS]; |
| 530 | unsigned long branch_break_address; |
| 531 | unsigned long delay_slot_pc; |
| 532 | unsigned long prefix_value; |
| 533 | int branch_found; |
| 534 | int prefix_found; |
| 535 | int invalid; |
| 536 | int slot_needed; |
| 537 | int delay_slot_pc_active; |
| 538 | int xflag_found; |
| 539 | int disable_interrupt; |
| 540 | int byte_order; |
| 541 | } inst_env_type; |
| 542 | |
| 543 | /* Machine-dependencies in CRIS for opcodes. */ |
| 544 | |
| 545 | /* Instruction sizes. */ |
| 546 | enum cris_instruction_sizes |
| 547 | { |
| 548 | INST_BYTE_SIZE = 0, |
| 549 | INST_WORD_SIZE = 1, |
| 550 | INST_DWORD_SIZE = 2 |
| 551 | }; |
| 552 | |
| 553 | /* Addressing modes. */ |
| 554 | enum cris_addressing_modes |
| 555 | { |
| 556 | REGISTER_MODE = 1, |
| 557 | INDIRECT_MODE = 2, |
| 558 | AUTOINC_MODE = 3 |
| 559 | }; |
| 560 | |
| 561 | /* Prefix addressing modes. */ |
| 562 | enum cris_prefix_addressing_modes |
| 563 | { |
| 564 | PREFIX_INDEX_MODE = 2, |
| 565 | PREFIX_ASSIGN_MODE = 3, |
| 566 | |
| 567 | /* Handle immediate byte offset addressing mode prefix format. */ |
| 568 | PREFIX_OFFSET_MODE = 2 |
| 569 | }; |
| 570 | |
| 571 | /* Masks for opcodes. */ |
| 572 | enum cris_opcode_masks |
| 573 | { |
| 574 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, |
| 575 | SIGNED_EXTEND_BIT_MASK = 0x2, |
| 576 | SIGNED_BYTE_MASK = 0x80, |
| 577 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, |
| 578 | SIGNED_WORD_MASK = 0x8000, |
| 579 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, |
| 580 | SIGNED_DWORD_MASK = 0x80000000, |
| 581 | SIGNED_QUICK_VALUE_MASK = 0x20, |
| 582 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 |
| 583 | }; |
| 584 | |
| 585 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: |
| 586 | Bit 15 - 12 Operand2 |
| 587 | 11 - 10 Mode |
| 588 | 9 - 6 Opcode |
| 589 | 5 - 4 Size |
| 590 | 3 - 0 Operand1 */ |
| 591 | |
| 592 | static int |
| 593 | cris_get_operand2 (unsigned short insn) |
| 594 | { |
| 595 | return ((insn & 0xF000) >> 12); |
| 596 | } |
| 597 | |
| 598 | static int |
| 599 | cris_get_mode (unsigned short insn) |
| 600 | { |
| 601 | return ((insn & 0x0C00) >> 10); |
| 602 | } |
| 603 | |
| 604 | static int |
| 605 | cris_get_opcode (unsigned short insn) |
| 606 | { |
| 607 | return ((insn & 0x03C0) >> 6); |
| 608 | } |
| 609 | |
| 610 | static int |
| 611 | cris_get_size (unsigned short insn) |
| 612 | { |
| 613 | return ((insn & 0x0030) >> 4); |
| 614 | } |
| 615 | |
| 616 | static int |
| 617 | cris_get_operand1 (unsigned short insn) |
| 618 | { |
| 619 | return (insn & 0x000F); |
| 620 | } |
| 621 | |
| 622 | /* Additional functions in order to handle opcodes. */ |
| 623 | |
| 624 | static int |
| 625 | cris_get_quick_value (unsigned short insn) |
| 626 | { |
| 627 | return (insn & 0x003F); |
| 628 | } |
| 629 | |
| 630 | static int |
| 631 | cris_get_bdap_quick_offset (unsigned short insn) |
| 632 | { |
| 633 | return (insn & 0x00FF); |
| 634 | } |
| 635 | |
| 636 | static int |
| 637 | cris_get_branch_short_offset (unsigned short insn) |
| 638 | { |
| 639 | return (insn & 0x00FF); |
| 640 | } |
| 641 | |
| 642 | static int |
| 643 | cris_get_asr_shift_steps (unsigned long value) |
| 644 | { |
| 645 | return (value & 0x3F); |
| 646 | } |
| 647 | |
| 648 | static int |
| 649 | cris_get_clear_size (unsigned short insn) |
| 650 | { |
| 651 | return ((insn) & 0xC000); |
| 652 | } |
| 653 | |
| 654 | static int |
| 655 | cris_is_signed_extend_bit_on (unsigned short insn) |
| 656 | { |
| 657 | return (((insn) & 0x20) == 0x20); |
| 658 | } |
| 659 | |
| 660 | static int |
| 661 | cris_is_xflag_bit_on (unsigned short insn) |
| 662 | { |
| 663 | return (((insn) & 0x1000) == 0x1000); |
| 664 | } |
| 665 | |
| 666 | static void |
| 667 | cris_set_size_to_dword (unsigned short *insn) |
| 668 | { |
| 669 | *insn &= 0xFFCF; |
| 670 | *insn |= 0x20; |
| 671 | } |
| 672 | |
| 673 | static signed char |
| 674 | cris_get_signed_offset (unsigned short insn) |
| 675 | { |
| 676 | return ((signed char) (insn & 0x00FF)); |
| 677 | } |
| 678 | |
| 679 | /* Calls an op function given the op-type, working on the insn and the |
| 680 | inst_env. */ |
| 681 | static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short, |
| 682 | inst_env_type *); |
| 683 | |
| 684 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
| 685 | struct gdbarch_list *); |
| 686 | |
| 687 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
| 688 | |
| 689 | static void set_cris_version (char *ignore_args, int from_tty, |
| 690 | struct cmd_list_element *c); |
| 691 | |
| 692 | static void set_cris_mode (char *ignore_args, int from_tty, |
| 693 | struct cmd_list_element *c); |
| 694 | |
| 695 | static void set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
| 696 | struct cmd_list_element *c); |
| 697 | |
| 698 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
| 699 | struct frame_info *this_frame, |
| 700 | struct cris_unwind_cache *info); |
| 701 | |
| 702 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
| 703 | struct frame_info *this_frame, |
| 704 | struct cris_unwind_cache *info); |
| 705 | |
| 706 | static CORE_ADDR cris_unwind_pc (struct gdbarch *gdbarch, |
| 707 | struct frame_info *next_frame); |
| 708 | |
| 709 | static CORE_ADDR cris_unwind_sp (struct gdbarch *gdbarch, |
| 710 | struct frame_info *next_frame); |
| 711 | |
| 712 | /* When arguments must be pushed onto the stack, they go on in reverse |
| 713 | order. The below implements a FILO (stack) to do this. |
| 714 | Copied from d10v-tdep.c. */ |
| 715 | |
| 716 | struct stack_item |
| 717 | { |
| 718 | int len; |
| 719 | struct stack_item *prev; |
| 720 | void *data; |
| 721 | }; |
| 722 | |
| 723 | static struct stack_item * |
| 724 | push_stack_item (struct stack_item *prev, void *contents, int len) |
| 725 | { |
| 726 | struct stack_item *si; |
| 727 | si = xmalloc (sizeof (struct stack_item)); |
| 728 | si->data = xmalloc (len); |
| 729 | si->len = len; |
| 730 | si->prev = prev; |
| 731 | memcpy (si->data, contents, len); |
| 732 | return si; |
| 733 | } |
| 734 | |
| 735 | static struct stack_item * |
| 736 | pop_stack_item (struct stack_item *si) |
| 737 | { |
| 738 | struct stack_item *dead = si; |
| 739 | si = si->prev; |
| 740 | xfree (dead->data); |
| 741 | xfree (dead); |
| 742 | return si; |
| 743 | } |
| 744 | |
| 745 | /* Put here the code to store, into fi->saved_regs, the addresses of |
| 746 | the saved registers of frame described by FRAME_INFO. This |
| 747 | includes special registers such as pc and fp saved in special ways |
| 748 | in the stack frame. sp is even more special: the address we return |
| 749 | for it IS the sp for the next frame. */ |
| 750 | |
| 751 | static struct cris_unwind_cache * |
| 752 | cris_frame_unwind_cache (struct frame_info *this_frame, |
| 753 | void **this_prologue_cache) |
| 754 | { |
| 755 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 756 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 757 | CORE_ADDR pc; |
| 758 | struct cris_unwind_cache *info; |
| 759 | int i; |
| 760 | |
| 761 | if ((*this_prologue_cache)) |
| 762 | return (*this_prologue_cache); |
| 763 | |
| 764 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); |
| 765 | (*this_prologue_cache) = info; |
| 766 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 767 | |
| 768 | /* Zero all fields. */ |
| 769 | info->prev_sp = 0; |
| 770 | info->base = 0; |
| 771 | info->size = 0; |
| 772 | info->sp_offset = 0; |
| 773 | info->r8_offset = 0; |
| 774 | info->uses_frame = 0; |
| 775 | info->return_pc = 0; |
| 776 | info->leaf_function = 0; |
| 777 | |
| 778 | /* Prologue analysis does the rest... */ |
| 779 | if (tdep->cris_version == 32) |
| 780 | crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info); |
| 781 | else |
| 782 | cris_scan_prologue (get_frame_func (this_frame), this_frame, info); |
| 783 | |
| 784 | return info; |
| 785 | } |
| 786 | |
| 787 | /* Given a GDB frame, determine the address of the calling function's |
| 788 | frame. This will be used to create a new GDB frame struct. */ |
| 789 | |
| 790 | static void |
| 791 | cris_frame_this_id (struct frame_info *this_frame, |
| 792 | void **this_prologue_cache, |
| 793 | struct frame_id *this_id) |
| 794 | { |
| 795 | struct cris_unwind_cache *info |
| 796 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
| 797 | CORE_ADDR base; |
| 798 | CORE_ADDR func; |
| 799 | struct frame_id id; |
| 800 | |
| 801 | /* The FUNC is easy. */ |
| 802 | func = get_frame_func (this_frame); |
| 803 | |
| 804 | /* Hopefully the prologue analysis either correctly determined the |
| 805 | frame's base (which is the SP from the previous frame), or set |
| 806 | that base to "NULL". */ |
| 807 | base = info->prev_sp; |
| 808 | if (base == 0) |
| 809 | return; |
| 810 | |
| 811 | id = frame_id_build (base, func); |
| 812 | |
| 813 | (*this_id) = id; |
| 814 | } |
| 815 | |
| 816 | static struct value * |
| 817 | cris_frame_prev_register (struct frame_info *this_frame, |
| 818 | void **this_prologue_cache, int regnum) |
| 819 | { |
| 820 | struct cris_unwind_cache *info |
| 821 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
| 822 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 823 | } |
| 824 | |
| 825 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
| 826 | frame. The frame ID's base needs to match the TOS value saved by |
| 827 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ |
| 828 | |
| 829 | static struct frame_id |
| 830 | cris_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 831 | { |
| 832 | CORE_ADDR sp; |
| 833 | sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); |
| 834 | return frame_id_build (sp, get_frame_pc (this_frame)); |
| 835 | } |
| 836 | |
| 837 | static CORE_ADDR |
| 838 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 839 | { |
| 840 | /* Align to the size of an instruction (so that they can safely be |
| 841 | pushed onto the stack). */ |
| 842 | return sp & ~3; |
| 843 | } |
| 844 | |
| 845 | static CORE_ADDR |
| 846 | cris_push_dummy_code (struct gdbarch *gdbarch, |
| 847 | CORE_ADDR sp, CORE_ADDR funaddr, |
| 848 | struct value **args, int nargs, |
| 849 | struct type *value_type, |
| 850 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
| 851 | struct regcache *regcache) |
| 852 | { |
| 853 | /* Allocate space sufficient for a breakpoint. */ |
| 854 | sp = (sp - 4) & ~3; |
| 855 | /* Store the address of that breakpoint */ |
| 856 | *bp_addr = sp; |
| 857 | /* CRIS always starts the call at the callee's entry point. */ |
| 858 | *real_pc = funaddr; |
| 859 | return sp; |
| 860 | } |
| 861 | |
| 862 | static CORE_ADDR |
| 863 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 864 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 865 | int nargs, struct value **args, CORE_ADDR sp, |
| 866 | int struct_return, CORE_ADDR struct_addr) |
| 867 | { |
| 868 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 869 | int stack_alloc; |
| 870 | int stack_offset; |
| 871 | int argreg; |
| 872 | int argnum; |
| 873 | |
| 874 | CORE_ADDR regval; |
| 875 | |
| 876 | /* The function's arguments and memory allocated by gdb for the arguments to |
| 877 | point at reside in separate areas on the stack. |
| 878 | Both frame pointers grow toward higher addresses. */ |
| 879 | CORE_ADDR fp_arg; |
| 880 | CORE_ADDR fp_mem; |
| 881 | |
| 882 | struct stack_item *si = NULL; |
| 883 | |
| 884 | /* Push the return address. */ |
| 885 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
| 886 | |
| 887 | /* Are we returning a value using a structure return or a normal value |
| 888 | return? struct_addr is the address of the reserved space for the return |
| 889 | structure to be written on the stack. */ |
| 890 | if (struct_return) |
| 891 | { |
| 892 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); |
| 893 | } |
| 894 | |
| 895 | /* Now load as many as possible of the first arguments into registers, |
| 896 | and push the rest onto the stack. */ |
| 897 | argreg = ARG1_REGNUM; |
| 898 | stack_offset = 0; |
| 899 | |
| 900 | for (argnum = 0; argnum < nargs; argnum++) |
| 901 | { |
| 902 | int len; |
| 903 | char *val; |
| 904 | int reg_demand; |
| 905 | int i; |
| 906 | |
| 907 | len = TYPE_LENGTH (value_type (args[argnum])); |
| 908 | val = (char *) value_contents (args[argnum]); |
| 909 | |
| 910 | /* How may registers worth of storage do we need for this argument? */ |
| 911 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); |
| 912 | |
| 913 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) |
| 914 | { |
| 915 | /* Data passed by value. Fits in available register(s). */ |
| 916 | for (i = 0; i < reg_demand; i++) |
| 917 | { |
| 918 | regcache_cooked_write (regcache, argreg, val); |
| 919 | argreg++; |
| 920 | val += 4; |
| 921 | } |
| 922 | } |
| 923 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) |
| 924 | { |
| 925 | /* Data passed by value. Does not fit in available register(s). |
| 926 | Use the register(s) first, then the stack. */ |
| 927 | for (i = 0; i < reg_demand; i++) |
| 928 | { |
| 929 | if (argreg <= ARG4_REGNUM) |
| 930 | { |
| 931 | regcache_cooked_write (regcache, argreg, val); |
| 932 | argreg++; |
| 933 | val += 4; |
| 934 | } |
| 935 | else |
| 936 | { |
| 937 | /* Push item for later so that pushed arguments |
| 938 | come in the right order. */ |
| 939 | si = push_stack_item (si, val, 4); |
| 940 | val += 4; |
| 941 | } |
| 942 | } |
| 943 | } |
| 944 | else if (len > (2 * 4)) |
| 945 | { |
| 946 | /* Data passed by reference. Push copy of data onto stack |
| 947 | and pass pointer to this copy as argument. */ |
| 948 | sp = (sp - len) & ~3; |
| 949 | write_memory (sp, val, len); |
| 950 | |
| 951 | if (argreg <= ARG4_REGNUM) |
| 952 | { |
| 953 | regcache_cooked_write_unsigned (regcache, argreg, sp); |
| 954 | argreg++; |
| 955 | } |
| 956 | else |
| 957 | { |
| 958 | gdb_byte buf[4]; |
| 959 | store_unsigned_integer (buf, 4, byte_order, sp); |
| 960 | si = push_stack_item (si, buf, 4); |
| 961 | } |
| 962 | } |
| 963 | else |
| 964 | { |
| 965 | /* Data passed by value. No available registers. Put it on |
| 966 | the stack. */ |
| 967 | si = push_stack_item (si, val, len); |
| 968 | } |
| 969 | } |
| 970 | |
| 971 | while (si) |
| 972 | { |
| 973 | /* fp_arg must be word-aligned (i.e., don't += len) to match |
| 974 | the function prologue. */ |
| 975 | sp = (sp - si->len) & ~3; |
| 976 | write_memory (sp, si->data, si->len); |
| 977 | si = pop_stack_item (si); |
| 978 | } |
| 979 | |
| 980 | /* Finally, update the SP register. */ |
| 981 | regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp); |
| 982 | |
| 983 | return sp; |
| 984 | } |
| 985 | |
| 986 | static const struct frame_unwind cris_frame_unwind = |
| 987 | { |
| 988 | NORMAL_FRAME, |
| 989 | default_frame_unwind_stop_reason, |
| 990 | cris_frame_this_id, |
| 991 | cris_frame_prev_register, |
| 992 | NULL, |
| 993 | default_frame_sniffer |
| 994 | }; |
| 995 | |
| 996 | static CORE_ADDR |
| 997 | cris_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 998 | { |
| 999 | struct cris_unwind_cache *info |
| 1000 | = cris_frame_unwind_cache (this_frame, this_cache); |
| 1001 | return info->base; |
| 1002 | } |
| 1003 | |
| 1004 | static const struct frame_base cris_frame_base = |
| 1005 | { |
| 1006 | &cris_frame_unwind, |
| 1007 | cris_frame_base_address, |
| 1008 | cris_frame_base_address, |
| 1009 | cris_frame_base_address |
| 1010 | }; |
| 1011 | |
| 1012 | /* Frames information. The definition of the struct frame_info is |
| 1013 | |
| 1014 | CORE_ADDR frame |
| 1015 | CORE_ADDR pc |
| 1016 | enum frame_type type; |
| 1017 | CORE_ADDR return_pc |
| 1018 | int leaf_function |
| 1019 | |
| 1020 | If the compilation option -fno-omit-frame-pointer is present the |
| 1021 | variable frame will be set to the content of R8 which is the frame |
| 1022 | pointer register. |
| 1023 | |
| 1024 | The variable pc contains the address where execution is performed |
| 1025 | in the present frame. The innermost frame contains the current content |
| 1026 | of the register PC. All other frames contain the content of the |
| 1027 | register PC in the next frame. |
| 1028 | |
| 1029 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
| 1030 | (associated with a signal handler), dummy (associated with a dummy |
| 1031 | frame). |
| 1032 | |
| 1033 | The variable return_pc contains the address where execution should be |
| 1034 | resumed when the present frame has finished, the return address. |
| 1035 | |
| 1036 | The variable leaf_function is 1 if the return address is in the register |
| 1037 | SRP, and 0 if it is on the stack. |
| 1038 | |
| 1039 | Prologue instructions C-code. |
| 1040 | The prologue may consist of (-fno-omit-frame-pointer) |
| 1041 | 1) 2) |
| 1042 | push srp |
| 1043 | push r8 push r8 |
| 1044 | move.d sp,r8 move.d sp,r8 |
| 1045 | subq X,sp subq X,sp |
| 1046 | movem rY,[sp] movem rY,[sp] |
| 1047 | move.S rZ,[r8-U] move.S rZ,[r8-U] |
| 1048 | |
| 1049 | where 1 is a non-terminal function, and 2 is a leaf-function. |
| 1050 | |
| 1051 | Note that this assumption is extremely brittle, and will break at the |
| 1052 | slightest change in GCC's prologue. |
| 1053 | |
| 1054 | If local variables are declared or register contents are saved on stack |
| 1055 | the subq-instruction will be present with X as the number of bytes |
| 1056 | needed for storage. The reshuffle with respect to r8 may be performed |
| 1057 | with any size S (b, w, d) and any of the general registers Z={0..13}. |
| 1058 | The offset U should be representable by a signed 8-bit value in all cases. |
| 1059 | Thus, the prefix word is assumed to be immediate byte offset mode followed |
| 1060 | by another word containing the instruction. |
| 1061 | |
| 1062 | Degenerate cases: |
| 1063 | 3) |
| 1064 | push r8 |
| 1065 | move.d sp,r8 |
| 1066 | move.d r8,sp |
| 1067 | pop r8 |
| 1068 | |
| 1069 | Prologue instructions C++-code. |
| 1070 | Case 1) and 2) in the C-code may be followed by |
| 1071 | |
| 1072 | move.d r10,rS ; this |
| 1073 | move.d r11,rT ; P1 |
| 1074 | move.d r12,rU ; P2 |
| 1075 | move.d r13,rV ; P3 |
| 1076 | move.S [r8+U],rZ ; P4 |
| 1077 | |
| 1078 | if any of the call parameters are stored. The host expects these |
| 1079 | instructions to be executed in order to get the call parameters right. */ |
| 1080 | |
| 1081 | /* Examine the prologue of a function. The variable ip is the address of |
| 1082 | the first instruction of the prologue. The variable limit is the address |
| 1083 | of the first instruction after the prologue. The variable fi contains the |
| 1084 | information in struct frame_info. The variable frameless_p controls whether |
| 1085 | the entire prologue is examined (0) or just enough instructions to |
| 1086 | determine that it is a prologue (1). */ |
| 1087 | |
| 1088 | static CORE_ADDR |
| 1089 | cris_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
| 1090 | struct cris_unwind_cache *info) |
| 1091 | { |
| 1092 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1093 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1094 | |
| 1095 | /* Present instruction. */ |
| 1096 | unsigned short insn; |
| 1097 | |
| 1098 | /* Next instruction, lookahead. */ |
| 1099 | unsigned short insn_next; |
| 1100 | int regno; |
| 1101 | |
| 1102 | /* Is there a push fp? */ |
| 1103 | int have_fp; |
| 1104 | |
| 1105 | /* Number of byte on stack used for local variables and movem. */ |
| 1106 | int val; |
| 1107 | |
| 1108 | /* Highest register number in a movem. */ |
| 1109 | int regsave; |
| 1110 | |
| 1111 | /* move.d r<source_register>,rS */ |
| 1112 | short source_register; |
| 1113 | |
| 1114 | /* Scan limit. */ |
| 1115 | int limit; |
| 1116 | |
| 1117 | /* This frame is with respect to a leaf until a push srp is found. */ |
| 1118 | if (info) |
| 1119 | { |
| 1120 | info->leaf_function = 1; |
| 1121 | } |
| 1122 | |
| 1123 | /* Assume nothing on stack. */ |
| 1124 | val = 0; |
| 1125 | regsave = -1; |
| 1126 | |
| 1127 | /* If we were called without a this_frame, that means we were called |
| 1128 | from cris_skip_prologue which already tried to find the end of the |
| 1129 | prologue through the symbol information. 64 instructions past current |
| 1130 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ |
| 1131 | limit = this_frame ? get_frame_pc (this_frame) : pc + 64; |
| 1132 | |
| 1133 | /* Find the prologue instructions. */ |
| 1134 | while (pc > 0 && pc < limit) |
| 1135 | { |
| 1136 | insn = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1137 | pc += 2; |
| 1138 | if (insn == 0xE1FC) |
| 1139 | { |
| 1140 | /* push <reg> 32 bit instruction. */ |
| 1141 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1142 | pc += 2; |
| 1143 | regno = cris_get_operand2 (insn_next); |
| 1144 | if (info) |
| 1145 | { |
| 1146 | info->sp_offset += 4; |
| 1147 | } |
| 1148 | /* This check, meant to recognize srp, used to be regno == |
| 1149 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ |
| 1150 | if (insn_next == 0xBE7E) |
| 1151 | { |
| 1152 | if (info) |
| 1153 | { |
| 1154 | info->leaf_function = 0; |
| 1155 | } |
| 1156 | } |
| 1157 | else if (insn_next == 0x8FEE) |
| 1158 | { |
| 1159 | /* push $r8 */ |
| 1160 | if (info) |
| 1161 | { |
| 1162 | info->r8_offset = info->sp_offset; |
| 1163 | } |
| 1164 | } |
| 1165 | } |
| 1166 | else if (insn == 0x866E) |
| 1167 | { |
| 1168 | /* move.d sp,r8 */ |
| 1169 | if (info) |
| 1170 | { |
| 1171 | info->uses_frame = 1; |
| 1172 | } |
| 1173 | continue; |
| 1174 | } |
| 1175 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
| 1176 | && cris_get_mode (insn) == 0x0000 |
| 1177 | && cris_get_opcode (insn) == 0x000A) |
| 1178 | { |
| 1179 | /* subq <val>,sp */ |
| 1180 | if (info) |
| 1181 | { |
| 1182 | info->sp_offset += cris_get_quick_value (insn); |
| 1183 | } |
| 1184 | } |
| 1185 | else if (cris_get_mode (insn) == 0x0002 |
| 1186 | && cris_get_opcode (insn) == 0x000F |
| 1187 | && cris_get_size (insn) == 0x0003 |
| 1188 | && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch)) |
| 1189 | { |
| 1190 | /* movem r<regsave>,[sp] */ |
| 1191 | regsave = cris_get_operand2 (insn); |
| 1192 | } |
| 1193 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
| 1194 | && ((insn & 0x0F00) >> 8) == 0x0001 |
| 1195 | && (cris_get_signed_offset (insn) < 0)) |
| 1196 | { |
| 1197 | /* Immediate byte offset addressing prefix word with sp as base |
| 1198 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> |
| 1199 | is between 64 and 128. |
| 1200 | movem r<regsave>,[sp=sp-<val>] */ |
| 1201 | if (info) |
| 1202 | { |
| 1203 | info->sp_offset += -cris_get_signed_offset (insn); |
| 1204 | } |
| 1205 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1206 | pc += 2; |
| 1207 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE |
| 1208 | && cris_get_opcode (insn_next) == 0x000F |
| 1209 | && cris_get_size (insn_next) == 0x0003 |
| 1210 | && cris_get_operand1 (insn_next) == gdbarch_sp_regnum |
| 1211 | (gdbarch)) |
| 1212 | { |
| 1213 | regsave = cris_get_operand2 (insn_next); |
| 1214 | } |
| 1215 | else |
| 1216 | { |
| 1217 | /* The prologue ended before the limit was reached. */ |
| 1218 | pc -= 4; |
| 1219 | break; |
| 1220 | } |
| 1221 | } |
| 1222 | else if (cris_get_mode (insn) == 0x0001 |
| 1223 | && cris_get_opcode (insn) == 0x0009 |
| 1224 | && cris_get_size (insn) == 0x0002) |
| 1225 | { |
| 1226 | /* move.d r<10..13>,r<0..15> */ |
| 1227 | source_register = cris_get_operand1 (insn); |
| 1228 | |
| 1229 | /* FIXME? In the glibc solibs, the prologue might contain something |
| 1230 | like (this example taken from relocate_doit): |
| 1231 | move.d $pc,$r0 |
| 1232 | sub.d 0xfffef426,$r0 |
| 1233 | which isn't covered by the source_register check below. Question |
| 1234 | is whether to add a check for this combo, or make better use of |
| 1235 | the limit variable instead. */ |
| 1236 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) |
| 1237 | { |
| 1238 | /* The prologue ended before the limit was reached. */ |
| 1239 | pc -= 2; |
| 1240 | break; |
| 1241 | } |
| 1242 | } |
| 1243 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
| 1244 | /* The size is a fixed-size. */ |
| 1245 | && ((insn & 0x0F00) >> 8) == 0x0001 |
| 1246 | /* A negative offset. */ |
| 1247 | && (cris_get_signed_offset (insn) < 0)) |
| 1248 | { |
| 1249 | /* move.S rZ,[r8-U] (?) */ |
| 1250 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1251 | pc += 2; |
| 1252 | regno = cris_get_operand2 (insn_next); |
| 1253 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
| 1254 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
| 1255 | && cris_get_opcode (insn_next) == 0x000F) |
| 1256 | { |
| 1257 | /* move.S rZ,[r8-U] */ |
| 1258 | continue; |
| 1259 | } |
| 1260 | else |
| 1261 | { |
| 1262 | /* The prologue ended before the limit was reached. */ |
| 1263 | pc -= 4; |
| 1264 | break; |
| 1265 | } |
| 1266 | } |
| 1267 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
| 1268 | /* The size is a fixed-size. */ |
| 1269 | && ((insn & 0x0F00) >> 8) == 0x0001 |
| 1270 | /* A positive offset. */ |
| 1271 | && (cris_get_signed_offset (insn) > 0)) |
| 1272 | { |
| 1273 | /* move.S [r8+U],rZ (?) */ |
| 1274 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
| 1275 | pc += 2; |
| 1276 | regno = cris_get_operand2 (insn_next); |
| 1277 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
| 1278 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE |
| 1279 | && cris_get_opcode (insn_next) == 0x0009 |
| 1280 | && cris_get_operand1 (insn_next) == regno) |
| 1281 | { |
| 1282 | /* move.S [r8+U],rZ */ |
| 1283 | continue; |
| 1284 | } |
| 1285 | else |
| 1286 | { |
| 1287 | /* The prologue ended before the limit was reached. */ |
| 1288 | pc -= 4; |
| 1289 | break; |
| 1290 | } |
| 1291 | } |
| 1292 | else |
| 1293 | { |
| 1294 | /* The prologue ended before the limit was reached. */ |
| 1295 | pc -= 2; |
| 1296 | break; |
| 1297 | } |
| 1298 | } |
| 1299 | |
| 1300 | /* We only want to know the end of the prologue when this_frame and info |
| 1301 | are NULL (called from cris_skip_prologue i.e.). */ |
| 1302 | if (this_frame == NULL && info == NULL) |
| 1303 | { |
| 1304 | return pc; |
| 1305 | } |
| 1306 | |
| 1307 | info->size = info->sp_offset; |
| 1308 | |
| 1309 | /* Compute the previous frame's stack pointer (which is also the |
| 1310 | frame's ID's stack address), and this frame's base pointer. */ |
| 1311 | if (info->uses_frame) |
| 1312 | { |
| 1313 | ULONGEST this_base; |
| 1314 | /* The SP was moved to the FP. This indicates that a new frame |
| 1315 | was created. Get THIS frame's FP value by unwinding it from |
| 1316 | the next frame. */ |
| 1317 | this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM); |
| 1318 | info->base = this_base; |
| 1319 | info->saved_regs[CRIS_FP_REGNUM].addr = info->base; |
| 1320 | |
| 1321 | /* The FP points at the last saved register. Adjust the FP back |
| 1322 | to before the first saved register giving the SP. */ |
| 1323 | info->prev_sp = info->base + info->r8_offset; |
| 1324 | } |
| 1325 | else |
| 1326 | { |
| 1327 | ULONGEST this_base; |
| 1328 | /* Assume that the FP is this frame's SP but with that pushed |
| 1329 | stack space added back. */ |
| 1330 | this_base = get_frame_register_unsigned (this_frame, |
| 1331 | gdbarch_sp_regnum (gdbarch)); |
| 1332 | info->base = this_base; |
| 1333 | info->prev_sp = info->base + info->size; |
| 1334 | } |
| 1335 | |
| 1336 | /* Calculate the addresses for the saved registers on the stack. */ |
| 1337 | /* FIXME: The address calculation should really be done on the fly while |
| 1338 | we're analyzing the prologue (we only hold one regsave value as it is |
| 1339 | now). */ |
| 1340 | val = info->sp_offset; |
| 1341 | |
| 1342 | for (regno = regsave; regno >= 0; regno--) |
| 1343 | { |
| 1344 | info->saved_regs[regno].addr = info->base + info->r8_offset - val; |
| 1345 | val -= 4; |
| 1346 | } |
| 1347 | |
| 1348 | /* The previous frame's SP needed to be computed. Save the computed |
| 1349 | value. */ |
| 1350 | trad_frame_set_value (info->saved_regs, |
| 1351 | gdbarch_sp_regnum (gdbarch), info->prev_sp); |
| 1352 | |
| 1353 | if (!info->leaf_function) |
| 1354 | { |
| 1355 | /* SRP saved on the stack. But where? */ |
| 1356 | if (info->r8_offset == 0) |
| 1357 | { |
| 1358 | /* R8 not pushed yet. */ |
| 1359 | info->saved_regs[SRP_REGNUM].addr = info->base; |
| 1360 | } |
| 1361 | else |
| 1362 | { |
| 1363 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ |
| 1364 | info->saved_regs[SRP_REGNUM].addr = info->base + 4; |
| 1365 | } |
| 1366 | } |
| 1367 | |
| 1368 | /* The PC is found in SRP (the actual register or located on the stack). */ |
| 1369 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
| 1370 | = info->saved_regs[SRP_REGNUM]; |
| 1371 | |
| 1372 | return pc; |
| 1373 | } |
| 1374 | |
| 1375 | static CORE_ADDR |
| 1376 | crisv32_scan_prologue (CORE_ADDR pc, struct frame_info *this_frame, |
| 1377 | struct cris_unwind_cache *info) |
| 1378 | { |
| 1379 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1380 | ULONGEST this_base; |
| 1381 | |
| 1382 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not |
| 1383 | meant to be a full-fledged prologue scanner. It is only needed for |
| 1384 | the cases where we end up in code always lacking DWARF-2 CFI, notably: |
| 1385 | |
| 1386 | * PLT stubs (library calls) |
| 1387 | * call dummys |
| 1388 | * signal trampolines |
| 1389 | |
| 1390 | For those cases, it is assumed that there is no actual prologue; that |
| 1391 | the stack pointer is not adjusted, and (as a consequence) the return |
| 1392 | address is not pushed onto the stack. */ |
| 1393 | |
| 1394 | /* We only want to know the end of the prologue when this_frame and info |
| 1395 | are NULL (called from cris_skip_prologue i.e.). */ |
| 1396 | if (this_frame == NULL && info == NULL) |
| 1397 | { |
| 1398 | return pc; |
| 1399 | } |
| 1400 | |
| 1401 | /* The SP is assumed to be unaltered. */ |
| 1402 | this_base = get_frame_register_unsigned (this_frame, |
| 1403 | gdbarch_sp_regnum (gdbarch)); |
| 1404 | info->base = this_base; |
| 1405 | info->prev_sp = this_base; |
| 1406 | |
| 1407 | /* The PC is assumed to be found in SRP. */ |
| 1408 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
| 1409 | = info->saved_regs[SRP_REGNUM]; |
| 1410 | |
| 1411 | return pc; |
| 1412 | } |
| 1413 | |
| 1414 | /* Advance pc beyond any function entry prologue instructions at pc |
| 1415 | to reach some "real" code. */ |
| 1416 | |
| 1417 | /* Given a PC value corresponding to the start of a function, return the PC |
| 1418 | of the first instruction after the function prologue. */ |
| 1419 | |
| 1420 | static CORE_ADDR |
| 1421 | cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1422 | { |
| 1423 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1424 | CORE_ADDR func_addr, func_end; |
| 1425 | struct symtab_and_line sal; |
| 1426 | CORE_ADDR pc_after_prologue; |
| 1427 | |
| 1428 | /* If we have line debugging information, then the end of the prologue |
| 1429 | should the first assembly instruction of the first source line. */ |
| 1430 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 1431 | { |
| 1432 | sal = find_pc_line (func_addr, 0); |
| 1433 | if (sal.end > 0 && sal.end < func_end) |
| 1434 | return sal.end; |
| 1435 | } |
| 1436 | |
| 1437 | if (tdep->cris_version == 32) |
| 1438 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); |
| 1439 | else |
| 1440 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); |
| 1441 | |
| 1442 | return pc_after_prologue; |
| 1443 | } |
| 1444 | |
| 1445 | static CORE_ADDR |
| 1446 | cris_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1447 | { |
| 1448 | ULONGEST pc; |
| 1449 | pc = frame_unwind_register_unsigned (next_frame, |
| 1450 | gdbarch_pc_regnum (gdbarch)); |
| 1451 | return pc; |
| 1452 | } |
| 1453 | |
| 1454 | static CORE_ADDR |
| 1455 | cris_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1456 | { |
| 1457 | ULONGEST sp; |
| 1458 | sp = frame_unwind_register_unsigned (next_frame, |
| 1459 | gdbarch_sp_regnum (gdbarch)); |
| 1460 | return sp; |
| 1461 | } |
| 1462 | |
| 1463 | /* Use the program counter to determine the contents and size of a breakpoint |
| 1464 | instruction. It returns a pointer to a string of bytes that encode a |
| 1465 | breakpoint instruction, stores the length of the string to *lenptr, and |
| 1466 | adjusts pcptr (if necessary) to point to the actual memory location where |
| 1467 | the breakpoint should be inserted. */ |
| 1468 | |
| 1469 | static const unsigned char * |
| 1470 | cris_breakpoint_from_pc (struct gdbarch *gdbarch, |
| 1471 | CORE_ADDR *pcptr, int *lenptr) |
| 1472 | { |
| 1473 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1474 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
| 1475 | static unsigned char break15_insn[] = {0x3f, 0xe9}; |
| 1476 | *lenptr = 2; |
| 1477 | |
| 1478 | if (tdep->cris_mode == cris_mode_guru) |
| 1479 | return break15_insn; |
| 1480 | else |
| 1481 | return break8_insn; |
| 1482 | } |
| 1483 | |
| 1484 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
| 1485 | 0 otherwise. */ |
| 1486 | |
| 1487 | static int |
| 1488 | cris_spec_reg_applicable (struct gdbarch *gdbarch, |
| 1489 | struct cris_spec_reg spec_reg) |
| 1490 | { |
| 1491 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1492 | int version = tdep->cris_version; |
| 1493 | |
| 1494 | switch (spec_reg.applicable_version) |
| 1495 | { |
| 1496 | case cris_ver_version_all: |
| 1497 | return 1; |
| 1498 | case cris_ver_warning: |
| 1499 | /* Indeterminate/obsolete. */ |
| 1500 | return 0; |
| 1501 | case cris_ver_v0_3: |
| 1502 | return (version >= 0 && version <= 3); |
| 1503 | case cris_ver_v3p: |
| 1504 | return (version >= 3); |
| 1505 | case cris_ver_v8: |
| 1506 | return (version == 8 || version == 9); |
| 1507 | case cris_ver_v8p: |
| 1508 | return (version >= 8); |
| 1509 | case cris_ver_v0_10: |
| 1510 | return (version >= 0 && version <= 10); |
| 1511 | case cris_ver_v3_10: |
| 1512 | return (version >= 3 && version <= 10); |
| 1513 | case cris_ver_v8_10: |
| 1514 | return (version >= 8 && version <= 10); |
| 1515 | case cris_ver_v10: |
| 1516 | return (version == 10); |
| 1517 | case cris_ver_v10p: |
| 1518 | return (version >= 10); |
| 1519 | case cris_ver_v32p: |
| 1520 | return (version >= 32); |
| 1521 | default: |
| 1522 | /* Invalid cris version. */ |
| 1523 | return 0; |
| 1524 | } |
| 1525 | } |
| 1526 | |
| 1527 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
| 1528 | register, -1 for an invalid register. */ |
| 1529 | |
| 1530 | static int |
| 1531 | cris_register_size (struct gdbarch *gdbarch, int regno) |
| 1532 | { |
| 1533 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1534 | int i; |
| 1535 | int spec_regno; |
| 1536 | |
| 1537 | if (regno >= 0 && regno < NUM_GENREGS) |
| 1538 | { |
| 1539 | /* General registers (R0 - R15) are 32 bits. */ |
| 1540 | return 4; |
| 1541 | } |
| 1542 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
| 1543 | { |
| 1544 | /* Special register (R16 - R31). cris_spec_regs is zero-based. |
| 1545 | Adjust regno accordingly. */ |
| 1546 | spec_regno = regno - NUM_GENREGS; |
| 1547 | |
| 1548 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
| 1549 | { |
| 1550 | if (cris_spec_regs[i].number == spec_regno |
| 1551 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
| 1552 | /* Go with the first applicable register. */ |
| 1553 | return cris_spec_regs[i].reg_size; |
| 1554 | } |
| 1555 | /* Special register not applicable to this CRIS version. */ |
| 1556 | return 0; |
| 1557 | } |
| 1558 | else if (regno >= gdbarch_pc_regnum (gdbarch) |
| 1559 | && regno < gdbarch_num_regs (gdbarch)) |
| 1560 | { |
| 1561 | /* This will apply to CRISv32 only where there are additional registers |
| 1562 | after the special registers (pseudo PC and support registers). */ |
| 1563 | return 4; |
| 1564 | } |
| 1565 | |
| 1566 | |
| 1567 | return -1; |
| 1568 | } |
| 1569 | |
| 1570 | /* Nonzero if regno should not be fetched from the target. This is the case |
| 1571 | for unimplemented (size 0) and non-existant registers. */ |
| 1572 | |
| 1573 | static int |
| 1574 | cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
| 1575 | { |
| 1576 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
| 1577 | || (cris_register_size (gdbarch, regno) == 0)); |
| 1578 | } |
| 1579 | |
| 1580 | /* Nonzero if regno should not be written to the target, for various |
| 1581 | reasons. */ |
| 1582 | |
| 1583 | static int |
| 1584 | cris_cannot_store_register (struct gdbarch *gdbarch, int regno) |
| 1585 | { |
| 1586 | /* There are three kinds of registers we refuse to write to. |
| 1587 | 1. Those that not implemented. |
| 1588 | 2. Those that are read-only (depends on the processor mode). |
| 1589 | 3. Those registers to which a write has no effect. */ |
| 1590 | |
| 1591 | if (regno < 0 |
| 1592 | || regno >= gdbarch_num_regs (gdbarch) |
| 1593 | || cris_register_size (gdbarch, regno) == 0) |
| 1594 | /* Not implemented. */ |
| 1595 | return 1; |
| 1596 | |
| 1597 | else if (regno == VR_REGNUM) |
| 1598 | /* Read-only. */ |
| 1599 | return 1; |
| 1600 | |
| 1601 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) |
| 1602 | /* Writing has no effect. */ |
| 1603 | return 1; |
| 1604 | |
| 1605 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
| 1606 | agent decide whether they are writable. */ |
| 1607 | |
| 1608 | return 0; |
| 1609 | } |
| 1610 | |
| 1611 | /* Nonzero if regno should not be fetched from the target. This is the case |
| 1612 | for unimplemented (size 0) and non-existant registers. */ |
| 1613 | |
| 1614 | static int |
| 1615 | crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
| 1616 | { |
| 1617 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
| 1618 | || (cris_register_size (gdbarch, regno) == 0)); |
| 1619 | } |
| 1620 | |
| 1621 | /* Nonzero if regno should not be written to the target, for various |
| 1622 | reasons. */ |
| 1623 | |
| 1624 | static int |
| 1625 | crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno) |
| 1626 | { |
| 1627 | /* There are three kinds of registers we refuse to write to. |
| 1628 | 1. Those that not implemented. |
| 1629 | 2. Those that are read-only (depends on the processor mode). |
| 1630 | 3. Those registers to which a write has no effect. */ |
| 1631 | |
| 1632 | if (regno < 0 |
| 1633 | || regno >= gdbarch_num_regs (gdbarch) |
| 1634 | || cris_register_size (gdbarch, regno) == 0) |
| 1635 | /* Not implemented. */ |
| 1636 | return 1; |
| 1637 | |
| 1638 | else if (regno == VR_REGNUM) |
| 1639 | /* Read-only. */ |
| 1640 | return 1; |
| 1641 | |
| 1642 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) |
| 1643 | /* Writing has no effect. */ |
| 1644 | return 1; |
| 1645 | |
| 1646 | /* Many special registers are read-only in user mode. Let the debug |
| 1647 | agent decide whether they are writable. */ |
| 1648 | |
| 1649 | return 0; |
| 1650 | } |
| 1651 | |
| 1652 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
| 1653 | of data in register regno. */ |
| 1654 | |
| 1655 | static struct type * |
| 1656 | cris_register_type (struct gdbarch *gdbarch, int regno) |
| 1657 | { |
| 1658 | if (regno == gdbarch_pc_regnum (gdbarch)) |
| 1659 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 1660 | else if (regno == gdbarch_sp_regnum (gdbarch) |
| 1661 | || regno == CRIS_FP_REGNUM) |
| 1662 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 1663 | else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
| 1664 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) |
| 1665 | /* Note: R8 taken care of previous clause. */ |
| 1666 | return builtin_type (gdbarch)->builtin_uint32; |
| 1667 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) |
| 1668 | return builtin_type (gdbarch)->builtin_uint16; |
| 1669 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) |
| 1670 | return builtin_type (gdbarch)->builtin_uint8; |
| 1671 | else |
| 1672 | /* Invalid (unimplemented) register. */ |
| 1673 | return builtin_type (gdbarch)->builtin_int0; |
| 1674 | } |
| 1675 | |
| 1676 | static struct type * |
| 1677 | crisv32_register_type (struct gdbarch *gdbarch, int regno) |
| 1678 | { |
| 1679 | if (regno == gdbarch_pc_regnum (gdbarch)) |
| 1680 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 1681 | else if (regno == gdbarch_sp_regnum (gdbarch) |
| 1682 | || regno == CRIS_FP_REGNUM) |
| 1683 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 1684 | else if ((regno >= 0 && regno <= ACR_REGNUM) |
| 1685 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) |
| 1686 | || (regno == PID_REGNUM) |
| 1687 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) |
| 1688 | /* Note: R8 and SP taken care of by previous clause. */ |
| 1689 | return builtin_type (gdbarch)->builtin_uint32; |
| 1690 | else if (regno == WZ_REGNUM) |
| 1691 | return builtin_type (gdbarch)->builtin_uint16; |
| 1692 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) |
| 1693 | return builtin_type (gdbarch)->builtin_uint8; |
| 1694 | else |
| 1695 | { |
| 1696 | /* Invalid (unimplemented) register. Should not happen as there are |
| 1697 | no unimplemented CRISv32 registers. */ |
| 1698 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
| 1699 | return builtin_type (gdbarch)->builtin_int0; |
| 1700 | } |
| 1701 | } |
| 1702 | |
| 1703 | /* Stores a function return value of type type, where valbuf is the address |
| 1704 | of the value to be stored. */ |
| 1705 | |
| 1706 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
| 1707 | |
| 1708 | static void |
| 1709 | cris_store_return_value (struct type *type, struct regcache *regcache, |
| 1710 | const void *valbuf) |
| 1711 | { |
| 1712 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1713 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1714 | ULONGEST val; |
| 1715 | int len = TYPE_LENGTH (type); |
| 1716 | |
| 1717 | if (len <= 4) |
| 1718 | { |
| 1719 | /* Put the return value in R10. */ |
| 1720 | val = extract_unsigned_integer (valbuf, len, byte_order); |
| 1721 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
| 1722 | } |
| 1723 | else if (len <= 8) |
| 1724 | { |
| 1725 | /* Put the return value in R10 and R11. */ |
| 1726 | val = extract_unsigned_integer (valbuf, 4, byte_order); |
| 1727 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
| 1728 | val = extract_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order); |
| 1729 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); |
| 1730 | } |
| 1731 | else |
| 1732 | error (_("cris_store_return_value: type length too large.")); |
| 1733 | } |
| 1734 | |
| 1735 | /* Return the name of register regno as a string. Return NULL for an |
| 1736 | invalid or unimplemented register. */ |
| 1737 | |
| 1738 | static const char * |
| 1739 | cris_special_register_name (struct gdbarch *gdbarch, int regno) |
| 1740 | { |
| 1741 | int spec_regno; |
| 1742 | int i; |
| 1743 | |
| 1744 | /* Special register (R16 - R31). cris_spec_regs is zero-based. |
| 1745 | Adjust regno accordingly. */ |
| 1746 | spec_regno = regno - NUM_GENREGS; |
| 1747 | |
| 1748 | /* Assume nothing about the layout of the cris_spec_regs struct |
| 1749 | when searching. */ |
| 1750 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
| 1751 | { |
| 1752 | if (cris_spec_regs[i].number == spec_regno |
| 1753 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
| 1754 | /* Go with the first applicable register. */ |
| 1755 | return cris_spec_regs[i].name; |
| 1756 | } |
| 1757 | /* Special register not applicable to this CRIS version. */ |
| 1758 | return NULL; |
| 1759 | } |
| 1760 | |
| 1761 | static const char * |
| 1762 | cris_register_name (struct gdbarch *gdbarch, int regno) |
| 1763 | { |
| 1764 | static char *cris_genreg_names[] = |
| 1765 | { "r0", "r1", "r2", "r3", \ |
| 1766 | "r4", "r5", "r6", "r7", \ |
| 1767 | "r8", "r9", "r10", "r11", \ |
| 1768 | "r12", "r13", "sp", "pc" }; |
| 1769 | |
| 1770 | if (regno >= 0 && regno < NUM_GENREGS) |
| 1771 | { |
| 1772 | /* General register. */ |
| 1773 | return cris_genreg_names[regno]; |
| 1774 | } |
| 1775 | else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch)) |
| 1776 | { |
| 1777 | return cris_special_register_name (gdbarch, regno); |
| 1778 | } |
| 1779 | else |
| 1780 | { |
| 1781 | /* Invalid register. */ |
| 1782 | return NULL; |
| 1783 | } |
| 1784 | } |
| 1785 | |
| 1786 | static const char * |
| 1787 | crisv32_register_name (struct gdbarch *gdbarch, int regno) |
| 1788 | { |
| 1789 | static char *crisv32_genreg_names[] = |
| 1790 | { "r0", "r1", "r2", "r3", \ |
| 1791 | "r4", "r5", "r6", "r7", \ |
| 1792 | "r8", "r9", "r10", "r11", \ |
| 1793 | "r12", "r13", "sp", "acr" |
| 1794 | }; |
| 1795 | |
| 1796 | static char *crisv32_sreg_names[] = |
| 1797 | { "s0", "s1", "s2", "s3", \ |
| 1798 | "s4", "s5", "s6", "s7", \ |
| 1799 | "s8", "s9", "s10", "s11", \ |
| 1800 | "s12", "s13", "s14", "s15" |
| 1801 | }; |
| 1802 | |
| 1803 | if (regno >= 0 && regno < NUM_GENREGS) |
| 1804 | { |
| 1805 | /* General register. */ |
| 1806 | return crisv32_genreg_names[regno]; |
| 1807 | } |
| 1808 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
| 1809 | { |
| 1810 | return cris_special_register_name (gdbarch, regno); |
| 1811 | } |
| 1812 | else if (regno == gdbarch_pc_regnum (gdbarch)) |
| 1813 | { |
| 1814 | return "pc"; |
| 1815 | } |
| 1816 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) |
| 1817 | { |
| 1818 | return crisv32_sreg_names[regno - S0_REGNUM]; |
| 1819 | } |
| 1820 | else |
| 1821 | { |
| 1822 | /* Invalid register. */ |
| 1823 | return NULL; |
| 1824 | } |
| 1825 | } |
| 1826 | |
| 1827 | /* Convert DWARF register number REG to the appropriate register |
| 1828 | number used by GDB. */ |
| 1829 | |
| 1830 | static int |
| 1831 | cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 1832 | { |
| 1833 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
| 1834 | numbering, MOF is 18). |
| 1835 | Adapted from gcc/config/cris/cris.h. */ |
| 1836 | static int cris_dwarf_regmap[] = { |
| 1837 | 0, 1, 2, 3, |
| 1838 | 4, 5, 6, 7, |
| 1839 | 8, 9, 10, 11, |
| 1840 | 12, 13, 14, 15, |
| 1841 | 27, -1, -1, -1, |
| 1842 | -1, -1, -1, 23, |
| 1843 | -1, -1, -1, 27, |
| 1844 | -1, -1, -1, -1 |
| 1845 | }; |
| 1846 | int regnum = -1; |
| 1847 | |
| 1848 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) |
| 1849 | regnum = cris_dwarf_regmap[reg]; |
| 1850 | |
| 1851 | if (regnum == -1) |
| 1852 | warning (_("Unmapped DWARF Register #%d encountered."), reg); |
| 1853 | |
| 1854 | return regnum; |
| 1855 | } |
| 1856 | |
| 1857 | /* DWARF-2 frame support. */ |
| 1858 | |
| 1859 | static void |
| 1860 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, |
| 1861 | struct dwarf2_frame_state_reg *reg, |
| 1862 | struct frame_info *this_frame) |
| 1863 | { |
| 1864 | /* The return address column. */ |
| 1865 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
| 1866 | reg->how = DWARF2_FRAME_REG_RA; |
| 1867 | |
| 1868 | /* The call frame address. */ |
| 1869 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
| 1870 | reg->how = DWARF2_FRAME_REG_CFA; |
| 1871 | } |
| 1872 | |
| 1873 | /* Extract from an array regbuf containing the raw register state a function |
| 1874 | return value of type type, and copy that, in virtual format, into |
| 1875 | valbuf. */ |
| 1876 | |
| 1877 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
| 1878 | |
| 1879 | static void |
| 1880 | cris_extract_return_value (struct type *type, struct regcache *regcache, |
| 1881 | void *valbuf) |
| 1882 | { |
| 1883 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1884 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1885 | ULONGEST val; |
| 1886 | int len = TYPE_LENGTH (type); |
| 1887 | |
| 1888 | if (len <= 4) |
| 1889 | { |
| 1890 | /* Get the return value from R10. */ |
| 1891 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); |
| 1892 | store_unsigned_integer (valbuf, len, byte_order, val); |
| 1893 | } |
| 1894 | else if (len <= 8) |
| 1895 | { |
| 1896 | /* Get the return value from R10 and R11. */ |
| 1897 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); |
| 1898 | store_unsigned_integer (valbuf, 4, byte_order, val); |
| 1899 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); |
| 1900 | store_unsigned_integer ((char *)valbuf + 4, len - 4, byte_order, val); |
| 1901 | } |
| 1902 | else |
| 1903 | error (_("cris_extract_return_value: type length too large")); |
| 1904 | } |
| 1905 | |
| 1906 | /* Handle the CRIS return value convention. */ |
| 1907 | |
| 1908 | static enum return_value_convention |
| 1909 | cris_return_value (struct gdbarch *gdbarch, struct type *func_type, |
| 1910 | struct type *type, struct regcache *regcache, |
| 1911 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 1912 | { |
| 1913 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 1914 | || TYPE_CODE (type) == TYPE_CODE_UNION |
| 1915 | || TYPE_LENGTH (type) > 8) |
| 1916 | /* Structs, unions, and anything larger than 8 bytes (2 registers) |
| 1917 | goes on the stack. */ |
| 1918 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1919 | |
| 1920 | if (readbuf) |
| 1921 | cris_extract_return_value (type, regcache, readbuf); |
| 1922 | if (writebuf) |
| 1923 | cris_store_return_value (type, regcache, writebuf); |
| 1924 | |
| 1925 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1926 | } |
| 1927 | |
| 1928 | /* Calculates a value that measures how good inst_args constraints an |
| 1929 | instruction. It stems from cris_constraint, found in cris-dis.c. */ |
| 1930 | |
| 1931 | static int |
| 1932 | constraint (unsigned int insn, const signed char *inst_args, |
| 1933 | inst_env_type *inst_env) |
| 1934 | { |
| 1935 | int retval = 0; |
| 1936 | int tmp, i; |
| 1937 | |
| 1938 | const char *s = inst_args; |
| 1939 | |
| 1940 | for (; *s; s++) |
| 1941 | switch (*s) |
| 1942 | { |
| 1943 | case 'm': |
| 1944 | if ((insn & 0x30) == 0x30) |
| 1945 | return -1; |
| 1946 | break; |
| 1947 | |
| 1948 | case 'S': |
| 1949 | /* A prefix operand. */ |
| 1950 | if (inst_env->prefix_found) |
| 1951 | break; |
| 1952 | else |
| 1953 | return -1; |
| 1954 | |
| 1955 | case 'B': |
| 1956 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for |
| 1957 | valid "push" size. In case of special register, it may be != 4. */ |
| 1958 | if (inst_env->prefix_found) |
| 1959 | break; |
| 1960 | else |
| 1961 | return -1; |
| 1962 | |
| 1963 | case 'D': |
| 1964 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); |
| 1965 | if (!retval) |
| 1966 | return -1; |
| 1967 | else |
| 1968 | retval += 4; |
| 1969 | break; |
| 1970 | |
| 1971 | case 'P': |
| 1972 | tmp = (insn >> 0xC) & 0xF; |
| 1973 | |
| 1974 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
| 1975 | { |
| 1976 | /* Since we match four bits, we will give a value of |
| 1977 | 4 - 1 = 3 in a match. If there is a corresponding |
| 1978 | exact match of a special register in another pattern, it |
| 1979 | will get a value of 4, which will be higher. This should |
| 1980 | be correct in that an exact pattern would match better that |
| 1981 | a general pattern. |
| 1982 | Note that there is a reason for not returning zero; the |
| 1983 | pattern for "clear" is partly matched in the bit-pattern |
| 1984 | (the two lower bits must be zero), while the bit-pattern |
| 1985 | for a move from a special register is matched in the |
| 1986 | register constraint. |
| 1987 | This also means we will will have a race condition if |
| 1988 | there is a partly match in three bits in the bit pattern. */ |
| 1989 | if (tmp == cris_spec_regs[i].number) |
| 1990 | { |
| 1991 | retval += 3; |
| 1992 | break; |
| 1993 | } |
| 1994 | } |
| 1995 | |
| 1996 | if (cris_spec_regs[i].name == NULL) |
| 1997 | return -1; |
| 1998 | break; |
| 1999 | } |
| 2000 | return retval; |
| 2001 | } |
| 2002 | |
| 2003 | /* Returns the number of bits set in the variable value. */ |
| 2004 | |
| 2005 | static int |
| 2006 | number_of_bits (unsigned int value) |
| 2007 | { |
| 2008 | int number_of_bits = 0; |
| 2009 | |
| 2010 | while (value != 0) |
| 2011 | { |
| 2012 | number_of_bits += 1; |
| 2013 | value &= (value - 1); |
| 2014 | } |
| 2015 | return number_of_bits; |
| 2016 | } |
| 2017 | |
| 2018 | /* Finds the address that should contain the single step breakpoint(s). |
| 2019 | It stems from code in cris-dis.c. */ |
| 2020 | |
| 2021 | static int |
| 2022 | find_cris_op (unsigned short insn, inst_env_type *inst_env) |
| 2023 | { |
| 2024 | int i; |
| 2025 | int max_level_of_match = -1; |
| 2026 | int max_matched = -1; |
| 2027 | int level_of_match; |
| 2028 | |
| 2029 | for (i = 0; cris_opcodes[i].name != NULL; i++) |
| 2030 | { |
| 2031 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) |
| 2032 | && ((cris_opcodes[i].lose & insn) == 0) |
| 2033 | /* Only CRISv10 instructions, please. */ |
| 2034 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) |
| 2035 | { |
| 2036 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); |
| 2037 | if (level_of_match >= 0) |
| 2038 | { |
| 2039 | level_of_match += |
| 2040 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); |
| 2041 | if (level_of_match > max_level_of_match) |
| 2042 | { |
| 2043 | max_matched = i; |
| 2044 | max_level_of_match = level_of_match; |
| 2045 | if (level_of_match == 16) |
| 2046 | { |
| 2047 | /* All bits matched, cannot find better. */ |
| 2048 | break; |
| 2049 | } |
| 2050 | } |
| 2051 | } |
| 2052 | } |
| 2053 | } |
| 2054 | return max_matched; |
| 2055 | } |
| 2056 | |
| 2057 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is |
| 2058 | actually an internal error. */ |
| 2059 | |
| 2060 | static int |
| 2061 | find_step_target (struct frame_info *frame, inst_env_type *inst_env) |
| 2062 | { |
| 2063 | int i; |
| 2064 | int offset; |
| 2065 | unsigned short insn; |
| 2066 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2067 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2068 | |
| 2069 | /* Create a local register image and set the initial state. */ |
| 2070 | for (i = 0; i < NUM_GENREGS; i++) |
| 2071 | { |
| 2072 | inst_env->reg[i] = |
| 2073 | (unsigned long) get_frame_register_unsigned (frame, i); |
| 2074 | } |
| 2075 | offset = NUM_GENREGS; |
| 2076 | for (i = 0; i < NUM_SPECREGS; i++) |
| 2077 | { |
| 2078 | inst_env->preg[i] = |
| 2079 | (unsigned long) get_frame_register_unsigned (frame, offset + i); |
| 2080 | } |
| 2081 | inst_env->branch_found = 0; |
| 2082 | inst_env->slot_needed = 0; |
| 2083 | inst_env->delay_slot_pc_active = 0; |
| 2084 | inst_env->prefix_found = 0; |
| 2085 | inst_env->invalid = 0; |
| 2086 | inst_env->xflag_found = 0; |
| 2087 | inst_env->disable_interrupt = 0; |
| 2088 | inst_env->byte_order = byte_order; |
| 2089 | |
| 2090 | /* Look for a step target. */ |
| 2091 | do |
| 2092 | { |
| 2093 | /* Read an instruction from the client. */ |
| 2094 | insn = read_memory_unsigned_integer |
| 2095 | (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order); |
| 2096 | |
| 2097 | /* If the instruction is not in a delay slot the new content of the |
| 2098 | PC is [PC] + 2. If the instruction is in a delay slot it is not |
| 2099 | that simple. Since a instruction in a delay slot cannot change |
| 2100 | the content of the PC, it does not matter what value PC will have. |
| 2101 | Just make sure it is a valid instruction. */ |
| 2102 | if (!inst_env->delay_slot_pc_active) |
| 2103 | { |
| 2104 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2; |
| 2105 | } |
| 2106 | else |
| 2107 | { |
| 2108 | inst_env->delay_slot_pc_active = 0; |
| 2109 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] |
| 2110 | = inst_env->delay_slot_pc; |
| 2111 | } |
| 2112 | /* Analyse the present instruction. */ |
| 2113 | i = find_cris_op (insn, inst_env); |
| 2114 | if (i == -1) |
| 2115 | { |
| 2116 | inst_env->invalid = 1; |
| 2117 | } |
| 2118 | else |
| 2119 | { |
| 2120 | cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env); |
| 2121 | } |
| 2122 | } while (!inst_env->invalid |
| 2123 | && (inst_env->prefix_found || inst_env->xflag_found |
| 2124 | || inst_env->slot_needed)); |
| 2125 | return i; |
| 2126 | } |
| 2127 | |
| 2128 | /* There is no hardware single-step support. The function find_step_target |
| 2129 | digs through the opcodes in order to find all possible targets. |
| 2130 | Either one ordinary target or two targets for branches may be found. */ |
| 2131 | |
| 2132 | static int |
| 2133 | cris_software_single_step (struct frame_info *frame) |
| 2134 | { |
| 2135 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2136 | struct address_space *aspace = get_frame_address_space (frame); |
| 2137 | inst_env_type inst_env; |
| 2138 | |
| 2139 | /* Analyse the present instruction environment and insert |
| 2140 | breakpoints. */ |
| 2141 | int status = find_step_target (frame, &inst_env); |
| 2142 | if (status == -1) |
| 2143 | { |
| 2144 | /* Could not find a target. Things are likely to go downhill |
| 2145 | from here. */ |
| 2146 | warning (_("CRIS software single step could not find a step target.")); |
| 2147 | } |
| 2148 | else |
| 2149 | { |
| 2150 | /* Insert at most two breakpoints. One for the next PC content |
| 2151 | and possibly another one for a branch, jump, etc. */ |
| 2152 | CORE_ADDR next_pc |
| 2153 | = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)]; |
| 2154 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
| 2155 | if (inst_env.branch_found |
| 2156 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) |
| 2157 | { |
| 2158 | CORE_ADDR branch_target_address |
| 2159 | = (CORE_ADDR) inst_env.branch_break_address; |
| 2160 | insert_single_step_breakpoint (gdbarch, |
| 2161 | aspace, branch_target_address); |
| 2162 | } |
| 2163 | } |
| 2164 | |
| 2165 | return 1; |
| 2166 | } |
| 2167 | |
| 2168 | /* Calculates the prefix value for quick offset addressing mode. */ |
| 2169 | |
| 2170 | static void |
| 2171 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
| 2172 | { |
| 2173 | /* It's invalid to be in a delay slot. You can't have a prefix to this |
| 2174 | instruction (not 100% sure). */ |
| 2175 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2176 | { |
| 2177 | inst_env->invalid = 1; |
| 2178 | return; |
| 2179 | } |
| 2180 | |
| 2181 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
| 2182 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); |
| 2183 | |
| 2184 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 2185 | need updating. */ |
| 2186 | inst_env->slot_needed = 0; |
| 2187 | inst_env->prefix_found = 1; |
| 2188 | } |
| 2189 | |
| 2190 | /* Updates the autoincrement register. The size of the increment is derived |
| 2191 | from the size of the operation. The PC is always kept aligned on even |
| 2192 | word addresses. */ |
| 2193 | |
| 2194 | static void |
| 2195 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
| 2196 | { |
| 2197 | if (size == INST_BYTE_SIZE) |
| 2198 | { |
| 2199 | inst_env->reg[cris_get_operand1 (inst)] += 1; |
| 2200 | |
| 2201 | /* The PC must be word aligned, so increase the PC with one |
| 2202 | word even if the size is byte. */ |
| 2203 | if (cris_get_operand1 (inst) == REG_PC) |
| 2204 | { |
| 2205 | inst_env->reg[REG_PC] += 1; |
| 2206 | } |
| 2207 | } |
| 2208 | else if (size == INST_WORD_SIZE) |
| 2209 | { |
| 2210 | inst_env->reg[cris_get_operand1 (inst)] += 2; |
| 2211 | } |
| 2212 | else if (size == INST_DWORD_SIZE) |
| 2213 | { |
| 2214 | inst_env->reg[cris_get_operand1 (inst)] += 4; |
| 2215 | } |
| 2216 | else |
| 2217 | { |
| 2218 | /* Invalid size. */ |
| 2219 | inst_env->invalid = 1; |
| 2220 | } |
| 2221 | } |
| 2222 | |
| 2223 | /* Just a forward declaration. */ |
| 2224 | |
| 2225 | static unsigned long get_data_from_address (unsigned short *inst, |
| 2226 | CORE_ADDR address, |
| 2227 | enum bfd_endian byte_order); |
| 2228 | |
| 2229 | /* Calculates the prefix value for the general case of offset addressing |
| 2230 | mode. */ |
| 2231 | |
| 2232 | static void |
| 2233 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
| 2234 | { |
| 2235 | |
| 2236 | long offset; |
| 2237 | |
| 2238 | /* It's invalid to be in a delay slot. */ |
| 2239 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2240 | { |
| 2241 | inst_env->invalid = 1; |
| 2242 | return; |
| 2243 | } |
| 2244 | |
| 2245 | /* The calculation of prefix_value used to be after process_autoincrement, |
| 2246 | but that fails for an instruction such as jsr [$r0+12] which is encoded |
| 2247 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it |
| 2248 | mustn't be incremented until we have read it and what it points at. */ |
| 2249 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
| 2250 | |
| 2251 | /* The offset is an indirection of the contents of the operand1 register. */ |
| 2252 | inst_env->prefix_value += |
| 2253 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)], |
| 2254 | inst_env->byte_order); |
| 2255 | |
| 2256 | if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2257 | { |
| 2258 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 2259 | } |
| 2260 | |
| 2261 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 2262 | need updating. */ |
| 2263 | inst_env->slot_needed = 0; |
| 2264 | inst_env->prefix_found = 1; |
| 2265 | } |
| 2266 | |
| 2267 | /* Calculates the prefix value for the index addressing mode. */ |
| 2268 | |
| 2269 | static void |
| 2270 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
| 2271 | { |
| 2272 | /* It's invalid to be in a delay slot. I can't see that it's possible to |
| 2273 | have a prefix to this instruction. So I will treat this as invalid. */ |
| 2274 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2275 | { |
| 2276 | inst_env->invalid = 1; |
| 2277 | return; |
| 2278 | } |
| 2279 | |
| 2280 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; |
| 2281 | |
| 2282 | /* The offset is the operand2 value shifted the size of the instruction |
| 2283 | to the left. */ |
| 2284 | inst_env->prefix_value += |
| 2285 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); |
| 2286 | |
| 2287 | /* If the PC is operand1 (base) the address used is the address after |
| 2288 | the main instruction, i.e. address + 2 (the PC is already compensated |
| 2289 | for the prefix operation). */ |
| 2290 | if (cris_get_operand1 (inst) == REG_PC) |
| 2291 | { |
| 2292 | inst_env->prefix_value += 2; |
| 2293 | } |
| 2294 | |
| 2295 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 2296 | need updating. */ |
| 2297 | inst_env->slot_needed = 0; |
| 2298 | inst_env->xflag_found = 0; |
| 2299 | inst_env->prefix_found = 1; |
| 2300 | } |
| 2301 | |
| 2302 | /* Calculates the prefix value for the double indirect addressing mode. */ |
| 2303 | |
| 2304 | static void |
| 2305 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
| 2306 | { |
| 2307 | |
| 2308 | CORE_ADDR address; |
| 2309 | |
| 2310 | /* It's invalid to be in a delay slot. */ |
| 2311 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2312 | { |
| 2313 | inst_env->invalid = 1; |
| 2314 | return; |
| 2315 | } |
| 2316 | |
| 2317 | /* The prefix value is one dereference of the contents of the operand1 |
| 2318 | register. */ |
| 2319 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; |
| 2320 | inst_env->prefix_value |
| 2321 | = read_memory_unsigned_integer (address, 4, inst_env->byte_order); |
| 2322 | |
| 2323 | /* Check if the mode is autoincrement. */ |
| 2324 | if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2325 | { |
| 2326 | inst_env->reg[cris_get_operand1 (inst)] += 4; |
| 2327 | } |
| 2328 | |
| 2329 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
| 2330 | need updating. */ |
| 2331 | inst_env->slot_needed = 0; |
| 2332 | inst_env->xflag_found = 0; |
| 2333 | inst_env->prefix_found = 1; |
| 2334 | } |
| 2335 | |
| 2336 | /* Finds the destination for a branch with 8-bits offset. */ |
| 2337 | |
| 2338 | static void |
| 2339 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
| 2340 | { |
| 2341 | |
| 2342 | short offset; |
| 2343 | |
| 2344 | /* If we have a prefix or are in a delay slot it's bad. */ |
| 2345 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2346 | { |
| 2347 | inst_env->invalid = 1; |
| 2348 | return; |
| 2349 | } |
| 2350 | |
| 2351 | /* We have a branch, find out where the branch will land. */ |
| 2352 | offset = cris_get_branch_short_offset (inst); |
| 2353 | |
| 2354 | /* Check if the offset is signed. */ |
| 2355 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) |
| 2356 | { |
| 2357 | offset |= 0xFF00; |
| 2358 | } |
| 2359 | |
| 2360 | /* The offset ends with the sign bit, set it to zero. The address |
| 2361 | should always be word aligned. */ |
| 2362 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; |
| 2363 | |
| 2364 | inst_env->branch_found = 1; |
| 2365 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; |
| 2366 | |
| 2367 | inst_env->slot_needed = 1; |
| 2368 | inst_env->prefix_found = 0; |
| 2369 | inst_env->xflag_found = 0; |
| 2370 | inst_env->disable_interrupt = 1; |
| 2371 | } |
| 2372 | |
| 2373 | /* Finds the destination for a branch with 16-bits offset. */ |
| 2374 | |
| 2375 | static void |
| 2376 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
| 2377 | { |
| 2378 | short offset; |
| 2379 | |
| 2380 | /* If we have a prefix or is in a delay slot it's bad. */ |
| 2381 | if (inst_env->slot_needed || inst_env->prefix_found) |
| 2382 | { |
| 2383 | inst_env->invalid = 1; |
| 2384 | return; |
| 2385 | } |
| 2386 | |
| 2387 | /* We have a branch, find out the offset for the branch. */ |
| 2388 | offset = read_memory_integer (inst_env->reg[REG_PC], 2, |
| 2389 | inst_env->byte_order); |
| 2390 | |
| 2391 | /* The instruction is one word longer than normal, so add one word |
| 2392 | to the PC. */ |
| 2393 | inst_env->reg[REG_PC] += 2; |
| 2394 | |
| 2395 | inst_env->branch_found = 1; |
| 2396 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; |
| 2397 | |
| 2398 | |
| 2399 | inst_env->slot_needed = 1; |
| 2400 | inst_env->prefix_found = 0; |
| 2401 | inst_env->xflag_found = 0; |
| 2402 | inst_env->disable_interrupt = 1; |
| 2403 | } |
| 2404 | |
| 2405 | /* Handles the ABS instruction. */ |
| 2406 | |
| 2407 | static void |
| 2408 | abs_op (unsigned short inst, inst_env_type *inst_env) |
| 2409 | { |
| 2410 | |
| 2411 | long value; |
| 2412 | |
| 2413 | /* ABS can't have a prefix, so it's bad if it does. */ |
| 2414 | if (inst_env->prefix_found) |
| 2415 | { |
| 2416 | inst_env->invalid = 1; |
| 2417 | return; |
| 2418 | } |
| 2419 | |
| 2420 | /* Check if the operation affects the PC. */ |
| 2421 | if (cris_get_operand2 (inst) == REG_PC) |
| 2422 | { |
| 2423 | |
| 2424 | /* It's invalid to change to the PC if we are in a delay slot. */ |
| 2425 | if (inst_env->slot_needed) |
| 2426 | { |
| 2427 | inst_env->invalid = 1; |
| 2428 | return; |
| 2429 | } |
| 2430 | |
| 2431 | value = (long) inst_env->reg[REG_PC]; |
| 2432 | |
| 2433 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ |
| 2434 | if (value != SIGNED_DWORD_MASK) |
| 2435 | { |
| 2436 | value = -value; |
| 2437 | inst_env->reg[REG_PC] = (long) value; |
| 2438 | } |
| 2439 | } |
| 2440 | |
| 2441 | inst_env->slot_needed = 0; |
| 2442 | inst_env->prefix_found = 0; |
| 2443 | inst_env->xflag_found = 0; |
| 2444 | inst_env->disable_interrupt = 0; |
| 2445 | } |
| 2446 | |
| 2447 | /* Handles the ADDI instruction. */ |
| 2448 | |
| 2449 | static void |
| 2450 | addi_op (unsigned short inst, inst_env_type *inst_env) |
| 2451 | { |
| 2452 | /* It's invalid to have the PC as base register. And ADDI can't have |
| 2453 | a prefix. */ |
| 2454 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) |
| 2455 | { |
| 2456 | inst_env->invalid = 1; |
| 2457 | return; |
| 2458 | } |
| 2459 | |
| 2460 | inst_env->slot_needed = 0; |
| 2461 | inst_env->prefix_found = 0; |
| 2462 | inst_env->xflag_found = 0; |
| 2463 | inst_env->disable_interrupt = 0; |
| 2464 | } |
| 2465 | |
| 2466 | /* Handles the ASR instruction. */ |
| 2467 | |
| 2468 | static void |
| 2469 | asr_op (unsigned short inst, inst_env_type *inst_env) |
| 2470 | { |
| 2471 | int shift_steps; |
| 2472 | unsigned long value; |
| 2473 | unsigned long signed_extend_mask = 0; |
| 2474 | |
| 2475 | /* ASR can't have a prefix, so check that it doesn't. */ |
| 2476 | if (inst_env->prefix_found) |
| 2477 | { |
| 2478 | inst_env->invalid = 1; |
| 2479 | return; |
| 2480 | } |
| 2481 | |
| 2482 | /* Check if the PC is the target register. */ |
| 2483 | if (cris_get_operand2 (inst) == REG_PC) |
| 2484 | { |
| 2485 | /* It's invalid to change the PC in a delay slot. */ |
| 2486 | if (inst_env->slot_needed) |
| 2487 | { |
| 2488 | inst_env->invalid = 1; |
| 2489 | return; |
| 2490 | } |
| 2491 | /* Get the number of bits to shift. */ |
| 2492 | shift_steps |
| 2493 | = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); |
| 2494 | value = inst_env->reg[REG_PC]; |
| 2495 | |
| 2496 | /* Find out how many bits the operation should apply to. */ |
| 2497 | if (cris_get_size (inst) == INST_BYTE_SIZE) |
| 2498 | { |
| 2499 | if (value & SIGNED_BYTE_MASK) |
| 2500 | { |
| 2501 | signed_extend_mask = 0xFF; |
| 2502 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2503 | signed_extend_mask = ~signed_extend_mask; |
| 2504 | } |
| 2505 | value = value >> shift_steps; |
| 2506 | value |= signed_extend_mask; |
| 2507 | value &= 0xFF; |
| 2508 | inst_env->reg[REG_PC] &= 0xFFFFFF00; |
| 2509 | inst_env->reg[REG_PC] |= value; |
| 2510 | } |
| 2511 | else if (cris_get_size (inst) == INST_WORD_SIZE) |
| 2512 | { |
| 2513 | if (value & SIGNED_WORD_MASK) |
| 2514 | { |
| 2515 | signed_extend_mask = 0xFFFF; |
| 2516 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2517 | signed_extend_mask = ~signed_extend_mask; |
| 2518 | } |
| 2519 | value = value >> shift_steps; |
| 2520 | value |= signed_extend_mask; |
| 2521 | value &= 0xFFFF; |
| 2522 | inst_env->reg[REG_PC] &= 0xFFFF0000; |
| 2523 | inst_env->reg[REG_PC] |= value; |
| 2524 | } |
| 2525 | else if (cris_get_size (inst) == INST_DWORD_SIZE) |
| 2526 | { |
| 2527 | if (value & SIGNED_DWORD_MASK) |
| 2528 | { |
| 2529 | signed_extend_mask = 0xFFFFFFFF; |
| 2530 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2531 | signed_extend_mask = ~signed_extend_mask; |
| 2532 | } |
| 2533 | value = value >> shift_steps; |
| 2534 | value |= signed_extend_mask; |
| 2535 | inst_env->reg[REG_PC] = value; |
| 2536 | } |
| 2537 | } |
| 2538 | inst_env->slot_needed = 0; |
| 2539 | inst_env->prefix_found = 0; |
| 2540 | inst_env->xflag_found = 0; |
| 2541 | inst_env->disable_interrupt = 0; |
| 2542 | } |
| 2543 | |
| 2544 | /* Handles the ASRQ instruction. */ |
| 2545 | |
| 2546 | static void |
| 2547 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
| 2548 | { |
| 2549 | |
| 2550 | int shift_steps; |
| 2551 | unsigned long value; |
| 2552 | unsigned long signed_extend_mask = 0; |
| 2553 | |
| 2554 | /* ASRQ can't have a prefix, so check that it doesn't. */ |
| 2555 | if (inst_env->prefix_found) |
| 2556 | { |
| 2557 | inst_env->invalid = 1; |
| 2558 | return; |
| 2559 | } |
| 2560 | |
| 2561 | /* Check if the PC is the target register. */ |
| 2562 | if (cris_get_operand2 (inst) == REG_PC) |
| 2563 | { |
| 2564 | |
| 2565 | /* It's invalid to change the PC in a delay slot. */ |
| 2566 | if (inst_env->slot_needed) |
| 2567 | { |
| 2568 | inst_env->invalid = 1; |
| 2569 | return; |
| 2570 | } |
| 2571 | /* The shift size is given as a 5 bit quick value, i.e. we don't |
| 2572 | want the sign bit of the quick value. */ |
| 2573 | shift_steps = cris_get_asr_shift_steps (inst); |
| 2574 | value = inst_env->reg[REG_PC]; |
| 2575 | if (value & SIGNED_DWORD_MASK) |
| 2576 | { |
| 2577 | signed_extend_mask = 0xFFFFFFFF; |
| 2578 | signed_extend_mask = signed_extend_mask >> shift_steps; |
| 2579 | signed_extend_mask = ~signed_extend_mask; |
| 2580 | } |
| 2581 | value = value >> shift_steps; |
| 2582 | value |= signed_extend_mask; |
| 2583 | inst_env->reg[REG_PC] = value; |
| 2584 | } |
| 2585 | inst_env->slot_needed = 0; |
| 2586 | inst_env->prefix_found = 0; |
| 2587 | inst_env->xflag_found = 0; |
| 2588 | inst_env->disable_interrupt = 0; |
| 2589 | } |
| 2590 | |
| 2591 | /* Handles the AX, EI and SETF instruction. */ |
| 2592 | |
| 2593 | static void |
| 2594 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
| 2595 | { |
| 2596 | if (inst_env->prefix_found) |
| 2597 | { |
| 2598 | inst_env->invalid = 1; |
| 2599 | return; |
| 2600 | } |
| 2601 | /* Check if the instruction is setting the X flag. */ |
| 2602 | if (cris_is_xflag_bit_on (inst)) |
| 2603 | { |
| 2604 | inst_env->xflag_found = 1; |
| 2605 | } |
| 2606 | else |
| 2607 | { |
| 2608 | inst_env->xflag_found = 0; |
| 2609 | } |
| 2610 | inst_env->slot_needed = 0; |
| 2611 | inst_env->prefix_found = 0; |
| 2612 | inst_env->disable_interrupt = 1; |
| 2613 | } |
| 2614 | |
| 2615 | /* Checks if the instruction is in assign mode. If so, it updates the assign |
| 2616 | register. Note that check_assign assumes that the caller has checked that |
| 2617 | there is a prefix to this instruction. The mode check depends on this. */ |
| 2618 | |
| 2619 | static void |
| 2620 | check_assign (unsigned short inst, inst_env_type *inst_env) |
| 2621 | { |
| 2622 | /* Check if it's an assign addressing mode. */ |
| 2623 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 2624 | { |
| 2625 | /* Assign the prefix value to operand 1. */ |
| 2626 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; |
| 2627 | } |
| 2628 | } |
| 2629 | |
| 2630 | /* Handles the 2-operand BOUND instruction. */ |
| 2631 | |
| 2632 | static void |
| 2633 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
| 2634 | { |
| 2635 | /* It's invalid to have the PC as the index operand. */ |
| 2636 | if (cris_get_operand2 (inst) == REG_PC) |
| 2637 | { |
| 2638 | inst_env->invalid = 1; |
| 2639 | return; |
| 2640 | } |
| 2641 | /* Check if we have a prefix. */ |
| 2642 | if (inst_env->prefix_found) |
| 2643 | { |
| 2644 | check_assign (inst, inst_env); |
| 2645 | } |
| 2646 | /* Check if this is an autoincrement mode. */ |
| 2647 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2648 | { |
| 2649 | /* It's invalid to change the PC in a delay slot. */ |
| 2650 | if (inst_env->slot_needed) |
| 2651 | { |
| 2652 | inst_env->invalid = 1; |
| 2653 | return; |
| 2654 | } |
| 2655 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 2656 | } |
| 2657 | inst_env->slot_needed = 0; |
| 2658 | inst_env->prefix_found = 0; |
| 2659 | inst_env->xflag_found = 0; |
| 2660 | inst_env->disable_interrupt = 0; |
| 2661 | } |
| 2662 | |
| 2663 | /* Handles the 3-operand BOUND instruction. */ |
| 2664 | |
| 2665 | static void |
| 2666 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
| 2667 | { |
| 2668 | /* It's an error if we haven't got a prefix. And it's also an error |
| 2669 | if the PC is the destination register. */ |
| 2670 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) |
| 2671 | { |
| 2672 | inst_env->invalid = 1; |
| 2673 | return; |
| 2674 | } |
| 2675 | inst_env->slot_needed = 0; |
| 2676 | inst_env->prefix_found = 0; |
| 2677 | inst_env->xflag_found = 0; |
| 2678 | inst_env->disable_interrupt = 0; |
| 2679 | } |
| 2680 | |
| 2681 | /* Clears the status flags in inst_env. */ |
| 2682 | |
| 2683 | static void |
| 2684 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
| 2685 | { |
| 2686 | /* It's an error if we have got a prefix. */ |
| 2687 | if (inst_env->prefix_found) |
| 2688 | { |
| 2689 | inst_env->invalid = 1; |
| 2690 | return; |
| 2691 | } |
| 2692 | |
| 2693 | inst_env->slot_needed = 0; |
| 2694 | inst_env->prefix_found = 0; |
| 2695 | inst_env->xflag_found = 0; |
| 2696 | inst_env->disable_interrupt = 0; |
| 2697 | } |
| 2698 | |
| 2699 | /* Clears the status flags in inst_env. */ |
| 2700 | |
| 2701 | static void |
| 2702 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
| 2703 | { |
| 2704 | /* It's an error if we have got a prefix. */ |
| 2705 | if (inst_env->prefix_found) |
| 2706 | { |
| 2707 | inst_env->invalid = 1; |
| 2708 | return; |
| 2709 | } |
| 2710 | |
| 2711 | inst_env->slot_needed = 0; |
| 2712 | inst_env->prefix_found = 0; |
| 2713 | inst_env->xflag_found = 0; |
| 2714 | inst_env->disable_interrupt = 1; |
| 2715 | } |
| 2716 | |
| 2717 | /* Handles the CLEAR instruction if it's in register mode. */ |
| 2718 | |
| 2719 | static void |
| 2720 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
| 2721 | { |
| 2722 | /* Check if the target is the PC. */ |
| 2723 | if (cris_get_operand2 (inst) == REG_PC) |
| 2724 | { |
| 2725 | /* The instruction will clear the instruction's size bits. */ |
| 2726 | int clear_size = cris_get_clear_size (inst); |
| 2727 | if (clear_size == INST_BYTE_SIZE) |
| 2728 | { |
| 2729 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; |
| 2730 | } |
| 2731 | if (clear_size == INST_WORD_SIZE) |
| 2732 | { |
| 2733 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; |
| 2734 | } |
| 2735 | if (clear_size == INST_DWORD_SIZE) |
| 2736 | { |
| 2737 | inst_env->delay_slot_pc = 0x0; |
| 2738 | } |
| 2739 | /* The jump will be delayed with one delay slot. So we need a delay |
| 2740 | slot. */ |
| 2741 | inst_env->slot_needed = 1; |
| 2742 | inst_env->delay_slot_pc_active = 1; |
| 2743 | } |
| 2744 | else |
| 2745 | { |
| 2746 | /* The PC will not change => no delay slot. */ |
| 2747 | inst_env->slot_needed = 0; |
| 2748 | } |
| 2749 | inst_env->prefix_found = 0; |
| 2750 | inst_env->xflag_found = 0; |
| 2751 | inst_env->disable_interrupt = 0; |
| 2752 | } |
| 2753 | |
| 2754 | /* Handles the TEST instruction if it's in register mode. */ |
| 2755 | |
| 2756 | static void |
| 2757 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
| 2758 | { |
| 2759 | /* It's an error if we have got a prefix. */ |
| 2760 | if (inst_env->prefix_found) |
| 2761 | { |
| 2762 | inst_env->invalid = 1; |
| 2763 | return; |
| 2764 | } |
| 2765 | inst_env->slot_needed = 0; |
| 2766 | inst_env->prefix_found = 0; |
| 2767 | inst_env->xflag_found = 0; |
| 2768 | inst_env->disable_interrupt = 0; |
| 2769 | |
| 2770 | } |
| 2771 | |
| 2772 | /* Handles the CLEAR and TEST instruction if the instruction isn't |
| 2773 | in register mode. */ |
| 2774 | |
| 2775 | static void |
| 2776 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
| 2777 | { |
| 2778 | /* Check if we are in a prefix mode. */ |
| 2779 | if (inst_env->prefix_found) |
| 2780 | { |
| 2781 | /* The only way the PC can change is if this instruction is in |
| 2782 | assign addressing mode. */ |
| 2783 | check_assign (inst, inst_env); |
| 2784 | } |
| 2785 | /* Indirect mode can't change the PC so just check if the mode is |
| 2786 | autoincrement. */ |
| 2787 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2788 | { |
| 2789 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
| 2790 | } |
| 2791 | inst_env->slot_needed = 0; |
| 2792 | inst_env->prefix_found = 0; |
| 2793 | inst_env->xflag_found = 0; |
| 2794 | inst_env->disable_interrupt = 0; |
| 2795 | } |
| 2796 | |
| 2797 | /* Checks that the PC isn't the destination register or the instructions has |
| 2798 | a prefix. */ |
| 2799 | |
| 2800 | static void |
| 2801 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
| 2802 | { |
| 2803 | /* It's invalid to have the PC as the destination. The instruction can't |
| 2804 | have a prefix. */ |
| 2805 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) |
| 2806 | { |
| 2807 | inst_env->invalid = 1; |
| 2808 | return; |
| 2809 | } |
| 2810 | |
| 2811 | inst_env->slot_needed = 0; |
| 2812 | inst_env->prefix_found = 0; |
| 2813 | inst_env->xflag_found = 0; |
| 2814 | inst_env->disable_interrupt = 0; |
| 2815 | } |
| 2816 | |
| 2817 | /* Checks that the instruction doesn't have a prefix. */ |
| 2818 | |
| 2819 | static void |
| 2820 | break_op (unsigned short inst, inst_env_type *inst_env) |
| 2821 | { |
| 2822 | /* The instruction can't have a prefix. */ |
| 2823 | if (inst_env->prefix_found) |
| 2824 | { |
| 2825 | inst_env->invalid = 1; |
| 2826 | return; |
| 2827 | } |
| 2828 | |
| 2829 | inst_env->slot_needed = 0; |
| 2830 | inst_env->prefix_found = 0; |
| 2831 | inst_env->xflag_found = 0; |
| 2832 | inst_env->disable_interrupt = 1; |
| 2833 | } |
| 2834 | |
| 2835 | /* Checks that the PC isn't the destination register and that the instruction |
| 2836 | doesn't have a prefix. */ |
| 2837 | |
| 2838 | static void |
| 2839 | scc_op (unsigned short inst, inst_env_type *inst_env) |
| 2840 | { |
| 2841 | /* It's invalid to have the PC as the destination. The instruction can't |
| 2842 | have a prefix. */ |
| 2843 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) |
| 2844 | { |
| 2845 | inst_env->invalid = 1; |
| 2846 | return; |
| 2847 | } |
| 2848 | |
| 2849 | inst_env->slot_needed = 0; |
| 2850 | inst_env->prefix_found = 0; |
| 2851 | inst_env->xflag_found = 0; |
| 2852 | inst_env->disable_interrupt = 1; |
| 2853 | } |
| 2854 | |
| 2855 | /* Handles the register mode JUMP instruction. */ |
| 2856 | |
| 2857 | static void |
| 2858 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
| 2859 | { |
| 2860 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so |
| 2861 | you can't have a prefix. */ |
| 2862 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) |
| 2863 | { |
| 2864 | inst_env->invalid = 1; |
| 2865 | return; |
| 2866 | } |
| 2867 | |
| 2868 | /* Just change the PC. */ |
| 2869 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; |
| 2870 | inst_env->slot_needed = 0; |
| 2871 | inst_env->prefix_found = 0; |
| 2872 | inst_env->xflag_found = 0; |
| 2873 | inst_env->disable_interrupt = 1; |
| 2874 | } |
| 2875 | |
| 2876 | /* Handles the JUMP instruction for all modes except register. */ |
| 2877 | |
| 2878 | static void |
| 2879 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
| 2880 | { |
| 2881 | unsigned long newpc; |
| 2882 | CORE_ADDR address; |
| 2883 | |
| 2884 | /* It's invalid to do a JUMP in a delay slot. */ |
| 2885 | if (inst_env->slot_needed) |
| 2886 | { |
| 2887 | inst_env->invalid = 1; |
| 2888 | } |
| 2889 | else |
| 2890 | { |
| 2891 | /* Check if we have a prefix. */ |
| 2892 | if (inst_env->prefix_found) |
| 2893 | { |
| 2894 | check_assign (inst, inst_env); |
| 2895 | |
| 2896 | /* Get the new value for the PC. */ |
| 2897 | newpc = |
| 2898 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, |
| 2899 | 4, inst_env->byte_order); |
| 2900 | } |
| 2901 | else |
| 2902 | { |
| 2903 | /* Get the new value for the PC. */ |
| 2904 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; |
| 2905 | newpc = read_memory_unsigned_integer (address, |
| 2906 | 4, inst_env->byte_order); |
| 2907 | |
| 2908 | /* Check if we should increment a register. */ |
| 2909 | if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2910 | { |
| 2911 | inst_env->reg[cris_get_operand1 (inst)] += 4; |
| 2912 | } |
| 2913 | } |
| 2914 | inst_env->reg[REG_PC] = newpc; |
| 2915 | } |
| 2916 | inst_env->slot_needed = 0; |
| 2917 | inst_env->prefix_found = 0; |
| 2918 | inst_env->xflag_found = 0; |
| 2919 | inst_env->disable_interrupt = 1; |
| 2920 | } |
| 2921 | |
| 2922 | /* Handles moves to special registers (aka P-register) for all modes. */ |
| 2923 | |
| 2924 | static void |
| 2925 | move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
| 2926 | inst_env_type *inst_env) |
| 2927 | { |
| 2928 | if (inst_env->prefix_found) |
| 2929 | { |
| 2930 | /* The instruction has a prefix that means we are only interested if |
| 2931 | the instruction is in assign mode. */ |
| 2932 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 2933 | { |
| 2934 | /* The prefix handles the problem if we are in a delay slot. */ |
| 2935 | if (cris_get_operand1 (inst) == REG_PC) |
| 2936 | { |
| 2937 | /* Just take care of the assign. */ |
| 2938 | check_assign (inst, inst_env); |
| 2939 | } |
| 2940 | } |
| 2941 | } |
| 2942 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 2943 | { |
| 2944 | /* The instruction doesn't have a prefix, the only case left that we |
| 2945 | are interested in is the autoincrement mode. */ |
| 2946 | if (cris_get_operand1 (inst) == REG_PC) |
| 2947 | { |
| 2948 | /* If the PC is to be incremented it's invalid to be in a |
| 2949 | delay slot. */ |
| 2950 | if (inst_env->slot_needed) |
| 2951 | { |
| 2952 | inst_env->invalid = 1; |
| 2953 | return; |
| 2954 | } |
| 2955 | |
| 2956 | /* The increment depends on the size of the special register. */ |
| 2957 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
| 2958 | { |
| 2959 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); |
| 2960 | } |
| 2961 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
| 2962 | { |
| 2963 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); |
| 2964 | } |
| 2965 | else |
| 2966 | { |
| 2967 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); |
| 2968 | } |
| 2969 | } |
| 2970 | } |
| 2971 | inst_env->slot_needed = 0; |
| 2972 | inst_env->prefix_found = 0; |
| 2973 | inst_env->xflag_found = 0; |
| 2974 | inst_env->disable_interrupt = 1; |
| 2975 | } |
| 2976 | |
| 2977 | /* Handles moves from special registers (aka P-register) for all modes |
| 2978 | except register. */ |
| 2979 | |
| 2980 | static void |
| 2981 | none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
| 2982 | inst_env_type *inst_env) |
| 2983 | { |
| 2984 | if (inst_env->prefix_found) |
| 2985 | { |
| 2986 | /* The instruction has a prefix that means we are only interested if |
| 2987 | the instruction is in assign mode. */ |
| 2988 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 2989 | { |
| 2990 | /* The prefix handles the problem if we are in a delay slot. */ |
| 2991 | if (cris_get_operand1 (inst) == REG_PC) |
| 2992 | { |
| 2993 | /* Just take care of the assign. */ |
| 2994 | check_assign (inst, inst_env); |
| 2995 | } |
| 2996 | } |
| 2997 | } |
| 2998 | /* The instruction doesn't have a prefix, the only case left that we |
| 2999 | are interested in is the autoincrement mode. */ |
| 3000 | else if (cris_get_mode (inst) == AUTOINC_MODE) |
| 3001 | { |
| 3002 | if (cris_get_operand1 (inst) == REG_PC) |
| 3003 | { |
| 3004 | /* If the PC is to be incremented it's invalid to be in a |
| 3005 | delay slot. */ |
| 3006 | if (inst_env->slot_needed) |
| 3007 | { |
| 3008 | inst_env->invalid = 1; |
| 3009 | return; |
| 3010 | } |
| 3011 | |
| 3012 | /* The increment depends on the size of the special register. */ |
| 3013 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) |
| 3014 | { |
| 3015 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); |
| 3016 | } |
| 3017 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) |
| 3018 | { |
| 3019 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); |
| 3020 | } |
| 3021 | else |
| 3022 | { |
| 3023 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); |
| 3024 | } |
| 3025 | } |
| 3026 | } |
| 3027 | inst_env->slot_needed = 0; |
| 3028 | inst_env->prefix_found = 0; |
| 3029 | inst_env->xflag_found = 0; |
| 3030 | inst_env->disable_interrupt = 1; |
| 3031 | } |
| 3032 | |
| 3033 | /* Handles moves from special registers (aka P-register) when the mode |
| 3034 | is register. */ |
| 3035 | |
| 3036 | static void |
| 3037 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
| 3038 | { |
| 3039 | /* Register mode move from special register can't have a prefix. */ |
| 3040 | if (inst_env->prefix_found) |
| 3041 | { |
| 3042 | inst_env->invalid = 1; |
| 3043 | return; |
| 3044 | } |
| 3045 | |
| 3046 | if (cris_get_operand1 (inst) == REG_PC) |
| 3047 | { |
| 3048 | /* It's invalid to change the PC in a delay slot. */ |
| 3049 | if (inst_env->slot_needed) |
| 3050 | { |
| 3051 | inst_env->invalid = 1; |
| 3052 | return; |
| 3053 | } |
| 3054 | /* The destination is the PC, the jump will have a delay slot. */ |
| 3055 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; |
| 3056 | inst_env->slot_needed = 1; |
| 3057 | inst_env->delay_slot_pc_active = 1; |
| 3058 | } |
| 3059 | else |
| 3060 | { |
| 3061 | /* If the destination isn't PC, there will be no jump. */ |
| 3062 | inst_env->slot_needed = 0; |
| 3063 | } |
| 3064 | inst_env->prefix_found = 0; |
| 3065 | inst_env->xflag_found = 0; |
| 3066 | inst_env->disable_interrupt = 1; |
| 3067 | } |
| 3068 | |
| 3069 | /* Handles the MOVEM from memory to general register instruction. */ |
| 3070 | |
| 3071 | static void |
| 3072 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
| 3073 | { |
| 3074 | if (inst_env->prefix_found) |
| 3075 | { |
| 3076 | /* The prefix handles the problem if we are in a delay slot. Is the |
| 3077 | MOVEM instruction going to change the PC? */ |
| 3078 | if (cris_get_operand2 (inst) >= REG_PC) |
| 3079 | { |
| 3080 | inst_env->reg[REG_PC] = |
| 3081 | read_memory_unsigned_integer (inst_env->prefix_value, |
| 3082 | 4, inst_env->byte_order); |
| 3083 | } |
| 3084 | /* The assign value is the value after the increment. Normally, the |
| 3085 | assign value is the value before the increment. */ |
| 3086 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3087 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) |
| 3088 | { |
| 3089 | inst_env->reg[REG_PC] = inst_env->prefix_value; |
| 3090 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 3091 | } |
| 3092 | } |
| 3093 | else |
| 3094 | { |
| 3095 | /* Is the MOVEM instruction going to change the PC? */ |
| 3096 | if (cris_get_operand2 (inst) == REG_PC) |
| 3097 | { |
| 3098 | /* It's invalid to change the PC in a delay slot. */ |
| 3099 | if (inst_env->slot_needed) |
| 3100 | { |
| 3101 | inst_env->invalid = 1; |
| 3102 | return; |
| 3103 | } |
| 3104 | inst_env->reg[REG_PC] = |
| 3105 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], |
| 3106 | 4, inst_env->byte_order); |
| 3107 | } |
| 3108 | /* The increment is not depending on the size, instead it's depending |
| 3109 | on the number of registers loaded from memory. */ |
| 3110 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3111 | && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 3112 | { |
| 3113 | /* It's invalid to change the PC in a delay slot. */ |
| 3114 | if (inst_env->slot_needed) |
| 3115 | { |
| 3116 | inst_env->invalid = 1; |
| 3117 | return; |
| 3118 | } |
| 3119 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 3120 | } |
| 3121 | } |
| 3122 | inst_env->slot_needed = 0; |
| 3123 | inst_env->prefix_found = 0; |
| 3124 | inst_env->xflag_found = 0; |
| 3125 | inst_env->disable_interrupt = 0; |
| 3126 | } |
| 3127 | |
| 3128 | /* Handles the MOVEM to memory from general register instruction. */ |
| 3129 | |
| 3130 | static void |
| 3131 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
| 3132 | { |
| 3133 | if (inst_env->prefix_found) |
| 3134 | { |
| 3135 | /* The assign value is the value after the increment. Normally, the |
| 3136 | assign value is the value before the increment. */ |
| 3137 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3138 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) |
| 3139 | { |
| 3140 | /* The prefix handles the problem if we are in a delay slot. */ |
| 3141 | inst_env->reg[REG_PC] = inst_env->prefix_value; |
| 3142 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 3143 | } |
| 3144 | } |
| 3145 | else |
| 3146 | { |
| 3147 | /* The increment is not depending on the size, instead it's depending |
| 3148 | on the number of registers loaded to memory. */ |
| 3149 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3150 | && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 3151 | { |
| 3152 | /* It's invalid to change the PC in a delay slot. */ |
| 3153 | if (inst_env->slot_needed) |
| 3154 | { |
| 3155 | inst_env->invalid = 1; |
| 3156 | return; |
| 3157 | } |
| 3158 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); |
| 3159 | } |
| 3160 | } |
| 3161 | inst_env->slot_needed = 0; |
| 3162 | inst_env->prefix_found = 0; |
| 3163 | inst_env->xflag_found = 0; |
| 3164 | inst_env->disable_interrupt = 0; |
| 3165 | } |
| 3166 | |
| 3167 | /* Handles the intructions that's not yet implemented, by setting |
| 3168 | inst_env->invalid to true. */ |
| 3169 | |
| 3170 | static void |
| 3171 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
| 3172 | { |
| 3173 | inst_env->invalid = 1; |
| 3174 | } |
| 3175 | |
| 3176 | /* Handles the XOR instruction. */ |
| 3177 | |
| 3178 | static void |
| 3179 | xor_op (unsigned short inst, inst_env_type *inst_env) |
| 3180 | { |
| 3181 | /* XOR can't have a prefix. */ |
| 3182 | if (inst_env->prefix_found) |
| 3183 | { |
| 3184 | inst_env->invalid = 1; |
| 3185 | return; |
| 3186 | } |
| 3187 | |
| 3188 | /* Check if the PC is the target. */ |
| 3189 | if (cris_get_operand2 (inst) == REG_PC) |
| 3190 | { |
| 3191 | /* It's invalid to change the PC in a delay slot. */ |
| 3192 | if (inst_env->slot_needed) |
| 3193 | { |
| 3194 | inst_env->invalid = 1; |
| 3195 | return; |
| 3196 | } |
| 3197 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; |
| 3198 | } |
| 3199 | inst_env->slot_needed = 0; |
| 3200 | inst_env->prefix_found = 0; |
| 3201 | inst_env->xflag_found = 0; |
| 3202 | inst_env->disable_interrupt = 0; |
| 3203 | } |
| 3204 | |
| 3205 | /* Handles the MULS instruction. */ |
| 3206 | |
| 3207 | static void |
| 3208 | muls_op (unsigned short inst, inst_env_type *inst_env) |
| 3209 | { |
| 3210 | /* MULS/U can't have a prefix. */ |
| 3211 | if (inst_env->prefix_found) |
| 3212 | { |
| 3213 | inst_env->invalid = 1; |
| 3214 | return; |
| 3215 | } |
| 3216 | |
| 3217 | /* Consider it invalid if the PC is the target. */ |
| 3218 | if (cris_get_operand2 (inst) == REG_PC) |
| 3219 | { |
| 3220 | inst_env->invalid = 1; |
| 3221 | return; |
| 3222 | } |
| 3223 | inst_env->slot_needed = 0; |
| 3224 | inst_env->prefix_found = 0; |
| 3225 | inst_env->xflag_found = 0; |
| 3226 | inst_env->disable_interrupt = 0; |
| 3227 | } |
| 3228 | |
| 3229 | /* Handles the MULU instruction. */ |
| 3230 | |
| 3231 | static void |
| 3232 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
| 3233 | { |
| 3234 | /* MULS/U can't have a prefix. */ |
| 3235 | if (inst_env->prefix_found) |
| 3236 | { |
| 3237 | inst_env->invalid = 1; |
| 3238 | return; |
| 3239 | } |
| 3240 | |
| 3241 | /* Consider it invalid if the PC is the target. */ |
| 3242 | if (cris_get_operand2 (inst) == REG_PC) |
| 3243 | { |
| 3244 | inst_env->invalid = 1; |
| 3245 | return; |
| 3246 | } |
| 3247 | inst_env->slot_needed = 0; |
| 3248 | inst_env->prefix_found = 0; |
| 3249 | inst_env->xflag_found = 0; |
| 3250 | inst_env->disable_interrupt = 0; |
| 3251 | } |
| 3252 | |
| 3253 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. |
| 3254 | The MOVE instruction is the move from source to register. */ |
| 3255 | |
| 3256 | static void |
| 3257 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
| 3258 | unsigned long source1, unsigned long source2) |
| 3259 | { |
| 3260 | unsigned long pc_mask; |
| 3261 | unsigned long operation_mask; |
| 3262 | |
| 3263 | /* Find out how many bits the operation should apply to. */ |
| 3264 | if (cris_get_size (inst) == INST_BYTE_SIZE) |
| 3265 | { |
| 3266 | pc_mask = 0xFFFFFF00; |
| 3267 | operation_mask = 0xFF; |
| 3268 | } |
| 3269 | else if (cris_get_size (inst) == INST_WORD_SIZE) |
| 3270 | { |
| 3271 | pc_mask = 0xFFFF0000; |
| 3272 | operation_mask = 0xFFFF; |
| 3273 | } |
| 3274 | else if (cris_get_size (inst) == INST_DWORD_SIZE) |
| 3275 | { |
| 3276 | pc_mask = 0x0; |
| 3277 | operation_mask = 0xFFFFFFFF; |
| 3278 | } |
| 3279 | else |
| 3280 | { |
| 3281 | /* The size is out of range. */ |
| 3282 | inst_env->invalid = 1; |
| 3283 | return; |
| 3284 | } |
| 3285 | |
| 3286 | /* The instruction just works on uw_operation_mask bits. */ |
| 3287 | source2 &= operation_mask; |
| 3288 | source1 &= operation_mask; |
| 3289 | |
| 3290 | /* Now calculate the result. The opcode's 3 first bits separates |
| 3291 | the different actions. */ |
| 3292 | switch (cris_get_opcode (inst) & 7) |
| 3293 | { |
| 3294 | case 0: /* add */ |
| 3295 | source1 += source2; |
| 3296 | break; |
| 3297 | |
| 3298 | case 1: /* move */ |
| 3299 | source1 = source2; |
| 3300 | break; |
| 3301 | |
| 3302 | case 2: /* subtract */ |
| 3303 | source1 -= source2; |
| 3304 | break; |
| 3305 | |
| 3306 | case 3: /* compare */ |
| 3307 | break; |
| 3308 | |
| 3309 | case 4: /* and */ |
| 3310 | source1 &= source2; |
| 3311 | break; |
| 3312 | |
| 3313 | case 5: /* or */ |
| 3314 | source1 |= source2; |
| 3315 | break; |
| 3316 | |
| 3317 | default: |
| 3318 | inst_env->invalid = 1; |
| 3319 | return; |
| 3320 | |
| 3321 | break; |
| 3322 | } |
| 3323 | |
| 3324 | /* Make sure that the result doesn't contain more than the instruction |
| 3325 | size bits. */ |
| 3326 | source2 &= operation_mask; |
| 3327 | |
| 3328 | /* Calculate the new breakpoint address. */ |
| 3329 | inst_env->reg[REG_PC] &= pc_mask; |
| 3330 | inst_env->reg[REG_PC] |= source1; |
| 3331 | |
| 3332 | } |
| 3333 | |
| 3334 | /* Extends the value from either byte or word size to a dword. If the mode |
| 3335 | is zero extend then the value is extended with zero. If instead the mode |
| 3336 | is signed extend the sign bit of the value is taken into consideration. */ |
| 3337 | |
| 3338 | static unsigned long |
| 3339 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
| 3340 | { |
| 3341 | /* The size can be either byte or word, check which one it is. |
| 3342 | Don't check the highest bit, it's indicating if it's a zero |
| 3343 | or sign extend. */ |
| 3344 | if (cris_get_size (*inst) & INST_WORD_SIZE) |
| 3345 | { |
| 3346 | /* Word size. */ |
| 3347 | value &= 0xFFFF; |
| 3348 | |
| 3349 | /* Check if the instruction is signed extend. If so, check if value has |
| 3350 | the sign bit on. */ |
| 3351 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) |
| 3352 | { |
| 3353 | value |= SIGNED_WORD_EXTEND_MASK; |
| 3354 | } |
| 3355 | } |
| 3356 | else |
| 3357 | { |
| 3358 | /* Byte size. */ |
| 3359 | value &= 0xFF; |
| 3360 | |
| 3361 | /* Check if the instruction is signed extend. If so, check if value has |
| 3362 | the sign bit on. */ |
| 3363 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) |
| 3364 | { |
| 3365 | value |= SIGNED_BYTE_EXTEND_MASK; |
| 3366 | } |
| 3367 | } |
| 3368 | /* The size should now be dword. */ |
| 3369 | cris_set_size_to_dword (inst); |
| 3370 | return value; |
| 3371 | } |
| 3372 | |
| 3373 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE |
| 3374 | instruction. The MOVE instruction is the move from source to register. */ |
| 3375 | |
| 3376 | static void |
| 3377 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
| 3378 | inst_env_type *inst_env) |
| 3379 | { |
| 3380 | unsigned long operand1; |
| 3381 | unsigned long operand2; |
| 3382 | |
| 3383 | /* It's invalid to have a prefix to the instruction. This is a register |
| 3384 | mode instruction and can't have a prefix. */ |
| 3385 | if (inst_env->prefix_found) |
| 3386 | { |
| 3387 | inst_env->invalid = 1; |
| 3388 | return; |
| 3389 | } |
| 3390 | /* Check if the instruction has PC as its target. */ |
| 3391 | if (cris_get_operand2 (inst) == REG_PC) |
| 3392 | { |
| 3393 | if (inst_env->slot_needed) |
| 3394 | { |
| 3395 | inst_env->invalid = 1; |
| 3396 | return; |
| 3397 | } |
| 3398 | /* The instruction has the PC as its target register. */ |
| 3399 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
| 3400 | operand2 = inst_env->reg[REG_PC]; |
| 3401 | |
| 3402 | /* Check if it's a extend, signed or zero instruction. */ |
| 3403 | if (cris_get_opcode (inst) < 4) |
| 3404 | { |
| 3405 | operand1 = do_sign_or_zero_extend (operand1, &inst); |
| 3406 | } |
| 3407 | /* Calculate the PC value after the instruction, i.e. where the |
| 3408 | breakpoint should be. The order of the udw_operands is vital. */ |
| 3409 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
| 3410 | } |
| 3411 | inst_env->slot_needed = 0; |
| 3412 | inst_env->prefix_found = 0; |
| 3413 | inst_env->xflag_found = 0; |
| 3414 | inst_env->disable_interrupt = 0; |
| 3415 | } |
| 3416 | |
| 3417 | /* Returns the data contained at address. The size of the data is derived from |
| 3418 | the size of the operation. If the instruction is a zero or signed |
| 3419 | extend instruction, the size field is changed in instruction. */ |
| 3420 | |
| 3421 | static unsigned long |
| 3422 | get_data_from_address (unsigned short *inst, CORE_ADDR address, |
| 3423 | enum bfd_endian byte_order) |
| 3424 | { |
| 3425 | int size = cris_get_size (*inst); |
| 3426 | unsigned long value; |
| 3427 | |
| 3428 | /* If it's an extend instruction we don't want the signed extend bit, |
| 3429 | because it influences the size. */ |
| 3430 | if (cris_get_opcode (*inst) < 4) |
| 3431 | { |
| 3432 | size &= ~SIGNED_EXTEND_BIT_MASK; |
| 3433 | } |
| 3434 | /* Is there a need for checking the size? Size should contain the number of |
| 3435 | bytes to read. */ |
| 3436 | size = 1 << size; |
| 3437 | value = read_memory_unsigned_integer (address, size, byte_order); |
| 3438 | |
| 3439 | /* Check if it's an extend, signed or zero instruction. */ |
| 3440 | if (cris_get_opcode (*inst) < 4) |
| 3441 | { |
| 3442 | value = do_sign_or_zero_extend (value, inst); |
| 3443 | } |
| 3444 | return value; |
| 3445 | } |
| 3446 | |
| 3447 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE |
| 3448 | instructions. The MOVE instruction is the move from source to register. */ |
| 3449 | |
| 3450 | static void |
| 3451 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
| 3452 | inst_env_type *inst_env) |
| 3453 | { |
| 3454 | unsigned long operand2; |
| 3455 | unsigned long operand3; |
| 3456 | |
| 3457 | check_assign (inst, inst_env); |
| 3458 | if (cris_get_operand2 (inst) == REG_PC) |
| 3459 | { |
| 3460 | operand2 = inst_env->reg[REG_PC]; |
| 3461 | |
| 3462 | /* Get the value of the third operand. */ |
| 3463 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
| 3464 | inst_env->byte_order); |
| 3465 | |
| 3466 | /* Calculate the PC value after the instruction, i.e. where the |
| 3467 | breakpoint should be. The order of the udw_operands is vital. */ |
| 3468 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
| 3469 | } |
| 3470 | inst_env->slot_needed = 0; |
| 3471 | inst_env->prefix_found = 0; |
| 3472 | inst_env->xflag_found = 0; |
| 3473 | inst_env->disable_interrupt = 0; |
| 3474 | } |
| 3475 | |
| 3476 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and |
| 3477 | OR instructions. Note that for this to work as expected, the calling |
| 3478 | function must have made sure that there is a prefix to this instruction. */ |
| 3479 | |
| 3480 | static void |
| 3481 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
| 3482 | inst_env_type *inst_env) |
| 3483 | { |
| 3484 | unsigned long operand2; |
| 3485 | unsigned long operand3; |
| 3486 | |
| 3487 | if (cris_get_operand1 (inst) == REG_PC) |
| 3488 | { |
| 3489 | /* The PC will be changed by the instruction. */ |
| 3490 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; |
| 3491 | |
| 3492 | /* Get the value of the third operand. */ |
| 3493 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
| 3494 | inst_env->byte_order); |
| 3495 | |
| 3496 | /* Calculate the PC value after the instruction, i.e. where the |
| 3497 | breakpoint should be. */ |
| 3498 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
| 3499 | } |
| 3500 | inst_env->slot_needed = 0; |
| 3501 | inst_env->prefix_found = 0; |
| 3502 | inst_env->xflag_found = 0; |
| 3503 | inst_env->disable_interrupt = 0; |
| 3504 | } |
| 3505 | |
| 3506 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE |
| 3507 | instructions. The MOVE instruction is the move from source to register. */ |
| 3508 | |
| 3509 | static void |
| 3510 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
| 3511 | inst_env_type *inst_env) |
| 3512 | { |
| 3513 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) |
| 3514 | { |
| 3515 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, |
| 3516 | SUB, AND or OR something weird is going on (if everything works these |
| 3517 | instructions should end up in the three operand version). */ |
| 3518 | inst_env->invalid = 1; |
| 3519 | return; |
| 3520 | } |
| 3521 | else |
| 3522 | { |
| 3523 | /* three_operand_add_sub_cmp_and_or does the same as we should do here |
| 3524 | so use it. */ |
| 3525 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); |
| 3526 | } |
| 3527 | inst_env->slot_needed = 0; |
| 3528 | inst_env->prefix_found = 0; |
| 3529 | inst_env->xflag_found = 0; |
| 3530 | inst_env->disable_interrupt = 0; |
| 3531 | } |
| 3532 | |
| 3533 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, |
| 3534 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from |
| 3535 | source to register. */ |
| 3536 | |
| 3537 | static void |
| 3538 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
| 3539 | inst_env_type *inst_env) |
| 3540 | { |
| 3541 | unsigned long operand1; |
| 3542 | unsigned long operand2; |
| 3543 | unsigned long operand3; |
| 3544 | int size; |
| 3545 | |
| 3546 | /* The instruction is either an indirect or autoincrement addressing mode. |
| 3547 | Check if the destination register is the PC. */ |
| 3548 | if (cris_get_operand2 (inst) == REG_PC) |
| 3549 | { |
| 3550 | /* Must be done here, get_data_from_address may change the size |
| 3551 | field. */ |
| 3552 | size = cris_get_size (inst); |
| 3553 | operand2 = inst_env->reg[REG_PC]; |
| 3554 | |
| 3555 | /* Get the value of the third operand, i.e. the indirect operand. */ |
| 3556 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
| 3557 | operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order); |
| 3558 | |
| 3559 | /* Calculate the PC value after the instruction, i.e. where the |
| 3560 | breakpoint should be. The order of the udw_operands is vital. */ |
| 3561 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
| 3562 | } |
| 3563 | /* If this is an autoincrement addressing mode, check if the increment |
| 3564 | changes the PC. */ |
| 3565 | if ((cris_get_operand1 (inst) == REG_PC) |
| 3566 | && (cris_get_mode (inst) == AUTOINC_MODE)) |
| 3567 | { |
| 3568 | /* Get the size field. */ |
| 3569 | size = cris_get_size (inst); |
| 3570 | |
| 3571 | /* If it's an extend instruction we don't want the signed extend bit, |
| 3572 | because it influences the size. */ |
| 3573 | if (cris_get_opcode (inst) < 4) |
| 3574 | { |
| 3575 | size &= ~SIGNED_EXTEND_BIT_MASK; |
| 3576 | } |
| 3577 | process_autoincrement (size, inst, inst_env); |
| 3578 | } |
| 3579 | inst_env->slot_needed = 0; |
| 3580 | inst_env->prefix_found = 0; |
| 3581 | inst_env->xflag_found = 0; |
| 3582 | inst_env->disable_interrupt = 0; |
| 3583 | } |
| 3584 | |
| 3585 | /* Handles the two-operand addressing mode, all modes except register, for |
| 3586 | the ADD, SUB CMP, AND and OR instruction. */ |
| 3587 | |
| 3588 | static void |
| 3589 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
| 3590 | inst_env_type *inst_env) |
| 3591 | { |
| 3592 | if (inst_env->prefix_found) |
| 3593 | { |
| 3594 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) |
| 3595 | { |
| 3596 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); |
| 3597 | } |
| 3598 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
| 3599 | { |
| 3600 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); |
| 3601 | } |
| 3602 | else |
| 3603 | { |
| 3604 | /* The mode is invalid for a prefixed base instruction. */ |
| 3605 | inst_env->invalid = 1; |
| 3606 | return; |
| 3607 | } |
| 3608 | } |
| 3609 | else |
| 3610 | { |
| 3611 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); |
| 3612 | } |
| 3613 | } |
| 3614 | |
| 3615 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ |
| 3616 | |
| 3617 | static void |
| 3618 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
| 3619 | { |
| 3620 | unsigned long operand1; |
| 3621 | unsigned long operand2; |
| 3622 | |
| 3623 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode |
| 3624 | instruction and can't have a prefix. */ |
| 3625 | if (inst_env->prefix_found) |
| 3626 | { |
| 3627 | inst_env->invalid = 1; |
| 3628 | return; |
| 3629 | } |
| 3630 | |
| 3631 | /* Check if the instruction has PC as its target. */ |
| 3632 | if (cris_get_operand2 (inst) == REG_PC) |
| 3633 | { |
| 3634 | if (inst_env->slot_needed) |
| 3635 | { |
| 3636 | inst_env->invalid = 1; |
| 3637 | return; |
| 3638 | } |
| 3639 | operand1 = cris_get_quick_value (inst); |
| 3640 | operand2 = inst_env->reg[REG_PC]; |
| 3641 | |
| 3642 | /* The size should now be dword. */ |
| 3643 | cris_set_size_to_dword (&inst); |
| 3644 | |
| 3645 | /* Calculate the PC value after the instruction, i.e. where the |
| 3646 | breakpoint should be. */ |
| 3647 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
| 3648 | } |
| 3649 | inst_env->slot_needed = 0; |
| 3650 | inst_env->prefix_found = 0; |
| 3651 | inst_env->xflag_found = 0; |
| 3652 | inst_env->disable_interrupt = 0; |
| 3653 | } |
| 3654 | |
| 3655 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ |
| 3656 | |
| 3657 | static void |
| 3658 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
| 3659 | { |
| 3660 | unsigned long operand1; |
| 3661 | unsigned long operand2; |
| 3662 | |
| 3663 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode |
| 3664 | instruction and can't have a prefix. */ |
| 3665 | if (inst_env->prefix_found) |
| 3666 | { |
| 3667 | inst_env->invalid = 1; |
| 3668 | return; |
| 3669 | } |
| 3670 | /* Check if the instruction has PC as its target. */ |
| 3671 | if (cris_get_operand2 (inst) == REG_PC) |
| 3672 | { |
| 3673 | if (inst_env->slot_needed) |
| 3674 | { |
| 3675 | inst_env->invalid = 1; |
| 3676 | return; |
| 3677 | } |
| 3678 | /* The instruction has the PC as its target register. */ |
| 3679 | operand1 = cris_get_quick_value (inst); |
| 3680 | operand2 = inst_env->reg[REG_PC]; |
| 3681 | |
| 3682 | /* The quick value is signed, so check if we must do a signed extend. */ |
| 3683 | if (operand1 & SIGNED_QUICK_VALUE_MASK) |
| 3684 | { |
| 3685 | /* sign extend */ |
| 3686 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; |
| 3687 | } |
| 3688 | /* The size should now be dword. */ |
| 3689 | cris_set_size_to_dword (&inst); |
| 3690 | |
| 3691 | /* Calculate the PC value after the instruction, i.e. where the |
| 3692 | breakpoint should be. */ |
| 3693 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
| 3694 | } |
| 3695 | inst_env->slot_needed = 0; |
| 3696 | inst_env->prefix_found = 0; |
| 3697 | inst_env->xflag_found = 0; |
| 3698 | inst_env->disable_interrupt = 0; |
| 3699 | } |
| 3700 | |
| 3701 | /* Translate op_type to a function and call it. */ |
| 3702 | |
| 3703 | static void |
| 3704 | cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type, |
| 3705 | unsigned short inst, inst_env_type *inst_env) |
| 3706 | { |
| 3707 | switch (op_type) |
| 3708 | { |
| 3709 | case cris_not_implemented_op: |
| 3710 | not_implemented_op (inst, inst_env); |
| 3711 | break; |
| 3712 | |
| 3713 | case cris_abs_op: |
| 3714 | abs_op (inst, inst_env); |
| 3715 | break; |
| 3716 | |
| 3717 | case cris_addi_op: |
| 3718 | addi_op (inst, inst_env); |
| 3719 | break; |
| 3720 | |
| 3721 | case cris_asr_op: |
| 3722 | asr_op (inst, inst_env); |
| 3723 | break; |
| 3724 | |
| 3725 | case cris_asrq_op: |
| 3726 | asrq_op (inst, inst_env); |
| 3727 | break; |
| 3728 | |
| 3729 | case cris_ax_ei_setf_op: |
| 3730 | ax_ei_setf_op (inst, inst_env); |
| 3731 | break; |
| 3732 | |
| 3733 | case cris_bdap_prefix: |
| 3734 | bdap_prefix (inst, inst_env); |
| 3735 | break; |
| 3736 | |
| 3737 | case cris_biap_prefix: |
| 3738 | biap_prefix (inst, inst_env); |
| 3739 | break; |
| 3740 | |
| 3741 | case cris_break_op: |
| 3742 | break_op (inst, inst_env); |
| 3743 | break; |
| 3744 | |
| 3745 | case cris_btst_nop_op: |
| 3746 | btst_nop_op (inst, inst_env); |
| 3747 | break; |
| 3748 | |
| 3749 | case cris_clearf_di_op: |
| 3750 | clearf_di_op (inst, inst_env); |
| 3751 | break; |
| 3752 | |
| 3753 | case cris_dip_prefix: |
| 3754 | dip_prefix (inst, inst_env); |
| 3755 | break; |
| 3756 | |
| 3757 | case cris_dstep_logshift_mstep_neg_not_op: |
| 3758 | dstep_logshift_mstep_neg_not_op (inst, inst_env); |
| 3759 | break; |
| 3760 | |
| 3761 | case cris_eight_bit_offset_branch_op: |
| 3762 | eight_bit_offset_branch_op (inst, inst_env); |
| 3763 | break; |
| 3764 | |
| 3765 | case cris_move_mem_to_reg_movem_op: |
| 3766 | move_mem_to_reg_movem_op (inst, inst_env); |
| 3767 | break; |
| 3768 | |
| 3769 | case cris_move_reg_to_mem_movem_op: |
| 3770 | move_reg_to_mem_movem_op (inst, inst_env); |
| 3771 | break; |
| 3772 | |
| 3773 | case cris_move_to_preg_op: |
| 3774 | move_to_preg_op (gdbarch, inst, inst_env); |
| 3775 | break; |
| 3776 | |
| 3777 | case cris_muls_op: |
| 3778 | muls_op (inst, inst_env); |
| 3779 | break; |
| 3780 | |
| 3781 | case cris_mulu_op: |
| 3782 | mulu_op (inst, inst_env); |
| 3783 | break; |
| 3784 | |
| 3785 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: |
| 3786 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); |
| 3787 | break; |
| 3788 | |
| 3789 | case cris_none_reg_mode_clear_test_op: |
| 3790 | none_reg_mode_clear_test_op (inst, inst_env); |
| 3791 | break; |
| 3792 | |
| 3793 | case cris_none_reg_mode_jump_op: |
| 3794 | none_reg_mode_jump_op (inst, inst_env); |
| 3795 | break; |
| 3796 | |
| 3797 | case cris_none_reg_mode_move_from_preg_op: |
| 3798 | none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env); |
| 3799 | break; |
| 3800 | |
| 3801 | case cris_quick_mode_add_sub_op: |
| 3802 | quick_mode_add_sub_op (inst, inst_env); |
| 3803 | break; |
| 3804 | |
| 3805 | case cris_quick_mode_and_cmp_move_or_op: |
| 3806 | quick_mode_and_cmp_move_or_op (inst, inst_env); |
| 3807 | break; |
| 3808 | |
| 3809 | case cris_quick_mode_bdap_prefix: |
| 3810 | quick_mode_bdap_prefix (inst, inst_env); |
| 3811 | break; |
| 3812 | |
| 3813 | case cris_reg_mode_add_sub_cmp_and_or_move_op: |
| 3814 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); |
| 3815 | break; |
| 3816 | |
| 3817 | case cris_reg_mode_clear_op: |
| 3818 | reg_mode_clear_op (inst, inst_env); |
| 3819 | break; |
| 3820 | |
| 3821 | case cris_reg_mode_jump_op: |
| 3822 | reg_mode_jump_op (inst, inst_env); |
| 3823 | break; |
| 3824 | |
| 3825 | case cris_reg_mode_move_from_preg_op: |
| 3826 | reg_mode_move_from_preg_op (inst, inst_env); |
| 3827 | break; |
| 3828 | |
| 3829 | case cris_reg_mode_test_op: |
| 3830 | reg_mode_test_op (inst, inst_env); |
| 3831 | break; |
| 3832 | |
| 3833 | case cris_scc_op: |
| 3834 | scc_op (inst, inst_env); |
| 3835 | break; |
| 3836 | |
| 3837 | case cris_sixteen_bit_offset_branch_op: |
| 3838 | sixteen_bit_offset_branch_op (inst, inst_env); |
| 3839 | break; |
| 3840 | |
| 3841 | case cris_three_operand_add_sub_cmp_and_or_op: |
| 3842 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); |
| 3843 | break; |
| 3844 | |
| 3845 | case cris_three_operand_bound_op: |
| 3846 | three_operand_bound_op (inst, inst_env); |
| 3847 | break; |
| 3848 | |
| 3849 | case cris_two_operand_bound_op: |
| 3850 | two_operand_bound_op (inst, inst_env); |
| 3851 | break; |
| 3852 | |
| 3853 | case cris_xor_op: |
| 3854 | xor_op (inst, inst_env); |
| 3855 | break; |
| 3856 | } |
| 3857 | } |
| 3858 | |
| 3859 | /* This wrapper is to avoid cris_get_assembler being called before |
| 3860 | exec_bfd has been set. */ |
| 3861 | |
| 3862 | static int |
| 3863 | cris_delayed_get_disassembler (bfd_vma addr, struct disassemble_info *info) |
| 3864 | { |
| 3865 | int (*print_insn) (bfd_vma addr, struct disassemble_info *info); |
| 3866 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
| 3867 | disassembler, even when there is no BFD. Does something like |
| 3868 | "gdb; target remote; disassmeble *0x123" work? */ |
| 3869 | gdb_assert (exec_bfd != NULL); |
| 3870 | print_insn = cris_get_disassembler (exec_bfd); |
| 3871 | gdb_assert (print_insn != NULL); |
| 3872 | return print_insn (addr, info); |
| 3873 | } |
| 3874 | |
| 3875 | /* Copied from <asm/elf.h>. */ |
| 3876 | typedef unsigned long elf_greg_t; |
| 3877 | |
| 3878 | /* Same as user_regs_struct struct in <asm/user.h>. */ |
| 3879 | #define CRISV10_ELF_NGREG 35 |
| 3880 | typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG]; |
| 3881 | |
| 3882 | #define CRISV32_ELF_NGREG 32 |
| 3883 | typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; |
| 3884 | |
| 3885 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
| 3886 | |
| 3887 | static void |
| 3888 | cris_supply_gregset (struct regcache *regcache, elf_gregset_t *gregsetp) |
| 3889 | { |
| 3890 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 3891 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3892 | int i; |
| 3893 | elf_greg_t *regp = *gregsetp; |
| 3894 | static char zerobuf[4] = {0}; |
| 3895 | |
| 3896 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register |
| 3897 | knows about the actual size of each register so that's no problem. */ |
| 3898 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) |
| 3899 | { |
| 3900 | regcache_raw_supply (regcache, i, (char *)®p[i]); |
| 3901 | } |
| 3902 | |
| 3903 | if (tdep->cris_version == 32) |
| 3904 | { |
| 3905 | /* Needed to set pseudo-register PC for CRISv32. */ |
| 3906 | /* FIXME: If ERP is in a delay slot at this point then the PC will |
| 3907 | be wrong. Issue a warning to alert the user. */ |
| 3908 | regcache_raw_supply (regcache, gdbarch_pc_regnum (gdbarch), |
| 3909 | (char *)®p[ERP_REGNUM]); |
| 3910 | |
| 3911 | if (*(char *)®p[ERP_REGNUM] & 0x1) |
| 3912 | fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n"); |
| 3913 | } |
| 3914 | } |
| 3915 | |
| 3916 | /* Use a local version of this function to get the correct types for |
| 3917 | regsets, until multi-arch core support is ready. */ |
| 3918 | |
| 3919 | static void |
| 3920 | fetch_core_registers (struct regcache *regcache, |
| 3921 | char *core_reg_sect, unsigned core_reg_size, |
| 3922 | int which, CORE_ADDR reg_addr) |
| 3923 | { |
| 3924 | elf_gregset_t gregset; |
| 3925 | |
| 3926 | switch (which) |
| 3927 | { |
| 3928 | case 0: |
| 3929 | if (core_reg_size != sizeof (elf_gregset_t) |
| 3930 | && core_reg_size != sizeof (crisv32_elf_gregset_t)) |
| 3931 | { |
| 3932 | warning (_("wrong size gregset struct in core file")); |
| 3933 | } |
| 3934 | else |
| 3935 | { |
| 3936 | memcpy (&gregset, core_reg_sect, sizeof (gregset)); |
| 3937 | cris_supply_gregset (regcache, &gregset); |
| 3938 | } |
| 3939 | |
| 3940 | default: |
| 3941 | /* We've covered all the kinds of registers we know about here, |
| 3942 | so this must be something we wouldn't know what to do with |
| 3943 | anyway. Just ignore it. */ |
| 3944 | break; |
| 3945 | } |
| 3946 | } |
| 3947 | |
| 3948 | static struct core_fns cris_elf_core_fns = |
| 3949 | { |
| 3950 | bfd_target_elf_flavour, /* core_flavour */ |
| 3951 | default_check_format, /* check_format */ |
| 3952 | default_core_sniffer, /* core_sniffer */ |
| 3953 | fetch_core_registers, /* core_read_registers */ |
| 3954 | NULL /* next */ |
| 3955 | }; |
| 3956 | |
| 3957 | extern initialize_file_ftype _initialize_cris_tdep; /* -Wmissing-prototypes */ |
| 3958 | |
| 3959 | void |
| 3960 | _initialize_cris_tdep (void) |
| 3961 | { |
| 3962 | static struct cmd_list_element *cris_set_cmdlist; |
| 3963 | static struct cmd_list_element *cris_show_cmdlist; |
| 3964 | |
| 3965 | struct cmd_list_element *c; |
| 3966 | |
| 3967 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); |
| 3968 | |
| 3969 | /* CRIS-specific user-commands. */ |
| 3970 | add_setshow_uinteger_cmd ("cris-version", class_support, |
| 3971 | &usr_cmd_cris_version, |
| 3972 | _("Set the current CRIS version."), |
| 3973 | _("Show the current CRIS version."), |
| 3974 | _("\ |
| 3975 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ |
| 3976 | Defaults to 10. "), |
| 3977 | set_cris_version, |
| 3978 | NULL, /* FIXME: i18n: Current CRIS version |
| 3979 | is %s. */ |
| 3980 | &setlist, &showlist); |
| 3981 | |
| 3982 | add_setshow_enum_cmd ("cris-mode", class_support, |
| 3983 | cris_modes, &usr_cmd_cris_mode, |
| 3984 | _("Set the current CRIS mode."), |
| 3985 | _("Show the current CRIS mode."), |
| 3986 | _("\ |
| 3987 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ |
| 3988 | Makes GDB use the NRP register instead of the ERP register in certain cases."), |
| 3989 | set_cris_mode, |
| 3990 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ |
| 3991 | &setlist, &showlist); |
| 3992 | |
| 3993 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
| 3994 | &usr_cmd_cris_dwarf2_cfi, |
| 3995 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
| 3996 | _("Show the usage of Dwarf-2 CFI for CRIS."), |
| 3997 | _("Set this to \"off\" if using gcc-cris < R59."), |
| 3998 | set_cris_dwarf2_cfi, |
| 3999 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI |
| 4000 | for CRIS is %d. */ |
| 4001 | &setlist, &showlist); |
| 4002 | |
| 4003 | deprecated_add_core_fns (&cris_elf_core_fns); |
| 4004 | } |
| 4005 | |
| 4006 | /* Prints out all target specific values. */ |
| 4007 | |
| 4008 | static void |
| 4009 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
| 4010 | { |
| 4011 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 4012 | if (tdep != NULL) |
| 4013 | { |
| 4014 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_version = %i\n", |
| 4015 | tdep->cris_version); |
| 4016 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_mode = %s\n", |
| 4017 | tdep->cris_mode); |
| 4018 | fprintf_unfiltered (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", |
| 4019 | tdep->cris_dwarf2_cfi); |
| 4020 | } |
| 4021 | } |
| 4022 | |
| 4023 | static void |
| 4024 | set_cris_version (char *ignore_args, int from_tty, |
| 4025 | struct cmd_list_element *c) |
| 4026 | { |
| 4027 | struct gdbarch_info info; |
| 4028 | |
| 4029 | usr_cmd_cris_version_valid = 1; |
| 4030 | |
| 4031 | /* Update the current architecture, if needed. */ |
| 4032 | gdbarch_info_init (&info); |
| 4033 | if (!gdbarch_update_p (info)) |
| 4034 | internal_error (__FILE__, __LINE__, |
| 4035 | _("cris_gdbarch_update: failed to update architecture.")); |
| 4036 | } |
| 4037 | |
| 4038 | static void |
| 4039 | set_cris_mode (char *ignore_args, int from_tty, |
| 4040 | struct cmd_list_element *c) |
| 4041 | { |
| 4042 | struct gdbarch_info info; |
| 4043 | |
| 4044 | /* Update the current architecture, if needed. */ |
| 4045 | gdbarch_info_init (&info); |
| 4046 | if (!gdbarch_update_p (info)) |
| 4047 | internal_error (__FILE__, __LINE__, |
| 4048 | "cris_gdbarch_update: failed to update architecture."); |
| 4049 | } |
| 4050 | |
| 4051 | static void |
| 4052 | set_cris_dwarf2_cfi (char *ignore_args, int from_tty, |
| 4053 | struct cmd_list_element *c) |
| 4054 | { |
| 4055 | struct gdbarch_info info; |
| 4056 | |
| 4057 | /* Update the current architecture, if needed. */ |
| 4058 | gdbarch_info_init (&info); |
| 4059 | if (!gdbarch_update_p (info)) |
| 4060 | internal_error (__FILE__, __LINE__, |
| 4061 | _("cris_gdbarch_update: failed to update architecture.")); |
| 4062 | } |
| 4063 | |
| 4064 | static struct gdbarch * |
| 4065 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 4066 | { |
| 4067 | struct gdbarch *gdbarch; |
| 4068 | struct gdbarch_tdep *tdep; |
| 4069 | int cris_version; |
| 4070 | |
| 4071 | if (usr_cmd_cris_version_valid) |
| 4072 | { |
| 4073 | /* Trust the user's CRIS version setting. */ |
| 4074 | cris_version = usr_cmd_cris_version; |
| 4075 | } |
| 4076 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
| 4077 | { |
| 4078 | cris_version = 32; |
| 4079 | } |
| 4080 | else |
| 4081 | { |
| 4082 | /* Assume it's CRIS version 10. */ |
| 4083 | cris_version = 10; |
| 4084 | } |
| 4085 | |
| 4086 | /* Make the current settings visible to the user. */ |
| 4087 | usr_cmd_cris_version = cris_version; |
| 4088 | |
| 4089 | /* Find a candidate among the list of pre-declared architectures. */ |
| 4090 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 4091 | arches != NULL; |
| 4092 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 4093 | { |
| 4094 | if ((gdbarch_tdep (arches->gdbarch)->cris_version |
| 4095 | == usr_cmd_cris_version) |
| 4096 | && (gdbarch_tdep (arches->gdbarch)->cris_mode |
| 4097 | == usr_cmd_cris_mode) |
| 4098 | && (gdbarch_tdep (arches->gdbarch)->cris_dwarf2_cfi |
| 4099 | == usr_cmd_cris_dwarf2_cfi)) |
| 4100 | return arches->gdbarch; |
| 4101 | } |
| 4102 | |
| 4103 | /* No matching architecture was found. Create a new one. */ |
| 4104 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
| 4105 | gdbarch = gdbarch_alloc (&info, tdep); |
| 4106 | |
| 4107 | tdep->cris_version = usr_cmd_cris_version; |
| 4108 | tdep->cris_mode = usr_cmd_cris_mode; |
| 4109 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
| 4110 | |
| 4111 | /* INIT shall ensure that the INFO.BYTE_ORDER is non-zero. */ |
| 4112 | switch (info.byte_order) |
| 4113 | { |
| 4114 | case BFD_ENDIAN_LITTLE: |
| 4115 | /* Ok. */ |
| 4116 | break; |
| 4117 | |
| 4118 | case BFD_ENDIAN_BIG: |
| 4119 | internal_error (__FILE__, __LINE__, |
| 4120 | _("cris_gdbarch_init: big endian byte order in info")); |
| 4121 | break; |
| 4122 | |
| 4123 | default: |
| 4124 | internal_error (__FILE__, __LINE__, |
| 4125 | _("cris_gdbarch_init: unknown byte order in info")); |
| 4126 | } |
| 4127 | |
| 4128 | set_gdbarch_return_value (gdbarch, cris_return_value); |
| 4129 | |
| 4130 | set_gdbarch_sp_regnum (gdbarch, 14); |
| 4131 | |
| 4132 | /* Length of ordinary registers used in push_word and a few other |
| 4133 | places. register_size() is the real way to know how big a |
| 4134 | register is. */ |
| 4135 | |
| 4136 | set_gdbarch_double_bit (gdbarch, 64); |
| 4137 | /* The default definition of a long double is 2 * gdbarch_double_bit, |
| 4138 | which means we have to set this explicitly. */ |
| 4139 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 4140 | |
| 4141 | /* The total amount of space needed to store (in an array called registers) |
| 4142 | GDB's copy of the machine's register state. Note: We can not use |
| 4143 | cris_register_size at this point, since it relies on gdbarch |
| 4144 | being set. */ |
| 4145 | switch (tdep->cris_version) |
| 4146 | { |
| 4147 | case 0: |
| 4148 | case 1: |
| 4149 | case 2: |
| 4150 | case 3: |
| 4151 | case 8: |
| 4152 | case 9: |
| 4153 | /* Old versions; not supported. */ |
| 4154 | internal_error (__FILE__, __LINE__, |
| 4155 | _("cris_gdbarch_init: unsupported CRIS version")); |
| 4156 | break; |
| 4157 | |
| 4158 | case 10: |
| 4159 | case 11: |
| 4160 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, |
| 4161 | P7 (32 bits), and P15 (32 bits) have been implemented. */ |
| 4162 | set_gdbarch_pc_regnum (gdbarch, 15); |
| 4163 | set_gdbarch_register_type (gdbarch, cris_register_type); |
| 4164 | /* There are 32 registers (some of which may not be implemented). */ |
| 4165 | set_gdbarch_num_regs (gdbarch, 32); |
| 4166 | set_gdbarch_register_name (gdbarch, cris_register_name); |
| 4167 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); |
| 4168 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); |
| 4169 | |
| 4170 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); |
| 4171 | break; |
| 4172 | |
| 4173 | case 32: |
| 4174 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers |
| 4175 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) |
| 4176 | and pseudo-register PC (32 bits). */ |
| 4177 | set_gdbarch_pc_regnum (gdbarch, 32); |
| 4178 | set_gdbarch_register_type (gdbarch, crisv32_register_type); |
| 4179 | /* 32 registers + pseudo-register PC + 16 support registers. */ |
| 4180 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); |
| 4181 | set_gdbarch_register_name (gdbarch, crisv32_register_name); |
| 4182 | |
| 4183 | set_gdbarch_cannot_store_register |
| 4184 | (gdbarch, crisv32_cannot_store_register); |
| 4185 | set_gdbarch_cannot_fetch_register |
| 4186 | (gdbarch, crisv32_cannot_fetch_register); |
| 4187 | |
| 4188 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
| 4189 | |
| 4190 | set_gdbarch_single_step_through_delay |
| 4191 | (gdbarch, crisv32_single_step_through_delay); |
| 4192 | |
| 4193 | break; |
| 4194 | |
| 4195 | default: |
| 4196 | internal_error (__FILE__, __LINE__, |
| 4197 | _("cris_gdbarch_init: unknown CRIS version")); |
| 4198 | } |
| 4199 | |
| 4200 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
| 4201 | have the same ABI). */ |
| 4202 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
| 4203 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); |
| 4204 | set_gdbarch_frame_align (gdbarch, cris_frame_align); |
| 4205 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
| 4206 | |
| 4207 | /* The stack grows downward. */ |
| 4208 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 4209 | |
| 4210 | set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); |
| 4211 | |
| 4212 | set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); |
| 4213 | set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); |
| 4214 | set_gdbarch_dummy_id (gdbarch, cris_dummy_id); |
| 4215 | |
| 4216 | if (tdep->cris_dwarf2_cfi == 1) |
| 4217 | { |
| 4218 | /* Hook in the Dwarf-2 frame sniffer. */ |
| 4219 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); |
| 4220 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); |
| 4221 | dwarf2_append_unwinders (gdbarch); |
| 4222 | } |
| 4223 | |
| 4224 | if (tdep->cris_mode != cris_mode_guru) |
| 4225 | { |
| 4226 | frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind); |
| 4227 | } |
| 4228 | |
| 4229 | frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind); |
| 4230 | frame_base_set_default (gdbarch, &cris_frame_base); |
| 4231 | |
| 4232 | set_solib_svr4_fetch_link_map_offsets |
| 4233 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
| 4234 | |
| 4235 | /* FIXME: cagney/2003-08-27: It should be possible to select a CRIS |
| 4236 | disassembler, even when there is no BFD. Does something like |
| 4237 | "gdb; target remote; disassmeble *0x123" work? */ |
| 4238 | set_gdbarch_print_insn (gdbarch, cris_delayed_get_disassembler); |
| 4239 | |
| 4240 | return gdbarch; |
| 4241 | } |