| 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
| 2 | Copyright (C) 1996, 1997 Free Software Foundation, Inc. |
| 3 | |
| 4 | This file is part of GDB. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify |
| 7 | it under the terms of the GNU General Public License as published by |
| 8 | the Free Software Foundation; either version 2 of the License, or |
| 9 | (at your option) any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, |
| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | GNU General Public License for more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License |
| 17 | along with this program; if not, write to the Free Software |
| 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
| 19 | |
| 20 | /* Contributed by Martin Hunt, hunt@cygnus.com */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "frame.h" |
| 24 | #include "obstack.h" |
| 25 | #include "symtab.h" |
| 26 | #include "gdbtypes.h" |
| 27 | #include "gdbcmd.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "gdb_string.h" |
| 30 | #include "value.h" |
| 31 | #include "inferior.h" |
| 32 | #include "dis-asm.h" |
| 33 | #include "symfile.h" |
| 34 | #include "objfiles.h" |
| 35 | |
| 36 | void d10v_frame_find_saved_regs PARAMS ((struct frame_info *fi, |
| 37 | struct frame_saved_regs *fsr)); |
| 38 | |
| 39 | /* Discard from the stack the innermost frame, restoring all saved |
| 40 | registers. */ |
| 41 | |
| 42 | void |
| 43 | d10v_pop_frame (frame) |
| 44 | struct frame_info *frame; |
| 45 | { |
| 46 | CORE_ADDR fp; |
| 47 | int regnum; |
| 48 | struct frame_saved_regs fsr; |
| 49 | char raw_buffer[8]; |
| 50 | |
| 51 | fp = FRAME_FP (frame); |
| 52 | /* fill out fsr with the address of where each */ |
| 53 | /* register was stored in the frame */ |
| 54 | get_frame_saved_regs (frame, &fsr); |
| 55 | |
| 56 | /* now update the current registers with the old values */ |
| 57 | for (regnum = A0_REGNUM; regnum < A0_REGNUM+2 ; regnum++) |
| 58 | { |
| 59 | if (fsr.regs[regnum]) |
| 60 | { |
| 61 | read_memory (fsr.regs[regnum], raw_buffer, REGISTER_RAW_SIZE(regnum)); |
| 62 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE(regnum)); |
| 63 | } |
| 64 | } |
| 65 | for (regnum = 0; regnum < SP_REGNUM; regnum++) |
| 66 | { |
| 67 | if (fsr.regs[regnum]) |
| 68 | { |
| 69 | write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], REGISTER_RAW_SIZE(regnum))); |
| 70 | } |
| 71 | } |
| 72 | if (fsr.regs[PSW_REGNUM]) |
| 73 | { |
| 74 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], REGISTER_RAW_SIZE(PSW_REGNUM))); |
| 75 | } |
| 76 | |
| 77 | write_register (PC_REGNUM, read_register (LR_REGNUM)); |
| 78 | write_register (SP_REGNUM, fp + frame->size); |
| 79 | target_store_registers (-1); |
| 80 | flush_cached_frames (); |
| 81 | } |
| 82 | |
| 83 | static int |
| 84 | check_prologue (op) |
| 85 | unsigned short op; |
| 86 | { |
| 87 | /* st rn, @-sp */ |
| 88 | if ((op & 0x7E1F) == 0x6C1F) |
| 89 | return 1; |
| 90 | |
| 91 | /* st2w rn, @-sp */ |
| 92 | if ((op & 0x7E3F) == 0x6E1F) |
| 93 | return 1; |
| 94 | |
| 95 | /* subi sp, n */ |
| 96 | if ((op & 0x7FE1) == 0x01E1) |
| 97 | return 1; |
| 98 | |
| 99 | /* mv r11, sp */ |
| 100 | if (op == 0x417E) |
| 101 | return 1; |
| 102 | |
| 103 | /* nop */ |
| 104 | if (op == 0x5E00) |
| 105 | return 1; |
| 106 | |
| 107 | /* st rn, @sp */ |
| 108 | if ((op & 0x7E1F) == 0x681E) |
| 109 | return 1; |
| 110 | |
| 111 | /* st2w rn, @sp */ |
| 112 | if ((op & 0x7E3F) == 0x3A1E) |
| 113 | return 1; |
| 114 | |
| 115 | return 0; |
| 116 | } |
| 117 | |
| 118 | CORE_ADDR |
| 119 | d10v_skip_prologue (pc) |
| 120 | CORE_ADDR pc; |
| 121 | { |
| 122 | unsigned long op; |
| 123 | unsigned short op1, op2; |
| 124 | CORE_ADDR func_addr, func_end; |
| 125 | struct symtab_and_line sal; |
| 126 | |
| 127 | /* If we have line debugging information, then the end of the */ |
| 128 | /* prologue should the first assembly instruction of the first source line */ |
| 129 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 130 | { |
| 131 | sal = find_pc_line (func_addr, 0); |
| 132 | if ( sal.end && sal.end < func_end) |
| 133 | return sal.end; |
| 134 | } |
| 135 | |
| 136 | if (target_read_memory (pc, (char *)&op, 4)) |
| 137 | return pc; /* Can't access it -- assume no prologue. */ |
| 138 | |
| 139 | while (1) |
| 140 | { |
| 141 | op = (unsigned long)read_memory_integer (pc, 4); |
| 142 | if ((op & 0xC0000000) == 0xC0000000) |
| 143 | { |
| 144 | /* long instruction */ |
| 145 | if ( ((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
| 146 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ |
| 147 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ |
| 148 | break; |
| 149 | } |
| 150 | else |
| 151 | { |
| 152 | /* short instructions */ |
| 153 | if ((op & 0xC0000000) == 0x80000000) |
| 154 | { |
| 155 | op2 = (op & 0x3FFF8000) >> 15; |
| 156 | op1 = op & 0x7FFF; |
| 157 | } |
| 158 | else |
| 159 | { |
| 160 | op1 = (op & 0x3FFF8000) >> 15; |
| 161 | op2 = op & 0x7FFF; |
| 162 | } |
| 163 | if (check_prologue(op1)) |
| 164 | { |
| 165 | if (!check_prologue(op2)) |
| 166 | { |
| 167 | /* if the previous opcode was really part of the prologue */ |
| 168 | /* and not just a NOP, then we want to break after both instructions */ |
| 169 | if (op1 != 0x5E00) |
| 170 | pc += 4; |
| 171 | break; |
| 172 | } |
| 173 | } |
| 174 | else |
| 175 | break; |
| 176 | } |
| 177 | pc += 4; |
| 178 | } |
| 179 | return pc; |
| 180 | } |
| 181 | |
| 182 | /* Given a GDB frame, determine the address of the calling function's frame. |
| 183 | This will be used to create a new GDB frame struct, and then |
| 184 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. |
| 185 | */ |
| 186 | |
| 187 | CORE_ADDR |
| 188 | d10v_frame_chain (frame) |
| 189 | struct frame_info *frame; |
| 190 | { |
| 191 | struct frame_saved_regs fsr; |
| 192 | |
| 193 | d10v_frame_find_saved_regs (frame, &fsr); |
| 194 | |
| 195 | if (frame->return_pc == IMEM_START || inside_entry_file(frame->return_pc)) |
| 196 | return (CORE_ADDR)0; |
| 197 | |
| 198 | if (!fsr.regs[FP_REGNUM]) |
| 199 | { |
| 200 | if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START) |
| 201 | return (CORE_ADDR)0; |
| 202 | |
| 203 | return fsr.regs[SP_REGNUM]; |
| 204 | } |
| 205 | |
| 206 | if (!read_memory_unsigned_integer(fsr.regs[FP_REGNUM], REGISTER_RAW_SIZE(FP_REGNUM))) |
| 207 | return (CORE_ADDR)0; |
| 208 | |
| 209 | return D10V_MAKE_DADDR (read_memory_unsigned_integer (fsr.regs[FP_REGNUM], REGISTER_RAW_SIZE (FP_REGNUM))); |
| 210 | } |
| 211 | |
| 212 | static int next_addr, uses_frame; |
| 213 | |
| 214 | static int |
| 215 | prologue_find_regs (op, fsr, addr) |
| 216 | unsigned short op; |
| 217 | struct frame_saved_regs *fsr; |
| 218 | CORE_ADDR addr; |
| 219 | { |
| 220 | int n; |
| 221 | |
| 222 | /* st rn, @-sp */ |
| 223 | if ((op & 0x7E1F) == 0x6C1F) |
| 224 | { |
| 225 | n = (op & 0x1E0) >> 5; |
| 226 | next_addr -= 2; |
| 227 | fsr->regs[n] = next_addr; |
| 228 | return 1; |
| 229 | } |
| 230 | |
| 231 | /* st2w rn, @-sp */ |
| 232 | else if ((op & 0x7E3F) == 0x6E1F) |
| 233 | { |
| 234 | n = (op & 0x1E0) >> 5; |
| 235 | next_addr -= 4; |
| 236 | fsr->regs[n] = next_addr; |
| 237 | fsr->regs[n+1] = next_addr+2; |
| 238 | return 1; |
| 239 | } |
| 240 | |
| 241 | /* subi sp, n */ |
| 242 | if ((op & 0x7FE1) == 0x01E1) |
| 243 | { |
| 244 | n = (op & 0x1E) >> 1; |
| 245 | if (n == 0) |
| 246 | n = 16; |
| 247 | next_addr -= n; |
| 248 | return 1; |
| 249 | } |
| 250 | |
| 251 | /* mv r11, sp */ |
| 252 | if (op == 0x417E) |
| 253 | { |
| 254 | uses_frame = 1; |
| 255 | return 1; |
| 256 | } |
| 257 | |
| 258 | /* nop */ |
| 259 | if (op == 0x5E00) |
| 260 | return 1; |
| 261 | |
| 262 | /* st rn, @sp */ |
| 263 | if ((op & 0x7E1F) == 0x681E) |
| 264 | { |
| 265 | n = (op & 0x1E0) >> 5; |
| 266 | fsr->regs[n] = next_addr; |
| 267 | return 1; |
| 268 | } |
| 269 | |
| 270 | /* st2w rn, @sp */ |
| 271 | if ((op & 0x7E3F) == 0x3A1E) |
| 272 | { |
| 273 | n = (op & 0x1E0) >> 5; |
| 274 | fsr->regs[n] = next_addr; |
| 275 | fsr->regs[n+1] = next_addr+2; |
| 276 | return 1; |
| 277 | } |
| 278 | |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | /* Put here the code to store, into a struct frame_saved_regs, the |
| 283 | addresses of the saved registers of frame described by FRAME_INFO. |
| 284 | This includes special registers such as pc and fp saved in special |
| 285 | ways in the stack frame. sp is even more special: the address we |
| 286 | return for it IS the sp for the next frame. */ |
| 287 | void |
| 288 | d10v_frame_find_saved_regs (fi, fsr) |
| 289 | struct frame_info *fi; |
| 290 | struct frame_saved_regs *fsr; |
| 291 | { |
| 292 | CORE_ADDR fp, pc; |
| 293 | unsigned long op; |
| 294 | unsigned short op1, op2; |
| 295 | int i; |
| 296 | |
| 297 | fp = fi->frame; |
| 298 | memset (fsr, 0, sizeof (*fsr)); |
| 299 | next_addr = 0; |
| 300 | |
| 301 | pc = get_pc_function_start (fi->pc); |
| 302 | |
| 303 | uses_frame = 0; |
| 304 | while (1) |
| 305 | { |
| 306 | op = (unsigned long)read_memory_integer (pc, 4); |
| 307 | if ((op & 0xC0000000) == 0xC0000000) |
| 308 | { |
| 309 | /* long instruction */ |
| 310 | if ((op & 0x3FFF0000) == 0x01FF0000) |
| 311 | { |
| 312 | /* add3 sp,sp,n */ |
| 313 | short n = op & 0xFFFF; |
| 314 | next_addr += n; |
| 315 | } |
| 316 | else if ((op & 0x3F0F0000) == 0x340F0000) |
| 317 | { |
| 318 | /* st rn, @(offset,sp) */ |
| 319 | short offset = op & 0xFFFF; |
| 320 | short n = (op >> 20) & 0xF; |
| 321 | fsr->regs[n] = next_addr + offset; |
| 322 | } |
| 323 | else if ((op & 0x3F1F0000) == 0x350F0000) |
| 324 | { |
| 325 | /* st2w rn, @(offset,sp) */ |
| 326 | short offset = op & 0xFFFF; |
| 327 | short n = (op >> 20) & 0xF; |
| 328 | fsr->regs[n] = next_addr + offset; |
| 329 | fsr->regs[n+1] = next_addr + offset + 2; |
| 330 | } |
| 331 | else |
| 332 | break; |
| 333 | } |
| 334 | else |
| 335 | { |
| 336 | /* short instructions */ |
| 337 | if ((op & 0xC0000000) == 0x80000000) |
| 338 | { |
| 339 | op2 = (op & 0x3FFF8000) >> 15; |
| 340 | op1 = op & 0x7FFF; |
| 341 | } |
| 342 | else |
| 343 | { |
| 344 | op1 = (op & 0x3FFF8000) >> 15; |
| 345 | op2 = op & 0x7FFF; |
| 346 | } |
| 347 | if (!prologue_find_regs(op1,fsr,pc) || !prologue_find_regs(op2,fsr,pc)) |
| 348 | break; |
| 349 | } |
| 350 | pc += 4; |
| 351 | } |
| 352 | |
| 353 | fi->size = -next_addr; |
| 354 | |
| 355 | if (!(fp & 0xffff)) |
| 356 | fp = D10V_MAKE_DADDR (read_register(SP_REGNUM)); |
| 357 | |
| 358 | for (i=0; i<NUM_REGS-1; i++) |
| 359 | if (fsr->regs[i]) |
| 360 | { |
| 361 | fsr->regs[i] = fp - (next_addr - fsr->regs[i]); |
| 362 | } |
| 363 | |
| 364 | if (fsr->regs[LR_REGNUM]) |
| 365 | { |
| 366 | CORE_ADDR return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); |
| 367 | fi->return_pc = D10V_MAKE_IADDR (return_pc); |
| 368 | } |
| 369 | else |
| 370 | { |
| 371 | fi->return_pc = D10V_MAKE_IADDR (read_register(LR_REGNUM)); |
| 372 | } |
| 373 | |
| 374 | /* th SP is not normally (ever?) saved, but check anyway */ |
| 375 | if (!fsr->regs[SP_REGNUM]) |
| 376 | { |
| 377 | /* if the FP was saved, that means the current FP is valid, */ |
| 378 | /* otherwise, it isn't being used, so we use the SP instead */ |
| 379 | if (uses_frame) |
| 380 | fsr->regs[SP_REGNUM] = read_register(FP_REGNUM) + fi->size; |
| 381 | else |
| 382 | { |
| 383 | fsr->regs[SP_REGNUM] = fp + fi->size; |
| 384 | fi->frameless = 1; |
| 385 | fsr->regs[FP_REGNUM] = 0; |
| 386 | } |
| 387 | } |
| 388 | } |
| 389 | |
| 390 | void |
| 391 | d10v_init_extra_frame_info (fromleaf, fi) |
| 392 | int fromleaf; |
| 393 | struct frame_info *fi; |
| 394 | { |
| 395 | fi->frameless = 0; |
| 396 | fi->size = 0; |
| 397 | fi->return_pc = 0; |
| 398 | |
| 399 | /* The call dummy doesn't save any registers on the stack, so we can |
| 400 | return now. */ |
| 401 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
| 402 | { |
| 403 | return; |
| 404 | } |
| 405 | else |
| 406 | { |
| 407 | struct frame_saved_regs dummy; |
| 408 | d10v_frame_find_saved_regs (fi, &dummy); |
| 409 | } |
| 410 | } |
| 411 | |
| 412 | static void |
| 413 | show_regs (args, from_tty) |
| 414 | char *args; |
| 415 | int from_tty; |
| 416 | { |
| 417 | int a; |
| 418 | printf_filtered ("PC=%04x (0x%x) PSW=%04x RPT_S=%04x RPT_E=%04x RPT_C=%04x\n", |
| 419 | read_register (PC_REGNUM), D10V_MAKE_IADDR (read_register (PC_REGNUM)), |
| 420 | read_register (PSW_REGNUM), |
| 421 | read_register (24), |
| 422 | read_register (25), |
| 423 | read_register (23)); |
| 424 | printf_filtered ("R0-R7 %04x %04x %04x %04x %04x %04x %04x %04x\n", |
| 425 | read_register (0), |
| 426 | read_register (1), |
| 427 | read_register (2), |
| 428 | read_register (3), |
| 429 | read_register (4), |
| 430 | read_register (5), |
| 431 | read_register (6), |
| 432 | read_register (7)); |
| 433 | printf_filtered ("R8-R15 %04x %04x %04x %04x %04x %04x %04x %04x\n", |
| 434 | read_register (8), |
| 435 | read_register (9), |
| 436 | read_register (10), |
| 437 | read_register (11), |
| 438 | read_register (12), |
| 439 | read_register (13), |
| 440 | read_register (14), |
| 441 | read_register (15)); |
| 442 | printf_filtered ("IMAP0 %04x IMAP1 %04x DMAP %04x\n", |
| 443 | read_register (IMAP0_REGNUM), |
| 444 | read_register (IMAP1_REGNUM), |
| 445 | read_register (DMAP_REGNUM)); |
| 446 | printf_filtered ("A0-A1"); |
| 447 | for (a = A0_REGNUM; a <= A0_REGNUM + 1; a++) |
| 448 | { |
| 449 | char num[MAX_REGISTER_RAW_SIZE]; |
| 450 | int i; |
| 451 | printf_filtered (" "); |
| 452 | read_register_gen (a, (char *)&num); |
| 453 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
| 454 | { |
| 455 | printf_filtered ("%02x", (num[i] & 0xff)); |
| 456 | } |
| 457 | } |
| 458 | printf_filtered ("\n"); |
| 459 | } |
| 460 | |
| 461 | CORE_ADDR |
| 462 | d10v_read_pc (pid) |
| 463 | int pid; |
| 464 | { |
| 465 | int save_pid; |
| 466 | CORE_ADDR pc; |
| 467 | CORE_ADDR retval; |
| 468 | |
| 469 | save_pid = inferior_pid; |
| 470 | inferior_pid = pid; |
| 471 | pc = (int) read_register (PC_REGNUM); |
| 472 | inferior_pid = save_pid; |
| 473 | retval = D10V_MAKE_IADDR (pc); |
| 474 | return retval; |
| 475 | } |
| 476 | |
| 477 | void |
| 478 | d10v_write_pc (val, pid) |
| 479 | CORE_ADDR val; |
| 480 | int pid; |
| 481 | { |
| 482 | int save_pid; |
| 483 | |
| 484 | save_pid = inferior_pid; |
| 485 | inferior_pid = pid; |
| 486 | write_register (PC_REGNUM, D10V_CONVERT_IADDR_TO_RAW (val)); |
| 487 | inferior_pid = save_pid; |
| 488 | } |
| 489 | |
| 490 | CORE_ADDR |
| 491 | d10v_read_sp () |
| 492 | { |
| 493 | return (D10V_MAKE_DADDR (read_register (SP_REGNUM))); |
| 494 | } |
| 495 | |
| 496 | void |
| 497 | d10v_write_sp (val) |
| 498 | CORE_ADDR val; |
| 499 | { |
| 500 | write_register (SP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); |
| 501 | } |
| 502 | |
| 503 | void |
| 504 | d10v_write_fp (val) |
| 505 | CORE_ADDR val; |
| 506 | { |
| 507 | write_register (FP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); |
| 508 | } |
| 509 | |
| 510 | CORE_ADDR |
| 511 | d10v_read_fp () |
| 512 | { |
| 513 | return (D10V_MAKE_DADDR (read_register(FP_REGNUM))); |
| 514 | } |
| 515 | |
| 516 | /* Function: push_return_address (pc) |
| 517 | Set up the return address for the inferior function call. |
| 518 | Needed for targets where we don't actually execute a JSR/BSR instruction */ |
| 519 | |
| 520 | CORE_ADDR |
| 521 | d10v_push_return_address (pc, sp) |
| 522 | CORE_ADDR pc; |
| 523 | CORE_ADDR sp; |
| 524 | { |
| 525 | write_register (LR_REGNUM, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ())); |
| 526 | return sp; |
| 527 | } |
| 528 | |
| 529 | |
| 530 | CORE_ADDR |
| 531 | d10v_push_arguments (nargs, args, sp, struct_return, struct_addr) |
| 532 | int nargs; |
| 533 | value_ptr *args; |
| 534 | CORE_ADDR sp; |
| 535 | int struct_return; |
| 536 | CORE_ADDR struct_addr; |
| 537 | { |
| 538 | int i; |
| 539 | int regnum = ARG1_REGNUM; |
| 540 | |
| 541 | /* Fill in registers and arg lists */ |
| 542 | for (i = 0; i < nargs; i++) |
| 543 | { |
| 544 | value_ptr arg = args[i]; |
| 545 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
| 546 | char *contents = VALUE_CONTENTS (arg); |
| 547 | int len = TYPE_LENGTH (type); |
| 548 | /* printf ("push: type=%d len=%d\n", type->code, len); */ |
| 549 | if (TYPE_CODE (type) == TYPE_CODE_PTR) |
| 550 | { |
| 551 | /* pointers require special handling - first convert and |
| 552 | then store */ |
| 553 | long val = extract_signed_integer (contents, len); |
| 554 | len = 2; |
| 555 | if (TYPE_TARGET_TYPE (type) |
| 556 | && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) |
| 557 | { |
| 558 | /* function pointer */ |
| 559 | val = D10V_CONVERT_IADDR_TO_RAW (val); |
| 560 | } |
| 561 | else if (D10V_IADDR_P (val)) |
| 562 | { |
| 563 | /* also function pointer! */ |
| 564 | val = D10V_CONVERT_DADDR_TO_RAW (val); |
| 565 | } |
| 566 | else |
| 567 | { |
| 568 | /* data pointer */ |
| 569 | val &= 0xFFFF; |
| 570 | } |
| 571 | if (regnum <= ARGN_REGNUM) |
| 572 | write_register (regnum++, val & 0xffff); |
| 573 | else |
| 574 | { |
| 575 | char ptr[2]; |
| 576 | sp -= 2; |
| 577 | store_address (ptr, val & 0xffff, 2); |
| 578 | write_memory (sp, ptr, 2); |
| 579 | } |
| 580 | } |
| 581 | else |
| 582 | { |
| 583 | int aligned_regnum = (regnum + 1) & ~1; |
| 584 | if (len <= 2 && regnum <= ARGN_REGNUM) |
| 585 | /* fits in a single register, do not align */ |
| 586 | { |
| 587 | long val = extract_unsigned_integer (contents, len); |
| 588 | write_register (regnum++, val); |
| 589 | } |
| 590 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) |
| 591 | /* value fits in remaining registers, store keeping left |
| 592 | aligned */ |
| 593 | { |
| 594 | int b; |
| 595 | regnum = aligned_regnum; |
| 596 | for (b = 0; b < (len & ~1); b += 2) |
| 597 | { |
| 598 | long val = extract_unsigned_integer (&contents[b], 2); |
| 599 | write_register (regnum++, val); |
| 600 | } |
| 601 | if (b < len) |
| 602 | { |
| 603 | long val = extract_unsigned_integer (&contents[b], 1); |
| 604 | write_register (regnum++, (val << 8)); |
| 605 | } |
| 606 | } |
| 607 | else |
| 608 | { |
| 609 | /* arg goes straight on stack */ |
| 610 | regnum = ARGN_REGNUM + 1; |
| 611 | sp = (sp - len) & ~1; |
| 612 | write_memory (sp, contents, len); |
| 613 | } |
| 614 | } |
| 615 | } |
| 616 | return sp; |
| 617 | } |
| 618 | |
| 619 | |
| 620 | /* Given a return value in `regbuf' with a type `valtype', |
| 621 | extract and copy its value into `valbuf'. */ |
| 622 | |
| 623 | void |
| 624 | d10v_extract_return_value (type, regbuf, valbuf) |
| 625 | struct type *type; |
| 626 | char regbuf[REGISTER_BYTES]; |
| 627 | char *valbuf; |
| 628 | { |
| 629 | int len; |
| 630 | /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */ |
| 631 | if (TYPE_CODE (type) == TYPE_CODE_PTR |
| 632 | && TYPE_TARGET_TYPE (type) |
| 633 | && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) |
| 634 | { |
| 635 | /* pointer to function */ |
| 636 | int num; |
| 637 | short snum; |
| 638 | snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); |
| 639 | store_address ( valbuf, 4, D10V_MAKE_IADDR(snum)); |
| 640 | } |
| 641 | else if (TYPE_CODE(type) == TYPE_CODE_PTR) |
| 642 | { |
| 643 | /* pointer to data */ |
| 644 | int num; |
| 645 | short snum; |
| 646 | snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); |
| 647 | store_address ( valbuf, 4, D10V_MAKE_DADDR(snum)); |
| 648 | } |
| 649 | else |
| 650 | { |
| 651 | len = TYPE_LENGTH (type); |
| 652 | if (len == 1) |
| 653 | { |
| 654 | unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); |
| 655 | store_unsigned_integer (valbuf, 1, c); |
| 656 | } |
| 657 | else if ((len & 1) == 0) |
| 658 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); |
| 659 | else |
| 660 | { |
| 661 | /* For return values of odd size, the first byte is in the |
| 662 | least significant part of the first register. The |
| 663 | remaining bytes in remaining registers. Interestingly, |
| 664 | when such values are passed in, the last byte is in the |
| 665 | most significant byte of that same register - wierd. */ |
| 666 | memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); |
| 667 | } |
| 668 | } |
| 669 | } |
| 670 | |
| 671 | /* The following code implements access to, and display of, the D10V's |
| 672 | instruction trace buffer. The buffer consists of 64K or more |
| 673 | 4-byte words of data, of which each words includes an 8-bit count, |
| 674 | an 8-bit segment number, and a 16-bit instruction address. |
| 675 | |
| 676 | In theory, the trace buffer is continuously capturing instruction |
| 677 | data that the CPU presents on its "debug bus", but in practice, the |
| 678 | ROMified GDB stub only enables tracing when it continues or steps |
| 679 | the program, and stops tracing when the program stops; so it |
| 680 | actually works for GDB to read the buffer counter out of memory and |
| 681 | then read each trace word. The counter records where the tracing |
| 682 | stops, but there is no record of where it started, so we remember |
| 683 | the PC when we resumed and then search backwards in the trace |
| 684 | buffer for a word that includes that address. This is not perfect, |
| 685 | because you will miss trace data if the resumption PC is the target |
| 686 | of a branch. (The value of the buffer counter is semi-random, any |
| 687 | trace data from a previous program stop is gone.) */ |
| 688 | |
| 689 | /* The address of the last word recorded in the trace buffer. */ |
| 690 | |
| 691 | #define DBBC_ADDR (0xd80000) |
| 692 | |
| 693 | /* The base of the trace buffer, at least for the "Board_0". */ |
| 694 | |
| 695 | #define TRACE_BUFFER_BASE (0xf40000) |
| 696 | |
| 697 | static void trace_command PARAMS ((char *, int)); |
| 698 | |
| 699 | static void untrace_command PARAMS ((char *, int)); |
| 700 | |
| 701 | static void trace_info PARAMS ((char *, int)); |
| 702 | |
| 703 | static void tdisassemble_command PARAMS ((char *, int)); |
| 704 | |
| 705 | static void display_trace PARAMS ((int, int)); |
| 706 | |
| 707 | /* True when instruction traces are being collected. */ |
| 708 | |
| 709 | static int tracing; |
| 710 | |
| 711 | /* Remembered PC. */ |
| 712 | |
| 713 | static CORE_ADDR last_pc; |
| 714 | |
| 715 | /* True when trace output should be displayed whenever program stops. */ |
| 716 | |
| 717 | static int trace_display; |
| 718 | |
| 719 | /* True when trace listing should include source lines. */ |
| 720 | |
| 721 | static int default_trace_show_source = 1; |
| 722 | |
| 723 | struct trace_buffer { |
| 724 | int size; |
| 725 | short *counts; |
| 726 | CORE_ADDR *addrs; |
| 727 | } trace_data; |
| 728 | |
| 729 | static void |
| 730 | trace_command (args, from_tty) |
| 731 | char *args; |
| 732 | int from_tty; |
| 733 | { |
| 734 | /* Clear the host-side trace buffer, allocating space if needed. */ |
| 735 | trace_data.size = 0; |
| 736 | if (trace_data.counts == NULL) |
| 737 | trace_data.counts = (short *) xmalloc (65536 * sizeof(short)); |
| 738 | if (trace_data.addrs == NULL) |
| 739 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof(CORE_ADDR)); |
| 740 | |
| 741 | tracing = 1; |
| 742 | |
| 743 | printf_filtered ("Tracing is now on.\n"); |
| 744 | } |
| 745 | |
| 746 | static void |
| 747 | untrace_command (args, from_tty) |
| 748 | char *args; |
| 749 | int from_tty; |
| 750 | { |
| 751 | tracing = 0; |
| 752 | |
| 753 | printf_filtered ("Tracing is now off.\n"); |
| 754 | } |
| 755 | |
| 756 | static void |
| 757 | trace_info (args, from_tty) |
| 758 | char *args; |
| 759 | int from_tty; |
| 760 | { |
| 761 | int i; |
| 762 | |
| 763 | if (trace_data.size) |
| 764 | { |
| 765 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); |
| 766 | |
| 767 | for (i = 0; i < trace_data.size; ++i) |
| 768 | { |
| 769 | printf_filtered ("%d: %d instruction%s at 0x%x\n", |
| 770 | i, trace_data.counts[i], |
| 771 | (trace_data.counts[i] == 1 ? "" : "s"), |
| 772 | trace_data.addrs[i]); |
| 773 | } |
| 774 | } |
| 775 | else |
| 776 | printf_filtered ("No entries in trace buffer.\n"); |
| 777 | |
| 778 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); |
| 779 | } |
| 780 | |
| 781 | /* Print the instruction at address MEMADDR in debugged memory, |
| 782 | on STREAM. Returns length of the instruction, in bytes. */ |
| 783 | |
| 784 | static int |
| 785 | print_insn (memaddr, stream) |
| 786 | CORE_ADDR memaddr; |
| 787 | GDB_FILE *stream; |
| 788 | { |
| 789 | /* If there's no disassembler, something is very wrong. */ |
| 790 | if (tm_print_insn == NULL) |
| 791 | abort (); |
| 792 | |
| 793 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 794 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; |
| 795 | else |
| 796 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; |
| 797 | return (*tm_print_insn) (memaddr, &tm_print_insn_info); |
| 798 | } |
| 799 | |
| 800 | void |
| 801 | d10v_eva_prepare_to_trace () |
| 802 | { |
| 803 | if (!tracing) |
| 804 | return; |
| 805 | |
| 806 | last_pc = read_register (PC_REGNUM); |
| 807 | } |
| 808 | |
| 809 | /* Collect trace data from the target board and format it into a form |
| 810 | more useful for display. */ |
| 811 | |
| 812 | void |
| 813 | d10v_eva_get_trace_data () |
| 814 | { |
| 815 | int count, i, j, oldsize; |
| 816 | int trace_addr, trace_seg, trace_cnt, next_cnt; |
| 817 | unsigned int last_trace, trace_word, next_word; |
| 818 | unsigned int *tmpspace; |
| 819 | |
| 820 | if (!tracing) |
| 821 | return; |
| 822 | |
| 823 | tmpspace = xmalloc (65536 * sizeof(unsigned int)); |
| 824 | |
| 825 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; |
| 826 | |
| 827 | /* Collect buffer contents from the target, stopping when we reach |
| 828 | the word recorded when execution resumed. */ |
| 829 | |
| 830 | count = 0; |
| 831 | while (last_trace > 0) |
| 832 | { |
| 833 | QUIT; |
| 834 | trace_word = |
| 835 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); |
| 836 | trace_addr = trace_word & 0xffff; |
| 837 | last_trace -= 4; |
| 838 | /* Ignore an apparently nonsensical entry. */ |
| 839 | if (trace_addr == 0xffd5) |
| 840 | continue; |
| 841 | tmpspace[count++] = trace_word; |
| 842 | if (trace_addr == last_pc) |
| 843 | break; |
| 844 | if (count > 65535) |
| 845 | break; |
| 846 | } |
| 847 | |
| 848 | /* Move the data to the host-side trace buffer, adjusting counts to |
| 849 | include the last instruction executed and transforming the address |
| 850 | into something that GDB likes. */ |
| 851 | |
| 852 | for (i = 0; i < count; ++i) |
| 853 | { |
| 854 | trace_word = tmpspace[i]; |
| 855 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); |
| 856 | trace_addr = trace_word & 0xffff; |
| 857 | next_cnt = (next_word >> 24) & 0xff; |
| 858 | j = trace_data.size + count - i - 1; |
| 859 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; |
| 860 | trace_data.counts[j] = next_cnt + 1; |
| 861 | } |
| 862 | |
| 863 | oldsize = trace_data.size; |
| 864 | trace_data.size += count; |
| 865 | |
| 866 | free (tmpspace); |
| 867 | |
| 868 | if (trace_display) |
| 869 | display_trace (oldsize, trace_data.size); |
| 870 | } |
| 871 | |
| 872 | static void |
| 873 | tdisassemble_command (arg, from_tty) |
| 874 | char *arg; |
| 875 | int from_tty; |
| 876 | { |
| 877 | int i, count; |
| 878 | CORE_ADDR low, high; |
| 879 | char *space_index; |
| 880 | |
| 881 | if (!arg) |
| 882 | { |
| 883 | low = 0; |
| 884 | high = trace_data.size; |
| 885 | } |
| 886 | else if (!(space_index = (char *) strchr (arg, ' '))) |
| 887 | { |
| 888 | low = parse_and_eval_address (arg); |
| 889 | high = low + 5; |
| 890 | } |
| 891 | else |
| 892 | { |
| 893 | /* Two arguments. */ |
| 894 | *space_index = '\0'; |
| 895 | low = parse_and_eval_address (arg); |
| 896 | high = parse_and_eval_address (space_index + 1); |
| 897 | if (high < low) |
| 898 | high = low; |
| 899 | } |
| 900 | |
| 901 | printf_filtered ("Dump of trace from %d to %d:\n", low, high); |
| 902 | |
| 903 | display_trace (low, high); |
| 904 | |
| 905 | printf_filtered ("End of trace dump.\n"); |
| 906 | gdb_flush (gdb_stdout); |
| 907 | } |
| 908 | |
| 909 | static void |
| 910 | display_trace (low, high) |
| 911 | int low, high; |
| 912 | { |
| 913 | int i, count, trace_show_source, first, suppress; |
| 914 | CORE_ADDR next_address; |
| 915 | |
| 916 | trace_show_source = default_trace_show_source; |
| 917 | if (!have_full_symbols () && !have_partial_symbols()) |
| 918 | { |
| 919 | trace_show_source = 0; |
| 920 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); |
| 921 | printf_filtered ("Trace will not display any source.\n"); |
| 922 | } |
| 923 | |
| 924 | first = 1; |
| 925 | suppress = 0; |
| 926 | for (i = low; i < high; ++i) |
| 927 | { |
| 928 | next_address = trace_data.addrs[i]; |
| 929 | count = trace_data.counts[i]; |
| 930 | while (count-- > 0) |
| 931 | { |
| 932 | QUIT; |
| 933 | if (trace_show_source) |
| 934 | { |
| 935 | struct symtab_and_line sal, sal_prev; |
| 936 | |
| 937 | sal_prev = find_pc_line (next_address - 4, 0); |
| 938 | sal = find_pc_line (next_address, 0); |
| 939 | |
| 940 | if (sal.symtab) |
| 941 | { |
| 942 | if (first || sal.line != sal_prev.line) |
| 943 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); |
| 944 | suppress = 0; |
| 945 | } |
| 946 | else |
| 947 | { |
| 948 | if (!suppress) |
| 949 | /* FIXME-32x64--assumes sal.pc fits in long. */ |
| 950 | printf_filtered ("No source file for address %s.\n", |
| 951 | local_hex_string((unsigned long) sal.pc)); |
| 952 | suppress = 1; |
| 953 | } |
| 954 | } |
| 955 | first = 0; |
| 956 | print_address (next_address, gdb_stdout); |
| 957 | printf_filtered (":"); |
| 958 | printf_filtered ("\t"); |
| 959 | wrap_here (" "); |
| 960 | next_address = next_address + print_insn (next_address, gdb_stdout); |
| 961 | printf_filtered ("\n"); |
| 962 | gdb_flush (gdb_stdout); |
| 963 | } |
| 964 | } |
| 965 | } |
| 966 | |
| 967 | extern void (*target_resume_hook) PARAMS ((void)); |
| 968 | extern void (*target_wait_loop_hook) PARAMS ((void)); |
| 969 | |
| 970 | void |
| 971 | _initialize_d10v_tdep () |
| 972 | { |
| 973 | tm_print_insn = print_insn_d10v; |
| 974 | |
| 975 | target_resume_hook = d10v_eva_prepare_to_trace; |
| 976 | target_wait_loop_hook = d10v_eva_get_trace_data; |
| 977 | |
| 978 | add_com ("regs", class_vars, show_regs, "Print all registers"); |
| 979 | |
| 980 | add_com ("trace", class_support, trace_command, |
| 981 | "Enable tracing of instruction execution."); |
| 982 | |
| 983 | add_com ("untrace", class_support, untrace_command, |
| 984 | "Disable tracing of instruction execution."); |
| 985 | |
| 986 | add_com ("tdisassemble", class_vars, tdisassemble_command, |
| 987 | "Disassemble the trace buffer.\n\ |
| 988 | Two optional arguments specify a range of trace buffer entries\n\ |
| 989 | as reported by info trace (NOT addresses!)."); |
| 990 | |
| 991 | add_info ("trace", trace_info, |
| 992 | "Display info about the trace data buffer."); |
| 993 | |
| 994 | add_show_from_set (add_set_cmd ("tracedisplay", no_class, |
| 995 | var_integer, (char *)&trace_display, |
| 996 | "Set automatic display of trace.\n", &setlist), |
| 997 | &showlist); |
| 998 | add_show_from_set (add_set_cmd ("tracesource", no_class, |
| 999 | var_integer, (char *)&default_trace_show_source, |
| 1000 | "Set display of source code with trace.\n", &setlist), |
| 1001 | &showlist); |
| 1002 | |
| 1003 | } |