| 1 | /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger. |
| 2 | |
| 3 | Copyright (C) 2002-2014 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include <string.h> |
| 22 | #include "inferior.h" |
| 23 | #include "gdbcore.h" |
| 24 | #include "arch-utils.h" |
| 25 | #include "regcache.h" |
| 26 | #include "frame.h" |
| 27 | #include "frame-unwind.h" |
| 28 | #include "frame-base.h" |
| 29 | #include "trad-frame.h" |
| 30 | #include "dis-asm.h" |
| 31 | #include "gdb_assert.h" |
| 32 | #include "sim-regno.h" |
| 33 | #include "gdb/sim-frv.h" |
| 34 | #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */ |
| 35 | #include "symtab.h" |
| 36 | #include "elf-bfd.h" |
| 37 | #include "elf/frv.h" |
| 38 | #include "osabi.h" |
| 39 | #include "infcall.h" |
| 40 | #include "solib.h" |
| 41 | #include "frv-tdep.h" |
| 42 | #include "objfiles.h" |
| 43 | |
| 44 | extern void _initialize_frv_tdep (void); |
| 45 | |
| 46 | struct frv_unwind_cache /* was struct frame_extra_info */ |
| 47 | { |
| 48 | /* The previous frame's inner-most stack address. Used as this |
| 49 | frame ID's stack_addr. */ |
| 50 | CORE_ADDR prev_sp; |
| 51 | |
| 52 | /* The frame's base, optionally used by the high-level debug info. */ |
| 53 | CORE_ADDR base; |
| 54 | |
| 55 | /* Table indicating the location of each and every register. */ |
| 56 | struct trad_frame_saved_reg *saved_regs; |
| 57 | }; |
| 58 | |
| 59 | /* A structure describing a particular variant of the FRV. |
| 60 | We allocate and initialize one of these structures when we create |
| 61 | the gdbarch object for a variant. |
| 62 | |
| 63 | At the moment, all the FR variants we support differ only in which |
| 64 | registers are present; the portable code of GDB knows that |
| 65 | registers whose names are the empty string don't exist, so the |
| 66 | `register_names' array captures all the per-variant information we |
| 67 | need. |
| 68 | |
| 69 | in the future, if we need to have per-variant maps for raw size, |
| 70 | virtual type, etc., we should replace register_names with an array |
| 71 | of structures, each of which gives all the necessary info for one |
| 72 | register. Don't stick parallel arrays in here --- that's so |
| 73 | Fortran. */ |
| 74 | struct gdbarch_tdep |
| 75 | { |
| 76 | /* Which ABI is in use? */ |
| 77 | enum frv_abi frv_abi; |
| 78 | |
| 79 | /* How many general-purpose registers does this variant have? */ |
| 80 | int num_gprs; |
| 81 | |
| 82 | /* How many floating-point registers does this variant have? */ |
| 83 | int num_fprs; |
| 84 | |
| 85 | /* How many hardware watchpoints can it support? */ |
| 86 | int num_hw_watchpoints; |
| 87 | |
| 88 | /* How many hardware breakpoints can it support? */ |
| 89 | int num_hw_breakpoints; |
| 90 | |
| 91 | /* Register names. */ |
| 92 | char **register_names; |
| 93 | }; |
| 94 | |
| 95 | /* Return the FR-V ABI associated with GDBARCH. */ |
| 96 | enum frv_abi |
| 97 | frv_abi (struct gdbarch *gdbarch) |
| 98 | { |
| 99 | return gdbarch_tdep (gdbarch)->frv_abi; |
| 100 | } |
| 101 | |
| 102 | /* Fetch the interpreter and executable loadmap addresses (for shared |
| 103 | library support) for the FDPIC ABI. Return 0 if successful, -1 if |
| 104 | not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */ |
| 105 | int |
| 106 | frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr, |
| 107 | CORE_ADDR *exec_addr) |
| 108 | { |
| 109 | if (frv_abi (gdbarch) != FRV_ABI_FDPIC) |
| 110 | return -1; |
| 111 | else |
| 112 | { |
| 113 | struct regcache *regcache = get_current_regcache (); |
| 114 | |
| 115 | if (interp_addr != NULL) |
| 116 | { |
| 117 | ULONGEST val; |
| 118 | regcache_cooked_read_unsigned (regcache, |
| 119 | fdpic_loadmap_interp_regnum, &val); |
| 120 | *interp_addr = val; |
| 121 | } |
| 122 | if (exec_addr != NULL) |
| 123 | { |
| 124 | ULONGEST val; |
| 125 | regcache_cooked_read_unsigned (regcache, |
| 126 | fdpic_loadmap_exec_regnum, &val); |
| 127 | *exec_addr = val; |
| 128 | } |
| 129 | return 0; |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | /* Allocate a new variant structure, and set up default values for all |
| 134 | the fields. */ |
| 135 | static struct gdbarch_tdep * |
| 136 | new_variant (void) |
| 137 | { |
| 138 | struct gdbarch_tdep *var; |
| 139 | int r; |
| 140 | |
| 141 | var = xmalloc (sizeof (*var)); |
| 142 | memset (var, 0, sizeof (*var)); |
| 143 | |
| 144 | var->frv_abi = FRV_ABI_EABI; |
| 145 | var->num_gprs = 64; |
| 146 | var->num_fprs = 64; |
| 147 | var->num_hw_watchpoints = 0; |
| 148 | var->num_hw_breakpoints = 0; |
| 149 | |
| 150 | /* By default, don't supply any general-purpose or floating-point |
| 151 | register names. */ |
| 152 | var->register_names |
| 153 | = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs) |
| 154 | * sizeof (char *)); |
| 155 | for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++) |
| 156 | var->register_names[r] = ""; |
| 157 | |
| 158 | /* Do, however, supply default names for the known special-purpose |
| 159 | registers. */ |
| 160 | |
| 161 | var->register_names[pc_regnum] = "pc"; |
| 162 | var->register_names[lr_regnum] = "lr"; |
| 163 | var->register_names[lcr_regnum] = "lcr"; |
| 164 | |
| 165 | var->register_names[psr_regnum] = "psr"; |
| 166 | var->register_names[ccr_regnum] = "ccr"; |
| 167 | var->register_names[cccr_regnum] = "cccr"; |
| 168 | var->register_names[tbr_regnum] = "tbr"; |
| 169 | |
| 170 | /* Debug registers. */ |
| 171 | var->register_names[brr_regnum] = "brr"; |
| 172 | var->register_names[dbar0_regnum] = "dbar0"; |
| 173 | var->register_names[dbar1_regnum] = "dbar1"; |
| 174 | var->register_names[dbar2_regnum] = "dbar2"; |
| 175 | var->register_names[dbar3_regnum] = "dbar3"; |
| 176 | |
| 177 | /* iacc0 (Only found on MB93405.) */ |
| 178 | var->register_names[iacc0h_regnum] = "iacc0h"; |
| 179 | var->register_names[iacc0l_regnum] = "iacc0l"; |
| 180 | var->register_names[iacc0_regnum] = "iacc0"; |
| 181 | |
| 182 | /* fsr0 (Found on FR555 and FR501.) */ |
| 183 | var->register_names[fsr0_regnum] = "fsr0"; |
| 184 | |
| 185 | /* acc0 - acc7. The architecture provides for the possibility of many |
| 186 | more (up to 64 total), but we don't want to make that big of a hole |
| 187 | in the G packet. If we need more in the future, we'll add them |
| 188 | elsewhere. */ |
| 189 | for (r = acc0_regnum; r <= acc7_regnum; r++) |
| 190 | { |
| 191 | char *buf; |
| 192 | buf = xstrprintf ("acc%d", r - acc0_regnum); |
| 193 | var->register_names[r] = buf; |
| 194 | } |
| 195 | |
| 196 | /* accg0 - accg7: These are one byte registers. The remote protocol |
| 197 | provides the raw values packed four into a slot. accg0123 and |
| 198 | accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively. |
| 199 | We don't provide names for accg0123 and accg4567 since the user will |
| 200 | likely not want to see these raw values. */ |
| 201 | |
| 202 | for (r = accg0_regnum; r <= accg7_regnum; r++) |
| 203 | { |
| 204 | char *buf; |
| 205 | buf = xstrprintf ("accg%d", r - accg0_regnum); |
| 206 | var->register_names[r] = buf; |
| 207 | } |
| 208 | |
| 209 | /* msr0 and msr1. */ |
| 210 | |
| 211 | var->register_names[msr0_regnum] = "msr0"; |
| 212 | var->register_names[msr1_regnum] = "msr1"; |
| 213 | |
| 214 | /* gner and fner registers. */ |
| 215 | var->register_names[gner0_regnum] = "gner0"; |
| 216 | var->register_names[gner1_regnum] = "gner1"; |
| 217 | var->register_names[fner0_regnum] = "fner0"; |
| 218 | var->register_names[fner1_regnum] = "fner1"; |
| 219 | |
| 220 | return var; |
| 221 | } |
| 222 | |
| 223 | |
| 224 | /* Indicate that the variant VAR has NUM_GPRS general-purpose |
| 225 | registers, and fill in the names array appropriately. */ |
| 226 | static void |
| 227 | set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs) |
| 228 | { |
| 229 | int r; |
| 230 | |
| 231 | var->num_gprs = num_gprs; |
| 232 | |
| 233 | for (r = 0; r < num_gprs; ++r) |
| 234 | { |
| 235 | char buf[20]; |
| 236 | |
| 237 | xsnprintf (buf, sizeof (buf), "gr%d", r); |
| 238 | var->register_names[first_gpr_regnum + r] = xstrdup (buf); |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | |
| 243 | /* Indicate that the variant VAR has NUM_FPRS floating-point |
| 244 | registers, and fill in the names array appropriately. */ |
| 245 | static void |
| 246 | set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs) |
| 247 | { |
| 248 | int r; |
| 249 | |
| 250 | var->num_fprs = num_fprs; |
| 251 | |
| 252 | for (r = 0; r < num_fprs; ++r) |
| 253 | { |
| 254 | char buf[20]; |
| 255 | |
| 256 | xsnprintf (buf, sizeof (buf), "fr%d", r); |
| 257 | var->register_names[first_fpr_regnum + r] = xstrdup (buf); |
| 258 | } |
| 259 | } |
| 260 | |
| 261 | static void |
| 262 | set_variant_abi_fdpic (struct gdbarch_tdep *var) |
| 263 | { |
| 264 | var->frv_abi = FRV_ABI_FDPIC; |
| 265 | var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec"); |
| 266 | var->register_names[fdpic_loadmap_interp_regnum] |
| 267 | = xstrdup ("loadmap_interp"); |
| 268 | } |
| 269 | |
| 270 | static void |
| 271 | set_variant_scratch_registers (struct gdbarch_tdep *var) |
| 272 | { |
| 273 | var->register_names[scr0_regnum] = xstrdup ("scr0"); |
| 274 | var->register_names[scr1_regnum] = xstrdup ("scr1"); |
| 275 | var->register_names[scr2_regnum] = xstrdup ("scr2"); |
| 276 | var->register_names[scr3_regnum] = xstrdup ("scr3"); |
| 277 | } |
| 278 | |
| 279 | static const char * |
| 280 | frv_register_name (struct gdbarch *gdbarch, int reg) |
| 281 | { |
| 282 | if (reg < 0) |
| 283 | return "?toosmall?"; |
| 284 | if (reg >= frv_num_regs + frv_num_pseudo_regs) |
| 285 | return "?toolarge?"; |
| 286 | |
| 287 | return gdbarch_tdep (gdbarch)->register_names[reg]; |
| 288 | } |
| 289 | |
| 290 | |
| 291 | static struct type * |
| 292 | frv_register_type (struct gdbarch *gdbarch, int reg) |
| 293 | { |
| 294 | if (reg >= first_fpr_regnum && reg <= last_fpr_regnum) |
| 295 | return builtin_type (gdbarch)->builtin_float; |
| 296 | else if (reg == iacc0_regnum) |
| 297 | return builtin_type (gdbarch)->builtin_int64; |
| 298 | else |
| 299 | return builtin_type (gdbarch)->builtin_int32; |
| 300 | } |
| 301 | |
| 302 | static enum register_status |
| 303 | frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
| 304 | int reg, gdb_byte *buffer) |
| 305 | { |
| 306 | enum register_status status; |
| 307 | |
| 308 | if (reg == iacc0_regnum) |
| 309 | { |
| 310 | status = regcache_raw_read (regcache, iacc0h_regnum, buffer); |
| 311 | if (status == REG_VALID) |
| 312 | status = regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); |
| 313 | } |
| 314 | else if (accg0_regnum <= reg && reg <= accg7_regnum) |
| 315 | { |
| 316 | /* The accg raw registers have four values in each slot with the |
| 317 | lowest register number occupying the first byte. */ |
| 318 | |
| 319 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; |
| 320 | int byte_num = (reg - accg0_regnum) % 4; |
| 321 | gdb_byte buf[4]; |
| 322 | |
| 323 | status = regcache_raw_read (regcache, raw_regnum, buf); |
| 324 | if (status == REG_VALID) |
| 325 | { |
| 326 | memset (buffer, 0, 4); |
| 327 | /* FR-V is big endian, so put the requested byte in the |
| 328 | first byte of the buffer allocated to hold the |
| 329 | pseudo-register. */ |
| 330 | buffer[0] = buf[byte_num]; |
| 331 | } |
| 332 | } |
| 333 | else |
| 334 | gdb_assert_not_reached ("invalid pseudo register number"); |
| 335 | |
| 336 | return status; |
| 337 | } |
| 338 | |
| 339 | static void |
| 340 | frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 341 | int reg, const gdb_byte *buffer) |
| 342 | { |
| 343 | if (reg == iacc0_regnum) |
| 344 | { |
| 345 | regcache_raw_write (regcache, iacc0h_regnum, buffer); |
| 346 | regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); |
| 347 | } |
| 348 | else if (accg0_regnum <= reg && reg <= accg7_regnum) |
| 349 | { |
| 350 | /* The accg raw registers have four values in each slot with the |
| 351 | lowest register number occupying the first byte. */ |
| 352 | |
| 353 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; |
| 354 | int byte_num = (reg - accg0_regnum) % 4; |
| 355 | gdb_byte buf[4]; |
| 356 | |
| 357 | regcache_raw_read (regcache, raw_regnum, buf); |
| 358 | buf[byte_num] = ((bfd_byte *) buffer)[0]; |
| 359 | regcache_raw_write (regcache, raw_regnum, buf); |
| 360 | } |
| 361 | } |
| 362 | |
| 363 | static int |
| 364 | frv_register_sim_regno (struct gdbarch *gdbarch, int reg) |
| 365 | { |
| 366 | static const int spr_map[] = |
| 367 | { |
| 368 | H_SPR_PSR, /* psr_regnum */ |
| 369 | H_SPR_CCR, /* ccr_regnum */ |
| 370 | H_SPR_CCCR, /* cccr_regnum */ |
| 371 | -1, /* fdpic_loadmap_exec_regnum */ |
| 372 | -1, /* fdpic_loadmap_interp_regnum */ |
| 373 | -1, /* 134 */ |
| 374 | H_SPR_TBR, /* tbr_regnum */ |
| 375 | H_SPR_BRR, /* brr_regnum */ |
| 376 | H_SPR_DBAR0, /* dbar0_regnum */ |
| 377 | H_SPR_DBAR1, /* dbar1_regnum */ |
| 378 | H_SPR_DBAR2, /* dbar2_regnum */ |
| 379 | H_SPR_DBAR3, /* dbar3_regnum */ |
| 380 | H_SPR_SCR0, /* scr0_regnum */ |
| 381 | H_SPR_SCR1, /* scr1_regnum */ |
| 382 | H_SPR_SCR2, /* scr2_regnum */ |
| 383 | H_SPR_SCR3, /* scr3_regnum */ |
| 384 | H_SPR_LR, /* lr_regnum */ |
| 385 | H_SPR_LCR, /* lcr_regnum */ |
| 386 | H_SPR_IACC0H, /* iacc0h_regnum */ |
| 387 | H_SPR_IACC0L, /* iacc0l_regnum */ |
| 388 | H_SPR_FSR0, /* fsr0_regnum */ |
| 389 | /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */ |
| 390 | -1, /* acc0_regnum */ |
| 391 | -1, /* acc1_regnum */ |
| 392 | -1, /* acc2_regnum */ |
| 393 | -1, /* acc3_regnum */ |
| 394 | -1, /* acc4_regnum */ |
| 395 | -1, /* acc5_regnum */ |
| 396 | -1, /* acc6_regnum */ |
| 397 | -1, /* acc7_regnum */ |
| 398 | -1, /* acc0123_regnum */ |
| 399 | -1, /* acc4567_regnum */ |
| 400 | H_SPR_MSR0, /* msr0_regnum */ |
| 401 | H_SPR_MSR1, /* msr1_regnum */ |
| 402 | H_SPR_GNER0, /* gner0_regnum */ |
| 403 | H_SPR_GNER1, /* gner1_regnum */ |
| 404 | H_SPR_FNER0, /* fner0_regnum */ |
| 405 | H_SPR_FNER1, /* fner1_regnum */ |
| 406 | }; |
| 407 | |
| 408 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
| 409 | |
| 410 | if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) |
| 411 | return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; |
| 412 | else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum) |
| 413 | return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM; |
| 414 | else if (pc_regnum == reg) |
| 415 | return SIM_FRV_PC_REGNUM; |
| 416 | else if (reg >= first_spr_regnum |
| 417 | && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0])) |
| 418 | { |
| 419 | int spr_reg_offset = spr_map[reg - first_spr_regnum]; |
| 420 | |
| 421 | if (spr_reg_offset < 0) |
| 422 | return SIM_REGNO_DOES_NOT_EXIST; |
| 423 | else |
| 424 | return SIM_FRV_SPR0_REGNUM + spr_reg_offset; |
| 425 | } |
| 426 | |
| 427 | internal_error (__FILE__, __LINE__, _("Bad register number %d"), reg); |
| 428 | } |
| 429 | |
| 430 | static const unsigned char * |
| 431 | frv_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenp) |
| 432 | { |
| 433 | static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01}; |
| 434 | *lenp = sizeof (breakpoint); |
| 435 | return breakpoint; |
| 436 | } |
| 437 | |
| 438 | /* Define the maximum number of instructions which may be packed into a |
| 439 | bundle (VLIW instruction). */ |
| 440 | static const int max_instrs_per_bundle = 8; |
| 441 | |
| 442 | /* Define the size (in bytes) of an FR-V instruction. */ |
| 443 | static const int frv_instr_size = 4; |
| 444 | |
| 445 | /* Adjust a breakpoint's address to account for the FR-V architecture's |
| 446 | constraint that a break instruction must not appear as any but the |
| 447 | first instruction in the bundle. */ |
| 448 | static CORE_ADDR |
| 449 | frv_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
| 450 | { |
| 451 | int count = max_instrs_per_bundle; |
| 452 | CORE_ADDR addr = bpaddr - frv_instr_size; |
| 453 | CORE_ADDR func_start = get_pc_function_start (bpaddr); |
| 454 | |
| 455 | /* Find the end of the previous packing sequence. This will be indicated |
| 456 | by either attempting to access some inaccessible memory or by finding |
| 457 | an instruction word whose packing bit is set to one. */ |
| 458 | while (count-- > 0 && addr >= func_start) |
| 459 | { |
| 460 | gdb_byte instr[frv_instr_size]; |
| 461 | int status; |
| 462 | |
| 463 | status = target_read_memory (addr, instr, sizeof instr); |
| 464 | |
| 465 | if (status != 0) |
| 466 | break; |
| 467 | |
| 468 | /* This is a big endian architecture, so byte zero will have most |
| 469 | significant byte. The most significant bit of this byte is the |
| 470 | packing bit. */ |
| 471 | if (instr[0] & 0x80) |
| 472 | break; |
| 473 | |
| 474 | addr -= frv_instr_size; |
| 475 | } |
| 476 | |
| 477 | if (count > 0) |
| 478 | bpaddr = addr + frv_instr_size; |
| 479 | |
| 480 | return bpaddr; |
| 481 | } |
| 482 | |
| 483 | |
| 484 | /* Return true if REG is a caller-saves ("scratch") register, |
| 485 | false otherwise. */ |
| 486 | static int |
| 487 | is_caller_saves_reg (int reg) |
| 488 | { |
| 489 | return ((4 <= reg && reg <= 7) |
| 490 | || (14 <= reg && reg <= 15) |
| 491 | || (32 <= reg && reg <= 47)); |
| 492 | } |
| 493 | |
| 494 | |
| 495 | /* Return true if REG is a callee-saves register, false otherwise. */ |
| 496 | static int |
| 497 | is_callee_saves_reg (int reg) |
| 498 | { |
| 499 | return ((16 <= reg && reg <= 31) |
| 500 | || (48 <= reg && reg <= 63)); |
| 501 | } |
| 502 | |
| 503 | |
| 504 | /* Return true if REG is an argument register, false otherwise. */ |
| 505 | static int |
| 506 | is_argument_reg (int reg) |
| 507 | { |
| 508 | return (8 <= reg && reg <= 13); |
| 509 | } |
| 510 | |
| 511 | /* Scan an FR-V prologue, starting at PC, until frame->PC. |
| 512 | If FRAME is non-zero, fill in its saved_regs with appropriate addresses. |
| 513 | We assume FRAME's saved_regs array has already been allocated and cleared. |
| 514 | Return the first PC value after the prologue. |
| 515 | |
| 516 | Note that, for unoptimized code, we almost don't need this function |
| 517 | at all; all arguments and locals live on the stack, so we just need |
| 518 | the FP to find everything. The catch: structures passed by value |
| 519 | have their addresses living in registers; they're never spilled to |
| 520 | the stack. So if you ever want to be able to get to these |
| 521 | arguments in any frame but the top, you'll need to do this serious |
| 522 | prologue analysis. */ |
| 523 | static CORE_ADDR |
| 524 | frv_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
| 525 | struct frame_info *this_frame, |
| 526 | struct frv_unwind_cache *info) |
| 527 | { |
| 528 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 529 | |
| 530 | /* When writing out instruction bitpatterns, we use the following |
| 531 | letters to label instruction fields: |
| 532 | P - The parallel bit. We don't use this. |
| 533 | J - The register number of GRj in the instruction description. |
| 534 | K - The register number of GRk in the instruction description. |
| 535 | I - The register number of GRi. |
| 536 | S - a signed imediate offset. |
| 537 | U - an unsigned immediate offset. |
| 538 | |
| 539 | The dots below the numbers indicate where hex digit boundaries |
| 540 | fall, to make it easier to check the numbers. */ |
| 541 | |
| 542 | /* Non-zero iff we've seen the instruction that initializes the |
| 543 | frame pointer for this function's frame. */ |
| 544 | int fp_set = 0; |
| 545 | |
| 546 | /* If fp_set is non_zero, then this is the distance from |
| 547 | the stack pointer to frame pointer: fp = sp + fp_offset. */ |
| 548 | int fp_offset = 0; |
| 549 | |
| 550 | /* Total size of frame prior to any alloca operations. */ |
| 551 | int framesize = 0; |
| 552 | |
| 553 | /* Flag indicating if lr has been saved on the stack. */ |
| 554 | int lr_saved_on_stack = 0; |
| 555 | |
| 556 | /* The number of the general-purpose register we saved the return |
| 557 | address ("link register") in, or -1 if we haven't moved it yet. */ |
| 558 | int lr_save_reg = -1; |
| 559 | |
| 560 | /* Offset (from sp) at which lr has been saved on the stack. */ |
| 561 | |
| 562 | int lr_sp_offset = 0; |
| 563 | |
| 564 | /* If gr_saved[i] is non-zero, then we've noticed that general |
| 565 | register i has been saved at gr_sp_offset[i] from the stack |
| 566 | pointer. */ |
| 567 | char gr_saved[64]; |
| 568 | int gr_sp_offset[64]; |
| 569 | |
| 570 | /* The address of the most recently scanned prologue instruction. */ |
| 571 | CORE_ADDR last_prologue_pc; |
| 572 | |
| 573 | /* The address of the next instruction. */ |
| 574 | CORE_ADDR next_pc; |
| 575 | |
| 576 | /* The upper bound to of the pc values to scan. */ |
| 577 | CORE_ADDR lim_pc; |
| 578 | |
| 579 | memset (gr_saved, 0, sizeof (gr_saved)); |
| 580 | |
| 581 | last_prologue_pc = pc; |
| 582 | |
| 583 | /* Try to compute an upper limit (on how far to scan) based on the |
| 584 | line number info. */ |
| 585 | lim_pc = skip_prologue_using_sal (gdbarch, pc); |
| 586 | /* If there's no line number info, lim_pc will be 0. In that case, |
| 587 | set the limit to be 100 instructions away from pc. Hopefully, this |
| 588 | will be far enough away to account for the entire prologue. Don't |
| 589 | worry about overshooting the end of the function. The scan loop |
| 590 | below contains some checks to avoid scanning unreasonably far. */ |
| 591 | if (lim_pc == 0) |
| 592 | lim_pc = pc + 400; |
| 593 | |
| 594 | /* If we have a frame, we don't want to scan past the frame's pc. This |
| 595 | will catch those cases where the pc is in the prologue. */ |
| 596 | if (this_frame) |
| 597 | { |
| 598 | CORE_ADDR frame_pc = get_frame_pc (this_frame); |
| 599 | if (frame_pc < lim_pc) |
| 600 | lim_pc = frame_pc; |
| 601 | } |
| 602 | |
| 603 | /* Scan the prologue. */ |
| 604 | while (pc < lim_pc) |
| 605 | { |
| 606 | gdb_byte buf[frv_instr_size]; |
| 607 | LONGEST op; |
| 608 | |
| 609 | if (target_read_memory (pc, buf, sizeof buf) != 0) |
| 610 | break; |
| 611 | op = extract_signed_integer (buf, sizeof buf, byte_order); |
| 612 | |
| 613 | next_pc = pc + 4; |
| 614 | |
| 615 | /* The tests in this chain of ifs should be in order of |
| 616 | decreasing selectivity, so that more particular patterns get |
| 617 | to fire before less particular patterns. */ |
| 618 | |
| 619 | /* Some sort of control transfer instruction: stop scanning prologue. |
| 620 | Integer Conditional Branch: |
| 621 | X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX |
| 622 | Floating-point / media Conditional Branch: |
| 623 | X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX |
| 624 | LCR Conditional Branch to LR |
| 625 | X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX |
| 626 | Integer conditional Branches to LR |
| 627 | X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX |
| 628 | X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX |
| 629 | Floating-point/Media Branches to LR |
| 630 | X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX |
| 631 | X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX |
| 632 | Jump and Link |
| 633 | X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX |
| 634 | X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX |
| 635 | Call |
| 636 | X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX |
| 637 | Return from Trap |
| 638 | X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX |
| 639 | Integer Conditional Trap |
| 640 | X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX |
| 641 | X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX |
| 642 | Floating-point /media Conditional Trap |
| 643 | X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX |
| 644 | X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX |
| 645 | Break |
| 646 | X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX |
| 647 | Media Trap |
| 648 | X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */ |
| 649 | if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */ |
| 650 | || (op & 0x01f80000) == 0x00300000 /* Jump and Link */ |
| 651 | || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */ |
| 652 | || (op & 0x01f80000) == 0x00700000) /* Trap immediate */ |
| 653 | { |
| 654 | /* Stop scanning; not in prologue any longer. */ |
| 655 | break; |
| 656 | } |
| 657 | |
| 658 | /* Loading something from memory into fp probably means that |
| 659 | we're in the epilogue. Stop scanning the prologue. |
| 660 | ld @(GRi, GRk), fp |
| 661 | X 000010 0000010 XXXXXX 000100 XXXXXX |
| 662 | ldi @(GRi, d12), fp |
| 663 | X 000010 0110010 XXXXXX XXXXXXXXXXXX */ |
| 664 | else if ((op & 0x7ffc0fc0) == 0x04080100 |
| 665 | || (op & 0x7ffc0000) == 0x04c80000) |
| 666 | { |
| 667 | break; |
| 668 | } |
| 669 | |
| 670 | /* Setting the FP from the SP: |
| 671 | ori sp, 0, fp |
| 672 | P 000010 0100010 000001 000000000000 = 0x04881000 |
| 673 | 0 111111 1111111 111111 111111111111 = 0x7fffffff |
| 674 | . . . . . . . . |
| 675 | We treat this as part of the prologue. */ |
| 676 | else if ((op & 0x7fffffff) == 0x04881000) |
| 677 | { |
| 678 | fp_set = 1; |
| 679 | fp_offset = 0; |
| 680 | last_prologue_pc = next_pc; |
| 681 | } |
| 682 | |
| 683 | /* Move the link register to the scratch register grJ, before saving: |
| 684 | movsg lr, grJ |
| 685 | P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0 |
| 686 | 0 111111 1111111 111111 111111 000000 = 0x7fffffc0 |
| 687 | . . . . . . . . |
| 688 | We treat this as part of the prologue. */ |
| 689 | else if ((op & 0x7fffffc0) == 0x080d01c0) |
| 690 | { |
| 691 | int gr_j = op & 0x3f; |
| 692 | |
| 693 | /* If we're moving it to a scratch register, that's fine. */ |
| 694 | if (is_caller_saves_reg (gr_j)) |
| 695 | { |
| 696 | lr_save_reg = gr_j; |
| 697 | last_prologue_pc = next_pc; |
| 698 | } |
| 699 | } |
| 700 | |
| 701 | /* To save multiple callee-saves registers on the stack, at |
| 702 | offset zero: |
| 703 | |
| 704 | std grK,@(sp,gr0) |
| 705 | P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0 |
| 706 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff |
| 707 | |
| 708 | stq grK,@(sp,gr0) |
| 709 | P KKKKKK 0000011 000001 000100 000000 = 0x000c1100 |
| 710 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff |
| 711 | . . . . . . . . |
| 712 | We treat this as part of the prologue, and record the register's |
| 713 | saved address in the frame structure. */ |
| 714 | else if ((op & 0x01ffffff) == 0x000c10c0 |
| 715 | || (op & 0x01ffffff) == 0x000c1100) |
| 716 | { |
| 717 | int gr_k = ((op >> 25) & 0x3f); |
| 718 | int ope = ((op >> 6) & 0x3f); |
| 719 | int count; |
| 720 | int i; |
| 721 | |
| 722 | /* Is it an std or an stq? */ |
| 723 | if (ope == 0x03) |
| 724 | count = 2; |
| 725 | else |
| 726 | count = 4; |
| 727 | |
| 728 | /* Is it really a callee-saves register? */ |
| 729 | if (is_callee_saves_reg (gr_k)) |
| 730 | { |
| 731 | for (i = 0; i < count; i++) |
| 732 | { |
| 733 | gr_saved[gr_k + i] = 1; |
| 734 | gr_sp_offset[gr_k + i] = 4 * i; |
| 735 | } |
| 736 | last_prologue_pc = next_pc; |
| 737 | } |
| 738 | } |
| 739 | |
| 740 | /* Adjusting the stack pointer. (The stack pointer is GR1.) |
| 741 | addi sp, S, sp |
| 742 | P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000 |
| 743 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 |
| 744 | . . . . . . . . |
| 745 | We treat this as part of the prologue. */ |
| 746 | else if ((op & 0x7ffff000) == 0x02401000) |
| 747 | { |
| 748 | if (framesize == 0) |
| 749 | { |
| 750 | /* Sign-extend the twelve-bit field. |
| 751 | (Isn't there a better way to do this?) */ |
| 752 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; |
| 753 | |
| 754 | framesize -= s; |
| 755 | last_prologue_pc = pc; |
| 756 | } |
| 757 | else |
| 758 | { |
| 759 | /* If the prologue is being adjusted again, we've |
| 760 | likely gone too far; i.e. we're probably in the |
| 761 | epilogue. */ |
| 762 | break; |
| 763 | } |
| 764 | } |
| 765 | |
| 766 | /* Setting the FP to a constant distance from the SP: |
| 767 | addi sp, S, fp |
| 768 | P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000 |
| 769 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 |
| 770 | . . . . . . . . |
| 771 | We treat this as part of the prologue. */ |
| 772 | else if ((op & 0x7ffff000) == 0x04401000) |
| 773 | { |
| 774 | /* Sign-extend the twelve-bit field. |
| 775 | (Isn't there a better way to do this?) */ |
| 776 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; |
| 777 | fp_set = 1; |
| 778 | fp_offset = s; |
| 779 | last_prologue_pc = pc; |
| 780 | } |
| 781 | |
| 782 | /* To spill an argument register to a scratch register: |
| 783 | ori GRi, 0, GRk |
| 784 | P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000 |
| 785 | 0 000000 1111111 000000 111111111111 = 0x01fc0fff |
| 786 | . . . . . . . . |
| 787 | For the time being, we treat this as a prologue instruction, |
| 788 | assuming that GRi is an argument register. This one's kind |
| 789 | of suspicious, because it seems like it could be part of a |
| 790 | legitimate body instruction. But we only come here when the |
| 791 | source info wasn't helpful, so we have to do the best we can. |
| 792 | Hopefully once GCC and GDB agree on how to emit line number |
| 793 | info for prologues, then this code will never come into play. */ |
| 794 | else if ((op & 0x01fc0fff) == 0x00880000) |
| 795 | { |
| 796 | int gr_i = ((op >> 12) & 0x3f); |
| 797 | |
| 798 | /* Make sure that the source is an arg register; if it is, we'll |
| 799 | treat it as a prologue instruction. */ |
| 800 | if (is_argument_reg (gr_i)) |
| 801 | last_prologue_pc = next_pc; |
| 802 | } |
| 803 | |
| 804 | /* To spill 16-bit values to the stack: |
| 805 | sthi GRk, @(fp, s) |
| 806 | P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000 |
| 807 | 0 000000 1111111 111111 000000000000 = 0x01fff000 |
| 808 | . . . . . . . . |
| 809 | And for 8-bit values, we use STB instructions. |
| 810 | stbi GRk, @(fp, s) |
| 811 | P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000 |
| 812 | 0 000000 1111111 111111 000000000000 = 0x01fff000 |
| 813 | . . . . . . . . |
| 814 | We check that GRk is really an argument register, and treat |
| 815 | all such as part of the prologue. */ |
| 816 | else if ( (op & 0x01fff000) == 0x01442000 |
| 817 | || (op & 0x01fff000) == 0x01402000) |
| 818 | { |
| 819 | int gr_k = ((op >> 25) & 0x3f); |
| 820 | |
| 821 | /* Make sure that GRk is really an argument register; treat |
| 822 | it as a prologue instruction if so. */ |
| 823 | if (is_argument_reg (gr_k)) |
| 824 | last_prologue_pc = next_pc; |
| 825 | } |
| 826 | |
| 827 | /* To save multiple callee-saves register on the stack, at a |
| 828 | non-zero offset: |
| 829 | |
| 830 | stdi GRk, @(sp, s) |
| 831 | P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000 |
| 832 | 0 000000 1111111 111111 000000000000 = 0x01fff000 |
| 833 | . . . . . . . . |
| 834 | stqi GRk, @(sp, s) |
| 835 | P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000 |
| 836 | 0 000000 1111111 111111 000000000000 = 0x01fff000 |
| 837 | . . . . . . . . |
| 838 | We treat this as part of the prologue, and record the register's |
| 839 | saved address in the frame structure. */ |
| 840 | else if ((op & 0x01fff000) == 0x014c1000 |
| 841 | || (op & 0x01fff000) == 0x01501000) |
| 842 | { |
| 843 | int gr_k = ((op >> 25) & 0x3f); |
| 844 | int count; |
| 845 | int i; |
| 846 | |
| 847 | /* Is it a stdi or a stqi? */ |
| 848 | if ((op & 0x01fff000) == 0x014c1000) |
| 849 | count = 2; |
| 850 | else |
| 851 | count = 4; |
| 852 | |
| 853 | /* Is it really a callee-saves register? */ |
| 854 | if (is_callee_saves_reg (gr_k)) |
| 855 | { |
| 856 | /* Sign-extend the twelve-bit field. |
| 857 | (Isn't there a better way to do this?) */ |
| 858 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; |
| 859 | |
| 860 | for (i = 0; i < count; i++) |
| 861 | { |
| 862 | gr_saved[gr_k + i] = 1; |
| 863 | gr_sp_offset[gr_k + i] = s + (4 * i); |
| 864 | } |
| 865 | last_prologue_pc = next_pc; |
| 866 | } |
| 867 | } |
| 868 | |
| 869 | /* Storing any kind of integer register at any constant offset |
| 870 | from any other register. |
| 871 | |
| 872 | st GRk, @(GRi, gr0) |
| 873 | P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080 |
| 874 | 0 000000 1111111 000000 111111 111111 = 0x01fc0fff |
| 875 | . . . . . . . . |
| 876 | sti GRk, @(GRi, d12) |
| 877 | P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000 |
| 878 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 |
| 879 | . . . . . . . . |
| 880 | These could be almost anything, but a lot of prologue |
| 881 | instructions fall into this pattern, so let's decode the |
| 882 | instruction once, and then work at a higher level. */ |
| 883 | else if (((op & 0x01fc0fff) == 0x000c0080) |
| 884 | || ((op & 0x01fc0000) == 0x01480000)) |
| 885 | { |
| 886 | int gr_k = ((op >> 25) & 0x3f); |
| 887 | int gr_i = ((op >> 12) & 0x3f); |
| 888 | int offset; |
| 889 | |
| 890 | /* Are we storing with gr0 as an offset, or using an |
| 891 | immediate value? */ |
| 892 | if ((op & 0x01fc0fff) == 0x000c0080) |
| 893 | offset = 0; |
| 894 | else |
| 895 | offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; |
| 896 | |
| 897 | /* If the address isn't relative to the SP or FP, it's not a |
| 898 | prologue instruction. */ |
| 899 | if (gr_i != sp_regnum && gr_i != fp_regnum) |
| 900 | { |
| 901 | /* Do nothing; not a prologue instruction. */ |
| 902 | } |
| 903 | |
| 904 | /* Saving the old FP in the new frame (relative to the SP). */ |
| 905 | else if (gr_k == fp_regnum && gr_i == sp_regnum) |
| 906 | { |
| 907 | gr_saved[fp_regnum] = 1; |
| 908 | gr_sp_offset[fp_regnum] = offset; |
| 909 | last_prologue_pc = next_pc; |
| 910 | } |
| 911 | |
| 912 | /* Saving callee-saves register(s) on the stack, relative to |
| 913 | the SP. */ |
| 914 | else if (gr_i == sp_regnum |
| 915 | && is_callee_saves_reg (gr_k)) |
| 916 | { |
| 917 | gr_saved[gr_k] = 1; |
| 918 | if (gr_i == sp_regnum) |
| 919 | gr_sp_offset[gr_k] = offset; |
| 920 | else |
| 921 | gr_sp_offset[gr_k] = offset + fp_offset; |
| 922 | last_prologue_pc = next_pc; |
| 923 | } |
| 924 | |
| 925 | /* Saving the scratch register holding the return address. */ |
| 926 | else if (lr_save_reg != -1 |
| 927 | && gr_k == lr_save_reg) |
| 928 | { |
| 929 | lr_saved_on_stack = 1; |
| 930 | if (gr_i == sp_regnum) |
| 931 | lr_sp_offset = offset; |
| 932 | else |
| 933 | lr_sp_offset = offset + fp_offset; |
| 934 | last_prologue_pc = next_pc; |
| 935 | } |
| 936 | |
| 937 | /* Spilling int-sized arguments to the stack. */ |
| 938 | else if (is_argument_reg (gr_k)) |
| 939 | last_prologue_pc = next_pc; |
| 940 | } |
| 941 | pc = next_pc; |
| 942 | } |
| 943 | |
| 944 | if (this_frame && info) |
| 945 | { |
| 946 | int i; |
| 947 | ULONGEST this_base; |
| 948 | |
| 949 | /* If we know the relationship between the stack and frame |
| 950 | pointers, record the addresses of the registers we noticed. |
| 951 | Note that we have to do this as a separate step at the end, |
| 952 | because instructions may save relative to the SP, but we need |
| 953 | their addresses relative to the FP. */ |
| 954 | if (fp_set) |
| 955 | this_base = get_frame_register_unsigned (this_frame, fp_regnum); |
| 956 | else |
| 957 | this_base = get_frame_register_unsigned (this_frame, sp_regnum); |
| 958 | |
| 959 | for (i = 0; i < 64; i++) |
| 960 | if (gr_saved[i]) |
| 961 | info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i]; |
| 962 | |
| 963 | info->prev_sp = this_base - fp_offset + framesize; |
| 964 | info->base = this_base; |
| 965 | |
| 966 | /* If LR was saved on the stack, record its location. */ |
| 967 | if (lr_saved_on_stack) |
| 968 | info->saved_regs[lr_regnum].addr |
| 969 | = this_base - fp_offset + lr_sp_offset; |
| 970 | |
| 971 | /* The call instruction moves the caller's PC in the callee's LR. |
| 972 | Since this is an unwind, do the reverse. Copy the location of LR |
| 973 | into PC (the address / regnum) so that a request for PC will be |
| 974 | converted into a request for the LR. */ |
| 975 | info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum]; |
| 976 | |
| 977 | /* Save the previous frame's computed SP value. */ |
| 978 | trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp); |
| 979 | } |
| 980 | |
| 981 | return last_prologue_pc; |
| 982 | } |
| 983 | |
| 984 | |
| 985 | static CORE_ADDR |
| 986 | frv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 987 | { |
| 988 | CORE_ADDR func_addr, func_end, new_pc; |
| 989 | |
| 990 | new_pc = pc; |
| 991 | |
| 992 | /* If the line table has entry for a line *within* the function |
| 993 | (i.e., not in the prologue, and not past the end), then that's |
| 994 | our location. */ |
| 995 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 996 | { |
| 997 | struct symtab_and_line sal; |
| 998 | |
| 999 | sal = find_pc_line (func_addr, 0); |
| 1000 | |
| 1001 | if (sal.line != 0 && sal.end < func_end) |
| 1002 | { |
| 1003 | new_pc = sal.end; |
| 1004 | } |
| 1005 | } |
| 1006 | |
| 1007 | /* The FR-V prologue is at least five instructions long (twenty bytes). |
| 1008 | If we didn't find a real source location past that, then |
| 1009 | do a full analysis of the prologue. */ |
| 1010 | if (new_pc < pc + 20) |
| 1011 | new_pc = frv_analyze_prologue (gdbarch, pc, 0, 0); |
| 1012 | |
| 1013 | return new_pc; |
| 1014 | } |
| 1015 | |
| 1016 | |
| 1017 | /* Examine the instruction pointed to by PC. If it corresponds to |
| 1018 | a call to __main, return the address of the next instruction. |
| 1019 | Otherwise, return PC. */ |
| 1020 | |
| 1021 | static CORE_ADDR |
| 1022 | frv_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1023 | { |
| 1024 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1025 | gdb_byte buf[4]; |
| 1026 | unsigned long op; |
| 1027 | CORE_ADDR orig_pc = pc; |
| 1028 | |
| 1029 | if (target_read_memory (pc, buf, 4)) |
| 1030 | return pc; |
| 1031 | op = extract_unsigned_integer (buf, 4, byte_order); |
| 1032 | |
| 1033 | /* In PIC code, GR15 may be loaded from some offset off of FP prior |
| 1034 | to the call instruction. |
| 1035 | |
| 1036 | Skip over this instruction if present. It won't be present in |
| 1037 | non-PIC code, and even in PIC code, it might not be present. |
| 1038 | (This is due to the fact that GR15, the FDPIC register, already |
| 1039 | contains the correct value.) |
| 1040 | |
| 1041 | The general form of the LDI is given first, followed by the |
| 1042 | specific instruction with the GRi and GRk filled in as FP and |
| 1043 | GR15. |
| 1044 | |
| 1045 | ldi @(GRi, d12), GRk |
| 1046 | P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000 |
| 1047 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 |
| 1048 | . . . . . . . . |
| 1049 | ldi @(FP, d12), GR15 |
| 1050 | P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000 |
| 1051 | 0 001111 1111111 000010 000000000000 = 0x7ffff000 |
| 1052 | . . . . . . . . */ |
| 1053 | |
| 1054 | if ((op & 0x7ffff000) == 0x1ec82000) |
| 1055 | { |
| 1056 | pc += 4; |
| 1057 | if (target_read_memory (pc, buf, 4)) |
| 1058 | return orig_pc; |
| 1059 | op = extract_unsigned_integer (buf, 4, byte_order); |
| 1060 | } |
| 1061 | |
| 1062 | /* The format of an FRV CALL instruction is as follows: |
| 1063 | |
| 1064 | call label24 |
| 1065 | P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000 |
| 1066 | 0 000000 1111111 000000000000000000 = 0x01fc0000 |
| 1067 | . . . . . . . . |
| 1068 | |
| 1069 | where label24 is constructed by concatenating the H bits with the |
| 1070 | L bits. The call target is PC + (4 * sign_ext(label24)). */ |
| 1071 | |
| 1072 | if ((op & 0x01fc0000) == 0x003c0000) |
| 1073 | { |
| 1074 | LONGEST displ; |
| 1075 | CORE_ADDR call_dest; |
| 1076 | struct bound_minimal_symbol s; |
| 1077 | |
| 1078 | displ = ((op & 0xfe000000) >> 7) | (op & 0x0003ffff); |
| 1079 | if ((displ & 0x00800000) != 0) |
| 1080 | displ |= ~((LONGEST) 0x00ffffff); |
| 1081 | |
| 1082 | call_dest = pc + 4 * displ; |
| 1083 | s = lookup_minimal_symbol_by_pc (call_dest); |
| 1084 | |
| 1085 | if (s.minsym != NULL |
| 1086 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
| 1087 | && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) |
| 1088 | { |
| 1089 | pc += 4; |
| 1090 | return pc; |
| 1091 | } |
| 1092 | } |
| 1093 | return orig_pc; |
| 1094 | } |
| 1095 | |
| 1096 | |
| 1097 | static struct frv_unwind_cache * |
| 1098 | frv_frame_unwind_cache (struct frame_info *this_frame, |
| 1099 | void **this_prologue_cache) |
| 1100 | { |
| 1101 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1102 | struct frv_unwind_cache *info; |
| 1103 | |
| 1104 | if ((*this_prologue_cache)) |
| 1105 | return (*this_prologue_cache); |
| 1106 | |
| 1107 | info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); |
| 1108 | (*this_prologue_cache) = info; |
| 1109 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 1110 | |
| 1111 | /* Prologue analysis does the rest... */ |
| 1112 | frv_analyze_prologue (gdbarch, |
| 1113 | get_frame_func (this_frame), this_frame, info); |
| 1114 | |
| 1115 | return info; |
| 1116 | } |
| 1117 | |
| 1118 | static void |
| 1119 | frv_extract_return_value (struct type *type, struct regcache *regcache, |
| 1120 | gdb_byte *valbuf) |
| 1121 | { |
| 1122 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
| 1123 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1124 | int len = TYPE_LENGTH (type); |
| 1125 | |
| 1126 | if (len <= 4) |
| 1127 | { |
| 1128 | ULONGEST gpr8_val; |
| 1129 | regcache_cooked_read_unsigned (regcache, 8, &gpr8_val); |
| 1130 | store_unsigned_integer (valbuf, len, byte_order, gpr8_val); |
| 1131 | } |
| 1132 | else if (len == 8) |
| 1133 | { |
| 1134 | ULONGEST regval; |
| 1135 | |
| 1136 | regcache_cooked_read_unsigned (regcache, 8, ®val); |
| 1137 | store_unsigned_integer (valbuf, 4, byte_order, regval); |
| 1138 | regcache_cooked_read_unsigned (regcache, 9, ®val); |
| 1139 | store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, byte_order, regval); |
| 1140 | } |
| 1141 | else |
| 1142 | internal_error (__FILE__, __LINE__, |
| 1143 | _("Illegal return value length: %d"), len); |
| 1144 | } |
| 1145 | |
| 1146 | static CORE_ADDR |
| 1147 | frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 1148 | { |
| 1149 | /* Require dword alignment. */ |
| 1150 | return align_down (sp, 8); |
| 1151 | } |
| 1152 | |
| 1153 | static CORE_ADDR |
| 1154 | find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point) |
| 1155 | { |
| 1156 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1157 | CORE_ADDR descr; |
| 1158 | gdb_byte valbuf[4]; |
| 1159 | CORE_ADDR start_addr; |
| 1160 | |
| 1161 | /* If we can't find the function in the symbol table, then we assume |
| 1162 | that the function address is already in descriptor form. */ |
| 1163 | if (!find_pc_partial_function (entry_point, NULL, &start_addr, NULL) |
| 1164 | || entry_point != start_addr) |
| 1165 | return entry_point; |
| 1166 | |
| 1167 | descr = frv_fdpic_find_canonical_descriptor (entry_point); |
| 1168 | |
| 1169 | if (descr != 0) |
| 1170 | return descr; |
| 1171 | |
| 1172 | /* Construct a non-canonical descriptor from space allocated on |
| 1173 | the stack. */ |
| 1174 | |
| 1175 | descr = value_as_long (value_allocate_space_in_inferior (8)); |
| 1176 | store_unsigned_integer (valbuf, 4, byte_order, entry_point); |
| 1177 | write_memory (descr, valbuf, 4); |
| 1178 | store_unsigned_integer (valbuf, 4, byte_order, |
| 1179 | frv_fdpic_find_global_pointer (entry_point)); |
| 1180 | write_memory (descr + 4, valbuf, 4); |
| 1181 | return descr; |
| 1182 | } |
| 1183 | |
| 1184 | static CORE_ADDR |
| 1185 | frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr, |
| 1186 | struct target_ops *targ) |
| 1187 | { |
| 1188 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1189 | CORE_ADDR entry_point; |
| 1190 | CORE_ADDR got_address; |
| 1191 | |
| 1192 | entry_point = get_target_memory_unsigned (targ, addr, 4, byte_order); |
| 1193 | got_address = get_target_memory_unsigned (targ, addr + 4, 4, byte_order); |
| 1194 | |
| 1195 | if (got_address == frv_fdpic_find_global_pointer (entry_point)) |
| 1196 | return entry_point; |
| 1197 | else |
| 1198 | return addr; |
| 1199 | } |
| 1200 | |
| 1201 | static CORE_ADDR |
| 1202 | frv_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 1203 | struct regcache *regcache, CORE_ADDR bp_addr, |
| 1204 | int nargs, struct value **args, CORE_ADDR sp, |
| 1205 | int struct_return, CORE_ADDR struct_addr) |
| 1206 | { |
| 1207 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1208 | int argreg; |
| 1209 | int argnum; |
| 1210 | const gdb_byte *val; |
| 1211 | gdb_byte valbuf[4]; |
| 1212 | struct value *arg; |
| 1213 | struct type *arg_type; |
| 1214 | int len; |
| 1215 | enum type_code typecode; |
| 1216 | CORE_ADDR regval; |
| 1217 | int stack_space; |
| 1218 | int stack_offset; |
| 1219 | enum frv_abi abi = frv_abi (gdbarch); |
| 1220 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
| 1221 | |
| 1222 | #if 0 |
| 1223 | printf("Push %d args at sp = %x, struct_return=%d (%x)\n", |
| 1224 | nargs, (int) sp, struct_return, struct_addr); |
| 1225 | #endif |
| 1226 | |
| 1227 | stack_space = 0; |
| 1228 | for (argnum = 0; argnum < nargs; ++argnum) |
| 1229 | stack_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4); |
| 1230 | |
| 1231 | stack_space -= (6 * 4); |
| 1232 | if (stack_space > 0) |
| 1233 | sp -= stack_space; |
| 1234 | |
| 1235 | /* Make sure stack is dword aligned. */ |
| 1236 | sp = align_down (sp, 8); |
| 1237 | |
| 1238 | stack_offset = 0; |
| 1239 | |
| 1240 | argreg = 8; |
| 1241 | |
| 1242 | if (struct_return) |
| 1243 | regcache_cooked_write_unsigned (regcache, struct_return_regnum, |
| 1244 | struct_addr); |
| 1245 | |
| 1246 | for (argnum = 0; argnum < nargs; ++argnum) |
| 1247 | { |
| 1248 | arg = args[argnum]; |
| 1249 | arg_type = check_typedef (value_type (arg)); |
| 1250 | len = TYPE_LENGTH (arg_type); |
| 1251 | typecode = TYPE_CODE (arg_type); |
| 1252 | |
| 1253 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) |
| 1254 | { |
| 1255 | store_unsigned_integer (valbuf, 4, byte_order, |
| 1256 | value_address (arg)); |
| 1257 | typecode = TYPE_CODE_PTR; |
| 1258 | len = 4; |
| 1259 | val = valbuf; |
| 1260 | } |
| 1261 | else if (abi == FRV_ABI_FDPIC |
| 1262 | && len == 4 |
| 1263 | && typecode == TYPE_CODE_PTR |
| 1264 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) |
| 1265 | { |
| 1266 | /* The FDPIC ABI requires function descriptors to be passed instead |
| 1267 | of entry points. */ |
| 1268 | CORE_ADDR addr = extract_unsigned_integer |
| 1269 | (value_contents (arg), 4, byte_order); |
| 1270 | addr = find_func_descr (gdbarch, addr); |
| 1271 | store_unsigned_integer (valbuf, 4, byte_order, addr); |
| 1272 | typecode = TYPE_CODE_PTR; |
| 1273 | len = 4; |
| 1274 | val = valbuf; |
| 1275 | } |
| 1276 | else |
| 1277 | { |
| 1278 | val = value_contents (arg); |
| 1279 | } |
| 1280 | |
| 1281 | while (len > 0) |
| 1282 | { |
| 1283 | int partial_len = (len < 4 ? len : 4); |
| 1284 | |
| 1285 | if (argreg < 14) |
| 1286 | { |
| 1287 | regval = extract_unsigned_integer (val, partial_len, byte_order); |
| 1288 | #if 0 |
| 1289 | printf(" Argnum %d data %x -> reg %d\n", |
| 1290 | argnum, (int) regval, argreg); |
| 1291 | #endif |
| 1292 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
| 1293 | ++argreg; |
| 1294 | } |
| 1295 | else |
| 1296 | { |
| 1297 | #if 0 |
| 1298 | printf(" Argnum %d data %x -> offset %d (%x)\n", |
| 1299 | argnum, *((int *)val), stack_offset, |
| 1300 | (int) (sp + stack_offset)); |
| 1301 | #endif |
| 1302 | write_memory (sp + stack_offset, val, partial_len); |
| 1303 | stack_offset += align_up (partial_len, 4); |
| 1304 | } |
| 1305 | len -= partial_len; |
| 1306 | val += partial_len; |
| 1307 | } |
| 1308 | } |
| 1309 | |
| 1310 | /* Set the return address. For the frv, the return breakpoint is |
| 1311 | always at BP_ADDR. */ |
| 1312 | regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr); |
| 1313 | |
| 1314 | if (abi == FRV_ABI_FDPIC) |
| 1315 | { |
| 1316 | /* Set the GOT register for the FDPIC ABI. */ |
| 1317 | regcache_cooked_write_unsigned |
| 1318 | (regcache, first_gpr_regnum + 15, |
| 1319 | frv_fdpic_find_global_pointer (func_addr)); |
| 1320 | } |
| 1321 | |
| 1322 | /* Finally, update the SP register. */ |
| 1323 | regcache_cooked_write_unsigned (regcache, sp_regnum, sp); |
| 1324 | |
| 1325 | return sp; |
| 1326 | } |
| 1327 | |
| 1328 | static void |
| 1329 | frv_store_return_value (struct type *type, struct regcache *regcache, |
| 1330 | const gdb_byte *valbuf) |
| 1331 | { |
| 1332 | int len = TYPE_LENGTH (type); |
| 1333 | |
| 1334 | if (len <= 4) |
| 1335 | { |
| 1336 | bfd_byte val[4]; |
| 1337 | memset (val, 0, sizeof (val)); |
| 1338 | memcpy (val + (4 - len), valbuf, len); |
| 1339 | regcache_cooked_write (regcache, 8, val); |
| 1340 | } |
| 1341 | else if (len == 8) |
| 1342 | { |
| 1343 | regcache_cooked_write (regcache, 8, valbuf); |
| 1344 | regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4); |
| 1345 | } |
| 1346 | else |
| 1347 | internal_error (__FILE__, __LINE__, |
| 1348 | _("Don't know how to return a %d-byte value."), len); |
| 1349 | } |
| 1350 | |
| 1351 | static enum return_value_convention |
| 1352 | frv_return_value (struct gdbarch *gdbarch, struct value *function, |
| 1353 | struct type *valtype, struct regcache *regcache, |
| 1354 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 1355 | { |
| 1356 | int struct_return = TYPE_CODE (valtype) == TYPE_CODE_STRUCT |
| 1357 | || TYPE_CODE (valtype) == TYPE_CODE_UNION |
| 1358 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY; |
| 1359 | |
| 1360 | if (writebuf != NULL) |
| 1361 | { |
| 1362 | gdb_assert (!struct_return); |
| 1363 | frv_store_return_value (valtype, regcache, writebuf); |
| 1364 | } |
| 1365 | |
| 1366 | if (readbuf != NULL) |
| 1367 | { |
| 1368 | gdb_assert (!struct_return); |
| 1369 | frv_extract_return_value (valtype, regcache, readbuf); |
| 1370 | } |
| 1371 | |
| 1372 | if (struct_return) |
| 1373 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 1374 | else |
| 1375 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 1376 | } |
| 1377 | |
| 1378 | static CORE_ADDR |
| 1379 | frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1380 | { |
| 1381 | return frame_unwind_register_unsigned (next_frame, pc_regnum); |
| 1382 | } |
| 1383 | |
| 1384 | /* Given a GDB frame, determine the address of the calling function's |
| 1385 | frame. This will be used to create a new GDB frame struct. */ |
| 1386 | |
| 1387 | static void |
| 1388 | frv_frame_this_id (struct frame_info *this_frame, |
| 1389 | void **this_prologue_cache, struct frame_id *this_id) |
| 1390 | { |
| 1391 | struct frv_unwind_cache *info |
| 1392 | = frv_frame_unwind_cache (this_frame, this_prologue_cache); |
| 1393 | CORE_ADDR base; |
| 1394 | CORE_ADDR func; |
| 1395 | struct bound_minimal_symbol msym_stack; |
| 1396 | struct frame_id id; |
| 1397 | |
| 1398 | /* The FUNC is easy. */ |
| 1399 | func = get_frame_func (this_frame); |
| 1400 | |
| 1401 | /* Check if the stack is empty. */ |
| 1402 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); |
| 1403 | if (msym_stack.minsym && info->base == BMSYMBOL_VALUE_ADDRESS (msym_stack)) |
| 1404 | return; |
| 1405 | |
| 1406 | /* Hopefully the prologue analysis either correctly determined the |
| 1407 | frame's base (which is the SP from the previous frame), or set |
| 1408 | that base to "NULL". */ |
| 1409 | base = info->prev_sp; |
| 1410 | if (base == 0) |
| 1411 | return; |
| 1412 | |
| 1413 | id = frame_id_build (base, func); |
| 1414 | (*this_id) = id; |
| 1415 | } |
| 1416 | |
| 1417 | static struct value * |
| 1418 | frv_frame_prev_register (struct frame_info *this_frame, |
| 1419 | void **this_prologue_cache, int regnum) |
| 1420 | { |
| 1421 | struct frv_unwind_cache *info |
| 1422 | = frv_frame_unwind_cache (this_frame, this_prologue_cache); |
| 1423 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 1424 | } |
| 1425 | |
| 1426 | static const struct frame_unwind frv_frame_unwind = { |
| 1427 | NORMAL_FRAME, |
| 1428 | default_frame_unwind_stop_reason, |
| 1429 | frv_frame_this_id, |
| 1430 | frv_frame_prev_register, |
| 1431 | NULL, |
| 1432 | default_frame_sniffer |
| 1433 | }; |
| 1434 | |
| 1435 | static CORE_ADDR |
| 1436 | frv_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 1437 | { |
| 1438 | struct frv_unwind_cache *info |
| 1439 | = frv_frame_unwind_cache (this_frame, this_cache); |
| 1440 | return info->base; |
| 1441 | } |
| 1442 | |
| 1443 | static const struct frame_base frv_frame_base = { |
| 1444 | &frv_frame_unwind, |
| 1445 | frv_frame_base_address, |
| 1446 | frv_frame_base_address, |
| 1447 | frv_frame_base_address |
| 1448 | }; |
| 1449 | |
| 1450 | static CORE_ADDR |
| 1451 | frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1452 | { |
| 1453 | return frame_unwind_register_unsigned (next_frame, sp_regnum); |
| 1454 | } |
| 1455 | |
| 1456 | |
| 1457 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
| 1458 | frame. The frame ID's base needs to match the TOS value saved by |
| 1459 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ |
| 1460 | |
| 1461 | static struct frame_id |
| 1462 | frv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 1463 | { |
| 1464 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, sp_regnum); |
| 1465 | return frame_id_build (sp, get_frame_pc (this_frame)); |
| 1466 | } |
| 1467 | |
| 1468 | static struct gdbarch * |
| 1469 | frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 1470 | { |
| 1471 | struct gdbarch *gdbarch; |
| 1472 | struct gdbarch_tdep *var; |
| 1473 | int elf_flags = 0; |
| 1474 | |
| 1475 | /* Check to see if we've already built an appropriate architecture |
| 1476 | object for this executable. */ |
| 1477 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 1478 | if (arches) |
| 1479 | return arches->gdbarch; |
| 1480 | |
| 1481 | /* Select the right tdep structure for this variant. */ |
| 1482 | var = new_variant (); |
| 1483 | switch (info.bfd_arch_info->mach) |
| 1484 | { |
| 1485 | case bfd_mach_frv: |
| 1486 | case bfd_mach_frvsimple: |
| 1487 | case bfd_mach_fr500: |
| 1488 | case bfd_mach_frvtomcat: |
| 1489 | case bfd_mach_fr550: |
| 1490 | set_variant_num_gprs (var, 64); |
| 1491 | set_variant_num_fprs (var, 64); |
| 1492 | break; |
| 1493 | |
| 1494 | case bfd_mach_fr400: |
| 1495 | case bfd_mach_fr450: |
| 1496 | set_variant_num_gprs (var, 32); |
| 1497 | set_variant_num_fprs (var, 32); |
| 1498 | break; |
| 1499 | |
| 1500 | default: |
| 1501 | /* Never heard of this variant. */ |
| 1502 | return 0; |
| 1503 | } |
| 1504 | |
| 1505 | /* Extract the ELF flags, if available. */ |
| 1506 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 1507 | elf_flags = elf_elfheader (info.abfd)->e_flags; |
| 1508 | |
| 1509 | if (elf_flags & EF_FRV_FDPIC) |
| 1510 | set_variant_abi_fdpic (var); |
| 1511 | |
| 1512 | if (elf_flags & EF_FRV_CPU_FR450) |
| 1513 | set_variant_scratch_registers (var); |
| 1514 | |
| 1515 | gdbarch = gdbarch_alloc (&info, var); |
| 1516 | |
| 1517 | set_gdbarch_short_bit (gdbarch, 16); |
| 1518 | set_gdbarch_int_bit (gdbarch, 32); |
| 1519 | set_gdbarch_long_bit (gdbarch, 32); |
| 1520 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 1521 | set_gdbarch_float_bit (gdbarch, 32); |
| 1522 | set_gdbarch_double_bit (gdbarch, 64); |
| 1523 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 1524 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 1525 | |
| 1526 | set_gdbarch_num_regs (gdbarch, frv_num_regs); |
| 1527 | set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs); |
| 1528 | |
| 1529 | set_gdbarch_sp_regnum (gdbarch, sp_regnum); |
| 1530 | set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum); |
| 1531 | set_gdbarch_pc_regnum (gdbarch, pc_regnum); |
| 1532 | |
| 1533 | set_gdbarch_register_name (gdbarch, frv_register_name); |
| 1534 | set_gdbarch_register_type (gdbarch, frv_register_type); |
| 1535 | set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno); |
| 1536 | |
| 1537 | set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read); |
| 1538 | set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write); |
| 1539 | |
| 1540 | set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue); |
| 1541 | set_gdbarch_skip_main_prologue (gdbarch, frv_skip_main_prologue); |
| 1542 | set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc); |
| 1543 | set_gdbarch_adjust_breakpoint_address |
| 1544 | (gdbarch, frv_adjust_breakpoint_address); |
| 1545 | |
| 1546 | set_gdbarch_return_value (gdbarch, frv_return_value); |
| 1547 | |
| 1548 | /* Frame stuff. */ |
| 1549 | set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc); |
| 1550 | set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp); |
| 1551 | set_gdbarch_frame_align (gdbarch, frv_frame_align); |
| 1552 | frame_base_set_default (gdbarch, &frv_frame_base); |
| 1553 | /* We set the sniffer lower down after the OSABI hooks have been |
| 1554 | established. */ |
| 1555 | |
| 1556 | /* Settings for calling functions in the inferior. */ |
| 1557 | set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call); |
| 1558 | set_gdbarch_dummy_id (gdbarch, frv_dummy_id); |
| 1559 | |
| 1560 | /* Settings that should be unnecessary. */ |
| 1561 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 1562 | |
| 1563 | /* Hardware watchpoint / breakpoint support. */ |
| 1564 | switch (info.bfd_arch_info->mach) |
| 1565 | { |
| 1566 | case bfd_mach_frv: |
| 1567 | case bfd_mach_frvsimple: |
| 1568 | case bfd_mach_fr500: |
| 1569 | case bfd_mach_frvtomcat: |
| 1570 | /* fr500-style hardware debugging support. */ |
| 1571 | var->num_hw_watchpoints = 4; |
| 1572 | var->num_hw_breakpoints = 4; |
| 1573 | break; |
| 1574 | |
| 1575 | case bfd_mach_fr400: |
| 1576 | case bfd_mach_fr450: |
| 1577 | /* fr400-style hardware debugging support. */ |
| 1578 | var->num_hw_watchpoints = 2; |
| 1579 | var->num_hw_breakpoints = 4; |
| 1580 | break; |
| 1581 | |
| 1582 | default: |
| 1583 | /* Otherwise, assume we don't have hardware debugging support. */ |
| 1584 | var->num_hw_watchpoints = 0; |
| 1585 | var->num_hw_breakpoints = 0; |
| 1586 | break; |
| 1587 | } |
| 1588 | |
| 1589 | set_gdbarch_print_insn (gdbarch, print_insn_frv); |
| 1590 | if (frv_abi (gdbarch) == FRV_ABI_FDPIC) |
| 1591 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
| 1592 | frv_convert_from_func_ptr_addr); |
| 1593 | |
| 1594 | set_solib_ops (gdbarch, &frv_so_ops); |
| 1595 | |
| 1596 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 1597 | gdbarch_init_osabi (info, gdbarch); |
| 1598 | |
| 1599 | /* Set the fallback (prologue based) frame sniffer. */ |
| 1600 | frame_unwind_append_unwinder (gdbarch, &frv_frame_unwind); |
| 1601 | |
| 1602 | /* Enable TLS support. */ |
| 1603 | set_gdbarch_fetch_tls_load_module_address (gdbarch, |
| 1604 | frv_fetch_objfile_link_map); |
| 1605 | |
| 1606 | return gdbarch; |
| 1607 | } |
| 1608 | |
| 1609 | void |
| 1610 | _initialize_frv_tdep (void) |
| 1611 | { |
| 1612 | register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init); |
| 1613 | } |