| 1 | /* GNU/Linux/AArch64 specific low level interface, for the remote server for |
| 2 | GDB. |
| 3 | |
| 4 | Copyright (C) 2009-2014 Free Software Foundation, Inc. |
| 5 | Contributed by ARM Ltd. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 3 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 | |
| 22 | #include "server.h" |
| 23 | #include "linux-low.h" |
| 24 | #include "elf/common.h" |
| 25 | |
| 26 | #include <signal.h> |
| 27 | #include <sys/user.h> |
| 28 | #include <sys/ptrace.h> |
| 29 | #include <asm/ptrace.h> |
| 30 | #include <sys/uio.h> |
| 31 | |
| 32 | #include "gdb_proc_service.h" |
| 33 | |
| 34 | /* Defined in auto-generated files. */ |
| 35 | void init_registers_aarch64 (void); |
| 36 | extern const struct target_desc *tdesc_aarch64; |
| 37 | |
| 38 | #ifdef HAVE_SYS_REG_H |
| 39 | #include <sys/reg.h> |
| 40 | #endif |
| 41 | |
| 42 | #define AARCH64_X_REGS_NUM 31 |
| 43 | #define AARCH64_V_REGS_NUM 32 |
| 44 | #define AARCH64_X0_REGNO 0 |
| 45 | #define AARCH64_SP_REGNO 31 |
| 46 | #define AARCH64_PC_REGNO 32 |
| 47 | #define AARCH64_CPSR_REGNO 33 |
| 48 | #define AARCH64_V0_REGNO 34 |
| 49 | |
| 50 | #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM) |
| 51 | |
| 52 | static int |
| 53 | aarch64_regmap [] = |
| 54 | { |
| 55 | /* These offsets correspond to GET/SETREGSET */ |
| 56 | /* x0... */ |
| 57 | 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, |
| 58 | 8*8, 9*8, 10*8, 11*8, 12*8, 13*8, 14*8, 15*8, |
| 59 | 16*8, 17*8, 18*8, 19*8, 20*8, 21*8, 22*8, 23*8, |
| 60 | 24*8, 25*8, 26*8, 27*8, 28*8, |
| 61 | 29*8, |
| 62 | 30*8, /* x30 lr */ |
| 63 | 31*8, /* x31 sp */ |
| 64 | 32*8, /* pc */ |
| 65 | 33*8, /* cpsr 4 bytes!*/ |
| 66 | |
| 67 | /* FP register offsets correspond to GET/SETFPREGSET */ |
| 68 | 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16, |
| 69 | 8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16, |
| 70 | 16*16, 17*16, 18*16, 19*16, 20*16, 21*16, 22*16, 23*16, |
| 71 | 24*16, 25*16, 26*16, 27*16, 28*16, 29*16, 30*16, 31*16 |
| 72 | }; |
| 73 | |
| 74 | /* Here starts the macro definitions, data structures, and code for |
| 75 | the hardware breakpoint and hardware watchpoint support. The |
| 76 | following is the abbreviations that are used frequently in the code |
| 77 | and comment: |
| 78 | |
| 79 | hw - hardware |
| 80 | bp - breakpoint |
| 81 | wp - watchpoint */ |
| 82 | |
| 83 | /* Maximum number of hardware breakpoint and watchpoint registers. |
| 84 | Neither of these values may exceed the width of dr_changed_t |
| 85 | measured in bits. */ |
| 86 | |
| 87 | #define AARCH64_HBP_MAX_NUM 16 |
| 88 | #define AARCH64_HWP_MAX_NUM 16 |
| 89 | |
| 90 | /* Alignment requirement in bytes of hardware breakpoint and |
| 91 | watchpoint address. This is the requirement for the addresses that |
| 92 | can be written to the hardware breakpoint/watchpoint value |
| 93 | registers. The kernel currently does not do any alignment on |
| 94 | addresses when receiving a writing request (via ptrace call) to |
| 95 | these debug registers, and it will reject any address that is |
| 96 | unaligned. |
| 97 | Some limited support has been provided in this gdbserver port for |
| 98 | unaligned watchpoints, so that from a gdb user point of view, an |
| 99 | unaligned watchpoint can still be set. This is achieved by |
| 100 | minimally enlarging the watched area to meet the alignment |
| 101 | requirement, and if necessary, splitting the watchpoint over |
| 102 | several hardware watchpoint registers. */ |
| 103 | |
| 104 | #define AARCH64_HBP_ALIGNMENT 4 |
| 105 | #define AARCH64_HWP_ALIGNMENT 8 |
| 106 | |
| 107 | /* The maximum length of a memory region that can be watched by one |
| 108 | hardware watchpoint register. */ |
| 109 | |
| 110 | #define AARCH64_HWP_MAX_LEN_PER_REG 8 |
| 111 | |
| 112 | /* Each bit of a variable of this type is used to indicate whether a |
| 113 | hardware breakpoint or watchpoint setting has been changed since |
| 114 | the last updating. Bit N corresponds to the Nth hardware |
| 115 | breakpoint or watchpoint setting which is managed in |
| 116 | aarch64_debug_reg_state. Where N is valid between 0 and the total |
| 117 | number of the hardware breakpoint or watchpoint debug registers |
| 118 | minus 1. When the bit N is 1, it indicates the corresponding |
| 119 | breakpoint or watchpoint setting is changed, and thus the |
| 120 | corresponding hardware debug register needs to be updated via the |
| 121 | ptrace interface. |
| 122 | |
| 123 | In the per-thread arch-specific data area, we define two such |
| 124 | variables for per-thread hardware breakpoint and watchpoint |
| 125 | settings respectively. |
| 126 | |
| 127 | This type is part of the mechanism which helps reduce the number of |
| 128 | ptrace calls to the kernel, i.e. avoid asking the kernel to write |
| 129 | to the debug registers with unchanged values. */ |
| 130 | |
| 131 | typedef unsigned long long dr_changed_t; |
| 132 | |
| 133 | /* Set each of the lower M bits of X to 1; assert X is wide enough. */ |
| 134 | |
| 135 | #define DR_MARK_ALL_CHANGED(x, m) \ |
| 136 | do \ |
| 137 | { \ |
| 138 | gdb_assert (sizeof ((x)) * 8 >= (m)); \ |
| 139 | (x) = (((dr_changed_t)1 << (m)) - 1); \ |
| 140 | } while (0) |
| 141 | |
| 142 | #define DR_MARK_N_CHANGED(x, n) \ |
| 143 | do \ |
| 144 | { \ |
| 145 | (x) |= ((dr_changed_t)1 << (n)); \ |
| 146 | } while (0) |
| 147 | |
| 148 | #define DR_CLEAR_CHANGED(x) \ |
| 149 | do \ |
| 150 | { \ |
| 151 | (x) = 0; \ |
| 152 | } while (0) |
| 153 | |
| 154 | #define DR_HAS_CHANGED(x) ((x) != 0) |
| 155 | #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n))) |
| 156 | |
| 157 | /* Structure for managing the hardware breakpoint/watchpoint resources. |
| 158 | DR_ADDR_* stores the address, DR_CTRL_* stores the control register |
| 159 | content, and DR_REF_COUNT_* counts the numbers of references to the |
| 160 | corresponding bp/wp, by which way the limited hardware resources |
| 161 | are not wasted on duplicated bp/wp settings (though so far gdb has |
| 162 | done a good job by not sending duplicated bp/wp requests). */ |
| 163 | |
| 164 | struct aarch64_debug_reg_state |
| 165 | { |
| 166 | /* hardware breakpoint */ |
| 167 | CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]; |
| 168 | unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]; |
| 169 | unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]; |
| 170 | |
| 171 | /* hardware watchpoint */ |
| 172 | CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]; |
| 173 | unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]; |
| 174 | unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]; |
| 175 | }; |
| 176 | |
| 177 | /* Per-process arch-specific data we want to keep. */ |
| 178 | |
| 179 | struct arch_process_info |
| 180 | { |
| 181 | /* Hardware breakpoint/watchpoint data. |
| 182 | The reason for them to be per-process rather than per-thread is |
| 183 | due to the lack of information in the gdbserver environment; |
| 184 | gdbserver is not told that whether a requested hardware |
| 185 | breakpoint/watchpoint is thread specific or not, so it has to set |
| 186 | each hw bp/wp for every thread in the current process. The |
| 187 | higher level bp/wp management in gdb will resume a thread if a hw |
| 188 | bp/wp trap is not expected for it. Since the hw bp/wp setting is |
| 189 | same for each thread, it is reasonable for the data to live here. |
| 190 | */ |
| 191 | struct aarch64_debug_reg_state debug_reg_state; |
| 192 | }; |
| 193 | |
| 194 | /* Per-thread arch-specific data we want to keep. */ |
| 195 | |
| 196 | struct arch_lwp_info |
| 197 | { |
| 198 | /* When bit N is 1, it indicates the Nth hardware breakpoint or |
| 199 | watchpoint register pair needs to be updated when the thread is |
| 200 | resumed; see aarch64_linux_prepare_to_resume. */ |
| 201 | dr_changed_t dr_changed_bp; |
| 202 | dr_changed_t dr_changed_wp; |
| 203 | }; |
| 204 | |
| 205 | /* Number of hardware breakpoints/watchpoints the target supports. |
| 206 | They are initialized with values obtained via the ptrace calls |
| 207 | with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */ |
| 208 | |
| 209 | static int aarch64_num_bp_regs; |
| 210 | static int aarch64_num_wp_regs; |
| 211 | |
| 212 | static int |
| 213 | aarch64_cannot_store_register (int regno) |
| 214 | { |
| 215 | return regno >= AARCH64_NUM_REGS; |
| 216 | } |
| 217 | |
| 218 | static int |
| 219 | aarch64_cannot_fetch_register (int regno) |
| 220 | { |
| 221 | return regno >= AARCH64_NUM_REGS; |
| 222 | } |
| 223 | |
| 224 | static void |
| 225 | aarch64_fill_gregset (struct regcache *regcache, void *buf) |
| 226 | { |
| 227 | struct user_pt_regs *regset = buf; |
| 228 | int i; |
| 229 | |
| 230 | for (i = 0; i < AARCH64_X_REGS_NUM; i++) |
| 231 | collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]); |
| 232 | collect_register (regcache, AARCH64_SP_REGNO, ®set->sp); |
| 233 | collect_register (regcache, AARCH64_PC_REGNO, ®set->pc); |
| 234 | collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate); |
| 235 | } |
| 236 | |
| 237 | static void |
| 238 | aarch64_store_gregset (struct regcache *regcache, const void *buf) |
| 239 | { |
| 240 | const struct user_pt_regs *regset = buf; |
| 241 | int i; |
| 242 | |
| 243 | for (i = 0; i < AARCH64_X_REGS_NUM; i++) |
| 244 | supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]); |
| 245 | supply_register (regcache, AARCH64_SP_REGNO, ®set->sp); |
| 246 | supply_register (regcache, AARCH64_PC_REGNO, ®set->pc); |
| 247 | supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate); |
| 248 | } |
| 249 | |
| 250 | static void |
| 251 | aarch64_fill_fpregset (struct regcache *regcache, void *buf) |
| 252 | { |
| 253 | struct user_fpsimd_state *regset = buf; |
| 254 | int i; |
| 255 | |
| 256 | for (i = 0; i < AARCH64_V_REGS_NUM; i++) |
| 257 | collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]); |
| 258 | } |
| 259 | |
| 260 | static void |
| 261 | aarch64_store_fpregset (struct regcache *regcache, const void *buf) |
| 262 | { |
| 263 | const struct user_fpsimd_state *regset = buf; |
| 264 | int i; |
| 265 | |
| 266 | for (i = 0; i < AARCH64_V_REGS_NUM; i++) |
| 267 | supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]); |
| 268 | } |
| 269 | |
| 270 | /* Debugging of hardware breakpoint/watchpoint support. */ |
| 271 | extern int debug_hw_points; |
| 272 | |
| 273 | /* Enable miscellaneous debugging output. The name is historical - it |
| 274 | was originally used to debug LinuxThreads support. */ |
| 275 | extern int debug_threads; |
| 276 | |
| 277 | static CORE_ADDR |
| 278 | aarch64_get_pc (struct regcache *regcache) |
| 279 | { |
| 280 | unsigned long pc; |
| 281 | |
| 282 | collect_register_by_name (regcache, "pc", &pc); |
| 283 | if (debug_threads) |
| 284 | debug_printf ("stop pc is %08lx\n", pc); |
| 285 | return pc; |
| 286 | } |
| 287 | |
| 288 | static void |
| 289 | aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc) |
| 290 | { |
| 291 | unsigned long newpc = pc; |
| 292 | supply_register_by_name (regcache, "pc", &newpc); |
| 293 | } |
| 294 | |
| 295 | /* Correct in either endianness. */ |
| 296 | |
| 297 | #define aarch64_breakpoint_len 4 |
| 298 | |
| 299 | static const unsigned long aarch64_breakpoint = 0x00800011; |
| 300 | |
| 301 | static int |
| 302 | aarch64_breakpoint_at (CORE_ADDR where) |
| 303 | { |
| 304 | unsigned long insn; |
| 305 | |
| 306 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); |
| 307 | if (insn == aarch64_breakpoint) |
| 308 | return 1; |
| 309 | |
| 310 | return 0; |
| 311 | } |
| 312 | |
| 313 | /* Print the values of the cached breakpoint/watchpoint registers. |
| 314 | This is enabled via the "set debug-hw-points" monitor command. */ |
| 315 | |
| 316 | static void |
| 317 | aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state, |
| 318 | const char *func, CORE_ADDR addr, |
| 319 | int len, enum target_hw_bp_type type) |
| 320 | { |
| 321 | int i; |
| 322 | |
| 323 | fprintf (stderr, "%s", func); |
| 324 | if (addr || len) |
| 325 | fprintf (stderr, " (addr=0x%08lx, len=%d, type=%s)", |
| 326 | (unsigned long) addr, len, |
| 327 | type == hw_write ? "hw-write-watchpoint" |
| 328 | : (type == hw_read ? "hw-read-watchpoint" |
| 329 | : (type == hw_access ? "hw-access-watchpoint" |
| 330 | : (type == hw_execute ? "hw-breakpoint" |
| 331 | : "??unknown??")))); |
| 332 | fprintf (stderr, ":\n"); |
| 333 | |
| 334 | fprintf (stderr, "\tBREAKPOINTs:\n"); |
| 335 | for (i = 0; i < aarch64_num_bp_regs; i++) |
| 336 | fprintf (stderr, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n", |
| 337 | i, paddress (state->dr_addr_bp[i]), |
| 338 | state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]); |
| 339 | |
| 340 | fprintf (stderr, "\tWATCHPOINTs:\n"); |
| 341 | for (i = 0; i < aarch64_num_wp_regs; i++) |
| 342 | fprintf (stderr, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n", |
| 343 | i, paddress (state->dr_addr_wp[i]), |
| 344 | state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]); |
| 345 | } |
| 346 | |
| 347 | static void |
| 348 | aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state) |
| 349 | { |
| 350 | int i; |
| 351 | |
| 352 | for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i) |
| 353 | { |
| 354 | state->dr_addr_bp[i] = 0; |
| 355 | state->dr_ctrl_bp[i] = 0; |
| 356 | state->dr_ref_count_bp[i] = 0; |
| 357 | } |
| 358 | |
| 359 | for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i) |
| 360 | { |
| 361 | state->dr_addr_wp[i] = 0; |
| 362 | state->dr_ctrl_wp[i] = 0; |
| 363 | state->dr_ref_count_wp[i] = 0; |
| 364 | } |
| 365 | } |
| 366 | |
| 367 | /* ptrace expects control registers to be formatted as follows: |
| 368 | |
| 369 | 31 13 5 3 1 0 |
| 370 | +--------------------------------+----------+------+------+----+ |
| 371 | | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN | |
| 372 | +--------------------------------+----------+------+------+----+ |
| 373 | |
| 374 | The TYPE field is ignored for breakpoints. */ |
| 375 | |
| 376 | #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1) |
| 377 | #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff) |
| 378 | |
| 379 | /* Utility function that returns the length in bytes of a watchpoint |
| 380 | according to the content of a hardware debug control register CTRL. |
| 381 | Note that the kernel currently only supports the following Byte |
| 382 | Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means |
| 383 | that for a hardware watchpoint, its valid length can only be 1 |
| 384 | byte, 2 bytes, 4 bytes or 8 bytes. */ |
| 385 | |
| 386 | static inline unsigned int |
| 387 | aarch64_watchpoint_length (unsigned int ctrl) |
| 388 | { |
| 389 | switch (DR_CONTROL_LENGTH (ctrl)) |
| 390 | { |
| 391 | case 0x01: |
| 392 | return 1; |
| 393 | case 0x03: |
| 394 | return 2; |
| 395 | case 0x0f: |
| 396 | return 4; |
| 397 | case 0xff: |
| 398 | return 8; |
| 399 | default: |
| 400 | return 0; |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | /* Given the hardware breakpoint or watchpoint type TYPE and its |
| 405 | length LEN, return the expected encoding for a hardware |
| 406 | breakpoint/watchpoint control register. */ |
| 407 | |
| 408 | static unsigned int |
| 409 | aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len) |
| 410 | { |
| 411 | unsigned int ctrl, ttype; |
| 412 | |
| 413 | /* type */ |
| 414 | switch (type) |
| 415 | { |
| 416 | case hw_write: |
| 417 | ttype = 2; |
| 418 | break; |
| 419 | case hw_read: |
| 420 | ttype = 1; |
| 421 | break; |
| 422 | case hw_access: |
| 423 | ttype = 3; |
| 424 | break; |
| 425 | case hw_execute: |
| 426 | ttype = 0; |
| 427 | break; |
| 428 | default: |
| 429 | perror_with_name (_("Unrecognized breakpoint/watchpoint type")); |
| 430 | } |
| 431 | |
| 432 | /* type */ |
| 433 | ctrl = ttype << 3; |
| 434 | /* length bitmask */ |
| 435 | ctrl |= ((1 << len) - 1) << 5; |
| 436 | /* enabled at el0 */ |
| 437 | ctrl |= (2 << 1) | 1; |
| 438 | |
| 439 | return ctrl; |
| 440 | } |
| 441 | |
| 442 | /* Addresses to be written to the hardware breakpoint and watchpoint |
| 443 | value registers need to be aligned; the alignment is 4-byte and |
| 444 | 8-type respectively. Linux kernel rejects any non-aligned address |
| 445 | it receives from the related ptrace call. Furthermore, the kernel |
| 446 | currently only supports the following Byte Address Select (BAS) |
| 447 | values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware |
| 448 | watchpoint to be accepted by the kernel (via ptrace call), its |
| 449 | valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes. |
| 450 | Despite these limitations, the unaligned watchpoint is supported in |
| 451 | this gdbserver port. |
| 452 | |
| 453 | Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */ |
| 454 | |
| 455 | static int |
| 456 | aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) |
| 457 | { |
| 458 | unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT |
| 459 | : AARCH64_HBP_ALIGNMENT; |
| 460 | |
| 461 | if (addr & (alignment - 1)) |
| 462 | return 0; |
| 463 | |
| 464 | if (len != 8 && len != 4 && len != 2 && len != 1) |
| 465 | return 0; |
| 466 | |
| 467 | return 1; |
| 468 | } |
| 469 | |
| 470 | /* Given the (potentially unaligned) watchpoint address in ADDR and |
| 471 | length in LEN, return the aligned address and aligned length in |
| 472 | *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned |
| 473 | aligned address and length will be valid to be written to the |
| 474 | hardware watchpoint value and control registers. See the comment |
| 475 | above aarch64_point_is_aligned for the information about the |
| 476 | alignment requirement. The given watchpoint may get truncated if |
| 477 | more than one hardware register is needed to cover the watched |
| 478 | region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the |
| 479 | address and length of the remaining part of the watchpoint (which |
| 480 | can be processed by calling this routine again to generate another |
| 481 | aligned address and length pair. |
| 482 | |
| 483 | Essentially, unaligned watchpoint is achieved by minimally |
| 484 | enlarging the watched area to meet the alignment requirement, and |
| 485 | if necessary, splitting the watchpoint over several hardware |
| 486 | watchpoint registers. The trade-off is that there will be |
| 487 | false-positive hits for the read-type or the access-type hardware |
| 488 | watchpoints; for the write type, which is more commonly used, there |
| 489 | will be no such issues, as the higher-level breakpoint management |
| 490 | in gdb always examines the exact watched region for any content |
| 491 | change, and transparently resumes a thread from a watchpoint trap |
| 492 | if there is no change to the watched region. |
| 493 | |
| 494 | Another limitation is that because the watched region is enlarged, |
| 495 | the watchpoint fault address returned by |
| 496 | aarch64_stopped_data_address may be outside of the original watched |
| 497 | region, especially when the triggering instruction is accessing a |
| 498 | larger region. When the fault address is not within any known |
| 499 | range, watchpoints_triggered in gdb will get confused, as the |
| 500 | higher-level watchpoint management is only aware of original |
| 501 | watched regions, and will think that some unknown watchpoint has |
| 502 | been triggered. In such a case, gdb may stop without displaying |
| 503 | any detailed information. |
| 504 | |
| 505 | Once the kernel provides the full support for Byte Address Select |
| 506 | (BAS) in the hardware watchpoint control register, these |
| 507 | limitations can be largely relaxed with some further work. */ |
| 508 | |
| 509 | static void |
| 510 | aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, |
| 511 | int *aligned_len_p, CORE_ADDR *next_addr_p, |
| 512 | int *next_len_p) |
| 513 | { |
| 514 | int aligned_len; |
| 515 | unsigned int offset; |
| 516 | CORE_ADDR aligned_addr; |
| 517 | const unsigned int alignment = AARCH64_HWP_ALIGNMENT; |
| 518 | const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG; |
| 519 | |
| 520 | /* As assumed by the algorithm. */ |
| 521 | gdb_assert (alignment == max_wp_len); |
| 522 | |
| 523 | if (len <= 0) |
| 524 | return; |
| 525 | |
| 526 | /* Address to be put into the hardware watchpoint value register |
| 527 | must be aligned. */ |
| 528 | offset = addr & (alignment - 1); |
| 529 | aligned_addr = addr - offset; |
| 530 | |
| 531 | gdb_assert (offset >= 0 && offset < alignment); |
| 532 | gdb_assert (aligned_addr >= 0 && aligned_addr <= addr); |
| 533 | gdb_assert ((offset + len) > 0); |
| 534 | |
| 535 | if (offset + len >= max_wp_len) |
| 536 | { |
| 537 | /* Need more than one watchpoint registers; truncate it at the |
| 538 | alignment boundary. */ |
| 539 | aligned_len = max_wp_len; |
| 540 | len -= (max_wp_len - offset); |
| 541 | addr += (max_wp_len - offset); |
| 542 | gdb_assert ((addr & (alignment - 1)) == 0); |
| 543 | } |
| 544 | else |
| 545 | { |
| 546 | /* Find the smallest valid length that is large enough to |
| 547 | accommodate this watchpoint. */ |
| 548 | static const unsigned char |
| 549 | aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] = |
| 550 | { 1, 2, 4, 4, 8, 8, 8, 8 }; |
| 551 | |
| 552 | aligned_len = aligned_len_array[offset + len - 1]; |
| 553 | addr += len; |
| 554 | len = 0; |
| 555 | } |
| 556 | |
| 557 | if (aligned_addr_p != NULL) |
| 558 | *aligned_addr_p = aligned_addr; |
| 559 | if (aligned_len_p != NULL) |
| 560 | *aligned_len_p = aligned_len; |
| 561 | if (next_addr_p != NULL) |
| 562 | *next_addr_p = addr; |
| 563 | if (next_len_p != NULL) |
| 564 | *next_len_p = len; |
| 565 | } |
| 566 | |
| 567 | /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint |
| 568 | registers with data from *STATE. */ |
| 569 | |
| 570 | static void |
| 571 | aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state, |
| 572 | int tid, int watchpoint) |
| 573 | { |
| 574 | int i, count; |
| 575 | struct iovec iov; |
| 576 | struct user_hwdebug_state regs; |
| 577 | const CORE_ADDR *addr; |
| 578 | const unsigned int *ctrl; |
| 579 | |
| 580 | memset (®s, 0, sizeof (regs)); |
| 581 | iov.iov_base = ®s; |
| 582 | count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs; |
| 583 | addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; |
| 584 | ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; |
| 585 | if (count == 0) |
| 586 | return; |
| 587 | iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1]) |
| 588 | + sizeof (regs.dbg_regs [count - 1])); |
| 589 | |
| 590 | for (i = 0; i < count; i++) |
| 591 | { |
| 592 | regs.dbg_regs[i].addr = addr[i]; |
| 593 | regs.dbg_regs[i].ctrl = ctrl[i]; |
| 594 | } |
| 595 | |
| 596 | if (ptrace (PTRACE_SETREGSET, tid, |
| 597 | watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK, |
| 598 | (void *) &iov)) |
| 599 | error (_("Unexpected error setting hardware debug registers")); |
| 600 | } |
| 601 | |
| 602 | struct aarch64_dr_update_callback_param |
| 603 | { |
| 604 | int pid; |
| 605 | int is_watchpoint; |
| 606 | unsigned int idx; |
| 607 | }; |
| 608 | |
| 609 | /* Callback function which records the information about the change of |
| 610 | one hardware breakpoint/watchpoint setting for the thread ENTRY. |
| 611 | The information is passed in via PTR. |
| 612 | N.B. The actual updating of hardware debug registers is not |
| 613 | carried out until the moment the thread is resumed. */ |
| 614 | |
| 615 | static int |
| 616 | debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr) |
| 617 | { |
| 618 | struct thread_info *thread = (struct thread_info *) entry; |
| 619 | struct lwp_info *lwp = get_thread_lwp (thread); |
| 620 | struct aarch64_dr_update_callback_param *param_p |
| 621 | = (struct aarch64_dr_update_callback_param *) ptr; |
| 622 | int pid = param_p->pid; |
| 623 | int idx = param_p->idx; |
| 624 | int is_watchpoint = param_p->is_watchpoint; |
| 625 | struct arch_lwp_info *info = lwp->arch_private; |
| 626 | dr_changed_t *dr_changed_ptr; |
| 627 | dr_changed_t dr_changed; |
| 628 | |
| 629 | if (debug_hw_points) |
| 630 | { |
| 631 | fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n"); |
| 632 | fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, " |
| 633 | "dr_changed_wp=0x%llx\n", |
| 634 | pid, lwpid_of (thread), info->dr_changed_bp, |
| 635 | info->dr_changed_wp); |
| 636 | } |
| 637 | |
| 638 | dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp |
| 639 | : &info->dr_changed_bp; |
| 640 | dr_changed = *dr_changed_ptr; |
| 641 | |
| 642 | /* Only update the threads of this process. */ |
| 643 | if (pid_of (thread) == pid) |
| 644 | { |
| 645 | gdb_assert (idx >= 0 |
| 646 | && (idx <= (is_watchpoint ? aarch64_num_wp_regs |
| 647 | : aarch64_num_bp_regs))); |
| 648 | |
| 649 | /* The following assertion is not right, as there can be changes |
| 650 | that have not been made to the hardware debug registers |
| 651 | before new changes overwrite the old ones. This can happen, |
| 652 | for instance, when the breakpoint/watchpoint hit one of the |
| 653 | threads and the user enters continue; then what happens is: |
| 654 | 1) all breakpoints/watchpoints are removed for all threads; |
| 655 | 2) a single step is carried out for the thread that was hit; |
| 656 | 3) all of the points are inserted again for all threads; |
| 657 | 4) all threads are resumed. |
| 658 | The 2nd step will only affect the one thread in which the |
| 659 | bp/wp was hit, which means only that one thread is resumed; |
| 660 | remember that the actual updating only happen in |
| 661 | aarch64_linux_prepare_to_resume, so other threads remain |
| 662 | stopped during the removal and insertion of bp/wp. Therefore |
| 663 | for those threads, the change of insertion of the bp/wp |
| 664 | overwrites that of the earlier removals. (The situation may |
| 665 | be different when bp/wp is steppable, or in the non-stop |
| 666 | mode.) */ |
| 667 | /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */ |
| 668 | |
| 669 | /* The actual update is done later just before resuming the lwp, |
| 670 | we just mark that one register pair needs updating. */ |
| 671 | DR_MARK_N_CHANGED (dr_changed, idx); |
| 672 | *dr_changed_ptr = dr_changed; |
| 673 | |
| 674 | /* If the lwp isn't stopped, force it to momentarily pause, so |
| 675 | we can update its debug registers. */ |
| 676 | if (!lwp->stopped) |
| 677 | linux_stop_lwp (lwp); |
| 678 | } |
| 679 | |
| 680 | if (debug_hw_points) |
| 681 | { |
| 682 | fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, " |
| 683 | "dr_changed_wp=0x%llx\n", |
| 684 | pid, lwpid_of (thread), info->dr_changed_bp, |
| 685 | info->dr_changed_wp); |
| 686 | } |
| 687 | |
| 688 | return 0; |
| 689 | } |
| 690 | |
| 691 | /* Notify each thread that their IDXth breakpoint/watchpoint register |
| 692 | pair needs to be updated. The message will be recorded in each |
| 693 | thread's arch-specific data area, the actual updating will be done |
| 694 | when the thread is resumed. */ |
| 695 | |
| 696 | void |
| 697 | aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state, |
| 698 | int is_watchpoint, unsigned int idx) |
| 699 | { |
| 700 | struct aarch64_dr_update_callback_param param; |
| 701 | |
| 702 | /* Only update the threads of this process. */ |
| 703 | param.pid = pid_of (current_inferior); |
| 704 | |
| 705 | param.is_watchpoint = is_watchpoint; |
| 706 | param.idx = idx; |
| 707 | |
| 708 | find_inferior (&all_threads, debug_reg_change_callback, (void *) ¶m); |
| 709 | } |
| 710 | |
| 711 | |
| 712 | /* Return the pointer to the debug register state structure in the |
| 713 | current process' arch-specific data area. */ |
| 714 | |
| 715 | static struct aarch64_debug_reg_state * |
| 716 | aarch64_get_debug_reg_state () |
| 717 | { |
| 718 | struct process_info *proc; |
| 719 | |
| 720 | proc = current_process (); |
| 721 | return &proc->private->arch_private->debug_reg_state; |
| 722 | } |
| 723 | |
| 724 | /* Record the insertion of one breakpoint/watchpoint, as represented |
| 725 | by ADDR and CTRL, in the process' arch-specific data area *STATE. */ |
| 726 | |
| 727 | static int |
| 728 | aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state, |
| 729 | enum target_hw_bp_type type, |
| 730 | CORE_ADDR addr, int len) |
| 731 | { |
| 732 | int i, idx, num_regs, is_watchpoint; |
| 733 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; |
| 734 | CORE_ADDR *dr_addr_p; |
| 735 | |
| 736 | /* Set up state pointers. */ |
| 737 | is_watchpoint = (type != hw_execute); |
| 738 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); |
| 739 | if (is_watchpoint) |
| 740 | { |
| 741 | num_regs = aarch64_num_wp_regs; |
| 742 | dr_addr_p = state->dr_addr_wp; |
| 743 | dr_ctrl_p = state->dr_ctrl_wp; |
| 744 | dr_ref_count = state->dr_ref_count_wp; |
| 745 | } |
| 746 | else |
| 747 | { |
| 748 | num_regs = aarch64_num_bp_regs; |
| 749 | dr_addr_p = state->dr_addr_bp; |
| 750 | dr_ctrl_p = state->dr_ctrl_bp; |
| 751 | dr_ref_count = state->dr_ref_count_bp; |
| 752 | } |
| 753 | |
| 754 | ctrl = aarch64_point_encode_ctrl_reg (type, len); |
| 755 | |
| 756 | /* Find an existing or free register in our cache. */ |
| 757 | idx = -1; |
| 758 | for (i = 0; i < num_regs; ++i) |
| 759 | { |
| 760 | if ((dr_ctrl_p[i] & 1) == 0) |
| 761 | { |
| 762 | gdb_assert (dr_ref_count[i] == 0); |
| 763 | idx = i; |
| 764 | /* no break; continue hunting for an exising one. */ |
| 765 | } |
| 766 | else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) |
| 767 | { |
| 768 | gdb_assert (dr_ref_count[i] != 0); |
| 769 | idx = i; |
| 770 | break; |
| 771 | } |
| 772 | } |
| 773 | |
| 774 | /* No space. */ |
| 775 | if (idx == -1) |
| 776 | return -1; |
| 777 | |
| 778 | /* Update our cache. */ |
| 779 | if ((dr_ctrl_p[idx] & 1) == 0) |
| 780 | { |
| 781 | /* new entry */ |
| 782 | dr_addr_p[idx] = addr; |
| 783 | dr_ctrl_p[idx] = ctrl; |
| 784 | dr_ref_count[idx] = 1; |
| 785 | /* Notify the change. */ |
| 786 | aarch64_notify_debug_reg_change (state, is_watchpoint, idx); |
| 787 | } |
| 788 | else |
| 789 | { |
| 790 | /* existing entry */ |
| 791 | dr_ref_count[idx]++; |
| 792 | } |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | /* Record the removal of one breakpoint/watchpoint, as represented by |
| 798 | ADDR and CTRL, in the process' arch-specific data area *STATE. */ |
| 799 | |
| 800 | static int |
| 801 | aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state, |
| 802 | enum target_hw_bp_type type, |
| 803 | CORE_ADDR addr, int len) |
| 804 | { |
| 805 | int i, num_regs, is_watchpoint; |
| 806 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; |
| 807 | CORE_ADDR *dr_addr_p; |
| 808 | |
| 809 | /* Set up state pointers. */ |
| 810 | is_watchpoint = (type != hw_execute); |
| 811 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); |
| 812 | if (is_watchpoint) |
| 813 | { |
| 814 | num_regs = aarch64_num_wp_regs; |
| 815 | dr_addr_p = state->dr_addr_wp; |
| 816 | dr_ctrl_p = state->dr_ctrl_wp; |
| 817 | dr_ref_count = state->dr_ref_count_wp; |
| 818 | } |
| 819 | else |
| 820 | { |
| 821 | num_regs = aarch64_num_bp_regs; |
| 822 | dr_addr_p = state->dr_addr_bp; |
| 823 | dr_ctrl_p = state->dr_ctrl_bp; |
| 824 | dr_ref_count = state->dr_ref_count_bp; |
| 825 | } |
| 826 | |
| 827 | ctrl = aarch64_point_encode_ctrl_reg (type, len); |
| 828 | |
| 829 | /* Find the entry that matches the ADDR and CTRL. */ |
| 830 | for (i = 0; i < num_regs; ++i) |
| 831 | if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) |
| 832 | { |
| 833 | gdb_assert (dr_ref_count[i] != 0); |
| 834 | break; |
| 835 | } |
| 836 | |
| 837 | /* Not found. */ |
| 838 | if (i == num_regs) |
| 839 | return -1; |
| 840 | |
| 841 | /* Clear our cache. */ |
| 842 | if (--dr_ref_count[i] == 0) |
| 843 | { |
| 844 | /* Clear the enable bit. */ |
| 845 | ctrl &= ~1; |
| 846 | dr_addr_p[i] = 0; |
| 847 | dr_ctrl_p[i] = ctrl; |
| 848 | /* Notify the change. */ |
| 849 | aarch64_notify_debug_reg_change (state, is_watchpoint, i); |
| 850 | } |
| 851 | |
| 852 | return 0; |
| 853 | } |
| 854 | |
| 855 | static int |
| 856 | aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr, |
| 857 | int len, int is_insert) |
| 858 | { |
| 859 | struct aarch64_debug_reg_state *state; |
| 860 | |
| 861 | /* The hardware breakpoint on AArch64 should always be 4-byte |
| 862 | aligned. */ |
| 863 | if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len)) |
| 864 | return -1; |
| 865 | |
| 866 | state = aarch64_get_debug_reg_state (); |
| 867 | |
| 868 | if (is_insert) |
| 869 | return aarch64_dr_state_insert_one_point (state, type, addr, len); |
| 870 | else |
| 871 | return aarch64_dr_state_remove_one_point (state, type, addr, len); |
| 872 | } |
| 873 | |
| 874 | /* This is essentially the same as aarch64_handle_breakpoint, apart |
| 875 | from that it is an aligned watchpoint to be handled. */ |
| 876 | |
| 877 | static int |
| 878 | aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type, |
| 879 | CORE_ADDR addr, int len, int is_insert) |
| 880 | { |
| 881 | struct aarch64_debug_reg_state *state; |
| 882 | |
| 883 | state = aarch64_get_debug_reg_state (); |
| 884 | |
| 885 | if (is_insert) |
| 886 | return aarch64_dr_state_insert_one_point (state, type, addr, len); |
| 887 | else |
| 888 | return aarch64_dr_state_remove_one_point (state, type, addr, len); |
| 889 | } |
| 890 | |
| 891 | /* Insert/remove unaligned watchpoint by calling |
| 892 | aarch64_align_watchpoint repeatedly until the whole watched region, |
| 893 | as represented by ADDR and LEN, has been properly aligned and ready |
| 894 | to be written to one or more hardware watchpoint registers. |
| 895 | IS_INSERT indicates whether this is an insertion or a deletion. |
| 896 | Return 0 if succeed. */ |
| 897 | |
| 898 | static int |
| 899 | aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type, |
| 900 | CORE_ADDR addr, int len, int is_insert) |
| 901 | { |
| 902 | struct aarch64_debug_reg_state *state |
| 903 | = aarch64_get_debug_reg_state (); |
| 904 | |
| 905 | while (len > 0) |
| 906 | { |
| 907 | CORE_ADDR aligned_addr; |
| 908 | int aligned_len, ret; |
| 909 | |
| 910 | aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len, |
| 911 | &addr, &len); |
| 912 | |
| 913 | if (is_insert) |
| 914 | ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr, |
| 915 | aligned_len); |
| 916 | else |
| 917 | ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr, |
| 918 | aligned_len); |
| 919 | |
| 920 | if (debug_hw_points) |
| 921 | fprintf (stderr, |
| 922 | "handle_unaligned_watchpoint: is_insert: %d\n" |
| 923 | " aligned_addr: 0x%s, aligned_len: %d\n" |
| 924 | " next_addr: 0x%s, next_len: %d\n", |
| 925 | is_insert, paddress (aligned_addr), aligned_len, |
| 926 | paddress (addr), len); |
| 927 | |
| 928 | if (ret != 0) |
| 929 | return ret; |
| 930 | } |
| 931 | |
| 932 | return 0; |
| 933 | } |
| 934 | |
| 935 | static int |
| 936 | aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr, |
| 937 | int len, int is_insert) |
| 938 | { |
| 939 | if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len)) |
| 940 | return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert); |
| 941 | else |
| 942 | return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert); |
| 943 | } |
| 944 | |
| 945 | static int |
| 946 | aarch64_supports_z_point_type (char z_type) |
| 947 | { |
| 948 | switch (z_type) |
| 949 | { |
| 950 | case Z_PACKET_HW_BP: |
| 951 | case Z_PACKET_WRITE_WP: |
| 952 | case Z_PACKET_READ_WP: |
| 953 | case Z_PACKET_ACCESS_WP: |
| 954 | return 1; |
| 955 | default: |
| 956 | /* Leave the handling of sw breakpoints with the gdb client. */ |
| 957 | return 0; |
| 958 | } |
| 959 | } |
| 960 | |
| 961 | /* Insert a hardware breakpoint/watchpoint. |
| 962 | It actually only records the info of the to-be-inserted bp/wp; |
| 963 | the actual insertion will happen when threads are resumed. |
| 964 | |
| 965 | Return 0 if succeed; |
| 966 | Return 1 if TYPE is unsupported type; |
| 967 | Return -1 if an error occurs. */ |
| 968 | |
| 969 | static int |
| 970 | aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
| 971 | int len, struct raw_breakpoint *bp) |
| 972 | { |
| 973 | int ret; |
| 974 | enum target_hw_bp_type targ_type; |
| 975 | |
| 976 | if (debug_hw_points) |
| 977 | fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n", |
| 978 | (unsigned long) addr, len); |
| 979 | |
| 980 | /* Determine the type from the raw breakpoint type. */ |
| 981 | targ_type = raw_bkpt_type_to_target_hw_bp_type (type); |
| 982 | |
| 983 | if (targ_type != hw_execute) |
| 984 | ret = |
| 985 | aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */); |
| 986 | else |
| 987 | ret = |
| 988 | aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */); |
| 989 | |
| 990 | if (debug_hw_points > 1) |
| 991 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), |
| 992 | "insert_point", addr, len, targ_type); |
| 993 | |
| 994 | return ret; |
| 995 | } |
| 996 | |
| 997 | /* Remove a hardware breakpoint/watchpoint. |
| 998 | It actually only records the info of the to-be-removed bp/wp, |
| 999 | the actual removal will be done when threads are resumed. |
| 1000 | |
| 1001 | Return 0 if succeed; |
| 1002 | Return 1 if TYPE is an unsupported type; |
| 1003 | Return -1 if an error occurs. */ |
| 1004 | |
| 1005 | static int |
| 1006 | aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
| 1007 | int len, struct raw_breakpoint *bp) |
| 1008 | { |
| 1009 | int ret; |
| 1010 | enum target_hw_bp_type targ_type; |
| 1011 | |
| 1012 | if (debug_hw_points) |
| 1013 | fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n", |
| 1014 | (unsigned long) addr, len); |
| 1015 | |
| 1016 | /* Determine the type from the raw breakpoint type. */ |
| 1017 | targ_type = raw_bkpt_type_to_target_hw_bp_type (type); |
| 1018 | |
| 1019 | /* Set up state pointers. */ |
| 1020 | if (targ_type != hw_execute) |
| 1021 | ret = |
| 1022 | aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */); |
| 1023 | else |
| 1024 | ret = |
| 1025 | aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */); |
| 1026 | |
| 1027 | if (debug_hw_points > 1) |
| 1028 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), |
| 1029 | "remove_point", addr, len, targ_type); |
| 1030 | |
| 1031 | return ret; |
| 1032 | } |
| 1033 | |
| 1034 | /* Returns the address associated with the watchpoint that hit, if |
| 1035 | any; returns 0 otherwise. */ |
| 1036 | |
| 1037 | static CORE_ADDR |
| 1038 | aarch64_stopped_data_address (void) |
| 1039 | { |
| 1040 | siginfo_t siginfo; |
| 1041 | int pid, i; |
| 1042 | struct aarch64_debug_reg_state *state; |
| 1043 | |
| 1044 | pid = lwpid_of (current_inferior); |
| 1045 | |
| 1046 | /* Get the siginfo. */ |
| 1047 | if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0) |
| 1048 | return (CORE_ADDR) 0; |
| 1049 | |
| 1050 | /* Need to be a hardware breakpoint/watchpoint trap. */ |
| 1051 | if (siginfo.si_signo != SIGTRAP |
| 1052 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) |
| 1053 | return (CORE_ADDR) 0; |
| 1054 | |
| 1055 | /* Check if the address matches any watched address. */ |
| 1056 | state = aarch64_get_debug_reg_state (); |
| 1057 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
| 1058 | { |
| 1059 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); |
| 1060 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; |
| 1061 | const CORE_ADDR addr_watch = state->dr_addr_wp[i]; |
| 1062 | if (state->dr_ref_count_wp[i] |
| 1063 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) |
| 1064 | && addr_trap >= addr_watch |
| 1065 | && addr_trap < addr_watch + len) |
| 1066 | return addr_trap; |
| 1067 | } |
| 1068 | |
| 1069 | return (CORE_ADDR) 0; |
| 1070 | } |
| 1071 | |
| 1072 | /* Returns 1 if target was stopped due to a watchpoint hit, 0 |
| 1073 | otherwise. */ |
| 1074 | |
| 1075 | static int |
| 1076 | aarch64_stopped_by_watchpoint (void) |
| 1077 | { |
| 1078 | if (aarch64_stopped_data_address () != 0) |
| 1079 | return 1; |
| 1080 | else |
| 1081 | return 0; |
| 1082 | } |
| 1083 | |
| 1084 | /* Fetch the thread-local storage pointer for libthread_db. */ |
| 1085 | |
| 1086 | ps_err_e |
| 1087 | ps_get_thread_area (const struct ps_prochandle *ph, |
| 1088 | lwpid_t lwpid, int idx, void **base) |
| 1089 | { |
| 1090 | struct iovec iovec; |
| 1091 | uint64_t reg; |
| 1092 | |
| 1093 | iovec.iov_base = ® |
| 1094 | iovec.iov_len = sizeof (reg); |
| 1095 | |
| 1096 | if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) |
| 1097 | return PS_ERR; |
| 1098 | |
| 1099 | /* IDX is the bias from the thread pointer to the beginning of the |
| 1100 | thread descriptor. It has to be subtracted due to implementation |
| 1101 | quirks in libthread_db. */ |
| 1102 | *base = (void *) (reg - idx); |
| 1103 | |
| 1104 | return PS_OK; |
| 1105 | } |
| 1106 | |
| 1107 | /* Called when a new process is created. */ |
| 1108 | |
| 1109 | static struct arch_process_info * |
| 1110 | aarch64_linux_new_process (void) |
| 1111 | { |
| 1112 | struct arch_process_info *info = xcalloc (1, sizeof (*info)); |
| 1113 | |
| 1114 | aarch64_init_debug_reg_state (&info->debug_reg_state); |
| 1115 | |
| 1116 | return info; |
| 1117 | } |
| 1118 | |
| 1119 | /* Called when a new thread is detected. */ |
| 1120 | |
| 1121 | static struct arch_lwp_info * |
| 1122 | aarch64_linux_new_thread (void) |
| 1123 | { |
| 1124 | struct arch_lwp_info *info = xcalloc (1, sizeof (*info)); |
| 1125 | |
| 1126 | /* Mark that all the hardware breakpoint/watchpoint register pairs |
| 1127 | for this thread need to be initialized (with data from |
| 1128 | aarch_process_info.debug_reg_state). */ |
| 1129 | DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs); |
| 1130 | DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs); |
| 1131 | |
| 1132 | return info; |
| 1133 | } |
| 1134 | |
| 1135 | /* Called when resuming a thread. |
| 1136 | If the debug regs have changed, update the thread's copies. */ |
| 1137 | |
| 1138 | static void |
| 1139 | aarch64_linux_prepare_to_resume (struct lwp_info *lwp) |
| 1140 | { |
| 1141 | struct thread_info *thread = get_lwp_thread (lwp); |
| 1142 | ptid_t ptid = ptid_of (thread); |
| 1143 | struct arch_lwp_info *info = lwp->arch_private; |
| 1144 | |
| 1145 | if (DR_HAS_CHANGED (info->dr_changed_bp) |
| 1146 | || DR_HAS_CHANGED (info->dr_changed_wp)) |
| 1147 | { |
| 1148 | int tid = ptid_get_lwp (ptid); |
| 1149 | struct process_info *proc = find_process_pid (ptid_get_pid (ptid)); |
| 1150 | struct aarch64_debug_reg_state *state |
| 1151 | = &proc->private->arch_private->debug_reg_state; |
| 1152 | |
| 1153 | if (debug_hw_points) |
| 1154 | fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread)); |
| 1155 | |
| 1156 | /* Watchpoints. */ |
| 1157 | if (DR_HAS_CHANGED (info->dr_changed_wp)) |
| 1158 | { |
| 1159 | aarch64_linux_set_debug_regs (state, tid, 1); |
| 1160 | DR_CLEAR_CHANGED (info->dr_changed_wp); |
| 1161 | } |
| 1162 | |
| 1163 | /* Breakpoints. */ |
| 1164 | if (DR_HAS_CHANGED (info->dr_changed_bp)) |
| 1165 | { |
| 1166 | aarch64_linux_set_debug_regs (state, tid, 0); |
| 1167 | DR_CLEAR_CHANGED (info->dr_changed_bp); |
| 1168 | } |
| 1169 | } |
| 1170 | } |
| 1171 | |
| 1172 | /* ptrace hardware breakpoint resource info is formatted as follows: |
| 1173 | |
| 1174 | 31 24 16 8 0 |
| 1175 | +---------------+--------------+---------------+---------------+ |
| 1176 | | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS | |
| 1177 | +---------------+--------------+---------------+---------------+ */ |
| 1178 | |
| 1179 | #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff) |
| 1180 | #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff) |
| 1181 | #define AARCH64_DEBUG_ARCH_V8 0x6 |
| 1182 | |
| 1183 | static void |
| 1184 | aarch64_arch_setup (void) |
| 1185 | { |
| 1186 | int pid; |
| 1187 | struct iovec iov; |
| 1188 | struct user_hwdebug_state dreg_state; |
| 1189 | |
| 1190 | current_process ()->tdesc = tdesc_aarch64; |
| 1191 | |
| 1192 | pid = lwpid_of (current_inferior); |
| 1193 | iov.iov_base = &dreg_state; |
| 1194 | iov.iov_len = sizeof (dreg_state); |
| 1195 | |
| 1196 | /* Get hardware watchpoint register info. */ |
| 1197 | if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0 |
| 1198 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) |
| 1199 | { |
| 1200 | aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); |
| 1201 | if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM) |
| 1202 | { |
| 1203 | warning ("Unexpected number of hardware watchpoint registers reported" |
| 1204 | " by ptrace, got %d, expected %d.", |
| 1205 | aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM); |
| 1206 | aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM; |
| 1207 | } |
| 1208 | } |
| 1209 | else |
| 1210 | { |
| 1211 | warning ("Unable to determine the number of hardware watchpoints" |
| 1212 | " available."); |
| 1213 | aarch64_num_wp_regs = 0; |
| 1214 | } |
| 1215 | |
| 1216 | /* Get hardware breakpoint register info. */ |
| 1217 | if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0 |
| 1218 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) |
| 1219 | { |
| 1220 | aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); |
| 1221 | if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM) |
| 1222 | { |
| 1223 | warning ("Unexpected number of hardware breakpoint registers reported" |
| 1224 | " by ptrace, got %d, expected %d.", |
| 1225 | aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM); |
| 1226 | aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM; |
| 1227 | } |
| 1228 | } |
| 1229 | else |
| 1230 | { |
| 1231 | warning ("Unable to determine the number of hardware breakpoints" |
| 1232 | " available."); |
| 1233 | aarch64_num_bp_regs = 0; |
| 1234 | } |
| 1235 | } |
| 1236 | |
| 1237 | static struct regset_info aarch64_regsets[] = |
| 1238 | { |
| 1239 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, |
| 1240 | sizeof (struct user_pt_regs), GENERAL_REGS, |
| 1241 | aarch64_fill_gregset, aarch64_store_gregset }, |
| 1242 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, |
| 1243 | sizeof (struct user_fpsimd_state), FP_REGS, |
| 1244 | aarch64_fill_fpregset, aarch64_store_fpregset |
| 1245 | }, |
| 1246 | { 0, 0, 0, -1, -1, NULL, NULL } |
| 1247 | }; |
| 1248 | |
| 1249 | static struct regsets_info aarch64_regsets_info = |
| 1250 | { |
| 1251 | aarch64_regsets, /* regsets */ |
| 1252 | 0, /* num_regsets */ |
| 1253 | NULL, /* disabled_regsets */ |
| 1254 | }; |
| 1255 | |
| 1256 | static struct usrregs_info aarch64_usrregs_info = |
| 1257 | { |
| 1258 | AARCH64_NUM_REGS, |
| 1259 | aarch64_regmap, |
| 1260 | }; |
| 1261 | |
| 1262 | static struct regs_info regs_info = |
| 1263 | { |
| 1264 | NULL, /* regset_bitmap */ |
| 1265 | &aarch64_usrregs_info, |
| 1266 | &aarch64_regsets_info, |
| 1267 | }; |
| 1268 | |
| 1269 | static const struct regs_info * |
| 1270 | aarch64_regs_info (void) |
| 1271 | { |
| 1272 | return ®s_info; |
| 1273 | } |
| 1274 | |
| 1275 | struct linux_target_ops the_low_target = |
| 1276 | { |
| 1277 | aarch64_arch_setup, |
| 1278 | aarch64_regs_info, |
| 1279 | aarch64_cannot_fetch_register, |
| 1280 | aarch64_cannot_store_register, |
| 1281 | NULL, |
| 1282 | aarch64_get_pc, |
| 1283 | aarch64_set_pc, |
| 1284 | (const unsigned char *) &aarch64_breakpoint, |
| 1285 | aarch64_breakpoint_len, |
| 1286 | NULL, |
| 1287 | 0, |
| 1288 | aarch64_breakpoint_at, |
| 1289 | aarch64_supports_z_point_type, |
| 1290 | aarch64_insert_point, |
| 1291 | aarch64_remove_point, |
| 1292 | aarch64_stopped_by_watchpoint, |
| 1293 | aarch64_stopped_data_address, |
| 1294 | NULL, |
| 1295 | NULL, |
| 1296 | NULL, |
| 1297 | aarch64_linux_new_process, |
| 1298 | aarch64_linux_new_thread, |
| 1299 | aarch64_linux_prepare_to_resume, |
| 1300 | }; |
| 1301 | |
| 1302 | void |
| 1303 | initialize_low_arch (void) |
| 1304 | { |
| 1305 | init_registers_aarch64 (); |
| 1306 | |
| 1307 | initialize_regsets_info (&aarch64_regsets_info); |
| 1308 | } |