| 1 | /* Native-dependent code for the i386. |
| 2 | |
| 3 | Copyright (C) 2001, 2004, 2005, 2007, 2008 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "breakpoint.h" |
| 22 | #include "command.h" |
| 23 | #include "gdbcmd.h" |
| 24 | #include "target.h" |
| 25 | |
| 26 | /* Support for hardware watchpoints and breakpoints using the i386 |
| 27 | debug registers. |
| 28 | |
| 29 | This provides several functions for inserting and removing |
| 30 | hardware-assisted breakpoints and watchpoints, testing if one or |
| 31 | more of the watchpoints triggered and at what address, checking |
| 32 | whether a given region can be watched, etc. |
| 33 | |
| 34 | A target which wants to use these functions should define several |
| 35 | macros, such as `target_insert_watchpoint' and |
| 36 | `target_stopped_data_address', listed in target.h, to call the |
| 37 | appropriate functions below. It should also define |
| 38 | I386_USE_GENERIC_WATCHPOINTS in its tm.h file. |
| 39 | |
| 40 | In addition, each target should provide several low-level macros |
| 41 | that will be called to insert watchpoints and hardware breakpoints |
| 42 | into the inferior, remove them, and check their status. These |
| 43 | macros are: |
| 44 | |
| 45 | I386_DR_LOW_SET_CONTROL -- set the debug control (DR7) |
| 46 | register to a given value |
| 47 | |
| 48 | I386_DR_LOW_SET_ADDR -- put an address into one debug |
| 49 | register |
| 50 | |
| 51 | I386_DR_LOW_RESET_ADDR -- reset the address stored in |
| 52 | one debug register |
| 53 | |
| 54 | I386_DR_LOW_GET_STATUS -- return the value of the debug |
| 55 | status (DR6) register. |
| 56 | |
| 57 | The functions below implement debug registers sharing by reference |
| 58 | counts, and allow to watch regions up to 16 bytes long. */ |
| 59 | |
| 60 | #ifdef I386_USE_GENERIC_WATCHPOINTS |
| 61 | |
| 62 | /* Support for 8-byte wide hw watchpoints. */ |
| 63 | #ifndef TARGET_HAS_DR_LEN_8 |
| 64 | #define TARGET_HAS_DR_LEN_8 0 |
| 65 | #endif |
| 66 | |
| 67 | /* Debug registers' indices. */ |
| 68 | #define DR_NADDR 4 /* The number of debug address registers. */ |
| 69 | #define DR_STATUS 6 /* Index of debug status register (DR6). */ |
| 70 | #define DR_CONTROL 7 /* Index of debug control register (DR7). */ |
| 71 | |
| 72 | /* DR7 Debug Control register fields. */ |
| 73 | |
| 74 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ |
| 75 | #define DR_CONTROL_SHIFT 16 |
| 76 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ |
| 77 | #define DR_CONTROL_SIZE 4 |
| 78 | |
| 79 | /* Watchpoint/breakpoint read/write fields in DR7. */ |
| 80 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
| 81 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ |
| 82 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ |
| 83 | |
| 84 | /* This is here for completeness. No platform supports this |
| 85 | functionality yet (as of March 2001). Note that the DE flag in the |
| 86 | CR4 register needs to be set to support this. */ |
| 87 | #ifndef DR_RW_IORW |
| 88 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
| 89 | #endif |
| 90 | |
| 91 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift |
| 92 | is so we could OR this with the read/write field defined above. */ |
| 93 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
| 94 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ |
| 95 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ |
| 96 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ |
| 97 | |
| 98 | /* Local and Global Enable flags in DR7. |
| 99 | |
| 100 | When the Local Enable flag is set, the breakpoint/watchpoint is |
| 101 | enabled only for the current task; the processor automatically |
| 102 | clears this flag on every task switch. When the Global Enable flag |
| 103 | is set, the breakpoint/watchpoint is enabled for all tasks; the |
| 104 | processor never clears this flag. |
| 105 | |
| 106 | Currently, all watchpoint are locally enabled. If you need to |
| 107 | enable them globally, read the comment which pertains to this in |
| 108 | i386_insert_aligned_watchpoint below. */ |
| 109 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
| 110 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ |
| 111 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ |
| 112 | |
| 113 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown |
| 114 | flags). These are only required on i386, to allow detection of the |
| 115 | exact instruction which caused a watchpoint to break; i486 and |
| 116 | later processors do that automatically. We set these flags for |
| 117 | backwards compatibility. */ |
| 118 | #define DR_LOCAL_SLOWDOWN (0x100) |
| 119 | #define DR_GLOBAL_SLOWDOWN (0x200) |
| 120 | |
| 121 | /* Fields reserved by Intel. This includes the GD (General Detect |
| 122 | Enable) flag, which causes a debug exception to be generated when a |
| 123 | MOV instruction accesses one of the debug registers. |
| 124 | |
| 125 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ |
| 126 | #define DR_CONTROL_RESERVED (0xFC00) |
| 127 | |
| 128 | /* Auxiliary helper macros. */ |
| 129 | |
| 130 | /* A value that masks all fields in DR7 that are reserved by Intel. */ |
| 131 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
| 132 | |
| 133 | /* The I'th debug register is vacant if its Local and Global Enable |
| 134 | bits are reset in the Debug Control register. */ |
| 135 | #define I386_DR_VACANT(i) \ |
| 136 | ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) |
| 137 | |
| 138 | /* Locally enable the break/watchpoint in the I'th debug register. */ |
| 139 | #define I386_DR_LOCAL_ENABLE(i) \ |
| 140 | dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) |
| 141 | |
| 142 | /* Globally enable the break/watchpoint in the I'th debug register. */ |
| 143 | #define I386_DR_GLOBAL_ENABLE(i) \ |
| 144 | dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) |
| 145 | |
| 146 | /* Disable the break/watchpoint in the I'th debug register. */ |
| 147 | #define I386_DR_DISABLE(i) \ |
| 148 | dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i))) |
| 149 | |
| 150 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ |
| 151 | #define I386_DR_SET_RW_LEN(i,rwlen) \ |
| 152 | do { \ |
| 153 | dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ |
| 154 | dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ |
| 155 | } while (0) |
| 156 | |
| 157 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ |
| 158 | #define I386_DR_GET_RW_LEN(i) \ |
| 159 | ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) |
| 160 | |
| 161 | /* Did the watchpoint whose address is in the I'th register break? */ |
| 162 | #define I386_DR_WATCH_HIT(i) (dr_status_mirror & (1 << (i))) |
| 163 | |
| 164 | /* A macro to loop over all debug registers. */ |
| 165 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) |
| 166 | |
| 167 | /* Mirror the inferior's DRi registers. We keep the status and |
| 168 | control registers separated because they don't hold addresses. */ |
| 169 | static CORE_ADDR dr_mirror[DR_NADDR]; |
| 170 | static unsigned dr_status_mirror, dr_control_mirror; |
| 171 | |
| 172 | /* Reference counts for each debug register. */ |
| 173 | static int dr_ref_count[DR_NADDR]; |
| 174 | |
| 175 | /* Whether or not to print the mirrored debug registers. */ |
| 176 | static int maint_show_dr; |
| 177 | |
| 178 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ |
| 179 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; |
| 180 | |
| 181 | /* Internal functions. */ |
| 182 | |
| 183 | /* Return the value of a 4-bit field for DR7 suitable for watching a |
| 184 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
| 185 | have the value of 1, 2, or 4. */ |
| 186 | static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); |
| 187 | |
| 188 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned |
| 189 | according to the length of the region to watch. LEN_RW_BITS is the |
| 190 | value of the bit-field from DR7 which describes the length and |
| 191 | access type of the region to be watched by this watchpoint. Return |
| 192 | 0 on success, -1 on failure. */ |
| 193 | static int i386_insert_aligned_watchpoint (CORE_ADDR addr, |
| 194 | unsigned len_rw_bits); |
| 195 | |
| 196 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned |
| 197 | according to the length of the region to watch. LEN_RW_BITS is the |
| 198 | value of the bits from DR7 which describes the length and access |
| 199 | type of the region watched by this watchpoint. Return 0 on |
| 200 | success, -1 on failure. */ |
| 201 | static int i386_remove_aligned_watchpoint (CORE_ADDR addr, |
| 202 | unsigned len_rw_bits); |
| 203 | |
| 204 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the |
| 205 | number of debug registers required to watch a region at address |
| 206 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on |
| 207 | successful insertion or removal, a positive number when queried |
| 208 | about the number of registers, or -1 on failure. If WHAT is not a |
| 209 | valid value, bombs through internal_error. */ |
| 210 | static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what, |
| 211 | CORE_ADDR addr, int len, |
| 212 | enum target_hw_bp_type type); |
| 213 | |
| 214 | /* Implementation. */ |
| 215 | |
| 216 | /* Clear the reference counts and forget everything we knew about the |
| 217 | debug registers. */ |
| 218 | |
| 219 | void |
| 220 | i386_cleanup_dregs (void) |
| 221 | { |
| 222 | int i; |
| 223 | |
| 224 | ALL_DEBUG_REGISTERS(i) |
| 225 | { |
| 226 | dr_mirror[i] = 0; |
| 227 | dr_ref_count[i] = 0; |
| 228 | } |
| 229 | dr_control_mirror = 0; |
| 230 | dr_status_mirror = 0; |
| 231 | } |
| 232 | |
| 233 | /* Reset all debug registers at each new startup to avoid missing |
| 234 | watchpoints after restart. */ |
| 235 | |
| 236 | void |
| 237 | child_post_startup_inferior (ptid_t ptid) |
| 238 | { |
| 239 | i386_cleanup_dregs (); |
| 240 | } |
| 241 | |
| 242 | /* Print the values of the mirrored debug registers. This is called |
| 243 | when maint_show_dr is non-zero. To set that up, type "maint |
| 244 | show-debug-regs" at GDB's prompt. */ |
| 245 | |
| 246 | static void |
| 247 | i386_show_dr (const char *func, CORE_ADDR addr, |
| 248 | int len, enum target_hw_bp_type type) |
| 249 | { |
| 250 | int i; |
| 251 | |
| 252 | puts_unfiltered (func); |
| 253 | if (addr || len) |
| 254 | printf_unfiltered (" (addr=%lx, len=%d, type=%s)", |
| 255 | /* This code is for ia32, so casting CORE_ADDR |
| 256 | to unsigned long should be okay. */ |
| 257 | (unsigned long)addr, len, |
| 258 | type == hw_write ? "data-write" |
| 259 | : (type == hw_read ? "data-read" |
| 260 | : (type == hw_access ? "data-read/write" |
| 261 | : (type == hw_execute ? "instruction-execute" |
| 262 | /* FIXME: if/when I/O read/write |
| 263 | watchpoints are supported, add them |
| 264 | here. */ |
| 265 | : "??unknown??")))); |
| 266 | puts_unfiltered (":\n"); |
| 267 | printf_unfiltered ("\tCONTROL (DR7): %08x STATUS (DR6): %08x\n", |
| 268 | dr_control_mirror, dr_status_mirror); |
| 269 | ALL_DEBUG_REGISTERS(i) |
| 270 | { |
| 271 | printf_unfiltered ("\ |
| 272 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", |
| 273 | i, paddr(dr_mirror[i]), dr_ref_count[i], |
| 274 | i+1, paddr(dr_mirror[i+1]), dr_ref_count[i+1]); |
| 275 | i++; |
| 276 | } |
| 277 | } |
| 278 | |
| 279 | /* Return the value of a 4-bit field for DR7 suitable for watching a |
| 280 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
| 281 | have the value of 1, 2, or 4. */ |
| 282 | |
| 283 | static unsigned |
| 284 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) |
| 285 | { |
| 286 | unsigned rw; |
| 287 | |
| 288 | switch (type) |
| 289 | { |
| 290 | case hw_execute: |
| 291 | rw = DR_RW_EXECUTE; |
| 292 | break; |
| 293 | case hw_write: |
| 294 | rw = DR_RW_WRITE; |
| 295 | break; |
| 296 | case hw_read: |
| 297 | /* The i386 doesn't support data-read watchpoints. */ |
| 298 | case hw_access: |
| 299 | rw = DR_RW_READ; |
| 300 | break; |
| 301 | #if 0 |
| 302 | /* Not yet supported. */ |
| 303 | case hw_io_access: |
| 304 | rw = DR_RW_IORW; |
| 305 | break; |
| 306 | #endif |
| 307 | default: |
| 308 | internal_error (__FILE__, __LINE__, _("\ |
| 309 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), |
| 310 | (int) type); |
| 311 | } |
| 312 | |
| 313 | switch (len) |
| 314 | { |
| 315 | case 1: |
| 316 | return (DR_LEN_1 | rw); |
| 317 | case 2: |
| 318 | return (DR_LEN_2 | rw); |
| 319 | case 4: |
| 320 | return (DR_LEN_4 | rw); |
| 321 | case 8: |
| 322 | if (TARGET_HAS_DR_LEN_8) |
| 323 | return (DR_LEN_8 | rw); |
| 324 | default: |
| 325 | internal_error (__FILE__, __LINE__, _("\ |
| 326 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); |
| 327 | } |
| 328 | } |
| 329 | |
| 330 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned |
| 331 | according to the length of the region to watch. LEN_RW_BITS is the |
| 332 | value of the bits from DR7 which describes the length and access |
| 333 | type of the region to be watched by this watchpoint. Return 0 on |
| 334 | success, -1 on failure. */ |
| 335 | |
| 336 | static int |
| 337 | i386_insert_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) |
| 338 | { |
| 339 | int i; |
| 340 | |
| 341 | /* First, look for an occupied debug register with the same address |
| 342 | and the same RW and LEN definitions. If we find one, we can |
| 343 | reuse it for this watchpoint as well (and save a register). */ |
| 344 | ALL_DEBUG_REGISTERS(i) |
| 345 | { |
| 346 | if (!I386_DR_VACANT (i) |
| 347 | && dr_mirror[i] == addr |
| 348 | && I386_DR_GET_RW_LEN (i) == len_rw_bits) |
| 349 | { |
| 350 | dr_ref_count[i]++; |
| 351 | return 0; |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | /* Next, look for a vacant debug register. */ |
| 356 | ALL_DEBUG_REGISTERS(i) |
| 357 | { |
| 358 | if (I386_DR_VACANT (i)) |
| 359 | break; |
| 360 | } |
| 361 | |
| 362 | /* No more debug registers! */ |
| 363 | if (i >= DR_NADDR) |
| 364 | return -1; |
| 365 | |
| 366 | /* Now set up the register I to watch our region. */ |
| 367 | |
| 368 | /* Record the info in our local mirrored array. */ |
| 369 | dr_mirror[i] = addr; |
| 370 | dr_ref_count[i] = 1; |
| 371 | I386_DR_SET_RW_LEN (i, len_rw_bits); |
| 372 | /* Note: we only enable the watchpoint locally, i.e. in the current |
| 373 | task. Currently, no i386 target allows or supports global |
| 374 | watchpoints; however, if any target would want that in the |
| 375 | future, GDB should probably provide a command to control whether |
| 376 | to enable watchpoints globally or locally, and the code below |
| 377 | should use global or local enable and slow-down flags as |
| 378 | appropriate. */ |
| 379 | I386_DR_LOCAL_ENABLE (i); |
| 380 | dr_control_mirror |= DR_LOCAL_SLOWDOWN; |
| 381 | dr_control_mirror &= I386_DR_CONTROL_MASK; |
| 382 | |
| 383 | /* Finally, actually pass the info to the inferior. */ |
| 384 | I386_DR_LOW_SET_ADDR (i, addr); |
| 385 | I386_DR_LOW_SET_CONTROL (dr_control_mirror); |
| 386 | |
| 387 | return 0; |
| 388 | } |
| 389 | |
| 390 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned |
| 391 | according to the length of the region to watch. LEN_RW_BITS is the |
| 392 | value of the bits from DR7 which describes the length and access |
| 393 | type of the region watched by this watchpoint. Return 0 on |
| 394 | success, -1 on failure. */ |
| 395 | |
| 396 | static int |
| 397 | i386_remove_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) |
| 398 | { |
| 399 | int i, retval = -1; |
| 400 | |
| 401 | ALL_DEBUG_REGISTERS(i) |
| 402 | { |
| 403 | if (!I386_DR_VACANT (i) |
| 404 | && dr_mirror[i] == addr |
| 405 | && I386_DR_GET_RW_LEN (i) == len_rw_bits) |
| 406 | { |
| 407 | if (--dr_ref_count[i] == 0) /* no longer in use? */ |
| 408 | { |
| 409 | /* Reset our mirror. */ |
| 410 | dr_mirror[i] = 0; |
| 411 | I386_DR_DISABLE (i); |
| 412 | /* Reset it in the inferior. */ |
| 413 | I386_DR_LOW_SET_CONTROL (dr_control_mirror); |
| 414 | I386_DR_LOW_RESET_ADDR (i); |
| 415 | } |
| 416 | retval = 0; |
| 417 | } |
| 418 | } |
| 419 | |
| 420 | return retval; |
| 421 | } |
| 422 | |
| 423 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the |
| 424 | number of debug registers required to watch a region at address |
| 425 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on |
| 426 | successful insertion or removal, a positive number when queried |
| 427 | about the number of registers, or -1 on failure. If WHAT is not a |
| 428 | valid value, bombs through internal_error. */ |
| 429 | |
| 430 | static int |
| 431 | i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len, |
| 432 | enum target_hw_bp_type type) |
| 433 | { |
| 434 | int retval = 0, status = 0; |
| 435 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
| 436 | |
| 437 | static int size_try_array[8][8] = |
| 438 | { |
| 439 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
| 440 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ |
| 441 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ |
| 442 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ |
| 443 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ |
| 444 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ |
| 445 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ |
| 446 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ |
| 447 | }; |
| 448 | |
| 449 | while (len > 0) |
| 450 | { |
| 451 | int align = addr % max_wp_len; |
| 452 | /* Four (eight on AMD64) is the maximum length a debug register |
| 453 | can watch. */ |
| 454 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
| 455 | int size = size_try_array[try][align]; |
| 456 | |
| 457 | if (what == WP_COUNT) |
| 458 | { |
| 459 | /* size_try_array[] is defined such that each iteration |
| 460 | through the loop is guaranteed to produce an address and a |
| 461 | size that can be watched with a single debug register. |
| 462 | Thus, for counting the registers required to watch a |
| 463 | region, we simply need to increment the count on each |
| 464 | iteration. */ |
| 465 | retval++; |
| 466 | } |
| 467 | else |
| 468 | { |
| 469 | unsigned len_rw = i386_length_and_rw_bits (size, type); |
| 470 | |
| 471 | if (what == WP_INSERT) |
| 472 | status = i386_insert_aligned_watchpoint (addr, len_rw); |
| 473 | else if (what == WP_REMOVE) |
| 474 | status = i386_remove_aligned_watchpoint (addr, len_rw); |
| 475 | else |
| 476 | internal_error (__FILE__, __LINE__, _("\ |
| 477 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), |
| 478 | (int)what); |
| 479 | /* We keep the loop going even after a failure, because some |
| 480 | of the other aligned watchpoints might still succeed |
| 481 | (e.g. if they watch addresses that are already watched, |
| 482 | in which case we just increment the reference counts of |
| 483 | occupied debug registers). If we break out of the loop |
| 484 | too early, we could cause those addresses watched by |
| 485 | other watchpoints to be disabled when breakpoint.c reacts |
| 486 | to our failure to insert this watchpoint and tries to |
| 487 | remove it. */ |
| 488 | if (status) |
| 489 | retval = status; |
| 490 | } |
| 491 | |
| 492 | addr += size; |
| 493 | len -= size; |
| 494 | } |
| 495 | |
| 496 | return retval; |
| 497 | } |
| 498 | |
| 499 | /* Insert a watchpoint to watch a memory region which starts at |
| 500 | address ADDR and whose length is LEN bytes. Watch memory accesses |
| 501 | of the type TYPE. Return 0 on success, -1 on failure. */ |
| 502 | |
| 503 | int |
| 504 | i386_insert_watchpoint (CORE_ADDR addr, int len, int type) |
| 505 | { |
| 506 | int retval; |
| 507 | |
| 508 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
| 509 | || addr % len != 0) |
| 510 | retval = i386_handle_nonaligned_watchpoint (WP_INSERT, addr, len, type); |
| 511 | else |
| 512 | { |
| 513 | unsigned len_rw = i386_length_and_rw_bits (len, type); |
| 514 | |
| 515 | retval = i386_insert_aligned_watchpoint (addr, len_rw); |
| 516 | } |
| 517 | |
| 518 | if (maint_show_dr) |
| 519 | i386_show_dr ("insert_watchpoint", addr, len, type); |
| 520 | |
| 521 | return retval; |
| 522 | } |
| 523 | |
| 524 | /* Remove a watchpoint that watched the memory region which starts at |
| 525 | address ADDR, whose length is LEN bytes, and for accesses of the |
| 526 | type TYPE. Return 0 on success, -1 on failure. */ |
| 527 | int |
| 528 | i386_remove_watchpoint (CORE_ADDR addr, int len, int type) |
| 529 | { |
| 530 | int retval; |
| 531 | |
| 532 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
| 533 | || addr % len != 0) |
| 534 | retval = i386_handle_nonaligned_watchpoint (WP_REMOVE, addr, len, type); |
| 535 | else |
| 536 | { |
| 537 | unsigned len_rw = i386_length_and_rw_bits (len, type); |
| 538 | |
| 539 | retval = i386_remove_aligned_watchpoint (addr, len_rw); |
| 540 | } |
| 541 | |
| 542 | if (maint_show_dr) |
| 543 | i386_show_dr ("remove_watchpoint", addr, len, type); |
| 544 | |
| 545 | return retval; |
| 546 | } |
| 547 | |
| 548 | /* Return non-zero if we can watch a memory region that starts at |
| 549 | address ADDR and whose length is LEN bytes. */ |
| 550 | |
| 551 | int |
| 552 | i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) |
| 553 | { |
| 554 | int nregs; |
| 555 | |
| 556 | /* Compute how many aligned watchpoints we would need to cover this |
| 557 | region. */ |
| 558 | nregs = i386_handle_nonaligned_watchpoint (WP_COUNT, addr, len, hw_write); |
| 559 | return nregs <= DR_NADDR ? 1 : 0; |
| 560 | } |
| 561 | |
| 562 | /* If the inferior has some watchpoint that triggered, set the |
| 563 | address associated with that watchpoint and return non-zero. |
| 564 | Otherwise, return zero. */ |
| 565 | |
| 566 | int |
| 567 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
| 568 | { |
| 569 | CORE_ADDR addr = 0; |
| 570 | int i; |
| 571 | int rc = 0; |
| 572 | |
| 573 | dr_status_mirror = I386_DR_LOW_GET_STATUS (); |
| 574 | |
| 575 | ALL_DEBUG_REGISTERS(i) |
| 576 | { |
| 577 | if (I386_DR_WATCH_HIT (i) |
| 578 | /* This second condition makes sure DRi is set up for a data |
| 579 | watchpoint, not a hardware breakpoint. The reason is |
| 580 | that GDB doesn't call the target_stopped_data_address |
| 581 | method except for data watchpoints. In other words, I'm |
| 582 | being paranoiac. */ |
| 583 | && I386_DR_GET_RW_LEN (i) != 0) |
| 584 | { |
| 585 | addr = dr_mirror[i]; |
| 586 | rc = 1; |
| 587 | if (maint_show_dr) |
| 588 | i386_show_dr ("watchpoint_hit", addr, -1, hw_write); |
| 589 | } |
| 590 | } |
| 591 | if (maint_show_dr && addr == 0) |
| 592 | i386_show_dr ("stopped_data_addr", 0, 0, hw_write); |
| 593 | |
| 594 | if (rc) |
| 595 | *addr_p = addr; |
| 596 | return rc; |
| 597 | } |
| 598 | |
| 599 | int |
| 600 | i386_stopped_by_watchpoint (void) |
| 601 | { |
| 602 | CORE_ADDR addr = 0; |
| 603 | return i386_stopped_data_address (¤t_target, &addr); |
| 604 | } |
| 605 | |
| 606 | /* Return non-zero if the inferior has some break/watchpoint that |
| 607 | triggered. */ |
| 608 | |
| 609 | int |
| 610 | i386_stopped_by_hwbp (void) |
| 611 | { |
| 612 | int i; |
| 613 | |
| 614 | dr_status_mirror = I386_DR_LOW_GET_STATUS (); |
| 615 | if (maint_show_dr) |
| 616 | i386_show_dr ("stopped_by_hwbp", 0, 0, hw_execute); |
| 617 | |
| 618 | ALL_DEBUG_REGISTERS(i) |
| 619 | { |
| 620 | if (I386_DR_WATCH_HIT (i)) |
| 621 | return 1; |
| 622 | } |
| 623 | |
| 624 | return 0; |
| 625 | } |
| 626 | |
| 627 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
| 628 | Return 0 on success, EBUSY on failure. */ |
| 629 | int |
| 630 | i386_insert_hw_breakpoint (struct bp_target_info *bp_tgt) |
| 631 | { |
| 632 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
| 633 | CORE_ADDR addr = bp_tgt->placed_address; |
| 634 | int retval = i386_insert_aligned_watchpoint (addr, len_rw) ? EBUSY : 0; |
| 635 | |
| 636 | if (maint_show_dr) |
| 637 | i386_show_dr ("insert_hwbp", addr, 1, hw_execute); |
| 638 | |
| 639 | return retval; |
| 640 | } |
| 641 | |
| 642 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
| 643 | Return 0 on success, -1 on failure. */ |
| 644 | |
| 645 | int |
| 646 | i386_remove_hw_breakpoint (struct bp_target_info *bp_tgt) |
| 647 | { |
| 648 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
| 649 | CORE_ADDR addr = bp_tgt->placed_address; |
| 650 | int retval = i386_remove_aligned_watchpoint (addr, len_rw); |
| 651 | |
| 652 | if (maint_show_dr) |
| 653 | i386_show_dr ("remove_hwbp", addr, 1, hw_execute); |
| 654 | |
| 655 | return retval; |
| 656 | } |
| 657 | |
| 658 | /* Returns the number of hardware watchpoints of type TYPE that we can |
| 659 | set. Value is positive if we can set CNT watchpoints, zero if |
| 660 | setting watchpoints of type TYPE is not supported, and negative if |
| 661 | CNT is more than the maximum number of watchpoints of type TYPE |
| 662 | that we can support. TYPE is one of bp_hardware_watchpoint, |
| 663 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. |
| 664 | CNT is the number of such watchpoints used so far (including this |
| 665 | one). OTHERTYPE is non-zero if other types of watchpoints are |
| 666 | currently enabled. |
| 667 | |
| 668 | We always return 1 here because we don't have enough information |
| 669 | about possible overlap of addresses that they want to watch. As an |
| 670 | extreme example, consider the case where all the watchpoints watch |
| 671 | the same address and the same region length: then we can handle a |
| 672 | virtually unlimited number of watchpoints, due to debug register |
| 673 | sharing implemented via reference counts in i386-nat.c. */ |
| 674 | |
| 675 | static int |
| 676 | i386_can_use_hw_breakpoint (int type, int cnt, int othertype) |
| 677 | { |
| 678 | return 1; |
| 679 | } |
| 680 | |
| 681 | void |
| 682 | i386_use_watchpoints (struct target_ops *t) |
| 683 | { |
| 684 | /* After a watchpoint trap, the PC points to the instruction after the |
| 685 | one that caused the trap. Therefore we don't need to step over it. |
| 686 | But we do need to reset the status register to avoid another trap. */ |
| 687 | t->to_have_continuable_watchpoint = 1; |
| 688 | |
| 689 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; |
| 690 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; |
| 691 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; |
| 692 | t->to_stopped_data_address = i386_stopped_data_address; |
| 693 | t->to_insert_watchpoint = i386_insert_watchpoint; |
| 694 | t->to_remove_watchpoint = i386_remove_watchpoint; |
| 695 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; |
| 696 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; |
| 697 | } |
| 698 | |
| 699 | #endif /* I386_USE_GENERIC_WATCHPOINTS */ |
| 700 | \f |
| 701 | |
| 702 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
| 703 | void _initialize_i386_nat (void); |
| 704 | |
| 705 | void |
| 706 | _initialize_i386_nat (void) |
| 707 | { |
| 708 | #ifdef I386_USE_GENERIC_WATCHPOINTS |
| 709 | /* A maintenance command to enable printing the internal DRi mirror |
| 710 | variables. */ |
| 711 | deprecated_add_set_cmd ("show-debug-regs", class_maintenance, |
| 712 | var_boolean, (char *) &maint_show_dr, _("\ |
| 713 | Set whether to show variables that mirror the x86 debug registers.\n\ |
| 714 | Use \"on\" to enable, \"off\" to disable.\n\ |
| 715 | If enabled, the debug registers values are shown when GDB inserts\n\ |
| 716 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ |
| 717 | triggers a breakpoint or watchpoint."), |
| 718 | &maintenancelist); |
| 719 | #endif |
| 720 | } |