| 1 | /* Intel 386 target-dependent stuff. |
| 2 | |
| 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "opcode/i386.h" |
| 22 | #include "arch-utils.h" |
| 23 | #include "command.h" |
| 24 | #include "dummy-frame.h" |
| 25 | #include "dwarf2-frame.h" |
| 26 | #include "doublest.h" |
| 27 | #include "frame.h" |
| 28 | #include "frame-base.h" |
| 29 | #include "frame-unwind.h" |
| 30 | #include "inferior.h" |
| 31 | #include "gdbcmd.h" |
| 32 | #include "gdbcore.h" |
| 33 | #include "gdbtypes.h" |
| 34 | #include "objfiles.h" |
| 35 | #include "osabi.h" |
| 36 | #include "regcache.h" |
| 37 | #include "reggroups.h" |
| 38 | #include "regset.h" |
| 39 | #include "symfile.h" |
| 40 | #include "symtab.h" |
| 41 | #include "target.h" |
| 42 | #include "value.h" |
| 43 | #include "dis-asm.h" |
| 44 | #include "disasm.h" |
| 45 | #include "remote.h" |
| 46 | #include "exceptions.h" |
| 47 | #include "gdb_assert.h" |
| 48 | #include "gdb_string.h" |
| 49 | |
| 50 | #include "i386-tdep.h" |
| 51 | #include "i387-tdep.h" |
| 52 | #include "i386-xstate.h" |
| 53 | |
| 54 | #include "record.h" |
| 55 | #include <stdint.h> |
| 56 | |
| 57 | #include "features/i386/i386.c" |
| 58 | #include "features/i386/i386-avx.c" |
| 59 | #include "features/i386/i386-mmx.c" |
| 60 | |
| 61 | #include "ax.h" |
| 62 | #include "ax-gdb.h" |
| 63 | |
| 64 | /* Register names. */ |
| 65 | |
| 66 | static const char *i386_register_names[] = |
| 67 | { |
| 68 | "eax", "ecx", "edx", "ebx", |
| 69 | "esp", "ebp", "esi", "edi", |
| 70 | "eip", "eflags", "cs", "ss", |
| 71 | "ds", "es", "fs", "gs", |
| 72 | "st0", "st1", "st2", "st3", |
| 73 | "st4", "st5", "st6", "st7", |
| 74 | "fctrl", "fstat", "ftag", "fiseg", |
| 75 | "fioff", "foseg", "fooff", "fop", |
| 76 | "xmm0", "xmm1", "xmm2", "xmm3", |
| 77 | "xmm4", "xmm5", "xmm6", "xmm7", |
| 78 | "mxcsr" |
| 79 | }; |
| 80 | |
| 81 | static const char *i386_ymm_names[] = |
| 82 | { |
| 83 | "ymm0", "ymm1", "ymm2", "ymm3", |
| 84 | "ymm4", "ymm5", "ymm6", "ymm7", |
| 85 | }; |
| 86 | |
| 87 | static const char *i386_ymmh_names[] = |
| 88 | { |
| 89 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", |
| 90 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", |
| 91 | }; |
| 92 | |
| 93 | /* Register names for MMX pseudo-registers. */ |
| 94 | |
| 95 | static const char *i386_mmx_names[] = |
| 96 | { |
| 97 | "mm0", "mm1", "mm2", "mm3", |
| 98 | "mm4", "mm5", "mm6", "mm7" |
| 99 | }; |
| 100 | |
| 101 | /* Register names for byte pseudo-registers. */ |
| 102 | |
| 103 | static const char *i386_byte_names[] = |
| 104 | { |
| 105 | "al", "cl", "dl", "bl", |
| 106 | "ah", "ch", "dh", "bh" |
| 107 | }; |
| 108 | |
| 109 | /* Register names for word pseudo-registers. */ |
| 110 | |
| 111 | static const char *i386_word_names[] = |
| 112 | { |
| 113 | "ax", "cx", "dx", "bx", |
| 114 | "", "bp", "si", "di" |
| 115 | }; |
| 116 | |
| 117 | /* MMX register? */ |
| 118 | |
| 119 | static int |
| 120 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 121 | { |
| 122 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 123 | int mm0_regnum = tdep->mm0_regnum; |
| 124 | |
| 125 | if (mm0_regnum < 0) |
| 126 | return 0; |
| 127 | |
| 128 | regnum -= mm0_regnum; |
| 129 | return regnum >= 0 && regnum < tdep->num_mmx_regs; |
| 130 | } |
| 131 | |
| 132 | /* Byte register? */ |
| 133 | |
| 134 | int |
| 135 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 136 | { |
| 137 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 138 | |
| 139 | regnum -= tdep->al_regnum; |
| 140 | return regnum >= 0 && regnum < tdep->num_byte_regs; |
| 141 | } |
| 142 | |
| 143 | /* Word register? */ |
| 144 | |
| 145 | int |
| 146 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 147 | { |
| 148 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 149 | |
| 150 | regnum -= tdep->ax_regnum; |
| 151 | return regnum >= 0 && regnum < tdep->num_word_regs; |
| 152 | } |
| 153 | |
| 154 | /* Dword register? */ |
| 155 | |
| 156 | int |
| 157 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 158 | { |
| 159 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 160 | int eax_regnum = tdep->eax_regnum; |
| 161 | |
| 162 | if (eax_regnum < 0) |
| 163 | return 0; |
| 164 | |
| 165 | regnum -= eax_regnum; |
| 166 | return regnum >= 0 && regnum < tdep->num_dword_regs; |
| 167 | } |
| 168 | |
| 169 | static int |
| 170 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 171 | { |
| 172 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 173 | int ymm0h_regnum = tdep->ymm0h_regnum; |
| 174 | |
| 175 | if (ymm0h_regnum < 0) |
| 176 | return 0; |
| 177 | |
| 178 | regnum -= ymm0h_regnum; |
| 179 | return regnum >= 0 && regnum < tdep->num_ymm_regs; |
| 180 | } |
| 181 | |
| 182 | /* AVX register? */ |
| 183 | |
| 184 | int |
| 185 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 186 | { |
| 187 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 188 | int ymm0_regnum = tdep->ymm0_regnum; |
| 189 | |
| 190 | if (ymm0_regnum < 0) |
| 191 | return 0; |
| 192 | |
| 193 | regnum -= ymm0_regnum; |
| 194 | return regnum >= 0 && regnum < tdep->num_ymm_regs; |
| 195 | } |
| 196 | |
| 197 | /* SSE register? */ |
| 198 | |
| 199 | int |
| 200 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 201 | { |
| 202 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 203 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
| 204 | |
| 205 | if (num_xmm_regs == 0) |
| 206 | return 0; |
| 207 | |
| 208 | regnum -= I387_XMM0_REGNUM (tdep); |
| 209 | return regnum >= 0 && regnum < num_xmm_regs; |
| 210 | } |
| 211 | |
| 212 | static int |
| 213 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 214 | { |
| 215 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 216 | |
| 217 | if (I387_NUM_XMM_REGS (tdep) == 0) |
| 218 | return 0; |
| 219 | |
| 220 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
| 221 | } |
| 222 | |
| 223 | /* FP register? */ |
| 224 | |
| 225 | int |
| 226 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 227 | { |
| 228 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 229 | |
| 230 | if (I387_ST0_REGNUM (tdep) < 0) |
| 231 | return 0; |
| 232 | |
| 233 | return (I387_ST0_REGNUM (tdep) <= regnum |
| 234 | && regnum < I387_FCTRL_REGNUM (tdep)); |
| 235 | } |
| 236 | |
| 237 | int |
| 238 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
| 239 | { |
| 240 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 241 | |
| 242 | if (I387_ST0_REGNUM (tdep) < 0) |
| 243 | return 0; |
| 244 | |
| 245 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
| 246 | && regnum < I387_XMM0_REGNUM (tdep)); |
| 247 | } |
| 248 | |
| 249 | /* Return the name of register REGNUM, or the empty string if it is |
| 250 | an anonymous register. */ |
| 251 | |
| 252 | static const char * |
| 253 | i386_register_name (struct gdbarch *gdbarch, int regnum) |
| 254 | { |
| 255 | /* Hide the upper YMM registers. */ |
| 256 | if (i386_ymmh_regnum_p (gdbarch, regnum)) |
| 257 | return ""; |
| 258 | |
| 259 | return tdesc_register_name (gdbarch, regnum); |
| 260 | } |
| 261 | |
| 262 | /* Return the name of register REGNUM. */ |
| 263 | |
| 264 | const char * |
| 265 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
| 266 | { |
| 267 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 268 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
| 269 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; |
| 270 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
| 271 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; |
| 272 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
| 273 | return i386_byte_names[regnum - tdep->al_regnum]; |
| 274 | else if (i386_word_regnum_p (gdbarch, regnum)) |
| 275 | return i386_word_names[regnum - tdep->ax_regnum]; |
| 276 | |
| 277 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 278 | } |
| 279 | |
| 280 | /* Convert a dbx register number REG to the appropriate register |
| 281 | number used by GDB. */ |
| 282 | |
| 283 | static int |
| 284 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 285 | { |
| 286 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 287 | |
| 288 | /* This implements what GCC calls the "default" register map |
| 289 | (dbx_register_map[]). */ |
| 290 | |
| 291 | if (reg >= 0 && reg <= 7) |
| 292 | { |
| 293 | /* General-purpose registers. The debug info calls %ebp |
| 294 | register 4, and %esp register 5. */ |
| 295 | if (reg == 4) |
| 296 | return 5; |
| 297 | else if (reg == 5) |
| 298 | return 4; |
| 299 | else return reg; |
| 300 | } |
| 301 | else if (reg >= 12 && reg <= 19) |
| 302 | { |
| 303 | /* Floating-point registers. */ |
| 304 | return reg - 12 + I387_ST0_REGNUM (tdep); |
| 305 | } |
| 306 | else if (reg >= 21 && reg <= 28) |
| 307 | { |
| 308 | /* SSE registers. */ |
| 309 | int ymm0_regnum = tdep->ymm0_regnum; |
| 310 | |
| 311 | if (ymm0_regnum >= 0 |
| 312 | && i386_xmm_regnum_p (gdbarch, reg)) |
| 313 | return reg - 21 + ymm0_regnum; |
| 314 | else |
| 315 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
| 316 | } |
| 317 | else if (reg >= 29 && reg <= 36) |
| 318 | { |
| 319 | /* MMX registers. */ |
| 320 | return reg - 29 + I387_MM0_REGNUM (tdep); |
| 321 | } |
| 322 | |
| 323 | /* This will hopefully provoke a warning. */ |
| 324 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
| 325 | } |
| 326 | |
| 327 | /* Convert SVR4 register number REG to the appropriate register number |
| 328 | used by GDB. */ |
| 329 | |
| 330 | static int |
| 331 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 332 | { |
| 333 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 334 | |
| 335 | /* This implements the GCC register map that tries to be compatible |
| 336 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ |
| 337 | |
| 338 | /* The SVR4 register numbering includes %eip and %eflags, and |
| 339 | numbers the floating point registers differently. */ |
| 340 | if (reg >= 0 && reg <= 9) |
| 341 | { |
| 342 | /* General-purpose registers. */ |
| 343 | return reg; |
| 344 | } |
| 345 | else if (reg >= 11 && reg <= 18) |
| 346 | { |
| 347 | /* Floating-point registers. */ |
| 348 | return reg - 11 + I387_ST0_REGNUM (tdep); |
| 349 | } |
| 350 | else if (reg >= 21 && reg <= 36) |
| 351 | { |
| 352 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
| 353 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
| 354 | } |
| 355 | |
| 356 | switch (reg) |
| 357 | { |
| 358 | case 37: return I387_FCTRL_REGNUM (tdep); |
| 359 | case 38: return I387_FSTAT_REGNUM (tdep); |
| 360 | case 39: return I387_MXCSR_REGNUM (tdep); |
| 361 | case 40: return I386_ES_REGNUM; |
| 362 | case 41: return I386_CS_REGNUM; |
| 363 | case 42: return I386_SS_REGNUM; |
| 364 | case 43: return I386_DS_REGNUM; |
| 365 | case 44: return I386_FS_REGNUM; |
| 366 | case 45: return I386_GS_REGNUM; |
| 367 | } |
| 368 | |
| 369 | /* This will hopefully provoke a warning. */ |
| 370 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
| 371 | } |
| 372 | |
| 373 | \f |
| 374 | |
| 375 | /* This is the variable that is set with "set disassembly-flavor", and |
| 376 | its legitimate values. */ |
| 377 | static const char att_flavor[] = "att"; |
| 378 | static const char intel_flavor[] = "intel"; |
| 379 | static const char *const valid_flavors[] = |
| 380 | { |
| 381 | att_flavor, |
| 382 | intel_flavor, |
| 383 | NULL |
| 384 | }; |
| 385 | static const char *disassembly_flavor = att_flavor; |
| 386 | \f |
| 387 | |
| 388 | /* Use the program counter to determine the contents and size of a |
| 389 | breakpoint instruction. Return a pointer to a string of bytes that |
| 390 | encode a breakpoint instruction, store the length of the string in |
| 391 | *LEN and optionally adjust *PC to point to the correct memory |
| 392 | location for inserting the breakpoint. |
| 393 | |
| 394 | On the i386 we have a single breakpoint that fits in a single byte |
| 395 | and can be inserted anywhere. |
| 396 | |
| 397 | This function is 64-bit safe. */ |
| 398 | |
| 399 | static const gdb_byte * |
| 400 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
| 401 | { |
| 402 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
| 403 | |
| 404 | *len = sizeof (break_insn); |
| 405 | return break_insn; |
| 406 | } |
| 407 | \f |
| 408 | /* Displaced instruction handling. */ |
| 409 | |
| 410 | /* Skip the legacy instruction prefixes in INSN. |
| 411 | Not all prefixes are valid for any particular insn |
| 412 | but we needn't care, the insn will fault if it's invalid. |
| 413 | The result is a pointer to the first opcode byte, |
| 414 | or NULL if we run off the end of the buffer. */ |
| 415 | |
| 416 | static gdb_byte * |
| 417 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) |
| 418 | { |
| 419 | gdb_byte *end = insn + max_len; |
| 420 | |
| 421 | while (insn < end) |
| 422 | { |
| 423 | switch (*insn) |
| 424 | { |
| 425 | case DATA_PREFIX_OPCODE: |
| 426 | case ADDR_PREFIX_OPCODE: |
| 427 | case CS_PREFIX_OPCODE: |
| 428 | case DS_PREFIX_OPCODE: |
| 429 | case ES_PREFIX_OPCODE: |
| 430 | case FS_PREFIX_OPCODE: |
| 431 | case GS_PREFIX_OPCODE: |
| 432 | case SS_PREFIX_OPCODE: |
| 433 | case LOCK_PREFIX_OPCODE: |
| 434 | case REPE_PREFIX_OPCODE: |
| 435 | case REPNE_PREFIX_OPCODE: |
| 436 | ++insn; |
| 437 | continue; |
| 438 | default: |
| 439 | return insn; |
| 440 | } |
| 441 | } |
| 442 | |
| 443 | return NULL; |
| 444 | } |
| 445 | |
| 446 | static int |
| 447 | i386_absolute_jmp_p (const gdb_byte *insn) |
| 448 | { |
| 449 | /* jmp far (absolute address in operand). */ |
| 450 | if (insn[0] == 0xea) |
| 451 | return 1; |
| 452 | |
| 453 | if (insn[0] == 0xff) |
| 454 | { |
| 455 | /* jump near, absolute indirect (/4). */ |
| 456 | if ((insn[1] & 0x38) == 0x20) |
| 457 | return 1; |
| 458 | |
| 459 | /* jump far, absolute indirect (/5). */ |
| 460 | if ((insn[1] & 0x38) == 0x28) |
| 461 | return 1; |
| 462 | } |
| 463 | |
| 464 | return 0; |
| 465 | } |
| 466 | |
| 467 | static int |
| 468 | i386_absolute_call_p (const gdb_byte *insn) |
| 469 | { |
| 470 | /* call far, absolute. */ |
| 471 | if (insn[0] == 0x9a) |
| 472 | return 1; |
| 473 | |
| 474 | if (insn[0] == 0xff) |
| 475 | { |
| 476 | /* Call near, absolute indirect (/2). */ |
| 477 | if ((insn[1] & 0x38) == 0x10) |
| 478 | return 1; |
| 479 | |
| 480 | /* Call far, absolute indirect (/3). */ |
| 481 | if ((insn[1] & 0x38) == 0x18) |
| 482 | return 1; |
| 483 | } |
| 484 | |
| 485 | return 0; |
| 486 | } |
| 487 | |
| 488 | static int |
| 489 | i386_ret_p (const gdb_byte *insn) |
| 490 | { |
| 491 | switch (insn[0]) |
| 492 | { |
| 493 | case 0xc2: /* ret near, pop N bytes. */ |
| 494 | case 0xc3: /* ret near */ |
| 495 | case 0xca: /* ret far, pop N bytes. */ |
| 496 | case 0xcb: /* ret far */ |
| 497 | case 0xcf: /* iret */ |
| 498 | return 1; |
| 499 | |
| 500 | default: |
| 501 | return 0; |
| 502 | } |
| 503 | } |
| 504 | |
| 505 | static int |
| 506 | i386_call_p (const gdb_byte *insn) |
| 507 | { |
| 508 | if (i386_absolute_call_p (insn)) |
| 509 | return 1; |
| 510 | |
| 511 | /* call near, relative. */ |
| 512 | if (insn[0] == 0xe8) |
| 513 | return 1; |
| 514 | |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
| 519 | length in bytes. Otherwise, return zero. */ |
| 520 | |
| 521 | static int |
| 522 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
| 523 | { |
| 524 | /* Is it 'int $0x80'? */ |
| 525 | if ((insn[0] == 0xcd && insn[1] == 0x80) |
| 526 | /* Or is it 'sysenter'? */ |
| 527 | || (insn[0] == 0x0f && insn[1] == 0x34) |
| 528 | /* Or is it 'syscall'? */ |
| 529 | || (insn[0] == 0x0f && insn[1] == 0x05)) |
| 530 | { |
| 531 | *lengthp = 2; |
| 532 | return 1; |
| 533 | } |
| 534 | |
| 535 | return 0; |
| 536 | } |
| 537 | |
| 538 | /* Some kernels may run one past a syscall insn, so we have to cope. |
| 539 | Otherwise this is just simple_displaced_step_copy_insn. */ |
| 540 | |
| 541 | struct displaced_step_closure * |
| 542 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, |
| 543 | CORE_ADDR from, CORE_ADDR to, |
| 544 | struct regcache *regs) |
| 545 | { |
| 546 | size_t len = gdbarch_max_insn_length (gdbarch); |
| 547 | gdb_byte *buf = xmalloc (len); |
| 548 | |
| 549 | read_memory (from, buf, len); |
| 550 | |
| 551 | /* GDB may get control back after the insn after the syscall. |
| 552 | Presumably this is a kernel bug. |
| 553 | If this is a syscall, make sure there's a nop afterwards. */ |
| 554 | { |
| 555 | int syscall_length; |
| 556 | gdb_byte *insn; |
| 557 | |
| 558 | insn = i386_skip_prefixes (buf, len); |
| 559 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) |
| 560 | insn[syscall_length] = NOP_OPCODE; |
| 561 | } |
| 562 | |
| 563 | write_memory (to, buf, len); |
| 564 | |
| 565 | if (debug_displaced) |
| 566 | { |
| 567 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", |
| 568 | paddress (gdbarch, from), paddress (gdbarch, to)); |
| 569 | displaced_step_dump_bytes (gdb_stdlog, buf, len); |
| 570 | } |
| 571 | |
| 572 | return (struct displaced_step_closure *) buf; |
| 573 | } |
| 574 | |
| 575 | /* Fix up the state of registers and memory after having single-stepped |
| 576 | a displaced instruction. */ |
| 577 | |
| 578 | void |
| 579 | i386_displaced_step_fixup (struct gdbarch *gdbarch, |
| 580 | struct displaced_step_closure *closure, |
| 581 | CORE_ADDR from, CORE_ADDR to, |
| 582 | struct regcache *regs) |
| 583 | { |
| 584 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 585 | |
| 586 | /* The offset we applied to the instruction's address. |
| 587 | This could well be negative (when viewed as a signed 32-bit |
| 588 | value), but ULONGEST won't reflect that, so take care when |
| 589 | applying it. */ |
| 590 | ULONGEST insn_offset = to - from; |
| 591 | |
| 592 | /* Since we use simple_displaced_step_copy_insn, our closure is a |
| 593 | copy of the instruction. */ |
| 594 | gdb_byte *insn = (gdb_byte *) closure; |
| 595 | /* The start of the insn, needed in case we see some prefixes. */ |
| 596 | gdb_byte *insn_start = insn; |
| 597 | |
| 598 | if (debug_displaced) |
| 599 | fprintf_unfiltered (gdb_stdlog, |
| 600 | "displaced: fixup (%s, %s), " |
| 601 | "insn = 0x%02x 0x%02x ...\n", |
| 602 | paddress (gdbarch, from), paddress (gdbarch, to), |
| 603 | insn[0], insn[1]); |
| 604 | |
| 605 | /* The list of issues to contend with here is taken from |
| 606 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. |
| 607 | Yay for Free Software! */ |
| 608 | |
| 609 | /* Relocate the %eip, if necessary. */ |
| 610 | |
| 611 | /* The instruction recognizers we use assume any leading prefixes |
| 612 | have been skipped. */ |
| 613 | { |
| 614 | /* This is the size of the buffer in closure. */ |
| 615 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); |
| 616 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); |
| 617 | /* If there are too many prefixes, just ignore the insn. |
| 618 | It will fault when run. */ |
| 619 | if (opcode != NULL) |
| 620 | insn = opcode; |
| 621 | } |
| 622 | |
| 623 | /* Except in the case of absolute or indirect jump or call |
| 624 | instructions, or a return instruction, the new eip is relative to |
| 625 | the displaced instruction; make it relative. Well, signal |
| 626 | handler returns don't need relocation either, but we use the |
| 627 | value of %eip to recognize those; see below. */ |
| 628 | if (! i386_absolute_jmp_p (insn) |
| 629 | && ! i386_absolute_call_p (insn) |
| 630 | && ! i386_ret_p (insn)) |
| 631 | { |
| 632 | ULONGEST orig_eip; |
| 633 | int insn_len; |
| 634 | |
| 635 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); |
| 636 | |
| 637 | /* A signal trampoline system call changes the %eip, resuming |
| 638 | execution of the main program after the signal handler has |
| 639 | returned. That makes them like 'return' instructions; we |
| 640 | shouldn't relocate %eip. |
| 641 | |
| 642 | But most system calls don't, and we do need to relocate %eip. |
| 643 | |
| 644 | Our heuristic for distinguishing these cases: if stepping |
| 645 | over the system call instruction left control directly after |
| 646 | the instruction, the we relocate --- control almost certainly |
| 647 | doesn't belong in the displaced copy. Otherwise, we assume |
| 648 | the instruction has put control where it belongs, and leave |
| 649 | it unrelocated. Goodness help us if there are PC-relative |
| 650 | system calls. */ |
| 651 | if (i386_syscall_p (insn, &insn_len) |
| 652 | && orig_eip != to + (insn - insn_start) + insn_len |
| 653 | /* GDB can get control back after the insn after the syscall. |
| 654 | Presumably this is a kernel bug. |
| 655 | i386_displaced_step_copy_insn ensures its a nop, |
| 656 | we add one to the length for it. */ |
| 657 | && orig_eip != to + (insn - insn_start) + insn_len + 1) |
| 658 | { |
| 659 | if (debug_displaced) |
| 660 | fprintf_unfiltered (gdb_stdlog, |
| 661 | "displaced: syscall changed %%eip; " |
| 662 | "not relocating\n"); |
| 663 | } |
| 664 | else |
| 665 | { |
| 666 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; |
| 667 | |
| 668 | /* If we just stepped over a breakpoint insn, we don't backup |
| 669 | the pc on purpose; this is to match behaviour without |
| 670 | stepping. */ |
| 671 | |
| 672 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); |
| 673 | |
| 674 | if (debug_displaced) |
| 675 | fprintf_unfiltered (gdb_stdlog, |
| 676 | "displaced: " |
| 677 | "relocated %%eip from %s to %s\n", |
| 678 | paddress (gdbarch, orig_eip), |
| 679 | paddress (gdbarch, eip)); |
| 680 | } |
| 681 | } |
| 682 | |
| 683 | /* If the instruction was PUSHFL, then the TF bit will be set in the |
| 684 | pushed value, and should be cleared. We'll leave this for later, |
| 685 | since GDB already messes up the TF flag when stepping over a |
| 686 | pushfl. */ |
| 687 | |
| 688 | /* If the instruction was a call, the return address now atop the |
| 689 | stack is the address following the copied instruction. We need |
| 690 | to make it the address following the original instruction. */ |
| 691 | if (i386_call_p (insn)) |
| 692 | { |
| 693 | ULONGEST esp; |
| 694 | ULONGEST retaddr; |
| 695 | const ULONGEST retaddr_len = 4; |
| 696 | |
| 697 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); |
| 698 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
| 699 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
| 700 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
| 701 | |
| 702 | if (debug_displaced) |
| 703 | fprintf_unfiltered (gdb_stdlog, |
| 704 | "displaced: relocated return addr at %s to %s\n", |
| 705 | paddress (gdbarch, esp), |
| 706 | paddress (gdbarch, retaddr)); |
| 707 | } |
| 708 | } |
| 709 | |
| 710 | static void |
| 711 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) |
| 712 | { |
| 713 | target_write_memory (*to, buf, len); |
| 714 | *to += len; |
| 715 | } |
| 716 | |
| 717 | static void |
| 718 | i386_relocate_instruction (struct gdbarch *gdbarch, |
| 719 | CORE_ADDR *to, CORE_ADDR oldloc) |
| 720 | { |
| 721 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 722 | gdb_byte buf[I386_MAX_INSN_LEN]; |
| 723 | int offset = 0, rel32, newrel; |
| 724 | int insn_length; |
| 725 | gdb_byte *insn = buf; |
| 726 | |
| 727 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); |
| 728 | |
| 729 | insn_length = gdb_buffered_insn_length (gdbarch, insn, |
| 730 | I386_MAX_INSN_LEN, oldloc); |
| 731 | |
| 732 | /* Get past the prefixes. */ |
| 733 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); |
| 734 | |
| 735 | /* Adjust calls with 32-bit relative addresses as push/jump, with |
| 736 | the address pushed being the location where the original call in |
| 737 | the user program would return to. */ |
| 738 | if (insn[0] == 0xe8) |
| 739 | { |
| 740 | gdb_byte push_buf[16]; |
| 741 | unsigned int ret_addr; |
| 742 | |
| 743 | /* Where "ret" in the original code will return to. */ |
| 744 | ret_addr = oldloc + insn_length; |
| 745 | push_buf[0] = 0x68; /* pushq $... */ |
| 746 | memcpy (&push_buf[1], &ret_addr, 4); |
| 747 | /* Push the push. */ |
| 748 | append_insns (to, 5, push_buf); |
| 749 | |
| 750 | /* Convert the relative call to a relative jump. */ |
| 751 | insn[0] = 0xe9; |
| 752 | |
| 753 | /* Adjust the destination offset. */ |
| 754 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); |
| 755 | newrel = (oldloc - *to) + rel32; |
| 756 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
| 757 | |
| 758 | if (debug_displaced) |
| 759 | fprintf_unfiltered (gdb_stdlog, |
| 760 | "Adjusted insn rel32=%s at %s to" |
| 761 | " rel32=%s at %s\n", |
| 762 | hex_string (rel32), paddress (gdbarch, oldloc), |
| 763 | hex_string (newrel), paddress (gdbarch, *to)); |
| 764 | |
| 765 | /* Write the adjusted jump into its displaced location. */ |
| 766 | append_insns (to, 5, insn); |
| 767 | return; |
| 768 | } |
| 769 | |
| 770 | /* Adjust jumps with 32-bit relative addresses. Calls are already |
| 771 | handled above. */ |
| 772 | if (insn[0] == 0xe9) |
| 773 | offset = 1; |
| 774 | /* Adjust conditional jumps. */ |
| 775 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) |
| 776 | offset = 2; |
| 777 | |
| 778 | if (offset) |
| 779 | { |
| 780 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); |
| 781 | newrel = (oldloc - *to) + rel32; |
| 782 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
| 783 | if (debug_displaced) |
| 784 | fprintf_unfiltered (gdb_stdlog, |
| 785 | "Adjusted insn rel32=%s at %s to" |
| 786 | " rel32=%s at %s\n", |
| 787 | hex_string (rel32), paddress (gdbarch, oldloc), |
| 788 | hex_string (newrel), paddress (gdbarch, *to)); |
| 789 | } |
| 790 | |
| 791 | /* Write the adjusted instructions into their displaced |
| 792 | location. */ |
| 793 | append_insns (to, insn_length, buf); |
| 794 | } |
| 795 | |
| 796 | \f |
| 797 | #ifdef I386_REGNO_TO_SYMMETRY |
| 798 | #error "The Sequent Symmetry is no longer supported." |
| 799 | #endif |
| 800 | |
| 801 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
| 802 | and %esp "belong" to the calling function. Therefore these |
| 803 | registers should be saved if they're going to be modified. */ |
| 804 | |
| 805 | /* The maximum number of saved registers. This should include all |
| 806 | registers mentioned above, and %eip. */ |
| 807 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
| 808 | |
| 809 | struct i386_frame_cache |
| 810 | { |
| 811 | /* Base address. */ |
| 812 | CORE_ADDR base; |
| 813 | int base_p; |
| 814 | LONGEST sp_offset; |
| 815 | CORE_ADDR pc; |
| 816 | |
| 817 | /* Saved registers. */ |
| 818 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; |
| 819 | CORE_ADDR saved_sp; |
| 820 | int saved_sp_reg; |
| 821 | int pc_in_eax; |
| 822 | |
| 823 | /* Stack space reserved for local variables. */ |
| 824 | long locals; |
| 825 | }; |
| 826 | |
| 827 | /* Allocate and initialize a frame cache. */ |
| 828 | |
| 829 | static struct i386_frame_cache * |
| 830 | i386_alloc_frame_cache (void) |
| 831 | { |
| 832 | struct i386_frame_cache *cache; |
| 833 | int i; |
| 834 | |
| 835 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); |
| 836 | |
| 837 | /* Base address. */ |
| 838 | cache->base_p = 0; |
| 839 | cache->base = 0; |
| 840 | cache->sp_offset = -4; |
| 841 | cache->pc = 0; |
| 842 | |
| 843 | /* Saved registers. We initialize these to -1 since zero is a valid |
| 844 | offset (that's where %ebp is supposed to be stored). */ |
| 845 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) |
| 846 | cache->saved_regs[i] = -1; |
| 847 | cache->saved_sp = 0; |
| 848 | cache->saved_sp_reg = -1; |
| 849 | cache->pc_in_eax = 0; |
| 850 | |
| 851 | /* Frameless until proven otherwise. */ |
| 852 | cache->locals = -1; |
| 853 | |
| 854 | return cache; |
| 855 | } |
| 856 | |
| 857 | /* If the instruction at PC is a jump, return the address of its |
| 858 | target. Otherwise, return PC. */ |
| 859 | |
| 860 | static CORE_ADDR |
| 861 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 862 | { |
| 863 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 864 | gdb_byte op; |
| 865 | long delta = 0; |
| 866 | int data16 = 0; |
| 867 | |
| 868 | if (target_read_memory (pc, &op, 1)) |
| 869 | return pc; |
| 870 | |
| 871 | if (op == 0x66) |
| 872 | { |
| 873 | data16 = 1; |
| 874 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
| 875 | } |
| 876 | |
| 877 | switch (op) |
| 878 | { |
| 879 | case 0xe9: |
| 880 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
| 881 | if (data16) |
| 882 | { |
| 883 | delta = read_memory_integer (pc + 2, 2, byte_order); |
| 884 | |
| 885 | /* Include the size of the jmp instruction (including the |
| 886 | 0x66 prefix). */ |
| 887 | delta += 4; |
| 888 | } |
| 889 | else |
| 890 | { |
| 891 | delta = read_memory_integer (pc + 1, 4, byte_order); |
| 892 | |
| 893 | /* Include the size of the jmp instruction. */ |
| 894 | delta += 5; |
| 895 | } |
| 896 | break; |
| 897 | case 0xeb: |
| 898 | /* Relative jump, disp8 (ignore data16). */ |
| 899 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
| 900 | |
| 901 | delta += data16 + 2; |
| 902 | break; |
| 903 | } |
| 904 | |
| 905 | return pc + delta; |
| 906 | } |
| 907 | |
| 908 | /* Check whether PC points at a prologue for a function returning a |
| 909 | structure or union. If so, it updates CACHE and returns the |
| 910 | address of the first instruction after the code sequence that |
| 911 | removes the "hidden" argument from the stack or CURRENT_PC, |
| 912 | whichever is smaller. Otherwise, return PC. */ |
| 913 | |
| 914 | static CORE_ADDR |
| 915 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, |
| 916 | struct i386_frame_cache *cache) |
| 917 | { |
| 918 | /* Functions that return a structure or union start with: |
| 919 | |
| 920 | popl %eax 0x58 |
| 921 | xchgl %eax, (%esp) 0x87 0x04 0x24 |
| 922 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 |
| 923 | |
| 924 | (the System V compiler puts out the second `xchg' instruction, |
| 925 | and the assembler doesn't try to optimize it, so the 'sib' form |
| 926 | gets generated). This sequence is used to get the address of the |
| 927 | return buffer for a function that returns a structure. */ |
| 928 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
| 929 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; |
| 930 | gdb_byte buf[4]; |
| 931 | gdb_byte op; |
| 932 | |
| 933 | if (current_pc <= pc) |
| 934 | return pc; |
| 935 | |
| 936 | if (target_read_memory (pc, &op, 1)) |
| 937 | return pc; |
| 938 | |
| 939 | if (op != 0x58) /* popl %eax */ |
| 940 | return pc; |
| 941 | |
| 942 | if (target_read_memory (pc + 1, buf, 4)) |
| 943 | return pc; |
| 944 | |
| 945 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
| 946 | return pc; |
| 947 | |
| 948 | if (current_pc == pc) |
| 949 | { |
| 950 | cache->sp_offset += 4; |
| 951 | return current_pc; |
| 952 | } |
| 953 | |
| 954 | if (current_pc == pc + 1) |
| 955 | { |
| 956 | cache->pc_in_eax = 1; |
| 957 | return current_pc; |
| 958 | } |
| 959 | |
| 960 | if (buf[1] == proto1[1]) |
| 961 | return pc + 4; |
| 962 | else |
| 963 | return pc + 5; |
| 964 | } |
| 965 | |
| 966 | static CORE_ADDR |
| 967 | i386_skip_probe (CORE_ADDR pc) |
| 968 | { |
| 969 | /* A function may start with |
| 970 | |
| 971 | pushl constant |
| 972 | call _probe |
| 973 | addl $4, %esp |
| 974 | |
| 975 | followed by |
| 976 | |
| 977 | pushl %ebp |
| 978 | |
| 979 | etc. */ |
| 980 | gdb_byte buf[8]; |
| 981 | gdb_byte op; |
| 982 | |
| 983 | if (target_read_memory (pc, &op, 1)) |
| 984 | return pc; |
| 985 | |
| 986 | if (op == 0x68 || op == 0x6a) |
| 987 | { |
| 988 | int delta; |
| 989 | |
| 990 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
| 991 | four-byte operand, depending on the opcode. */ |
| 992 | if (op == 0x68) |
| 993 | delta = 5; |
| 994 | else |
| 995 | delta = 2; |
| 996 | |
| 997 | /* Read the following 8 bytes, which should be `call _probe' (6 |
| 998 | bytes) followed by `addl $4,%esp' (2 bytes). */ |
| 999 | read_memory (pc + delta, buf, sizeof (buf)); |
| 1000 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
| 1001 | pc += delta + sizeof (buf); |
| 1002 | } |
| 1003 | |
| 1004 | return pc; |
| 1005 | } |
| 1006 | |
| 1007 | /* GCC 4.1 and later, can put code in the prologue to realign the |
| 1008 | stack pointer. Check whether PC points to such code, and update |
| 1009 | CACHE accordingly. Return the first instruction after the code |
| 1010 | sequence or CURRENT_PC, whichever is smaller. If we don't |
| 1011 | recognize the code, return PC. */ |
| 1012 | |
| 1013 | static CORE_ADDR |
| 1014 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, |
| 1015 | struct i386_frame_cache *cache) |
| 1016 | { |
| 1017 | /* There are 2 code sequences to re-align stack before the frame |
| 1018 | gets set up: |
| 1019 | |
| 1020 | 1. Use a caller-saved saved register: |
| 1021 | |
| 1022 | leal 4(%esp), %reg |
| 1023 | andl $-XXX, %esp |
| 1024 | pushl -4(%reg) |
| 1025 | |
| 1026 | 2. Use a callee-saved saved register: |
| 1027 | |
| 1028 | pushl %reg |
| 1029 | leal 8(%esp), %reg |
| 1030 | andl $-XXX, %esp |
| 1031 | pushl -4(%reg) |
| 1032 | |
| 1033 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: |
| 1034 | |
| 1035 | 0x83 0xe4 0xf0 andl $-16, %esp |
| 1036 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp |
| 1037 | */ |
| 1038 | |
| 1039 | gdb_byte buf[14]; |
| 1040 | int reg; |
| 1041 | int offset, offset_and; |
| 1042 | static int regnums[8] = { |
| 1043 | I386_EAX_REGNUM, /* %eax */ |
| 1044 | I386_ECX_REGNUM, /* %ecx */ |
| 1045 | I386_EDX_REGNUM, /* %edx */ |
| 1046 | I386_EBX_REGNUM, /* %ebx */ |
| 1047 | I386_ESP_REGNUM, /* %esp */ |
| 1048 | I386_EBP_REGNUM, /* %ebp */ |
| 1049 | I386_ESI_REGNUM, /* %esi */ |
| 1050 | I386_EDI_REGNUM /* %edi */ |
| 1051 | }; |
| 1052 | |
| 1053 | if (target_read_memory (pc, buf, sizeof buf)) |
| 1054 | return pc; |
| 1055 | |
| 1056 | /* Check caller-saved saved register. The first instruction has |
| 1057 | to be "leal 4(%esp), %reg". */ |
| 1058 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) |
| 1059 | { |
| 1060 | /* MOD must be binary 10 and R/M must be binary 100. */ |
| 1061 | if ((buf[1] & 0xc7) != 0x44) |
| 1062 | return pc; |
| 1063 | |
| 1064 | /* REG has register number. */ |
| 1065 | reg = (buf[1] >> 3) & 7; |
| 1066 | offset = 4; |
| 1067 | } |
| 1068 | else |
| 1069 | { |
| 1070 | /* Check callee-saved saved register. The first instruction |
| 1071 | has to be "pushl %reg". */ |
| 1072 | if ((buf[0] & 0xf8) != 0x50) |
| 1073 | return pc; |
| 1074 | |
| 1075 | /* Get register. */ |
| 1076 | reg = buf[0] & 0x7; |
| 1077 | |
| 1078 | /* The next instruction has to be "leal 8(%esp), %reg". */ |
| 1079 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) |
| 1080 | return pc; |
| 1081 | |
| 1082 | /* MOD must be binary 10 and R/M must be binary 100. */ |
| 1083 | if ((buf[2] & 0xc7) != 0x44) |
| 1084 | return pc; |
| 1085 | |
| 1086 | /* REG has register number. Registers in pushl and leal have to |
| 1087 | be the same. */ |
| 1088 | if (reg != ((buf[2] >> 3) & 7)) |
| 1089 | return pc; |
| 1090 | |
| 1091 | offset = 5; |
| 1092 | } |
| 1093 | |
| 1094 | /* Rigister can't be %esp nor %ebp. */ |
| 1095 | if (reg == 4 || reg == 5) |
| 1096 | return pc; |
| 1097 | |
| 1098 | /* The next instruction has to be "andl $-XXX, %esp". */ |
| 1099 | if (buf[offset + 1] != 0xe4 |
| 1100 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) |
| 1101 | return pc; |
| 1102 | |
| 1103 | offset_and = offset; |
| 1104 | offset += buf[offset] == 0x81 ? 6 : 3; |
| 1105 | |
| 1106 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is |
| 1107 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ |
| 1108 | if (buf[offset] != 0xff |
| 1109 | || buf[offset + 2] != 0xfc |
| 1110 | || (buf[offset + 1] & 0xf8) != 0x70) |
| 1111 | return pc; |
| 1112 | |
| 1113 | /* R/M has register. Registers in leal and pushl have to be the |
| 1114 | same. */ |
| 1115 | if (reg != (buf[offset + 1] & 7)) |
| 1116 | return pc; |
| 1117 | |
| 1118 | if (current_pc > pc + offset_and) |
| 1119 | cache->saved_sp_reg = regnums[reg]; |
| 1120 | |
| 1121 | return min (pc + offset + 3, current_pc); |
| 1122 | } |
| 1123 | |
| 1124 | /* Maximum instruction length we need to handle. */ |
| 1125 | #define I386_MAX_MATCHED_INSN_LEN 6 |
| 1126 | |
| 1127 | /* Instruction description. */ |
| 1128 | struct i386_insn |
| 1129 | { |
| 1130 | size_t len; |
| 1131 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
| 1132 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; |
| 1133 | }; |
| 1134 | |
| 1135 | /* Return whether instruction at PC matches PATTERN. */ |
| 1136 | |
| 1137 | static int |
| 1138 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) |
| 1139 | { |
| 1140 | gdb_byte op; |
| 1141 | |
| 1142 | if (target_read_memory (pc, &op, 1)) |
| 1143 | return 0; |
| 1144 | |
| 1145 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
| 1146 | { |
| 1147 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
| 1148 | int insn_matched = 1; |
| 1149 | size_t i; |
| 1150 | |
| 1151 | gdb_assert (pattern.len > 1); |
| 1152 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); |
| 1153 | |
| 1154 | if (target_read_memory (pc + 1, buf, pattern.len - 1)) |
| 1155 | return 0; |
| 1156 | |
| 1157 | for (i = 1; i < pattern.len; i++) |
| 1158 | { |
| 1159 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) |
| 1160 | insn_matched = 0; |
| 1161 | } |
| 1162 | return insn_matched; |
| 1163 | } |
| 1164 | return 0; |
| 1165 | } |
| 1166 | |
| 1167 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return |
| 1168 | the first instruction description that matches. Otherwise, return |
| 1169 | NULL. */ |
| 1170 | |
| 1171 | static struct i386_insn * |
| 1172 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) |
| 1173 | { |
| 1174 | struct i386_insn *pattern; |
| 1175 | |
| 1176 | for (pattern = insn_patterns; pattern->len > 0; pattern++) |
| 1177 | { |
| 1178 | if (i386_match_pattern (pc, *pattern)) |
| 1179 | return pattern; |
| 1180 | } |
| 1181 | |
| 1182 | return NULL; |
| 1183 | } |
| 1184 | |
| 1185 | /* Return whether PC points inside a sequence of instructions that |
| 1186 | matches INSN_PATTERNS. */ |
| 1187 | |
| 1188 | static int |
| 1189 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) |
| 1190 | { |
| 1191 | CORE_ADDR current_pc; |
| 1192 | int ix, i; |
| 1193 | gdb_byte op; |
| 1194 | struct i386_insn *insn; |
| 1195 | |
| 1196 | insn = i386_match_insn (pc, insn_patterns); |
| 1197 | if (insn == NULL) |
| 1198 | return 0; |
| 1199 | |
| 1200 | current_pc = pc; |
| 1201 | ix = insn - insn_patterns; |
| 1202 | for (i = ix - 1; i >= 0; i--) |
| 1203 | { |
| 1204 | current_pc -= insn_patterns[i].len; |
| 1205 | |
| 1206 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
| 1207 | return 0; |
| 1208 | } |
| 1209 | |
| 1210 | current_pc = pc + insn->len; |
| 1211 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) |
| 1212 | { |
| 1213 | if (!i386_match_pattern (current_pc, *insn)) |
| 1214 | return 0; |
| 1215 | |
| 1216 | current_pc += insn->len; |
| 1217 | } |
| 1218 | |
| 1219 | return 1; |
| 1220 | } |
| 1221 | |
| 1222 | /* Some special instructions that might be migrated by GCC into the |
| 1223 | part of the prologue that sets up the new stack frame. Because the |
| 1224 | stack frame hasn't been setup yet, no registers have been saved |
| 1225 | yet, and only the scratch registers %eax, %ecx and %edx can be |
| 1226 | touched. */ |
| 1227 | |
| 1228 | struct i386_insn i386_frame_setup_skip_insns[] = |
| 1229 | { |
| 1230 | /* Check for `movb imm8, r' and `movl imm32, r'. |
| 1231 | |
| 1232 | ??? Should we handle 16-bit operand-sizes here? */ |
| 1233 | |
| 1234 | /* `movb imm8, %al' and `movb imm8, %ah' */ |
| 1235 | /* `movb imm8, %cl' and `movb imm8, %ch' */ |
| 1236 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, |
| 1237 | /* `movb imm8, %dl' and `movb imm8, %dh' */ |
| 1238 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, |
| 1239 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ |
| 1240 | { 5, { 0xb8 }, { 0xfe } }, |
| 1241 | /* `movl imm32, %edx' */ |
| 1242 | { 5, { 0xba }, { 0xff } }, |
| 1243 | |
| 1244 | /* Check for `mov imm32, r32'. Note that there is an alternative |
| 1245 | encoding for `mov m32, %eax'. |
| 1246 | |
| 1247 | ??? Should we handle SIB adressing here? |
| 1248 | ??? Should we handle 16-bit operand-sizes here? */ |
| 1249 | |
| 1250 | /* `movl m32, %eax' */ |
| 1251 | { 5, { 0xa1 }, { 0xff } }, |
| 1252 | /* `movl m32, %eax' and `mov; m32, %ecx' */ |
| 1253 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, |
| 1254 | /* `movl m32, %edx' */ |
| 1255 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, |
| 1256 | |
| 1257 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. |
| 1258 | Because of the symmetry, there are actually two ways to encode |
| 1259 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and |
| 1260 | opcode bytes 0x31 and 0x33 for `xorl'. */ |
| 1261 | |
| 1262 | /* `subl %eax, %eax' */ |
| 1263 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, |
| 1264 | /* `subl %ecx, %ecx' */ |
| 1265 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, |
| 1266 | /* `subl %edx, %edx' */ |
| 1267 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, |
| 1268 | /* `xorl %eax, %eax' */ |
| 1269 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, |
| 1270 | /* `xorl %ecx, %ecx' */ |
| 1271 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, |
| 1272 | /* `xorl %edx, %edx' */ |
| 1273 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, |
| 1274 | { 0 } |
| 1275 | }; |
| 1276 | |
| 1277 | |
| 1278 | /* Check whether PC points to a no-op instruction. */ |
| 1279 | static CORE_ADDR |
| 1280 | i386_skip_noop (CORE_ADDR pc) |
| 1281 | { |
| 1282 | gdb_byte op; |
| 1283 | int check = 1; |
| 1284 | |
| 1285 | if (target_read_memory (pc, &op, 1)) |
| 1286 | return pc; |
| 1287 | |
| 1288 | while (check) |
| 1289 | { |
| 1290 | check = 0; |
| 1291 | /* Ignore `nop' instruction. */ |
| 1292 | if (op == 0x90) |
| 1293 | { |
| 1294 | pc += 1; |
| 1295 | if (target_read_memory (pc, &op, 1)) |
| 1296 | return pc; |
| 1297 | check = 1; |
| 1298 | } |
| 1299 | /* Ignore no-op instruction `mov %edi, %edi'. |
| 1300 | Microsoft system dlls often start with |
| 1301 | a `mov %edi,%edi' instruction. |
| 1302 | The 5 bytes before the function start are |
| 1303 | filled with `nop' instructions. |
| 1304 | This pattern can be used for hot-patching: |
| 1305 | The `mov %edi, %edi' instruction can be replaced by a |
| 1306 | near jump to the location of the 5 `nop' instructions |
| 1307 | which can be replaced by a 32-bit jump to anywhere |
| 1308 | in the 32-bit address space. */ |
| 1309 | |
| 1310 | else if (op == 0x8b) |
| 1311 | { |
| 1312 | if (target_read_memory (pc + 1, &op, 1)) |
| 1313 | return pc; |
| 1314 | |
| 1315 | if (op == 0xff) |
| 1316 | { |
| 1317 | pc += 2; |
| 1318 | if (target_read_memory (pc, &op, 1)) |
| 1319 | return pc; |
| 1320 | |
| 1321 | check = 1; |
| 1322 | } |
| 1323 | } |
| 1324 | } |
| 1325 | return pc; |
| 1326 | } |
| 1327 | |
| 1328 | /* Check whether PC points at a code that sets up a new stack frame. |
| 1329 | If so, it updates CACHE and returns the address of the first |
| 1330 | instruction after the sequence that sets up the frame or LIMIT, |
| 1331 | whichever is smaller. If we don't recognize the code, return PC. */ |
| 1332 | |
| 1333 | static CORE_ADDR |
| 1334 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
| 1335 | CORE_ADDR pc, CORE_ADDR limit, |
| 1336 | struct i386_frame_cache *cache) |
| 1337 | { |
| 1338 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1339 | struct i386_insn *insn; |
| 1340 | gdb_byte op; |
| 1341 | int skip = 0; |
| 1342 | |
| 1343 | if (limit <= pc) |
| 1344 | return limit; |
| 1345 | |
| 1346 | if (target_read_memory (pc, &op, 1)) |
| 1347 | return pc; |
| 1348 | |
| 1349 | if (op == 0x55) /* pushl %ebp */ |
| 1350 | { |
| 1351 | /* Take into account that we've executed the `pushl %ebp' that |
| 1352 | starts this instruction sequence. */ |
| 1353 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
| 1354 | cache->sp_offset += 4; |
| 1355 | pc++; |
| 1356 | |
| 1357 | /* If that's all, return now. */ |
| 1358 | if (limit <= pc) |
| 1359 | return limit; |
| 1360 | |
| 1361 | /* Check for some special instructions that might be migrated by |
| 1362 | GCC into the prologue and skip them. At this point in the |
| 1363 | prologue, code should only touch the scratch registers %eax, |
| 1364 | %ecx and %edx, so while the number of posibilities is sheer, |
| 1365 | it is limited. |
| 1366 | |
| 1367 | Make sure we only skip these instructions if we later see the |
| 1368 | `movl %esp, %ebp' that actually sets up the frame. */ |
| 1369 | while (pc + skip < limit) |
| 1370 | { |
| 1371 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
| 1372 | if (insn == NULL) |
| 1373 | break; |
| 1374 | |
| 1375 | skip += insn->len; |
| 1376 | } |
| 1377 | |
| 1378 | /* If that's all, return now. */ |
| 1379 | if (limit <= pc + skip) |
| 1380 | return limit; |
| 1381 | |
| 1382 | if (target_read_memory (pc + skip, &op, 1)) |
| 1383 | return pc + skip; |
| 1384 | |
| 1385 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
| 1386 | switch (op) |
| 1387 | { |
| 1388 | case 0x8b: |
| 1389 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
| 1390 | != 0xec) |
| 1391 | return pc; |
| 1392 | break; |
| 1393 | case 0x89: |
| 1394 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
| 1395 | != 0xe5) |
| 1396 | return pc; |
| 1397 | break; |
| 1398 | default: |
| 1399 | return pc; |
| 1400 | } |
| 1401 | |
| 1402 | /* OK, we actually have a frame. We just don't know how large |
| 1403 | it is yet. Set its size to zero. We'll adjust it if |
| 1404 | necessary. We also now commit to skipping the special |
| 1405 | instructions mentioned before. */ |
| 1406 | cache->locals = 0; |
| 1407 | pc += (skip + 2); |
| 1408 | |
| 1409 | /* If that's all, return now. */ |
| 1410 | if (limit <= pc) |
| 1411 | return limit; |
| 1412 | |
| 1413 | /* Check for stack adjustment |
| 1414 | |
| 1415 | subl $XXX, %esp |
| 1416 | |
| 1417 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
| 1418 | reg, so we don't have to worry about a data16 prefix. */ |
| 1419 | if (target_read_memory (pc, &op, 1)) |
| 1420 | return pc; |
| 1421 | if (op == 0x83) |
| 1422 | { |
| 1423 | /* `subl' with 8-bit immediate. */ |
| 1424 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
| 1425 | /* Some instruction starting with 0x83 other than `subl'. */ |
| 1426 | return pc; |
| 1427 | |
| 1428 | /* `subl' with signed 8-bit immediate (though it wouldn't |
| 1429 | make sense to be negative). */ |
| 1430 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
| 1431 | return pc + 3; |
| 1432 | } |
| 1433 | else if (op == 0x81) |
| 1434 | { |
| 1435 | /* Maybe it is `subl' with a 32-bit immediate. */ |
| 1436 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
| 1437 | /* Some instruction starting with 0x81 other than `subl'. */ |
| 1438 | return pc; |
| 1439 | |
| 1440 | /* It is `subl' with a 32-bit immediate. */ |
| 1441 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
| 1442 | return pc + 6; |
| 1443 | } |
| 1444 | else |
| 1445 | { |
| 1446 | /* Some instruction other than `subl'. */ |
| 1447 | return pc; |
| 1448 | } |
| 1449 | } |
| 1450 | else if (op == 0xc8) /* enter */ |
| 1451 | { |
| 1452 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
| 1453 | return pc + 4; |
| 1454 | } |
| 1455 | |
| 1456 | return pc; |
| 1457 | } |
| 1458 | |
| 1459 | /* Check whether PC points at code that saves registers on the stack. |
| 1460 | If so, it updates CACHE and returns the address of the first |
| 1461 | instruction after the register saves or CURRENT_PC, whichever is |
| 1462 | smaller. Otherwise, return PC. */ |
| 1463 | |
| 1464 | static CORE_ADDR |
| 1465 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
| 1466 | struct i386_frame_cache *cache) |
| 1467 | { |
| 1468 | CORE_ADDR offset = 0; |
| 1469 | gdb_byte op; |
| 1470 | int i; |
| 1471 | |
| 1472 | if (cache->locals > 0) |
| 1473 | offset -= cache->locals; |
| 1474 | for (i = 0; i < 8 && pc < current_pc; i++) |
| 1475 | { |
| 1476 | if (target_read_memory (pc, &op, 1)) |
| 1477 | return pc; |
| 1478 | if (op < 0x50 || op > 0x57) |
| 1479 | break; |
| 1480 | |
| 1481 | offset -= 4; |
| 1482 | cache->saved_regs[op - 0x50] = offset; |
| 1483 | cache->sp_offset += 4; |
| 1484 | pc++; |
| 1485 | } |
| 1486 | |
| 1487 | return pc; |
| 1488 | } |
| 1489 | |
| 1490 | /* Do a full analysis of the prologue at PC and update CACHE |
| 1491 | accordingly. Bail out early if CURRENT_PC is reached. Return the |
| 1492 | address where the analysis stopped. |
| 1493 | |
| 1494 | We handle these cases: |
| 1495 | |
| 1496 | The startup sequence can be at the start of the function, or the |
| 1497 | function can start with a branch to startup code at the end. |
| 1498 | |
| 1499 | %ebp can be set up with either the 'enter' instruction, or "pushl |
| 1500 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was |
| 1501 | once used in the System V compiler). |
| 1502 | |
| 1503 | Local space is allocated just below the saved %ebp by either the |
| 1504 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
| 1505 | 16-bit unsigned argument for space to allocate, and the 'addl' |
| 1506 | instruction could have either a signed byte, or 32-bit immediate. |
| 1507 | |
| 1508 | Next, the registers used by this function are pushed. With the |
| 1509 | System V compiler they will always be in the order: %edi, %esi, |
| 1510 | %ebx (and sometimes a harmless bug causes it to also save but not |
| 1511 | restore %eax); however, the code below is willing to see the pushes |
| 1512 | in any order, and will handle up to 8 of them. |
| 1513 | |
| 1514 | If the setup sequence is at the end of the function, then the next |
| 1515 | instruction will be a branch back to the start. */ |
| 1516 | |
| 1517 | static CORE_ADDR |
| 1518 | i386_analyze_prologue (struct gdbarch *gdbarch, |
| 1519 | CORE_ADDR pc, CORE_ADDR current_pc, |
| 1520 | struct i386_frame_cache *cache) |
| 1521 | { |
| 1522 | pc = i386_skip_noop (pc); |
| 1523 | pc = i386_follow_jump (gdbarch, pc); |
| 1524 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
| 1525 | pc = i386_skip_probe (pc); |
| 1526 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
| 1527 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
| 1528 | return i386_analyze_register_saves (pc, current_pc, cache); |
| 1529 | } |
| 1530 | |
| 1531 | /* Return PC of first real instruction. */ |
| 1532 | |
| 1533 | static CORE_ADDR |
| 1534 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
| 1535 | { |
| 1536 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1537 | |
| 1538 | static gdb_byte pic_pat[6] = |
| 1539 | { |
| 1540 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ |
| 1541 | 0x5b, /* popl %ebx */ |
| 1542 | }; |
| 1543 | struct i386_frame_cache cache; |
| 1544 | CORE_ADDR pc; |
| 1545 | gdb_byte op; |
| 1546 | int i; |
| 1547 | |
| 1548 | cache.locals = -1; |
| 1549 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
| 1550 | if (cache.locals < 0) |
| 1551 | return start_pc; |
| 1552 | |
| 1553 | /* Found valid frame setup. */ |
| 1554 | |
| 1555 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
| 1556 | to get the address of the global offset table (GOT) into register |
| 1557 | %ebx: |
| 1558 | |
| 1559 | call 0x0 |
| 1560 | popl %ebx |
| 1561 | movl %ebx,x(%ebp) (optional) |
| 1562 | addl y,%ebx |
| 1563 | |
| 1564 | This code is with the rest of the prologue (at the end of the |
| 1565 | function), so we have to skip it to get to the first real |
| 1566 | instruction at the start of the function. */ |
| 1567 | |
| 1568 | for (i = 0; i < 6; i++) |
| 1569 | { |
| 1570 | if (target_read_memory (pc + i, &op, 1)) |
| 1571 | return pc; |
| 1572 | |
| 1573 | if (pic_pat[i] != op) |
| 1574 | break; |
| 1575 | } |
| 1576 | if (i == 6) |
| 1577 | { |
| 1578 | int delta = 6; |
| 1579 | |
| 1580 | if (target_read_memory (pc + delta, &op, 1)) |
| 1581 | return pc; |
| 1582 | |
| 1583 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
| 1584 | { |
| 1585 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
| 1586 | |
| 1587 | if (op == 0x5d) /* One byte offset from %ebp. */ |
| 1588 | delta += 3; |
| 1589 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
| 1590 | delta += 6; |
| 1591 | else /* Unexpected instruction. */ |
| 1592 | delta = 0; |
| 1593 | |
| 1594 | if (target_read_memory (pc + delta, &op, 1)) |
| 1595 | return pc; |
| 1596 | } |
| 1597 | |
| 1598 | /* addl y,%ebx */ |
| 1599 | if (delta > 0 && op == 0x81 |
| 1600 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
| 1601 | == 0xc3) |
| 1602 | { |
| 1603 | pc += delta + 6; |
| 1604 | } |
| 1605 | } |
| 1606 | |
| 1607 | /* If the function starts with a branch (to startup code at the end) |
| 1608 | the last instruction should bring us back to the first |
| 1609 | instruction of the real code. */ |
| 1610 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
| 1611 | pc = i386_follow_jump (gdbarch, pc); |
| 1612 | |
| 1613 | return pc; |
| 1614 | } |
| 1615 | |
| 1616 | /* Check that the code pointed to by PC corresponds to a call to |
| 1617 | __main, skip it if so. Return PC otherwise. */ |
| 1618 | |
| 1619 | CORE_ADDR |
| 1620 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1621 | { |
| 1622 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1623 | gdb_byte op; |
| 1624 | |
| 1625 | if (target_read_memory (pc, &op, 1)) |
| 1626 | return pc; |
| 1627 | if (op == 0xe8) |
| 1628 | { |
| 1629 | gdb_byte buf[4]; |
| 1630 | |
| 1631 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) |
| 1632 | { |
| 1633 | /* Make sure address is computed correctly as a 32bit |
| 1634 | integer even if CORE_ADDR is 64 bit wide. */ |
| 1635 | struct minimal_symbol *s; |
| 1636 | CORE_ADDR call_dest; |
| 1637 | |
| 1638 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
| 1639 | call_dest = call_dest & 0xffffffffU; |
| 1640 | s = lookup_minimal_symbol_by_pc (call_dest); |
| 1641 | if (s != NULL |
| 1642 | && SYMBOL_LINKAGE_NAME (s) != NULL |
| 1643 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) |
| 1644 | pc += 5; |
| 1645 | } |
| 1646 | } |
| 1647 | |
| 1648 | return pc; |
| 1649 | } |
| 1650 | |
| 1651 | /* This function is 64-bit safe. */ |
| 1652 | |
| 1653 | static CORE_ADDR |
| 1654 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 1655 | { |
| 1656 | gdb_byte buf[8]; |
| 1657 | |
| 1658 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
| 1659 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
| 1660 | } |
| 1661 | \f |
| 1662 | |
| 1663 | /* Normal frames. */ |
| 1664 | |
| 1665 | static void |
| 1666 | i386_frame_cache_1 (struct frame_info *this_frame, |
| 1667 | struct i386_frame_cache *cache) |
| 1668 | { |
| 1669 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 1670 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 1671 | gdb_byte buf[4]; |
| 1672 | int i; |
| 1673 | |
| 1674 | cache->pc = get_frame_func (this_frame); |
| 1675 | |
| 1676 | /* In principle, for normal frames, %ebp holds the frame pointer, |
| 1677 | which holds the base address for the current stack frame. |
| 1678 | However, for functions that don't need it, the frame pointer is |
| 1679 | optional. For these "frameless" functions the frame pointer is |
| 1680 | actually the frame pointer of the calling frame. Signal |
| 1681 | trampolines are just a special case of a "frameless" function. |
| 1682 | They (usually) share their frame pointer with the frame that was |
| 1683 | in progress when the signal occurred. */ |
| 1684 | |
| 1685 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
| 1686 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
| 1687 | if (cache->base == 0) |
| 1688 | { |
| 1689 | cache->base_p = 1; |
| 1690 | return; |
| 1691 | } |
| 1692 | |
| 1693 | /* For normal frames, %eip is stored at 4(%ebp). */ |
| 1694 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
| 1695 | |
| 1696 | if (cache->pc != 0) |
| 1697 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
| 1698 | cache); |
| 1699 | |
| 1700 | if (cache->locals < 0) |
| 1701 | { |
| 1702 | /* We didn't find a valid frame, which means that CACHE->base |
| 1703 | currently holds the frame pointer for our calling frame. If |
| 1704 | we're at the start of a function, or somewhere half-way its |
| 1705 | prologue, the function's frame probably hasn't been fully |
| 1706 | setup yet. Try to reconstruct the base address for the stack |
| 1707 | frame by looking at the stack pointer. For truly "frameless" |
| 1708 | functions this might work too. */ |
| 1709 | |
| 1710 | if (cache->saved_sp_reg != -1) |
| 1711 | { |
| 1712 | /* Saved stack pointer has been saved. */ |
| 1713 | get_frame_register (this_frame, cache->saved_sp_reg, buf); |
| 1714 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
| 1715 | |
| 1716 | /* We're halfway aligning the stack. */ |
| 1717 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; |
| 1718 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; |
| 1719 | |
| 1720 | /* This will be added back below. */ |
| 1721 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; |
| 1722 | } |
| 1723 | else if (cache->pc != 0 |
| 1724 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) |
| 1725 | { |
| 1726 | /* We're in a known function, but did not find a frame |
| 1727 | setup. Assume that the function does not use %ebp. |
| 1728 | Alternatively, we may have jumped to an invalid |
| 1729 | address; in that case there is definitely no new |
| 1730 | frame in %ebp. */ |
| 1731 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
| 1732 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
| 1733 | + cache->sp_offset; |
| 1734 | } |
| 1735 | else |
| 1736 | /* We're in an unknown function. We could not find the start |
| 1737 | of the function to analyze the prologue; our best option is |
| 1738 | to assume a typical frame layout with the caller's %ebp |
| 1739 | saved. */ |
| 1740 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
| 1741 | } |
| 1742 | |
| 1743 | if (cache->saved_sp_reg != -1) |
| 1744 | { |
| 1745 | /* Saved stack pointer has been saved (but the SAVED_SP_REG |
| 1746 | register may be unavailable). */ |
| 1747 | if (cache->saved_sp == 0 |
| 1748 | && frame_register_read (this_frame, cache->saved_sp_reg, buf)) |
| 1749 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
| 1750 | } |
| 1751 | /* Now that we have the base address for the stack frame we can |
| 1752 | calculate the value of %esp in the calling frame. */ |
| 1753 | else if (cache->saved_sp == 0) |
| 1754 | cache->saved_sp = cache->base + 8; |
| 1755 | |
| 1756 | /* Adjust all the saved registers such that they contain addresses |
| 1757 | instead of offsets. */ |
| 1758 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) |
| 1759 | if (cache->saved_regs[i] != -1) |
| 1760 | cache->saved_regs[i] += cache->base; |
| 1761 | |
| 1762 | cache->base_p = 1; |
| 1763 | } |
| 1764 | |
| 1765 | static struct i386_frame_cache * |
| 1766 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 1767 | { |
| 1768 | volatile struct gdb_exception ex; |
| 1769 | struct i386_frame_cache *cache; |
| 1770 | |
| 1771 | if (*this_cache) |
| 1772 | return *this_cache; |
| 1773 | |
| 1774 | cache = i386_alloc_frame_cache (); |
| 1775 | *this_cache = cache; |
| 1776 | |
| 1777 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
| 1778 | { |
| 1779 | i386_frame_cache_1 (this_frame, cache); |
| 1780 | } |
| 1781 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
| 1782 | throw_exception (ex); |
| 1783 | |
| 1784 | return cache; |
| 1785 | } |
| 1786 | |
| 1787 | static void |
| 1788 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 1789 | struct frame_id *this_id) |
| 1790 | { |
| 1791 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
| 1792 | |
| 1793 | /* This marks the outermost frame. */ |
| 1794 | if (cache->base == 0) |
| 1795 | return; |
| 1796 | |
| 1797 | /* See the end of i386_push_dummy_call. */ |
| 1798 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
| 1799 | } |
| 1800 | |
| 1801 | static enum unwind_stop_reason |
| 1802 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, |
| 1803 | void **this_cache) |
| 1804 | { |
| 1805 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
| 1806 | |
| 1807 | if (!cache->base_p) |
| 1808 | return UNWIND_UNAVAILABLE; |
| 1809 | |
| 1810 | /* This marks the outermost frame. */ |
| 1811 | if (cache->base == 0) |
| 1812 | return UNWIND_OUTERMOST; |
| 1813 | |
| 1814 | return UNWIND_NO_REASON; |
| 1815 | } |
| 1816 | |
| 1817 | static struct value * |
| 1818 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, |
| 1819 | int regnum) |
| 1820 | { |
| 1821 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
| 1822 | |
| 1823 | gdb_assert (regnum >= 0); |
| 1824 | |
| 1825 | /* The System V ABI says that: |
| 1826 | |
| 1827 | "The flags register contains the system flags, such as the |
| 1828 | direction flag and the carry flag. The direction flag must be |
| 1829 | set to the forward (that is, zero) direction before entry and |
| 1830 | upon exit from a function. Other user flags have no specified |
| 1831 | role in the standard calling sequence and are not preserved." |
| 1832 | |
| 1833 | To guarantee the "upon exit" part of that statement we fake a |
| 1834 | saved flags register that has its direction flag cleared. |
| 1835 | |
| 1836 | Note that GCC doesn't seem to rely on the fact that the direction |
| 1837 | flag is cleared after a function return; it always explicitly |
| 1838 | clears the flag before operations where it matters. |
| 1839 | |
| 1840 | FIXME: kettenis/20030316: I'm not quite sure whether this is the |
| 1841 | right thing to do. The way we fake the flags register here makes |
| 1842 | it impossible to change it. */ |
| 1843 | |
| 1844 | if (regnum == I386_EFLAGS_REGNUM) |
| 1845 | { |
| 1846 | ULONGEST val; |
| 1847 | |
| 1848 | val = get_frame_register_unsigned (this_frame, regnum); |
| 1849 | val &= ~(1 << 10); |
| 1850 | return frame_unwind_got_constant (this_frame, regnum, val); |
| 1851 | } |
| 1852 | |
| 1853 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
| 1854 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
| 1855 | |
| 1856 | if (regnum == I386_ESP_REGNUM |
| 1857 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) |
| 1858 | { |
| 1859 | /* If the SP has been saved, but we don't know where, then this |
| 1860 | means that SAVED_SP_REG register was found unavailable back |
| 1861 | when we built the cache. */ |
| 1862 | if (cache->saved_sp == 0) |
| 1863 | return frame_unwind_got_register (this_frame, regnum, |
| 1864 | cache->saved_sp_reg); |
| 1865 | else |
| 1866 | return frame_unwind_got_constant (this_frame, regnum, |
| 1867 | cache->saved_sp); |
| 1868 | } |
| 1869 | |
| 1870 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
| 1871 | return frame_unwind_got_memory (this_frame, regnum, |
| 1872 | cache->saved_regs[regnum]); |
| 1873 | |
| 1874 | return frame_unwind_got_register (this_frame, regnum, regnum); |
| 1875 | } |
| 1876 | |
| 1877 | static const struct frame_unwind i386_frame_unwind = |
| 1878 | { |
| 1879 | NORMAL_FRAME, |
| 1880 | i386_frame_unwind_stop_reason, |
| 1881 | i386_frame_this_id, |
| 1882 | i386_frame_prev_register, |
| 1883 | NULL, |
| 1884 | default_frame_sniffer |
| 1885 | }; |
| 1886 | |
| 1887 | /* Normal frames, but in a function epilogue. */ |
| 1888 | |
| 1889 | /* The epilogue is defined here as the 'ret' instruction, which will |
| 1890 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
| 1891 | the function's stack frame. */ |
| 1892 | |
| 1893 | static int |
| 1894 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1895 | { |
| 1896 | gdb_byte insn; |
| 1897 | struct symtab *symtab; |
| 1898 | |
| 1899 | symtab = find_pc_symtab (pc); |
| 1900 | if (symtab && symtab->epilogue_unwind_valid) |
| 1901 | return 0; |
| 1902 | |
| 1903 | if (target_read_memory (pc, &insn, 1)) |
| 1904 | return 0; /* Can't read memory at pc. */ |
| 1905 | |
| 1906 | if (insn != 0xc3) /* 'ret' instruction. */ |
| 1907 | return 0; |
| 1908 | |
| 1909 | return 1; |
| 1910 | } |
| 1911 | |
| 1912 | static int |
| 1913 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, |
| 1914 | struct frame_info *this_frame, |
| 1915 | void **this_prologue_cache) |
| 1916 | { |
| 1917 | if (frame_relative_level (this_frame) == 0) |
| 1918 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), |
| 1919 | get_frame_pc (this_frame)); |
| 1920 | else |
| 1921 | return 0; |
| 1922 | } |
| 1923 | |
| 1924 | static struct i386_frame_cache * |
| 1925 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 1926 | { |
| 1927 | volatile struct gdb_exception ex; |
| 1928 | struct i386_frame_cache *cache; |
| 1929 | CORE_ADDR sp; |
| 1930 | |
| 1931 | if (*this_cache) |
| 1932 | return *this_cache; |
| 1933 | |
| 1934 | cache = i386_alloc_frame_cache (); |
| 1935 | *this_cache = cache; |
| 1936 | |
| 1937 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
| 1938 | { |
| 1939 | cache->pc = get_frame_func (this_frame); |
| 1940 | |
| 1941 | /* At this point the stack looks as if we just entered the |
| 1942 | function, with the return address at the top of the |
| 1943 | stack. */ |
| 1944 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); |
| 1945 | cache->base = sp + cache->sp_offset; |
| 1946 | cache->saved_sp = cache->base + 8; |
| 1947 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
| 1948 | |
| 1949 | cache->base_p = 1; |
| 1950 | } |
| 1951 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
| 1952 | throw_exception (ex); |
| 1953 | |
| 1954 | return cache; |
| 1955 | } |
| 1956 | |
| 1957 | static enum unwind_stop_reason |
| 1958 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, |
| 1959 | void **this_cache) |
| 1960 | { |
| 1961 | struct i386_frame_cache *cache = |
| 1962 | i386_epilogue_frame_cache (this_frame, this_cache); |
| 1963 | |
| 1964 | if (!cache->base_p) |
| 1965 | return UNWIND_UNAVAILABLE; |
| 1966 | |
| 1967 | return UNWIND_NO_REASON; |
| 1968 | } |
| 1969 | |
| 1970 | static void |
| 1971 | i386_epilogue_frame_this_id (struct frame_info *this_frame, |
| 1972 | void **this_cache, |
| 1973 | struct frame_id *this_id) |
| 1974 | { |
| 1975 | struct i386_frame_cache *cache = |
| 1976 | i386_epilogue_frame_cache (this_frame, this_cache); |
| 1977 | |
| 1978 | if (!cache->base_p) |
| 1979 | return; |
| 1980 | |
| 1981 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
| 1982 | } |
| 1983 | |
| 1984 | static struct value * |
| 1985 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, |
| 1986 | void **this_cache, int regnum) |
| 1987 | { |
| 1988 | /* Make sure we've initialized the cache. */ |
| 1989 | i386_epilogue_frame_cache (this_frame, this_cache); |
| 1990 | |
| 1991 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
| 1992 | } |
| 1993 | |
| 1994 | static const struct frame_unwind i386_epilogue_frame_unwind = |
| 1995 | { |
| 1996 | NORMAL_FRAME, |
| 1997 | i386_epilogue_frame_unwind_stop_reason, |
| 1998 | i386_epilogue_frame_this_id, |
| 1999 | i386_epilogue_frame_prev_register, |
| 2000 | NULL, |
| 2001 | i386_epilogue_frame_sniffer |
| 2002 | }; |
| 2003 | \f |
| 2004 | |
| 2005 | /* Stack-based trampolines. */ |
| 2006 | |
| 2007 | /* These trampolines are used on cross x86 targets, when taking the |
| 2008 | address of a nested function. When executing these trampolines, |
| 2009 | no stack frame is set up, so we are in a similar situation as in |
| 2010 | epilogues and i386_epilogue_frame_this_id can be re-used. */ |
| 2011 | |
| 2012 | /* Static chain passed in register. */ |
| 2013 | |
| 2014 | struct i386_insn i386_tramp_chain_in_reg_insns[] = |
| 2015 | { |
| 2016 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ |
| 2017 | { 5, { 0xb8 }, { 0xfe } }, |
| 2018 | |
| 2019 | /* `jmp imm32' */ |
| 2020 | { 5, { 0xe9 }, { 0xff } }, |
| 2021 | |
| 2022 | {0} |
| 2023 | }; |
| 2024 | |
| 2025 | /* Static chain passed on stack (when regparm=3). */ |
| 2026 | |
| 2027 | struct i386_insn i386_tramp_chain_on_stack_insns[] = |
| 2028 | { |
| 2029 | /* `push imm32' */ |
| 2030 | { 5, { 0x68 }, { 0xff } }, |
| 2031 | |
| 2032 | /* `jmp imm32' */ |
| 2033 | { 5, { 0xe9 }, { 0xff } }, |
| 2034 | |
| 2035 | {0} |
| 2036 | }; |
| 2037 | |
| 2038 | /* Return whether PC points inside a stack trampoline. */ |
| 2039 | |
| 2040 | static int |
| 2041 | i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 2042 | { |
| 2043 | gdb_byte insn; |
| 2044 | const char *name; |
| 2045 | |
| 2046 | /* A stack trampoline is detected if no name is associated |
| 2047 | to the current pc and if it points inside a trampoline |
| 2048 | sequence. */ |
| 2049 | |
| 2050 | find_pc_partial_function (pc, &name, NULL, NULL); |
| 2051 | if (name) |
| 2052 | return 0; |
| 2053 | |
| 2054 | if (target_read_memory (pc, &insn, 1)) |
| 2055 | return 0; |
| 2056 | |
| 2057 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) |
| 2058 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) |
| 2059 | return 0; |
| 2060 | |
| 2061 | return 1; |
| 2062 | } |
| 2063 | |
| 2064 | static int |
| 2065 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, |
| 2066 | struct frame_info *this_frame, |
| 2067 | void **this_cache) |
| 2068 | { |
| 2069 | if (frame_relative_level (this_frame) == 0) |
| 2070 | return i386_in_stack_tramp_p (get_frame_arch (this_frame), |
| 2071 | get_frame_pc (this_frame)); |
| 2072 | else |
| 2073 | return 0; |
| 2074 | } |
| 2075 | |
| 2076 | static const struct frame_unwind i386_stack_tramp_frame_unwind = |
| 2077 | { |
| 2078 | NORMAL_FRAME, |
| 2079 | i386_epilogue_frame_unwind_stop_reason, |
| 2080 | i386_epilogue_frame_this_id, |
| 2081 | i386_epilogue_frame_prev_register, |
| 2082 | NULL, |
| 2083 | i386_stack_tramp_frame_sniffer |
| 2084 | }; |
| 2085 | \f |
| 2086 | /* Generate a bytecode expression to get the value of the saved PC. */ |
| 2087 | |
| 2088 | static void |
| 2089 | i386_gen_return_address (struct gdbarch *gdbarch, |
| 2090 | struct agent_expr *ax, struct axs_value *value, |
| 2091 | CORE_ADDR scope) |
| 2092 | { |
| 2093 | /* The following sequence assumes the traditional use of the base |
| 2094 | register. */ |
| 2095 | ax_reg (ax, I386_EBP_REGNUM); |
| 2096 | ax_const_l (ax, 4); |
| 2097 | ax_simple (ax, aop_add); |
| 2098 | value->type = register_type (gdbarch, I386_EIP_REGNUM); |
| 2099 | value->kind = axs_lvalue_memory; |
| 2100 | } |
| 2101 | \f |
| 2102 | |
| 2103 | /* Signal trampolines. */ |
| 2104 | |
| 2105 | static struct i386_frame_cache * |
| 2106 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 2107 | { |
| 2108 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 2109 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2110 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2111 | volatile struct gdb_exception ex; |
| 2112 | struct i386_frame_cache *cache; |
| 2113 | CORE_ADDR addr; |
| 2114 | gdb_byte buf[4]; |
| 2115 | |
| 2116 | if (*this_cache) |
| 2117 | return *this_cache; |
| 2118 | |
| 2119 | cache = i386_alloc_frame_cache (); |
| 2120 | |
| 2121 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
| 2122 | { |
| 2123 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
| 2124 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; |
| 2125 | |
| 2126 | addr = tdep->sigcontext_addr (this_frame); |
| 2127 | if (tdep->sc_reg_offset) |
| 2128 | { |
| 2129 | int i; |
| 2130 | |
| 2131 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
| 2132 | |
| 2133 | for (i = 0; i < tdep->sc_num_regs; i++) |
| 2134 | if (tdep->sc_reg_offset[i] != -1) |
| 2135 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
| 2136 | } |
| 2137 | else |
| 2138 | { |
| 2139 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
| 2140 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; |
| 2141 | } |
| 2142 | |
| 2143 | cache->base_p = 1; |
| 2144 | } |
| 2145 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
| 2146 | throw_exception (ex); |
| 2147 | |
| 2148 | *this_cache = cache; |
| 2149 | return cache; |
| 2150 | } |
| 2151 | |
| 2152 | static enum unwind_stop_reason |
| 2153 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, |
| 2154 | void **this_cache) |
| 2155 | { |
| 2156 | struct i386_frame_cache *cache = |
| 2157 | i386_sigtramp_frame_cache (this_frame, this_cache); |
| 2158 | |
| 2159 | if (!cache->base_p) |
| 2160 | return UNWIND_UNAVAILABLE; |
| 2161 | |
| 2162 | return UNWIND_NO_REASON; |
| 2163 | } |
| 2164 | |
| 2165 | static void |
| 2166 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 2167 | struct frame_id *this_id) |
| 2168 | { |
| 2169 | struct i386_frame_cache *cache = |
| 2170 | i386_sigtramp_frame_cache (this_frame, this_cache); |
| 2171 | |
| 2172 | if (!cache->base_p) |
| 2173 | return; |
| 2174 | |
| 2175 | /* See the end of i386_push_dummy_call. */ |
| 2176 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
| 2177 | } |
| 2178 | |
| 2179 | static struct value * |
| 2180 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, |
| 2181 | void **this_cache, int regnum) |
| 2182 | { |
| 2183 | /* Make sure we've initialized the cache. */ |
| 2184 | i386_sigtramp_frame_cache (this_frame, this_cache); |
| 2185 | |
| 2186 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
| 2187 | } |
| 2188 | |
| 2189 | static int |
| 2190 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, |
| 2191 | struct frame_info *this_frame, |
| 2192 | void **this_prologue_cache) |
| 2193 | { |
| 2194 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
| 2195 | |
| 2196 | /* We shouldn't even bother if we don't have a sigcontext_addr |
| 2197 | handler. */ |
| 2198 | if (tdep->sigcontext_addr == NULL) |
| 2199 | return 0; |
| 2200 | |
| 2201 | if (tdep->sigtramp_p != NULL) |
| 2202 | { |
| 2203 | if (tdep->sigtramp_p (this_frame)) |
| 2204 | return 1; |
| 2205 | } |
| 2206 | |
| 2207 | if (tdep->sigtramp_start != 0) |
| 2208 | { |
| 2209 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 2210 | |
| 2211 | gdb_assert (tdep->sigtramp_end != 0); |
| 2212 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) |
| 2213 | return 1; |
| 2214 | } |
| 2215 | |
| 2216 | return 0; |
| 2217 | } |
| 2218 | |
| 2219 | static const struct frame_unwind i386_sigtramp_frame_unwind = |
| 2220 | { |
| 2221 | SIGTRAMP_FRAME, |
| 2222 | i386_sigtramp_frame_unwind_stop_reason, |
| 2223 | i386_sigtramp_frame_this_id, |
| 2224 | i386_sigtramp_frame_prev_register, |
| 2225 | NULL, |
| 2226 | i386_sigtramp_frame_sniffer |
| 2227 | }; |
| 2228 | \f |
| 2229 | |
| 2230 | static CORE_ADDR |
| 2231 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 2232 | { |
| 2233 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
| 2234 | |
| 2235 | return cache->base; |
| 2236 | } |
| 2237 | |
| 2238 | static const struct frame_base i386_frame_base = |
| 2239 | { |
| 2240 | &i386_frame_unwind, |
| 2241 | i386_frame_base_address, |
| 2242 | i386_frame_base_address, |
| 2243 | i386_frame_base_address |
| 2244 | }; |
| 2245 | |
| 2246 | static struct frame_id |
| 2247 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 2248 | { |
| 2249 | CORE_ADDR fp; |
| 2250 | |
| 2251 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
| 2252 | |
| 2253 | /* See the end of i386_push_dummy_call. */ |
| 2254 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
| 2255 | } |
| 2256 | |
| 2257 | /* _Decimal128 function return values need 16-byte alignment on the |
| 2258 | stack. */ |
| 2259 | |
| 2260 | static CORE_ADDR |
| 2261 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) |
| 2262 | { |
| 2263 | return sp & -(CORE_ADDR)16; |
| 2264 | } |
| 2265 | \f |
| 2266 | |
| 2267 | /* Figure out where the longjmp will land. Slurp the args out of the |
| 2268 | stack. We expect the first arg to be a pointer to the jmp_buf |
| 2269 | structure from which we extract the address that we will land at. |
| 2270 | This address is copied into PC. This routine returns non-zero on |
| 2271 | success. */ |
| 2272 | |
| 2273 | static int |
| 2274 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
| 2275 | { |
| 2276 | gdb_byte buf[4]; |
| 2277 | CORE_ADDR sp, jb_addr; |
| 2278 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2279 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2280 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
| 2281 | |
| 2282 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
| 2283 | longjmp will land. */ |
| 2284 | if (jb_pc_offset == -1) |
| 2285 | return 0; |
| 2286 | |
| 2287 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
| 2288 | sp = extract_unsigned_integer (buf, 4, byte_order); |
| 2289 | if (target_read_memory (sp + 4, buf, 4)) |
| 2290 | return 0; |
| 2291 | |
| 2292 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
| 2293 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
| 2294 | return 0; |
| 2295 | |
| 2296 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
| 2297 | return 1; |
| 2298 | } |
| 2299 | \f |
| 2300 | |
| 2301 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
| 2302 | function argument. 16-byte vectors, _Decimal128 and structures or |
| 2303 | unions containing such types must be 16-byte-aligned; other |
| 2304 | arguments are 4-byte-aligned. */ |
| 2305 | |
| 2306 | static int |
| 2307 | i386_16_byte_align_p (struct type *type) |
| 2308 | { |
| 2309 | type = check_typedef (type); |
| 2310 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT |
| 2311 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) |
| 2312 | && TYPE_LENGTH (type) == 16) |
| 2313 | return 1; |
| 2314 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
| 2315 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); |
| 2316 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
| 2317 | || TYPE_CODE (type) == TYPE_CODE_UNION) |
| 2318 | { |
| 2319 | int i; |
| 2320 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 2321 | { |
| 2322 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) |
| 2323 | return 1; |
| 2324 | } |
| 2325 | } |
| 2326 | return 0; |
| 2327 | } |
| 2328 | |
| 2329 | static CORE_ADDR |
| 2330 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 2331 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
| 2332 | struct value **args, CORE_ADDR sp, int struct_return, |
| 2333 | CORE_ADDR struct_addr) |
| 2334 | { |
| 2335 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2336 | gdb_byte buf[4]; |
| 2337 | int i; |
| 2338 | int write_pass; |
| 2339 | int args_space = 0; |
| 2340 | |
| 2341 | /* Determine the total space required for arguments and struct |
| 2342 | return address in a first pass (allowing for 16-byte-aligned |
| 2343 | arguments), then push arguments in a second pass. */ |
| 2344 | |
| 2345 | for (write_pass = 0; write_pass < 2; write_pass++) |
| 2346 | { |
| 2347 | int args_space_used = 0; |
| 2348 | int have_16_byte_aligned_arg = 0; |
| 2349 | |
| 2350 | if (struct_return) |
| 2351 | { |
| 2352 | if (write_pass) |
| 2353 | { |
| 2354 | /* Push value address. */ |
| 2355 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
| 2356 | write_memory (sp, buf, 4); |
| 2357 | args_space_used += 4; |
| 2358 | } |
| 2359 | else |
| 2360 | args_space += 4; |
| 2361 | } |
| 2362 | |
| 2363 | for (i = 0; i < nargs; i++) |
| 2364 | { |
| 2365 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); |
| 2366 | |
| 2367 | if (write_pass) |
| 2368 | { |
| 2369 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) |
| 2370 | args_space_used = align_up (args_space_used, 16); |
| 2371 | |
| 2372 | write_memory (sp + args_space_used, |
| 2373 | value_contents_all (args[i]), len); |
| 2374 | /* The System V ABI says that: |
| 2375 | |
| 2376 | "An argument's size is increased, if necessary, to make it a |
| 2377 | multiple of [32-bit] words. This may require tail padding, |
| 2378 | depending on the size of the argument." |
| 2379 | |
| 2380 | This makes sure the stack stays word-aligned. */ |
| 2381 | args_space_used += align_up (len, 4); |
| 2382 | } |
| 2383 | else |
| 2384 | { |
| 2385 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) |
| 2386 | { |
| 2387 | args_space = align_up (args_space, 16); |
| 2388 | have_16_byte_aligned_arg = 1; |
| 2389 | } |
| 2390 | args_space += align_up (len, 4); |
| 2391 | } |
| 2392 | } |
| 2393 | |
| 2394 | if (!write_pass) |
| 2395 | { |
| 2396 | if (have_16_byte_aligned_arg) |
| 2397 | args_space = align_up (args_space, 16); |
| 2398 | sp -= args_space; |
| 2399 | } |
| 2400 | } |
| 2401 | |
| 2402 | /* Store return address. */ |
| 2403 | sp -= 4; |
| 2404 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
| 2405 | write_memory (sp, buf, 4); |
| 2406 | |
| 2407 | /* Finally, update the stack pointer... */ |
| 2408 | store_unsigned_integer (buf, 4, byte_order, sp); |
| 2409 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
| 2410 | |
| 2411 | /* ...and fake a frame pointer. */ |
| 2412 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); |
| 2413 | |
| 2414 | /* MarkK wrote: This "+ 8" is all over the place: |
| 2415 | (i386_frame_this_id, i386_sigtramp_frame_this_id, |
| 2416 | i386_dummy_id). It's there, since all frame unwinders for |
| 2417 | a given target have to agree (within a certain margin) on the |
| 2418 | definition of the stack address of a frame. Otherwise frame id |
| 2419 | comparison might not work correctly. Since DWARF2/GCC uses the |
| 2420 | stack address *before* the function call as a frame's CFA. On |
| 2421 | the i386, when %ebp is used as a frame pointer, the offset |
| 2422 | between the contents %ebp and the CFA as defined by GCC. */ |
| 2423 | return sp + 8; |
| 2424 | } |
| 2425 | |
| 2426 | /* These registers are used for returning integers (and on some |
| 2427 | targets also for returning `struct' and `union' values when their |
| 2428 | size and alignment match an integer type). */ |
| 2429 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
| 2430 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ |
| 2431 | |
| 2432 | /* Read, for architecture GDBARCH, a function return value of TYPE |
| 2433 | from REGCACHE, and copy that into VALBUF. */ |
| 2434 | |
| 2435 | static void |
| 2436 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
| 2437 | struct regcache *regcache, gdb_byte *valbuf) |
| 2438 | { |
| 2439 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2440 | int len = TYPE_LENGTH (type); |
| 2441 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
| 2442 | |
| 2443 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 2444 | { |
| 2445 | if (tdep->st0_regnum < 0) |
| 2446 | { |
| 2447 | warning (_("Cannot find floating-point return value.")); |
| 2448 | memset (valbuf, 0, len); |
| 2449 | return; |
| 2450 | } |
| 2451 | |
| 2452 | /* Floating-point return values can be found in %st(0). Convert |
| 2453 | its contents to the desired type. This is probably not |
| 2454 | exactly how it would happen on the target itself, but it is |
| 2455 | the best we can do. */ |
| 2456 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
| 2457 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
| 2458 | } |
| 2459 | else |
| 2460 | { |
| 2461 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
| 2462 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); |
| 2463 | |
| 2464 | if (len <= low_size) |
| 2465 | { |
| 2466 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
| 2467 | memcpy (valbuf, buf, len); |
| 2468 | } |
| 2469 | else if (len <= (low_size + high_size)) |
| 2470 | { |
| 2471 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
| 2472 | memcpy (valbuf, buf, low_size); |
| 2473 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
| 2474 | memcpy (valbuf + low_size, buf, len - low_size); |
| 2475 | } |
| 2476 | else |
| 2477 | internal_error (__FILE__, __LINE__, |
| 2478 | _("Cannot extract return value of %d bytes long."), |
| 2479 | len); |
| 2480 | } |
| 2481 | } |
| 2482 | |
| 2483 | /* Write, for architecture GDBARCH, a function return value of TYPE |
| 2484 | from VALBUF into REGCACHE. */ |
| 2485 | |
| 2486 | static void |
| 2487 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
| 2488 | struct regcache *regcache, const gdb_byte *valbuf) |
| 2489 | { |
| 2490 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2491 | int len = TYPE_LENGTH (type); |
| 2492 | |
| 2493 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 2494 | { |
| 2495 | ULONGEST fstat; |
| 2496 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
| 2497 | |
| 2498 | if (tdep->st0_regnum < 0) |
| 2499 | { |
| 2500 | warning (_("Cannot set floating-point return value.")); |
| 2501 | return; |
| 2502 | } |
| 2503 | |
| 2504 | /* Returning floating-point values is a bit tricky. Apart from |
| 2505 | storing the return value in %st(0), we have to simulate the |
| 2506 | state of the FPU at function return point. */ |
| 2507 | |
| 2508 | /* Convert the value found in VALBUF to the extended |
| 2509 | floating-point format used by the FPU. This is probably |
| 2510 | not exactly how it would happen on the target itself, but |
| 2511 | it is the best we can do. */ |
| 2512 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
| 2513 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
| 2514 | |
| 2515 | /* Set the top of the floating-point register stack to 7. The |
| 2516 | actual value doesn't really matter, but 7 is what a normal |
| 2517 | function return would end up with if the program started out |
| 2518 | with a freshly initialized FPU. */ |
| 2519 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
| 2520 | fstat |= (7 << 11); |
| 2521 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
| 2522 | |
| 2523 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
| 2524 | the floating-point register stack to 7, the appropriate value |
| 2525 | for the tag word is 0x3fff. */ |
| 2526 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
| 2527 | } |
| 2528 | else |
| 2529 | { |
| 2530 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
| 2531 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); |
| 2532 | |
| 2533 | if (len <= low_size) |
| 2534 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
| 2535 | else if (len <= (low_size + high_size)) |
| 2536 | { |
| 2537 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
| 2538 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, |
| 2539 | len - low_size, valbuf + low_size); |
| 2540 | } |
| 2541 | else |
| 2542 | internal_error (__FILE__, __LINE__, |
| 2543 | _("Cannot store return value of %d bytes long."), len); |
| 2544 | } |
| 2545 | } |
| 2546 | \f |
| 2547 | |
| 2548 | /* This is the variable that is set with "set struct-convention", and |
| 2549 | its legitimate values. */ |
| 2550 | static const char default_struct_convention[] = "default"; |
| 2551 | static const char pcc_struct_convention[] = "pcc"; |
| 2552 | static const char reg_struct_convention[] = "reg"; |
| 2553 | static const char *const valid_conventions[] = |
| 2554 | { |
| 2555 | default_struct_convention, |
| 2556 | pcc_struct_convention, |
| 2557 | reg_struct_convention, |
| 2558 | NULL |
| 2559 | }; |
| 2560 | static const char *struct_convention = default_struct_convention; |
| 2561 | |
| 2562 | /* Return non-zero if TYPE, which is assumed to be a structure, |
| 2563 | a union type, or an array type, should be returned in registers |
| 2564 | for architecture GDBARCH. */ |
| 2565 | |
| 2566 | static int |
| 2567 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
| 2568 | { |
| 2569 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2570 | enum type_code code = TYPE_CODE (type); |
| 2571 | int len = TYPE_LENGTH (type); |
| 2572 | |
| 2573 | gdb_assert (code == TYPE_CODE_STRUCT |
| 2574 | || code == TYPE_CODE_UNION |
| 2575 | || code == TYPE_CODE_ARRAY); |
| 2576 | |
| 2577 | if (struct_convention == pcc_struct_convention |
| 2578 | || (struct_convention == default_struct_convention |
| 2579 | && tdep->struct_return == pcc_struct_return)) |
| 2580 | return 0; |
| 2581 | |
| 2582 | /* Structures consisting of a single `float', `double' or 'long |
| 2583 | double' member are returned in %st(0). */ |
| 2584 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
| 2585 | { |
| 2586 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); |
| 2587 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
| 2588 | return (len == 4 || len == 8 || len == 12); |
| 2589 | } |
| 2590 | |
| 2591 | return (len == 1 || len == 2 || len == 4 || len == 8); |
| 2592 | } |
| 2593 | |
| 2594 | /* Determine, for architecture GDBARCH, how a return value of TYPE |
| 2595 | should be returned. If it is supposed to be returned in registers, |
| 2596 | and READBUF is non-zero, read the appropriate value from REGCACHE, |
| 2597 | and copy it into READBUF. If WRITEBUF is non-zero, write the value |
| 2598 | from WRITEBUF into REGCACHE. */ |
| 2599 | |
| 2600 | static enum return_value_convention |
| 2601 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
| 2602 | struct type *type, struct regcache *regcache, |
| 2603 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 2604 | { |
| 2605 | enum type_code code = TYPE_CODE (type); |
| 2606 | |
| 2607 | if (((code == TYPE_CODE_STRUCT |
| 2608 | || code == TYPE_CODE_UNION |
| 2609 | || code == TYPE_CODE_ARRAY) |
| 2610 | && !i386_reg_struct_return_p (gdbarch, type)) |
| 2611 | /* 128-bit decimal float uses the struct return convention. */ |
| 2612 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) |
| 2613 | { |
| 2614 | /* The System V ABI says that: |
| 2615 | |
| 2616 | "A function that returns a structure or union also sets %eax |
| 2617 | to the value of the original address of the caller's area |
| 2618 | before it returns. Thus when the caller receives control |
| 2619 | again, the address of the returned object resides in register |
| 2620 | %eax and can be used to access the object." |
| 2621 | |
| 2622 | So the ABI guarantees that we can always find the return |
| 2623 | value just after the function has returned. */ |
| 2624 | |
| 2625 | /* Note that the ABI doesn't mention functions returning arrays, |
| 2626 | which is something possible in certain languages such as Ada. |
| 2627 | In this case, the value is returned as if it was wrapped in |
| 2628 | a record, so the convention applied to records also applies |
| 2629 | to arrays. */ |
| 2630 | |
| 2631 | if (readbuf) |
| 2632 | { |
| 2633 | ULONGEST addr; |
| 2634 | |
| 2635 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); |
| 2636 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
| 2637 | } |
| 2638 | |
| 2639 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; |
| 2640 | } |
| 2641 | |
| 2642 | /* This special case is for structures consisting of a single |
| 2643 | `float', `double' or 'long double' member. These structures are |
| 2644 | returned in %st(0). For these structures, we call ourselves |
| 2645 | recursively, changing TYPE into the type of the first member of |
| 2646 | the structure. Since that should work for all structures that |
| 2647 | have only one member, we don't bother to check the member's type |
| 2648 | here. */ |
| 2649 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
| 2650 | { |
| 2651 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); |
| 2652 | return i386_return_value (gdbarch, func_type, type, regcache, |
| 2653 | readbuf, writebuf); |
| 2654 | } |
| 2655 | |
| 2656 | if (readbuf) |
| 2657 | i386_extract_return_value (gdbarch, type, regcache, readbuf); |
| 2658 | if (writebuf) |
| 2659 | i386_store_return_value (gdbarch, type, regcache, writebuf); |
| 2660 | |
| 2661 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 2662 | } |
| 2663 | \f |
| 2664 | |
| 2665 | struct type * |
| 2666 | i387_ext_type (struct gdbarch *gdbarch) |
| 2667 | { |
| 2668 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2669 | |
| 2670 | if (!tdep->i387_ext_type) |
| 2671 | { |
| 2672 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); |
| 2673 | gdb_assert (tdep->i387_ext_type != NULL); |
| 2674 | } |
| 2675 | |
| 2676 | return tdep->i387_ext_type; |
| 2677 | } |
| 2678 | |
| 2679 | /* Construct vector type for pseudo YMM registers. We can't use |
| 2680 | tdesc_find_type since YMM isn't described in target description. */ |
| 2681 | |
| 2682 | static struct type * |
| 2683 | i386_ymm_type (struct gdbarch *gdbarch) |
| 2684 | { |
| 2685 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2686 | |
| 2687 | if (!tdep->i386_ymm_type) |
| 2688 | { |
| 2689 | const struct builtin_type *bt = builtin_type (gdbarch); |
| 2690 | |
| 2691 | /* The type we're building is this: */ |
| 2692 | #if 0 |
| 2693 | union __gdb_builtin_type_vec256i |
| 2694 | { |
| 2695 | int128_t uint128[2]; |
| 2696 | int64_t v2_int64[4]; |
| 2697 | int32_t v4_int32[8]; |
| 2698 | int16_t v8_int16[16]; |
| 2699 | int8_t v16_int8[32]; |
| 2700 | double v2_double[4]; |
| 2701 | float v4_float[8]; |
| 2702 | }; |
| 2703 | #endif |
| 2704 | |
| 2705 | struct type *t; |
| 2706 | |
| 2707 | t = arch_composite_type (gdbarch, |
| 2708 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); |
| 2709 | append_composite_type_field (t, "v8_float", |
| 2710 | init_vector_type (bt->builtin_float, 8)); |
| 2711 | append_composite_type_field (t, "v4_double", |
| 2712 | init_vector_type (bt->builtin_double, 4)); |
| 2713 | append_composite_type_field (t, "v32_int8", |
| 2714 | init_vector_type (bt->builtin_int8, 32)); |
| 2715 | append_composite_type_field (t, "v16_int16", |
| 2716 | init_vector_type (bt->builtin_int16, 16)); |
| 2717 | append_composite_type_field (t, "v8_int32", |
| 2718 | init_vector_type (bt->builtin_int32, 8)); |
| 2719 | append_composite_type_field (t, "v4_int64", |
| 2720 | init_vector_type (bt->builtin_int64, 4)); |
| 2721 | append_composite_type_field (t, "v2_int128", |
| 2722 | init_vector_type (bt->builtin_int128, 2)); |
| 2723 | |
| 2724 | TYPE_VECTOR (t) = 1; |
| 2725 | TYPE_NAME (t) = "builtin_type_vec256i"; |
| 2726 | tdep->i386_ymm_type = t; |
| 2727 | } |
| 2728 | |
| 2729 | return tdep->i386_ymm_type; |
| 2730 | } |
| 2731 | |
| 2732 | /* Construct vector type for MMX registers. */ |
| 2733 | static struct type * |
| 2734 | i386_mmx_type (struct gdbarch *gdbarch) |
| 2735 | { |
| 2736 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2737 | |
| 2738 | if (!tdep->i386_mmx_type) |
| 2739 | { |
| 2740 | const struct builtin_type *bt = builtin_type (gdbarch); |
| 2741 | |
| 2742 | /* The type we're building is this: */ |
| 2743 | #if 0 |
| 2744 | union __gdb_builtin_type_vec64i |
| 2745 | { |
| 2746 | int64_t uint64; |
| 2747 | int32_t v2_int32[2]; |
| 2748 | int16_t v4_int16[4]; |
| 2749 | int8_t v8_int8[8]; |
| 2750 | }; |
| 2751 | #endif |
| 2752 | |
| 2753 | struct type *t; |
| 2754 | |
| 2755 | t = arch_composite_type (gdbarch, |
| 2756 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); |
| 2757 | |
| 2758 | append_composite_type_field (t, "uint64", bt->builtin_int64); |
| 2759 | append_composite_type_field (t, "v2_int32", |
| 2760 | init_vector_type (bt->builtin_int32, 2)); |
| 2761 | append_composite_type_field (t, "v4_int16", |
| 2762 | init_vector_type (bt->builtin_int16, 4)); |
| 2763 | append_composite_type_field (t, "v8_int8", |
| 2764 | init_vector_type (bt->builtin_int8, 8)); |
| 2765 | |
| 2766 | TYPE_VECTOR (t) = 1; |
| 2767 | TYPE_NAME (t) = "builtin_type_vec64i"; |
| 2768 | tdep->i386_mmx_type = t; |
| 2769 | } |
| 2770 | |
| 2771 | return tdep->i386_mmx_type; |
| 2772 | } |
| 2773 | |
| 2774 | /* Return the GDB type object for the "standard" data type of data in |
| 2775 | register REGNUM. */ |
| 2776 | |
| 2777 | static struct type * |
| 2778 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
| 2779 | { |
| 2780 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
| 2781 | return i386_mmx_type (gdbarch); |
| 2782 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
| 2783 | return i386_ymm_type (gdbarch); |
| 2784 | else |
| 2785 | { |
| 2786 | const struct builtin_type *bt = builtin_type (gdbarch); |
| 2787 | if (i386_byte_regnum_p (gdbarch, regnum)) |
| 2788 | return bt->builtin_int8; |
| 2789 | else if (i386_word_regnum_p (gdbarch, regnum)) |
| 2790 | return bt->builtin_int16; |
| 2791 | else if (i386_dword_regnum_p (gdbarch, regnum)) |
| 2792 | return bt->builtin_int32; |
| 2793 | } |
| 2794 | |
| 2795 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 2796 | } |
| 2797 | |
| 2798 | /* Map a cooked register onto a raw register or memory. For the i386, |
| 2799 | the MMX registers need to be mapped onto floating point registers. */ |
| 2800 | |
| 2801 | static int |
| 2802 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
| 2803 | { |
| 2804 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
| 2805 | int mmxreg, fpreg; |
| 2806 | ULONGEST fstat; |
| 2807 | int tos; |
| 2808 | |
| 2809 | mmxreg = regnum - tdep->mm0_regnum; |
| 2810 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
| 2811 | tos = (fstat >> 11) & 0x7; |
| 2812 | fpreg = (mmxreg + tos) % 8; |
| 2813 | |
| 2814 | return (I387_ST0_REGNUM (tdep) + fpreg); |
| 2815 | } |
| 2816 | |
| 2817 | /* A helper function for us by i386_pseudo_register_read_value and |
| 2818 | amd64_pseudo_register_read_value. It does all the work but reads |
| 2819 | the data into an already-allocated value. */ |
| 2820 | |
| 2821 | void |
| 2822 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, |
| 2823 | struct regcache *regcache, |
| 2824 | int regnum, |
| 2825 | struct value *result_value) |
| 2826 | { |
| 2827 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
| 2828 | enum register_status status; |
| 2829 | gdb_byte *buf = value_contents_raw (result_value); |
| 2830 | |
| 2831 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
| 2832 | { |
| 2833 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
| 2834 | |
| 2835 | /* Extract (always little endian). */ |
| 2836 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
| 2837 | if (status != REG_VALID) |
| 2838 | mark_value_bytes_unavailable (result_value, 0, |
| 2839 | TYPE_LENGTH (value_type (result_value))); |
| 2840 | else |
| 2841 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); |
| 2842 | } |
| 2843 | else |
| 2844 | { |
| 2845 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2846 | |
| 2847 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
| 2848 | { |
| 2849 | regnum -= tdep->ymm0_regnum; |
| 2850 | |
| 2851 | /* Extract (always little endian). Read lower 128bits. */ |
| 2852 | status = regcache_raw_read (regcache, |
| 2853 | I387_XMM0_REGNUM (tdep) + regnum, |
| 2854 | raw_buf); |
| 2855 | if (status != REG_VALID) |
| 2856 | mark_value_bytes_unavailable (result_value, 0, 16); |
| 2857 | else |
| 2858 | memcpy (buf, raw_buf, 16); |
| 2859 | /* Read upper 128bits. */ |
| 2860 | status = regcache_raw_read (regcache, |
| 2861 | tdep->ymm0h_regnum + regnum, |
| 2862 | raw_buf); |
| 2863 | if (status != REG_VALID) |
| 2864 | mark_value_bytes_unavailable (result_value, 16, 32); |
| 2865 | else |
| 2866 | memcpy (buf + 16, raw_buf, 16); |
| 2867 | } |
| 2868 | else if (i386_word_regnum_p (gdbarch, regnum)) |
| 2869 | { |
| 2870 | int gpnum = regnum - tdep->ax_regnum; |
| 2871 | |
| 2872 | /* Extract (always little endian). */ |
| 2873 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
| 2874 | if (status != REG_VALID) |
| 2875 | mark_value_bytes_unavailable (result_value, 0, |
| 2876 | TYPE_LENGTH (value_type (result_value))); |
| 2877 | else |
| 2878 | memcpy (buf, raw_buf, 2); |
| 2879 | } |
| 2880 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
| 2881 | { |
| 2882 | /* Check byte pseudo registers last since this function will |
| 2883 | be called from amd64_pseudo_register_read, which handles |
| 2884 | byte pseudo registers differently. */ |
| 2885 | int gpnum = regnum - tdep->al_regnum; |
| 2886 | |
| 2887 | /* Extract (always little endian). We read both lower and |
| 2888 | upper registers. */ |
| 2889 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
| 2890 | if (status != REG_VALID) |
| 2891 | mark_value_bytes_unavailable (result_value, 0, |
| 2892 | TYPE_LENGTH (value_type (result_value))); |
| 2893 | else if (gpnum >= 4) |
| 2894 | memcpy (buf, raw_buf + 1, 1); |
| 2895 | else |
| 2896 | memcpy (buf, raw_buf, 1); |
| 2897 | } |
| 2898 | else |
| 2899 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 2900 | } |
| 2901 | } |
| 2902 | |
| 2903 | static struct value * |
| 2904 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, |
| 2905 | struct regcache *regcache, |
| 2906 | int regnum) |
| 2907 | { |
| 2908 | struct value *result; |
| 2909 | |
| 2910 | result = allocate_value (register_type (gdbarch, regnum)); |
| 2911 | VALUE_LVAL (result) = lval_register; |
| 2912 | VALUE_REGNUM (result) = regnum; |
| 2913 | |
| 2914 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); |
| 2915 | |
| 2916 | return result; |
| 2917 | } |
| 2918 | |
| 2919 | void |
| 2920 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
| 2921 | int regnum, const gdb_byte *buf) |
| 2922 | { |
| 2923 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
| 2924 | |
| 2925 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
| 2926 | { |
| 2927 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
| 2928 | |
| 2929 | /* Read ... */ |
| 2930 | regcache_raw_read (regcache, fpnum, raw_buf); |
| 2931 | /* ... Modify ... (always little endian). */ |
| 2932 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
| 2933 | /* ... Write. */ |
| 2934 | regcache_raw_write (regcache, fpnum, raw_buf); |
| 2935 | } |
| 2936 | else |
| 2937 | { |
| 2938 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2939 | |
| 2940 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
| 2941 | { |
| 2942 | regnum -= tdep->ymm0_regnum; |
| 2943 | |
| 2944 | /* ... Write lower 128bits. */ |
| 2945 | regcache_raw_write (regcache, |
| 2946 | I387_XMM0_REGNUM (tdep) + regnum, |
| 2947 | buf); |
| 2948 | /* ... Write upper 128bits. */ |
| 2949 | regcache_raw_write (regcache, |
| 2950 | tdep->ymm0h_regnum + regnum, |
| 2951 | buf + 16); |
| 2952 | } |
| 2953 | else if (i386_word_regnum_p (gdbarch, regnum)) |
| 2954 | { |
| 2955 | int gpnum = regnum - tdep->ax_regnum; |
| 2956 | |
| 2957 | /* Read ... */ |
| 2958 | regcache_raw_read (regcache, gpnum, raw_buf); |
| 2959 | /* ... Modify ... (always little endian). */ |
| 2960 | memcpy (raw_buf, buf, 2); |
| 2961 | /* ... Write. */ |
| 2962 | regcache_raw_write (regcache, gpnum, raw_buf); |
| 2963 | } |
| 2964 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
| 2965 | { |
| 2966 | /* Check byte pseudo registers last since this function will |
| 2967 | be called from amd64_pseudo_register_read, which handles |
| 2968 | byte pseudo registers differently. */ |
| 2969 | int gpnum = regnum - tdep->al_regnum; |
| 2970 | |
| 2971 | /* Read ... We read both lower and upper registers. */ |
| 2972 | regcache_raw_read (regcache, gpnum % 4, raw_buf); |
| 2973 | /* ... Modify ... (always little endian). */ |
| 2974 | if (gpnum >= 4) |
| 2975 | memcpy (raw_buf + 1, buf, 1); |
| 2976 | else |
| 2977 | memcpy (raw_buf, buf, 1); |
| 2978 | /* ... Write. */ |
| 2979 | regcache_raw_write (regcache, gpnum % 4, raw_buf); |
| 2980 | } |
| 2981 | else |
| 2982 | internal_error (__FILE__, __LINE__, _("invalid regnum")); |
| 2983 | } |
| 2984 | } |
| 2985 | \f |
| 2986 | |
| 2987 | /* Return the register number of the register allocated by GCC after |
| 2988 | REGNUM, or -1 if there is no such register. */ |
| 2989 | |
| 2990 | static int |
| 2991 | i386_next_regnum (int regnum) |
| 2992 | { |
| 2993 | /* GCC allocates the registers in the order: |
| 2994 | |
| 2995 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... |
| 2996 | |
| 2997 | Since storing a variable in %esp doesn't make any sense we return |
| 2998 | -1 for %ebp and for %esp itself. */ |
| 2999 | static int next_regnum[] = |
| 3000 | { |
| 3001 | I386_EDX_REGNUM, /* Slot for %eax. */ |
| 3002 | I386_EBX_REGNUM, /* Slot for %ecx. */ |
| 3003 | I386_ECX_REGNUM, /* Slot for %edx. */ |
| 3004 | I386_ESI_REGNUM, /* Slot for %ebx. */ |
| 3005 | -1, -1, /* Slots for %esp and %ebp. */ |
| 3006 | I386_EDI_REGNUM, /* Slot for %esi. */ |
| 3007 | I386_EBP_REGNUM /* Slot for %edi. */ |
| 3008 | }; |
| 3009 | |
| 3010 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
| 3011 | return next_regnum[regnum]; |
| 3012 | |
| 3013 | return -1; |
| 3014 | } |
| 3015 | |
| 3016 | /* Return nonzero if a value of type TYPE stored in register REGNUM |
| 3017 | needs any special handling. */ |
| 3018 | |
| 3019 | static int |
| 3020 | i386_convert_register_p (struct gdbarch *gdbarch, |
| 3021 | int regnum, struct type *type) |
| 3022 | { |
| 3023 | int len = TYPE_LENGTH (type); |
| 3024 | |
| 3025 | /* Values may be spread across multiple registers. Most debugging |
| 3026 | formats aren't expressive enough to specify the locations, so |
| 3027 | some heuristics is involved. Right now we only handle types that |
| 3028 | have a length that is a multiple of the word size, since GCC |
| 3029 | doesn't seem to put any other types into registers. */ |
| 3030 | if (len > 4 && len % 4 == 0) |
| 3031 | { |
| 3032 | int last_regnum = regnum; |
| 3033 | |
| 3034 | while (len > 4) |
| 3035 | { |
| 3036 | last_regnum = i386_next_regnum (last_regnum); |
| 3037 | len -= 4; |
| 3038 | } |
| 3039 | |
| 3040 | if (last_regnum != -1) |
| 3041 | return 1; |
| 3042 | } |
| 3043 | |
| 3044 | return i387_convert_register_p (gdbarch, regnum, type); |
| 3045 | } |
| 3046 | |
| 3047 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
| 3048 | return its contents in TO. */ |
| 3049 | |
| 3050 | static int |
| 3051 | i386_register_to_value (struct frame_info *frame, int regnum, |
| 3052 | struct type *type, gdb_byte *to, |
| 3053 | int *optimizedp, int *unavailablep) |
| 3054 | { |
| 3055 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 3056 | int len = TYPE_LENGTH (type); |
| 3057 | |
| 3058 | if (i386_fp_regnum_p (gdbarch, regnum)) |
| 3059 | return i387_register_to_value (frame, regnum, type, to, |
| 3060 | optimizedp, unavailablep); |
| 3061 | |
| 3062 | /* Read a value spread across multiple registers. */ |
| 3063 | |
| 3064 | gdb_assert (len > 4 && len % 4 == 0); |
| 3065 | |
| 3066 | while (len > 0) |
| 3067 | { |
| 3068 | gdb_assert (regnum != -1); |
| 3069 | gdb_assert (register_size (gdbarch, regnum) == 4); |
| 3070 | |
| 3071 | if (!get_frame_register_bytes (frame, regnum, 0, |
| 3072 | register_size (gdbarch, regnum), |
| 3073 | to, optimizedp, unavailablep)) |
| 3074 | return 0; |
| 3075 | |
| 3076 | regnum = i386_next_regnum (regnum); |
| 3077 | len -= 4; |
| 3078 | to += 4; |
| 3079 | } |
| 3080 | |
| 3081 | *optimizedp = *unavailablep = 0; |
| 3082 | return 1; |
| 3083 | } |
| 3084 | |
| 3085 | /* Write the contents FROM of a value of type TYPE into register |
| 3086 | REGNUM in frame FRAME. */ |
| 3087 | |
| 3088 | static void |
| 3089 | i386_value_to_register (struct frame_info *frame, int regnum, |
| 3090 | struct type *type, const gdb_byte *from) |
| 3091 | { |
| 3092 | int len = TYPE_LENGTH (type); |
| 3093 | |
| 3094 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
| 3095 | { |
| 3096 | i387_value_to_register (frame, regnum, type, from); |
| 3097 | return; |
| 3098 | } |
| 3099 | |
| 3100 | /* Write a value spread across multiple registers. */ |
| 3101 | |
| 3102 | gdb_assert (len > 4 && len % 4 == 0); |
| 3103 | |
| 3104 | while (len > 0) |
| 3105 | { |
| 3106 | gdb_assert (regnum != -1); |
| 3107 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
| 3108 | |
| 3109 | put_frame_register (frame, regnum, from); |
| 3110 | regnum = i386_next_regnum (regnum); |
| 3111 | len -= 4; |
| 3112 | from += 4; |
| 3113 | } |
| 3114 | } |
| 3115 | \f |
| 3116 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
| 3117 | in the general-purpose register set REGSET to register cache |
| 3118 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ |
| 3119 | |
| 3120 | void |
| 3121 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
| 3122 | int regnum, const void *gregs, size_t len) |
| 3123 | { |
| 3124 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
| 3125 | const gdb_byte *regs = gregs; |
| 3126 | int i; |
| 3127 | |
| 3128 | gdb_assert (len == tdep->sizeof_gregset); |
| 3129 | |
| 3130 | for (i = 0; i < tdep->gregset_num_regs; i++) |
| 3131 | { |
| 3132 | if ((regnum == i || regnum == -1) |
| 3133 | && tdep->gregset_reg_offset[i] != -1) |
| 3134 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); |
| 3135 | } |
| 3136 | } |
| 3137 | |
| 3138 | /* Collect register REGNUM from the register cache REGCACHE and store |
| 3139 | it in the buffer specified by GREGS and LEN as described by the |
| 3140 | general-purpose register set REGSET. If REGNUM is -1, do this for |
| 3141 | all registers in REGSET. */ |
| 3142 | |
| 3143 | void |
| 3144 | i386_collect_gregset (const struct regset *regset, |
| 3145 | const struct regcache *regcache, |
| 3146 | int regnum, void *gregs, size_t len) |
| 3147 | { |
| 3148 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
| 3149 | gdb_byte *regs = gregs; |
| 3150 | int i; |
| 3151 | |
| 3152 | gdb_assert (len == tdep->sizeof_gregset); |
| 3153 | |
| 3154 | for (i = 0; i < tdep->gregset_num_regs; i++) |
| 3155 | { |
| 3156 | if ((regnum == i || regnum == -1) |
| 3157 | && tdep->gregset_reg_offset[i] != -1) |
| 3158 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); |
| 3159 | } |
| 3160 | } |
| 3161 | |
| 3162 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN |
| 3163 | in the floating-point register set REGSET to register cache |
| 3164 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ |
| 3165 | |
| 3166 | static void |
| 3167 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, |
| 3168 | int regnum, const void *fpregs, size_t len) |
| 3169 | { |
| 3170 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
| 3171 | |
| 3172 | if (len == I387_SIZEOF_FXSAVE) |
| 3173 | { |
| 3174 | i387_supply_fxsave (regcache, regnum, fpregs); |
| 3175 | return; |
| 3176 | } |
| 3177 | |
| 3178 | gdb_assert (len == tdep->sizeof_fpregset); |
| 3179 | i387_supply_fsave (regcache, regnum, fpregs); |
| 3180 | } |
| 3181 | |
| 3182 | /* Collect register REGNUM from the register cache REGCACHE and store |
| 3183 | it in the buffer specified by FPREGS and LEN as described by the |
| 3184 | floating-point register set REGSET. If REGNUM is -1, do this for |
| 3185 | all registers in REGSET. */ |
| 3186 | |
| 3187 | static void |
| 3188 | i386_collect_fpregset (const struct regset *regset, |
| 3189 | const struct regcache *regcache, |
| 3190 | int regnum, void *fpregs, size_t len) |
| 3191 | { |
| 3192 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
| 3193 | |
| 3194 | if (len == I387_SIZEOF_FXSAVE) |
| 3195 | { |
| 3196 | i387_collect_fxsave (regcache, regnum, fpregs); |
| 3197 | return; |
| 3198 | } |
| 3199 | |
| 3200 | gdb_assert (len == tdep->sizeof_fpregset); |
| 3201 | i387_collect_fsave (regcache, regnum, fpregs); |
| 3202 | } |
| 3203 | |
| 3204 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
| 3205 | |
| 3206 | static void |
| 3207 | i386_supply_xstateregset (const struct regset *regset, |
| 3208 | struct regcache *regcache, int regnum, |
| 3209 | const void *xstateregs, size_t len) |
| 3210 | { |
| 3211 | i387_supply_xsave (regcache, regnum, xstateregs); |
| 3212 | } |
| 3213 | |
| 3214 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ |
| 3215 | |
| 3216 | static void |
| 3217 | i386_collect_xstateregset (const struct regset *regset, |
| 3218 | const struct regcache *regcache, |
| 3219 | int regnum, void *xstateregs, size_t len) |
| 3220 | { |
| 3221 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
| 3222 | } |
| 3223 | |
| 3224 | /* Return the appropriate register set for the core section identified |
| 3225 | by SECT_NAME and SECT_SIZE. */ |
| 3226 | |
| 3227 | const struct regset * |
| 3228 | i386_regset_from_core_section (struct gdbarch *gdbarch, |
| 3229 | const char *sect_name, size_t sect_size) |
| 3230 | { |
| 3231 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3232 | |
| 3233 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) |
| 3234 | { |
| 3235 | if (tdep->gregset == NULL) |
| 3236 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
| 3237 | i386_collect_gregset); |
| 3238 | return tdep->gregset; |
| 3239 | } |
| 3240 | |
| 3241 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
| 3242 | || (strcmp (sect_name, ".reg-xfp") == 0 |
| 3243 | && sect_size == I387_SIZEOF_FXSAVE)) |
| 3244 | { |
| 3245 | if (tdep->fpregset == NULL) |
| 3246 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
| 3247 | i386_collect_fpregset); |
| 3248 | return tdep->fpregset; |
| 3249 | } |
| 3250 | |
| 3251 | if (strcmp (sect_name, ".reg-xstate") == 0) |
| 3252 | { |
| 3253 | if (tdep->xstateregset == NULL) |
| 3254 | tdep->xstateregset = regset_alloc (gdbarch, |
| 3255 | i386_supply_xstateregset, |
| 3256 | i386_collect_xstateregset); |
| 3257 | |
| 3258 | return tdep->xstateregset; |
| 3259 | } |
| 3260 | |
| 3261 | return NULL; |
| 3262 | } |
| 3263 | \f |
| 3264 | |
| 3265 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
| 3266 | |
| 3267 | CORE_ADDR |
| 3268 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
| 3269 | CORE_ADDR pc, char *name) |
| 3270 | { |
| 3271 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 3272 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3273 | |
| 3274 | /* jmp *(dest) */ |
| 3275 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) |
| 3276 | { |
| 3277 | unsigned long indirect = |
| 3278 | read_memory_unsigned_integer (pc + 2, 4, byte_order); |
| 3279 | struct minimal_symbol *indsym = |
| 3280 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
| 3281 | const char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
| 3282 | |
| 3283 | if (symname) |
| 3284 | { |
| 3285 | if (strncmp (symname, "__imp_", 6) == 0 |
| 3286 | || strncmp (symname, "_imp_", 5) == 0) |
| 3287 | return name ? 1 : |
| 3288 | read_memory_unsigned_integer (indirect, 4, byte_order); |
| 3289 | } |
| 3290 | } |
| 3291 | return 0; /* Not a trampoline. */ |
| 3292 | } |
| 3293 | \f |
| 3294 | |
| 3295 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
| 3296 | routine. */ |
| 3297 | |
| 3298 | int |
| 3299 | i386_sigtramp_p (struct frame_info *this_frame) |
| 3300 | { |
| 3301 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 3302 | const char *name; |
| 3303 | |
| 3304 | find_pc_partial_function (pc, &name, NULL, NULL); |
| 3305 | return (name && strcmp ("_sigtramp", name) == 0); |
| 3306 | } |
| 3307 | \f |
| 3308 | |
| 3309 | /* We have two flavours of disassembly. The machinery on this page |
| 3310 | deals with switching between those. */ |
| 3311 | |
| 3312 | static int |
| 3313 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
| 3314 | { |
| 3315 | gdb_assert (disassembly_flavor == att_flavor |
| 3316 | || disassembly_flavor == intel_flavor); |
| 3317 | |
| 3318 | /* FIXME: kettenis/20020915: Until disassembler_options is properly |
| 3319 | constified, cast to prevent a compiler warning. */ |
| 3320 | info->disassembler_options = (char *) disassembly_flavor; |
| 3321 | |
| 3322 | return print_insn_i386 (pc, info); |
| 3323 | } |
| 3324 | \f |
| 3325 | |
| 3326 | /* There are a few i386 architecture variants that differ only |
| 3327 | slightly from the generic i386 target. For now, we don't give them |
| 3328 | their own source file, but include them here. As a consequence, |
| 3329 | they'll always be included. */ |
| 3330 | |
| 3331 | /* System V Release 4 (SVR4). */ |
| 3332 | |
| 3333 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
| 3334 | routine. */ |
| 3335 | |
| 3336 | static int |
| 3337 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
| 3338 | { |
| 3339 | CORE_ADDR pc = get_frame_pc (this_frame); |
| 3340 | const char *name; |
| 3341 | |
| 3342 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
| 3343 | currently unknown. */ |
| 3344 | find_pc_partial_function (pc, &name, NULL, NULL); |
| 3345 | return (name && (strcmp ("_sigreturn", name) == 0 |
| 3346 | || strcmp ("_sigacthandler", name) == 0 |
| 3347 | || strcmp ("sigvechandler", name) == 0)); |
| 3348 | } |
| 3349 | |
| 3350 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
| 3351 | address of the associated sigcontext (ucontext) structure. */ |
| 3352 | |
| 3353 | static CORE_ADDR |
| 3354 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
| 3355 | { |
| 3356 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 3357 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3358 | gdb_byte buf[4]; |
| 3359 | CORE_ADDR sp; |
| 3360 | |
| 3361 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
| 3362 | sp = extract_unsigned_integer (buf, 4, byte_order); |
| 3363 | |
| 3364 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
| 3365 | } |
| 3366 | \f |
| 3367 | |
| 3368 | /* Generic ELF. */ |
| 3369 | |
| 3370 | void |
| 3371 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
| 3372 | { |
| 3373 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
| 3374 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
| 3375 | } |
| 3376 | |
| 3377 | /* System V Release 4 (SVR4). */ |
| 3378 | |
| 3379 | void |
| 3380 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
| 3381 | { |
| 3382 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3383 | |
| 3384 | /* System V Release 4 uses ELF. */ |
| 3385 | i386_elf_init_abi (info, gdbarch); |
| 3386 | |
| 3387 | /* System V Release 4 has shared libraries. */ |
| 3388 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
| 3389 | |
| 3390 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
| 3391 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
| 3392 | tdep->sc_pc_offset = 36 + 14 * 4; |
| 3393 | tdep->sc_sp_offset = 36 + 17 * 4; |
| 3394 | |
| 3395 | tdep->jb_pc_offset = 20; |
| 3396 | } |
| 3397 | |
| 3398 | /* DJGPP. */ |
| 3399 | |
| 3400 | static void |
| 3401 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
| 3402 | { |
| 3403 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3404 | |
| 3405 | /* DJGPP doesn't have any special frames for signal handlers. */ |
| 3406 | tdep->sigtramp_p = NULL; |
| 3407 | |
| 3408 | tdep->jb_pc_offset = 36; |
| 3409 | |
| 3410 | /* DJGPP does not support the SSE registers. */ |
| 3411 | if (! tdesc_has_registers (info.target_desc)) |
| 3412 | tdep->tdesc = tdesc_i386_mmx; |
| 3413 | |
| 3414 | /* Native compiler is GCC, which uses the SVR4 register numbering |
| 3415 | even in COFF and STABS. See the comment in i386_gdbarch_init, |
| 3416 | before the calls to set_gdbarch_stab_reg_to_regnum and |
| 3417 | set_gdbarch_sdb_reg_to_regnum. */ |
| 3418 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
| 3419 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
| 3420 | |
| 3421 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); |
| 3422 | } |
| 3423 | \f |
| 3424 | |
| 3425 | /* i386 register groups. In addition to the normal groups, add "mmx" |
| 3426 | and "sse". */ |
| 3427 | |
| 3428 | static struct reggroup *i386_sse_reggroup; |
| 3429 | static struct reggroup *i386_mmx_reggroup; |
| 3430 | |
| 3431 | static void |
| 3432 | i386_init_reggroups (void) |
| 3433 | { |
| 3434 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); |
| 3435 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); |
| 3436 | } |
| 3437 | |
| 3438 | static void |
| 3439 | i386_add_reggroups (struct gdbarch *gdbarch) |
| 3440 | { |
| 3441 | reggroup_add (gdbarch, i386_sse_reggroup); |
| 3442 | reggroup_add (gdbarch, i386_mmx_reggroup); |
| 3443 | reggroup_add (gdbarch, general_reggroup); |
| 3444 | reggroup_add (gdbarch, float_reggroup); |
| 3445 | reggroup_add (gdbarch, all_reggroup); |
| 3446 | reggroup_add (gdbarch, save_reggroup); |
| 3447 | reggroup_add (gdbarch, restore_reggroup); |
| 3448 | reggroup_add (gdbarch, vector_reggroup); |
| 3449 | reggroup_add (gdbarch, system_reggroup); |
| 3450 | } |
| 3451 | |
| 3452 | int |
| 3453 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 3454 | struct reggroup *group) |
| 3455 | { |
| 3456 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3457 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, |
| 3458 | ymm_regnum_p, ymmh_regnum_p; |
| 3459 | |
| 3460 | /* Don't include pseudo registers, except for MMX, in any register |
| 3461 | groups. */ |
| 3462 | if (i386_byte_regnum_p (gdbarch, regnum)) |
| 3463 | return 0; |
| 3464 | |
| 3465 | if (i386_word_regnum_p (gdbarch, regnum)) |
| 3466 | return 0; |
| 3467 | |
| 3468 | if (i386_dword_regnum_p (gdbarch, regnum)) |
| 3469 | return 0; |
| 3470 | |
| 3471 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); |
| 3472 | if (group == i386_mmx_reggroup) |
| 3473 | return mmx_regnum_p; |
| 3474 | |
| 3475 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
| 3476 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
| 3477 | if (group == i386_sse_reggroup) |
| 3478 | return xmm_regnum_p || mxcsr_regnum_p; |
| 3479 | |
| 3480 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); |
| 3481 | if (group == vector_reggroup) |
| 3482 | return (mmx_regnum_p |
| 3483 | || ymm_regnum_p |
| 3484 | || mxcsr_regnum_p |
| 3485 | || (xmm_regnum_p |
| 3486 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) |
| 3487 | == I386_XSTATE_SSE_MASK))); |
| 3488 | |
| 3489 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) |
| 3490 | || i386_fpc_regnum_p (gdbarch, regnum)); |
| 3491 | if (group == float_reggroup) |
| 3492 | return fp_regnum_p; |
| 3493 | |
| 3494 | /* For "info reg all", don't include upper YMM registers nor XMM |
| 3495 | registers when AVX is supported. */ |
| 3496 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); |
| 3497 | if (group == all_reggroup |
| 3498 | && ((xmm_regnum_p |
| 3499 | && (tdep->xcr0 & I386_XSTATE_AVX)) |
| 3500 | || ymmh_regnum_p)) |
| 3501 | return 0; |
| 3502 | |
| 3503 | if (group == general_reggroup) |
| 3504 | return (!fp_regnum_p |
| 3505 | && !mmx_regnum_p |
| 3506 | && !mxcsr_regnum_p |
| 3507 | && !xmm_regnum_p |
| 3508 | && !ymm_regnum_p |
| 3509 | && !ymmh_regnum_p); |
| 3510 | |
| 3511 | return default_register_reggroup_p (gdbarch, regnum, group); |
| 3512 | } |
| 3513 | \f |
| 3514 | |
| 3515 | /* Get the ARGIth function argument for the current function. */ |
| 3516 | |
| 3517 | static CORE_ADDR |
| 3518 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
| 3519 | struct type *type) |
| 3520 | { |
| 3521 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 3522 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3523 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
| 3524 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
| 3525 | } |
| 3526 | |
| 3527 | static void |
| 3528 | i386_skip_permanent_breakpoint (struct regcache *regcache) |
| 3529 | { |
| 3530 | CORE_ADDR current_pc = regcache_read_pc (regcache); |
| 3531 | |
| 3532 | /* On i386, breakpoint is exactly 1 byte long, so we just |
| 3533 | adjust the PC in the regcache. */ |
| 3534 | current_pc += 1; |
| 3535 | regcache_write_pc (regcache, current_pc); |
| 3536 | } |
| 3537 | |
| 3538 | |
| 3539 | #define PREFIX_REPZ 0x01 |
| 3540 | #define PREFIX_REPNZ 0x02 |
| 3541 | #define PREFIX_LOCK 0x04 |
| 3542 | #define PREFIX_DATA 0x08 |
| 3543 | #define PREFIX_ADDR 0x10 |
| 3544 | |
| 3545 | /* operand size */ |
| 3546 | enum |
| 3547 | { |
| 3548 | OT_BYTE = 0, |
| 3549 | OT_WORD, |
| 3550 | OT_LONG, |
| 3551 | OT_QUAD, |
| 3552 | OT_DQUAD, |
| 3553 | }; |
| 3554 | |
| 3555 | /* i386 arith/logic operations */ |
| 3556 | enum |
| 3557 | { |
| 3558 | OP_ADDL, |
| 3559 | OP_ORL, |
| 3560 | OP_ADCL, |
| 3561 | OP_SBBL, |
| 3562 | OP_ANDL, |
| 3563 | OP_SUBL, |
| 3564 | OP_XORL, |
| 3565 | OP_CMPL, |
| 3566 | }; |
| 3567 | |
| 3568 | struct i386_record_s |
| 3569 | { |
| 3570 | struct gdbarch *gdbarch; |
| 3571 | struct regcache *regcache; |
| 3572 | CORE_ADDR orig_addr; |
| 3573 | CORE_ADDR addr; |
| 3574 | int aflag; |
| 3575 | int dflag; |
| 3576 | int override; |
| 3577 | uint8_t modrm; |
| 3578 | uint8_t mod, reg, rm; |
| 3579 | int ot; |
| 3580 | uint8_t rex_x; |
| 3581 | uint8_t rex_b; |
| 3582 | int rip_offset; |
| 3583 | int popl_esp_hack; |
| 3584 | const int *regmap; |
| 3585 | }; |
| 3586 | |
| 3587 | /* Parse "modrm" part in current memory address that irp->addr point to |
| 3588 | Return -1 if something wrong. */ |
| 3589 | |
| 3590 | static int |
| 3591 | i386_record_modrm (struct i386_record_s *irp) |
| 3592 | { |
| 3593 | struct gdbarch *gdbarch = irp->gdbarch; |
| 3594 | |
| 3595 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
| 3596 | { |
| 3597 | if (record_debug) |
| 3598 | printf_unfiltered (_("Process record: error reading memory at " |
| 3599 | "addr %s len = 1.\n"), |
| 3600 | paddress (gdbarch, irp->addr)); |
| 3601 | return -1; |
| 3602 | } |
| 3603 | irp->addr++; |
| 3604 | irp->mod = (irp->modrm >> 6) & 3; |
| 3605 | irp->reg = (irp->modrm >> 3) & 7; |
| 3606 | irp->rm = irp->modrm & 7; |
| 3607 | |
| 3608 | return 0; |
| 3609 | } |
| 3610 | |
| 3611 | /* Get the memory address that current instruction write to and set it to |
| 3612 | the argument "addr". |
| 3613 | Return -1 if something wrong. */ |
| 3614 | |
| 3615 | static int |
| 3616 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
| 3617 | { |
| 3618 | struct gdbarch *gdbarch = irp->gdbarch; |
| 3619 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3620 | gdb_byte buf[4]; |
| 3621 | ULONGEST offset64; |
| 3622 | |
| 3623 | *addr = 0; |
| 3624 | if (irp->aflag) |
| 3625 | { |
| 3626 | /* 32 bits */ |
| 3627 | int havesib = 0; |
| 3628 | uint8_t scale = 0; |
| 3629 | uint8_t byte; |
| 3630 | uint8_t index = 0; |
| 3631 | uint8_t base = irp->rm; |
| 3632 | |
| 3633 | if (base == 4) |
| 3634 | { |
| 3635 | havesib = 1; |
| 3636 | if (target_read_memory (irp->addr, &byte, 1)) |
| 3637 | { |
| 3638 | if (record_debug) |
| 3639 | printf_unfiltered (_("Process record: error reading memory " |
| 3640 | "at addr %s len = 1.\n"), |
| 3641 | paddress (gdbarch, irp->addr)); |
| 3642 | return -1; |
| 3643 | } |
| 3644 | irp->addr++; |
| 3645 | scale = (byte >> 6) & 3; |
| 3646 | index = ((byte >> 3) & 7) | irp->rex_x; |
| 3647 | base = (byte & 7); |
| 3648 | } |
| 3649 | base |= irp->rex_b; |
| 3650 | |
| 3651 | switch (irp->mod) |
| 3652 | { |
| 3653 | case 0: |
| 3654 | if ((base & 7) == 5) |
| 3655 | { |
| 3656 | base = 0xff; |
| 3657 | if (target_read_memory (irp->addr, buf, 4)) |
| 3658 | { |
| 3659 | if (record_debug) |
| 3660 | printf_unfiltered (_("Process record: error reading " |
| 3661 | "memory at addr %s len = 4.\n"), |
| 3662 | paddress (gdbarch, irp->addr)); |
| 3663 | return -1; |
| 3664 | } |
| 3665 | irp->addr += 4; |
| 3666 | *addr = extract_signed_integer (buf, 4, byte_order); |
| 3667 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
| 3668 | *addr += irp->addr + irp->rip_offset; |
| 3669 | } |
| 3670 | break; |
| 3671 | case 1: |
| 3672 | if (target_read_memory (irp->addr, buf, 1)) |
| 3673 | { |
| 3674 | if (record_debug) |
| 3675 | printf_unfiltered (_("Process record: error reading memory " |
| 3676 | "at addr %s len = 1.\n"), |
| 3677 | paddress (gdbarch, irp->addr)); |
| 3678 | return -1; |
| 3679 | } |
| 3680 | irp->addr++; |
| 3681 | *addr = (int8_t) buf[0]; |
| 3682 | break; |
| 3683 | case 2: |
| 3684 | if (target_read_memory (irp->addr, buf, 4)) |
| 3685 | { |
| 3686 | if (record_debug) |
| 3687 | printf_unfiltered (_("Process record: error reading memory " |
| 3688 | "at addr %s len = 4.\n"), |
| 3689 | paddress (gdbarch, irp->addr)); |
| 3690 | return -1; |
| 3691 | } |
| 3692 | *addr = extract_signed_integer (buf, 4, byte_order); |
| 3693 | irp->addr += 4; |
| 3694 | break; |
| 3695 | } |
| 3696 | |
| 3697 | offset64 = 0; |
| 3698 | if (base != 0xff) |
| 3699 | { |
| 3700 | if (base == 4 && irp->popl_esp_hack) |
| 3701 | *addr += irp->popl_esp_hack; |
| 3702 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], |
| 3703 | &offset64); |
| 3704 | } |
| 3705 | if (irp->aflag == 2) |
| 3706 | { |
| 3707 | *addr += offset64; |
| 3708 | } |
| 3709 | else |
| 3710 | *addr = (uint32_t) (offset64 + *addr); |
| 3711 | |
| 3712 | if (havesib && (index != 4 || scale != 0)) |
| 3713 | { |
| 3714 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
| 3715 | &offset64); |
| 3716 | if (irp->aflag == 2) |
| 3717 | *addr += offset64 << scale; |
| 3718 | else |
| 3719 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
| 3720 | } |
| 3721 | } |
| 3722 | else |
| 3723 | { |
| 3724 | /* 16 bits */ |
| 3725 | switch (irp->mod) |
| 3726 | { |
| 3727 | case 0: |
| 3728 | if (irp->rm == 6) |
| 3729 | { |
| 3730 | if (target_read_memory (irp->addr, buf, 2)) |
| 3731 | { |
| 3732 | if (record_debug) |
| 3733 | printf_unfiltered (_("Process record: error reading " |
| 3734 | "memory at addr %s len = 2.\n"), |
| 3735 | paddress (gdbarch, irp->addr)); |
| 3736 | return -1; |
| 3737 | } |
| 3738 | irp->addr += 2; |
| 3739 | *addr = extract_signed_integer (buf, 2, byte_order); |
| 3740 | irp->rm = 0; |
| 3741 | goto no_rm; |
| 3742 | } |
| 3743 | break; |
| 3744 | case 1: |
| 3745 | if (target_read_memory (irp->addr, buf, 1)) |
| 3746 | { |
| 3747 | if (record_debug) |
| 3748 | printf_unfiltered (_("Process record: error reading memory " |
| 3749 | "at addr %s len = 1.\n"), |
| 3750 | paddress (gdbarch, irp->addr)); |
| 3751 | return -1; |
| 3752 | } |
| 3753 | irp->addr++; |
| 3754 | *addr = (int8_t) buf[0]; |
| 3755 | break; |
| 3756 | case 2: |
| 3757 | if (target_read_memory (irp->addr, buf, 2)) |
| 3758 | { |
| 3759 | if (record_debug) |
| 3760 | printf_unfiltered (_("Process record: error reading memory " |
| 3761 | "at addr %s len = 2.\n"), |
| 3762 | paddress (gdbarch, irp->addr)); |
| 3763 | return -1; |
| 3764 | } |
| 3765 | irp->addr += 2; |
| 3766 | *addr = extract_signed_integer (buf, 2, byte_order); |
| 3767 | break; |
| 3768 | } |
| 3769 | |
| 3770 | switch (irp->rm) |
| 3771 | { |
| 3772 | case 0: |
| 3773 | regcache_raw_read_unsigned (irp->regcache, |
| 3774 | irp->regmap[X86_RECORD_REBX_REGNUM], |
| 3775 | &offset64); |
| 3776 | *addr = (uint32_t) (*addr + offset64); |
| 3777 | regcache_raw_read_unsigned (irp->regcache, |
| 3778 | irp->regmap[X86_RECORD_RESI_REGNUM], |
| 3779 | &offset64); |
| 3780 | *addr = (uint32_t) (*addr + offset64); |
| 3781 | break; |
| 3782 | case 1: |
| 3783 | regcache_raw_read_unsigned (irp->regcache, |
| 3784 | irp->regmap[X86_RECORD_REBX_REGNUM], |
| 3785 | &offset64); |
| 3786 | *addr = (uint32_t) (*addr + offset64); |
| 3787 | regcache_raw_read_unsigned (irp->regcache, |
| 3788 | irp->regmap[X86_RECORD_REDI_REGNUM], |
| 3789 | &offset64); |
| 3790 | *addr = (uint32_t) (*addr + offset64); |
| 3791 | break; |
| 3792 | case 2: |
| 3793 | regcache_raw_read_unsigned (irp->regcache, |
| 3794 | irp->regmap[X86_RECORD_REBP_REGNUM], |
| 3795 | &offset64); |
| 3796 | *addr = (uint32_t) (*addr + offset64); |
| 3797 | regcache_raw_read_unsigned (irp->regcache, |
| 3798 | irp->regmap[X86_RECORD_RESI_REGNUM], |
| 3799 | &offset64); |
| 3800 | *addr = (uint32_t) (*addr + offset64); |
| 3801 | break; |
| 3802 | case 3: |
| 3803 | regcache_raw_read_unsigned (irp->regcache, |
| 3804 | irp->regmap[X86_RECORD_REBP_REGNUM], |
| 3805 | &offset64); |
| 3806 | *addr = (uint32_t) (*addr + offset64); |
| 3807 | regcache_raw_read_unsigned (irp->regcache, |
| 3808 | irp->regmap[X86_RECORD_REDI_REGNUM], |
| 3809 | &offset64); |
| 3810 | *addr = (uint32_t) (*addr + offset64); |
| 3811 | break; |
| 3812 | case 4: |
| 3813 | regcache_raw_read_unsigned (irp->regcache, |
| 3814 | irp->regmap[X86_RECORD_RESI_REGNUM], |
| 3815 | &offset64); |
| 3816 | *addr = (uint32_t) (*addr + offset64); |
| 3817 | break; |
| 3818 | case 5: |
| 3819 | regcache_raw_read_unsigned (irp->regcache, |
| 3820 | irp->regmap[X86_RECORD_REDI_REGNUM], |
| 3821 | &offset64); |
| 3822 | *addr = (uint32_t) (*addr + offset64); |
| 3823 | break; |
| 3824 | case 6: |
| 3825 | regcache_raw_read_unsigned (irp->regcache, |
| 3826 | irp->regmap[X86_RECORD_REBP_REGNUM], |
| 3827 | &offset64); |
| 3828 | *addr = (uint32_t) (*addr + offset64); |
| 3829 | break; |
| 3830 | case 7: |
| 3831 | regcache_raw_read_unsigned (irp->regcache, |
| 3832 | irp->regmap[X86_RECORD_REBX_REGNUM], |
| 3833 | &offset64); |
| 3834 | *addr = (uint32_t) (*addr + offset64); |
| 3835 | break; |
| 3836 | } |
| 3837 | *addr &= 0xffff; |
| 3838 | } |
| 3839 | |
| 3840 | no_rm: |
| 3841 | return 0; |
| 3842 | } |
| 3843 | |
| 3844 | /* Record the value of the memory that willbe changed in current instruction |
| 3845 | to "record_arch_list". |
| 3846 | Return -1 if something wrong. */ |
| 3847 | |
| 3848 | static int |
| 3849 | i386_record_lea_modrm (struct i386_record_s *irp) |
| 3850 | { |
| 3851 | struct gdbarch *gdbarch = irp->gdbarch; |
| 3852 | uint64_t addr; |
| 3853 | |
| 3854 | if (irp->override >= 0) |
| 3855 | { |
| 3856 | if (record_memory_query) |
| 3857 | { |
| 3858 | int q; |
| 3859 | |
| 3860 | target_terminal_ours (); |
| 3861 | q = yquery (_("\ |
| 3862 | Process record ignores the memory change of instruction at address %s\n\ |
| 3863 | because it can't get the value of the segment register.\n\ |
| 3864 | Do you want to stop the program?"), |
| 3865 | paddress (gdbarch, irp->orig_addr)); |
| 3866 | target_terminal_inferior (); |
| 3867 | if (q) |
| 3868 | return -1; |
| 3869 | } |
| 3870 | |
| 3871 | return 0; |
| 3872 | } |
| 3873 | |
| 3874 | if (i386_record_lea_modrm_addr (irp, &addr)) |
| 3875 | return -1; |
| 3876 | |
| 3877 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
| 3878 | return -1; |
| 3879 | |
| 3880 | return 0; |
| 3881 | } |
| 3882 | |
| 3883 | /* Record the push operation to "record_arch_list". |
| 3884 | Return -1 if something wrong. */ |
| 3885 | |
| 3886 | static int |
| 3887 | i386_record_push (struct i386_record_s *irp, int size) |
| 3888 | { |
| 3889 | ULONGEST addr; |
| 3890 | |
| 3891 | if (record_arch_list_add_reg (irp->regcache, |
| 3892 | irp->regmap[X86_RECORD_RESP_REGNUM])) |
| 3893 | return -1; |
| 3894 | regcache_raw_read_unsigned (irp->regcache, |
| 3895 | irp->regmap[X86_RECORD_RESP_REGNUM], |
| 3896 | &addr); |
| 3897 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
| 3898 | return -1; |
| 3899 | |
| 3900 | return 0; |
| 3901 | } |
| 3902 | |
| 3903 | |
| 3904 | /* Defines contents to record. */ |
| 3905 | #define I386_SAVE_FPU_REGS 0xfffd |
| 3906 | #define I386_SAVE_FPU_ENV 0xfffe |
| 3907 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff |
| 3908 | |
| 3909 | /* Record the value of floating point registers which will be changed |
| 3910 | by the current instruction to "record_arch_list". Return -1 if |
| 3911 | something is wrong. */ |
| 3912 | |
| 3913 | static int i386_record_floats (struct gdbarch *gdbarch, |
| 3914 | struct i386_record_s *ir, |
| 3915 | uint32_t iregnum) |
| 3916 | { |
| 3917 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3918 | int i; |
| 3919 | |
| 3920 | /* Oza: Because of floating point insn push/pop of fpu stack is going to |
| 3921 | happen. Currently we store st0-st7 registers, but we need not store all |
| 3922 | registers all the time, in future we use ftag register and record only |
| 3923 | those who are not marked as an empty. */ |
| 3924 | |
| 3925 | if (I386_SAVE_FPU_REGS == iregnum) |
| 3926 | { |
| 3927 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) |
| 3928 | { |
| 3929 | if (record_arch_list_add_reg (ir->regcache, i)) |
| 3930 | return -1; |
| 3931 | } |
| 3932 | } |
| 3933 | else if (I386_SAVE_FPU_ENV == iregnum) |
| 3934 | { |
| 3935 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) |
| 3936 | { |
| 3937 | if (record_arch_list_add_reg (ir->regcache, i)) |
| 3938 | return -1; |
| 3939 | } |
| 3940 | } |
| 3941 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) |
| 3942 | { |
| 3943 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) |
| 3944 | { |
| 3945 | if (record_arch_list_add_reg (ir->regcache, i)) |
| 3946 | return -1; |
| 3947 | } |
| 3948 | } |
| 3949 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && |
| 3950 | (iregnum <= I387_FOP_REGNUM (tdep))) |
| 3951 | { |
| 3952 | if (record_arch_list_add_reg (ir->regcache,iregnum)) |
| 3953 | return -1; |
| 3954 | } |
| 3955 | else |
| 3956 | { |
| 3957 | /* Parameter error. */ |
| 3958 | return -1; |
| 3959 | } |
| 3960 | if(I386_SAVE_FPU_ENV != iregnum) |
| 3961 | { |
| 3962 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) |
| 3963 | { |
| 3964 | if (record_arch_list_add_reg (ir->regcache, i)) |
| 3965 | return -1; |
| 3966 | } |
| 3967 | } |
| 3968 | return 0; |
| 3969 | } |
| 3970 | |
| 3971 | /* Parse the current instruction and record the values of the registers and |
| 3972 | memory that will be changed in current instruction to "record_arch_list". |
| 3973 | Return -1 if something wrong. */ |
| 3974 | |
| 3975 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
| 3976 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) |
| 3977 | |
| 3978 | int |
| 3979 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
| 3980 | CORE_ADDR input_addr) |
| 3981 | { |
| 3982 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 3983 | int prefixes = 0; |
| 3984 | int regnum = 0; |
| 3985 | uint32_t opcode; |
| 3986 | uint8_t opcode8; |
| 3987 | ULONGEST addr; |
| 3988 | gdb_byte buf[MAX_REGISTER_SIZE]; |
| 3989 | struct i386_record_s ir; |
| 3990 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 3991 | int rex = 0; |
| 3992 | uint8_t rex_w = -1; |
| 3993 | uint8_t rex_r = 0; |
| 3994 | |
| 3995 | memset (&ir, 0, sizeof (struct i386_record_s)); |
| 3996 | ir.regcache = regcache; |
| 3997 | ir.addr = input_addr; |
| 3998 | ir.orig_addr = input_addr; |
| 3999 | ir.aflag = 1; |
| 4000 | ir.dflag = 1; |
| 4001 | ir.override = -1; |
| 4002 | ir.popl_esp_hack = 0; |
| 4003 | ir.regmap = tdep->record_regmap; |
| 4004 | ir.gdbarch = gdbarch; |
| 4005 | |
| 4006 | if (record_debug > 1) |
| 4007 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " |
| 4008 | "addr = %s\n", |
| 4009 | paddress (gdbarch, ir.addr)); |
| 4010 | |
| 4011 | /* prefixes */ |
| 4012 | while (1) |
| 4013 | { |
| 4014 | if (target_read_memory (ir.addr, &opcode8, 1)) |
| 4015 | { |
| 4016 | if (record_debug) |
| 4017 | printf_unfiltered (_("Process record: error reading memory at " |
| 4018 | "addr %s len = 1.\n"), |
| 4019 | paddress (gdbarch, ir.addr)); |
| 4020 | return -1; |
| 4021 | } |
| 4022 | ir.addr++; |
| 4023 | switch (opcode8) /* Instruction prefixes */ |
| 4024 | { |
| 4025 | case REPE_PREFIX_OPCODE: |
| 4026 | prefixes |= PREFIX_REPZ; |
| 4027 | break; |
| 4028 | case REPNE_PREFIX_OPCODE: |
| 4029 | prefixes |= PREFIX_REPNZ; |
| 4030 | break; |
| 4031 | case LOCK_PREFIX_OPCODE: |
| 4032 | prefixes |= PREFIX_LOCK; |
| 4033 | break; |
| 4034 | case CS_PREFIX_OPCODE: |
| 4035 | ir.override = X86_RECORD_CS_REGNUM; |
| 4036 | break; |
| 4037 | case SS_PREFIX_OPCODE: |
| 4038 | ir.override = X86_RECORD_SS_REGNUM; |
| 4039 | break; |
| 4040 | case DS_PREFIX_OPCODE: |
| 4041 | ir.override = X86_RECORD_DS_REGNUM; |
| 4042 | break; |
| 4043 | case ES_PREFIX_OPCODE: |
| 4044 | ir.override = X86_RECORD_ES_REGNUM; |
| 4045 | break; |
| 4046 | case FS_PREFIX_OPCODE: |
| 4047 | ir.override = X86_RECORD_FS_REGNUM; |
| 4048 | break; |
| 4049 | case GS_PREFIX_OPCODE: |
| 4050 | ir.override = X86_RECORD_GS_REGNUM; |
| 4051 | break; |
| 4052 | case DATA_PREFIX_OPCODE: |
| 4053 | prefixes |= PREFIX_DATA; |
| 4054 | break; |
| 4055 | case ADDR_PREFIX_OPCODE: |
| 4056 | prefixes |= PREFIX_ADDR; |
| 4057 | break; |
| 4058 | case 0x40: /* i386 inc %eax */ |
| 4059 | case 0x41: /* i386 inc %ecx */ |
| 4060 | case 0x42: /* i386 inc %edx */ |
| 4061 | case 0x43: /* i386 inc %ebx */ |
| 4062 | case 0x44: /* i386 inc %esp */ |
| 4063 | case 0x45: /* i386 inc %ebp */ |
| 4064 | case 0x46: /* i386 inc %esi */ |
| 4065 | case 0x47: /* i386 inc %edi */ |
| 4066 | case 0x48: /* i386 dec %eax */ |
| 4067 | case 0x49: /* i386 dec %ecx */ |
| 4068 | case 0x4a: /* i386 dec %edx */ |
| 4069 | case 0x4b: /* i386 dec %ebx */ |
| 4070 | case 0x4c: /* i386 dec %esp */ |
| 4071 | case 0x4d: /* i386 dec %ebp */ |
| 4072 | case 0x4e: /* i386 dec %esi */ |
| 4073 | case 0x4f: /* i386 dec %edi */ |
| 4074 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ |
| 4075 | { |
| 4076 | /* REX */ |
| 4077 | rex = 1; |
| 4078 | rex_w = (opcode8 >> 3) & 1; |
| 4079 | rex_r = (opcode8 & 0x4) << 1; |
| 4080 | ir.rex_x = (opcode8 & 0x2) << 2; |
| 4081 | ir.rex_b = (opcode8 & 0x1) << 3; |
| 4082 | } |
| 4083 | else /* 32 bit target */ |
| 4084 | goto out_prefixes; |
| 4085 | break; |
| 4086 | default: |
| 4087 | goto out_prefixes; |
| 4088 | break; |
| 4089 | } |
| 4090 | } |
| 4091 | out_prefixes: |
| 4092 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
| 4093 | { |
| 4094 | ir.dflag = 2; |
| 4095 | } |
| 4096 | else |
| 4097 | { |
| 4098 | if (prefixes & PREFIX_DATA) |
| 4099 | ir.dflag ^= 1; |
| 4100 | } |
| 4101 | if (prefixes & PREFIX_ADDR) |
| 4102 | ir.aflag ^= 1; |
| 4103 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4104 | ir.aflag = 2; |
| 4105 | |
| 4106 | /* Now check op code. */ |
| 4107 | opcode = (uint32_t) opcode8; |
| 4108 | reswitch: |
| 4109 | switch (opcode) |
| 4110 | { |
| 4111 | case 0x0f: |
| 4112 | if (target_read_memory (ir.addr, &opcode8, 1)) |
| 4113 | { |
| 4114 | if (record_debug) |
| 4115 | printf_unfiltered (_("Process record: error reading memory at " |
| 4116 | "addr %s len = 1.\n"), |
| 4117 | paddress (gdbarch, ir.addr)); |
| 4118 | return -1; |
| 4119 | } |
| 4120 | ir.addr++; |
| 4121 | opcode = (uint32_t) opcode8 | 0x0f00; |
| 4122 | goto reswitch; |
| 4123 | break; |
| 4124 | |
| 4125 | case 0x00: /* arith & logic */ |
| 4126 | case 0x01: |
| 4127 | case 0x02: |
| 4128 | case 0x03: |
| 4129 | case 0x04: |
| 4130 | case 0x05: |
| 4131 | case 0x08: |
| 4132 | case 0x09: |
| 4133 | case 0x0a: |
| 4134 | case 0x0b: |
| 4135 | case 0x0c: |
| 4136 | case 0x0d: |
| 4137 | case 0x10: |
| 4138 | case 0x11: |
| 4139 | case 0x12: |
| 4140 | case 0x13: |
| 4141 | case 0x14: |
| 4142 | case 0x15: |
| 4143 | case 0x18: |
| 4144 | case 0x19: |
| 4145 | case 0x1a: |
| 4146 | case 0x1b: |
| 4147 | case 0x1c: |
| 4148 | case 0x1d: |
| 4149 | case 0x20: |
| 4150 | case 0x21: |
| 4151 | case 0x22: |
| 4152 | case 0x23: |
| 4153 | case 0x24: |
| 4154 | case 0x25: |
| 4155 | case 0x28: |
| 4156 | case 0x29: |
| 4157 | case 0x2a: |
| 4158 | case 0x2b: |
| 4159 | case 0x2c: |
| 4160 | case 0x2d: |
| 4161 | case 0x30: |
| 4162 | case 0x31: |
| 4163 | case 0x32: |
| 4164 | case 0x33: |
| 4165 | case 0x34: |
| 4166 | case 0x35: |
| 4167 | case 0x38: |
| 4168 | case 0x39: |
| 4169 | case 0x3a: |
| 4170 | case 0x3b: |
| 4171 | case 0x3c: |
| 4172 | case 0x3d: |
| 4173 | if (((opcode >> 3) & 7) != OP_CMPL) |
| 4174 | { |
| 4175 | if ((opcode & 1) == 0) |
| 4176 | ir.ot = OT_BYTE; |
| 4177 | else |
| 4178 | ir.ot = ir.dflag + OT_WORD; |
| 4179 | |
| 4180 | switch ((opcode >> 1) & 3) |
| 4181 | { |
| 4182 | case 0: /* OP Ev, Gv */ |
| 4183 | if (i386_record_modrm (&ir)) |
| 4184 | return -1; |
| 4185 | if (ir.mod != 3) |
| 4186 | { |
| 4187 | if (i386_record_lea_modrm (&ir)) |
| 4188 | return -1; |
| 4189 | } |
| 4190 | else |
| 4191 | { |
| 4192 | ir.rm |= ir.rex_b; |
| 4193 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4194 | ir.rm &= 0x3; |
| 4195 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4196 | } |
| 4197 | break; |
| 4198 | case 1: /* OP Gv, Ev */ |
| 4199 | if (i386_record_modrm (&ir)) |
| 4200 | return -1; |
| 4201 | ir.reg |= rex_r; |
| 4202 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4203 | ir.reg &= 0x3; |
| 4204 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4205 | break; |
| 4206 | case 2: /* OP A, Iv */ |
| 4207 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4208 | break; |
| 4209 | } |
| 4210 | } |
| 4211 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4212 | break; |
| 4213 | |
| 4214 | case 0x80: /* GRP1 */ |
| 4215 | case 0x81: |
| 4216 | case 0x82: |
| 4217 | case 0x83: |
| 4218 | if (i386_record_modrm (&ir)) |
| 4219 | return -1; |
| 4220 | |
| 4221 | if (ir.reg != OP_CMPL) |
| 4222 | { |
| 4223 | if ((opcode & 1) == 0) |
| 4224 | ir.ot = OT_BYTE; |
| 4225 | else |
| 4226 | ir.ot = ir.dflag + OT_WORD; |
| 4227 | |
| 4228 | if (ir.mod != 3) |
| 4229 | { |
| 4230 | if (opcode == 0x83) |
| 4231 | ir.rip_offset = 1; |
| 4232 | else |
| 4233 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
| 4234 | if (i386_record_lea_modrm (&ir)) |
| 4235 | return -1; |
| 4236 | } |
| 4237 | else |
| 4238 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 4239 | } |
| 4240 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4241 | break; |
| 4242 | |
| 4243 | case 0x40: /* inc */ |
| 4244 | case 0x41: |
| 4245 | case 0x42: |
| 4246 | case 0x43: |
| 4247 | case 0x44: |
| 4248 | case 0x45: |
| 4249 | case 0x46: |
| 4250 | case 0x47: |
| 4251 | |
| 4252 | case 0x48: /* dec */ |
| 4253 | case 0x49: |
| 4254 | case 0x4a: |
| 4255 | case 0x4b: |
| 4256 | case 0x4c: |
| 4257 | case 0x4d: |
| 4258 | case 0x4e: |
| 4259 | case 0x4f: |
| 4260 | |
| 4261 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
| 4262 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4263 | break; |
| 4264 | |
| 4265 | case 0xf6: /* GRP3 */ |
| 4266 | case 0xf7: |
| 4267 | if ((opcode & 1) == 0) |
| 4268 | ir.ot = OT_BYTE; |
| 4269 | else |
| 4270 | ir.ot = ir.dflag + OT_WORD; |
| 4271 | if (i386_record_modrm (&ir)) |
| 4272 | return -1; |
| 4273 | |
| 4274 | if (ir.mod != 3 && ir.reg == 0) |
| 4275 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
| 4276 | |
| 4277 | switch (ir.reg) |
| 4278 | { |
| 4279 | case 0: /* test */ |
| 4280 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4281 | break; |
| 4282 | case 2: /* not */ |
| 4283 | case 3: /* neg */ |
| 4284 | if (ir.mod != 3) |
| 4285 | { |
| 4286 | if (i386_record_lea_modrm (&ir)) |
| 4287 | return -1; |
| 4288 | } |
| 4289 | else |
| 4290 | { |
| 4291 | ir.rm |= ir.rex_b; |
| 4292 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4293 | ir.rm &= 0x3; |
| 4294 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4295 | } |
| 4296 | if (ir.reg == 3) /* neg */ |
| 4297 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4298 | break; |
| 4299 | case 4: /* mul */ |
| 4300 | case 5: /* imul */ |
| 4301 | case 6: /* div */ |
| 4302 | case 7: /* idiv */ |
| 4303 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4304 | if (ir.ot != OT_BYTE) |
| 4305 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 4306 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4307 | break; |
| 4308 | default: |
| 4309 | ir.addr -= 2; |
| 4310 | opcode = opcode << 8 | ir.modrm; |
| 4311 | goto no_support; |
| 4312 | break; |
| 4313 | } |
| 4314 | break; |
| 4315 | |
| 4316 | case 0xfe: /* GRP4 */ |
| 4317 | case 0xff: /* GRP5 */ |
| 4318 | if (i386_record_modrm (&ir)) |
| 4319 | return -1; |
| 4320 | if (ir.reg >= 2 && opcode == 0xfe) |
| 4321 | { |
| 4322 | ir.addr -= 2; |
| 4323 | opcode = opcode << 8 | ir.modrm; |
| 4324 | goto no_support; |
| 4325 | } |
| 4326 | switch (ir.reg) |
| 4327 | { |
| 4328 | case 0: /* inc */ |
| 4329 | case 1: /* dec */ |
| 4330 | if ((opcode & 1) == 0) |
| 4331 | ir.ot = OT_BYTE; |
| 4332 | else |
| 4333 | ir.ot = ir.dflag + OT_WORD; |
| 4334 | if (ir.mod != 3) |
| 4335 | { |
| 4336 | if (i386_record_lea_modrm (&ir)) |
| 4337 | return -1; |
| 4338 | } |
| 4339 | else |
| 4340 | { |
| 4341 | ir.rm |= ir.rex_b; |
| 4342 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4343 | ir.rm &= 0x3; |
| 4344 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4345 | } |
| 4346 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4347 | break; |
| 4348 | case 2: /* call */ |
| 4349 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 4350 | ir.dflag = 2; |
| 4351 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4352 | return -1; |
| 4353 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4354 | break; |
| 4355 | case 3: /* lcall */ |
| 4356 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
| 4357 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4358 | return -1; |
| 4359 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4360 | break; |
| 4361 | case 4: /* jmp */ |
| 4362 | case 5: /* ljmp */ |
| 4363 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4364 | break; |
| 4365 | case 6: /* push */ |
| 4366 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 4367 | ir.dflag = 2; |
| 4368 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4369 | return -1; |
| 4370 | break; |
| 4371 | default: |
| 4372 | ir.addr -= 2; |
| 4373 | opcode = opcode << 8 | ir.modrm; |
| 4374 | goto no_support; |
| 4375 | break; |
| 4376 | } |
| 4377 | break; |
| 4378 | |
| 4379 | case 0x84: /* test */ |
| 4380 | case 0x85: |
| 4381 | case 0xa8: |
| 4382 | case 0xa9: |
| 4383 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4384 | break; |
| 4385 | |
| 4386 | case 0x98: /* CWDE/CBW */ |
| 4387 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4388 | break; |
| 4389 | |
| 4390 | case 0x99: /* CDQ/CWD */ |
| 4391 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4392 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 4393 | break; |
| 4394 | |
| 4395 | case 0x0faf: /* imul */ |
| 4396 | case 0x69: |
| 4397 | case 0x6b: |
| 4398 | ir.ot = ir.dflag + OT_WORD; |
| 4399 | if (i386_record_modrm (&ir)) |
| 4400 | return -1; |
| 4401 | if (opcode == 0x69) |
| 4402 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
| 4403 | else if (opcode == 0x6b) |
| 4404 | ir.rip_offset = 1; |
| 4405 | ir.reg |= rex_r; |
| 4406 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4407 | ir.reg &= 0x3; |
| 4408 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4409 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4410 | break; |
| 4411 | |
| 4412 | case 0x0fc0: /* xadd */ |
| 4413 | case 0x0fc1: |
| 4414 | if ((opcode & 1) == 0) |
| 4415 | ir.ot = OT_BYTE; |
| 4416 | else |
| 4417 | ir.ot = ir.dflag + OT_WORD; |
| 4418 | if (i386_record_modrm (&ir)) |
| 4419 | return -1; |
| 4420 | ir.reg |= rex_r; |
| 4421 | if (ir.mod == 3) |
| 4422 | { |
| 4423 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4424 | ir.reg &= 0x3; |
| 4425 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4426 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4427 | ir.rm &= 0x3; |
| 4428 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4429 | } |
| 4430 | else |
| 4431 | { |
| 4432 | if (i386_record_lea_modrm (&ir)) |
| 4433 | return -1; |
| 4434 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4435 | ir.reg &= 0x3; |
| 4436 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4437 | } |
| 4438 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4439 | break; |
| 4440 | |
| 4441 | case 0x0fb0: /* cmpxchg */ |
| 4442 | case 0x0fb1: |
| 4443 | if ((opcode & 1) == 0) |
| 4444 | ir.ot = OT_BYTE; |
| 4445 | else |
| 4446 | ir.ot = ir.dflag + OT_WORD; |
| 4447 | if (i386_record_modrm (&ir)) |
| 4448 | return -1; |
| 4449 | if (ir.mod == 3) |
| 4450 | { |
| 4451 | ir.reg |= rex_r; |
| 4452 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4453 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4454 | ir.reg &= 0x3; |
| 4455 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4456 | } |
| 4457 | else |
| 4458 | { |
| 4459 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4460 | if (i386_record_lea_modrm (&ir)) |
| 4461 | return -1; |
| 4462 | } |
| 4463 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4464 | break; |
| 4465 | |
| 4466 | case 0x0fc7: /* cmpxchg8b */ |
| 4467 | if (i386_record_modrm (&ir)) |
| 4468 | return -1; |
| 4469 | if (ir.mod == 3) |
| 4470 | { |
| 4471 | ir.addr -= 2; |
| 4472 | opcode = opcode << 8 | ir.modrm; |
| 4473 | goto no_support; |
| 4474 | } |
| 4475 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4476 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 4477 | if (i386_record_lea_modrm (&ir)) |
| 4478 | return -1; |
| 4479 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4480 | break; |
| 4481 | |
| 4482 | case 0x50: /* push */ |
| 4483 | case 0x51: |
| 4484 | case 0x52: |
| 4485 | case 0x53: |
| 4486 | case 0x54: |
| 4487 | case 0x55: |
| 4488 | case 0x56: |
| 4489 | case 0x57: |
| 4490 | case 0x68: |
| 4491 | case 0x6a: |
| 4492 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 4493 | ir.dflag = 2; |
| 4494 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4495 | return -1; |
| 4496 | break; |
| 4497 | |
| 4498 | case 0x06: /* push es */ |
| 4499 | case 0x0e: /* push cs */ |
| 4500 | case 0x16: /* push ss */ |
| 4501 | case 0x1e: /* push ds */ |
| 4502 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4503 | { |
| 4504 | ir.addr -= 1; |
| 4505 | goto no_support; |
| 4506 | } |
| 4507 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4508 | return -1; |
| 4509 | break; |
| 4510 | |
| 4511 | case 0x0fa0: /* push fs */ |
| 4512 | case 0x0fa8: /* push gs */ |
| 4513 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4514 | { |
| 4515 | ir.addr -= 2; |
| 4516 | goto no_support; |
| 4517 | } |
| 4518 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4519 | return -1; |
| 4520 | break; |
| 4521 | |
| 4522 | case 0x60: /* pusha */ |
| 4523 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4524 | { |
| 4525 | ir.addr -= 1; |
| 4526 | goto no_support; |
| 4527 | } |
| 4528 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) |
| 4529 | return -1; |
| 4530 | break; |
| 4531 | |
| 4532 | case 0x58: /* pop */ |
| 4533 | case 0x59: |
| 4534 | case 0x5a: |
| 4535 | case 0x5b: |
| 4536 | case 0x5c: |
| 4537 | case 0x5d: |
| 4538 | case 0x5e: |
| 4539 | case 0x5f: |
| 4540 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4541 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
| 4542 | break; |
| 4543 | |
| 4544 | case 0x61: /* popa */ |
| 4545 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4546 | { |
| 4547 | ir.addr -= 1; |
| 4548 | goto no_support; |
| 4549 | } |
| 4550 | for (regnum = X86_RECORD_REAX_REGNUM; |
| 4551 | regnum <= X86_RECORD_REDI_REGNUM; |
| 4552 | regnum++) |
| 4553 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
| 4554 | break; |
| 4555 | |
| 4556 | case 0x8f: /* pop */ |
| 4557 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4558 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; |
| 4559 | else |
| 4560 | ir.ot = ir.dflag + OT_WORD; |
| 4561 | if (i386_record_modrm (&ir)) |
| 4562 | return -1; |
| 4563 | if (ir.mod == 3) |
| 4564 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 4565 | else |
| 4566 | { |
| 4567 | ir.popl_esp_hack = 1 << ir.ot; |
| 4568 | if (i386_record_lea_modrm (&ir)) |
| 4569 | return -1; |
| 4570 | } |
| 4571 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4572 | break; |
| 4573 | |
| 4574 | case 0xc8: /* enter */ |
| 4575 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
| 4576 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 4577 | ir.dflag = 2; |
| 4578 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 4579 | return -1; |
| 4580 | break; |
| 4581 | |
| 4582 | case 0xc9: /* leave */ |
| 4583 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4584 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
| 4585 | break; |
| 4586 | |
| 4587 | case 0x07: /* pop es */ |
| 4588 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4589 | { |
| 4590 | ir.addr -= 1; |
| 4591 | goto no_support; |
| 4592 | } |
| 4593 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4594 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); |
| 4595 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4596 | break; |
| 4597 | |
| 4598 | case 0x17: /* pop ss */ |
| 4599 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4600 | { |
| 4601 | ir.addr -= 1; |
| 4602 | goto no_support; |
| 4603 | } |
| 4604 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4605 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); |
| 4606 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4607 | break; |
| 4608 | |
| 4609 | case 0x1f: /* pop ds */ |
| 4610 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4611 | { |
| 4612 | ir.addr -= 1; |
| 4613 | goto no_support; |
| 4614 | } |
| 4615 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4616 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); |
| 4617 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4618 | break; |
| 4619 | |
| 4620 | case 0x0fa1: /* pop fs */ |
| 4621 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4622 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); |
| 4623 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4624 | break; |
| 4625 | |
| 4626 | case 0x0fa9: /* pop gs */ |
| 4627 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 4628 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
| 4629 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4630 | break; |
| 4631 | |
| 4632 | case 0x88: /* mov */ |
| 4633 | case 0x89: |
| 4634 | case 0xc6: |
| 4635 | case 0xc7: |
| 4636 | if ((opcode & 1) == 0) |
| 4637 | ir.ot = OT_BYTE; |
| 4638 | else |
| 4639 | ir.ot = ir.dflag + OT_WORD; |
| 4640 | |
| 4641 | if (i386_record_modrm (&ir)) |
| 4642 | return -1; |
| 4643 | |
| 4644 | if (ir.mod != 3) |
| 4645 | { |
| 4646 | if (opcode == 0xc6 || opcode == 0xc7) |
| 4647 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
| 4648 | if (i386_record_lea_modrm (&ir)) |
| 4649 | return -1; |
| 4650 | } |
| 4651 | else |
| 4652 | { |
| 4653 | if (opcode == 0xc6 || opcode == 0xc7) |
| 4654 | ir.rm |= ir.rex_b; |
| 4655 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4656 | ir.rm &= 0x3; |
| 4657 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4658 | } |
| 4659 | break; |
| 4660 | |
| 4661 | case 0x8a: /* mov */ |
| 4662 | case 0x8b: |
| 4663 | if ((opcode & 1) == 0) |
| 4664 | ir.ot = OT_BYTE; |
| 4665 | else |
| 4666 | ir.ot = ir.dflag + OT_WORD; |
| 4667 | if (i386_record_modrm (&ir)) |
| 4668 | return -1; |
| 4669 | ir.reg |= rex_r; |
| 4670 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4671 | ir.reg &= 0x3; |
| 4672 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4673 | break; |
| 4674 | |
| 4675 | case 0x8c: /* mov seg */ |
| 4676 | if (i386_record_modrm (&ir)) |
| 4677 | return -1; |
| 4678 | if (ir.reg > 5) |
| 4679 | { |
| 4680 | ir.addr -= 2; |
| 4681 | opcode = opcode << 8 | ir.modrm; |
| 4682 | goto no_support; |
| 4683 | } |
| 4684 | |
| 4685 | if (ir.mod == 3) |
| 4686 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4687 | else |
| 4688 | { |
| 4689 | ir.ot = OT_WORD; |
| 4690 | if (i386_record_lea_modrm (&ir)) |
| 4691 | return -1; |
| 4692 | } |
| 4693 | break; |
| 4694 | |
| 4695 | case 0x8e: /* mov seg */ |
| 4696 | if (i386_record_modrm (&ir)) |
| 4697 | return -1; |
| 4698 | switch (ir.reg) |
| 4699 | { |
| 4700 | case 0: |
| 4701 | regnum = X86_RECORD_ES_REGNUM; |
| 4702 | break; |
| 4703 | case 2: |
| 4704 | regnum = X86_RECORD_SS_REGNUM; |
| 4705 | break; |
| 4706 | case 3: |
| 4707 | regnum = X86_RECORD_DS_REGNUM; |
| 4708 | break; |
| 4709 | case 4: |
| 4710 | regnum = X86_RECORD_FS_REGNUM; |
| 4711 | break; |
| 4712 | case 5: |
| 4713 | regnum = X86_RECORD_GS_REGNUM; |
| 4714 | break; |
| 4715 | default: |
| 4716 | ir.addr -= 2; |
| 4717 | opcode = opcode << 8 | ir.modrm; |
| 4718 | goto no_support; |
| 4719 | break; |
| 4720 | } |
| 4721 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
| 4722 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4723 | break; |
| 4724 | |
| 4725 | case 0x0fb6: /* movzbS */ |
| 4726 | case 0x0fb7: /* movzwS */ |
| 4727 | case 0x0fbe: /* movsbS */ |
| 4728 | case 0x0fbf: /* movswS */ |
| 4729 | if (i386_record_modrm (&ir)) |
| 4730 | return -1; |
| 4731 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
| 4732 | break; |
| 4733 | |
| 4734 | case 0x8d: /* lea */ |
| 4735 | if (i386_record_modrm (&ir)) |
| 4736 | return -1; |
| 4737 | if (ir.mod == 3) |
| 4738 | { |
| 4739 | ir.addr -= 2; |
| 4740 | opcode = opcode << 8 | ir.modrm; |
| 4741 | goto no_support; |
| 4742 | } |
| 4743 | ir.ot = ir.dflag; |
| 4744 | ir.reg |= rex_r; |
| 4745 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4746 | ir.reg &= 0x3; |
| 4747 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4748 | break; |
| 4749 | |
| 4750 | case 0xa0: /* mov EAX */ |
| 4751 | case 0xa1: |
| 4752 | |
| 4753 | case 0xd7: /* xlat */ |
| 4754 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4755 | break; |
| 4756 | |
| 4757 | case 0xa2: /* mov EAX */ |
| 4758 | case 0xa3: |
| 4759 | if (ir.override >= 0) |
| 4760 | { |
| 4761 | if (record_memory_query) |
| 4762 | { |
| 4763 | int q; |
| 4764 | |
| 4765 | target_terminal_ours (); |
| 4766 | q = yquery (_("\ |
| 4767 | Process record ignores the memory change of instruction at address %s\n\ |
| 4768 | because it can't get the value of the segment register.\n\ |
| 4769 | Do you want to stop the program?"), |
| 4770 | paddress (gdbarch, ir.orig_addr)); |
| 4771 | target_terminal_inferior (); |
| 4772 | if (q) |
| 4773 | return -1; |
| 4774 | } |
| 4775 | } |
| 4776 | else |
| 4777 | { |
| 4778 | if ((opcode & 1) == 0) |
| 4779 | ir.ot = OT_BYTE; |
| 4780 | else |
| 4781 | ir.ot = ir.dflag + OT_WORD; |
| 4782 | if (ir.aflag == 2) |
| 4783 | { |
| 4784 | if (target_read_memory (ir.addr, buf, 8)) |
| 4785 | { |
| 4786 | if (record_debug) |
| 4787 | printf_unfiltered (_("Process record: error reading " |
| 4788 | "memory at addr 0x%s len = 8.\n"), |
| 4789 | paddress (gdbarch, ir.addr)); |
| 4790 | return -1; |
| 4791 | } |
| 4792 | ir.addr += 8; |
| 4793 | addr = extract_unsigned_integer (buf, 8, byte_order); |
| 4794 | } |
| 4795 | else if (ir.aflag) |
| 4796 | { |
| 4797 | if (target_read_memory (ir.addr, buf, 4)) |
| 4798 | { |
| 4799 | if (record_debug) |
| 4800 | printf_unfiltered (_("Process record: error reading " |
| 4801 | "memory at addr 0x%s len = 4.\n"), |
| 4802 | paddress (gdbarch, ir.addr)); |
| 4803 | return -1; |
| 4804 | } |
| 4805 | ir.addr += 4; |
| 4806 | addr = extract_unsigned_integer (buf, 4, byte_order); |
| 4807 | } |
| 4808 | else |
| 4809 | { |
| 4810 | if (target_read_memory (ir.addr, buf, 2)) |
| 4811 | { |
| 4812 | if (record_debug) |
| 4813 | printf_unfiltered (_("Process record: error reading " |
| 4814 | "memory at addr 0x%s len = 2.\n"), |
| 4815 | paddress (gdbarch, ir.addr)); |
| 4816 | return -1; |
| 4817 | } |
| 4818 | ir.addr += 2; |
| 4819 | addr = extract_unsigned_integer (buf, 2, byte_order); |
| 4820 | } |
| 4821 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
| 4822 | return -1; |
| 4823 | } |
| 4824 | break; |
| 4825 | |
| 4826 | case 0xb0: /* mov R, Ib */ |
| 4827 | case 0xb1: |
| 4828 | case 0xb2: |
| 4829 | case 0xb3: |
| 4830 | case 0xb4: |
| 4831 | case 0xb5: |
| 4832 | case 0xb6: |
| 4833 | case 0xb7: |
| 4834 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4835 | ? ((opcode & 0x7) | ir.rex_b) |
| 4836 | : ((opcode & 0x7) & 0x3)); |
| 4837 | break; |
| 4838 | |
| 4839 | case 0xb8: /* mov R, Iv */ |
| 4840 | case 0xb9: |
| 4841 | case 0xba: |
| 4842 | case 0xbb: |
| 4843 | case 0xbc: |
| 4844 | case 0xbd: |
| 4845 | case 0xbe: |
| 4846 | case 0xbf: |
| 4847 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
| 4848 | break; |
| 4849 | |
| 4850 | case 0x91: /* xchg R, EAX */ |
| 4851 | case 0x92: |
| 4852 | case 0x93: |
| 4853 | case 0x94: |
| 4854 | case 0x95: |
| 4855 | case 0x96: |
| 4856 | case 0x97: |
| 4857 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 4858 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); |
| 4859 | break; |
| 4860 | |
| 4861 | case 0x86: /* xchg Ev, Gv */ |
| 4862 | case 0x87: |
| 4863 | if ((opcode & 1) == 0) |
| 4864 | ir.ot = OT_BYTE; |
| 4865 | else |
| 4866 | ir.ot = ir.dflag + OT_WORD; |
| 4867 | if (i386_record_modrm (&ir)) |
| 4868 | return -1; |
| 4869 | if (ir.mod == 3) |
| 4870 | { |
| 4871 | ir.rm |= ir.rex_b; |
| 4872 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4873 | ir.rm &= 0x3; |
| 4874 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4875 | } |
| 4876 | else |
| 4877 | { |
| 4878 | if (i386_record_lea_modrm (&ir)) |
| 4879 | return -1; |
| 4880 | } |
| 4881 | ir.reg |= rex_r; |
| 4882 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4883 | ir.reg &= 0x3; |
| 4884 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 4885 | break; |
| 4886 | |
| 4887 | case 0xc4: /* les Gv */ |
| 4888 | case 0xc5: /* lds Gv */ |
| 4889 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4890 | { |
| 4891 | ir.addr -= 1; |
| 4892 | goto no_support; |
| 4893 | } |
| 4894 | /* FALLTHROUGH */ |
| 4895 | case 0x0fb2: /* lss Gv */ |
| 4896 | case 0x0fb4: /* lfs Gv */ |
| 4897 | case 0x0fb5: /* lgs Gv */ |
| 4898 | if (i386_record_modrm (&ir)) |
| 4899 | return -1; |
| 4900 | if (ir.mod == 3) |
| 4901 | { |
| 4902 | if (opcode > 0xff) |
| 4903 | ir.addr -= 3; |
| 4904 | else |
| 4905 | ir.addr -= 2; |
| 4906 | opcode = opcode << 8 | ir.modrm; |
| 4907 | goto no_support; |
| 4908 | } |
| 4909 | switch (opcode) |
| 4910 | { |
| 4911 | case 0xc4: /* les Gv */ |
| 4912 | regnum = X86_RECORD_ES_REGNUM; |
| 4913 | break; |
| 4914 | case 0xc5: /* lds Gv */ |
| 4915 | regnum = X86_RECORD_DS_REGNUM; |
| 4916 | break; |
| 4917 | case 0x0fb2: /* lss Gv */ |
| 4918 | regnum = X86_RECORD_SS_REGNUM; |
| 4919 | break; |
| 4920 | case 0x0fb4: /* lfs Gv */ |
| 4921 | regnum = X86_RECORD_FS_REGNUM; |
| 4922 | break; |
| 4923 | case 0x0fb5: /* lgs Gv */ |
| 4924 | regnum = X86_RECORD_GS_REGNUM; |
| 4925 | break; |
| 4926 | } |
| 4927 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
| 4928 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
| 4929 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4930 | break; |
| 4931 | |
| 4932 | case 0xc0: /* shifts */ |
| 4933 | case 0xc1: |
| 4934 | case 0xd0: |
| 4935 | case 0xd1: |
| 4936 | case 0xd2: |
| 4937 | case 0xd3: |
| 4938 | if ((opcode & 1) == 0) |
| 4939 | ir.ot = OT_BYTE; |
| 4940 | else |
| 4941 | ir.ot = ir.dflag + OT_WORD; |
| 4942 | if (i386_record_modrm (&ir)) |
| 4943 | return -1; |
| 4944 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
| 4945 | { |
| 4946 | if (i386_record_lea_modrm (&ir)) |
| 4947 | return -1; |
| 4948 | } |
| 4949 | else |
| 4950 | { |
| 4951 | ir.rm |= ir.rex_b; |
| 4952 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
| 4953 | ir.rm &= 0x3; |
| 4954 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
| 4955 | } |
| 4956 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 4957 | break; |
| 4958 | |
| 4959 | case 0x0fa4: |
| 4960 | case 0x0fa5: |
| 4961 | case 0x0fac: |
| 4962 | case 0x0fad: |
| 4963 | if (i386_record_modrm (&ir)) |
| 4964 | return -1; |
| 4965 | if (ir.mod == 3) |
| 4966 | { |
| 4967 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) |
| 4968 | return -1; |
| 4969 | } |
| 4970 | else |
| 4971 | { |
| 4972 | if (i386_record_lea_modrm (&ir)) |
| 4973 | return -1; |
| 4974 | } |
| 4975 | break; |
| 4976 | |
| 4977 | case 0xd8: /* Floats. */ |
| 4978 | case 0xd9: |
| 4979 | case 0xda: |
| 4980 | case 0xdb: |
| 4981 | case 0xdc: |
| 4982 | case 0xdd: |
| 4983 | case 0xde: |
| 4984 | case 0xdf: |
| 4985 | if (i386_record_modrm (&ir)) |
| 4986 | return -1; |
| 4987 | ir.reg |= ((opcode & 7) << 3); |
| 4988 | if (ir.mod != 3) |
| 4989 | { |
| 4990 | /* Memory. */ |
| 4991 | uint64_t addr64; |
| 4992 | |
| 4993 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
| 4994 | return -1; |
| 4995 | switch (ir.reg) |
| 4996 | { |
| 4997 | case 0x02: |
| 4998 | case 0x12: |
| 4999 | case 0x22: |
| 5000 | case 0x32: |
| 5001 | /* For fcom, ficom nothing to do. */ |
| 5002 | break; |
| 5003 | case 0x03: |
| 5004 | case 0x13: |
| 5005 | case 0x23: |
| 5006 | case 0x33: |
| 5007 | /* For fcomp, ficomp pop FPU stack, store all. */ |
| 5008 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 5009 | return -1; |
| 5010 | break; |
| 5011 | case 0x00: |
| 5012 | case 0x01: |
| 5013 | case 0x04: |
| 5014 | case 0x05: |
| 5015 | case 0x06: |
| 5016 | case 0x07: |
| 5017 | case 0x10: |
| 5018 | case 0x11: |
| 5019 | case 0x14: |
| 5020 | case 0x15: |
| 5021 | case 0x16: |
| 5022 | case 0x17: |
| 5023 | case 0x20: |
| 5024 | case 0x21: |
| 5025 | case 0x24: |
| 5026 | case 0x25: |
| 5027 | case 0x26: |
| 5028 | case 0x27: |
| 5029 | case 0x30: |
| 5030 | case 0x31: |
| 5031 | case 0x34: |
| 5032 | case 0x35: |
| 5033 | case 0x36: |
| 5034 | case 0x37: |
| 5035 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
| 5036 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension |
| 5037 | of code, always affects st(0) register. */ |
| 5038 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) |
| 5039 | return -1; |
| 5040 | break; |
| 5041 | case 0x08: |
| 5042 | case 0x0a: |
| 5043 | case 0x0b: |
| 5044 | case 0x18: |
| 5045 | case 0x19: |
| 5046 | case 0x1a: |
| 5047 | case 0x1b: |
| 5048 | case 0x1d: |
| 5049 | case 0x28: |
| 5050 | case 0x29: |
| 5051 | case 0x2a: |
| 5052 | case 0x2b: |
| 5053 | case 0x38: |
| 5054 | case 0x39: |
| 5055 | case 0x3a: |
| 5056 | case 0x3b: |
| 5057 | case 0x3c: |
| 5058 | case 0x3d: |
| 5059 | switch (ir.reg & 7) |
| 5060 | { |
| 5061 | case 0: |
| 5062 | /* Handling fld, fild. */ |
| 5063 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 5064 | return -1; |
| 5065 | break; |
| 5066 | case 1: |
| 5067 | switch (ir.reg >> 4) |
| 5068 | { |
| 5069 | case 0: |
| 5070 | if (record_arch_list_add_mem (addr64, 4)) |
| 5071 | return -1; |
| 5072 | break; |
| 5073 | case 2: |
| 5074 | if (record_arch_list_add_mem (addr64, 8)) |
| 5075 | return -1; |
| 5076 | break; |
| 5077 | case 3: |
| 5078 | break; |
| 5079 | default: |
| 5080 | if (record_arch_list_add_mem (addr64, 2)) |
| 5081 | return -1; |
| 5082 | break; |
| 5083 | } |
| 5084 | break; |
| 5085 | default: |
| 5086 | switch (ir.reg >> 4) |
| 5087 | { |
| 5088 | case 0: |
| 5089 | if (record_arch_list_add_mem (addr64, 4)) |
| 5090 | return -1; |
| 5091 | if (3 == (ir.reg & 7)) |
| 5092 | { |
| 5093 | /* For fstp m32fp. */ |
| 5094 | if (i386_record_floats (gdbarch, &ir, |
| 5095 | I386_SAVE_FPU_REGS)) |
| 5096 | return -1; |
| 5097 | } |
| 5098 | break; |
| 5099 | case 1: |
| 5100 | if (record_arch_list_add_mem (addr64, 4)) |
| 5101 | return -1; |
| 5102 | if ((3 == (ir.reg & 7)) |
| 5103 | || (5 == (ir.reg & 7)) |
| 5104 | || (7 == (ir.reg & 7))) |
| 5105 | { |
| 5106 | /* For fstp insn. */ |
| 5107 | if (i386_record_floats (gdbarch, &ir, |
| 5108 | I386_SAVE_FPU_REGS)) |
| 5109 | return -1; |
| 5110 | } |
| 5111 | break; |
| 5112 | case 2: |
| 5113 | if (record_arch_list_add_mem (addr64, 8)) |
| 5114 | return -1; |
| 5115 | if (3 == (ir.reg & 7)) |
| 5116 | { |
| 5117 | /* For fstp m64fp. */ |
| 5118 | if (i386_record_floats (gdbarch, &ir, |
| 5119 | I386_SAVE_FPU_REGS)) |
| 5120 | return -1; |
| 5121 | } |
| 5122 | break; |
| 5123 | case 3: |
| 5124 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
| 5125 | { |
| 5126 | /* For fistp, fbld, fild, fbstp. */ |
| 5127 | if (i386_record_floats (gdbarch, &ir, |
| 5128 | I386_SAVE_FPU_REGS)) |
| 5129 | return -1; |
| 5130 | } |
| 5131 | /* Fall through */ |
| 5132 | default: |
| 5133 | if (record_arch_list_add_mem (addr64, 2)) |
| 5134 | return -1; |
| 5135 | break; |
| 5136 | } |
| 5137 | break; |
| 5138 | } |
| 5139 | break; |
| 5140 | case 0x0c: |
| 5141 | /* Insn fldenv. */ |
| 5142 | if (i386_record_floats (gdbarch, &ir, |
| 5143 | I386_SAVE_FPU_ENV_REG_STACK)) |
| 5144 | return -1; |
| 5145 | break; |
| 5146 | case 0x0d: |
| 5147 | /* Insn fldcw. */ |
| 5148 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) |
| 5149 | return -1; |
| 5150 | break; |
| 5151 | case 0x2c: |
| 5152 | /* Insn frstor. */ |
| 5153 | if (i386_record_floats (gdbarch, &ir, |
| 5154 | I386_SAVE_FPU_ENV_REG_STACK)) |
| 5155 | return -1; |
| 5156 | break; |
| 5157 | case 0x0e: |
| 5158 | if (ir.dflag) |
| 5159 | { |
| 5160 | if (record_arch_list_add_mem (addr64, 28)) |
| 5161 | return -1; |
| 5162 | } |
| 5163 | else |
| 5164 | { |
| 5165 | if (record_arch_list_add_mem (addr64, 14)) |
| 5166 | return -1; |
| 5167 | } |
| 5168 | break; |
| 5169 | case 0x0f: |
| 5170 | case 0x2f: |
| 5171 | if (record_arch_list_add_mem (addr64, 2)) |
| 5172 | return -1; |
| 5173 | /* Insn fstp, fbstp. */ |
| 5174 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 5175 | return -1; |
| 5176 | break; |
| 5177 | case 0x1f: |
| 5178 | case 0x3e: |
| 5179 | if (record_arch_list_add_mem (addr64, 10)) |
| 5180 | return -1; |
| 5181 | break; |
| 5182 | case 0x2e: |
| 5183 | if (ir.dflag) |
| 5184 | { |
| 5185 | if (record_arch_list_add_mem (addr64, 28)) |
| 5186 | return -1; |
| 5187 | addr64 += 28; |
| 5188 | } |
| 5189 | else |
| 5190 | { |
| 5191 | if (record_arch_list_add_mem (addr64, 14)) |
| 5192 | return -1; |
| 5193 | addr64 += 14; |
| 5194 | } |
| 5195 | if (record_arch_list_add_mem (addr64, 80)) |
| 5196 | return -1; |
| 5197 | /* Insn fsave. */ |
| 5198 | if (i386_record_floats (gdbarch, &ir, |
| 5199 | I386_SAVE_FPU_ENV_REG_STACK)) |
| 5200 | return -1; |
| 5201 | break; |
| 5202 | case 0x3f: |
| 5203 | if (record_arch_list_add_mem (addr64, 8)) |
| 5204 | return -1; |
| 5205 | /* Insn fistp. */ |
| 5206 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 5207 | return -1; |
| 5208 | break; |
| 5209 | default: |
| 5210 | ir.addr -= 2; |
| 5211 | opcode = opcode << 8 | ir.modrm; |
| 5212 | goto no_support; |
| 5213 | break; |
| 5214 | } |
| 5215 | } |
| 5216 | /* Opcode is an extension of modR/M byte. */ |
| 5217 | else |
| 5218 | { |
| 5219 | switch (opcode) |
| 5220 | { |
| 5221 | case 0xd8: |
| 5222 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) |
| 5223 | return -1; |
| 5224 | break; |
| 5225 | case 0xd9: |
| 5226 | if (0x0c == (ir.modrm >> 4)) |
| 5227 | { |
| 5228 | if ((ir.modrm & 0x0f) <= 7) |
| 5229 | { |
| 5230 | if (i386_record_floats (gdbarch, &ir, |
| 5231 | I386_SAVE_FPU_REGS)) |
| 5232 | return -1; |
| 5233 | } |
| 5234 | else |
| 5235 | { |
| 5236 | if (i386_record_floats (gdbarch, &ir, |
| 5237 | I387_ST0_REGNUM (tdep))) |
| 5238 | return -1; |
| 5239 | /* If only st(0) is changing, then we have already |
| 5240 | recorded. */ |
| 5241 | if ((ir.modrm & 0x0f) - 0x08) |
| 5242 | { |
| 5243 | if (i386_record_floats (gdbarch, &ir, |
| 5244 | I387_ST0_REGNUM (tdep) + |
| 5245 | ((ir.modrm & 0x0f) - 0x08))) |
| 5246 | return -1; |
| 5247 | } |
| 5248 | } |
| 5249 | } |
| 5250 | else |
| 5251 | { |
| 5252 | switch (ir.modrm) |
| 5253 | { |
| 5254 | case 0xe0: |
| 5255 | case 0xe1: |
| 5256 | case 0xf0: |
| 5257 | case 0xf5: |
| 5258 | case 0xf8: |
| 5259 | case 0xfa: |
| 5260 | case 0xfc: |
| 5261 | case 0xfe: |
| 5262 | case 0xff: |
| 5263 | if (i386_record_floats (gdbarch, &ir, |
| 5264 | I387_ST0_REGNUM (tdep))) |
| 5265 | return -1; |
| 5266 | break; |
| 5267 | case 0xf1: |
| 5268 | case 0xf2: |
| 5269 | case 0xf3: |
| 5270 | case 0xf4: |
| 5271 | case 0xf6: |
| 5272 | case 0xf7: |
| 5273 | case 0xe8: |
| 5274 | case 0xe9: |
| 5275 | case 0xea: |
| 5276 | case 0xeb: |
| 5277 | case 0xec: |
| 5278 | case 0xed: |
| 5279 | case 0xee: |
| 5280 | case 0xf9: |
| 5281 | case 0xfb: |
| 5282 | if (i386_record_floats (gdbarch, &ir, |
| 5283 | I386_SAVE_FPU_REGS)) |
| 5284 | return -1; |
| 5285 | break; |
| 5286 | case 0xfd: |
| 5287 | if (i386_record_floats (gdbarch, &ir, |
| 5288 | I387_ST0_REGNUM (tdep))) |
| 5289 | return -1; |
| 5290 | if (i386_record_floats (gdbarch, &ir, |
| 5291 | I387_ST0_REGNUM (tdep) + 1)) |
| 5292 | return -1; |
| 5293 | break; |
| 5294 | } |
| 5295 | } |
| 5296 | break; |
| 5297 | case 0xda: |
| 5298 | if (0xe9 == ir.modrm) |
| 5299 | { |
| 5300 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 5301 | return -1; |
| 5302 | } |
| 5303 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) |
| 5304 | { |
| 5305 | if (i386_record_floats (gdbarch, &ir, |
| 5306 | I387_ST0_REGNUM (tdep))) |
| 5307 | return -1; |
| 5308 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) |
| 5309 | { |
| 5310 | if (i386_record_floats (gdbarch, &ir, |
| 5311 | I387_ST0_REGNUM (tdep) + |
| 5312 | (ir.modrm & 0x0f))) |
| 5313 | return -1; |
| 5314 | } |
| 5315 | else if ((ir.modrm & 0x0f) - 0x08) |
| 5316 | { |
| 5317 | if (i386_record_floats (gdbarch, &ir, |
| 5318 | I387_ST0_REGNUM (tdep) + |
| 5319 | ((ir.modrm & 0x0f) - 0x08))) |
| 5320 | return -1; |
| 5321 | } |
| 5322 | } |
| 5323 | break; |
| 5324 | case 0xdb: |
| 5325 | if (0xe3 == ir.modrm) |
| 5326 | { |
| 5327 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) |
| 5328 | return -1; |
| 5329 | } |
| 5330 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) |
| 5331 | { |
| 5332 | if (i386_record_floats (gdbarch, &ir, |
| 5333 | I387_ST0_REGNUM (tdep))) |
| 5334 | return -1; |
| 5335 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) |
| 5336 | { |
| 5337 | if (i386_record_floats (gdbarch, &ir, |
| 5338 | I387_ST0_REGNUM (tdep) + |
| 5339 | (ir.modrm & 0x0f))) |
| 5340 | return -1; |
| 5341 | } |
| 5342 | else if ((ir.modrm & 0x0f) - 0x08) |
| 5343 | { |
| 5344 | if (i386_record_floats (gdbarch, &ir, |
| 5345 | I387_ST0_REGNUM (tdep) + |
| 5346 | ((ir.modrm & 0x0f) - 0x08))) |
| 5347 | return -1; |
| 5348 | } |
| 5349 | } |
| 5350 | break; |
| 5351 | case 0xdc: |
| 5352 | if ((0x0c == ir.modrm >> 4) |
| 5353 | || (0x0d == ir.modrm >> 4) |
| 5354 | || (0x0f == ir.modrm >> 4)) |
| 5355 | { |
| 5356 | if ((ir.modrm & 0x0f) <= 7) |
| 5357 | { |
| 5358 | if (i386_record_floats (gdbarch, &ir, |
| 5359 | I387_ST0_REGNUM (tdep) + |
| 5360 | (ir.modrm & 0x0f))) |
| 5361 | return -1; |
| 5362 | } |
| 5363 | else |
| 5364 | { |
| 5365 | if (i386_record_floats (gdbarch, &ir, |
| 5366 | I387_ST0_REGNUM (tdep) + |
| 5367 | ((ir.modrm & 0x0f) - 0x08))) |
| 5368 | return -1; |
| 5369 | } |
| 5370 | } |
| 5371 | break; |
| 5372 | case 0xdd: |
| 5373 | if (0x0c == ir.modrm >> 4) |
| 5374 | { |
| 5375 | if (i386_record_floats (gdbarch, &ir, |
| 5376 | I387_FTAG_REGNUM (tdep))) |
| 5377 | return -1; |
| 5378 | } |
| 5379 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) |
| 5380 | { |
| 5381 | if ((ir.modrm & 0x0f) <= 7) |
| 5382 | { |
| 5383 | if (i386_record_floats (gdbarch, &ir, |
| 5384 | I387_ST0_REGNUM (tdep) + |
| 5385 | (ir.modrm & 0x0f))) |
| 5386 | return -1; |
| 5387 | } |
| 5388 | else |
| 5389 | { |
| 5390 | if (i386_record_floats (gdbarch, &ir, |
| 5391 | I386_SAVE_FPU_REGS)) |
| 5392 | return -1; |
| 5393 | } |
| 5394 | } |
| 5395 | break; |
| 5396 | case 0xde: |
| 5397 | if ((0x0c == ir.modrm >> 4) |
| 5398 | || (0x0e == ir.modrm >> 4) |
| 5399 | || (0x0f == ir.modrm >> 4) |
| 5400 | || (0xd9 == ir.modrm)) |
| 5401 | { |
| 5402 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 5403 | return -1; |
| 5404 | } |
| 5405 | break; |
| 5406 | case 0xdf: |
| 5407 | if (0xe0 == ir.modrm) |
| 5408 | { |
| 5409 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) |
| 5410 | return -1; |
| 5411 | } |
| 5412 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) |
| 5413 | { |
| 5414 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
| 5415 | return -1; |
| 5416 | } |
| 5417 | break; |
| 5418 | } |
| 5419 | } |
| 5420 | break; |
| 5421 | /* string ops */ |
| 5422 | case 0xa4: /* movsS */ |
| 5423 | case 0xa5: |
| 5424 | case 0xaa: /* stosS */ |
| 5425 | case 0xab: |
| 5426 | case 0x6c: /* insS */ |
| 5427 | case 0x6d: |
| 5428 | regcache_raw_read_unsigned (ir.regcache, |
| 5429 | ir.regmap[X86_RECORD_RECX_REGNUM], |
| 5430 | &addr); |
| 5431 | if (addr) |
| 5432 | { |
| 5433 | ULONGEST es, ds; |
| 5434 | |
| 5435 | if ((opcode & 1) == 0) |
| 5436 | ir.ot = OT_BYTE; |
| 5437 | else |
| 5438 | ir.ot = ir.dflag + OT_WORD; |
| 5439 | regcache_raw_read_unsigned (ir.regcache, |
| 5440 | ir.regmap[X86_RECORD_REDI_REGNUM], |
| 5441 | &addr); |
| 5442 | |
| 5443 | regcache_raw_read_unsigned (ir.regcache, |
| 5444 | ir.regmap[X86_RECORD_ES_REGNUM], |
| 5445 | &es); |
| 5446 | regcache_raw_read_unsigned (ir.regcache, |
| 5447 | ir.regmap[X86_RECORD_DS_REGNUM], |
| 5448 | &ds); |
| 5449 | if (ir.aflag && (es != ds)) |
| 5450 | { |
| 5451 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ |
| 5452 | if (record_memory_query) |
| 5453 | { |
| 5454 | int q; |
| 5455 | |
| 5456 | target_terminal_ours (); |
| 5457 | q = yquery (_("\ |
| 5458 | Process record ignores the memory change of instruction at address %s\n\ |
| 5459 | because it can't get the value of the segment register.\n\ |
| 5460 | Do you want to stop the program?"), |
| 5461 | paddress (gdbarch, ir.orig_addr)); |
| 5462 | target_terminal_inferior (); |
| 5463 | if (q) |
| 5464 | return -1; |
| 5465 | } |
| 5466 | } |
| 5467 | else |
| 5468 | { |
| 5469 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
| 5470 | return -1; |
| 5471 | } |
| 5472 | |
| 5473 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 5474 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 5475 | if (opcode == 0xa4 || opcode == 0xa5) |
| 5476 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
| 5477 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
| 5478 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5479 | } |
| 5480 | break; |
| 5481 | |
| 5482 | case 0xa6: /* cmpsS */ |
| 5483 | case 0xa7: |
| 5484 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
| 5485 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
| 5486 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 5487 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 5488 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5489 | break; |
| 5490 | |
| 5491 | case 0xac: /* lodsS */ |
| 5492 | case 0xad: |
| 5493 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5494 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
| 5495 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 5496 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 5497 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5498 | break; |
| 5499 | |
| 5500 | case 0xae: /* scasS */ |
| 5501 | case 0xaf: |
| 5502 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
| 5503 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 5504 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 5505 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5506 | break; |
| 5507 | |
| 5508 | case 0x6e: /* outsS */ |
| 5509 | case 0x6f: |
| 5510 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
| 5511 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
| 5512 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 5513 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5514 | break; |
| 5515 | |
| 5516 | case 0xe4: /* port I/O */ |
| 5517 | case 0xe5: |
| 5518 | case 0xec: |
| 5519 | case 0xed: |
| 5520 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5521 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5522 | break; |
| 5523 | |
| 5524 | case 0xe6: |
| 5525 | case 0xe7: |
| 5526 | case 0xee: |
| 5527 | case 0xef: |
| 5528 | break; |
| 5529 | |
| 5530 | /* control */ |
| 5531 | case 0xc2: /* ret im */ |
| 5532 | case 0xc3: /* ret */ |
| 5533 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 5534 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5535 | break; |
| 5536 | |
| 5537 | case 0xca: /* lret im */ |
| 5538 | case 0xcb: /* lret */ |
| 5539 | case 0xcf: /* iret */ |
| 5540 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
| 5541 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 5542 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5543 | break; |
| 5544 | |
| 5545 | case 0xe8: /* call im */ |
| 5546 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 5547 | ir.dflag = 2; |
| 5548 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 5549 | return -1; |
| 5550 | break; |
| 5551 | |
| 5552 | case 0x9a: /* lcall im */ |
| 5553 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5554 | { |
| 5555 | ir.addr -= 1; |
| 5556 | goto no_support; |
| 5557 | } |
| 5558 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
| 5559 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 5560 | return -1; |
| 5561 | break; |
| 5562 | |
| 5563 | case 0xe9: /* jmp im */ |
| 5564 | case 0xea: /* ljmp im */ |
| 5565 | case 0xeb: /* jmp Jb */ |
| 5566 | case 0x70: /* jcc Jb */ |
| 5567 | case 0x71: |
| 5568 | case 0x72: |
| 5569 | case 0x73: |
| 5570 | case 0x74: |
| 5571 | case 0x75: |
| 5572 | case 0x76: |
| 5573 | case 0x77: |
| 5574 | case 0x78: |
| 5575 | case 0x79: |
| 5576 | case 0x7a: |
| 5577 | case 0x7b: |
| 5578 | case 0x7c: |
| 5579 | case 0x7d: |
| 5580 | case 0x7e: |
| 5581 | case 0x7f: |
| 5582 | case 0x0f80: /* jcc Jv */ |
| 5583 | case 0x0f81: |
| 5584 | case 0x0f82: |
| 5585 | case 0x0f83: |
| 5586 | case 0x0f84: |
| 5587 | case 0x0f85: |
| 5588 | case 0x0f86: |
| 5589 | case 0x0f87: |
| 5590 | case 0x0f88: |
| 5591 | case 0x0f89: |
| 5592 | case 0x0f8a: |
| 5593 | case 0x0f8b: |
| 5594 | case 0x0f8c: |
| 5595 | case 0x0f8d: |
| 5596 | case 0x0f8e: |
| 5597 | case 0x0f8f: |
| 5598 | break; |
| 5599 | |
| 5600 | case 0x0f90: /* setcc Gv */ |
| 5601 | case 0x0f91: |
| 5602 | case 0x0f92: |
| 5603 | case 0x0f93: |
| 5604 | case 0x0f94: |
| 5605 | case 0x0f95: |
| 5606 | case 0x0f96: |
| 5607 | case 0x0f97: |
| 5608 | case 0x0f98: |
| 5609 | case 0x0f99: |
| 5610 | case 0x0f9a: |
| 5611 | case 0x0f9b: |
| 5612 | case 0x0f9c: |
| 5613 | case 0x0f9d: |
| 5614 | case 0x0f9e: |
| 5615 | case 0x0f9f: |
| 5616 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5617 | ir.ot = OT_BYTE; |
| 5618 | if (i386_record_modrm (&ir)) |
| 5619 | return -1; |
| 5620 | if (ir.mod == 3) |
| 5621 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
| 5622 | : (ir.rm & 0x3)); |
| 5623 | else |
| 5624 | { |
| 5625 | if (i386_record_lea_modrm (&ir)) |
| 5626 | return -1; |
| 5627 | } |
| 5628 | break; |
| 5629 | |
| 5630 | case 0x0f40: /* cmov Gv, Ev */ |
| 5631 | case 0x0f41: |
| 5632 | case 0x0f42: |
| 5633 | case 0x0f43: |
| 5634 | case 0x0f44: |
| 5635 | case 0x0f45: |
| 5636 | case 0x0f46: |
| 5637 | case 0x0f47: |
| 5638 | case 0x0f48: |
| 5639 | case 0x0f49: |
| 5640 | case 0x0f4a: |
| 5641 | case 0x0f4b: |
| 5642 | case 0x0f4c: |
| 5643 | case 0x0f4d: |
| 5644 | case 0x0f4e: |
| 5645 | case 0x0f4f: |
| 5646 | if (i386_record_modrm (&ir)) |
| 5647 | return -1; |
| 5648 | ir.reg |= rex_r; |
| 5649 | if (ir.dflag == OT_BYTE) |
| 5650 | ir.reg &= 0x3; |
| 5651 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 5652 | break; |
| 5653 | |
| 5654 | /* flags */ |
| 5655 | case 0x9c: /* pushf */ |
| 5656 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5657 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
| 5658 | ir.dflag = 2; |
| 5659 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
| 5660 | return -1; |
| 5661 | break; |
| 5662 | |
| 5663 | case 0x9d: /* popf */ |
| 5664 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 5665 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5666 | break; |
| 5667 | |
| 5668 | case 0x9e: /* sahf */ |
| 5669 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5670 | { |
| 5671 | ir.addr -= 1; |
| 5672 | goto no_support; |
| 5673 | } |
| 5674 | /* FALLTHROUGH */ |
| 5675 | case 0xf5: /* cmc */ |
| 5676 | case 0xf8: /* clc */ |
| 5677 | case 0xf9: /* stc */ |
| 5678 | case 0xfc: /* cld */ |
| 5679 | case 0xfd: /* std */ |
| 5680 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5681 | break; |
| 5682 | |
| 5683 | case 0x9f: /* lahf */ |
| 5684 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5685 | { |
| 5686 | ir.addr -= 1; |
| 5687 | goto no_support; |
| 5688 | } |
| 5689 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5690 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5691 | break; |
| 5692 | |
| 5693 | /* bit operations */ |
| 5694 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
| 5695 | ir.ot = ir.dflag + OT_WORD; |
| 5696 | if (i386_record_modrm (&ir)) |
| 5697 | return -1; |
| 5698 | if (ir.reg < 4) |
| 5699 | { |
| 5700 | ir.addr -= 2; |
| 5701 | opcode = opcode << 8 | ir.modrm; |
| 5702 | goto no_support; |
| 5703 | } |
| 5704 | if (ir.reg != 4) |
| 5705 | { |
| 5706 | if (ir.mod == 3) |
| 5707 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 5708 | else |
| 5709 | { |
| 5710 | if (i386_record_lea_modrm (&ir)) |
| 5711 | return -1; |
| 5712 | } |
| 5713 | } |
| 5714 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5715 | break; |
| 5716 | |
| 5717 | case 0x0fa3: /* bt Gv, Ev */ |
| 5718 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5719 | break; |
| 5720 | |
| 5721 | case 0x0fab: /* bts */ |
| 5722 | case 0x0fb3: /* btr */ |
| 5723 | case 0x0fbb: /* btc */ |
| 5724 | ir.ot = ir.dflag + OT_WORD; |
| 5725 | if (i386_record_modrm (&ir)) |
| 5726 | return -1; |
| 5727 | if (ir.mod == 3) |
| 5728 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 5729 | else |
| 5730 | { |
| 5731 | uint64_t addr64; |
| 5732 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
| 5733 | return -1; |
| 5734 | regcache_raw_read_unsigned (ir.regcache, |
| 5735 | ir.regmap[ir.reg | rex_r], |
| 5736 | &addr); |
| 5737 | switch (ir.dflag) |
| 5738 | { |
| 5739 | case 0: |
| 5740 | addr64 += ((int16_t) addr >> 4) << 4; |
| 5741 | break; |
| 5742 | case 1: |
| 5743 | addr64 += ((int32_t) addr >> 5) << 5; |
| 5744 | break; |
| 5745 | case 2: |
| 5746 | addr64 += ((int64_t) addr >> 6) << 6; |
| 5747 | break; |
| 5748 | } |
| 5749 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
| 5750 | return -1; |
| 5751 | if (i386_record_lea_modrm (&ir)) |
| 5752 | return -1; |
| 5753 | } |
| 5754 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5755 | break; |
| 5756 | |
| 5757 | case 0x0fbc: /* bsf */ |
| 5758 | case 0x0fbd: /* bsr */ |
| 5759 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
| 5760 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5761 | break; |
| 5762 | |
| 5763 | /* bcd */ |
| 5764 | case 0x27: /* daa */ |
| 5765 | case 0x2f: /* das */ |
| 5766 | case 0x37: /* aaa */ |
| 5767 | case 0x3f: /* aas */ |
| 5768 | case 0xd4: /* aam */ |
| 5769 | case 0xd5: /* aad */ |
| 5770 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5771 | { |
| 5772 | ir.addr -= 1; |
| 5773 | goto no_support; |
| 5774 | } |
| 5775 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5776 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5777 | break; |
| 5778 | |
| 5779 | /* misc */ |
| 5780 | case 0x90: /* nop */ |
| 5781 | if (prefixes & PREFIX_LOCK) |
| 5782 | { |
| 5783 | ir.addr -= 1; |
| 5784 | goto no_support; |
| 5785 | } |
| 5786 | break; |
| 5787 | |
| 5788 | case 0x9b: /* fwait */ |
| 5789 | if (target_read_memory (ir.addr, &opcode8, 1)) |
| 5790 | { |
| 5791 | if (record_debug) |
| 5792 | printf_unfiltered (_("Process record: error reading memory at " |
| 5793 | "addr 0x%s len = 1.\n"), |
| 5794 | paddress (gdbarch, ir.addr)); |
| 5795 | return -1; |
| 5796 | } |
| 5797 | opcode = (uint32_t) opcode8; |
| 5798 | ir.addr++; |
| 5799 | goto reswitch; |
| 5800 | break; |
| 5801 | |
| 5802 | /* XXX */ |
| 5803 | case 0xcc: /* int3 */ |
| 5804 | printf_unfiltered (_("Process record does not support instruction " |
| 5805 | "int3.\n")); |
| 5806 | ir.addr -= 1; |
| 5807 | goto no_support; |
| 5808 | break; |
| 5809 | |
| 5810 | /* XXX */ |
| 5811 | case 0xcd: /* int */ |
| 5812 | { |
| 5813 | int ret; |
| 5814 | uint8_t interrupt; |
| 5815 | if (target_read_memory (ir.addr, &interrupt, 1)) |
| 5816 | { |
| 5817 | if (record_debug) |
| 5818 | printf_unfiltered (_("Process record: error reading memory " |
| 5819 | "at addr %s len = 1.\n"), |
| 5820 | paddress (gdbarch, ir.addr)); |
| 5821 | return -1; |
| 5822 | } |
| 5823 | ir.addr++; |
| 5824 | if (interrupt != 0x80 |
| 5825 | || tdep->i386_intx80_record == NULL) |
| 5826 | { |
| 5827 | printf_unfiltered (_("Process record does not support " |
| 5828 | "instruction int 0x%02x.\n"), |
| 5829 | interrupt); |
| 5830 | ir.addr -= 2; |
| 5831 | goto no_support; |
| 5832 | } |
| 5833 | ret = tdep->i386_intx80_record (ir.regcache); |
| 5834 | if (ret) |
| 5835 | return ret; |
| 5836 | } |
| 5837 | break; |
| 5838 | |
| 5839 | /* XXX */ |
| 5840 | case 0xce: /* into */ |
| 5841 | printf_unfiltered (_("Process record does not support " |
| 5842 | "instruction into.\n")); |
| 5843 | ir.addr -= 1; |
| 5844 | goto no_support; |
| 5845 | break; |
| 5846 | |
| 5847 | case 0xfa: /* cli */ |
| 5848 | case 0xfb: /* sti */ |
| 5849 | break; |
| 5850 | |
| 5851 | case 0x62: /* bound */ |
| 5852 | printf_unfiltered (_("Process record does not support " |
| 5853 | "instruction bound.\n")); |
| 5854 | ir.addr -= 1; |
| 5855 | goto no_support; |
| 5856 | break; |
| 5857 | |
| 5858 | case 0x0fc8: /* bswap reg */ |
| 5859 | case 0x0fc9: |
| 5860 | case 0x0fca: |
| 5861 | case 0x0fcb: |
| 5862 | case 0x0fcc: |
| 5863 | case 0x0fcd: |
| 5864 | case 0x0fce: |
| 5865 | case 0x0fcf: |
| 5866 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
| 5867 | break; |
| 5868 | |
| 5869 | case 0xd6: /* salc */ |
| 5870 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5871 | { |
| 5872 | ir.addr -= 1; |
| 5873 | goto no_support; |
| 5874 | } |
| 5875 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5876 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5877 | break; |
| 5878 | |
| 5879 | case 0xe0: /* loopnz */ |
| 5880 | case 0xe1: /* loopz */ |
| 5881 | case 0xe2: /* loop */ |
| 5882 | case 0xe3: /* jecxz */ |
| 5883 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 5884 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5885 | break; |
| 5886 | |
| 5887 | case 0x0f30: /* wrmsr */ |
| 5888 | printf_unfiltered (_("Process record does not support " |
| 5889 | "instruction wrmsr.\n")); |
| 5890 | ir.addr -= 2; |
| 5891 | goto no_support; |
| 5892 | break; |
| 5893 | |
| 5894 | case 0x0f32: /* rdmsr */ |
| 5895 | printf_unfiltered (_("Process record does not support " |
| 5896 | "instruction rdmsr.\n")); |
| 5897 | ir.addr -= 2; |
| 5898 | goto no_support; |
| 5899 | break; |
| 5900 | |
| 5901 | case 0x0f31: /* rdtsc */ |
| 5902 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5903 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 5904 | break; |
| 5905 | |
| 5906 | case 0x0f34: /* sysenter */ |
| 5907 | { |
| 5908 | int ret; |
| 5909 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 5910 | { |
| 5911 | ir.addr -= 2; |
| 5912 | goto no_support; |
| 5913 | } |
| 5914 | if (tdep->i386_sysenter_record == NULL) |
| 5915 | { |
| 5916 | printf_unfiltered (_("Process record does not support " |
| 5917 | "instruction sysenter.\n")); |
| 5918 | ir.addr -= 2; |
| 5919 | goto no_support; |
| 5920 | } |
| 5921 | ret = tdep->i386_sysenter_record (ir.regcache); |
| 5922 | if (ret) |
| 5923 | return ret; |
| 5924 | } |
| 5925 | break; |
| 5926 | |
| 5927 | case 0x0f35: /* sysexit */ |
| 5928 | printf_unfiltered (_("Process record does not support " |
| 5929 | "instruction sysexit.\n")); |
| 5930 | ir.addr -= 2; |
| 5931 | goto no_support; |
| 5932 | break; |
| 5933 | |
| 5934 | case 0x0f05: /* syscall */ |
| 5935 | { |
| 5936 | int ret; |
| 5937 | if (tdep->i386_syscall_record == NULL) |
| 5938 | { |
| 5939 | printf_unfiltered (_("Process record does not support " |
| 5940 | "instruction syscall.\n")); |
| 5941 | ir.addr -= 2; |
| 5942 | goto no_support; |
| 5943 | } |
| 5944 | ret = tdep->i386_syscall_record (ir.regcache); |
| 5945 | if (ret) |
| 5946 | return ret; |
| 5947 | } |
| 5948 | break; |
| 5949 | |
| 5950 | case 0x0f07: /* sysret */ |
| 5951 | printf_unfiltered (_("Process record does not support " |
| 5952 | "instruction sysret.\n")); |
| 5953 | ir.addr -= 2; |
| 5954 | goto no_support; |
| 5955 | break; |
| 5956 | |
| 5957 | case 0x0fa2: /* cpuid */ |
| 5958 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 5959 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 5960 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 5961 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); |
| 5962 | break; |
| 5963 | |
| 5964 | case 0xf4: /* hlt */ |
| 5965 | printf_unfiltered (_("Process record does not support " |
| 5966 | "instruction hlt.\n")); |
| 5967 | ir.addr -= 1; |
| 5968 | goto no_support; |
| 5969 | break; |
| 5970 | |
| 5971 | case 0x0f00: |
| 5972 | if (i386_record_modrm (&ir)) |
| 5973 | return -1; |
| 5974 | switch (ir.reg) |
| 5975 | { |
| 5976 | case 0: /* sldt */ |
| 5977 | case 1: /* str */ |
| 5978 | if (ir.mod == 3) |
| 5979 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 5980 | else |
| 5981 | { |
| 5982 | ir.ot = OT_WORD; |
| 5983 | if (i386_record_lea_modrm (&ir)) |
| 5984 | return -1; |
| 5985 | } |
| 5986 | break; |
| 5987 | case 2: /* lldt */ |
| 5988 | case 3: /* ltr */ |
| 5989 | break; |
| 5990 | case 4: /* verr */ |
| 5991 | case 5: /* verw */ |
| 5992 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 5993 | break; |
| 5994 | default: |
| 5995 | ir.addr -= 3; |
| 5996 | opcode = opcode << 8 | ir.modrm; |
| 5997 | goto no_support; |
| 5998 | break; |
| 5999 | } |
| 6000 | break; |
| 6001 | |
| 6002 | case 0x0f01: |
| 6003 | if (i386_record_modrm (&ir)) |
| 6004 | return -1; |
| 6005 | switch (ir.reg) |
| 6006 | { |
| 6007 | case 0: /* sgdt */ |
| 6008 | { |
| 6009 | uint64_t addr64; |
| 6010 | |
| 6011 | if (ir.mod == 3) |
| 6012 | { |
| 6013 | ir.addr -= 3; |
| 6014 | opcode = opcode << 8 | ir.modrm; |
| 6015 | goto no_support; |
| 6016 | } |
| 6017 | if (ir.override >= 0) |
| 6018 | { |
| 6019 | if (record_memory_query) |
| 6020 | { |
| 6021 | int q; |
| 6022 | |
| 6023 | target_terminal_ours (); |
| 6024 | q = yquery (_("\ |
| 6025 | Process record ignores the memory change of instruction at address %s\n\ |
| 6026 | because it can't get the value of the segment register.\n\ |
| 6027 | Do you want to stop the program?"), |
| 6028 | paddress (gdbarch, ir.orig_addr)); |
| 6029 | target_terminal_inferior (); |
| 6030 | if (q) |
| 6031 | return -1; |
| 6032 | } |
| 6033 | } |
| 6034 | else |
| 6035 | { |
| 6036 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
| 6037 | return -1; |
| 6038 | if (record_arch_list_add_mem (addr64, 2)) |
| 6039 | return -1; |
| 6040 | addr64 += 2; |
| 6041 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 6042 | { |
| 6043 | if (record_arch_list_add_mem (addr64, 8)) |
| 6044 | return -1; |
| 6045 | } |
| 6046 | else |
| 6047 | { |
| 6048 | if (record_arch_list_add_mem (addr64, 4)) |
| 6049 | return -1; |
| 6050 | } |
| 6051 | } |
| 6052 | } |
| 6053 | break; |
| 6054 | case 1: |
| 6055 | if (ir.mod == 3) |
| 6056 | { |
| 6057 | switch (ir.rm) |
| 6058 | { |
| 6059 | case 0: /* monitor */ |
| 6060 | break; |
| 6061 | case 1: /* mwait */ |
| 6062 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6063 | break; |
| 6064 | default: |
| 6065 | ir.addr -= 3; |
| 6066 | opcode = opcode << 8 | ir.modrm; |
| 6067 | goto no_support; |
| 6068 | break; |
| 6069 | } |
| 6070 | } |
| 6071 | else |
| 6072 | { |
| 6073 | /* sidt */ |
| 6074 | if (ir.override >= 0) |
| 6075 | { |
| 6076 | if (record_memory_query) |
| 6077 | { |
| 6078 | int q; |
| 6079 | |
| 6080 | target_terminal_ours (); |
| 6081 | q = yquery (_("\ |
| 6082 | Process record ignores the memory change of instruction at address %s\n\ |
| 6083 | because it can't get the value of the segment register.\n\ |
| 6084 | Do you want to stop the program?"), |
| 6085 | paddress (gdbarch, ir.orig_addr)); |
| 6086 | target_terminal_inferior (); |
| 6087 | if (q) |
| 6088 | return -1; |
| 6089 | } |
| 6090 | } |
| 6091 | else |
| 6092 | { |
| 6093 | uint64_t addr64; |
| 6094 | |
| 6095 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
| 6096 | return -1; |
| 6097 | if (record_arch_list_add_mem (addr64, 2)) |
| 6098 | return -1; |
| 6099 | addr64 += 2; |
| 6100 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
| 6101 | { |
| 6102 | if (record_arch_list_add_mem (addr64, 8)) |
| 6103 | return -1; |
| 6104 | } |
| 6105 | else |
| 6106 | { |
| 6107 | if (record_arch_list_add_mem (addr64, 4)) |
| 6108 | return -1; |
| 6109 | } |
| 6110 | } |
| 6111 | } |
| 6112 | break; |
| 6113 | case 2: /* lgdt */ |
| 6114 | if (ir.mod == 3) |
| 6115 | { |
| 6116 | /* xgetbv */ |
| 6117 | if (ir.rm == 0) |
| 6118 | { |
| 6119 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 6120 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 6121 | break; |
| 6122 | } |
| 6123 | /* xsetbv */ |
| 6124 | else if (ir.rm == 1) |
| 6125 | break; |
| 6126 | } |
| 6127 | case 3: /* lidt */ |
| 6128 | if (ir.mod == 3) |
| 6129 | { |
| 6130 | ir.addr -= 3; |
| 6131 | opcode = opcode << 8 | ir.modrm; |
| 6132 | goto no_support; |
| 6133 | } |
| 6134 | break; |
| 6135 | case 4: /* smsw */ |
| 6136 | if (ir.mod == 3) |
| 6137 | { |
| 6138 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
| 6139 | return -1; |
| 6140 | } |
| 6141 | else |
| 6142 | { |
| 6143 | ir.ot = OT_WORD; |
| 6144 | if (i386_record_lea_modrm (&ir)) |
| 6145 | return -1; |
| 6146 | } |
| 6147 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6148 | break; |
| 6149 | case 6: /* lmsw */ |
| 6150 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6151 | break; |
| 6152 | case 7: /* invlpg */ |
| 6153 | if (ir.mod == 3) |
| 6154 | { |
| 6155 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) |
| 6156 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
| 6157 | else |
| 6158 | { |
| 6159 | ir.addr -= 3; |
| 6160 | opcode = opcode << 8 | ir.modrm; |
| 6161 | goto no_support; |
| 6162 | } |
| 6163 | } |
| 6164 | else |
| 6165 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6166 | break; |
| 6167 | default: |
| 6168 | ir.addr -= 3; |
| 6169 | opcode = opcode << 8 | ir.modrm; |
| 6170 | goto no_support; |
| 6171 | break; |
| 6172 | } |
| 6173 | break; |
| 6174 | |
| 6175 | case 0x0f08: /* invd */ |
| 6176 | case 0x0f09: /* wbinvd */ |
| 6177 | break; |
| 6178 | |
| 6179 | case 0x63: /* arpl */ |
| 6180 | if (i386_record_modrm (&ir)) |
| 6181 | return -1; |
| 6182 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
| 6183 | { |
| 6184 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
| 6185 | ? (ir.reg | rex_r) : ir.rm); |
| 6186 | } |
| 6187 | else |
| 6188 | { |
| 6189 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; |
| 6190 | if (i386_record_lea_modrm (&ir)) |
| 6191 | return -1; |
| 6192 | } |
| 6193 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) |
| 6194 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6195 | break; |
| 6196 | |
| 6197 | case 0x0f02: /* lar */ |
| 6198 | case 0x0f03: /* lsl */ |
| 6199 | if (i386_record_modrm (&ir)) |
| 6200 | return -1; |
| 6201 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
| 6202 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6203 | break; |
| 6204 | |
| 6205 | case 0x0f18: |
| 6206 | if (i386_record_modrm (&ir)) |
| 6207 | return -1; |
| 6208 | if (ir.mod == 3 && ir.reg == 3) |
| 6209 | { |
| 6210 | ir.addr -= 3; |
| 6211 | opcode = opcode << 8 | ir.modrm; |
| 6212 | goto no_support; |
| 6213 | } |
| 6214 | break; |
| 6215 | |
| 6216 | case 0x0f19: |
| 6217 | case 0x0f1a: |
| 6218 | case 0x0f1b: |
| 6219 | case 0x0f1c: |
| 6220 | case 0x0f1d: |
| 6221 | case 0x0f1e: |
| 6222 | case 0x0f1f: |
| 6223 | /* nop (multi byte) */ |
| 6224 | break; |
| 6225 | |
| 6226 | case 0x0f20: /* mov reg, crN */ |
| 6227 | case 0x0f22: /* mov crN, reg */ |
| 6228 | if (i386_record_modrm (&ir)) |
| 6229 | return -1; |
| 6230 | if ((ir.modrm & 0xc0) != 0xc0) |
| 6231 | { |
| 6232 | ir.addr -= 3; |
| 6233 | opcode = opcode << 8 | ir.modrm; |
| 6234 | goto no_support; |
| 6235 | } |
| 6236 | switch (ir.reg) |
| 6237 | { |
| 6238 | case 0: |
| 6239 | case 2: |
| 6240 | case 3: |
| 6241 | case 4: |
| 6242 | case 8: |
| 6243 | if (opcode & 2) |
| 6244 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6245 | else |
| 6246 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 6247 | break; |
| 6248 | default: |
| 6249 | ir.addr -= 3; |
| 6250 | opcode = opcode << 8 | ir.modrm; |
| 6251 | goto no_support; |
| 6252 | break; |
| 6253 | } |
| 6254 | break; |
| 6255 | |
| 6256 | case 0x0f21: /* mov reg, drN */ |
| 6257 | case 0x0f23: /* mov drN, reg */ |
| 6258 | if (i386_record_modrm (&ir)) |
| 6259 | return -1; |
| 6260 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 |
| 6261 | || ir.reg == 5 || ir.reg >= 8) |
| 6262 | { |
| 6263 | ir.addr -= 3; |
| 6264 | opcode = opcode << 8 | ir.modrm; |
| 6265 | goto no_support; |
| 6266 | } |
| 6267 | if (opcode & 2) |
| 6268 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6269 | else |
| 6270 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 6271 | break; |
| 6272 | |
| 6273 | case 0x0f06: /* clts */ |
| 6274 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6275 | break; |
| 6276 | |
| 6277 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
| 6278 | |
| 6279 | case 0x0f0d: /* 3DNow! prefetch */ |
| 6280 | break; |
| 6281 | |
| 6282 | case 0x0f0e: /* 3DNow! femms */ |
| 6283 | case 0x0f77: /* emms */ |
| 6284 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) |
| 6285 | goto no_support; |
| 6286 | record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
| 6287 | break; |
| 6288 | |
| 6289 | case 0x0f0f: /* 3DNow! data */ |
| 6290 | if (i386_record_modrm (&ir)) |
| 6291 | return -1; |
| 6292 | if (target_read_memory (ir.addr, &opcode8, 1)) |
| 6293 | { |
| 6294 | printf_unfiltered (_("Process record: error reading memory at " |
| 6295 | "addr %s len = 1.\n"), |
| 6296 | paddress (gdbarch, ir.addr)); |
| 6297 | return -1; |
| 6298 | } |
| 6299 | ir.addr++; |
| 6300 | switch (opcode8) |
| 6301 | { |
| 6302 | case 0x0c: /* 3DNow! pi2fw */ |
| 6303 | case 0x0d: /* 3DNow! pi2fd */ |
| 6304 | case 0x1c: /* 3DNow! pf2iw */ |
| 6305 | case 0x1d: /* 3DNow! pf2id */ |
| 6306 | case 0x8a: /* 3DNow! pfnacc */ |
| 6307 | case 0x8e: /* 3DNow! pfpnacc */ |
| 6308 | case 0x90: /* 3DNow! pfcmpge */ |
| 6309 | case 0x94: /* 3DNow! pfmin */ |
| 6310 | case 0x96: /* 3DNow! pfrcp */ |
| 6311 | case 0x97: /* 3DNow! pfrsqrt */ |
| 6312 | case 0x9a: /* 3DNow! pfsub */ |
| 6313 | case 0x9e: /* 3DNow! pfadd */ |
| 6314 | case 0xa0: /* 3DNow! pfcmpgt */ |
| 6315 | case 0xa4: /* 3DNow! pfmax */ |
| 6316 | case 0xa6: /* 3DNow! pfrcpit1 */ |
| 6317 | case 0xa7: /* 3DNow! pfrsqit1 */ |
| 6318 | case 0xaa: /* 3DNow! pfsubr */ |
| 6319 | case 0xae: /* 3DNow! pfacc */ |
| 6320 | case 0xb0: /* 3DNow! pfcmpeq */ |
| 6321 | case 0xb4: /* 3DNow! pfmul */ |
| 6322 | case 0xb6: /* 3DNow! pfrcpit2 */ |
| 6323 | case 0xb7: /* 3DNow! pmulhrw */ |
| 6324 | case 0xbb: /* 3DNow! pswapd */ |
| 6325 | case 0xbf: /* 3DNow! pavgusb */ |
| 6326 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) |
| 6327 | goto no_support_3dnow_data; |
| 6328 | record_arch_list_add_reg (ir.regcache, ir.reg); |
| 6329 | break; |
| 6330 | |
| 6331 | default: |
| 6332 | no_support_3dnow_data: |
| 6333 | opcode = (opcode << 8) | opcode8; |
| 6334 | goto no_support; |
| 6335 | break; |
| 6336 | } |
| 6337 | break; |
| 6338 | |
| 6339 | case 0x0faa: /* rsm */ |
| 6340 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6341 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
| 6342 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
| 6343 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
| 6344 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); |
| 6345 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
| 6346 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
| 6347 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
| 6348 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
| 6349 | break; |
| 6350 | |
| 6351 | case 0x0fae: |
| 6352 | if (i386_record_modrm (&ir)) |
| 6353 | return -1; |
| 6354 | switch(ir.reg) |
| 6355 | { |
| 6356 | case 0: /* fxsave */ |
| 6357 | { |
| 6358 | uint64_t tmpu64; |
| 6359 | |
| 6360 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6361 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
| 6362 | return -1; |
| 6363 | if (record_arch_list_add_mem (tmpu64, 512)) |
| 6364 | return -1; |
| 6365 | } |
| 6366 | break; |
| 6367 | |
| 6368 | case 1: /* fxrstor */ |
| 6369 | { |
| 6370 | int i; |
| 6371 | |
| 6372 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6373 | |
| 6374 | for (i = I387_MM0_REGNUM (tdep); |
| 6375 | i386_mmx_regnum_p (gdbarch, i); i++) |
| 6376 | record_arch_list_add_reg (ir.regcache, i); |
| 6377 | |
| 6378 | for (i = I387_XMM0_REGNUM (tdep); |
| 6379 | i386_xmm_regnum_p (gdbarch, i); i++) |
| 6380 | record_arch_list_add_reg (ir.regcache, i); |
| 6381 | |
| 6382 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) |
| 6383 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
| 6384 | |
| 6385 | for (i = I387_ST0_REGNUM (tdep); |
| 6386 | i386_fp_regnum_p (gdbarch, i); i++) |
| 6387 | record_arch_list_add_reg (ir.regcache, i); |
| 6388 | |
| 6389 | for (i = I387_FCTRL_REGNUM (tdep); |
| 6390 | i386_fpc_regnum_p (gdbarch, i); i++) |
| 6391 | record_arch_list_add_reg (ir.regcache, i); |
| 6392 | } |
| 6393 | break; |
| 6394 | |
| 6395 | case 2: /* ldmxcsr */ |
| 6396 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) |
| 6397 | goto no_support; |
| 6398 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
| 6399 | break; |
| 6400 | |
| 6401 | case 3: /* stmxcsr */ |
| 6402 | ir.ot = OT_LONG; |
| 6403 | if (i386_record_lea_modrm (&ir)) |
| 6404 | return -1; |
| 6405 | break; |
| 6406 | |
| 6407 | case 5: /* lfence */ |
| 6408 | case 6: /* mfence */ |
| 6409 | case 7: /* sfence clflush */ |
| 6410 | break; |
| 6411 | |
| 6412 | default: |
| 6413 | opcode = (opcode << 8) | ir.modrm; |
| 6414 | goto no_support; |
| 6415 | break; |
| 6416 | } |
| 6417 | break; |
| 6418 | |
| 6419 | case 0x0fc3: /* movnti */ |
| 6420 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; |
| 6421 | if (i386_record_modrm (&ir)) |
| 6422 | return -1; |
| 6423 | if (ir.mod == 3) |
| 6424 | goto no_support; |
| 6425 | ir.reg |= rex_r; |
| 6426 | if (i386_record_lea_modrm (&ir)) |
| 6427 | return -1; |
| 6428 | break; |
| 6429 | |
| 6430 | /* Add prefix to opcode. */ |
| 6431 | case 0x0f10: |
| 6432 | case 0x0f11: |
| 6433 | case 0x0f12: |
| 6434 | case 0x0f13: |
| 6435 | case 0x0f14: |
| 6436 | case 0x0f15: |
| 6437 | case 0x0f16: |
| 6438 | case 0x0f17: |
| 6439 | case 0x0f28: |
| 6440 | case 0x0f29: |
| 6441 | case 0x0f2a: |
| 6442 | case 0x0f2b: |
| 6443 | case 0x0f2c: |
| 6444 | case 0x0f2d: |
| 6445 | case 0x0f2e: |
| 6446 | case 0x0f2f: |
| 6447 | case 0x0f38: |
| 6448 | case 0x0f39: |
| 6449 | case 0x0f3a: |
| 6450 | case 0x0f50: |
| 6451 | case 0x0f51: |
| 6452 | case 0x0f52: |
| 6453 | case 0x0f53: |
| 6454 | case 0x0f54: |
| 6455 | case 0x0f55: |
| 6456 | case 0x0f56: |
| 6457 | case 0x0f57: |
| 6458 | case 0x0f58: |
| 6459 | case 0x0f59: |
| 6460 | case 0x0f5a: |
| 6461 | case 0x0f5b: |
| 6462 | case 0x0f5c: |
| 6463 | case 0x0f5d: |
| 6464 | case 0x0f5e: |
| 6465 | case 0x0f5f: |
| 6466 | case 0x0f60: |
| 6467 | case 0x0f61: |
| 6468 | case 0x0f62: |
| 6469 | case 0x0f63: |
| 6470 | case 0x0f64: |
| 6471 | case 0x0f65: |
| 6472 | case 0x0f66: |
| 6473 | case 0x0f67: |
| 6474 | case 0x0f68: |
| 6475 | case 0x0f69: |
| 6476 | case 0x0f6a: |
| 6477 | case 0x0f6b: |
| 6478 | case 0x0f6c: |
| 6479 | case 0x0f6d: |
| 6480 | case 0x0f6e: |
| 6481 | case 0x0f6f: |
| 6482 | case 0x0f70: |
| 6483 | case 0x0f71: |
| 6484 | case 0x0f72: |
| 6485 | case 0x0f73: |
| 6486 | case 0x0f74: |
| 6487 | case 0x0f75: |
| 6488 | case 0x0f76: |
| 6489 | case 0x0f7c: |
| 6490 | case 0x0f7d: |
| 6491 | case 0x0f7e: |
| 6492 | case 0x0f7f: |
| 6493 | case 0x0fb8: |
| 6494 | case 0x0fc2: |
| 6495 | case 0x0fc4: |
| 6496 | case 0x0fc5: |
| 6497 | case 0x0fc6: |
| 6498 | case 0x0fd0: |
| 6499 | case 0x0fd1: |
| 6500 | case 0x0fd2: |
| 6501 | case 0x0fd3: |
| 6502 | case 0x0fd4: |
| 6503 | case 0x0fd5: |
| 6504 | case 0x0fd6: |
| 6505 | case 0x0fd7: |
| 6506 | case 0x0fd8: |
| 6507 | case 0x0fd9: |
| 6508 | case 0x0fda: |
| 6509 | case 0x0fdb: |
| 6510 | case 0x0fdc: |
| 6511 | case 0x0fdd: |
| 6512 | case 0x0fde: |
| 6513 | case 0x0fdf: |
| 6514 | case 0x0fe0: |
| 6515 | case 0x0fe1: |
| 6516 | case 0x0fe2: |
| 6517 | case 0x0fe3: |
| 6518 | case 0x0fe4: |
| 6519 | case 0x0fe5: |
| 6520 | case 0x0fe6: |
| 6521 | case 0x0fe7: |
| 6522 | case 0x0fe8: |
| 6523 | case 0x0fe9: |
| 6524 | case 0x0fea: |
| 6525 | case 0x0feb: |
| 6526 | case 0x0fec: |
| 6527 | case 0x0fed: |
| 6528 | case 0x0fee: |
| 6529 | case 0x0fef: |
| 6530 | case 0x0ff0: |
| 6531 | case 0x0ff1: |
| 6532 | case 0x0ff2: |
| 6533 | case 0x0ff3: |
| 6534 | case 0x0ff4: |
| 6535 | case 0x0ff5: |
| 6536 | case 0x0ff6: |
| 6537 | case 0x0ff7: |
| 6538 | case 0x0ff8: |
| 6539 | case 0x0ff9: |
| 6540 | case 0x0ffa: |
| 6541 | case 0x0ffb: |
| 6542 | case 0x0ffc: |
| 6543 | case 0x0ffd: |
| 6544 | case 0x0ffe: |
| 6545 | switch (prefixes) |
| 6546 | { |
| 6547 | case PREFIX_REPNZ: |
| 6548 | opcode |= 0xf20000; |
| 6549 | break; |
| 6550 | case PREFIX_DATA: |
| 6551 | opcode |= 0x660000; |
| 6552 | break; |
| 6553 | case PREFIX_REPZ: |
| 6554 | opcode |= 0xf30000; |
| 6555 | break; |
| 6556 | } |
| 6557 | reswitch_prefix_add: |
| 6558 | switch (opcode) |
| 6559 | { |
| 6560 | case 0x0f38: |
| 6561 | case 0x660f38: |
| 6562 | case 0xf20f38: |
| 6563 | case 0x0f3a: |
| 6564 | case 0x660f3a: |
| 6565 | if (target_read_memory (ir.addr, &opcode8, 1)) |
| 6566 | { |
| 6567 | printf_unfiltered (_("Process record: error reading memory at " |
| 6568 | "addr %s len = 1.\n"), |
| 6569 | paddress (gdbarch, ir.addr)); |
| 6570 | return -1; |
| 6571 | } |
| 6572 | ir.addr++; |
| 6573 | opcode = (uint32_t) opcode8 | opcode << 8; |
| 6574 | goto reswitch_prefix_add; |
| 6575 | break; |
| 6576 | |
| 6577 | case 0x0f10: /* movups */ |
| 6578 | case 0x660f10: /* movupd */ |
| 6579 | case 0xf30f10: /* movss */ |
| 6580 | case 0xf20f10: /* movsd */ |
| 6581 | case 0x0f12: /* movlps */ |
| 6582 | case 0x660f12: /* movlpd */ |
| 6583 | case 0xf30f12: /* movsldup */ |
| 6584 | case 0xf20f12: /* movddup */ |
| 6585 | case 0x0f14: /* unpcklps */ |
| 6586 | case 0x660f14: /* unpcklpd */ |
| 6587 | case 0x0f15: /* unpckhps */ |
| 6588 | case 0x660f15: /* unpckhpd */ |
| 6589 | case 0x0f16: /* movhps */ |
| 6590 | case 0x660f16: /* movhpd */ |
| 6591 | case 0xf30f16: /* movshdup */ |
| 6592 | case 0x0f28: /* movaps */ |
| 6593 | case 0x660f28: /* movapd */ |
| 6594 | case 0x0f2a: /* cvtpi2ps */ |
| 6595 | case 0x660f2a: /* cvtpi2pd */ |
| 6596 | case 0xf30f2a: /* cvtsi2ss */ |
| 6597 | case 0xf20f2a: /* cvtsi2sd */ |
| 6598 | case 0x0f2c: /* cvttps2pi */ |
| 6599 | case 0x660f2c: /* cvttpd2pi */ |
| 6600 | case 0x0f2d: /* cvtps2pi */ |
| 6601 | case 0x660f2d: /* cvtpd2pi */ |
| 6602 | case 0x660f3800: /* pshufb */ |
| 6603 | case 0x660f3801: /* phaddw */ |
| 6604 | case 0x660f3802: /* phaddd */ |
| 6605 | case 0x660f3803: /* phaddsw */ |
| 6606 | case 0x660f3804: /* pmaddubsw */ |
| 6607 | case 0x660f3805: /* phsubw */ |
| 6608 | case 0x660f3806: /* phsubd */ |
| 6609 | case 0x660f3807: /* phsubsw */ |
| 6610 | case 0x660f3808: /* psignb */ |
| 6611 | case 0x660f3809: /* psignw */ |
| 6612 | case 0x660f380a: /* psignd */ |
| 6613 | case 0x660f380b: /* pmulhrsw */ |
| 6614 | case 0x660f3810: /* pblendvb */ |
| 6615 | case 0x660f3814: /* blendvps */ |
| 6616 | case 0x660f3815: /* blendvpd */ |
| 6617 | case 0x660f381c: /* pabsb */ |
| 6618 | case 0x660f381d: /* pabsw */ |
| 6619 | case 0x660f381e: /* pabsd */ |
| 6620 | case 0x660f3820: /* pmovsxbw */ |
| 6621 | case 0x660f3821: /* pmovsxbd */ |
| 6622 | case 0x660f3822: /* pmovsxbq */ |
| 6623 | case 0x660f3823: /* pmovsxwd */ |
| 6624 | case 0x660f3824: /* pmovsxwq */ |
| 6625 | case 0x660f3825: /* pmovsxdq */ |
| 6626 | case 0x660f3828: /* pmuldq */ |
| 6627 | case 0x660f3829: /* pcmpeqq */ |
| 6628 | case 0x660f382a: /* movntdqa */ |
| 6629 | case 0x660f3a08: /* roundps */ |
| 6630 | case 0x660f3a09: /* roundpd */ |
| 6631 | case 0x660f3a0a: /* roundss */ |
| 6632 | case 0x660f3a0b: /* roundsd */ |
| 6633 | case 0x660f3a0c: /* blendps */ |
| 6634 | case 0x660f3a0d: /* blendpd */ |
| 6635 | case 0x660f3a0e: /* pblendw */ |
| 6636 | case 0x660f3a0f: /* palignr */ |
| 6637 | case 0x660f3a20: /* pinsrb */ |
| 6638 | case 0x660f3a21: /* insertps */ |
| 6639 | case 0x660f3a22: /* pinsrd pinsrq */ |
| 6640 | case 0x660f3a40: /* dpps */ |
| 6641 | case 0x660f3a41: /* dppd */ |
| 6642 | case 0x660f3a42: /* mpsadbw */ |
| 6643 | case 0x660f3a60: /* pcmpestrm */ |
| 6644 | case 0x660f3a61: /* pcmpestri */ |
| 6645 | case 0x660f3a62: /* pcmpistrm */ |
| 6646 | case 0x660f3a63: /* pcmpistri */ |
| 6647 | case 0x0f51: /* sqrtps */ |
| 6648 | case 0x660f51: /* sqrtpd */ |
| 6649 | case 0xf20f51: /* sqrtsd */ |
| 6650 | case 0xf30f51: /* sqrtss */ |
| 6651 | case 0x0f52: /* rsqrtps */ |
| 6652 | case 0xf30f52: /* rsqrtss */ |
| 6653 | case 0x0f53: /* rcpps */ |
| 6654 | case 0xf30f53: /* rcpss */ |
| 6655 | case 0x0f54: /* andps */ |
| 6656 | case 0x660f54: /* andpd */ |
| 6657 | case 0x0f55: /* andnps */ |
| 6658 | case 0x660f55: /* andnpd */ |
| 6659 | case 0x0f56: /* orps */ |
| 6660 | case 0x660f56: /* orpd */ |
| 6661 | case 0x0f57: /* xorps */ |
| 6662 | case 0x660f57: /* xorpd */ |
| 6663 | case 0x0f58: /* addps */ |
| 6664 | case 0x660f58: /* addpd */ |
| 6665 | case 0xf20f58: /* addsd */ |
| 6666 | case 0xf30f58: /* addss */ |
| 6667 | case 0x0f59: /* mulps */ |
| 6668 | case 0x660f59: /* mulpd */ |
| 6669 | case 0xf20f59: /* mulsd */ |
| 6670 | case 0xf30f59: /* mulss */ |
| 6671 | case 0x0f5a: /* cvtps2pd */ |
| 6672 | case 0x660f5a: /* cvtpd2ps */ |
| 6673 | case 0xf20f5a: /* cvtsd2ss */ |
| 6674 | case 0xf30f5a: /* cvtss2sd */ |
| 6675 | case 0x0f5b: /* cvtdq2ps */ |
| 6676 | case 0x660f5b: /* cvtps2dq */ |
| 6677 | case 0xf30f5b: /* cvttps2dq */ |
| 6678 | case 0x0f5c: /* subps */ |
| 6679 | case 0x660f5c: /* subpd */ |
| 6680 | case 0xf20f5c: /* subsd */ |
| 6681 | case 0xf30f5c: /* subss */ |
| 6682 | case 0x0f5d: /* minps */ |
| 6683 | case 0x660f5d: /* minpd */ |
| 6684 | case 0xf20f5d: /* minsd */ |
| 6685 | case 0xf30f5d: /* minss */ |
| 6686 | case 0x0f5e: /* divps */ |
| 6687 | case 0x660f5e: /* divpd */ |
| 6688 | case 0xf20f5e: /* divsd */ |
| 6689 | case 0xf30f5e: /* divss */ |
| 6690 | case 0x0f5f: /* maxps */ |
| 6691 | case 0x660f5f: /* maxpd */ |
| 6692 | case 0xf20f5f: /* maxsd */ |
| 6693 | case 0xf30f5f: /* maxss */ |
| 6694 | case 0x660f60: /* punpcklbw */ |
| 6695 | case 0x660f61: /* punpcklwd */ |
| 6696 | case 0x660f62: /* punpckldq */ |
| 6697 | case 0x660f63: /* packsswb */ |
| 6698 | case 0x660f64: /* pcmpgtb */ |
| 6699 | case 0x660f65: /* pcmpgtw */ |
| 6700 | case 0x660f66: /* pcmpgtd */ |
| 6701 | case 0x660f67: /* packuswb */ |
| 6702 | case 0x660f68: /* punpckhbw */ |
| 6703 | case 0x660f69: /* punpckhwd */ |
| 6704 | case 0x660f6a: /* punpckhdq */ |
| 6705 | case 0x660f6b: /* packssdw */ |
| 6706 | case 0x660f6c: /* punpcklqdq */ |
| 6707 | case 0x660f6d: /* punpckhqdq */ |
| 6708 | case 0x660f6e: /* movd */ |
| 6709 | case 0x660f6f: /* movdqa */ |
| 6710 | case 0xf30f6f: /* movdqu */ |
| 6711 | case 0x660f70: /* pshufd */ |
| 6712 | case 0xf20f70: /* pshuflw */ |
| 6713 | case 0xf30f70: /* pshufhw */ |
| 6714 | case 0x660f74: /* pcmpeqb */ |
| 6715 | case 0x660f75: /* pcmpeqw */ |
| 6716 | case 0x660f76: /* pcmpeqd */ |
| 6717 | case 0x660f7c: /* haddpd */ |
| 6718 | case 0xf20f7c: /* haddps */ |
| 6719 | case 0x660f7d: /* hsubpd */ |
| 6720 | case 0xf20f7d: /* hsubps */ |
| 6721 | case 0xf30f7e: /* movq */ |
| 6722 | case 0x0fc2: /* cmpps */ |
| 6723 | case 0x660fc2: /* cmppd */ |
| 6724 | case 0xf20fc2: /* cmpsd */ |
| 6725 | case 0xf30fc2: /* cmpss */ |
| 6726 | case 0x660fc4: /* pinsrw */ |
| 6727 | case 0x0fc6: /* shufps */ |
| 6728 | case 0x660fc6: /* shufpd */ |
| 6729 | case 0x660fd0: /* addsubpd */ |
| 6730 | case 0xf20fd0: /* addsubps */ |
| 6731 | case 0x660fd1: /* psrlw */ |
| 6732 | case 0x660fd2: /* psrld */ |
| 6733 | case 0x660fd3: /* psrlq */ |
| 6734 | case 0x660fd4: /* paddq */ |
| 6735 | case 0x660fd5: /* pmullw */ |
| 6736 | case 0xf30fd6: /* movq2dq */ |
| 6737 | case 0x660fd8: /* psubusb */ |
| 6738 | case 0x660fd9: /* psubusw */ |
| 6739 | case 0x660fda: /* pminub */ |
| 6740 | case 0x660fdb: /* pand */ |
| 6741 | case 0x660fdc: /* paddusb */ |
| 6742 | case 0x660fdd: /* paddusw */ |
| 6743 | case 0x660fde: /* pmaxub */ |
| 6744 | case 0x660fdf: /* pandn */ |
| 6745 | case 0x660fe0: /* pavgb */ |
| 6746 | case 0x660fe1: /* psraw */ |
| 6747 | case 0x660fe2: /* psrad */ |
| 6748 | case 0x660fe3: /* pavgw */ |
| 6749 | case 0x660fe4: /* pmulhuw */ |
| 6750 | case 0x660fe5: /* pmulhw */ |
| 6751 | case 0x660fe6: /* cvttpd2dq */ |
| 6752 | case 0xf20fe6: /* cvtpd2dq */ |
| 6753 | case 0xf30fe6: /* cvtdq2pd */ |
| 6754 | case 0x660fe8: /* psubsb */ |
| 6755 | case 0x660fe9: /* psubsw */ |
| 6756 | case 0x660fea: /* pminsw */ |
| 6757 | case 0x660feb: /* por */ |
| 6758 | case 0x660fec: /* paddsb */ |
| 6759 | case 0x660fed: /* paddsw */ |
| 6760 | case 0x660fee: /* pmaxsw */ |
| 6761 | case 0x660fef: /* pxor */ |
| 6762 | case 0xf20ff0: /* lddqu */ |
| 6763 | case 0x660ff1: /* psllw */ |
| 6764 | case 0x660ff2: /* pslld */ |
| 6765 | case 0x660ff3: /* psllq */ |
| 6766 | case 0x660ff4: /* pmuludq */ |
| 6767 | case 0x660ff5: /* pmaddwd */ |
| 6768 | case 0x660ff6: /* psadbw */ |
| 6769 | case 0x660ff8: /* psubb */ |
| 6770 | case 0x660ff9: /* psubw */ |
| 6771 | case 0x660ffa: /* psubd */ |
| 6772 | case 0x660ffb: /* psubq */ |
| 6773 | case 0x660ffc: /* paddb */ |
| 6774 | case 0x660ffd: /* paddw */ |
| 6775 | case 0x660ffe: /* paddd */ |
| 6776 | if (i386_record_modrm (&ir)) |
| 6777 | return -1; |
| 6778 | ir.reg |= rex_r; |
| 6779 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
| 6780 | goto no_support; |
| 6781 | record_arch_list_add_reg (ir.regcache, |
| 6782 | I387_XMM0_REGNUM (tdep) + ir.reg); |
| 6783 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
| 6784 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 6785 | break; |
| 6786 | |
| 6787 | case 0x0f11: /* movups */ |
| 6788 | case 0x660f11: /* movupd */ |
| 6789 | case 0xf30f11: /* movss */ |
| 6790 | case 0xf20f11: /* movsd */ |
| 6791 | case 0x0f13: /* movlps */ |
| 6792 | case 0x660f13: /* movlpd */ |
| 6793 | case 0x0f17: /* movhps */ |
| 6794 | case 0x660f17: /* movhpd */ |
| 6795 | case 0x0f29: /* movaps */ |
| 6796 | case 0x660f29: /* movapd */ |
| 6797 | case 0x660f3a14: /* pextrb */ |
| 6798 | case 0x660f3a15: /* pextrw */ |
| 6799 | case 0x660f3a16: /* pextrd pextrq */ |
| 6800 | case 0x660f3a17: /* extractps */ |
| 6801 | case 0x660f7f: /* movdqa */ |
| 6802 | case 0xf30f7f: /* movdqu */ |
| 6803 | if (i386_record_modrm (&ir)) |
| 6804 | return -1; |
| 6805 | if (ir.mod == 3) |
| 6806 | { |
| 6807 | if (opcode == 0x0f13 || opcode == 0x660f13 |
| 6808 | || opcode == 0x0f17 || opcode == 0x660f17) |
| 6809 | goto no_support; |
| 6810 | ir.rm |= ir.rex_b; |
| 6811 | if (!i386_xmm_regnum_p (gdbarch, |
| 6812 | I387_XMM0_REGNUM (tdep) + ir.rm)) |
| 6813 | goto no_support; |
| 6814 | record_arch_list_add_reg (ir.regcache, |
| 6815 | I387_XMM0_REGNUM (tdep) + ir.rm); |
| 6816 | } |
| 6817 | else |
| 6818 | { |
| 6819 | switch (opcode) |
| 6820 | { |
| 6821 | case 0x660f3a14: |
| 6822 | ir.ot = OT_BYTE; |
| 6823 | break; |
| 6824 | case 0x660f3a15: |
| 6825 | ir.ot = OT_WORD; |
| 6826 | break; |
| 6827 | case 0x660f3a16: |
| 6828 | ir.ot = OT_LONG; |
| 6829 | break; |
| 6830 | case 0x660f3a17: |
| 6831 | ir.ot = OT_QUAD; |
| 6832 | break; |
| 6833 | default: |
| 6834 | ir.ot = OT_DQUAD; |
| 6835 | break; |
| 6836 | } |
| 6837 | if (i386_record_lea_modrm (&ir)) |
| 6838 | return -1; |
| 6839 | } |
| 6840 | break; |
| 6841 | |
| 6842 | case 0x0f2b: /* movntps */ |
| 6843 | case 0x660f2b: /* movntpd */ |
| 6844 | case 0x0fe7: /* movntq */ |
| 6845 | case 0x660fe7: /* movntdq */ |
| 6846 | if (ir.mod == 3) |
| 6847 | goto no_support; |
| 6848 | if (opcode == 0x0fe7) |
| 6849 | ir.ot = OT_QUAD; |
| 6850 | else |
| 6851 | ir.ot = OT_DQUAD; |
| 6852 | if (i386_record_lea_modrm (&ir)) |
| 6853 | return -1; |
| 6854 | break; |
| 6855 | |
| 6856 | case 0xf30f2c: /* cvttss2si */ |
| 6857 | case 0xf20f2c: /* cvttsd2si */ |
| 6858 | case 0xf30f2d: /* cvtss2si */ |
| 6859 | case 0xf20f2d: /* cvtsd2si */ |
| 6860 | case 0xf20f38f0: /* crc32 */ |
| 6861 | case 0xf20f38f1: /* crc32 */ |
| 6862 | case 0x0f50: /* movmskps */ |
| 6863 | case 0x660f50: /* movmskpd */ |
| 6864 | case 0x0fc5: /* pextrw */ |
| 6865 | case 0x660fc5: /* pextrw */ |
| 6866 | case 0x0fd7: /* pmovmskb */ |
| 6867 | case 0x660fd7: /* pmovmskb */ |
| 6868 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
| 6869 | break; |
| 6870 | |
| 6871 | case 0x0f3800: /* pshufb */ |
| 6872 | case 0x0f3801: /* phaddw */ |
| 6873 | case 0x0f3802: /* phaddd */ |
| 6874 | case 0x0f3803: /* phaddsw */ |
| 6875 | case 0x0f3804: /* pmaddubsw */ |
| 6876 | case 0x0f3805: /* phsubw */ |
| 6877 | case 0x0f3806: /* phsubd */ |
| 6878 | case 0x0f3807: /* phsubsw */ |
| 6879 | case 0x0f3808: /* psignb */ |
| 6880 | case 0x0f3809: /* psignw */ |
| 6881 | case 0x0f380a: /* psignd */ |
| 6882 | case 0x0f380b: /* pmulhrsw */ |
| 6883 | case 0x0f381c: /* pabsb */ |
| 6884 | case 0x0f381d: /* pabsw */ |
| 6885 | case 0x0f381e: /* pabsd */ |
| 6886 | case 0x0f382b: /* packusdw */ |
| 6887 | case 0x0f3830: /* pmovzxbw */ |
| 6888 | case 0x0f3831: /* pmovzxbd */ |
| 6889 | case 0x0f3832: /* pmovzxbq */ |
| 6890 | case 0x0f3833: /* pmovzxwd */ |
| 6891 | case 0x0f3834: /* pmovzxwq */ |
| 6892 | case 0x0f3835: /* pmovzxdq */ |
| 6893 | case 0x0f3837: /* pcmpgtq */ |
| 6894 | case 0x0f3838: /* pminsb */ |
| 6895 | case 0x0f3839: /* pminsd */ |
| 6896 | case 0x0f383a: /* pminuw */ |
| 6897 | case 0x0f383b: /* pminud */ |
| 6898 | case 0x0f383c: /* pmaxsb */ |
| 6899 | case 0x0f383d: /* pmaxsd */ |
| 6900 | case 0x0f383e: /* pmaxuw */ |
| 6901 | case 0x0f383f: /* pmaxud */ |
| 6902 | case 0x0f3840: /* pmulld */ |
| 6903 | case 0x0f3841: /* phminposuw */ |
| 6904 | case 0x0f3a0f: /* palignr */ |
| 6905 | case 0x0f60: /* punpcklbw */ |
| 6906 | case 0x0f61: /* punpcklwd */ |
| 6907 | case 0x0f62: /* punpckldq */ |
| 6908 | case 0x0f63: /* packsswb */ |
| 6909 | case 0x0f64: /* pcmpgtb */ |
| 6910 | case 0x0f65: /* pcmpgtw */ |
| 6911 | case 0x0f66: /* pcmpgtd */ |
| 6912 | case 0x0f67: /* packuswb */ |
| 6913 | case 0x0f68: /* punpckhbw */ |
| 6914 | case 0x0f69: /* punpckhwd */ |
| 6915 | case 0x0f6a: /* punpckhdq */ |
| 6916 | case 0x0f6b: /* packssdw */ |
| 6917 | case 0x0f6e: /* movd */ |
| 6918 | case 0x0f6f: /* movq */ |
| 6919 | case 0x0f70: /* pshufw */ |
| 6920 | case 0x0f74: /* pcmpeqb */ |
| 6921 | case 0x0f75: /* pcmpeqw */ |
| 6922 | case 0x0f76: /* pcmpeqd */ |
| 6923 | case 0x0fc4: /* pinsrw */ |
| 6924 | case 0x0fd1: /* psrlw */ |
| 6925 | case 0x0fd2: /* psrld */ |
| 6926 | case 0x0fd3: /* psrlq */ |
| 6927 | case 0x0fd4: /* paddq */ |
| 6928 | case 0x0fd5: /* pmullw */ |
| 6929 | case 0xf20fd6: /* movdq2q */ |
| 6930 | case 0x0fd8: /* psubusb */ |
| 6931 | case 0x0fd9: /* psubusw */ |
| 6932 | case 0x0fda: /* pminub */ |
| 6933 | case 0x0fdb: /* pand */ |
| 6934 | case 0x0fdc: /* paddusb */ |
| 6935 | case 0x0fdd: /* paddusw */ |
| 6936 | case 0x0fde: /* pmaxub */ |
| 6937 | case 0x0fdf: /* pandn */ |
| 6938 | case 0x0fe0: /* pavgb */ |
| 6939 | case 0x0fe1: /* psraw */ |
| 6940 | case 0x0fe2: /* psrad */ |
| 6941 | case 0x0fe3: /* pavgw */ |
| 6942 | case 0x0fe4: /* pmulhuw */ |
| 6943 | case 0x0fe5: /* pmulhw */ |
| 6944 | case 0x0fe8: /* psubsb */ |
| 6945 | case 0x0fe9: /* psubsw */ |
| 6946 | case 0x0fea: /* pminsw */ |
| 6947 | case 0x0feb: /* por */ |
| 6948 | case 0x0fec: /* paddsb */ |
| 6949 | case 0x0fed: /* paddsw */ |
| 6950 | case 0x0fee: /* pmaxsw */ |
| 6951 | case 0x0fef: /* pxor */ |
| 6952 | case 0x0ff1: /* psllw */ |
| 6953 | case 0x0ff2: /* pslld */ |
| 6954 | case 0x0ff3: /* psllq */ |
| 6955 | case 0x0ff4: /* pmuludq */ |
| 6956 | case 0x0ff5: /* pmaddwd */ |
| 6957 | case 0x0ff6: /* psadbw */ |
| 6958 | case 0x0ff8: /* psubb */ |
| 6959 | case 0x0ff9: /* psubw */ |
| 6960 | case 0x0ffa: /* psubd */ |
| 6961 | case 0x0ffb: /* psubq */ |
| 6962 | case 0x0ffc: /* paddb */ |
| 6963 | case 0x0ffd: /* paddw */ |
| 6964 | case 0x0ffe: /* paddd */ |
| 6965 | if (i386_record_modrm (&ir)) |
| 6966 | return -1; |
| 6967 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) |
| 6968 | goto no_support; |
| 6969 | record_arch_list_add_reg (ir.regcache, |
| 6970 | I387_MM0_REGNUM (tdep) + ir.reg); |
| 6971 | break; |
| 6972 | |
| 6973 | case 0x0f71: /* psllw */ |
| 6974 | case 0x0f72: /* pslld */ |
| 6975 | case 0x0f73: /* psllq */ |
| 6976 | if (i386_record_modrm (&ir)) |
| 6977 | return -1; |
| 6978 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) |
| 6979 | goto no_support; |
| 6980 | record_arch_list_add_reg (ir.regcache, |
| 6981 | I387_MM0_REGNUM (tdep) + ir.rm); |
| 6982 | break; |
| 6983 | |
| 6984 | case 0x660f71: /* psllw */ |
| 6985 | case 0x660f72: /* pslld */ |
| 6986 | case 0x660f73: /* psllq */ |
| 6987 | if (i386_record_modrm (&ir)) |
| 6988 | return -1; |
| 6989 | ir.rm |= ir.rex_b; |
| 6990 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
| 6991 | goto no_support; |
| 6992 | record_arch_list_add_reg (ir.regcache, |
| 6993 | I387_XMM0_REGNUM (tdep) + ir.rm); |
| 6994 | break; |
| 6995 | |
| 6996 | case 0x0f7e: /* movd */ |
| 6997 | case 0x660f7e: /* movd */ |
| 6998 | if (i386_record_modrm (&ir)) |
| 6999 | return -1; |
| 7000 | if (ir.mod == 3) |
| 7001 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
| 7002 | else |
| 7003 | { |
| 7004 | if (ir.dflag == 2) |
| 7005 | ir.ot = OT_QUAD; |
| 7006 | else |
| 7007 | ir.ot = OT_LONG; |
| 7008 | if (i386_record_lea_modrm (&ir)) |
| 7009 | return -1; |
| 7010 | } |
| 7011 | break; |
| 7012 | |
| 7013 | case 0x0f7f: /* movq */ |
| 7014 | if (i386_record_modrm (&ir)) |
| 7015 | return -1; |
| 7016 | if (ir.mod == 3) |
| 7017 | { |
| 7018 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) |
| 7019 | goto no_support; |
| 7020 | record_arch_list_add_reg (ir.regcache, |
| 7021 | I387_MM0_REGNUM (tdep) + ir.rm); |
| 7022 | } |
| 7023 | else |
| 7024 | { |
| 7025 | ir.ot = OT_QUAD; |
| 7026 | if (i386_record_lea_modrm (&ir)) |
| 7027 | return -1; |
| 7028 | } |
| 7029 | break; |
| 7030 | |
| 7031 | case 0xf30fb8: /* popcnt */ |
| 7032 | if (i386_record_modrm (&ir)) |
| 7033 | return -1; |
| 7034 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
| 7035 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 7036 | break; |
| 7037 | |
| 7038 | case 0x660fd6: /* movq */ |
| 7039 | if (i386_record_modrm (&ir)) |
| 7040 | return -1; |
| 7041 | if (ir.mod == 3) |
| 7042 | { |
| 7043 | ir.rm |= ir.rex_b; |
| 7044 | if (!i386_xmm_regnum_p (gdbarch, |
| 7045 | I387_XMM0_REGNUM (tdep) + ir.rm)) |
| 7046 | goto no_support; |
| 7047 | record_arch_list_add_reg (ir.regcache, |
| 7048 | I387_XMM0_REGNUM (tdep) + ir.rm); |
| 7049 | } |
| 7050 | else |
| 7051 | { |
| 7052 | ir.ot = OT_QUAD; |
| 7053 | if (i386_record_lea_modrm (&ir)) |
| 7054 | return -1; |
| 7055 | } |
| 7056 | break; |
| 7057 | |
| 7058 | case 0x660f3817: /* ptest */ |
| 7059 | case 0x0f2e: /* ucomiss */ |
| 7060 | case 0x660f2e: /* ucomisd */ |
| 7061 | case 0x0f2f: /* comiss */ |
| 7062 | case 0x660f2f: /* comisd */ |
| 7063 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
| 7064 | break; |
| 7065 | |
| 7066 | case 0x0ff7: /* maskmovq */ |
| 7067 | regcache_raw_read_unsigned (ir.regcache, |
| 7068 | ir.regmap[X86_RECORD_REDI_REGNUM], |
| 7069 | &addr); |
| 7070 | if (record_arch_list_add_mem (addr, 64)) |
| 7071 | return -1; |
| 7072 | break; |
| 7073 | |
| 7074 | case 0x660ff7: /* maskmovdqu */ |
| 7075 | regcache_raw_read_unsigned (ir.regcache, |
| 7076 | ir.regmap[X86_RECORD_REDI_REGNUM], |
| 7077 | &addr); |
| 7078 | if (record_arch_list_add_mem (addr, 128)) |
| 7079 | return -1; |
| 7080 | break; |
| 7081 | |
| 7082 | default: |
| 7083 | goto no_support; |
| 7084 | break; |
| 7085 | } |
| 7086 | break; |
| 7087 | |
| 7088 | default: |
| 7089 | goto no_support; |
| 7090 | break; |
| 7091 | } |
| 7092 | |
| 7093 | /* In the future, maybe still need to deal with need_dasm. */ |
| 7094 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
| 7095 | if (record_arch_list_add_end ()) |
| 7096 | return -1; |
| 7097 | |
| 7098 | return 0; |
| 7099 | |
| 7100 | no_support: |
| 7101 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
| 7102 | "at address %s.\n"), |
| 7103 | (unsigned int) (opcode), |
| 7104 | paddress (gdbarch, ir.orig_addr)); |
| 7105 | return -1; |
| 7106 | } |
| 7107 | |
| 7108 | static const int i386_record_regmap[] = |
| 7109 | { |
| 7110 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, |
| 7111 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, |
| 7112 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 7113 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, |
| 7114 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM |
| 7115 | }; |
| 7116 | |
| 7117 | /* Check that the given address appears suitable for a fast |
| 7118 | tracepoint, which on x86-64 means that we need an instruction of at |
| 7119 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
| 7120 | jump and not have to worry about program jumps to an address in the |
| 7121 | middle of the tracepoint jump. On x86, it may be possible to use |
| 7122 | 4-byte jumps with a 2-byte offset to a trampoline located in the |
| 7123 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size |
| 7124 | of instruction to replace, and 0 if not, plus an explanatory |
| 7125 | string. */ |
| 7126 | |
| 7127 | static int |
| 7128 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, |
| 7129 | CORE_ADDR addr, int *isize, char **msg) |
| 7130 | { |
| 7131 | int len, jumplen; |
| 7132 | static struct ui_file *gdb_null = NULL; |
| 7133 | |
| 7134 | /* Ask the target for the minimum instruction length supported. */ |
| 7135 | jumplen = target_get_min_fast_tracepoint_insn_len (); |
| 7136 | |
| 7137 | if (jumplen < 0) |
| 7138 | { |
| 7139 | /* If the target does not support the get_min_fast_tracepoint_insn_len |
| 7140 | operation, assume that fast tracepoints will always be implemented |
| 7141 | using 4-byte relative jumps on both x86 and x86-64. */ |
| 7142 | jumplen = 5; |
| 7143 | } |
| 7144 | else if (jumplen == 0) |
| 7145 | { |
| 7146 | /* If the target does support get_min_fast_tracepoint_insn_len but |
| 7147 | returns zero, then the IPA has not loaded yet. In this case, |
| 7148 | we optimistically assume that truncated 2-byte relative jumps |
| 7149 | will be available on x86, and compensate later if this assumption |
| 7150 | turns out to be incorrect. On x86-64 architectures, 4-byte relative |
| 7151 | jumps will always be used. */ |
| 7152 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; |
| 7153 | } |
| 7154 | |
| 7155 | /* Dummy file descriptor for the disassembler. */ |
| 7156 | if (!gdb_null) |
| 7157 | gdb_null = ui_file_new (); |
| 7158 | |
| 7159 | /* Check for fit. */ |
| 7160 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); |
| 7161 | if (isize) |
| 7162 | *isize = len; |
| 7163 | |
| 7164 | if (len < jumplen) |
| 7165 | { |
| 7166 | /* Return a bit of target-specific detail to add to the caller's |
| 7167 | generic failure message. */ |
| 7168 | if (msg) |
| 7169 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
| 7170 | "need at least %d bytes for the jump"), |
| 7171 | len, jumplen); |
| 7172 | return 0; |
| 7173 | } |
| 7174 | else |
| 7175 | { |
| 7176 | if (msg) |
| 7177 | *msg = NULL; |
| 7178 | return 1; |
| 7179 | } |
| 7180 | } |
| 7181 | |
| 7182 | static int |
| 7183 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, |
| 7184 | struct tdesc_arch_data *tdesc_data) |
| 7185 | { |
| 7186 | const struct target_desc *tdesc = tdep->tdesc; |
| 7187 | const struct tdesc_feature *feature_core; |
| 7188 | const struct tdesc_feature *feature_sse, *feature_avx; |
| 7189 | int i, num_regs, valid_p; |
| 7190 | |
| 7191 | if (! tdesc_has_registers (tdesc)) |
| 7192 | return 0; |
| 7193 | |
| 7194 | /* Get core registers. */ |
| 7195 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); |
| 7196 | if (feature_core == NULL) |
| 7197 | return 0; |
| 7198 | |
| 7199 | /* Get SSE registers. */ |
| 7200 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
| 7201 | |
| 7202 | /* Try AVX registers. */ |
| 7203 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); |
| 7204 | |
| 7205 | valid_p = 1; |
| 7206 | |
| 7207 | /* The XCR0 bits. */ |
| 7208 | if (feature_avx) |
| 7209 | { |
| 7210 | /* AVX register description requires SSE register description. */ |
| 7211 | if (!feature_sse) |
| 7212 | return 0; |
| 7213 | |
| 7214 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
| 7215 | |
| 7216 | /* It may have been set by OSABI initialization function. */ |
| 7217 | if (tdep->num_ymm_regs == 0) |
| 7218 | { |
| 7219 | tdep->ymmh_register_names = i386_ymmh_names; |
| 7220 | tdep->num_ymm_regs = 8; |
| 7221 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; |
| 7222 | } |
| 7223 | |
| 7224 | for (i = 0; i < tdep->num_ymm_regs; i++) |
| 7225 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, |
| 7226 | tdep->ymm0h_regnum + i, |
| 7227 | tdep->ymmh_register_names[i]); |
| 7228 | } |
| 7229 | else if (feature_sse) |
| 7230 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
| 7231 | else |
| 7232 | { |
| 7233 | tdep->xcr0 = I386_XSTATE_X87_MASK; |
| 7234 | tdep->num_xmm_regs = 0; |
| 7235 | } |
| 7236 | |
| 7237 | num_regs = tdep->num_core_regs; |
| 7238 | for (i = 0; i < num_regs; i++) |
| 7239 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, |
| 7240 | tdep->register_names[i]); |
| 7241 | |
| 7242 | if (feature_sse) |
| 7243 | { |
| 7244 | /* Need to include %mxcsr, so add one. */ |
| 7245 | num_regs += tdep->num_xmm_regs + 1; |
| 7246 | for (; i < num_regs; i++) |
| 7247 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, |
| 7248 | tdep->register_names[i]); |
| 7249 | } |
| 7250 | |
| 7251 | return valid_p; |
| 7252 | } |
| 7253 | |
| 7254 | \f |
| 7255 | static struct gdbarch * |
| 7256 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 7257 | { |
| 7258 | struct gdbarch_tdep *tdep; |
| 7259 | struct gdbarch *gdbarch; |
| 7260 | struct tdesc_arch_data *tdesc_data; |
| 7261 | const struct target_desc *tdesc; |
| 7262 | int mm0_regnum; |
| 7263 | int ymm0_regnum; |
| 7264 | |
| 7265 | /* If there is already a candidate, use it. */ |
| 7266 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 7267 | if (arches != NULL) |
| 7268 | return arches->gdbarch; |
| 7269 | |
| 7270 | /* Allocate space for the new architecture. */ |
| 7271 | tdep = XCALLOC (1, struct gdbarch_tdep); |
| 7272 | gdbarch = gdbarch_alloc (&info, tdep); |
| 7273 | |
| 7274 | /* General-purpose registers. */ |
| 7275 | tdep->gregset = NULL; |
| 7276 | tdep->gregset_reg_offset = NULL; |
| 7277 | tdep->gregset_num_regs = I386_NUM_GREGS; |
| 7278 | tdep->sizeof_gregset = 0; |
| 7279 | |
| 7280 | /* Floating-point registers. */ |
| 7281 | tdep->fpregset = NULL; |
| 7282 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
| 7283 | |
| 7284 | tdep->xstateregset = NULL; |
| 7285 | |
| 7286 | /* The default settings include the FPU registers, the MMX registers |
| 7287 | and the SSE registers. This can be overridden for a specific ABI |
| 7288 | by adjusting the members `st0_regnum', `mm0_regnum' and |
| 7289 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers |
| 7290 | will show up in the output of "info all-registers". */ |
| 7291 | |
| 7292 | tdep->st0_regnum = I386_ST0_REGNUM; |
| 7293 | |
| 7294 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
| 7295 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; |
| 7296 | |
| 7297 | tdep->jb_pc_offset = -1; |
| 7298 | tdep->struct_return = pcc_struct_return; |
| 7299 | tdep->sigtramp_start = 0; |
| 7300 | tdep->sigtramp_end = 0; |
| 7301 | tdep->sigtramp_p = i386_sigtramp_p; |
| 7302 | tdep->sigcontext_addr = NULL; |
| 7303 | tdep->sc_reg_offset = NULL; |
| 7304 | tdep->sc_pc_offset = -1; |
| 7305 | tdep->sc_sp_offset = -1; |
| 7306 | |
| 7307 | tdep->xsave_xcr0_offset = -1; |
| 7308 | |
| 7309 | tdep->record_regmap = i386_record_regmap; |
| 7310 | |
| 7311 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
| 7312 | |
| 7313 | /* The format used for `long double' on almost all i386 targets is |
| 7314 | the i387 extended floating-point format. In fact, of all targets |
| 7315 | in the GCC 2.95 tree, only OSF/1 does it different, and insists |
| 7316 | on having a `long double' that's not `long' at all. */ |
| 7317 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); |
| 7318 | |
| 7319 | /* Although the i387 extended floating-point has only 80 significant |
| 7320 | bits, a `long double' actually takes up 96, probably to enforce |
| 7321 | alignment. */ |
| 7322 | set_gdbarch_long_double_bit (gdbarch, 96); |
| 7323 | |
| 7324 | /* Register numbers of various important registers. */ |
| 7325 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ |
| 7326 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ |
| 7327 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ |
| 7328 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ |
| 7329 | |
| 7330 | /* NOTE: kettenis/20040418: GCC does have two possible register |
| 7331 | numbering schemes on the i386: dbx and SVR4. These schemes |
| 7332 | differ in how they number %ebp, %esp, %eflags, and the |
| 7333 | floating-point registers, and are implemented by the arrays |
| 7334 | dbx_register_map[] and svr4_dbx_register_map in |
| 7335 | gcc/config/i386.c. GCC also defines a third numbering scheme in |
| 7336 | gcc/config/i386.c, which it designates as the "default" register |
| 7337 | map used in 64bit mode. This last register numbering scheme is |
| 7338 | implemented in dbx64_register_map, and is used for AMD64; see |
| 7339 | amd64-tdep.c. |
| 7340 | |
| 7341 | Currently, each GCC i386 target always uses the same register |
| 7342 | numbering scheme across all its supported debugging formats |
| 7343 | i.e. SDB (COFF), stabs and DWARF 2. This is because |
| 7344 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the |
| 7345 | DBX_REGISTER_NUMBER macro which is defined by each target's |
| 7346 | respective config header in a manner independent of the requested |
| 7347 | output debugging format. |
| 7348 | |
| 7349 | This does not match the arrangement below, which presumes that |
| 7350 | the SDB and stabs numbering schemes differ from the DWARF and |
| 7351 | DWARF 2 ones. The reason for this arrangement is that it is |
| 7352 | likely to get the numbering scheme for the target's |
| 7353 | default/native debug format right. For targets where GCC is the |
| 7354 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for |
| 7355 | targets where the native toolchain uses a different numbering |
| 7356 | scheme for a particular debug format (stabs-in-ELF on Solaris) |
| 7357 | the defaults below will have to be overridden, like |
| 7358 | i386_elf_init_abi() does. */ |
| 7359 | |
| 7360 | /* Use the dbx register numbering scheme for stabs and COFF. */ |
| 7361 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); |
| 7362 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); |
| 7363 | |
| 7364 | /* Use the SVR4 register numbering scheme for DWARF 2. */ |
| 7365 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
| 7366 | |
| 7367 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to |
| 7368 | be in use on any of the supported i386 targets. */ |
| 7369 | |
| 7370 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); |
| 7371 | |
| 7372 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); |
| 7373 | |
| 7374 | /* Call dummy code. */ |
| 7375 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
| 7376 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
| 7377 | |
| 7378 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); |
| 7379 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); |
| 7380 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); |
| 7381 | |
| 7382 | set_gdbarch_return_value (gdbarch, i386_return_value); |
| 7383 | |
| 7384 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); |
| 7385 | |
| 7386 | /* Stack grows downward. */ |
| 7387 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 7388 | |
| 7389 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); |
| 7390 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
| 7391 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); |
| 7392 | |
| 7393 | set_gdbarch_frame_args_skip (gdbarch, 8); |
| 7394 | |
| 7395 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
| 7396 | |
| 7397 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); |
| 7398 | |
| 7399 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); |
| 7400 | |
| 7401 | /* Add the i386 register groups. */ |
| 7402 | i386_add_reggroups (gdbarch); |
| 7403 | tdep->register_reggroup_p = i386_register_reggroup_p; |
| 7404 | |
| 7405 | /* Helper for function argument information. */ |
| 7406 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); |
| 7407 | |
| 7408 | /* Hook the function epilogue frame unwinder. This unwinder is |
| 7409 | appended to the list first, so that it supercedes the DWARF |
| 7410 | unwinder in function epilogues (where the DWARF unwinder |
| 7411 | currently fails). */ |
| 7412 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); |
| 7413 | |
| 7414 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended |
| 7415 | to the list before the prologue-based unwinders, so that DWARF |
| 7416 | CFI info will be used if it is available. */ |
| 7417 | dwarf2_append_unwinders (gdbarch); |
| 7418 | |
| 7419 | frame_base_set_default (gdbarch, &i386_frame_base); |
| 7420 | |
| 7421 | /* Pseudo registers may be changed by amd64_init_abi. */ |
| 7422 | set_gdbarch_pseudo_register_read_value (gdbarch, |
| 7423 | i386_pseudo_register_read_value); |
| 7424 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
| 7425 | |
| 7426 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); |
| 7427 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); |
| 7428 | |
| 7429 | /* Override the normal target description method to make the AVX |
| 7430 | upper halves anonymous. */ |
| 7431 | set_gdbarch_register_name (gdbarch, i386_register_name); |
| 7432 | |
| 7433 | /* Even though the default ABI only includes general-purpose registers, |
| 7434 | floating-point registers and the SSE registers, we have to leave a |
| 7435 | gap for the upper AVX registers. */ |
| 7436 | set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); |
| 7437 | |
| 7438 | /* Get the x86 target description from INFO. */ |
| 7439 | tdesc = info.target_desc; |
| 7440 | if (! tdesc_has_registers (tdesc)) |
| 7441 | tdesc = tdesc_i386; |
| 7442 | tdep->tdesc = tdesc; |
| 7443 | |
| 7444 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; |
| 7445 | tdep->register_names = i386_register_names; |
| 7446 | |
| 7447 | /* No upper YMM registers. */ |
| 7448 | tdep->ymmh_register_names = NULL; |
| 7449 | tdep->ymm0h_regnum = -1; |
| 7450 | |
| 7451 | tdep->num_byte_regs = 8; |
| 7452 | tdep->num_word_regs = 8; |
| 7453 | tdep->num_dword_regs = 0; |
| 7454 | tdep->num_mmx_regs = 8; |
| 7455 | tdep->num_ymm_regs = 0; |
| 7456 | |
| 7457 | tdesc_data = tdesc_data_alloc (); |
| 7458 | |
| 7459 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
| 7460 | |
| 7461 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
| 7462 | |
| 7463 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 7464 | info.tdep_info = (void *) tdesc_data; |
| 7465 | gdbarch_init_osabi (info, gdbarch); |
| 7466 | |
| 7467 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
| 7468 | { |
| 7469 | tdesc_data_cleanup (tdesc_data); |
| 7470 | xfree (tdep); |
| 7471 | gdbarch_free (gdbarch); |
| 7472 | return NULL; |
| 7473 | } |
| 7474 | |
| 7475 | /* Wire in pseudo registers. Number of pseudo registers may be |
| 7476 | changed. */ |
| 7477 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs |
| 7478 | + tdep->num_word_regs |
| 7479 | + tdep->num_dword_regs |
| 7480 | + tdep->num_mmx_regs |
| 7481 | + tdep->num_ymm_regs)); |
| 7482 | |
| 7483 | /* Target description may be changed. */ |
| 7484 | tdesc = tdep->tdesc; |
| 7485 | |
| 7486 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
| 7487 | |
| 7488 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ |
| 7489 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); |
| 7490 | |
| 7491 | /* Make %al the first pseudo-register. */ |
| 7492 | tdep->al_regnum = gdbarch_num_regs (gdbarch); |
| 7493 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; |
| 7494 | |
| 7495 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
| 7496 | if (tdep->num_dword_regs) |
| 7497 | { |
| 7498 | /* Support dword pseudo-register if it hasn't been disabled. */ |
| 7499 | tdep->eax_regnum = ymm0_regnum; |
| 7500 | ymm0_regnum += tdep->num_dword_regs; |
| 7501 | } |
| 7502 | else |
| 7503 | tdep->eax_regnum = -1; |
| 7504 | |
| 7505 | mm0_regnum = ymm0_regnum; |
| 7506 | if (tdep->num_ymm_regs) |
| 7507 | { |
| 7508 | /* Support YMM pseudo-register if it is available. */ |
| 7509 | tdep->ymm0_regnum = ymm0_regnum; |
| 7510 | mm0_regnum += tdep->num_ymm_regs; |
| 7511 | } |
| 7512 | else |
| 7513 | tdep->ymm0_regnum = -1; |
| 7514 | |
| 7515 | if (tdep->num_mmx_regs != 0) |
| 7516 | { |
| 7517 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
| 7518 | tdep->mm0_regnum = mm0_regnum; |
| 7519 | } |
| 7520 | else |
| 7521 | tdep->mm0_regnum = -1; |
| 7522 | |
| 7523 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
| 7524 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
| 7525 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
| 7526 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); |
| 7527 | |
| 7528 | /* If we have a register mapping, enable the generic core file |
| 7529 | support, unless it has already been enabled. */ |
| 7530 | if (tdep->gregset_reg_offset |
| 7531 | && !gdbarch_regset_from_core_section_p (gdbarch)) |
| 7532 | set_gdbarch_regset_from_core_section (gdbarch, |
| 7533 | i386_regset_from_core_section); |
| 7534 | |
| 7535 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
| 7536 | i386_skip_permanent_breakpoint); |
| 7537 | |
| 7538 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
| 7539 | i386_fast_tracepoint_valid_at); |
| 7540 | |
| 7541 | return gdbarch; |
| 7542 | } |
| 7543 | |
| 7544 | static enum gdb_osabi |
| 7545 | i386_coff_osabi_sniffer (bfd *abfd) |
| 7546 | { |
| 7547 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
| 7548 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) |
| 7549 | return GDB_OSABI_GO32; |
| 7550 | |
| 7551 | return GDB_OSABI_UNKNOWN; |
| 7552 | } |
| 7553 | \f |
| 7554 | |
| 7555 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
| 7556 | void _initialize_i386_tdep (void); |
| 7557 | |
| 7558 | void |
| 7559 | _initialize_i386_tdep (void) |
| 7560 | { |
| 7561 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
| 7562 | |
| 7563 | /* Add the variable that controls the disassembly flavor. */ |
| 7564 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
| 7565 | &disassembly_flavor, _("\ |
| 7566 | Set the disassembly flavor."), _("\ |
| 7567 | Show the disassembly flavor."), _("\ |
| 7568 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), |
| 7569 | NULL, |
| 7570 | NULL, /* FIXME: i18n: */ |
| 7571 | &setlist, &showlist); |
| 7572 | |
| 7573 | /* Add the variable that controls the convention for returning |
| 7574 | structs. */ |
| 7575 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
| 7576 | &struct_convention, _("\ |
| 7577 | Set the convention for returning small structs."), _("\ |
| 7578 | Show the convention for returning small structs."), _("\ |
| 7579 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ |
| 7580 | is \"default\"."), |
| 7581 | NULL, |
| 7582 | NULL, /* FIXME: i18n: */ |
| 7583 | &setlist, &showlist); |
| 7584 | |
| 7585 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, |
| 7586 | i386_coff_osabi_sniffer); |
| 7587 | |
| 7588 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
| 7589 | i386_svr4_init_abi); |
| 7590 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
| 7591 | i386_go32_init_abi); |
| 7592 | |
| 7593 | /* Initialize the i386-specific register groups. */ |
| 7594 | i386_init_reggroups (); |
| 7595 | |
| 7596 | /* Initialize the standard target descriptions. */ |
| 7597 | initialize_tdesc_i386 (); |
| 7598 | initialize_tdesc_i386_mmx (); |
| 7599 | initialize_tdesc_i386_avx (); |
| 7600 | |
| 7601 | /* Tell remote stub that we support XML target description. */ |
| 7602 | register_remote_support_xml ("i386"); |
| 7603 | } |