| 1 | /* Target-machine dependent code for the Intel 960 |
| 2 | Copyright (C) 1991 Free Software Foundation, Inc. |
| 3 | Contributed by Intel Corporation. |
| 4 | examine_prologue and other parts contributed by Wind River Systems. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 2 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program; if not, write to the Free Software |
| 20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
| 21 | |
| 22 | /* Miscellaneous i80960-dependent routines. |
| 23 | Most are called from macros defined in "tm-i960.h". */ |
| 24 | |
| 25 | #include "defs.h" |
| 26 | #include <signal.h> |
| 27 | #include "symtab.h" |
| 28 | #include "value.h" |
| 29 | #include "frame.h" |
| 30 | #include "ieee-float.h" |
| 31 | |
| 32 | /* Structure of i960 extended floating point format. */ |
| 33 | |
| 34 | const struct ext_format ext_format_i960 = { |
| 35 | /* tot sbyte smask expbyte manbyte */ |
| 36 | 12, 9, 0x80, 9,8, 4,0, /* i960 */ |
| 37 | }; |
| 38 | |
| 39 | /* gdb960 is always running on a non-960 host. Check its characteristics. |
| 40 | This routine must be called as part of gdb initialization. */ |
| 41 | |
| 42 | static void |
| 43 | check_host() |
| 44 | { |
| 45 | int i; |
| 46 | |
| 47 | static struct typestruct { |
| 48 | int hostsize; /* Size of type on host */ |
| 49 | int i960size; /* Size of type on i960 */ |
| 50 | char *typename; /* Name of type, for error msg */ |
| 51 | } types[] = { |
| 52 | { sizeof(short), 2, "short" }, |
| 53 | { sizeof(int), 4, "int" }, |
| 54 | { sizeof(long), 4, "long" }, |
| 55 | { sizeof(float), 4, "float" }, |
| 56 | { sizeof(double), 8, "double" }, |
| 57 | { sizeof(char *), 4, "pointer" }, |
| 58 | }; |
| 59 | #define TYPELEN (sizeof(types) / sizeof(struct typestruct)) |
| 60 | |
| 61 | /* Make sure that host type sizes are same as i960 |
| 62 | */ |
| 63 | for ( i = 0; i < TYPELEN; i++ ){ |
| 64 | if ( types[i].hostsize != types[i].i960size ){ |
| 65 | printf("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n", |
| 66 | types[i].typename, types[i].i960size ); |
| 67 | } |
| 68 | |
| 69 | } |
| 70 | } |
| 71 | \f |
| 72 | /* Examine an i960 function prologue, recording the addresses at which |
| 73 | registers are saved explicitly by the prologue code, and returning |
| 74 | the address of the first instruction after the prologue (but not |
| 75 | after the instruction at address LIMIT, as explained below). |
| 76 | |
| 77 | LIMIT places an upper bound on addresses of the instructions to be |
| 78 | examined. If the prologue code scan reaches LIMIT, the scan is |
| 79 | aborted and LIMIT is returned. This is used, when examining the |
| 80 | prologue for the current frame, to keep examine_prologue () from |
| 81 | claiming that a given register has been saved when in fact the |
| 82 | instruction that saves it has not yet been executed. LIMIT is used |
| 83 | at other times to stop the scan when we hit code after the true |
| 84 | function prologue (e.g. for the first source line) which might |
| 85 | otherwise be mistaken for function prologue. |
| 86 | |
| 87 | The format of the function prologue matched by this routine is |
| 88 | derived from examination of the source to gcc960 1.21, particularly |
| 89 | the routine i960_function_prologue (). A "regular expression" for |
| 90 | the function prologue is given below: |
| 91 | |
| 92 | (lda LRn, g14 |
| 93 | mov g14, g[0-7] |
| 94 | (mov 0, g14) | (lda 0, g14))? |
| 95 | |
| 96 | (mov[qtl]? g[0-15], r[4-15])* |
| 97 | ((addo [1-31], sp, sp) | (lda n(sp), sp))? |
| 98 | (st[qtl]? g[0-15], n(fp))* |
| 99 | |
| 100 | (cmpobne 0, g14, LFn |
| 101 | mov sp, g14 |
| 102 | lda 0x30(sp), sp |
| 103 | LFn: stq g0, (g14) |
| 104 | stq g4, 0x10(g14) |
| 105 | stq g8, 0x20(g14))? |
| 106 | |
| 107 | (st g14, n(fp))? |
| 108 | (mov g13,r[4-15])? |
| 109 | */ |
| 110 | |
| 111 | /* Macros for extracting fields from i960 instructions. */ |
| 112 | |
| 113 | #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos)) |
| 114 | #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width)) |
| 115 | |
| 116 | #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5) |
| 117 | #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5) |
| 118 | #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) |
| 119 | #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) |
| 120 | #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12) |
| 121 | |
| 122 | /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or |
| 123 | is not the address of a valid instruction, the address of the next |
| 124 | instruction beyond ADDR otherwise. *PWORD1 receives the first word |
| 125 | of the instruction, and (for two-word instructions), *PWORD2 receives |
| 126 | the second. */ |
| 127 | |
| 128 | #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \ |
| 129 | (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0) |
| 130 | |
| 131 | static CORE_ADDR |
| 132 | examine_prologue (ip, limit, frame_addr, fsr) |
| 133 | register CORE_ADDR ip; |
| 134 | register CORE_ADDR limit; |
| 135 | FRAME_ADDR frame_addr; |
| 136 | struct frame_saved_regs *fsr; |
| 137 | { |
| 138 | register CORE_ADDR next_ip; |
| 139 | register int src, dst; |
| 140 | register unsigned int *pcode; |
| 141 | unsigned int insn1, insn2; |
| 142 | int size; |
| 143 | int within_leaf_prologue; |
| 144 | CORE_ADDR save_addr; |
| 145 | static unsigned int varargs_prologue_code [] = |
| 146 | { |
| 147 | 0x3507a00c, /* cmpobne 0x0, g14, LFn */ |
| 148 | 0x5cf01601, /* mov sp, g14 */ |
| 149 | 0x8c086030, /* lda 0x30(sp), sp */ |
| 150 | 0xb2879000, /* LFn: stq g0, (g14) */ |
| 151 | 0xb2a7a010, /* stq g4, 0x10(g14) */ |
| 152 | 0xb2c7a020 /* stq g8, 0x20(g14) */ |
| 153 | }; |
| 154 | |
| 155 | /* Accept a leaf procedure prologue code fragment if present. |
| 156 | Note that ip might point to either the leaf or non-leaf |
| 157 | entry point; we look for the non-leaf entry point first: */ |
| 158 | |
| 159 | within_leaf_prologue = 0; |
| 160 | if ((next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2)) |
| 161 | && ((insn1 & 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */ |
| 162 | || (insn1 & 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */ |
| 163 | { |
| 164 | within_leaf_prologue = 1; |
| 165 | next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2); |
| 166 | } |
| 167 | |
| 168 | /* Now look for the prologue code at a leaf entry point: */ |
| 169 | |
| 170 | if (next_ip |
| 171 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
| 172 | && REG_SRCDST (insn1) <= G0_REGNUM + 7) |
| 173 | { |
| 174 | within_leaf_prologue = 1; |
| 175 | if ((next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2)) |
| 176 | && (insn1 == 0x8cf00000 /* lda 0, g14 */ |
| 177 | || insn1 == 0x5cf01e00)) /* mov 0, g14 */ |
| 178 | { |
| 179 | ip = next_ip; |
| 180 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 181 | within_leaf_prologue = 0; |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | /* If something that looks like the beginning of a leaf prologue |
| 186 | has been seen, but the remainder of the prologue is missing, bail. |
| 187 | We don't know what we've got. */ |
| 188 | |
| 189 | if (within_leaf_prologue) |
| 190 | return (ip); |
| 191 | |
| 192 | /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4. |
| 193 | This may cause us to mistake the moving of a register |
| 194 | parameter to a local register for the saving of a callee-saved |
| 195 | register, but that can't be helped, since with the |
| 196 | "-fcall-saved" flag, any register can be made callee-saved. */ |
| 197 | |
| 198 | while (next_ip |
| 199 | && (insn1 & 0xfc802fb0) == 0x5c000610 |
| 200 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) |
| 201 | { |
| 202 | src = REG_SRC1 (insn1); |
| 203 | size = EXTRACT_FIELD (insn1, 24, 2) + 1; |
| 204 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); |
| 205 | while (size--) |
| 206 | { |
| 207 | fsr->regs[src++] = save_addr; |
| 208 | save_addr += 4; |
| 209 | } |
| 210 | ip = next_ip; |
| 211 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 212 | } |
| 213 | |
| 214 | /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */ |
| 215 | |
| 216 | if (next_ip && |
| 217 | ((insn1 & 0xffffffe0) == 0x59084800 /* addo n, sp, sp */ |
| 218 | || (insn1 & 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */ |
| 219 | || (insn1 & 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */ |
| 220 | { |
| 221 | ip = next_ip; |
| 222 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 223 | } |
| 224 | |
| 225 | /* Accept zero or more instances of "st[qtl]? gx, n(fp)". |
| 226 | This may cause us to mistake the copying of a register |
| 227 | parameter to the frame for the saving of a callee-saved |
| 228 | register, but that can't be helped, since with the |
| 229 | "-fcall-saved" flag, any register can be made callee-saved. |
| 230 | We can, however, refuse to accept a save of register g14, |
| 231 | since that is matched explicitly below. */ |
| 232 | |
| 233 | while (next_ip && |
| 234 | ((insn1 & 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */ |
| 235 | || (insn1 & 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */ |
| 236 | || (insn1 & 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */ |
| 237 | || (insn1 & 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */ |
| 238 | && ((src = MEM_SRCDST (insn1)) != G14_REGNUM)) |
| 239 | { |
| 240 | save_addr = frame_addr + ((insn1 & BITMASK (12, 1)) |
| 241 | ? insn2 : MEMA_OFFSET (insn1)); |
| 242 | size = (insn1 & BITMASK (29, 1)) ? ((insn1 & BITMASK (28, 1)) ? 4 : 3) |
| 243 | : ((insn1 & BITMASK (27, 1)) ? 2 : 1); |
| 244 | while (size--) |
| 245 | { |
| 246 | fsr->regs[src++] = save_addr; |
| 247 | save_addr += 4; |
| 248 | } |
| 249 | ip = next_ip; |
| 250 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 251 | } |
| 252 | |
| 253 | /* Accept the varargs prologue code if present. */ |
| 254 | |
| 255 | size = sizeof (varargs_prologue_code) / sizeof (int); |
| 256 | pcode = varargs_prologue_code; |
| 257 | while (size-- && next_ip && *pcode++ == insn1) |
| 258 | { |
| 259 | ip = next_ip; |
| 260 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 261 | } |
| 262 | |
| 263 | /* Accept an optional "st g14, n(fp)". */ |
| 264 | |
| 265 | if (next_ip && |
| 266 | ((insn1 & 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */ |
| 267 | || (insn1 & 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */ |
| 268 | { |
| 269 | fsr->regs[G14_REGNUM] = frame_addr + ((insn1 & BITMASK (12, 1)) |
| 270 | ? insn2 : MEMA_OFFSET (insn1)); |
| 271 | ip = next_ip; |
| 272 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 273 | } |
| 274 | |
| 275 | /* Accept zero or one instance of "mov g13, ry", where y >= 4. |
| 276 | This is saving the address where a struct should be returned. */ |
| 277 | |
| 278 | if (next_ip |
| 279 | && (insn1 & 0xff802fbf) == 0x5c00061d |
| 280 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) |
| 281 | { |
| 282 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); |
| 283 | fsr->regs[G0_REGNUM+13] = save_addr; |
| 284 | ip = next_ip; |
| 285 | #if 0 /* We'll need this once there is a subsequent instruction examined. */ |
| 286 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 287 | #endif |
| 288 | } |
| 289 | |
| 290 | return (ip); |
| 291 | } |
| 292 | |
| 293 | /* Given an ip value corresponding to the start of a function, |
| 294 | return the ip of the first instruction after the function |
| 295 | prologue. */ |
| 296 | |
| 297 | CORE_ADDR |
| 298 | skip_prologue (ip) |
| 299 | CORE_ADDR (ip); |
| 300 | { |
| 301 | struct frame_saved_regs saved_regs_dummy; |
| 302 | struct symtab_and_line sal; |
| 303 | CORE_ADDR limit; |
| 304 | |
| 305 | sal = find_pc_line (ip, 0); |
| 306 | limit = (sal.end) ? sal.end : 0xffffffff; |
| 307 | |
| 308 | return (examine_prologue (ip, limit, (FRAME_ADDR) 0, &saved_regs_dummy)); |
| 309 | } |
| 310 | |
| 311 | /* Put here the code to store, into a struct frame_saved_regs, |
| 312 | the addresses of the saved registers of frame described by FRAME_INFO. |
| 313 | This includes special registers such as pc and fp saved in special |
| 314 | ways in the stack frame. sp is even more special: |
| 315 | the address we return for it IS the sp for the next frame. |
| 316 | |
| 317 | We cache the result of doing this in the frame_cache_obstack, since |
| 318 | it is fairly expensive. */ |
| 319 | |
| 320 | void |
| 321 | frame_find_saved_regs (fi, fsr) |
| 322 | struct frame_info *fi; |
| 323 | struct frame_saved_regs *fsr; |
| 324 | { |
| 325 | register CORE_ADDR next_addr; |
| 326 | register CORE_ADDR *saved_regs; |
| 327 | register int regnum; |
| 328 | register struct frame_saved_regs *cache_fsr; |
| 329 | extern struct obstack frame_cache_obstack; |
| 330 | CORE_ADDR ip; |
| 331 | struct symtab_and_line sal; |
| 332 | CORE_ADDR limit; |
| 333 | |
| 334 | if (!fi->fsr) |
| 335 | { |
| 336 | cache_fsr = (struct frame_saved_regs *) |
| 337 | obstack_alloc (&frame_cache_obstack, |
| 338 | sizeof (struct frame_saved_regs)); |
| 339 | bzero (cache_fsr, sizeof (struct frame_saved_regs)); |
| 340 | fi->fsr = cache_fsr; |
| 341 | |
| 342 | /* Find the start and end of the function prologue. If the PC |
| 343 | is in the function prologue, we only consider the part that |
| 344 | has executed already. */ |
| 345 | |
| 346 | ip = get_pc_function_start (fi->pc); |
| 347 | sal = find_pc_line (ip, 0); |
| 348 | limit = (sal.end && sal.end < fi->pc) ? sal.end: fi->pc; |
| 349 | |
| 350 | examine_prologue (ip, limit, fi->frame, cache_fsr); |
| 351 | |
| 352 | /* Record the addresses at which the local registers are saved. |
| 353 | Strictly speaking, we should only do this for non-leaf procedures, |
| 354 | but no one will ever look at these values if it is a leaf procedure, |
| 355 | since local registers are always caller-saved. */ |
| 356 | |
| 357 | next_addr = (CORE_ADDR) fi->frame; |
| 358 | saved_regs = cache_fsr->regs; |
| 359 | for (regnum = R0_REGNUM; regnum <= R15_REGNUM; regnum++) |
| 360 | { |
| 361 | *saved_regs++ = next_addr; |
| 362 | next_addr += 4; |
| 363 | } |
| 364 | |
| 365 | cache_fsr->regs[FP_REGNUM] = cache_fsr->regs[PFP_REGNUM]; |
| 366 | } |
| 367 | |
| 368 | *fsr = *fi->fsr; |
| 369 | |
| 370 | /* Fetch the value of the sp from memory every time, since it |
| 371 | is conceivable that it has changed since the cache was flushed. |
| 372 | This unfortunately undoes much of the savings from caching the |
| 373 | saved register values. I suggest adding an argument to |
| 374 | get_frame_saved_regs () specifying the register number we're |
| 375 | interested in (or -1 for all registers). This would be passed |
| 376 | through to FRAME_FIND_SAVED_REGS (), permitting more efficient |
| 377 | computation of saved register addresses (e.g., on the i960, |
| 378 | we don't have to examine the prologue to find local registers). |
| 379 | -- markf@wrs.com |
| 380 | FIXME, we don't need to refetch this, since the cache is cleared |
| 381 | every time the child process is restarted. If GDB itself |
| 382 | modifies SP, it has to clear the cache by hand (does it?). -gnu */ |
| 383 | |
| 384 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[SP_REGNUM], 4); |
| 385 | } |
| 386 | |
| 387 | /* Return the address of the argument block for the frame |
| 388 | described by FI. Returns 0 if the address is unknown. */ |
| 389 | |
| 390 | CORE_ADDR |
| 391 | frame_args_address (fi, must_be_correct) |
| 392 | struct frame_info *fi; |
| 393 | { |
| 394 | register FRAME frame; |
| 395 | struct frame_saved_regs fsr; |
| 396 | CORE_ADDR ap; |
| 397 | |
| 398 | /* If g14 was saved in the frame by the function prologue code, return |
| 399 | the saved value. If the frame is current and we are being sloppy, |
| 400 | return the value of g14. Otherwise, return zero. */ |
| 401 | |
| 402 | frame = FRAME_INFO_ID (fi); |
| 403 | get_frame_saved_regs (fi, &fsr); |
| 404 | if (fsr.regs[G14_REGNUM]) |
| 405 | ap = read_memory_integer (fsr.regs[G14_REGNUM],4); |
| 406 | else { |
| 407 | if (must_be_correct) |
| 408 | return 0; /* Don't cache this result */ |
| 409 | if (get_next_frame (frame)) |
| 410 | ap = 0; |
| 411 | else |
| 412 | ap = read_register (G14_REGNUM); |
| 413 | if (ap == 0) |
| 414 | ap = fi->frame; |
| 415 | } |
| 416 | fi->arg_pointer = ap; /* Cache it for next time */ |
| 417 | return ap; |
| 418 | } |
| 419 | |
| 420 | /* Return the address of the return struct for the frame |
| 421 | described by FI. Returns 0 if the address is unknown. */ |
| 422 | |
| 423 | CORE_ADDR |
| 424 | frame_struct_result_address (fi) |
| 425 | struct frame_info *fi; |
| 426 | { |
| 427 | register FRAME frame; |
| 428 | struct frame_saved_regs fsr; |
| 429 | CORE_ADDR ap; |
| 430 | |
| 431 | /* If the frame is non-current, check to see if g14 was saved in the |
| 432 | frame by the function prologue code; return the saved value if so, |
| 433 | zero otherwise. If the frame is current, return the value of g14. |
| 434 | |
| 435 | FIXME, shouldn't this use the saved value as long as we are past |
| 436 | the function prologue, and only use the current value if we have |
| 437 | no saved value and are at TOS? -- gnu@cygnus.com */ |
| 438 | |
| 439 | frame = FRAME_INFO_ID (fi); |
| 440 | if (get_next_frame (frame)) { |
| 441 | get_frame_saved_regs (fi, &fsr); |
| 442 | if (fsr.regs[G13_REGNUM]) |
| 443 | ap = read_memory_integer (fsr.regs[G13_REGNUM],4); |
| 444 | else |
| 445 | ap = 0; |
| 446 | } else { |
| 447 | ap = read_register (G13_REGNUM); |
| 448 | } |
| 449 | return ap; |
| 450 | } |
| 451 | |
| 452 | /* Return address to which the currently executing leafproc will return, |
| 453 | or 0 if ip is not in a leafproc (or if we can't tell if it is). |
| 454 | |
| 455 | Do this by finding the starting address of the routine in which ip lies. |
| 456 | If the instruction there is "mov g14, gx" (where x is in [0,7]), this |
| 457 | is a leafproc and the return address is in register gx. Well, this is |
| 458 | true unless the return address points at a RET instruction in the current |
| 459 | procedure, which indicates that we have a 'dual entry' routine that |
| 460 | has been entered through the CALL entry point. */ |
| 461 | |
| 462 | CORE_ADDR |
| 463 | leafproc_return (ip) |
| 464 | CORE_ADDR ip; /* ip from currently executing function */ |
| 465 | { |
| 466 | register struct minimal_symbol *msymbol; |
| 467 | char *p; |
| 468 | int dst; |
| 469 | unsigned int insn1, insn2; |
| 470 | CORE_ADDR return_addr; |
| 471 | char *index (); |
| 472 | |
| 473 | if ((msymbol = lookup_minimal_symbol_by_pc (ip)) != NULL) |
| 474 | { |
| 475 | if ((p = index (SYMBOL_NAME (msymbol), '.')) && STREQ (p, ".lf")) |
| 476 | { |
| 477 | if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol), &insn1, &insn2) |
| 478 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
| 479 | && (dst = REG_SRCDST (insn1)) <= G0_REGNUM + 7) |
| 480 | { |
| 481 | /* Get the return address. If the "mov g14, gx" |
| 482 | instruction hasn't been executed yet, read |
| 483 | the return address from g14; otherwise, read it |
| 484 | from the register into which g14 was moved. */ |
| 485 | |
| 486 | return_addr = |
| 487 | read_register ((ip == SYMBOL_VALUE_ADDRESS (msymbol)) |
| 488 | ? G14_REGNUM : dst); |
| 489 | |
| 490 | /* We know we are in a leaf procedure, but we don't know |
| 491 | whether the caller actually did a "bal" to the ".lf" |
| 492 | entry point, or a normal "call" to the non-leaf entry |
| 493 | point one instruction before. In the latter case, the |
| 494 | return address will be the address of a "ret" |
| 495 | instruction within the procedure itself. We test for |
| 496 | this below. */ |
| 497 | |
| 498 | if (!next_insn (return_addr, &insn1, &insn2) |
| 499 | || (insn1 & 0xff000000) != 0xa000000 /* ret */ |
| 500 | || lookup_minimal_symbol_by_pc (return_addr) != msymbol) |
| 501 | return (return_addr); |
| 502 | } |
| 503 | } |
| 504 | } |
| 505 | |
| 506 | return (0); |
| 507 | } |
| 508 | |
| 509 | /* Immediately after a function call, return the saved pc. |
| 510 | Can't go through the frames for this because on some machines |
| 511 | the new frame is not set up until the new function executes |
| 512 | some instructions. |
| 513 | On the i960, the frame *is* set up immediately after the call, |
| 514 | unless the function is a leaf procedure. */ |
| 515 | |
| 516 | CORE_ADDR |
| 517 | saved_pc_after_call (frame) |
| 518 | FRAME frame; |
| 519 | { |
| 520 | CORE_ADDR saved_pc; |
| 521 | CORE_ADDR get_frame_pc (); |
| 522 | |
| 523 | saved_pc = leafproc_return (get_frame_pc (frame)); |
| 524 | if (!saved_pc) |
| 525 | saved_pc = FRAME_SAVED_PC (frame); |
| 526 | |
| 527 | return (saved_pc); |
| 528 | } |
| 529 | |
| 530 | /* Discard from the stack the innermost frame, |
| 531 | restoring all saved registers. */ |
| 532 | |
| 533 | pop_frame () |
| 534 | { |
| 535 | register struct frame_info *current_fi, *prev_fi; |
| 536 | register int i; |
| 537 | CORE_ADDR save_addr; |
| 538 | CORE_ADDR leaf_return_addr; |
| 539 | struct frame_saved_regs fsr; |
| 540 | char local_regs_buf[16 * 4]; |
| 541 | |
| 542 | current_fi = get_frame_info (get_current_frame ()); |
| 543 | |
| 544 | /* First, undo what the hardware does when we return. |
| 545 | If this is a non-leaf procedure, restore local registers from |
| 546 | the save area in the calling frame. Otherwise, load the return |
| 547 | address obtained from leafproc_return () into the rip. */ |
| 548 | |
| 549 | leaf_return_addr = leafproc_return (current_fi->pc); |
| 550 | if (!leaf_return_addr) |
| 551 | { |
| 552 | /* Non-leaf procedure. Restore local registers, incl IP. */ |
| 553 | prev_fi = get_frame_info (get_prev_frame (FRAME_INFO_ID (current_fi))); |
| 554 | read_memory (prev_fi->frame, local_regs_buf, sizeof (local_regs_buf)); |
| 555 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), local_regs_buf, |
| 556 | sizeof (local_regs_buf)); |
| 557 | |
| 558 | /* Restore frame pointer. */ |
| 559 | write_register (FP_REGNUM, prev_fi->frame); |
| 560 | } |
| 561 | else |
| 562 | { |
| 563 | /* Leaf procedure. Just restore the return address into the IP. */ |
| 564 | write_register (RIP_REGNUM, leaf_return_addr); |
| 565 | } |
| 566 | |
| 567 | /* Now restore any global regs that the current function had saved. */ |
| 568 | get_frame_saved_regs (current_fi, &fsr); |
| 569 | for (i = G0_REGNUM; i < G14_REGNUM; i++) |
| 570 | { |
| 571 | if (save_addr = fsr.regs[i]) |
| 572 | write_register (i, read_memory_integer (save_addr, 4)); |
| 573 | } |
| 574 | |
| 575 | /* Flush the frame cache, create a frame for the new innermost frame, |
| 576 | and make it the current frame. */ |
| 577 | |
| 578 | flush_cached_frames (); |
| 579 | set_current_frame (create_new_frame (read_register (FP_REGNUM), read_pc ())); |
| 580 | } |
| 581 | |
| 582 | /* Print out text describing a "signal number" with which the i80960 halted. |
| 583 | |
| 584 | See the file "fault.c" in the nindy monitor source code for a list |
| 585 | of stop codes. */ |
| 586 | |
| 587 | void |
| 588 | print_fault( siggnal ) |
| 589 | int siggnal; /* Signal number, as returned by target_wait() */ |
| 590 | { |
| 591 | static char unknown[] = "Unknown fault or trace"; |
| 592 | static char *sigmsgs[] = { |
| 593 | /* FAULTS */ |
| 594 | "parallel fault", /* 0x00 */ |
| 595 | unknown, /* 0x01 */ |
| 596 | "operation fault", /* 0x02 */ |
| 597 | "arithmetic fault", /* 0x03 */ |
| 598 | "floating point fault", /* 0x04 */ |
| 599 | "constraint fault", /* 0x05 */ |
| 600 | "virtual memory fault", /* 0x06 */ |
| 601 | "protection fault", /* 0x07 */ |
| 602 | "machine fault", /* 0x08 */ |
| 603 | "structural fault", /* 0x09 */ |
| 604 | "type fault", /* 0x0a */ |
| 605 | "reserved (0xb) fault", /* 0x0b */ |
| 606 | "process fault", /* 0x0c */ |
| 607 | "descriptor fault", /* 0x0d */ |
| 608 | "event fault", /* 0x0e */ |
| 609 | "reserved (0xf) fault", /* 0x0f */ |
| 610 | |
| 611 | /* TRACES */ |
| 612 | "single-step trace", /* 0x10 */ |
| 613 | "branch trace", /* 0x11 */ |
| 614 | "call trace", /* 0x12 */ |
| 615 | "return trace", /* 0x13 */ |
| 616 | "pre-return trace", /* 0x14 */ |
| 617 | "supervisor call trace",/* 0x15 */ |
| 618 | "breakpoint trace", /* 0x16 */ |
| 619 | }; |
| 620 | # define NUMMSGS ((int)( sizeof(sigmsgs) / sizeof(sigmsgs[0]) )) |
| 621 | |
| 622 | if (siggnal < NSIG) { |
| 623 | printf ("\nProgram received signal %d, %s\n", |
| 624 | siggnal, safe_strsignal (siggnal)); |
| 625 | } else { |
| 626 | /* The various target_wait()s bias the 80960 "signal number" |
| 627 | by adding NSIG to it, so it won't get confused with any |
| 628 | of the Unix signals elsewhere in GDB. We need to |
| 629 | "unbias" it before using it. */ |
| 630 | siggnal -= NSIG; |
| 631 | |
| 632 | printf("Program stopped for reason #%d: %s.\n", siggnal, |
| 633 | (siggnal < NUMMSGS && siggnal >= 0)? |
| 634 | sigmsgs[siggnal] : unknown ); |
| 635 | } |
| 636 | } |
| 637 | |
| 638 | /* Initialization stub */ |
| 639 | |
| 640 | _initialize_i960_tdep () |
| 641 | { |
| 642 | check_host (); |
| 643 | } |