| 1 | /* Target-machine dependent code for the Intel 960 |
| 2 | Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. |
| 3 | Contributed by Intel Corporation. |
| 4 | examine_prologue and other parts contributed by Wind River Systems. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 2 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program; if not, write to the Free Software |
| 20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
| 21 | |
| 22 | #include "defs.h" |
| 23 | #include "symtab.h" |
| 24 | #include "value.h" |
| 25 | #include "frame.h" |
| 26 | #include "floatformat.h" |
| 27 | #include "target.h" |
| 28 | |
| 29 | static CORE_ADDR next_insn PARAMS ((CORE_ADDR memaddr, |
| 30 | unsigned long *pword1, |
| 31 | unsigned long *pword2)); |
| 32 | |
| 33 | /* gdb960 is always running on a non-960 host. Check its characteristics. |
| 34 | This routine must be called as part of gdb initialization. */ |
| 35 | |
| 36 | static void |
| 37 | check_host() |
| 38 | { |
| 39 | int i; |
| 40 | |
| 41 | static struct typestruct { |
| 42 | int hostsize; /* Size of type on host */ |
| 43 | int i960size; /* Size of type on i960 */ |
| 44 | char *typename; /* Name of type, for error msg */ |
| 45 | } types[] = { |
| 46 | { sizeof(short), 2, "short" }, |
| 47 | { sizeof(int), 4, "int" }, |
| 48 | { sizeof(long), 4, "long" }, |
| 49 | { sizeof(float), 4, "float" }, |
| 50 | { sizeof(double), 8, "double" }, |
| 51 | { sizeof(char *), 4, "pointer" }, |
| 52 | }; |
| 53 | #define TYPELEN (sizeof(types) / sizeof(struct typestruct)) |
| 54 | |
| 55 | /* Make sure that host type sizes are same as i960 |
| 56 | */ |
| 57 | for ( i = 0; i < TYPELEN; i++ ){ |
| 58 | if ( types[i].hostsize != types[i].i960size ){ |
| 59 | printf_unfiltered("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n", |
| 60 | types[i].typename, types[i].i960size ); |
| 61 | } |
| 62 | |
| 63 | } |
| 64 | } |
| 65 | \f |
| 66 | /* Examine an i960 function prologue, recording the addresses at which |
| 67 | registers are saved explicitly by the prologue code, and returning |
| 68 | the address of the first instruction after the prologue (but not |
| 69 | after the instruction at address LIMIT, as explained below). |
| 70 | |
| 71 | LIMIT places an upper bound on addresses of the instructions to be |
| 72 | examined. If the prologue code scan reaches LIMIT, the scan is |
| 73 | aborted and LIMIT is returned. This is used, when examining the |
| 74 | prologue for the current frame, to keep examine_prologue () from |
| 75 | claiming that a given register has been saved when in fact the |
| 76 | instruction that saves it has not yet been executed. LIMIT is used |
| 77 | at other times to stop the scan when we hit code after the true |
| 78 | function prologue (e.g. for the first source line) which might |
| 79 | otherwise be mistaken for function prologue. |
| 80 | |
| 81 | The format of the function prologue matched by this routine is |
| 82 | derived from examination of the source to gcc960 1.21, particularly |
| 83 | the routine i960_function_prologue (). A "regular expression" for |
| 84 | the function prologue is given below: |
| 85 | |
| 86 | (lda LRn, g14 |
| 87 | mov g14, g[0-7] |
| 88 | (mov 0, g14) | (lda 0, g14))? |
| 89 | |
| 90 | (mov[qtl]? g[0-15], r[4-15])* |
| 91 | ((addo [1-31], sp, sp) | (lda n(sp), sp))? |
| 92 | (st[qtl]? g[0-15], n(fp))* |
| 93 | |
| 94 | (cmpobne 0, g14, LFn |
| 95 | mov sp, g14 |
| 96 | lda 0x30(sp), sp |
| 97 | LFn: stq g0, (g14) |
| 98 | stq g4, 0x10(g14) |
| 99 | stq g8, 0x20(g14))? |
| 100 | |
| 101 | (st g14, n(fp))? |
| 102 | (mov g13,r[4-15])? |
| 103 | */ |
| 104 | |
| 105 | /* Macros for extracting fields from i960 instructions. */ |
| 106 | |
| 107 | #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos)) |
| 108 | #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width)) |
| 109 | |
| 110 | #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5) |
| 111 | #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5) |
| 112 | #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) |
| 113 | #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) |
| 114 | #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12) |
| 115 | |
| 116 | /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or |
| 117 | is not the address of a valid instruction, the address of the next |
| 118 | instruction beyond ADDR otherwise. *PWORD1 receives the first word |
| 119 | of the instruction, and (for two-word instructions), *PWORD2 receives |
| 120 | the second. */ |
| 121 | |
| 122 | #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \ |
| 123 | (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0) |
| 124 | |
| 125 | static CORE_ADDR |
| 126 | examine_prologue (ip, limit, frame_addr, fsr) |
| 127 | register CORE_ADDR ip; |
| 128 | register CORE_ADDR limit; |
| 129 | CORE_ADDR frame_addr; |
| 130 | struct frame_saved_regs *fsr; |
| 131 | { |
| 132 | register CORE_ADDR next_ip; |
| 133 | register int src, dst; |
| 134 | register unsigned int *pcode; |
| 135 | unsigned int insn1, insn2; |
| 136 | int size; |
| 137 | int within_leaf_prologue; |
| 138 | CORE_ADDR save_addr; |
| 139 | static unsigned int varargs_prologue_code [] = |
| 140 | { |
| 141 | 0x3507a00c, /* cmpobne 0x0, g14, LFn */ |
| 142 | 0x5cf01601, /* mov sp, g14 */ |
| 143 | 0x8c086030, /* lda 0x30(sp), sp */ |
| 144 | 0xb2879000, /* LFn: stq g0, (g14) */ |
| 145 | 0xb2a7a010, /* stq g4, 0x10(g14) */ |
| 146 | 0xb2c7a020 /* stq g8, 0x20(g14) */ |
| 147 | }; |
| 148 | |
| 149 | /* Accept a leaf procedure prologue code fragment if present. |
| 150 | Note that ip might point to either the leaf or non-leaf |
| 151 | entry point; we look for the non-leaf entry point first: */ |
| 152 | |
| 153 | within_leaf_prologue = 0; |
| 154 | if ((next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2)) |
| 155 | && ((insn1 & 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */ |
| 156 | || (insn1 & 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */ |
| 157 | { |
| 158 | within_leaf_prologue = 1; |
| 159 | next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2); |
| 160 | } |
| 161 | |
| 162 | /* Now look for the prologue code at a leaf entry point: */ |
| 163 | |
| 164 | if (next_ip |
| 165 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
| 166 | && REG_SRCDST (insn1) <= G0_REGNUM + 7) |
| 167 | { |
| 168 | within_leaf_prologue = 1; |
| 169 | if ((next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2)) |
| 170 | && (insn1 == 0x8cf00000 /* lda 0, g14 */ |
| 171 | || insn1 == 0x5cf01e00)) /* mov 0, g14 */ |
| 172 | { |
| 173 | ip = next_ip; |
| 174 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 175 | within_leaf_prologue = 0; |
| 176 | } |
| 177 | } |
| 178 | |
| 179 | /* If something that looks like the beginning of a leaf prologue |
| 180 | has been seen, but the remainder of the prologue is missing, bail. |
| 181 | We don't know what we've got. */ |
| 182 | |
| 183 | if (within_leaf_prologue) |
| 184 | return (ip); |
| 185 | |
| 186 | /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4. |
| 187 | This may cause us to mistake the moving of a register |
| 188 | parameter to a local register for the saving of a callee-saved |
| 189 | register, but that can't be helped, since with the |
| 190 | "-fcall-saved" flag, any register can be made callee-saved. */ |
| 191 | |
| 192 | while (next_ip |
| 193 | && (insn1 & 0xfc802fb0) == 0x5c000610 |
| 194 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) |
| 195 | { |
| 196 | src = REG_SRC1 (insn1); |
| 197 | size = EXTRACT_FIELD (insn1, 24, 2) + 1; |
| 198 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); |
| 199 | while (size--) |
| 200 | { |
| 201 | fsr->regs[src++] = save_addr; |
| 202 | save_addr += 4; |
| 203 | } |
| 204 | ip = next_ip; |
| 205 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 206 | } |
| 207 | |
| 208 | /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */ |
| 209 | |
| 210 | if (next_ip && |
| 211 | ((insn1 & 0xffffffe0) == 0x59084800 /* addo n, sp, sp */ |
| 212 | || (insn1 & 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */ |
| 213 | || (insn1 & 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */ |
| 214 | { |
| 215 | ip = next_ip; |
| 216 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 217 | } |
| 218 | |
| 219 | /* Accept zero or more instances of "st[qtl]? gx, n(fp)". |
| 220 | This may cause us to mistake the copying of a register |
| 221 | parameter to the frame for the saving of a callee-saved |
| 222 | register, but that can't be helped, since with the |
| 223 | "-fcall-saved" flag, any register can be made callee-saved. |
| 224 | We can, however, refuse to accept a save of register g14, |
| 225 | since that is matched explicitly below. */ |
| 226 | |
| 227 | while (next_ip && |
| 228 | ((insn1 & 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */ |
| 229 | || (insn1 & 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */ |
| 230 | || (insn1 & 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */ |
| 231 | || (insn1 & 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */ |
| 232 | && ((src = MEM_SRCDST (insn1)) != G14_REGNUM)) |
| 233 | { |
| 234 | save_addr = frame_addr + ((insn1 & BITMASK (12, 1)) |
| 235 | ? insn2 : MEMA_OFFSET (insn1)); |
| 236 | size = (insn1 & BITMASK (29, 1)) ? ((insn1 & BITMASK (28, 1)) ? 4 : 3) |
| 237 | : ((insn1 & BITMASK (27, 1)) ? 2 : 1); |
| 238 | while (size--) |
| 239 | { |
| 240 | fsr->regs[src++] = save_addr; |
| 241 | save_addr += 4; |
| 242 | } |
| 243 | ip = next_ip; |
| 244 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 245 | } |
| 246 | |
| 247 | /* Accept the varargs prologue code if present. */ |
| 248 | |
| 249 | size = sizeof (varargs_prologue_code) / sizeof (int); |
| 250 | pcode = varargs_prologue_code; |
| 251 | while (size-- && next_ip && *pcode++ == insn1) |
| 252 | { |
| 253 | ip = next_ip; |
| 254 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 255 | } |
| 256 | |
| 257 | /* Accept an optional "st g14, n(fp)". */ |
| 258 | |
| 259 | if (next_ip && |
| 260 | ((insn1 & 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */ |
| 261 | || (insn1 & 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */ |
| 262 | { |
| 263 | fsr->regs[G14_REGNUM] = frame_addr + ((insn1 & BITMASK (12, 1)) |
| 264 | ? insn2 : MEMA_OFFSET (insn1)); |
| 265 | ip = next_ip; |
| 266 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 267 | } |
| 268 | |
| 269 | /* Accept zero or one instance of "mov g13, ry", where y >= 4. |
| 270 | This is saving the address where a struct should be returned. */ |
| 271 | |
| 272 | if (next_ip |
| 273 | && (insn1 & 0xff802fbf) == 0x5c00061d |
| 274 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) |
| 275 | { |
| 276 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); |
| 277 | fsr->regs[G0_REGNUM+13] = save_addr; |
| 278 | ip = next_ip; |
| 279 | #if 0 /* We'll need this once there is a subsequent instruction examined. */ |
| 280 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
| 281 | #endif |
| 282 | } |
| 283 | |
| 284 | return (ip); |
| 285 | } |
| 286 | |
| 287 | /* Given an ip value corresponding to the start of a function, |
| 288 | return the ip of the first instruction after the function |
| 289 | prologue. */ |
| 290 | |
| 291 | CORE_ADDR |
| 292 | skip_prologue (ip) |
| 293 | CORE_ADDR (ip); |
| 294 | { |
| 295 | struct frame_saved_regs saved_regs_dummy; |
| 296 | struct symtab_and_line sal; |
| 297 | CORE_ADDR limit; |
| 298 | |
| 299 | sal = find_pc_line (ip, 0); |
| 300 | limit = (sal.end) ? sal.end : 0xffffffff; |
| 301 | |
| 302 | return (examine_prologue (ip, limit, (CORE_ADDR) 0, &saved_regs_dummy)); |
| 303 | } |
| 304 | |
| 305 | /* Put here the code to store, into a struct frame_saved_regs, |
| 306 | the addresses of the saved registers of frame described by FRAME_INFO. |
| 307 | This includes special registers such as pc and fp saved in special |
| 308 | ways in the stack frame. sp is even more special: |
| 309 | the address we return for it IS the sp for the next frame. |
| 310 | |
| 311 | We cache the result of doing this in the frame_cache_obstack, since |
| 312 | it is fairly expensive. */ |
| 313 | |
| 314 | void |
| 315 | frame_find_saved_regs (fi, fsr) |
| 316 | struct frame_info *fi; |
| 317 | struct frame_saved_regs *fsr; |
| 318 | { |
| 319 | register CORE_ADDR next_addr; |
| 320 | register CORE_ADDR *saved_regs; |
| 321 | register int regnum; |
| 322 | register struct frame_saved_regs *cache_fsr; |
| 323 | extern struct obstack frame_cache_obstack; |
| 324 | CORE_ADDR ip; |
| 325 | struct symtab_and_line sal; |
| 326 | CORE_ADDR limit; |
| 327 | |
| 328 | if (!fi->fsr) |
| 329 | { |
| 330 | cache_fsr = (struct frame_saved_regs *) |
| 331 | obstack_alloc (&frame_cache_obstack, |
| 332 | sizeof (struct frame_saved_regs)); |
| 333 | memset (cache_fsr, '\0', sizeof (struct frame_saved_regs)); |
| 334 | fi->fsr = cache_fsr; |
| 335 | |
| 336 | /* Find the start and end of the function prologue. If the PC |
| 337 | is in the function prologue, we only consider the part that |
| 338 | has executed already. */ |
| 339 | |
| 340 | ip = get_pc_function_start (fi->pc); |
| 341 | sal = find_pc_line (ip, 0); |
| 342 | limit = (sal.end && sal.end < fi->pc) ? sal.end: fi->pc; |
| 343 | |
| 344 | examine_prologue (ip, limit, fi->frame, cache_fsr); |
| 345 | |
| 346 | /* Record the addresses at which the local registers are saved. |
| 347 | Strictly speaking, we should only do this for non-leaf procedures, |
| 348 | but no one will ever look at these values if it is a leaf procedure, |
| 349 | since local registers are always caller-saved. */ |
| 350 | |
| 351 | next_addr = (CORE_ADDR) fi->frame; |
| 352 | saved_regs = cache_fsr->regs; |
| 353 | for (regnum = R0_REGNUM; regnum <= R15_REGNUM; regnum++) |
| 354 | { |
| 355 | *saved_regs++ = next_addr; |
| 356 | next_addr += 4; |
| 357 | } |
| 358 | |
| 359 | cache_fsr->regs[FP_REGNUM] = cache_fsr->regs[PFP_REGNUM]; |
| 360 | } |
| 361 | |
| 362 | *fsr = *fi->fsr; |
| 363 | |
| 364 | /* Fetch the value of the sp from memory every time, since it |
| 365 | is conceivable that it has changed since the cache was flushed. |
| 366 | This unfortunately undoes much of the savings from caching the |
| 367 | saved register values. I suggest adding an argument to |
| 368 | get_frame_saved_regs () specifying the register number we're |
| 369 | interested in (or -1 for all registers). This would be passed |
| 370 | through to FRAME_FIND_SAVED_REGS (), permitting more efficient |
| 371 | computation of saved register addresses (e.g., on the i960, |
| 372 | we don't have to examine the prologue to find local registers). |
| 373 | -- markf@wrs.com |
| 374 | FIXME, we don't need to refetch this, since the cache is cleared |
| 375 | every time the child process is restarted. If GDB itself |
| 376 | modifies SP, it has to clear the cache by hand (does it?). -gnu */ |
| 377 | |
| 378 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[SP_REGNUM], 4); |
| 379 | } |
| 380 | |
| 381 | /* Return the address of the argument block for the frame |
| 382 | described by FI. Returns 0 if the address is unknown. */ |
| 383 | |
| 384 | CORE_ADDR |
| 385 | frame_args_address (fi, must_be_correct) |
| 386 | struct frame_info *fi; |
| 387 | { |
| 388 | struct frame_saved_regs fsr; |
| 389 | CORE_ADDR ap; |
| 390 | |
| 391 | /* If g14 was saved in the frame by the function prologue code, return |
| 392 | the saved value. If the frame is current and we are being sloppy, |
| 393 | return the value of g14. Otherwise, return zero. */ |
| 394 | |
| 395 | get_frame_saved_regs (fi, &fsr); |
| 396 | if (fsr.regs[G14_REGNUM]) |
| 397 | ap = read_memory_integer (fsr.regs[G14_REGNUM],4); |
| 398 | else |
| 399 | { |
| 400 | if (must_be_correct) |
| 401 | return 0; /* Don't cache this result */ |
| 402 | if (get_next_frame (fi)) |
| 403 | ap = 0; |
| 404 | else |
| 405 | ap = read_register (G14_REGNUM); |
| 406 | if (ap == 0) |
| 407 | ap = fi->frame; |
| 408 | } |
| 409 | fi->arg_pointer = ap; /* Cache it for next time */ |
| 410 | return ap; |
| 411 | } |
| 412 | |
| 413 | /* Return the address of the return struct for the frame |
| 414 | described by FI. Returns 0 if the address is unknown. */ |
| 415 | |
| 416 | CORE_ADDR |
| 417 | frame_struct_result_address (fi) |
| 418 | struct frame_info *fi; |
| 419 | { |
| 420 | struct frame_saved_regs fsr; |
| 421 | CORE_ADDR ap; |
| 422 | |
| 423 | /* If the frame is non-current, check to see if g14 was saved in the |
| 424 | frame by the function prologue code; return the saved value if so, |
| 425 | zero otherwise. If the frame is current, return the value of g14. |
| 426 | |
| 427 | FIXME, shouldn't this use the saved value as long as we are past |
| 428 | the function prologue, and only use the current value if we have |
| 429 | no saved value and are at TOS? -- gnu@cygnus.com */ |
| 430 | |
| 431 | if (get_next_frame (fi)) |
| 432 | { |
| 433 | get_frame_saved_regs (fi, &fsr); |
| 434 | if (fsr.regs[G13_REGNUM]) |
| 435 | ap = read_memory_integer (fsr.regs[G13_REGNUM],4); |
| 436 | else |
| 437 | ap = 0; |
| 438 | } |
| 439 | else |
| 440 | ap = read_register (G13_REGNUM); |
| 441 | |
| 442 | return ap; |
| 443 | } |
| 444 | |
| 445 | /* Return address to which the currently executing leafproc will return, |
| 446 | or 0 if ip is not in a leafproc (or if we can't tell if it is). |
| 447 | |
| 448 | Do this by finding the starting address of the routine in which ip lies. |
| 449 | If the instruction there is "mov g14, gx" (where x is in [0,7]), this |
| 450 | is a leafproc and the return address is in register gx. Well, this is |
| 451 | true unless the return address points at a RET instruction in the current |
| 452 | procedure, which indicates that we have a 'dual entry' routine that |
| 453 | has been entered through the CALL entry point. */ |
| 454 | |
| 455 | CORE_ADDR |
| 456 | leafproc_return (ip) |
| 457 | CORE_ADDR ip; /* ip from currently executing function */ |
| 458 | { |
| 459 | register struct minimal_symbol *msymbol; |
| 460 | char *p; |
| 461 | int dst; |
| 462 | unsigned int insn1, insn2; |
| 463 | CORE_ADDR return_addr; |
| 464 | |
| 465 | if ((msymbol = lookup_minimal_symbol_by_pc (ip)) != NULL) |
| 466 | { |
| 467 | if ((p = strchr(SYMBOL_NAME (msymbol), '.')) && STREQ (p, ".lf")) |
| 468 | { |
| 469 | if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol), &insn1, &insn2) |
| 470 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
| 471 | && (dst = REG_SRCDST (insn1)) <= G0_REGNUM + 7) |
| 472 | { |
| 473 | /* Get the return address. If the "mov g14, gx" |
| 474 | instruction hasn't been executed yet, read |
| 475 | the return address from g14; otherwise, read it |
| 476 | from the register into which g14 was moved. */ |
| 477 | |
| 478 | return_addr = |
| 479 | read_register ((ip == SYMBOL_VALUE_ADDRESS (msymbol)) |
| 480 | ? G14_REGNUM : dst); |
| 481 | |
| 482 | /* We know we are in a leaf procedure, but we don't know |
| 483 | whether the caller actually did a "bal" to the ".lf" |
| 484 | entry point, or a normal "call" to the non-leaf entry |
| 485 | point one instruction before. In the latter case, the |
| 486 | return address will be the address of a "ret" |
| 487 | instruction within the procedure itself. We test for |
| 488 | this below. */ |
| 489 | |
| 490 | if (!next_insn (return_addr, &insn1, &insn2) |
| 491 | || (insn1 & 0xff000000) != 0xa000000 /* ret */ |
| 492 | || lookup_minimal_symbol_by_pc (return_addr) != msymbol) |
| 493 | return (return_addr); |
| 494 | } |
| 495 | } |
| 496 | } |
| 497 | |
| 498 | return (0); |
| 499 | } |
| 500 | |
| 501 | /* Immediately after a function call, return the saved pc. |
| 502 | Can't go through the frames for this because on some machines |
| 503 | the new frame is not set up until the new function executes |
| 504 | some instructions. |
| 505 | On the i960, the frame *is* set up immediately after the call, |
| 506 | unless the function is a leaf procedure. */ |
| 507 | |
| 508 | CORE_ADDR |
| 509 | saved_pc_after_call (frame) |
| 510 | struct frame_info *frame; |
| 511 | { |
| 512 | CORE_ADDR saved_pc; |
| 513 | |
| 514 | saved_pc = leafproc_return (get_frame_pc (frame)); |
| 515 | if (!saved_pc) |
| 516 | saved_pc = FRAME_SAVED_PC (frame); |
| 517 | |
| 518 | return saved_pc; |
| 519 | } |
| 520 | |
| 521 | /* Discard from the stack the innermost frame, |
| 522 | restoring all saved registers. */ |
| 523 | |
| 524 | pop_frame () |
| 525 | { |
| 526 | register struct frame_info *current_fi, *prev_fi; |
| 527 | register int i; |
| 528 | CORE_ADDR save_addr; |
| 529 | CORE_ADDR leaf_return_addr; |
| 530 | struct frame_saved_regs fsr; |
| 531 | char local_regs_buf[16 * 4]; |
| 532 | |
| 533 | current_fi = get_current_frame (); |
| 534 | |
| 535 | /* First, undo what the hardware does when we return. |
| 536 | If this is a non-leaf procedure, restore local registers from |
| 537 | the save area in the calling frame. Otherwise, load the return |
| 538 | address obtained from leafproc_return () into the rip. */ |
| 539 | |
| 540 | leaf_return_addr = leafproc_return (current_fi->pc); |
| 541 | if (!leaf_return_addr) |
| 542 | { |
| 543 | /* Non-leaf procedure. Restore local registers, incl IP. */ |
| 544 | prev_fi = get_prev_frame (current_fi); |
| 545 | read_memory (prev_fi->frame, local_regs_buf, sizeof (local_regs_buf)); |
| 546 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), local_regs_buf, |
| 547 | sizeof (local_regs_buf)); |
| 548 | |
| 549 | /* Restore frame pointer. */ |
| 550 | write_register (FP_REGNUM, prev_fi->frame); |
| 551 | } |
| 552 | else |
| 553 | { |
| 554 | /* Leaf procedure. Just restore the return address into the IP. */ |
| 555 | write_register (RIP_REGNUM, leaf_return_addr); |
| 556 | } |
| 557 | |
| 558 | /* Now restore any global regs that the current function had saved. */ |
| 559 | get_frame_saved_regs (current_fi, &fsr); |
| 560 | for (i = G0_REGNUM; i < G14_REGNUM; i++) |
| 561 | { |
| 562 | if (save_addr = fsr.regs[i]) |
| 563 | write_register (i, read_memory_integer (save_addr, 4)); |
| 564 | } |
| 565 | |
| 566 | /* Flush the frame cache, create a frame for the new innermost frame, |
| 567 | and make it the current frame. */ |
| 568 | |
| 569 | flush_cached_frames (); |
| 570 | } |
| 571 | |
| 572 | /* Given a 960 stop code (fault or trace), return the signal which |
| 573 | corresponds. */ |
| 574 | |
| 575 | enum target_signal |
| 576 | i960_fault_to_signal (fault) |
| 577 | int fault; |
| 578 | { |
| 579 | switch (fault) |
| 580 | { |
| 581 | case 0: return TARGET_SIGNAL_BUS; /* parallel fault */ |
| 582 | case 1: return TARGET_SIGNAL_UNKNOWN; |
| 583 | case 2: return TARGET_SIGNAL_ILL; /* operation fault */ |
| 584 | case 3: return TARGET_SIGNAL_FPE; /* arithmetic fault */ |
| 585 | case 4: return TARGET_SIGNAL_FPE; /* floating point fault */ |
| 586 | |
| 587 | /* constraint fault. This appears not to distinguish between |
| 588 | a range constraint fault (which should be SIGFPE) and a privileged |
| 589 | fault (which should be SIGILL). */ |
| 590 | case 5: return TARGET_SIGNAL_ILL; |
| 591 | |
| 592 | case 6: return TARGET_SIGNAL_SEGV; /* virtual memory fault */ |
| 593 | |
| 594 | /* protection fault. This is for an out-of-range argument to |
| 595 | "calls". I guess it also could be SIGILL. */ |
| 596 | case 7: return TARGET_SIGNAL_SEGV; |
| 597 | |
| 598 | case 8: return TARGET_SIGNAL_BUS; /* machine fault */ |
| 599 | case 9: return TARGET_SIGNAL_BUS; /* structural fault */ |
| 600 | case 0xa: return TARGET_SIGNAL_ILL; /* type fault */ |
| 601 | case 0xb: return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ |
| 602 | case 0xc: return TARGET_SIGNAL_BUS; /* process fault */ |
| 603 | case 0xd: return TARGET_SIGNAL_SEGV; /* descriptor fault */ |
| 604 | case 0xe: return TARGET_SIGNAL_BUS; /* event fault */ |
| 605 | case 0xf: return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ |
| 606 | case 0x10: return TARGET_SIGNAL_TRAP; /* single-step trace */ |
| 607 | case 0x11: return TARGET_SIGNAL_TRAP; /* branch trace */ |
| 608 | case 0x12: return TARGET_SIGNAL_TRAP; /* call trace */ |
| 609 | case 0x13: return TARGET_SIGNAL_TRAP; /* return trace */ |
| 610 | case 0x14: return TARGET_SIGNAL_TRAP; /* pre-return trace */ |
| 611 | case 0x15: return TARGET_SIGNAL_TRAP; /* supervisor call trace */ |
| 612 | case 0x16: return TARGET_SIGNAL_TRAP; /* breakpoint trace */ |
| 613 | default: return TARGET_SIGNAL_UNKNOWN; |
| 614 | } |
| 615 | } |
| 616 | |
| 617 | /****************************************/ |
| 618 | /* MEM format */ |
| 619 | /****************************************/ |
| 620 | |
| 621 | struct tabent { |
| 622 | char *name; |
| 623 | char numops; |
| 624 | }; |
| 625 | |
| 626 | static int /* returns instruction length: 4 or 8 */ |
| 627 | mem( memaddr, word1, word2, noprint ) |
| 628 | unsigned long memaddr; |
| 629 | unsigned long word1, word2; |
| 630 | int noprint; /* If TRUE, return instruction length, but |
| 631 | don't output any text. */ |
| 632 | { |
| 633 | int i, j; |
| 634 | int len; |
| 635 | int mode; |
| 636 | int offset; |
| 637 | const char *reg1, *reg2, *reg3; |
| 638 | |
| 639 | /* This lookup table is too sparse to make it worth typing in, but not |
| 640 | * so large as to make a sparse array necessary. We allocate the |
| 641 | * table at runtime, initialize all entries to empty, and copy the |
| 642 | * real ones in from an initialization table. |
| 643 | * |
| 644 | * NOTE: In this table, the meaning of 'numops' is: |
| 645 | * 1: single operand |
| 646 | * 2: 2 operands, load instruction |
| 647 | * -2: 2 operands, store instruction |
| 648 | */ |
| 649 | static struct tabent *mem_tab = NULL; |
| 650 | /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ |
| 651 | #define MEM_MIN 0x80 |
| 652 | #define MEM_MAX 0xcf |
| 653 | #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent)) |
| 654 | |
| 655 | static struct { int opcode; char *name; char numops; } mem_init[] = { |
| 656 | 0x80, "ldob", 2, |
| 657 | 0x82, "stob", -2, |
| 658 | 0x84, "bx", 1, |
| 659 | 0x85, "balx", 2, |
| 660 | 0x86, "callx", 1, |
| 661 | 0x88, "ldos", 2, |
| 662 | 0x8a, "stos", -2, |
| 663 | 0x8c, "lda", 2, |
| 664 | 0x90, "ld", 2, |
| 665 | 0x92, "st", -2, |
| 666 | 0x98, "ldl", 2, |
| 667 | 0x9a, "stl", -2, |
| 668 | 0xa0, "ldt", 2, |
| 669 | 0xa2, "stt", -2, |
| 670 | 0xb0, "ldq", 2, |
| 671 | 0xb2, "stq", -2, |
| 672 | 0xc0, "ldib", 2, |
| 673 | 0xc2, "stib", -2, |
| 674 | 0xc8, "ldis", 2, |
| 675 | 0xca, "stis", -2, |
| 676 | 0, NULL, 0 |
| 677 | }; |
| 678 | |
| 679 | if ( mem_tab == NULL ){ |
| 680 | mem_tab = (struct tabent *) xmalloc( MEM_SIZ ); |
| 681 | memset( mem_tab, '\0', MEM_SIZ ); |
| 682 | for ( i = 0; mem_init[i].opcode != 0; i++ ){ |
| 683 | j = mem_init[i].opcode - MEM_MIN; |
| 684 | mem_tab[j].name = mem_init[i].name; |
| 685 | mem_tab[j].numops = mem_init[i].numops; |
| 686 | } |
| 687 | } |
| 688 | |
| 689 | i = ((word1 >> 24) & 0xff) - MEM_MIN; |
| 690 | mode = (word1 >> 10) & 0xf; |
| 691 | |
| 692 | if ( (mem_tab[i].name != NULL) /* Valid instruction */ |
| 693 | && ((mode == 5) || (mode >=12)) ){ /* With 32-bit displacement */ |
| 694 | len = 8; |
| 695 | } else { |
| 696 | len = 4; |
| 697 | } |
| 698 | |
| 699 | if ( noprint ){ |
| 700 | return len; |
| 701 | } |
| 702 | abort (); |
| 703 | } |
| 704 | |
| 705 | /* Read the i960 instruction at 'memaddr' and return the address of |
| 706 | the next instruction after that, or 0 if 'memaddr' is not the |
| 707 | address of a valid instruction. The first word of the instruction |
| 708 | is stored at 'pword1', and the second word, if any, is stored at |
| 709 | 'pword2'. */ |
| 710 | |
| 711 | static CORE_ADDR |
| 712 | next_insn (memaddr, pword1, pword2) |
| 713 | unsigned long *pword1, *pword2; |
| 714 | CORE_ADDR memaddr; |
| 715 | { |
| 716 | int len; |
| 717 | char buf[8]; |
| 718 | |
| 719 | /* Read the two (potential) words of the instruction at once, |
| 720 | to eliminate the overhead of two calls to read_memory (). |
| 721 | FIXME: Loses if the first one is readable but the second is not |
| 722 | (e.g. last word of the segment). */ |
| 723 | |
| 724 | read_memory (memaddr, buf, 8); |
| 725 | *pword1 = extract_unsigned_integer (buf, 4); |
| 726 | *pword2 = extract_unsigned_integer (buf + 4, 4); |
| 727 | |
| 728 | /* Divide instruction set into classes based on high 4 bits of opcode*/ |
| 729 | |
| 730 | switch ((*pword1 >> 28) & 0xf) |
| 731 | { |
| 732 | case 0x0: |
| 733 | case 0x1: /* ctrl */ |
| 734 | |
| 735 | case 0x2: |
| 736 | case 0x3: /* cobr */ |
| 737 | |
| 738 | case 0x5: |
| 739 | case 0x6: |
| 740 | case 0x7: /* reg */ |
| 741 | len = 4; |
| 742 | break; |
| 743 | |
| 744 | case 0x8: |
| 745 | case 0x9: |
| 746 | case 0xa: |
| 747 | case 0xb: |
| 748 | case 0xc: |
| 749 | len = mem (memaddr, *pword1, *pword2, 1); |
| 750 | break; |
| 751 | |
| 752 | default: /* invalid instruction */ |
| 753 | len = 0; |
| 754 | break; |
| 755 | } |
| 756 | |
| 757 | if (len) |
| 758 | return memaddr + len; |
| 759 | else |
| 760 | return 0; |
| 761 | } |
| 762 | |
| 763 | void |
| 764 | _initialize_i960_tdep () |
| 765 | { |
| 766 | check_host (); |
| 767 | |
| 768 | tm_print_insn = print_insn_i960; |
| 769 | } |