| 1 | /* Functions specific to running gdb native on IA-64 running |
| 2 | GNU/Linux. |
| 3 | |
| 4 | Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, |
| 5 | Inc. |
| 6 | |
| 7 | This file is part of GDB. |
| 8 | |
| 9 | This program is free software; you can redistribute it and/or modify |
| 10 | it under the terms of the GNU General Public License as published by |
| 11 | the Free Software Foundation; either version 2 of the License, or |
| 12 | (at your option) any later version. |
| 13 | |
| 14 | This program is distributed in the hope that it will be useful, |
| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | GNU General Public License for more details. |
| 18 | |
| 19 | You should have received a copy of the GNU General Public License |
| 20 | along with this program; if not, write to the Free Software |
| 21 | Foundation, Inc., 59 Temple Place - Suite 330, |
| 22 | Boston, MA 02111-1307, USA. */ |
| 23 | |
| 24 | #include "defs.h" |
| 25 | #include "gdb_string.h" |
| 26 | #include "inferior.h" |
| 27 | #include "target.h" |
| 28 | #include "gdbcore.h" |
| 29 | #include "regcache.h" |
| 30 | |
| 31 | #include <signal.h> |
| 32 | #include <sys/ptrace.h> |
| 33 | #include "gdb_wait.h" |
| 34 | #ifdef HAVE_SYS_REG_H |
| 35 | #include <sys/reg.h> |
| 36 | #endif |
| 37 | #include <sys/user.h> |
| 38 | |
| 39 | #include <asm/ptrace_offsets.h> |
| 40 | #include <sys/procfs.h> |
| 41 | |
| 42 | /* Prototypes for supply_gregset etc. */ |
| 43 | #include "gregset.h" |
| 44 | |
| 45 | /* These must match the order of the register names. |
| 46 | |
| 47 | Some sort of lookup table is needed because the offsets associated |
| 48 | with the registers are all over the board. */ |
| 49 | |
| 50 | static int u_offsets[] = |
| 51 | { |
| 52 | /* general registers */ |
| 53 | -1, /* gr0 not available; i.e, it's always zero */ |
| 54 | PT_R1, |
| 55 | PT_R2, |
| 56 | PT_R3, |
| 57 | PT_R4, |
| 58 | PT_R5, |
| 59 | PT_R6, |
| 60 | PT_R7, |
| 61 | PT_R8, |
| 62 | PT_R9, |
| 63 | PT_R10, |
| 64 | PT_R11, |
| 65 | PT_R12, |
| 66 | PT_R13, |
| 67 | PT_R14, |
| 68 | PT_R15, |
| 69 | PT_R16, |
| 70 | PT_R17, |
| 71 | PT_R18, |
| 72 | PT_R19, |
| 73 | PT_R20, |
| 74 | PT_R21, |
| 75 | PT_R22, |
| 76 | PT_R23, |
| 77 | PT_R24, |
| 78 | PT_R25, |
| 79 | PT_R26, |
| 80 | PT_R27, |
| 81 | PT_R28, |
| 82 | PT_R29, |
| 83 | PT_R30, |
| 84 | PT_R31, |
| 85 | /* gr32 through gr127 not directly available via the ptrace interface */ |
| 86 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 87 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 88 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 89 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 90 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 91 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 92 | /* Floating point registers */ |
| 93 | -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */ |
| 94 | PT_F2, |
| 95 | PT_F3, |
| 96 | PT_F4, |
| 97 | PT_F5, |
| 98 | PT_F6, |
| 99 | PT_F7, |
| 100 | PT_F8, |
| 101 | PT_F9, |
| 102 | PT_F10, |
| 103 | PT_F11, |
| 104 | PT_F12, |
| 105 | PT_F13, |
| 106 | PT_F14, |
| 107 | PT_F15, |
| 108 | PT_F16, |
| 109 | PT_F17, |
| 110 | PT_F18, |
| 111 | PT_F19, |
| 112 | PT_F20, |
| 113 | PT_F21, |
| 114 | PT_F22, |
| 115 | PT_F23, |
| 116 | PT_F24, |
| 117 | PT_F25, |
| 118 | PT_F26, |
| 119 | PT_F27, |
| 120 | PT_F28, |
| 121 | PT_F29, |
| 122 | PT_F30, |
| 123 | PT_F31, |
| 124 | PT_F32, |
| 125 | PT_F33, |
| 126 | PT_F34, |
| 127 | PT_F35, |
| 128 | PT_F36, |
| 129 | PT_F37, |
| 130 | PT_F38, |
| 131 | PT_F39, |
| 132 | PT_F40, |
| 133 | PT_F41, |
| 134 | PT_F42, |
| 135 | PT_F43, |
| 136 | PT_F44, |
| 137 | PT_F45, |
| 138 | PT_F46, |
| 139 | PT_F47, |
| 140 | PT_F48, |
| 141 | PT_F49, |
| 142 | PT_F50, |
| 143 | PT_F51, |
| 144 | PT_F52, |
| 145 | PT_F53, |
| 146 | PT_F54, |
| 147 | PT_F55, |
| 148 | PT_F56, |
| 149 | PT_F57, |
| 150 | PT_F58, |
| 151 | PT_F59, |
| 152 | PT_F60, |
| 153 | PT_F61, |
| 154 | PT_F62, |
| 155 | PT_F63, |
| 156 | PT_F64, |
| 157 | PT_F65, |
| 158 | PT_F66, |
| 159 | PT_F67, |
| 160 | PT_F68, |
| 161 | PT_F69, |
| 162 | PT_F70, |
| 163 | PT_F71, |
| 164 | PT_F72, |
| 165 | PT_F73, |
| 166 | PT_F74, |
| 167 | PT_F75, |
| 168 | PT_F76, |
| 169 | PT_F77, |
| 170 | PT_F78, |
| 171 | PT_F79, |
| 172 | PT_F80, |
| 173 | PT_F81, |
| 174 | PT_F82, |
| 175 | PT_F83, |
| 176 | PT_F84, |
| 177 | PT_F85, |
| 178 | PT_F86, |
| 179 | PT_F87, |
| 180 | PT_F88, |
| 181 | PT_F89, |
| 182 | PT_F90, |
| 183 | PT_F91, |
| 184 | PT_F92, |
| 185 | PT_F93, |
| 186 | PT_F94, |
| 187 | PT_F95, |
| 188 | PT_F96, |
| 189 | PT_F97, |
| 190 | PT_F98, |
| 191 | PT_F99, |
| 192 | PT_F100, |
| 193 | PT_F101, |
| 194 | PT_F102, |
| 195 | PT_F103, |
| 196 | PT_F104, |
| 197 | PT_F105, |
| 198 | PT_F106, |
| 199 | PT_F107, |
| 200 | PT_F108, |
| 201 | PT_F109, |
| 202 | PT_F110, |
| 203 | PT_F111, |
| 204 | PT_F112, |
| 205 | PT_F113, |
| 206 | PT_F114, |
| 207 | PT_F115, |
| 208 | PT_F116, |
| 209 | PT_F117, |
| 210 | PT_F118, |
| 211 | PT_F119, |
| 212 | PT_F120, |
| 213 | PT_F121, |
| 214 | PT_F122, |
| 215 | PT_F123, |
| 216 | PT_F124, |
| 217 | PT_F125, |
| 218 | PT_F126, |
| 219 | PT_F127, |
| 220 | /* predicate registers - we don't fetch these individually */ |
| 221 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 222 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 223 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 224 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 225 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 226 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 227 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 228 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 229 | /* branch registers */ |
| 230 | PT_B0, |
| 231 | PT_B1, |
| 232 | PT_B2, |
| 233 | PT_B3, |
| 234 | PT_B4, |
| 235 | PT_B5, |
| 236 | PT_B6, |
| 237 | PT_B7, |
| 238 | /* virtual frame pointer and virtual return address pointer */ |
| 239 | -1, -1, |
| 240 | /* other registers */ |
| 241 | PT_PR, |
| 242 | PT_CR_IIP, /* ip */ |
| 243 | PT_CR_IPSR, /* psr */ |
| 244 | PT_CFM, /* cfm */ |
| 245 | /* kernel registers not visible via ptrace interface (?) */ |
| 246 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 247 | /* hole */ |
| 248 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 249 | PT_AR_RSC, |
| 250 | PT_AR_BSP, |
| 251 | PT_AR_BSPSTORE, |
| 252 | PT_AR_RNAT, |
| 253 | -1, |
| 254 | -1, /* Not available: FCR, IA32 floating control register */ |
| 255 | -1, -1, |
| 256 | -1, /* Not available: EFLAG */ |
| 257 | -1, /* Not available: CSD */ |
| 258 | -1, /* Not available: SSD */ |
| 259 | -1, /* Not available: CFLG */ |
| 260 | -1, /* Not available: FSR */ |
| 261 | -1, /* Not available: FIR */ |
| 262 | -1, /* Not available: FDR */ |
| 263 | -1, |
| 264 | PT_AR_CCV, |
| 265 | -1, -1, -1, |
| 266 | PT_AR_UNAT, |
| 267 | -1, -1, -1, |
| 268 | PT_AR_FPSR, |
| 269 | -1, -1, -1, |
| 270 | -1, /* Not available: ITC */ |
| 271 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 272 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 273 | PT_AR_PFS, |
| 274 | PT_AR_LC, |
| 275 | -1, /* Not available: EC, the Epilog Count register */ |
| 276 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 277 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 278 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 279 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 280 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 281 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, |
| 282 | -1, |
| 283 | /* nat bits - not fetched directly; instead we obtain these bits from |
| 284 | either rnat or unat or from memory. */ |
| 285 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 286 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 287 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 288 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 289 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 290 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 291 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 292 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 293 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 294 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 295 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 296 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 297 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 298 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 299 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 300 | -1, -1, -1, -1, -1, -1, -1, -1, |
| 301 | }; |
| 302 | |
| 303 | CORE_ADDR |
| 304 | register_addr (int regno, CORE_ADDR blockend) |
| 305 | { |
| 306 | CORE_ADDR addr; |
| 307 | |
| 308 | if (regno < 0 || regno >= NUM_REGS) |
| 309 | error ("Invalid register number %d.", regno); |
| 310 | |
| 311 | if (u_offsets[regno] == -1) |
| 312 | addr = 0; |
| 313 | else |
| 314 | addr = (CORE_ADDR) u_offsets[regno]; |
| 315 | |
| 316 | return addr; |
| 317 | } |
| 318 | |
| 319 | int ia64_cannot_fetch_register (regno) |
| 320 | int regno; |
| 321 | { |
| 322 | return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1; |
| 323 | } |
| 324 | |
| 325 | int ia64_cannot_store_register (regno) |
| 326 | int regno; |
| 327 | { |
| 328 | /* Rationale behind not permitting stores to bspstore... |
| 329 | |
| 330 | The IA-64 architecture provides bspstore and bsp which refer |
| 331 | memory locations in the RSE's backing store. bspstore is the |
| 332 | next location which will be written when the RSE needs to write |
| 333 | to memory. bsp is the address at which r32 in the current frame |
| 334 | would be found if it were written to the backing store. |
| 335 | |
| 336 | The IA-64 architecture provides read-only access to bsp and |
| 337 | read/write access to bspstore (but only when the RSE is in |
| 338 | the enforced lazy mode). It should be noted that stores |
| 339 | to bspstore also affect the value of bsp. Changing bspstore |
| 340 | does not affect the number of dirty entries between bspstore |
| 341 | and bsp, so changing bspstore by N words will also cause bsp |
| 342 | to be changed by (roughly) N as well. (It could be N-1 or N+1 |
| 343 | depending upon where the NaT collection bits fall.) |
| 344 | |
| 345 | OTOH, the Linux kernel provides read/write access to bsp (and |
| 346 | currently read/write access to bspstore as well). But it |
| 347 | is definitely the case that if you change one, the other |
| 348 | will change at the same time. It is more useful to gdb to |
| 349 | be able to change bsp. So in order to prevent strange and |
| 350 | undesirable things from happening when a dummy stack frame |
| 351 | is popped (after calling an inferior function), we allow |
| 352 | bspstore to be read, but not written. (Note that popping |
| 353 | a (generic) dummy stack frame causes all registers that |
| 354 | were previously read from the inferior process to be written |
| 355 | back.) */ |
| 356 | |
| 357 | return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1 |
| 358 | || regno == IA64_BSPSTORE_REGNUM; |
| 359 | } |
| 360 | |
| 361 | void |
| 362 | supply_gregset (gregset_t *gregsetp) |
| 363 | { |
| 364 | int regi; |
| 365 | greg_t *regp = (greg_t *) gregsetp; |
| 366 | |
| 367 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) |
| 368 | { |
| 369 | supply_register (regi, (char *) (regp + (regi - IA64_GR0_REGNUM))); |
| 370 | } |
| 371 | |
| 372 | /* FIXME: NAT collection bits are at index 32; gotta deal with these |
| 373 | somehow... */ |
| 374 | |
| 375 | supply_register (IA64_PR_REGNUM, (char *) (regp + 33)); |
| 376 | |
| 377 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) |
| 378 | { |
| 379 | supply_register (regi, (char *) (regp + 34 + (regi - IA64_BR0_REGNUM))); |
| 380 | } |
| 381 | |
| 382 | supply_register (IA64_IP_REGNUM, (char *) (regp + 42)); |
| 383 | supply_register (IA64_CFM_REGNUM, (char *) (regp + 43)); |
| 384 | supply_register (IA64_PSR_REGNUM, (char *) (regp + 44)); |
| 385 | supply_register (IA64_RSC_REGNUM, (char *) (regp + 45)); |
| 386 | supply_register (IA64_BSP_REGNUM, (char *) (regp + 46)); |
| 387 | supply_register (IA64_BSPSTORE_REGNUM, (char *) (regp + 47)); |
| 388 | supply_register (IA64_RNAT_REGNUM, (char *) (regp + 48)); |
| 389 | supply_register (IA64_CCV_REGNUM, (char *) (regp + 49)); |
| 390 | supply_register (IA64_UNAT_REGNUM, (char *) (regp + 50)); |
| 391 | supply_register (IA64_FPSR_REGNUM, (char *) (regp + 51)); |
| 392 | supply_register (IA64_PFS_REGNUM, (char *) (regp + 52)); |
| 393 | supply_register (IA64_LC_REGNUM, (char *) (regp + 53)); |
| 394 | supply_register (IA64_EC_REGNUM, (char *) (regp + 54)); |
| 395 | } |
| 396 | |
| 397 | void |
| 398 | fill_gregset (gregset_t *gregsetp, int regno) |
| 399 | { |
| 400 | int regi; |
| 401 | greg_t *regp = (greg_t *) gregsetp; |
| 402 | |
| 403 | #define COPY_REG(_idx_,_regi_) \ |
| 404 | if ((regno == -1) || regno == _regi_) \ |
| 405 | memcpy (regp + _idx_, &deprecated_registers[REGISTER_BYTE (_regi_)], \ |
| 406 | REGISTER_RAW_SIZE (_regi_)) |
| 407 | |
| 408 | for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++) |
| 409 | { |
| 410 | COPY_REG (regi - IA64_GR0_REGNUM, regi); |
| 411 | } |
| 412 | |
| 413 | /* FIXME: NAT collection bits at index 32? */ |
| 414 | |
| 415 | COPY_REG (33, IA64_PR_REGNUM); |
| 416 | |
| 417 | for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++) |
| 418 | { |
| 419 | COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi); |
| 420 | } |
| 421 | |
| 422 | COPY_REG (42, IA64_IP_REGNUM); |
| 423 | COPY_REG (43, IA64_CFM_REGNUM); |
| 424 | COPY_REG (44, IA64_PSR_REGNUM); |
| 425 | COPY_REG (45, IA64_RSC_REGNUM); |
| 426 | COPY_REG (46, IA64_BSP_REGNUM); |
| 427 | COPY_REG (47, IA64_BSPSTORE_REGNUM); |
| 428 | COPY_REG (48, IA64_RNAT_REGNUM); |
| 429 | COPY_REG (49, IA64_CCV_REGNUM); |
| 430 | COPY_REG (50, IA64_UNAT_REGNUM); |
| 431 | COPY_REG (51, IA64_FPSR_REGNUM); |
| 432 | COPY_REG (52, IA64_PFS_REGNUM); |
| 433 | COPY_REG (53, IA64_LC_REGNUM); |
| 434 | COPY_REG (54, IA64_EC_REGNUM); |
| 435 | } |
| 436 | |
| 437 | /* Given a pointer to a floating point register set in /proc format |
| 438 | (fpregset_t *), unpack the register contents and supply them as gdb's |
| 439 | idea of the current floating point register values. */ |
| 440 | |
| 441 | void |
| 442 | supply_fpregset (fpregset_t *fpregsetp) |
| 443 | { |
| 444 | register int regi; |
| 445 | char *from; |
| 446 | |
| 447 | for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) |
| 448 | { |
| 449 | from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); |
| 450 | supply_register (regi, from); |
| 451 | } |
| 452 | } |
| 453 | |
| 454 | /* Given a pointer to a floating point register set in /proc format |
| 455 | (fpregset_t *), update the register specified by REGNO from gdb's idea |
| 456 | of the current floating point register set. If REGNO is -1, update |
| 457 | them all. */ |
| 458 | |
| 459 | void |
| 460 | fill_fpregset (fpregset_t *fpregsetp, int regno) |
| 461 | { |
| 462 | int regi; |
| 463 | char *to; |
| 464 | char *from; |
| 465 | |
| 466 | for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++) |
| 467 | { |
| 468 | if ((regno == -1) || (regno == regi)) |
| 469 | { |
| 470 | from = (char *) &deprecated_registers[REGISTER_BYTE (regi)]; |
| 471 | to = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]); |
| 472 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); |
| 473 | } |
| 474 | } |
| 475 | } |
| 476 | |
| 477 | #define IA64_PSR_DB (1UL << 24) |
| 478 | #define IA64_PSR_DD (1UL << 39) |
| 479 | |
| 480 | static void |
| 481 | enable_watchpoints_in_psr (ptid_t ptid) |
| 482 | { |
| 483 | CORE_ADDR psr; |
| 484 | |
| 485 | psr = read_register_pid (IA64_PSR_REGNUM, ptid); |
| 486 | if (!(psr & IA64_PSR_DB)) |
| 487 | { |
| 488 | psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware |
| 489 | watchpoints and breakpoints. */ |
| 490 | write_register_pid (IA64_PSR_REGNUM, psr, ptid); |
| 491 | } |
| 492 | } |
| 493 | |
| 494 | static long |
| 495 | fetch_debug_register (ptid_t ptid, int idx) |
| 496 | { |
| 497 | long val; |
| 498 | int tid; |
| 499 | |
| 500 | tid = TIDGET (ptid); |
| 501 | if (tid == 0) |
| 502 | tid = PIDGET (ptid); |
| 503 | |
| 504 | val = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), 0); |
| 505 | |
| 506 | return val; |
| 507 | } |
| 508 | |
| 509 | static void |
| 510 | store_debug_register (ptid_t ptid, int idx, long val) |
| 511 | { |
| 512 | int tid; |
| 513 | |
| 514 | tid = TIDGET (ptid); |
| 515 | if (tid == 0) |
| 516 | tid = PIDGET (ptid); |
| 517 | |
| 518 | (void) ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) (PT_DBR + 8 * idx), val); |
| 519 | } |
| 520 | |
| 521 | static void |
| 522 | fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask) |
| 523 | { |
| 524 | if (dbr_addr) |
| 525 | *dbr_addr = fetch_debug_register (ptid, 2 * idx); |
| 526 | if (dbr_mask) |
| 527 | *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1); |
| 528 | } |
| 529 | |
| 530 | static void |
| 531 | store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask) |
| 532 | { |
| 533 | if (dbr_addr) |
| 534 | store_debug_register (ptid, 2 * idx, *dbr_addr); |
| 535 | if (dbr_mask) |
| 536 | store_debug_register (ptid, 2 * idx + 1, *dbr_mask); |
| 537 | } |
| 538 | |
| 539 | static int |
| 540 | is_power_of_2 (int val) |
| 541 | { |
| 542 | int i, onecount; |
| 543 | |
| 544 | onecount = 0; |
| 545 | for (i = 0; i < 8 * sizeof (val); i++) |
| 546 | if (val & (1 << i)) |
| 547 | onecount++; |
| 548 | |
| 549 | return onecount <= 1; |
| 550 | } |
| 551 | |
| 552 | int |
| 553 | ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw) |
| 554 | { |
| 555 | int idx; |
| 556 | long dbr_addr, dbr_mask; |
| 557 | int max_watchpoints = 4; |
| 558 | |
| 559 | if (len <= 0 || !is_power_of_2 (len)) |
| 560 | return -1; |
| 561 | |
| 562 | for (idx = 0; idx < max_watchpoints; idx++) |
| 563 | { |
| 564 | fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask); |
| 565 | if ((dbr_mask & (0x3UL << 62)) == 0) |
| 566 | { |
| 567 | /* Exit loop if both r and w bits clear */ |
| 568 | break; |
| 569 | } |
| 570 | } |
| 571 | |
| 572 | if (idx == max_watchpoints) |
| 573 | return -1; |
| 574 | |
| 575 | dbr_addr = (long) addr; |
| 576 | dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */ |
| 577 | dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */ |
| 578 | switch (rw) |
| 579 | { |
| 580 | case hw_write: |
| 581 | dbr_mask |= (1L << 62); /* Set w bit */ |
| 582 | break; |
| 583 | case hw_read: |
| 584 | dbr_mask |= (1L << 63); /* Set r bit */ |
| 585 | break; |
| 586 | case hw_access: |
| 587 | dbr_mask |= (3L << 62); /* Set both r and w bits */ |
| 588 | break; |
| 589 | default: |
| 590 | return -1; |
| 591 | } |
| 592 | |
| 593 | store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); |
| 594 | enable_watchpoints_in_psr (ptid); |
| 595 | |
| 596 | return 0; |
| 597 | } |
| 598 | |
| 599 | int |
| 600 | ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len) |
| 601 | { |
| 602 | int idx; |
| 603 | long dbr_addr, dbr_mask; |
| 604 | int max_watchpoints = 4; |
| 605 | |
| 606 | if (len <= 0 || !is_power_of_2 (len)) |
| 607 | return -1; |
| 608 | |
| 609 | for (idx = 0; idx < max_watchpoints; idx++) |
| 610 | { |
| 611 | fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); |
| 612 | if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr) |
| 613 | { |
| 614 | dbr_addr = 0; |
| 615 | dbr_mask = 0; |
| 616 | store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask); |
| 617 | return 0; |
| 618 | } |
| 619 | } |
| 620 | return -1; |
| 621 | } |
| 622 | |
| 623 | CORE_ADDR |
| 624 | ia64_linux_stopped_by_watchpoint (ptid_t ptid) |
| 625 | { |
| 626 | CORE_ADDR psr; |
| 627 | int tid; |
| 628 | struct siginfo siginfo; |
| 629 | |
| 630 | tid = TIDGET(ptid); |
| 631 | if (tid == 0) |
| 632 | tid = PIDGET (ptid); |
| 633 | |
| 634 | errno = 0; |
| 635 | ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_ARG3_TYPE) 0, &siginfo); |
| 636 | |
| 637 | if (errno != 0 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) |
| 638 | return 0; |
| 639 | |
| 640 | psr = read_register_pid (IA64_PSR_REGNUM, ptid); |
| 641 | psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint |
| 642 | for the next instruction */ |
| 643 | write_register_pid (IA64_PSR_REGNUM, psr, ptid); |
| 644 | |
| 645 | return (CORE_ADDR) siginfo.si_addr; |
| 646 | } |