| 1 | /* Renesas M32C target-dependent code for GDB, the GNU debugger. |
| 2 | |
| 3 | Copyright (C) 2004-2015 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "elf-bfd.h" |
| 22 | #include "elf/m32c.h" |
| 23 | #include "gdb/sim-m32c.h" |
| 24 | #include "dis-asm.h" |
| 25 | #include "gdbtypes.h" |
| 26 | #include "regcache.h" |
| 27 | #include "arch-utils.h" |
| 28 | #include "frame.h" |
| 29 | #include "frame-unwind.h" |
| 30 | #include "dwarf2-frame.h" |
| 31 | #include "dwarf2expr.h" |
| 32 | #include "symtab.h" |
| 33 | #include "gdbcore.h" |
| 34 | #include "value.h" |
| 35 | #include "reggroups.h" |
| 36 | #include "prologue-value.h" |
| 37 | #include "target.h" |
| 38 | #include "objfiles.h" |
| 39 | |
| 40 | \f |
| 41 | /* The m32c tdep structure. */ |
| 42 | |
| 43 | static struct reggroup *m32c_dma_reggroup; |
| 44 | |
| 45 | struct m32c_reg; |
| 46 | |
| 47 | /* The type of a function that moves the value of REG between CACHE or |
| 48 | BUF --- in either direction. */ |
| 49 | typedef enum register_status (m32c_move_reg_t) (struct m32c_reg *reg, |
| 50 | struct regcache *cache, |
| 51 | void *buf); |
| 52 | |
| 53 | struct m32c_reg |
| 54 | { |
| 55 | /* The name of this register. */ |
| 56 | const char *name; |
| 57 | |
| 58 | /* Its type. */ |
| 59 | struct type *type; |
| 60 | |
| 61 | /* The architecture this register belongs to. */ |
| 62 | struct gdbarch *arch; |
| 63 | |
| 64 | /* Its GDB register number. */ |
| 65 | int num; |
| 66 | |
| 67 | /* Its sim register number. */ |
| 68 | int sim_num; |
| 69 | |
| 70 | /* Its DWARF register number, or -1 if it doesn't have one. */ |
| 71 | int dwarf_num; |
| 72 | |
| 73 | /* Register group memberships. */ |
| 74 | unsigned int general_p : 1; |
| 75 | unsigned int dma_p : 1; |
| 76 | unsigned int system_p : 1; |
| 77 | unsigned int save_restore_p : 1; |
| 78 | |
| 79 | /* Functions to read its value from a regcache, and write its value |
| 80 | to a regcache. */ |
| 81 | m32c_move_reg_t *read, *write; |
| 82 | |
| 83 | /* Data for READ and WRITE functions. The exact meaning depends on |
| 84 | the specific functions selected; see the comments for those |
| 85 | functions. */ |
| 86 | struct m32c_reg *rx, *ry; |
| 87 | int n; |
| 88 | }; |
| 89 | |
| 90 | |
| 91 | /* An overestimate of the number of raw and pseudoregisters we will |
| 92 | have. The exact answer depends on the variant of the architecture |
| 93 | at hand, but we can use this to declare statically allocated |
| 94 | arrays, and bump it up when needed. */ |
| 95 | #define M32C_MAX_NUM_REGS (75) |
| 96 | |
| 97 | /* The largest assigned DWARF register number. */ |
| 98 | #define M32C_MAX_DWARF_REGNUM (40) |
| 99 | |
| 100 | |
| 101 | struct gdbarch_tdep |
| 102 | { |
| 103 | /* All the registers for this variant, indexed by GDB register |
| 104 | number, and the number of registers present. */ |
| 105 | struct m32c_reg regs[M32C_MAX_NUM_REGS]; |
| 106 | |
| 107 | /* The number of valid registers. */ |
| 108 | int num_regs; |
| 109 | |
| 110 | /* Interesting registers. These are pointers into REGS. */ |
| 111 | struct m32c_reg *pc, *flg; |
| 112 | struct m32c_reg *r0, *r1, *r2, *r3, *a0, *a1; |
| 113 | struct m32c_reg *r2r0, *r3r2r1r0, *r3r1r2r0; |
| 114 | struct m32c_reg *sb, *fb, *sp; |
| 115 | |
| 116 | /* A table indexed by DWARF register numbers, pointing into |
| 117 | REGS. */ |
| 118 | struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1]; |
| 119 | |
| 120 | /* Types for this architecture. We can't use the builtin_type_foo |
| 121 | types, because they're not initialized when building a gdbarch |
| 122 | structure. */ |
| 123 | struct type *voyd, *ptr_voyd, *func_voyd; |
| 124 | struct type *uint8, *uint16; |
| 125 | struct type *int8, *int16, *int32, *int64; |
| 126 | |
| 127 | /* The types for data address and code address registers. */ |
| 128 | struct type *data_addr_reg_type, *code_addr_reg_type; |
| 129 | |
| 130 | /* The number of bytes a return address pushed by a 'jsr' instruction |
| 131 | occupies on the stack. */ |
| 132 | int ret_addr_bytes; |
| 133 | |
| 134 | /* The number of bytes an address register occupies on the stack |
| 135 | when saved by an 'enter' or 'pushm' instruction. */ |
| 136 | int push_addr_bytes; |
| 137 | }; |
| 138 | |
| 139 | \f |
| 140 | /* Types. */ |
| 141 | |
| 142 | static void |
| 143 | make_types (struct gdbarch *arch) |
| 144 | { |
| 145 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 146 | unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; |
| 147 | int data_addr_reg_bits, code_addr_reg_bits; |
| 148 | char type_name[50]; |
| 149 | |
| 150 | #if 0 |
| 151 | /* This is used to clip CORE_ADDR values, so this value is |
| 152 | appropriate both on the m32c, where pointers are 32 bits long, |
| 153 | and on the m16c, where pointers are sixteen bits long, but there |
| 154 | may be code above the 64k boundary. */ |
| 155 | set_gdbarch_addr_bit (arch, 24); |
| 156 | #else |
| 157 | /* GCC uses 32 bits for addrs in the dwarf info, even though |
| 158 | only 16/24 bits are used. Setting addr_bit to 24 causes |
| 159 | errors in reading the dwarf addresses. */ |
| 160 | set_gdbarch_addr_bit (arch, 32); |
| 161 | #endif |
| 162 | |
| 163 | set_gdbarch_int_bit (arch, 16); |
| 164 | switch (mach) |
| 165 | { |
| 166 | case bfd_mach_m16c: |
| 167 | data_addr_reg_bits = 16; |
| 168 | code_addr_reg_bits = 24; |
| 169 | set_gdbarch_ptr_bit (arch, 16); |
| 170 | tdep->ret_addr_bytes = 3; |
| 171 | tdep->push_addr_bytes = 2; |
| 172 | break; |
| 173 | |
| 174 | case bfd_mach_m32c: |
| 175 | data_addr_reg_bits = 24; |
| 176 | code_addr_reg_bits = 24; |
| 177 | set_gdbarch_ptr_bit (arch, 32); |
| 178 | tdep->ret_addr_bytes = 4; |
| 179 | tdep->push_addr_bytes = 4; |
| 180 | break; |
| 181 | |
| 182 | default: |
| 183 | gdb_assert_not_reached ("unexpected mach"); |
| 184 | } |
| 185 | |
| 186 | /* The builtin_type_mumble variables are sometimes uninitialized when |
| 187 | this is called, so we avoid using them. */ |
| 188 | tdep->voyd = arch_type (arch, TYPE_CODE_VOID, 1, "void"); |
| 189 | tdep->ptr_voyd |
| 190 | = arch_type (arch, TYPE_CODE_PTR, gdbarch_ptr_bit (arch) / TARGET_CHAR_BIT, |
| 191 | NULL); |
| 192 | TYPE_TARGET_TYPE (tdep->ptr_voyd) = tdep->voyd; |
| 193 | TYPE_UNSIGNED (tdep->ptr_voyd) = 1; |
| 194 | tdep->func_voyd = lookup_function_type (tdep->voyd); |
| 195 | |
| 196 | xsnprintf (type_name, sizeof (type_name), "%s_data_addr_t", |
| 197 | gdbarch_bfd_arch_info (arch)->printable_name); |
| 198 | tdep->data_addr_reg_type |
| 199 | = arch_type (arch, TYPE_CODE_PTR, data_addr_reg_bits / TARGET_CHAR_BIT, |
| 200 | xstrdup (type_name)); |
| 201 | TYPE_TARGET_TYPE (tdep->data_addr_reg_type) = tdep->voyd; |
| 202 | TYPE_UNSIGNED (tdep->data_addr_reg_type) = 1; |
| 203 | |
| 204 | xsnprintf (type_name, sizeof (type_name), "%s_code_addr_t", |
| 205 | gdbarch_bfd_arch_info (arch)->printable_name); |
| 206 | tdep->code_addr_reg_type |
| 207 | = arch_type (arch, TYPE_CODE_PTR, code_addr_reg_bits / TARGET_CHAR_BIT, |
| 208 | xstrdup (type_name)); |
| 209 | TYPE_TARGET_TYPE (tdep->code_addr_reg_type) = tdep->func_voyd; |
| 210 | TYPE_UNSIGNED (tdep->code_addr_reg_type) = 1; |
| 211 | |
| 212 | tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t"); |
| 213 | tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t"); |
| 214 | tdep->int8 = arch_integer_type (arch, 8, 0, "int8_t"); |
| 215 | tdep->int16 = arch_integer_type (arch, 16, 0, "int16_t"); |
| 216 | tdep->int32 = arch_integer_type (arch, 32, 0, "int32_t"); |
| 217 | tdep->int64 = arch_integer_type (arch, 64, 0, "int64_t"); |
| 218 | } |
| 219 | |
| 220 | |
| 221 | \f |
| 222 | /* Register set. */ |
| 223 | |
| 224 | static const char * |
| 225 | m32c_register_name (struct gdbarch *gdbarch, int num) |
| 226 | { |
| 227 | return gdbarch_tdep (gdbarch)->regs[num].name; |
| 228 | } |
| 229 | |
| 230 | |
| 231 | static struct type * |
| 232 | m32c_register_type (struct gdbarch *arch, int reg_nr) |
| 233 | { |
| 234 | return gdbarch_tdep (arch)->regs[reg_nr].type; |
| 235 | } |
| 236 | |
| 237 | |
| 238 | static int |
| 239 | m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr) |
| 240 | { |
| 241 | return gdbarch_tdep (gdbarch)->regs[reg_nr].sim_num; |
| 242 | } |
| 243 | |
| 244 | |
| 245 | static int |
| 246 | m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr) |
| 247 | { |
| 248 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 249 | if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM |
| 250 | && tdep->dwarf_regs[reg_nr]) |
| 251 | return tdep->dwarf_regs[reg_nr]->num; |
| 252 | else |
| 253 | /* The DWARF CFI code expects to see -1 for invalid register |
| 254 | numbers. */ |
| 255 | return -1; |
| 256 | } |
| 257 | |
| 258 | |
| 259 | static int |
| 260 | m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
| 261 | struct reggroup *group) |
| 262 | { |
| 263 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 264 | struct m32c_reg *reg = &tdep->regs[regnum]; |
| 265 | |
| 266 | /* The anonymous raw registers aren't in any groups. */ |
| 267 | if (! reg->name) |
| 268 | return 0; |
| 269 | |
| 270 | if (group == all_reggroup) |
| 271 | return 1; |
| 272 | |
| 273 | if (group == general_reggroup |
| 274 | && reg->general_p) |
| 275 | return 1; |
| 276 | |
| 277 | if (group == m32c_dma_reggroup |
| 278 | && reg->dma_p) |
| 279 | return 1; |
| 280 | |
| 281 | if (group == system_reggroup |
| 282 | && reg->system_p) |
| 283 | return 1; |
| 284 | |
| 285 | /* Since the m32c DWARF register numbers refer to cooked registers, not |
| 286 | raw registers, and frame_pop depends on the save and restore groups |
| 287 | containing registers the DWARF CFI will actually mention, our save |
| 288 | and restore groups are cooked registers, not raw registers. (This is |
| 289 | why we can't use the default reggroup function.) */ |
| 290 | if ((group == save_reggroup |
| 291 | || group == restore_reggroup) |
| 292 | && reg->save_restore_p) |
| 293 | return 1; |
| 294 | |
| 295 | return 0; |
| 296 | } |
| 297 | |
| 298 | |
| 299 | /* Register move functions. We declare them here using |
| 300 | m32c_move_reg_t to check the types. */ |
| 301 | static m32c_move_reg_t m32c_raw_read, m32c_raw_write; |
| 302 | static m32c_move_reg_t m32c_banked_read, m32c_banked_write; |
| 303 | static m32c_move_reg_t m32c_sb_read, m32c_sb_write; |
| 304 | static m32c_move_reg_t m32c_part_read, m32c_part_write; |
| 305 | static m32c_move_reg_t m32c_cat_read, m32c_cat_write; |
| 306 | static m32c_move_reg_t m32c_r3r2r1r0_read, m32c_r3r2r1r0_write; |
| 307 | |
| 308 | |
| 309 | /* Copy the value of the raw register REG from CACHE to BUF. */ |
| 310 | static enum register_status |
| 311 | m32c_raw_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 312 | { |
| 313 | return regcache_raw_read (cache, reg->num, buf); |
| 314 | } |
| 315 | |
| 316 | |
| 317 | /* Copy the value of the raw register REG from BUF to CACHE. */ |
| 318 | static enum register_status |
| 319 | m32c_raw_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 320 | { |
| 321 | regcache_raw_write (cache, reg->num, (const void *) buf); |
| 322 | |
| 323 | return REG_VALID; |
| 324 | } |
| 325 | |
| 326 | |
| 327 | /* Return the value of the 'flg' register in CACHE. */ |
| 328 | static int |
| 329 | m32c_read_flg (struct regcache *cache) |
| 330 | { |
| 331 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (cache)); |
| 332 | ULONGEST flg; |
| 333 | regcache_raw_read_unsigned (cache, tdep->flg->num, &flg); |
| 334 | return flg & 0xffff; |
| 335 | } |
| 336 | |
| 337 | |
| 338 | /* Evaluate the real register number of a banked register. */ |
| 339 | static struct m32c_reg * |
| 340 | m32c_banked_register (struct m32c_reg *reg, struct regcache *cache) |
| 341 | { |
| 342 | return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx); |
| 343 | } |
| 344 | |
| 345 | |
| 346 | /* Move the value of a banked register from CACHE to BUF. |
| 347 | If the value of the 'flg' register in CACHE has any of the bits |
| 348 | masked in REG->n set, then read REG->ry. Otherwise, read |
| 349 | REG->rx. */ |
| 350 | static enum register_status |
| 351 | m32c_banked_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 352 | { |
| 353 | struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); |
| 354 | return regcache_raw_read (cache, bank_reg->num, buf); |
| 355 | } |
| 356 | |
| 357 | |
| 358 | /* Move the value of a banked register from BUF to CACHE. |
| 359 | If the value of the 'flg' register in CACHE has any of the bits |
| 360 | masked in REG->n set, then write REG->ry. Otherwise, write |
| 361 | REG->rx. */ |
| 362 | static enum register_status |
| 363 | m32c_banked_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 364 | { |
| 365 | struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); |
| 366 | regcache_raw_write (cache, bank_reg->num, (const void *) buf); |
| 367 | |
| 368 | return REG_VALID; |
| 369 | } |
| 370 | |
| 371 | |
| 372 | /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a |
| 373 | banked register; on bfd_mach_m16c, it's not. */ |
| 374 | static enum register_status |
| 375 | m32c_sb_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 376 | { |
| 377 | if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) |
| 378 | return m32c_raw_read (reg->rx, cache, buf); |
| 379 | else |
| 380 | return m32c_banked_read (reg, cache, buf); |
| 381 | } |
| 382 | |
| 383 | |
| 384 | /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a |
| 385 | banked register; on bfd_mach_m16c, it's not. */ |
| 386 | static enum register_status |
| 387 | m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 388 | { |
| 389 | if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) |
| 390 | m32c_raw_write (reg->rx, cache, buf); |
| 391 | else |
| 392 | m32c_banked_write (reg, cache, buf); |
| 393 | |
| 394 | return REG_VALID; |
| 395 | } |
| 396 | |
| 397 | |
| 398 | /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P |
| 399 | and *LEN_P to the offset and length, in bytes, of the part REG |
| 400 | occupies in its underlying register. The offset is from the |
| 401 | lower-addressed end, regardless of the architecture's endianness. |
| 402 | (The M32C family is always little-endian, but let's keep those |
| 403 | assumptions out of here.) */ |
| 404 | static void |
| 405 | m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p) |
| 406 | { |
| 407 | /* The length of the containing register, of which REG is one part. */ |
| 408 | int containing_len = TYPE_LENGTH (reg->rx->type); |
| 409 | |
| 410 | /* The length of one "element" in our imaginary array. */ |
| 411 | int elt_len = TYPE_LENGTH (reg->type); |
| 412 | |
| 413 | /* The offset of REG's "element" from the least significant end of |
| 414 | the containing register. */ |
| 415 | int elt_offset = reg->n * elt_len; |
| 416 | |
| 417 | /* If we extend off the end, trim the length of the element. */ |
| 418 | if (elt_offset + elt_len > containing_len) |
| 419 | { |
| 420 | elt_len = containing_len - elt_offset; |
| 421 | /* We shouldn't be declaring partial registers that go off the |
| 422 | end of their containing registers. */ |
| 423 | gdb_assert (elt_len > 0); |
| 424 | } |
| 425 | |
| 426 | /* Flip the offset around if we're big-endian. */ |
| 427 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) |
| 428 | elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len; |
| 429 | |
| 430 | *offset_p = elt_offset; |
| 431 | *len_p = elt_len; |
| 432 | } |
| 433 | |
| 434 | |
| 435 | /* Move the value of a partial register (r0h, intbl, etc.) from CACHE |
| 436 | to BUF. Treating the value of the register REG->rx as an array of |
| 437 | REG->type values, where higher indices refer to more significant |
| 438 | bits, read the value of the REG->n'th element. */ |
| 439 | static enum register_status |
| 440 | m32c_part_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 441 | { |
| 442 | int offset, len; |
| 443 | |
| 444 | memset (buf, 0, TYPE_LENGTH (reg->type)); |
| 445 | m32c_find_part (reg, &offset, &len); |
| 446 | return regcache_cooked_read_part (cache, reg->rx->num, offset, len, buf); |
| 447 | } |
| 448 | |
| 449 | |
| 450 | /* Move the value of a banked register from BUF to CACHE. |
| 451 | Treating the value of the register REG->rx as an array of REG->type |
| 452 | values, where higher indices refer to more significant bits, write |
| 453 | the value of the REG->n'th element. */ |
| 454 | static enum register_status |
| 455 | m32c_part_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 456 | { |
| 457 | int offset, len; |
| 458 | |
| 459 | m32c_find_part (reg, &offset, &len); |
| 460 | regcache_cooked_write_part (cache, reg->rx->num, offset, len, buf); |
| 461 | |
| 462 | return REG_VALID; |
| 463 | } |
| 464 | |
| 465 | |
| 466 | /* Move the value of REG from CACHE to BUF. REG's value is the |
| 467 | concatenation of the values of the registers REG->rx and REG->ry, |
| 468 | with REG->rx contributing the more significant bits. */ |
| 469 | static enum register_status |
| 470 | m32c_cat_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 471 | { |
| 472 | int high_bytes = TYPE_LENGTH (reg->rx->type); |
| 473 | int low_bytes = TYPE_LENGTH (reg->ry->type); |
| 474 | /* For address arithmetic. */ |
| 475 | unsigned char *cbuf = buf; |
| 476 | enum register_status status; |
| 477 | |
| 478 | gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); |
| 479 | |
| 480 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) |
| 481 | { |
| 482 | status = regcache_cooked_read (cache, reg->rx->num, cbuf); |
| 483 | if (status == REG_VALID) |
| 484 | status = regcache_cooked_read (cache, reg->ry->num, cbuf + high_bytes); |
| 485 | } |
| 486 | else |
| 487 | { |
| 488 | status = regcache_cooked_read (cache, reg->rx->num, cbuf + low_bytes); |
| 489 | if (status == REG_VALID) |
| 490 | status = regcache_cooked_read (cache, reg->ry->num, cbuf); |
| 491 | } |
| 492 | |
| 493 | return status; |
| 494 | } |
| 495 | |
| 496 | |
| 497 | /* Move the value of REG from CACHE to BUF. REG's value is the |
| 498 | concatenation of the values of the registers REG->rx and REG->ry, |
| 499 | with REG->rx contributing the more significant bits. */ |
| 500 | static enum register_status |
| 501 | m32c_cat_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 502 | { |
| 503 | int high_bytes = TYPE_LENGTH (reg->rx->type); |
| 504 | int low_bytes = TYPE_LENGTH (reg->ry->type); |
| 505 | /* For address arithmetic. */ |
| 506 | unsigned char *cbuf = buf; |
| 507 | |
| 508 | gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); |
| 509 | |
| 510 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) |
| 511 | { |
| 512 | regcache_cooked_write (cache, reg->rx->num, cbuf); |
| 513 | regcache_cooked_write (cache, reg->ry->num, cbuf + high_bytes); |
| 514 | } |
| 515 | else |
| 516 | { |
| 517 | regcache_cooked_write (cache, reg->rx->num, cbuf + low_bytes); |
| 518 | regcache_cooked_write (cache, reg->ry->num, cbuf); |
| 519 | } |
| 520 | |
| 521 | return REG_VALID; |
| 522 | } |
| 523 | |
| 524 | |
| 525 | /* Copy the value of the raw register REG from CACHE to BUF. REG is |
| 526 | the concatenation (from most significant to least) of r3, r2, r1, |
| 527 | and r0. */ |
| 528 | static enum register_status |
| 529 | m32c_r3r2r1r0_read (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 530 | { |
| 531 | struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch); |
| 532 | int len = TYPE_LENGTH (tdep->r0->type); |
| 533 | enum register_status status; |
| 534 | |
| 535 | /* For address arithmetic. */ |
| 536 | unsigned char *cbuf = buf; |
| 537 | |
| 538 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) |
| 539 | { |
| 540 | status = regcache_cooked_read (cache, tdep->r0->num, cbuf + len * 3); |
| 541 | if (status == REG_VALID) |
| 542 | status = regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 2); |
| 543 | if (status == REG_VALID) |
| 544 | status = regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 1); |
| 545 | if (status == REG_VALID) |
| 546 | status = regcache_cooked_read (cache, tdep->r3->num, cbuf); |
| 547 | } |
| 548 | else |
| 549 | { |
| 550 | status = regcache_cooked_read (cache, tdep->r0->num, cbuf); |
| 551 | if (status == REG_VALID) |
| 552 | status = regcache_cooked_read (cache, tdep->r1->num, cbuf + len * 1); |
| 553 | if (status == REG_VALID) |
| 554 | status = regcache_cooked_read (cache, tdep->r2->num, cbuf + len * 2); |
| 555 | if (status == REG_VALID) |
| 556 | status = regcache_cooked_read (cache, tdep->r3->num, cbuf + len * 3); |
| 557 | } |
| 558 | |
| 559 | return status; |
| 560 | } |
| 561 | |
| 562 | |
| 563 | /* Copy the value of the raw register REG from BUF to CACHE. REG is |
| 564 | the concatenation (from most significant to least) of r3, r2, r1, |
| 565 | and r0. */ |
| 566 | static enum register_status |
| 567 | m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache, void *buf) |
| 568 | { |
| 569 | struct gdbarch_tdep *tdep = gdbarch_tdep (reg->arch); |
| 570 | int len = TYPE_LENGTH (tdep->r0->type); |
| 571 | |
| 572 | /* For address arithmetic. */ |
| 573 | unsigned char *cbuf = buf; |
| 574 | |
| 575 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) |
| 576 | { |
| 577 | regcache_cooked_write (cache, tdep->r0->num, cbuf + len * 3); |
| 578 | regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 2); |
| 579 | regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 1); |
| 580 | regcache_cooked_write (cache, tdep->r3->num, cbuf); |
| 581 | } |
| 582 | else |
| 583 | { |
| 584 | regcache_cooked_write (cache, tdep->r0->num, cbuf); |
| 585 | regcache_cooked_write (cache, tdep->r1->num, cbuf + len * 1); |
| 586 | regcache_cooked_write (cache, tdep->r2->num, cbuf + len * 2); |
| 587 | regcache_cooked_write (cache, tdep->r3->num, cbuf + len * 3); |
| 588 | } |
| 589 | |
| 590 | return REG_VALID; |
| 591 | } |
| 592 | |
| 593 | |
| 594 | static enum register_status |
| 595 | m32c_pseudo_register_read (struct gdbarch *arch, |
| 596 | struct regcache *cache, |
| 597 | int cookednum, |
| 598 | gdb_byte *buf) |
| 599 | { |
| 600 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 601 | struct m32c_reg *reg; |
| 602 | |
| 603 | gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); |
| 604 | gdb_assert (arch == get_regcache_arch (cache)); |
| 605 | gdb_assert (arch == tdep->regs[cookednum].arch); |
| 606 | reg = &tdep->regs[cookednum]; |
| 607 | |
| 608 | return reg->read (reg, cache, buf); |
| 609 | } |
| 610 | |
| 611 | |
| 612 | static void |
| 613 | m32c_pseudo_register_write (struct gdbarch *arch, |
| 614 | struct regcache *cache, |
| 615 | int cookednum, |
| 616 | const gdb_byte *buf) |
| 617 | { |
| 618 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 619 | struct m32c_reg *reg; |
| 620 | |
| 621 | gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); |
| 622 | gdb_assert (arch == get_regcache_arch (cache)); |
| 623 | gdb_assert (arch == tdep->regs[cookednum].arch); |
| 624 | reg = &tdep->regs[cookednum]; |
| 625 | |
| 626 | reg->write (reg, cache, (void *) buf); |
| 627 | } |
| 628 | |
| 629 | |
| 630 | /* Add a register with the given fields to the end of ARCH's table. |
| 631 | Return a pointer to the newly added register. */ |
| 632 | static struct m32c_reg * |
| 633 | add_reg (struct gdbarch *arch, |
| 634 | const char *name, |
| 635 | struct type *type, |
| 636 | int sim_num, |
| 637 | m32c_move_reg_t *read, |
| 638 | m32c_move_reg_t *write, |
| 639 | struct m32c_reg *rx, |
| 640 | struct m32c_reg *ry, |
| 641 | int n) |
| 642 | { |
| 643 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 644 | struct m32c_reg *r = &tdep->regs[tdep->num_regs]; |
| 645 | |
| 646 | gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS); |
| 647 | |
| 648 | r->name = name; |
| 649 | r->type = type; |
| 650 | r->arch = arch; |
| 651 | r->num = tdep->num_regs; |
| 652 | r->sim_num = sim_num; |
| 653 | r->dwarf_num = -1; |
| 654 | r->general_p = 0; |
| 655 | r->dma_p = 0; |
| 656 | r->system_p = 0; |
| 657 | r->save_restore_p = 0; |
| 658 | r->read = read; |
| 659 | r->write = write; |
| 660 | r->rx = rx; |
| 661 | r->ry = ry; |
| 662 | r->n = n; |
| 663 | |
| 664 | tdep->num_regs++; |
| 665 | |
| 666 | return r; |
| 667 | } |
| 668 | |
| 669 | |
| 670 | /* Record NUM as REG's DWARF register number. */ |
| 671 | static void |
| 672 | set_dwarf_regnum (struct m32c_reg *reg, int num) |
| 673 | { |
| 674 | gdb_assert (num < M32C_MAX_NUM_REGS); |
| 675 | |
| 676 | /* Update the reg->DWARF mapping. Only count the first number |
| 677 | assigned to this register. */ |
| 678 | if (reg->dwarf_num == -1) |
| 679 | reg->dwarf_num = num; |
| 680 | |
| 681 | /* Update the DWARF->reg mapping. */ |
| 682 | gdbarch_tdep (reg->arch)->dwarf_regs[num] = reg; |
| 683 | } |
| 684 | |
| 685 | |
| 686 | /* Mark REG as a general-purpose register, and return it. */ |
| 687 | static struct m32c_reg * |
| 688 | mark_general (struct m32c_reg *reg) |
| 689 | { |
| 690 | reg->general_p = 1; |
| 691 | return reg; |
| 692 | } |
| 693 | |
| 694 | |
| 695 | /* Mark REG as a DMA register, and return it. */ |
| 696 | static struct m32c_reg * |
| 697 | mark_dma (struct m32c_reg *reg) |
| 698 | { |
| 699 | reg->dma_p = 1; |
| 700 | return reg; |
| 701 | } |
| 702 | |
| 703 | |
| 704 | /* Mark REG as a SYSTEM register, and return it. */ |
| 705 | static struct m32c_reg * |
| 706 | mark_system (struct m32c_reg *reg) |
| 707 | { |
| 708 | reg->system_p = 1; |
| 709 | return reg; |
| 710 | } |
| 711 | |
| 712 | |
| 713 | /* Mark REG as a save-restore register, and return it. */ |
| 714 | static struct m32c_reg * |
| 715 | mark_save_restore (struct m32c_reg *reg) |
| 716 | { |
| 717 | reg->save_restore_p = 1; |
| 718 | return reg; |
| 719 | } |
| 720 | |
| 721 | |
| 722 | #define FLAGBIT_B 0x0010 |
| 723 | #define FLAGBIT_U 0x0080 |
| 724 | |
| 725 | /* Handy macros for declaring registers. These all evaluate to |
| 726 | pointers to the register declared. Macros that define two |
| 727 | registers evaluate to a pointer to the first. */ |
| 728 | |
| 729 | /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */ |
| 730 | #define R(name, type, sim_num) \ |
| 731 | (add_reg (arch, (name), (type), (sim_num), \ |
| 732 | m32c_raw_read, m32c_raw_write, NULL, NULL, 0)) |
| 733 | |
| 734 | /* The simulator register number for a raw register named NAME. */ |
| 735 | #define SIM(name) (m32c_sim_reg_ ## name) |
| 736 | |
| 737 | /* A raw unsigned 16-bit data register named NAME. |
| 738 | NAME should be an identifier, not a string. */ |
| 739 | #define R16U(name) \ |
| 740 | (R(#name, tdep->uint16, SIM (name))) |
| 741 | |
| 742 | /* A raw data address register named NAME. |
| 743 | NAME should be an identifier, not a string. */ |
| 744 | #define RA(name) \ |
| 745 | (R(#name, tdep->data_addr_reg_type, SIM (name))) |
| 746 | |
| 747 | /* A raw code address register named NAME. NAME should |
| 748 | be an identifier, not a string. */ |
| 749 | #define RC(name) \ |
| 750 | (R(#name, tdep->code_addr_reg_type, SIM (name))) |
| 751 | |
| 752 | /* A pair of raw registers named NAME0 and NAME1, with type TYPE. |
| 753 | NAME should be an identifier, not a string. */ |
| 754 | #define RP(name, type) \ |
| 755 | (R(#name "0", (type), SIM (name ## 0)), \ |
| 756 | R(#name "1", (type), SIM (name ## 1)) - 1) |
| 757 | |
| 758 | /* A raw banked general-purpose data register named NAME. |
| 759 | NAME should be an identifier, not a string. */ |
| 760 | #define RBD(name) \ |
| 761 | (R(NULL, tdep->int16, SIM (name ## _bank0)), \ |
| 762 | R(NULL, tdep->int16, SIM (name ## _bank1)) - 1) |
| 763 | |
| 764 | /* A raw banked data address register named NAME. |
| 765 | NAME should be an identifier, not a string. */ |
| 766 | #define RBA(name) \ |
| 767 | (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)), \ |
| 768 | R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1) |
| 769 | |
| 770 | /* A cooked register named NAME referring to a raw banked register |
| 771 | from the bank selected by the current value of FLG. RAW_PAIR |
| 772 | should be a pointer to the first register in the banked pair. |
| 773 | NAME must be an identifier, not a string. */ |
| 774 | #define CB(name, raw_pair) \ |
| 775 | (add_reg (arch, #name, (raw_pair)->type, 0, \ |
| 776 | m32c_banked_read, m32c_banked_write, \ |
| 777 | (raw_pair), (raw_pair + 1), FLAGBIT_B)) |
| 778 | |
| 779 | /* A pair of registers named NAMEH and NAMEL, of type TYPE, that |
| 780 | access the top and bottom halves of the register pointed to by |
| 781 | NAME. NAME should be an identifier. */ |
| 782 | #define CHL(name, type) \ |
| 783 | (add_reg (arch, #name "h", (type), 0, \ |
| 784 | m32c_part_read, m32c_part_write, name, NULL, 1), \ |
| 785 | add_reg (arch, #name "l", (type), 0, \ |
| 786 | m32c_part_read, m32c_part_write, name, NULL, 0) - 1) |
| 787 | |
| 788 | /* A register constructed by concatenating the two registers HIGH and |
| 789 | LOW, whose name is HIGHLOW and whose type is TYPE. */ |
| 790 | #define CCAT(high, low, type) \ |
| 791 | (add_reg (arch, #high #low, (type), 0, \ |
| 792 | m32c_cat_read, m32c_cat_write, (high), (low), 0)) |
| 793 | |
| 794 | /* Abbreviations for marking register group membership. */ |
| 795 | #define G(reg) (mark_general (reg)) |
| 796 | #define S(reg) (mark_system (reg)) |
| 797 | #define DMA(reg) (mark_dma (reg)) |
| 798 | |
| 799 | |
| 800 | /* Construct the register set for ARCH. */ |
| 801 | static void |
| 802 | make_regs (struct gdbarch *arch) |
| 803 | { |
| 804 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 805 | int mach = gdbarch_bfd_arch_info (arch)->mach; |
| 806 | int num_raw_regs; |
| 807 | int num_cooked_regs; |
| 808 | |
| 809 | struct m32c_reg *r0; |
| 810 | struct m32c_reg *r1; |
| 811 | struct m32c_reg *r2; |
| 812 | struct m32c_reg *r3; |
| 813 | struct m32c_reg *a0; |
| 814 | struct m32c_reg *a1; |
| 815 | struct m32c_reg *fb; |
| 816 | struct m32c_reg *sb; |
| 817 | struct m32c_reg *sp; |
| 818 | struct m32c_reg *r0hl; |
| 819 | struct m32c_reg *r1hl; |
| 820 | struct m32c_reg *r2hl; |
| 821 | struct m32c_reg *r3hl; |
| 822 | struct m32c_reg *intbhl; |
| 823 | struct m32c_reg *r2r0; |
| 824 | struct m32c_reg *r3r1; |
| 825 | struct m32c_reg *r3r1r2r0; |
| 826 | struct m32c_reg *r3r2r1r0; |
| 827 | struct m32c_reg *a1a0; |
| 828 | |
| 829 | struct m32c_reg *raw_r0_pair = RBD (r0); |
| 830 | struct m32c_reg *raw_r1_pair = RBD (r1); |
| 831 | struct m32c_reg *raw_r2_pair = RBD (r2); |
| 832 | struct m32c_reg *raw_r3_pair = RBD (r3); |
| 833 | struct m32c_reg *raw_a0_pair = RBA (a0); |
| 834 | struct m32c_reg *raw_a1_pair = RBA (a1); |
| 835 | struct m32c_reg *raw_fb_pair = RBA (fb); |
| 836 | |
| 837 | /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. |
| 838 | We always declare both raw registers, and deal with the distinction |
| 839 | in the pseudoregister. */ |
| 840 | struct m32c_reg *raw_sb_pair = RBA (sb); |
| 841 | |
| 842 | struct m32c_reg *usp = S (RA (usp)); |
| 843 | struct m32c_reg *isp = S (RA (isp)); |
| 844 | struct m32c_reg *intb = S (RC (intb)); |
| 845 | struct m32c_reg *pc = G (RC (pc)); |
| 846 | struct m32c_reg *flg = G (R16U (flg)); |
| 847 | |
| 848 | if (mach == bfd_mach_m32c) |
| 849 | { |
| 850 | struct m32c_reg *svf = S (R16U (svf)); |
| 851 | struct m32c_reg *svp = S (RC (svp)); |
| 852 | struct m32c_reg *vct = S (RC (vct)); |
| 853 | |
| 854 | struct m32c_reg *dmd01 = DMA (RP (dmd, tdep->uint8)); |
| 855 | struct m32c_reg *dct01 = DMA (RP (dct, tdep->uint16)); |
| 856 | struct m32c_reg *drc01 = DMA (RP (drc, tdep->uint16)); |
| 857 | struct m32c_reg *dma01 = DMA (RP (dma, tdep->data_addr_reg_type)); |
| 858 | struct m32c_reg *dsa01 = DMA (RP (dsa, tdep->data_addr_reg_type)); |
| 859 | struct m32c_reg *dra01 = DMA (RP (dra, tdep->data_addr_reg_type)); |
| 860 | } |
| 861 | |
| 862 | num_raw_regs = tdep->num_regs; |
| 863 | |
| 864 | r0 = G (CB (r0, raw_r0_pair)); |
| 865 | r1 = G (CB (r1, raw_r1_pair)); |
| 866 | r2 = G (CB (r2, raw_r2_pair)); |
| 867 | r3 = G (CB (r3, raw_r3_pair)); |
| 868 | a0 = G (CB (a0, raw_a0_pair)); |
| 869 | a1 = G (CB (a1, raw_a1_pair)); |
| 870 | fb = G (CB (fb, raw_fb_pair)); |
| 871 | |
| 872 | /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. |
| 873 | Specify custom read/write functions that do the right thing. */ |
| 874 | sb = G (add_reg (arch, "sb", raw_sb_pair->type, 0, |
| 875 | m32c_sb_read, m32c_sb_write, |
| 876 | raw_sb_pair, raw_sb_pair + 1, 0)); |
| 877 | |
| 878 | /* The current sp is either usp or isp, depending on the value of |
| 879 | the FLG register's U bit. */ |
| 880 | sp = G (add_reg (arch, "sp", usp->type, 0, |
| 881 | m32c_banked_read, m32c_banked_write, |
| 882 | isp, usp, FLAGBIT_U)); |
| 883 | |
| 884 | r0hl = CHL (r0, tdep->int8); |
| 885 | r1hl = CHL (r1, tdep->int8); |
| 886 | r2hl = CHL (r2, tdep->int8); |
| 887 | r3hl = CHL (r3, tdep->int8); |
| 888 | intbhl = CHL (intb, tdep->int16); |
| 889 | |
| 890 | r2r0 = CCAT (r2, r0, tdep->int32); |
| 891 | r3r1 = CCAT (r3, r1, tdep->int32); |
| 892 | r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64); |
| 893 | |
| 894 | r3r2r1r0 |
| 895 | = add_reg (arch, "r3r2r1r0", tdep->int64, 0, |
| 896 | m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0); |
| 897 | |
| 898 | if (mach == bfd_mach_m16c) |
| 899 | a1a0 = CCAT (a1, a0, tdep->int32); |
| 900 | else |
| 901 | a1a0 = NULL; |
| 902 | |
| 903 | num_cooked_regs = tdep->num_regs - num_raw_regs; |
| 904 | |
| 905 | tdep->pc = pc; |
| 906 | tdep->flg = flg; |
| 907 | tdep->r0 = r0; |
| 908 | tdep->r1 = r1; |
| 909 | tdep->r2 = r2; |
| 910 | tdep->r3 = r3; |
| 911 | tdep->r2r0 = r2r0; |
| 912 | tdep->r3r2r1r0 = r3r2r1r0; |
| 913 | tdep->r3r1r2r0 = r3r1r2r0; |
| 914 | tdep->a0 = a0; |
| 915 | tdep->a1 = a1; |
| 916 | tdep->sb = sb; |
| 917 | tdep->fb = fb; |
| 918 | tdep->sp = sp; |
| 919 | |
| 920 | /* Set up the DWARF register table. */ |
| 921 | memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs)); |
| 922 | set_dwarf_regnum (r0hl + 1, 0x01); |
| 923 | set_dwarf_regnum (r0hl + 0, 0x02); |
| 924 | set_dwarf_regnum (r1hl + 1, 0x03); |
| 925 | set_dwarf_regnum (r1hl + 0, 0x04); |
| 926 | set_dwarf_regnum (r0, 0x05); |
| 927 | set_dwarf_regnum (r1, 0x06); |
| 928 | set_dwarf_regnum (r2, 0x07); |
| 929 | set_dwarf_regnum (r3, 0x08); |
| 930 | set_dwarf_regnum (a0, 0x09); |
| 931 | set_dwarf_regnum (a1, 0x0a); |
| 932 | set_dwarf_regnum (fb, 0x0b); |
| 933 | set_dwarf_regnum (sp, 0x0c); |
| 934 | set_dwarf_regnum (pc, 0x0d); /* GCC's invention */ |
| 935 | set_dwarf_regnum (sb, 0x13); |
| 936 | set_dwarf_regnum (r2r0, 0x15); |
| 937 | set_dwarf_regnum (r3r1, 0x16); |
| 938 | if (a1a0) |
| 939 | set_dwarf_regnum (a1a0, 0x17); |
| 940 | |
| 941 | /* Enumerate the save/restore register group. |
| 942 | |
| 943 | The regcache_save and regcache_restore functions apply their read |
| 944 | function to each register in this group. |
| 945 | |
| 946 | Since frame_pop supplies frame_unwind_register as its read |
| 947 | function, the registers meaningful to the Dwarf unwinder need to |
| 948 | be in this group. |
| 949 | |
| 950 | On the other hand, when we make inferior calls, save_inferior_status |
| 951 | and restore_inferior_status use them to preserve the current register |
| 952 | values across the inferior call. For this, you'd kind of like to |
| 953 | preserve all the raw registers, to protect the interrupted code from |
| 954 | any sort of bank switching the callee might have done. But we handle |
| 955 | those cases so badly anyway --- for example, it matters whether we |
| 956 | restore FLG before or after we restore the general-purpose registers, |
| 957 | but there's no way to express that --- that it isn't worth worrying |
| 958 | about. |
| 959 | |
| 960 | We omit control registers like inthl: if you call a function that |
| 961 | changes those, it's probably because you wanted that change to be |
| 962 | visible to the interrupted code. */ |
| 963 | mark_save_restore (r0); |
| 964 | mark_save_restore (r1); |
| 965 | mark_save_restore (r2); |
| 966 | mark_save_restore (r3); |
| 967 | mark_save_restore (a0); |
| 968 | mark_save_restore (a1); |
| 969 | mark_save_restore (sb); |
| 970 | mark_save_restore (fb); |
| 971 | mark_save_restore (sp); |
| 972 | mark_save_restore (pc); |
| 973 | mark_save_restore (flg); |
| 974 | |
| 975 | set_gdbarch_num_regs (arch, num_raw_regs); |
| 976 | set_gdbarch_num_pseudo_regs (arch, num_cooked_regs); |
| 977 | set_gdbarch_pc_regnum (arch, pc->num); |
| 978 | set_gdbarch_sp_regnum (arch, sp->num); |
| 979 | set_gdbarch_register_name (arch, m32c_register_name); |
| 980 | set_gdbarch_register_type (arch, m32c_register_type); |
| 981 | set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read); |
| 982 | set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write); |
| 983 | set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno); |
| 984 | set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); |
| 985 | set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); |
| 986 | set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p); |
| 987 | |
| 988 | reggroup_add (arch, general_reggroup); |
| 989 | reggroup_add (arch, all_reggroup); |
| 990 | reggroup_add (arch, save_reggroup); |
| 991 | reggroup_add (arch, restore_reggroup); |
| 992 | reggroup_add (arch, system_reggroup); |
| 993 | reggroup_add (arch, m32c_dma_reggroup); |
| 994 | } |
| 995 | |
| 996 | |
| 997 | \f |
| 998 | /* Breakpoints. */ |
| 999 | |
| 1000 | static const unsigned char * |
| 1001 | m32c_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
| 1002 | { |
| 1003 | static unsigned char break_insn[] = { 0x00 }; /* brk */ |
| 1004 | |
| 1005 | *len = sizeof (break_insn); |
| 1006 | return break_insn; |
| 1007 | } |
| 1008 | |
| 1009 | |
| 1010 | \f |
| 1011 | /* Prologue analysis. */ |
| 1012 | |
| 1013 | enum m32c_prologue_kind |
| 1014 | { |
| 1015 | /* This function uses a frame pointer. */ |
| 1016 | prologue_with_frame_ptr, |
| 1017 | |
| 1018 | /* This function has no frame pointer. */ |
| 1019 | prologue_sans_frame_ptr, |
| 1020 | |
| 1021 | /* This function sets up the stack, so its frame is the first |
| 1022 | frame on the stack. */ |
| 1023 | prologue_first_frame |
| 1024 | }; |
| 1025 | |
| 1026 | struct m32c_prologue |
| 1027 | { |
| 1028 | /* For consistency with the DWARF 2 .debug_frame info generated by |
| 1029 | GCC, a frame's CFA is the address immediately after the saved |
| 1030 | return address. */ |
| 1031 | |
| 1032 | /* The architecture for which we generated this prologue info. */ |
| 1033 | struct gdbarch *arch; |
| 1034 | |
| 1035 | enum m32c_prologue_kind kind; |
| 1036 | |
| 1037 | /* If KIND is prologue_with_frame_ptr, this is the offset from the |
| 1038 | CFA to where the frame pointer points. This is always zero or |
| 1039 | negative. */ |
| 1040 | LONGEST frame_ptr_offset; |
| 1041 | |
| 1042 | /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to |
| 1043 | the stack pointer --- always zero or negative. |
| 1044 | |
| 1045 | Calling this a "size" is a bit misleading, but given that the |
| 1046 | stack grows downwards, using offsets for everything keeps one |
| 1047 | from going completely sign-crazy: you never change anything's |
| 1048 | sign for an ADD instruction; always change the second operand's |
| 1049 | sign for a SUB instruction; and everything takes care of |
| 1050 | itself. |
| 1051 | |
| 1052 | Functions that use alloca don't have a constant frame size. But |
| 1053 | they always have frame pointers, so we must use that to find the |
| 1054 | CFA (and perhaps to unwind the stack pointer). */ |
| 1055 | LONGEST frame_size; |
| 1056 | |
| 1057 | /* The address of the first instruction at which the frame has been |
| 1058 | set up and the arguments are where the debug info says they are |
| 1059 | --- as best as we can tell. */ |
| 1060 | CORE_ADDR prologue_end; |
| 1061 | |
| 1062 | /* reg_offset[R] is the offset from the CFA at which register R is |
| 1063 | saved, or 1 if register R has not been saved. (Real values are |
| 1064 | always zero or negative.) */ |
| 1065 | LONGEST reg_offset[M32C_MAX_NUM_REGS]; |
| 1066 | }; |
| 1067 | |
| 1068 | |
| 1069 | /* The longest I've seen, anyway. */ |
| 1070 | #define M32C_MAX_INSN_LEN (9) |
| 1071 | |
| 1072 | /* Processor state, for the prologue analyzer. */ |
| 1073 | struct m32c_pv_state |
| 1074 | { |
| 1075 | struct gdbarch *arch; |
| 1076 | pv_t r0, r1, r2, r3; |
| 1077 | pv_t a0, a1; |
| 1078 | pv_t sb, fb, sp; |
| 1079 | pv_t pc; |
| 1080 | struct pv_area *stack; |
| 1081 | |
| 1082 | /* Bytes from the current PC, the address they were read from, |
| 1083 | and the address of the next unconsumed byte. */ |
| 1084 | gdb_byte insn[M32C_MAX_INSN_LEN]; |
| 1085 | CORE_ADDR scan_pc, next_addr; |
| 1086 | }; |
| 1087 | |
| 1088 | |
| 1089 | /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if |
| 1090 | all went well, or non-zero if simulating the action would trash our |
| 1091 | state. */ |
| 1092 | static int |
| 1093 | m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size) |
| 1094 | { |
| 1095 | if (pv_area_store_would_trash (state->stack, state->sp)) |
| 1096 | return 1; |
| 1097 | |
| 1098 | state->sp = pv_add_constant (state->sp, -size); |
| 1099 | pv_area_store (state->stack, state->sp, size, value); |
| 1100 | |
| 1101 | return 0; |
| 1102 | } |
| 1103 | |
| 1104 | |
| 1105 | enum srcdest_kind |
| 1106 | { |
| 1107 | srcdest_reg, |
| 1108 | srcdest_partial_reg, |
| 1109 | srcdest_mem |
| 1110 | }; |
| 1111 | |
| 1112 | /* A source or destination location for an m16c or m32c |
| 1113 | instruction. */ |
| 1114 | struct srcdest |
| 1115 | { |
| 1116 | /* If srcdest_reg, the location is a register pointed to by REG. |
| 1117 | If srcdest_partial_reg, the location is part of a register pointed |
| 1118 | to by REG. We don't try to handle this too well. |
| 1119 | If srcdest_mem, the location is memory whose address is ADDR. */ |
| 1120 | enum srcdest_kind kind; |
| 1121 | pv_t *reg, addr; |
| 1122 | }; |
| 1123 | |
| 1124 | |
| 1125 | /* Return the SIZE-byte value at LOC in STATE. */ |
| 1126 | static pv_t |
| 1127 | m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size) |
| 1128 | { |
| 1129 | if (loc.kind == srcdest_mem) |
| 1130 | return pv_area_fetch (state->stack, loc.addr, size); |
| 1131 | else if (loc.kind == srcdest_partial_reg) |
| 1132 | return pv_unknown (); |
| 1133 | else |
| 1134 | return *loc.reg; |
| 1135 | } |
| 1136 | |
| 1137 | |
| 1138 | /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if |
| 1139 | all went well, or non-zero if simulating the store would trash our |
| 1140 | state. */ |
| 1141 | static int |
| 1142 | m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc, |
| 1143 | pv_t value, int size) |
| 1144 | { |
| 1145 | if (loc.kind == srcdest_mem) |
| 1146 | { |
| 1147 | if (pv_area_store_would_trash (state->stack, loc.addr)) |
| 1148 | return 1; |
| 1149 | pv_area_store (state->stack, loc.addr, size, value); |
| 1150 | } |
| 1151 | else if (loc.kind == srcdest_partial_reg) |
| 1152 | *loc.reg = pv_unknown (); |
| 1153 | else |
| 1154 | *loc.reg = value; |
| 1155 | |
| 1156 | return 0; |
| 1157 | } |
| 1158 | |
| 1159 | |
| 1160 | static int |
| 1161 | m32c_sign_ext (int v, int bits) |
| 1162 | { |
| 1163 | int mask = 1 << (bits - 1); |
| 1164 | return (v ^ mask) - mask; |
| 1165 | } |
| 1166 | |
| 1167 | static unsigned int |
| 1168 | m32c_next_byte (struct m32c_pv_state *st) |
| 1169 | { |
| 1170 | gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn)); |
| 1171 | return st->insn[st->next_addr++ - st->scan_pc]; |
| 1172 | } |
| 1173 | |
| 1174 | static int |
| 1175 | m32c_udisp8 (struct m32c_pv_state *st) |
| 1176 | { |
| 1177 | return m32c_next_byte (st); |
| 1178 | } |
| 1179 | |
| 1180 | |
| 1181 | static int |
| 1182 | m32c_sdisp8 (struct m32c_pv_state *st) |
| 1183 | { |
| 1184 | return m32c_sign_ext (m32c_next_byte (st), 8); |
| 1185 | } |
| 1186 | |
| 1187 | |
| 1188 | static int |
| 1189 | m32c_udisp16 (struct m32c_pv_state *st) |
| 1190 | { |
| 1191 | int low = m32c_next_byte (st); |
| 1192 | int high = m32c_next_byte (st); |
| 1193 | |
| 1194 | return low + (high << 8); |
| 1195 | } |
| 1196 | |
| 1197 | |
| 1198 | static int |
| 1199 | m32c_sdisp16 (struct m32c_pv_state *st) |
| 1200 | { |
| 1201 | int low = m32c_next_byte (st); |
| 1202 | int high = m32c_next_byte (st); |
| 1203 | |
| 1204 | return m32c_sign_ext (low + (high << 8), 16); |
| 1205 | } |
| 1206 | |
| 1207 | |
| 1208 | static int |
| 1209 | m32c_udisp24 (struct m32c_pv_state *st) |
| 1210 | { |
| 1211 | int low = m32c_next_byte (st); |
| 1212 | int mid = m32c_next_byte (st); |
| 1213 | int high = m32c_next_byte (st); |
| 1214 | |
| 1215 | return low + (mid << 8) + (high << 16); |
| 1216 | } |
| 1217 | |
| 1218 | |
| 1219 | /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */ |
| 1220 | static int |
| 1221 | m32c_get_src23 (unsigned char *i) |
| 1222 | { |
| 1223 | return (((i[0] & 0x70) >> 2) |
| 1224 | | ((i[1] & 0x30) >> 4)); |
| 1225 | } |
| 1226 | |
| 1227 | |
| 1228 | /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */ |
| 1229 | static int |
| 1230 | m32c_get_dest23 (unsigned char *i) |
| 1231 | { |
| 1232 | return (((i[0] & 0x0e) << 1) |
| 1233 | | ((i[1] & 0xc0) >> 6)); |
| 1234 | } |
| 1235 | |
| 1236 | |
| 1237 | static struct srcdest |
| 1238 | m32c_decode_srcdest4 (struct m32c_pv_state *st, |
| 1239 | int code, int size) |
| 1240 | { |
| 1241 | struct srcdest sd; |
| 1242 | |
| 1243 | if (code < 6) |
| 1244 | sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg); |
| 1245 | else |
| 1246 | sd.kind = srcdest_mem; |
| 1247 | |
| 1248 | sd.addr = pv_unknown (); |
| 1249 | sd.reg = 0; |
| 1250 | |
| 1251 | switch (code) |
| 1252 | { |
| 1253 | case 0x0: sd.reg = (size == 1 ? &st->r0 : &st->r0); break; |
| 1254 | case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break; |
| 1255 | case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break; |
| 1256 | case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break; |
| 1257 | |
| 1258 | case 0x4: sd.reg = &st->a0; break; |
| 1259 | case 0x5: sd.reg = &st->a1; break; |
| 1260 | |
| 1261 | case 0x6: sd.addr = st->a0; break; |
| 1262 | case 0x7: sd.addr = st->a1; break; |
| 1263 | |
| 1264 | case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; |
| 1265 | case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; |
| 1266 | case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; |
| 1267 | case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; |
| 1268 | |
| 1269 | case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; |
| 1270 | case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; |
| 1271 | case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; |
| 1272 | case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break; |
| 1273 | |
| 1274 | default: |
| 1275 | gdb_assert_not_reached ("unexpected srcdest4"); |
| 1276 | } |
| 1277 | |
| 1278 | return sd; |
| 1279 | } |
| 1280 | |
| 1281 | |
| 1282 | static struct srcdest |
| 1283 | m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind) |
| 1284 | { |
| 1285 | struct srcdest sd; |
| 1286 | |
| 1287 | sd.addr = pv_unknown (); |
| 1288 | sd.reg = 0; |
| 1289 | |
| 1290 | switch (code) |
| 1291 | { |
| 1292 | case 0x12: |
| 1293 | case 0x13: |
| 1294 | case 0x10: |
| 1295 | case 0x11: |
| 1296 | sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg; |
| 1297 | break; |
| 1298 | |
| 1299 | case 0x02: |
| 1300 | case 0x03: |
| 1301 | sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg; |
| 1302 | break; |
| 1303 | |
| 1304 | default: |
| 1305 | sd.kind = srcdest_mem; |
| 1306 | break; |
| 1307 | |
| 1308 | } |
| 1309 | |
| 1310 | switch (code) |
| 1311 | { |
| 1312 | case 0x12: sd.reg = &st->r0; break; |
| 1313 | case 0x13: sd.reg = &st->r1; break; |
| 1314 | case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break; |
| 1315 | case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break; |
| 1316 | case 0x02: sd.reg = &st->a0; break; |
| 1317 | case 0x03: sd.reg = &st->a1; break; |
| 1318 | |
| 1319 | case 0x00: sd.addr = st->a0; break; |
| 1320 | case 0x01: sd.addr = st->a1; break; |
| 1321 | case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; |
| 1322 | case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; |
| 1323 | case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; |
| 1324 | case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; |
| 1325 | case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; |
| 1326 | case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; |
| 1327 | case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; |
| 1328 | case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break; |
| 1329 | case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break; |
| 1330 | case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break; |
| 1331 | case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break; |
| 1332 | case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break; |
| 1333 | default: |
| 1334 | gdb_assert_not_reached ("unexpected sd23"); |
| 1335 | } |
| 1336 | |
| 1337 | if (ind) |
| 1338 | { |
| 1339 | sd.addr = m32c_srcdest_fetch (st, sd, 4); |
| 1340 | sd.kind = srcdest_mem; |
| 1341 | } |
| 1342 | |
| 1343 | return sd; |
| 1344 | } |
| 1345 | |
| 1346 | |
| 1347 | /* The r16c and r32c machines have instructions with similar |
| 1348 | semantics, but completely different machine language encodings. So |
| 1349 | we break out the semantics into their own functions, and leave |
| 1350 | machine-specific decoding in m32c_analyze_prologue. |
| 1351 | |
| 1352 | The following functions all expect their arguments already decoded, |
| 1353 | and they all return zero if analysis should continue past this |
| 1354 | instruction, or non-zero if analysis should stop. */ |
| 1355 | |
| 1356 | |
| 1357 | /* Simulate an 'enter SIZE' instruction in STATE. */ |
| 1358 | static int |
| 1359 | m32c_pv_enter (struct m32c_pv_state *state, int size) |
| 1360 | { |
| 1361 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); |
| 1362 | |
| 1363 | /* If simulating this store would require us to forget |
| 1364 | everything we know about the stack frame in the name of |
| 1365 | accuracy, it would be better to just quit now. */ |
| 1366 | if (pv_area_store_would_trash (state->stack, state->sp)) |
| 1367 | return 1; |
| 1368 | |
| 1369 | if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes)) |
| 1370 | return 1; |
| 1371 | state->fb = state->sp; |
| 1372 | state->sp = pv_add_constant (state->sp, -size); |
| 1373 | |
| 1374 | return 0; |
| 1375 | } |
| 1376 | |
| 1377 | |
| 1378 | static int |
| 1379 | m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg, |
| 1380 | int bit, int src, int size) |
| 1381 | { |
| 1382 | if (bit & src) |
| 1383 | { |
| 1384 | if (m32c_pv_push (state, reg, size)) |
| 1385 | return 1; |
| 1386 | } |
| 1387 | |
| 1388 | return 0; |
| 1389 | } |
| 1390 | |
| 1391 | |
| 1392 | /* Simulate a 'pushm SRC' instruction in STATE. */ |
| 1393 | static int |
| 1394 | m32c_pv_pushm (struct m32c_pv_state *state, int src) |
| 1395 | { |
| 1396 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); |
| 1397 | |
| 1398 | /* The bits in SRC indicating which registers to save are: |
| 1399 | r0 r1 r2 r3 a0 a1 sb fb */ |
| 1400 | return |
| 1401 | ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes) |
| 1402 | || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes) |
| 1403 | || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes) |
| 1404 | || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes) |
| 1405 | || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2) |
| 1406 | || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2) |
| 1407 | || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2) |
| 1408 | || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2)); |
| 1409 | } |
| 1410 | |
| 1411 | /* Return non-zero if VALUE is the first incoming argument register. */ |
| 1412 | |
| 1413 | static int |
| 1414 | m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value) |
| 1415 | { |
| 1416 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); |
| 1417 | return (value.kind == pvk_register |
| 1418 | && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c |
| 1419 | ? (value.reg == tdep->r1->num) |
| 1420 | : (value.reg == tdep->r0->num)) |
| 1421 | && value.k == 0); |
| 1422 | } |
| 1423 | |
| 1424 | /* Return non-zero if VALUE is an incoming argument register. */ |
| 1425 | |
| 1426 | static int |
| 1427 | m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value) |
| 1428 | { |
| 1429 | struct gdbarch_tdep *tdep = gdbarch_tdep (state->arch); |
| 1430 | return (value.kind == pvk_register |
| 1431 | && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c |
| 1432 | ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num) |
| 1433 | : (value.reg == tdep->r0->num)) |
| 1434 | && value.k == 0); |
| 1435 | } |
| 1436 | |
| 1437 | /* Return non-zero if a store of VALUE to LOC is probably spilling an |
| 1438 | argument register to its stack slot in STATE. Such instructions |
| 1439 | should be included in the prologue, if possible. |
| 1440 | |
| 1441 | The store is a spill if: |
| 1442 | - the value being stored is the original value of an argument register; |
| 1443 | - the value has not already been stored somewhere in STACK; and |
| 1444 | - LOC is a stack slot (e.g., a memory location whose address is |
| 1445 | relative to the original value of the SP). */ |
| 1446 | |
| 1447 | static int |
| 1448 | m32c_is_arg_spill (struct m32c_pv_state *st, |
| 1449 | struct srcdest loc, |
| 1450 | pv_t value) |
| 1451 | { |
| 1452 | struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); |
| 1453 | |
| 1454 | return (m32c_is_arg_reg (st, value) |
| 1455 | && loc.kind == srcdest_mem |
| 1456 | && pv_is_register (loc.addr, tdep->sp->num) |
| 1457 | && ! pv_area_find_reg (st->stack, st->arch, value.reg, 0)); |
| 1458 | } |
| 1459 | |
| 1460 | /* Return non-zero if a store of VALUE to LOC is probably |
| 1461 | copying the struct return address into an address register |
| 1462 | for immediate use. This is basically a "spill" into the |
| 1463 | address register, instead of onto the stack. |
| 1464 | |
| 1465 | The prerequisites are: |
| 1466 | - value being stored is original value of the FIRST arg register; |
| 1467 | - value has not already been stored on stack; and |
| 1468 | - LOC is an address register (a0 or a1). */ |
| 1469 | |
| 1470 | static int |
| 1471 | m32c_is_struct_return (struct m32c_pv_state *st, |
| 1472 | struct srcdest loc, |
| 1473 | pv_t value) |
| 1474 | { |
| 1475 | struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); |
| 1476 | |
| 1477 | return (m32c_is_1st_arg_reg (st, value) |
| 1478 | && !pv_area_find_reg (st->stack, st->arch, value.reg, 0) |
| 1479 | && loc.kind == srcdest_reg |
| 1480 | && (pv_is_register (*loc.reg, tdep->a0->num) |
| 1481 | || pv_is_register (*loc.reg, tdep->a1->num))); |
| 1482 | } |
| 1483 | |
| 1484 | /* Return non-zero if a 'pushm' saving the registers indicated by SRC |
| 1485 | was a register save: |
| 1486 | - all the named registers should have their original values, and |
| 1487 | - the stack pointer should be at a constant offset from the |
| 1488 | original stack pointer. */ |
| 1489 | static int |
| 1490 | m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src) |
| 1491 | { |
| 1492 | struct gdbarch_tdep *tdep = gdbarch_tdep (st->arch); |
| 1493 | /* The bits in SRC indicating which registers to save are: |
| 1494 | r0 r1 r2 r3 a0 a1 sb fb */ |
| 1495 | return |
| 1496 | (pv_is_register (st->sp, tdep->sp->num) |
| 1497 | && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0)) |
| 1498 | && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0)) |
| 1499 | && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0)) |
| 1500 | && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0)) |
| 1501 | && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0)) |
| 1502 | && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0)) |
| 1503 | && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0)) |
| 1504 | && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0))); |
| 1505 | } |
| 1506 | |
| 1507 | |
| 1508 | /* Function for finding saved registers in a 'struct pv_area'; we pass |
| 1509 | this to pv_area_scan. |
| 1510 | |
| 1511 | If VALUE is a saved register, ADDR says it was saved at a constant |
| 1512 | offset from the frame base, and SIZE indicates that the whole |
| 1513 | register was saved, record its offset in RESULT_UNTYPED. */ |
| 1514 | static void |
| 1515 | check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value) |
| 1516 | { |
| 1517 | struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped; |
| 1518 | struct gdbarch *arch = prologue->arch; |
| 1519 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 1520 | |
| 1521 | /* Is this the unchanged value of some register being saved on the |
| 1522 | stack? */ |
| 1523 | if (value.kind == pvk_register |
| 1524 | && value.k == 0 |
| 1525 | && pv_is_register (addr, tdep->sp->num)) |
| 1526 | { |
| 1527 | /* Some registers require special handling: they're saved as a |
| 1528 | larger value than the register itself. */ |
| 1529 | CORE_ADDR saved_size = register_size (arch, value.reg); |
| 1530 | |
| 1531 | if (value.reg == tdep->pc->num) |
| 1532 | saved_size = tdep->ret_addr_bytes; |
| 1533 | else if (register_type (arch, value.reg) |
| 1534 | == tdep->data_addr_reg_type) |
| 1535 | saved_size = tdep->push_addr_bytes; |
| 1536 | |
| 1537 | if (size == saved_size) |
| 1538 | { |
| 1539 | /* Find which end of the saved value corresponds to our |
| 1540 | register. */ |
| 1541 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) |
| 1542 | prologue->reg_offset[value.reg] |
| 1543 | = (addr.k + saved_size - register_size (arch, value.reg)); |
| 1544 | else |
| 1545 | prologue->reg_offset[value.reg] = addr.k; |
| 1546 | } |
| 1547 | } |
| 1548 | } |
| 1549 | |
| 1550 | |
| 1551 | /* Analyze the function prologue for ARCH at START, going no further |
| 1552 | than LIMIT, and place a description of what we found in |
| 1553 | PROLOGUE. */ |
| 1554 | static void |
| 1555 | m32c_analyze_prologue (struct gdbarch *arch, |
| 1556 | CORE_ADDR start, CORE_ADDR limit, |
| 1557 | struct m32c_prologue *prologue) |
| 1558 | { |
| 1559 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 1560 | unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; |
| 1561 | CORE_ADDR after_last_frame_related_insn; |
| 1562 | struct cleanup *back_to; |
| 1563 | struct m32c_pv_state st; |
| 1564 | |
| 1565 | st.arch = arch; |
| 1566 | st.r0 = pv_register (tdep->r0->num, 0); |
| 1567 | st.r1 = pv_register (tdep->r1->num, 0); |
| 1568 | st.r2 = pv_register (tdep->r2->num, 0); |
| 1569 | st.r3 = pv_register (tdep->r3->num, 0); |
| 1570 | st.a0 = pv_register (tdep->a0->num, 0); |
| 1571 | st.a1 = pv_register (tdep->a1->num, 0); |
| 1572 | st.sb = pv_register (tdep->sb->num, 0); |
| 1573 | st.fb = pv_register (tdep->fb->num, 0); |
| 1574 | st.sp = pv_register (tdep->sp->num, 0); |
| 1575 | st.pc = pv_register (tdep->pc->num, 0); |
| 1576 | st.stack = make_pv_area (tdep->sp->num, gdbarch_addr_bit (arch)); |
| 1577 | back_to = make_cleanup_free_pv_area (st.stack); |
| 1578 | |
| 1579 | /* Record that the call instruction has saved the return address on |
| 1580 | the stack. */ |
| 1581 | m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes); |
| 1582 | |
| 1583 | memset (prologue, 0, sizeof (*prologue)); |
| 1584 | prologue->arch = arch; |
| 1585 | { |
| 1586 | int i; |
| 1587 | for (i = 0; i < M32C_MAX_NUM_REGS; i++) |
| 1588 | prologue->reg_offset[i] = 1; |
| 1589 | } |
| 1590 | |
| 1591 | st.scan_pc = after_last_frame_related_insn = start; |
| 1592 | |
| 1593 | while (st.scan_pc < limit) |
| 1594 | { |
| 1595 | pv_t pre_insn_fb = st.fb; |
| 1596 | pv_t pre_insn_sp = st.sp; |
| 1597 | |
| 1598 | /* In theory we could get in trouble by trying to read ahead |
| 1599 | here, when we only know we're expecting one byte. In |
| 1600 | practice I doubt anyone will care, and it makes the rest of |
| 1601 | the code easier. */ |
| 1602 | if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn))) |
| 1603 | /* If we can't fetch the instruction from memory, stop here |
| 1604 | and hope for the best. */ |
| 1605 | break; |
| 1606 | st.next_addr = st.scan_pc; |
| 1607 | |
| 1608 | /* The assembly instructions are written as they appear in the |
| 1609 | section of the processor manuals that describe the |
| 1610 | instruction encodings. |
| 1611 | |
| 1612 | When a single assembly language instruction has several |
| 1613 | different machine-language encodings, the manual |
| 1614 | distinguishes them by a number in parens, before the |
| 1615 | mnemonic. Those numbers are included, as well. |
| 1616 | |
| 1617 | The srcdest decoding instructions have the same names as the |
| 1618 | analogous functions in the simulator. */ |
| 1619 | if (mach == bfd_mach_m16c) |
| 1620 | { |
| 1621 | /* (1) ENTER #imm8 */ |
| 1622 | if (st.insn[0] == 0x7c && st.insn[1] == 0xf2) |
| 1623 | { |
| 1624 | if (m32c_pv_enter (&st, st.insn[2])) |
| 1625 | break; |
| 1626 | st.next_addr += 3; |
| 1627 | } |
| 1628 | /* (1) PUSHM src */ |
| 1629 | else if (st.insn[0] == 0xec) |
| 1630 | { |
| 1631 | int src = st.insn[1]; |
| 1632 | if (m32c_pv_pushm (&st, src)) |
| 1633 | break; |
| 1634 | st.next_addr += 2; |
| 1635 | |
| 1636 | if (m32c_pushm_is_reg_save (&st, src)) |
| 1637 | after_last_frame_related_insn = st.next_addr; |
| 1638 | } |
| 1639 | |
| 1640 | /* (6) MOV.size:G src, dest */ |
| 1641 | else if ((st.insn[0] & 0xfe) == 0x72) |
| 1642 | { |
| 1643 | int size = (st.insn[0] & 0x01) ? 2 : 1; |
| 1644 | struct srcdest src; |
| 1645 | struct srcdest dest; |
| 1646 | pv_t src_value; |
| 1647 | st.next_addr += 2; |
| 1648 | |
| 1649 | src |
| 1650 | = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size); |
| 1651 | dest |
| 1652 | = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size); |
| 1653 | src_value = m32c_srcdest_fetch (&st, src, size); |
| 1654 | |
| 1655 | if (m32c_is_arg_spill (&st, dest, src_value)) |
| 1656 | after_last_frame_related_insn = st.next_addr; |
| 1657 | else if (m32c_is_struct_return (&st, dest, src_value)) |
| 1658 | after_last_frame_related_insn = st.next_addr; |
| 1659 | |
| 1660 | if (m32c_srcdest_store (&st, dest, src_value, size)) |
| 1661 | break; |
| 1662 | } |
| 1663 | |
| 1664 | /* (1) LDC #IMM16, sp */ |
| 1665 | else if (st.insn[0] == 0xeb |
| 1666 | && st.insn[1] == 0x50) |
| 1667 | { |
| 1668 | st.next_addr += 2; |
| 1669 | st.sp = pv_constant (m32c_udisp16 (&st)); |
| 1670 | } |
| 1671 | |
| 1672 | else |
| 1673 | /* We've hit some instruction we don't know how to simulate. |
| 1674 | Strictly speaking, we should set every value we're |
| 1675 | tracking to "unknown". But we'll be optimistic, assume |
| 1676 | that we have enough information already, and stop |
| 1677 | analysis here. */ |
| 1678 | break; |
| 1679 | } |
| 1680 | else |
| 1681 | { |
| 1682 | int src_indirect = 0; |
| 1683 | int dest_indirect = 0; |
| 1684 | int i = 0; |
| 1685 | |
| 1686 | gdb_assert (mach == bfd_mach_m32c); |
| 1687 | |
| 1688 | /* Check for prefix bytes indicating indirect addressing. */ |
| 1689 | if (st.insn[0] == 0x41) |
| 1690 | { |
| 1691 | src_indirect = 1; |
| 1692 | i++; |
| 1693 | } |
| 1694 | else if (st.insn[0] == 0x09) |
| 1695 | { |
| 1696 | dest_indirect = 1; |
| 1697 | i++; |
| 1698 | } |
| 1699 | else if (st.insn[0] == 0x49) |
| 1700 | { |
| 1701 | src_indirect = dest_indirect = 1; |
| 1702 | i++; |
| 1703 | } |
| 1704 | |
| 1705 | /* (1) ENTER #imm8 */ |
| 1706 | if (st.insn[i] == 0xec) |
| 1707 | { |
| 1708 | if (m32c_pv_enter (&st, st.insn[i + 1])) |
| 1709 | break; |
| 1710 | st.next_addr += 2; |
| 1711 | } |
| 1712 | |
| 1713 | /* (1) PUSHM src */ |
| 1714 | else if (st.insn[i] == 0x8f) |
| 1715 | { |
| 1716 | int src = st.insn[i + 1]; |
| 1717 | if (m32c_pv_pushm (&st, src)) |
| 1718 | break; |
| 1719 | st.next_addr += 2; |
| 1720 | |
| 1721 | if (m32c_pushm_is_reg_save (&st, src)) |
| 1722 | after_last_frame_related_insn = st.next_addr; |
| 1723 | } |
| 1724 | |
| 1725 | /* (7) MOV.size:G src, dest */ |
| 1726 | else if ((st.insn[i] & 0x80) == 0x80 |
| 1727 | && (st.insn[i + 1] & 0x0f) == 0x0b |
| 1728 | && m32c_get_src23 (&st.insn[i]) < 20 |
| 1729 | && m32c_get_dest23 (&st.insn[i]) < 20) |
| 1730 | { |
| 1731 | struct srcdest src; |
| 1732 | struct srcdest dest; |
| 1733 | pv_t src_value; |
| 1734 | int bw = st.insn[i] & 0x01; |
| 1735 | int size = bw ? 2 : 1; |
| 1736 | st.next_addr += 2; |
| 1737 | |
| 1738 | src |
| 1739 | = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]), |
| 1740 | size, src_indirect); |
| 1741 | dest |
| 1742 | = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]), |
| 1743 | size, dest_indirect); |
| 1744 | src_value = m32c_srcdest_fetch (&st, src, size); |
| 1745 | |
| 1746 | if (m32c_is_arg_spill (&st, dest, src_value)) |
| 1747 | after_last_frame_related_insn = st.next_addr; |
| 1748 | |
| 1749 | if (m32c_srcdest_store (&st, dest, src_value, size)) |
| 1750 | break; |
| 1751 | } |
| 1752 | /* (2) LDC #IMM24, sp */ |
| 1753 | else if (st.insn[i] == 0xd5 |
| 1754 | && st.insn[i + 1] == 0x29) |
| 1755 | { |
| 1756 | st.next_addr += 2; |
| 1757 | st.sp = pv_constant (m32c_udisp24 (&st)); |
| 1758 | } |
| 1759 | else |
| 1760 | /* We've hit some instruction we don't know how to simulate. |
| 1761 | Strictly speaking, we should set every value we're |
| 1762 | tracking to "unknown". But we'll be optimistic, assume |
| 1763 | that we have enough information already, and stop |
| 1764 | analysis here. */ |
| 1765 | break; |
| 1766 | } |
| 1767 | |
| 1768 | /* If this instruction changed the FB or decreased the SP (i.e., |
| 1769 | allocated more stack space), then this may be a good place to |
| 1770 | declare the prologue finished. However, there are some |
| 1771 | exceptions: |
| 1772 | |
| 1773 | - If the instruction just changed the FB back to its original |
| 1774 | value, then that's probably a restore instruction. The |
| 1775 | prologue should definitely end before that. |
| 1776 | |
| 1777 | - If the instruction increased the value of the SP (that is, |
| 1778 | shrunk the frame), then it's probably part of a frame |
| 1779 | teardown sequence, and the prologue should end before |
| 1780 | that. */ |
| 1781 | |
| 1782 | if (! pv_is_identical (st.fb, pre_insn_fb)) |
| 1783 | { |
| 1784 | if (! pv_is_register_k (st.fb, tdep->fb->num, 0)) |
| 1785 | after_last_frame_related_insn = st.next_addr; |
| 1786 | } |
| 1787 | else if (! pv_is_identical (st.sp, pre_insn_sp)) |
| 1788 | { |
| 1789 | /* The comparison of the constants looks odd, there, because |
| 1790 | .k is unsigned. All it really means is that the SP is |
| 1791 | lower than it was before the instruction. */ |
| 1792 | if ( pv_is_register (pre_insn_sp, tdep->sp->num) |
| 1793 | && pv_is_register (st.sp, tdep->sp->num) |
| 1794 | && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k))) |
| 1795 | after_last_frame_related_insn = st.next_addr; |
| 1796 | } |
| 1797 | |
| 1798 | st.scan_pc = st.next_addr; |
| 1799 | } |
| 1800 | |
| 1801 | /* Did we load a constant value into the stack pointer? */ |
| 1802 | if (pv_is_constant (st.sp)) |
| 1803 | prologue->kind = prologue_first_frame; |
| 1804 | |
| 1805 | /* Alternatively, did we initialize the frame pointer? Remember |
| 1806 | that the CFA is the address after the return address. */ |
| 1807 | if (pv_is_register (st.fb, tdep->sp->num)) |
| 1808 | { |
| 1809 | prologue->kind = prologue_with_frame_ptr; |
| 1810 | prologue->frame_ptr_offset = st.fb.k; |
| 1811 | } |
| 1812 | |
| 1813 | /* Is the frame size a known constant? Remember that frame_size is |
| 1814 | actually the offset from the CFA to the SP (i.e., a negative |
| 1815 | value). */ |
| 1816 | else if (pv_is_register (st.sp, tdep->sp->num)) |
| 1817 | { |
| 1818 | prologue->kind = prologue_sans_frame_ptr; |
| 1819 | prologue->frame_size = st.sp.k; |
| 1820 | } |
| 1821 | |
| 1822 | /* We haven't been able to make sense of this function's frame. Treat |
| 1823 | it as the first frame. */ |
| 1824 | else |
| 1825 | prologue->kind = prologue_first_frame; |
| 1826 | |
| 1827 | /* Record where all the registers were saved. */ |
| 1828 | pv_area_scan (st.stack, check_for_saved, (void *) prologue); |
| 1829 | |
| 1830 | prologue->prologue_end = after_last_frame_related_insn; |
| 1831 | |
| 1832 | do_cleanups (back_to); |
| 1833 | } |
| 1834 | |
| 1835 | |
| 1836 | static CORE_ADDR |
| 1837 | m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip) |
| 1838 | { |
| 1839 | const char *name; |
| 1840 | CORE_ADDR func_addr, func_end, sal_end; |
| 1841 | struct m32c_prologue p; |
| 1842 | |
| 1843 | /* Try to find the extent of the function that contains IP. */ |
| 1844 | if (! find_pc_partial_function (ip, &name, &func_addr, &func_end)) |
| 1845 | return ip; |
| 1846 | |
| 1847 | /* Find end by prologue analysis. */ |
| 1848 | m32c_analyze_prologue (gdbarch, ip, func_end, &p); |
| 1849 | /* Find end by line info. */ |
| 1850 | sal_end = skip_prologue_using_sal (gdbarch, ip); |
| 1851 | /* Return whichever is lower. */ |
| 1852 | if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end) |
| 1853 | return sal_end; |
| 1854 | else |
| 1855 | return p.prologue_end; |
| 1856 | } |
| 1857 | |
| 1858 | |
| 1859 | \f |
| 1860 | /* Stack unwinding. */ |
| 1861 | |
| 1862 | static struct m32c_prologue * |
| 1863 | m32c_analyze_frame_prologue (struct frame_info *this_frame, |
| 1864 | void **this_prologue_cache) |
| 1865 | { |
| 1866 | if (! *this_prologue_cache) |
| 1867 | { |
| 1868 | CORE_ADDR func_start = get_frame_func (this_frame); |
| 1869 | CORE_ADDR stop_addr = get_frame_pc (this_frame); |
| 1870 | |
| 1871 | /* If we couldn't find any function containing the PC, then |
| 1872 | just initialize the prologue cache, but don't do anything. */ |
| 1873 | if (! func_start) |
| 1874 | stop_addr = func_start; |
| 1875 | |
| 1876 | *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue); |
| 1877 | m32c_analyze_prologue (get_frame_arch (this_frame), |
| 1878 | func_start, stop_addr, *this_prologue_cache); |
| 1879 | } |
| 1880 | |
| 1881 | return *this_prologue_cache; |
| 1882 | } |
| 1883 | |
| 1884 | |
| 1885 | static CORE_ADDR |
| 1886 | m32c_frame_base (struct frame_info *this_frame, |
| 1887 | void **this_prologue_cache) |
| 1888 | { |
| 1889 | struct m32c_prologue *p |
| 1890 | = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); |
| 1891 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
| 1892 | |
| 1893 | /* In functions that use alloca, the distance between the stack |
| 1894 | pointer and the frame base varies dynamically, so we can't use |
| 1895 | the SP plus static information like prologue analysis to find the |
| 1896 | frame base. However, such functions must have a frame pointer, |
| 1897 | to be able to restore the SP on exit. So whenever we do have a |
| 1898 | frame pointer, use that to find the base. */ |
| 1899 | switch (p->kind) |
| 1900 | { |
| 1901 | case prologue_with_frame_ptr: |
| 1902 | { |
| 1903 | CORE_ADDR fb |
| 1904 | = get_frame_register_unsigned (this_frame, tdep->fb->num); |
| 1905 | return fb - p->frame_ptr_offset; |
| 1906 | } |
| 1907 | |
| 1908 | case prologue_sans_frame_ptr: |
| 1909 | { |
| 1910 | CORE_ADDR sp |
| 1911 | = get_frame_register_unsigned (this_frame, tdep->sp->num); |
| 1912 | return sp - p->frame_size; |
| 1913 | } |
| 1914 | |
| 1915 | case prologue_first_frame: |
| 1916 | return 0; |
| 1917 | |
| 1918 | default: |
| 1919 | gdb_assert_not_reached ("unexpected prologue kind"); |
| 1920 | } |
| 1921 | } |
| 1922 | |
| 1923 | |
| 1924 | static void |
| 1925 | m32c_this_id (struct frame_info *this_frame, |
| 1926 | void **this_prologue_cache, |
| 1927 | struct frame_id *this_id) |
| 1928 | { |
| 1929 | CORE_ADDR base = m32c_frame_base (this_frame, this_prologue_cache); |
| 1930 | |
| 1931 | if (base) |
| 1932 | *this_id = frame_id_build (base, get_frame_func (this_frame)); |
| 1933 | /* Otherwise, leave it unset, and that will terminate the backtrace. */ |
| 1934 | } |
| 1935 | |
| 1936 | |
| 1937 | static struct value * |
| 1938 | m32c_prev_register (struct frame_info *this_frame, |
| 1939 | void **this_prologue_cache, int regnum) |
| 1940 | { |
| 1941 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
| 1942 | struct m32c_prologue *p |
| 1943 | = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); |
| 1944 | CORE_ADDR frame_base = m32c_frame_base (this_frame, this_prologue_cache); |
| 1945 | int reg_size = register_size (get_frame_arch (this_frame), regnum); |
| 1946 | |
| 1947 | if (regnum == tdep->sp->num) |
| 1948 | return frame_unwind_got_constant (this_frame, regnum, frame_base); |
| 1949 | |
| 1950 | /* If prologue analysis says we saved this register somewhere, |
| 1951 | return a description of the stack slot holding it. */ |
| 1952 | if (p->reg_offset[regnum] != 1) |
| 1953 | return frame_unwind_got_memory (this_frame, regnum, |
| 1954 | frame_base + p->reg_offset[regnum]); |
| 1955 | |
| 1956 | /* Otherwise, presume we haven't changed the value of this |
| 1957 | register, and get it from the next frame. */ |
| 1958 | return frame_unwind_got_register (this_frame, regnum, regnum); |
| 1959 | } |
| 1960 | |
| 1961 | |
| 1962 | static const struct frame_unwind m32c_unwind = { |
| 1963 | NORMAL_FRAME, |
| 1964 | default_frame_unwind_stop_reason, |
| 1965 | m32c_this_id, |
| 1966 | m32c_prev_register, |
| 1967 | NULL, |
| 1968 | default_frame_sniffer |
| 1969 | }; |
| 1970 | |
| 1971 | |
| 1972 | static CORE_ADDR |
| 1973 | m32c_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame) |
| 1974 | { |
| 1975 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 1976 | return frame_unwind_register_unsigned (next_frame, tdep->pc->num); |
| 1977 | } |
| 1978 | |
| 1979 | |
| 1980 | static CORE_ADDR |
| 1981 | m32c_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame) |
| 1982 | { |
| 1983 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
| 1984 | return frame_unwind_register_unsigned (next_frame, tdep->sp->num); |
| 1985 | } |
| 1986 | |
| 1987 | \f |
| 1988 | /* Inferior calls. */ |
| 1989 | |
| 1990 | /* The calling conventions, according to GCC: |
| 1991 | |
| 1992 | r8c, m16c |
| 1993 | --------- |
| 1994 | First arg may be passed in r1l or r1 if it (1) fits (QImode or |
| 1995 | HImode), (2) is named, and (3) is an integer or pointer type (no |
| 1996 | structs, floats, etc). Otherwise, it's passed on the stack. |
| 1997 | |
| 1998 | Second arg may be passed in r2, same restrictions (but not QImode), |
| 1999 | even if the first arg is passed on the stack. |
| 2000 | |
| 2001 | Third and further args are passed on the stack. No padding is |
| 2002 | used, stack "alignment" is 8 bits. |
| 2003 | |
| 2004 | m32cm, m32c |
| 2005 | ----------- |
| 2006 | |
| 2007 | First arg may be passed in r0l or r0, same restrictions as above. |
| 2008 | |
| 2009 | Second and further args are passed on the stack. Padding is used |
| 2010 | after QImode parameters (i.e. lower-addressed byte is the value, |
| 2011 | higher-addressed byte is the padding), stack "alignment" is 16 |
| 2012 | bits. */ |
| 2013 | |
| 2014 | |
| 2015 | /* Return true if TYPE is a type that can be passed in registers. (We |
| 2016 | ignore the size, and pay attention only to the type code; |
| 2017 | acceptable sizes depends on which register is being considered to |
| 2018 | hold it.) */ |
| 2019 | static int |
| 2020 | m32c_reg_arg_type (struct type *type) |
| 2021 | { |
| 2022 | enum type_code code = TYPE_CODE (type); |
| 2023 | |
| 2024 | return (code == TYPE_CODE_INT |
| 2025 | || code == TYPE_CODE_ENUM |
| 2026 | || code == TYPE_CODE_PTR |
| 2027 | || code == TYPE_CODE_REF |
| 2028 | || code == TYPE_CODE_BOOL |
| 2029 | || code == TYPE_CODE_CHAR); |
| 2030 | } |
| 2031 | |
| 2032 | |
| 2033 | static CORE_ADDR |
| 2034 | m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 2035 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
| 2036 | struct value **args, CORE_ADDR sp, int struct_return, |
| 2037 | CORE_ADDR struct_addr) |
| 2038 | { |
| 2039 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2040 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2041 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
| 2042 | CORE_ADDR cfa; |
| 2043 | int i; |
| 2044 | |
| 2045 | /* The number of arguments given in this function's prototype, or |
| 2046 | zero if it has a non-prototyped function type. The m32c ABI |
| 2047 | passes arguments mentioned in the prototype differently from |
| 2048 | those in the ellipsis of a varargs function, or from those passed |
| 2049 | to a non-prototyped function. */ |
| 2050 | int num_prototyped_args = 0; |
| 2051 | |
| 2052 | { |
| 2053 | struct type *func_type = value_type (function); |
| 2054 | |
| 2055 | /* Dereference function pointer types. */ |
| 2056 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) |
| 2057 | func_type = TYPE_TARGET_TYPE (func_type); |
| 2058 | |
| 2059 | gdb_assert (TYPE_CODE (func_type) == TYPE_CODE_FUNC || |
| 2060 | TYPE_CODE (func_type) == TYPE_CODE_METHOD); |
| 2061 | |
| 2062 | #if 0 |
| 2063 | /* The ABI description in gcc/config/m32c/m32c.abi says that |
| 2064 | we need to handle prototyped and non-prototyped functions |
| 2065 | separately, but the code in GCC doesn't actually do so. */ |
| 2066 | if (TYPE_PROTOTYPED (func_type)) |
| 2067 | #endif |
| 2068 | num_prototyped_args = TYPE_NFIELDS (func_type); |
| 2069 | } |
| 2070 | |
| 2071 | /* First, if the function returns an aggregate by value, push a |
| 2072 | pointer to a buffer for it. This doesn't affect the way |
| 2073 | subsequent arguments are allocated to registers. */ |
| 2074 | if (struct_return) |
| 2075 | { |
| 2076 | int ptr_len = TYPE_LENGTH (tdep->ptr_voyd); |
| 2077 | sp -= ptr_len; |
| 2078 | write_memory_unsigned_integer (sp, ptr_len, byte_order, struct_addr); |
| 2079 | } |
| 2080 | |
| 2081 | /* Push the arguments. */ |
| 2082 | for (i = nargs - 1; i >= 0; i--) |
| 2083 | { |
| 2084 | struct value *arg = args[i]; |
| 2085 | const gdb_byte *arg_bits = value_contents (arg); |
| 2086 | struct type *arg_type = value_type (arg); |
| 2087 | ULONGEST arg_size = TYPE_LENGTH (arg_type); |
| 2088 | |
| 2089 | /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */ |
| 2090 | if (i == 0 |
| 2091 | && arg_size <= 2 |
| 2092 | && i < num_prototyped_args |
| 2093 | && m32c_reg_arg_type (arg_type)) |
| 2094 | { |
| 2095 | /* Extract and re-store as an integer as a terse way to make |
| 2096 | sure it ends up in the least significant end of r1. (GDB |
| 2097 | should avoid assuming endianness, even on uni-endian |
| 2098 | processors.) */ |
| 2099 | ULONGEST u = extract_unsigned_integer (arg_bits, arg_size, |
| 2100 | byte_order); |
| 2101 | struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0; |
| 2102 | regcache_cooked_write_unsigned (regcache, reg->num, u); |
| 2103 | } |
| 2104 | |
| 2105 | /* Can it go in r2? */ |
| 2106 | else if (mach == bfd_mach_m16c |
| 2107 | && i == 1 |
| 2108 | && arg_size == 2 |
| 2109 | && i < num_prototyped_args |
| 2110 | && m32c_reg_arg_type (arg_type)) |
| 2111 | regcache_cooked_write (regcache, tdep->r2->num, arg_bits); |
| 2112 | |
| 2113 | /* Everything else goes on the stack. */ |
| 2114 | else |
| 2115 | { |
| 2116 | sp -= arg_size; |
| 2117 | |
| 2118 | /* Align the stack. */ |
| 2119 | if (mach == bfd_mach_m32c) |
| 2120 | sp &= ~1; |
| 2121 | |
| 2122 | write_memory (sp, arg_bits, arg_size); |
| 2123 | } |
| 2124 | } |
| 2125 | |
| 2126 | /* This is the CFA we use to identify the dummy frame. */ |
| 2127 | cfa = sp; |
| 2128 | |
| 2129 | /* Push the return address. */ |
| 2130 | sp -= tdep->ret_addr_bytes; |
| 2131 | write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, byte_order, |
| 2132 | bp_addr); |
| 2133 | |
| 2134 | /* Update the stack pointer. */ |
| 2135 | regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp); |
| 2136 | |
| 2137 | /* We need to borrow an odd trick from the i386 target here. |
| 2138 | |
| 2139 | The value we return from this function gets used as the stack |
| 2140 | address (the CFA) for the dummy frame's ID. The obvious thing is |
| 2141 | to return the new TOS. However, that points at the return |
| 2142 | address, saved on the stack, which is inconsistent with the CFA's |
| 2143 | described by GCC's DWARF 2 .debug_frame information: DWARF 2 |
| 2144 | .debug_frame info uses the address immediately after the saved |
| 2145 | return address. So you end up with a dummy frame whose CFA |
| 2146 | points at the return address, but the frame for the function |
| 2147 | being called has a CFA pointing after the return address: the |
| 2148 | younger CFA is *greater than* the older CFA. The sanity checks |
| 2149 | in frame.c don't like that. |
| 2150 | |
| 2151 | So we try to be consistent with the CFA's used by DWARF 2. |
| 2152 | Having a dummy frame and a real frame with the *same* CFA is |
| 2153 | tolerable. */ |
| 2154 | return cfa; |
| 2155 | } |
| 2156 | |
| 2157 | |
| 2158 | static struct frame_id |
| 2159 | m32c_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
| 2160 | { |
| 2161 | /* This needs to return a frame ID whose PC is the return address |
| 2162 | passed to m32c_push_dummy_call, and whose stack_addr is the SP |
| 2163 | m32c_push_dummy_call returned. |
| 2164 | |
| 2165 | m32c_unwind_sp gives us the CFA, which is the value the SP had |
| 2166 | before the return address was pushed. */ |
| 2167 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2168 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, tdep->sp->num); |
| 2169 | return frame_id_build (sp, get_frame_pc (this_frame)); |
| 2170 | } |
| 2171 | |
| 2172 | |
| 2173 | \f |
| 2174 | /* Return values. */ |
| 2175 | |
| 2176 | /* Return value conventions, according to GCC: |
| 2177 | |
| 2178 | r8c, m16c |
| 2179 | --------- |
| 2180 | |
| 2181 | QImode in r0l |
| 2182 | HImode in r0 |
| 2183 | SImode in r2r0 |
| 2184 | near pointer in r0 |
| 2185 | far pointer in r2r0 |
| 2186 | |
| 2187 | Aggregate values (regardless of size) are returned by pushing a |
| 2188 | pointer to a temporary area on the stack after the args are pushed. |
| 2189 | The function fills in this area with the value. Note that this |
| 2190 | pointer on the stack does not affect how register arguments, if any, |
| 2191 | are configured. |
| 2192 | |
| 2193 | m32cm, m32c |
| 2194 | ----------- |
| 2195 | Same. */ |
| 2196 | |
| 2197 | /* Return non-zero if values of type TYPE are returned by storing them |
| 2198 | in a buffer whose address is passed on the stack, ahead of the |
| 2199 | other arguments. */ |
| 2200 | static int |
| 2201 | m32c_return_by_passed_buf (struct type *type) |
| 2202 | { |
| 2203 | enum type_code code = TYPE_CODE (type); |
| 2204 | |
| 2205 | return (code == TYPE_CODE_STRUCT |
| 2206 | || code == TYPE_CODE_UNION); |
| 2207 | } |
| 2208 | |
| 2209 | static enum return_value_convention |
| 2210 | m32c_return_value (struct gdbarch *gdbarch, |
| 2211 | struct value *function, |
| 2212 | struct type *valtype, |
| 2213 | struct regcache *regcache, |
| 2214 | gdb_byte *readbuf, |
| 2215 | const gdb_byte *writebuf) |
| 2216 | { |
| 2217 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2218 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2219 | enum return_value_convention conv; |
| 2220 | ULONGEST valtype_len = TYPE_LENGTH (valtype); |
| 2221 | |
| 2222 | if (m32c_return_by_passed_buf (valtype)) |
| 2223 | conv = RETURN_VALUE_STRUCT_CONVENTION; |
| 2224 | else |
| 2225 | conv = RETURN_VALUE_REGISTER_CONVENTION; |
| 2226 | |
| 2227 | if (readbuf) |
| 2228 | { |
| 2229 | /* We should never be called to find values being returned by |
| 2230 | RETURN_VALUE_STRUCT_CONVENTION. Those can't be located, |
| 2231 | unless we made the call ourselves. */ |
| 2232 | gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); |
| 2233 | |
| 2234 | gdb_assert (valtype_len <= 8); |
| 2235 | |
| 2236 | /* Anything that fits in r0 is returned there. */ |
| 2237 | if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) |
| 2238 | { |
| 2239 | ULONGEST u; |
| 2240 | regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u); |
| 2241 | store_unsigned_integer (readbuf, valtype_len, byte_order, u); |
| 2242 | } |
| 2243 | else |
| 2244 | { |
| 2245 | /* Everything else is passed in mem0, using as many bytes as |
| 2246 | needed. This is not what the Renesas tools do, but it's |
| 2247 | what GCC does at the moment. */ |
| 2248 | struct bound_minimal_symbol mem0 |
| 2249 | = lookup_minimal_symbol ("mem0", NULL, NULL); |
| 2250 | |
| 2251 | if (! mem0.minsym) |
| 2252 | error (_("The return value is stored in memory at 'mem0', " |
| 2253 | "but GDB cannot find\n" |
| 2254 | "its address.")); |
| 2255 | read_memory (BMSYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len); |
| 2256 | } |
| 2257 | } |
| 2258 | |
| 2259 | if (writebuf) |
| 2260 | { |
| 2261 | /* We should never be called to store values to be returned |
| 2262 | using RETURN_VALUE_STRUCT_CONVENTION. We have no way of |
| 2263 | finding the buffer, unless we made the call ourselves. */ |
| 2264 | gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); |
| 2265 | |
| 2266 | gdb_assert (valtype_len <= 8); |
| 2267 | |
| 2268 | /* Anything that fits in r0 is returned there. */ |
| 2269 | if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) |
| 2270 | { |
| 2271 | ULONGEST u = extract_unsigned_integer (writebuf, valtype_len, |
| 2272 | byte_order); |
| 2273 | regcache_cooked_write_unsigned (regcache, tdep->r0->num, u); |
| 2274 | } |
| 2275 | else |
| 2276 | { |
| 2277 | /* Everything else is passed in mem0, using as many bytes as |
| 2278 | needed. This is not what the Renesas tools do, but it's |
| 2279 | what GCC does at the moment. */ |
| 2280 | struct bound_minimal_symbol mem0 |
| 2281 | = lookup_minimal_symbol ("mem0", NULL, NULL); |
| 2282 | |
| 2283 | if (! mem0.minsym) |
| 2284 | error (_("The return value is stored in memory at 'mem0', " |
| 2285 | "but GDB cannot find\n" |
| 2286 | " its address.")); |
| 2287 | write_memory (BMSYMBOL_VALUE_ADDRESS (mem0), writebuf, valtype_len); |
| 2288 | } |
| 2289 | } |
| 2290 | |
| 2291 | return conv; |
| 2292 | } |
| 2293 | |
| 2294 | |
| 2295 | \f |
| 2296 | /* Trampolines. */ |
| 2297 | |
| 2298 | /* The m16c and m32c use a trampoline function for indirect function |
| 2299 | calls. An indirect call looks like this: |
| 2300 | |
| 2301 | ... push arguments ... |
| 2302 | ... push target function address ... |
| 2303 | jsr.a m32c_jsri16 |
| 2304 | |
| 2305 | The code for m32c_jsri16 looks like this: |
| 2306 | |
| 2307 | m32c_jsri16: |
| 2308 | |
| 2309 | # Save return address. |
| 2310 | pop.w m32c_jsri_ret |
| 2311 | pop.b m32c_jsri_ret+2 |
| 2312 | |
| 2313 | # Store target function address. |
| 2314 | pop.w m32c_jsri_addr |
| 2315 | |
| 2316 | # Re-push return address. |
| 2317 | push.b m32c_jsri_ret+2 |
| 2318 | push.w m32c_jsri_ret |
| 2319 | |
| 2320 | # Call the target function. |
| 2321 | jmpi.a m32c_jsri_addr |
| 2322 | |
| 2323 | Without further information, GDB will treat calls to m32c_jsri16 |
| 2324 | like calls to any other function. Since m32c_jsri16 doesn't have |
| 2325 | debugging information, that normally means that GDB sets a step- |
| 2326 | resume breakpoint and lets the program continue --- which is not |
| 2327 | what the user wanted. (Giving the trampoline debugging info |
| 2328 | doesn't help: the user expects the program to stop in the function |
| 2329 | their program is calling, not in some trampoline code they've never |
| 2330 | seen before.) |
| 2331 | |
| 2332 | The gdbarch_skip_trampoline_code method tells GDB how to step |
| 2333 | through such trampoline functions transparently to the user. When |
| 2334 | given the address of a trampoline function's first instruction, |
| 2335 | gdbarch_skip_trampoline_code should return the address of the first |
| 2336 | instruction of the function really being called. If GDB decides it |
| 2337 | wants to step into that function, it will set a breakpoint there |
| 2338 | and silently continue to it. |
| 2339 | |
| 2340 | We recognize the trampoline by name, and extract the target address |
| 2341 | directly from the stack. This isn't great, but recognizing by its |
| 2342 | code sequence seems more fragile. */ |
| 2343 | |
| 2344 | static CORE_ADDR |
| 2345 | m32c_skip_trampoline_code (struct frame_info *frame, CORE_ADDR stop_pc) |
| 2346 | { |
| 2347 | struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2348 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2349 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2350 | |
| 2351 | /* It would be nicer to simply look up the addresses of known |
| 2352 | trampolines once, and then compare stop_pc with them. However, |
| 2353 | we'd need to ensure that that cached address got invalidated when |
| 2354 | someone loaded a new executable, and I'm not quite sure of the |
| 2355 | best way to do that. find_pc_partial_function does do some |
| 2356 | caching, so we'll see how this goes. */ |
| 2357 | const char *name; |
| 2358 | CORE_ADDR start, end; |
| 2359 | |
| 2360 | if (find_pc_partial_function (stop_pc, &name, &start, &end)) |
| 2361 | { |
| 2362 | /* Are we stopped at the beginning of the trampoline function? */ |
| 2363 | if (strcmp (name, "m32c_jsri16") == 0 |
| 2364 | && stop_pc == start) |
| 2365 | { |
| 2366 | /* Get the stack pointer. The return address is at the top, |
| 2367 | and the target function's address is just below that. We |
| 2368 | know it's a two-byte address, since the trampoline is |
| 2369 | m32c_jsri*16*. */ |
| 2370 | CORE_ADDR sp = get_frame_sp (get_current_frame ()); |
| 2371 | CORE_ADDR target |
| 2372 | = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes, |
| 2373 | 2, byte_order); |
| 2374 | |
| 2375 | /* What we have now is the address of a jump instruction. |
| 2376 | What we need is the destination of that jump. |
| 2377 | The opcode is 1 byte, and the destination is the next 3 bytes. */ |
| 2378 | |
| 2379 | target = read_memory_unsigned_integer (target + 1, 3, byte_order); |
| 2380 | return target; |
| 2381 | } |
| 2382 | } |
| 2383 | |
| 2384 | return 0; |
| 2385 | } |
| 2386 | |
| 2387 | |
| 2388 | /* Address/pointer conversions. */ |
| 2389 | |
| 2390 | /* On the m16c, there is a 24-bit address space, but only a very few |
| 2391 | instructions can generate addresses larger than 0xffff: jumps, |
| 2392 | jumps to subroutines, and the lde/std (load/store extended) |
| 2393 | instructions. |
| 2394 | |
| 2395 | Since GCC can only support one size of pointer, we can't have |
| 2396 | distinct 'near' and 'far' pointer types; we have to pick one size |
| 2397 | for everything. If we wanted to use 24-bit pointers, then GCC |
| 2398 | would have to use lde and ste for all memory references, which |
| 2399 | would be terrible for performance and code size. So the GNU |
| 2400 | toolchain uses 16-bit pointers for everything, and gives up the |
| 2401 | ability to have pointers point outside the first 64k of memory. |
| 2402 | |
| 2403 | However, as a special hack, we let the linker place functions at |
| 2404 | addresses above 0xffff, as long as it also places a trampoline in |
| 2405 | the low 64k for every function whose address is taken. Each |
| 2406 | trampoline consists of a single jmp.a instruction that jumps to the |
| 2407 | function's real entry point. Pointers to functions can be 16 bits |
| 2408 | long, even though the functions themselves are at higher addresses: |
| 2409 | the pointers refer to the trampolines, not the functions. |
| 2410 | |
| 2411 | This complicates things for GDB, however: given the address of a |
| 2412 | function (from debug info or linker symbols, say) which could be |
| 2413 | anywhere in the 24-bit address space, how can we find an |
| 2414 | appropriate 16-bit value to use as a pointer to it? |
| 2415 | |
| 2416 | If the linker has not generated a trampoline for the function, |
| 2417 | we're out of luck. Well, I guess we could malloc some space and |
| 2418 | write a jmp.a instruction to it, but I'm not going to get into that |
| 2419 | at the moment. |
| 2420 | |
| 2421 | If the linker has generated a trampoline for the function, then it |
| 2422 | also emitted a symbol for the trampoline: if the function's linker |
| 2423 | symbol is named NAME, then the function's trampoline's linker |
| 2424 | symbol is named NAME.plt. |
| 2425 | |
| 2426 | So, given a code address: |
| 2427 | - We try to find a linker symbol at that address. |
| 2428 | - If we find such a symbol named NAME, we look for a linker symbol |
| 2429 | named NAME.plt. |
| 2430 | - If we find such a symbol, we assume it is a trampoline, and use |
| 2431 | its address as the pointer value. |
| 2432 | |
| 2433 | And, given a function pointer: |
| 2434 | - We try to find a linker symbol at that address named NAME.plt. |
| 2435 | - If we find such a symbol, we look for a linker symbol named NAME. |
| 2436 | - If we find that, we provide that as the function's address. |
| 2437 | - If any of the above steps fail, we return the original address |
| 2438 | unchanged; it might really be a function in the low 64k. |
| 2439 | |
| 2440 | See? You *knew* there was a reason you wanted to be a computer |
| 2441 | programmer! :) */ |
| 2442 | |
| 2443 | static void |
| 2444 | m32c_m16c_address_to_pointer (struct gdbarch *gdbarch, |
| 2445 | struct type *type, gdb_byte *buf, CORE_ADDR addr) |
| 2446 | { |
| 2447 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2448 | enum type_code target_code; |
| 2449 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || |
| 2450 | TYPE_CODE (type) == TYPE_CODE_REF); |
| 2451 | |
| 2452 | target_code = TYPE_CODE (TYPE_TARGET_TYPE (type)); |
| 2453 | |
| 2454 | if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) |
| 2455 | { |
| 2456 | const char *func_name; |
| 2457 | char *tramp_name; |
| 2458 | struct bound_minimal_symbol tramp_msym; |
| 2459 | |
| 2460 | /* Try to find a linker symbol at this address. */ |
| 2461 | struct bound_minimal_symbol func_msym |
| 2462 | = lookup_minimal_symbol_by_pc (addr); |
| 2463 | |
| 2464 | if (! func_msym.minsym) |
| 2465 | error (_("Cannot convert code address %s to function pointer:\n" |
| 2466 | "couldn't find a symbol at that address, to find trampoline."), |
| 2467 | paddress (gdbarch, addr)); |
| 2468 | |
| 2469 | func_name = MSYMBOL_LINKAGE_NAME (func_msym.minsym); |
| 2470 | tramp_name = xmalloc (strlen (func_name) + 5); |
| 2471 | strcpy (tramp_name, func_name); |
| 2472 | strcat (tramp_name, ".plt"); |
| 2473 | |
| 2474 | /* Try to find a linker symbol for the trampoline. */ |
| 2475 | tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL); |
| 2476 | |
| 2477 | /* We've either got another copy of the name now, or don't need |
| 2478 | the name any more. */ |
| 2479 | xfree (tramp_name); |
| 2480 | |
| 2481 | if (! tramp_msym.minsym) |
| 2482 | { |
| 2483 | CORE_ADDR ptrval; |
| 2484 | |
| 2485 | /* No PLT entry found. Mask off the upper bits of the address |
| 2486 | to make a pointer. As noted in the warning to the user |
| 2487 | below, this value might be useful if converted back into |
| 2488 | an address by GDB, but will otherwise, almost certainly, |
| 2489 | be garbage. |
| 2490 | |
| 2491 | Using this masked result does seem to be useful |
| 2492 | in gdb.cp/cplusfuncs.exp in which ~40 FAILs turn into |
| 2493 | PASSes. These results appear to be correct as well. |
| 2494 | |
| 2495 | We print a warning here so that the user can make a |
| 2496 | determination about whether the result is useful or not. */ |
| 2497 | ptrval = addr & 0xffff; |
| 2498 | |
| 2499 | warning (_("Cannot convert code address %s to function pointer:\n" |
| 2500 | "couldn't find trampoline named '%s.plt'.\n" |
| 2501 | "Returning pointer value %s instead; this may produce\n" |
| 2502 | "a useful result if converted back into an address by GDB,\n" |
| 2503 | "but will most likely not be useful otherwise.\n"), |
| 2504 | paddress (gdbarch, addr), func_name, |
| 2505 | paddress (gdbarch, ptrval)); |
| 2506 | |
| 2507 | addr = ptrval; |
| 2508 | |
| 2509 | } |
| 2510 | else |
| 2511 | { |
| 2512 | /* The trampoline's address is our pointer. */ |
| 2513 | addr = BMSYMBOL_VALUE_ADDRESS (tramp_msym); |
| 2514 | } |
| 2515 | } |
| 2516 | |
| 2517 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, addr); |
| 2518 | } |
| 2519 | |
| 2520 | |
| 2521 | static CORE_ADDR |
| 2522 | m32c_m16c_pointer_to_address (struct gdbarch *gdbarch, |
| 2523 | struct type *type, const gdb_byte *buf) |
| 2524 | { |
| 2525 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 2526 | CORE_ADDR ptr; |
| 2527 | enum type_code target_code; |
| 2528 | |
| 2529 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_PTR || |
| 2530 | TYPE_CODE (type) == TYPE_CODE_REF); |
| 2531 | |
| 2532 | ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); |
| 2533 | |
| 2534 | target_code = TYPE_CODE (TYPE_TARGET_TYPE (type)); |
| 2535 | |
| 2536 | if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) |
| 2537 | { |
| 2538 | /* See if there is a minimal symbol at that address whose name is |
| 2539 | "NAME.plt". */ |
| 2540 | struct bound_minimal_symbol ptr_msym = lookup_minimal_symbol_by_pc (ptr); |
| 2541 | |
| 2542 | if (ptr_msym.minsym) |
| 2543 | { |
| 2544 | const char *ptr_msym_name = MSYMBOL_LINKAGE_NAME (ptr_msym.minsym); |
| 2545 | int len = strlen (ptr_msym_name); |
| 2546 | |
| 2547 | if (len > 4 |
| 2548 | && strcmp (ptr_msym_name + len - 4, ".plt") == 0) |
| 2549 | { |
| 2550 | struct bound_minimal_symbol func_msym; |
| 2551 | /* We have a .plt symbol; try to find the symbol for the |
| 2552 | corresponding function. |
| 2553 | |
| 2554 | Since the trampoline contains a jump instruction, we |
| 2555 | could also just extract the jump's target address. I |
| 2556 | don't see much advantage one way or the other. */ |
| 2557 | char *func_name = xmalloc (len - 4 + 1); |
| 2558 | memcpy (func_name, ptr_msym_name, len - 4); |
| 2559 | func_name[len - 4] = '\0'; |
| 2560 | func_msym |
| 2561 | = lookup_minimal_symbol (func_name, NULL, NULL); |
| 2562 | |
| 2563 | /* If we do have such a symbol, return its value as the |
| 2564 | function's true address. */ |
| 2565 | if (func_msym.minsym) |
| 2566 | ptr = BMSYMBOL_VALUE_ADDRESS (func_msym); |
| 2567 | } |
| 2568 | } |
| 2569 | else |
| 2570 | { |
| 2571 | int aspace; |
| 2572 | |
| 2573 | for (aspace = 1; aspace <= 15; aspace++) |
| 2574 | { |
| 2575 | ptr_msym = lookup_minimal_symbol_by_pc ((aspace << 16) | ptr); |
| 2576 | |
| 2577 | if (ptr_msym.minsym) |
| 2578 | ptr |= aspace << 16; |
| 2579 | } |
| 2580 | } |
| 2581 | } |
| 2582 | |
| 2583 | return ptr; |
| 2584 | } |
| 2585 | |
| 2586 | static void |
| 2587 | m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, |
| 2588 | int *frame_regnum, |
| 2589 | LONGEST *frame_offset) |
| 2590 | { |
| 2591 | const char *name; |
| 2592 | CORE_ADDR func_addr, func_end; |
| 2593 | struct m32c_prologue p; |
| 2594 | |
| 2595 | struct regcache *regcache = get_current_regcache (); |
| 2596 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 2597 | |
| 2598 | if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) |
| 2599 | internal_error (__FILE__, __LINE__, |
| 2600 | _("No virtual frame pointer available")); |
| 2601 | |
| 2602 | m32c_analyze_prologue (gdbarch, func_addr, pc, &p); |
| 2603 | switch (p.kind) |
| 2604 | { |
| 2605 | case prologue_with_frame_ptr: |
| 2606 | *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num; |
| 2607 | *frame_offset = p.frame_ptr_offset; |
| 2608 | break; |
| 2609 | case prologue_sans_frame_ptr: |
| 2610 | *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; |
| 2611 | *frame_offset = p.frame_size; |
| 2612 | break; |
| 2613 | default: |
| 2614 | *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; |
| 2615 | *frame_offset = 0; |
| 2616 | break; |
| 2617 | } |
| 2618 | /* Sanity check */ |
| 2619 | if (*frame_regnum > gdbarch_num_regs (gdbarch)) |
| 2620 | internal_error (__FILE__, __LINE__, |
| 2621 | _("No virtual frame pointer available")); |
| 2622 | } |
| 2623 | |
| 2624 | \f |
| 2625 | /* Initialization. */ |
| 2626 | |
| 2627 | static struct gdbarch * |
| 2628 | m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 2629 | { |
| 2630 | struct gdbarch *arch; |
| 2631 | struct gdbarch_tdep *tdep; |
| 2632 | unsigned long mach = info.bfd_arch_info->mach; |
| 2633 | |
| 2634 | /* Find a candidate among the list of architectures we've created |
| 2635 | already. */ |
| 2636 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 2637 | arches != NULL; |
| 2638 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 2639 | return arches->gdbarch; |
| 2640 | |
| 2641 | tdep = xcalloc (1, sizeof (*tdep)); |
| 2642 | arch = gdbarch_alloc (&info, tdep); |
| 2643 | |
| 2644 | /* Essential types. */ |
| 2645 | make_types (arch); |
| 2646 | |
| 2647 | /* Address/pointer conversions. */ |
| 2648 | if (mach == bfd_mach_m16c) |
| 2649 | { |
| 2650 | set_gdbarch_address_to_pointer (arch, m32c_m16c_address_to_pointer); |
| 2651 | set_gdbarch_pointer_to_address (arch, m32c_m16c_pointer_to_address); |
| 2652 | } |
| 2653 | |
| 2654 | /* Register set. */ |
| 2655 | make_regs (arch); |
| 2656 | |
| 2657 | /* Disassembly. */ |
| 2658 | set_gdbarch_print_insn (arch, print_insn_m32c); |
| 2659 | |
| 2660 | /* Breakpoints. */ |
| 2661 | set_gdbarch_breakpoint_from_pc (arch, m32c_breakpoint_from_pc); |
| 2662 | |
| 2663 | /* Prologue analysis and unwinding. */ |
| 2664 | set_gdbarch_inner_than (arch, core_addr_lessthan); |
| 2665 | set_gdbarch_skip_prologue (arch, m32c_skip_prologue); |
| 2666 | set_gdbarch_unwind_pc (arch, m32c_unwind_pc); |
| 2667 | set_gdbarch_unwind_sp (arch, m32c_unwind_sp); |
| 2668 | #if 0 |
| 2669 | /* I'm dropping the dwarf2 sniffer because it has a few problems. |
| 2670 | They may be in the dwarf2 cfi code in GDB, or they may be in |
| 2671 | the debug info emitted by the upstream toolchain. I don't |
| 2672 | know which, but I do know that the prologue analyzer works better. |
| 2673 | MVS 04/13/06 */ |
| 2674 | dwarf2_append_sniffers (arch); |
| 2675 | #endif |
| 2676 | frame_unwind_append_unwinder (arch, &m32c_unwind); |
| 2677 | |
| 2678 | /* Inferior calls. */ |
| 2679 | set_gdbarch_push_dummy_call (arch, m32c_push_dummy_call); |
| 2680 | set_gdbarch_return_value (arch, m32c_return_value); |
| 2681 | set_gdbarch_dummy_id (arch, m32c_dummy_id); |
| 2682 | |
| 2683 | /* Trampolines. */ |
| 2684 | set_gdbarch_skip_trampoline_code (arch, m32c_skip_trampoline_code); |
| 2685 | |
| 2686 | set_gdbarch_virtual_frame_pointer (arch, m32c_virtual_frame_pointer); |
| 2687 | |
| 2688 | /* m32c function boundary addresses are not necessarily even. |
| 2689 | Therefore, the `vbit', which indicates a pointer to a virtual |
| 2690 | member function, is stored in the delta field, rather than as |
| 2691 | the low bit of a function pointer address. |
| 2692 | |
| 2693 | In order to verify this, see the definition of |
| 2694 | TARGET_PTRMEMFUNC_VBIT_LOCATION in gcc/defaults.h along with the |
| 2695 | definition of FUNCTION_BOUNDARY in gcc/config/m32c/m32c.h. */ |
| 2696 | set_gdbarch_vbit_in_delta (arch, 1); |
| 2697 | |
| 2698 | return arch; |
| 2699 | } |
| 2700 | |
| 2701 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
| 2702 | extern initialize_file_ftype _initialize_m32c_tdep; |
| 2703 | |
| 2704 | void |
| 2705 | _initialize_m32c_tdep (void) |
| 2706 | { |
| 2707 | register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init); |
| 2708 | |
| 2709 | m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP); |
| 2710 | } |