| 1 | /* Target-dependent code for the Motorola 88000 series. |
| 2 | |
| 3 | Copyright (C) 2004-2018 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "arch-utils.h" |
| 22 | #include "dis-asm.h" |
| 23 | #include "frame.h" |
| 24 | #include "frame-base.h" |
| 25 | #include "frame-unwind.h" |
| 26 | #include "gdbcore.h" |
| 27 | #include "gdbtypes.h" |
| 28 | #include "regcache.h" |
| 29 | #include "regset.h" |
| 30 | #include "symtab.h" |
| 31 | #include "trad-frame.h" |
| 32 | #include "value.h" |
| 33 | #include <algorithm> |
| 34 | |
| 35 | #include "m88k-tdep.h" |
| 36 | |
| 37 | /* Fetch the instruction at PC. */ |
| 38 | |
| 39 | static unsigned long |
| 40 | m88k_fetch_instruction (CORE_ADDR pc, enum bfd_endian byte_order) |
| 41 | { |
| 42 | return read_memory_unsigned_integer (pc, 4, byte_order); |
| 43 | } |
| 44 | |
| 45 | /* Register information. */ |
| 46 | |
| 47 | /* Return the name of register REGNUM. */ |
| 48 | |
| 49 | static const char * |
| 50 | m88k_register_name (struct gdbarch *gdbarch, int regnum) |
| 51 | { |
| 52 | static const char *register_names[] = |
| 53 | { |
| 54 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 55 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 56 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 57 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 58 | "epsr", "fpsr", "fpcr", "sxip", "snip", "sfip" |
| 59 | }; |
| 60 | |
| 61 | if (regnum >= 0 && regnum < ARRAY_SIZE (register_names)) |
| 62 | return register_names[regnum]; |
| 63 | |
| 64 | return NULL; |
| 65 | } |
| 66 | |
| 67 | /* Return the GDB type object for the "standard" data type of data in |
| 68 | register REGNUM. */ |
| 69 | |
| 70 | static struct type * |
| 71 | m88k_register_type (struct gdbarch *gdbarch, int regnum) |
| 72 | { |
| 73 | /* SXIP, SNIP, SFIP and R1 contain code addresses. */ |
| 74 | if ((regnum >= M88K_SXIP_REGNUM && regnum <= M88K_SFIP_REGNUM) |
| 75 | || regnum == M88K_R1_REGNUM) |
| 76 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 77 | |
| 78 | /* R30 and R31 typically contains data addresses. */ |
| 79 | if (regnum == M88K_R30_REGNUM || regnum == M88K_R31_REGNUM) |
| 80 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 81 | |
| 82 | return builtin_type (gdbarch)->builtin_int32; |
| 83 | } |
| 84 | \f |
| 85 | |
| 86 | static CORE_ADDR |
| 87 | m88k_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 88 | { |
| 89 | /* All instructures are 4-byte aligned. The lower 2 bits of SXIP, |
| 90 | SNIP and SFIP are used for special purposes: bit 0 is the |
| 91 | exception bit and bit 1 is the valid bit. */ |
| 92 | return addr & ~0x3; |
| 93 | } |
| 94 | |
| 95 | /* Use the program counter to determine the contents and size of a |
| 96 | breakpoint instruction. Return a pointer to a string of bytes that |
| 97 | encode a breakpoint instruction, store the length of the string in |
| 98 | *LEN and optionally adjust *PC to point to the correct memory |
| 99 | location for inserting the breakpoint. */ |
| 100 | |
| 101 | /* tb 0,r0,511 */ |
| 102 | constexpr gdb_byte m88k_break_insn[] = { 0xf0, 0x00, 0xd1, 0xff }; |
| 103 | |
| 104 | typedef BP_MANIPULATION (m88k_break_insn) m88k_breakpoint; |
| 105 | |
| 106 | static CORE_ADDR |
| 107 | m88k_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 108 | { |
| 109 | CORE_ADDR pc; |
| 110 | |
| 111 | pc = frame_unwind_register_unsigned (next_frame, M88K_SXIP_REGNUM); |
| 112 | return m88k_addr_bits_remove (gdbarch, pc); |
| 113 | } |
| 114 | |
| 115 | static void |
| 116 | m88k_write_pc (struct regcache *regcache, CORE_ADDR pc) |
| 117 | { |
| 118 | /* According to the MC88100 RISC Microprocessor User's Manual, |
| 119 | section 6.4.3.1.2: |
| 120 | |
| 121 | "... can be made to return to a particular instruction by placing |
| 122 | a valid instruction address in the SNIP and the next sequential |
| 123 | instruction address in the SFIP (with V bits set and E bits |
| 124 | clear). The rte resumes execution at the instruction pointed to |
| 125 | by the SNIP, then the SFIP." |
| 126 | |
| 127 | The E bit is the least significant bit (bit 0). The V (valid) |
| 128 | bit is bit 1. This is why we logical or 2 into the values we are |
| 129 | writing below. It turns out that SXIP plays no role when |
| 130 | returning from an exception so nothing special has to be done |
| 131 | with it. We could even (presumably) give it a totally bogus |
| 132 | value. */ |
| 133 | |
| 134 | regcache_cooked_write_unsigned (regcache, M88K_SXIP_REGNUM, pc); |
| 135 | regcache_cooked_write_unsigned (regcache, M88K_SNIP_REGNUM, pc | 2); |
| 136 | regcache_cooked_write_unsigned (regcache, M88K_SFIP_REGNUM, (pc + 4) | 2); |
| 137 | } |
| 138 | \f |
| 139 | |
| 140 | /* The functions on this page are intended to be used to classify |
| 141 | function arguments. */ |
| 142 | |
| 143 | /* Check whether TYPE is "Integral or Pointer". */ |
| 144 | |
| 145 | static int |
| 146 | m88k_integral_or_pointer_p (const struct type *type) |
| 147 | { |
| 148 | switch (TYPE_CODE (type)) |
| 149 | { |
| 150 | case TYPE_CODE_INT: |
| 151 | case TYPE_CODE_BOOL: |
| 152 | case TYPE_CODE_CHAR: |
| 153 | case TYPE_CODE_ENUM: |
| 154 | case TYPE_CODE_RANGE: |
| 155 | { |
| 156 | /* We have byte, half-word, word and extended-word/doubleword |
| 157 | integral types. */ |
| 158 | int len = TYPE_LENGTH (type); |
| 159 | return (len == 1 || len == 2 || len == 4 || len == 8); |
| 160 | } |
| 161 | return 1; |
| 162 | case TYPE_CODE_PTR: |
| 163 | case TYPE_CODE_REF: |
| 164 | case TYPE_CODE_RVALUE_REF: |
| 165 | { |
| 166 | /* Allow only 32-bit pointers. */ |
| 167 | return (TYPE_LENGTH (type) == 4); |
| 168 | } |
| 169 | return 1; |
| 170 | default: |
| 171 | break; |
| 172 | } |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
| 177 | /* Check whether TYPE is "Floating". */ |
| 178 | |
| 179 | static int |
| 180 | m88k_floating_p (const struct type *type) |
| 181 | { |
| 182 | switch (TYPE_CODE (type)) |
| 183 | { |
| 184 | case TYPE_CODE_FLT: |
| 185 | { |
| 186 | int len = TYPE_LENGTH (type); |
| 187 | return (len == 4 || len == 8); |
| 188 | } |
| 189 | default: |
| 190 | break; |
| 191 | } |
| 192 | |
| 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | /* Check whether TYPE is "Structure or Union". */ |
| 197 | |
| 198 | static int |
| 199 | m88k_structure_or_union_p (const struct type *type) |
| 200 | { |
| 201 | switch (TYPE_CODE (type)) |
| 202 | { |
| 203 | case TYPE_CODE_STRUCT: |
| 204 | case TYPE_CODE_UNION: |
| 205 | return 1; |
| 206 | default: |
| 207 | break; |
| 208 | } |
| 209 | |
| 210 | return 0; |
| 211 | } |
| 212 | |
| 213 | /* Check whether TYPE has 8-byte alignment. */ |
| 214 | |
| 215 | static int |
| 216 | m88k_8_byte_align_p (struct type *type) |
| 217 | { |
| 218 | if (m88k_structure_or_union_p (type)) |
| 219 | { |
| 220 | int i; |
| 221 | |
| 222 | for (i = 0; i < TYPE_NFIELDS (type); i++) |
| 223 | { |
| 224 | struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); |
| 225 | |
| 226 | if (m88k_8_byte_align_p (subtype)) |
| 227 | return 1; |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | if (m88k_integral_or_pointer_p (type) || m88k_floating_p (type)) |
| 232 | return (TYPE_LENGTH (type) == 8); |
| 233 | |
| 234 | return 0; |
| 235 | } |
| 236 | |
| 237 | /* Check whether TYPE can be passed in a register. */ |
| 238 | |
| 239 | static int |
| 240 | m88k_in_register_p (struct type *type) |
| 241 | { |
| 242 | if (m88k_integral_or_pointer_p (type) || m88k_floating_p (type)) |
| 243 | return 1; |
| 244 | |
| 245 | if (m88k_structure_or_union_p (type) && TYPE_LENGTH (type) == 4) |
| 246 | return 1; |
| 247 | |
| 248 | return 0; |
| 249 | } |
| 250 | |
| 251 | static CORE_ADDR |
| 252 | m88k_store_arguments (struct regcache *regcache, int nargs, |
| 253 | struct value **args, CORE_ADDR sp) |
| 254 | { |
| 255 | struct gdbarch *gdbarch = regcache->arch (); |
| 256 | int num_register_words = 0; |
| 257 | int num_stack_words = 0; |
| 258 | int i; |
| 259 | |
| 260 | for (i = 0; i < nargs; i++) |
| 261 | { |
| 262 | struct type *type = value_type (args[i]); |
| 263 | int len = TYPE_LENGTH (type); |
| 264 | |
| 265 | if (m88k_integral_or_pointer_p (type) && len < 4) |
| 266 | { |
| 267 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
| 268 | args[i]); |
| 269 | type = value_type (args[i]); |
| 270 | len = TYPE_LENGTH (type); |
| 271 | } |
| 272 | |
| 273 | if (m88k_in_register_p (type)) |
| 274 | { |
| 275 | int num_words = 0; |
| 276 | |
| 277 | if (num_register_words % 2 == 1 && m88k_8_byte_align_p (type)) |
| 278 | num_words++; |
| 279 | |
| 280 | num_words += ((len + 3) / 4); |
| 281 | if (num_register_words + num_words <= 8) |
| 282 | { |
| 283 | num_register_words += num_words; |
| 284 | continue; |
| 285 | } |
| 286 | |
| 287 | /* We've run out of available registers. Pass the argument |
| 288 | on the stack. */ |
| 289 | } |
| 290 | |
| 291 | if (num_stack_words % 2 == 1 && m88k_8_byte_align_p (type)) |
| 292 | num_stack_words++; |
| 293 | |
| 294 | num_stack_words += ((len + 3) / 4); |
| 295 | } |
| 296 | |
| 297 | /* Allocate stack space. */ |
| 298 | sp = align_down (sp - 32 - num_stack_words * 4, 16); |
| 299 | num_stack_words = num_register_words = 0; |
| 300 | |
| 301 | for (i = 0; i < nargs; i++) |
| 302 | { |
| 303 | const bfd_byte *valbuf = value_contents (args[i]); |
| 304 | struct type *type = value_type (args[i]); |
| 305 | int len = TYPE_LENGTH (type); |
| 306 | int stack_word = num_stack_words; |
| 307 | |
| 308 | if (m88k_in_register_p (type)) |
| 309 | { |
| 310 | int register_word = num_register_words; |
| 311 | |
| 312 | if (register_word % 2 == 1 && m88k_8_byte_align_p (type)) |
| 313 | register_word++; |
| 314 | |
| 315 | gdb_assert (len == 4 || len == 8); |
| 316 | |
| 317 | if (register_word + len / 8 < 8) |
| 318 | { |
| 319 | int regnum = M88K_R2_REGNUM + register_word; |
| 320 | |
| 321 | regcache_raw_write (regcache, regnum, valbuf); |
| 322 | if (len > 4) |
| 323 | regcache_raw_write (regcache, regnum + 1, valbuf + 4); |
| 324 | |
| 325 | num_register_words = (register_word + len / 4); |
| 326 | continue; |
| 327 | } |
| 328 | } |
| 329 | |
| 330 | if (stack_word % 2 == -1 && m88k_8_byte_align_p (type)) |
| 331 | stack_word++; |
| 332 | |
| 333 | write_memory (sp + stack_word * 4, valbuf, len); |
| 334 | num_stack_words = (stack_word + (len + 3) / 4); |
| 335 | } |
| 336 | |
| 337 | return sp; |
| 338 | } |
| 339 | |
| 340 | static CORE_ADDR |
| 341 | m88k_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
| 342 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
| 343 | struct value **args, CORE_ADDR sp, int struct_return, |
| 344 | CORE_ADDR struct_addr) |
| 345 | { |
| 346 | /* Set up the function arguments. */ |
| 347 | sp = m88k_store_arguments (regcache, nargs, args, sp); |
| 348 | gdb_assert (sp % 16 == 0); |
| 349 | |
| 350 | /* Store return value address. */ |
| 351 | if (struct_return) |
| 352 | regcache_raw_write_unsigned (regcache, M88K_R12_REGNUM, struct_addr); |
| 353 | |
| 354 | /* Store the stack pointer and return address in the appropriate |
| 355 | registers. */ |
| 356 | regcache_raw_write_unsigned (regcache, M88K_R31_REGNUM, sp); |
| 357 | regcache_raw_write_unsigned (regcache, M88K_R1_REGNUM, bp_addr); |
| 358 | |
| 359 | /* Return the stack pointer. */ |
| 360 | return sp; |
| 361 | } |
| 362 | |
| 363 | static struct frame_id |
| 364 | m88k_dummy_id (struct gdbarch *arch, struct frame_info *this_frame) |
| 365 | { |
| 366 | CORE_ADDR sp; |
| 367 | |
| 368 | sp = get_frame_register_unsigned (this_frame, M88K_R31_REGNUM); |
| 369 | return frame_id_build (sp, get_frame_pc (this_frame)); |
| 370 | } |
| 371 | \f |
| 372 | |
| 373 | /* Determine, for architecture GDBARCH, how a return value of TYPE |
| 374 | should be returned. If it is supposed to be returned in registers, |
| 375 | and READBUF is non-zero, read the appropriate value from REGCACHE, |
| 376 | and copy it into READBUF. If WRITEBUF is non-zero, write the value |
| 377 | from WRITEBUF into REGCACHE. */ |
| 378 | |
| 379 | static enum return_value_convention |
| 380 | m88k_return_value (struct gdbarch *gdbarch, struct value *function, |
| 381 | struct type *type, struct regcache *regcache, |
| 382 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 383 | { |
| 384 | int len = TYPE_LENGTH (type); |
| 385 | gdb_byte buf[8]; |
| 386 | |
| 387 | if (!m88k_integral_or_pointer_p (type) && !m88k_floating_p (type)) |
| 388 | return RETURN_VALUE_STRUCT_CONVENTION; |
| 389 | |
| 390 | if (readbuf) |
| 391 | { |
| 392 | /* Read the contents of R2 and (if necessary) R3. */ |
| 393 | regcache_cooked_read (regcache, M88K_R2_REGNUM, buf); |
| 394 | if (len > 4) |
| 395 | { |
| 396 | regcache_cooked_read (regcache, M88K_R3_REGNUM, buf + 4); |
| 397 | gdb_assert (len == 8); |
| 398 | memcpy (readbuf, buf, len); |
| 399 | } |
| 400 | else |
| 401 | { |
| 402 | /* Just stripping off any unused bytes should preserve the |
| 403 | signed-ness just fine. */ |
| 404 | memcpy (readbuf, buf + 4 - len, len); |
| 405 | } |
| 406 | } |
| 407 | |
| 408 | if (writebuf) |
| 409 | { |
| 410 | /* Read the contents to R2 and (if necessary) R3. */ |
| 411 | if (len > 4) |
| 412 | { |
| 413 | gdb_assert (len == 8); |
| 414 | memcpy (buf, writebuf, 8); |
| 415 | regcache_cooked_write (regcache, M88K_R3_REGNUM, buf + 4); |
| 416 | } |
| 417 | else |
| 418 | { |
| 419 | /* ??? Do we need to do any sign-extension here? */ |
| 420 | memcpy (buf + 4 - len, writebuf, len); |
| 421 | } |
| 422 | regcache_cooked_write (regcache, M88K_R2_REGNUM, buf); |
| 423 | } |
| 424 | |
| 425 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 426 | } |
| 427 | \f |
| 428 | /* Default frame unwinder. */ |
| 429 | |
| 430 | struct m88k_frame_cache |
| 431 | { |
| 432 | /* Base address. */ |
| 433 | CORE_ADDR base; |
| 434 | CORE_ADDR pc; |
| 435 | |
| 436 | int sp_offset; |
| 437 | int fp_offset; |
| 438 | |
| 439 | /* Table of saved registers. */ |
| 440 | struct trad_frame_saved_reg *saved_regs; |
| 441 | }; |
| 442 | |
| 443 | /* Prologue analysis. */ |
| 444 | |
| 445 | /* Macros for extracting fields from instructions. */ |
| 446 | |
| 447 | #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos)) |
| 448 | #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width)) |
| 449 | #define SUBU_OFFSET(x) ((unsigned)(x & 0xFFFF)) |
| 450 | #define ST_OFFSET(x) ((unsigned)((x) & 0xFFFF)) |
| 451 | #define ST_SRC(x) EXTRACT_FIELD ((x), 21, 5) |
| 452 | #define ADDU_OFFSET(x) ((unsigned)(x & 0xFFFF)) |
| 453 | |
| 454 | /* Possible actions to be taken by the prologue analyzer for the |
| 455 | instructions it encounters. */ |
| 456 | |
| 457 | enum m88k_prologue_insn_action |
| 458 | { |
| 459 | M88K_PIA_SKIP, /* Ignore. */ |
| 460 | M88K_PIA_NOTE_ST, /* Note register store. */ |
| 461 | M88K_PIA_NOTE_STD, /* Note register pair store. */ |
| 462 | M88K_PIA_NOTE_SP_ADJUSTMENT, /* Note stack pointer adjustment. */ |
| 463 | M88K_PIA_NOTE_FP_ASSIGNMENT, /* Note frame pointer assignment. */ |
| 464 | M88K_PIA_NOTE_BRANCH, /* Note branch. */ |
| 465 | M88K_PIA_NOTE_PROLOGUE_END /* Note end of prologue. */ |
| 466 | }; |
| 467 | |
| 468 | /* Table of instructions that may comprise a function prologue. */ |
| 469 | |
| 470 | struct m88k_prologue_insn |
| 471 | { |
| 472 | unsigned long insn; |
| 473 | unsigned long mask; |
| 474 | enum m88k_prologue_insn_action action; |
| 475 | }; |
| 476 | |
| 477 | struct m88k_prologue_insn m88k_prologue_insn_table[] = |
| 478 | { |
| 479 | /* Various register move instructions. */ |
| 480 | { 0x58000000, 0xf800ffff, M88K_PIA_SKIP }, /* or/or.u with immed of 0 */ |
| 481 | { 0xf4005800, 0xfc1fffe0, M88K_PIA_SKIP }, /* or rd,r0,rs */ |
| 482 | { 0xf4005800, 0xfc00ffff, M88K_PIA_SKIP }, /* or rd,rs,r0 */ |
| 483 | |
| 484 | /* Various other instructions. */ |
| 485 | { 0x58000000, 0xf8000000, M88K_PIA_SKIP }, /* or/or.u */ |
| 486 | |
| 487 | /* Stack pointer setup: "subu sp,sp,n" where n is a multiple of 8. */ |
| 488 | { 0x67ff0000, 0xffff0007, M88K_PIA_NOTE_SP_ADJUSTMENT }, |
| 489 | |
| 490 | /* Frame pointer assignment: "addu r30,r31,n". */ |
| 491 | { 0x63df0000, 0xffff0000, M88K_PIA_NOTE_FP_ASSIGNMENT }, |
| 492 | |
| 493 | /* Store to stack instructions; either "st rx,sp,n" or "st.d rx,sp,n". */ |
| 494 | { 0x241f0000, 0xfc1f0000, M88K_PIA_NOTE_ST }, /* st rx,sp,n */ |
| 495 | { 0x201f0000, 0xfc1f0000, M88K_PIA_NOTE_STD }, /* st.d rs,sp,n */ |
| 496 | |
| 497 | /* Instructions needed for setting up r25 for pic code. */ |
| 498 | { 0x5f200000, 0xffff0000, M88K_PIA_SKIP }, /* or.u r25,r0,offset_high */ |
| 499 | { 0xcc000002, 0xffffffff, M88K_PIA_SKIP }, /* bsr.n Lab */ |
| 500 | { 0x5b390000, 0xffff0000, M88K_PIA_SKIP }, /* or r25,r25,offset_low */ |
| 501 | { 0xf7396001, 0xffffffff, M88K_PIA_SKIP }, /* Lab: addu r25,r25,r1 */ |
| 502 | |
| 503 | /* Various branch or jump instructions which have a delay slot -- |
| 504 | these do not form part of the prologue, but the instruction in |
| 505 | the delay slot might be a store instruction which should be |
| 506 | noted. */ |
| 507 | { 0xc4000000, 0xe4000000, M88K_PIA_NOTE_BRANCH }, |
| 508 | /* br.n, bsr.n, bb0.n, or bb1.n */ |
| 509 | { 0xec000000, 0xfc000000, M88K_PIA_NOTE_BRANCH }, /* bcnd.n */ |
| 510 | { 0xf400c400, 0xfffff7e0, M88K_PIA_NOTE_BRANCH }, /* jmp.n or jsr.n */ |
| 511 | |
| 512 | /* Catch all. Ends prologue analysis. */ |
| 513 | { 0x00000000, 0x00000000, M88K_PIA_NOTE_PROLOGUE_END } |
| 514 | }; |
| 515 | |
| 516 | /* Do a full analysis of the function prologue at PC and update CACHE |
| 517 | accordingly. Bail out early if LIMIT is reached. Return the |
| 518 | address where the analysis stopped. If LIMIT points beyond the |
| 519 | function prologue, the return address should be the end of the |
| 520 | prologue. */ |
| 521 | |
| 522 | static CORE_ADDR |
| 523 | m88k_analyze_prologue (struct gdbarch *gdbarch, |
| 524 | CORE_ADDR pc, CORE_ADDR limit, |
| 525 | struct m88k_frame_cache *cache) |
| 526 | { |
| 527 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 528 | CORE_ADDR end = limit; |
| 529 | |
| 530 | /* Provide a dummy cache if necessary. */ |
| 531 | if (cache == NULL) |
| 532 | { |
| 533 | cache = XALLOCA (struct m88k_frame_cache); |
| 534 | cache->saved_regs = |
| 535 | XALLOCAVEC (struct trad_frame_saved_reg, M88K_R31_REGNUM + 1); |
| 536 | |
| 537 | /* We only initialize the members we care about. */ |
| 538 | cache->saved_regs[M88K_R1_REGNUM].addr = -1; |
| 539 | cache->fp_offset = -1; |
| 540 | } |
| 541 | |
| 542 | while (pc < limit) |
| 543 | { |
| 544 | struct m88k_prologue_insn *pi = m88k_prologue_insn_table; |
| 545 | unsigned long insn = m88k_fetch_instruction (pc, byte_order); |
| 546 | |
| 547 | while ((insn & pi->mask) != pi->insn) |
| 548 | pi++; |
| 549 | |
| 550 | switch (pi->action) |
| 551 | { |
| 552 | case M88K_PIA_SKIP: |
| 553 | /* If we have a frame pointer, and R1 has been saved, |
| 554 | consider this instruction as not being part of the |
| 555 | prologue. */ |
| 556 | if (cache->fp_offset != -1 |
| 557 | && cache->saved_regs[M88K_R1_REGNUM].addr != -1) |
| 558 | return std::min (pc, end); |
| 559 | break; |
| 560 | |
| 561 | case M88K_PIA_NOTE_ST: |
| 562 | case M88K_PIA_NOTE_STD: |
| 563 | /* If no frame has been allocated, the stores aren't part of |
| 564 | the prologue. */ |
| 565 | if (cache->sp_offset == 0) |
| 566 | return std::min (pc, end); |
| 567 | |
| 568 | /* Record location of saved registers. */ |
| 569 | { |
| 570 | int regnum = ST_SRC (insn) + M88K_R0_REGNUM; |
| 571 | ULONGEST offset = ST_OFFSET (insn); |
| 572 | |
| 573 | cache->saved_regs[regnum].addr = offset; |
| 574 | if (pi->action == M88K_PIA_NOTE_STD && regnum < M88K_R31_REGNUM) |
| 575 | cache->saved_regs[regnum + 1].addr = offset + 4; |
| 576 | } |
| 577 | break; |
| 578 | |
| 579 | case M88K_PIA_NOTE_SP_ADJUSTMENT: |
| 580 | /* A second stack pointer adjustment isn't part of the |
| 581 | prologue. */ |
| 582 | if (cache->sp_offset != 0) |
| 583 | return std::min (pc, end); |
| 584 | |
| 585 | /* Store stack pointer adjustment. */ |
| 586 | cache->sp_offset = -SUBU_OFFSET (insn); |
| 587 | break; |
| 588 | |
| 589 | case M88K_PIA_NOTE_FP_ASSIGNMENT: |
| 590 | /* A second frame pointer assignment isn't part of the |
| 591 | prologue. */ |
| 592 | if (cache->fp_offset != -1) |
| 593 | return std::min (pc, end); |
| 594 | |
| 595 | /* Record frame pointer assignment. */ |
| 596 | cache->fp_offset = ADDU_OFFSET (insn); |
| 597 | break; |
| 598 | |
| 599 | case M88K_PIA_NOTE_BRANCH: |
| 600 | /* The branch instruction isn't part of the prologue, but |
| 601 | the instruction in the delay slot might be. Limit the |
| 602 | prologue analysis to the delay slot and record the branch |
| 603 | instruction as the end of the prologue. */ |
| 604 | limit = std::min (limit, pc + 2 * M88K_INSN_SIZE); |
| 605 | end = pc; |
| 606 | break; |
| 607 | |
| 608 | case M88K_PIA_NOTE_PROLOGUE_END: |
| 609 | return std::min (pc, end); |
| 610 | } |
| 611 | |
| 612 | pc += M88K_INSN_SIZE; |
| 613 | } |
| 614 | |
| 615 | return end; |
| 616 | } |
| 617 | |
| 618 | /* An upper limit to the size of the prologue. */ |
| 619 | const int m88k_max_prologue_size = 128 * M88K_INSN_SIZE; |
| 620 | |
| 621 | /* Return the address of first real instruction of the function |
| 622 | starting at PC. */ |
| 623 | |
| 624 | static CORE_ADDR |
| 625 | m88k_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 626 | { |
| 627 | struct symtab_and_line sal; |
| 628 | CORE_ADDR func_start, func_end; |
| 629 | |
| 630 | /* This is the preferred method, find the end of the prologue by |
| 631 | using the debugging information. */ |
| 632 | if (find_pc_partial_function (pc, NULL, &func_start, &func_end)) |
| 633 | { |
| 634 | sal = find_pc_line (func_start, 0); |
| 635 | |
| 636 | if (sal.end < func_end && pc <= sal.end) |
| 637 | return sal.end; |
| 638 | } |
| 639 | |
| 640 | return m88k_analyze_prologue (gdbarch, pc, pc + m88k_max_prologue_size, |
| 641 | NULL); |
| 642 | } |
| 643 | |
| 644 | static struct m88k_frame_cache * |
| 645 | m88k_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 646 | { |
| 647 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 648 | struct m88k_frame_cache *cache; |
| 649 | CORE_ADDR frame_sp; |
| 650 | |
| 651 | if (*this_cache) |
| 652 | return (struct m88k_frame_cache *) *this_cache; |
| 653 | |
| 654 | cache = FRAME_OBSTACK_ZALLOC (struct m88k_frame_cache); |
| 655 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 656 | cache->fp_offset = -1; |
| 657 | |
| 658 | cache->pc = get_frame_func (this_frame); |
| 659 | if (cache->pc != 0) |
| 660 | m88k_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
| 661 | cache); |
| 662 | |
| 663 | /* Calculate the stack pointer used in the prologue. */ |
| 664 | if (cache->fp_offset != -1) |
| 665 | { |
| 666 | CORE_ADDR fp; |
| 667 | |
| 668 | fp = get_frame_register_unsigned (this_frame, M88K_R30_REGNUM); |
| 669 | frame_sp = fp - cache->fp_offset; |
| 670 | } |
| 671 | else |
| 672 | { |
| 673 | /* If we know where the return address is saved, we can take a |
| 674 | solid guess at what the frame pointer should be. */ |
| 675 | if (cache->saved_regs[M88K_R1_REGNUM].addr != -1) |
| 676 | cache->fp_offset = cache->saved_regs[M88K_R1_REGNUM].addr - 4; |
| 677 | frame_sp = get_frame_register_unsigned (this_frame, M88K_R31_REGNUM); |
| 678 | } |
| 679 | |
| 680 | /* Now that we know the stack pointer, adjust the location of the |
| 681 | saved registers. */ |
| 682 | { |
| 683 | int regnum; |
| 684 | |
| 685 | for (regnum = M88K_R0_REGNUM; regnum < M88K_R31_REGNUM; regnum ++) |
| 686 | if (cache->saved_regs[regnum].addr != -1) |
| 687 | cache->saved_regs[regnum].addr += frame_sp; |
| 688 | } |
| 689 | |
| 690 | /* Calculate the frame's base. */ |
| 691 | cache->base = frame_sp - cache->sp_offset; |
| 692 | trad_frame_set_value (cache->saved_regs, M88K_R31_REGNUM, cache->base); |
| 693 | |
| 694 | /* Identify SXIP with the return address in R1. */ |
| 695 | cache->saved_regs[M88K_SXIP_REGNUM] = cache->saved_regs[M88K_R1_REGNUM]; |
| 696 | |
| 697 | *this_cache = cache; |
| 698 | return cache; |
| 699 | } |
| 700 | |
| 701 | static void |
| 702 | m88k_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 703 | struct frame_id *this_id) |
| 704 | { |
| 705 | struct m88k_frame_cache *cache = m88k_frame_cache (this_frame, this_cache); |
| 706 | |
| 707 | /* This marks the outermost frame. */ |
| 708 | if (cache->base == 0) |
| 709 | return; |
| 710 | |
| 711 | (*this_id) = frame_id_build (cache->base, cache->pc); |
| 712 | } |
| 713 | |
| 714 | static struct value * |
| 715 | m88k_frame_prev_register (struct frame_info *this_frame, |
| 716 | void **this_cache, int regnum) |
| 717 | { |
| 718 | struct m88k_frame_cache *cache = m88k_frame_cache (this_frame, this_cache); |
| 719 | |
| 720 | if (regnum == M88K_SNIP_REGNUM || regnum == M88K_SFIP_REGNUM) |
| 721 | { |
| 722 | struct value *value; |
| 723 | CORE_ADDR pc; |
| 724 | |
| 725 | value = trad_frame_get_prev_register (this_frame, cache->saved_regs, |
| 726 | M88K_SXIP_REGNUM); |
| 727 | pc = value_as_long (value); |
| 728 | release_value (value); |
| 729 | |
| 730 | if (regnum == M88K_SFIP_REGNUM) |
| 731 | pc += 4; |
| 732 | |
| 733 | return frame_unwind_got_constant (this_frame, regnum, pc + 4); |
| 734 | } |
| 735 | |
| 736 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum); |
| 737 | } |
| 738 | |
| 739 | static const struct frame_unwind m88k_frame_unwind = |
| 740 | { |
| 741 | NORMAL_FRAME, |
| 742 | default_frame_unwind_stop_reason, |
| 743 | m88k_frame_this_id, |
| 744 | m88k_frame_prev_register, |
| 745 | NULL, |
| 746 | default_frame_sniffer |
| 747 | }; |
| 748 | \f |
| 749 | |
| 750 | static CORE_ADDR |
| 751 | m88k_frame_base_address (struct frame_info *this_frame, void **this_cache) |
| 752 | { |
| 753 | struct m88k_frame_cache *cache = m88k_frame_cache (this_frame, this_cache); |
| 754 | |
| 755 | if (cache->fp_offset != -1) |
| 756 | return cache->base + cache->sp_offset + cache->fp_offset; |
| 757 | |
| 758 | return 0; |
| 759 | } |
| 760 | |
| 761 | static const struct frame_base m88k_frame_base = |
| 762 | { |
| 763 | &m88k_frame_unwind, |
| 764 | m88k_frame_base_address, |
| 765 | m88k_frame_base_address, |
| 766 | m88k_frame_base_address |
| 767 | }; |
| 768 | \f |
| 769 | |
| 770 | /* Core file support. */ |
| 771 | |
| 772 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
| 773 | in the general-purpose register set REGSET to register cache |
| 774 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ |
| 775 | |
| 776 | static void |
| 777 | m88k_supply_gregset (const struct regset *regset, |
| 778 | struct regcache *regcache, |
| 779 | int regnum, const void *gregs, size_t len) |
| 780 | { |
| 781 | const gdb_byte *regs = (const gdb_byte *) gregs; |
| 782 | int i; |
| 783 | |
| 784 | for (i = 0; i < M88K_NUM_REGS; i++) |
| 785 | { |
| 786 | if (regnum == i || regnum == -1) |
| 787 | regcache_raw_supply (regcache, i, regs + i * 4); |
| 788 | } |
| 789 | } |
| 790 | |
| 791 | /* Motorola 88000 register set. */ |
| 792 | |
| 793 | static const struct regset m88k_gregset = |
| 794 | { |
| 795 | NULL, |
| 796 | m88k_supply_gregset |
| 797 | }; |
| 798 | |
| 799 | /* Iterate over supported core file register note sections. */ |
| 800 | |
| 801 | static void |
| 802 | m88k_iterate_over_regset_sections (struct gdbarch *gdbarch, |
| 803 | iterate_over_regset_sections_cb *cb, |
| 804 | void *cb_data, |
| 805 | const struct regcache *regcache) |
| 806 | { |
| 807 | cb (".reg", M88K_NUM_REGS * 4, &m88k_gregset, NULL, cb_data); |
| 808 | } |
| 809 | \f |
| 810 | |
| 811 | static struct gdbarch * |
| 812 | m88k_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 813 | { |
| 814 | struct gdbarch *gdbarch; |
| 815 | |
| 816 | /* If there is already a candidate, use it. */ |
| 817 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 818 | if (arches != NULL) |
| 819 | return arches->gdbarch; |
| 820 | |
| 821 | /* Allocate space for the new architecture. */ |
| 822 | gdbarch = gdbarch_alloc (&info, NULL); |
| 823 | |
| 824 | /* There is no real `long double'. */ |
| 825 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 826 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); |
| 827 | |
| 828 | set_gdbarch_num_regs (gdbarch, M88K_NUM_REGS); |
| 829 | set_gdbarch_register_name (gdbarch, m88k_register_name); |
| 830 | set_gdbarch_register_type (gdbarch, m88k_register_type); |
| 831 | |
| 832 | /* Register numbers of various important registers. */ |
| 833 | set_gdbarch_sp_regnum (gdbarch, M88K_R31_REGNUM); |
| 834 | set_gdbarch_pc_regnum (gdbarch, M88K_SXIP_REGNUM); |
| 835 | |
| 836 | /* Core file support. */ |
| 837 | set_gdbarch_iterate_over_regset_sections |
| 838 | (gdbarch, m88k_iterate_over_regset_sections); |
| 839 | |
| 840 | set_gdbarch_skip_prologue (gdbarch, m88k_skip_prologue); |
| 841 | |
| 842 | /* Stack grows downward. */ |
| 843 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 844 | |
| 845 | /* Call dummy code. */ |
| 846 | set_gdbarch_push_dummy_call (gdbarch, m88k_push_dummy_call); |
| 847 | set_gdbarch_dummy_id (gdbarch, m88k_dummy_id); |
| 848 | |
| 849 | /* Return value info. */ |
| 850 | set_gdbarch_return_value (gdbarch, m88k_return_value); |
| 851 | |
| 852 | set_gdbarch_addr_bits_remove (gdbarch, m88k_addr_bits_remove); |
| 853 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, m88k_breakpoint::kind_from_pc); |
| 854 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, m88k_breakpoint::bp_from_kind); |
| 855 | set_gdbarch_unwind_pc (gdbarch, m88k_unwind_pc); |
| 856 | set_gdbarch_write_pc (gdbarch, m88k_write_pc); |
| 857 | |
| 858 | frame_base_set_default (gdbarch, &m88k_frame_base); |
| 859 | frame_unwind_append_unwinder (gdbarch, &m88k_frame_unwind); |
| 860 | |
| 861 | return gdbarch; |
| 862 | } |
| 863 | |
| 864 | void |
| 865 | _initialize_m88k_tdep (void) |
| 866 | { |
| 867 | gdbarch_register (bfd_arch_m88k, m88k_gdbarch_init, NULL); |
| 868 | } |