| 1 | /* Target-dependent code for Xilinx MicroBlaze. |
| 2 | |
| 3 | Copyright (C) 2009-2017 Free Software Foundation, Inc. |
| 4 | |
| 5 | This file is part of GDB. |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 3 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 19 | |
| 20 | #include "defs.h" |
| 21 | #include "arch-utils.h" |
| 22 | #include "dis-asm.h" |
| 23 | #include "frame.h" |
| 24 | #include "trad-frame.h" |
| 25 | #include "symtab.h" |
| 26 | #include "value.h" |
| 27 | #include "gdbcmd.h" |
| 28 | #include "breakpoint.h" |
| 29 | #include "inferior.h" |
| 30 | #include "regcache.h" |
| 31 | #include "target.h" |
| 32 | #include "frame-base.h" |
| 33 | #include "frame-unwind.h" |
| 34 | #include "dwarf2-frame.h" |
| 35 | #include "osabi.h" |
| 36 | #include "target-descriptions.h" |
| 37 | #include "opcodes/microblaze-opcm.h" |
| 38 | #include "opcodes/microblaze-dis.h" |
| 39 | #include "microblaze-tdep.h" |
| 40 | #include "remote.h" |
| 41 | |
| 42 | #include "features/microblaze-with-stack-protect.c" |
| 43 | #include "features/microblaze.c" |
| 44 | \f |
| 45 | /* Instruction macros used for analyzing the prologue. */ |
| 46 | /* This set of instruction macros need to be changed whenever the |
| 47 | prologue generated by the compiler could have more instructions or |
| 48 | different type of instructions. |
| 49 | This set also needs to be verified if it is complete. */ |
| 50 | #define IS_RETURN(op) (op == rtsd || op == rtid) |
| 51 | #define IS_UPDATE_SP(op, rd, ra) \ |
| 52 | ((op == addik || op == addi) && rd == REG_SP && ra == REG_SP) |
| 53 | #define IS_SPILL_SP(op, rd, ra) \ |
| 54 | ((op == swi || op == sw) && rd == REG_SP && ra == REG_SP) |
| 55 | #define IS_SPILL_REG(op, rd, ra) \ |
| 56 | ((op == swi || op == sw) && rd != REG_SP && ra == REG_SP) |
| 57 | #define IS_ALSO_SPILL_REG(op, rd, ra, rb) \ |
| 58 | ((op == swi || op == sw) && rd != REG_SP && ra == 0 && rb == REG_SP) |
| 59 | #define IS_SETUP_FP(op, ra, rb) \ |
| 60 | ((op == add || op == addik || op == addk) && ra == REG_SP && rb == 0) |
| 61 | #define IS_SPILL_REG_FP(op, rd, ra, fpregnum) \ |
| 62 | ((op == swi || op == sw) && rd != REG_SP && ra == fpregnum && ra != 0) |
| 63 | #define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \ |
| 64 | ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0) |
| 65 | |
| 66 | /* The registers of the Xilinx microblaze processor. */ |
| 67 | |
| 68 | static const char *microblaze_register_names[] = |
| 69 | { |
| 70 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
| 71 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
| 72 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
| 73 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
| 74 | "rpc", "rmsr", "rear", "resr", "rfsr", "rbtr", |
| 75 | "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6", |
| 76 | "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11", |
| 77 | "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi", |
| 78 | "rslr", "rshr" |
| 79 | }; |
| 80 | |
| 81 | #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names) |
| 82 | \f |
| 83 | static unsigned int microblaze_debug_flag = 0; |
| 84 | |
| 85 | static void ATTRIBUTE_PRINTF (1, 2) |
| 86 | microblaze_debug (const char *fmt, ...) |
| 87 | { |
| 88 | if (microblaze_debug_flag) |
| 89 | { |
| 90 | va_list args; |
| 91 | |
| 92 | va_start (args, fmt); |
| 93 | printf_unfiltered ("MICROBLAZE: "); |
| 94 | vprintf_unfiltered (fmt, args); |
| 95 | va_end (args); |
| 96 | } |
| 97 | } |
| 98 | \f |
| 99 | /* Return the name of register REGNUM. */ |
| 100 | |
| 101 | static const char * |
| 102 | microblaze_register_name (struct gdbarch *gdbarch, int regnum) |
| 103 | { |
| 104 | if (regnum >= 0 && regnum < MICROBLAZE_NUM_REGS) |
| 105 | return microblaze_register_names[regnum]; |
| 106 | return NULL; |
| 107 | } |
| 108 | |
| 109 | static struct type * |
| 110 | microblaze_register_type (struct gdbarch *gdbarch, int regnum) |
| 111 | { |
| 112 | if (regnum == MICROBLAZE_SP_REGNUM) |
| 113 | return builtin_type (gdbarch)->builtin_data_ptr; |
| 114 | |
| 115 | if (regnum == MICROBLAZE_PC_REGNUM) |
| 116 | return builtin_type (gdbarch)->builtin_func_ptr; |
| 117 | |
| 118 | return builtin_type (gdbarch)->builtin_int; |
| 119 | } |
| 120 | |
| 121 | \f |
| 122 | /* Fetch the instruction at PC. */ |
| 123 | |
| 124 | static unsigned long |
| 125 | microblaze_fetch_instruction (CORE_ADDR pc) |
| 126 | { |
| 127 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
| 128 | gdb_byte buf[4]; |
| 129 | |
| 130 | /* If we can't read the instruction at PC, return zero. */ |
| 131 | if (target_read_code (pc, buf, sizeof (buf))) |
| 132 | return 0; |
| 133 | |
| 134 | return extract_unsigned_integer (buf, 4, byte_order); |
| 135 | } |
| 136 | \f |
| 137 | constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT; |
| 138 | |
| 139 | typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint; |
| 140 | |
| 141 | \f |
| 142 | /* Allocate and initialize a frame cache. */ |
| 143 | |
| 144 | static struct microblaze_frame_cache * |
| 145 | microblaze_alloc_frame_cache (void) |
| 146 | { |
| 147 | struct microblaze_frame_cache *cache; |
| 148 | |
| 149 | cache = FRAME_OBSTACK_ZALLOC (struct microblaze_frame_cache); |
| 150 | |
| 151 | /* Base address. */ |
| 152 | cache->base = 0; |
| 153 | cache->pc = 0; |
| 154 | |
| 155 | /* Frameless until proven otherwise. */ |
| 156 | cache->frameless_p = 1; |
| 157 | |
| 158 | return cache; |
| 159 | } |
| 160 | |
| 161 | /* The base of the current frame is actually in the stack pointer. |
| 162 | This happens when there is no frame pointer (microblaze ABI does not |
| 163 | require a frame pointer) or when we're stopped in the prologue or |
| 164 | epilogue itself. In these cases, microblaze_analyze_prologue will need |
| 165 | to update fi->frame before returning or analyzing the register |
| 166 | save instructions. */ |
| 167 | #define MICROBLAZE_MY_FRAME_IN_SP 0x1 |
| 168 | |
| 169 | /* The base of the current frame is in a frame pointer register. |
| 170 | This register is noted in frame_extra_info->fp_regnum. |
| 171 | |
| 172 | Note that the existance of an FP might also indicate that the |
| 173 | function has called alloca. */ |
| 174 | #define MICROBLAZE_MY_FRAME_IN_FP 0x2 |
| 175 | |
| 176 | /* Function prologues on the Xilinx microblaze processors consist of: |
| 177 | |
| 178 | - adjustments to the stack pointer (r1) (addi r1, r1, imm) |
| 179 | - making a copy of r1 into another register (a "frame" pointer) |
| 180 | (add r?, r1, r0) |
| 181 | - store word/multiples that use r1 or the frame pointer as the |
| 182 | base address (swi r?, r1, imm OR swi r?, fp, imm) |
| 183 | |
| 184 | Note that microblaze really doesn't have a real frame pointer. |
| 185 | Instead, the compiler may copy the SP into a register (usually |
| 186 | r19) to act as an arg pointer. For our target-dependent purposes, |
| 187 | the frame info's "frame" member will be the beginning of the |
| 188 | frame. The SP could, in fact, point below this. |
| 189 | |
| 190 | The prologue ends when an instruction fails to meet either of |
| 191 | these criteria. */ |
| 192 | |
| 193 | /* Analyze the prologue to determine where registers are saved, |
| 194 | the end of the prologue, etc. Return the address of the first line |
| 195 | of "real" code (i.e., the end of the prologue). */ |
| 196 | |
| 197 | static CORE_ADDR |
| 198 | microblaze_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
| 199 | CORE_ADDR current_pc, |
| 200 | struct microblaze_frame_cache *cache) |
| 201 | { |
| 202 | const char *name; |
| 203 | CORE_ADDR func_addr, func_end, addr, stop, prologue_end_addr = 0; |
| 204 | unsigned long insn; |
| 205 | int rd, ra, rb, imm; |
| 206 | enum microblaze_instr op; |
| 207 | int flags = 0; |
| 208 | int save_hidden_pointer_found = 0; |
| 209 | int non_stack_instruction_found = 0; |
| 210 | |
| 211 | /* Find the start of this function. */ |
| 212 | find_pc_partial_function (pc, &name, &func_addr, &func_end); |
| 213 | if (func_addr < pc) |
| 214 | pc = func_addr; |
| 215 | |
| 216 | if (current_pc < pc) |
| 217 | return current_pc; |
| 218 | |
| 219 | /* Initialize info about frame. */ |
| 220 | cache->framesize = 0; |
| 221 | cache->fp_regnum = MICROBLAZE_SP_REGNUM; |
| 222 | cache->frameless_p = 1; |
| 223 | |
| 224 | /* Start decoding the prologue. We start by checking two special cases: |
| 225 | |
| 226 | 1. We're about to return |
| 227 | 2. We're at the first insn of the prologue. |
| 228 | |
| 229 | If we're about to return, our frame has already been deallocated. |
| 230 | If we are stopped at the first instruction of a prologue, |
| 231 | then our frame has not yet been set up. */ |
| 232 | |
| 233 | /* Get the first insn from memory. */ |
| 234 | |
| 235 | insn = microblaze_fetch_instruction (pc); |
| 236 | op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); |
| 237 | |
| 238 | if (IS_RETURN(op)) |
| 239 | return pc; |
| 240 | |
| 241 | /* Start at beginning of function and analyze until we get to the |
| 242 | current pc, or the end of the function, whichever is first. */ |
| 243 | stop = (current_pc < func_end ? current_pc : func_end); |
| 244 | |
| 245 | microblaze_debug ("Scanning prologue: name=%s, func_addr=%s, stop=%s\n", |
| 246 | name, paddress (gdbarch, func_addr), |
| 247 | paddress (gdbarch, stop)); |
| 248 | |
| 249 | for (addr = func_addr; addr < stop; addr += INST_WORD_SIZE) |
| 250 | { |
| 251 | insn = microblaze_fetch_instruction (addr); |
| 252 | op = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm); |
| 253 | microblaze_debug ("%s %08lx\n", paddress (gdbarch, pc), insn); |
| 254 | |
| 255 | /* This code is very sensitive to what functions are present in the |
| 256 | prologue. It assumes that the (addi, addik, swi, sw) can be the |
| 257 | only instructions in the prologue. */ |
| 258 | if (IS_UPDATE_SP(op, rd, ra)) |
| 259 | { |
| 260 | microblaze_debug ("got addi r1,r1,%d; contnuing\n", imm); |
| 261 | if (cache->framesize) |
| 262 | break; /* break if framesize already computed. */ |
| 263 | cache->framesize = -imm; /* stack grows towards low memory. */ |
| 264 | cache->frameless_p = 0; /* Frame found. */ |
| 265 | save_hidden_pointer_found = 0; |
| 266 | non_stack_instruction_found = 0; |
| 267 | continue; |
| 268 | } |
| 269 | else if (IS_SPILL_SP(op, rd, ra)) |
| 270 | { |
| 271 | /* Spill stack pointer. */ |
| 272 | cache->register_offsets[rd] = imm; /* SP spilled before updating. */ |
| 273 | |
| 274 | microblaze_debug ("swi r1 r1 %d, continuing\n", imm); |
| 275 | save_hidden_pointer_found = 0; |
| 276 | if (!cache->framesize) |
| 277 | non_stack_instruction_found = 0; |
| 278 | continue; |
| 279 | } |
| 280 | else if (IS_SPILL_REG(op, rd, ra)) |
| 281 | { |
| 282 | /* Spill register. */ |
| 283 | cache->register_offsets[rd] = imm - cache->framesize; |
| 284 | |
| 285 | microblaze_debug ("swi %d r1 %d, continuing\n", rd, imm); |
| 286 | save_hidden_pointer_found = 0; |
| 287 | if (!cache->framesize) |
| 288 | non_stack_instruction_found = 0; |
| 289 | continue; |
| 290 | } |
| 291 | else if (IS_ALSO_SPILL_REG(op, rd, ra, rb)) |
| 292 | { |
| 293 | /* Spill register. */ |
| 294 | cache->register_offsets[rd] = 0 - cache->framesize; |
| 295 | |
| 296 | microblaze_debug ("sw %d r0 r1, continuing\n", rd); |
| 297 | save_hidden_pointer_found = 0; |
| 298 | if (!cache->framesize) |
| 299 | non_stack_instruction_found = 0; |
| 300 | continue; |
| 301 | } |
| 302 | else if (IS_SETUP_FP(op, ra, rb)) |
| 303 | { |
| 304 | /* We have a frame pointer. Note the register which is |
| 305 | acting as the frame pointer. */ |
| 306 | flags |= MICROBLAZE_MY_FRAME_IN_FP; |
| 307 | flags &= ~MICROBLAZE_MY_FRAME_IN_SP; |
| 308 | cache->fp_regnum = rd; |
| 309 | microblaze_debug ("Found a frame pointer: r%d\n", cache->fp_regnum); |
| 310 | save_hidden_pointer_found = 0; |
| 311 | if (!cache->framesize) |
| 312 | non_stack_instruction_found = 0; |
| 313 | continue; |
| 314 | } |
| 315 | else if (IS_SPILL_REG_FP(op, rd, ra, cache->fp_regnum)) |
| 316 | { |
| 317 | /* reg spilled after updating. */ |
| 318 | cache->register_offsets[rd] = imm - cache->framesize; |
| 319 | |
| 320 | microblaze_debug ("swi %d %d %d, continuing\n", rd, ra, imm); |
| 321 | save_hidden_pointer_found = 0; |
| 322 | if (!cache->framesize) |
| 323 | non_stack_instruction_found = 0; |
| 324 | continue; |
| 325 | } |
| 326 | else if (IS_SAVE_HIDDEN_PTR(op, rd, ra, rb)) |
| 327 | { |
| 328 | /* If the first argument is a hidden pointer to the area where the |
| 329 | return structure is to be saved, then it is saved as part of the |
| 330 | prologue. */ |
| 331 | |
| 332 | microblaze_debug ("add %d %d %d, continuing\n", rd, ra, rb); |
| 333 | save_hidden_pointer_found = 1; |
| 334 | if (!cache->framesize) |
| 335 | non_stack_instruction_found = 0; |
| 336 | continue; |
| 337 | } |
| 338 | |
| 339 | /* As a result of the modification in the next step where we continue |
| 340 | to analyze the prologue till we reach a control flow instruction, |
| 341 | we need another variable to store when exactly a non-stack |
| 342 | instruction was encountered, which is the current definition |
| 343 | of a prologue. */ |
| 344 | if (!non_stack_instruction_found) |
| 345 | prologue_end_addr = addr; |
| 346 | non_stack_instruction_found = 1; |
| 347 | |
| 348 | /* When optimizations are enabled, it is not guaranteed that prologue |
| 349 | instructions are not mixed in with other instructions from the |
| 350 | program. Some programs show this behavior at -O2. This can be |
| 351 | avoided by adding -fno-schedule-insns2 switch as of now (edk 8.1) |
| 352 | In such cases, we scan the function until we see the first control |
| 353 | instruction. */ |
| 354 | |
| 355 | { |
| 356 | unsigned op = (unsigned)insn >> 26; |
| 357 | |
| 358 | /* continue if not control flow (branch, return). */ |
| 359 | if (op != 0x26 && op != 0x27 && op != 0x2d && op != 0x2e && op != 0x2f) |
| 360 | continue; |
| 361 | else if (op == 0x2c) |
| 362 | continue; /* continue if imm. */ |
| 363 | } |
| 364 | |
| 365 | /* This is not a prologue insn, so stop here. */ |
| 366 | microblaze_debug ("insn is not a prologue insn -- ending scan\n"); |
| 367 | break; |
| 368 | } |
| 369 | |
| 370 | microblaze_debug ("done analyzing prologue\n"); |
| 371 | microblaze_debug ("prologue end = 0x%x\n", (int) addr); |
| 372 | |
| 373 | /* If the last instruction was an add rd, r5, r0 then don't count it as |
| 374 | part of the prologue. */ |
| 375 | if (save_hidden_pointer_found) |
| 376 | prologue_end_addr -= INST_WORD_SIZE; |
| 377 | |
| 378 | return prologue_end_addr; |
| 379 | } |
| 380 | |
| 381 | static CORE_ADDR |
| 382 | microblaze_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
| 383 | { |
| 384 | gdb_byte buf[4]; |
| 385 | CORE_ADDR pc; |
| 386 | |
| 387 | frame_unwind_register (next_frame, MICROBLAZE_PC_REGNUM, buf); |
| 388 | pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
| 389 | /* For sentinel frame, return address is actual PC. For other frames, |
| 390 | return address is pc+8. This is a workaround because gcc does not |
| 391 | generate correct return address in CIE. */ |
| 392 | if (frame_relative_level (next_frame) >= 0) |
| 393 | pc += 8; |
| 394 | return pc; |
| 395 | } |
| 396 | |
| 397 | /* Return PC of first real instruction of the function starting at |
| 398 | START_PC. */ |
| 399 | |
| 400 | static CORE_ADDR |
| 401 | microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
| 402 | { |
| 403 | struct symtab_and_line sal; |
| 404 | CORE_ADDR func_start, func_end, ostart_pc; |
| 405 | struct microblaze_frame_cache cache; |
| 406 | |
| 407 | /* This is the preferred method, find the end of the prologue by |
| 408 | using the debugging information. Debugging info does not always |
| 409 | give the right answer since parameters are stored on stack after this. |
| 410 | Always analyze the prologue. */ |
| 411 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) |
| 412 | { |
| 413 | sal = find_pc_line (func_start, 0); |
| 414 | |
| 415 | if (sal.end < func_end |
| 416 | && start_pc <= sal.end) |
| 417 | start_pc = sal.end; |
| 418 | } |
| 419 | |
| 420 | ostart_pc = microblaze_analyze_prologue (gdbarch, func_start, 0xffffffffUL, |
| 421 | &cache); |
| 422 | |
| 423 | if (ostart_pc > start_pc) |
| 424 | return ostart_pc; |
| 425 | return start_pc; |
| 426 | } |
| 427 | |
| 428 | /* Normal frames. */ |
| 429 | |
| 430 | static struct microblaze_frame_cache * |
| 431 | microblaze_frame_cache (struct frame_info *next_frame, void **this_cache) |
| 432 | { |
| 433 | struct microblaze_frame_cache *cache; |
| 434 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
| 435 | int rn; |
| 436 | |
| 437 | if (*this_cache) |
| 438 | return (struct microblaze_frame_cache *) *this_cache; |
| 439 | |
| 440 | cache = microblaze_alloc_frame_cache (); |
| 441 | *this_cache = cache; |
| 442 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); |
| 443 | |
| 444 | /* Clear offsets to saved regs in frame. */ |
| 445 | for (rn = 0; rn < gdbarch_num_regs (gdbarch); rn++) |
| 446 | cache->register_offsets[rn] = -1; |
| 447 | |
| 448 | /* Call for side effects. */ |
| 449 | get_frame_func (next_frame); |
| 450 | |
| 451 | cache->pc = get_frame_address_in_block (next_frame); |
| 452 | |
| 453 | return cache; |
| 454 | } |
| 455 | |
| 456 | static void |
| 457 | microblaze_frame_this_id (struct frame_info *next_frame, void **this_cache, |
| 458 | struct frame_id *this_id) |
| 459 | { |
| 460 | struct microblaze_frame_cache *cache = |
| 461 | microblaze_frame_cache (next_frame, this_cache); |
| 462 | |
| 463 | /* This marks the outermost frame. */ |
| 464 | if (cache->base == 0) |
| 465 | return; |
| 466 | |
| 467 | (*this_id) = frame_id_build (cache->base, cache->pc); |
| 468 | } |
| 469 | |
| 470 | static struct value * |
| 471 | microblaze_frame_prev_register (struct frame_info *this_frame, |
| 472 | void **this_cache, int regnum) |
| 473 | { |
| 474 | struct microblaze_frame_cache *cache = |
| 475 | microblaze_frame_cache (this_frame, this_cache); |
| 476 | |
| 477 | if (cache->frameless_p) |
| 478 | { |
| 479 | if (regnum == MICROBLAZE_PC_REGNUM) |
| 480 | regnum = 15; |
| 481 | if (regnum == MICROBLAZE_SP_REGNUM) |
| 482 | regnum = 1; |
| 483 | return trad_frame_get_prev_register (this_frame, |
| 484 | cache->saved_regs, regnum); |
| 485 | } |
| 486 | else |
| 487 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, |
| 488 | regnum); |
| 489 | |
| 490 | } |
| 491 | |
| 492 | static const struct frame_unwind microblaze_frame_unwind = |
| 493 | { |
| 494 | NORMAL_FRAME, |
| 495 | default_frame_unwind_stop_reason, |
| 496 | microblaze_frame_this_id, |
| 497 | microblaze_frame_prev_register, |
| 498 | NULL, |
| 499 | default_frame_sniffer |
| 500 | }; |
| 501 | \f |
| 502 | static CORE_ADDR |
| 503 | microblaze_frame_base_address (struct frame_info *next_frame, |
| 504 | void **this_cache) |
| 505 | { |
| 506 | struct microblaze_frame_cache *cache = |
| 507 | microblaze_frame_cache (next_frame, this_cache); |
| 508 | |
| 509 | return cache->base; |
| 510 | } |
| 511 | |
| 512 | static const struct frame_base microblaze_frame_base = |
| 513 | { |
| 514 | µblaze_frame_unwind, |
| 515 | microblaze_frame_base_address, |
| 516 | microblaze_frame_base_address, |
| 517 | microblaze_frame_base_address |
| 518 | }; |
| 519 | \f |
| 520 | /* Extract from an array REGBUF containing the (raw) register state, a |
| 521 | function return value of TYPE, and copy that into VALBUF. */ |
| 522 | static void |
| 523 | microblaze_extract_return_value (struct type *type, struct regcache *regcache, |
| 524 | gdb_byte *valbuf) |
| 525 | { |
| 526 | gdb_byte buf[8]; |
| 527 | |
| 528 | /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF. */ |
| 529 | switch (TYPE_LENGTH (type)) |
| 530 | { |
| 531 | case 1: /* return last byte in the register. */ |
| 532 | regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf); |
| 533 | memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1); |
| 534 | return; |
| 535 | case 2: /* return last 2 bytes in register. */ |
| 536 | regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf); |
| 537 | memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2); |
| 538 | return; |
| 539 | case 4: /* for sizes 4 or 8, copy the required length. */ |
| 540 | case 8: |
| 541 | regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM, buf); |
| 542 | regcache_cooked_read (regcache, MICROBLAZE_RETVAL_REGNUM+1, buf+4); |
| 543 | memcpy (valbuf, buf, TYPE_LENGTH (type)); |
| 544 | return; |
| 545 | default: |
| 546 | internal_error (__FILE__, __LINE__, |
| 547 | _("Unsupported return value size requested")); |
| 548 | } |
| 549 | } |
| 550 | |
| 551 | /* Store the return value in VALBUF (of type TYPE) where the caller |
| 552 | expects to see it. |
| 553 | |
| 554 | Integers up to four bytes are stored in r3. |
| 555 | |
| 556 | Longs are stored in r3 (most significant word) and r4 (least |
| 557 | significant word). |
| 558 | |
| 559 | Small structures are always returned on stack. */ |
| 560 | |
| 561 | static void |
| 562 | microblaze_store_return_value (struct type *type, struct regcache *regcache, |
| 563 | const gdb_byte *valbuf) |
| 564 | { |
| 565 | int len = TYPE_LENGTH (type); |
| 566 | gdb_byte buf[8]; |
| 567 | |
| 568 | memset (buf, 0, sizeof(buf)); |
| 569 | |
| 570 | /* Integral and pointer return values. */ |
| 571 | |
| 572 | if (len > 4) |
| 573 | { |
| 574 | gdb_assert (len == 8); |
| 575 | memcpy (buf, valbuf, 8); |
| 576 | regcache_cooked_write (regcache, MICROBLAZE_RETVAL_REGNUM+1, buf + 4); |
| 577 | } |
| 578 | else |
| 579 | /* ??? Do we need to do any sign-extension here? */ |
| 580 | memcpy (buf + 4 - len, valbuf, len); |
| 581 | |
| 582 | regcache_cooked_write (regcache, MICROBLAZE_RETVAL_REGNUM, buf); |
| 583 | } |
| 584 | |
| 585 | static enum return_value_convention |
| 586 | microblaze_return_value (struct gdbarch *gdbarch, struct value *function, |
| 587 | struct type *type, struct regcache *regcache, |
| 588 | gdb_byte *readbuf, const gdb_byte *writebuf) |
| 589 | { |
| 590 | if (readbuf) |
| 591 | microblaze_extract_return_value (type, regcache, readbuf); |
| 592 | if (writebuf) |
| 593 | microblaze_store_return_value (type, regcache, writebuf); |
| 594 | |
| 595 | return RETURN_VALUE_REGISTER_CONVENTION; |
| 596 | } |
| 597 | |
| 598 | static int |
| 599 | microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) |
| 600 | { |
| 601 | return (TYPE_LENGTH (type) == 16); |
| 602 | } |
| 603 | |
| 604 | static void |
| 605 | microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc) |
| 606 | { |
| 607 | regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc); |
| 608 | } |
| 609 | \f |
| 610 | static int dwarf2_to_reg_map[78] = |
| 611 | { 0 /* r0 */, 1 /* r1 */, 2 /* r2 */, 3 /* r3 */, /* 0- 3 */ |
| 612 | 4 /* r4 */, 5 /* r5 */, 6 /* r6 */, 7 /* r7 */, /* 4- 7 */ |
| 613 | 8 /* r8 */, 9 /* r9 */, 10 /* r10 */, 11 /* r11 */, /* 8-11 */ |
| 614 | 12 /* r12 */, 13 /* r13 */, 14 /* r14 */, 15 /* r15 */, /* 12-15 */ |
| 615 | 16 /* r16 */, 17 /* r17 */, 18 /* r18 */, 19 /* r19 */, /* 16-19 */ |
| 616 | 20 /* r20 */, 21 /* r21 */, 22 /* r22 */, 23 /* r23 */, /* 20-23 */ |
| 617 | 24 /* r24 */, 25 /* r25 */, 26 /* r26 */, 27 /* r27 */, /* 24-25 */ |
| 618 | 28 /* r28 */, 29 /* r29 */, 30 /* r30 */, 31 /* r31 */, /* 28-31 */ |
| 619 | -1 /* $f0 */, -1 /* $f1 */, -1 /* $f2 */, -1 /* $f3 */, /* 32-35 */ |
| 620 | -1 /* $f4 */, -1 /* $f5 */, -1 /* $f6 */, -1 /* $f7 */, /* 36-39 */ |
| 621 | -1 /* $f8 */, -1 /* $f9 */, -1 /* $f10 */, -1 /* $f11 */, /* 40-43 */ |
| 622 | -1 /* $f12 */, -1 /* $f13 */, -1 /* $f14 */, -1 /* $f15 */, /* 44-47 */ |
| 623 | -1 /* $f16 */, -1 /* $f17 */, -1 /* $f18 */, -1 /* $f19 */, /* 48-51 */ |
| 624 | -1 /* $f20 */, -1 /* $f21 */, -1 /* $f22 */, -1 /* $f23 */, /* 52-55 */ |
| 625 | -1 /* $f24 */, -1 /* $f25 */, -1 /* $f26 */, -1 /* $f27 */, /* 56-59 */ |
| 626 | -1 /* $f28 */, -1 /* $f29 */, -1 /* $f30 */, -1 /* $f31 */, /* 60-63 */ |
| 627 | -1 /* hi */, -1 /* lo */, -1 /* accum*/, 33 /* rmsr */, /* 64-67 */ |
| 628 | -1 /* $fcc1*/, -1 /* $fcc2*/, -1 /* $fcc3*/, -1 /* $fcc4*/, /* 68-71 */ |
| 629 | -1 /* $fcc5*/, -1 /* $fcc6*/, -1 /* $fcc7*/, -1 /* $ap */, /* 72-75 */ |
| 630 | -1 /* $rap */, -1 /* $frp */ /* 76-77 */ |
| 631 | }; |
| 632 | |
| 633 | static int |
| 634 | microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
| 635 | { |
| 636 | if (reg >= 0 && reg < sizeof (dwarf2_to_reg_map)) |
| 637 | return dwarf2_to_reg_map[reg]; |
| 638 | return -1; |
| 639 | } |
| 640 | |
| 641 | static void |
| 642 | microblaze_register_g_packet_guesses (struct gdbarch *gdbarch) |
| 643 | { |
| 644 | register_remote_g_packet_guess (gdbarch, |
| 645 | 4 * MICROBLAZE_NUM_CORE_REGS, |
| 646 | tdesc_microblaze); |
| 647 | |
| 648 | register_remote_g_packet_guess (gdbarch, |
| 649 | 4 * MICROBLAZE_NUM_REGS, |
| 650 | tdesc_microblaze_with_stack_protect); |
| 651 | } |
| 652 | |
| 653 | static struct gdbarch * |
| 654 | microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
| 655 | { |
| 656 | struct gdbarch_tdep *tdep; |
| 657 | struct gdbarch *gdbarch; |
| 658 | struct tdesc_arch_data *tdesc_data = NULL; |
| 659 | const struct target_desc *tdesc = info.target_desc; |
| 660 | |
| 661 | /* If there is already a candidate, use it. */ |
| 662 | arches = gdbarch_list_lookup_by_info (arches, &info); |
| 663 | if (arches != NULL) |
| 664 | return arches->gdbarch; |
| 665 | if (tdesc == NULL) |
| 666 | tdesc = tdesc_microblaze; |
| 667 | |
| 668 | /* Check any target description for validity. */ |
| 669 | if (tdesc_has_registers (tdesc)) |
| 670 | { |
| 671 | const struct tdesc_feature *feature; |
| 672 | int valid_p; |
| 673 | int i; |
| 674 | |
| 675 | feature = tdesc_find_feature (tdesc, |
| 676 | "org.gnu.gdb.microblaze.core"); |
| 677 | if (feature == NULL) |
| 678 | return NULL; |
| 679 | tdesc_data = tdesc_data_alloc (); |
| 680 | |
| 681 | valid_p = 1; |
| 682 | for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++) |
| 683 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
| 684 | microblaze_register_names[i]); |
| 685 | feature = tdesc_find_feature (tdesc, |
| 686 | "org.gnu.gdb.microblaze.stack-protect"); |
| 687 | if (feature != NULL) |
| 688 | { |
| 689 | valid_p = 1; |
| 690 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 691 | MICROBLAZE_SLR_REGNUM, |
| 692 | "rslr"); |
| 693 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 694 | MICROBLAZE_SHR_REGNUM, |
| 695 | "rshr"); |
| 696 | } |
| 697 | |
| 698 | if (!valid_p) |
| 699 | { |
| 700 | tdesc_data_cleanup (tdesc_data); |
| 701 | return NULL; |
| 702 | } |
| 703 | } |
| 704 | |
| 705 | /* Allocate space for the new architecture. */ |
| 706 | tdep = XCNEW (struct gdbarch_tdep); |
| 707 | gdbarch = gdbarch_alloc (&info, tdep); |
| 708 | |
| 709 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 710 | |
| 711 | set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS); |
| 712 | set_gdbarch_register_name (gdbarch, microblaze_register_name); |
| 713 | set_gdbarch_register_type (gdbarch, microblaze_register_type); |
| 714 | |
| 715 | /* Register numbers of various important registers. */ |
| 716 | set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); |
| 717 | set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); |
| 718 | |
| 719 | /* Map Dwarf2 registers to GDB registers. */ |
| 720 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum); |
| 721 | |
| 722 | /* Call dummy code. */ |
| 723 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
| 724 | |
| 725 | set_gdbarch_return_value (gdbarch, microblaze_return_value); |
| 726 | set_gdbarch_stabs_argument_has_addr |
| 727 | (gdbarch, microblaze_stabs_argument_has_addr); |
| 728 | |
| 729 | set_gdbarch_skip_prologue (gdbarch, microblaze_skip_prologue); |
| 730 | |
| 731 | /* Stack grows downward. */ |
| 732 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
| 733 | |
| 734 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
| 735 | microblaze_breakpoint::kind_from_pc); |
| 736 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, |
| 737 | microblaze_breakpoint::bp_from_kind); |
| 738 | |
| 739 | set_gdbarch_frame_args_skip (gdbarch, 8); |
| 740 | |
| 741 | set_gdbarch_write_pc (gdbarch, microblaze_write_pc); |
| 742 | |
| 743 | set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc); |
| 744 | |
| 745 | microblaze_register_g_packet_guesses (gdbarch); |
| 746 | |
| 747 | frame_base_set_default (gdbarch, µblaze_frame_base); |
| 748 | |
| 749 | /* Hook in ABI-specific overrides, if they have been registered. */ |
| 750 | gdbarch_init_osabi (info, gdbarch); |
| 751 | |
| 752 | /* Unwind the frame. */ |
| 753 | dwarf2_append_unwinders (gdbarch); |
| 754 | frame_unwind_append_unwinder (gdbarch, µblaze_frame_unwind); |
| 755 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
| 756 | if (tdesc_data != NULL) |
| 757 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
| 758 | |
| 759 | return gdbarch; |
| 760 | } |
| 761 | |
| 762 | void |
| 763 | _initialize_microblaze_tdep (void) |
| 764 | { |
| 765 | register_gdbarch_init (bfd_arch_microblaze, microblaze_gdbarch_init); |
| 766 | |
| 767 | initialize_tdesc_microblaze_with_stack_protect (); |
| 768 | initialize_tdesc_microblaze (); |
| 769 | /* Debug this files internals. */ |
| 770 | add_setshow_zuinteger_cmd ("microblaze", class_maintenance, |
| 771 | µblaze_debug_flag, _("\ |
| 772 | Set microblaze debugging."), _("\ |
| 773 | Show microblaze debugging."), _("\ |
| 774 | When non-zero, microblaze specific debugging is enabled."), |
| 775 | NULL, |
| 776 | NULL, |
| 777 | &setdebuglist, &showdebuglist); |
| 778 | |
| 779 | } |