| 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
| 2 | |
| 3 | Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007 |
| 4 | Free Software Foundation, Inc. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 2 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program; if not, write to the Free Software |
| 20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 21 | Boston, MA 02110-1301, USA. */ |
| 22 | |
| 23 | #include "defs.h" |
| 24 | #include "gdbcore.h" |
| 25 | #include "target.h" |
| 26 | #include "solib-svr4.h" |
| 27 | #include "osabi.h" |
| 28 | #include "mips-tdep.h" |
| 29 | #include "gdb_string.h" |
| 30 | #include "gdb_assert.h" |
| 31 | #include "frame.h" |
| 32 | #include "regcache.h" |
| 33 | #include "trad-frame.h" |
| 34 | #include "tramp-frame.h" |
| 35 | #include "gdbtypes.h" |
| 36 | #include "solib.h" |
| 37 | #include "symtab.h" |
| 38 | #include "mips-linux-tdep.h" |
| 39 | |
| 40 | /* Figure out where the longjmp will land. |
| 41 | We expect the first arg to be a pointer to the jmp_buf structure |
| 42 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land |
| 43 | at. The pc is copied into PC. This routine returns 1 on |
| 44 | success. */ |
| 45 | |
| 46 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
| 47 | #define MIPS_LINUX_JB_PC 0 |
| 48 | |
| 49 | static int |
| 50 | mips_linux_get_longjmp_target (CORE_ADDR *pc) |
| 51 | { |
| 52 | CORE_ADDR jb_addr; |
| 53 | char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT]; |
| 54 | |
| 55 | jb_addr = read_register (MIPS_A0_REGNUM); |
| 56 | |
| 57 | if (target_read_memory (jb_addr |
| 58 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE, |
| 59 | buf, TARGET_PTR_BIT / TARGET_CHAR_BIT)) |
| 60 | return 0; |
| 61 | |
| 62 | *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT); |
| 63 | |
| 64 | return 1; |
| 65 | } |
| 66 | |
| 67 | /* Transform the bits comprising a 32-bit register to the right size |
| 68 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
| 69 | is 8. */ |
| 70 | |
| 71 | static void |
| 72 | supply_32bit_reg (int regnum, const void *addr) |
| 73 | { |
| 74 | gdb_byte buf[MAX_REGISTER_SIZE]; |
| 75 | store_signed_integer (buf, register_size (current_gdbarch, regnum), |
| 76 | extract_signed_integer (addr, 4)); |
| 77 | regcache_raw_supply (current_regcache, regnum, buf); |
| 78 | } |
| 79 | |
| 80 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
| 81 | |
| 82 | void |
| 83 | mips_supply_gregset (mips_elf_gregset_t *gregsetp) |
| 84 | { |
| 85 | int regi; |
| 86 | mips_elf_greg_t *regp = *gregsetp; |
| 87 | char zerobuf[MAX_REGISTER_SIZE]; |
| 88 | |
| 89 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
| 90 | |
| 91 | for (regi = EF_REG0; regi <= EF_REG31; regi++) |
| 92 | supply_32bit_reg ((regi - EF_REG0), (char *)(regp + regi)); |
| 93 | |
| 94 | supply_32bit_reg (mips_regnum (current_gdbarch)->lo, |
| 95 | (char *)(regp + EF_LO)); |
| 96 | supply_32bit_reg (mips_regnum (current_gdbarch)->hi, |
| 97 | (char *)(regp + EF_HI)); |
| 98 | |
| 99 | supply_32bit_reg (mips_regnum (current_gdbarch)->pc, |
| 100 | (char *)(regp + EF_CP0_EPC)); |
| 101 | supply_32bit_reg (mips_regnum (current_gdbarch)->badvaddr, |
| 102 | (char *)(regp + EF_CP0_BADVADDR)); |
| 103 | supply_32bit_reg (MIPS_PS_REGNUM, (char *)(regp + EF_CP0_STATUS)); |
| 104 | supply_32bit_reg (mips_regnum (current_gdbarch)->cause, |
| 105 | (char *)(regp + EF_CP0_CAUSE)); |
| 106 | |
| 107 | /* Fill inaccessible registers with zero. */ |
| 108 | regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf); |
| 109 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
| 110 | regi < MIPS_LAST_EMBED_REGNUM; |
| 111 | regi++) |
| 112 | regcache_raw_supply (current_regcache, regi, zerobuf); |
| 113 | } |
| 114 | |
| 115 | /* Pack our registers (or one register) into an elf_gregset_t. */ |
| 116 | |
| 117 | void |
| 118 | mips_fill_gregset (mips_elf_gregset_t *gregsetp, int regno) |
| 119 | { |
| 120 | int regaddr, regi; |
| 121 | mips_elf_greg_t *regp = *gregsetp; |
| 122 | void *dst; |
| 123 | |
| 124 | if (regno == -1) |
| 125 | { |
| 126 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
| 127 | for (regi = 0; regi < 32; regi++) |
| 128 | mips_fill_gregset (gregsetp, regi); |
| 129 | mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo); |
| 130 | mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi); |
| 131 | mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc); |
| 132 | mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->badvaddr); |
| 133 | mips_fill_gregset (gregsetp, MIPS_PS_REGNUM); |
| 134 | mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->cause); |
| 135 | |
| 136 | return; |
| 137 | } |
| 138 | |
| 139 | if (regno < 32) |
| 140 | { |
| 141 | dst = regp + regno + EF_REG0; |
| 142 | regcache_raw_collect (current_regcache, regno, dst); |
| 143 | return; |
| 144 | } |
| 145 | |
| 146 | if (regno == mips_regnum (current_gdbarch)->lo) |
| 147 | regaddr = EF_LO; |
| 148 | else if (regno == mips_regnum (current_gdbarch)->hi) |
| 149 | regaddr = EF_HI; |
| 150 | else if (regno == mips_regnum (current_gdbarch)->pc) |
| 151 | regaddr = EF_CP0_EPC; |
| 152 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) |
| 153 | regaddr = EF_CP0_BADVADDR; |
| 154 | else if (regno == MIPS_PS_REGNUM) |
| 155 | regaddr = EF_CP0_STATUS; |
| 156 | else if (regno == mips_regnum (current_gdbarch)->cause) |
| 157 | regaddr = EF_CP0_CAUSE; |
| 158 | else |
| 159 | regaddr = -1; |
| 160 | |
| 161 | if (regaddr != -1) |
| 162 | { |
| 163 | dst = regp + regaddr; |
| 164 | regcache_raw_collect (current_regcache, regno, dst); |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | /* Likewise, unpack an elf_fpregset_t. */ |
| 169 | |
| 170 | void |
| 171 | mips_supply_fpregset (mips_elf_fpregset_t *fpregsetp) |
| 172 | { |
| 173 | int regi; |
| 174 | char zerobuf[MAX_REGISTER_SIZE]; |
| 175 | |
| 176 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
| 177 | |
| 178 | for (regi = 0; regi < 32; regi++) |
| 179 | regcache_raw_supply (current_regcache, FP0_REGNUM + regi, |
| 180 | (char *)(*fpregsetp + regi)); |
| 181 | |
| 182 | regcache_raw_supply (current_regcache, |
| 183 | mips_regnum (current_gdbarch)->fp_control_status, |
| 184 | (char *)(*fpregsetp + 32)); |
| 185 | |
| 186 | /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */ |
| 187 | regcache_raw_supply (current_regcache, |
| 188 | mips_regnum (current_gdbarch)->fp_implementation_revision, |
| 189 | zerobuf); |
| 190 | } |
| 191 | |
| 192 | /* Likewise, pack one or all floating point registers into an |
| 193 | elf_fpregset_t. */ |
| 194 | |
| 195 | void |
| 196 | mips_fill_fpregset (mips_elf_fpregset_t *fpregsetp, int regno) |
| 197 | { |
| 198 | char *from, *to; |
| 199 | |
| 200 | if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32)) |
| 201 | { |
| 202 | to = (char *) (*fpregsetp + regno - FP0_REGNUM); |
| 203 | regcache_raw_collect (current_regcache, regno, to); |
| 204 | } |
| 205 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
| 206 | { |
| 207 | to = (char *) (*fpregsetp + 32); |
| 208 | regcache_raw_collect (current_regcache, regno, to); |
| 209 | } |
| 210 | else if (regno == -1) |
| 211 | { |
| 212 | int regi; |
| 213 | |
| 214 | for (regi = 0; regi < 32; regi++) |
| 215 | mips_fill_fpregset (fpregsetp, FP0_REGNUM + regi); |
| 216 | mips_fill_fpregset (fpregsetp, |
| 217 | mips_regnum (current_gdbarch)->fp_control_status); |
| 218 | } |
| 219 | } |
| 220 | |
| 221 | /* Map gdb internal register number to ptrace ``address''. |
| 222 | These ``addresses'' are normally defined in <asm/ptrace.h>. */ |
| 223 | |
| 224 | static CORE_ADDR |
| 225 | mips_linux_register_addr (int regno, CORE_ADDR blockend) |
| 226 | { |
| 227 | int regaddr; |
| 228 | |
| 229 | if (regno < 0 || regno >= NUM_REGS) |
| 230 | error (_("Bogon register number %d."), regno); |
| 231 | |
| 232 | if (regno < 32) |
| 233 | regaddr = regno; |
| 234 | else if ((regno >= mips_regnum (current_gdbarch)->fp0) |
| 235 | && (regno < mips_regnum (current_gdbarch)->fp0 + 32)) |
| 236 | regaddr = FPR_BASE + (regno - mips_regnum (current_gdbarch)->fp0); |
| 237 | else if (regno == mips_regnum (current_gdbarch)->pc) |
| 238 | regaddr = PC; |
| 239 | else if (regno == mips_regnum (current_gdbarch)->cause) |
| 240 | regaddr = CAUSE; |
| 241 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) |
| 242 | regaddr = BADVADDR; |
| 243 | else if (regno == mips_regnum (current_gdbarch)->lo) |
| 244 | regaddr = MMLO; |
| 245 | else if (regno == mips_regnum (current_gdbarch)->hi) |
| 246 | regaddr = MMHI; |
| 247 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
| 248 | regaddr = FPC_CSR; |
| 249 | else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision) |
| 250 | regaddr = FPC_EIR; |
| 251 | else |
| 252 | error (_("Unknowable register number %d."), regno); |
| 253 | |
| 254 | return regaddr; |
| 255 | } |
| 256 | |
| 257 | /* Support for 64-bit ABIs. */ |
| 258 | |
| 259 | /* Figure out where the longjmp will land. |
| 260 | We expect the first arg to be a pointer to the jmp_buf structure |
| 261 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land |
| 262 | at. The pc is copied into PC. This routine returns 1 on |
| 263 | success. */ |
| 264 | |
| 265 | /* Details about jmp_buf. */ |
| 266 | |
| 267 | #define MIPS64_LINUX_JB_PC 0 |
| 268 | |
| 269 | static int |
| 270 | mips64_linux_get_longjmp_target (CORE_ADDR *pc) |
| 271 | { |
| 272 | CORE_ADDR jb_addr; |
| 273 | void *buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT); |
| 274 | int element_size = TARGET_PTR_BIT == 32 ? 4 : 8; |
| 275 | |
| 276 | jb_addr = read_register (MIPS_A0_REGNUM); |
| 277 | |
| 278 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, |
| 279 | buf, TARGET_PTR_BIT / TARGET_CHAR_BIT)) |
| 280 | return 0; |
| 281 | |
| 282 | *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT); |
| 283 | |
| 284 | return 1; |
| 285 | } |
| 286 | |
| 287 | /* Register set support functions. These operate on standard 64-bit |
| 288 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit |
| 289 | target will still use the 64-bit format for PTRACE_GETREGS. */ |
| 290 | |
| 291 | /* Supply a 64-bit register. */ |
| 292 | |
| 293 | void |
| 294 | supply_64bit_reg (int regnum, const gdb_byte *buf) |
| 295 | { |
| 296 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
| 297 | && register_size (current_gdbarch, regnum) == 4) |
| 298 | regcache_raw_supply (current_regcache, regnum, buf + 4); |
| 299 | else |
| 300 | regcache_raw_supply (current_regcache, regnum, buf); |
| 301 | } |
| 302 | |
| 303 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ |
| 304 | |
| 305 | void |
| 306 | mips64_supply_gregset (mips64_elf_gregset_t *gregsetp) |
| 307 | { |
| 308 | int regi; |
| 309 | mips64_elf_greg_t *regp = *gregsetp; |
| 310 | gdb_byte zerobuf[MAX_REGISTER_SIZE]; |
| 311 | |
| 312 | memset (zerobuf, 0, MAX_REGISTER_SIZE); |
| 313 | |
| 314 | for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++) |
| 315 | supply_64bit_reg (regi - MIPS64_EF_REG0, (gdb_byte *)(regp + regi)); |
| 316 | |
| 317 | supply_64bit_reg (mips_regnum (current_gdbarch)->lo, |
| 318 | (gdb_byte *) (regp + MIPS64_EF_LO)); |
| 319 | supply_64bit_reg (mips_regnum (current_gdbarch)->hi, |
| 320 | (gdb_byte *) (regp + MIPS64_EF_HI)); |
| 321 | |
| 322 | supply_64bit_reg (mips_regnum (current_gdbarch)->pc, |
| 323 | (gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); |
| 324 | supply_64bit_reg (mips_regnum (current_gdbarch)->badvaddr, |
| 325 | (gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); |
| 326 | supply_64bit_reg (MIPS_PS_REGNUM, |
| 327 | (gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); |
| 328 | supply_64bit_reg (mips_regnum (current_gdbarch)->cause, |
| 329 | (gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); |
| 330 | |
| 331 | /* Fill inaccessible registers with zero. */ |
| 332 | regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf); |
| 333 | for (regi = MIPS_FIRST_EMBED_REGNUM; |
| 334 | regi < MIPS_LAST_EMBED_REGNUM; |
| 335 | regi++) |
| 336 | regcache_raw_supply (current_regcache, regi, zerobuf); |
| 337 | } |
| 338 | |
| 339 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
| 340 | |
| 341 | void |
| 342 | mips64_fill_gregset (mips64_elf_gregset_t *gregsetp, int regno) |
| 343 | { |
| 344 | int regaddr, regi; |
| 345 | mips64_elf_greg_t *regp = *gregsetp; |
| 346 | void *src, *dst; |
| 347 | |
| 348 | if (regno == -1) |
| 349 | { |
| 350 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); |
| 351 | for (regi = 0; regi < 32; regi++) |
| 352 | mips64_fill_gregset (gregsetp, regi); |
| 353 | mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo); |
| 354 | mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi); |
| 355 | mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc); |
| 356 | mips64_fill_gregset (gregsetp, |
| 357 | mips_regnum (current_gdbarch)->badvaddr); |
| 358 | mips64_fill_gregset (gregsetp, MIPS_PS_REGNUM); |
| 359 | mips64_fill_gregset (gregsetp, |
| 360 | mips_regnum (current_gdbarch)->cause); |
| 361 | |
| 362 | return; |
| 363 | } |
| 364 | |
| 365 | if (regno < 32) |
| 366 | regaddr = regno + MIPS64_EF_REG0; |
| 367 | else if (regno == mips_regnum (current_gdbarch)->lo) |
| 368 | regaddr = MIPS64_EF_LO; |
| 369 | else if (regno == mips_regnum (current_gdbarch)->hi) |
| 370 | regaddr = MIPS64_EF_HI; |
| 371 | else if (regno == mips_regnum (current_gdbarch)->pc) |
| 372 | regaddr = MIPS64_EF_CP0_EPC; |
| 373 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) |
| 374 | regaddr = MIPS64_EF_CP0_BADVADDR; |
| 375 | else if (regno == MIPS_PS_REGNUM) |
| 376 | regaddr = MIPS64_EF_CP0_STATUS; |
| 377 | else if (regno == mips_regnum (current_gdbarch)->cause) |
| 378 | regaddr = MIPS64_EF_CP0_CAUSE; |
| 379 | else |
| 380 | regaddr = -1; |
| 381 | |
| 382 | if (regaddr != -1) |
| 383 | { |
| 384 | gdb_byte buf[MAX_REGISTER_SIZE]; |
| 385 | LONGEST val; |
| 386 | |
| 387 | regcache_raw_collect (current_regcache, regno, buf); |
| 388 | val = extract_signed_integer (buf, |
| 389 | register_size (current_gdbarch, regno)); |
| 390 | dst = regp + regaddr; |
| 391 | store_signed_integer (dst, 8, val); |
| 392 | } |
| 393 | } |
| 394 | |
| 395 | /* Likewise, unpack an elf_fpregset_t. */ |
| 396 | |
| 397 | void |
| 398 | mips64_supply_fpregset (mips64_elf_fpregset_t *fpregsetp) |
| 399 | { |
| 400 | int regi; |
| 401 | |
| 402 | /* See mips_linux_o32_sigframe_init for a description of the |
| 403 | peculiar FP register layout. */ |
| 404 | if (register_size (current_gdbarch, FP0_REGNUM) == 4) |
| 405 | for (regi = 0; regi < 32; regi++) |
| 406 | { |
| 407 | gdb_byte *reg_ptr = (gdb_byte *) (*fpregsetp + (regi & ~1)); |
| 408 | if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1)) |
| 409 | reg_ptr += 4; |
| 410 | regcache_raw_supply (current_regcache, FP0_REGNUM + regi, reg_ptr); |
| 411 | } |
| 412 | else |
| 413 | for (regi = 0; regi < 32; regi++) |
| 414 | regcache_raw_supply (current_regcache, FP0_REGNUM + regi, |
| 415 | (char *)(*fpregsetp + regi)); |
| 416 | |
| 417 | supply_32bit_reg (mips_regnum (current_gdbarch)->fp_control_status, |
| 418 | (gdb_byte *)(*fpregsetp + 32)); |
| 419 | |
| 420 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't |
| 421 | include it - but the result of PTRACE_GETFPREGS does. The best we |
| 422 | can do is to assume that its value is present. */ |
| 423 | supply_32bit_reg (mips_regnum (current_gdbarch)->fp_implementation_revision, |
| 424 | (gdb_byte *)(*fpregsetp + 32) + 4); |
| 425 | } |
| 426 | |
| 427 | /* Likewise, pack one or all floating point registers into an |
| 428 | elf_fpregset_t. */ |
| 429 | |
| 430 | void |
| 431 | mips64_fill_fpregset (mips64_elf_fpregset_t *fpregsetp, int regno) |
| 432 | { |
| 433 | gdb_byte *to; |
| 434 | |
| 435 | if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32)) |
| 436 | { |
| 437 | /* See mips_linux_o32_sigframe_init for a description of the |
| 438 | peculiar FP register layout. */ |
| 439 | if (register_size (current_gdbarch, regno) == 4) |
| 440 | { |
| 441 | int regi = regno - FP0_REGNUM; |
| 442 | |
| 443 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); |
| 444 | if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1)) |
| 445 | to += 4; |
| 446 | regcache_raw_collect (current_regcache, regno, to); |
| 447 | } |
| 448 | else |
| 449 | { |
| 450 | to = (gdb_byte *) (*fpregsetp + regno - FP0_REGNUM); |
| 451 | regcache_raw_collect (current_regcache, regno, to); |
| 452 | } |
| 453 | } |
| 454 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
| 455 | { |
| 456 | gdb_byte buf[MAX_REGISTER_SIZE]; |
| 457 | LONGEST val; |
| 458 | |
| 459 | regcache_raw_collect (current_regcache, regno, buf); |
| 460 | val = extract_signed_integer (buf, |
| 461 | register_size (current_gdbarch, regno)); |
| 462 | to = (gdb_byte *) (*fpregsetp + 32); |
| 463 | store_signed_integer (to, 4, val); |
| 464 | } |
| 465 | else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision) |
| 466 | { |
| 467 | gdb_byte buf[MAX_REGISTER_SIZE]; |
| 468 | LONGEST val; |
| 469 | |
| 470 | regcache_raw_collect (current_regcache, regno, buf); |
| 471 | val = extract_signed_integer (buf, |
| 472 | register_size (current_gdbarch, regno)); |
| 473 | to = (gdb_byte *) (*fpregsetp + 32) + 4; |
| 474 | store_signed_integer (to, 4, val); |
| 475 | } |
| 476 | else if (regno == -1) |
| 477 | { |
| 478 | int regi; |
| 479 | |
| 480 | for (regi = 0; regi < 32; regi++) |
| 481 | mips64_fill_fpregset (fpregsetp, FP0_REGNUM + regi); |
| 482 | mips64_fill_fpregset (fpregsetp, |
| 483 | mips_regnum (current_gdbarch)->fp_control_status); |
| 484 | mips64_fill_fpregset (fpregsetp, (mips_regnum (current_gdbarch) |
| 485 | ->fp_implementation_revision)); |
| 486 | } |
| 487 | } |
| 488 | |
| 489 | |
| 490 | /* Map gdb internal register number to ptrace ``address''. |
| 491 | These ``addresses'' are normally defined in <asm/ptrace.h>. */ |
| 492 | |
| 493 | static CORE_ADDR |
| 494 | mips64_linux_register_addr (int regno, CORE_ADDR blockend) |
| 495 | { |
| 496 | int regaddr; |
| 497 | |
| 498 | if (regno < 0 || regno >= NUM_REGS) |
| 499 | error (_("Bogon register number %d."), regno); |
| 500 | |
| 501 | if (regno < 32) |
| 502 | regaddr = regno; |
| 503 | else if ((regno >= mips_regnum (current_gdbarch)->fp0) |
| 504 | && (regno < mips_regnum (current_gdbarch)->fp0 + 32)) |
| 505 | regaddr = MIPS64_FPR_BASE + (regno - FP0_REGNUM); |
| 506 | else if (regno == mips_regnum (current_gdbarch)->pc) |
| 507 | regaddr = MIPS64_PC; |
| 508 | else if (regno == mips_regnum (current_gdbarch)->cause) |
| 509 | regaddr = MIPS64_CAUSE; |
| 510 | else if (regno == mips_regnum (current_gdbarch)->badvaddr) |
| 511 | regaddr = MIPS64_BADVADDR; |
| 512 | else if (regno == mips_regnum (current_gdbarch)->lo) |
| 513 | regaddr = MIPS64_MMLO; |
| 514 | else if (regno == mips_regnum (current_gdbarch)->hi) |
| 515 | regaddr = MIPS64_MMHI; |
| 516 | else if (regno == mips_regnum (current_gdbarch)->fp_control_status) |
| 517 | regaddr = MIPS64_FPC_CSR; |
| 518 | else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision) |
| 519 | regaddr = MIPS64_FPC_EIR; |
| 520 | else |
| 521 | error (_("Unknowable register number %d."), regno); |
| 522 | |
| 523 | return regaddr; |
| 524 | } |
| 525 | |
| 526 | /* Use a local version of this function to get the correct types for |
| 527 | regsets, until multi-arch core support is ready. */ |
| 528 | |
| 529 | static void |
| 530 | fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, |
| 531 | int which, CORE_ADDR reg_addr) |
| 532 | { |
| 533 | mips_elf_gregset_t gregset; |
| 534 | mips_elf_fpregset_t fpregset; |
| 535 | mips64_elf_gregset_t gregset64; |
| 536 | mips64_elf_fpregset_t fpregset64; |
| 537 | |
| 538 | if (which == 0) |
| 539 | { |
| 540 | if (core_reg_size == sizeof (gregset)) |
| 541 | { |
| 542 | memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset)); |
| 543 | mips_supply_gregset (&gregset); |
| 544 | } |
| 545 | else if (core_reg_size == sizeof (gregset64)) |
| 546 | { |
| 547 | memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64)); |
| 548 | mips64_supply_gregset (&gregset64); |
| 549 | } |
| 550 | else |
| 551 | { |
| 552 | warning (_("wrong size gregset struct in core file")); |
| 553 | } |
| 554 | } |
| 555 | else if (which == 2) |
| 556 | { |
| 557 | if (core_reg_size == sizeof (fpregset)) |
| 558 | { |
| 559 | memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset)); |
| 560 | mips_supply_fpregset (&fpregset); |
| 561 | } |
| 562 | else if (core_reg_size == sizeof (fpregset64)) |
| 563 | { |
| 564 | memcpy ((char *) &fpregset64, core_reg_sect, |
| 565 | sizeof (fpregset64)); |
| 566 | mips64_supply_fpregset (&fpregset64); |
| 567 | } |
| 568 | else |
| 569 | { |
| 570 | warning (_("wrong size fpregset struct in core file")); |
| 571 | } |
| 572 | } |
| 573 | } |
| 574 | |
| 575 | /* Register that we are able to handle ELF file formats using standard |
| 576 | procfs "regset" structures. */ |
| 577 | |
| 578 | static struct core_fns regset_core_fns = |
| 579 | { |
| 580 | bfd_target_elf_flavour, /* core_flavour */ |
| 581 | default_check_format, /* check_format */ |
| 582 | default_core_sniffer, /* core_sniffer */ |
| 583 | fetch_core_registers, /* core_read_registers */ |
| 584 | NULL /* next */ |
| 585 | }; |
| 586 | |
| 587 | /* Handle for obtaining pointer to the current register_addr() |
| 588 | function for a given architecture. */ |
| 589 | static struct gdbarch_data *register_addr_data; |
| 590 | |
| 591 | CORE_ADDR |
| 592 | register_addr (int regno, CORE_ADDR blockend) |
| 593 | { |
| 594 | CORE_ADDR (*register_addr_ptr) (int, CORE_ADDR) = |
| 595 | gdbarch_data (current_gdbarch, register_addr_data); |
| 596 | |
| 597 | gdb_assert (register_addr_ptr != 0); |
| 598 | |
| 599 | return register_addr_ptr (regno, blockend); |
| 600 | } |
| 601 | |
| 602 | static void |
| 603 | set_mips_linux_register_addr (struct gdbarch *gdbarch, |
| 604 | CORE_ADDR (*register_addr_ptr) (int, |
| 605 | CORE_ADDR)) |
| 606 | { |
| 607 | deprecated_set_gdbarch_data (gdbarch, register_addr_data, |
| 608 | register_addr_ptr); |
| 609 | } |
| 610 | |
| 611 | static void * |
| 612 | init_register_addr_data (struct gdbarch *gdbarch) |
| 613 | { |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
| 618 | Because they aren't in the .plt section, we pattern-match on the |
| 619 | code generated by GNU ld. They look like this: |
| 620 | |
| 621 | lw t9,0x8010(gp) |
| 622 | addu t7,ra |
| 623 | jalr t9,ra |
| 624 | addiu t8,zero,INDEX |
| 625 | |
| 626 | (with the appropriate doubleword instructions for N64). Also |
| 627 | return the dynamic symbol index used in the last instruction. */ |
| 628 | |
| 629 | static int |
| 630 | mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name) |
| 631 | { |
| 632 | unsigned char buf[28], *p; |
| 633 | ULONGEST insn, insn1; |
| 634 | int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64); |
| 635 | |
| 636 | read_memory (pc - 12, buf, 28); |
| 637 | |
| 638 | if (n64) |
| 639 | { |
| 640 | /* ld t9,0x8010(gp) */ |
| 641 | insn1 = 0xdf998010; |
| 642 | } |
| 643 | else |
| 644 | { |
| 645 | /* lw t9,0x8010(gp) */ |
| 646 | insn1 = 0x8f998010; |
| 647 | } |
| 648 | |
| 649 | p = buf + 12; |
| 650 | while (p >= buf) |
| 651 | { |
| 652 | insn = extract_unsigned_integer (p, 4); |
| 653 | if (insn == insn1) |
| 654 | break; |
| 655 | p -= 4; |
| 656 | } |
| 657 | if (p < buf) |
| 658 | return 0; |
| 659 | |
| 660 | insn = extract_unsigned_integer (p + 4, 4); |
| 661 | if (n64) |
| 662 | { |
| 663 | /* daddu t7,ra */ |
| 664 | if (insn != 0x03e0782d) |
| 665 | return 0; |
| 666 | } |
| 667 | else |
| 668 | { |
| 669 | /* addu t7,ra */ |
| 670 | if (insn != 0x03e07821) |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | insn = extract_unsigned_integer (p + 8, 4); |
| 675 | /* jalr t9,ra */ |
| 676 | if (insn != 0x0320f809) |
| 677 | return 0; |
| 678 | |
| 679 | insn = extract_unsigned_integer (p + 12, 4); |
| 680 | if (n64) |
| 681 | { |
| 682 | /* daddiu t8,zero,0 */ |
| 683 | if ((insn & 0xffff0000) != 0x64180000) |
| 684 | return 0; |
| 685 | } |
| 686 | else |
| 687 | { |
| 688 | /* addiu t8,zero,0 */ |
| 689 | if ((insn & 0xffff0000) != 0x24180000) |
| 690 | return 0; |
| 691 | } |
| 692 | |
| 693 | return (insn & 0xffff); |
| 694 | } |
| 695 | |
| 696 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
| 697 | code or to a stub. */ |
| 698 | |
| 699 | int |
| 700 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
| 701 | { |
| 702 | /* Check whether PC is in the dynamic linker. This also checks |
| 703 | whether it is in the .plt section, which MIPS does not use. */ |
| 704 | if (in_solib_dynsym_resolve_code (pc)) |
| 705 | return 1; |
| 706 | |
| 707 | /* Pattern match for the stub. It would be nice if there were a |
| 708 | more efficient way to avoid this check. */ |
| 709 | if (mips_linux_in_dynsym_stub (pc, NULL)) |
| 710 | return 1; |
| 711 | |
| 712 | return 0; |
| 713 | } |
| 714 | |
| 715 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, |
| 716 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc |
| 717 | implementation of this triggers at "fixup" from the same objfile as |
| 718 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
| 719 | "__dl_runtime_resolve" directly. An unresolved PLT entry will |
| 720 | point to _dl_runtime_resolve, which will first call |
| 721 | __dl_runtime_resolve, and then pass control to the resolved |
| 722 | function. */ |
| 723 | |
| 724 | static CORE_ADDR |
| 725 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 726 | { |
| 727 | struct minimal_symbol *resolver; |
| 728 | |
| 729 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); |
| 730 | |
| 731 | if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc) |
| 732 | return frame_pc_unwind (get_current_frame ()); |
| 733 | |
| 734 | return 0; |
| 735 | } |
| 736 | |
| 737 | /* Signal trampoline support. There are four supported layouts for a |
| 738 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and |
| 739 | n64 rt_sigframe. We handle them all independently; not the most |
| 740 | efficient way, but simplest. First, declare all the unwinders. */ |
| 741 | |
| 742 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, |
| 743 | struct frame_info *next_frame, |
| 744 | struct trad_frame_cache *this_cache, |
| 745 | CORE_ADDR func); |
| 746 | |
| 747 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, |
| 748 | struct frame_info *next_frame, |
| 749 | struct trad_frame_cache *this_cache, |
| 750 | CORE_ADDR func); |
| 751 | |
| 752 | #define MIPS_NR_LINUX 4000 |
| 753 | #define MIPS_NR_N64_LINUX 5000 |
| 754 | #define MIPS_NR_N32_LINUX 6000 |
| 755 | |
| 756 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 |
| 757 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 |
| 758 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 |
| 759 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 |
| 760 | |
| 761 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn |
| 762 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn |
| 763 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn |
| 764 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn |
| 765 | #define MIPS_INST_SYSCALL 0x0000000c |
| 766 | |
| 767 | static const struct tramp_frame mips_linux_o32_sigframe = { |
| 768 | SIGTRAMP_FRAME, |
| 769 | 4, |
| 770 | { |
| 771 | { MIPS_INST_LI_V0_SIGRETURN, -1 }, |
| 772 | { MIPS_INST_SYSCALL, -1 }, |
| 773 | { TRAMP_SENTINEL_INSN, -1 } |
| 774 | }, |
| 775 | mips_linux_o32_sigframe_init |
| 776 | }; |
| 777 | |
| 778 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
| 779 | SIGTRAMP_FRAME, |
| 780 | 4, |
| 781 | { |
| 782 | { MIPS_INST_LI_V0_RT_SIGRETURN, -1 }, |
| 783 | { MIPS_INST_SYSCALL, -1 }, |
| 784 | { TRAMP_SENTINEL_INSN, -1 } }, |
| 785 | mips_linux_o32_sigframe_init |
| 786 | }; |
| 787 | |
| 788 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
| 789 | SIGTRAMP_FRAME, |
| 790 | 4, |
| 791 | { |
| 792 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 }, |
| 793 | { MIPS_INST_SYSCALL, -1 }, |
| 794 | { TRAMP_SENTINEL_INSN, -1 } |
| 795 | }, |
| 796 | mips_linux_n32n64_sigframe_init |
| 797 | }; |
| 798 | |
| 799 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
| 800 | SIGTRAMP_FRAME, |
| 801 | 4, |
| 802 | { |
| 803 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, -1 }, |
| 804 | { MIPS_INST_SYSCALL, -1 }, |
| 805 | { TRAMP_SENTINEL_INSN, -1 } |
| 806 | }, |
| 807 | mips_linux_n32n64_sigframe_init |
| 808 | }; |
| 809 | |
| 810 | /* *INDENT-OFF* */ |
| 811 | /* The unwinder for o32 signal frames. The legacy structures look |
| 812 | like this: |
| 813 | |
| 814 | struct sigframe { |
| 815 | u32 sf_ass[4]; [argument save space for o32] |
| 816 | u32 sf_code[2]; [signal trampoline] |
| 817 | struct sigcontext sf_sc; |
| 818 | sigset_t sf_mask; |
| 819 | }; |
| 820 | |
| 821 | struct sigcontext { |
| 822 | unsigned int sc_regmask; [Unused] |
| 823 | unsigned int sc_status; |
| 824 | unsigned long long sc_pc; |
| 825 | unsigned long long sc_regs[32]; |
| 826 | unsigned long long sc_fpregs[32]; |
| 827 | unsigned int sc_ownedfp; |
| 828 | unsigned int sc_fpc_csr; |
| 829 | unsigned int sc_fpc_eir; [Unused] |
| 830 | unsigned int sc_used_math; |
| 831 | unsigned int sc_ssflags; [Unused] |
| 832 | [Alignment hole of four bytes] |
| 833 | unsigned long long sc_mdhi; |
| 834 | unsigned long long sc_mdlo; |
| 835 | |
| 836 | unsigned int sc_cause; [Unused] |
| 837 | unsigned int sc_badvaddr; [Unused] |
| 838 | |
| 839 | unsigned long sc_sigset[4]; [kernel's sigset_t] |
| 840 | }; |
| 841 | |
| 842 | The RT signal frames look like this: |
| 843 | |
| 844 | struct rt_sigframe { |
| 845 | u32 rs_ass[4]; [argument save space for o32] |
| 846 | u32 rs_code[2] [signal trampoline] |
| 847 | struct siginfo rs_info; |
| 848 | struct ucontext rs_uc; |
| 849 | }; |
| 850 | |
| 851 | struct ucontext { |
| 852 | unsigned long uc_flags; |
| 853 | struct ucontext *uc_link; |
| 854 | stack_t uc_stack; |
| 855 | [Alignment hole of four bytes] |
| 856 | struct sigcontext uc_mcontext; |
| 857 | sigset_t uc_sigmask; |
| 858 | }; */ |
| 859 | /* *INDENT-ON* */ |
| 860 | |
| 861 | #define SIGFRAME_CODE_OFFSET (4 * 4) |
| 862 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) |
| 863 | |
| 864 | #define RTSIGFRAME_SIGINFO_SIZE 128 |
| 865 | #define STACK_T_SIZE (3 * 4) |
| 866 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) |
| 867 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ |
| 868 | + RTSIGFRAME_SIGINFO_SIZE \ |
| 869 | + UCONTEXT_SIGCONTEXT_OFFSET) |
| 870 | |
| 871 | #define SIGCONTEXT_PC (1 * 8) |
| 872 | #define SIGCONTEXT_REGS (2 * 8) |
| 873 | #define SIGCONTEXT_FPREGS (34 * 8) |
| 874 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) |
| 875 | #define SIGCONTEXT_HI (69 * 8) |
| 876 | #define SIGCONTEXT_LO (70 * 8) |
| 877 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) |
| 878 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) |
| 879 | |
| 880 | #define SIGCONTEXT_REG_SIZE 8 |
| 881 | |
| 882 | static void |
| 883 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, |
| 884 | struct frame_info *next_frame, |
| 885 | struct trad_frame_cache *this_cache, |
| 886 | CORE_ADDR func) |
| 887 | { |
| 888 | int ireg, reg_position; |
| 889 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; |
| 890 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); |
| 891 | CORE_ADDR regs_base; |
| 892 | |
| 893 | if (self == &mips_linux_o32_sigframe) |
| 894 | sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET; |
| 895 | else |
| 896 | sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET; |
| 897 | |
| 898 | /* I'm not proud of this hack. Eventually we will have the |
| 899 | infrastructure to indicate the size of saved registers on a |
| 900 | per-frame basis, but right now we don't; the kernel saves eight |
| 901 | bytes but we only want four. Use regs_base to access any |
| 902 | 64-bit fields. */ |
| 903 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
| 904 | regs_base = sigcontext_base + 4; |
| 905 | else |
| 906 | regs_base = sigcontext_base; |
| 907 | |
| 908 | #if 0 |
| 909 | trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS, |
| 910 | regs_base + SIGCONTEXT_REGS); |
| 911 | #endif |
| 912 | |
| 913 | for (ireg = 1; ireg < 32; ireg++) |
| 914 | trad_frame_set_reg_addr (this_cache, |
| 915 | ireg + MIPS_ZERO_REGNUM + NUM_REGS, |
| 916 | regs_base + SIGCONTEXT_REGS |
| 917 | + ireg * SIGCONTEXT_REG_SIZE); |
| 918 | |
| 919 | /* The way that floating point registers are saved, unfortunately, |
| 920 | depends on the architecture the kernel is built for. For the r3000 and |
| 921 | tx39, four bytes of each register are at the beginning of each of the |
| 922 | 32 eight byte slots. For everything else, the registers are saved |
| 923 | using double precision; only the even-numbered slots are initialized, |
| 924 | and the high bits are the odd-numbered register. Assume the latter |
| 925 | layout, since we can't tell, and it's much more common. Which bits are |
| 926 | the "high" bits depends on endianness. */ |
| 927 | for (ireg = 0; ireg < 32; ireg++) |
| 928 | if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (ireg & 1)) |
| 929 | trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS, |
| 930 | sigcontext_base + SIGCONTEXT_FPREGS + 4 |
| 931 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); |
| 932 | else |
| 933 | trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS, |
| 934 | sigcontext_base + SIGCONTEXT_FPREGS |
| 935 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE); |
| 936 | |
| 937 | trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS, |
| 938 | regs_base + SIGCONTEXT_PC); |
| 939 | |
| 940 | trad_frame_set_reg_addr (this_cache, |
| 941 | regs->fp_control_status + NUM_REGS, |
| 942 | sigcontext_base + SIGCONTEXT_FPCSR); |
| 943 | trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS, |
| 944 | regs_base + SIGCONTEXT_HI); |
| 945 | trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS, |
| 946 | regs_base + SIGCONTEXT_LO); |
| 947 | trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS, |
| 948 | sigcontext_base + SIGCONTEXT_CAUSE); |
| 949 | trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS, |
| 950 | sigcontext_base + SIGCONTEXT_BADVADDR); |
| 951 | |
| 952 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ |
| 953 | trad_frame_set_id (this_cache, |
| 954 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
| 955 | func)); |
| 956 | } |
| 957 | |
| 958 | /* *INDENT-OFF* */ |
| 959 | /* For N32/N64 things look different. There is no non-rt signal frame. |
| 960 | |
| 961 | struct rt_sigframe_n32 { |
| 962 | u32 rs_ass[4]; [ argument save space for o32 ] |
| 963 | u32 rs_code[2]; [ signal trampoline ] |
| 964 | struct siginfo rs_info; |
| 965 | struct ucontextn32 rs_uc; |
| 966 | }; |
| 967 | |
| 968 | struct ucontextn32 { |
| 969 | u32 uc_flags; |
| 970 | s32 uc_link; |
| 971 | stack32_t uc_stack; |
| 972 | struct sigcontext uc_mcontext; |
| 973 | sigset_t uc_sigmask; [ mask last for extensibility ] |
| 974 | }; |
| 975 | |
| 976 | struct rt_sigframe_n32 { |
| 977 | u32 rs_ass[4]; [ argument save space for o32 ] |
| 978 | u32 rs_code[2]; [ signal trampoline ] |
| 979 | struct siginfo rs_info; |
| 980 | struct ucontext rs_uc; |
| 981 | }; |
| 982 | |
| 983 | struct ucontext { |
| 984 | unsigned long uc_flags; |
| 985 | struct ucontext *uc_link; |
| 986 | stack_t uc_stack; |
| 987 | struct sigcontext uc_mcontext; |
| 988 | sigset_t uc_sigmask; [ mask last for extensibility ] |
| 989 | }; |
| 990 | |
| 991 | And the sigcontext is different (this is for both n32 and n64): |
| 992 | |
| 993 | struct sigcontext { |
| 994 | unsigned long long sc_regs[32]; |
| 995 | unsigned long long sc_fpregs[32]; |
| 996 | unsigned long long sc_mdhi; |
| 997 | unsigned long long sc_mdlo; |
| 998 | unsigned long long sc_pc; |
| 999 | unsigned int sc_status; |
| 1000 | unsigned int sc_fpc_csr; |
| 1001 | unsigned int sc_fpc_eir; |
| 1002 | unsigned int sc_used_math; |
| 1003 | unsigned int sc_cause; |
| 1004 | unsigned int sc_badvaddr; |
| 1005 | }; */ |
| 1006 | /* *INDENT-ON* */ |
| 1007 | |
| 1008 | #define N32_STACK_T_SIZE STACK_T_SIZE |
| 1009 | #define N64_STACK_T_SIZE (2 * 8 + 4) |
| 1010 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) |
| 1011 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) |
| 1012 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ |
| 1013 | + RTSIGFRAME_SIGINFO_SIZE \ |
| 1014 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) |
| 1015 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ |
| 1016 | + RTSIGFRAME_SIGINFO_SIZE \ |
| 1017 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) |
| 1018 | |
| 1019 | #define N64_SIGCONTEXT_REGS (0 * 8) |
| 1020 | #define N64_SIGCONTEXT_FPREGS (32 * 8) |
| 1021 | #define N64_SIGCONTEXT_HI (64 * 8) |
| 1022 | #define N64_SIGCONTEXT_LO (65 * 8) |
| 1023 | #define N64_SIGCONTEXT_PC (66 * 8) |
| 1024 | #define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4) |
| 1025 | #define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4) |
| 1026 | #define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4) |
| 1027 | #define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4) |
| 1028 | |
| 1029 | #define N64_SIGCONTEXT_REG_SIZE 8 |
| 1030 | |
| 1031 | static void |
| 1032 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, |
| 1033 | struct frame_info *next_frame, |
| 1034 | struct trad_frame_cache *this_cache, |
| 1035 | CORE_ADDR func) |
| 1036 | { |
| 1037 | int ireg, reg_position; |
| 1038 | CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; |
| 1039 | const struct mips_regnum *regs = mips_regnum (current_gdbarch); |
| 1040 | |
| 1041 | if (self == &mips_linux_n32_rt_sigframe) |
| 1042 | sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET; |
| 1043 | else |
| 1044 | sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET; |
| 1045 | |
| 1046 | #if 0 |
| 1047 | trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS, |
| 1048 | sigcontext_base + N64_SIGCONTEXT_REGS); |
| 1049 | #endif |
| 1050 | |
| 1051 | for (ireg = 1; ireg < 32; ireg++) |
| 1052 | trad_frame_set_reg_addr (this_cache, |
| 1053 | ireg + MIPS_ZERO_REGNUM + NUM_REGS, |
| 1054 | sigcontext_base + N64_SIGCONTEXT_REGS |
| 1055 | + ireg * N64_SIGCONTEXT_REG_SIZE); |
| 1056 | |
| 1057 | for (ireg = 0; ireg < 32; ireg++) |
| 1058 | trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS, |
| 1059 | sigcontext_base + N64_SIGCONTEXT_FPREGS |
| 1060 | + ireg * N64_SIGCONTEXT_REG_SIZE); |
| 1061 | |
| 1062 | trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS, |
| 1063 | sigcontext_base + N64_SIGCONTEXT_PC); |
| 1064 | |
| 1065 | trad_frame_set_reg_addr (this_cache, |
| 1066 | regs->fp_control_status + NUM_REGS, |
| 1067 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
| 1068 | trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS, |
| 1069 | sigcontext_base + N64_SIGCONTEXT_HI); |
| 1070 | trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS, |
| 1071 | sigcontext_base + N64_SIGCONTEXT_LO); |
| 1072 | trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS, |
| 1073 | sigcontext_base + N64_SIGCONTEXT_CAUSE); |
| 1074 | trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS, |
| 1075 | sigcontext_base + N64_SIGCONTEXT_BADVADDR); |
| 1076 | |
| 1077 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ |
| 1078 | trad_frame_set_id (this_cache, |
| 1079 | frame_id_build (func - SIGFRAME_CODE_OFFSET, |
| 1080 | func)); |
| 1081 | } |
| 1082 | |
| 1083 | /* Wrapper functions. These are only used by libthread_db. */ |
| 1084 | |
| 1085 | void |
| 1086 | supply_gregset (mips_elf_gregset_t *gregsetp) |
| 1087 | { |
| 1088 | if (mips_isa_regsize (current_gdbarch) == 4) |
| 1089 | mips_supply_gregset (gregsetp); |
| 1090 | else |
| 1091 | mips64_supply_gregset ((void *) gregsetp); |
| 1092 | } |
| 1093 | |
| 1094 | void |
| 1095 | fill_gregset (mips_elf_gregset_t *gregsetp, int regno) |
| 1096 | { |
| 1097 | if (mips_isa_regsize (current_gdbarch) == 4) |
| 1098 | mips_fill_gregset (gregsetp, regno); |
| 1099 | else |
| 1100 | mips64_fill_gregset ((void *) gregsetp, regno); |
| 1101 | } |
| 1102 | |
| 1103 | /* Likewise, unpack an elf_fpregset_t. */ |
| 1104 | |
| 1105 | void |
| 1106 | supply_fpregset (mips_elf_fpregset_t *fpregsetp) |
| 1107 | { |
| 1108 | if (mips_isa_regsize (current_gdbarch) == 4) |
| 1109 | mips_supply_fpregset (fpregsetp); |
| 1110 | else |
| 1111 | mips64_supply_fpregset ((void *) fpregsetp); |
| 1112 | } |
| 1113 | |
| 1114 | /* Likewise, pack one or all floating point registers into an |
| 1115 | elf_fpregset_t. */ |
| 1116 | |
| 1117 | void |
| 1118 | fill_fpregset (mips_elf_fpregset_t *fpregsetp, int regno) |
| 1119 | { |
| 1120 | if (mips_isa_regsize (current_gdbarch) == 4) |
| 1121 | mips_fill_fpregset (fpregsetp, regno); |
| 1122 | else |
| 1123 | mips64_fill_fpregset ((void *) fpregsetp, regno); |
| 1124 | } |
| 1125 | |
| 1126 | /* Initialize one of the GNU/Linux OS ABIs. */ |
| 1127 | |
| 1128 | static void |
| 1129 | mips_linux_init_abi (struct gdbarch_info info, |
| 1130 | struct gdbarch *gdbarch) |
| 1131 | { |
| 1132 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 1133 | enum mips_abi abi = mips_abi (gdbarch); |
| 1134 | |
| 1135 | switch (abi) |
| 1136 | { |
| 1137 | case MIPS_ABI_O32: |
| 1138 | set_gdbarch_get_longjmp_target (gdbarch, |
| 1139 | mips_linux_get_longjmp_target); |
| 1140 | set_solib_svr4_fetch_link_map_offsets |
| 1141 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
| 1142 | set_mips_linux_register_addr (gdbarch, mips_linux_register_addr); |
| 1143 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
| 1144 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); |
| 1145 | break; |
| 1146 | case MIPS_ABI_N32: |
| 1147 | set_gdbarch_get_longjmp_target (gdbarch, |
| 1148 | mips_linux_get_longjmp_target); |
| 1149 | set_solib_svr4_fetch_link_map_offsets |
| 1150 | (gdbarch, svr4_ilp32_fetch_link_map_offsets); |
| 1151 | set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr); |
| 1152 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 1153 | /* These floatformats should probably be renamed. MIPS uses |
| 1154 | the same 128-bit IEEE floating point format that IA-64 uses, |
| 1155 | except that the quiet/signalling NaN bit is reversed (GDB |
| 1156 | does not distinguish between quiet and signalling NaNs). */ |
| 1157 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
| 1158 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
| 1159 | break; |
| 1160 | case MIPS_ABI_N64: |
| 1161 | set_gdbarch_get_longjmp_target (gdbarch, |
| 1162 | mips64_linux_get_longjmp_target); |
| 1163 | set_solib_svr4_fetch_link_map_offsets |
| 1164 | (gdbarch, svr4_lp64_fetch_link_map_offsets); |
| 1165 | set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr); |
| 1166 | set_gdbarch_long_double_bit (gdbarch, 128); |
| 1167 | /* These floatformats should probably be renamed. MIPS uses |
| 1168 | the same 128-bit IEEE floating point format that IA-64 uses, |
| 1169 | except that the quiet/signalling NaN bit is reversed (GDB |
| 1170 | does not distinguish between quiet and signalling NaNs). */ |
| 1171 | set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad); |
| 1172 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
| 1173 | break; |
| 1174 | default: |
| 1175 | internal_error (__FILE__, __LINE__, _("can't handle ABI")); |
| 1176 | break; |
| 1177 | } |
| 1178 | |
| 1179 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
| 1180 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); |
| 1181 | |
| 1182 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
| 1183 | |
| 1184 | /* Enable TLS support. */ |
| 1185 | set_gdbarch_fetch_tls_load_module_address (gdbarch, |
| 1186 | svr4_fetch_objfile_link_map); |
| 1187 | } |
| 1188 | |
| 1189 | void |
| 1190 | _initialize_mips_linux_tdep (void) |
| 1191 | { |
| 1192 | const struct bfd_arch_info *arch_info; |
| 1193 | |
| 1194 | register_addr_data = |
| 1195 | gdbarch_data_register_post_init (init_register_addr_data); |
| 1196 | |
| 1197 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
| 1198 | arch_info != NULL; |
| 1199 | arch_info = arch_info->next) |
| 1200 | { |
| 1201 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
| 1202 | GDB_OSABI_LINUX, |
| 1203 | mips_linux_init_abi); |
| 1204 | } |
| 1205 | |
| 1206 | deprecated_add_core_fns (®set_core_fns); |
| 1207 | } |