| 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
| 2 | Copyright 1988-1999, Free Software Foundation, Inc. |
| 3 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
| 4 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. |
| 5 | |
| 6 | This file is part of GDB. |
| 7 | |
| 8 | This program is free software; you can redistribute it and/or modify |
| 9 | it under the terms of the GNU General Public License as published by |
| 10 | the Free Software Foundation; either version 2 of the License, or |
| 11 | (at your option) any later version. |
| 12 | |
| 13 | This program is distributed in the hope that it will be useful, |
| 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | GNU General Public License for more details. |
| 17 | |
| 18 | You should have received a copy of the GNU General Public License |
| 19 | along with this program; if not, write to the Free Software |
| 20 | Foundation, Inc., 59 Temple Place - Suite 330, |
| 21 | Boston, MA 02111-1307, USA. */ |
| 22 | |
| 23 | #include "defs.h" |
| 24 | #include "gdb_string.h" |
| 25 | #include "frame.h" |
| 26 | #include "inferior.h" |
| 27 | #include "symtab.h" |
| 28 | #include "value.h" |
| 29 | #include "gdbcmd.h" |
| 30 | #include "language.h" |
| 31 | #include "gdbcore.h" |
| 32 | #include "symfile.h" |
| 33 | #include "objfiles.h" |
| 34 | #include "gdbtypes.h" |
| 35 | #include "target.h" |
| 36 | |
| 37 | #include "opcode/mips.h" |
| 38 | #include "elf/mips.h" |
| 39 | #include "elf-bfd.h" |
| 40 | |
| 41 | |
| 42 | struct frame_extra_info |
| 43 | { |
| 44 | mips_extra_func_info_t proc_desc; |
| 45 | int num_args; |
| 46 | }; |
| 47 | |
| 48 | /* Some MIPS boards don't support floating point while others only |
| 49 | support single-precision floating-point operations. See also |
| 50 | FP_REGISTER_DOUBLE. */ |
| 51 | |
| 52 | enum mips_fpu_type |
| 53 | { |
| 54 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ |
| 55 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ |
| 56 | MIPS_FPU_NONE /* No floating point. */ |
| 57 | }; |
| 58 | |
| 59 | #ifndef MIPS_DEFAULT_FPU_TYPE |
| 60 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE |
| 61 | #endif |
| 62 | static int mips_fpu_type_auto = 1; |
| 63 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; |
| 64 | #define MIPS_FPU_TYPE mips_fpu_type |
| 65 | |
| 66 | #ifndef MIPS_SAVED_REGSIZE |
| 67 | #define MIPS_SAVED_REGSIZE MIPS_REGSIZE |
| 68 | #endif |
| 69 | |
| 70 | /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */ |
| 71 | #ifndef FP_REGISTER_DOUBLE |
| 72 | #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8) |
| 73 | #endif |
| 74 | |
| 75 | |
| 76 | /* MIPS specific per-architecture information */ |
| 77 | struct gdbarch_tdep |
| 78 | { |
| 79 | /* from the elf header */ |
| 80 | int elf_flags; |
| 81 | /* mips options */ |
| 82 | int mips_eabi; |
| 83 | enum mips_fpu_type mips_fpu_type; |
| 84 | int mips_last_arg_regnum; |
| 85 | int mips_last_fp_arg_regnum; |
| 86 | int mips_saved_regsize; |
| 87 | int mips_fp_register_double; |
| 88 | }; |
| 89 | |
| 90 | #if GDB_MULTI_ARCH |
| 91 | #undef MIPS_EABI |
| 92 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_eabi) |
| 93 | #endif |
| 94 | |
| 95 | #if GDB_MULTI_ARCH |
| 96 | #undef MIPS_LAST_FP_ARG_REGNUM |
| 97 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
| 98 | #endif |
| 99 | |
| 100 | #if GDB_MULTI_ARCH |
| 101 | #undef MIPS_LAST_ARG_REGNUM |
| 102 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
| 103 | #endif |
| 104 | |
| 105 | #if GDB_MULTI_ARCH |
| 106 | #undef MIPS_FPU_TYPE |
| 107 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
| 108 | #endif |
| 109 | |
| 110 | #if GDB_MULTI_ARCH |
| 111 | #undef MIPS_SAVED_REGSIZE |
| 112 | #define MIPS_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_saved_regsize) |
| 113 | #endif |
| 114 | |
| 115 | /* Indicate that the ABI makes use of double-precision registers |
| 116 | provided by the FPU (rather than combining pairs of registers to |
| 117 | form double-precision values). Do not use "TARGET_IS_MIPS64" to |
| 118 | determine if the ABI is using double-precision registers. See also |
| 119 | MIPS_FPU_TYPE. */ |
| 120 | #if GDB_MULTI_ARCH |
| 121 | #undef FP_REGISTER_DOUBLE |
| 122 | #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double) |
| 123 | #endif |
| 124 | |
| 125 | |
| 126 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
| 127 | |
| 128 | #if 0 |
| 129 | static int mips_in_lenient_prologue PARAMS ((CORE_ADDR, CORE_ADDR)); |
| 130 | #endif |
| 131 | |
| 132 | int gdb_print_insn_mips PARAMS ((bfd_vma, disassemble_info *)); |
| 133 | |
| 134 | static void mips_print_register PARAMS ((int, int)); |
| 135 | |
| 136 | static mips_extra_func_info_t |
| 137 | heuristic_proc_desc PARAMS ((CORE_ADDR, CORE_ADDR, struct frame_info *)); |
| 138 | |
| 139 | static CORE_ADDR heuristic_proc_start PARAMS ((CORE_ADDR)); |
| 140 | |
| 141 | static CORE_ADDR read_next_frame_reg PARAMS ((struct frame_info *, int)); |
| 142 | |
| 143 | int mips_set_processor_type PARAMS ((char *)); |
| 144 | |
| 145 | static void mips_show_processor_type_command PARAMS ((char *, int)); |
| 146 | |
| 147 | static void reinit_frame_cache_sfunc PARAMS ((char *, int, |
| 148 | struct cmd_list_element *)); |
| 149 | |
| 150 | static mips_extra_func_info_t |
| 151 | find_proc_desc PARAMS ((CORE_ADDR pc, struct frame_info * next_frame)); |
| 152 | |
| 153 | static CORE_ADDR after_prologue PARAMS ((CORE_ADDR pc, |
| 154 | mips_extra_func_info_t proc_desc)); |
| 155 | |
| 156 | /* This value is the model of MIPS in use. It is derived from the value |
| 157 | of the PrID register. */ |
| 158 | |
| 159 | char *mips_processor_type; |
| 160 | |
| 161 | char *tmp_mips_processor_type; |
| 162 | |
| 163 | /* A set of original names, to be used when restoring back to generic |
| 164 | registers from a specific set. */ |
| 165 | |
| 166 | char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; |
| 167 | char **mips_processor_reg_names = mips_generic_reg_names; |
| 168 | |
| 169 | char * |
| 170 | mips_register_name (i) |
| 171 | int i; |
| 172 | { |
| 173 | return mips_processor_reg_names[i]; |
| 174 | } |
| 175 | /* *INDENT-OFF* */ |
| 176 | /* Names of IDT R3041 registers. */ |
| 177 | |
| 178 | char *mips_r3041_reg_names[] = { |
| 179 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 180 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 181 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 182 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 183 | "sr", "lo", "hi", "bad", "cause","pc", |
| 184 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 185 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 186 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 187 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 188 | "fsr", "fir", "fp", "", |
| 189 | "", "", "bus", "ccfg", "", "", "", "", |
| 190 | "", "", "port", "cmp", "", "", "epc", "prid", |
| 191 | }; |
| 192 | |
| 193 | /* Names of IDT R3051 registers. */ |
| 194 | |
| 195 | char *mips_r3051_reg_names[] = { |
| 196 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 197 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 198 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 199 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 200 | "sr", "lo", "hi", "bad", "cause","pc", |
| 201 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 202 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 203 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 204 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 205 | "fsr", "fir", "fp", "", |
| 206 | "inx", "rand", "elo", "", "ctxt", "", "", "", |
| 207 | "", "", "ehi", "", "", "", "epc", "prid", |
| 208 | }; |
| 209 | |
| 210 | /* Names of IDT R3081 registers. */ |
| 211 | |
| 212 | char *mips_r3081_reg_names[] = { |
| 213 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 214 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 215 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 216 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 217 | "sr", "lo", "hi", "bad", "cause","pc", |
| 218 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 219 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 220 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 221 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 222 | "fsr", "fir", "fp", "", |
| 223 | "inx", "rand", "elo", "cfg", "ctxt", "", "", "", |
| 224 | "", "", "ehi", "", "", "", "epc", "prid", |
| 225 | }; |
| 226 | |
| 227 | /* Names of LSI 33k registers. */ |
| 228 | |
| 229 | char *mips_lsi33k_reg_names[] = { |
| 230 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
| 231 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
| 232 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", |
| 233 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", |
| 234 | "epc", "hi", "lo", "sr", "cause","badvaddr", |
| 235 | "dcic", "bpc", "bda", "", "", "", "", "", |
| 236 | "", "", "", "", "", "", "", "", |
| 237 | "", "", "", "", "", "", "", "", |
| 238 | "", "", "", "", "", "", "", "", |
| 239 | "", "", "", "", |
| 240 | "", "", "", "", "", "", "", "", |
| 241 | "", "", "", "", "", "", "", "", |
| 242 | }; |
| 243 | |
| 244 | struct { |
| 245 | char *name; |
| 246 | char **regnames; |
| 247 | } mips_processor_type_table[] = { |
| 248 | { "generic", mips_generic_reg_names }, |
| 249 | { "r3041", mips_r3041_reg_names }, |
| 250 | { "r3051", mips_r3051_reg_names }, |
| 251 | { "r3071", mips_r3081_reg_names }, |
| 252 | { "r3081", mips_r3081_reg_names }, |
| 253 | { "lsi33k", mips_lsi33k_reg_names }, |
| 254 | { NULL, NULL } |
| 255 | }; |
| 256 | /* *INDENT-ON* */ |
| 257 | |
| 258 | |
| 259 | |
| 260 | |
| 261 | /* Table to translate MIPS16 register field to actual register number. */ |
| 262 | static int mips16_to_32_reg[8] = |
| 263 | {16, 17, 2, 3, 4, 5, 6, 7}; |
| 264 | |
| 265 | /* Heuristic_proc_start may hunt through the text section for a long |
| 266 | time across a 2400 baud serial line. Allows the user to limit this |
| 267 | search. */ |
| 268 | |
| 269 | static unsigned int heuristic_fence_post = 0; |
| 270 | |
| 271 | #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */ |
| 272 | #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */ |
| 273 | #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset) |
| 274 | #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg) |
| 275 | #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust) |
| 276 | #define PROC_REG_MASK(proc) ((proc)->pdr.regmask) |
| 277 | #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask) |
| 278 | #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset) |
| 279 | #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset) |
| 280 | #define PROC_PC_REG(proc) ((proc)->pdr.pcreg) |
| 281 | #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym) |
| 282 | #define _PROC_MAGIC_ 0x0F0F0F0F |
| 283 | #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_) |
| 284 | #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_) |
| 285 | |
| 286 | struct linked_proc_info |
| 287 | { |
| 288 | struct mips_extra_func_info info; |
| 289 | struct linked_proc_info *next; |
| 290 | } |
| 291 | *linked_proc_desc_table = NULL; |
| 292 | |
| 293 | void |
| 294 | mips_print_extra_frame_info (fi) |
| 295 | struct frame_info *fi; |
| 296 | { |
| 297 | if (fi |
| 298 | && fi->extra_info |
| 299 | && fi->extra_info->proc_desc |
| 300 | && fi->extra_info->proc_desc->pdr.framereg < NUM_REGS) |
| 301 | printf_filtered (" frame pointer is at %s+%s\n", |
| 302 | REGISTER_NAME (fi->extra_info->proc_desc->pdr.framereg), |
| 303 | paddr_d (fi->extra_info->proc_desc->pdr.frameoffset)); |
| 304 | } |
| 305 | |
| 306 | /* Convert between RAW and VIRTUAL registers. The RAW register size |
| 307 | defines the remote-gdb packet. */ |
| 308 | |
| 309 | static int mips64_transfers_32bit_regs_p = 0; |
| 310 | |
| 311 | int |
| 312 | mips_register_raw_size (reg_nr) |
| 313 | int reg_nr; |
| 314 | { |
| 315 | if (mips64_transfers_32bit_regs_p) |
| 316 | return REGISTER_VIRTUAL_SIZE (reg_nr); |
| 317 | else |
| 318 | return MIPS_REGSIZE; |
| 319 | } |
| 320 | |
| 321 | int |
| 322 | mips_register_convertible (reg_nr) |
| 323 | int reg_nr; |
| 324 | { |
| 325 | if (mips64_transfers_32bit_regs_p) |
| 326 | return 0; |
| 327 | else |
| 328 | return (REGISTER_RAW_SIZE (reg_nr) > REGISTER_VIRTUAL_SIZE (reg_nr)); |
| 329 | } |
| 330 | |
| 331 | void |
| 332 | mips_register_convert_to_virtual (n, virtual_type, raw_buf, virt_buf) |
| 333 | int n; |
| 334 | struct type *virtual_type; |
| 335 | char *raw_buf; |
| 336 | char *virt_buf; |
| 337 | { |
| 338 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 339 | memcpy (virt_buf, |
| 340 | raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
| 341 | TYPE_LENGTH (virtual_type)); |
| 342 | else |
| 343 | memcpy (virt_buf, |
| 344 | raw_buf, |
| 345 | TYPE_LENGTH (virtual_type)); |
| 346 | } |
| 347 | |
| 348 | void |
| 349 | mips_register_convert_to_raw (virtual_type, n, virt_buf, raw_buf) |
| 350 | struct type *virtual_type; |
| 351 | int n; |
| 352 | char *virt_buf; |
| 353 | char *raw_buf; |
| 354 | { |
| 355 | memset (raw_buf, 0, REGISTER_RAW_SIZE (n)); |
| 356 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 357 | memcpy (raw_buf + (REGISTER_RAW_SIZE (n) - TYPE_LENGTH (virtual_type)), |
| 358 | virt_buf, |
| 359 | TYPE_LENGTH (virtual_type)); |
| 360 | else |
| 361 | memcpy (raw_buf, |
| 362 | virt_buf, |
| 363 | TYPE_LENGTH (virtual_type)); |
| 364 | } |
| 365 | |
| 366 | /* Should the upper word of 64-bit addresses be zeroed? */ |
| 367 | static int mask_address_p = 1; |
| 368 | |
| 369 | /* Should call_function allocate stack space for a struct return? */ |
| 370 | int |
| 371 | mips_use_struct_convention (gcc_p, type) |
| 372 | int gcc_p; |
| 373 | struct type *type; |
| 374 | { |
| 375 | if (MIPS_EABI) |
| 376 | return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); |
| 377 | else |
| 378 | return 1; /* Structures are returned by ref in extra arg0 */ |
| 379 | } |
| 380 | |
| 381 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
| 382 | |
| 383 | static int |
| 384 | pc_is_mips16 (bfd_vma memaddr) |
| 385 | { |
| 386 | struct minimal_symbol *sym; |
| 387 | |
| 388 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ |
| 389 | if (IS_MIPS16_ADDR (memaddr)) |
| 390 | return 1; |
| 391 | |
| 392 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in |
| 393 | the high bit of the info field. Use this to decide if the function is |
| 394 | MIPS16 or normal MIPS. */ |
| 395 | sym = lookup_minimal_symbol_by_pc (memaddr); |
| 396 | if (sym) |
| 397 | return MSYMBOL_IS_SPECIAL (sym); |
| 398 | else |
| 399 | return 0; |
| 400 | } |
| 401 | |
| 402 | |
| 403 | /* This returns the PC of the first inst after the prologue. If we can't |
| 404 | find the prologue, then return 0. */ |
| 405 | |
| 406 | static CORE_ADDR |
| 407 | after_prologue (pc, proc_desc) |
| 408 | CORE_ADDR pc; |
| 409 | mips_extra_func_info_t proc_desc; |
| 410 | { |
| 411 | struct symtab_and_line sal; |
| 412 | CORE_ADDR func_addr, func_end; |
| 413 | |
| 414 | if (!proc_desc) |
| 415 | proc_desc = find_proc_desc (pc, NULL); |
| 416 | |
| 417 | if (proc_desc) |
| 418 | { |
| 419 | /* If function is frameless, then we need to do it the hard way. I |
| 420 | strongly suspect that frameless always means prologueless... */ |
| 421 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
| 422 | && PROC_FRAME_OFFSET (proc_desc) == 0) |
| 423 | return 0; |
| 424 | } |
| 425 | |
| 426 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 427 | return 0; /* Unknown */ |
| 428 | |
| 429 | sal = find_pc_line (func_addr, 0); |
| 430 | |
| 431 | if (sal.end < func_end) |
| 432 | return sal.end; |
| 433 | |
| 434 | /* The line after the prologue is after the end of the function. In this |
| 435 | case, tell the caller to find the prologue the hard way. */ |
| 436 | |
| 437 | return 0; |
| 438 | } |
| 439 | |
| 440 | /* Decode a MIPS32 instruction that saves a register in the stack, and |
| 441 | set the appropriate bit in the general register mask or float register mask |
| 442 | to indicate which register is saved. This is a helper function |
| 443 | for mips_find_saved_regs. */ |
| 444 | |
| 445 | static void |
| 446 | mips32_decode_reg_save (inst, gen_mask, float_mask) |
| 447 | t_inst inst; |
| 448 | unsigned long *gen_mask; |
| 449 | unsigned long *float_mask; |
| 450 | { |
| 451 | int reg; |
| 452 | |
| 453 | if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */ |
| 454 | || (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */ |
| 455 | || (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */ |
| 456 | { |
| 457 | /* It might be possible to use the instruction to |
| 458 | find the offset, rather than the code below which |
| 459 | is based on things being in a certain order in the |
| 460 | frame, but figuring out what the instruction's offset |
| 461 | is relative to might be a little tricky. */ |
| 462 | reg = (inst & 0x001f0000) >> 16; |
| 463 | *gen_mask |= (1 << reg); |
| 464 | } |
| 465 | else if ((inst & 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */ |
| 466 | || (inst & 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */ |
| 467 | || (inst & 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */ |
| 468 | |
| 469 | { |
| 470 | reg = ((inst & 0x001f0000) >> 16); |
| 471 | *float_mask |= (1 << reg); |
| 472 | } |
| 473 | } |
| 474 | |
| 475 | /* Decode a MIPS16 instruction that saves a register in the stack, and |
| 476 | set the appropriate bit in the general register or float register mask |
| 477 | to indicate which register is saved. This is a helper function |
| 478 | for mips_find_saved_regs. */ |
| 479 | |
| 480 | static void |
| 481 | mips16_decode_reg_save (inst, gen_mask) |
| 482 | t_inst inst; |
| 483 | unsigned long *gen_mask; |
| 484 | { |
| 485 | if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
| 486 | { |
| 487 | int reg = mips16_to_32_reg[(inst & 0x700) >> 8]; |
| 488 | *gen_mask |= (1 << reg); |
| 489 | } |
| 490 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
| 491 | { |
| 492 | int reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; |
| 493 | *gen_mask |= (1 << reg); |
| 494 | } |
| 495 | else if ((inst & 0xff00) == 0x6200 /* sw $ra,n($sp) */ |
| 496 | || (inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
| 497 | *gen_mask |= (1 << RA_REGNUM); |
| 498 | } |
| 499 | |
| 500 | |
| 501 | /* Fetch and return instruction from the specified location. If the PC |
| 502 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ |
| 503 | |
| 504 | static t_inst |
| 505 | mips_fetch_instruction (addr) |
| 506 | CORE_ADDR addr; |
| 507 | { |
| 508 | char buf[MIPS_INSTLEN]; |
| 509 | int instlen; |
| 510 | int status; |
| 511 | |
| 512 | if (pc_is_mips16 (addr)) |
| 513 | { |
| 514 | instlen = MIPS16_INSTLEN; |
| 515 | addr = UNMAKE_MIPS16_ADDR (addr); |
| 516 | } |
| 517 | else |
| 518 | instlen = MIPS_INSTLEN; |
| 519 | status = read_memory_nobpt (addr, buf, instlen); |
| 520 | if (status) |
| 521 | memory_error (status, addr); |
| 522 | return extract_unsigned_integer (buf, instlen); |
| 523 | } |
| 524 | |
| 525 | |
| 526 | /* These the fields of 32 bit mips instructions */ |
| 527 | #define mips32_op(x) (x >> 25) |
| 528 | #define itype_op(x) (x >> 25) |
| 529 | #define itype_rs(x) ((x >> 21)& 0x1f) |
| 530 | #define itype_rt(x) ((x >> 16) & 0x1f) |
| 531 | #define itype_immediate(x) ( x & 0xffff) |
| 532 | |
| 533 | #define jtype_op(x) (x >> 25) |
| 534 | #define jtype_target(x) ( x & 0x03fffff) |
| 535 | |
| 536 | #define rtype_op(x) (x >>25) |
| 537 | #define rtype_rs(x) ((x>>21) & 0x1f) |
| 538 | #define rtype_rt(x) ((x>>16) & 0x1f) |
| 539 | #define rtype_rd(x) ((x>>11) & 0x1f) |
| 540 | #define rtype_shamt(x) ((x>>6) & 0x1f) |
| 541 | #define rtype_funct(x) (x & 0x3f ) |
| 542 | |
| 543 | static CORE_ADDR |
| 544 | mips32_relative_offset (unsigned long inst) |
| 545 | { |
| 546 | long x; |
| 547 | x = itype_immediate (inst); |
| 548 | if (x & 0x8000) /* sign bit set */ |
| 549 | { |
| 550 | x |= 0xffff0000; /* sign extension */ |
| 551 | } |
| 552 | x = x << 2; |
| 553 | return x; |
| 554 | } |
| 555 | |
| 556 | /* Determine whate to set a single step breakpoint while considering |
| 557 | branch prediction */ |
| 558 | CORE_ADDR |
| 559 | mips32_next_pc (CORE_ADDR pc) |
| 560 | { |
| 561 | unsigned long inst; |
| 562 | int op; |
| 563 | inst = mips_fetch_instruction (pc); |
| 564 | if ((inst & 0xe0000000) != 0) /* Not a special, junp or branch instruction */ |
| 565 | { |
| 566 | if ((inst >> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */ |
| 567 | { |
| 568 | op = ((inst >> 25) & 0x03); |
| 569 | switch (op) |
| 570 | { |
| 571 | case 0: |
| 572 | goto equal_branch; /* BEQL */ |
| 573 | case 1: |
| 574 | goto neq_branch; /* BNEZ */ |
| 575 | case 2: |
| 576 | goto less_branch; /* BLEZ */ |
| 577 | case 3: |
| 578 | goto greater_branch; /* BGTZ */ |
| 579 | default: |
| 580 | pc += 4; |
| 581 | } |
| 582 | } |
| 583 | else |
| 584 | pc += 4; /* Not a branch, next instruction is easy */ |
| 585 | } |
| 586 | else |
| 587 | { /* This gets way messy */ |
| 588 | |
| 589 | /* Further subdivide into SPECIAL, REGIMM and other */ |
| 590 | switch (op = ((inst >> 26) & 0x07)) /* extract bits 28,27,26 */ |
| 591 | { |
| 592 | case 0: /* SPECIAL */ |
| 593 | op = rtype_funct (inst); |
| 594 | switch (op) |
| 595 | { |
| 596 | case 8: /* JR */ |
| 597 | case 9: /* JALR */ |
| 598 | pc = read_register (rtype_rs (inst)); /* Set PC to that address */ |
| 599 | break; |
| 600 | default: |
| 601 | pc += 4; |
| 602 | } |
| 603 | |
| 604 | break; /* end special */ |
| 605 | case 1: /* REGIMM */ |
| 606 | { |
| 607 | op = jtype_op (inst); /* branch condition */ |
| 608 | switch (jtype_op (inst)) |
| 609 | { |
| 610 | case 0: /* BLTZ */ |
| 611 | case 2: /* BLTXL */ |
| 612 | case 16: /* BLTZALL */ |
| 613 | case 18: /* BLTZALL */ |
| 614 | less_branch: |
| 615 | if (read_register (itype_rs (inst)) < 0) |
| 616 | pc += mips32_relative_offset (inst) + 4; |
| 617 | else |
| 618 | pc += 8; /* after the delay slot */ |
| 619 | break; |
| 620 | case 1: /* GEZ */ |
| 621 | case 3: /* BGEZL */ |
| 622 | case 17: /* BGEZAL */ |
| 623 | case 19: /* BGEZALL */ |
| 624 | greater_equal_branch: |
| 625 | if (read_register (itype_rs (inst)) >= 0) |
| 626 | pc += mips32_relative_offset (inst) + 4; |
| 627 | else |
| 628 | pc += 8; /* after the delay slot */ |
| 629 | break; |
| 630 | /* All of the other intructions in the REGIMM catagory */ |
| 631 | default: |
| 632 | pc += 4; |
| 633 | } |
| 634 | } |
| 635 | break; /* end REGIMM */ |
| 636 | case 2: /* J */ |
| 637 | case 3: /* JAL */ |
| 638 | { |
| 639 | unsigned long reg; |
| 640 | reg = jtype_target (inst) << 2; |
| 641 | pc = reg + ((pc + 4) & 0xf0000000); |
| 642 | /* Whats this mysterious 0xf000000 adjustment ??? */ |
| 643 | } |
| 644 | break; |
| 645 | /* FIXME case JALX : */ |
| 646 | { |
| 647 | unsigned long reg; |
| 648 | reg = jtype_target (inst) << 2; |
| 649 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ |
| 650 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
| 651 | } |
| 652 | break; /* The new PC will be alternate mode */ |
| 653 | case 4: /* BEQ , BEQL */ |
| 654 | equal_branch: |
| 655 | if (read_register (itype_rs (inst)) == |
| 656 | read_register (itype_rt (inst))) |
| 657 | pc += mips32_relative_offset (inst) + 4; |
| 658 | else |
| 659 | pc += 8; |
| 660 | break; |
| 661 | case 5: /* BNE , BNEL */ |
| 662 | neq_branch: |
| 663 | if (read_register (itype_rs (inst)) != |
| 664 | read_register (itype_rs (inst))) |
| 665 | pc += mips32_relative_offset (inst) + 4; |
| 666 | else |
| 667 | pc += 8; |
| 668 | break; |
| 669 | case 6: /* BLEZ , BLEZL */ |
| 670 | less_zero_branch: |
| 671 | if (read_register (itype_rs (inst) <= 0)) |
| 672 | pc += mips32_relative_offset (inst) + 4; |
| 673 | else |
| 674 | pc += 8; |
| 675 | break; |
| 676 | case 7: |
| 677 | greater_branch: /* BGTZ BGTZL */ |
| 678 | if (read_register (itype_rs (inst) > 0)) |
| 679 | pc += mips32_relative_offset (inst) + 4; |
| 680 | else |
| 681 | pc += 8; |
| 682 | break; |
| 683 | default: |
| 684 | pc += 8; |
| 685 | } /* switch */ |
| 686 | } /* else */ |
| 687 | return pc; |
| 688 | } /* mips32_next_pc */ |
| 689 | |
| 690 | /* Decoding the next place to set a breakpoint is irregular for the |
| 691 | mips 16 variant, but fortunatly, there fewer instructions. We have to cope |
| 692 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
| 693 | We dont want to set a single step instruction on the extend instruction |
| 694 | either. |
| 695 | */ |
| 696 | |
| 697 | /* Lots of mips16 instruction formats */ |
| 698 | /* Predicting jumps requires itype,ritype,i8type |
| 699 | and their extensions extItype,extritype,extI8type |
| 700 | */ |
| 701 | enum mips16_inst_fmts |
| 702 | { |
| 703 | itype, /* 0 immediate 5,10 */ |
| 704 | ritype, /* 1 5,3,8 */ |
| 705 | rrtype, /* 2 5,3,3,5 */ |
| 706 | rritype, /* 3 5,3,3,5 */ |
| 707 | rrrtype, /* 4 5,3,3,3,2 */ |
| 708 | rriatype, /* 5 5,3,3,1,4 */ |
| 709 | shifttype, /* 6 5,3,3,3,2 */ |
| 710 | i8type, /* 7 5,3,8 */ |
| 711 | i8movtype, /* 8 5,3,3,5 */ |
| 712 | i8mov32rtype, /* 9 5,3,5,3 */ |
| 713 | i64type, /* 10 5,3,8 */ |
| 714 | ri64type, /* 11 5,3,3,5 */ |
| 715 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ |
| 716 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ |
| 717 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ |
| 718 | extRRItype, /* 15 5,5,5,5,3,3,5 */ |
| 719 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ |
| 720 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ |
| 721 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ |
| 722 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ |
| 723 | extRi64type, /* 20 5,6,5,5,3,3,5 */ |
| 724 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ |
| 725 | }; |
| 726 | /* I am heaping all the fields of the formats into one structure and then, |
| 727 | only the fields which are involved in instruction extension */ |
| 728 | struct upk_mips16 |
| 729 | { |
| 730 | unsigned short inst; |
| 731 | enum mips16_inst_fmts fmt; |
| 732 | unsigned long offset; |
| 733 | unsigned int regx; /* Function in i8 type */ |
| 734 | unsigned int regy; |
| 735 | }; |
| 736 | |
| 737 | |
| 738 | |
| 739 | static void |
| 740 | print_unpack (char *comment, |
| 741 | struct upk_mips16 *u) |
| 742 | { |
| 743 | printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n", |
| 744 | comment, u->inst, u->fmt, paddr (u->offset), u->regx, u->regy); |
| 745 | } |
| 746 | |
| 747 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same |
| 748 | format for the bits which make up the immediatate extension. |
| 749 | */ |
| 750 | static unsigned long |
| 751 | extended_offset (unsigned long extension) |
| 752 | { |
| 753 | unsigned long value; |
| 754 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
| 755 | value = value << 6; |
| 756 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ |
| 757 | value = value << 5; |
| 758 | value |= extension & 0x01f; /* extract 4:0 */ |
| 759 | return value; |
| 760 | } |
| 761 | |
| 762 | /* Only call this function if you know that this is an extendable |
| 763 | instruction, It wont malfunction, but why make excess remote memory references? |
| 764 | If the immediate operands get sign extended or somthing, do it after |
| 765 | the extension is performed. |
| 766 | */ |
| 767 | /* FIXME: Every one of these cases needs to worry about sign extension |
| 768 | when the offset is to be used in relative addressing */ |
| 769 | |
| 770 | |
| 771 | static unsigned short |
| 772 | fetch_mips_16 (CORE_ADDR pc) |
| 773 | { |
| 774 | char buf[8]; |
| 775 | pc &= 0xfffffffe; /* clear the low order bit */ |
| 776 | target_read_memory (pc, buf, 2); |
| 777 | return extract_unsigned_integer (buf, 2); |
| 778 | } |
| 779 | |
| 780 | static void |
| 781 | unpack_mips16 (CORE_ADDR pc, |
| 782 | struct upk_mips16 *upk) |
| 783 | { |
| 784 | CORE_ADDR extpc; |
| 785 | unsigned long extension; |
| 786 | int extended; |
| 787 | extpc = (pc - 4) & ~0x01; /* Extensions are 32 bit instructions */ |
| 788 | /* Decrement to previous address and loose the 16bit mode flag */ |
| 789 | /* return if the instruction was extendable, but not actually extended */ |
| 790 | extended = ((mips32_op (extension) == 30) ? 1 : 0); |
| 791 | if (extended) |
| 792 | { |
| 793 | extension = mips_fetch_instruction (extpc); |
| 794 | } |
| 795 | switch (upk->fmt) |
| 796 | { |
| 797 | case itype: |
| 798 | { |
| 799 | unsigned long value; |
| 800 | if (extended) |
| 801 | { |
| 802 | value = extended_offset (extension); |
| 803 | value = value << 11; /* rom for the original value */ |
| 804 | value |= upk->inst & 0x7ff; /* eleven bits from instruction */ |
| 805 | } |
| 806 | else |
| 807 | { |
| 808 | value = upk->inst & 0x7ff; |
| 809 | /* FIXME : Consider sign extension */ |
| 810 | } |
| 811 | upk->offset = value; |
| 812 | } |
| 813 | break; |
| 814 | case ritype: |
| 815 | case i8type: |
| 816 | { /* A register identifier and an offset */ |
| 817 | /* Most of the fields are the same as I type but the |
| 818 | immediate value is of a different length */ |
| 819 | unsigned long value; |
| 820 | if (extended) |
| 821 | { |
| 822 | value = extended_offset (extension); |
| 823 | value = value << 8; /* from the original instruction */ |
| 824 | value |= upk->inst & 0xff; /* eleven bits from instruction */ |
| 825 | upk->regx = (extension >> 8) & 0x07; /* or i8 funct */ |
| 826 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
| 827 | { |
| 828 | value &= ~0x3fff; /* remove the sign bit */ |
| 829 | value = -value; |
| 830 | } |
| 831 | } |
| 832 | else |
| 833 | { |
| 834 | value = upk->inst & 0xff; /* 8 bits */ |
| 835 | upk->regx = (upk->inst >> 8) & 0x07; /* or i8 funct */ |
| 836 | /* FIXME: Do sign extension , this format needs it */ |
| 837 | if (value & 0x80) /* THIS CONFUSES ME */ |
| 838 | { |
| 839 | value &= 0xef; /* remove the sign bit */ |
| 840 | value = -value; |
| 841 | } |
| 842 | |
| 843 | } |
| 844 | upk->offset = value; |
| 845 | break; |
| 846 | } |
| 847 | case jalxtype: |
| 848 | { |
| 849 | unsigned long value; |
| 850 | unsigned short nexthalf; |
| 851 | value = ((upk->inst & 0x1f) << 5) | ((upk->inst >> 5) & 0x1f); |
| 852 | value = value << 16; |
| 853 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ |
| 854 | value |= nexthalf; |
| 855 | upk->offset = value; |
| 856 | break; |
| 857 | } |
| 858 | default: |
| 859 | printf_filtered ("Decoding unimplemented instruction format type\n"); |
| 860 | break; |
| 861 | } |
| 862 | /* print_unpack("UPK",upk) ; */ |
| 863 | } |
| 864 | |
| 865 | |
| 866 | #define mips16_op(x) (x >> 11) |
| 867 | |
| 868 | /* This is a map of the opcodes which ae known to perform branches */ |
| 869 | static unsigned char map16[32] = |
| 870 | {0, 0, 1, 1, 1, 1, 0, 0, |
| 871 | 0, 0, 0, 0, 1, 0, 0, 0, |
| 872 | 0, 0, 0, 0, 0, 0, 0, 0, |
| 873 | 0, 0, 0, 0, 0, 1, 1, 0 |
| 874 | }; |
| 875 | |
| 876 | static CORE_ADDR |
| 877 | add_offset_16 (CORE_ADDR pc, int offset) |
| 878 | { |
| 879 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
| 880 | |
| 881 | } |
| 882 | |
| 883 | |
| 884 | |
| 885 | static struct upk_mips16 upk; |
| 886 | |
| 887 | CORE_ADDR |
| 888 | mips16_next_pc (CORE_ADDR pc) |
| 889 | { |
| 890 | int op; |
| 891 | t_inst inst; |
| 892 | /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */ |
| 893 | inst = fetch_mips_16 (pc); |
| 894 | upk.inst = inst; |
| 895 | op = mips16_op (upk.inst); |
| 896 | if (map16[op]) |
| 897 | { |
| 898 | int reg; |
| 899 | switch (op) |
| 900 | { |
| 901 | case 2: /* Branch */ |
| 902 | upk.fmt = itype; |
| 903 | unpack_mips16 (pc, &upk); |
| 904 | { |
| 905 | long offset; |
| 906 | offset = upk.offset; |
| 907 | if (offset & 0x800) |
| 908 | { |
| 909 | offset &= 0xeff; |
| 910 | offset = -offset; |
| 911 | } |
| 912 | pc += (offset << 1) + 2; |
| 913 | } |
| 914 | break; |
| 915 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
| 916 | upk.fmt = jalxtype; |
| 917 | unpack_mips16 (pc, &upk); |
| 918 | pc = add_offset_16 (pc, upk.offset); |
| 919 | if ((upk.inst >> 10) & 0x01) /* Exchange mode */ |
| 920 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ |
| 921 | else |
| 922 | pc |= 0x01; |
| 923 | break; |
| 924 | case 4: /* beqz */ |
| 925 | upk.fmt = ritype; |
| 926 | unpack_mips16 (pc, &upk); |
| 927 | reg = read_register (upk.regx); |
| 928 | if (reg == 0) |
| 929 | pc += (upk.offset << 1) + 2; |
| 930 | else |
| 931 | pc += 2; |
| 932 | break; |
| 933 | case 5: /* bnez */ |
| 934 | upk.fmt = ritype; |
| 935 | unpack_mips16 (pc, &upk); |
| 936 | reg = read_register (upk.regx); |
| 937 | if (reg != 0) |
| 938 | pc += (upk.offset << 1) + 2; |
| 939 | else |
| 940 | pc += 2; |
| 941 | break; |
| 942 | case 12: /* I8 Formats btez btnez */ |
| 943 | upk.fmt = i8type; |
| 944 | unpack_mips16 (pc, &upk); |
| 945 | /* upk.regx contains the opcode */ |
| 946 | reg = read_register (24); /* Test register is 24 */ |
| 947 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
| 948 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ |
| 949 | /* pc = add_offset_16(pc,upk.offset) ; */ |
| 950 | pc += (upk.offset << 1) + 2; |
| 951 | else |
| 952 | pc += 2; |
| 953 | break; |
| 954 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
| 955 | upk.fmt = rrtype; |
| 956 | op = upk.inst & 0x1f; |
| 957 | if (op == 0) |
| 958 | { |
| 959 | upk.regx = (upk.inst >> 8) & 0x07; |
| 960 | upk.regy = (upk.inst >> 5) & 0x07; |
| 961 | switch (upk.regy) |
| 962 | { |
| 963 | case 0: |
| 964 | reg = upk.regx; |
| 965 | break; |
| 966 | case 1: |
| 967 | reg = 31; |
| 968 | break; /* Function return instruction */ |
| 969 | case 2: |
| 970 | reg = upk.regx; |
| 971 | break; |
| 972 | default: |
| 973 | reg = 31; |
| 974 | break; /* BOGUS Guess */ |
| 975 | } |
| 976 | pc = read_register (reg); |
| 977 | } |
| 978 | else |
| 979 | pc += 2; |
| 980 | break; |
| 981 | case 30: /* This is an extend instruction */ |
| 982 | pc += 4; /* Dont be setting breakpints on the second half */ |
| 983 | break; |
| 984 | default: |
| 985 | printf ("Filtered - next PC probably incorrrect due to jump inst\n"); |
| 986 | pc += 2; |
| 987 | break; |
| 988 | } |
| 989 | } |
| 990 | else |
| 991 | pc += 2; /* just a good old instruction */ |
| 992 | /* See if we CAN actually break on the next instruction */ |
| 993 | /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */ |
| 994 | return pc; |
| 995 | } /* mips16_next_pc */ |
| 996 | |
| 997 | /* The mips_next_pc function supports single_tep when the remote target monitor or |
| 998 | stub is not developed enough to so a single_step. |
| 999 | It works by decoding the current instruction and predicting where a branch |
| 1000 | will go. This isnt hard because all the data is available. |
| 1001 | The MIPS32 and MIPS16 variants are quite different |
| 1002 | */ |
| 1003 | CORE_ADDR |
| 1004 | mips_next_pc (CORE_ADDR pc) |
| 1005 | { |
| 1006 | t_inst inst; |
| 1007 | /* inst = mips_fetch_instruction(pc) ; */ |
| 1008 | /* if (pc_is_mips16) <----- This is failing */ |
| 1009 | if (pc & 0x01) |
| 1010 | return mips16_next_pc (pc); |
| 1011 | else |
| 1012 | return mips32_next_pc (pc); |
| 1013 | } /* mips_next_pc */ |
| 1014 | |
| 1015 | /* Guaranteed to set fci->saved_regs to some values (it never leaves it |
| 1016 | NULL). */ |
| 1017 | |
| 1018 | void |
| 1019 | mips_find_saved_regs (fci) |
| 1020 | struct frame_info *fci; |
| 1021 | { |
| 1022 | int ireg; |
| 1023 | CORE_ADDR reg_position; |
| 1024 | /* r0 bit means kernel trap */ |
| 1025 | int kernel_trap; |
| 1026 | /* What registers have been saved? Bitmasks. */ |
| 1027 | unsigned long gen_mask, float_mask; |
| 1028 | mips_extra_func_info_t proc_desc; |
| 1029 | t_inst inst; |
| 1030 | |
| 1031 | frame_saved_regs_zalloc (fci); |
| 1032 | |
| 1033 | /* If it is the frame for sigtramp, the saved registers are located |
| 1034 | in a sigcontext structure somewhere on the stack. |
| 1035 | If the stack layout for sigtramp changes we might have to change these |
| 1036 | constants and the companion fixup_sigtramp in mdebugread.c */ |
| 1037 | #ifndef SIGFRAME_BASE |
| 1038 | /* To satisfy alignment restrictions, sigcontext is located 4 bytes |
| 1039 | above the sigtramp frame. */ |
| 1040 | #define SIGFRAME_BASE MIPS_REGSIZE |
| 1041 | /* FIXME! Are these correct?? */ |
| 1042 | #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE) |
| 1043 | #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE) |
| 1044 | #define SIGFRAME_FPREGSAVE_OFF \ |
| 1045 | (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE) |
| 1046 | #endif |
| 1047 | #ifndef SIGFRAME_REG_SIZE |
| 1048 | /* FIXME! Is this correct?? */ |
| 1049 | #define SIGFRAME_REG_SIZE MIPS_REGSIZE |
| 1050 | #endif |
| 1051 | if (fci->signal_handler_caller) |
| 1052 | { |
| 1053 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
| 1054 | { |
| 1055 | reg_position = fci->frame + SIGFRAME_REGSAVE_OFF |
| 1056 | + ireg * SIGFRAME_REG_SIZE; |
| 1057 | fci->saved_regs[ireg] = reg_position; |
| 1058 | } |
| 1059 | for (ireg = 0; ireg < MIPS_NUMREGS; ireg++) |
| 1060 | { |
| 1061 | reg_position = fci->frame + SIGFRAME_FPREGSAVE_OFF |
| 1062 | + ireg * SIGFRAME_REG_SIZE; |
| 1063 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
| 1064 | } |
| 1065 | fci->saved_regs[PC_REGNUM] = fci->frame + SIGFRAME_PC_OFF; |
| 1066 | return; |
| 1067 | } |
| 1068 | |
| 1069 | proc_desc = fci->extra_info->proc_desc; |
| 1070 | if (proc_desc == NULL) |
| 1071 | /* I'm not sure how/whether this can happen. Normally when we can't |
| 1072 | find a proc_desc, we "synthesize" one using heuristic_proc_desc |
| 1073 | and set the saved_regs right away. */ |
| 1074 | return; |
| 1075 | |
| 1076 | kernel_trap = PROC_REG_MASK (proc_desc) & 1; |
| 1077 | gen_mask = kernel_trap ? 0xFFFFFFFF : PROC_REG_MASK (proc_desc); |
| 1078 | float_mask = kernel_trap ? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc); |
| 1079 | |
| 1080 | if ( /* In any frame other than the innermost or a frame interrupted by |
| 1081 | a signal, we assume that all registers have been saved. |
| 1082 | This assumes that all register saves in a function happen before |
| 1083 | the first function call. */ |
| 1084 | (fci->next == NULL || fci->next->signal_handler_caller) |
| 1085 | |
| 1086 | /* In a dummy frame we know exactly where things are saved. */ |
| 1087 | && !PROC_DESC_IS_DUMMY (proc_desc) |
| 1088 | |
| 1089 | /* Don't bother unless we are inside a function prologue. Outside the |
| 1090 | prologue, we know where everything is. */ |
| 1091 | |
| 1092 | && in_prologue (fci->pc, PROC_LOW_ADDR (proc_desc)) |
| 1093 | |
| 1094 | /* Not sure exactly what kernel_trap means, but if it means |
| 1095 | the kernel saves the registers without a prologue doing it, |
| 1096 | we better not examine the prologue to see whether registers |
| 1097 | have been saved yet. */ |
| 1098 | && !kernel_trap) |
| 1099 | { |
| 1100 | /* We need to figure out whether the registers that the proc_desc |
| 1101 | claims are saved have been saved yet. */ |
| 1102 | |
| 1103 | CORE_ADDR addr; |
| 1104 | |
| 1105 | /* Bitmasks; set if we have found a save for the register. */ |
| 1106 | unsigned long gen_save_found = 0; |
| 1107 | unsigned long float_save_found = 0; |
| 1108 | int instlen; |
| 1109 | |
| 1110 | /* If the address is odd, assume this is MIPS16 code. */ |
| 1111 | addr = PROC_LOW_ADDR (proc_desc); |
| 1112 | instlen = pc_is_mips16 (addr) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
| 1113 | |
| 1114 | /* Scan through this function's instructions preceding the current |
| 1115 | PC, and look for those that save registers. */ |
| 1116 | while (addr < fci->pc) |
| 1117 | { |
| 1118 | inst = mips_fetch_instruction (addr); |
| 1119 | if (pc_is_mips16 (addr)) |
| 1120 | mips16_decode_reg_save (inst, &gen_save_found); |
| 1121 | else |
| 1122 | mips32_decode_reg_save (inst, &gen_save_found, &float_save_found); |
| 1123 | addr += instlen; |
| 1124 | } |
| 1125 | gen_mask = gen_save_found; |
| 1126 | float_mask = float_save_found; |
| 1127 | } |
| 1128 | |
| 1129 | /* Fill in the offsets for the registers which gen_mask says |
| 1130 | were saved. */ |
| 1131 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); |
| 1132 | for (ireg = MIPS_NUMREGS - 1; gen_mask; --ireg, gen_mask <<= 1) |
| 1133 | if (gen_mask & 0x80000000) |
| 1134 | { |
| 1135 | fci->saved_regs[ireg] = reg_position; |
| 1136 | reg_position -= MIPS_SAVED_REGSIZE; |
| 1137 | } |
| 1138 | |
| 1139 | /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order |
| 1140 | of that normally used by gcc. Therefore, we have to fetch the first |
| 1141 | instruction of the function, and if it's an entry instruction that |
| 1142 | saves $s0 or $s1, correct their saved addresses. */ |
| 1143 | if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc))) |
| 1144 | { |
| 1145 | inst = mips_fetch_instruction (PROC_LOW_ADDR (proc_desc)); |
| 1146 | if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
| 1147 | { |
| 1148 | int reg; |
| 1149 | int sreg_count = (inst >> 6) & 3; |
| 1150 | |
| 1151 | /* Check if the ra register was pushed on the stack. */ |
| 1152 | reg_position = fci->frame + PROC_REG_OFFSET (proc_desc); |
| 1153 | if (inst & 0x20) |
| 1154 | reg_position -= MIPS_SAVED_REGSIZE; |
| 1155 | |
| 1156 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
| 1157 | for (reg = 16; reg < sreg_count + 16; reg++) |
| 1158 | { |
| 1159 | fci->saved_regs[reg] = reg_position; |
| 1160 | reg_position -= MIPS_SAVED_REGSIZE; |
| 1161 | } |
| 1162 | } |
| 1163 | } |
| 1164 | |
| 1165 | /* Fill in the offsets for the registers which float_mask says |
| 1166 | were saved. */ |
| 1167 | reg_position = fci->frame + PROC_FREG_OFFSET (proc_desc); |
| 1168 | |
| 1169 | /* The freg_offset points to where the first *double* register |
| 1170 | is saved. So skip to the high-order word. */ |
| 1171 | if (!GDB_TARGET_IS_MIPS64) |
| 1172 | reg_position += MIPS_SAVED_REGSIZE; |
| 1173 | |
| 1174 | /* Fill in the offsets for the float registers which float_mask says |
| 1175 | were saved. */ |
| 1176 | for (ireg = MIPS_NUMREGS - 1; float_mask; --ireg, float_mask <<= 1) |
| 1177 | if (float_mask & 0x80000000) |
| 1178 | { |
| 1179 | fci->saved_regs[FP0_REGNUM + ireg] = reg_position; |
| 1180 | reg_position -= MIPS_SAVED_REGSIZE; |
| 1181 | } |
| 1182 | |
| 1183 | fci->saved_regs[PC_REGNUM] = fci->saved_regs[RA_REGNUM]; |
| 1184 | } |
| 1185 | |
| 1186 | static CORE_ADDR |
| 1187 | read_next_frame_reg (fi, regno) |
| 1188 | struct frame_info *fi; |
| 1189 | int regno; |
| 1190 | { |
| 1191 | for (; fi; fi = fi->next) |
| 1192 | { |
| 1193 | /* We have to get the saved sp from the sigcontext |
| 1194 | if it is a signal handler frame. */ |
| 1195 | if (regno == SP_REGNUM && !fi->signal_handler_caller) |
| 1196 | return fi->frame; |
| 1197 | else |
| 1198 | { |
| 1199 | if (fi->saved_regs == NULL) |
| 1200 | mips_find_saved_regs (fi); |
| 1201 | if (fi->saved_regs[regno]) |
| 1202 | return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE); |
| 1203 | } |
| 1204 | } |
| 1205 | return read_register (regno); |
| 1206 | } |
| 1207 | |
| 1208 | /* mips_addr_bits_remove - remove useless address bits */ |
| 1209 | |
| 1210 | CORE_ADDR |
| 1211 | mips_addr_bits_remove (addr) |
| 1212 | CORE_ADDR addr; |
| 1213 | { |
| 1214 | #if GDB_TARGET_IS_MIPS64 |
| 1215 | if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff)) |
| 1216 | { |
| 1217 | /* This hack is a work-around for existing boards using PMON, |
| 1218 | the simulator, and any other 64-bit targets that doesn't have |
| 1219 | true 64-bit addressing. On these targets, the upper 32 bits |
| 1220 | of addresses are ignored by the hardware. Thus, the PC or SP |
| 1221 | are likely to have been sign extended to all 1s by instruction |
| 1222 | sequences that load 32-bit addresses. For example, a typical |
| 1223 | piece of code that loads an address is this: |
| 1224 | lui $r2, <upper 16 bits> |
| 1225 | ori $r2, <lower 16 bits> |
| 1226 | But the lui sign-extends the value such that the upper 32 bits |
| 1227 | may be all 1s. The workaround is simply to mask off these bits. |
| 1228 | In the future, gcc may be changed to support true 64-bit |
| 1229 | addressing, and this masking will have to be disabled. */ |
| 1230 | addr &= (CORE_ADDR) 0xffffffff; |
| 1231 | } |
| 1232 | #else |
| 1233 | /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf), |
| 1234 | BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits. |
| 1235 | So we still have to mask off useless bits from addresses. */ |
| 1236 | addr &= (CORE_ADDR) 0xffffffff; |
| 1237 | #endif |
| 1238 | |
| 1239 | return addr; |
| 1240 | } |
| 1241 | |
| 1242 | void |
| 1243 | mips_init_frame_pc_first (fromleaf, prev) |
| 1244 | int fromleaf; |
| 1245 | struct frame_info *prev; |
| 1246 | { |
| 1247 | CORE_ADDR pc, tmp; |
| 1248 | |
| 1249 | pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : |
| 1250 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); |
| 1251 | tmp = mips_skip_stub (pc); |
| 1252 | prev->pc = tmp ? tmp : pc; |
| 1253 | } |
| 1254 | |
| 1255 | |
| 1256 | CORE_ADDR |
| 1257 | mips_frame_saved_pc (frame) |
| 1258 | struct frame_info *frame; |
| 1259 | { |
| 1260 | CORE_ADDR saved_pc; |
| 1261 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
| 1262 | /* We have to get the saved pc from the sigcontext |
| 1263 | if it is a signal handler frame. */ |
| 1264 | int pcreg = frame->signal_handler_caller ? PC_REGNUM |
| 1265 | : (proc_desc ? PROC_PC_REG (proc_desc) : RA_REGNUM); |
| 1266 | |
| 1267 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
| 1268 | saved_pc = read_memory_integer (frame->frame - MIPS_SAVED_REGSIZE, MIPS_SAVED_REGSIZE); |
| 1269 | else |
| 1270 | saved_pc = read_next_frame_reg (frame, pcreg); |
| 1271 | |
| 1272 | return ADDR_BITS_REMOVE (saved_pc); |
| 1273 | } |
| 1274 | |
| 1275 | static struct mips_extra_func_info temp_proc_desc; |
| 1276 | static CORE_ADDR temp_saved_regs[NUM_REGS]; |
| 1277 | |
| 1278 | /* Set a register's saved stack address in temp_saved_regs. If an address |
| 1279 | has already been set for this register, do nothing; this way we will |
| 1280 | only recognize the first save of a given register in a function prologue. |
| 1281 | This is a helper function for mips{16,32}_heuristic_proc_desc. */ |
| 1282 | |
| 1283 | static void |
| 1284 | set_reg_offset (regno, offset) |
| 1285 | int regno; |
| 1286 | CORE_ADDR offset; |
| 1287 | { |
| 1288 | if (temp_saved_regs[regno] == 0) |
| 1289 | temp_saved_regs[regno] = offset; |
| 1290 | } |
| 1291 | |
| 1292 | |
| 1293 | /* Test whether the PC points to the return instruction at the |
| 1294 | end of a function. */ |
| 1295 | |
| 1296 | static int |
| 1297 | mips_about_to_return (pc) |
| 1298 | CORE_ADDR pc; |
| 1299 | { |
| 1300 | if (pc_is_mips16 (pc)) |
| 1301 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
| 1302 | generates a "jr $ra"; other times it generates code to load |
| 1303 | the return address from the stack to an accessible register (such |
| 1304 | as $a3), then a "jr" using that register. This second case |
| 1305 | is almost impossible to distinguish from an indirect jump |
| 1306 | used for switch statements, so we don't even try. */ |
| 1307 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ |
| 1308 | else |
| 1309 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ |
| 1310 | } |
| 1311 | |
| 1312 | |
| 1313 | /* This fencepost looks highly suspicious to me. Removing it also |
| 1314 | seems suspicious as it could affect remote debugging across serial |
| 1315 | lines. */ |
| 1316 | |
| 1317 | static CORE_ADDR |
| 1318 | heuristic_proc_start (pc) |
| 1319 | CORE_ADDR pc; |
| 1320 | { |
| 1321 | CORE_ADDR start_pc; |
| 1322 | CORE_ADDR fence; |
| 1323 | int instlen; |
| 1324 | int seen_adjsp = 0; |
| 1325 | |
| 1326 | pc = ADDR_BITS_REMOVE (pc); |
| 1327 | start_pc = pc; |
| 1328 | fence = start_pc - heuristic_fence_post; |
| 1329 | if (start_pc == 0) |
| 1330 | return 0; |
| 1331 | |
| 1332 | if (heuristic_fence_post == UINT_MAX |
| 1333 | || fence < VM_MIN_ADDRESS) |
| 1334 | fence = VM_MIN_ADDRESS; |
| 1335 | |
| 1336 | instlen = pc_is_mips16 (pc) ? MIPS16_INSTLEN : MIPS_INSTLEN; |
| 1337 | |
| 1338 | /* search back for previous return */ |
| 1339 | for (start_pc -= instlen;; start_pc -= instlen) |
| 1340 | if (start_pc < fence) |
| 1341 | { |
| 1342 | /* It's not clear to me why we reach this point when |
| 1343 | stop_soon_quietly, but with this test, at least we |
| 1344 | don't print out warnings for every child forked (eg, on |
| 1345 | decstation). 22apr93 rich@cygnus.com. */ |
| 1346 | if (!stop_soon_quietly) |
| 1347 | { |
| 1348 | static int blurb_printed = 0; |
| 1349 | |
| 1350 | warning ("Warning: GDB can't find the start of the function at 0x%s.", |
| 1351 | paddr_nz (pc)); |
| 1352 | |
| 1353 | if (!blurb_printed) |
| 1354 | { |
| 1355 | /* This actually happens frequently in embedded |
| 1356 | development, when you first connect to a board |
| 1357 | and your stack pointer and pc are nowhere in |
| 1358 | particular. This message needs to give people |
| 1359 | in that situation enough information to |
| 1360 | determine that it's no big deal. */ |
| 1361 | printf_filtered ("\n\ |
| 1362 | GDB is unable to find the start of the function at 0x%s\n\ |
| 1363 | and thus can't determine the size of that function's stack frame.\n\ |
| 1364 | This means that GDB may be unable to access that stack frame, or\n\ |
| 1365 | the frames below it.\n\ |
| 1366 | This problem is most likely caused by an invalid program counter or\n\ |
| 1367 | stack pointer.\n\ |
| 1368 | However, if you think GDB should simply search farther back\n\ |
| 1369 | from 0x%s for code which looks like the beginning of a\n\ |
| 1370 | function, you can increase the range of the search using the `set\n\ |
| 1371 | heuristic-fence-post' command.\n", |
| 1372 | paddr_nz (pc), paddr_nz (pc)); |
| 1373 | blurb_printed = 1; |
| 1374 | } |
| 1375 | } |
| 1376 | |
| 1377 | return 0; |
| 1378 | } |
| 1379 | else if (pc_is_mips16 (start_pc)) |
| 1380 | { |
| 1381 | unsigned short inst; |
| 1382 | |
| 1383 | /* On MIPS16, any one of the following is likely to be the |
| 1384 | start of a function: |
| 1385 | entry |
| 1386 | addiu sp,-n |
| 1387 | daddiu sp,-n |
| 1388 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ |
| 1389 | inst = mips_fetch_instruction (start_pc); |
| 1390 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
| 1391 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ |
| 1392 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ |
| 1393 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ |
| 1394 | break; |
| 1395 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
| 1396 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
| 1397 | seen_adjsp = 1; |
| 1398 | else |
| 1399 | seen_adjsp = 0; |
| 1400 | } |
| 1401 | else if (mips_about_to_return (start_pc)) |
| 1402 | { |
| 1403 | start_pc += 2 * MIPS_INSTLEN; /* skip return, and its delay slot */ |
| 1404 | break; |
| 1405 | } |
| 1406 | |
| 1407 | #if 0 |
| 1408 | /* skip nops (usually 1) 0 - is this */ |
| 1409 | while (start_pc < pc && read_memory_integer (start_pc, MIPS_INSTLEN) == 0) |
| 1410 | start_pc += MIPS_INSTLEN; |
| 1411 | #endif |
| 1412 | return start_pc; |
| 1413 | } |
| 1414 | |
| 1415 | /* Fetch the immediate value from a MIPS16 instruction. |
| 1416 | If the previous instruction was an EXTEND, use it to extend |
| 1417 | the upper bits of the immediate value. This is a helper function |
| 1418 | for mips16_heuristic_proc_desc. */ |
| 1419 | |
| 1420 | static int |
| 1421 | mips16_get_imm (prev_inst, inst, nbits, scale, is_signed) |
| 1422 | unsigned short prev_inst; /* previous instruction */ |
| 1423 | unsigned short inst; /* current instruction */ |
| 1424 | int nbits; /* number of bits in imm field */ |
| 1425 | int scale; /* scale factor to be applied to imm */ |
| 1426 | int is_signed; /* is the imm field signed? */ |
| 1427 | { |
| 1428 | int offset; |
| 1429 | |
| 1430 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
| 1431 | { |
| 1432 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); |
| 1433 | if (offset & 0x8000) /* check for negative extend */ |
| 1434 | offset = 0 - (0x10000 - (offset & 0xffff)); |
| 1435 | return offset | (inst & 0x1f); |
| 1436 | } |
| 1437 | else |
| 1438 | { |
| 1439 | int max_imm = 1 << nbits; |
| 1440 | int mask = max_imm - 1; |
| 1441 | int sign_bit = max_imm >> 1; |
| 1442 | |
| 1443 | offset = inst & mask; |
| 1444 | if (is_signed && (offset & sign_bit)) |
| 1445 | offset = 0 - (max_imm - offset); |
| 1446 | return offset * scale; |
| 1447 | } |
| 1448 | } |
| 1449 | |
| 1450 | |
| 1451 | /* Fill in values in temp_proc_desc based on the MIPS16 instruction |
| 1452 | stream from start_pc to limit_pc. */ |
| 1453 | |
| 1454 | static void |
| 1455 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp) |
| 1456 | CORE_ADDR start_pc, limit_pc; |
| 1457 | struct frame_info *next_frame; |
| 1458 | CORE_ADDR sp; |
| 1459 | { |
| 1460 | CORE_ADDR cur_pc; |
| 1461 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ |
| 1462 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ |
| 1463 | unsigned inst = 0; /* current instruction */ |
| 1464 | unsigned entry_inst = 0; /* the entry instruction */ |
| 1465 | int reg, offset; |
| 1466 | |
| 1467 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; /* size of stack frame */ |
| 1468 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
| 1469 | |
| 1470 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSTLEN) |
| 1471 | { |
| 1472 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
| 1473 | the immediate offset extension from it in mips16_get_imm. */ |
| 1474 | prev_inst = inst; |
| 1475 | |
| 1476 | /* Fetch and decode the instruction. */ |
| 1477 | inst = (unsigned short) mips_fetch_instruction (cur_pc); |
| 1478 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
| 1479 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
| 1480 | { |
| 1481 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); |
| 1482 | if (offset < 0) /* negative stack adjustment? */ |
| 1483 | PROC_FRAME_OFFSET (&temp_proc_desc) -= offset; |
| 1484 | else |
| 1485 | /* Exit loop if a positive stack adjustment is found, which |
| 1486 | usually means that the stack cleanup code in the function |
| 1487 | epilogue is reached. */ |
| 1488 | break; |
| 1489 | } |
| 1490 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
| 1491 | { |
| 1492 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
| 1493 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; |
| 1494 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
| 1495 | set_reg_offset (reg, sp + offset); |
| 1496 | } |
| 1497 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
| 1498 | { |
| 1499 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); |
| 1500 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; |
| 1501 | PROC_REG_MASK (&temp_proc_desc) |= (1 << reg); |
| 1502 | set_reg_offset (reg, sp + offset); |
| 1503 | } |
| 1504 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ |
| 1505 | { |
| 1506 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
| 1507 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
| 1508 | set_reg_offset (RA_REGNUM, sp + offset); |
| 1509 | } |
| 1510 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
| 1511 | { |
| 1512 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); |
| 1513 | PROC_REG_MASK (&temp_proc_desc) |= (1 << RA_REGNUM); |
| 1514 | set_reg_offset (RA_REGNUM, sp + offset); |
| 1515 | } |
| 1516 | else if (inst == 0x673d) /* move $s1, $sp */ |
| 1517 | { |
| 1518 | frame_addr = sp; |
| 1519 | PROC_FRAME_REG (&temp_proc_desc) = 17; |
| 1520 | } |
| 1521 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ |
| 1522 | { |
| 1523 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
| 1524 | frame_addr = sp + offset; |
| 1525 | PROC_FRAME_REG (&temp_proc_desc) = 17; |
| 1526 | PROC_FRAME_ADJUST (&temp_proc_desc) = offset; |
| 1527 | } |
| 1528 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ |
| 1529 | { |
| 1530 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); |
| 1531 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; |
| 1532 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
| 1533 | set_reg_offset (reg, frame_addr + offset); |
| 1534 | } |
| 1535 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ |
| 1536 | { |
| 1537 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); |
| 1538 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; |
| 1539 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
| 1540 | set_reg_offset (reg, frame_addr + offset); |
| 1541 | } |
| 1542 | else if ((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ |
| 1543 | entry_inst = inst; /* save for later processing */ |
| 1544 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
| 1545 | cur_pc += MIPS16_INSTLEN; /* 32-bit instruction */ |
| 1546 | } |
| 1547 | |
| 1548 | /* The entry instruction is typically the first instruction in a function, |
| 1549 | and it stores registers at offsets relative to the value of the old SP |
| 1550 | (before the prologue). But the value of the sp parameter to this |
| 1551 | function is the new SP (after the prologue has been executed). So we |
| 1552 | can't calculate those offsets until we've seen the entire prologue, |
| 1553 | and can calculate what the old SP must have been. */ |
| 1554 | if (entry_inst != 0) |
| 1555 | { |
| 1556 | int areg_count = (entry_inst >> 8) & 7; |
| 1557 | int sreg_count = (entry_inst >> 6) & 3; |
| 1558 | |
| 1559 | /* The entry instruction always subtracts 32 from the SP. */ |
| 1560 | PROC_FRAME_OFFSET (&temp_proc_desc) += 32; |
| 1561 | |
| 1562 | /* Now we can calculate what the SP must have been at the |
| 1563 | start of the function prologue. */ |
| 1564 | sp += PROC_FRAME_OFFSET (&temp_proc_desc); |
| 1565 | |
| 1566 | /* Check if a0-a3 were saved in the caller's argument save area. */ |
| 1567 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) |
| 1568 | { |
| 1569 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
| 1570 | set_reg_offset (reg, sp + offset); |
| 1571 | offset += MIPS_SAVED_REGSIZE; |
| 1572 | } |
| 1573 | |
| 1574 | /* Check if the ra register was pushed on the stack. */ |
| 1575 | offset = -4; |
| 1576 | if (entry_inst & 0x20) |
| 1577 | { |
| 1578 | PROC_REG_MASK (&temp_proc_desc) |= 1 << RA_REGNUM; |
| 1579 | set_reg_offset (RA_REGNUM, sp + offset); |
| 1580 | offset -= MIPS_SAVED_REGSIZE; |
| 1581 | } |
| 1582 | |
| 1583 | /* Check if the s0 and s1 registers were pushed on the stack. */ |
| 1584 | for (reg = 16; reg < sreg_count + 16; reg++) |
| 1585 | { |
| 1586 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
| 1587 | set_reg_offset (reg, sp + offset); |
| 1588 | offset -= MIPS_SAVED_REGSIZE; |
| 1589 | } |
| 1590 | } |
| 1591 | } |
| 1592 | |
| 1593 | static void |
| 1594 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp) |
| 1595 | CORE_ADDR start_pc, limit_pc; |
| 1596 | struct frame_info *next_frame; |
| 1597 | CORE_ADDR sp; |
| 1598 | { |
| 1599 | CORE_ADDR cur_pc; |
| 1600 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ |
| 1601 | restart: |
| 1602 | memset (temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
| 1603 | PROC_FRAME_OFFSET (&temp_proc_desc) = 0; |
| 1604 | PROC_FRAME_ADJUST (&temp_proc_desc) = 0; /* offset of FP from SP */ |
| 1605 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSTLEN) |
| 1606 | { |
| 1607 | unsigned long inst, high_word, low_word; |
| 1608 | int reg; |
| 1609 | |
| 1610 | /* Fetch the instruction. */ |
| 1611 | inst = (unsigned long) mips_fetch_instruction (cur_pc); |
| 1612 | |
| 1613 | /* Save some code by pre-extracting some useful fields. */ |
| 1614 | high_word = (inst >> 16) & 0xffff; |
| 1615 | low_word = inst & 0xffff; |
| 1616 | reg = high_word & 0x1f; |
| 1617 | |
| 1618 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
| 1619 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
| 1620 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ |
| 1621 | { |
| 1622 | if (low_word & 0x8000) /* negative stack adjustment? */ |
| 1623 | PROC_FRAME_OFFSET (&temp_proc_desc) += 0x10000 - low_word; |
| 1624 | else |
| 1625 | /* Exit loop if a positive stack adjustment is found, which |
| 1626 | usually means that the stack cleanup code in the function |
| 1627 | epilogue is reached. */ |
| 1628 | break; |
| 1629 | } |
| 1630 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
| 1631 | { |
| 1632 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
| 1633 | set_reg_offset (reg, sp + low_word); |
| 1634 | } |
| 1635 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
| 1636 | { |
| 1637 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra, |
| 1638 | but the register size used is only 32 bits. Make the address |
| 1639 | for the saved register point to the lower 32 bits. */ |
| 1640 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
| 1641 | set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE); |
| 1642 | } |
| 1643 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ |
| 1644 | { |
| 1645 | /* Old gcc frame, r30 is virtual frame pointer. */ |
| 1646 | if ((long) low_word != PROC_FRAME_OFFSET (&temp_proc_desc)) |
| 1647 | frame_addr = sp + low_word; |
| 1648 | else if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
| 1649 | { |
| 1650 | unsigned alloca_adjust; |
| 1651 | PROC_FRAME_REG (&temp_proc_desc) = 30; |
| 1652 | frame_addr = read_next_frame_reg (next_frame, 30); |
| 1653 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
| 1654 | if (alloca_adjust > 0) |
| 1655 | { |
| 1656 | /* FP > SP + frame_size. This may be because |
| 1657 | * of an alloca or somethings similar. |
| 1658 | * Fix sp to "pre-alloca" value, and try again. |
| 1659 | */ |
| 1660 | sp += alloca_adjust; |
| 1661 | goto restart; |
| 1662 | } |
| 1663 | } |
| 1664 | } |
| 1665 | /* move $30,$sp. With different versions of gas this will be either |
| 1666 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. |
| 1667 | Accept any one of these. */ |
| 1668 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
| 1669 | { |
| 1670 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ |
| 1671 | if (PROC_FRAME_REG (&temp_proc_desc) == SP_REGNUM) |
| 1672 | { |
| 1673 | unsigned alloca_adjust; |
| 1674 | PROC_FRAME_REG (&temp_proc_desc) = 30; |
| 1675 | frame_addr = read_next_frame_reg (next_frame, 30); |
| 1676 | alloca_adjust = (unsigned) (frame_addr - sp); |
| 1677 | if (alloca_adjust > 0) |
| 1678 | { |
| 1679 | /* FP > SP + frame_size. This may be because |
| 1680 | * of an alloca or somethings similar. |
| 1681 | * Fix sp to "pre-alloca" value, and try again. |
| 1682 | */ |
| 1683 | sp += alloca_adjust; |
| 1684 | goto restart; |
| 1685 | } |
| 1686 | } |
| 1687 | } |
| 1688 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ |
| 1689 | { |
| 1690 | PROC_REG_MASK (&temp_proc_desc) |= 1 << reg; |
| 1691 | set_reg_offset (reg, frame_addr + low_word); |
| 1692 | } |
| 1693 | } |
| 1694 | } |
| 1695 | |
| 1696 | static mips_extra_func_info_t |
| 1697 | heuristic_proc_desc (start_pc, limit_pc, next_frame) |
| 1698 | CORE_ADDR start_pc, limit_pc; |
| 1699 | struct frame_info *next_frame; |
| 1700 | { |
| 1701 | CORE_ADDR sp = read_next_frame_reg (next_frame, SP_REGNUM); |
| 1702 | |
| 1703 | if (start_pc == 0) |
| 1704 | return NULL; |
| 1705 | memset (&temp_proc_desc, '\0', sizeof (temp_proc_desc)); |
| 1706 | memset (&temp_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); |
| 1707 | PROC_LOW_ADDR (&temp_proc_desc) = start_pc; |
| 1708 | PROC_FRAME_REG (&temp_proc_desc) = SP_REGNUM; |
| 1709 | PROC_PC_REG (&temp_proc_desc) = RA_REGNUM; |
| 1710 | |
| 1711 | if (start_pc + 200 < limit_pc) |
| 1712 | limit_pc = start_pc + 200; |
| 1713 | if (pc_is_mips16 (start_pc)) |
| 1714 | mips16_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); |
| 1715 | else |
| 1716 | mips32_heuristic_proc_desc (start_pc, limit_pc, next_frame, sp); |
| 1717 | return &temp_proc_desc; |
| 1718 | } |
| 1719 | |
| 1720 | static mips_extra_func_info_t |
| 1721 | non_heuristic_proc_desc (pc, addrptr) |
| 1722 | CORE_ADDR pc; |
| 1723 | CORE_ADDR *addrptr; |
| 1724 | { |
| 1725 | CORE_ADDR startaddr; |
| 1726 | mips_extra_func_info_t proc_desc; |
| 1727 | struct block *b = block_for_pc (pc); |
| 1728 | struct symbol *sym; |
| 1729 | |
| 1730 | find_pc_partial_function (pc, NULL, &startaddr, NULL); |
| 1731 | if (addrptr) |
| 1732 | *addrptr = startaddr; |
| 1733 | if (b == NULL || PC_IN_CALL_DUMMY (pc, 0, 0)) |
| 1734 | sym = NULL; |
| 1735 | else |
| 1736 | { |
| 1737 | if (startaddr > BLOCK_START (b)) |
| 1738 | /* This is the "pathological" case referred to in a comment in |
| 1739 | print_frame_info. It might be better to move this check into |
| 1740 | symbol reading. */ |
| 1741 | sym = NULL; |
| 1742 | else |
| 1743 | sym = lookup_symbol (MIPS_EFI_SYMBOL_NAME, b, LABEL_NAMESPACE, 0, NULL); |
| 1744 | } |
| 1745 | |
| 1746 | /* If we never found a PDR for this function in symbol reading, then |
| 1747 | examine prologues to find the information. */ |
| 1748 | if (sym) |
| 1749 | { |
| 1750 | proc_desc = (mips_extra_func_info_t) SYMBOL_VALUE (sym); |
| 1751 | if (PROC_FRAME_REG (proc_desc) == -1) |
| 1752 | return NULL; |
| 1753 | else |
| 1754 | return proc_desc; |
| 1755 | } |
| 1756 | else |
| 1757 | return NULL; |
| 1758 | } |
| 1759 | |
| 1760 | |
| 1761 | static mips_extra_func_info_t |
| 1762 | find_proc_desc (pc, next_frame) |
| 1763 | CORE_ADDR pc; |
| 1764 | struct frame_info *next_frame; |
| 1765 | { |
| 1766 | mips_extra_func_info_t proc_desc; |
| 1767 | CORE_ADDR startaddr; |
| 1768 | |
| 1769 | proc_desc = non_heuristic_proc_desc (pc, &startaddr); |
| 1770 | |
| 1771 | if (proc_desc) |
| 1772 | { |
| 1773 | /* IF this is the topmost frame AND |
| 1774 | * (this proc does not have debugging information OR |
| 1775 | * the PC is in the procedure prologue) |
| 1776 | * THEN create a "heuristic" proc_desc (by analyzing |
| 1777 | * the actual code) to replace the "official" proc_desc. |
| 1778 | */ |
| 1779 | if (next_frame == NULL) |
| 1780 | { |
| 1781 | struct symtab_and_line val; |
| 1782 | struct symbol *proc_symbol = |
| 1783 | PROC_DESC_IS_DUMMY (proc_desc) ? 0 : PROC_SYMBOL (proc_desc); |
| 1784 | |
| 1785 | if (proc_symbol) |
| 1786 | { |
| 1787 | val = find_pc_line (BLOCK_START |
| 1788 | (SYMBOL_BLOCK_VALUE (proc_symbol)), |
| 1789 | 0); |
| 1790 | val.pc = val.end ? val.end : pc; |
| 1791 | } |
| 1792 | if (!proc_symbol || pc < val.pc) |
| 1793 | { |
| 1794 | mips_extra_func_info_t found_heuristic = |
| 1795 | heuristic_proc_desc (PROC_LOW_ADDR (proc_desc), |
| 1796 | pc, next_frame); |
| 1797 | if (found_heuristic) |
| 1798 | proc_desc = found_heuristic; |
| 1799 | } |
| 1800 | } |
| 1801 | } |
| 1802 | else |
| 1803 | { |
| 1804 | /* Is linked_proc_desc_table really necessary? It only seems to be used |
| 1805 | by procedure call dummys. However, the procedures being called ought |
| 1806 | to have their own proc_descs, and even if they don't, |
| 1807 | heuristic_proc_desc knows how to create them! */ |
| 1808 | |
| 1809 | register struct linked_proc_info *link; |
| 1810 | |
| 1811 | for (link = linked_proc_desc_table; link; link = link->next) |
| 1812 | if (PROC_LOW_ADDR (&link->info) <= pc |
| 1813 | && PROC_HIGH_ADDR (&link->info) > pc) |
| 1814 | return &link->info; |
| 1815 | |
| 1816 | if (startaddr == 0) |
| 1817 | startaddr = heuristic_proc_start (pc); |
| 1818 | |
| 1819 | proc_desc = |
| 1820 | heuristic_proc_desc (startaddr, pc, next_frame); |
| 1821 | } |
| 1822 | return proc_desc; |
| 1823 | } |
| 1824 | |
| 1825 | static CORE_ADDR |
| 1826 | get_frame_pointer (frame, proc_desc) |
| 1827 | struct frame_info *frame; |
| 1828 | mips_extra_func_info_t proc_desc; |
| 1829 | { |
| 1830 | return ADDR_BITS_REMOVE ( |
| 1831 | read_next_frame_reg (frame, PROC_FRAME_REG (proc_desc)) + |
| 1832 | PROC_FRAME_OFFSET (proc_desc) - PROC_FRAME_ADJUST (proc_desc)); |
| 1833 | } |
| 1834 | |
| 1835 | mips_extra_func_info_t cached_proc_desc; |
| 1836 | |
| 1837 | CORE_ADDR |
| 1838 | mips_frame_chain (frame) |
| 1839 | struct frame_info *frame; |
| 1840 | { |
| 1841 | mips_extra_func_info_t proc_desc; |
| 1842 | CORE_ADDR tmp; |
| 1843 | CORE_ADDR saved_pc = FRAME_SAVED_PC (frame); |
| 1844 | |
| 1845 | if (saved_pc == 0 || inside_entry_file (saved_pc)) |
| 1846 | return 0; |
| 1847 | |
| 1848 | /* Check if the PC is inside a call stub. If it is, fetch the |
| 1849 | PC of the caller of that stub. */ |
| 1850 | if ((tmp = mips_skip_stub (saved_pc)) != 0) |
| 1851 | saved_pc = tmp; |
| 1852 | |
| 1853 | /* Look up the procedure descriptor for this PC. */ |
| 1854 | proc_desc = find_proc_desc (saved_pc, frame); |
| 1855 | if (!proc_desc) |
| 1856 | return 0; |
| 1857 | |
| 1858 | cached_proc_desc = proc_desc; |
| 1859 | |
| 1860 | /* If no frame pointer and frame size is zero, we must be at end |
| 1861 | of stack (or otherwise hosed). If we don't check frame size, |
| 1862 | we loop forever if we see a zero size frame. */ |
| 1863 | if (PROC_FRAME_REG (proc_desc) == SP_REGNUM |
| 1864 | && PROC_FRAME_OFFSET (proc_desc) == 0 |
| 1865 | /* The previous frame from a sigtramp frame might be frameless |
| 1866 | and have frame size zero. */ |
| 1867 | && !frame->signal_handler_caller) |
| 1868 | return 0; |
| 1869 | else |
| 1870 | return get_frame_pointer (frame, proc_desc); |
| 1871 | } |
| 1872 | |
| 1873 | void |
| 1874 | mips_init_extra_frame_info (fromleaf, fci) |
| 1875 | int fromleaf; |
| 1876 | struct frame_info *fci; |
| 1877 | { |
| 1878 | int regnum; |
| 1879 | |
| 1880 | /* Use proc_desc calculated in frame_chain */ |
| 1881 | mips_extra_func_info_t proc_desc = |
| 1882 | fci->next ? cached_proc_desc : find_proc_desc (fci->pc, fci->next); |
| 1883 | |
| 1884 | fci->extra_info = (struct frame_extra_info *) |
| 1885 | frame_obstack_alloc (sizeof (struct frame_extra_info)); |
| 1886 | |
| 1887 | fci->saved_regs = NULL; |
| 1888 | fci->extra_info->proc_desc = |
| 1889 | proc_desc == &temp_proc_desc ? 0 : proc_desc; |
| 1890 | if (proc_desc) |
| 1891 | { |
| 1892 | /* Fixup frame-pointer - only needed for top frame */ |
| 1893 | /* This may not be quite right, if proc has a real frame register. |
| 1894 | Get the value of the frame relative sp, procedure might have been |
| 1895 | interrupted by a signal at it's very start. */ |
| 1896 | if (fci->pc == PROC_LOW_ADDR (proc_desc) |
| 1897 | && !PROC_DESC_IS_DUMMY (proc_desc)) |
| 1898 | fci->frame = read_next_frame_reg (fci->next, SP_REGNUM); |
| 1899 | else |
| 1900 | fci->frame = get_frame_pointer (fci->next, proc_desc); |
| 1901 | |
| 1902 | if (proc_desc == &temp_proc_desc) |
| 1903 | { |
| 1904 | char *name; |
| 1905 | |
| 1906 | /* Do not set the saved registers for a sigtramp frame, |
| 1907 | mips_find_saved_registers will do that for us. |
| 1908 | We can't use fci->signal_handler_caller, it is not yet set. */ |
| 1909 | find_pc_partial_function (fci->pc, &name, |
| 1910 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
| 1911 | if (!IN_SIGTRAMP (fci->pc, name)) |
| 1912 | { |
| 1913 | frame_saved_regs_zalloc (fci); |
| 1914 | memcpy (fci->saved_regs, temp_saved_regs, SIZEOF_FRAME_SAVED_REGS); |
| 1915 | fci->saved_regs[PC_REGNUM] |
| 1916 | = fci->saved_regs[RA_REGNUM]; |
| 1917 | } |
| 1918 | } |
| 1919 | |
| 1920 | /* hack: if argument regs are saved, guess these contain args */ |
| 1921 | /* assume we can't tell how many args for now */ |
| 1922 | fci->extra_info->num_args = -1; |
| 1923 | for (regnum = MIPS_LAST_ARG_REGNUM; regnum >= A0_REGNUM; regnum--) |
| 1924 | { |
| 1925 | if (PROC_REG_MASK (proc_desc) & (1 << regnum)) |
| 1926 | { |
| 1927 | fci->extra_info->num_args = regnum - A0_REGNUM + 1; |
| 1928 | break; |
| 1929 | } |
| 1930 | } |
| 1931 | } |
| 1932 | } |
| 1933 | |
| 1934 | /* MIPS stack frames are almost impenetrable. When execution stops, |
| 1935 | we basically have to look at symbol information for the function |
| 1936 | that we stopped in, which tells us *which* register (if any) is |
| 1937 | the base of the frame pointer, and what offset from that register |
| 1938 | the frame itself is at. |
| 1939 | |
| 1940 | This presents a problem when trying to examine a stack in memory |
| 1941 | (that isn't executing at the moment), using the "frame" command. We |
| 1942 | don't have a PC, nor do we have any registers except SP. |
| 1943 | |
| 1944 | This routine takes two arguments, SP and PC, and tries to make the |
| 1945 | cached frames look as if these two arguments defined a frame on the |
| 1946 | cache. This allows the rest of info frame to extract the important |
| 1947 | arguments without difficulty. */ |
| 1948 | |
| 1949 | struct frame_info * |
| 1950 | setup_arbitrary_frame (argc, argv) |
| 1951 | int argc; |
| 1952 | CORE_ADDR *argv; |
| 1953 | { |
| 1954 | if (argc != 2) |
| 1955 | error ("MIPS frame specifications require two arguments: sp and pc"); |
| 1956 | |
| 1957 | return create_new_frame (argv[0], argv[1]); |
| 1958 | } |
| 1959 | |
| 1960 | /* |
| 1961 | * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack? |
| 1962 | * |
| 1963 | * For n32 ABI, eight. |
| 1964 | * For all others, he same as the size of a general register. |
| 1965 | */ |
| 1966 | #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32 |
| 1967 | #define MIPS_NABI32 1 |
| 1968 | #define STACK_ARGSIZE 8 |
| 1969 | #else |
| 1970 | #define MIPS_NABI32 0 |
| 1971 | #define STACK_ARGSIZE MIPS_SAVED_REGSIZE |
| 1972 | #endif |
| 1973 | |
| 1974 | CORE_ADDR |
| 1975 | mips_push_arguments (nargs, args, sp, struct_return, struct_addr) |
| 1976 | int nargs; |
| 1977 | value_ptr *args; |
| 1978 | CORE_ADDR sp; |
| 1979 | int struct_return; |
| 1980 | CORE_ADDR struct_addr; |
| 1981 | { |
| 1982 | int argreg; |
| 1983 | int float_argreg; |
| 1984 | int argnum; |
| 1985 | int len = 0; |
| 1986 | int stack_offset = 0; |
| 1987 | |
| 1988 | /* Macros to round N up or down to the next A boundary; A must be |
| 1989 | a power of two. */ |
| 1990 | #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) |
| 1991 | #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) |
| 1992 | |
| 1993 | /* First ensure that the stack and structure return address (if any) |
| 1994 | are properly aligned. The stack has to be at least 64-bit aligned |
| 1995 | even on 32-bit machines, because doubles must be 64-bit aligned. |
| 1996 | On at least one MIPS variant, stack frames need to be 128-bit |
| 1997 | aligned, so we round to this widest known alignment. */ |
| 1998 | sp = ROUND_DOWN (sp, 16); |
| 1999 | struct_addr = ROUND_DOWN (struct_addr, MIPS_SAVED_REGSIZE); |
| 2000 | |
| 2001 | /* Now make space on the stack for the args. We allocate more |
| 2002 | than necessary for EABI, because the first few arguments are |
| 2003 | passed in registers, but that's OK. */ |
| 2004 | for (argnum = 0; argnum < nargs; argnum++) |
| 2005 | len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_SAVED_REGSIZE); |
| 2006 | sp -= ROUND_UP (len, 16); |
| 2007 | |
| 2008 | /* Initialize the integer and float register pointers. */ |
| 2009 | argreg = A0_REGNUM; |
| 2010 | float_argreg = FPA0_REGNUM; |
| 2011 | |
| 2012 | /* the struct_return pointer occupies the first parameter-passing reg */ |
| 2013 | if (struct_return) |
| 2014 | write_register (argreg++, struct_addr); |
| 2015 | |
| 2016 | /* Now load as many as possible of the first arguments into |
| 2017 | registers, and push the rest onto the stack. Loop thru args |
| 2018 | from first to last. */ |
| 2019 | for (argnum = 0; argnum < nargs; argnum++) |
| 2020 | { |
| 2021 | char *val; |
| 2022 | char valbuf[MAX_REGISTER_RAW_SIZE]; |
| 2023 | value_ptr arg = args[argnum]; |
| 2024 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
| 2025 | int len = TYPE_LENGTH (arg_type); |
| 2026 | enum type_code typecode = TYPE_CODE (arg_type); |
| 2027 | |
| 2028 | /* The EABI passes structures that do not fit in a register by |
| 2029 | reference. In all other cases, pass the structure by value. */ |
| 2030 | if (MIPS_EABI && len > MIPS_SAVED_REGSIZE && |
| 2031 | (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
| 2032 | { |
| 2033 | store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg)); |
| 2034 | typecode = TYPE_CODE_PTR; |
| 2035 | len = MIPS_SAVED_REGSIZE; |
| 2036 | val = valbuf; |
| 2037 | } |
| 2038 | else |
| 2039 | val = (char *) VALUE_CONTENTS (arg); |
| 2040 | |
| 2041 | /* 32-bit ABIs always start floating point arguments in an |
| 2042 | even-numbered floating point register. */ |
| 2043 | if (!FP_REGISTER_DOUBLE && typecode == TYPE_CODE_FLT |
| 2044 | && (float_argreg & 1)) |
| 2045 | float_argreg++; |
| 2046 | |
| 2047 | /* Floating point arguments passed in registers have to be |
| 2048 | treated specially. On 32-bit architectures, doubles |
| 2049 | are passed in register pairs; the even register gets |
| 2050 | the low word, and the odd register gets the high word. |
| 2051 | On non-EABI processors, the first two floating point arguments are |
| 2052 | also copied to general registers, because MIPS16 functions |
| 2053 | don't use float registers for arguments. This duplication of |
| 2054 | arguments in general registers can't hurt non-MIPS16 functions |
| 2055 | because those registers are normally skipped. */ |
| 2056 | if (typecode == TYPE_CODE_FLT |
| 2057 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM |
| 2058 | && MIPS_FPU_TYPE != MIPS_FPU_NONE) |
| 2059 | { |
| 2060 | if (!FP_REGISTER_DOUBLE && len == 8) |
| 2061 | { |
| 2062 | int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; |
| 2063 | unsigned long regval; |
| 2064 | |
| 2065 | /* Write the low word of the double to the even register(s). */ |
| 2066 | regval = extract_unsigned_integer (val + low_offset, 4); |
| 2067 | write_register (float_argreg++, regval); |
| 2068 | if (!MIPS_EABI) |
| 2069 | write_register (argreg + 1, regval); |
| 2070 | |
| 2071 | /* Write the high word of the double to the odd register(s). */ |
| 2072 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
| 2073 | write_register (float_argreg++, regval); |
| 2074 | if (!MIPS_EABI) |
| 2075 | { |
| 2076 | write_register (argreg, regval); |
| 2077 | argreg += 2; |
| 2078 | } |
| 2079 | |
| 2080 | } |
| 2081 | else |
| 2082 | { |
| 2083 | /* This is a floating point value that fits entirely |
| 2084 | in a single register. */ |
| 2085 | /* On 32 bit ABI's the float_argreg is further adjusted |
| 2086 | above to ensure that it is even register aligned. */ |
| 2087 | CORE_ADDR regval = extract_address (val, len); |
| 2088 | write_register (float_argreg++, regval); |
| 2089 | if (!MIPS_EABI) |
| 2090 | { |
| 2091 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
| 2092 | registers for each argument. The below is (my |
| 2093 | guess) to ensure that the corresponding integer |
| 2094 | register has reserved the same space. */ |
| 2095 | write_register (argreg, regval); |
| 2096 | argreg += FP_REGISTER_DOUBLE ? 1 : 2; |
| 2097 | } |
| 2098 | } |
| 2099 | } |
| 2100 | else |
| 2101 | { |
| 2102 | /* Copy the argument to general registers or the stack in |
| 2103 | register-sized pieces. Large arguments are split between |
| 2104 | registers and stack. */ |
| 2105 | /* Note: structs whose size is not a multiple of MIPS_REGSIZE |
| 2106 | are treated specially: Irix cc passes them in registers |
| 2107 | where gcc sometimes puts them on the stack. For maximum |
| 2108 | compatibility, we will put them in both places. */ |
| 2109 | |
| 2110 | int odd_sized_struct = ((len > MIPS_SAVED_REGSIZE) && |
| 2111 | (len % MIPS_SAVED_REGSIZE != 0)); |
| 2112 | while (len > 0) |
| 2113 | { |
| 2114 | int partial_len = len < MIPS_SAVED_REGSIZE ? len : MIPS_SAVED_REGSIZE; |
| 2115 | |
| 2116 | if (argreg > MIPS_LAST_ARG_REGNUM || odd_sized_struct) |
| 2117 | { |
| 2118 | /* Write this portion of the argument to the stack. */ |
| 2119 | /* Should shorter than int integer values be |
| 2120 | promoted to int before being stored? */ |
| 2121 | |
| 2122 | int longword_offset = 0; |
| 2123 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 2124 | { |
| 2125 | if (STACK_ARGSIZE == 8 && |
| 2126 | (typecode == TYPE_CODE_INT || |
| 2127 | typecode == TYPE_CODE_PTR || |
| 2128 | typecode == TYPE_CODE_FLT) && len <= 4) |
| 2129 | longword_offset = STACK_ARGSIZE - len; |
| 2130 | else if ((typecode == TYPE_CODE_STRUCT || |
| 2131 | typecode == TYPE_CODE_UNION) && |
| 2132 | TYPE_LENGTH (arg_type) < STACK_ARGSIZE) |
| 2133 | longword_offset = STACK_ARGSIZE - len; |
| 2134 | } |
| 2135 | |
| 2136 | write_memory (sp + stack_offset + longword_offset, |
| 2137 | val, partial_len); |
| 2138 | } |
| 2139 | |
| 2140 | /* Note!!! This is NOT an else clause. |
| 2141 | Odd sized structs may go thru BOTH paths. */ |
| 2142 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
| 2143 | { |
| 2144 | CORE_ADDR regval = extract_address (val, partial_len); |
| 2145 | |
| 2146 | /* A non-floating-point argument being passed in a |
| 2147 | general register. If a struct or union, and if |
| 2148 | the remaining length is smaller than the register |
| 2149 | size, we have to adjust the register value on |
| 2150 | big endian targets. |
| 2151 | |
| 2152 | It does not seem to be necessary to do the |
| 2153 | same for integral types. |
| 2154 | |
| 2155 | Also don't do this adjustment on EABI and O64 |
| 2156 | binaries. */ |
| 2157 | |
| 2158 | if (!MIPS_EABI |
| 2159 | && MIPS_SAVED_REGSIZE < 8 |
| 2160 | && TARGET_BYTE_ORDER == BIG_ENDIAN |
| 2161 | && partial_len < MIPS_SAVED_REGSIZE |
| 2162 | && (typecode == TYPE_CODE_STRUCT || |
| 2163 | typecode == TYPE_CODE_UNION)) |
| 2164 | regval <<= ((MIPS_SAVED_REGSIZE - partial_len) * |
| 2165 | TARGET_CHAR_BIT); |
| 2166 | |
| 2167 | write_register (argreg, regval); |
| 2168 | argreg++; |
| 2169 | |
| 2170 | /* If this is the old ABI, prevent subsequent floating |
| 2171 | point arguments from being passed in floating point |
| 2172 | registers. */ |
| 2173 | if (!MIPS_EABI) |
| 2174 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; |
| 2175 | } |
| 2176 | |
| 2177 | len -= partial_len; |
| 2178 | val += partial_len; |
| 2179 | |
| 2180 | /* The offset onto the stack at which we will start |
| 2181 | copying parameters (after the registers are used up) |
| 2182 | begins at (4 * MIPS_REGSIZE) in the old ABI. This |
| 2183 | leaves room for the "home" area for register parameters. |
| 2184 | |
| 2185 | In the new EABI (and the NABI32), the 8 register parameters |
| 2186 | do not have "home" stack space reserved for them, so the |
| 2187 | stack offset does not get incremented until after |
| 2188 | we have used up the 8 parameter registers. */ |
| 2189 | |
| 2190 | if (!(MIPS_EABI || MIPS_NABI32) || |
| 2191 | argnum >= 8) |
| 2192 | stack_offset += ROUND_UP (partial_len, STACK_ARGSIZE); |
| 2193 | } |
| 2194 | } |
| 2195 | } |
| 2196 | |
| 2197 | /* Return adjusted stack pointer. */ |
| 2198 | return sp; |
| 2199 | } |
| 2200 | |
| 2201 | CORE_ADDR |
| 2202 | mips_push_return_address (pc, sp) |
| 2203 | CORE_ADDR pc; |
| 2204 | CORE_ADDR sp; |
| 2205 | { |
| 2206 | /* Set the return address register to point to the entry |
| 2207 | point of the program, where a breakpoint lies in wait. */ |
| 2208 | write_register (RA_REGNUM, CALL_DUMMY_ADDRESS ()); |
| 2209 | return sp; |
| 2210 | } |
| 2211 | |
| 2212 | static void |
| 2213 | mips_push_register (CORE_ADDR * sp, int regno) |
| 2214 | { |
| 2215 | char buffer[MAX_REGISTER_RAW_SIZE]; |
| 2216 | int regsize; |
| 2217 | int offset; |
| 2218 | if (MIPS_SAVED_REGSIZE < REGISTER_RAW_SIZE (regno)) |
| 2219 | { |
| 2220 | regsize = MIPS_SAVED_REGSIZE; |
| 2221 | offset = (TARGET_BYTE_ORDER == BIG_ENDIAN |
| 2222 | ? REGISTER_RAW_SIZE (regno) - MIPS_SAVED_REGSIZE |
| 2223 | : 0); |
| 2224 | } |
| 2225 | else |
| 2226 | { |
| 2227 | regsize = REGISTER_RAW_SIZE (regno); |
| 2228 | offset = 0; |
| 2229 | } |
| 2230 | *sp -= regsize; |
| 2231 | read_register_gen (regno, buffer); |
| 2232 | write_memory (*sp, buffer + offset, regsize); |
| 2233 | } |
| 2234 | |
| 2235 | /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */ |
| 2236 | #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1)) |
| 2237 | |
| 2238 | void |
| 2239 | mips_push_dummy_frame () |
| 2240 | { |
| 2241 | int ireg; |
| 2242 | struct linked_proc_info *link = (struct linked_proc_info *) |
| 2243 | xmalloc (sizeof (struct linked_proc_info)); |
| 2244 | mips_extra_func_info_t proc_desc = &link->info; |
| 2245 | CORE_ADDR sp = ADDR_BITS_REMOVE (read_register (SP_REGNUM)); |
| 2246 | CORE_ADDR old_sp = sp; |
| 2247 | link->next = linked_proc_desc_table; |
| 2248 | linked_proc_desc_table = link; |
| 2249 | |
| 2250 | /* FIXME! are these correct ? */ |
| 2251 | #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */ |
| 2252 | #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1)) |
| 2253 | #define FLOAT_REG_SAVE_MASK MASK(0,19) |
| 2254 | #define FLOAT_SINGLE_REG_SAVE_MASK \ |
| 2255 | ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0)) |
| 2256 | /* |
| 2257 | * The registers we must save are all those not preserved across |
| 2258 | * procedure calls. Dest_Reg (see tm-mips.h) must also be saved. |
| 2259 | * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI |
| 2260 | * and FP Control/Status registers. |
| 2261 | * |
| 2262 | * |
| 2263 | * Dummy frame layout: |
| 2264 | * (high memory) |
| 2265 | * Saved PC |
| 2266 | * Saved MMHI, MMLO, FPC_CSR |
| 2267 | * Saved R31 |
| 2268 | * Saved R28 |
| 2269 | * ... |
| 2270 | * Saved R1 |
| 2271 | * Saved D18 (i.e. F19, F18) |
| 2272 | * ... |
| 2273 | * Saved D0 (i.e. F1, F0) |
| 2274 | * Argument build area and stack arguments written via mips_push_arguments |
| 2275 | * (low memory) |
| 2276 | */ |
| 2277 | |
| 2278 | /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */ |
| 2279 | PROC_FRAME_REG (proc_desc) = PUSH_FP_REGNUM; |
| 2280 | PROC_FRAME_OFFSET (proc_desc) = 0; |
| 2281 | PROC_FRAME_ADJUST (proc_desc) = 0; |
| 2282 | mips_push_register (&sp, PC_REGNUM); |
| 2283 | mips_push_register (&sp, HI_REGNUM); |
| 2284 | mips_push_register (&sp, LO_REGNUM); |
| 2285 | mips_push_register (&sp, MIPS_FPU_TYPE == MIPS_FPU_NONE ? 0 : FCRCS_REGNUM); |
| 2286 | |
| 2287 | /* Save general CPU registers */ |
| 2288 | PROC_REG_MASK (proc_desc) = GEN_REG_SAVE_MASK; |
| 2289 | /* PROC_REG_OFFSET is the offset of the first saved register from FP. */ |
| 2290 | PROC_REG_OFFSET (proc_desc) = sp - old_sp - MIPS_SAVED_REGSIZE; |
| 2291 | for (ireg = 32; --ireg >= 0;) |
| 2292 | if (PROC_REG_MASK (proc_desc) & (1 << ireg)) |
| 2293 | mips_push_register (&sp, ireg); |
| 2294 | |
| 2295 | /* Save floating point registers starting with high order word */ |
| 2296 | PROC_FREG_MASK (proc_desc) = |
| 2297 | MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK |
| 2298 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0; |
| 2299 | /* PROC_FREG_OFFSET is the offset of the first saved *double* register |
| 2300 | from FP. */ |
| 2301 | PROC_FREG_OFFSET (proc_desc) = sp - old_sp - 8; |
| 2302 | for (ireg = 32; --ireg >= 0;) |
| 2303 | if (PROC_FREG_MASK (proc_desc) & (1 << ireg)) |
| 2304 | mips_push_register (&sp, ireg + FP0_REGNUM); |
| 2305 | |
| 2306 | /* Update the frame pointer for the call dummy and the stack pointer. |
| 2307 | Set the procedure's starting and ending addresses to point to the |
| 2308 | call dummy address at the entry point. */ |
| 2309 | write_register (PUSH_FP_REGNUM, old_sp); |
| 2310 | write_register (SP_REGNUM, sp); |
| 2311 | PROC_LOW_ADDR (proc_desc) = CALL_DUMMY_ADDRESS (); |
| 2312 | PROC_HIGH_ADDR (proc_desc) = CALL_DUMMY_ADDRESS () + 4; |
| 2313 | SET_PROC_DESC_IS_DUMMY (proc_desc); |
| 2314 | PROC_PC_REG (proc_desc) = RA_REGNUM; |
| 2315 | } |
| 2316 | |
| 2317 | void |
| 2318 | mips_pop_frame () |
| 2319 | { |
| 2320 | register int regnum; |
| 2321 | struct frame_info *frame = get_current_frame (); |
| 2322 | CORE_ADDR new_sp = FRAME_FP (frame); |
| 2323 | |
| 2324 | mips_extra_func_info_t proc_desc = frame->extra_info->proc_desc; |
| 2325 | |
| 2326 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); |
| 2327 | if (frame->saved_regs == NULL) |
| 2328 | mips_find_saved_regs (frame); |
| 2329 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
| 2330 | { |
| 2331 | if (regnum != SP_REGNUM && regnum != PC_REGNUM |
| 2332 | && frame->saved_regs[regnum]) |
| 2333 | write_register (regnum, |
| 2334 | read_memory_integer (frame->saved_regs[regnum], |
| 2335 | MIPS_SAVED_REGSIZE)); |
| 2336 | } |
| 2337 | write_register (SP_REGNUM, new_sp); |
| 2338 | flush_cached_frames (); |
| 2339 | |
| 2340 | if (proc_desc && PROC_DESC_IS_DUMMY (proc_desc)) |
| 2341 | { |
| 2342 | struct linked_proc_info *pi_ptr, *prev_ptr; |
| 2343 | |
| 2344 | for (pi_ptr = linked_proc_desc_table, prev_ptr = NULL; |
| 2345 | pi_ptr != NULL; |
| 2346 | prev_ptr = pi_ptr, pi_ptr = pi_ptr->next) |
| 2347 | { |
| 2348 | if (&pi_ptr->info == proc_desc) |
| 2349 | break; |
| 2350 | } |
| 2351 | |
| 2352 | if (pi_ptr == NULL) |
| 2353 | error ("Can't locate dummy extra frame info\n"); |
| 2354 | |
| 2355 | if (prev_ptr != NULL) |
| 2356 | prev_ptr->next = pi_ptr->next; |
| 2357 | else |
| 2358 | linked_proc_desc_table = pi_ptr->next; |
| 2359 | |
| 2360 | free (pi_ptr); |
| 2361 | |
| 2362 | write_register (HI_REGNUM, |
| 2363 | read_memory_integer (new_sp - 2 * MIPS_SAVED_REGSIZE, |
| 2364 | MIPS_SAVED_REGSIZE)); |
| 2365 | write_register (LO_REGNUM, |
| 2366 | read_memory_integer (new_sp - 3 * MIPS_SAVED_REGSIZE, |
| 2367 | MIPS_SAVED_REGSIZE)); |
| 2368 | if (MIPS_FPU_TYPE != MIPS_FPU_NONE) |
| 2369 | write_register (FCRCS_REGNUM, |
| 2370 | read_memory_integer (new_sp - 4 * MIPS_SAVED_REGSIZE, |
| 2371 | MIPS_SAVED_REGSIZE)); |
| 2372 | } |
| 2373 | } |
| 2374 | |
| 2375 | static void |
| 2376 | mips_print_register (regnum, all) |
| 2377 | int regnum, all; |
| 2378 | { |
| 2379 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
| 2380 | |
| 2381 | /* Get the data in raw format. */ |
| 2382 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) |
| 2383 | { |
| 2384 | printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum)); |
| 2385 | return; |
| 2386 | } |
| 2387 | |
| 2388 | /* If an even floating point register, also print as double. */ |
| 2389 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT |
| 2390 | && !((regnum - FP0_REGNUM) & 1)) |
| 2391 | if (REGISTER_RAW_SIZE (regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */ |
| 2392 | { |
| 2393 | char dbuffer[2 * MAX_REGISTER_RAW_SIZE]; |
| 2394 | |
| 2395 | read_relative_register_raw_bytes (regnum, dbuffer); |
| 2396 | read_relative_register_raw_bytes (regnum + 1, dbuffer + MIPS_REGSIZE); |
| 2397 | REGISTER_CONVERT_TO_TYPE (regnum, builtin_type_double, dbuffer); |
| 2398 | |
| 2399 | printf_filtered ("(d%d: ", regnum - FP0_REGNUM); |
| 2400 | val_print (builtin_type_double, dbuffer, 0, 0, |
| 2401 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
| 2402 | printf_filtered ("); "); |
| 2403 | } |
| 2404 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); |
| 2405 | |
| 2406 | /* The problem with printing numeric register names (r26, etc.) is that |
| 2407 | the user can't use them on input. Probably the best solution is to |
| 2408 | fix it so that either the numeric or the funky (a2, etc.) names |
| 2409 | are accepted on input. */ |
| 2410 | if (regnum < MIPS_NUMREGS) |
| 2411 | printf_filtered ("(r%d): ", regnum); |
| 2412 | else |
| 2413 | printf_filtered (": "); |
| 2414 | |
| 2415 | /* If virtual format is floating, print it that way. */ |
| 2416 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
| 2417 | if (FP_REGISTER_DOUBLE) |
| 2418 | { /* show 8-byte floats as float AND double: */ |
| 2419 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
| 2420 | |
| 2421 | printf_filtered (" (float) "); |
| 2422 | val_print (builtin_type_float, raw_buffer + offset, 0, 0, |
| 2423 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
| 2424 | printf_filtered (", (double) "); |
| 2425 | val_print (builtin_type_double, raw_buffer, 0, 0, |
| 2426 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
| 2427 | } |
| 2428 | else |
| 2429 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, |
| 2430 | gdb_stdout, 0, 1, 0, Val_pretty_default); |
| 2431 | /* Else print as integer in hex. */ |
| 2432 | else |
| 2433 | { |
| 2434 | int offset; |
| 2435 | |
| 2436 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 2437 | offset = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
| 2438 | else |
| 2439 | offset = 0; |
| 2440 | |
| 2441 | print_scalar_formatted (raw_buffer + offset, |
| 2442 | REGISTER_VIRTUAL_TYPE (regnum), |
| 2443 | 'x', 0, gdb_stdout); |
| 2444 | } |
| 2445 | } |
| 2446 | |
| 2447 | /* Replacement for generic do_registers_info. |
| 2448 | Print regs in pretty columns. */ |
| 2449 | |
| 2450 | static int |
| 2451 | do_fp_register_row (regnum) |
| 2452 | int regnum; |
| 2453 | { /* do values for FP (float) regs */ |
| 2454 | char *raw_buffer[2]; |
| 2455 | char *dbl_buffer; |
| 2456 | /* use HI and LO to control the order of combining two flt regs */ |
| 2457 | int HI = (TARGET_BYTE_ORDER == BIG_ENDIAN); |
| 2458 | int LO = (TARGET_BYTE_ORDER != BIG_ENDIAN); |
| 2459 | double doub, flt1, flt2; /* doubles extracted from raw hex data */ |
| 2460 | int inv1, inv2, inv3; |
| 2461 | |
| 2462 | raw_buffer[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); |
| 2463 | raw_buffer[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); |
| 2464 | dbl_buffer = (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM)); |
| 2465 | |
| 2466 | /* Get the data in raw format. */ |
| 2467 | if (read_relative_register_raw_bytes (regnum, raw_buffer[HI])) |
| 2468 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
| 2469 | if (REGISTER_RAW_SIZE (regnum) == 4) |
| 2470 | { |
| 2471 | /* 4-byte registers: we can fit two registers per row. */ |
| 2472 | /* Also print every pair of 4-byte regs as an 8-byte double. */ |
| 2473 | if (read_relative_register_raw_bytes (regnum + 1, raw_buffer[LO])) |
| 2474 | error ("can't read register %d (%s)", |
| 2475 | regnum + 1, REGISTER_NAME (regnum + 1)); |
| 2476 | |
| 2477 | /* copy the two floats into one double, and unpack both */ |
| 2478 | memcpy (dbl_buffer, raw_buffer, sizeof (dbl_buffer)); |
| 2479 | flt1 = unpack_double (builtin_type_float, raw_buffer[HI], &inv1); |
| 2480 | flt2 = unpack_double (builtin_type_float, raw_buffer[LO], &inv2); |
| 2481 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); |
| 2482 | |
| 2483 | printf_filtered (inv1 ? " %-5s: <invalid float>" : |
| 2484 | " %-5s%-17.9g", REGISTER_NAME (regnum), flt1); |
| 2485 | printf_filtered (inv2 ? " %-5s: <invalid float>" : |
| 2486 | " %-5s%-17.9g", REGISTER_NAME (regnum + 1), flt2); |
| 2487 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : |
| 2488 | " dbl: %-24.17g\n", doub); |
| 2489 | /* may want to do hex display here (future enhancement) */ |
| 2490 | regnum += 2; |
| 2491 | } |
| 2492 | else |
| 2493 | { /* eight byte registers: print each one as float AND as double. */ |
| 2494 | int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN); |
| 2495 | |
| 2496 | memcpy (dbl_buffer, raw_buffer[HI], sizeof (dbl_buffer)); |
| 2497 | flt1 = unpack_double (builtin_type_float, |
| 2498 | &raw_buffer[HI][offset], &inv1); |
| 2499 | doub = unpack_double (builtin_type_double, dbl_buffer, &inv3); |
| 2500 | |
| 2501 | printf_filtered (inv1 ? " %-5s: <invalid float>" : |
| 2502 | " %-5s flt: %-17.9g", REGISTER_NAME (regnum), flt1); |
| 2503 | printf_filtered (inv3 ? " dbl: <invalid double>\n" : |
| 2504 | " dbl: %-24.17g\n", doub); |
| 2505 | /* may want to do hex display here (future enhancement) */ |
| 2506 | regnum++; |
| 2507 | } |
| 2508 | return regnum; |
| 2509 | } |
| 2510 | |
| 2511 | /* Print a row's worth of GP (int) registers, with name labels above */ |
| 2512 | |
| 2513 | static int |
| 2514 | do_gp_register_row (regnum) |
| 2515 | int regnum; |
| 2516 | { |
| 2517 | /* do values for GP (int) regs */ |
| 2518 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
| 2519 | int ncols = (MIPS_REGSIZE == 8 ? 4 : 8); /* display cols per row */ |
| 2520 | int col, byte; |
| 2521 | int start_regnum = regnum; |
| 2522 | int numregs = NUM_REGS; |
| 2523 | |
| 2524 | |
| 2525 | /* For GP registers, we print a separate row of names above the vals */ |
| 2526 | printf_filtered (" "); |
| 2527 | for (col = 0; col < ncols && regnum < numregs; regnum++) |
| 2528 | { |
| 2529 | if (*REGISTER_NAME (regnum) == '\0') |
| 2530 | continue; /* unused register */ |
| 2531 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
| 2532 | break; /* end the row: reached FP register */ |
| 2533 | printf_filtered (MIPS_REGSIZE == 8 ? "%17s" : "%9s", |
| 2534 | REGISTER_NAME (regnum)); |
| 2535 | col++; |
| 2536 | } |
| 2537 | printf_filtered (start_regnum < MIPS_NUMREGS ? "\n R%-4d" : "\n ", |
| 2538 | start_regnum); /* print the R0 to R31 names */ |
| 2539 | |
| 2540 | regnum = start_regnum; /* go back to start of row */ |
| 2541 | /* now print the values in hex, 4 or 8 to the row */ |
| 2542 | for (col = 0; col < ncols && regnum < numregs; regnum++) |
| 2543 | { |
| 2544 | if (*REGISTER_NAME (regnum) == '\0') |
| 2545 | continue; /* unused register */ |
| 2546 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
| 2547 | break; /* end row: reached FP register */ |
| 2548 | /* OK: get the data in raw format. */ |
| 2549 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) |
| 2550 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
| 2551 | /* pad small registers */ |
| 2552 | for (byte = 0; byte < (MIPS_REGSIZE - REGISTER_VIRTUAL_SIZE (regnum)); byte++) |
| 2553 | printf_filtered (" "); |
| 2554 | /* Now print the register value in hex, endian order. */ |
| 2555 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 2556 | for (byte = REGISTER_RAW_SIZE (regnum) - REGISTER_VIRTUAL_SIZE (regnum); |
| 2557 | byte < REGISTER_RAW_SIZE (regnum); |
| 2558 | byte++) |
| 2559 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
| 2560 | else |
| 2561 | for (byte = REGISTER_VIRTUAL_SIZE (regnum) - 1; |
| 2562 | byte >= 0; |
| 2563 | byte--) |
| 2564 | printf_filtered ("%02x", (unsigned char) raw_buffer[byte]); |
| 2565 | printf_filtered (" "); |
| 2566 | col++; |
| 2567 | } |
| 2568 | if (col > 0) /* ie. if we actually printed anything... */ |
| 2569 | printf_filtered ("\n"); |
| 2570 | |
| 2571 | return regnum; |
| 2572 | } |
| 2573 | |
| 2574 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ |
| 2575 | |
| 2576 | void |
| 2577 | mips_do_registers_info (regnum, fpregs) |
| 2578 | int regnum; |
| 2579 | int fpregs; |
| 2580 | { |
| 2581 | if (regnum != -1) /* do one specified register */ |
| 2582 | { |
| 2583 | if (*(REGISTER_NAME (regnum)) == '\0') |
| 2584 | error ("Not a valid register for the current processor type"); |
| 2585 | |
| 2586 | mips_print_register (regnum, 0); |
| 2587 | printf_filtered ("\n"); |
| 2588 | } |
| 2589 | else |
| 2590 | /* do all (or most) registers */ |
| 2591 | { |
| 2592 | regnum = 0; |
| 2593 | while (regnum < NUM_REGS) |
| 2594 | { |
| 2595 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) |
| 2596 | if (fpregs) /* true for "INFO ALL-REGISTERS" command */ |
| 2597 | regnum = do_fp_register_row (regnum); /* FP regs */ |
| 2598 | else |
| 2599 | regnum += MIPS_NUMREGS; /* skip floating point regs */ |
| 2600 | else |
| 2601 | regnum = do_gp_register_row (regnum); /* GP (int) regs */ |
| 2602 | } |
| 2603 | } |
| 2604 | } |
| 2605 | |
| 2606 | /* Return number of args passed to a frame. described by FIP. |
| 2607 | Can return -1, meaning no way to tell. */ |
| 2608 | |
| 2609 | int |
| 2610 | mips_frame_num_args (frame) |
| 2611 | struct frame_info *frame; |
| 2612 | { |
| 2613 | #if 0 /* FIXME Use or lose this! */ |
| 2614 | struct chain_info_t *p; |
| 2615 | |
| 2616 | p = mips_find_cached_frame (FRAME_FP (frame)); |
| 2617 | if (p->valid) |
| 2618 | return p->the_info.numargs; |
| 2619 | #endif |
| 2620 | return -1; |
| 2621 | } |
| 2622 | |
| 2623 | /* Is this a branch with a delay slot? */ |
| 2624 | |
| 2625 | static int is_delayed PARAMS ((unsigned long)); |
| 2626 | |
| 2627 | static int |
| 2628 | is_delayed (insn) |
| 2629 | unsigned long insn; |
| 2630 | { |
| 2631 | int i; |
| 2632 | for (i = 0; i < NUMOPCODES; ++i) |
| 2633 | if (mips_opcodes[i].pinfo != INSN_MACRO |
| 2634 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) |
| 2635 | break; |
| 2636 | return (i < NUMOPCODES |
| 2637 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY |
| 2638 | | INSN_COND_BRANCH_DELAY |
| 2639 | | INSN_COND_BRANCH_LIKELY))); |
| 2640 | } |
| 2641 | |
| 2642 | int |
| 2643 | mips_step_skips_delay (pc) |
| 2644 | CORE_ADDR pc; |
| 2645 | { |
| 2646 | char buf[MIPS_INSTLEN]; |
| 2647 | |
| 2648 | /* There is no branch delay slot on MIPS16. */ |
| 2649 | if (pc_is_mips16 (pc)) |
| 2650 | return 0; |
| 2651 | |
| 2652 | if (target_read_memory (pc, buf, MIPS_INSTLEN) != 0) |
| 2653 | /* If error reading memory, guess that it is not a delayed branch. */ |
| 2654 | return 0; |
| 2655 | return is_delayed ((unsigned long) extract_unsigned_integer (buf, MIPS_INSTLEN)); |
| 2656 | } |
| 2657 | |
| 2658 | |
| 2659 | /* Skip the PC past function prologue instructions (32-bit version). |
| 2660 | This is a helper function for mips_skip_prologue. */ |
| 2661 | |
| 2662 | static CORE_ADDR |
| 2663 | mips32_skip_prologue (pc, lenient) |
| 2664 | CORE_ADDR pc; /* starting PC to search from */ |
| 2665 | int lenient; |
| 2666 | { |
| 2667 | t_inst inst; |
| 2668 | CORE_ADDR end_pc; |
| 2669 | int seen_sp_adjust = 0; |
| 2670 | int load_immediate_bytes = 0; |
| 2671 | |
| 2672 | /* Skip the typical prologue instructions. These are the stack adjustment |
| 2673 | instruction and the instructions that save registers on the stack |
| 2674 | or in the gcc frame. */ |
| 2675 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS_INSTLEN) |
| 2676 | { |
| 2677 | unsigned long high_word; |
| 2678 | |
| 2679 | inst = mips_fetch_instruction (pc); |
| 2680 | high_word = (inst >> 16) & 0xffff; |
| 2681 | |
| 2682 | #if 0 |
| 2683 | if (lenient && is_delayed (inst)) |
| 2684 | continue; |
| 2685 | #endif |
| 2686 | |
| 2687 | if (high_word == 0x27bd /* addiu $sp,$sp,offset */ |
| 2688 | || high_word == 0x67bd) /* daddiu $sp,$sp,offset */ |
| 2689 | seen_sp_adjust = 1; |
| 2690 | else if (inst == 0x03a1e823 || /* subu $sp,$sp,$at */ |
| 2691 | inst == 0x03a8e823) /* subu $sp,$sp,$t0 */ |
| 2692 | seen_sp_adjust = 1; |
| 2693 | else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */ |
| 2694 | || (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */ |
| 2695 | && (inst & 0x001F0000)) /* reg != $zero */ |
| 2696 | continue; |
| 2697 | |
| 2698 | else if ((inst & 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */ |
| 2699 | continue; |
| 2700 | else if ((inst & 0xF3E00000) == 0xA3C00000 && (inst & 0x001F0000)) |
| 2701 | /* sx reg,n($s8) */ |
| 2702 | continue; /* reg != $zero */ |
| 2703 | |
| 2704 | /* move $s8,$sp. With different versions of gas this will be either |
| 2705 | `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'. |
| 2706 | Accept any one of these. */ |
| 2707 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
| 2708 | continue; |
| 2709 | |
| 2710 | else if ((inst & 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */ |
| 2711 | continue; |
| 2712 | else if (high_word == 0x3c1c) /* lui $gp,n */ |
| 2713 | continue; |
| 2714 | else if (high_word == 0x279c) /* addiu $gp,$gp,n */ |
| 2715 | continue; |
| 2716 | else if (inst == 0x0399e021 /* addu $gp,$gp,$t9 */ |
| 2717 | || inst == 0x033ce021) /* addu $gp,$t9,$gp */ |
| 2718 | continue; |
| 2719 | /* The following instructions load $at or $t0 with an immediate |
| 2720 | value in preparation for a stack adjustment via |
| 2721 | subu $sp,$sp,[$at,$t0]. These instructions could also initialize |
| 2722 | a local variable, so we accept them only before a stack adjustment |
| 2723 | instruction was seen. */ |
| 2724 | else if (!seen_sp_adjust) |
| 2725 | { |
| 2726 | if (high_word == 0x3c01 || /* lui $at,n */ |
| 2727 | high_word == 0x3c08) /* lui $t0,n */ |
| 2728 | { |
| 2729 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
| 2730 | continue; |
| 2731 | } |
| 2732 | else if (high_word == 0x3421 || /* ori $at,$at,n */ |
| 2733 | high_word == 0x3508 || /* ori $t0,$t0,n */ |
| 2734 | high_word == 0x3401 || /* ori $at,$zero,n */ |
| 2735 | high_word == 0x3408) /* ori $t0,$zero,n */ |
| 2736 | { |
| 2737 | load_immediate_bytes += MIPS_INSTLEN; /* FIXME!! */ |
| 2738 | continue; |
| 2739 | } |
| 2740 | else |
| 2741 | break; |
| 2742 | } |
| 2743 | else |
| 2744 | break; |
| 2745 | } |
| 2746 | |
| 2747 | /* In a frameless function, we might have incorrectly |
| 2748 | skipped some load immediate instructions. Undo the skipping |
| 2749 | if the load immediate was not followed by a stack adjustment. */ |
| 2750 | if (load_immediate_bytes && !seen_sp_adjust) |
| 2751 | pc -= load_immediate_bytes; |
| 2752 | return pc; |
| 2753 | } |
| 2754 | |
| 2755 | /* Skip the PC past function prologue instructions (16-bit version). |
| 2756 | This is a helper function for mips_skip_prologue. */ |
| 2757 | |
| 2758 | static CORE_ADDR |
| 2759 | mips16_skip_prologue (pc, lenient) |
| 2760 | CORE_ADDR pc; /* starting PC to search from */ |
| 2761 | int lenient; |
| 2762 | { |
| 2763 | CORE_ADDR end_pc; |
| 2764 | int extend_bytes = 0; |
| 2765 | int prev_extend_bytes; |
| 2766 | |
| 2767 | /* Table of instructions likely to be found in a function prologue. */ |
| 2768 | static struct |
| 2769 | { |
| 2770 | unsigned short inst; |
| 2771 | unsigned short mask; |
| 2772 | } |
| 2773 | table[] = |
| 2774 | { |
| 2775 | { |
| 2776 | 0x6300, 0xff00 |
| 2777 | } |
| 2778 | , /* addiu $sp,offset */ |
| 2779 | { |
| 2780 | 0xfb00, 0xff00 |
| 2781 | } |
| 2782 | , /* daddiu $sp,offset */ |
| 2783 | { |
| 2784 | 0xd000, 0xf800 |
| 2785 | } |
| 2786 | , /* sw reg,n($sp) */ |
| 2787 | { |
| 2788 | 0xf900, 0xff00 |
| 2789 | } |
| 2790 | , /* sd reg,n($sp) */ |
| 2791 | { |
| 2792 | 0x6200, 0xff00 |
| 2793 | } |
| 2794 | , /* sw $ra,n($sp) */ |
| 2795 | { |
| 2796 | 0xfa00, 0xff00 |
| 2797 | } |
| 2798 | , /* sd $ra,n($sp) */ |
| 2799 | { |
| 2800 | 0x673d, 0xffff |
| 2801 | } |
| 2802 | , /* move $s1,sp */ |
| 2803 | { |
| 2804 | 0xd980, 0xff80 |
| 2805 | } |
| 2806 | , /* sw $a0-$a3,n($s1) */ |
| 2807 | { |
| 2808 | 0x6704, 0xff1c |
| 2809 | } |
| 2810 | , /* move reg,$a0-$a3 */ |
| 2811 | { |
| 2812 | 0xe809, 0xf81f |
| 2813 | } |
| 2814 | , /* entry pseudo-op */ |
| 2815 | { |
| 2816 | 0x0100, 0xff00 |
| 2817 | } |
| 2818 | , /* addiu $s1,$sp,n */ |
| 2819 | { |
| 2820 | 0, 0 |
| 2821 | } /* end of table marker */ |
| 2822 | }; |
| 2823 | |
| 2824 | /* Skip the typical prologue instructions. These are the stack adjustment |
| 2825 | instruction and the instructions that save registers on the stack |
| 2826 | or in the gcc frame. */ |
| 2827 | for (end_pc = pc + 100; pc < end_pc; pc += MIPS16_INSTLEN) |
| 2828 | { |
| 2829 | unsigned short inst; |
| 2830 | int i; |
| 2831 | |
| 2832 | inst = mips_fetch_instruction (pc); |
| 2833 | |
| 2834 | /* Normally we ignore an extend instruction. However, if it is |
| 2835 | not followed by a valid prologue instruction, we must adjust |
| 2836 | the pc back over the extend so that it won't be considered |
| 2837 | part of the prologue. */ |
| 2838 | if ((inst & 0xf800) == 0xf000) /* extend */ |
| 2839 | { |
| 2840 | extend_bytes = MIPS16_INSTLEN; |
| 2841 | continue; |
| 2842 | } |
| 2843 | prev_extend_bytes = extend_bytes; |
| 2844 | extend_bytes = 0; |
| 2845 | |
| 2846 | /* Check for other valid prologue instructions besides extend. */ |
| 2847 | for (i = 0; table[i].mask != 0; i++) |
| 2848 | if ((inst & table[i].mask) == table[i].inst) /* found, get out */ |
| 2849 | break; |
| 2850 | if (table[i].mask != 0) /* it was in table? */ |
| 2851 | continue; /* ignore it */ |
| 2852 | else |
| 2853 | /* non-prologue */ |
| 2854 | { |
| 2855 | /* Return the current pc, adjusted backwards by 2 if |
| 2856 | the previous instruction was an extend. */ |
| 2857 | return pc - prev_extend_bytes; |
| 2858 | } |
| 2859 | } |
| 2860 | return pc; |
| 2861 | } |
| 2862 | |
| 2863 | /* To skip prologues, I use this predicate. Returns either PC itself |
| 2864 | if the code at PC does not look like a function prologue; otherwise |
| 2865 | returns an address that (if we're lucky) follows the prologue. If |
| 2866 | LENIENT, then we must skip everything which is involved in setting |
| 2867 | up the frame (it's OK to skip more, just so long as we don't skip |
| 2868 | anything which might clobber the registers which are being saved. |
| 2869 | We must skip more in the case where part of the prologue is in the |
| 2870 | delay slot of a non-prologue instruction). */ |
| 2871 | |
| 2872 | CORE_ADDR |
| 2873 | mips_skip_prologue (pc, lenient) |
| 2874 | CORE_ADDR pc; |
| 2875 | int lenient; |
| 2876 | { |
| 2877 | /* See if we can determine the end of the prologue via the symbol table. |
| 2878 | If so, then return either PC, or the PC after the prologue, whichever |
| 2879 | is greater. */ |
| 2880 | |
| 2881 | CORE_ADDR post_prologue_pc = after_prologue (pc, NULL); |
| 2882 | |
| 2883 | if (post_prologue_pc != 0) |
| 2884 | return max (pc, post_prologue_pc); |
| 2885 | |
| 2886 | /* Can't determine prologue from the symbol table, need to examine |
| 2887 | instructions. */ |
| 2888 | |
| 2889 | if (pc_is_mips16 (pc)) |
| 2890 | return mips16_skip_prologue (pc, lenient); |
| 2891 | else |
| 2892 | return mips32_skip_prologue (pc, lenient); |
| 2893 | } |
| 2894 | |
| 2895 | #if 0 |
| 2896 | /* The lenient prologue stuff should be superseded by the code in |
| 2897 | init_extra_frame_info which looks to see whether the stores mentioned |
| 2898 | in the proc_desc have actually taken place. */ |
| 2899 | |
| 2900 | /* Is address PC in the prologue (loosely defined) for function at |
| 2901 | STARTADDR? */ |
| 2902 | |
| 2903 | static int |
| 2904 | mips_in_lenient_prologue (startaddr, pc) |
| 2905 | CORE_ADDR startaddr; |
| 2906 | CORE_ADDR pc; |
| 2907 | { |
| 2908 | CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1); |
| 2909 | return pc >= startaddr && pc < end_prologue; |
| 2910 | } |
| 2911 | #endif |
| 2912 | |
| 2913 | /* Determine how a return value is stored within the MIPS register |
| 2914 | file, given the return type `valtype'. */ |
| 2915 | |
| 2916 | struct return_value_word |
| 2917 | { |
| 2918 | int len; |
| 2919 | int reg; |
| 2920 | int reg_offset; |
| 2921 | int buf_offset; |
| 2922 | }; |
| 2923 | |
| 2924 | static void return_value_location PARAMS ((struct type *, struct return_value_word *, struct return_value_word *)); |
| 2925 | |
| 2926 | static void |
| 2927 | return_value_location (valtype, hi, lo) |
| 2928 | struct type *valtype; |
| 2929 | struct return_value_word *hi; |
| 2930 | struct return_value_word *lo; |
| 2931 | { |
| 2932 | int len = TYPE_LENGTH (valtype); |
| 2933 | |
| 2934 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
| 2935 | && ((MIPS_FPU_TYPE == MIPS_FPU_DOUBLE && (len == 4 || len == 8)) |
| 2936 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE && len == 4))) |
| 2937 | { |
| 2938 | if (!FP_REGISTER_DOUBLE && len == 8) |
| 2939 | { |
| 2940 | /* We need to break a 64bit float in two 32 bit halves and |
| 2941 | spread them across a floating-point register pair. */ |
| 2942 | lo->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0; |
| 2943 | hi->buf_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 0 : 4; |
| 2944 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN |
| 2945 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8) |
| 2946 | ? 4 : 0); |
| 2947 | hi->reg_offset = lo->reg_offset; |
| 2948 | lo->reg = FP0_REGNUM + 0; |
| 2949 | hi->reg = FP0_REGNUM + 1; |
| 2950 | lo->len = 4; |
| 2951 | hi->len = 4; |
| 2952 | } |
| 2953 | else |
| 2954 | { |
| 2955 | /* The floating point value fits in a single floating-point |
| 2956 | register. */ |
| 2957 | lo->reg_offset = ((TARGET_BYTE_ORDER == BIG_ENDIAN |
| 2958 | && REGISTER_RAW_SIZE (FP0_REGNUM) == 8 |
| 2959 | && len == 4) |
| 2960 | ? 4 : 0); |
| 2961 | lo->reg = FP0_REGNUM; |
| 2962 | lo->len = len; |
| 2963 | lo->buf_offset = 0; |
| 2964 | hi->len = 0; |
| 2965 | hi->reg_offset = 0; |
| 2966 | hi->buf_offset = 0; |
| 2967 | hi->reg = 0; |
| 2968 | } |
| 2969 | } |
| 2970 | else |
| 2971 | { |
| 2972 | /* Locate a result possibly spread across two registers. */ |
| 2973 | int regnum = 2; |
| 2974 | lo->reg = regnum + 0; |
| 2975 | hi->reg = regnum + 1; |
| 2976 | if (TARGET_BYTE_ORDER == BIG_ENDIAN |
| 2977 | && len < MIPS_SAVED_REGSIZE) |
| 2978 | { |
| 2979 | /* "un-left-justify" the value in the low register */ |
| 2980 | lo->reg_offset = MIPS_SAVED_REGSIZE - len; |
| 2981 | lo->len = len; |
| 2982 | hi->reg_offset = 0; |
| 2983 | hi->len = 0; |
| 2984 | } |
| 2985 | else if (TARGET_BYTE_ORDER == BIG_ENDIAN |
| 2986 | && len > MIPS_SAVED_REGSIZE /* odd-size structs */ |
| 2987 | && len < MIPS_SAVED_REGSIZE * 2 |
| 2988 | && (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || |
| 2989 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) |
| 2990 | { |
| 2991 | /* "un-left-justify" the value spread across two registers. */ |
| 2992 | lo->reg_offset = 2 * MIPS_SAVED_REGSIZE - len; |
| 2993 | lo->len = MIPS_SAVED_REGSIZE - lo->reg_offset; |
| 2994 | hi->reg_offset = 0; |
| 2995 | hi->len = len - lo->len; |
| 2996 | } |
| 2997 | else |
| 2998 | { |
| 2999 | /* Only perform a partial copy of the second register. */ |
| 3000 | lo->reg_offset = 0; |
| 3001 | hi->reg_offset = 0; |
| 3002 | if (len > MIPS_SAVED_REGSIZE) |
| 3003 | { |
| 3004 | lo->len = MIPS_SAVED_REGSIZE; |
| 3005 | hi->len = len - MIPS_SAVED_REGSIZE; |
| 3006 | } |
| 3007 | else |
| 3008 | { |
| 3009 | lo->len = len; |
| 3010 | hi->len = 0; |
| 3011 | } |
| 3012 | } |
| 3013 | if (TARGET_BYTE_ORDER == BIG_ENDIAN |
| 3014 | && REGISTER_RAW_SIZE (regnum) == 8 |
| 3015 | && MIPS_SAVED_REGSIZE == 4) |
| 3016 | { |
| 3017 | /* Account for the fact that only the least-signficant part |
| 3018 | of the register is being used */ |
| 3019 | lo->reg_offset += 4; |
| 3020 | hi->reg_offset += 4; |
| 3021 | } |
| 3022 | lo->buf_offset = 0; |
| 3023 | hi->buf_offset = lo->len; |
| 3024 | } |
| 3025 | } |
| 3026 | |
| 3027 | /* Given a return value in `regbuf' with a type `valtype', extract and |
| 3028 | copy its value into `valbuf'. */ |
| 3029 | |
| 3030 | void |
| 3031 | mips_extract_return_value (valtype, regbuf, valbuf) |
| 3032 | struct type *valtype; |
| 3033 | char regbuf[REGISTER_BYTES]; |
| 3034 | char *valbuf; |
| 3035 | { |
| 3036 | struct return_value_word lo; |
| 3037 | struct return_value_word hi; |
| 3038 | return_value_location (valtype, &lo, &hi); |
| 3039 | |
| 3040 | memcpy (valbuf + lo.buf_offset, |
| 3041 | regbuf + REGISTER_BYTE (lo.reg) + lo.reg_offset, |
| 3042 | lo.len); |
| 3043 | |
| 3044 | if (hi.len > 0) |
| 3045 | memcpy (valbuf + hi.buf_offset, |
| 3046 | regbuf + REGISTER_BYTE (hi.reg) + hi.reg_offset, |
| 3047 | hi.len); |
| 3048 | |
| 3049 | #if 0 |
| 3050 | int regnum; |
| 3051 | int offset = 0; |
| 3052 | int len = TYPE_LENGTH (valtype); |
| 3053 | |
| 3054 | regnum = 2; |
| 3055 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
| 3056 | && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE |
| 3057 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE |
| 3058 | && len <= MIPS_FPU_SINGLE_REGSIZE))) |
| 3059 | regnum = FP0_REGNUM; |
| 3060 | |
| 3061 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 3062 | { /* "un-left-justify" the value from the register */ |
| 3063 | if (len < REGISTER_RAW_SIZE (regnum)) |
| 3064 | offset = REGISTER_RAW_SIZE (regnum) - len; |
| 3065 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ |
| 3066 | len < REGISTER_RAW_SIZE (regnum) * 2 && |
| 3067 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || |
| 3068 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) |
| 3069 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; |
| 3070 | } |
| 3071 | memcpy (valbuf, regbuf + REGISTER_BYTE (regnum) + offset, len); |
| 3072 | REGISTER_CONVERT_TO_TYPE (regnum, valtype, valbuf); |
| 3073 | #endif |
| 3074 | } |
| 3075 | |
| 3076 | /* Given a return value in `valbuf' with a type `valtype', write it's |
| 3077 | value into the appropriate register. */ |
| 3078 | |
| 3079 | void |
| 3080 | mips_store_return_value (valtype, valbuf) |
| 3081 | struct type *valtype; |
| 3082 | char *valbuf; |
| 3083 | { |
| 3084 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
| 3085 | struct return_value_word lo; |
| 3086 | struct return_value_word hi; |
| 3087 | return_value_location (valtype, &lo, &hi); |
| 3088 | |
| 3089 | memset (raw_buffer, 0, sizeof (raw_buffer)); |
| 3090 | memcpy (raw_buffer + lo.reg_offset, valbuf + lo.buf_offset, lo.len); |
| 3091 | write_register_bytes (REGISTER_BYTE (lo.reg), |
| 3092 | raw_buffer, |
| 3093 | REGISTER_RAW_SIZE (lo.reg)); |
| 3094 | |
| 3095 | if (hi.len > 0) |
| 3096 | { |
| 3097 | memset (raw_buffer, 0, sizeof (raw_buffer)); |
| 3098 | memcpy (raw_buffer + hi.reg_offset, valbuf + hi.buf_offset, hi.len); |
| 3099 | write_register_bytes (REGISTER_BYTE (hi.reg), |
| 3100 | raw_buffer, |
| 3101 | REGISTER_RAW_SIZE (hi.reg)); |
| 3102 | } |
| 3103 | |
| 3104 | #if 0 |
| 3105 | int regnum; |
| 3106 | int offset = 0; |
| 3107 | int len = TYPE_LENGTH (valtype); |
| 3108 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; |
| 3109 | |
| 3110 | regnum = 2; |
| 3111 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT |
| 3112 | && (MIPS_FPU_TYPE == MIPS_FPU_DOUBLE |
| 3113 | || (MIPS_FPU_TYPE == MIPS_FPU_SINGLE |
| 3114 | && len <= MIPS_REGSIZE))) |
| 3115 | regnum = FP0_REGNUM; |
| 3116 | |
| 3117 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 3118 | { /* "left-justify" the value in the register */ |
| 3119 | if (len < REGISTER_RAW_SIZE (regnum)) |
| 3120 | offset = REGISTER_RAW_SIZE (regnum) - len; |
| 3121 | if (len > REGISTER_RAW_SIZE (regnum) && /* odd-size structs */ |
| 3122 | len < REGISTER_RAW_SIZE (regnum) * 2 && |
| 3123 | (TYPE_CODE (valtype) == TYPE_CODE_STRUCT || |
| 3124 | TYPE_CODE (valtype) == TYPE_CODE_UNION)) |
| 3125 | offset = 2 * REGISTER_RAW_SIZE (regnum) - len; |
| 3126 | } |
| 3127 | memcpy (raw_buffer + offset, valbuf, len); |
| 3128 | REGISTER_CONVERT_FROM_TYPE (regnum, valtype, raw_buffer); |
| 3129 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, |
| 3130 | len > REGISTER_RAW_SIZE (regnum) ? |
| 3131 | len : REGISTER_RAW_SIZE (regnum)); |
| 3132 | #endif |
| 3133 | } |
| 3134 | |
| 3135 | /* Exported procedure: Is PC in the signal trampoline code */ |
| 3136 | |
| 3137 | int |
| 3138 | in_sigtramp (pc, ignore) |
| 3139 | CORE_ADDR pc; |
| 3140 | char *ignore; /* function name */ |
| 3141 | { |
| 3142 | if (sigtramp_address == 0) |
| 3143 | fixup_sigtramp (); |
| 3144 | return (pc >= sigtramp_address && pc < sigtramp_end); |
| 3145 | } |
| 3146 | |
| 3147 | /* Commands to show/set the MIPS FPU type. */ |
| 3148 | |
| 3149 | static void show_mipsfpu_command PARAMS ((char *, int)); |
| 3150 | static void |
| 3151 | show_mipsfpu_command (args, from_tty) |
| 3152 | char *args; |
| 3153 | int from_tty; |
| 3154 | { |
| 3155 | char *msg; |
| 3156 | char *fpu; |
| 3157 | switch (MIPS_FPU_TYPE) |
| 3158 | { |
| 3159 | case MIPS_FPU_SINGLE: |
| 3160 | fpu = "single-precision"; |
| 3161 | break; |
| 3162 | case MIPS_FPU_DOUBLE: |
| 3163 | fpu = "double-precision"; |
| 3164 | break; |
| 3165 | case MIPS_FPU_NONE: |
| 3166 | fpu = "absent (none)"; |
| 3167 | break; |
| 3168 | } |
| 3169 | if (mips_fpu_type_auto) |
| 3170 | printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", |
| 3171 | fpu); |
| 3172 | else |
| 3173 | printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n", |
| 3174 | fpu); |
| 3175 | } |
| 3176 | |
| 3177 | |
| 3178 | static void set_mipsfpu_command PARAMS ((char *, int)); |
| 3179 | static void |
| 3180 | set_mipsfpu_command (args, from_tty) |
| 3181 | char *args; |
| 3182 | int from_tty; |
| 3183 | { |
| 3184 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); |
| 3185 | show_mipsfpu_command (args, from_tty); |
| 3186 | } |
| 3187 | |
| 3188 | static void set_mipsfpu_single_command PARAMS ((char *, int)); |
| 3189 | static void |
| 3190 | set_mipsfpu_single_command (args, from_tty) |
| 3191 | char *args; |
| 3192 | int from_tty; |
| 3193 | { |
| 3194 | mips_fpu_type = MIPS_FPU_SINGLE; |
| 3195 | mips_fpu_type_auto = 0; |
| 3196 | if (GDB_MULTI_ARCH) |
| 3197 | { |
| 3198 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_SINGLE; |
| 3199 | } |
| 3200 | } |
| 3201 | |
| 3202 | static void set_mipsfpu_double_command PARAMS ((char *, int)); |
| 3203 | static void |
| 3204 | set_mipsfpu_double_command (args, from_tty) |
| 3205 | char *args; |
| 3206 | int from_tty; |
| 3207 | { |
| 3208 | mips_fpu_type = MIPS_FPU_DOUBLE; |
| 3209 | mips_fpu_type_auto = 0; |
| 3210 | if (GDB_MULTI_ARCH) |
| 3211 | { |
| 3212 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_DOUBLE; |
| 3213 | } |
| 3214 | } |
| 3215 | |
| 3216 | static void set_mipsfpu_none_command PARAMS ((char *, int)); |
| 3217 | static void |
| 3218 | set_mipsfpu_none_command (args, from_tty) |
| 3219 | char *args; |
| 3220 | int from_tty; |
| 3221 | { |
| 3222 | mips_fpu_type = MIPS_FPU_NONE; |
| 3223 | mips_fpu_type_auto = 0; |
| 3224 | if (GDB_MULTI_ARCH) |
| 3225 | { |
| 3226 | gdbarch_tdep (current_gdbarch)->mips_fpu_type = MIPS_FPU_NONE; |
| 3227 | } |
| 3228 | } |
| 3229 | |
| 3230 | static void set_mipsfpu_auto_command PARAMS ((char *, int)); |
| 3231 | static void |
| 3232 | set_mipsfpu_auto_command (args, from_tty) |
| 3233 | char *args; |
| 3234 | int from_tty; |
| 3235 | { |
| 3236 | mips_fpu_type_auto = 1; |
| 3237 | } |
| 3238 | |
| 3239 | /* Command to set the processor type. */ |
| 3240 | |
| 3241 | void |
| 3242 | mips_set_processor_type_command (args, from_tty) |
| 3243 | char *args; |
| 3244 | int from_tty; |
| 3245 | { |
| 3246 | int i; |
| 3247 | |
| 3248 | if (tmp_mips_processor_type == NULL || *tmp_mips_processor_type == '\0') |
| 3249 | { |
| 3250 | printf_unfiltered ("The known MIPS processor types are as follows:\n\n"); |
| 3251 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) |
| 3252 | printf_unfiltered ("%s\n", mips_processor_type_table[i].name); |
| 3253 | |
| 3254 | /* Restore the value. */ |
| 3255 | tmp_mips_processor_type = strsave (mips_processor_type); |
| 3256 | |
| 3257 | return; |
| 3258 | } |
| 3259 | |
| 3260 | if (!mips_set_processor_type (tmp_mips_processor_type)) |
| 3261 | { |
| 3262 | error ("Unknown processor type `%s'.", tmp_mips_processor_type); |
| 3263 | /* Restore its value. */ |
| 3264 | tmp_mips_processor_type = strsave (mips_processor_type); |
| 3265 | } |
| 3266 | } |
| 3267 | |
| 3268 | static void |
| 3269 | mips_show_processor_type_command (args, from_tty) |
| 3270 | char *args; |
| 3271 | int from_tty; |
| 3272 | { |
| 3273 | } |
| 3274 | |
| 3275 | /* Modify the actual processor type. */ |
| 3276 | |
| 3277 | int |
| 3278 | mips_set_processor_type (str) |
| 3279 | char *str; |
| 3280 | { |
| 3281 | int i, j; |
| 3282 | |
| 3283 | if (str == NULL) |
| 3284 | return 0; |
| 3285 | |
| 3286 | for (i = 0; mips_processor_type_table[i].name != NULL; ++i) |
| 3287 | { |
| 3288 | if (strcasecmp (str, mips_processor_type_table[i].name) == 0) |
| 3289 | { |
| 3290 | mips_processor_type = str; |
| 3291 | mips_processor_reg_names = mips_processor_type_table[i].regnames; |
| 3292 | return 1; |
| 3293 | /* FIXME tweak fpu flag too */ |
| 3294 | } |
| 3295 | } |
| 3296 | |
| 3297 | return 0; |
| 3298 | } |
| 3299 | |
| 3300 | /* Attempt to identify the particular processor model by reading the |
| 3301 | processor id. */ |
| 3302 | |
| 3303 | char * |
| 3304 | mips_read_processor_type () |
| 3305 | { |
| 3306 | CORE_ADDR prid; |
| 3307 | |
| 3308 | prid = read_register (PRID_REGNUM); |
| 3309 | |
| 3310 | if ((prid & ~0xf) == 0x700) |
| 3311 | return savestring ("r3041", strlen ("r3041")); |
| 3312 | |
| 3313 | return NULL; |
| 3314 | } |
| 3315 | |
| 3316 | /* Just like reinit_frame_cache, but with the right arguments to be |
| 3317 | callable as an sfunc. */ |
| 3318 | |
| 3319 | static void |
| 3320 | reinit_frame_cache_sfunc (args, from_tty, c) |
| 3321 | char *args; |
| 3322 | int from_tty; |
| 3323 | struct cmd_list_element *c; |
| 3324 | { |
| 3325 | reinit_frame_cache (); |
| 3326 | } |
| 3327 | |
| 3328 | int |
| 3329 | gdb_print_insn_mips (memaddr, info) |
| 3330 | bfd_vma memaddr; |
| 3331 | disassemble_info *info; |
| 3332 | { |
| 3333 | mips_extra_func_info_t proc_desc; |
| 3334 | |
| 3335 | /* Search for the function containing this address. Set the low bit |
| 3336 | of the address when searching, in case we were given an even address |
| 3337 | that is the start of a 16-bit function. If we didn't do this, |
| 3338 | the search would fail because the symbol table says the function |
| 3339 | starts at an odd address, i.e. 1 byte past the given address. */ |
| 3340 | memaddr = ADDR_BITS_REMOVE (memaddr); |
| 3341 | proc_desc = non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr), NULL); |
| 3342 | |
| 3343 | /* Make an attempt to determine if this is a 16-bit function. If |
| 3344 | the procedure descriptor exists and the address therein is odd, |
| 3345 | it's definitely a 16-bit function. Otherwise, we have to just |
| 3346 | guess that if the address passed in is odd, it's 16-bits. */ |
| 3347 | if (proc_desc) |
| 3348 | info->mach = pc_is_mips16 (PROC_LOW_ADDR (proc_desc)) ? 16 : TM_PRINT_INSN_MACH; |
| 3349 | else |
| 3350 | info->mach = pc_is_mips16 (memaddr) ? 16 : TM_PRINT_INSN_MACH; |
| 3351 | |
| 3352 | /* Round down the instruction address to the appropriate boundary. */ |
| 3353 | memaddr &= (info->mach == 16 ? ~1 : ~3); |
| 3354 | |
| 3355 | /* Call the appropriate disassembler based on the target endian-ness. */ |
| 3356 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 3357 | return print_insn_big_mips (memaddr, info); |
| 3358 | else |
| 3359 | return print_insn_little_mips (memaddr, info); |
| 3360 | } |
| 3361 | |
| 3362 | /* Old-style breakpoint macros. |
| 3363 | The IDT board uses an unusual breakpoint value, and sometimes gets |
| 3364 | confused when it sees the usual MIPS breakpoint instruction. */ |
| 3365 | |
| 3366 | #define BIG_BREAKPOINT {0, 0x5, 0, 0xd} |
| 3367 | #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0} |
| 3368 | #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd} |
| 3369 | #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0} |
| 3370 | #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd} |
| 3371 | #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0} |
| 3372 | #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5} |
| 3373 | #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8} |
| 3374 | |
| 3375 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
| 3376 | counter value to determine whether a 16- or 32-bit breakpoint should be |
| 3377 | used. It returns a pointer to a string of bytes that encode a breakpoint |
| 3378 | instruction, stores the length of the string to *lenptr, and adjusts pc |
| 3379 | (if necessary) to point to the actual memory location where the |
| 3380 | breakpoint should be inserted. */ |
| 3381 | |
| 3382 | unsigned char * |
| 3383 | mips_breakpoint_from_pc (pcptr, lenptr) |
| 3384 | CORE_ADDR *pcptr; |
| 3385 | int *lenptr; |
| 3386 | { |
| 3387 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
| 3388 | { |
| 3389 | if (pc_is_mips16 (*pcptr)) |
| 3390 | { |
| 3391 | static char mips16_big_breakpoint[] = MIPS16_BIG_BREAKPOINT; |
| 3392 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
| 3393 | *lenptr = sizeof (mips16_big_breakpoint); |
| 3394 | return mips16_big_breakpoint; |
| 3395 | } |
| 3396 | else |
| 3397 | { |
| 3398 | static char big_breakpoint[] = BIG_BREAKPOINT; |
| 3399 | static char pmon_big_breakpoint[] = PMON_BIG_BREAKPOINT; |
| 3400 | static char idt_big_breakpoint[] = IDT_BIG_BREAKPOINT; |
| 3401 | |
| 3402 | *lenptr = sizeof (big_breakpoint); |
| 3403 | |
| 3404 | if (strcmp (target_shortname, "mips") == 0) |
| 3405 | return idt_big_breakpoint; |
| 3406 | else if (strcmp (target_shortname, "ddb") == 0 |
| 3407 | || strcmp (target_shortname, "pmon") == 0 |
| 3408 | || strcmp (target_shortname, "lsi") == 0) |
| 3409 | return pmon_big_breakpoint; |
| 3410 | else |
| 3411 | return big_breakpoint; |
| 3412 | } |
| 3413 | } |
| 3414 | else |
| 3415 | { |
| 3416 | if (pc_is_mips16 (*pcptr)) |
| 3417 | { |
| 3418 | static char mips16_little_breakpoint[] = MIPS16_LITTLE_BREAKPOINT; |
| 3419 | *pcptr = UNMAKE_MIPS16_ADDR (*pcptr); |
| 3420 | *lenptr = sizeof (mips16_little_breakpoint); |
| 3421 | return mips16_little_breakpoint; |
| 3422 | } |
| 3423 | else |
| 3424 | { |
| 3425 | static char little_breakpoint[] = LITTLE_BREAKPOINT; |
| 3426 | static char pmon_little_breakpoint[] = PMON_LITTLE_BREAKPOINT; |
| 3427 | static char idt_little_breakpoint[] = IDT_LITTLE_BREAKPOINT; |
| 3428 | |
| 3429 | *lenptr = sizeof (little_breakpoint); |
| 3430 | |
| 3431 | if (strcmp (target_shortname, "mips") == 0) |
| 3432 | return idt_little_breakpoint; |
| 3433 | else if (strcmp (target_shortname, "ddb") == 0 |
| 3434 | || strcmp (target_shortname, "pmon") == 0 |
| 3435 | || strcmp (target_shortname, "lsi") == 0) |
| 3436 | return pmon_little_breakpoint; |
| 3437 | else |
| 3438 | return little_breakpoint; |
| 3439 | } |
| 3440 | } |
| 3441 | } |
| 3442 | |
| 3443 | /* If PC is in a mips16 call or return stub, return the address of the target |
| 3444 | PC, which is either the callee or the caller. There are several |
| 3445 | cases which must be handled: |
| 3446 | |
| 3447 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the |
| 3448 | target PC is in $31 ($ra). |
| 3449 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
| 3450 | and the target PC is in $2. |
| 3451 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
| 3452 | before the jal instruction, this is effectively a call stub |
| 3453 | and the the target PC is in $2. Otherwise this is effectively |
| 3454 | a return stub and the target PC is in $18. |
| 3455 | |
| 3456 | See the source code for the stubs in gcc/config/mips/mips16.S for |
| 3457 | gory details. |
| 3458 | |
| 3459 | This function implements the SKIP_TRAMPOLINE_CODE macro. |
| 3460 | */ |
| 3461 | |
| 3462 | CORE_ADDR |
| 3463 | mips_skip_stub (pc) |
| 3464 | CORE_ADDR pc; |
| 3465 | { |
| 3466 | char *name; |
| 3467 | CORE_ADDR start_addr; |
| 3468 | |
| 3469 | /* Find the starting address and name of the function containing the PC. */ |
| 3470 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 3471 | return 0; |
| 3472 | |
| 3473 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the |
| 3474 | target PC is in $31 ($ra). */ |
| 3475 | if (strcmp (name, "__mips16_ret_sf") == 0 |
| 3476 | || strcmp (name, "__mips16_ret_df") == 0) |
| 3477 | return read_register (RA_REGNUM); |
| 3478 | |
| 3479 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) |
| 3480 | { |
| 3481 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
| 3482 | and the target PC is in $2. */ |
| 3483 | if (name[19] >= '0' && name[19] <= '9') |
| 3484 | return read_register (2); |
| 3485 | |
| 3486 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
| 3487 | before the jal instruction, this is effectively a call stub |
| 3488 | and the the target PC is in $2. Otherwise this is effectively |
| 3489 | a return stub and the target PC is in $18. */ |
| 3490 | else if (name[19] == 's' || name[19] == 'd') |
| 3491 | { |
| 3492 | if (pc == start_addr) |
| 3493 | { |
| 3494 | /* Check if the target of the stub is a compiler-generated |
| 3495 | stub. Such a stub for a function bar might have a name |
| 3496 | like __fn_stub_bar, and might look like this: |
| 3497 | mfc1 $4,$f13 |
| 3498 | mfc1 $5,$f12 |
| 3499 | mfc1 $6,$f15 |
| 3500 | mfc1 $7,$f14 |
| 3501 | la $1,bar (becomes a lui/addiu pair) |
| 3502 | jr $1 |
| 3503 | So scan down to the lui/addi and extract the target |
| 3504 | address from those two instructions. */ |
| 3505 | |
| 3506 | CORE_ADDR target_pc = read_register (2); |
| 3507 | t_inst inst; |
| 3508 | int i; |
| 3509 | |
| 3510 | /* See if the name of the target function is __fn_stub_*. */ |
| 3511 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == 0) |
| 3512 | return target_pc; |
| 3513 | if (strncmp (name, "__fn_stub_", 10) != 0 |
| 3514 | && strcmp (name, "etext") != 0 |
| 3515 | && strcmp (name, "_etext") != 0) |
| 3516 | return target_pc; |
| 3517 | |
| 3518 | /* Scan through this _fn_stub_ code for the lui/addiu pair. |
| 3519 | The limit on the search is arbitrarily set to 20 |
| 3520 | instructions. FIXME. */ |
| 3521 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSTLEN) |
| 3522 | { |
| 3523 | inst = mips_fetch_instruction (target_pc); |
| 3524 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
| 3525 | pc = (inst << 16) & 0xffff0000; /* high word */ |
| 3526 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ |
| 3527 | return pc | (inst & 0xffff); /* low word */ |
| 3528 | } |
| 3529 | |
| 3530 | /* Couldn't find the lui/addui pair, so return stub address. */ |
| 3531 | return target_pc; |
| 3532 | } |
| 3533 | else |
| 3534 | /* This is the 'return' part of a call stub. The return |
| 3535 | address is in $r18. */ |
| 3536 | return read_register (18); |
| 3537 | } |
| 3538 | } |
| 3539 | return 0; /* not a stub */ |
| 3540 | } |
| 3541 | |
| 3542 | |
| 3543 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). |
| 3544 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ |
| 3545 | |
| 3546 | int |
| 3547 | mips_in_call_stub (pc, name) |
| 3548 | CORE_ADDR pc; |
| 3549 | char *name; |
| 3550 | { |
| 3551 | CORE_ADDR start_addr; |
| 3552 | |
| 3553 | /* Find the starting address of the function containing the PC. If the |
| 3554 | caller didn't give us a name, look it up at the same time. */ |
| 3555 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) |
| 3556 | return 0; |
| 3557 | |
| 3558 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) |
| 3559 | { |
| 3560 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ |
| 3561 | if (name[19] >= '0' && name[19] <= '9') |
| 3562 | return 1; |
| 3563 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
| 3564 | before the jal instruction, this is effectively a call stub. */ |
| 3565 | else if (name[19] == 's' || name[19] == 'd') |
| 3566 | return pc == start_addr; |
| 3567 | } |
| 3568 | |
| 3569 | return 0; /* not a stub */ |
| 3570 | } |
| 3571 | |
| 3572 | |
| 3573 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). |
| 3574 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ |
| 3575 | |
| 3576 | int |
| 3577 | mips_in_return_stub (pc, name) |
| 3578 | CORE_ADDR pc; |
| 3579 | char *name; |
| 3580 | { |
| 3581 | CORE_ADDR start_addr; |
| 3582 | |
| 3583 | /* Find the starting address of the function containing the PC. */ |
| 3584 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) |
| 3585 | return 0; |
| 3586 | |
| 3587 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ |
| 3588 | if (strcmp (name, "__mips16_ret_sf") == 0 |
| 3589 | || strcmp (name, "__mips16_ret_df") == 0) |
| 3590 | return 1; |
| 3591 | |
| 3592 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, |
| 3593 | i.e. after the jal instruction, this is effectively a return stub. */ |
| 3594 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
| 3595 | && (name[19] == 's' || name[19] == 'd') |
| 3596 | && pc != start_addr) |
| 3597 | return 1; |
| 3598 | |
| 3599 | return 0; /* not a stub */ |
| 3600 | } |
| 3601 | |
| 3602 | |
| 3603 | /* Return non-zero if the PC is in a library helper function that should |
| 3604 | be ignored. This implements the IGNORE_HELPER_CALL macro. */ |
| 3605 | |
| 3606 | int |
| 3607 | mips_ignore_helper (pc) |
| 3608 | CORE_ADDR pc; |
| 3609 | { |
| 3610 | char *name; |
| 3611 | |
| 3612 | /* Find the starting address and name of the function containing the PC. */ |
| 3613 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) |
| 3614 | return 0; |
| 3615 | |
| 3616 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function |
| 3617 | that we want to ignore. */ |
| 3618 | return (strcmp (name, "__mips16_ret_sf") == 0 |
| 3619 | || strcmp (name, "__mips16_ret_df") == 0); |
| 3620 | } |
| 3621 | |
| 3622 | |
| 3623 | /* Return a location where we can set a breakpoint that will be hit |
| 3624 | when an inferior function call returns. This is normally the |
| 3625 | program's entry point. Executables that don't have an entry |
| 3626 | point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS |
| 3627 | whose address is the location where the breakpoint should be placed. */ |
| 3628 | |
| 3629 | CORE_ADDR |
| 3630 | mips_call_dummy_address () |
| 3631 | { |
| 3632 | struct minimal_symbol *sym; |
| 3633 | |
| 3634 | sym = lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL, NULL); |
| 3635 | if (sym) |
| 3636 | return SYMBOL_VALUE_ADDRESS (sym); |
| 3637 | else |
| 3638 | return entry_point_address (); |
| 3639 | } |
| 3640 | |
| 3641 | |
| 3642 | |
| 3643 | static gdbarch_init_ftype mips_gdbarch_init; |
| 3644 | static struct gdbarch * |
| 3645 | mips_gdbarch_init (info, arches) |
| 3646 | struct gdbarch_info info; |
| 3647 | struct gdbarch_list *arches; |
| 3648 | { |
| 3649 | static LONGEST mips_call_dummy_words[] = |
| 3650 | {0}; |
| 3651 | struct gdbarch *gdbarch; |
| 3652 | struct gdbarch_tdep *tdep; |
| 3653 | int elf_flags; |
| 3654 | char *ef_mips_abi; |
| 3655 | int ef_mips_bitptrs; |
| 3656 | int ef_mips_arch; |
| 3657 | |
| 3658 | /* Extract the elf_flags if available */ |
| 3659 | if (info.abfd != NULL |
| 3660 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
| 3661 | elf_flags = elf_elfheader (info.abfd)->e_flags; |
| 3662 | else |
| 3663 | elf_flags = 0; |
| 3664 | |
| 3665 | /* try to find a pre-existing architecture */ |
| 3666 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
| 3667 | arches != NULL; |
| 3668 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) |
| 3669 | { |
| 3670 | /* MIPS needs to be pedantic about which ABI the object is |
| 3671 | using. */ |
| 3672 | if (gdbarch_tdep (current_gdbarch)->elf_flags != elf_flags) |
| 3673 | continue; |
| 3674 | return arches->gdbarch; |
| 3675 | } |
| 3676 | |
| 3677 | /* Need a new architecture. Fill in a target specific vector. */ |
| 3678 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
| 3679 | gdbarch = gdbarch_alloc (&info, tdep); |
| 3680 | tdep->elf_flags = elf_flags; |
| 3681 | |
| 3682 | /* Initially set everything according to the ABI. */ |
| 3683 | set_gdbarch_short_bit (gdbarch, 16); |
| 3684 | set_gdbarch_int_bit (gdbarch, 32); |
| 3685 | set_gdbarch_float_bit (gdbarch, 32); |
| 3686 | set_gdbarch_double_bit (gdbarch, 64); |
| 3687 | set_gdbarch_long_double_bit (gdbarch, 64); |
| 3688 | switch ((elf_flags & EF_MIPS_ABI)) |
| 3689 | { |
| 3690 | case E_MIPS_ABI_O32: |
| 3691 | ef_mips_abi = "o32"; |
| 3692 | tdep->mips_eabi = 0; |
| 3693 | tdep->mips_saved_regsize = 4; |
| 3694 | tdep->mips_fp_register_double = 0; |
| 3695 | set_gdbarch_long_bit (gdbarch, 32); |
| 3696 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 3697 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 3698 | break; |
| 3699 | case E_MIPS_ABI_O64: |
| 3700 | ef_mips_abi = "o64"; |
| 3701 | tdep->mips_eabi = 0; |
| 3702 | tdep->mips_saved_regsize = 8; |
| 3703 | tdep->mips_fp_register_double = 1; |
| 3704 | set_gdbarch_long_bit (gdbarch, 32); |
| 3705 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 3706 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 3707 | break; |
| 3708 | case E_MIPS_ABI_EABI32: |
| 3709 | ef_mips_abi = "eabi32"; |
| 3710 | tdep->mips_eabi = 1; |
| 3711 | tdep->mips_saved_regsize = 4; |
| 3712 | tdep->mips_fp_register_double = 0; |
| 3713 | set_gdbarch_long_bit (gdbarch, 32); |
| 3714 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 3715 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 3716 | break; |
| 3717 | case E_MIPS_ABI_EABI64: |
| 3718 | ef_mips_abi = "eabi64"; |
| 3719 | tdep->mips_eabi = 1; |
| 3720 | tdep->mips_saved_regsize = 8; |
| 3721 | tdep->mips_fp_register_double = 1; |
| 3722 | set_gdbarch_long_bit (gdbarch, 64); |
| 3723 | set_gdbarch_ptr_bit (gdbarch, 64); |
| 3724 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 3725 | break; |
| 3726 | default: |
| 3727 | ef_mips_abi = "default"; |
| 3728 | tdep->mips_eabi = 0; |
| 3729 | tdep->mips_saved_regsize = MIPS_REGSIZE; |
| 3730 | tdep->mips_fp_register_double = (REGISTER_VIRTUAL_SIZE (FP0_REGNUM) == 8); |
| 3731 | set_gdbarch_long_bit (gdbarch, 32); |
| 3732 | set_gdbarch_ptr_bit (gdbarch, 32); |
| 3733 | set_gdbarch_long_long_bit (gdbarch, 64); |
| 3734 | break; |
| 3735 | } |
| 3736 | |
| 3737 | /* determine the ISA */ |
| 3738 | switch (elf_flags & EF_MIPS_ARCH) |
| 3739 | { |
| 3740 | case E_MIPS_ARCH_1: |
| 3741 | ef_mips_arch = 1; |
| 3742 | break; |
| 3743 | case E_MIPS_ARCH_2: |
| 3744 | ef_mips_arch = 2; |
| 3745 | break; |
| 3746 | case E_MIPS_ARCH_3: |
| 3747 | ef_mips_arch = 3; |
| 3748 | break; |
| 3749 | case E_MIPS_ARCH_4: |
| 3750 | ef_mips_arch = 0; |
| 3751 | break; |
| 3752 | default: |
| 3753 | break; |
| 3754 | } |
| 3755 | |
| 3756 | #if 0 |
| 3757 | /* determine the size of a pointer */ |
| 3758 | if ((elf_flags & EF_MIPS_32BITPTRS)) |
| 3759 | { |
| 3760 | ef_mips_bitptrs = 32; |
| 3761 | } |
| 3762 | else if ((elf_flags & EF_MIPS_64BITPTRS)) |
| 3763 | { |
| 3764 | ef_mips_bitptrs = 64; |
| 3765 | } |
| 3766 | else |
| 3767 | { |
| 3768 | ef_mips_bitptrs = 0; |
| 3769 | } |
| 3770 | #endif |
| 3771 | |
| 3772 | /* Select either of the two alternative ABI's */ |
| 3773 | if (tdep->mips_eabi) |
| 3774 | { |
| 3775 | /* EABI uses R4 through R11 for args */ |
| 3776 | tdep->mips_last_arg_regnum = 11; |
| 3777 | /* EABI uses F12 through F19 for args */ |
| 3778 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19; |
| 3779 | } |
| 3780 | else |
| 3781 | { |
| 3782 | /* old ABI uses R4 through R7 for args */ |
| 3783 | tdep->mips_last_arg_regnum = 7; |
| 3784 | /* old ABI uses F12 through F15 for args */ |
| 3785 | tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15; |
| 3786 | } |
| 3787 | |
| 3788 | /* enable/disable the MIPS FPU */ |
| 3789 | if (!mips_fpu_type_auto) |
| 3790 | tdep->mips_fpu_type = mips_fpu_type; |
| 3791 | else if (info.bfd_arch_info != NULL |
| 3792 | && info.bfd_arch_info->arch == bfd_arch_mips) |
| 3793 | switch (info.bfd_arch_info->mach) |
| 3794 | { |
| 3795 | case bfd_mach_mips4100: |
| 3796 | case bfd_mach_mips4111: |
| 3797 | tdep->mips_fpu_type = MIPS_FPU_NONE; |
| 3798 | break; |
| 3799 | default: |
| 3800 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; |
| 3801 | break; |
| 3802 | } |
| 3803 | else |
| 3804 | tdep->mips_fpu_type = MIPS_FPU_DOUBLE; |
| 3805 | |
| 3806 | /* MIPS version of register names. NOTE: At present the MIPS |
| 3807 | register name management is part way between the old - |
| 3808 | #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). |
| 3809 | Further work on it is required. */ |
| 3810 | set_gdbarch_register_name (gdbarch, mips_register_name); |
| 3811 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); |
| 3812 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
| 3813 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); |
| 3814 | set_gdbarch_write_fp (gdbarch, generic_target_write_fp); |
| 3815 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
| 3816 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); |
| 3817 | |
| 3818 | /* Initialize a frame */ |
| 3819 | set_gdbarch_init_extra_frame_info (gdbarch, mips_init_extra_frame_info); |
| 3820 | |
| 3821 | /* MIPS version of CALL_DUMMY */ |
| 3822 | |
| 3823 | set_gdbarch_call_dummy_p (gdbarch, 1); |
| 3824 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); |
| 3825 | set_gdbarch_use_generic_dummy_frames (gdbarch, 0); |
| 3826 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); |
| 3827 | set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); |
| 3828 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); |
| 3829 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); |
| 3830 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); |
| 3831 | set_gdbarch_call_dummy_length (gdbarch, 0); |
| 3832 | set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); |
| 3833 | set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); |
| 3834 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); |
| 3835 | set_gdbarch_push_return_address (gdbarch, mips_push_return_address); |
| 3836 | set_gdbarch_push_arguments (gdbarch, mips_push_arguments); |
| 3837 | set_gdbarch_register_convertible (gdbarch, generic_register_convertible_not); |
| 3838 | |
| 3839 | set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); |
| 3840 | set_gdbarch_get_saved_register (gdbarch, default_get_saved_register); |
| 3841 | |
| 3842 | if (gdbarch_debug) |
| 3843 | { |
| 3844 | fprintf_unfiltered (gdb_stderr, |
| 3845 | "mips_gdbarch_init: (info)elf_flags = 0x%x\n", |
| 3846 | elf_flags); |
| 3847 | fprintf_unfiltered (gdb_stderr, |
| 3848 | "mips_gdbarch_init: (info)ef_mips_abi = %s\n", |
| 3849 | ef_mips_abi); |
| 3850 | fprintf_unfiltered (gdb_stderr, |
| 3851 | "mips_gdbarch_init: (info)ef_mips_arch = %d\n", |
| 3852 | ef_mips_arch); |
| 3853 | fprintf_unfiltered (gdb_stderr, |
| 3854 | "mips_gdbarch_init: (info)ef_mips_bitptrs = %d\n", |
| 3855 | ef_mips_bitptrs); |
| 3856 | fprintf_unfiltered (gdb_stderr, |
| 3857 | "mips_gdbarch_init: MIPS_EABI = %d\n", |
| 3858 | tdep->mips_eabi); |
| 3859 | fprintf_unfiltered (gdb_stderr, |
| 3860 | "mips_gdbarch_init: MIPS_LAST_ARG_REGNUM = %d\n", |
| 3861 | tdep->mips_last_arg_regnum); |
| 3862 | fprintf_unfiltered (gdb_stderr, |
| 3863 | "mips_gdbarch_init: MIPS_LAST_FP_ARG_REGNUM = %d (%d)\n", |
| 3864 | tdep->mips_last_fp_arg_regnum, |
| 3865 | tdep->mips_last_fp_arg_regnum - FP0_REGNUM); |
| 3866 | fprintf_unfiltered (gdb_stderr, |
| 3867 | "mips_gdbarch_init: tdep->mips_fpu_type = %d (%s)\n", |
| 3868 | tdep->mips_fpu_type, |
| 3869 | (tdep->mips_fpu_type == MIPS_FPU_NONE ? "none" |
| 3870 | : tdep->mips_fpu_type == MIPS_FPU_SINGLE ? "single" |
| 3871 | : tdep->mips_fpu_type == MIPS_FPU_DOUBLE ? "double" |
| 3872 | : "???")); |
| 3873 | fprintf_unfiltered (gdb_stderr, |
| 3874 | "mips_gdbarch_init: tdep->mips_saved_regsize = %d\n", |
| 3875 | tdep->mips_saved_regsize); |
| 3876 | fprintf_unfiltered (gdb_stderr, |
| 3877 | "mips_gdbarch_init: tdep->mips_fp_register_double = %d (%s)\n", |
| 3878 | tdep->mips_fp_register_double, |
| 3879 | (tdep->mips_fp_register_double ? "true" : "false")); |
| 3880 | } |
| 3881 | |
| 3882 | return gdbarch; |
| 3883 | } |
| 3884 | |
| 3885 | |
| 3886 | void |
| 3887 | _initialize_mips_tdep () |
| 3888 | { |
| 3889 | static struct cmd_list_element *mipsfpulist = NULL; |
| 3890 | struct cmd_list_element *c; |
| 3891 | |
| 3892 | if (GDB_MULTI_ARCH) |
| 3893 | register_gdbarch_init (bfd_arch_mips, mips_gdbarch_init); |
| 3894 | if (!tm_print_insn) /* Someone may have already set it */ |
| 3895 | tm_print_insn = gdb_print_insn_mips; |
| 3896 | |
| 3897 | /* Let the user turn off floating point and set the fence post for |
| 3898 | heuristic_proc_start. */ |
| 3899 | |
| 3900 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, |
| 3901 | "Set use of MIPS floating-point coprocessor.", |
| 3902 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
| 3903 | add_cmd ("single", class_support, set_mipsfpu_single_command, |
| 3904 | "Select single-precision MIPS floating-point coprocessor.", |
| 3905 | &mipsfpulist); |
| 3906 | add_cmd ("double", class_support, set_mipsfpu_double_command, |
| 3907 | "Select double-precision MIPS floating-point coprocessor .", |
| 3908 | &mipsfpulist); |
| 3909 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); |
| 3910 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); |
| 3911 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); |
| 3912 | add_cmd ("none", class_support, set_mipsfpu_none_command, |
| 3913 | "Select no MIPS floating-point coprocessor.", |
| 3914 | &mipsfpulist); |
| 3915 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
| 3916 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); |
| 3917 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); |
| 3918 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, |
| 3919 | "Select MIPS floating-point coprocessor automatically.", |
| 3920 | &mipsfpulist); |
| 3921 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, |
| 3922 | "Show current use of MIPS floating-point coprocessor target.", |
| 3923 | &showlist); |
| 3924 | |
| 3925 | #if !GDB_MULTI_ARCH |
| 3926 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
| 3927 | (char *) &tmp_mips_processor_type, |
| 3928 | "Set the type of MIPS processor in use.\n\ |
| 3929 | Set this to be able to access processor-type-specific registers.\n\ |
| 3930 | ", |
| 3931 | &setlist); |
| 3932 | c->function.cfunc = mips_set_processor_type_command; |
| 3933 | c = add_show_from_set (c, &showlist); |
| 3934 | c->function.cfunc = mips_show_processor_type_command; |
| 3935 | |
| 3936 | tmp_mips_processor_type = strsave (DEFAULT_MIPS_TYPE); |
| 3937 | mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE), 0); |
| 3938 | #endif |
| 3939 | |
| 3940 | /* We really would like to have both "0" and "unlimited" work, but |
| 3941 | command.c doesn't deal with that. So make it a var_zinteger |
| 3942 | because the user can always use "999999" or some such for unlimited. */ |
| 3943 | c = add_set_cmd ("heuristic-fence-post", class_support, var_zinteger, |
| 3944 | (char *) &heuristic_fence_post, |
| 3945 | "\ |
| 3946 | Set the distance searched for the start of a function.\n\ |
| 3947 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
| 3948 | program for the start of a function. This command sets the distance of the\n\ |
| 3949 | search. The only need to set it is when debugging a stripped executable.", |
| 3950 | &setlist); |
| 3951 | /* We need to throw away the frame cache when we set this, since it |
| 3952 | might change our ability to get backtraces. */ |
| 3953 | c->function.sfunc = reinit_frame_cache_sfunc; |
| 3954 | add_show_from_set (c, &showlist); |
| 3955 | |
| 3956 | /* Allow the user to control whether the upper bits of 64-bit |
| 3957 | addresses should be zeroed. */ |
| 3958 | add_show_from_set |
| 3959 | (add_set_cmd ("mask-address", no_class, var_boolean, (char *) &mask_address_p, |
| 3960 | "Set zeroing of upper 32 bits of 64-bit addresses.\n\ |
| 3961 | Use \"on\" to enable the masking, and \"off\" to disable it.\n\ |
| 3962 | Without an argument, zeroing of upper address bits is enabled.", &setlist), |
| 3963 | &showlist); |
| 3964 | |
| 3965 | /* Allow the user to control the size of 32 bit registers within the |
| 3966 | raw remote packet. */ |
| 3967 | add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs", |
| 3968 | class_obscure, |
| 3969 | var_boolean, |
| 3970 | (char *)&mips64_transfers_32bit_regs_p, "\ |
| 3971 | Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\ |
| 3972 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
| 3973 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ |
| 3974 | 64 bits for others. Use \"off\" to disable compatibility mode", |
| 3975 | &setlist), |
| 3976 | &showlist); |
| 3977 | } |